From b40a8f816b7333dc42ef9a723d9ff710803de236 Mon Sep 17 00:00:00 2001
From: yufanyufan77 <765637468@qq.com>
Date: Fri, 14 Dec 2018 08:58:40 +0800
Subject: 添加cpu复位函数 RT_WEAK void rt_hw_cpu_reset(void)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/arm/cortex-m0/cpuport.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m0/cpuport.c b/libcpu/arm/cortex-m0/cpuport.c
index f5ff8ec113..5d36fa11fe 100644
--- a/libcpu/arm/cortex-m0/cpuport.c
+++ b/libcpu/arm/cortex-m0/cpuport.c
@@ -114,3 +114,22 @@ void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
 
     while (1);
 }
+
+#define SCB_CFSR        (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
+#define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
+#define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
+#define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED00)  /* Reset control Address Register */
+#define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
+
+#define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
+#define SCB_CFSR_BFSR   (*(volatile const unsigned char*)0xE000ED29)  /* Bus Fault Status Register */
+#define SCB_CFSR_UFSR   (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
+
+/**
+ * reset CPU
+ */
+RT_WEAK void rt_hw_cpu_reset(void)
+{
+    SCB_AIRCR  = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk);
+}
-- 
cgit v1.3.1


From fd347fdb9026af8f2b15d362c1118cab46ffc2c9 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 15 Dec 2018 11:47:10 +0800
Subject: [libcpu][risc-v] fix the rt_thread_switch_interrupt_flag issue

---
 libcpu/risc-v/e310/interrupt_gcc.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/risc-v/e310/interrupt_gcc.S b/libcpu/risc-v/e310/interrupt_gcc.S
index 297851d71e..1eac7af90a 100644
--- a/libcpu/risc-v/e310/interrupt_gcc.S
+++ b/libcpu/risc-v/e310/interrupt_gcc.S
@@ -69,9 +69,9 @@ trap_entry:
 
     /* need to switch new thread */
     la    s0, rt_thread_switch_interrupt_flag
-    LOAD  s2, 0(s0)
+    lw    s2, 0(s0)
     beqz  s2, spurious_interrupt
-    STORE zero, 0(s0)
+    sw    zero, 0(s0)
 
     csrr  a0, mepc
     STORE a0, 0 * REGBYTES(sp)
-- 
cgit v1.3.1


From 885d99ee9b76bfdd838d5b3f358137fe255d92e7 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sat, 15 Dec 2018 11:47:59 +0800
Subject: [libcpu][risc-v] fix rt_thread_switch_interrupt_flag issue.

---
 libcpu/risc-v/rv32m1/interrupt_gcc.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/risc-v/rv32m1/interrupt_gcc.S b/libcpu/risc-v/rv32m1/interrupt_gcc.S
index d74cf441bc..eacf667c67 100644
--- a/libcpu/risc-v/rv32m1/interrupt_gcc.S
+++ b/libcpu/risc-v/rv32m1/interrupt_gcc.S
@@ -69,10 +69,10 @@ IRQ_Handler:
 
     /* need to switch new thread */
     la    s0, rt_thread_switch_interrupt_flag
-    LOAD  s2, 0(s0)
+    lw    s2, 0(s0)
     beqz  s2, spurious_interrupt
     /* clear switch interrupt flag */
-    STORE zero, 0(s0)
+    sw    zero, 0(s0)
 
     csrr  a0, mepc
     STORE a0, 0 * REGBYTES(sp)
-- 
cgit v1.3.1


From 5e0f8cb3aa0d9459985bf0345eef0192857d1b41 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Tue, 18 Dec 2018 21:01:03 +0800
Subject: [libcpu] Add k210 BSP.

---
 bsp/k210/.config                   | 374 +++++++++++++++++++++++++++++++++++++
 bsp/k210/Kconfig                   |  31 +++
 bsp/k210/README.md                 |  93 +++++++++
 bsp/k210/SConscript                |  14 ++
 bsp/k210/SConstruct                |  35 ++++
 bsp/k210/applications/SConscript   |   9 +
 bsp/k210/applications/main.c       |  19 ++
 bsp/k210/applications/mnt.c        |  15 ++
 bsp/k210/driver/Kconfig            |  25 +++
 bsp/k210/driver/SConscript         |  38 ++++
 bsp/k210/driver/board.c            | 115 ++++++++++++
 bsp/k210/driver/board.h            |  22 +++
 bsp/k210/driver/drv_uart.c         | 209 +++++++++++++++++++++
 bsp/k210/driver/drv_uart.h         |  16 ++
 bsp/k210/images/flash.png          | Bin 0 -> 7624 bytes
 bsp/k210/images/k210.png           | Bin 0 -> 7493 bytes
 bsp/k210/link.lds                  | 160 ++++++++++++++++
 bsp/k210/link_stacksize.lds        |   1 +
 bsp/k210/rtconfig.h                | 178 ++++++++++++++++++
 bsp/k210/rtconfig.py               |  58 ++++++
 libcpu/risc-v/k210/interrupt.c     | 203 ++++++++++++++++++++
 libcpu/risc-v/k210/interrupt_gcc.S | 137 ++++++++++++++
 libcpu/risc-v/k210/startup_gcc.S   | 128 +++++++++++++
 libcpu/risc-v/k210/tick.c          |  48 +++++
 libcpu/risc-v/k210/tick.h          |  17 ++
 25 files changed, 1945 insertions(+)
 create mode 100644 bsp/k210/.config
 create mode 100644 bsp/k210/Kconfig
 create mode 100644 bsp/k210/README.md
 create mode 100644 bsp/k210/SConscript
 create mode 100644 bsp/k210/SConstruct
 create mode 100644 bsp/k210/applications/SConscript
 create mode 100644 bsp/k210/applications/main.c
 create mode 100644 bsp/k210/applications/mnt.c
 create mode 100644 bsp/k210/driver/Kconfig
 create mode 100644 bsp/k210/driver/SConscript
 create mode 100644 bsp/k210/driver/board.c
 create mode 100644 bsp/k210/driver/board.h
 create mode 100644 bsp/k210/driver/drv_uart.c
 create mode 100644 bsp/k210/driver/drv_uart.h
 create mode 100644 bsp/k210/images/flash.png
 create mode 100644 bsp/k210/images/k210.png
 create mode 100644 bsp/k210/link.lds
 create mode 100644 bsp/k210/link_stacksize.lds
 create mode 100644 bsp/k210/rtconfig.h
 create mode 100644 bsp/k210/rtconfig.py
 create mode 100644 libcpu/risc-v/k210/interrupt.c
 create mode 100644 libcpu/risc-v/k210/interrupt_gcc.S
 create mode 100644 libcpu/risc-v/k210/startup_gcc.S
 create mode 100644 libcpu/risc-v/k210/tick.c
 create mode 100644 libcpu/risc-v/k210/tick.h

(limited to 'libcpu')

diff --git a/bsp/k210/.config b/bsp/k210/.config
new file mode 100644
index 0000000000..d1279d3b74
--- /dev/null
+++ b/bsp/k210/.config
@@ -0,0 +1,374 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_INIT_CONFIG=y
+CONFIG_RT_DEBUG_INIT=1
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uarths"
+CONFIG_RT_VER_NUM=0x40000
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV64=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+
+#
+# Using WiFi
+#
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+CONFIG_PKG_USING_KENDRYTE_SDK=y
+CONFIG_PKG_KENDRYTE_SDK_PATH="/packages/peripherals/kendryte-sdk"
+CONFIG_PKG_USING_KENDRYTE_SDK_V052=y
+# CONFIG_PKG_USING_KENDRYTE_SDK_LATEST_VERSION is not set
+CONFIG_PKG_KENDRYTE_SDK_VER="v0.5.2"
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+
+#
+# sample package
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+# CONFIG_PKG_USING_JS_PERSIMMON is not set
+# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RDBD_SRC is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_RTX is not set
+CONFIG_BOARD_K210_EVB=y
+CONFIG_BSP_USING_UART_HS=y
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_I2C1 is not set
+# CONFIG_BSP_USING_SPI1 is not set
+CONFIG___STACKSIZE__=4096
diff --git a/bsp/k210/Kconfig b/bsp/k210/Kconfig
new file mode 100644
index 0000000000..ccb4adf6dc
--- /dev/null
+++ b/bsp/k210/Kconfig
@@ -0,0 +1,31 @@
+mainmenu "RT-Thread Project Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default: "../.."
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BOARD_K210_EVB
+    bool
+    select ARCH_RISCV64
+    select PKG_USING_KENDRYTE_SDK
+    default y
+
+source "driver/Kconfig"
+
+config __STACKSIZE__
+    int "stack size for interrupt"
+    default 4096
diff --git a/bsp/k210/README.md b/bsp/k210/README.md
new file mode 100644
index 0000000000..6de922d7a2
--- /dev/null
+++ b/bsp/k210/README.md
@@ -0,0 +1,93 @@
+# Kendryte K210板级支持包说明
+
+## 1. 简介
+
+Kendryte K210 是集成机器视觉与机器听觉能力的系统级芯片(SoC)。使用台积电 (TSMC) 超低功耗的 28 纳米先进制程，具有双核64位处理器，拥有较好的功耗性能，稳定性与可靠性。该方案力求零门槛开发，可在最短时效部署于用户的产品中，赋予产品人工智能。
+
+Kendryte K210 定位于AI与IoT市场的SoC，同时是使用非常方便的MCU。
+
+Kendryte中文含义为勘智，而勘智取自勘物探智。这颗芯片主要应用领域为物联网领域，在物联网领域进行开发，因此为勘物；这颗芯片主要提供的是人工智能解决方案，在人工智能领域探索，因此为探智。
+
+* 具备机器视觉能力
+* 具备机器听觉能力
+* 更好的低功耗视觉处理速度与准确率
+* 具备卷积人工神经网络硬件加速器KPU，可高性能进行卷积人工神经网络运算
+* TSMC 28nm先进制程，温度范围-40°C到125°C，稳定可靠
+* 支持固件加密，难以使用普通方法破解
+* 独特的可编程IO阵列，使产品设计更加灵活
+* 低电压，与相同处理能力的系统相比具有更低功耗
+* 3.3V/1.8V双电压支持，无需电平转换，节约成本
+
+芯片规格包括如下：
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| K210 |
+|CPU| 双核RV64GC |
+|主频| 400MHz |
+|片内SRAM| 8MB |
+| 外设 | 内嵌AES与SHA256算法加速器 |
+| | DVP、JTAG、OTP、FPIOA、GPIO、UART、SPI、RTC、I²S、I²C、WDT、Timer与PWM |
+
+## 2. 编译说明
+
+编译K210，需要先下载K210 BSP以及RT-Thread代码：
+
+    git clone https://github.com/BernardXiong/K210.git
+    cd K210
+    git submodule init
+    git submodule update
+
+    git clone https://github.com/RT-Thread/rt-thread.git
+    cd rt-thread
+    git checkout -b dev-4.0.x origin/dev-4.0.x
+
+注意，因为RT-Thread整体代码太庞大，所以并未把RT-Thread git repo以一个submodule方式加入到K210 BSP git repo中，
+而是需要把RT-Thread代码克隆到K210目录下，并切换到dev-4.0.x分支。
+
+编译推荐使用[env工具][1]，可以在console下进入到`K210`目录中，运行以下命令：
+
+    set RTT_EXEC_PATH=your_toolchains
+    scons
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
+
+## 3. 烧写及执行
+
+连接好串口，然后使用[K-Flash](https://kendryte.com/downloads/)工具进行烧写bin文件。
+
+![K-Flash](images/flash.png)
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+![terminal](images/k210.png)
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | 高速UART，用于shell |
+
+## 5. 联系人信息
+
+维护人：[bernard](https://github.com/BernardXiong)
+
+## 6. 注意事项
+
+在进行系统menuconfig配置时，以下项是必选的
+
+| 配置项 | 强制配置值 |
+| -----  | --------- |
+| Alignment size for CPU architecture data access | 8 |
+| The stack size of idle thread | > 1024 |
+| the device name for console | "uarths" |
+| Set main thread stack size | 4096 |
+
+## 7. 参考
+
+* 芯片[datasheet][2]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: https://s3.cn-north-1.amazonaws.com.cn/dl.kendryte.com/documents/kendryte_datasheet_20180919020633.pdf
diff --git a/bsp/k210/SConscript b/bsp/k210/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/k210/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/k210/SConstruct b/bsp/k210/SConstruct
new file mode 100644
index 0000000000..dc55b29194
--- /dev/null
+++ b/bsp/k210/SConstruct
@@ -0,0 +1,35 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+stack_size = 4096
+
+stack_lds = open('link_stacksize.lds', 'w')
+if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
+stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
+stack_lds.close()
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/k210/applications/SConscript b/bsp/k210/applications/SConscript
new file mode 100644
index 0000000000..c583d3016e
--- /dev/null
+++ b/bsp/k210/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/k210/applications/main.c b/bsp/k210/applications/main.c
new file mode 100644
index 0000000000..b18163ef8d
--- /dev/null
+++ b/bsp/k210/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/09/30     Bernard      The first version
+ */
+
+#include <rtthread.h>
+#include <stdio.h>
+
+int main(void)
+{
+    rt_kprintf("Hello, world\n");
+
+    return 0;
+}
diff --git a/bsp/k210/applications/mnt.c b/bsp/k210/applications/mnt.c
new file mode 100644
index 0000000000..d528a7424d
--- /dev/null
+++ b/bsp/k210/applications/mnt.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rtthread.h>
+
+int mnt_init(void)
+{
+    return 0;
+}
diff --git a/bsp/k210/driver/Kconfig b/bsp/k210/driver/Kconfig
new file mode 100644
index 0000000000..902d7c2444
--- /dev/null
+++ b/bsp/k210/driver/Kconfig
@@ -0,0 +1,25 @@
+config BSP_USING_UART_HS
+    bool "Enable High Speed UART"
+    default y
+
+config BSP_USING_UART1
+    bool "Enable UART1 (GPIO0/1)"
+    default n
+
+config BSP_USING_UART2
+    bool "Enable UART2 (GPIO0/1)"
+    default n
+
+config BSP_USING_UART3
+    bool "Enable UART3 (GPIO0/1)"
+    default n
+
+config BSP_USING_I2C1
+    bool "Enable I2C1 (GPIO0/1)"
+    select RT_USING_I2C
+    default n
+
+config BSP_USING_SPI1
+    bool "Enable SPI1 (GPIO0/1)"
+    select RT_USING_SPI
+    default n
diff --git a/bsp/k210/driver/SConscript b/bsp/k210/driver/SConscript
new file mode 100644
index 0000000000..3ea01aa83f
--- /dev/null
+++ b/bsp/k210/driver/SConscript
@@ -0,0 +1,38 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split('''
+board.c
+drv_uart.c
+''')
+CPPPATH = [cwd]
+
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+if GetDepend('RT_USING_HWTIMER'):
+    src += ['drv_hw_timer.c']
+
+if GetDepend('RT_USING_CPUTIME'):
+    src += ['drv_cputime.c']
+
+if GetDepend('RT_USING_I2C'):
+    src += ['drv_i2c.c']
+
+if GetDepend('RT_USING_SPI'):
+    src += ['drv_spi.c']
+
+if GetDepend('RT_USING_PWM'):
+    src += ['drv_pwm.c']
+
+if GetDepend('RT_USING_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend('RT_USING_WDT'):
+    src += ['drv_wdt.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/k210/driver/board.c b/bsp/k210/driver/board.c
new file mode 100644
index 0000000000..aac2adbc49
--- /dev/null
+++ b/bsp/k210/driver/board.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "tick.h"
+
+#include "drv_uart.h"
+
+#include "encoding.h"
+#include "fpioa.h"
+#include "dmac.h"
+
+#include "uarths.h"
+void rt_hw_console_output(const char *str)
+{
+    uarths_puts(str);
+    return ;
+}
+
+void init_bss(void)
+{
+    unsigned int *dst;
+
+    dst = &__bss_start;
+    while (dst < &__bss_end)
+    {
+        *dst++ = 0;
+    }
+}
+
+void cpu_entry(int cpuid)
+{
+    extern void entry(void);
+
+    /* disable global interrupt */
+    rt_hw_interrupt_disable();
+    if (cpuid == 0)
+    {
+        init_bss();
+        entry();
+    }
+    else
+    {
+        while (1) ;
+    }
+}
+
+#include <clint.h>
+#include <sysctl.h>
+
+int freq(void)
+{
+    rt_uint64_t value = 0;
+
+    value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL0);
+    rt_kprintf("PLL0: %d\n", value);
+    value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
+    rt_kprintf("PLL1: %d\n", value);
+    value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
+    rt_kprintf("PLL2: %d\n", value);
+    value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
+    rt_kprintf("CPU : %d\n", value);
+    value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0);
+    rt_kprintf("APB0: %d\n", value);
+    value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1);
+    rt_kprintf("APB1: %d\n", value);
+    value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB2);
+    rt_kprintf("APB2: %d\n", value);
+    value = sysctl_clock_get_freq(SYSCTL_CLOCK_HCLK);
+    rt_kprintf("HCLK: %d\n", value);
+
+    value = clint_get_time();
+    rt_kprintf("mtime: %d\n", value);
+
+    return 0;
+}
+MSH_CMD_EXPORT(freq, show freq info);
+
+void rt_hw_board_init(void)
+{
+    /* Init FPIOA */
+    fpioa_init();
+    /* Dmac init */
+    dmac_init();
+
+    /* initalize interrupt */
+    rt_hw_interrupt_init();
+    /* initialize hardware interrupt */
+    rt_hw_uart_init();
+    rt_hw_tick_init();
+
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_HEAP
+    rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
diff --git a/bsp/k210/driver/board.h b/bsp/k210/driver/board.h
new file mode 100644
index 0000000000..0d270abd2b
--- /dev/null
+++ b/bsp/k210/driver/board.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+extern unsigned int __bss_start;
+extern unsigned int __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(0x80000000 + 6 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/k210/driver/drv_uart.c b/bsp/k210/driver/drv_uart.c
new file mode 100644
index 0000000000..74ba05e203
--- /dev/null
+++ b/bsp/k210/driver/drv_uart.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include <stdio.h>
+
+// #include "uart.h"
+#include "uarths.h"
+#include "plic.h"
+
+struct device_uart
+{
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t  uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t  uart_control(struct rt_serial_device *serial, int cmd, void *arg);
+static int       drv_uart_putc(struct rt_serial_device *serial, char c);
+static int       drv_uart_getc(struct rt_serial_device *serial);
+
+static void     uart_irq_handler(int irqno, void *param);
+
+const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    drv_uart_putc,
+    drv_uart_getc,
+    RT_NULL
+};
+
+/*
+ * UART Initiation
+ */
+int rt_hw_uart_init(void)
+{
+    struct rt_serial_device *serial;
+    struct device_uart      *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef BSP_USING_UART_HS
+    {
+        static struct rt_serial_device  serial_hs;
+        static struct device_uart       uart_hs;
+
+        serial  = &serial_hs;
+        uart    = &uart_hs;
+
+        serial->ops              = &_uart_ops;
+        serial->config           = config;
+        serial->config.baud_rate = 115200;
+
+        uart->hw_base   = UARTHS_BASE_ADDR;
+        uart->irqno     = IRQN_UARTHS_INTERRUPT;
+
+        /* initialize UART HS */
+        uarths_init();
+
+        rt_hw_serial_register(serial,
+                              "uarths",
+                              RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                              uart);
+    }
+#endif
+
+#ifdef BSP_USING_UART1
+    {
+        static struct rt_serial_device  serial1;
+        static struct device_uart       uart1;
+
+        serial  = &serial1;
+        uart    = &uart1;
+
+        serial->ops              = &_uart_ops;
+        serial->config           = config;
+        serial->config.baud_rate = 115200;
+
+        uart->hw_base   = UART1_BASE_ADDR;
+        uart->irqno     = IRQN_UART1_INTERRUPT;
+
+        rt_hw_serial_register(serial,
+                              "uarths",
+                              RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                              uart);
+    }
+#endif
+
+#ifdef BSP_USING_UART2
+#endif
+
+#ifdef BSP_USING_UART3
+#endif
+
+    return 0;
+}
+
+/*
+ * UART interface
+ */
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    rt_uint32_t baud_div;
+    struct device_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    serial->config = *cfg;
+
+    uart = serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    /* Init UART Hardware */
+
+    /* Enable UART clock */
+
+    /* Set both receiver and transmitter in UART mode (not SIR) */
+
+    /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+
+    /* set baudrate */
+
+    return (RT_EOK);
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct device_uart *uart;
+
+    uart = serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* Disable the UART Interrupt */
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* install interrupt */
+        rt_hw_interrupt_install(uart->irqno, uart_irq_handler,
+                                serial, serial->parent.parent.name);
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int drv_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct device_uart *uart;
+
+    uart = serial->parent.user_data;
+    if (uart->hw_base == UARTHS_BASE_ADDR)
+    {
+        uarths_putchar(c);
+    }
+    else
+    {
+        /* other uart */
+    }
+
+    return (1);
+}
+
+static int drv_uart_getc(struct rt_serial_device *serial)
+{
+    int ret = -1;
+    struct device_uart *uart = serial->parent.user_data;
+
+    if (uart->hw_base == UARTHS_BASE_ADDR)
+    {
+        ret = uarths_getc();
+        if (ret != EOF) return ret;
+    }
+
+    /* Receive Data Available */
+
+    return (-1);
+}
+
+/* UART ISR */
+static void uart_irq_handler(int irqno, void *param)
+{
+    rt_ubase_t isr;
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+    struct device_uart *uart = serial->parent.user_data;
+
+    /* read interrupt status and clear it */
+    if (uart->hw_base == UARTHS_BASE_ADDR)
+    {
+        if (uarths->ip.rxwm) 
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+}
diff --git a/bsp/k210/driver/drv_uart.h b/bsp/k210/driver/drv_uart.h
new file mode 100644
index 0000000000..deac702fe1
--- /dev/null
+++ b/bsp/k210/driver/drv_uart.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/10/01     Bernard      The first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif /* __DRV_UART_H__ */
diff --git a/bsp/k210/images/flash.png b/bsp/k210/images/flash.png
new file mode 100644
index 0000000000..2a3c6eaf61
Binary files /dev/null and b/bsp/k210/images/flash.png differ
diff --git a/bsp/k210/images/k210.png b/bsp/k210/images/k210.png
new file mode 100644
index 0000000000..2d59f3aa58
Binary files /dev/null and b/bsp/k210/images/k210.png differ
diff --git a/bsp/k210/link.lds b/bsp/k210/link.lds
new file mode 100644
index 0000000000..851861f19f
--- /dev/null
+++ b/bsp/k210/link.lds
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+INCLUDE "link_stacksize.lds"
+
+/*
+ * The OUTPUT_ARCH command specifies the machine architecture where the
+ * argument is one of the names used in the Kendryte library.
+ */
+OUTPUT_ARCH( "riscv" )
+
+MEMORY
+{
+   /* 6M SRAM */
+   SRAM : ORIGIN = 0x80000000, LENGTH = 0x600000
+}
+
+ENTRY(_start)
+SECTIONS
+{
+    . = 0x80000000 ;
+
+    /* __STACKSIZE__ = 4096; */
+
+    .start :
+    {
+        *(.start);
+    } > SRAM
+
+    . = ALIGN(4);
+
+    .text : 
+    {
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+     
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > SRAM
+
+    .eh_frame_hdr : 
+    { 
+         *(.eh_frame_hdr) 
+         *(.eh_frame_entry)
+    } > SRAM
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
+
+    . = ALIGN(4);
+
+    .data : 
+    {
+        *(.data)
+        *(.data.*)
+    
+        *(.data1)
+        *(.data1.*)
+
+        . = ALIGN(8);
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.sdata)
+        *(.sdata.*)
+    } > SRAM
+
+    /* stack for dual core */
+    .stack :
+    {
+        . = ALIGN(64);
+        __stack_start__ = .;
+
+        . += __STACKSIZE__;
+        __stack_cpu0 = .;
+
+        . += __STACKSIZE__;
+        __stack_cpu1 = .;
+    } > SRAM
+
+    .sbss : 
+    {
+    __bss_start = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.dynsbss)
+        *(.scommon)
+    } > SRAM
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+    __bss_end = .;
+    } > SRAM
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/k210/link_stacksize.lds b/bsp/k210/link_stacksize.lds
new file mode 100644
index 0000000000..1dd893422c
--- /dev/null
+++ b/bsp/k210/link_stacksize.lds
@@ -0,0 +1 @@
+__STACKSIZE__ = 4096;
\ No newline at end of file
diff --git a/bsp/k210/rtconfig.h b/bsp/k210/rtconfig.h
new file mode 100644
index 0000000000..629a34f31c
--- /dev/null
+++ b/bsp/k210/rtconfig.h
@@ -0,0 +1,178 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDEL_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+#define RT_DEBUG
+#define RT_DEBUG_INIT_CONFIG
+#define RT_DEBUG_INIT 1
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uarths"
+#define RT_VER_NUM 0x40000
+#define ARCH_CPU_64BIT
+#define ARCH_RISCV
+#define ARCH_RISCV64
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_USING_PIN
+
+/* Using WiFi */
+
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* light weight TCP/IP stack */
+
+
+/* Modbus master and slave stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_KENDRYTE_SDK
+#define PKG_USING_KENDRYTE_SDK_V052
+
+/* miscellaneous packages */
+
+
+/* sample package */
+
+/* samples: kernel and components samples */
+
+
+/* example package: hello */
+
+
+/* Privated Packages of RealThread */
+
+
+/* Network Utilities */
+
+#define BOARD_K210_EVB
+#define BSP_USING_UART_HS
+#define __STACKSIZE__ 4096
+
+#endif
diff --git a/bsp/k210/rtconfig.py b/bsp/k210/rtconfig.py
new file mode 100644
index 0000000000..c2df896f4c
--- /dev/null
+++ b/bsp/k210/rtconfig.py
@@ -0,0 +1,58 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+CPU         ='k210'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'rt-thread'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/riscv64-unknown-elf-gcc-2018.07.0-x86_64-linux-ubuntu14/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv-none-embed-'
+    # PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -mcmodel=medany'
+    CFLAGS  = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields '
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -ggdb'
+        AFLAGS += ' -ggdb'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c
new file mode 100644
index 0000000000..6d8866c3f0
--- /dev/null
+++ b/libcpu/risc-v/k210/interrupt.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/10/01     Bernard      The first version
+ */
+
+#include <rthw.h>
+
+#include "tick.h"
+
+#include <plic.h>
+#include <clint.h>
+#include <interrupt.h>
+
+#define CPU_NUM         2
+#define MAX_HANDLERS    IRQN_MAX
+
+static struct rt_irq_desc irq_desc[CPU_NUM][MAX_HANDLERS];
+
+static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
+{
+    rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
+    return RT_NULL;
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    int idx;
+    int cpuid;
+
+    cpuid = current_coreid();
+
+    /* Disable all interrupts for the current core. */
+    for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++)
+        plic->target_enables.target[cpuid].enable[idx] = 0;
+
+    /* Set priorities to zero. */
+    for (idx = 0; idx < PLIC_NUM_SOURCES; idx++)
+        plic->source_priorities.priority[idx] = 0;
+
+    /* Set the threshold to zero. */
+    plic->targets.target[cpuid].priority_threshold = 0;
+
+    /* init exceptions table */
+    for (idx = 0; idx < MAX_HANDLERS; idx++)
+    {
+        rt_hw_interrupt_mask(idx);
+        irq_desc[cpuid][idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+        irq_desc[cpuid][idx].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[cpuid][idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx][cpuid].counter = 0;
+#endif
+    }
+
+    /* Enable machine external interrupts. */
+    set_csr(mie, MIP_MEIP);
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    plic_irq_disable(vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    plic_set_priority(vector, 1);
+    plic_irq_enable(vector);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    int cpuid;
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    cpuid = current_coreid();
+
+    if(vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[cpuid][vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[cpuid][vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[cpuid][vector].param = param;
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[cpuid][vector].name, RT_NAME_MAX - 1, "%s", name);
+            irq_desc[cpuid][vector].counter = 0;
+#endif
+        }
+    }
+
+    return old_handler;
+}
+
+uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
+{
+    /*
+     * After the highest-priority pending interrupt is claimed by a target
+     * and the corresponding IP bit is cleared, other lower-priority
+     * pending interrupts might then become visible to the target, and so
+     * the PLIC EIP bit might not be cleared after a claim. The interrupt
+     * handler can check the local meip/heip/seip/ueip bits before exiting
+     * the handler, to allow more efficient service of other interrupts
+     * without first restoring the interrupted context and taking another
+     * interrupt trap.
+     */
+    if (read_csr(mip) & MIP_MEIP)
+    {
+        /* Get current core id */
+        uint64_t core_id = current_coreid();
+        /* Get primitive interrupt enable flag */
+        uint64_t ie_flag = read_csr(mie);
+        /* Get current IRQ num */
+        uint32_t int_num = plic->targets.target[core_id].claim_complete;
+        /* Get primitive IRQ threshold */
+        uint32_t int_threshold = plic->targets.target[core_id].priority_threshold;
+        /* Set new IRQ threshold = current IRQ threshold */
+        plic->targets.target[core_id].priority_threshold = plic->source_priorities.priority[int_num];
+
+        /* Disable software interrupt and timer interrupt */
+        clear_csr(mie, MIP_MTIP | MIP_MSIP);
+
+        if (irq_desc[core_id][int_num].handler)
+        {
+            irq_desc[core_id][int_num].handler(int_num, irq_desc[core_id][int_num].param);
+        }
+
+        /* Perform IRQ complete */
+        plic->targets.target[core_id].claim_complete = int_num;
+        /* Set MPIE and MPP flag used to MRET instructions restore MIE flag */
+        set_csr(mstatus, MSTATUS_MPIE | MSTATUS_MPP);
+        /* Restore primitive interrupt enable flag */
+        write_csr(mie, ie_flag);
+        /* Restore primitive IRQ threshold */
+        plic->targets.target[core_id].priority_threshold = int_threshold;
+    }
+    else
+    {
+        rt_kprintf("unhandled trap!\n");
+    }
+
+    return epc;
+}
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
+{
+    int cause = mcause & CAUSE_MACHINE_IRQ_REASON_MASK;
+
+    if (mcause & (1UL << 63))
+    {
+        switch (cause)
+        {
+            case IRQ_M_SOFT:
+                break;
+            case IRQ_M_EXT:
+                handle_irq_m_ext(mcause, epc);
+                break;
+            case IRQ_M_TIMER:
+                tick_isr();
+                break;
+        }
+    }
+    else
+    {
+        rt_thread_t tid;
+        extern long list_thread();
+
+        rt_hw_interrupt_disable();
+
+        tid = rt_thread_self();
+        rt_kprintf("\n");
+        rt_kprintf("unhandled trap, epc => 0x%08x, INT[%d]\n", epc, rt_interrupt_get_nest());
+        rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name);
+#ifdef RT_USING_FINSH
+        list_thread();
+#endif
+        while(1);
+    }
+
+    return epc;
+}
diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S
new file mode 100644
index 0000000000..5783322237
--- /dev/null
+++ b/libcpu/risc-v/k210/interrupt_gcc.S
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/10/02     Bernard      The first version
+ */
+
+#include "cpuport.h"
+
+  .section      .text.entry
+  .align 2
+  .global trap_entry
+trap_entry:
+
+    /* save thread context to thread stack */
+    addi sp, sp, -32 * REGBYTES
+
+    STORE x1,   1 * REGBYTES(sp)
+    li    t0,   0x80
+    STORE t0,   2 * REGBYTES(sp)
+
+    STORE x4,   4 * REGBYTES(sp)
+    STORE x5,   5 * REGBYTES(sp)
+    STORE x6,   6 * REGBYTES(sp)
+    STORE x7,   7 * REGBYTES(sp)
+    STORE x8,   8 * REGBYTES(sp)
+    STORE x9,   9 * REGBYTES(sp)
+    STORE x10, 10 * REGBYTES(sp)
+    STORE x11, 11 * REGBYTES(sp)
+    STORE x12, 12 * REGBYTES(sp)
+    STORE x13, 13 * REGBYTES(sp)
+    STORE x14, 14 * REGBYTES(sp)
+    STORE x15, 15 * REGBYTES(sp)
+    STORE x16, 16 * REGBYTES(sp)
+    STORE x17, 17 * REGBYTES(sp)
+    STORE x18, 18 * REGBYTES(sp)
+    STORE x19, 19 * REGBYTES(sp)
+    STORE x20, 20 * REGBYTES(sp)
+    STORE x21, 21 * REGBYTES(sp)
+    STORE x22, 22 * REGBYTES(sp)
+    STORE x23, 23 * REGBYTES(sp)
+    STORE x24, 24 * REGBYTES(sp)
+    STORE x25, 25 * REGBYTES(sp)
+    STORE x26, 26 * REGBYTES(sp)
+    STORE x27, 27 * REGBYTES(sp)
+    STORE x28, 28 * REGBYTES(sp)
+    STORE x29, 29 * REGBYTES(sp)
+    STORE x30, 30 * REGBYTES(sp)
+    STORE x31, 31 * REGBYTES(sp)
+
+    /* switch to interrupt stack */
+    move  s0, sp
+
+    /* get cpu id */
+    csrr  t0, mhartid
+
+    /* switch interrupt stack of current cpu */
+    la    sp, __stack_start__
+    addi  t1, t0, 1
+    li    t2, __STACKSIZE__
+    mul   t1, t1, t2
+    add   sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
+
+    /* handle interrupt */
+    call  rt_interrupt_enter
+    csrr  a0, mcause
+    csrr  a1, mepc
+    mv    a2, sp
+    call  handle_trap
+    call  rt_interrupt_leave
+
+    /* switch to from_thread stack */
+    move  sp, s0
+
+    /* need to switch new thread */
+    la    s0, rt_thread_switch_interrupt_flag
+    lw    s2, 0(s0)
+    beqz  s2, spurious_interrupt
+    sw    zero, 0(s0)
+
+    csrr  a0, mepc
+    STORE a0, 0 * REGBYTES(sp)
+
+    la    s0, rt_interrupt_from_thread
+    LOAD  s1, 0(s0)
+    STORE sp, 0(s1)
+
+    la    s0, rt_interrupt_to_thread
+    LOAD  s1, 0(s0)
+    LOAD  sp, 0(s1)
+
+    LOAD  a0,  0 * REGBYTES(sp)
+    csrw  mepc, a0
+
+spurious_interrupt:
+    LOAD  x1,   1 * REGBYTES(sp)
+
+    /* Remain in M-mode after mret */
+    li    t0, 0x00001800
+    csrs  mstatus, t0
+    LOAD  t0,   2 * REGBYTES(sp)
+    csrs  mstatus, t0 
+
+    LOAD  x4,   4 * REGBYTES(sp)
+    LOAD  x5,   5 * REGBYTES(sp)
+    LOAD  x6,   6 * REGBYTES(sp)
+    LOAD  x7,   7 * REGBYTES(sp)
+    LOAD  x8,   8 * REGBYTES(sp)
+    LOAD  x9,   9 * REGBYTES(sp)
+    LOAD  x10, 10 * REGBYTES(sp)
+    LOAD  x11, 11 * REGBYTES(sp)
+    LOAD  x12, 12 * REGBYTES(sp)
+    LOAD  x13, 13 * REGBYTES(sp)
+    LOAD  x14, 14 * REGBYTES(sp)
+    LOAD  x15, 15 * REGBYTES(sp)
+    LOAD  x16, 16 * REGBYTES(sp)
+    LOAD  x17, 17 * REGBYTES(sp)
+    LOAD  x18, 18 * REGBYTES(sp)
+    LOAD  x19, 19 * REGBYTES(sp)
+    LOAD  x20, 20 * REGBYTES(sp)
+    LOAD  x21, 21 * REGBYTES(sp)
+    LOAD  x22, 22 * REGBYTES(sp)
+    LOAD  x23, 23 * REGBYTES(sp)
+    LOAD  x24, 24 * REGBYTES(sp)
+    LOAD  x25, 25 * REGBYTES(sp)
+    LOAD  x26, 26 * REGBYTES(sp)
+    LOAD  x27, 27 * REGBYTES(sp)
+    LOAD  x28, 28 * REGBYTES(sp)
+    LOAD  x29, 29 * REGBYTES(sp)
+    LOAD  x30, 30 * REGBYTES(sp)
+    LOAD  x31, 31 * REGBYTES(sp)
+
+    addi  sp, sp, 32 * REGBYTES
+    mret
diff --git a/libcpu/risc-v/k210/startup_gcc.S b/libcpu/risc-v/k210/startup_gcc.S
new file mode 100644
index 0000000000..bc73f51e03
--- /dev/null
+++ b/libcpu/risc-v/k210/startup_gcc.S
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/10/01     Bernard      The first version
+ */
+
+#define MSTATUS_FS      0x00006000U /* initial state of FPU     */
+#include <cpuport.h>
+
+  .global	_start
+  .section ".start", "ax"
+_start:
+  j 1f
+  .word 0xdeadbeef
+1:
+  csrw mideleg, 0
+  csrw medeleg, 0
+  csrw mie, 0
+  csrw mip, 0
+  la t0, trap_entry
+  csrw mtvec, t0
+
+  li x1, 0
+  li x2, 0
+  li x3, 0
+  li x4, 0
+  li x5, 0
+  li x6, 0
+  li x7, 0
+  li x8, 0
+  li x9, 0
+  li x10,0
+  li x11,0
+  li x12,0
+  li x13,0
+  li x14,0
+  li x15,0
+  li x16,0
+  li x17,0
+  li x18,0
+  li x19,0
+  li x20,0
+  li x21,0
+  li x22,0
+  li x23,0
+  li x24,0
+  li x25,0
+  li x26,0
+  li x27,0
+  li x28,0
+  li x29,0
+  li x30,0
+  li x31,0
+
+  /* set to initial state of FPU and disable interrupt */
+  li t0, MSTATUS_FS
+  csrs mstatus, t0
+
+  fssr    x0
+  fmv.d.x f0, x0
+  fmv.d.x f1, x0
+  fmv.d.x f2, x0
+  fmv.d.x f3, x0
+  fmv.d.x f4, x0
+  fmv.d.x f5, x0
+  fmv.d.x f6, x0
+  fmv.d.x f7, x0
+  fmv.d.x f8, x0
+  fmv.d.x f9, x0
+  fmv.d.x f10,x0
+  fmv.d.x f11,x0
+  fmv.d.x f12,x0
+  fmv.d.x f13,x0
+  fmv.d.x f14,x0
+  fmv.d.x f15,x0
+  fmv.d.x f16,x0
+  fmv.d.x f17,x0
+  fmv.d.x f18,x0
+  fmv.d.x f19,x0
+  fmv.d.x f20,x0
+  fmv.d.x f21,x0
+  fmv.d.x f22,x0
+  fmv.d.x f23,x0
+  fmv.d.x f24,x0
+  fmv.d.x f25,x0
+  fmv.d.x f26,x0
+  fmv.d.x f27,x0
+  fmv.d.x f28,x0
+  fmv.d.x f29,x0
+  fmv.d.x f30,x0
+  fmv.d.x f31,x0
+
+.option push
+.option norelax
+  la gp, __global_pointer$
+.option pop
+
+  /* get cpu id */
+  csrr a0, mhartid
+
+  la   sp, __stack_start__
+  addi t1, a0, 1
+  li   t2, __STACKSIZE__
+  mul  t1, t1, t2
+  add  sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
+
+  /* other cpu core, jump to cpu entry directly */
+  bnez a0, _cpu_entry
+
+#if 0
+  /* clear bss section */
+  la a0, __bss_start
+  la a1, __bss_end
+  bgeu a0, a1, 2f
+1:
+  sw zero, (a0)
+  addi a0, a0, REGBYTES
+  bltu a0, a1, 1b
+2:
+#endif
+
+_cpu_entry:
+  csrr a0, mhartid
+  j cpu_entry
diff --git a/libcpu/risc-v/k210/tick.c b/libcpu/risc-v/k210/tick.c
new file mode 100644
index 0000000000..144f7f1fff
--- /dev/null
+++ b/libcpu/risc-v/k210/tick.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/10/28     Bernard      The unify RISC-V porting code.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <encoding.h>
+#include <clint.h>
+#include <sysctl.h>
+
+static volatile unsigned long tick_cycles = 0;
+int tick_isr(void)
+{
+    uint64_t core_id = current_coreid();
+
+    clint->mtimecmp[core_id] += tick_cycles;
+    rt_tick_increase();
+
+    return 0;
+}
+
+/* Sets and enable the timer interrupt */
+int rt_hw_tick_init(void)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    unsigned long interval = 1000/RT_TICK_PER_SECOND;
+
+    /* Clear the Machine-Timer bit in MIE */
+    clear_csr(mie, MIP_MTIP);
+
+    /* calculate the tick cycles */
+    tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1;
+    /* Set mtimecmp by core id */
+    clint->mtimecmp[core_id] = clint->mtime + tick_cycles;
+
+    /* Enable the Machine-Timer bit in MIE */
+    set_csr(mie, MIP_MTIP);
+
+    return 0;
+}
diff --git a/libcpu/risc-v/k210/tick.h b/libcpu/risc-v/k210/tick.h
new file mode 100644
index 0000000000..0821004263
--- /dev/null
+++ b/libcpu/risc-v/k210/tick.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/10/28     Bernard      The unify RISC-V porting code.
+ */
+
+#ifndef TICK_H__
+#define TICK_H__
+
+int tick_isr(void);
+int rt_hw_tick_init(void);
+
+#endif
-- 
cgit v1.3.1


From 597d71cc032bf30098c2a5f890eec48ce5ff418d Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sun, 23 Dec 2018 14:11:25 +0800
Subject: [bsp][k210] Add get_free_heap_size function.

* Add get_free_heap_size function;
* Increase shell stack for KPU module.
---
 bsp/k210/.config                 | 36 +++++++++++++++++++++++++++++++++++-
 bsp/k210/README.md               |  4 ++++
 bsp/k210/driver/SConscript       |  1 +
 bsp/k210/driver/heap.c           | 11 +++++++++++
 bsp/k210/rtconfig.h              |  2 +-
 bsp/k210/rtconfig.py             |  2 +-
 libcpu/risc-v/k210/interrupt.c   | 14 +++++++++++++-
 libcpu/risc-v/k210/startup_gcc.S |  5 +++++
 8 files changed, 71 insertions(+), 4 deletions(-)
 create mode 100644 bsp/k210/driver/heap.c

(limited to 'libcpu')

diff --git a/bsp/k210/.config b/bsp/k210/.config
index c696886459..a9737f1c80 100644
--- a/bsp/k210/.config
+++ b/bsp/k210/.config
@@ -93,7 +93,7 @@ CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_THREAD_STACK_SIZE=16384
 CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_USING_MSH=y
@@ -325,6 +325,40 @@ CONFIG_PKG_KENDRYTE_SDK_VER="v0.5.2"
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO_V001 is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO_LATEST_VERSION is not set
+# CONFIG_KENDRYTE_DEMO_NONE is not set
+# CONFIG_KENDRYTE_DEMO_AES_128_TEST is not set
+# CONFIG_KENDRYTE_DEMO_AES_192_TEST is not set
+# CONFIG_KENDRYTE_DEMO_AES_256_TEST is not set
+# CONFIG_KENDRYTE_DEMO_AI_DEMO_SIM is not set
+# CONFIG_KENDRYTE_DEMO_DVP_OV is not set
+# CONFIG_KENDRYTE_DEMO_FACE_DETECT is not set
+# CONFIG_KENDRYTE_DEMO_FFT_TEST is not set
+# CONFIG_KENDRYTE_DEMO_FLASH_W25QXX is not set
+# CONFIG_KENDRYTE_DEMO_FLASH_W25QXX_DMA_TEST is not set
+# CONFIG_KENDRYTE_DEMO_FLASH_W25QXX_TEST is not set
+# CONFIG_KENDRYTE_DEMO_GPIOHS_LED is not set
+# CONFIG_KENDRYTE_DEMO_GPIO_LED is not set
+# CONFIG_KENDRYTE_DEMO_HELLO_WORLD is not set
+# CONFIG_KENDRYTE_DEMO_I2C_SLAVE is not set
+# CONFIG_KENDRYTE_DEMO_KPU is not set
+# CONFIG_KENDRYTE_DEMO_LCD is not set
+# CONFIG_KENDRYTE_DEMO_MIC_PLAY is not set
+# CONFIG_KENDRYTE_DEMO_PLAY_PCM is not set
+# CONFIG_KENDRYTE_DEMO_PWM is not set
+# CONFIG_KENDRYTE_DEMO_RTC is not set
+# CONFIG_KENDRYTE_DEMO_RTC_SD3068 is not set
+# CONFIG_KENDRYTE_DEMO_SD_CARD is not set
+# CONFIG_KENDRYTE_DEMO_SERVO is not set
+# CONFIG_KENDRYTE_DEMO_SHA256_TEST is not set
+# CONFIG_KENDRYTE_DEMO_TIMER is not set
+# CONFIG_KENDRYTE_DEMO_UART is not set
+# CONFIG_KENDRYTE_DEMO_UART_DMA is not set
+# CONFIG_KENDRYTE_DEMO_UART_DMA_IRQ is not set
+# CONFIG_KENDRYTE_DEMO_UART_INTERRUPT is not set
+# CONFIG_KENDRYTE_DEMO_WATCHDOG is not set
 
 #
 # samples: kernel and components samples
diff --git a/bsp/k210/README.md b/bsp/k210/README.md
index 6de922d7a2..66bdf2287d 100644
--- a/bsp/k210/README.md
+++ b/bsp/k210/README.md
@@ -64,6 +64,10 @@ Kendryte中文含义为勘智，而勘智取自勘物探智。这颗芯片主要
 
 ![terminal](images/k210.png)
 
+如果是K210-test_v0.2开发板，可以用如下命令来打开串口：
+
+    python -m serial.tools.miniterm --rts 0 --dtr 0 COM9 115200
+
 ## 4. 驱动支持情况及计划
 
 | 驱动 | 支持情况  |  备注  |
diff --git a/bsp/k210/driver/SConscript b/bsp/k210/driver/SConscript
index 3ea01aa83f..7d5d6e54ce 100644
--- a/bsp/k210/driver/SConscript
+++ b/bsp/k210/driver/SConscript
@@ -5,6 +5,7 @@ from building import *
 cwd     = GetCurrentDir()
 src     = Split('''
 board.c
+heap.c
 drv_uart.c
 ''')
 CPPPATH = [cwd]
diff --git a/bsp/k210/driver/heap.c b/bsp/k210/driver/heap.c
new file mode 100644
index 0000000000..f1d6d2c27a
--- /dev/null
+++ b/bsp/k210/driver/heap.c
@@ -0,0 +1,11 @@
+#include <rtthread.h>
+#include <stdlib.h>
+
+size_t get_free_heap_size(void)
+{
+    rt_uint32_t total, used, max;
+
+    rt_memory_info(&total, &used, &max);
+
+    return total - used;
+}
diff --git a/bsp/k210/rtconfig.h b/bsp/k210/rtconfig.h
index bb101c8c8d..b5fe0dfd48 100644
--- a/bsp/k210/rtconfig.h
+++ b/bsp/k210/rtconfig.h
@@ -64,7 +64,7 @@
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
 #define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_THREAD_STACK_SIZE 16384
 #define FINSH_CMD_SIZE 80
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
diff --git a/bsp/k210/rtconfig.py b/bsp/k210/rtconfig.py
index b159d6fb9e..418c1d7456 100644
--- a/bsp/k210/rtconfig.py
+++ b/bsp/k210/rtconfig.py
@@ -50,7 +50,7 @@ if PLATFORM == 'gcc':
         CFLAGS += ' -O0 -ggdb'
         AFLAGS += ' -ggdb'
     else:
-        CFLAGS += ' -O2'
+        CFLAGS += ' -O2 -Os'
 
     CXXFLAGS = CFLAGS
 
diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c
index 6d8866c3f0..f9c3eb5a67 100644
--- a/libcpu/risc-v/k210/interrupt.c
+++ b/libcpu/risc-v/k210/interrupt.c
@@ -114,6 +114,13 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
     return old_handler;
 }
 
+RT_WEAK
+void plic_irq_handle(plic_irq_t irq)
+{
+    rt_kprintf("UN-handled interrupt %d occurred!!!\n", irq);
+    return ;
+}
+
 uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
 {
     /*
@@ -142,7 +149,12 @@ uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
         /* Disable software interrupt and timer interrupt */
         clear_csr(mie, MIP_MTIP | MIP_MSIP);
 
-        if (irq_desc[core_id][int_num].handler)
+        if (irq_desc[core_id][int_num].handler == (rt_isr_handler_t)rt_hw_interrupt_handle)
+        {
+            /* default handler, route to kendryte bsp plic driver */
+            plic_irq_handle(int_num);
+        }
+        else if (irq_desc[core_id][int_num].handler)
         {
             irq_desc[core_id][int_num].handler(int_num, irq_desc[core_id][int_num].param);
         }
diff --git a/libcpu/risc-v/k210/startup_gcc.S b/libcpu/risc-v/k210/startup_gcc.S
index bc73f51e03..2e69c5021e 100644
--- a/libcpu/risc-v/k210/startup_gcc.S
+++ b/libcpu/risc-v/k210/startup_gcc.S
@@ -16,6 +16,11 @@
 _start:
   j 1f
   .word 0xdeadbeef
+  .align 3
+  .global g_wake_up
+  g_wake_up:
+      .dword 1
+      .dword 0
 1:
   csrw mideleg, 0
   csrw medeleg, 0
-- 
cgit v1.3.1


From fb693418eed74535e01e6b1aca29a2e76536fbbd Mon Sep 17 00:00:00 2001
From: zhuhongbing <hongbingzhu@gmail.com>
Date: Wed, 26 Dec 2018 12:50:52 +0800
Subject: add project support for at91sam9260, add support for at91sam9g45

---
 bsp/at91sam9260/.config                           |  311 +
 bsp/at91sam9260/Kconfig                           |   46 +
 bsp/at91sam9260/applications/application.c        |    6 +-
 bsp/at91sam9260/drivers/board.c                   |    6 +-
 bsp/at91sam9260/drivers/led.c                     |   37 +-
 bsp/at91sam9260/platform/interrupt.c              |   58 +-
 bsp/at91sam9260/rtconfig.h                        |  268 +-
 bsp/at91sam9260/rtconfig.py                       |    6 +
 bsp/at91sam9260/template.ewp                      | 1914 ++++++
 bsp/at91sam9260/template.eww                      |   10 +
 bsp/at91sam9260/template.uvopt                    |  174 +
 bsp/at91sam9260/template.uvproj                   |  407 ++
 bsp/at91sam9g45/.config                           |  311 +
 bsp/at91sam9g45/SConscript                        |   14 +
 bsp/at91sam9g45/SConstruct                        |   39 +
 bsp/at91sam9g45/applications/SConscript           |   11 +
 bsp/at91sam9g45/applications/application.c        |  173 +
 bsp/at91sam9g45/drivers/SConscript                |   31 +
 bsp/at91sam9g45/drivers/at91_i2c_gpio.c           |  130 +
 bsp/at91sam9g45/drivers/at91_mci.c                |  924 +++
 bsp/at91sam9g45/drivers/at91_mci.h                |  124 +
 bsp/at91sam9g45/drivers/board.c                   |  248 +
 bsp/at91sam9g45/drivers/board.h                   |   32 +
 bsp/at91sam9g45/drivers/led.c                     |   54 +
 bsp/at91sam9g45/drivers/led.h                     |   32 +
 bsp/at91sam9g45/drivers/macb.c                    |  911 +++
 bsp/at91sam9g45/drivers/macb.h                    |  346 +
 bsp/at91sam9g45/drivers/mii.h                     |  191 +
 bsp/at91sam9g45/drivers/usart.c                   |  398 ++
 bsp/at91sam9g45/link_scripts/at91sam9g45_ram.icf  |   55 +
 bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld   |   98 +
 bsp/at91sam9g45/link_scripts/at91sam9g45_ram.scat |   40 +
 bsp/at91sam9g45/platform/SConscript               |   26 +
 bsp/at91sam9g45/platform/at91sam9g45.h            | 7213 +++++++++++++++++++++
 bsp/at91sam9g45/platform/gpio.h                   |  208 +
 bsp/at91sam9g45/platform/interrupt.c              |  453 ++
 bsp/at91sam9g45/platform/interrupt.h              |   31 +
 bsp/at91sam9g45/platform/io.h                     |   39 +
 bsp/at91sam9g45/platform/irq.h                    |   52 +
 bsp/at91sam9g45/platform/reset.c                  |   68 +
 bsp/at91sam9g45/platform/rt_low_level_init.c      |   63 +
 bsp/at91sam9g45/platform/rt_low_level_init.h      |   35 +
 bsp/at91sam9g45/platform/system_clock.c           |  270 +
 bsp/at91sam9g45/rtconfig.h                        |  159 +
 bsp/at91sam9g45/rtconfig.py                       |  138 +
 bsp/at91sam9g45/template.ewp                      | 1914 ++++++
 bsp/at91sam9g45/template.eww                      |   10 +
 bsp/at91sam9g45/template.uvopt                    |  174 +
 bsp/at91sam9g45/template.uvproj                   |  407 ++
 libcpu/arm/arm926/start_rvds.S                    |    9 +-
 50 files changed, 18449 insertions(+), 225 deletions(-)
 create mode 100644 bsp/at91sam9260/.config
 create mode 100644 bsp/at91sam9260/Kconfig
 create mode 100644 bsp/at91sam9260/template.ewp
 create mode 100644 bsp/at91sam9260/template.eww
 create mode 100644 bsp/at91sam9260/template.uvopt
 create mode 100644 bsp/at91sam9260/template.uvproj
 create mode 100644 bsp/at91sam9g45/.config
 create mode 100644 bsp/at91sam9g45/SConscript
 create mode 100644 bsp/at91sam9g45/SConstruct
 create mode 100644 bsp/at91sam9g45/applications/SConscript
 create mode 100644 bsp/at91sam9g45/applications/application.c
 create mode 100644 bsp/at91sam9g45/drivers/SConscript
 create mode 100644 bsp/at91sam9g45/drivers/at91_i2c_gpio.c
 create mode 100644 bsp/at91sam9g45/drivers/at91_mci.c
 create mode 100644 bsp/at91sam9g45/drivers/at91_mci.h
 create mode 100644 bsp/at91sam9g45/drivers/board.c
 create mode 100644 bsp/at91sam9g45/drivers/board.h
 create mode 100644 bsp/at91sam9g45/drivers/led.c
 create mode 100644 bsp/at91sam9g45/drivers/led.h
 create mode 100644 bsp/at91sam9g45/drivers/macb.c
 create mode 100644 bsp/at91sam9g45/drivers/macb.h
 create mode 100644 bsp/at91sam9g45/drivers/mii.h
 create mode 100644 bsp/at91sam9g45/drivers/usart.c
 create mode 100644 bsp/at91sam9g45/link_scripts/at91sam9g45_ram.icf
 create mode 100644 bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld
 create mode 100644 bsp/at91sam9g45/link_scripts/at91sam9g45_ram.scat
 create mode 100644 bsp/at91sam9g45/platform/SConscript
 create mode 100644 bsp/at91sam9g45/platform/at91sam9g45.h
 create mode 100644 bsp/at91sam9g45/platform/gpio.h
 create mode 100644 bsp/at91sam9g45/platform/interrupt.c
 create mode 100644 bsp/at91sam9g45/platform/interrupt.h
 create mode 100644 bsp/at91sam9g45/platform/io.h
 create mode 100644 bsp/at91sam9g45/platform/irq.h
 create mode 100644 bsp/at91sam9g45/platform/reset.c
 create mode 100644 bsp/at91sam9g45/platform/rt_low_level_init.c
 create mode 100644 bsp/at91sam9g45/platform/rt_low_level_init.h
 create mode 100644 bsp/at91sam9g45/platform/system_clock.c
 create mode 100644 bsp/at91sam9g45/rtconfig.h
 create mode 100644 bsp/at91sam9g45/rtconfig.py
 create mode 100644 bsp/at91sam9g45/template.ewp
 create mode 100644 bsp/at91sam9g45/template.eww
 create mode 100644 bsp/at91sam9g45/template.uvopt
 create mode 100644 bsp/at91sam9g45/template.uvproj

(limited to 'libcpu')

diff --git a/bsp/at91sam9260/.config b/bsp/at91sam9260/.config
new file mode 100644
index 0000000000..a19ac15d3d
--- /dev/null
+++ b/bsp/at91sam9260/.config
@@ -0,0 +1,311 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+CONFIG_RT_USING_INTERRUPT_INFO=y
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="dbgu"
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_AUDIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_STM32F4_HAL is not set
+# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_RT_USING_DBGU=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_RT_USING_UART1 is not set
+# CONFIG_RT_USING_UART2 is not set
+# CONFIG_RT_USING_UART3 is not set
+CONFIG_RT_USING_LED=y
diff --git a/bsp/at91sam9260/Kconfig b/bsp/at91sam9260/Kconfig
new file mode 100644
index 0000000000..f07968f982
--- /dev/null
+++ b/bsp/at91sam9260/Kconfig
@@ -0,0 +1,46 @@
+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config RT_USING_DBGU
+    bool "Using RT_USING_DBGU"
+    default y    
+	
+config RT_USING_UART0
+    bool "Using RT_USING_UART0"
+    default n    
+	
+config RT_USING_UART1
+    bool "Using RT_USING_UART1"
+    default n    
+	
+config RT_USING_UART2
+    bool "Using RT_USING_UART2"
+    default n    
+	
+config RT_USING_UART3
+    bool "Using RT_USING_UART3"
+    default n    
+	
+config RT_USING_LED
+	bool "Using RT_USING_LED"
+	default y
+	help
+		led blink demo
+ 
diff --git a/bsp/at91sam9260/applications/application.c b/bsp/at91sam9260/applications/application.c
index 5800ba53d2..48c526957a 100644
--- a/bsp/at91sam9260/applications/application.c
+++ b/bsp/at91sam9260/applications/application.c
@@ -96,7 +96,10 @@ int main(void)
 #endif
 	}
 #endif
-
+	
+#ifdef RT_USING_LED
+	rt_led_app_init();
+#endif
 }
 
 #ifdef RT_USING_LED
@@ -121,7 +124,6 @@ void rt_led_thread_entry(void* parameter)
 			led_on(3);
 		else
 			led_off(3);
-			
 	}
 }
 #endif
diff --git a/bsp/at91sam9260/drivers/board.c b/bsp/at91sam9260/drivers/board.c
index d058c30935..a7ec6008da 100644
--- a/bsp/at91sam9260/drivers/board.c
+++ b/bsp/at91sam9260/drivers/board.c
@@ -43,7 +43,7 @@ extern unsigned char __bss_end__;
 #define HEAP_BEGIN  (__section_end(".noinit"))
 #endif
 
-#define HEAP_END    (0x24000000)
+#define HEAP_END    (((rt_uint32_t)HEAP_BEGIN & (0xF0 << 24)) + (32 << 20))
 
 extern void rt_hw_interrupt_init(void);
 extern void rt_hw_clock_init(void);
@@ -57,8 +57,8 @@ static struct mem_desc at91_mem_desc[] = {
 	{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },     /* None cached for 4G memory */
 	{ 0x20000000, 0x24000000-1, 0x20000000, RW_CB },     /* 64M cached SDRAM memory */
 	{ 0x00000000, 0x100000, 0x20000000, RW_CB },         /* isr vector table */
-	{ 0x90000000, 0x90400000 - 1, 0x00200000, RW_NCNB }, /* 4K SRAM0 + 4k SRAM1 */
-	{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }   /* 64M none-cached SDRAM memory */
+	{ 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB },   /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
+	{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }    /* 64M none-cached SDRAM memory */
 };
 
 
diff --git a/bsp/at91sam9260/drivers/led.c b/bsp/at91sam9260/drivers/led.c
index 6c8f202108..3791b2a568 100644
--- a/bsp/at91sam9260/drivers/led.c
+++ b/bsp/at91sam9260/drivers/led.c
@@ -26,12 +26,27 @@
 #include <at91sam926x.h>
 #include "led.h"
 
+#if 1
+// GB9260 board
+#define PIO_LED		AT91_PIOB
+#define LED1		(1 << 25)	// LED_SYS
+#define LED2		(0)
+#define LED3		(1 << 23)	// LED_USR
+#define LED_ALL		(LED1 | LED2 | LED3)
+#else
+#define PIO_LED		AT91_PIOC
+#define LED1		(1 << 8)
+#define LED2		(1 << 11)
+#define LED3		(1 << 6)
+#define LED_ALL		(LED1 | LED2 | LED3)
+#endif
+
 void led_init(void)
 {
-	at91_sys_write(AT91_PIOC, (1<<8)|(1<<11)|(1<<6));
-	at91_sys_write(AT91_PIOC+0x10, (1<<8)|(1<<11)|(1<<6));
-	at91_sys_write(AT91_PIOC+0x64, (1<<8)|(1<<11)|(1<<6));
-	at91_sys_write(AT91_PIOC+0x30, (1<<8)|(1<<11)|(1<<6));
+	at91_sys_write(PIO_LED+0x00, LED_ALL);
+	at91_sys_write(PIO_LED+0x10, LED_ALL);
+	at91_sys_write(PIO_LED+0x64, LED_ALL);
+	at91_sys_write(PIO_LED+0x30, LED_ALL);
 }
 
 void led_on(int num)
@@ -39,18 +54,17 @@ void led_on(int num)
 	switch(num)
 	{
 		case 1:
-			at91_sys_write(AT91_PIOC+0x34, 1<<8);
+			at91_sys_write(PIO_LED+0x34, LED1);
 			break;
 		case 2:
-			at91_sys_write(AT91_PIOC+0x34, 1<<11);
+			at91_sys_write(PIO_LED+0x34, LED2);
 			break;
 		case 3:
-			at91_sys_write(AT91_PIOC+0x34, 1<<6);
+			at91_sys_write(PIO_LED+0x34, LED3);
 			break;
 		default:
 			break;
 	}
-	
 }
 
 void led_off(int num)
@@ -58,16 +72,15 @@ void led_off(int num)
 	switch(num)
 	{
 		case 1:
-			at91_sys_write(AT91_PIOC+0x30, 1<<8);
+			at91_sys_write(PIO_LED+0x30, LED1);
 			break;
 		case 2:
-			at91_sys_write(AT91_PIOC+0x30, 1<<11);
+			at91_sys_write(PIO_LED+0x30, LED2);
 			break;
 		case 3:
-			at91_sys_write(AT91_PIOC+0x30, 1<<6);
+			at91_sys_write(PIO_LED+0x30, LED3);
 			break;
 		default:
 			break;
 	}
-	//at91_sys_write(AT91_PIOC+0x30, 1<<8);
 }
diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c
index 7a83fca494..0708460578 100644
--- a/bsp/at91sam9260/platform/interrupt.c
+++ b/bsp/at91sam9260/platform/interrupt.c
@@ -30,7 +30,7 @@
 extern rt_uint32_t rt_interrupt_nest;
 
 /* exception and interrupt handler table */
-struct rt_irq_desc irq_desc[MAX_HANDLERS]; 
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
 
 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
 rt_uint32_t rt_thread_switch_interrupt_flag;
@@ -101,17 +101,17 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector, void *param)
     rt_uint32_t isr, pio, irq_n;
     void *parameter;
 
-    if (vector == AT91SAM9260_ID_PIOA) 
+    if (vector == AT91SAM9260_ID_PIOA)
     {
         pio = AT91_PIOA;
         irq_n = AIC_IRQS;
     }
-    else if (vector == AT91SAM9260_ID_PIOB) 
+    else if (vector == AT91SAM9260_ID_PIOB)
     {
         pio = AT91_PIOB;
         irq_n = AIC_IRQS + 32;
     }
-    else if (vector == AT91SAM9260_ID_PIOC) 
+    else if (vector == AT91SAM9260_ID_PIOC)
     {
         pio = AT91_PIOC;
         irq_n = AIC_IRQS + 32*2;
@@ -119,9 +119,9 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector, void *param)
     else
         return RT_NULL;
     isr = at91_sys_read(pio+PIO_ISR) & at91_sys_read(pio+PIO_IMR);
-    while (isr) 
+    while (isr)
     {
-        if (isr & 1) 
+        if (isr & 1)
         {
             parameter = irq_desc[irq_n].param;
             irq_desc[irq_n].handler(irq_n, parameter);
@@ -175,7 +175,7 @@ static void at91_gpio_irq_init()
 {
     int i, idx;
     char *name[] = {"PIOA", "PIOB", "PIOC"};
-    
+
     at91_sys_write(AT91_PIOA+PIO_IDR, 0xffffffff);
     at91_sys_write(AT91_PIOB+PIO_IDR, 0xffffffff);
     at91_sys_write(AT91_PIOC+PIO_IDR, 0xffffffff);
@@ -183,11 +183,13 @@ static void at91_gpio_irq_init()
     idx = AT91SAM9260_ID_PIOA;
     for (i = 0; i < 3; i++)
     {
-        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
         irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle;
         irq_desc[idx].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
         irq_desc[idx].counter = 0;
-        idx++;
+#endif
+		idx++;
     }
 
     rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA);
@@ -203,7 +205,7 @@ void rt_hw_interrupt_init(void)
 {
     register rt_uint32_t idx;
     rt_uint32_t *priority = at91sam9260_default_irq_priority;
-    
+
     at91_extern_irq = (1UL << AT91SAM9260_ID_IRQ0) | (1UL << AT91SAM9260_ID_IRQ1)
             | (1UL << AT91SAM9260_ID_IRQ2);
 
@@ -213,10 +215,12 @@ void rt_hw_interrupt_init(void)
     /* init exceptions table */
     for(idx=0; idx < MAX_HANDLERS; idx++)
     {
-        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
         irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
         irq_desc[idx].param = RT_NULL;
-		irq_desc[idx].counter = 0;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx].counter = 0;
+#endif
     }
 
     at91_gpio_irq_init();
@@ -234,15 +238,15 @@ static void at91_gpio_irq_mask(int irq)
 
     bank = (irq - AIC_IRQS)>>5;
 
-    if (bank == 0) 
+    if (bank == 0)
     {
         pio = AT91_PIOA;
     }
-    else if (bank == 1) 
+    else if (bank == 1)
     {
         pio = AT91_PIOB;
     }
-    else if (bank == 2) 
+    else if (bank == 2)
     {
         pio = AT91_PIOC;
     }
@@ -258,7 +262,7 @@ static void at91_gpio_irq_mask(int irq)
  */
 void rt_hw_interrupt_mask(int irq)
 {
-    if (irq >= AIC_IRQS) 
+    if (irq >= AIC_IRQS)
     {
         at91_gpio_irq_mask(irq);
     }
@@ -275,15 +279,15 @@ static void at91_gpio_irq_umask(int irq)
 
     bank = (irq - AIC_IRQS)>>5;
 
-    if (bank == 0) 
+    if (bank == 0)
     {
         pio = AT91_PIOA;
     }
-    else if (bank == 1) 
+    else if (bank == 1)
     {
         pio = AT91_PIOB;
     }
-    else if (bank == 2) 
+    else if (bank == 2)
     {
         pio = AT91_PIOC;
     }
@@ -299,7 +303,7 @@ static void at91_gpio_irq_umask(int irq)
  */
 void rt_hw_interrupt_umask(int irq)
 {
-    if (irq >= AIC_IRQS) 
+    if (irq >= AIC_IRQS)
     {
         at91_gpio_irq_umask(irq);
     }
@@ -328,10 +332,12 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
         old_handler = irq_desc[vector].handler;
         if (handler != RT_NULL)
         {
-            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
             irq_desc[vector].handler = (rt_isr_handler_t)handler;
             irq_desc[vector].param = param;
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
 			irq_desc[vector].counter = 0;
+#endif
         }
     }
 
@@ -353,15 +359,15 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
         srctype = AT91_AIC_SRCTYPE_RISING;
         break;
     case IRQ_TYPE_LEVEL_LOW:
-        // only supported on external interrupts 
-        if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))     
+        // only supported on external interrupts
+        if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))
             srctype = AT91_AIC_SRCTYPE_LOW;
         else
             return -1;
         break;
     case IRQ_TYPE_EDGE_FALLING:
-        // only supported on external interrupts 
-        if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))     
+        // only supported on external interrupts
+        if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))
             srctype = AT91_AIC_SRCTYPE_FALLING;
         else
             return -1;
@@ -409,7 +415,7 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
 void list_irq(void)
 {
 	int irq;
-	
+
 	rt_kprintf("number\tcount\tname\n");
 	for (irq = 0; irq < MAX_HANDLERS; irq++)
 	{
diff --git a/bsp/at91sam9260/rtconfig.h b/bsp/at91sam9260/rtconfig.h
index b9ec26f390..816054c3e1 100755
--- a/bsp/at91sam9260/rtconfig.h
+++ b/bsp/at91sam9260/rtconfig.h
@@ -1,254 +1,160 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
 
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	32
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
 
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	256
-
-/* Tick per Second */
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug */
-#define RT_DEBUG
-//#define SCHEDULER_DEBUG
-/* #define RT_THREAD_DEBUG */
+/* RT-Thread Kernel */
 
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
-
-#define RT_USING_INTERRUPT_INFO
-
-/* Using Hook */
 #define RT_USING_HOOK
+#define RT_IDEL_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_DEBUG
 
-/* Using Software Timer */
-#define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO		8
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
+/* Inter-Thread communication */
 
-/* SECTION: IPC */
-/* Using Semaphore */
 #define RT_USING_SEMAPHORE
-
-/* Using Mutex */
 #define RT_USING_MUTEX
-
-/* Using Event */
 #define RT_USING_EVENT
-
-/* Using MailBox */
 #define RT_USING_MAILBOX
-
-/* Using Message Queue */
 #define RT_USING_MESSAGEQUEUE
 
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
+/* Memory Management */
 
-/* Using Dynamic Heap Management */
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
 #define RT_USING_HEAP
 
-/* Using Small MM */
-/* #define RT_USING_SMALL_MEM */
+/* Kernel Device Object */
 
-/* Using SLAB Allocator */
-#define RT_USING_SLAB
+#define RT_USING_DEVICE
+#define RT_USING_INTERRUPT_INFO
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "dbgu"
 
-/* SECTION: the runtime libc library */
-/* the runtime libc library */
-#define RT_USING_LIBC
-#define RT_USING_PTHREADS
+/* RT-Thread Components */
 
-/* Using Module System */
-#define RT_USING_MODULE
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
 
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
+/* C++ features */
 
 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
 #define RT_SERIAL_USING_DMA
 
-/* SECTION: Console options */
-#define RT_USING_CONSOLE
-/* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	128
-#define RT_CONSOLE_DEVICE_NAME "dbgu"
+/* Command shell */
 
-/* SECTION: finsh, a C-Express shell */
-/* Using FinSH as Shell*/
 #define RT_USING_FINSH
-/* Using symbol table */
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
 #define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
 #define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
 
-/* SECTION: C++ support */
-/* Using C++ support */
-/* #define RT_USING_CPLUSPLUS */
+/* Device virtual file system */
 
-/* SECTION: Device filesystem support */
-/* using DFS support */
 #define RT_USING_DFS
-#define RT_USING_DFS_ELMFAT
-/* use long file name feature */
-#define RT_DFS_ELM_USE_LFN			2
-#define RT_DFS_ELM_REENTRANT
-/* define OEM code page */
-#define RT_DFS_ELM_CODE_PAGE	936
-/* Using OEM code page file */
-// #define RT_DFS_ELM_CODE_PAGE_FILE
-/* the max number of file length */
-#define RT_DFS_ELM_MAX_LFN			128
-/* #define RT_USING_DFS_YAFFS2 */
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
 #define RT_USING_DFS_DEVFS
 
-#define RT_USING_DFS_NFS
-#define RT_NFS_HOST_EXPORT		"192.168.1.5:/"
+/* Device Drivers */
 
-#define DFS_USING_WORKDIR
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_USING_PIN
 
-/* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX		4
-/* the max number of opened files */
-#define DFS_FD_MAX					16
-/* the max number of cached sector */
-#define DFS_CACHE_MAX_NUM   		4
+/* Using USB */
 
-/* Enable freemodbus protocol stack*/
-/* #define RT_USING_MODBUS */
 
-//#define RT_USING_LED
+/* POSIX layer and C standard library */
 
-#define RT_USING_SDIO
+#define RT_USING_LIBC
 
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
+/* Network */
 
-#define RT_USING_DBGU
-/* #define RT_USING_UART0 */
-/* #define RT_USING_UART1 */
-/* #define RT_USING_UART2 */
-/* #define RT_USING_UART3 */
+/* Socket abstraction layer */
 
-/* SECTION: lwip, a lightweight TCP/IP protocol stack */
-/* Using lightweight TCP/IP protocol stack */
-#define RT_USING_LWIP
-#define RT_LWIP_DNS
 
-/* Trace LwIP protocol */
-// #define RT_LWIP_DEBUG
+/* light weight TCP/IP stack */
 
-/* Enable ICMP protocol */
-#define RT_LWIP_ICMP
 
-/* Enable IGMP protocol */
-#define RT_LWIP_IGMP
+/* Modbus master and slave stack */
 
-/* Enable UDP protocol */
-#define RT_LWIP_UDP
 
-/* Enable TCP protocol */
-#define RT_LWIP_TCP
+/* AT commands */
 
-/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM	5
 
-/* TCP sender buffer space */
-#define RT_LWIP_TCP_SND_BUF	1024*10
+/* VBUS(Virtual Software BUS) */
 
-/* TCP receive window. */
-#define RT_LWIP_TCP_WND	1024*8
 
-/* Enable SNMP protocol */
-/* #define RT_LWIP_SNMP */
+/* Utilities */
 
-/* Using DHCP */
-/* #define RT_LWIP_DHCP */
 
-/* ip address of target */
-#define RT_LWIP_IPADDR "192.168.1.30"
+/* RT-Thread online packages */
 
-/* gateway address of target */
-#define RT_LWIP_GWADDR  "192.168.1.1"
+/* IoT - internet of things */
 
-/* mask address of target */
-#define RT_LWIP_MSKADDR  "255.255.255.0"
 
-/* the number of blocks for pbuf */
-#define RT_LWIP_PBUF_NUM	16
+/* Wi-Fi */
 
-/* the number of simultaneously queued TCP */
-#define RT_LWIP_TCP_SEG_NUM    40
+/* Marvell WiFi */
 
-/* thread priority of tcpip thread */
-#define RT_LWIP_TCPTHREAD_PRIORITY	128
 
-/* mail box size of tcpip thread to wait for */
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	32
+/* Wiced WiFi */
 
-/* thread stack size of tcpip thread */
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
 
-/* thread priority of ethnetif thread */
-#define RT_LWIP_ETHTHREAD_PRIORITY	144
+/* IoT Cloud */
 
-/* mail box size of ethnetif thread to wait for */
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	32
 
-/* thread stack size of ethnetif thread */
-#define RT_LWIP_ETHTHREAD_STACKSIZE	1024
+/* security packages */
 
 
-/* SECTION: RTGUI support */
-/* using RTGUI support */
-/* #define RT_USING_RTGUI */
+/* language packages */
 
-/* name length of RTGUI object */
-//#define RTGUI_NAME_MAX		16
-/* support 16 weight font */
-//#define RTGUI_USING_FONT16
-/* support 16 weight font */
-//#define RTGUI_USING_FONT12
-/* support Chinese font */
-//#define RTGUI_USING_FONTHZ
-/* use DFS as file interface */
-//#define RTGUI_USING_DFS_FILERW
-/* use font file as Chinese font */
-/* #define RTGUI_USING_HZ_FILE */
-/* use Chinese bitmap font */
-//#define RTGUI_USING_HZ_BMP
-/* use small size in RTGUI */
-/* #define RTGUI_USING_SMALL_SIZE */
-/* use mouse cursor */
-/* #define RTGUI_USING_MOUSE_CURSOR */
 
-/* SECTION: FTK support */
-/* using FTK support */
-/* #define RT_USING_FTK */
+/* multimedia packages */
 
-/*
- * Note on FTK:
- *
- * FTK depends :
- * #define RT_USING_NEWLIB
- * #define DFS_USING_WORKDIR
- *
- * And the maximal length must great than 64
- * #define RT_DFS_ELM_MAX_LFN	128
- */
 
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* sample package */
+
+/* samples: kernel and components samples */
+
+
+/* example package: hello */
+
+#define RT_USING_DBGU
+#define RT_USING_LED
 
 #endif
diff --git a/bsp/at91sam9260/rtconfig.py b/bsp/at91sam9260/rtconfig.py
index 3aefb30fad..da3be0fd59 100755
--- a/bsp/at91sam9260/rtconfig.py
+++ b/bsp/at91sam9260/rtconfig.py
@@ -11,6 +11,12 @@ if os.getenv('RTT_CC'):
 if  CROSS_TOOL == 'gcc':
 	PLATFORM 	= 'gcc'
 	EXEC_PATH = r'D:\arm-2013.11\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	EXEC_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2'
 
 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
diff --git a/bsp/at91sam9260/template.ewp b/bsp/at91sam9260/template.ewp
new file mode 100644
index 0000000000..c9cc04c3db
--- /dev/null
+++ b/bsp/at91sam9260/template.ewp
@@ -0,0 +1,1914 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>24</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>build\Debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>build\Debug\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>build\Debug\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting, without multibyte support.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting, without multibyte support.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>7.40.3.8937</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.40.3.8937</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>AT91SAM9260	Atmel AT91SAM9260</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>22</version>
+          <state>12</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>22</version>
+          <state>12</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state>AT91SAM9260	Atmel AT91SAM9260</state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>22</version>
+          <state>12</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCDefines</name>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>00000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCNoLiteralPool</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategySlave</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCGuardCalls</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>9</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
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+          <state>3</state>
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+          <state>1</state>
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+        <option>
+          <name>OOCOutputFile</name>
+          <state>rtthread.bin</state>
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+        <option>
+          <name>OOCCommandLineProducer</name>
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+        <extensions></extensions>
+        <cmdline></cmdline>
+        <hasPrio>0</hasPrio>
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+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+          <state></state>
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+          <state></state>
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+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
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+          <state></state>
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+          <name>IlinkRawBinaryAlign</name>
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+          <state>$PROJ_DIR$\link_scripts\at91sam9260_ram.icf</state>
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+          <state>1</state>
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+          <state></state>
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+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+          <name>CrcFullSize</name>
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+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
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+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
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+        <option>
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+          <state></state>
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+        <option>
+          <name>IlinkThreadsSlave</name>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCNoLiteralPool</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategySlave</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCGuardCalls</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>9</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state>$PROJ_DIR$\platform</state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>3</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>c.srec</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+        <hasPrio>0</hasPrio>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>16</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>rtthread.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\link_scripts\at91sam9260_ram.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+</project>
+
+
diff --git a/bsp/at91sam9260/template.eww b/bsp/at91sam9260/template.eww
new file mode 100644
index 0000000000..bd036bb4c9
--- /dev/null
+++ b/bsp/at91sam9260/template.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
diff --git a/bsp/at91sam9260/template.uvopt b/bsp/at91sam9260/template.uvopt
new file mode 100644
index 0000000000..2dca5102b8
--- /dev/null
+++ b/bsp/at91sam9260/template.uvopt
@@ -0,0 +1,174 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>18432000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>16</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ATMEL\AT91SAM9260_DS.PDF</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Summary</Title>
+          <Path>DATASHTS\ATMEL\AT91SAM9260_DC.PDF</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>5</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\jlink\at91sam9260.ini</tIfile>
+        <pMon>Segger\JLTAgdi.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JLTAgdi</Key>
+          <Name>-O558 -J1 -Y1000 -Z1 -FO0 -FD200000 -FC800 -FN0</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2ARM</Key>
+          <Name>-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
diff --git a/bsp/at91sam9260/template.uvproj b/bsp/at91sam9260/template.uvproj
new file mode 100644
index 0000000000..c644bc5440
--- /dev/null
+++ b/bsp/at91sam9260/template.uvproj
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>AT91SAM9260</Device>
+          <Vendor>Atmel</Vendor>
+          <Cpu>IRAM(0x200000-0x200FFF) IRAM2(0x300000-0x300FFF) IROM(0x100000-0x107FFF) CLOCK(18432000) CPUTYPE(ARM926EJ-S)</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\Atmel\SAM9260.s" ("Atmel AT91SAM9260 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2ARM(-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)</FlashDriverDll>
+          <DeviceId>4210</DeviceId>
+          <RegisterFile>AT91SAM9260.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Atmel\SAM9260\</RegisterFilePath>
+          <DBRegisterFilePath>Atmel\SAM9260\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARM.DLL</SimDllName>
+          <SimDllArguments>-cAT91SAM9260</SimDllArguments>
+          <SimDlgDll>DARMATS9.DLL</SimDlgDll>
+          <SimDlgDllArguments>-p91SAM9260</SimDlgDllArguments>
+          <TargetDllName>SARM.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMATS9.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-p91SAM9260</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>5</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\jlink\at91sam9260.ini</InitializationFile>
+            <Driver>Segger\JLTAgdi.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2ARM.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4>.\jlink\at91sam9260.ini</Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>ARM926EJ-S</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>1</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>1</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x1000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x100000</StartAddress>
+                <Size>0x8000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x800000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x100000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x20800000</StartAddress>
+                <Size>0x1800000</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x300000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>RT_USING_INTERRUPT_INFO</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\platform</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x20000000</TextAddressRange>
+            <DataAddressRange>0x20800000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\link_scripts\at91sam9260_ram.scat</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/bsp/at91sam9g45/.config b/bsp/at91sam9g45/.config
new file mode 100644
index 0000000000..5f3ae78673
--- /dev/null
+++ b/bsp/at91sam9g45/.config
@@ -0,0 +1,311 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+CONFIG_RT_USING_INTERRUPT_INFO=y
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="dbgu"
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+CONFIG_RT_USING_CPLUSPLUS=y
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_AUDIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+CONFIG_RT_USING_PTHREADS=y
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_STM32F4_HAL is not set
+# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_RT_USING_DBGU=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_RT_USING_UART1 is not set
+# CONFIG_RT_USING_UART2 is not set
+# CONFIG_RT_USING_UART3 is not set
+CONFIG_RT_USING_LED=y
diff --git a/bsp/at91sam9g45/SConscript b/bsp/at91sam9g45/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/at91sam9g45/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/at91sam9g45/SConstruct b/bsp/at91sam9g45/SConstruct
new file mode 100644
index 0000000000..41139a3377
--- /dev/null
+++ b/bsp/at91sam9g45/SConstruct
@@ -0,0 +1,39 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-at91sam9g45.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+if GetDepend('RT_USING_WEBSERVER'):
+    objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0)
+
+if GetDepend('RT_USING_RTGUI'):
+    objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
+
+# libc testsuite 
+objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/at91sam9g45/applications/SConscript b/bsp/at91sam9g45/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/at91sam9g45/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/at91sam9g45/applications/application.c b/bsp/at91sam9g45/applications/application.c
new file mode 100644
index 0000000000..ec878faa85
--- /dev/null
+++ b/bsp/at91sam9g45/applications/application.c
@@ -0,0 +1,173 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-01-13     weety		first version
+ */
+
+/**
+ * @addtogroup at91sam9260
+ */
+/*@{*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#ifdef RT_USING_DFS
+/* dfs Filesystem APIs */
+#include <dfs_fs.h>
+#endif
+
+#ifdef RT_USING_SDIO
+#include <drivers/mmcsd_core.h>
+#include "at91_mci.h"
+#endif
+
+#ifdef RT_USING_LED
+#include "led.h"
+#endif
+
+static int rt_led_app_init(void);
+
+RT_WEAK int main(void)
+{
+#ifdef RT_USING_SDIO
+	int timeout = 0;
+#endif
+
+/* Filesystem Initialization */
+#ifdef RT_USING_DFS
+	{
+#if defined(RT_USING_DFS_ROMFS)
+		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
+		{
+			rt_kprintf("ROM File System initialized!\n");
+		}
+		else
+			rt_kprintf("ROM File System initialzation failed!\n");
+#endif
+
+#if defined(RT_USING_DFS_UFFS)
+	{
+		/* mount flash device as flash directory */
+		if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
+			rt_kprintf("UFFS File System initialized!\n");
+		else
+			rt_kprintf("UFFS File System initialzation failed!\n");
+	}
+#endif
+
+#ifdef RT_USING_SDIO
+	timeout = 0;
+	while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
+	{
+		rt_thread_delay(1);
+	}
+
+	if (timeout < RT_TICK_PER_SECOND*2)
+	{
+		/* mount sd card fat partition 1 as root directory */
+		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+		{
+			rt_kprintf("File System initialized!\n");
+		}
+		else
+			rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
+	}
+	else
+	{
+		rt_kprintf("No SD card found.\n");
+	}
+#endif
+	}
+#endif
+
+	rt_led_app_init();
+}
+
+#ifdef RT_USING_LED
+void rt_led_thread_entry(void* parameter)
+{
+	rt_uint8_t cnt = 0;
+	led_init();
+	while(1)
+	{
+		/* light on leds for one second */
+		rt_thread_delay(40);
+		cnt++;
+		if (cnt&0x01)
+			led_on(1);
+		else
+			led_off(1);
+		if (cnt&0x02)
+			led_on(2);
+		else
+			led_off(2);
+		if (cnt&0x04)
+			led_on(3);
+		else
+			led_off(3);
+			
+	}
+}
+#endif
+
+static int rt_led_app_init(void)
+{
+#ifdef RT_USING_LED
+	rt_thread_t led_thread;
+
+#if (RT_THREAD_PRIORITY_MAX == 32)
+	led_thread = rt_thread_create("led",
+								rt_led_thread_entry, RT_NULL,
+								512, 20, 20);						
+#else
+	led_thread = rt_thread_create("led",
+								rt_led_thread_entry, RT_NULL,
+								512, 200, 20);					
+#endif
+
+	if(led_thread != RT_NULL)
+		rt_thread_startup(led_thread);
+#endif
+
+	return 0;
+}
+
+/* NFSv3 Initialization */
+#if defined(RT_USING_DFS) && defined(RT_USING_LWIP) && defined(RT_USING_DFS_NFS)
+#include <dfs_nfs.h>
+void nfs_start(void)
+{
+	nfs_init();
+
+	if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
+	{
+		rt_kprintf("NFSv3 File System initialized!\n");
+	}
+	else
+		rt_kprintf("NFSv3 File System initialzation failed!\n");
+}
+
+#include "finsh.h"
+FINSH_FUNCTION_EXPORT(nfs_start, start net filesystem);
+#endif
+
+/*@}*/
diff --git a/bsp/at91sam9g45/drivers/SConscript b/bsp/at91sam9g45/drivers/SConscript
new file mode 100644
index 0000000000..d0470f9049
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/SConscript
@@ -0,0 +1,31 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+
+# add the general drvers.
+src = Split("""
+board.c
+usart.c
+""")
+
+# add Ethernet drvers.
+if GetDepend('RT_USING_LED'):
+	src += ['led.c']
+
+if GetDepend('RT_USING_SDIO'):
+	src += ['at91_mci.c']
+
+if GetDepend('RT_USING_LWIP'):
+	src += ['macb.c']
+
+if GetDepend('RT_USING_I2C') and GetDepend('RT_USING_I2C_BITOPS'):
+	src += ['at91_i2c_gpio.c']
+
+    
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/at91sam9g45/drivers/at91_i2c_gpio.c b/bsp/at91sam9g45/drivers/at91_i2c_gpio.c
new file mode 100644
index 0000000000..91ca646c7a
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/at91_i2c_gpio.c
@@ -0,0 +1,130 @@
+/*
+ * File      : at91_i2c_gpio.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2012-04-25     weety		first version
+ */
+
+#include <rtdevice.h>
+#include <rthw.h>
+#include <at91sam9g45.h>
+
+
+static void at91_i2c_gpio_init()
+{
+	AT91C_BASE_PMC->PMC_PCER  = 1 << AT91C_ID_PIOA; //enable PIOA clock
+	AT91C_BASE_PIOA->PIO_PUER = (1 << 23);
+	AT91C_BASE_PIOA->PIO_PER  = (1 << 23);
+	AT91C_BASE_PIOA->PIO_MDER = (1 << 23);
+	AT91C_BASE_PIOA->PIO_PUER = (1 << 24);
+	AT91C_BASE_PIOA->PIO_PER  = (1 << 24);
+	AT91C_BASE_PIOA->PIO_MDER = (1 << 24);
+
+	AT91C_BASE_PIOA->PIO_OER  = (1 << 23);
+	AT91C_BASE_PIOA->PIO_OER  = (1 << 24);
+
+	AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
+	AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
+}
+
+static void at91_set_sda(void *data, rt_int32_t state)
+{
+	if (state)
+	{
+		AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
+	}
+	else
+	{
+		AT91C_BASE_PIOA->PIO_CODR = (1 << 23);
+	}
+}
+
+static void at91_set_scl(void *data, rt_int32_t state)
+{
+	if (state)
+	{
+		AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
+	}
+	else
+	{
+		AT91C_BASE_PIOA->PIO_CODR = (1 << 24);
+	}
+}
+
+static rt_int32_t  at91_get_sda(void *data)
+{
+	return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23);
+}
+
+static rt_int32_t  at91_get_scl(void *data)
+{
+	return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24);
+}
+
+static void at91_udelay (rt_uint32_t us)
+{
+	rt_int32_t i;
+	for (; us > 0; us--)
+	{
+		i = 50000;
+		while(i > 0)
+		{
+			i--;
+		}
+	}
+}
+
+static const struct rt_i2c_bit_ops bit_ops = {
+	RT_NULL,
+	at91_set_sda,
+	at91_set_scl,
+	at91_get_sda,
+	at91_get_scl,
+	
+	at91_udelay,
+
+	5,
+	100
+};
+
+int at91_i2c_init(void)
+{
+	struct rt_i2c_bus_device *bus;
+
+	bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
+	if (bus == RT_NULL)
+	{
+		rt_kprintf("rt_malloc failed\n");
+		return -RT_ENOMEM;
+	}
+	
+	rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
+
+	bus->priv = (void *)&bit_ops;
+
+	at91_i2c_gpio_init();
+
+	rt_i2c_bit_add_bus(bus, "i2c0");
+
+	return 0;
+}
+
+INIT_DEVICE_EXPORT(at91_i2c_init);
+
diff --git a/bsp/at91sam9g45/drivers/at91_mci.c b/bsp/at91sam9g45/drivers/at91_mci.c
new file mode 100644
index 0000000000..0ad5590df6
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/at91_mci.c
@@ -0,0 +1,924 @@
+/*
+ * File      : at91_mci.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author		Notes
+ * 2011-07-25     weety		first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <drivers/mmcsd_core.h>
+#include <at91sam9g45.h>
+#include "at91_mci.h"
+
+#define USE_SLOT_B
+//#define RT_MCI_DBG
+
+#ifdef RT_MCI_DBG
+#define mci_dbg(fmt, ...)  rt_kprintf(fmt, ##__VA_ARGS__)
+#else
+#define mci_dbg(fmt, ...)
+#endif
+
+#define MMU_NOCACHE_ADDR(a)      	((rt_uint32_t)a | (1UL<<31))
+
+extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
+extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
+
+
+#define AT91C_MCI_ERRORS	(AT91C_MCI_RINDE | AT91C_MCI_RDIRE | AT91C_MCI_RCRCE	\
+		| AT91C_MCI_RENDE | AT91C_MCI_RTOE | AT91C_MCI_DCRCE		\
+		| AT91C_MCI_DTOE | AT91C_MCI_OVRE | AT91C_MCI_UNRE)
+
+#define at91_mci_read(reg)	readl(AT91C_BASE_MCI + (reg))
+#define at91_mci_write(reg, val)	writel((val), AT91C_BASE_MCI + (reg))
+
+
+#define REQ_ST_INIT	(1U << 0)
+#define REQ_ST_CMD	(1U << 1)
+#define REQ_ST_STOP	(1U << 2)
+
+struct at91_mci {
+	struct rt_mmcsd_host *host;
+	struct rt_mmcsd_req *req;
+	struct rt_mmcsd_cmd *cmd;
+	struct rt_timer timer;
+	//struct rt_semaphore sem_ack;
+	rt_uint32_t *buf;
+	rt_uint32_t current_status;
+};
+
+/*
+ * Reset the controller and restore most of the state
+ */
+static void at91_reset_host()
+{
+	rt_uint32_t mr;
+	rt_uint32_t sdcr;
+	rt_uint32_t dtor;
+	rt_uint32_t imr;
+	rt_uint32_t level;
+
+	level = rt_hw_interrupt_disable();
+
+	imr = at91_mci_read(AT91C_MCI_IMR);
+
+	at91_mci_write(AT91C_MCI_IDR, 0xffffffff);
+
+	/* save current state */
+	mr = at91_mci_read(AT91C_MCI_MR) & 0x7fff;
+	sdcr = at91_mci_read(AT91C_MCI_SDCR);
+	dtor = at91_mci_read(AT91C_MCI_DTOR);
+
+	/* reset the controller */
+	at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST);
+
+	/* restore state */
+	at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN);
+	at91_mci_write(AT91C_MCI_MR, mr);
+	at91_mci_write(AT91C_MCI_SDCR, sdcr);
+	at91_mci_write(AT91C_MCI_DTOR, dtor);
+	at91_mci_write(AT91C_MCI_IER, imr);
+
+	/* make sure sdio interrupts will fire */
+	at91_mci_read(AT91C_MCI_SR);
+	rt_hw_interrupt_enable(level);
+
+}
+
+
+/*
+ * Enable the controller
+ */
+static void at91_mci_enable()
+{
+	rt_uint32_t mr;
+
+	at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN);
+	at91_mci_write(AT91C_MCI_IDR, 0xffffffff);
+	at91_mci_write(AT91C_MCI_DTOR, AT91C_MCI_DTOMUL_1M | AT91C_MCI_DTOCYC);
+	mr = AT91C_MCI_PDCMODE | 0x34a;
+
+	mr |= AT91C_MCI_RDPROOF | AT91C_MCI_WRPROOF;
+
+	at91_mci_write(AT91C_MCI_MR, mr);
+
+	/* use Slot A or B (only one at same time) */
+	at91_mci_write(AT91C_MCI_SDCR, 1); /* use slot b */
+}
+
+/*
+ * Disable the controller
+ */
+static void at91_mci_disable()
+{
+	at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST);
+}
+
+static void at91_timeout_timer(void *data)
+{
+	struct at91_mci *mci;
+
+	mci = (struct at91_mci *)data;
+
+	if (mci->req) 
+	{
+		rt_kprintf("Timeout waiting end of packet\n");
+
+		if (mci->current_status == REQ_ST_CMD) 
+		{
+			if (mci->req->cmd && mci->req->data) 
+			{
+				mci->req->data->err = -RT_ETIMEOUT;
+			} 
+			else 
+			{
+				if (mci->req->cmd)
+					mci->req->cmd->err = -RT_ETIMEOUT;
+			}
+		}
+		else if (mci->current_status == REQ_ST_STOP) 
+		{
+			mci->req->stop->err = -RT_ETIMEOUT;
+		}
+
+		at91_reset_host();
+		mmcsd_req_complete(mci->host);
+	}
+}
+
+/*
+ * Prepare a dma read
+ */
+static void at91_mci_init_dma_read(struct at91_mci *mci)
+{
+	rt_uint8_t i;
+	struct rt_mmcsd_cmd *cmd;
+	struct rt_mmcsd_data *data;
+	rt_uint32_t length;
+
+	mci_dbg("pre dma read\n");
+
+	cmd = mci->cmd;
+	if (!cmd)
+	{
+		mci_dbg("no command\n");
+		return;
+	}
+
+	data = cmd->data;
+	if (!data)
+	{
+		mci_dbg("no data\n");
+		return;
+	}
+
+	for (i = 0; i < 1; i++) 
+	{
+		/* Check to see if this needs filling */
+		if (i == 0) 
+		{
+			if (at91_mci_read(AT91C_PDC_RCR) != 0) 
+			{
+				mci_dbg("Transfer active in current\n");
+				continue;
+			}
+		}
+		else {
+			if (at91_mci_read(AT91C_PDC_RNCR) != 0)
+			{
+				mci_dbg("Transfer active in next\n");
+				continue;
+			}
+		}
+
+		length = data->blksize * data->blks;
+		mci_dbg("dma address = %08X, length = %d\n", data->buf, length);
+
+		if (i == 0) 
+		{
+			at91_mci_write(AT91C_PDC_RPR, (rt_uint32_t)(data->buf));
+			at91_mci_write(AT91C_PDC_RCR, (data->blksize & 0x3) ? length : length / 4);
+		}
+		else 
+		{
+			at91_mci_write(AT91C_PDC_RNPR, (rt_uint32_t)(data->buf));
+			at91_mci_write(AT91C_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4);
+		}
+	}
+
+	mci_dbg("pre dma read done\n");
+}
+
+/*
+ * Send a command
+ */
+static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd)
+{
+	rt_uint32_t cmdr, mr;
+	rt_uint32_t block_length;
+	struct rt_mmcsd_data *data = cmd->data;
+	struct rt_mmcsd_host *host = mci->host;
+
+	rt_uint32_t blocks;
+	rt_uint32_t ier = 0;
+	rt_uint32_t length;
+
+	mci->cmd = cmd;
+
+	/* Needed for leaving busy state before CMD1 */
+	if ((at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_RTOE) && (cmd->cmd_code == 1)) 
+	{
+		mci_dbg("Clearing timeout\n");
+		at91_mci_write(AT91C_MCI_ARGR, 0);
+		at91_mci_write(AT91C_MCI_CMDR, AT91C_MCI_OPDCMD);
+		while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) 
+		{
+			/* spin */
+			mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91C_MCI_SR));
+		}
+	}
+
+	cmdr = cmd->cmd_code;
+
+	if (resp_type(cmd) == RESP_NONE)
+		cmdr |= AT91C_MCI_RSPTYP_NONE;
+	else 
+	{
+		/* if a response is expected then allow maximum response latancy */
+		cmdr |= AT91C_MCI_MAXLAT;
+		/* set 136 bit response for R2, 48 bit response otherwise */
+		if (resp_type(cmd) == RESP_R2)
+			cmdr |= AT91C_MCI_RSPTYP_136;
+		else
+			cmdr |= AT91C_MCI_RSPTYP_48;
+	}
+
+	if (data) 
+	{
+
+		block_length = data->blksize;
+		blocks = data->blks;
+
+		/* always set data start - also set direction flag for read */
+		if (data->flags & DATA_DIR_READ)
+			cmdr |= (AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START);
+		else if (data->flags & DATA_DIR_WRITE)
+			cmdr |= AT91C_MCI_TRCMD_START;
+
+		if (data->flags & DATA_STREAM)
+			cmdr |= AT91C_MCI_TRTYP_STREAM;
+		if (data->blks > 1)
+			cmdr |= AT91C_MCI_TRTYP_MULTIPLE;
+	}
+	else 
+	{
+		block_length = 0;
+		blocks = 0;
+	}
+
+	/*if (cmd->cmd_code == GO_IDLE_STATE) 
+	{
+		cmdr |= AT91C_MCI_SPCMD_INIT;
+	}*/
+
+	if (cmd->cmd_code == STOP_TRANSMISSION)
+		cmdr |= AT91C_MCI_TRCMD_STOP;
+
+	if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN)
+		cmdr |= AT91C_MCI_OPDCMD;
+
+	/*
+	 * Set the arguments and send the command
+	 */
+	mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
+		cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91C_MCI_MR));
+
+	if (!data) 
+	{
+		at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS);
+		at91_mci_write(AT91C_PDC_RPR, 0);
+		at91_mci_write(AT91C_PDC_RCR, 0);
+		at91_mci_write(AT91C_PDC_RNPR, 0);
+		at91_mci_write(AT91C_PDC_RNCR, 0);
+		at91_mci_write(AT91C_PDC_TPR, 0);
+		at91_mci_write(AT91C_PDC_TCR, 0);
+		at91_mci_write(AT91C_PDC_TNPR, 0);
+		at91_mci_write(AT91C_PDC_TNCR, 0);
+		ier = AT91C_MCI_CMDRDY;
+	} 
+	else 
+	{
+		/* zero block length and PDC mode */
+		mr = at91_mci_read(AT91C_MCI_MR) & 0x5fff;
+		mr |= (data->blksize & 0x3) ? AT91C_MCI_PDCFBYTE : 0;
+		mr |= (block_length << 16);
+		mr |= AT91C_MCI_PDCMODE;
+		at91_mci_write(AT91C_MCI_MR, mr);
+
+		at91_mci_write(AT91C_MCI_BLKR,
+			AT91C_MCI_BLKR_BCNT(blocks) |
+			AT91C_MCI_BLKR_BLKLEN(block_length));
+
+		/*
+		 * Disable the PDC controller
+		 */
+		at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
+
+		if (cmdr & AT91C_MCI_TRCMD_START) 
+		{
+			if (cmdr & AT91C_MCI_TRDIR) 
+			{
+				/*
+				 * Handle a read
+				 */
+
+				mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
+				at91_mci_init_dma_read(mci);
+				ier = AT91C_MCI_ENDRX /* | AT91C_MCI_RXBUFF */;
+			}
+			else 
+			{
+				/*
+				 * Handle a write
+				 */
+				length = block_length * blocks;
+				/*
+				 * at91mci MCI1 rev2xx Data Write Operation and
+				 * number of bytes erratum
+				 */
+				if (length < 12)
+				{
+					length = 12;
+					mci->buf = rt_malloc(length);
+					if (!mci->buf)
+					{
+						rt_kprintf("rt alloc tx buffer failed\n");
+						cmd->err = -RT_ENOMEM;
+						mmcsd_req_complete(mci->host);
+						return;
+					}
+					rt_memset(mci->buf, 0, 12);
+					rt_memcpy(mci->buf, data->buf, length);
+					mmu_clean_dcache((rt_uint32_t)mci->buf, length);
+					at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(mci->buf));
+					at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ?
+							length : length / 4);
+				}
+				else
+				{
+					mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
+					at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(data->buf));
+					at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ?
+							length : length / 4);
+				}
+				mci_dbg("Transmitting %d bytes\n", length);
+				ier = AT91C_MCI_CMDRDY;
+			}
+		}
+	}
+
+	/*
+	 * Send the command and then enable the PDC - not the other way round as
+	 * the data sheet says
+	 */
+
+	at91_mci_write(AT91C_MCI_ARGR, cmd->arg);
+	at91_mci_write(AT91C_MCI_CMDR, cmdr);
+
+	if (cmdr & AT91C_MCI_TRCMD_START) 
+	{
+		if (cmdr & AT91C_MCI_TRDIR)
+			at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTEN);
+	}
+
+	/* Enable selected interrupts */
+	at91_mci_write(AT91C_MCI_IER, AT91C_MCI_ERRORS | ier);
+}
+
+/*
+ * Process the next step in the request
+ */
+static void at91_mci_process_next(struct at91_mci *mci)
+{
+	if (mci->current_status == REQ_ST_INIT) 
+	{
+		mci->current_status = REQ_ST_CMD;
+		at91_mci_send_command(mci, mci->req->cmd);
+	}
+	else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) 
+	{
+		mci->current_status = REQ_ST_STOP;
+		at91_mci_send_command(mci, mci->req->stop);
+	} 
+	else 
+	{
+		rt_timer_stop(&mci->timer);
+		/* the mci controller hangs after some transfers,
+		 * and the workaround is to reset it after each transfer.
+		 */
+		at91_reset_host();
+		mmcsd_req_complete(mci->host);
+	}
+}
+
+/*
+ * Handle an MMC request
+ */
+static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+	rt_uint32_t timeout = RT_TICK_PER_SECOND;
+	struct at91_mci *mci = host->private_data;
+	mci->req = req;
+	mci->current_status = REQ_ST_INIT;
+
+	rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout);
+	rt_timer_start(&mci->timer);
+
+	at91_mci_process_next(mci);
+}
+
+/*
+ * Handle transmitted data
+ */
+static void at91_mci_handle_transmitted(struct at91_mci *mci)
+{
+	struct rt_mmcsd_cmd *cmd;
+	struct rt_mmcsd_data *data;
+
+	mci_dbg("Handling the transmit\n");
+
+	/* Disable the transfer */
+	at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
+
+	/* Now wait for cmd ready */
+	at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_TXBUFE);
+
+	cmd = mci->cmd;
+	if (!cmd) return;
+
+	data = cmd->data;
+	if (!data) return;
+
+	if (data->blks > 1) 
+	{
+		mci_dbg("multiple write : wait for BLKE...\n");
+		at91_mci_write(AT91C_MCI_IER, AT91C_MCI_BLKE);
+	} else
+		at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY);
+}
+
+
+/*
+ * Handle after a dma read
+ */
+static void at91_mci_post_dma_read(struct at91_mci *mci)
+{
+	struct rt_mmcsd_cmd *cmd;
+	struct rt_mmcsd_data *data;
+
+	mci_dbg("post dma read\n");
+
+	cmd = mci->cmd;
+	if (!cmd)
+	{
+		mci_dbg("no command\n");
+		return;
+	}
+
+	data = cmd->data;
+	if (!data)
+	{
+		mci_dbg("no data\n");
+		return;
+	}
+
+	at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_ENDRX);
+	at91_mci_write(AT91C_MCI_IER, AT91C_MCI_RXBUFF);
+
+	mci_dbg("post dma read done\n");
+}
+
+/*Handle after command sent ready*/
+static int at91_mci_handle_cmdrdy(struct at91_mci *mci)
+{
+	if (!mci->cmd)
+		return 1;
+	else if (!mci->cmd->data) 
+	{
+		if (mci->current_status == REQ_ST_STOP) 
+		{
+			/*After multi block write, we must wait for NOTBUSY*/
+			at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY);
+		}
+		else return 1;
+	}
+	else if (mci->cmd->data->flags & DATA_DIR_WRITE)
+	{
+		/*After sendding multi-block-write command, start DMA transfer*/
+		at91_mci_write(AT91C_MCI_IER, AT91C_MCI_TXBUFE | AT91C_MCI_BLKE);
+		at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTEN);
+	}
+
+	/* command not completed, have to wait */
+	return 0;
+}
+
+/*
+ * Handle a command that has been completed
+ */
+static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status)
+{
+	struct rt_mmcsd_cmd *cmd = mci->cmd;
+	struct rt_mmcsd_data *data = cmd->data;
+
+	at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB));
+
+	cmd->resp[0] = at91_mci_read(AT91C_MCI_RSPR(0));
+	cmd->resp[1] = at91_mci_read(AT91C_MCI_RSPR(1));
+	cmd->resp[2] = at91_mci_read(AT91C_MCI_RSPR(2));
+	cmd->resp[3] = at91_mci_read(AT91C_MCI_RSPR(3));
+
+	if (mci->buf) 
+	{
+		//rt_memcpy(data->buf, mci->buf, data->blksize*data->blks);
+		rt_free(mci->buf);
+		mci->buf = RT_NULL;
+	}
+
+	mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n",
+		 status, at91_mci_read(AT91C_MCI_SR),
+		 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+
+	if (status & AT91C_MCI_ERRORS) 
+	{
+		if ((status & AT91C_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) 
+		{
+			cmd->err = 0;
+		}
+		else 
+		{
+			if (status & (AT91C_MCI_DTOE | AT91C_MCI_DCRCE)) 
+			{
+				if (data) 
+				{
+					if (status & AT91C_MCI_DTOE)
+						data->err = -RT_ETIMEOUT;
+					else if (status & AT91C_MCI_DCRCE)
+						data->err = -RT_ERROR;
+				}
+			} 
+			else 
+			{
+				if (status & AT91C_MCI_RTOE)
+					cmd->err = -RT_ETIMEOUT;
+				else if (status & AT91C_MCI_RCRCE)
+					cmd->err = -RT_ERROR;
+				else
+					cmd->err = -RT_ERROR;
+			}
+
+			rt_kprintf("error detected and set to %d/%d (cmd = %d)\n",
+				cmd->err, data ? data->err : 0,
+				 cmd->cmd_code);
+		}
+	}
+	else
+		cmd->err = 0;
+
+	at91_mci_process_next(mci);
+}
+
+/*
+ * Handle an interrupt
+ */
+static void at91_mci_irq(int irq, void *param)
+{
+	struct at91_mci *mci = (struct at91_mci *)param;
+	rt_int32_t completed = 0;
+	rt_uint32_t int_status, int_mask;
+
+	int_status = at91_mci_read(AT91C_MCI_SR);
+	int_mask = at91_mci_read(AT91C_MCI_IMR);
+
+	mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
+		int_status & int_mask);
+
+	int_status = int_status & int_mask;
+
+	if (int_status & AT91C_MCI_ERRORS) 
+	{
+		completed = 1;
+
+		if (int_status & AT91C_MCI_UNRE)
+			mci_dbg("MMC: Underrun error\n");
+		if (int_status & AT91C_MCI_OVRE)
+			mci_dbg("MMC: Overrun error\n");
+		if (int_status & AT91C_MCI_DTOE)
+			mci_dbg("MMC: Data timeout\n");
+		if (int_status & AT91C_MCI_DCRCE)
+			mci_dbg("MMC: CRC error in data\n");
+		if (int_status & AT91C_MCI_RTOE)
+			mci_dbg("MMC: Response timeout\n");
+		if (int_status & AT91C_MCI_RENDE)
+			mci_dbg("MMC: Response end bit error\n");
+		if (int_status & AT91C_MCI_RCRCE)
+			mci_dbg("MMC: Response CRC error\n");
+		if (int_status & AT91C_MCI_RDIRE)
+			mci_dbg("MMC: Response direction error\n");
+		if (int_status & AT91C_MCI_RINDE)
+			mci_dbg("MMC: Response index error\n");
+	} 
+	else 
+	{
+		/* Only continue processing if no errors */
+
+		if (int_status & AT91C_MCI_TXBUFE) 
+		{
+			mci_dbg("TX buffer empty\n");
+			at91_mci_handle_transmitted(mci);
+		}
+
+		if (int_status & AT91C_MCI_ENDRX) 
+		{
+			mci_dbg("ENDRX\n");
+			at91_mci_post_dma_read(mci);
+		}
+
+		if (int_status & AT91C_MCI_RXBUFF) 
+		{
+			mci_dbg("RX buffer full\n");
+			at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
+			at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_RXBUFF | AT91C_MCI_ENDRX);
+			completed = 1;
+		}
+
+		if (int_status & AT91C_MCI_ENDTX)
+			mci_dbg("Transmit has ended\n");
+
+		if (int_status & AT91C_MCI_NOTBUSY) 
+		{
+			mci_dbg("Card is ready\n");
+			//at91_mci_update_bytes_xfered(host);
+			completed = 1;
+		}
+
+		if (int_status & AT91C_MCI_DTIP)
+			mci_dbg("Data transfer in progress\n");
+
+		if (int_status & AT91C_MCI_BLKE) 
+		{
+			mci_dbg("Block transfer has ended\n");
+			if (mci->req->data && mci->req->data->blks > 1) 
+			{
+				/* multi block write : complete multi write
+				 * command and send stop */
+				completed = 1;
+			} 
+			else 
+			{
+				at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY);
+			}
+		}
+
+		/*if (int_status & AT91C_MCI_SDIOIRQA)
+			rt_mmcsd_signal_sdio_irq(host->mmc);*/
+
+		if (int_status & AT91C_MCI_SDIOIRQB)
+			sdio_irq_wakeup(mci->host);
+
+		if (int_status & AT91C_MCI_TXRDY)
+			mci_dbg("Ready to transmit\n");
+
+		if (int_status & AT91C_MCI_RXRDY)
+			mci_dbg("Ready to receive\n");
+
+		if (int_status & AT91C_MCI_CMDRDY) 
+		{
+			mci_dbg("Command ready\n");
+			completed = at91_mci_handle_cmdrdy(mci);
+		}
+	}
+
+	if (completed) 
+	{
+		mci_dbg("Completed command\n");
+		at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB));
+		at91_mci_completed_command(mci, int_status);
+	} 
+	else
+		at91_mci_write(AT91C_MCI_IDR, int_status & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB));
+
+}
+
+
+/*
+ * Set the IOCFG
+ */
+static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+	rt_uint32_t clkdiv;
+	//struct at91_mci *mci = host->private_data;
+	rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck"));
+
+	if (io_cfg->clock == 0) 
+	{
+		/* Disable the MCI controller */
+		at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS);
+		clkdiv = 0;
+	}
+	else 
+	{
+		/* Enable the MCI controller */
+		at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN);
+
+		if ((at91_master_clock % (io_cfg->clock * 2)) == 0)
+			clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1;
+		else
+			clkdiv = (at91_master_clock / io_cfg->clock) / 2;
+
+		mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv,
+			at91_master_clock / (2 * (clkdiv + 1)));
+	}
+	if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) 
+	{
+		mci_dbg("MMC: Setting controller bus width to 4\n");
+		at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) | AT91C_MCI_SDCBUS);
+	}
+	else 
+	{
+		mci_dbg("MMC: Setting controller bus width to 1\n");
+		at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) & ~AT91C_MCI_SDCBUS);
+	}
+
+	/* Set the clock divider */
+	at91_mci_write(AT91C_MCI_MR, (at91_mci_read(AT91C_MCI_MR) & ~AT91C_MCI_CLKDIV) | clkdiv);
+
+	/* maybe switch power to the card */
+	switch (io_cfg->power_mode) 
+	{
+		case MMCSD_POWER_OFF:
+			break;
+		case MMCSD_POWER_UP:
+			break;
+		case MMCSD_POWER_ON:
+			/*at91_mci_write(AT91C_MCI_ARGR, 0);
+			at91_mci_write(AT91C_MCI_CMDR, 0|AT91C_MCI_SPCMD_INIT|AT91C_MCI_OPDCMD);
+			mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91C_MCI_SR));
+			while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) 
+			{
+				
+			}
+			mci_dbg("at91 mci power on\n");*/
+			break;
+		default:
+			rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode);
+			break;
+	}
+
+}
+
+
+static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable)
+{
+	at91_mci_write(enable ? AT91C_MCI_IER : AT91C_MCI_IDR, AT91C_MCI_SDIOIRQB);
+}
+
+
+static const struct rt_mmcsd_host_ops ops = {
+	at91_mci_request,
+	at91_mci_set_iocfg,
+        RT_NULL,
+	at91_mci_enable_sdio_irq,
+};
+
+void at91_mci_detect(int irq, void *param)
+{
+	rt_kprintf("mmcsd gpio detected\n");
+}
+
+static void mci_gpio_init()
+{
+#ifdef USE_SLOT_B
+	AT91C_BASE_PIOA->PIO_PUER = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5);
+	AT91C_BASE_PIOA->PIO_PUDR = (1 << 8);
+	AT91C_BASE_PIOA->PIO_BSR  = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5);
+	AT91C_BASE_PIOA->PIO_ASR  = (1 << 8);
+	AT91C_BASE_PIOA->PIO_PDR  = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8);
+
+	AT91C_BASE_PIOA->PIO_IDR  = (1 << 6)|(1 << 7);
+	AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7);
+	AT91C_BASE_PIOA->PIO_ODR  = (1 << 6)|(1 << 7);
+	AT91C_BASE_PIOA->PIO_PER  = (1 << 6)|(1 << 7);
+#else
+	AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11);
+	AT91C_BASE_PIOA->PIO_ASR  = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8);
+	AT91C_BASE_PIOA->PIO_PDR  = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8);
+#endif
+}
+
+int at91_mci_init(void)
+{
+	struct rt_mmcsd_host *host;
+	struct at91_mci *mci;
+
+	host = mmcsd_alloc_host();
+	if (!host) 
+	{
+		return -RT_ERROR;
+	}
+
+	mci = rt_malloc(sizeof(struct at91_mci));
+	if (!mci) 
+	{
+		rt_kprintf("alloc mci failed\n");
+		goto err;
+	}
+
+	rt_memset(mci, 0, sizeof(struct at91_mci));
+
+	host->ops = &ops;
+	host->freq_min = 375000;
+	host->freq_max = 25000000;
+	host->valid_ocr = VDD_32_33 | VDD_33_34;
+	host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
+				MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
+	host->max_seg_size = 65535;
+	host->max_dma_segs = 2;
+	host->max_blk_size = 512;
+	host->max_blk_count = 4096;
+
+	mci->host = host;
+
+	mci_gpio_init();
+	AT91C_BASE_PMC->AT91C_PMC_PCER = 1 << AT91C_ID_MCI; //enable MCI clock
+	
+	at91_mci_disable();
+	at91_mci_enable();
+
+	/* instal interrupt */
+	rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, 
+							(void *)mci, "MMC");
+	rt_hw_interrupt_umask(AT91SAM9260_ID_MCI);
+	rt_hw_interrupt_install(gpio_to_irq(AT91C_PIN_PA7), 
+							at91_mci_detect, RT_NULL, "MMC_DETECT");
+	rt_hw_interrupt_umask(gpio_to_irq(AT91C_PIN_PA7));
+
+	rt_timer_init(&mci->timer, "mci_timer", 
+		at91_timeout_timer, 
+		mci, 
+		RT_TICK_PER_SECOND, 
+		RT_TIMER_FLAG_PERIODIC);
+
+	//rt_timer_start(&mci->timer);
+
+	//rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
+
+	host->private_data = mci;
+
+	mmcsd_change(host);
+
+	return 0;
+
+err:
+	mmcsd_free_host(host);
+
+	return -RT_ENOMEM;
+}
+
+INIT_DEVICE_EXPORT(at91_mci_init);
+
+#include "finsh.h"
+FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init);
+
+void mci_dump(void)
+{
+	rt_uint32_t i;
+
+	rt_kprintf("PIOA_PSR=0x%08x\n", readl(AT91C_PIOA+PIO_PSR));
+	rt_kprintf("PIOA_ABSR=0x%08x\n", readl(AT91C_PIOA+PIO_ABSR));
+	rt_kprintf("PIOA_PUSR=0x%08x\n", readl(AT91C_PIOA+PIO_PUSR));
+
+	for (i = 0; i <= 0x4c; i += 4) {
+		rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i));
+	}
+}
+
+FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci);
diff --git a/bsp/at91sam9g45/drivers/at91_mci.h b/bsp/at91sam9g45/drivers/at91_mci.h
new file mode 100644
index 0000000000..b3bfd289b1
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/at91_mci.h
@@ -0,0 +1,124 @@
+/*
+ * File      : at91_mci.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-06-09     weety      first version
+ */
+
+#ifndef __AT91C_MCI_H__
+#define __AT91C_MCI_H__
+
+#define AT91C_MCI_CR		0x00		/* Control Register */
+#define		AT91C_MCI_MCIEN		(1 <<  0)	/* Multi-Media Interface Enable */
+#define		AT91C_MCI_MCIDIS		(1 <<  1)	/* Multi-Media Interface Disable */
+#define		AT91C_MCI_PWSEN		(1 <<  2)	/* Power Save Mode Enable */
+#define		AT91C_MCI_PWSDIS		(1 <<  3)	/* Power Save Mode Disable */
+#define		AT91C_MCI_SWRST		(1 <<  7)	/* Software Reset */
+
+#define AT91C_MCI_MR		0x04		/* Mode Register */
+#define		AT91C_MCI_CLKDIV		(0xff  <<  0)	/* Clock Divider */
+#define		AT91C_MCI_PWSDIV		(7     <<  8)	/* Power Saving Divider */
+#define		AT91C_MCI_RDPROOF	(1     << 11)	/* Read Proof Enable [SAM926[03] only] */
+#define		AT91C_MCI_WRPROOF	(1     << 12)	/* Write Proof Enable [SAM926[03] only] */
+#define		AT91C_MCI_PDCFBYTE	(1     << 13)	/* PDC Force Byte Transfer [SAM926[03] only] */
+#define		AT91C_MCI_PDCPADV	(1     << 14)	/* PDC Padding Value */
+#define		AT91C_MCI_PDCMODE	(1     << 15)	/* PDC-orientated Mode */
+#define		AT91C_MCI_BLKLEN		(0xfff << 18)	/* Data Block Length */
+
+#define AT91C_MCI_DTOR		0x08		/* Data Timeout Register */
+#define		AT91C_MCI_DTOCYC		(0xf << 0)	/* Data Timeout Cycle Number */
+#define		AT91C_MCI_DTOMUL		(7   << 4)	/* Data Timeout Multiplier */
+#define		AT91C_MCI_DTOMUL_1		(0 <<  4)
+#define		AT91C_MCI_DTOMUL_16		(1 <<  4)
+#define		AT91C_MCI_DTOMUL_128		(2 <<  4)
+#define		AT91C_MCI_DTOMUL_256		(3 <<  4)
+#define		AT91C_MCI_DTOMUL_1K		(4 <<  4)
+#define		AT91C_MCI_DTOMUL_4K		(5 <<  4)
+#define		AT91C_MCI_DTOMUL_64K		(6 <<  4)
+#define		AT91C_MCI_DTOMUL_1M		(7 <<  4)
+
+#define AT91C_MCI_SDCR		0x0c		/* SD Card Register */
+#define		AT91C_MCI_SDCSEL		(3 << 0)	/* SD Card Selector */
+#define		AT91C_MCI_SDCBUS		(1 << 7)	/* 1-bit or 4-bit bus */
+
+#define AT91C_MCI_ARGR		0x10		/* Argument Register */
+
+#define AT91C_MCI_CMDR		0x14		/* Command Register */
+#define		AT91C_MCI_CMDNB		(0x3f << 0)	/* Command Number */
+#define		AT91C_MCI_RSPTYP		(3    << 6)	/* Response Type */
+#define			AT91C_MCI_RSPTYP_NONE	(0 <<  6)
+#define			AT91C_MCI_RSPTYP_48	(1 <<  6)
+#define			AT91C_MCI_RSPTYP_136	(2 <<  6)
+#define		AT91C_MCI_SPCMD		(7    << 8)	/* Special Command */
+#define			AT91C_MCI_SPCMD_NONE	(0 <<  8)
+#define			AT91C_MCI_SPCMD_INIT	(1 <<  8)
+#define			AT91C_MCI_SPCMD_SYNC	(2 <<  8)
+#define			AT91C_MCI_SPCMD_ICMD	(4 <<  8)
+#define			AT91C_MCI_SPCMD_IRESP	(5 <<  8)
+#define		AT91C_MCI_OPDCMD		(1 << 11)	/* Open Drain Command */
+#define		AT91C_MCI_MAXLAT		(1 << 12)	/* Max Latency for Command to Response */
+#define		AT91C_MCI_TRCMD		(3 << 16)	/* Transfer Command */
+#define			AT91C_MCI_TRCMD_NONE	(0 << 16)
+#define			AT91C_MCI_TRCMD_START	(1 << 16)
+#define			AT91C_MCI_TRCMD_STOP	(2 << 16)
+#define		AT91C_MCI_TRDIR		(1 << 18)	/* Transfer Direction */
+#define		AT91C_MCI_TRTYP		(3 << 19)	/* Transfer Type */
+#define			AT91C_MCI_TRTYP_BLOCK	(0 << 19)
+#define			AT91C_MCI_TRTYP_MULTIPLE	(1 << 19)
+#define			AT91C_MCI_TRTYP_STREAM	(2 << 19)
+
+#define AT91C_MCI_BLKR		0x18		/* Block Register */
+#define		AT91C_MCI_BLKR_BCNT(n)	((0xffff & (n)) << 0)	/* Block count */
+#define		AT91C_MCI_BLKR_BLKLEN(n)	((0xffff & (n)) << 16)	/* Block lenght */
+
+#define AT91C_MCI_RSPR(n)	(0x20 + ((n) * 4))	/* Response Registers 0-3 */
+#define AT91C_MCR_RDR		0x30		/* Receive Data Register */
+#define AT91C_MCR_TDR		0x34		/* Transmit Data Register */
+
+#define AT91C_MCI_SR		0x40		/* Status Register */
+#define		AT91C_MCI_CMDRDY		(1U <<  0)	/* Command Ready */
+#define		AT91C_MCI_RXRDY		(1U <<  1)	/* Receiver Ready */
+#define		AT91C_MCI_TXRDY		(1U <<  2)	/* Transmit Ready */
+#define		AT91C_MCI_BLKE		(1U <<  3)	/* Data Block Ended */
+#define		AT91C_MCI_DTIP		(1U <<  4)	/* Data Transfer in Progress */
+#define		AT91C_MCI_NOTBUSY	(1U <<  5)	/* Data Not Busy */
+#define		AT91C_MCI_ENDRX		(1U <<  6)	/* End of RX Buffer */
+#define		AT91C_MCI_ENDTX		(1U <<  7)	/* End fo TX Buffer */
+#define		AT91C_MCI_SDIOIRQA	(1U <<  8)	/* SDIO Interrupt for Slot A */
+#define		AT91C_MCI_SDIOIRQB	(1U <<  9)	/* SDIO Interrupt for Slot B */
+#define		AT91C_MCI_RXBUFF		(1U << 14)	/* RX Buffer Full */
+#define		AT91C_MCI_TXBUFE		(1U << 15)	/* TX Buffer Empty */
+#define		AT91C_MCI_RINDE		(1U << 16)	/* Response Index Error */
+#define		AT91C_MCI_RDIRE		(1U << 17)	/* Response Direction Error */
+#define		AT91C_MCI_RCRCE		(1U << 18)	/* Response CRC Error */
+#define		AT91C_MCI_RENDE		(1U << 19)	/* Response End Bit Error */
+#define		AT91C_MCI_RTOE		(1U << 20)	/* Reponse Time-out Error */
+#define		AT91C_MCI_DCRCE		(1U << 21)	/* Data CRC Error */
+#define		AT91C_MCI_DTOE		(1U << 22)	/* Data Time-out Error */
+#define		AT91C_MCI_OVRE		(1U << 30)	/* Overrun */
+#define		AT91C_MCI_UNRE		(1U << 31)	/* Underrun */
+
+#define AT91C_MCI_IER		0x44		/* Interrupt Enable Register */
+#define AT91C_MCI_IDR		0x48		/* Interrupt Disable Register */
+#define AT91C_MCI_IMR		0x4c		/* Interrupt Mask Register */
+
+extern int at91_mci_init(void);
+
+#endif
diff --git a/bsp/at91sam9g45/drivers/board.c b/bsp/at91sam9g45/drivers/board.c
new file mode 100644
index 0000000000..c14055f310
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/board.c
@@ -0,0 +1,248 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "board.h"
+#include <mmu.h>
+
+/**
+ * @addtogroup at91sam9g45
+ */
+/*@{*/
+#if defined(__CC_ARM)
+extern int Image$$ER_ZI$$ZI$$Limit;
+#define HEAP_BEGIN  (&Image$$ER_ZI$$ZI$$Limit)
+#elif (defined (__GNUC__))
+extern unsigned char __bss_end__;
+#define HEAP_BEGIN  (&__bss_end__)
+#elif (defined (__ICCARM__))
+#pragma section=".noinit"
+#define HEAP_BEGIN  (__section_end(".noinit"))
+#endif
+
+#define HEAP_END    (((rt_uint32_t)HEAP_BEGIN & 0xF0000000) + 0x04000000)
+
+extern void rt_hw_interrupt_init(void);
+extern void rt_hw_clock_init(void);
+
+extern void rt_hw_get_clock(void);
+extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
+extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
+extern void rt_dbgu_isr(void);
+
+#define SAM9G45_BLOCK_SIZE	0x10000000		// 256M
+#define MMU_SECTION_SIZE	0x100000		// 1M
+#define PERIPHERALS_ADDR			// 1M
+
+#define SECTION_END(sa)		((sa) + MMU_SECTION_SIZE - 1)	// sa: start address
+#define BLOCK_END(ba)		((ba) + SAM9G45_BLOCK_SIZE - 1)	// ba: block address
+
+static struct mem_desc at91_mem_desc[] = {	/* FIXME, hornby, to confirm MMU and memory */
+	  { 0x00000000,             0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */
+	//{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB  }, /* TLB for ITCM, ITCM map to address zero, 32KB */
+	//{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB  }, /* TLB for DTCM, 32KB */
+	//{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB  }, /* TLB for internal RAM, 64KB, we use it as global variable area */
+	//{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */
+	//{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */
+	//{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */
+	//{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB   }, /* 1M external SRAM for program code and stack */
+	//{ 0x40000000,   BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */
+	//{ 0x60000000,   BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */
+	//{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */
+	  { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB   }, /* isr */
+	  { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB   }, /* 128M for main DDR-SDRAM for print data */
+	//{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */
+};
+
+
+#define PIT_CPIV(x)		((x) & AT91C_PITC_CPIV)
+#define PIT_PICNT(x)	(((x) & AT91C_PITC_PICNT) >> 20)
+
+static rt_uint32_t pit_cycle;	/* write-once */
+static rt_uint32_t pit_cnt;		/* access only w/system irq blocked */
+
+/**
+ * This function will handle rtos timer
+ */
+void rt_timer_handler(int vector, void *param)
+{
+#ifdef RT_USING_DBGU
+	if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY)
+	{
+		rt_dbgu_isr();
+	}
+#endif
+	if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS)
+	{
+		unsigned nr_ticks;
+
+		/* Get number of ticks performed before irq, and ack it */
+		nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR));
+        while (nr_ticks--)
+    		rt_tick_increase();
+	}
+}
+
+static void at91sam9g45_pit_reset(void)
+{
+	/* Disable timer and irqs */
+	AT91C_BASE_PITC->PITC_PIMR = 0;
+
+	/* Clear any pending interrupts, wait for PIT to stop counting */
+	while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0)
+		;
+
+	/* Start PIT but don't enable IRQ */
+	//AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN;
+	pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR));
+	AT91C_BASE_PITC->PITC_PIMR =
+			(pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+	rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR));
+}
+
+/*
+ * Set up both clocksource and clockevent support.
+ */
+static void at91sam9g45_pit_init(void)
+{
+	rt_uint32_t	pit_rate;
+	//rt_uint32_t	bits;
+
+	/*
+	 * Use our actual MCK to figure out how many MCK/16 ticks per
+	 * 1/HZ period (instead of a compile-time constant LATCH).
+	 */
+	pit_rate = clk_get_rate(clk_get("mck")) / 16;
+	rt_kprintf("pit_rate=%dHZ\n", pit_rate);
+	pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
+
+	/* Initialize and enable the timer */
+	at91sam9g45_pit_reset();
+}
+
+/**
+ * This function will init pit for system ticks
+ */
+void rt_hw_timer_init()
+{
+	at91sam9g45_pit_init();
+
+	/* install interrupt handler */
+	rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler,
+							RT_NULL, "system");
+	rt_hw_interrupt_umask(AT91C_ID_SYS);
+}
+
+void at91_tc1_init()
+{
+	AT91C_BASE_PMC->PMC_PCER = 1<<AT91C_ID_TC;
+	writel(AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE, AT91C_TCB0_BMR);
+	writel(AT91C_TC_CLKDIS, AT91C_TC0_CCR);
+	writel(AT91C_TC_CLKS_TIMER_DIV4_CLOCK, AT91C_TC0_CMR);
+	writel(0xffff, AT91C_TC0_CV);
+}
+
+#define BPS			115200	/* serial console port baudrate */
+
+static void at91_usart_putc(char c)
+{
+	while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY))
+		;
+	AT91C_BASE_DBGU->DBGU_THR = c;
+}
+
+/**
+ * This function is used to display a string on console, normally, it's
+ * invoked by rt_kprintf
+ *
+ * @param str the displayed string
+ */
+void rt_hw_console_output(const char* str)
+{
+	while (*str)
+	{
+		if (*str=='\n')
+		{
+			at91_usart_putc('\r');
+		}
+
+		at91_usart_putc(*str++);
+	}
+}
+
+static void rt_hw_console_init(void)
+{
+	int div;
+	int mode = 0;
+
+	AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
+	       AT91C_US_RXDIS | AT91C_US_TXDIS;
+	mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
+	       AT91C_US_CHMODE_NORMAL;
+	mode |= AT91C_US_CHRL_8_BITS;
+	mode |= AT91C_US_NBSTOP_1_BIT;
+	mode |= AT91C_US_PAR_NONE;
+	AT91C_BASE_DBGU->DBGU_MR = mode;
+	div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
+	AT91C_BASE_DBGU->DBGU_BRGR = div;
+	AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+}
+
+
+/**
+ * This function will init at91sam9g45 board
+ */
+void rt_hw_board_init()
+{
+	/* initialize the system clock */
+	rt_hw_clock_init();
+
+	/* initialize console */
+	rt_hw_console_init();
+
+	/* initialize mmu */
+	rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
+
+	/* initialize hardware interrupt */
+	rt_hw_interrupt_init();
+
+	/* initialize early device */
+#ifdef RT_USING_COMPONENTS_INIT
+	rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+	/* initialize timer0 */
+	rt_hw_timer_init();
+
+/* initialize board */
+#ifdef RT_USING_HEAP
+	rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/at91sam9g45/drivers/board.h b/bsp/at91sam9g45/drivers/board.h
new file mode 100644
index 0000000000..a6ec4e0ef7
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/board.h
@@ -0,0 +1,32 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <at91sam9g45.h>
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/at91sam9g45/drivers/led.c b/bsp/at91sam9g45/drivers/led.c
new file mode 100644
index 0000000000..fb8b417033
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/led.c
@@ -0,0 +1,54 @@
+/*
+ * File      : led.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      first version
+ */
+
+#include <rtthread.h>
+#include <at91sam9g45.h>
+#include "led.h"
+
+// BYHX A-Plus Board
+#define LED0    (1UL << 30)
+#define LED1    (1UL << 31)
+#define LED2    (1UL << 29)
+#define LED3    (1UL << 28)
+#define LED_ALL     (LED0 | LED1 | LED2 | LED3)
+
+void led_init(void)
+{
+	AT91C_BASE_PIOC->PIO_PER   = LED_ALL;
+	AT91C_BASE_PIOC->PIO_OER   = LED_ALL;
+	AT91C_BASE_PIOC->PIO_PPUER = LED_ALL;
+	AT91C_BASE_PIOC->PIO_SODR  = LED_ALL;
+}
+
+const static rt_uint32_t m_leds[] = { LED0, LED1, LED2, LED3 };
+
+void led_on(int num)
+{
+    if (num < 4) AT91C_BASE_PIOC->PIO_CODR = m_leds[num];
+}
+
+void led_off(int num)
+{
+    if (num < 4) AT91C_BASE_PIOC->PIO_SODR = m_leds[num];
+}
diff --git a/bsp/at91sam9g45/drivers/led.h b/bsp/at91sam9g45/drivers/led.h
new file mode 100644
index 0000000000..f2967bc92d
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/led.h
@@ -0,0 +1,32 @@
+/*
+ * File      : led.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety       first version
+ */
+
+#ifndef __LED_H__
+#define __LED_H__
+
+void led_init(void);
+void led_on(int num);
+void led_off(int num);
+
+#endif
diff --git a/bsp/at91sam9g45/drivers/macb.c b/bsp/at91sam9g45/drivers/macb.c
new file mode 100644
index 0000000000..b5cffaa1d2
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/macb.c
@@ -0,0 +1,911 @@
+/*
+ * File      : macb.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-03-18     weety      first version
+ */
+
+#include <rtthread.h>
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+#include <at91sam9g45.h>
+#include "macb.h"
+
+#define MMU_NOCACHE_ADDR(a)      	((rt_uint32_t)a | (1UL<<31))
+
+extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
+extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
+
+/* Cache macros - Packet buffers would be from pbuf pool which is cached */
+#define EMAC_VIRT_NOCACHE(addr) (addr)
+#define EMAC_CACHE_INVALIDATE(addr, size) \
+	mmu_invalidate_dcache((rt_uint32_t)addr, size)
+#define EMAC_CACHE_WRITEBACK(addr, size) \
+	mmu_clean_dcache((rt_uint32_t)addr, size)
+#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
+	mmu_clean_invalidated_dcache((rt_uint32_t)addr, size)
+
+/* EMAC has BD's in cached memory - so need cache functions */
+#define BD_CACHE_INVALIDATE(addr, size)
+#define BD_CACHE_WRITEBACK(addr, size)
+#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
+
+/* EMAC internal utility function */
+rt_inline unsigned long emac_virt_to_phys(unsigned long addr)
+{
+	return addr;
+}
+
+
+#define AT91SAM9260_SRAM0_VIRT_BASE (0x90000000)
+
+#define MACB_TX_SRAM
+
+#if defined(MACB_TX_SRAM)
+#define MACB_TX_RING_SIZE		2
+#define MACB_TX_BUFFER_SIZE		(1536 * MACB_TX_RING_SIZE)
+#define TX_RING_BYTES			(sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE)
+#else
+#define MACB_TX_RING_SIZE		16
+#define MACB_TX_BUFFER_SIZE		(1536 * MACB_TX_RING_SIZE)
+#endif
+
+#define MACB_RX_BUFFER_SIZE		(4096*4)
+#define MACB_RX_RING_SIZE		(MACB_RX_BUFFER_SIZE / 128)
+
+#define DEF_TX_RING_PENDING	(MACB_TX_RING_SIZE)
+
+#define TX_RING_GAP(macb)						\
+	(MACB_TX_RING_SIZE - (macb)->tx_pending)
+
+#define TX_BUFFS_AVAIL(macb)					\
+	(((macb)->tx_tail <= (macb)->tx_head) ?			\
+	 (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head :	\
+	 (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb))
+
+#define NEXT_TX(n)		(((n) + 1) & (MACB_TX_RING_SIZE - 1))
+
+#define NEXT_RX(n)		(((n) + 1) & (MACB_RX_RING_SIZE - 1))
+
+/* minimum number of free TX descriptors before waking up TX process */
+#define MACB_TX_WAKEUP_THRESH	(MACB_TX_RING_SIZE / 4)
+
+#define MACB_RX_INT_FLAGS	(MACB_BIT(RCOMP) | MACB_BIT(RXUBR)	\
+				 | MACB_BIT(ISR_ROVR))
+
+#define MACB_TX_TIMEOUT		1000
+#define MACB_AUTONEG_TIMEOUT	5000000	
+#define MACB_LINK_TIMEOUT		500000  
+
+#define CONFIG_RMII
+
+struct macb_dma_desc {
+	rt_uint32_t	addr;
+	rt_uint32_t	ctrl;
+};
+
+#define RXADDR_USED		0x00000001
+#define RXADDR_WRAP		0x00000002
+
+#define RXBUF_FRMLEN_MASK	0x00000fff
+#define RXBUF_FRAME_START	0x00004000
+#define RXBUF_FRAME_END		0x00008000
+#define RXBUF_TYPEID_MATCH	0x00400000
+#define RXBUF_ADDR4_MATCH	0x00800000
+#define RXBUF_ADDR3_MATCH	0x01000000
+#define RXBUF_ADDR2_MATCH	0x02000000
+#define RXBUF_ADDR1_MATCH	0x04000000
+#define RXBUF_BROADCAST		0x80000000
+
+#define TXBUF_FRMLEN_MASK	0x000007ff
+#define TXBUF_FRAME_END		0x00008000
+#define TXBUF_NOCRC		0x00010000
+#define TXBUF_EXHAUSTED		0x08000000
+#define TXBUF_UNDERRUN		0x10000000
+#define TXBUF_MAXRETRY		0x20000000
+#define TXBUF_WRAP		0x40000000
+#define TXBUF_USED		0x80000000
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF		0x00
+#define DUPLEX_FULL		0x01
+
+#define MAX_ADDR_LEN 6
+struct rt_macb_eth
+{
+	/* inherit from ethernet device */
+	struct eth_device parent;
+
+	unsigned int		regs;
+
+	unsigned int		rx_tail;
+	unsigned int		tx_head;
+	unsigned int		tx_tail;
+	unsigned int		rx_pending;
+	unsigned int		tx_pending;
+
+	void			*rx_buffer;
+	void			*tx_buffer;
+	struct macb_dma_desc	*rx_ring;
+	struct macb_dma_desc	*tx_ring;
+
+	unsigned long		rx_buffer_dma;
+	unsigned long		tx_buffer_dma;
+	unsigned long		rx_ring_dma;
+	unsigned long		tx_ring_dma;
+
+	unsigned int		tx_stop;
+
+	/* interface address info. */
+	rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+	unsigned short		phy_addr;
+
+	struct rt_semaphore mdio_bus_lock;
+	struct rt_semaphore tx_lock;
+	struct rt_semaphore rx_lock;
+	struct rt_semaphore tx_ack;
+	rt_uint32_t  speed;
+	rt_uint32_t  duplex;
+	rt_uint32_t link;
+	struct rt_timer  timer;
+};
+static struct rt_macb_eth macb_device;
+
+static void macb_tx(struct rt_macb_eth *macb);
+
+static void udelay(rt_uint32_t us)
+{
+    rt_uint32_t len;
+    for (;us > 0; us --)
+        for (len = 0; len < 10; len++ );
+}
+
+static void rt_macb_isr(int irq, void *param)
+{
+	struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
+	rt_device_t dev = &(macb->parent.parent);
+	rt_uint32_t status, rsr, tsr;
+
+	status = macb_readl(macb, ISR);
+
+	while (status) {
+
+		if (status & MACB_RX_INT_FLAGS)
+		{
+			rsr = macb_readl(macb, RSR);
+			macb_writel(macb, RSR, rsr);
+			/* a frame has been received */
+			eth_device_ready(&(macb_device.parent));
+		
+		}
+
+		if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
+			    MACB_BIT(ISR_RLE)))
+		{
+			macb_tx(macb);
+		}
+
+		/*
+		 * Link change detection isn't possible with RMII, so we'll
+		 * add that if/when we get our hands on a full-blown MII PHY.
+		 */
+
+		if (status & MACB_BIT(HRESP))
+		{
+			/*
+			 * TODO: Reset the hardware, and maybe move the printk
+			 * to a lower-priority context as well (work queue?)
+			 */
+			rt_kprintf("%s: DMA bus error: HRESP not OK\n",
+			       dev->parent.name);
+		}
+
+		status = macb_readl(macb, ISR);
+	}
+
+
+}
+
+static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value)
+{
+	unsigned long netctl;
+	unsigned long netstat;
+	unsigned long frame;
+
+	rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
+	netctl = macb_readl(macb, NCR);
+	netctl |= MACB_BIT(MPE);
+	macb_writel(macb, NCR, netctl);
+
+	frame = (MACB_BF(SOF, 1)
+		 | MACB_BF(RW, 1)
+		 | MACB_BF(PHYA, macb->phy_addr)
+		 | MACB_BF(REGA, reg)
+		 | MACB_BF(CODE, 2)
+		 | MACB_BF(DATA, value));
+	macb_writel(macb, MAN, frame);
+
+	do {
+		netstat = macb_readl(macb, NSR);
+	} while (!(netstat & MACB_BIT(IDLE)));
+
+	netctl = macb_readl(macb, NCR);
+	netctl &= ~MACB_BIT(MPE);
+	macb_writel(macb, NCR, netctl);
+	rt_sem_release(&macb->mdio_bus_lock);
+}
+
+static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg)
+{
+	unsigned long netctl;
+	unsigned long netstat;
+	unsigned long frame;
+
+	rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
+	netctl = macb_readl(macb, NCR);
+	netctl |= MACB_BIT(MPE);
+	macb_writel(macb, NCR, netctl);
+
+	frame = (MACB_BF(SOF, 1)
+		 | MACB_BF(RW, 2)
+		 | MACB_BF(PHYA, macb->phy_addr)
+		 | MACB_BF(REGA, reg)
+		 | MACB_BF(CODE, 2));
+	macb_writel(macb, MAN, frame);
+
+	do {
+		netstat = macb_readl(macb, NSR);
+	} while (!(netstat & MACB_BIT(IDLE)));
+
+	frame = macb_readl(macb, MAN);
+
+	netctl = macb_readl(macb, NCR);
+	netctl &= ~MACB_BIT(MPE);
+	macb_writel(macb, NCR, netctl);
+	rt_sem_release(&macb->mdio_bus_lock);
+
+	return MACB_BFEXT(DATA, frame);
+}
+
+static void macb_phy_reset(rt_device_t dev)
+{
+	int i;
+	rt_uint16_t status, adv;
+	struct rt_macb_eth *macb = dev->user_data;;
+
+	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
+	macb_mdio_write(macb, MII_ADVERTISE, adv);
+	rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name);
+	macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
+					 | BMCR_ANRESTART));
+
+	for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++)
+	{
+		status = macb_mdio_read(macb, MII_BMSR);
+		if (status & BMSR_ANEGCOMPLETE)
+			break;
+		udelay(100);
+	}
+
+	if (status & BMSR_ANEGCOMPLETE)
+		rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name);
+	else
+		rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n",
+		       dev->parent.name, status);
+}
+
+
+static int macb_phy_init(rt_device_t dev)
+{
+	struct rt_macb_eth *macb = dev->user_data;
+	rt_uint32_t ncfgr;
+	rt_uint16_t phy_id, status, adv, lpa;
+	int media, speed, duplex;
+	int i;
+
+	/* Check if the PHY is up to snuff... */
+	phy_id = macb_mdio_read(macb, MII_PHYSID1);
+	if (phy_id == 0xffff)
+	{
+		rt_kprintf("%s: No PHY present\n", dev->parent.name);
+		return 0;
+	}
+
+	status = macb_mdio_read(macb, MII_BMSR);
+	if (!(status & BMSR_LSTATUS))
+	{
+		/* Try to re-negotiate if we don't have link already. */
+		macb_phy_reset(dev);
+
+		for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++)
+		{
+			status = macb_mdio_read(macb, MII_BMSR);
+			if (status & BMSR_LSTATUS)
+				break;
+			udelay(100);
+		}
+	}
+
+	if (!(status & BMSR_LSTATUS))
+	{
+		rt_kprintf("%s: link down (status: 0x%04x)\n",
+		       dev->parent.name, status);
+		return 0;
+	}
+	else
+	{
+		adv = macb_mdio_read(macb, MII_ADVERTISE);
+		lpa = macb_mdio_read(macb, MII_LPA);
+		media = mii_nway_result(lpa & adv);
+		speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
+			 ? 1 : 0);
+		duplex = (media & ADVERTISE_FULL) ? 1 : 0;
+		rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
+		       dev->parent.name,
+		       speed ? "100" : "10",
+		       duplex ? "full" : "half",
+		       lpa);
+
+		ncfgr = macb_readl(macb, NCFGR);
+		ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
+		if (speed)
+			ncfgr |= MACB_BIT(SPD);
+		if (duplex)
+			ncfgr |= MACB_BIT(FD);
+		macb_writel(macb, NCFGR, ncfgr);
+		return 1;
+	}
+}
+
+void macb_update_link(void *param)
+{
+	struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
+	rt_device_t dev = &macb->parent.parent;
+	int status, status_change = 0;
+	rt_uint32_t link;
+	rt_uint32_t media;
+	rt_uint16_t adv, lpa;
+
+	/* Do a fake read */
+	status = macb_mdio_read(macb, MII_BMSR);
+	if (status < 0)
+		return;
+
+	/* Read link and autonegotiation status */
+	status = macb_mdio_read(macb, MII_BMSR);
+	if (status < 0)
+		return;
+	
+	if ((status & BMSR_LSTATUS) == 0)
+		link = 0;
+	else
+		link = 1;
+
+	if (link != macb->link)
+	{
+		macb->link = link;
+		status_change = 1;
+	}
+
+	if (status_change)
+	{
+		if (macb->link)
+		{
+			adv = macb_mdio_read(macb, MII_ADVERTISE);
+			lpa = macb_mdio_read(macb, MII_LPA);
+			media = mii_nway_result(lpa & adv);
+			macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
+				 ? 100 : 10);
+			macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0;
+			rt_kprintf("%s: link up (%dMbps/%s-duplex)\n",
+					dev->parent.name, macb->speed,
+					DUPLEX_FULL == macb->duplex ? "Full":"Half");
+			eth_device_linkchange(&macb->parent, RT_TRUE);
+		}
+		else
+		{
+			rt_kprintf("%s: link down\n", dev->parent.name);
+			eth_device_linkchange(&macb->parent, RT_FALSE);
+		}
+
+	}
+
+}
+
+/* RT-Thread Device Interface */
+/* initialize the interface */
+
+static rt_err_t rt_macb_init(rt_device_t dev)
+{
+	struct rt_macb_eth *macb = dev->user_data;
+	unsigned long paddr;
+	rt_uint32_t hwaddr_bottom;
+	rt_uint16_t hwaddr_top;
+	int i;
+
+	/*
+	 * macb_halt should have been called at some point before now,
+	 * so we'll assume the controller is idle.
+	 */
+
+	/* initialize DMA descriptors */
+	paddr = macb->rx_buffer_dma;
+	for (i = 0; i < MACB_RX_RING_SIZE; i++)
+	{
+		if (i == (MACB_RX_RING_SIZE - 1))
+			paddr |= RXADDR_WRAP;
+		macb->rx_ring[i].addr = paddr;
+		macb->rx_ring[i].ctrl = 0;
+		paddr += 128;
+	}
+	paddr = macb->tx_buffer_dma;
+	for (i = 0; i < MACB_TX_RING_SIZE; i++)
+	{
+		macb->tx_ring[i].addr = paddr;
+		if (i == (MACB_TX_RING_SIZE - 1))
+			macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
+		else
+			macb->tx_ring[i].ctrl = TXBUF_USED;
+		paddr += 1536;
+	}
+	macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
+
+	BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
+	BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
+	macb_writel(macb, RBQP, macb->rx_ring_dma);
+	macb_writel(macb, TBQP, macb->tx_ring_dma);
+	
+	/* set hardware address */
+	hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr));
+	macb_writel(macb, SA1B, hwaddr_bottom);
+	hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4)));
+	macb_writel(macb, SA1T, hwaddr_top);
+
+	
+	/* choose RMII or MII mode. This depends on the board */
+#ifdef CONFIG_RMII
+	macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
+#else
+	macb_writel(macb, USRIO, MACB_BIT(CLKEN));
+#endif /* CONFIG_RMII */
+
+	if (!macb_phy_init(dev))
+		return -RT_ERROR;
+
+	/* Enable TX and RX */
+	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE));
+	
+	/* Enable interrupts */
+	macb_writel(macb, IER, (MACB_BIT(RCOMP)
+			      | MACB_BIT(RXUBR)
+			      | MACB_BIT(ISR_TUND)
+			      | MACB_BIT(ISR_RLE)
+			      | MACB_BIT(TXERR)
+			      | MACB_BIT(TCOMP)
+			      | MACB_BIT(ISR_ROVR)
+			      | MACB_BIT(HRESP)));
+	
+	/* instal interrupt */
+	rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, 
+							(void *)macb, "emac");
+	rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC);
+
+	rt_timer_init(&macb->timer, "link_timer", 
+		macb_update_link, 
+		(void *)macb, 
+		RT_TICK_PER_SECOND, 
+		RT_TIMER_FLAG_PERIODIC);
+
+	rt_timer_start(&macb->timer);
+	
+	return RT_EOK;
+}
+
+static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+static rt_err_t rt_macb_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args)
+{
+	switch(cmd)
+	{
+	case NIOCTL_GADDR:
+		/* get mac address */
+		if(args) rt_memcpy(args, macb_device.dev_addr, 6);
+		else return -RT_ERROR;
+		break;
+
+	default :
+		break;
+	}
+
+	return RT_EOK;
+}
+
+static void macb_tx(struct rt_macb_eth *macb)
+{
+	unsigned int tail;
+	unsigned int head;
+	rt_uint32_t status;
+
+	status = macb_readl(macb, TSR);
+	macb_writel(macb, TSR, status);
+
+	/*rt_kprintf("macb_tx status = %02lx\n",
+		(unsigned long)status);*/
+
+	if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE)))
+	{
+		int i;
+		rt_kprintf("%s: TX %s, resetting buffers\n",
+			macb->parent.parent.parent.name, status & MACB_BIT(UND) ?
+			"underrun" : "retry limit exceeded");
+
+		/* Transfer ongoing, disable transmitter, to avoid confusion */
+		if (status & MACB_BIT(TGO))
+			macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
+
+		head = macb->tx_head;
+
+		/*Mark all the buffer as used to avoid sending a lost buffer*/
+		for (i = 0; i < MACB_TX_RING_SIZE; i++)
+			macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
+
+		/* free transmit buffer in upper layer*/
+
+		macb->tx_head = macb->tx_tail = 0;
+
+		/* Enable the transmitter again */
+		if (status & MACB_BIT(TGO))
+			macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE));
+	}
+
+	if (!(status & MACB_BIT(COMP)))
+		/*
+		 * This may happen when a buffer becomes complete
+		 * between reading the ISR and scanning the
+		 * descriptors.  Nothing to worry about.
+		 */
+		return;
+
+	head = macb->tx_head;
+	for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail))
+	{
+		rt_uint32_t bufstat;
+
+		bufstat = macb->tx_ring[tail].ctrl;
+
+		if (!(bufstat & MACB_BIT(TX_USED)))
+			break;
+	}
+
+	macb->tx_tail = tail;
+	if ((macb->tx_stop == 1) &&
+	    TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH)
+		rt_sem_release(&macb->tx_ack);
+}
+
+
+/* ethernet device interface */
+/* transmit packet. */
+rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p)
+{
+	unsigned long ctrl;
+	struct pbuf* q;
+	rt_uint8_t* bufptr;
+	rt_uint32_t mapping;
+	struct rt_macb_eth *macb = dev->user_data;
+	unsigned int tx_head = macb->tx_head;
+
+	rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER);
+	if (TX_BUFFS_AVAIL(macb) < 1)
+	{
+		rt_sem_release(&macb->tx_lock);
+		rt_kprintf("Tx Ring full!\n");
+		rt_kprintf("tx_head = %u, tx_tail = %u\n",
+			macb->tx_head, macb->tx_tail);
+		return -RT_ERROR;
+	}
+
+	macb->tx_stop = 0;
+
+	ctrl = p->tot_len & TXBUF_FRMLEN_MASK;
+	ctrl |= TXBUF_FRAME_END;
+	if (tx_head == (MACB_TX_RING_SIZE - 1))
+	{
+		ctrl |= TXBUF_WRAP;
+	}
+#if defined(MACB_TX_SRAM)
+	bufptr = macb->tx_buffer + tx_head * 1536;
+#else
+	mapping = (unsigned long)macb->tx_buffer + tx_head * 1536;
+	bufptr = (rt_uint8_t *)mapping;
+#endif
+
+	for (q = p; q != NULL; q = q->next)
+	{
+		memcpy(bufptr, q->payload, q->len);
+		bufptr += q->len;
+	}
+#if !defined(MACB_TX_SRAM)
+	EMAC_CACHE_WRITEBACK(mapping, p->tot_len);
+#endif
+	macb->tx_ring[tx_head].ctrl = ctrl;
+	BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc));
+	tx_head = NEXT_TX(tx_head);
+	macb->tx_head = tx_head;
+	macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
+	macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
+
+	if (TX_BUFFS_AVAIL(macb) < 1)
+	{
+		macb->tx_stop = 1;
+		rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER);
+	}
+	rt_sem_release(&macb->tx_lock);
+
+	return RT_EOK;
+}
+
+static void reclaim_rx_buffers(struct rt_macb_eth *macb,
+			       unsigned int new_tail)
+{
+	unsigned int i;
+
+	i = macb->rx_tail;
+	while (i > new_tail)
+	{
+		macb->rx_ring[i].addr &= ~RXADDR_USED;
+		i++;
+		if (i > MACB_RX_RING_SIZE)
+			i = 0;
+	}
+
+	while (i < new_tail)
+	{
+		macb->rx_ring[i].addr &= ~RXADDR_USED;
+		i++;
+	}
+
+	macb->rx_tail = new_tail;
+}
+
+/* reception packet. */
+struct pbuf *rt_macb_rx(rt_device_t dev)
+{
+	struct rt_macb_eth *macb = dev->user_data;
+	struct pbuf* p = RT_NULL;
+	rt_uint32_t len;
+	unsigned int rx_tail = macb->rx_tail;
+	void *buffer;
+	int wrapped = 0;
+	rt_uint32_t status;
+
+	rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER);
+	for (;;)
+	{
+		if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
+			break;
+
+		status = macb->rx_ring[rx_tail].ctrl;
+		if (status & RXBUF_FRAME_START)
+		{
+			if (rx_tail != macb->rx_tail)
+				reclaim_rx_buffers(macb, rx_tail);
+			wrapped = 0;
+		}
+
+		if (status & RXBUF_FRAME_END)
+		{
+			buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail);
+			len = status & RXBUF_FRMLEN_MASK;
+			p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
+			if (!p)
+			{
+				rt_kprintf("alloc pbuf failed\n");
+				break;
+			}
+			if (wrapped)
+			{
+				unsigned int headlen, taillen;
+
+				headlen = 128 * (MACB_RX_RING_SIZE
+						 - macb->rx_tail);
+				taillen = len - headlen;
+				EMAC_CACHE_INVALIDATE(buffer, headlen);
+				EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen);
+				memcpy((void *)p->payload, buffer, headlen);
+				memcpy((void *)((unsigned int)p->payload + headlen),
+				       macb->rx_buffer, taillen);
+			}
+			else
+			{
+				EMAC_CACHE_INVALIDATE(buffer, len);
+				memcpy((void *)p->payload, buffer, p->len);
+			}
+			
+			if (++rx_tail >= MACB_RX_RING_SIZE)
+				rx_tail = 0;
+			reclaim_rx_buffers(macb, rx_tail);
+			break;
+		}
+		else
+		{
+			if (++rx_tail >= MACB_RX_RING_SIZE)
+			{
+				wrapped = 1;
+				rx_tail = 0;
+			}
+		}
+	}
+
+	rt_sem_release(&macb->rx_lock);
+
+	return p;
+}
+
+void macb_gpio_init()
+{
+	/* Pins used for MII and RMII */
+	AT91C_BASE_PIOA->PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20);
+	AT91C_BASE_PIOA->PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20);
+
+#ifndef GONFIG_RMII
+	AT91C_BASE_PIOA->PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29);
+	AT91C_BASE_PIOA->PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29);
+#endif
+}
+
+rt_err_t macb_initialize()
+{
+	struct rt_macb_eth *macb = &macb_device;
+	unsigned long macb_hz;
+	rt_uint32_t ncfgr;
+	
+#if defined(MACB_TX_SRAM)
+	macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE;
+	macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE;
+	macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES;
+	macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES;
+#else
+	macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
+	if (macb->tx_ring == RT_NULL)
+		goto err1;
+	EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
+	macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring);
+	macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring);
+	macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE);
+	if (macb->tx_buffer == RT_NULL)
+		goto err2;
+	macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer);
+#endif
+
+	macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
+	if (macb->rx_ring == RT_NULL)
+		goto err3;
+	EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
+	macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring);
+	macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring);
+	macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE);
+	if (macb->rx_buffer == RT_NULL)
+		goto err4;
+	macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer);
+
+	macb->tx_pending = DEF_TX_RING_PENDING;
+
+	macb->regs = AT91SAM9260_BASE_EMAC;
+	macb->phy_addr = 0x00;
+	
+	/*
+	 * Do some basic initialization so that we at least can talk
+	 * to the PHY
+	 */
+	macb_hz = clk_get_rate(clk_get("mck"));
+	if (macb_hz < 20000000)
+		ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
+	else if (macb_hz < 40000000)
+		ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
+	else if (macb_hz < 80000000)
+		ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
+	else
+		ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
+
+	macb_writel(macb, NCFGR, ncfgr);
+
+	macb->link = 0;
+
+	return RT_EOK;
+
+err4:
+	rt_free(macb->rx_ring);
+	macb->rx_ring = RT_NULL;
+err3:
+#if !defined(MACB_TX_SRAM)
+	rt_free(macb->tx_buffer);
+	macb->tx_buffer = RT_NULL;
+err2:
+	rt_free(macb->tx_ring);
+	macb->tx_ring = RT_NULL;
+err1:
+#endif
+	return -RT_ENOMEM;
+}
+
+int rt_hw_macb_init(void)
+{
+	rt_err_t ret;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; //enable macb clock
+	macb_gpio_init();
+	rt_memset(&macb_device, 0, sizeof(macb_device));
+	ret = macb_initialize();
+	if (ret != RT_EOK)
+	{
+		rt_kprintf("AT91 EMAC initialized failed\n");
+		return -1;
+	}
+	rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
+	rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO);
+	rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO);
+
+	macb_device.dev_addr[0] = 0x00;
+	macb_device.dev_addr[1] = 0x60;
+	macb_device.dev_addr[2] = 0x6E;
+	macb_device.dev_addr[3] = 0x11;
+	macb_device.dev_addr[4] = 0x22;
+	macb_device.dev_addr[5] = 0x33;
+	
+	macb_device.parent.parent.init       = rt_macb_init;
+	macb_device.parent.parent.open       = rt_macb_open;
+	macb_device.parent.parent.close      = rt_macb_close;
+	macb_device.parent.parent.read       = rt_macb_read;
+	macb_device.parent.parent.write      = rt_macb_write;
+	macb_device.parent.parent.control    = rt_macb_control;
+	macb_device.parent.parent.user_data  = &macb_device;
+
+	macb_device.parent.eth_rx     = rt_macb_rx;
+	macb_device.parent.eth_tx     = rt_macb_tx;
+
+	rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO);
+
+	eth_device_init(&(macb_device.parent), "e0");
+
+	return 0;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_macb_init);
+
diff --git a/bsp/at91sam9g45/drivers/macb.h b/bsp/at91sam9g45/drivers/macb.h
new file mode 100644
index 0000000000..9df2883534
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/macb.h
@@ -0,0 +1,346 @@
+/*
+ * File      : macb.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-03-18     weety      first version
+ */
+#ifndef _MACB_H
+#define _MACB_H
+#include <mii.h>
+
+/* MACB register offsets */
+#define MACB_NCR				0x0000
+#define MACB_NCFGR				0x0004
+#define MACB_NSR				0x0008
+#define MACB_TSR				0x0014
+#define MACB_RBQP				0x0018
+#define MACB_TBQP				0x001c
+#define MACB_RSR				0x0020
+#define MACB_ISR				0x0024
+#define MACB_IER				0x0028
+#define MACB_IDR				0x002c
+#define MACB_IMR				0x0030
+#define MACB_MAN				0x0034
+#define MACB_PTR				0x0038
+#define MACB_PFR				0x003c
+#define MACB_FTO				0x0040
+#define MACB_SCF				0x0044
+#define MACB_MCF				0x0048
+#define MACB_FRO				0x004c
+#define MACB_FCSE				0x0050
+#define MACB_ALE				0x0054
+#define MACB_DTF				0x0058
+#define MACB_LCOL				0x005c
+#define MACB_EXCOL				0x0060
+#define MACB_TUND				0x0064
+#define MACB_CSE				0x0068
+#define MACB_RRE				0x006c
+#define MACB_ROVR				0x0070
+#define MACB_RSE				0x0074
+#define MACB_ELE				0x0078
+#define MACB_RJA				0x007c
+#define MACB_USF				0x0080
+#define MACB_STE				0x0084
+#define MACB_RLE				0x0088
+#define MACB_TPF				0x008c
+#define MACB_HRB				0x0090
+#define MACB_HRT				0x0094
+#define MACB_SA1B				0x0098
+#define MACB_SA1T				0x009c
+#define MACB_SA2B				0x00a0
+#define MACB_SA2T				0x00a4
+#define MACB_SA3B				0x00a8
+#define MACB_SA3T				0x00ac
+#define MACB_SA4B				0x00b0
+#define MACB_SA4T				0x00b4
+#define MACB_TID				0x00b8
+#define MACB_TPQ				0x00bc
+#define MACB_USRIO				0x00c0
+#define MACB_WOL				0x00c4
+
+/* Bitfields in NCR */
+#define MACB_LB_OFFSET				0
+#define MACB_LB_SIZE				1
+#define MACB_LLB_OFFSET				1
+#define MACB_LLB_SIZE				1
+#define MACB_RE_OFFSET				2
+#define MACB_RE_SIZE				1
+#define MACB_TE_OFFSET				3
+#define MACB_TE_SIZE				1
+#define MACB_MPE_OFFSET				4
+#define MACB_MPE_SIZE				1
+#define MACB_CLRSTAT_OFFSET			5
+#define MACB_CLRSTAT_SIZE			1
+#define MACB_INCSTAT_OFFSET			6
+#define MACB_INCSTAT_SIZE			1
+#define MACB_WESTAT_OFFSET			7
+#define MACB_WESTAT_SIZE			1
+#define MACB_BP_OFFSET				8
+#define MACB_BP_SIZE				1
+#define MACB_TSTART_OFFSET			9
+#define MACB_TSTART_SIZE			1
+#define MACB_THALT_OFFSET			10
+#define MACB_THALT_SIZE				1
+#define MACB_NCR_TPF_OFFSET			11
+#define MACB_NCR_TPF_SIZE			1
+#define MACB_TZQ_OFFSET				12
+#define MACB_TZQ_SIZE				1
+
+/* Bitfields in NCFGR */
+#define MACB_SPD_OFFSET				0
+#define MACB_SPD_SIZE				1
+#define MACB_FD_OFFSET				1
+#define MACB_FD_SIZE				1
+#define MACB_BIT_RATE_OFFSET			2
+#define MACB_BIT_RATE_SIZE			1
+#define MACB_JFRAME_OFFSET			3
+#define MACB_JFRAME_SIZE			1
+#define MACB_CAF_OFFSET				4
+#define MACB_CAF_SIZE				1
+#define MACB_NBC_OFFSET				5
+#define MACB_NBC_SIZE				1
+#define MACB_NCFGR_MTI_OFFSET			6
+#define MACB_NCFGR_MTI_SIZE			1
+#define MACB_UNI_OFFSET				7
+#define MACB_UNI_SIZE				1
+#define MACB_BIG_OFFSET				8
+#define MACB_BIG_SIZE				1
+#define MACB_EAE_OFFSET				9
+#define MACB_EAE_SIZE				1
+#define MACB_CLK_OFFSET				10
+#define MACB_CLK_SIZE				2
+#define MACB_RTY_OFFSET				12
+#define MACB_RTY_SIZE				1
+#define MACB_PAE_OFFSET				13
+#define MACB_PAE_SIZE				1
+#define MACB_RBOF_OFFSET			14
+#define MACB_RBOF_SIZE				2
+#define MACB_RLCE_OFFSET			16
+#define MACB_RLCE_SIZE				1
+#define MACB_DRFCS_OFFSET			17
+#define MACB_DRFCS_SIZE				1
+#define MACB_EFRHD_OFFSET			18
+#define MACB_EFRHD_SIZE				1
+#define MACB_IRXFCS_OFFSET			19
+#define MACB_IRXFCS_SIZE			1
+
+/* Bitfields in NSR */
+#define MACB_NSR_LINK_OFFSET			0
+#define MACB_NSR_LINK_SIZE			1
+#define MACB_MDIO_OFFSET			1
+#define MACB_MDIO_SIZE				1
+#define MACB_IDLE_OFFSET			2
+#define MACB_IDLE_SIZE				1
+
+/* Bitfields in TSR */
+#define MACB_UBR_OFFSET				0
+#define MACB_UBR_SIZE				1
+#define MACB_COL_OFFSET				1
+#define MACB_COL_SIZE				1
+#define MACB_TSR_RLE_OFFSET			2
+#define MACB_TSR_RLE_SIZE			1
+#define MACB_TGO_OFFSET				3
+#define MACB_TGO_SIZE				1
+#define MACB_BEX_OFFSET				4
+#define MACB_BEX_SIZE				1
+#define MACB_COMP_OFFSET			5
+#define MACB_COMP_SIZE				1
+#define MACB_UND_OFFSET				6
+#define MACB_UND_SIZE				1
+
+/* Bitfields in RSR */
+#define MACB_BNA_OFFSET				0
+#define MACB_BNA_SIZE				1
+#define MACB_REC_OFFSET				1
+#define MACB_REC_SIZE				1
+#define MACB_OVR_OFFSET				2
+#define MACB_OVR_SIZE				1
+
+/* Bitfields in ISR/IER/IDR/IMR */
+#define MACB_MFD_OFFSET				0
+#define MACB_MFD_SIZE				1
+#define MACB_RCOMP_OFFSET			1
+#define MACB_RCOMP_SIZE				1
+#define MACB_RXUBR_OFFSET			2
+#define MACB_RXUBR_SIZE				1
+#define MACB_TXUBR_OFFSET			3
+#define MACB_TXUBR_SIZE				1
+#define MACB_ISR_TUND_OFFSET			4
+#define MACB_ISR_TUND_SIZE			1
+#define MACB_ISR_RLE_OFFSET			5
+#define MACB_ISR_RLE_SIZE			1
+#define MACB_TXERR_OFFSET			6
+#define MACB_TXERR_SIZE				1
+#define MACB_TCOMP_OFFSET			7
+#define MACB_TCOMP_SIZE				1
+#define MACB_ISR_LINK_OFFSET			9
+#define MACB_ISR_LINK_SIZE			1
+#define MACB_ISR_ROVR_OFFSET			10
+#define MACB_ISR_ROVR_SIZE			1
+#define MACB_HRESP_OFFSET			11
+#define MACB_HRESP_SIZE				1
+#define MACB_PFR_OFFSET				12
+#define MACB_PFR_SIZE				1
+#define MACB_PTZ_OFFSET				13
+#define MACB_PTZ_SIZE				1
+
+/* Bitfields in MAN */
+#define MACB_DATA_OFFSET			0
+#define MACB_DATA_SIZE				16
+#define MACB_CODE_OFFSET			16
+#define MACB_CODE_SIZE				2
+#define MACB_REGA_OFFSET			18
+#define MACB_REGA_SIZE				5
+#define MACB_PHYA_OFFSET			23
+#define MACB_PHYA_SIZE				5
+#define MACB_RW_OFFSET				28
+#define MACB_RW_SIZE				2
+#define MACB_SOF_OFFSET				30
+#define MACB_SOF_SIZE				2
+
+/* Bitfields in USRIO (AVR32) */
+#define MACB_MII_OFFSET				0
+#define MACB_MII_SIZE				1
+#define MACB_EAM_OFFSET				1
+#define MACB_EAM_SIZE				1
+#define MACB_TX_PAUSE_OFFSET			2
+#define MACB_TX_PAUSE_SIZE			1
+#define MACB_TX_PAUSE_ZERO_OFFSET		3
+#define MACB_TX_PAUSE_ZERO_SIZE			1
+
+/* Bitfields in USRIO (AT91) */
+#define MACB_RMII_OFFSET			0
+#define MACB_RMII_SIZE				1
+#define MACB_CLKEN_OFFSET			1
+#define MACB_CLKEN_SIZE				1
+
+/* Bitfields in WOL */
+#define MACB_IP_OFFSET				0
+#define MACB_IP_SIZE				16
+#define MACB_MAG_OFFSET				16
+#define MACB_MAG_SIZE				1
+#define MACB_ARP_OFFSET				17
+#define MACB_ARP_SIZE				1
+#define MACB_SA1_OFFSET				18
+#define MACB_SA1_SIZE				1
+#define MACB_WOL_MTI_OFFSET			19
+#define MACB_WOL_MTI_SIZE			1
+
+/* Constants for CLK */
+#define MACB_CLK_DIV8				0
+#define MACB_CLK_DIV16				1
+#define MACB_CLK_DIV32				2
+#define MACB_CLK_DIV64				3
+
+/* Constants for MAN register */
+#define MACB_MAN_SOF				1
+#define MACB_MAN_WRITE				1
+#define MACB_MAN_READ				2
+#define MACB_MAN_CODE				2
+
+/* Bit manipulation macros */
+#define MACB_BIT(name)					\
+	(1 << MACB_##name##_OFFSET)
+#define MACB_BF(name,value)				\
+	(((value) & ((1 << MACB_##name##_SIZE) - 1))	\
+	 << MACB_##name##_OFFSET)
+#define MACB_BFEXT(name,value)\
+	(((value) >> MACB_##name##_OFFSET)		\
+	 & ((1 << MACB_##name##_SIZE) - 1))
+#define MACB_BFINS(name,value,old)			\
+	(((old) & ~(((1 << MACB_##name##_SIZE) - 1)	\
+		    << MACB_##name##_OFFSET))		\
+	 | MACB_BF(name,value))
+
+/* Register access macros */
+#define macb_readl(port,reg)				\
+	readl((port)->regs + MACB_##reg)
+#define macb_writel(port,reg,value)			\
+	writel((value), (port)->regs + MACB_##reg)
+
+struct dma_desc {
+	rt_uint32_t	addr;
+	rt_uint32_t	ctrl;
+};
+
+/* DMA descriptor bitfields */
+#define MACB_RX_USED_OFFSET			0
+#define MACB_RX_USED_SIZE			1
+#define MACB_RX_WRAP_OFFSET			1
+#define MACB_RX_WRAP_SIZE			1
+#define MACB_RX_WADDR_OFFSET			2
+#define MACB_RX_WADDR_SIZE			30
+
+#define MACB_RX_FRMLEN_OFFSET			0
+#define MACB_RX_FRMLEN_SIZE			12
+#define MACB_RX_OFFSET_OFFSET			12
+#define MACB_RX_OFFSET_SIZE			2
+#define MACB_RX_SOF_OFFSET			14
+#define MACB_RX_SOF_SIZE			1
+#define MACB_RX_EOF_OFFSET			15
+#define MACB_RX_EOF_SIZE			1
+#define MACB_RX_CFI_OFFSET			16
+#define MACB_RX_CFI_SIZE			1
+#define MACB_RX_VLAN_PRI_OFFSET			17
+#define MACB_RX_VLAN_PRI_SIZE			3
+#define MACB_RX_PRI_TAG_OFFSET			20
+#define MACB_RX_PRI_TAG_SIZE			1
+#define MACB_RX_VLAN_TAG_OFFSET			21
+#define MACB_RX_VLAN_TAG_SIZE			1
+#define MACB_RX_TYPEID_MATCH_OFFSET		22
+#define MACB_RX_TYPEID_MATCH_SIZE		1
+#define MACB_RX_SA4_MATCH_OFFSET		23
+#define MACB_RX_SA4_MATCH_SIZE			1
+#define MACB_RX_SA3_MATCH_OFFSET		24
+#define MACB_RX_SA3_MATCH_SIZE			1
+#define MACB_RX_SA2_MATCH_OFFSET		25
+#define MACB_RX_SA2_MATCH_SIZE			1
+#define MACB_RX_SA1_MATCH_OFFSET		26
+#define MACB_RX_SA1_MATCH_SIZE			1
+#define MACB_RX_EXT_MATCH_OFFSET		28
+#define MACB_RX_EXT_MATCH_SIZE			1
+#define MACB_RX_UHASH_MATCH_OFFSET		29
+#define MACB_RX_UHASH_MATCH_SIZE		1
+#define MACB_RX_MHASH_MATCH_OFFSET		30
+#define MACB_RX_MHASH_MATCH_SIZE		1
+#define MACB_RX_BROADCAST_OFFSET		31
+#define MACB_RX_BROADCAST_SIZE			1
+
+#define MACB_TX_FRMLEN_OFFSET			0
+#define MACB_TX_FRMLEN_SIZE			11
+#define MACB_TX_LAST_OFFSET			15
+#define MACB_TX_LAST_SIZE			1
+#define MACB_TX_NOCRC_OFFSET			16
+#define MACB_TX_NOCRC_SIZE			1
+#define MACB_TX_BUF_EXHAUSTED_OFFSET		27
+#define MACB_TX_BUF_EXHAUSTED_SIZE		1
+#define MACB_TX_UNDERRUN_OFFSET			28
+#define MACB_TX_UNDERRUN_SIZE			1
+#define MACB_TX_ERROR_OFFSET			29
+#define MACB_TX_ERROR_SIZE			1
+#define MACB_TX_WRAP_OFFSET			30
+#define MACB_TX_WRAP_SIZE			1
+#define MACB_TX_USED_OFFSET			31
+#define MACB_TX_USED_SIZE			1
+
+extern int rt_hw_macb_init();
+
+#endif /* _MACB_H */
+
diff --git a/bsp/at91sam9g45/drivers/mii.h b/bsp/at91sam9g45/drivers/mii.h
new file mode 100644
index 0000000000..2f6dd18e71
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/mii.h
@@ -0,0 +1,191 @@
+/*
+ * File      : mii.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-03-18     weety      first version
+ */
+
+#ifndef __MII_H__
+#define __MII_H__
+
+/* Generic MII registers. */
+
+#define MII_BMCR            0x00        /* Basic mode control register */
+#define MII_BMSR            0x01        /* Basic mode status register  */
+#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
+#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
+#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
+#define MII_LPA             0x05        /* Link partner ability reg    */
+#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_CTRL1000        0x09        /* 1000BASE-T control          */
+#define MII_STAT1000        0x0a        /* 1000BASE-T status           */
+#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_DCOUNTER        0x12        /* Disconnect counter          */
+#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
+#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
+#define MII_SREVISION       0x16        /* Silicon revision            */
+#define MII_RESV1           0x17        /* Reserved...                 */
+#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
+#define MII_PHYADDR         0x19        /* PHY address                 */
+#define MII_RESV2           0x1a        /* Reserved...                 */
+#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
+#define MII_NCONFIG         0x1c        /* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x003f  /* Unused...                   */
+#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the DP83840           */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x00c0  /* Unused...                   */
+#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
+#define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
+#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
+#define ADVERTISE_RESV          0x1000  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_1000XFULL           0x0020  /* Can do 1000BASE-X full-duplex */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_1000XHALF           0x0040  /* Can do 1000BASE-X half-duplex */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_1000XPAUSE          0x0080  /* Can do 1000BASE-X pause     */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_1000XPAUSE_ASYM     0x0100  /* Can do 1000BASE-X pause asym*/
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_PAUSE_CAP           0x0400  /* Can pause                   */
+#define LPA_PAUSE_ASYM          0x0800  /* Can pause asymetrically     */
+#define LPA_RESV                0x1000  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
+#define EXPANSION_RESV          0xffe0  /* Unused...                   */
+
+#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
+#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
+
+/* 1000BASE-T Control register */
+#define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex */
+
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK       0x2000  /* Link partner local receiver status */
+#define LPA_1000REMRXOK         0x1000  /* Link partner remote receiver status */
+#define LPA_1000FULL            0x0800  /* Link partner 1000BASE-T full duplex */
+#define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
+
+/* Flow control flags */
+#define FLOW_CTRL_TX		0x01
+#define FLOW_CTRL_RX		0x02
+
+/**
+ * mii_nway_result
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * Given a set of MII abilities, check each bit and returns the
+ * currently supported media, in the priority order defined by
+ * IEEE 802.3u.  We use LPA_xxx constants but note this is not the
+ * value of LPA solely, as described above.
+ *
+ * The one exception to IEEE 802.3u is that 100baseT4 is placed
+ * between 100T-full and 100T-half.  If your phy does not support
+ * 100T4 this is fine.  If your phy places 100T4 elsewhere in the
+ * priority order, you will need to roll your own function.
+ */
+rt_inline unsigned int mii_nway_result (unsigned int negotiated)
+{
+        unsigned int ret;
+
+        if (negotiated & LPA_100FULL)
+                ret = LPA_100FULL;
+        else if (negotiated & LPA_100BASE4)
+                ret = LPA_100BASE4;
+        else if (negotiated & LPA_100HALF)
+                ret = LPA_100HALF;
+        else if (negotiated & LPA_10FULL)
+                ret = LPA_10FULL;
+        else
+                ret = LPA_10HALF;
+
+        return ret;
+}
+
+
+#endif /* __MII_H__ */
+
diff --git a/bsp/at91sam9g45/drivers/usart.c b/bsp/at91sam9g45/drivers/usart.c
new file mode 100644
index 0000000000..d4ba657232
--- /dev/null
+++ b/bsp/at91sam9g45/drivers/usart.c
@@ -0,0 +1,398 @@
+/*
+ * File      : usart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety       first version
+ * 2013-07-21     weety       using serial component
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <at91sam9g45.h>
+#include <rtdevice.h>
+
+
+struct at91_uart {
+	AT91S_USART *port;
+	int irq;
+};
+
+
+/**
+ * This function will handle serial port interrupt
+ */
+void rt_at91_usart_handler(int vector, void *param)
+{
+	int status;
+	struct at91_uart *uart;
+	rt_device_t dev = (rt_device_t)param;
+	uart = (struct at91_uart *)dev->user_data;
+	status = uart->port->US_CSR;
+	if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */
+	{
+		return;
+	}
+	rt_interrupt_enter();
+	rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
+	rt_interrupt_leave();
+}
+
+/**
+ * UART device in RT-Thread
+ */
+static rt_err_t at91_usart_configure(struct rt_serial_device *serial,
+                                struct serial_configure *cfg)
+{
+	int div;
+	int mode = 0;
+	struct at91_uart *uart;
+
+	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+	uart = (struct at91_uart *)serial->parent.user_data;
+
+	uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
+	       AT91C_US_RXDIS | AT91C_US_TXDIS;
+	mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
+	       AT91C_US_CHMODE_NORMAL;
+	switch (cfg->data_bits)
+	{
+	case DATA_BITS_8:
+		mode |= AT91C_US_CHRL_8_BITS;
+		break;
+	case DATA_BITS_7:
+		mode |= AT91C_US_CHRL_7_BITS;
+		break;
+	case DATA_BITS_6:
+		mode |= AT91C_US_CHRL_6_BITS;
+		break;
+	case DATA_BITS_5:
+		mode |= AT91C_US_CHRL_5_BITS;
+		break;
+	default:
+		mode |= AT91C_US_CHRL_8_BITS;
+		break;
+	}
+
+	switch (cfg->stop_bits)
+	{
+	case STOP_BITS_2:
+		mode |= AT91C_US_NBSTOP_2_BIT;
+		break;
+	case STOP_BITS_1:
+	default:
+		mode |= AT91C_US_NBSTOP_1_BIT;
+		break;
+	}
+
+	switch (cfg->parity)
+	{
+	case PARITY_ODD:
+		mode |= AT91C_US_PAR_ODD;
+		break;
+	case PARITY_EVEN:
+		mode |= AT91C_US_PAR_EVEN;
+		break;
+	case PARITY_NONE:
+	default:
+		mode |= AT91C_US_PAR_NONE;
+		break;
+	}
+
+	uart->port->US_MR = mode;
+    /* Assume OVER is cleared and fractional baudrate generator is disabled */
+	div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
+	uart->port->US_BRGR = div;
+	uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+	uart->port->US_IER = AT91C_US_RXRDY;
+
+    return RT_EOK;
+}
+
+static rt_err_t at91_usart_control(struct rt_serial_device *serial,
+                              int cmd, void *arg)
+{
+    struct at91_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct at91_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+		rt_hw_interrupt_mask(uart->irq);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+		rt_hw_interrupt_umask(uart->irq);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int at91_usart_putc(struct rt_serial_device *serial, char c)
+{
+    //rt_uint32_t level;
+	struct at91_uart *uart = serial->parent.user_data;
+
+    while (!(uart->port->US_CSR & AT91C_US_TXRDY));
+	uart->port->US_THR = c;
+
+    return 1;
+}
+
+static int at91_usart_getc(struct rt_serial_device *serial)
+{
+    int result;
+	struct at91_uart *uart = serial->parent.user_data;
+
+    if (uart->port->US_CSR & AT91C_US_RXRDY)
+	{
+		result = uart->port->US_RHR & 0xff;
+	}
+	else
+	{
+		result = -1;
+	}
+
+    return result;
+}
+
+static const struct rt_uart_ops at91_usart_ops =
+{
+    at91_usart_configure,
+    at91_usart_control,
+    at91_usart_putc,
+    at91_usart_getc,
+};
+
+#if defined(RT_USING_DBGU)
+static struct rt_serial_device serial_dbgu;
+struct at91_uart dbgu = {
+	(AT91PS_USART)AT91C_BASE_DBGU,
+	AT91C_ID_SYS
+};
+
+#endif
+
+#if defined(RT_USING_UART0)
+static struct rt_serial_device serial0;
+struct at91_uart uart0 = {
+	AT91C_BASE_US0,
+	AT91C_ID_US0
+};
+#endif
+
+#if defined(RT_USING_UART1)
+static struct rt_serial_device serial1;
+struct at91_uart uart1 = {
+	AT91C_BASE_US1,
+	AT91C_ID_US1
+};
+#endif
+
+#if defined(RT_USING_UART2)
+static struct rt_serial_device serial2;
+struct at91_uart uart2 = {
+	AT91C_BASE_US2,
+	AT91C_ID_US2
+};
+#endif
+
+#if defined(RT_USING_UART3)
+static struct rt_serial_device serial3;
+struct at91_uart uart3 = {
+	AT91C_BASE_US3,
+	AT91C_ID_US3
+};
+#endif
+
+
+void at91_usart_gpio_init(void)
+{
+#ifdef RT_USING_DBGU
+#define DRXD	12		// DBGU  rx as Peripheral A on PB12
+#define DTXD	13		// DBGU  tx as Peripheral A on PB13
+	AT91C_BASE_PIOB->PIO_IDR,   (1<<DRXD)|(1<<DTXD);   // Disables the Input Change Interrupt on the I/O line
+	AT91C_BASE_PIOB->PIO_PPUDR, (1<<DRXD)|(1<<DTXD);   // Disables the pull up resistor on the I/O line
+	AT91C_BASE_PIOB->PIO_ASR,   (1<<DRXD)|(1<<DTXD);   // Assigns the I/O line to the Peripheral A function
+	AT91C_BASE_PIOB->PIO_PDR,   (1<<DRXD)|(1<<DTXD);   // enables peripheral control of the pin
+	AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_SYS;
+#endif
+
+#ifdef RT_USING_UART0
+#define RXD0    18		// UART0 rx as Peripheral A on PB18
+#define TXD0    19		// UART0 tx as Peripheral A on PB19
+	AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US0;
+	AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD0)|(1<<TXD0);
+	AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD0);
+	AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD0);
+	AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD0)|(1<<TXD0);
+	AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD0)|(1<<TXD0);
+#endif
+
+#ifdef RT_USING_UART1
+#define TXD1     4		// UART1 tx as Peripheral A on PB4
+#define RXD1     5		// UART1 rx as Peripheral A on PB5
+	AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US1;
+	AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD1)|(1<<TXD1);
+	AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD1);
+	AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD1);
+	AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD1)|(1<<TXD1);
+	AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD1)|(1<<TXD1);
+#endif
+
+#ifdef RT_USING_UART2
+#define TXD2     6		// UART2 tx as Peripheral A on PB6
+#define RXD2     7		// UART2 rx as Peripheral A on PB7
+	AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US2;
+	AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD2)|(1<<TXD2);
+	AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD2);
+	AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD2);
+	AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD2)|(1<<TXD2);
+	AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD2)|(1<<TXD2);
+#endif
+
+#ifdef RT_USING_UART3
+#define TXD3     8		// UART3 tx as Peripheral A on PB8
+#define RXD3     9		// UART3 rx as Peripheral A on PB9
+	AT91C_BASE_PMC->PMC_PCER,    1<<AT91C_ID_US3;
+	AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD3)|(1<<TXD3);
+	AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD3);
+	AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD3);
+	AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD3)|(1<<TXD3);
+	AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD3)|(1<<TXD3);
+#endif
+}
+
+/**
+ * This function will handle init uart
+ */
+int rt_hw_uart_init(void)
+{
+	at91_usart_gpio_init();
+
+#if defined(RT_USING_DBGU)
+	serial_dbgu.ops = &at91_usart_ops;
+	serial_dbgu.config.baud_rate = BAUD_RATE_115200;
+    serial_dbgu.config.bit_order = BIT_ORDER_LSB;
+    serial_dbgu.config.data_bits = DATA_BITS_8;
+    serial_dbgu.config.parity = PARITY_NONE;
+    serial_dbgu.config.stop_bits = STOP_BITS_1;
+    serial_dbgu.config.invert = NRZ_NORMAL;
+	serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
+
+    /* register vcom device */
+    rt_hw_serial_register(&serial_dbgu, "dbgu",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &dbgu);
+#endif
+
+#if defined(RT_USING_UART0)
+	serial0.ops = &at91_usart_ops;
+	serial0.config.baud_rate = BAUD_RATE_115200;
+    serial0.config.bit_order = BIT_ORDER_LSB;
+    serial0.config.data_bits = DATA_BITS_8;
+    serial0.config.parity = PARITY_NONE;
+    serial0.config.stop_bits = STOP_BITS_1;
+    serial0.config.invert = NRZ_NORMAL;
+	serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
+
+    /* register vcom device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart0);
+	rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
+							(void *)&(serial0.parent), "UART0");
+	rt_hw_interrupt_umask(uart0.irq);
+#endif
+
+#if defined(RT_USING_UART1)
+	serial1.ops = &at91_usart_ops;
+	serial1.config.baud_rate = BAUD_RATE_115200;
+    serial1.config.bit_order = BIT_ORDER_LSB;
+    serial1.config.data_bits = DATA_BITS_8;
+    serial1.config.parity = PARITY_NONE;
+    serial1.config.stop_bits = STOP_BITS_1;
+    serial1.config.invert = NRZ_NORMAL;
+	serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
+
+    /* register vcom device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &uart1);
+	rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
+							(void *)&(serial1.parent), "UART1");
+	rt_hw_interrupt_umask(uart1.irq);
+#endif
+
+#if defined(RT_USING_UART2)
+	serial2.ops = &at91_usart_ops;
+	serial2.config.baud_rate = BAUD_RATE_115200;
+    serial2.config.bit_order = BIT_ORDER_LSB;
+    serial2.config.data_bits = DATA_BITS_8;
+    serial2.config.parity = PARITY_NONE;
+    serial2.config.stop_bits = STOP_BITS_1;
+    serial2.config.invert = NRZ_NORMAL;
+	serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
+
+    /* register vcom device */
+    rt_hw_serial_register(&serial2, "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &uart2);
+	rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
+							(void *)&(serial2.parent), "UART2");
+	rt_hw_interrupt_umask(uart2.irq);
+#endif
+
+#if defined(RT_USING_UART3)
+	serial3.ops = &at91_usart_ops;
+	serial3.config.baud_rate = BAUD_RATE_115200;
+    serial3.config.bit_order = BIT_ORDER_LSB;
+    serial3.config.data_bits = DATA_BITS_8;
+    serial3.config.parity = PARITY_NONE;
+    serial3.config.stop_bits = STOP_BITS_1;
+    serial3.config.invert = NRZ_NORMAL;
+	serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
+
+    /* register vcom device */
+    rt_hw_serial_register(&serial3, "uart3",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &uart3);
+	rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
+							(void *)&(serial3.parent), "UART3");
+	rt_hw_interrupt_umask(uart3.irq);
+#endif
+
+	return 0;
+}
+
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#ifdef RT_USING_DBGU
+void rt_dbgu_isr(void)
+{
+	rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
+}
+#endif
+
+
diff --git a/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.icf b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.icf
new file mode 100644
index 0000000000..6228026138
--- /dev/null
+++ b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.icf
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------
+//      Linker scatter for running in external SDRAM on the AT91SAM9260
+//------------------------------------------------------------------------------
+
+//
+// Define a memory region that covers the entire 4 GB addressible space of the
+// processor.
+//
+define memory mem with size = 4G;
+
+//
+// Define a region for the on-chip flash.
+//
+define region FLASH = mem:[from 0x70000000 to 0x707FFFFF];
+
+//
+// Define a region for the on-chip SRAM.
+//
+define region SRAM  = mem:[from 0x70800000 to 0x73FFFFFF];
+
+//
+// Indicate that the read/write values should be initialized by copying from
+// flash.
+//
+initialize by copy { readwrite };
+
+//
+// Indicate that the noinit values should be left alone.  This includes the
+// stack, which if initialized will destroy the return address from the
+// initialization code, causing the processor to branch to zero and fault.
+//
+do not initialize { section .noinit };
+
+//
+// Place the interrupt vectors at the start of flash.
+//
+place at start of FLASH { readonly section .intvec };
+
+//
+// Place the remainder of the read-only items into flash.
+//
+place in FLASH { readonly };
+
+//
+// Place the RAM vector table at the start of SRAM.
+//
+place at start of SRAM { section VTABLE };
+
+//
+// Place all read/write items into SRAM.
+//
+place in SRAM { readwrite};
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
diff --git a/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld
new file mode 100644
index 0000000000..a0dd88e868
--- /dev/null
+++ b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld
@@ -0,0 +1,98 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(start)
+SECTIONS
+{
+    . = 0x70000000;
+
+    . = ALIGN(4);
+    .text : 
+    {
+        *(.init)
+        *(.text)
+        *(.gnu.linkonce.t*)
+        
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);   
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+    }
+
+    . = ALIGN(4);
+    .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(4);
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+    }
+
+    . = ALIGN(4);
+    .nobss : { *(.nobss) }
+    
+    . = ALIGN(4);
+    __bss_start__ = .;
+    .bss : { *(.bss)}
+    __bss_end__ = .;
+
+    /* stabs debugging sections. */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+
+    _end = .;
+}
diff --git a/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.scat b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.scat
new file mode 100644
index 0000000000..f002d68afe
--- /dev/null
+++ b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.scat
@@ -0,0 +1,40 @@
+;*------------------------------------------------------------------------------
+;*      Linker scatter for running in external SDRAM on the AT91SAM9260
+;*----------------------------------------------------------------------------*/
+
+Load_region 0x70000000 0x00800000
+{
+
+    Fixed_region 0x70000000
+    {
+        * (RESET +First)
+       .ANY (+RO +RW)
+    }
+
+    ARM_LIB_HEAP +0 EMPTY 0x1000
+    {
+    }
+
+    ARM_LIB_STACK +0 EMPTY 0x1000
+    {
+    }
+
+    ; Application ZI data (.bss)
+    ER_ZI +0
+    {
+        * (+ZI)
+    }
+  
+    ;Relocate_region 0x200000 0x1000
+    ;{
+    ;    *.o (VECTOR, +First)
+    ;}
+    
+    ;ARM_LIB_HEAP 0x21FFE000 EMPTY 0x1000
+    ;{
+    ;}
+
+    ;ARM_LIB_STACK 0x22000000 EMPTY -0x1000
+    ;{
+    ;}
+}
diff --git a/bsp/at91sam9g45/platform/SConscript b/bsp/at91sam9g45/platform/SConscript
new file mode 100644
index 0000000000..1f5de6e772
--- /dev/null
+++ b/bsp/at91sam9g45/platform/SConscript
@@ -0,0 +1,26 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+# The set of source files associated with this SConscript file.
+if rtconfig.PLATFORM == 'armcc':
+	src = Glob('*.c') + Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+	src = Glob('*.c') + Glob('*_gcc.S') + Glob('*_init.S')
+
+if rtconfig.PLATFORM == 'iar':
+	src = Glob('*.c') + Glob('*_iar.S')
+
+if rtconfig.PLATFORM == 'cl':
+	src = Glob('*.c')
+
+if rtconfig.PLATFORM == 'mingw':
+	src = Glob('*.c')
+
+group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/at91sam9g45/platform/at91sam9g45.h b/bsp/at91sam9g45/platform/at91sam9g45.h
new file mode 100644
index 0000000000..348e265822
--- /dev/null
+++ b/bsp/at91sam9g45/platform/at91sam9g45.h
@@ -0,0 +1,7213 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  Copyright (c) 2008, Atmel Corporation
+// 
+//  All rights reserved.
+// 
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions are met:
+// 
+//  - Redistributions of source code must retain the above copyright notice,
+//  this list of conditions and the disclaimer below.
+// 
+//  Atmel's name may not be used to endorse or promote products derived from
+//  this software without specific prior written permission. 
+//  
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM9G45.h
+// Object              : AT91SAM9G45 definitions
+// Generated           : AT91 SW Application Group  06/25/2009 (10:53:08)
+// 
+// CVS Reference       : /AT91SAM9G45.pl/1.1/Wed May 20 12:05:51 2009//
+// CVS Reference       : /SYS_SAM9264.pl/1.2/Tue Oct  2 12:19:30 2007//
+// CVS Reference       : /HMATRIX2_SAM9G45.pl/1.1/Wed May 20 09:31:20 2009//
+// CVS Reference       : /PMC_SAM9264.pl/1.9/Thu Nov 29 09:55:11 2007//
+// CVS Reference       : /HDDRSDRC2_6304B.pl/1.1/Thu Oct 11 10:44:49 2007//
+// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//
+// CVS Reference       : /HSMC3_SAM9264.pl/1.1/Wed Oct 10 09:39:31 2007//
+// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb  9 17:16:57 2005//
+// CVS Reference       : /SFR_SAM9264.pl/1.4/Fri Feb 29 14:02:55 2008//
+// CVS Reference       : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
+// CVS Reference       : /PIO_SAM9264.pl/1.1/Wed Oct 10 09:38:26 2007//
+// CVS Reference       : /RSTC_6098A.pl/1.4/Fri Oct 17 13:27:55 2008//
+// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct  6 14:16:58 2004//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
+// CVS Reference       : /TC_6082A.pl/1.8/Fri Oct 17 13:27:58 2008//
+// CVS Reference       : /MCI_6101F.pl/1.3/Fri Jan 23 09:15:32 2009//
+// CVS Reference       : /TWI_6061B.pl/1.3/Fri Oct 17 13:27:59 2008//
+// CVS Reference       : /US_6089J.pl/1.3/Fri Oct 17 13:27:59 2008//
+// CVS Reference       : /SSC_6078B.pl/1.3/Fri Oct 17 13:27:57 2008//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
+// CVS Reference       : /AC97C_XXXX.pl/1.3/Tue Feb 22 17:08:27 2005//
+// CVS Reference       : /PWM_6044D.pl/1.2/Tue May 10 12:39:09 2005//
+// CVS Reference       : /LCDC_6063A.pl/1.6/Tue Jan 20 16:29:59 2009//
+// CVS Reference       : /HDMA_SAM9264.pl/1.2/Thu Sep 13 11:48:30 2007//
+// CVS Reference       : /UDPHS_SAM9_7ept6dma4iso.pl/1.4/Tue Jun 24 13:05:14 2008//
+// CVS Reference       : /TSC_SAM9264.pl/1.2/Thu Jun 25 08:43:26 2009//
+// CVS Reference       : /RTC_1245D.pl/1.3/Fri Sep 17 14:01:31 2004//
+// CVS Reference       : /EMACB_SAM9264.pl/1.1/Tue Sep 25 12:07:23 2007//
+// CVS Reference       : /uhphs_ohci.pl/1.1/Fri Jun 22 14:20:34 2007//
+// CVS Reference       : /uhphs_ehci.pl/1.3/Tue Jul 17 07:50:29 2007//
+// CVS Reference       : /ISI_SAM9264.pl/1.2/Wed Sep  3 08:30:55 2008//
+// CVS Reference       : /TRNG_xxxxx.pl/1.1/Wed Jul 18 12:02:58 2007//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM9G45_H
+#define AT91SAM9G45_H
+
+#ifndef __ASSEMBLY__
+typedef volatile unsigned int AT91C_REG;// Hardware register definition
+#define AT91C_CAST(a) (a)
+#else
+#define AT91C_CAST(a)
+#endif
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+//for CPSR
+
+#define ARM_MODE_ABT     0x17
+#define ARM_MODE_FIQ     0x11
+#define ARM_MODE_IRQ     0x12
+#define ARM_MODE_SVC     0x13
+#define ARM_MODE_SYS     0x1F
+#define ARM_MODE_UND     0x1b
+#define ARM_MODE_USR     0x10
+
+#define ARM_MODE_MASK    0x1F
+
+#define I_BIT            0x80
+#define F_BIT            0x40
+#define T_BIT            0x20
+
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR SPECIAL FUNCTION REGISTER
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SFR {
+	AT91C_REG	 SFR_EMA; 	// memory Extra Margin Adjustment control
+	AT91C_REG	 SFR_DDRCFG; 	// DDR2 SSTL18 control
+	AT91C_REG	 SFR_DDRDELAY; 	// DDR2 controller clock delay
+	AT91C_REG	 SFR_EBIDELAY; 	// EBI DDR controller clock delay
+	AT91C_REG	 SFR_UTMICFG; 	// UTMI Software Reset, and OHCI suspend interrupt control
+	AT91C_REG	 SFR_INT; 	// OHCI suspend Interrupt status
+} AT91S_SFR, *AT91PS_SFR;
+#else
+#define SFR_EMA         (AT91C_CAST(AT91C_REG *) 	0x00000000) // (SFR_EMA) memory Extra Margin Adjustment control
+#define SFR_DDRCFG      (AT91C_CAST(AT91C_REG *) 	0x00000004) // (SFR_DDRCFG) DDR2 SSTL18 control
+#define SFR_DDRDELAY    (AT91C_CAST(AT91C_REG *) 	0x00000008) // (SFR_DDRDELAY) DDR2 controller clock delay
+#define SFR_EBIDELAY    (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (SFR_EBIDELAY) EBI DDR controller clock delay
+#define SFR_UTMICFG     (AT91C_CAST(AT91C_REG *) 	0x00000010) // (SFR_UTMICFG) UTMI Software Reset, and OHCI suspend interrupt control
+#define SFR_OHCI_SUSP_INT (AT91C_CAST(AT91C_REG *) 	0x00000014) // (SFR_OHCI_SUSP_INT) OHCI suspend Interrupt status
+
+#endif
+// -------- SFR_EMA : (SFR Offset: 0x0) memory Extra Margin Adjustment control register -------- 
+#define AT91C_SFR_RAM_EMA     (0x7 <<  0) // (SFR) SRAM EMA
+#define 	AT91C_SFR_RAM_EMA_0                    (0x0) // (SFR) Normal Mode
+#define 	AT91C_SFR_RAM_EMA_1                    (0x1) // (SFR) DEBUG MODE 1
+#define 	AT91C_SFR_RAM_EMA_2                    (0x2) // (SFR) DEBUG MODE 2
+#define 	AT91C_SFR_RAM_EMA_3                    (0x3) // (SFR) DEBUG MODE 3
+#define 	AT91C_SFR_RAM_EMA_4                    (0x4) // (SFR) DEBUG MODE 4
+#define 	AT91C_SFR_RAM_EMA_5                    (0x5) // (SFR) DEBUG MODE 5
+#define 	AT91C_SFR_RAM_EMA_6                    (0x6) // (SFR) DEBUG MODE 6
+#define 	AT91C_SFR_RAM_EMA_7                    (0x7) // (SFR) DEBUG MODE 7
+#define AT91C_SFR_DPRAM_EMA   (0x7 <<  4) // (SFR) SRAM EMA
+#define 	AT91C_SFR_DPRAM_EMA_0                    (0x0 <<  4) // (SFR) Normal Mode
+#define 	AT91C_SFR_DPRAM_EMA_1                    (0x1 <<  4) // (SFR) DEBUG MODE 1
+#define 	AT91C_SFR_DPRAM_EMA_2                    (0x2 <<  4) // (SFR) DEBUG MODE 2
+#define 	AT91C_SFR_DPRAM_EMA_3                    (0x3 <<  4) // (SFR) DEBUG MODE 3
+#define 	AT91C_SFR_DPRAM_EMA_4                    (0x4 <<  4) // (SFR) DEBUG MODE 4
+#define 	AT91C_SFR_DPRAM_EMA_5                    (0x5 <<  4) // (SFR) DEBUG MODE 5
+#define 	AT91C_SFR_DPRAM_EMA_6                    (0x6 <<  4) // (SFR) DEBUG MODE 6
+#define 	AT91C_SFR_DPRAM_EMA_7                    (0x7 <<  4) // (SFR) DEBUG MODE 7
+#define AT91C_SFR_RF_EMA      (0x7 <<  8) // (SFR) SRAM EMA
+#define 	AT91C_SFR_RF_EMA_0                    (0x0 <<  8) // (SFR) Normal Mode
+#define 	AT91C_SFR_RF_EMA_1                    (0x1 <<  8) // (SFR) DEBUG MODE 1
+#define 	AT91C_SFR_RF_EMA_2                    (0x2 <<  8) // (SFR) DEBUG MODE 2
+#define 	AT91C_SFR_RF_EMA_3                    (0x3 <<  8) // (SFR) DEBUG MODE 3
+#define 	AT91C_SFR_RF_EMA_4                    (0x4 <<  8) // (SFR) DEBUG MODE 4
+#define 	AT91C_SFR_RF_EMA_5                    (0x5 <<  8) // (SFR) DEBUG MODE 5
+#define 	AT91C_SFR_RF_EMA_6                    (0x6 <<  8) // (SFR) DEBUG MODE 6
+#define 	AT91C_SFR_RF_EMA_7                    (0x7 <<  8) // (SFR) DEBUG MODE 7
+#define AT91C_SFR_DPRF_EMA    (0x7 << 12) // (SFR) SRAM EMA
+#define 	AT91C_SFR_DPRF_EMA_0                    (0x0 << 12) // (SFR) Normal Mode
+#define 	AT91C_SFR_DPRF_EMA_1                    (0x1 << 12) // (SFR) DEBUG MODE 1
+#define 	AT91C_SFR_DPRF_EMA_2                    (0x2 << 12) // (SFR) DEBUG MODE 2
+#define 	AT91C_SFR_DPRF_EMA_3                    (0x3 << 12) // (SFR) DEBUG MODE 3
+#define 	AT91C_SFR_DPRF_EMA_4                    (0x4 << 12) // (SFR) DEBUG MODE 4
+#define 	AT91C_SFR_DPRF_EMA_5                    (0x5 << 12) // (SFR) DEBUG MODE 5
+#define 	AT91C_SFR_DPRF_EMA_6                    (0x6 << 12) // (SFR) DEBUG MODE 6
+#define 	AT91C_SFR_DPRF_EMA_7                    (0x7 << 12) // (SFR) DEBUG MODE 7
+#define AT91C_SFR_ROM_EMA     (0x7 << 16) // (SFR) SRAM EMA
+#define 	AT91C_SFR_ROM_EMA_0                    (0x0 << 16) // (SFR) Normal Mode
+#define 	AT91C_SFR_ROM_EMA_1                    (0x1 << 16) // (SFR) DEBUG MODE 1
+#define 	AT91C_SFR_ROM_EMA_2                    (0x2 << 16) // (SFR) DEBUG MODE 2
+#define 	AT91C_SFR_ROM_EMA_3                    (0x3 << 16) // (SFR) DEBUG MODE 3
+#define 	AT91C_SFR_ROM_EMA_4                    (0x4 << 16) // (SFR) DEBUG MODE 4
+#define 	AT91C_SFR_ROM_EMA_5                    (0x5 << 16) // (SFR) DEBUG MODE 5
+#define 	AT91C_SFR_ROM_EMA_6                    (0x6 << 16) // (SFR) DEBUG MODE 6
+#define 	AT91C_SFR_ROM_EMA_7                    (0x7 << 16) // (SFR) DEBUG MODE 7
+// -------- SFR_DDRCFG : (SFR Offset: 0x4) DDR2 SSTL18 control register -------- 
+#define AT91C_SFR_DDRCFG_SSTL (0x1 <<  0) // (SFR) Control DDR2 pads SSTL mode control
+#define 	AT91C_SFR_DDRCFG_SSTL_NORMAL               (0x0) // (SFR) Force pads in SSTL18 mode when DDR2 is connected
+#define 	AT91C_SFR_DDRCFG_SSTL_COMPATIBLE           (0x1) // (SFR) LVCMOS level (compatible SSTL18)
+#define AT91C_SFR_DDRCFG_CLKDELAY (0x1 <<  8) // (SFR) Control DDR2 pads clocks delay on clk, dqs0, dqs1
+#define 	AT91C_SFR_DDRCFG_CLKDELAY_HARD                 (0x0 <<  8) // (SFR) Fixed by hardware
+#define 	AT91C_SFR_DDRCFG_CLKDELAY_SOFT                 (0x1 <<  8) // (SFR) Software must write correct delay value
+// -------- SFR_DDRDELAY : (SFR Offset: 0x8) DDR2 controller clock delay -------- 
+#define AT91C_SFR_DDRDELAY_CLK (0xFF <<  0) // (SFR) Control CLK clock delay
+#define 	AT91C_SFR_DDRDELAY_CLK_0                    (0x0) // (SFR) minimum delay
+#define 	AT91C_SFR_DDRDELAY_CLK_1                    (0x1) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_2                    (0x2) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_3                    (0x3) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_4                    (0x4) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_5                    (0x5) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_6                    (0x6) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_7                    (0x7) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_8                    (0x8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_9                    (0x9) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_10                   (0xA) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_11                   (0xB) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_12                   (0xC) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_13                   (0xD) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_14                   (0xE) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_15                   (0xF) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_CLK_16                   (0x10) // (SFR) 
+#define AT91C_SFR_DDRDELAY_DQS0 (0xFF <<  8) // (SFR) Control DQS0 clock delay
+#define 	AT91C_SFR_DDRDELAY_DQS0_0                    (0x0 <<  8) // (SFR) minimum delay
+#define 	AT91C_SFR_DDRDELAY_DQS0_1                    (0x1 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_2                    (0x2 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_3                    (0x3 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_4                    (0x4 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_5                    (0x5 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_6                    (0x6 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_7                    (0x7 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_8                    (0x8 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_9                    (0x9 <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_10                   (0xA <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_11                   (0xB <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_12                   (0xC <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_13                   (0xD <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_14                   (0xE <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_15                   (0xF <<  8) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS0_16                   (0x10 <<  8) // (SFR) 
+#define AT91C_SFR_DDRDELAY_DQS1 (0xFF << 16) // (SFR) Control DQS1 clock delay
+#define 	AT91C_SFR_DDRDELAY_DQS1_0                    (0x0 << 16) // (SFR) minimum delay
+#define 	AT91C_SFR_DDRDELAY_DQS1_1                    (0x1 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_2                    (0x2 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_3                    (0x3 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_4                    (0x4 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_5                    (0x5 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_6                    (0x6 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_7                    (0x7 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_8                    (0x8 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_9                    (0x9 << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_10                   (0xA << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_11                   (0xB << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_12                   (0xC << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_13                   (0xD << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_14                   (0xE << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_15                   (0xF << 16) // (SFR) 
+#define 	AT91C_SFR_DDRDELAY_DQS1_16                   (0x10 << 16) // (SFR) 
+// -------- SFR_EBIDELAY : (SFR Offset: 0xc) EBI DDR controller clock delay -------- 
+#define AT91C_SFR_EBIDELAY_CLK (0xFF <<  0) // (SFR) Control CLK clock delay
+#define 	AT91C_SFR_EBIDELAY_CLK_0                    (0x0) // (SFR) minimum delay
+#define 	AT91C_SFR_EBIDELAY_CLK_1                    (0x1) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_2                    (0x2) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_3                    (0x3) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_4                    (0x4) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_5                    (0x5) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_6                    (0x6) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_7                    (0x7) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_8                    (0x8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_9                    (0x9) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_10                   (0xA) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_11                   (0xB) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_12                   (0xC) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_13                   (0xD) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_14                   (0xE) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_15                   (0xF) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_CLK_16                   (0x10) // (SFR) 
+#define AT91C_SFR_EBIDELAY_DQS0 (0xFF <<  8) // (SFR) Control DQS0 clock delay
+#define 	AT91C_SFR_EBIDELAY_DQS0_0                    (0x0 <<  8) // (SFR) minimum delay
+#define 	AT91C_SFR_EBIDELAY_DQS0_1                    (0x1 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_2                    (0x2 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_3                    (0x3 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_4                    (0x4 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_5                    (0x5 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_6                    (0x6 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_7                    (0x7 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_8                    (0x8 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_9                    (0x9 <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_10                   (0xA <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_11                   (0xB <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_12                   (0xC <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_13                   (0xD <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_14                   (0xE <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_15                   (0xF <<  8) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS0_16                   (0x10 <<  8) // (SFR) 
+#define AT91C_SFR_EBIDELAY_DQS1 (0xFF << 16) // (SFR) Control DQS1 clock delay
+#define 	AT91C_SFR_EBIDELAY_DQS1_0                    (0x0 << 16) // (SFR) minimum delay
+#define 	AT91C_SFR_EBIDELAY_DQS1_1                    (0x1 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_2                    (0x2 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_3                    (0x3 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_4                    (0x4 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_5                    (0x5 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_6                    (0x6 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_7                    (0x7 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_8                    (0x8 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_9                    (0x9 << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_10                   (0xA << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_11                   (0xB << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_12                   (0xC << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_13                   (0xD << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_14                   (0xE << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_15                   (0xF << 16) // (SFR) 
+#define 	AT91C_SFR_EBIDELAY_DQS1_16                   (0x10 << 16) // (SFR) 
+// -------- SFR_UTMICFG : (SFR Offset: 0x10) UTMI Software Reset -------- 
+#define AT91C_SFR_UTMICFG_PORT0 (0x1 <<  0) // (SFR) UTMI Software Reset port 0
+#define AT91C_SFR_UTMICFG_PORT1 (0x1 <<  1) // (SFR) UTMI Software Reset port 1
+#define AT91C_SFR_UTMICFG_OHCI_SUSP_INT_ENABLE (0x1 <<  2) // (SFR) OHCI Suspend Interrupt enable
+// -------- SFR_OHCI_SUSP_INT : (SFR Offset: 0x14) OHCI suspend Interrupt status -------- 
+#define AT91C_SFR_OHCI_SUSP_INT_STATUS (0x3 <<  0) // (SFR) OHCI suspend Interrupt status
+#define 	AT91C_SFR_OHCI_SUSP_INT_STATUS_PORT0                (0x1) // (SFR) OHCI suspend Interrupt status for port 0
+#define 	AT91C_SFR_OHCI_SUSP_INT_STATUS_PORT1                (0x2) // (SFR) OHCI suspend Interrupt status for port 1
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SYS {
+	AT91C_REG	 Reserved0[3904]; 	// 
+	AT91C_REG	 SYS_RSTC_RCR; 	// Reset Control Register
+	AT91C_REG	 SYS_RSTC_RSR; 	// Reset Status Register
+	AT91C_REG	 SYS_RSTC_RMR; 	// Reset Mode Register
+	AT91C_REG	 Reserved1[1]; 	// 
+	AT91C_REG	 SYS_SHDWC_SHCR; 	// Shut Down Control Register
+	AT91C_REG	 SYS_SHDWC_SHMR; 	// Shut Down Mode Register
+	AT91C_REG	 SYS_SHDWC_SHSR; 	// Shut Down Status Register
+	AT91C_REG	 Reserved2[1]; 	// 
+	AT91C_REG	 SYS_RTTC0_RTMR; 	// Real-time Mode Register
+	AT91C_REG	 SYS_RTTC0_RTAR; 	// Real-time Alarm Register
+	AT91C_REG	 SYS_RTTC0_RTVR; 	// Real-time Value Register
+	AT91C_REG	 SYS_RTTC0_RTSR; 	// Real-time Status Register
+	AT91C_REG	 SYS_PITC_PIMR; 	// Period Interval Mode Register
+	AT91C_REG	 SYS_PITC_PISR; 	// Period Interval Status Register
+	AT91C_REG	 SYS_PITC_PIVR; 	// Period Interval Value Register
+	AT91C_REG	 SYS_PITC_PIIR; 	// Period Interval Image Register
+	AT91C_REG	 SYS_WDTC_WDCR; 	// Watchdog Control Register
+	AT91C_REG	 SYS_WDTC_WDMR; 	// Watchdog Mode Register
+	AT91C_REG	 SYS_WDTC_WDSR; 	// Watchdog Status Register
+	AT91C_REG	 Reserved3[1]; 	// 
+	AT91C_REG	 SYS_SLCKSEL; 	// Slow Clock Selection Register
+	AT91C_REG	 Reserved4[3]; 	// 
+	AT91C_REG	 SYS_GPBR[4]; 	// General Purpose Register
+	AT91C_REG	 Reserved5[16]; 	// 
+	AT91C_REG	 RTC_CR; 	// Control Register
+	AT91C_REG	 RTC_MR; 	// Mode Register
+	AT91C_REG	 RTC_TIMR; 	// Time Register
+	AT91C_REG	 RTC_CALR; 	// Calendar Register
+	AT91C_REG	 RTC_TIMALR; 	// Time Alarm Register
+	AT91C_REG	 RTC_CALALR; 	// Calendar Alarm Register
+	AT91C_REG	 RTC_SR; 	// Status Register
+	AT91C_REG	 RTC_SCCR; 	// Status Clear Command Register
+	AT91C_REG	 RTC_IER; 	// Interrupt Enable Register
+	AT91C_REG	 RTC_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 RTC_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 RTC_VER; 	// Valid Entry Register
+	AT91C_REG	 Reserved6[7]; 	// 
+	AT91C_REG	 SYS_RSTC_VER; 	// Version Register
+} AT91S_SYS, *AT91PS_SYS;
+#else
+#define SLCKSEL         (AT91C_CAST(AT91C_REG *) 	0x00003D50) // (SLCKSEL) Slow Clock Selection Register
+#define GPBR            (AT91C_CAST(AT91C_REG *) 	0x00003D60) // (GPBR) General Purpose Register
+
+#endif
+// -------- SLCKSEL : (SYS Offset: 0x3d50) Slow Clock Selection Register -------- 
+#define AT91C_SLCKSEL_RCEN    (0x1 <<  0) // (SYS) Enable Internal RC Oscillator
+#define AT91C_SLCKSEL_OSC32EN (0x1 <<  1) // (SYS) Enable External Oscillator
+#define AT91C_SLCKSEL_OSC32BYP (0x1 <<  2) // (SYS) Bypass External Oscillator
+#define AT91C_SLCKSEL_OSCSEL  (0x1 <<  3) // (SYS) OSC Selection
+// -------- GPBR : (SYS Offset: 0x3d60) GPBR General Purpose Register -------- 
+#define AT91C_GPBR_GPRV       (0x0 <<  0) // (SYS) General Purpose Register Value
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR External Bus Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EBI {
+	AT91C_REG	 EBI_DUMMY; 	// Dummy register - Do not use
+} AT91S_EBI, *AT91PS_EBI;
+#else
+#define EBI_DUMMY       (AT91C_CAST(AT91C_REG *) 	0x00000000) // (EBI_DUMMY) Dummy register - Do not use
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR DDR2/SDRAM Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_HDDRSDRC2 {
+	AT91C_REG	 HDDRSDRC2_MR; 	// Mode Register
+	AT91C_REG	 HDDRSDRC2_RTR; 	// Refresh Timer Register
+	AT91C_REG	 HDDRSDRC2_CR; 	// Configuration Register
+	AT91C_REG	 HDDRSDRC2_T0PR; 	// Timing0 Register
+	AT91C_REG	 HDDRSDRC2_T1PR; 	// Timing1 Register
+	AT91C_REG	 HDDRSDRC2_T2PR; 	// Timing2 Register
+	AT91C_REG	 HDDRSDRC2_T3PR; 	// Timing3 Register
+	AT91C_REG	 HDDRSDRC2_LPR; 	// Low-power Register
+	AT91C_REG	 HDDRSDRC2_MDR; 	// Memory Device Register
+	AT91C_REG	 HDDRSDRC2_DLL; 	// DLL Information Register
+	AT91C_REG	 HDDRSDRC2_VER; 	// DLL Version Register
+	AT91C_REG	 HDDRSDRC2_HS; 	// High Speed Register
+	AT91C_REG	 HDDRSDRC2_DELAY1; 	// Pad delay1 Register
+	AT91C_REG	 HDDRSDRC2_DELAY2; 	// Pad delay2 Register
+	AT91C_REG	 HDDRSDRC2_DELAY3; 	// Pad delay3 Register
+	AT91C_REG	 HDDRSDRC2_DELAY4; 	// Pad delay4 Register
+	AT91C_REG	 HDDRSDRC2_DELAY5; 	// Pad delay5 Register
+	AT91C_REG	 HDDRSDRC2_DELAY6; 	// Pad delay6 Register
+	AT91C_REG	 HDDRSDRC2_DELAY7; 	// Pad delay7 Register
+	AT91C_REG	 HDDRSDRC2_DELAY8; 	// Pad delay8 Register
+	AT91C_REG	 Reserved0[37]; 	// 
+	AT91C_REG	 HDDRSDRC2_WPCR; 	// High Speed Register
+	AT91C_REG	 HDDRSDRC2_WPSR; 	// High Speed Register
+	AT91C_REG	 Reserved1[4]; 	// 
+	AT91C_REG	 HDDRSDRC2_VERSION; 	// Version Register
+} AT91S_HDDRSDRC2, *AT91PS_HDDRSDRC2;
+#else
+#define HDDRSDRC2_MR    (AT91C_CAST(AT91C_REG *) 	0x00000000) // (HDDRSDRC2_MR) Mode Register
+#define HDDRSDRC2_RTR   (AT91C_CAST(AT91C_REG *) 	0x00000004) // (HDDRSDRC2_RTR) Refresh Timer Register
+#define HDDRSDRC2_CR    (AT91C_CAST(AT91C_REG *) 	0x00000008) // (HDDRSDRC2_CR) Configuration Register
+#define HDDRSDRC2_T0PR  (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (HDDRSDRC2_T0PR) Timing0 Register
+#define HDDRSDRC2_T1PR  (AT91C_CAST(AT91C_REG *) 	0x00000010) // (HDDRSDRC2_T1PR) Timing1 Register
+#define HDDRSDRC2_T2PR  (AT91C_CAST(AT91C_REG *) 	0x00000014) // (HDDRSDRC2_T2PR) Timing2 Register
+#define HDDRSDRC2_T3PR  (AT91C_CAST(AT91C_REG *) 	0x00000018) // (HDDRSDRC2_T3PR) Timing3 Register
+#define HDDRSDRC2_LPR   (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (HDDRSDRC2_LPR) Low-power Register
+#define HDDRSDRC2_MDR   (AT91C_CAST(AT91C_REG *) 	0x00000020) // (HDDRSDRC2_MDR) Memory Device Register
+#define HDDRSDRC2_DLL   (AT91C_CAST(AT91C_REG *) 	0x00000024) // (HDDRSDRC2_DLL) DLL Information Register
+#define HDDRSDRC2_DLL_VER (AT91C_CAST(AT91C_REG *) 	0x00000028) // (HDDRSDRC2_DLL_VER) DLL Version Register
+#define HDDRSDRC2_HS    (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (HDDRSDRC2_HS) High Speed Register
+#define HDDRSDRC2_DELAY1 (AT91C_CAST(AT91C_REG *) 	0x00000030) // (HDDRSDRC2_DELAY1) Pad delay1 Register
+#define HDDRSDRC2_DELAY2 (AT91C_CAST(AT91C_REG *) 	0x00000034) // (HDDRSDRC2_DELAY2) Pad delay2 Register
+#define HDDRSDRC2_DELAY3 (AT91C_CAST(AT91C_REG *) 	0x00000038) // (HDDRSDRC2_DELAY3) Pad delay3 Register
+#define HDDRSDRC2_DELAY4 (AT91C_CAST(AT91C_REG *) 	0x0000003C) // (HDDRSDRC2_DELAY4) Pad delay4 Register
+#define HDDRSDRC2_DELAY5 (AT91C_CAST(AT91C_REG *) 	0x00000040) // (HDDRSDRC2_DELAY5) Pad delay5 Register
+#define HDDRSDRC2_DELAY6 (AT91C_CAST(AT91C_REG *) 	0x00000044) // (HDDRSDRC2_DELAY6) Pad delay6 Register
+#define HDDRSDRC2_DELAY7 (AT91C_CAST(AT91C_REG *) 	0x00000048) // (HDDRSDRC2_DELAY7) Pad delay7 Register
+#define HDDRSDRC2_DELAY8 (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (HDDRSDRC2_DELAY8) Pad delay8 Register
+#define HDDRSDRC2_WPCR  (AT91C_CAST(AT91C_REG *) 	0x000000E4) // (HDDRSDRC2_WPCR) High Speed Register
+#define HDDRSDRC2_WPSR  (AT91C_CAST(AT91C_REG *) 	0x000000E8) // (HDDRSDRC2_WPSR) High Speed Register
+#define HDDRSDRC2_VERSION (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (HDDRSDRC2_VERSION) Version Register
+
+#endif
+// -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register -------- 
+#define AT91C_DDRC2_MODE      (0x7 <<  0) // (HDDRSDRC2) DDR/SDRAM Command Mode
+#define 	AT91C_DDRC2_MODE_NORMAL_CMD           (0x0) // (HDDRSDRC2) Normal Mode
+#define 	AT91C_DDRC2_MODE_NOP_CMD              (0x1) // (HDDRSDRC2) Issue a NOP Command at every access
+#define 	AT91C_DDRC2_MODE_PRCGALL_CMD          (0x2) // (HDDRSDRC2) Issue a All Banks Precharge Command at every access
+#define 	AT91C_DDRC2_MODE_LMR_CMD              (0x3) // (HDDRSDRC2) Issue a Load Mode Register at every access
+#define 	AT91C_DDRC2_MODE_RFSH_CMD             (0x4) // (HDDRSDRC2) Issue a Refresh
+#define 	AT91C_DDRC2_MODE_EXT_LMR_CMD          (0x5) // (HDDRSDRC2) Issue an Extended Load Mode Register
+#define 	AT91C_DDRC2_MODE_DEEP_CMD             (0x6) // (HDDRSDRC2) Enter Deep Power Mode
+#define 	AT91C_DDRC2_MODE_Reserved             (0x7) // (HDDRSDRC2) Reserved value
+// -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register -------- 
+#define AT91C_DDRC2_COUNT     (0xFFF <<  0) // (HDDRSDRC2) Refresh Timer Count
+// -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register -------- 
+#define AT91C_DDRC2_NC        (0x3 <<  0) // (HDDRSDRC2) Number of Column Bits
+#define 	AT91C_DDRC2_NC_DDR9_SDR8            (0x0) // (HDDRSDRC2) DDR 9 Bits | SDR 8 Bits
+#define 	AT91C_DDRC2_NC_DDR10_SDR9           (0x1) // (HDDRSDRC2) DDR 10 Bits | SDR 9 Bits
+#define 	AT91C_DDRC2_NC_DDR11_SDR10          (0x2) // (HDDRSDRC2) DDR 11 Bits | SDR 10 Bits
+#define 	AT91C_DDRC2_NC_DDR12_SDR11          (0x3) // (HDDRSDRC2) DDR 12 Bits | SDR 11 Bits
+#define AT91C_DDRC2_NR        (0x3 <<  2) // (HDDRSDRC2) Number of Row Bits
+#define 	AT91C_DDRC2_NR_11                   (0x0 <<  2) // (HDDRSDRC2) 11 Bits
+#define 	AT91C_DDRC2_NR_12                   (0x1 <<  2) // (HDDRSDRC2) 12 Bits
+#define 	AT91C_DDRC2_NR_13                   (0x2 <<  2) // (HDDRSDRC2) 13 Bits
+#define 	AT91C_DDRC2_NR_14                   (0x3 <<  2) // (HDDRSDRC2) 14 Bits
+#define AT91C_DDRC2_CAS       (0x7 <<  4) // (HDDRSDRC2) CAS Latency
+#define 	AT91C_DDRC2_CAS_2                    (0x2 <<  4) // (HDDRSDRC2) 2 cycles (DDR1/SDR)
+#define 	AT91C_DDRC2_CAS_3                    (0x3 <<  4) // (HDDRSDRC2) 3 cycles (DDR2/DDR1/SDR)
+#define 	AT91C_DDRC2_CAS_4                    (0x4 <<  4) // (HDDRSDRC2) 4 cycles (DDR2)
+#define 	AT91C_DDRC2_CAS_2_5                  (0x6 <<  4) // (HDDRSDRC2) 2.5 cycles (DDR1)
+#define AT91C_DDRC2_DLL       (0x1 <<  7) // (HDDRSDRC2) DLL Reset
+#define 	AT91C_DDRC2_DLL_RESET_DISABLED       (0x0 <<  7) // (HDDRSDRC2) DLL normal mode
+#define 	AT91C_DDRC2_DLL_RESET_ENABLED        (0x1 <<  7) // (HDDRSDRC2) Reset DLL
+#define AT91C_DDRC2_DIC_DS    (0x1 <<  8) // (HDDRSDRC2) Output driver impedance control
+#define AT91C_DDRC2_OCD       (0x7 << 12) // (HDDRSDRC2) Off chip driver
+#define 	AT91C_DDRC2_OCD_EXIT                 (0x0 << 12) // (HDDRSDRC2) Exit OCD calibration mode.
+#define 	AT91C_DDRC2_OCD_DEFAULT              (0x7 << 12) // (HDDRSDRC2) Program OCD calibration default value.
+#define AT91C_DDRC2_DQMS      (0x1 << 16) // (HDDRSDRC2) Data Mask share
+#define 	AT91C_DDRC2_DQMS_NOT_SHARED           (0x0 << 16) // (HDDRSDRC2) Used DQM bits are not shared
+#define 	AT91C_DDRC2_DQMS_SHARED               (0x1 << 16) // (HDDRSDRC2) Used DQM bits are shared
+#define AT91C_DDRC2_ENRDM     (0x1 << 17) // (HDDRSDRC2) DQS/DATA phase error correction
+#define 	AT91C_DDRC2_ENRDM_OFF                  (0x0 << 17) // (HDDRSDRC2) phase error correction disabled
+#define 	AT91C_DDRC2_ENRDM_ON                   (0x1 << 17) // (HDDRSDRC2) phase error correction enabled
+// -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register -------- 
+#define AT91C_DDRC2_TRAS      (0xF <<  0) // (HDDRSDRC2) Active to precharge delay
+#define 	AT91C_DDRC2_TRAS_0                    (0x0) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TRAS_1                    (0x1) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TRAS_2                    (0x2) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TRAS_3                    (0x3) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TRAS_4                    (0x4) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TRAS_5                    (0x5) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TRAS_6                    (0x6) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TRAS_7                    (0x7) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TRAS_8                    (0x8) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TRAS_9                    (0x9) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TRAS_10                   (0xA) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TRAS_11                   (0xB) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TRAS_12                   (0xC) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TRAS_13                   (0xD) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TRAS_14                   (0xE) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TRAS_15                   (0xF) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TRCD      (0xF <<  4) // (HDDRSDRC2) Row to column delay
+#define 	AT91C_DDRC2_TRCD_0                    (0x0 <<  4) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TRCD_1                    (0x1 <<  4) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TRCD_2                    (0x2 <<  4) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TRCD_3                    (0x3 <<  4) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TRCD_4                    (0x4 <<  4) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TRCD_5                    (0x5 <<  4) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TRCD_6                    (0x6 <<  4) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TRCD_7                    (0x7 <<  4) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TRCD_8                    (0x8 <<  4) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TRCD_9                    (0x9 <<  4) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TRCD_10                   (0xA <<  4) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TRCD_11                   (0xB <<  4) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TRCD_12                   (0xC <<  4) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TRCD_13                   (0xD <<  4) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TRCD_14                   (0xE <<  4) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TRCD_15                   (0xF <<  4) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TWR       (0xF <<  8) // (HDDRSDRC2) Write recovery delay
+#define 	AT91C_DDRC2_TWR_0                    (0x0 <<  8) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TWR_1                    (0x1 <<  8) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TWR_2                    (0x2 <<  8) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TWR_3                    (0x3 <<  8) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TWR_4                    (0x4 <<  8) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TWR_5                    (0x5 <<  8) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TWR_6                    (0x6 <<  8) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TWR_7                    (0x7 <<  8) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TWR_8                    (0x8 <<  8) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TWR_9                    (0x9 <<  8) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TWR_10                   (0xA <<  8) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TWR_11                   (0xB <<  8) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TWR_12                   (0xC <<  8) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TWR_13                   (0xD <<  8) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TWR_14                   (0xE <<  8) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TWR_15                   (0xF <<  8) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TRC       (0xF << 12) // (HDDRSDRC2) Row cycle delay
+#define 	AT91C_DDRC2_TRC_0                    (0x0 << 12) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TRC_1                    (0x1 << 12) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TRC_2                    (0x2 << 12) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TRC_3                    (0x3 << 12) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TRC_4                    (0x4 << 12) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TRC_5                    (0x5 << 12) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TRC_6                    (0x6 << 12) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TRC_7                    (0x7 << 12) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TRC_8                    (0x8 << 12) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TRC_9                    (0x9 << 12) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TRC_10                   (0xA << 12) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TRC_11                   (0xB << 12) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TRC_12                   (0xC << 12) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TRC_13                   (0xD << 12) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TRC_14                   (0xE << 12) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TRC_15                   (0xF << 12) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TRP       (0xF << 16) // (HDDRSDRC2) Row precharge delay
+#define 	AT91C_DDRC2_TRP_0                    (0x0 << 16) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TRP_1                    (0x1 << 16) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TRP_2                    (0x2 << 16) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TRP_3                    (0x3 << 16) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TRP_4                    (0x4 << 16) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TRP_5                    (0x5 << 16) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TRP_6                    (0x6 << 16) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TRP_7                    (0x7 << 16) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TRP_8                    (0x8 << 16) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TRP_9                    (0x9 << 16) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TRP_10                   (0xA << 16) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TRP_11                   (0xB << 16) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TRP_12                   (0xC << 16) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TRP_13                   (0xD << 16) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TRP_14                   (0xE << 16) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TRP_15                   (0xF << 16) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TRRD      (0xF << 20) // (HDDRSDRC2) Active bankA to Active bankB
+#define 	AT91C_DDRC2_TRRD_0                    (0x0 << 20) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TRRD_1                    (0x1 << 20) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TRRD_2                    (0x2 << 20) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TRRD_3                    (0x3 << 20) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TRRD_4                    (0x4 << 20) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TRRD_5                    (0x5 << 20) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TRRD_6                    (0x6 << 20) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TRRD_7                    (0x7 << 20) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TRRD_8                    (0x8 << 20) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TRRD_9                    (0x9 << 20) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TRRD_10                   (0xA << 20) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TRRD_11                   (0xB << 20) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TRRD_12                   (0xC << 20) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TRRD_13                   (0xD << 20) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TRRD_14                   (0xE << 20) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TRRD_15                   (0xF << 20) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TWTR      (0x1 << 24) // (HDDRSDRC2) Internal write to read delay
+#define 	AT91C_DDRC2_TWTR_0                    (0x0 << 24) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TWTR_1                    (0x1 << 24) // (HDDRSDRC2) Value :  1
+#define AT91C_DDRC2_TMRD      (0xF << 28) // (HDDRSDRC2) Load mode register command to active or refresh command
+#define 	AT91C_DDRC2_TMRD_0                    (0x0 << 28) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TMRD_1                    (0x1 << 28) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TMRD_2                    (0x2 << 28) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TMRD_3                    (0x3 << 28) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TMRD_4                    (0x4 << 28) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TMRD_5                    (0x5 << 28) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TMRD_6                    (0x6 << 28) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TMRD_7                    (0x7 << 28) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TMRD_8                    (0x8 << 28) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TMRD_9                    (0x9 << 28) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TMRD_10                   (0xA << 28) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TMRD_11                   (0xB << 28) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TMRD_12                   (0xC << 28) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TMRD_13                   (0xD << 28) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TMRD_14                   (0xE << 28) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TMRD_15                   (0xF << 28) // (HDDRSDRC2) Value : 15
+// -------- HDDRSDRC2_T1PR : (HDDRSDRC2 Offset: 0x10) Timing1 Register -------- 
+#define AT91C_DDRC2_TRFC      (0x1F <<  0) // (HDDRSDRC2) row cycle delay
+#define 	AT91C_DDRC2_TRFC_0                    (0x0) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TRFC_1                    (0x1) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TRFC_2                    (0x2) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TRFC_3                    (0x3) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TRFC_4                    (0x4) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TRFC_5                    (0x5) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TRFC_6                    (0x6) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TRFC_7                    (0x7) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TRFC_8                    (0x8) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TRFC_9                    (0x9) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TRFC_10                   (0xA) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TRFC_11                   (0xB) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TRFC_12                   (0xC) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TRFC_13                   (0xD) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TRFC_14                   (0xE) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TRFC_15                   (0xF) // (HDDRSDRC2) Value : 15
+#define 	AT91C_DDRC2_TRFC_16                   (0x10) // (HDDRSDRC2) Value : 16
+#define 	AT91C_DDRC2_TRFC_17                   (0x11) // (HDDRSDRC2) Value : 17
+#define 	AT91C_DDRC2_TRFC_18                   (0x12) // (HDDRSDRC2) Value : 18
+#define 	AT91C_DDRC2_TRFC_19                   (0x13) // (HDDRSDRC2) Value : 19
+#define 	AT91C_DDRC2_TRFC_20                   (0x14) // (HDDRSDRC2) Value : 20
+#define 	AT91C_DDRC2_TRFC_21                   (0x15) // (HDDRSDRC2) Value : 21
+#define 	AT91C_DDRC2_TRFC_22                   (0x16) // (HDDRSDRC2) Value : 22
+#define 	AT91C_DDRC2_TRFC_23                   (0x17) // (HDDRSDRC2) Value : 23
+#define 	AT91C_DDRC2_TRFC_24                   (0x18) // (HDDRSDRC2) Value : 24
+#define 	AT91C_DDRC2_TRFC_25                   (0x19) // (HDDRSDRC2) Value : 25
+#define 	AT91C_DDRC2_TRFC_26                   (0x1A) // (HDDRSDRC2) Value : 26
+#define 	AT91C_DDRC2_TRFC_27                   (0x1B) // (HDDRSDRC2) Value : 27
+#define 	AT91C_DDRC2_TRFC_28                   (0x1C) // (HDDRSDRC2) Value : 28
+#define 	AT91C_DDRC2_TRFC_29                   (0x1D) // (HDDRSDRC2) Value : 29
+#define 	AT91C_DDRC2_TRFC_30                   (0x1E) // (HDDRSDRC2) Value : 30
+#define 	AT91C_DDRC2_TRFC_31                   (0x1F) // (HDDRSDRC2) Value : 31
+#define AT91C_DDRC2_TXSNR     (0xFF <<  8) // (HDDRSDRC2) Exit self refresh delay to Read command
+#define 	AT91C_DDRC2_TXSNR_0                    (0x0 <<  8) // (HDDRSDRC2) Value :   0
+#define 	AT91C_DDRC2_TXSNR_8                    (0x8 <<  8) // (HDDRSDRC2) Value :   8
+#define 	AT91C_DDRC2_TXSNR_16                   (0x10 <<  8) // (HDDRSDRC2) Value :  16
+#define 	AT91C_DDRC2_TXSNR_32                   (0x20 <<  8) // (HDDRSDRC2) Value :  32
+#define 	AT91C_DDRC2_TXSNR_48                   (0x30 <<  8) // (HDDRSDRC2) Value :  48
+#define 	AT91C_DDRC2_TXSNR_64                   (0x40 <<  8) // (HDDRSDRC2) Value :  64
+#define 	AT91C_DDRC2_TXSNR_80                   (0x50 <<  8) // (HDDRSDRC2) Value :  80
+#define 	AT91C_DDRC2_TXSNR_96                   (0x60 <<  8) // (HDDRSDRC2) Value :  96
+#define 	AT91C_DDRC2_TXSNR_112                  (0x70 <<  8) // (HDDRSDRC2) Value : 112
+#define 	AT91C_DDRC2_TXSNR_128                  (0x80 <<  8) // (HDDRSDRC2) Value : 128
+#define 	AT91C_DDRC2_TXSNR_144                  (0x90 <<  8) // (HDDRSDRC2) Value : 144
+#define 	AT91C_DDRC2_TXSNR_160                  (0xA0 <<  8) // (HDDRSDRC2) Value : 160
+#define 	AT91C_DDRC2_TXSNR_176                  (0xB0 <<  8) // (HDDRSDRC2) Value : 176
+#define 	AT91C_DDRC2_TXSNR_192                  (0xC0 <<  8) // (HDDRSDRC2) Value : 192
+#define 	AT91C_DDRC2_TXSNR_208                  (0xD0 <<  8) // (HDDRSDRC2) Value : 208
+#define 	AT91C_DDRC2_TXSNR_224                  (0xE0 <<  8) // (HDDRSDRC2) Value : 224
+#define 	AT91C_DDRC2_TXSNR_240                  (0xF0 <<  8) // (HDDRSDRC2) Value : 240
+#define 	AT91C_DDRC2_TXSNR_255                  (0xFF <<  8) // (HDDRSDRC2) Value : 255
+#define AT91C_DDRC2_TXSRD     (0xFF << 16) // (HDDRSDRC2) Exit self refresh delay to Read command
+#define 	AT91C_DDRC2_TXSRD_0                    (0x0 << 16) // (HDDRSDRC2) Value :   0
+#define 	AT91C_DDRC2_TXSRD_8                    (0x8 << 16) // (HDDRSDRC2) Value :   8
+#define 	AT91C_DDRC2_TXSRD_16                   (0x10 << 16) // (HDDRSDRC2) Value :  16
+#define 	AT91C_DDRC2_TXSRD_32                   (0x20 << 16) // (HDDRSDRC2) Value :  32
+#define 	AT91C_DDRC2_TXSRD_48                   (0x30 << 16) // (HDDRSDRC2) Value :  48
+#define 	AT91C_DDRC2_TXSRD_64                   (0x40 << 16) // (HDDRSDRC2) Value :  64
+#define 	AT91C_DDRC2_TXSRD_80                   (0x50 << 16) // (HDDRSDRC2) Value :  80
+#define 	AT91C_DDRC2_TXSRD_96                   (0x60 << 16) // (HDDRSDRC2) Value :  96
+#define 	AT91C_DDRC2_TXSRD_112                  (0x70 << 16) // (HDDRSDRC2) Value : 112
+#define 	AT91C_DDRC2_TXSRD_128                  (0x80 << 16) // (HDDRSDRC2) Value : 128
+#define 	AT91C_DDRC2_TXSRD_144                  (0x90 << 16) // (HDDRSDRC2) Value : 144
+#define 	AT91C_DDRC2_TXSRD_160                  (0xA0 << 16) // (HDDRSDRC2) Value : 160
+#define 	AT91C_DDRC2_TXSRD_176                  (0xB0 << 16) // (HDDRSDRC2) Value : 176
+#define 	AT91C_DDRC2_TXSRD_192                  (0xC0 << 16) // (HDDRSDRC2) Value : 192
+#define 	AT91C_DDRC2_TXSRD_208                  (0xD0 << 16) // (HDDRSDRC2) Value : 208
+#define 	AT91C_DDRC2_TXSRD_224                  (0xE0 << 16) // (HDDRSDRC2) Value : 224
+#define 	AT91C_DDRC2_TXSRD_240                  (0xF0 << 16) // (HDDRSDRC2) Value : 240
+#define 	AT91C_DDRC2_TXSRD_255                  (0xFF << 16) // (HDDRSDRC2) Value : 255
+#define AT91C_DDRC2_TXP       (0xF << 24) // (HDDRSDRC2) Exit Power-down delay to first command
+#define 	AT91C_DDRC2_TXP_0                    (0x0 << 24) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TXP_1                    (0x1 << 24) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TXP_2                    (0x2 << 24) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TXP_3                    (0x3 << 24) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TXP_4                    (0x4 << 24) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TXP_5                    (0x5 << 24) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TXP_6                    (0x6 << 24) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TXP_7                    (0x7 << 24) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TXP_8                    (0x8 << 24) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TXP_9                    (0x9 << 24) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TXP_10                   (0xA << 24) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TXP_11                   (0xB << 24) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TXP_12                   (0xC << 24) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TXP_13                   (0xD << 24) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TXP_14                   (0xE << 24) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TXP_15                   (0xF << 24) // (HDDRSDRC2) Value : 15
+// -------- HDDRSDRC2_T2PR : (HDDRSDRC2 Offset: 0x14) Timing2 Register -------- 
+#define AT91C_DDRC2_TXARD     (0xF <<  0) // (HDDRSDRC2) Exit active power down delay to read command in 'Fast Exit' mode.
+#define 	AT91C_DDRC2_TXARD_0                    (0x0) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TXARD_1                    (0x1) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TXARD_2                    (0x2) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TXARD_3                    (0x3) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TXARD_4                    (0x4) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TXARD_5                    (0x5) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TXARD_6                    (0x6) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TXARD_7                    (0x7) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TXARD_8                    (0x8) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TXARD_9                    (0x9) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TXARD_10                   (0xA) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TXARD_11                   (0xB) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TXARD_12                   (0xC) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TXARD_13                   (0xD) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TXARD_14                   (0xE) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TXARD_15                   (0xF) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TXARDS    (0xF <<  4) // (HDDRSDRC2) Exit active power down delay to read command in 'Slow Exit' mode.
+#define 	AT91C_DDRC2_TXARDS_0                    (0x0 <<  4) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TXARDS_1                    (0x1 <<  4) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TXARDS_2                    (0x2 <<  4) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TXARDS_3                    (0x3 <<  4) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TXARDS_4                    (0x4 <<  4) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TXARDS_5                    (0x5 <<  4) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TXARDS_6                    (0x6 <<  4) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TXARDS_7                    (0x7 <<  4) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TXARDS_8                    (0x8 <<  4) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TXARDS_9                    (0x9 <<  4) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TXARDS_10                   (0xA <<  4) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TXARDS_11                   (0xB <<  4) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TXARDS_12                   (0xC <<  4) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TXARDS_13                   (0xD <<  4) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TXARDS_14                   (0xE <<  4) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TXARDS_15                   (0xF <<  4) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TRPA      (0xF << 8) // (HDDRSDRC2) Row precharge all delay
+#define 	AT91C_DDRC2_TRPA_0                    (0x0 << 8) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TRPA_1                    (0x1 << 8) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TRPA_2                    (0x2 << 8) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TRPA_3                    (0x3 << 8) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TRPA_4                    (0x4 << 8) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TRPA_5                    (0x5 << 8) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TRPA_6                    (0x6 << 8) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TRPA_7                    (0x7 << 8) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TRPA_8                    (0x8 << 8) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TRPA_9                    (0x9 << 8) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TRPA_10                   (0xA << 8) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TRPA_11                   (0xB << 8) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TRPA_12                   (0xC << 8) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TRPA_13                   (0xD << 8) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TRPA_14                   (0xE << 8) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TRPA_15                   (0xF << 8) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TRTP      (0x7 << 12) // (HDDRSDRC2) Read to Precharge delay
+#define 	AT91C_DDRC2_TRTP_0                    (0x0 << 12) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TRTP_1                    (0x1 << 12) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TRTP_2                    (0x2 << 12) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TRTP_3                    (0x3 << 12) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TRTP_4                    (0x4 << 12) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TRTP_5                    (0x5 << 12) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TRTP_6                    (0x6 << 12) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TRTP_7                    (0x7 << 12) // (HDDRSDRC2) Value :  7
+// -------- HDDRSDRC2_T3PR : (HDDRSDRC2 Offset: 0x18) Timing3 Register -------- 
+#define AT91C_DDRC2_TANPD     (0xF <<  0) // (HDDRSDRC2) ODT to power down entry
+#define 	AT91C_DDRC2_TANPD_0                    (0x0) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TANPD_1                    (0x1) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TANPD_2                    (0x2) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TANPD_3                    (0x3) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TANPD_4                    (0x4) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TANPD_5                    (0x5) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TANPD_6                    (0x6) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TANPD_7                    (0x7) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TANPD_8                    (0x8) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TANPD_9                    (0x9) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TANPD_10                   (0xA) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TANPD_11                   (0xB) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TANPD_12                   (0xC) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TANPD_13                   (0xD) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TANPD_14                   (0xE) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TANPD_15                   (0xF) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TAXPD     (0xF <<  4) // (HDDRSDRC2) ODT power down exit
+#define 	AT91C_DDRC2_TAXPD_0                    (0x0 <<  4) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TAXPD_1                    (0x1 <<  4) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TAXPD_2                    (0x2 <<  4) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TAXPD_3                    (0x3 <<  4) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TAXPD_4                    (0x4 <<  4) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TAXPD_5                    (0x5 <<  4) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TAXPD_6                    (0x6 <<  4) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TAXPD_7                    (0x7 <<  4) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TAXPD_8                    (0x8 <<  4) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TAXPD_9                    (0x9 <<  4) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TAXPD_10                   (0xA <<  4) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TAXPD_11                   (0xB <<  4) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TAXPD_12                   (0xC <<  4) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TAXPD_13                   (0xD <<  4) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TAXPD_14                   (0xE <<  4) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TAXPD_15                   (0xF <<  4) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TAOFPD    (0xF <<  8) // (HDDRSDRC2) ODT turn off in power down mode
+#define 	AT91C_DDRC2_TAOFPD_0                    (0x0 <<  8) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TAOFPD_1                    (0x1 <<  8) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TAOFPD_2                    (0x2 <<  8) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TAOFPD_3                    (0x3 <<  8) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TAOFPD_4                    (0x4 <<  8) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TAOFPD_5                    (0x5 <<  8) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TAOFPD_6                    (0x6 <<  8) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TAOFPD_7                    (0x7 <<  8) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TAOFPD_8                    (0x8 <<  8) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TAOFPD_9                    (0x9 <<  8) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TAOFPD_10                   (0xA <<  8) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TAOFPD_11                   (0xB <<  8) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TAOFPD_12                   (0xC <<  8) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TAOFPD_13                   (0xD <<  8) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TAOFPD_14                   (0xE <<  8) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TAOFPD_15                   (0xF <<  8) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TAOFD     (0xF << 12) // (HDDRSDRC2) ODT turn off delay
+#define 	AT91C_DDRC2_TAOFD_0                    (0x0 << 12) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TAOFD_1                    (0x1 << 12) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TAOFD_2                    (0x2 << 12) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TAOFD_3                    (0x3 << 12) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TAOFD_4                    (0x4 << 12) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TAOFD_5                    (0x5 << 12) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TAOFD_6                    (0x6 << 12) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TAOFD_7                    (0x7 << 12) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TAOFD_8                    (0x8 << 12) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TAOFD_9                    (0x9 << 12) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TAOFD_10                   (0xA << 12) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TAOFD_11                   (0xB << 12) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TAOFD_12                   (0xC << 12) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TAOFD_13                   (0xD << 12) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TAOFD_14                   (0xE << 12) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TAOFD_15                   (0xF << 12) // (HDDRSDRC2) Value : 15
+#define AT91C_DDRC2_TAONPD    (0xF << 16) // (HDDRSDRC2) ODT turn on in power down mode
+#define 	AT91C_DDRC2_TAONPD_0                    (0x0 << 16) // (HDDRSDRC2) Value :  0
+#define 	AT91C_DDRC2_TAONPD_1                    (0x1 << 16) // (HDDRSDRC2) Value :  1
+#define 	AT91C_DDRC2_TAONPD_2                    (0x2 << 16) // (HDDRSDRC2) Value :  2
+#define 	AT91C_DDRC2_TAONPD_3                    (0x3 << 16) // (HDDRSDRC2) Value :  3
+#define 	AT91C_DDRC2_TAONPD_4                    (0x4 << 16) // (HDDRSDRC2) Value :  4
+#define 	AT91C_DDRC2_TAONPD_5                    (0x5 << 16) // (HDDRSDRC2) Value :  5
+#define 	AT91C_DDRC2_TAONPD_6                    (0x6 << 16) // (HDDRSDRC2) Value :  6
+#define 	AT91C_DDRC2_TAONPD_7                    (0x7 << 16) // (HDDRSDRC2) Value :  7
+#define 	AT91C_DDRC2_TAONPD_8                    (0x8 << 16) // (HDDRSDRC2) Value :  8
+#define 	AT91C_DDRC2_TAONPD_9                    (0x9 << 16) // (HDDRSDRC2) Value :  9
+#define 	AT91C_DDRC2_TAONPD_10                   (0xA << 16) // (HDDRSDRC2) Value : 10
+#define 	AT91C_DDRC2_TAONPD_11                   (0xB << 16) // (HDDRSDRC2) Value : 11
+#define 	AT91C_DDRC2_TAONPD_12                   (0xC << 16) // (HDDRSDRC2) Value : 12
+#define 	AT91C_DDRC2_TAONPD_13                   (0xD << 16) // (HDDRSDRC2) Value : 13
+#define 	AT91C_DDRC2_TAONPD_14                   (0xE << 16) // (HDDRSDRC2) Value : 14
+#define 	AT91C_DDRC2_TAONPD_15                   (0xF << 16) // (HDDRSDRC2) Value : 15
+// -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c)  -------- 
+#define AT91C_DDRC2_LPCB      (0x3 <<  0) // (HDDRSDRC2) Low-power Command Bit
+#define 	AT91C_DDRC2_LPCB_DISABLED             (0x0) // (HDDRSDRC2) Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
+#define 	AT91C_DDRC2_LPCB_SELFREFRESH          (0x1) // (HDDRSDRC2) The DDRSDRAMC Controller issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
+#define 	AT91C_DDRC2_LPCB_POWERDOWN            (0x2) // (HDDRSDRC2) The HDDRSDRC2 Controller issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low. The SDRAM device leaves the power-down mode when accessed and enters it after the access.
+#define 	AT91C_DDRC2_LPCB_DEEP_PWD             (0x3) // (HDDRSDRC2) The HDDRSDRC2 Controller issues a Deep Power-down Command to the Mobile SDRAM device. This mode is unique to Mobile SDRAM devices
+#define AT91C_DDRC2_CLK_FR    (0x1 <<  2) // (HDDRSDRC2) Clock frozen Command Bit
+#define 	AT91C_DDRC2_CLK_FR_DISABLED             (0x0 <<  2) // (HDDRSDRC2) Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
+#define 	AT91C_DDRC2_CLK_FR_SELFREFRESH          (0x1 <<  2) // (HDDRSDRC2) The DDRSDRAMC Controller issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
+#define 	AT91C_DDRC2_CLK_FR_POWERDOWN            (0x2 <<  2) // (HDDRSDRC2) The HDDRSDRC2 Controller issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low. The SDRAM device leaves the power-down mode when accessed and enters it after the access.
+#define 	AT91C_DDRC2_CLK_FR_DEEP_PWD             (0x3 <<  2) // (HDDRSDRC2) The HDDRSDRC2 Controller issues a Deep Power-down Command to the Mobile SDRAM device. This mode is unique to Mobile SDRAM devices
+#define AT91C_DDRC2_PASR      (0x7 <<  4) // (HDDRSDRC2) Partial Array Self Refresh
+#define AT91C_                (0x0 <<  8) // (HDDRSDRC2) 
+#define AT91C_DDRC2_DS        (0x3 << 10) // (HDDRSDRC2) Drive strength
+#define AT91C_DDRC2_TIMEOUT   (0x3 << 12) // (HDDRSDRC2) low-power mode delay
+#define 	AT91C_DDRC2_TIMEOUT_0                    (0x0 << 12) // (HDDRSDRC2) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
+#define 	AT91C_DDRC2_TIMEOUT_64                   (0x1 << 12) // (HDDRSDRC2) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
+#define 	AT91C_DDRC2_TIMEOUT_128                  (0x2 << 12) // (HDDRSDRC2) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.
+#define 	AT91C_DDRC2_TIMEOUT_Reserved             (0x3 << 12) // (HDDRSDRC2) Reserved
+#define AT91C_DDRC2_ADPE      (0x1 << 16) // (HDDRSDRC2) Active Power Down Exit time
+#define 	AT91C_DDRC2_ADPE_FAST                 (0x0 << 16) // (HDDRSDRC2) Fast Exit
+#define 	AT91C_DDRC2_ADPE_SLOW                 (0x1 << 16) // (HDDRSDRC2) Slow Exit
+// -------- HDDRSDRC2_MDR : (HDDRSDRC2 Offset: 0x20) Memory Device Register -------- 
+#define AT91C_DDRC2_MD        (0x7 <<  0) // (HDDRSDRC2) memory device
+#define 	AT91C_DDRC2_MD_SDR_SDRAM            (0x0) // (HDDRSDRC2) SDR SDRAM
+#define 	AT91C_DDRC2_MD_LP_SDR_SDRAM         (0x1) // (HDDRSDRC2) Low Power SDR SDRAM
+#define 	AT91C_DDRC2_MD_DDR_SDRAM            (0x2) // (HDDRSDRC2) DDR SDRAM
+#define 	AT91C_DDRC2_MD_LP_DDR_SDRAM         (0x3) // (HDDRSDRC2) Low Power DDR SDRAM
+#define 	AT91C_DDRC2_MD_DDR2_SDRAM           (0x6) // (HDDRSDRC2) DDR2 SDRAM
+#define AT91C_DDRC2_DBW       (0x1 <<  4) // (HDDRSDRC2) Data Bus Width
+#define 	AT91C_DDRC2_DBW_32_BITS              (0x0 <<  4) // (HDDRSDRC2) 32 Bits datas bus
+#define 	AT91C_DDRC2_DBW_16_BITS              (0x1 <<  4) // (HDDRSDRC2) 16 Bits datas bus
+// -------- HDDRSDRC2_DLL : (HDDRSDRC2 Offset: 0x24) DLL Information Register -------- 
+#define AT91C_DDRC2_MDINC     (0x1 <<  0) // (HDDRSDRC2) DLL Master Delay Increment
+#define AT91C_DDRC2_MDDEC     (0x1 <<  1) // (HDDRSDRC2) DLL Master Delay Decrement
+#define AT91C_DDRC2_MDOVF     (0x1 <<  2) // (HDDRSDRC2) DLL Master Delay Overflow Flag
+#define AT91C_DDRC2_SDCOVF    (0x1 <<  3) // (HDDRSDRC2) DLL Slave Delay Correction Overflow Flag
+#define AT91C_DDRC2_SDCUDF    (0x1 <<  4) // (HDDRSDRC2) DLL Slave Delay Correction Underflow Flag
+#define AT91C_DDRC2_SDERF     (0x1 <<  5) // (HDDRSDRC2) DLL Slave Delay Correction Error Flag
+#define AT91C_DDRC2_MDVAL     (0xFF <<  8) // (HDDRSDRC2) DLL Master Delay Value
+#define AT91C_DDRC2_SDVAL     (0xFF << 16) // (HDDRSDRC2) DLL Slave Delay Value
+#define AT91C_DDRC2_SDCVAL    (0xFF << 24) // (HDDRSDRC2) DLL Slave Delay Correction Value
+// -------- HDDRSDRC2_HS : (HDDRSDRC2 Offset: 0x2c) High Speed Register -------- 
+#define AT91C_DDRC2_DA        (0x1 <<  0) // (HDDRSDRC2) Decode cycle
+#define AT91C_DDRC2_NO_OPT    (0x1 <<  1) // (HDDRSDRC2) Disable optimization
+#define AT91C_DDRC2_NO_ANT    (0x1 <<  2) // (HDDRSDRC2) Disable Anticipated read
+#define AT91C_DDRC2_RES_DQS   (0x1 <<  3) // (HDDRSDRC2) Reset DQS Active
+// -------- HDDRSDRC2_DELAY1 : (HDDRSDRC2 Offset: 0x30) Pad delay1 Register -------- 
+#define AT91C_DDRC2_DELAY     (0xF <<  0) // (HDDRSDRC2) Pad delay value
+// -------- HDDRSDRC2_DELAY2 : (HDDRSDRC2 Offset: 0x34) Pad delay2 Register -------- 
+// -------- HDDRSDRC2_DELAY3 : (HDDRSDRC2 Offset: 0x38) Pad delay3 Register -------- 
+// -------- HDDRSDRC2_DELAY4 : (HDDRSDRC2 Offset: 0x3c) Pad delay4 Register -------- 
+// -------- HDDRSDRC2_DELAY5 : (HDDRSDRC2 Offset: 0x40) Pad delay5 Register -------- 
+// -------- HDDRSDRC2_DELAY6 : (HDDRSDRC2 Offset: 0x44) Pad delay6 Register -------- 
+// -------- HDDRSDRC2_DELAY7 : (HDDRSDRC2 Offset: 0x48) Pad delay7 Register -------- 
+// -------- HDDRSDRC2_DELAY8 : (HDDRSDRC2 Offset: 0x4c) Pad delay8 Register -------- 
+// -------- HDDRSDRC2_WPCR : (HDDRSDRC2 Offset: 0xe4) Write Protect Control Register -------- 
+#define AT91C_DDRC2_WPEN      (0x1 <<  0) // (HDDRSDRC2) write protect enable
+#define AT91C_DDRC2_WPKEY     (0xFFFFFF <<  8) // (HDDRSDRC2) write protect key
+// -------- HDDRSDRC2_WPSR : (HDDRSDRC2 Offset: 0xe8) Write Protect Status Register -------- 
+#define AT91C_DDRC2_WPVS      (0x1 <<  0) // (HDDRSDRC2) write protect violation status
+#define AT91C_DDRC2_WPSRC     (0xFFFF <<  8) // (HDDRSDRC2) write protect source address
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Static Memory Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SMC {
+	AT91C_REG	 SMC_SETUP0; 	//  Setup Register for CS 0
+	AT91C_REG	 SMC_PULSE0; 	//  Pulse Register for CS 0
+	AT91C_REG	 SMC_CYCLE0; 	//  Cycle Register for CS 0
+	AT91C_REG	 SMC_CTRL0; 	//  Control Register for CS 0
+	AT91C_REG	 SMC_SETUP1; 	//  Setup Register for CS 1
+	AT91C_REG	 SMC_PULSE1; 	//  Pulse Register for CS 1
+	AT91C_REG	 SMC_CYCLE1; 	//  Cycle Register for CS 1
+	AT91C_REG	 SMC_CTRL1; 	//  Control Register for CS 1
+	AT91C_REG	 SMC_SETUP2; 	//  Setup Register for CS 2
+	AT91C_REG	 SMC_PULSE2; 	//  Pulse Register for CS 2
+	AT91C_REG	 SMC_CYCLE2; 	//  Cycle Register for CS 2
+	AT91C_REG	 SMC_CTRL2; 	//  Control Register for CS 2
+	AT91C_REG	 SMC_SETUP3; 	//  Setup Register for CS 3
+	AT91C_REG	 SMC_PULSE3; 	//  Pulse Register for CS 3
+	AT91C_REG	 SMC_CYCLE3; 	//  Cycle Register for CS 3
+	AT91C_REG	 SMC_CTRL3; 	//  Control Register for CS 3
+	AT91C_REG	 SMC_SETUP4; 	//  Setup Register for CS 4
+	AT91C_REG	 SMC_PULSE4; 	//  Pulse Register for CS 4
+	AT91C_REG	 SMC_CYCLE4; 	//  Cycle Register for CS 4
+	AT91C_REG	 SMC_CTRL4; 	//  Control Register for CS 4
+	AT91C_REG	 SMC_SETUP5; 	//  Setup Register for CS 5
+	AT91C_REG	 SMC_PULSE5; 	//  Pulse Register for CS 5
+	AT91C_REG	 SMC_CYCLE5; 	//  Cycle Register for CS 5
+	AT91C_REG	 SMC_CTRL5; 	//  Control Register for CS 5
+	AT91C_REG	 SMC_SETUP6; 	//  Setup Register for CS 6
+	AT91C_REG	 SMC_PULSE6; 	//  Pulse Register for CS 6
+	AT91C_REG	 SMC_CYCLE6; 	//  Cycle Register for CS 6
+	AT91C_REG	 SMC_CTRL6; 	//  Control Register for CS 6
+	AT91C_REG	 SMC_SETUP7; 	//  Setup Register for CS 7
+	AT91C_REG	 SMC_PULSE7; 	//  Pulse Register for CS 7
+	AT91C_REG	 SMC_CYCLE7; 	//  Cycle Register for CS 7
+	AT91C_REG	 SMC_CTRL7; 	//  Control Register for CS 7
+	AT91C_REG	 Reserved0[16]; 	// 
+	AT91C_REG	 SMC_DELAY1; 	// SMC Delay Control Register
+	AT91C_REG	 SMC_DELAY2; 	// SMC Delay Control Register
+	AT91C_REG	 SMC_DELAY3; 	// SMC Delay Control Register
+	AT91C_REG	 SMC_DELAY4; 	// SMC Delay Control Register
+	AT91C_REG	 SMC_DELAY5; 	// SMC Delay Control Register
+	AT91C_REG	 SMC_DELAY6; 	// SMC Delay Control Register
+	AT91C_REG	 SMC_DELAY7; 	// SMC Delay Control Register
+	AT91C_REG	 SMC_DELAY8; 	// SMC Delay Control Register
+} AT91S_SMC, *AT91PS_SMC;
+#else
+#define SETUP0          (AT91C_CAST(AT91C_REG *) 	0x00000000) // (SETUP0)  Setup Register for CS 0
+#define PULSE0          (AT91C_CAST(AT91C_REG *) 	0x00000004) // (PULSE0)  Pulse Register for CS 0
+#define CYCLE0          (AT91C_CAST(AT91C_REG *) 	0x00000008) // (CYCLE0)  Cycle Register for CS 0
+#define CTRL0           (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (CTRL0)  Control Register for CS 0
+#define SETUP1          (AT91C_CAST(AT91C_REG *) 	0x00000010) // (SETUP1)  Setup Register for CS 1
+#define PULSE1          (AT91C_CAST(AT91C_REG *) 	0x00000014) // (PULSE1)  Pulse Register for CS 1
+#define CYCLE1          (AT91C_CAST(AT91C_REG *) 	0x00000018) // (CYCLE1)  Cycle Register for CS 1
+#define CTRL1           (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (CTRL1)  Control Register for CS 1
+#define SETUP2          (AT91C_CAST(AT91C_REG *) 	0x00000020) // (SETUP2)  Setup Register for CS 2
+#define PULSE2          (AT91C_CAST(AT91C_REG *) 	0x00000024) // (PULSE2)  Pulse Register for CS 2
+#define CYCLE2          (AT91C_CAST(AT91C_REG *) 	0x00000028) // (CYCLE2)  Cycle Register for CS 2
+#define CTRL2           (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (CTRL2)  Control Register for CS 2
+#define SETUP3          (AT91C_CAST(AT91C_REG *) 	0x00000030) // (SETUP3)  Setup Register for CS 3
+#define PULSE3          (AT91C_CAST(AT91C_REG *) 	0x00000034) // (PULSE3)  Pulse Register for CS 3
+#define CYCLE3          (AT91C_CAST(AT91C_REG *) 	0x00000038) // (CYCLE3)  Cycle Register for CS 3
+#define CTRL3           (AT91C_CAST(AT91C_REG *) 	0x0000003C) // (CTRL3)  Control Register for CS 3
+#define SETUP4          (AT91C_CAST(AT91C_REG *) 	0x00000040) // (SETUP4)  Setup Register for CS 4
+#define PULSE4          (AT91C_CAST(AT91C_REG *) 	0x00000044) // (PULSE4)  Pulse Register for CS 4
+#define CYCLE4          (AT91C_CAST(AT91C_REG *) 	0x00000048) // (CYCLE4)  Cycle Register for CS 4
+#define CTRL4           (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (CTRL4)  Control Register for CS 4
+#define SETUP5          (AT91C_CAST(AT91C_REG *) 	0x00000050) // (SETUP5)  Setup Register for CS 5
+#define PULSE5          (AT91C_CAST(AT91C_REG *) 	0x00000054) // (PULSE5)  Pulse Register for CS 5
+#define CYCLE5          (AT91C_CAST(AT91C_REG *) 	0x00000058) // (CYCLE5)  Cycle Register for CS 5
+#define CTRL5           (AT91C_CAST(AT91C_REG *) 	0x0000005C) // (CTRL5)  Control Register for CS 5
+#define SETUP6          (AT91C_CAST(AT91C_REG *) 	0x00000060) // (SETUP6)  Setup Register for CS 6
+#define PULSE6          (AT91C_CAST(AT91C_REG *) 	0x00000064) // (PULSE6)  Pulse Register for CS 6
+#define CYCLE6          (AT91C_CAST(AT91C_REG *) 	0x00000068) // (CYCLE6)  Cycle Register for CS 6
+#define CTRL6           (AT91C_CAST(AT91C_REG *) 	0x0000006C) // (CTRL6)  Control Register for CS 6
+#define SETUP7          (AT91C_CAST(AT91C_REG *) 	0x00000070) // (SETUP7)  Setup Register for CS 7
+#define PULSE7          (AT91C_CAST(AT91C_REG *) 	0x00000074) // (PULSE7)  Pulse Register for CS 7
+#define CYCLE7          (AT91C_CAST(AT91C_REG *) 	0x00000078) // (CYCLE7)  Cycle Register for CS 7
+#define CTRL7           (AT91C_CAST(AT91C_REG *) 	0x0000007C) // (CTRL7)  Control Register for CS 7
+#define DELAY1          (AT91C_CAST(AT91C_REG *) 	0x000000C0) // (DELAY1) SMC Delay Control Register
+#define DELAY2          (AT91C_CAST(AT91C_REG *) 	0x000000C4) // (DELAY2) SMC Delay Control Register
+#define DELAY3          (AT91C_CAST(AT91C_REG *) 	0x000000C8) // (DELAY3) SMC Delay Control Register
+#define DELAY4          (AT91C_CAST(AT91C_REG *) 	0x000000CC) // (DELAY4) SMC Delay Control Register
+#define DELAY5          (AT91C_CAST(AT91C_REG *) 	0x000000D0) // (DELAY5) SMC Delay Control Register
+#define DELAY6          (AT91C_CAST(AT91C_REG *) 	0x000000D4) // (DELAY6) SMC Delay Control Register
+#define DELAY7          (AT91C_CAST(AT91C_REG *) 	0x000000D8) // (DELAY7) SMC Delay Control Register
+#define DELAY8          (AT91C_CAST(AT91C_REG *) 	0x000000DC) // (DELAY8) SMC Delay Control Register
+
+#endif
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- 
+#define AT91C_SMC_NWESETUP    (0x3F <<  0) // (SMC) NWE Setup Length
+#define AT91C_SMC_NCSSETUPWR  (0x3F <<  8) // (SMC) NCS Setup Length in WRite Access
+#define AT91C_SMC_NRDSETUP    (0x3F << 16) // (SMC) NRD Setup Length
+#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- 
+#define AT91C_SMC_NWEPULSE    (0x7F <<  0) // (SMC) NWE Pulse Length
+#define AT91C_SMC_NCSPULSEWR  (0x7F <<  8) // (SMC) NCS Pulse Length in WRite Access
+#define AT91C_SMC_NRDPULSE    (0x7F << 16) // (SMC) NRD Pulse Length
+#define AT91C_SMC_NCSPULSERD  (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- 
+#define AT91C_SMC_NWECYCLE    (0x1FF <<  0) // (SMC) Total Write Cycle Length
+#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) // (SMC) Total Read Cycle Length
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- 
+#define AT91C_SMC_READMODE    (0x1 <<  0) // (SMC) Read Mode
+#define AT91C_SMC_WRITEMODE   (0x1 <<  1) // (SMC) Write Mode
+#define AT91C_SMC_NWAITM      (0x3 <<  4) // (SMC) NWAIT Mode
+#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  4) // (SMC) External NWAIT disabled.
+#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  4) // (SMC) External NWAIT enabled in frozen mode.
+#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  4) // (SMC) External NWAIT enabled in ready mode.
+#define AT91C_SMC_BAT         (0x1 <<  8) // (SMC) Byte Access Type
+#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
+#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
+#define AT91C_SMC_DBW         (0x3 << 12) // (SMC) Data Bus Width
+#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (SMC) 8 bits.
+#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (SMC) 16 bits.
+#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
+#define AT91C_SMC_TDF         (0xF << 16) // (SMC) Data Float Time.
+#define AT91C_SMC_TDFEN       (0x1 << 20) // (SMC) TDF Enabled.
+#define AT91C_SMC_PMEN        (0x1 << 24) // (SMC) Page Mode Enabled.
+#define AT91C_SMC_PS          (0x3 << 28) // (SMC) Page Size
+#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (SMC) 4 bytes.
+#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (SMC) 8 bytes.
+#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (SMC) 16 bytes.
+#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR AHB Matrix Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MATRIX {
+	AT91C_REG	 MATRIX_MCFG0; 	//  Master Configuration Register 0 : ARM-I
+	AT91C_REG	 MATRIX_MCFG1; 	//  Master Configuration Register 1 ; ARM-D
+	AT91C_REG	 MATRIX_MCFG2; 	//  Master Configuration Register 2 : pdc
+	AT91C_REG	 MATRIX_MCFG3; 	//  Master Configuration Register 3 : USB Host OHCI
+	AT91C_REG	 MATRIX_MCFG4; 	//  Master Configuration Register 4 : DMA0
+	AT91C_REG	 MATRIX_MCFG5; 	//  Master Configuration Register 5 : DMA1
+	AT91C_REG	 MATRIX_MCFG6; 	//  Master Configuration Register 6 : hisi
+	AT91C_REG	 MATRIX_MCFG7; 	//  Master Configuration Register 7 : lcdc
+	AT91C_REG	 MATRIX_MCFG8; 	//  Master Configuration Register 8 : eMAC
+	AT91C_REG	 MATRIX_MCFG9; 	//  Master Configuration Register 9 : USB Device
+	AT91C_REG	 MATRIX_MCFG10; 	//  Master Configuration Register 10 : USB Host EHCI
+	AT91C_REG	 Reserved0[5]; 	// 
+	AT91C_REG	 MATRIX_SCFG0; 	//  Slave Configuration Register 0 : SRAM S0
+	AT91C_REG	 MATRIX_SCFG1; 	//  Slave Configuration Register 1 : SRAM S1
+	AT91C_REG	 MATRIX_SCFG2; 	//  Slave Configuration Register 2 : SRAM S2
+	AT91C_REG	 MATRIX_SCFG3; 	//  Slave Configuration Register 3 : SRAM S3
+	AT91C_REG	 MATRIX_SCFG4; 	//  Slave Configuration Register 4 ; ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+	AT91C_REG	 MATRIX_SCFG5; 	//  Slave Configuration Register 5 : DDR2 S0
+	AT91C_REG	 MATRIX_SCFG6; 	//  Slave Configuration Register 6 : DDR2 S1
+	AT91C_REG	 MATRIX_SCFG7; 	//  Slave Configuration Register 7 : DDR2 S2
+	AT91C_REG	 Reserved1[8]; 	// 
+	AT91C_REG	 MATRIX_PRAS0; 	//  PRAS0 : SRAM S0
+	AT91C_REG	 MATRIX_PRBS0; 	//  PRBS0 : SRAM S0
+	AT91C_REG	 MATRIX_PRAS1; 	//  PRAS1 : SRAM S1
+	AT91C_REG	 MATRIX_PRBS1; 	//  PRBS1 : SRAM S1
+	AT91C_REG	 MATRIX_PRAS2; 	//  PRAS2 : SRAM S2
+	AT91C_REG	 MATRIX_PRBS2; 	//  PRBS2 : SRAM S2
+	AT91C_REG	 MATRIX_PRAS3; 	//  PRAS3 : SRAM S3
+	AT91C_REG	 MATRIX_PRBS3; 	//  PRBS3 : SRAM S3
+	AT91C_REG	 MATRIX_PRAS4; 	//  PRAS4 : ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+	AT91C_REG	 MATRIX_PRBS4; 	//  PRBS4 : ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+	AT91C_REG	 MATRIX_PRAS5; 	//  PRAS5 : DDR2 S0
+	AT91C_REG	 MATRIX_PRBS5; 	//  PRBS5 : DDR2 S0
+	AT91C_REG	 MATRIX_PRAS6; 	//  PRAS6 : DDR2 S1
+	AT91C_REG	 MATRIX_PRBS6; 	//  PRBS6 : DDR2 S1
+	AT91C_REG	 MATRIX_PRAS7; 	//  PRAS7 : DDR2 S2
+	AT91C_REG	 MATRIX_PRBS7; 	//  PRBS7 : DDR2 S2
+	AT91C_REG	 Reserved2[16]; 	// 
+	AT91C_REG	 MATRIX_MRCR; 	//  Master Remap Control Register 
+	AT91C_REG	 Reserved3[3]; 	// 
+	AT91C_REG	 MATRIX_TCMR; 	//  Bus Matrix TCM Configuration Register 
+	AT91C_REG	 Reserved4[1]; 	// 
+	AT91C_REG	 MATRIX_DDRMPR; 	//  DDR Multi-Port Register 
+	AT91C_REG	 Reserved5[3]; 	// 
+	AT91C_REG	 MATRIX_EBICSA; 	//  EBI Chip Select Assignment Register 
+	AT91C_REG	 Reserved6[46]; 	// 
+	AT91C_REG	 MATRIX_WRPROTEN; 	//  Write Protection Control Register 
+	AT91C_REG	 MATRIX_WRPROTST; 	//  Write Protection Status Register 
+} AT91S_MATRIX, *AT91PS_MATRIX;
+#else
+#define MATRIX_MCFG0    (AT91C_CAST(AT91C_REG *) 	0x00000000) // (MATRIX_MCFG0)  Master Configuration Register 0 : ARM-I
+#define MATRIX_MCFG1    (AT91C_CAST(AT91C_REG *) 	0x00000004) // (MATRIX_MCFG1)  Master Configuration Register 1 ; ARM-D
+#define MATRIX_MCFG2    (AT91C_CAST(AT91C_REG *) 	0x00000008) // (MATRIX_MCFG2)  Master Configuration Register 2 : pdc
+#define MATRIX_MCFG3    (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (MATRIX_MCFG3)  Master Configuration Register 3 : USB Host OHCI
+#define MATRIX_MCFG4    (AT91C_CAST(AT91C_REG *) 	0x00000010) // (MATRIX_MCFG4)  Master Configuration Register 4 : DMA0
+#define MATRIX_MCFG5    (AT91C_CAST(AT91C_REG *) 	0x00000014) // (MATRIX_MCFG5)  Master Configuration Register 5 : DMA1
+#define MATRIX_MCFG6    (AT91C_CAST(AT91C_REG *) 	0x00000018) // (MATRIX_MCFG6)  Master Configuration Register 6 : hisi
+#define MATRIX_MCFG7    (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (MATRIX_MCFG7)  Master Configuration Register 7 : lcdc
+#define MATRIX_MCFG8    (AT91C_CAST(AT91C_REG *) 	0x00000020) // (MATRIX_MCFG8)  Master Configuration Register 8 : eMAC
+#define MATRIX_MCFG9    (AT91C_CAST(AT91C_REG *) 	0x00000024) // (MATRIX_MCFG9)  Master Configuration Register 9 : USB Device
+#define MATRIX_MCFG10   (AT91C_CAST(AT91C_REG *) 	0x00000028) // (MATRIX_MCFG10)  Master Configuration Register 10 : USB Host EHCI
+#define MATRIX_SCFG0    (AT91C_CAST(AT91C_REG *) 	0x00000040) // (MATRIX_SCFG0)  Slave Configuration Register 0 : SRAM S0
+#define MATRIX_SCFG1    (AT91C_CAST(AT91C_REG *) 	0x00000044) // (MATRIX_SCFG1)  Slave Configuration Register 1 : SRAM S1
+#define MATRIX_SCFG2    (AT91C_CAST(AT91C_REG *) 	0x00000048) // (MATRIX_SCFG2)  Slave Configuration Register 2 : SRAM S2
+#define MATRIX_SCFG3    (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (MATRIX_SCFG3)  Slave Configuration Register 3 : SRAM S3
+#define MATRIX_SCFG4    (AT91C_CAST(AT91C_REG *) 	0x00000050) // (MATRIX_SCFG4)  Slave Configuration Register 4 ; ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+#define MATRIX_SCFG5    (AT91C_CAST(AT91C_REG *) 	0x00000054) // (MATRIX_SCFG5)  Slave Configuration Register 5 : DDR2 S0
+#define MATRIX_SCFG6    (AT91C_CAST(AT91C_REG *) 	0x00000058) // (MATRIX_SCFG6)  Slave Configuration Register 6 : DDR2 S1
+#define MATRIX_SCFG7    (AT91C_CAST(AT91C_REG *) 	0x0000005C) // (MATRIX_SCFG7)  Slave Configuration Register 7 : DDR2 S2
+#define MATRIX_PRAS0    (AT91C_CAST(AT91C_REG *) 	0x00000080) // (MATRIX_PRAS0)  PRAS0 : SRAM S0
+#define MATRIX_PRBS0    (AT91C_CAST(AT91C_REG *) 	0x00000084) // (MATRIX_PRBS0)  PRBS0 : SRAM S0
+#define MATRIX_PRAS1    (AT91C_CAST(AT91C_REG *) 	0x00000088) // (MATRIX_PRAS1)  PRAS1 : SRAM S1
+#define MATRIX_PRBS1    (AT91C_CAST(AT91C_REG *) 	0x0000008C) // (MATRIX_PRBS1)  PRBS1 : SRAM S1
+#define MATRIX_PRAS2    (AT91C_CAST(AT91C_REG *) 	0x00000090) // (MATRIX_PRAS2)  PRAS2 : SRAM S2
+#define MATRIX_PRBS2    (AT91C_CAST(AT91C_REG *) 	0x00000094) // (MATRIX_PRBS2)  PRBS2 : SRAM S2
+#define MATRIX_PRAS3    (AT91C_CAST(AT91C_REG *) 	0x00000098) // (MATRIX_PRAS3)  PRAS3 : SRAM S3
+#define MATRIX_PRBS3    (AT91C_CAST(AT91C_REG *) 	0x0000009C) // (MATRIX_PRBS3)  PRBS3 : SRAM S3
+#define MATRIX_PRAS4    (AT91C_CAST(AT91C_REG *) 	0x000000A0) // (MATRIX_PRAS4)  PRAS4 : ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+#define MATRIX_PRBS4    (AT91C_CAST(AT91C_REG *) 	0x000000A4) // (MATRIX_PRBS4)  PRBS4 : ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+#define MATRIX_PRAS5    (AT91C_CAST(AT91C_REG *) 	0x000000A8) // (MATRIX_PRAS5)  PRAS5 : DDR2 S0
+#define MATRIX_PRBS5    (AT91C_CAST(AT91C_REG *) 	0x000000AC) // (MATRIX_PRBS5)  PRBS5 : DDR2 S0
+#define MATRIX_PRAS6    (AT91C_CAST(AT91C_REG *) 	0x000000B0) // (MATRIX_PRAS6)  PRAS6 : DDR2 S1
+#define MATRIX_PRBS6    (AT91C_CAST(AT91C_REG *) 	0x000000B4) // (MATRIX_PRBS6)  PRBS6 : DDR2 S1
+#define MATRIX_PRAS7    (AT91C_CAST(AT91C_REG *) 	0x000000B8) // (MATRIX_PRAS7)  PRAS7 : DDR2 S2
+#define MATRIX_PRBS7    (AT91C_CAST(AT91C_REG *) 	0x000000BC) // (MATRIX_PRBS7)  PRBS7 : DDR2 S2
+#define MATRIX_MRCR     (AT91C_CAST(AT91C_REG *) 	0x00000100) // (MATRIX_MRCR)  Master Remap Control Register 
+#define HMATRIX_CCFG_TCMR (AT91C_CAST(AT91C_REG *) 	0x00000110) // (HMATRIX_CCFG_TCMR)  Bus Matrix TCM Configuration Register 
+#define HMATRIX_CCFG_DDRMPR (AT91C_CAST(AT91C_REG *) 	0x00000118) // (HMATRIX_CCFG_DDRMPR)  DDR Multi-Port Register 
+#define HMATRIX_CCFG_EBICSA (AT91C_CAST(AT91C_REG *) 	0x00000128) // (HMATRIX_CCFG_EBICSA)  EBI Chip Select Assignment Register 
+#define MATRIX_WRPROTEN (AT91C_CAST(AT91C_REG *) 	0x000001E4) // (MATRIX_WRPROTEN)  Write Protection Control Register 
+#define MATRIX_WRPROTST (AT91C_CAST(AT91C_REG *) 	0x000001E8) // (MATRIX_WRPROTST)  Write Protection Status Register 
+
+#endif
+// -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register ARM-I -------- 
+#define AT91C_MATRIX_ULBT     (0x7 <<  0) // (MATRIX) Undefined Length Burst Type
+// -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register ARM-D -------- 
+// -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register PDC -------- 
+// -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register USB Host OHCI -------- 
+// -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register DMA0 -------- 
+// -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register DMA1 -------- 
+// -------- MATRIX_MCFG6 : (MATRIX Offset: 0x18) Master Configuration Register HISI -------- 
+// -------- MATRIX_MCFG7 : (MATRIX Offset: 0x1c) Master Configuration Register LCD -------- 
+// -------- MATRIX_MCFG8 : (MATRIX Offset: 0x20) Master Configuration Register EMAC -------- 
+// -------- MATRIX_MCFG9 : (MATRIX Offset: 0x24) Master Configuration Register USB Device -------- 
+// -------- MATRIX_MCFG10 : (MATRIX Offset: 0x28) Master Configuration Register USB Host EHCI -------- 
+// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- 
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF <<  0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
+#define AT91C_MATRIX_FIXED_DEFMSTR0 (0xF << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_PDC                  (0x2 << 18) // (MATRIX) PDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_UHPHS_OHCI           (0x3 << 18) // (MATRIX) USB Host OHCI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_DMA0                 (0x4 << 18) // (MATRIX) DMA0 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_DMA1                 (0x5 << 18) // (MATRIX) DMA1 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ISI                  (0x6 << 18) // (MATRIX) ISI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_EMAC                 (0x8 << 18) // (MATRIX) EMAC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_UDPHS                (0x9 << 18) // (MATRIX) USB Device Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_UHPHS_EHCI           (0xA << 18) // (MATRIX) USB Host EHCI Master is Default Master
+#define AT91C_MATRIX_ARBT     (0x3 << 24) // (MATRIX) Arbitration Type
+// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR1 (0xF << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_PDC                  (0x2 << 18) // (MATRIX) PDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ISI                  (0x6 << 18) // (MATRIX) ISI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_UDPHS                (0x9 << 18) // (MATRIX) USB Device Master is Default Master
+// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR2 (0xF << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR2_VDEC                 (0xB << 18) // (MATRIX) Video Decoder Master is Default Master
+// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR3 (0xF << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_LCD                  (0x7 << 18) // (MATRIX) LCD Master is Default Master
+// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR4 (0xF << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_PDC                  (0x2 << 18) // (MATRIX) PDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_UHPHS_OHCI           (0x3 << 18) // (MATRIX) USB Host OHCI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_DMA0                 (0x4 << 18) // (MATRIX) DMA0 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_DMA1                 (0x5 << 18) // (MATRIX) DMA1 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ISI                  (0x6 << 18) // (MATRIX) ISI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_EMAC                 (0x8 << 18) // (MATRIX) EMAC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_UDPHS                (0x9 << 18) // (MATRIX) USB Device Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_UHPHS_EHCI           (0xA << 18) // (MATRIX) USB Host EHCI Master is Default Master
+// -------- MATRIX_SCFG5 : (MATRIX Offset: 0x54) Slave Configuration Register 5 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR5 (0xF << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_PDC                  (0x2 << 18) // (MATRIX) PDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_UHPHS_OHCI           (0x3 << 18) // (MATRIX) USB Host OHCI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_DMA0                 (0x4 << 18) // (MATRIX) DMA0 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_DMA1                 (0x5 << 18) // (MATRIX) DMA1 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_ISI                  (0x6 << 18) // (MATRIX) ISI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_EMAC                 (0x8 << 18) // (MATRIX) EMAC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_UDPHS                (0x9 << 18) // (MATRIX) USB Device Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR5_UHPHS_EHCI           (0xA << 18) // (MATRIX) USB Host EHCI Master is Default Master
+// -------- MATRIX_SCFG6 : (MATRIX Offset: 0x58) Slave Configuration Register 6 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR6 (0xF << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_PDC                  (0x2 << 18) // (MATRIX) PDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_UHPHS_OHCI           (0x3 << 18) // (MATRIX) USB Host OHCI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_DMA0                 (0x4 << 18) // (MATRIX) DMA0 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_DMA1                 (0x5 << 18) // (MATRIX) DMA1 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_ISI                  (0x6 << 18) // (MATRIX) ISI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_LCD                  (0x7 << 18) // (MATRIX) LCD Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_EMAC                 (0x8 << 18) // (MATRIX) EMAC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_UDPHS                (0x9 << 18) // (MATRIX) USB Device Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_UHPHS_EHCI           (0xA << 18) // (MATRIX) USB Host EHCI Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR6_VDEC                 (0xB << 18) // (MATRIX) Video Decoder Master is Default Master
+// -------- MATRIX_SCFG7 : (MATRIX Offset: 0x5c) Slave Configuration Register 7 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR7 (0xF << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR7_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR7_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR7_PDC                  (0x2 << 18) // (MATRIX) PDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR7_DMA0                 (0x4 << 18) // (MATRIX) DMA0 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR7_DMA1                 (0x5 << 18) // (MATRIX) DMA1 Master is Default Master
+// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- 
+#define AT91C_MATRIX_M0PR     (0x3 <<  0) // (MATRIX) ARM926EJ-S Instruction priority
+#define AT91C_MATRIX_M1PR     (0x3 <<  4) // (MATRIX) ARM926EJ-S Data priority
+#define AT91C_MATRIX_M2PR     (0x3 <<  8) // (MATRIX) PDC priority
+#define AT91C_MATRIX_M3PR     (0x3 << 12) // (MATRIX) USB Host OHCI priority
+#define AT91C_MATRIX_M4PR     (0x3 << 16) // (MATRIX) DMA0 priority
+#define AT91C_MATRIX_M5PR     (0x3 << 20) // (MATRIX) DMA1 priority
+#define AT91C_MATRIX_M6PR     (0x3 << 24) // (MATRIX) ISI priority
+#define AT91C_MATRIX_M7PR     (0x3 << 28) // (MATRIX) LCD priority
+// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- 
+#define AT91C_MATRIX_M8PR     (0x3 <<  0) // (MATRIX) EMAC priority
+#define AT91C_MATRIX_M9PR     (0x3 <<  4) // (MATRIX) USB Device priority
+#define AT91C_MATRIX_M10PR    (0x3 <<  8) // (MATRIX) USB Host EHCI priority
+#define AT91C_MATRIX_M11PR    (0x3 << 12) // (MATRIX) Video Decoder priority
+// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- 
+// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- 
+// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- 
+// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- 
+// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- 
+// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- 
+// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- 
+// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- 
+// -------- MATRIX_PRAS5 : (MATRIX Offset: 0xa8) PRAS5 Register -------- 
+// -------- MATRIX_PRBS5 : (MATRIX Offset: 0xac) PRBS5 Register -------- 
+// -------- MATRIX_PRAS6 : (MATRIX Offset: 0xb0) PRAS6 Register -------- 
+// -------- MATRIX_PRBS6 : (MATRIX Offset: 0xb4) PRBS6 Register -------- 
+// -------- MATRIX_PRAS7 : (MATRIX Offset: 0xb8) PRAS7 Register -------- 
+// -------- MATRIX_PRBS7 : (MATRIX Offset: 0xbc) PRBS7 Register -------- 
+// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- 
+#define AT91C_MATRIX_RCA926I  (0x1 <<  0) // (MATRIX) Remap Command Bit for ARM926EJ-S Instruction
+#define AT91C_MATRIX_RCA926D  (0x1 <<  1) // (MATRIX) Remap Command Bit for ARM926EJ-S Data
+#define AT91C_MATRIX_RCB2     (0x1 <<  2) // (MATRIX) Remap Command Bit for PDC
+#define AT91C_MATRIX_RCB3     (0x1 <<  3) // (MATRIX) Remap Command Bit for USB Host OHCI
+#define AT91C_MATRIX_RCB4     (0x1 <<  4) // (MATRIX) Remap Command Bit for DMA0
+#define AT91C_MATRIX_RCB5     (0x1 <<  5) // (MATRIX) Remap Command Bit for DMA1
+#define AT91C_MATRIX_RCB6     (0x1 <<  6) // (MATRIX) Remap Command Bit for ISI
+#define AT91C_MATRIX_RCB7     (0x1 <<  7) // (MATRIX) Remap Command Bit for LCD
+#define AT91C_MATRIX_RCB8     (0x1 <<  8) // (MATRIX) Remap Command Bit for EMAC
+#define AT91C_MATRIX_RCB9     (0x1 <<  9) // (MATRIX) Remap Command Bit for USB Device
+#define AT91C_MATRIX_RCB10    (0x1 << 10) // (MATRIX) Remap Command Bit for USB Host EHCI
+#define AT91C_MATRIX_RCB11    (0x1 << 11) // (MATRIX) Remap Command Bit for Video Decoder
+// -------- HMATRIX_CCFG_TCMR : (MATRIX Offset: 0x110) TCMR Register -------- 
+#define AT91C_ITCM_SIZE       (0xF <<  0) // (MATRIX) Size of ITCM enabled memory block
+#define 	AT91C_ITCM_SIZE_0KB                  (0x0) // (MATRIX) 0 KB (No ITCM Memory)
+#define 	AT91C_ITCM_SIZE_32KB                 (0x6) // (MATRIX) 32 KB
+#define AT91C_DTCM_SIZE       (0xF <<  4) // (MATRIX) Size of DTCM enabled memory block
+#define 	AT91C_DTCM_SIZE_0KB                  (0x0 <<  4) // (MATRIX) 0 KB (No DTCM Memory)
+#define 	AT91C_DTCM_SIZE_32KB                 (0x6 <<  4) // (MATRIX) 32 KB
+#define 	AT91C_DTCM_SIZE_64KB                 (0x7 <<  4) // (MATRIX) 64 KB
+#define AT91C_TCM_NWS         (0x1 << 11) // (MATRIX) TCM Wait State
+#define 	AT91C_TCM_NWS_NO_WS                (0x0 << 11) // (MATRIX) NO WAIT STATE : 0 WS
+#define 	AT91C_TCM_NWS_ONE_WS               (0x1 << 11) // (MATRIX) 1 WS activated (only for RATIO 3:1 or 4:1
+// -------- HMATRIX_CCFG_DDRMPR : (MATRIX Offset: 0x118) DDR Multi-Port Register -------- 
+#define AT91C_DDRMP_DIS       (0x1 <<  0) // (MATRIX) DDR Multi-Port Disable
+// -------- HMATRIX_CCFG_EBICSA : (MATRIX Offset: 0x128) CCFG_EBICSA Register -------- 
+#define AT91C_EBI_CS1A        (0x1 <<  1) // (MATRIX) EBI Chip Select 1 Assignment
+#define 	AT91C_EBI_CS1A_SMC                  (0x0 <<  1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
+#define 	AT91C_EBI_CS1A_SDRAMC               (0x1 <<  1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_EBI_CS3A        (0x1 <<  3) // (MATRIX) EBI Chip Select 3 Assignment
+#define 	AT91C_EBI_CS3A_SMC                  (0x0 <<  3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
+#define 	AT91C_EBI_CS3A_SM                   (0x1 <<  3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_EBI_CS4A        (0x1 <<  4) // (MATRIX) EBI Chip Select 4 Assignment
+#define 	AT91C_EBI_CS4A_SMC                  (0x0 <<  4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
+#define 	AT91C_EBI_CS4A_CF                   (0x1 <<  4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
+#define AT91C_EBI_CS5A        (0x1 <<  5) // (MATRIX) EBI Chip Select 5 Assignment
+#define 	AT91C_EBI_CS5A_SMC                  (0x0 <<  5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
+#define 	AT91C_EBI_CS5A_CF                   (0x1 <<  5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
+#define AT91C_EBI_DBPUC       (0x1 <<  8) // (MATRIX) EBI Data Bus Pull-Up Configuration
+#define AT91C_EBI_DRIVE       (0x3 << 16) // (MATRIX) EBI I/O Drive Configuration
+#define 	AT91C_EBI_DRIVE_18RD                 (0x0 << 16) // (MATRIX) optimized for 1.8V powered memories with Reduced Drive
+#define 	AT91C_EBI_DRIVE_33RD                 (0x1 << 16) // (MATRIX) optimized for 3.3V powered memories with Reduced Drive
+#define 	AT91C_EBI_DRIVE_18ND                 (0x2 << 16) // (MATRIX) optimized for 1.8V powered memories with Normal Drive
+#define 	AT91C_EBI_DRIVE_33ND                 (0x3 << 16) // (MATRIX) optimized for 3.3V powered memories with Normal Drive
+#define AT91C_DDR_DRIVE       (0x1 << 18) // (MATRIX) DDR2 dedicated port I/O slew rate selection
+// -------- MATRIX_WRPROTEN : (MATRIX Offset: 0x1e4) Write Protection Control Register -------- 
+#define AT91C_MATRIX_WRPROT   (0x1 <<  0) // (MATRIX) Enable/Disable Write Protection of HMATRIX2 configuration registers (requires key)
+#define 	AT91C_MATRIX_WRPROT_DISABLE              (0x0) // (MATRIX) Disable Write Protection of HMATRIX2 configuration registers
+#define 	AT91C_MATRIX_WRPROT_ENABLE               (0x1) // (MATRIX) Enable  Write Protection of HMATRIX2 configuration registers
+// -------- MATRIX_WRPROTST : (MATRIX Offset: 0x1e8) Write Protection Status Register -------- 
+#define AT91C_MATRIX_WRPROT_VIOLATION (0x1 <<  0) // (MATRIX) Violation of Write Protection of HMATRIX2 configuration registers
+#define 	AT91C_MATRIX_WRPROT_VIOLATION_UNDETECTED           (0x0) // (MATRIX) No violation of Write Protection of HMATRIX2 configuration registers
+#define 	AT91C_MATRIX_WRPROT_VIOLATION_DETECTED             (0x1) // (MATRIX) Violation of  Write Protection of HMATRIX2 configuration registers
+#define AT91C_MATRIX_WRPROT_VIOLATION_OFFSET (0x1FF <<  8) // (MATRIX) Offset where violation of Write Protection of HMATRIX2 configuration registers is detected
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_AIC {
+	AT91C_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91C_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91C_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91C_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91C_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91C_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91C_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91C_REG	 Reserved0[2]; 	// 
+	AT91C_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91C_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91C_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91C_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91C_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91C_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91C_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91C_REG	 Reserved1[1]; 	// 
+	AT91C_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91C_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91C_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+#else
+#define AIC_SMR         (AT91C_CAST(AT91C_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
+#define AIC_SVR         (AT91C_CAST(AT91C_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
+#define AIC_IVR         (AT91C_CAST(AT91C_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
+#define AIC_FVR         (AT91C_CAST(AT91C_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
+#define AIC_ISR         (AT91C_CAST(AT91C_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
+#define AIC_IPR         (AT91C_CAST(AT91C_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
+#define AIC_IMR         (AT91C_CAST(AT91C_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
+#define AIC_CISR        (AT91C_CAST(AT91C_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
+#define AIC_IECR        (AT91C_CAST(AT91C_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
+#define AIC_IDCR        (AT91C_CAST(AT91C_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
+#define AIC_ICCR        (AT91C_CAST(AT91C_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
+#define AIC_ISCR        (AT91C_CAST(AT91C_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
+#define AIC_EOICR       (AT91C_CAST(AT91C_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
+#define AIC_SPU         (AT91C_CAST(AT91C_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
+#define AIC_DCR         (AT91C_CAST(AT91C_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
+#define AIC_FFER        (AT91C_CAST(AT91C_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
+#define AIC_FFDR        (AT91C_CAST(AT91C_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
+#define AIC_FFSR        (AT91C_CAST(AT91C_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
+
+#endif
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PDC {
+	AT91C_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91C_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91C_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91C_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+#else
+#define PDC_RPR         (AT91C_CAST(AT91C_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
+#define PDC_RCR         (AT91C_CAST(AT91C_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
+#define PDC_TPR         (AT91C_CAST(AT91C_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
+#define PDC_TCR         (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
+#define PDC_RNPR        (AT91C_CAST(AT91C_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
+#define PDC_RNCR        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
+#define PDC_TNPR        (AT91C_CAST(AT91C_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
+#define PDC_TNCR        (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
+#define PDC_PTCR        (AT91C_CAST(AT91C_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
+#define PDC_PTSR        (AT91C_CAST(AT91C_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
+
+#endif
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_DBGU {
+	AT91C_REG	 DBGU_CR; 	// Control Register
+	AT91C_REG	 DBGU_MR; 	// Mode Register
+	AT91C_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91C_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91C_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91C_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91C_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91C_REG	 Reserved0[7]; 	// 
+	AT91C_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91C_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91C_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91C_REG	 Reserved1[45]; 	// 
+	AT91C_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91C_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91C_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91C_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+#else
+#define DBGU_CR         (AT91C_CAST(AT91C_REG *) 	0x00000000) // (DBGU_CR) Control Register
+#define DBGU_MR         (AT91C_CAST(AT91C_REG *) 	0x00000004) // (DBGU_MR) Mode Register
+#define DBGU_IER        (AT91C_CAST(AT91C_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
+#define DBGU_IDR        (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
+#define DBGU_IMR        (AT91C_CAST(AT91C_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
+#define DBGU_CSR        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
+#define DBGU_RHR        (AT91C_CAST(AT91C_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
+#define DBGU_THR        (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
+#define DBGU_BRGR       (AT91C_CAST(AT91C_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
+#define DBGU_CIDR       (AT91C_CAST(AT91C_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
+#define DBGU_EXID       (AT91C_CAST(AT91C_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
+#define DBGU_FNTR       (AT91C_CAST(AT91C_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
+
+#endif
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PIO {
+	AT91C_REG	 PIO_PER; 	// PIO Enable Register
+	AT91C_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91C_REG	 PIO_PSR; 	// PIO Status Register
+	AT91C_REG	 Reserved0[1]; 	// 
+	AT91C_REG	 PIO_OER; 	// Output Enable Register
+	AT91C_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91C_REG	 PIO_OSR; 	// Output Status Register
+	AT91C_REG	 Reserved1[1]; 	// 
+	AT91C_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91C_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91C_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91C_REG	 Reserved2[1]; 	// 
+	AT91C_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91C_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91C_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91C_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91C_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91C_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91C_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91C_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91C_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91C_REG	 Reserved3[1]; 	// 
+	AT91C_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91C_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91C_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91C_REG	 Reserved4[1]; 	// 
+	AT91C_REG	 PIO_ASR; 	// Select A Register
+	AT91C_REG	 PIO_BSR; 	// Select B Register
+	AT91C_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91C_REG	 Reserved5[9]; 	// 
+	AT91C_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91C_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91C_REG	 PIO_OWSR; 	// Output Write Status Register
+	AT91C_REG	 Reserved6[1]; 	// 
+	AT91C_REG	 PIO_SLEWRATE1; 	// PIO Slewrate Control Register
+	AT91C_REG	 Reserved7[3]; 	// 
+	AT91C_REG	 PIO_DELAY1; 	// PIO Delay Control Register
+	AT91C_REG	 PIO_DELAY2; 	// PIO Delay Control Register
+	AT91C_REG	 PIO_DELAY3; 	// PIO Delay Control Register
+	AT91C_REG	 PIO_DELAY4; 	// PIO Delay Control Register
+	AT91C_REG	 Reserved8[11]; 	// 
+	AT91C_REG	 PIO_VERSION; 	// PIO Version Register
+} AT91S_PIO, *AT91PS_PIO;
+#else
+#define PIO_PER         (AT91C_CAST(AT91C_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
+#define PIO_PDR         (AT91C_CAST(AT91C_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
+#define PIO_PSR         (AT91C_CAST(AT91C_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
+#define PIO_OER         (AT91C_CAST(AT91C_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
+#define PIO_ODR         (AT91C_CAST(AT91C_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
+#define PIO_OSR         (AT91C_CAST(AT91C_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
+#define PIO_IFER        (AT91C_CAST(AT91C_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
+#define PIO_IFDR        (AT91C_CAST(AT91C_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
+#define PIO_IFSR        (AT91C_CAST(AT91C_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
+#define PIO_SODR        (AT91C_CAST(AT91C_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
+#define PIO_CODR        (AT91C_CAST(AT91C_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
+#define PIO_ODSR        (AT91C_CAST(AT91C_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
+#define PIO_PDSR        (AT91C_CAST(AT91C_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
+#define PIO_IER         (AT91C_CAST(AT91C_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
+#define PIO_IDR         (AT91C_CAST(AT91C_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
+#define PIO_IMR         (AT91C_CAST(AT91C_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
+#define PIO_ISR         (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
+#define PIO_MDER        (AT91C_CAST(AT91C_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
+#define PIO_MDDR        (AT91C_CAST(AT91C_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
+#define PIO_MDSR        (AT91C_CAST(AT91C_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
+#define PIO_PPUDR       (AT91C_CAST(AT91C_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
+#define PIO_PPUER       (AT91C_CAST(AT91C_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
+#define PIO_PPUSR       (AT91C_CAST(AT91C_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
+#define PIO_ASR         (AT91C_CAST(AT91C_REG *) 	0x00000070) // (PIO_ASR) Select A Register
+#define PIO_BSR         (AT91C_CAST(AT91C_REG *) 	0x00000074) // (PIO_BSR) Select B Register
+#define PIO_ABSR        (AT91C_CAST(AT91C_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
+#define PIO_OWER        (AT91C_CAST(AT91C_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
+#define PIO_OWDR        (AT91C_CAST(AT91C_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
+#define PIO_OWSR        (AT91C_CAST(AT91C_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
+#define SLEWRATE1       (AT91C_CAST(AT91C_REG *) 	0x000000B0) // (SLEWRATE1) PIO Slewrate Control Register
+#define PIO_VERSION     (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (PIO_VERSION) PIO Version Register
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controller V610
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PMC {
+	AT91C_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91C_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91C_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91C_REG	 Reserved0[1]; 	// 
+	AT91C_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91C_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91C_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91C_REG	 PMC_UCKR; 	// UTMI Clock Configuration Register
+	AT91C_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91C_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91C_REG	 PMC_PLLAR; 	// PLL A Register
+	AT91C_REG	 Reserved1[1]; 	// 
+	AT91C_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91C_REG	 Reserved2[1]; 	// 
+	AT91C_REG	 PMC_USB; 	// USB clock register
+	AT91C_REG	 Reserved3[1]; 	// 
+	AT91C_REG	 PMC_PCKR[2]; 	// Programmable Clock 0 Register
+	AT91C_REG	 Reserved4[6]; 	// 
+	AT91C_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91C_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 PMC_SR; 	// Status Register
+	AT91C_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 Reserved5[4]; 	// 
+	AT91C_REG	 PMC_PLLICPR; 	// PLL Charge Pump Current Register
+	AT91C_REG	 Reserved6[26]; 	// 
+	AT91C_REG	 PMC_ADDRSIZE; 	// 
+	AT91C_REG	 PMC_NAME1; 	// 
+	AT91C_REG	 PMC_NAME2; 	// 
+	AT91C_REG	 PMC_FEATURES; 	// 
+	AT91C_REG	 PMC_VERSION; 	// 
+} AT91S_PMC, *AT91PS_PMC;
+#else
+#define PMC_SCER        (AT91C_CAST(AT91C_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
+#define PMC_SCDR        (AT91C_CAST(AT91C_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
+#define PMC_SCSR        (AT91C_CAST(AT91C_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
+#define PMC_PCER        (AT91C_CAST(AT91C_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
+#define PMC_PCDR        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
+#define PMC_PCSR        (AT91C_CAST(AT91C_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
+#define CKGR_UCKR       (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (CKGR_UCKR) UTMI Clock Configuration Register
+#define CKGR_MOR        (AT91C_CAST(AT91C_REG *) 	0x00000020) // (CKGR_MOR) Main Oscillator Register
+#define CKGR_MCFR       (AT91C_CAST(AT91C_REG *) 	0x00000024) // (CKGR_MCFR) Main Clock  Frequency Register
+#define CKGR_PLLAR      (AT91C_CAST(AT91C_REG *) 	0x00000028) // (CKGR_PLLAR) PLL A Register
+#define PMC_MCKR        (AT91C_CAST(AT91C_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
+#define PMC_USB         (AT91C_CAST(AT91C_REG *) 	0x00000038) // (PMC_USB) USB clock register
+#define PMC_PCKR        (AT91C_CAST(AT91C_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock 0 Register
+#define PMC_IER         (AT91C_CAST(AT91C_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
+#define PMC_IDR         (AT91C_CAST(AT91C_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
+#define PMC_SR          (AT91C_CAST(AT91C_REG *) 	0x00000068) // (PMC_SR) Status Register
+#define PMC_IMR         (AT91C_CAST(AT91C_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
+#define PMC_PLLICPR     (AT91C_CAST(AT91C_REG *) 	0x00000080) // (PMC_PLLICPR) PLL Charge Pump Current Register
+#define PMC_ADDRSIZE    (AT91C_CAST(AT91C_REG *) 	0x000000EC) // (PMC_ADDRSIZE) 
+#define PMC_NAME1       (AT91C_CAST(AT91C_REG *) 	0x000000F0) // (PMC_NAME1) 
+#define PMC_NAME2       (AT91C_CAST(AT91C_REG *) 	0x000000F4) // (PMC_NAME2) 
+#define PMC_FEATURES    (AT91C_CAST(AT91C_REG *) 	0x000000F8) // (PMC_FEATURES) 
+#define PMC_VERSION     (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (PMC_VERSION) 
+
+#endif
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_DDR         (0x1 <<  2) // (PMC) DDR controller Clock2x
+#define AT91C_PMC_UHP         (0x1 <<  6) // (PMC) USB Host Port Clock
+#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register -------- 
+#define AT91C_CKGR_UPLLEN     (0x1 << 16) // (PMC) UTMI PLL Enable
+#define 	AT91C_CKGR_UPLLEN_DISABLED             (0x0 << 16) // (PMC) The UTMI PLL is disabled
+#define 	AT91C_CKGR_UPLLEN_ENABLED              (0x1 << 16) // (PMC) The UTMI PLL is enabled
+#define AT91C_CKGR_PLLCOUNT   (0xF << 20) // (PMC) UTMI Oscillator Start-up Time
+#define AT91C_CKGR_BIASEN     (0x1 << 24) // (PMC) UTMI BIAS Enable
+#define 	AT91C_CKGR_BIASEN_DISABLED             (0x0 << 24) // (PMC) The UTMI BIAS is disabled
+#define 	AT91C_CKGR_BIASEN_ENABLED              (0x1 << 24) // (PMC) The UTMI BIAS is enabled
+#define AT91C_CKGR_BIASCOUNT  (0xF << 28) // (PMC) UTMI BIAS Start-up Time
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (PMC) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (PMC) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (PMC) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (PMC) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (PMC) Main Clock Ready
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- 
+#define AT91C_CKGR_DIVA       (0xFF <<  0) // (PMC) Divider A Selected
+#define 	AT91C_CKGR_DIVA_0                    (0x0) // (PMC) Divider A output is 0
+#define 	AT91C_CKGR_DIVA_BYPASS               (0x1) // (PMC) Divider A is bypassed
+#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) // (PMC) PLL A Counter
+#define AT91C_CKGR_OUTA       (0x3 << 14) // (PMC) PLL A Output Frequency Range
+#define 	AT91C_CKGR_OUTA_0                    (0x0 << 14) // (PMC) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_1                    (0x1 << 14) // (PMC) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_2                    (0x2 << 14) // (PMC) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_3                    (0x3 << 14) // (PMC) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA       (0xFF << 16) // (PMC) PLL A Multiplier
+#define AT91C_CKGR_SRCA       (0x1 << 29) // (PMC) 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected
+#define 	AT91C_PMC_CSS_UPLL_CLK             (0x3) // (PMC) Clock from UTMI PLL is selected
+#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+#define AT91C_PMC_MDIV        (0x3 <<  8) // (PMC) Master Clock Division
+#define 	AT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) Processor clock = Master Clock ; DDR Clock = Master Clock
+#define 	AT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) Processor clock = 2 * Master Clock ; DDR Clock = 2 * Master Clock
+#define 	AT91C_PMC_MDIV_4                    (0x2 <<  8) // (PMC) Processor clock = 4 * Master Clock ; DDR Clock = 2 * Master Clock
+#define 	AT91C_PMC_MDIV_3                    (0x3 <<  8) // (PMC) Processor clock = 3 * Master Clock ; DDR Clock = 2 * Master Clock
+#define AT91C_PMC_PLLADIV2    (0x1 << 12) // (PMC) PLLA divisor by 2
+#define 	AT91C_PMC_PLLADIV2_1                    (0x0 << 12) // (PMC) PLLA clock frequency is divided by 1
+#define 	AT91C_PMC_PLLADIV2_2                    (0x1 << 12) // (PMC) PLLA clock frequency is divided by 2
+// -------- PMC_USB : (PMC Offset: 0x38) USB Clock Register -------- 
+#define AT91C_PMC_USBS        (0x1 <<  0) // (PMC) USBS
+#define 	AT91C_PMC_USBS_USB_PLLA             (0x0) // (PMC) USB Clock Input is PLLA
+#define 	AT91C_PMC_USBS_USB_UPLL             (0x1) // (PMC) USB Clock Input is UPLL
+#define AT91C_PMC_USBDIV      (0xF <<  8) // (PMC) USBDIV
+#define 	AT91C_PMC_USBDIV_1                    (0x0 <<  8) // (PMC) USB Clock divided by 1
+#define 	AT91C_PMC_USBDIV_2                    (0x1 <<  8) // (PMC) USB Clock divided by 2
+#define 	AT91C_PMC_USBDIV_3                    (0x2 <<  8) // (PMC) USB Clock divided by 3
+#define 	AT91C_PMC_USBDIV_4                    (0x3 <<  8) // (PMC) USB Clock divided by 4
+#define 	AT91C_PMC_USBDIV_5                    (0x4 <<  8) // (PMC) USB Clock divided by 5
+#define 	AT91C_PMC_USBDIV_6                    (0x5 <<  8) // (PMC) USB Clock divided by 6
+#define 	AT91C_PMC_USBDIV_7                    (0x6 <<  8) // (PMC) USB Clock divided by 7
+#define 	AT91C_PMC_USBDIV_8                    (0x7 <<  8) // (PMC) USB Clock divided by 8
+#define 	AT91C_PMC_USBDIV_9                    (0x8 <<  8) // (PMC) USB Clock divided by 9
+#define 	AT91C_PMC_USBDIV_10                   (0x9 <<  8) // (PMC) USB Clock divided by 10
+#define 	AT91C_PMC_USBDIV_11                   (0xA <<  8) // (PMC) USB Clock divided by 11
+#define 	AT91C_PMC_USBDIV_12                   (0xB <<  8) // (PMC) USB Clock divided by 12
+#define 	AT91C_PMC_USBDIV_13                   (0xC <<  8) // (PMC) USB Clock divided by 13
+#define 	AT91C_PMC_USBDIV_14                   (0xD <<  8) // (PMC) USB Clock divided by 14
+#define 	AT91C_PMC_USBDIV_15                   (0xE <<  8) // (PMC) USB Clock divided by 15
+#define 	AT91C_PMC_USBDIV_16                   (0xF <<  8) // (PMC) USB Clock divided by 16
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock 0 Register -------- 
+#define         AT91C_PMC_CLKSRC_SLCKMCK (0x0)
+#define         AT91C_PMC_CLKSRC_MAINCK     (0x1)
+#define         AT91C_PMC_CLKSRC_PCK     (0x2)
+#define         AT91C_PMC_CLKSRC_UPLLCK     (0x3)
+#define         AT91C_PMC_PRESCALER_1 (0x0<<2)
+#define         AT91C_PMC_PRESCALER_2 (0x1<<2)
+#define         AT91C_PMC_PRESCALER_4 (0x2<<2)
+#define         AT91C_PMC_PRESCALER_8 (0x3<<2)
+#define         AT91C_PMC_PRESCALER_16 (0x4<<2)
+#define         AT91C_PMC_PRESCALER_32 (0x5<<2)
+#define         AT91C_PMC_PRESCALER_64 (0x6<<2)
+#define AT91C_PMC_SLCKMCK     (0x1 <<  8) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_SLCKMCK_SLCK                 (0x0 <<  8) // (PMC) Slow Clock selected
+#define 	AT91C_PMC_SLCKMCK_MCK                  (0x1 <<  8) // (PMC) Master Clock selected
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA       (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) Master Clock Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKU       (0x1 <<  6) // (PMC) PLL UTMI Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+// -------- PMC_PLLICPR : (PMC Offset: 0x80) PLL Charge Pump Current Register -------- 
+#define AT91C_PMC_ICPPLLA     (0xF <<  0) // (PMC) PLLA charge pump current setting
+#define 	AT91C_PMC_ICPPLLA_0                    (0x0) // (PMC) 595-800 MHz
+#define 	AT91C_PMC_ICPPLLA_1                    (0x1) // (PMC) 395-600 MHz
+#define AT91C_PMC_REALLOCK    (0x1 <<  7) // (PMC) PLLs use real lock signals when 1
+#define AT91C_PMC_IPLLA       (0xF <<  8) // (PMC) PLLA special setting
+#define 	AT91C_PMC_IPLLA_0                    (0x0 <<  8) // (PMC) Internal LFT
+#define 	AT91C_PMC_IPLLA_1                    (0x1 <<  8) // (PMC) External LFT
+// -------- PMC_FEATURES : (PMC Offset: 0xf8)   -------- 
+#define AT91C_PMC_CFGAHBCLK   (0x1 <<  0) // (PMC) 
+#define 	AT91C_PMC_CFGAHBCLK_0                    (0x0) // (PMC) 
+#define 	AT91C_PMC_CFGAHBCLK_1                    (0x1) // (PMC) 
+#define AT91C_PMC_HCLKEN      (0x1 <<  1) // (PMC) 
+#define 	AT91C_PMC_HCLKEN_0                    (0x0 <<  1) // (PMC) 
+#define 	AT91C_PMC_HCLKEN_1                    (0x1 <<  1) // (PMC) 
+#define AT91C_PMC_PERMCLK     (0x1 <<  2) // (PMC) 
+#define 	AT91C_PMC_PERMCLK_0                    (0x0 <<  2) // (PMC) 
+#define 	AT91C_PMC_PERMCLK_1                    (0x1 <<  2) // (PMC) 
+#define AT91C_PMC_CORE2       (0x1 <<  3) // (PMC) 
+#define 	AT91C_PMC_CORE2_0                    (0x0 <<  3) // (PMC) 
+#define 	AT91C_PMC_CORE2_1                    (0x1 <<  3) // (PMC) 
+#define AT91C_PMC_USBDEVCK    (0x1 <<  4) // (PMC) 
+#define 	AT91C_PMC_USBDEVCK_0                    (0x0 <<  4) // (PMC) 
+#define 	AT91C_PMC_USBDEVCK_1                    (0x1 <<  4) // (PMC) 
+#define AT91C_PMC_USBHOSTCK   (0x1 <<  5) // (PMC) 
+#define 	AT91C_PMC_USBHOSTCK_0                    (0x0 <<  5) // (PMC) 
+#define 	AT91C_PMC_USBHOSTCK_1                    (0x1 <<  5) // (PMC) 
+#define AT91C_PMC_USBOTGCK    (0x1 <<  6) // (PMC) 
+#define 	AT91C_PMC_USBOTGCK_0                    (0x0 <<  6) // (PMC) 
+#define 	AT91C_PMC_USBOTGCK_1                    (0x1 <<  6) // (PMC) 
+#define AT91C_PMC_UHSYNRST    (0x1 <<  7) // (PMC) 
+#define 	AT91C_PMC_UHSYNRST_0                    (0x0 <<  7) // (PMC) 
+#define 	AT91C_PMC_UHSYNRST_1                    (0x1 <<  7) // (PMC) 
+#define AT91C_PMC_UOSYNRST    (0x1 <<  8) // (PMC) 
+#define 	AT91C_PMC_UOSYNRST_0                    (0x0 <<  8) // (PMC) 
+#define 	AT91C_PMC_UOSYNRST_1                    (0x1 <<  8) // (PMC) 
+#define AT91C_PMC_PLLENPOL    (0x1 <<  9) // (PMC) 
+#define 	AT91C_PMC_PLLENPOL_0                    (0x0 <<  9) // (PMC) 
+#define 	AT91C_PMC_PLLENPOL_1                    (0x1 <<  9) // (PMC) 
+#define AT91C_PMC_BIASREG     (0x1 << 10) // (PMC) 
+#define 	AT91C_PMC_BIASREG_0                    (0x0 << 10) // (PMC) 
+#define 	AT91C_PMC_BIASREG_1                    (0x1 << 10) // (PMC) 
+#define AT91C_PMC_OUTPLL      (0x1 << 11) // (PMC) 
+#define 	AT91C_PMC_OUTPLL_0                    (0x0 << 11) // (PMC) 
+#define 	AT91C_PMC_OUTPLL_1                    (0x1 << 11) // (PMC) 
+#define AT91C_PMC_OUTCURR     (0x1 << 12) // (PMC) 
+#define 	AT91C_PMC_OUTCURR_0                    (0x0 << 12) // (PMC) 
+#define 	AT91C_PMC_OUTCURR_1                    (0x1 << 12) // (PMC) 
+#define AT91C_PMC_FWUP        (0x1 << 13) // (PMC) 
+#define 	AT91C_PMC_FWUP_0                    (0x0 << 13) // (PMC) 
+#define 	AT91C_PMC_FWUP_1                    (0x1 << 13) // (PMC) 
+#define AT91C_PMC_SELMAINCLK  (0x1 << 14) // (PMC) 
+#define 	AT91C_PMC_SELMAINCLK_0                    (0x0 << 14) // (PMC) 
+#define 	AT91C_PMC_SELMAINCLK_1                    (0x1 << 14) // (PMC) 
+#define AT91C_PMC_RSTCLKM     (0x1 << 15) // (PMC) 
+#define 	AT91C_PMC_RSTCLKM_0                    (0x0 << 15) // (PMC) 
+#define 	AT91C_PMC_RSTCLKM_1                    (0x1 << 15) // (PMC) 
+#define AT91C_PMC_NB_PERIPH_CLOCK (0xFF << 16) // (PMC) 
+// -------- PMC_VERSION : (PMC Offset: 0xfc)   -------- 
+#define AT91C_PMC_Version     (0xFFFF <<  0) // (PMC) 
+#define 	AT91C_PMC_Version_0                    (0x0) // (PMC) 
+#define 	AT91C_PMC_Version_1                    (0x1) // (PMC) 
+#define AT91C_PMC_MFN         (0x7 << 16) // (PMC) 
+#define 	AT91C_PMC_MFN_0                    (0x0 << 16) // (PMC) 
+#define 	AT91C_PMC_MFN_1                    (0x1 << 16) // (PMC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CKGR {
+	AT91C_REG	 CKGR_UCKR; 	// UTMI Clock Configuration Register
+	AT91C_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91C_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91C_REG	 CKGR_PLLAR; 	// PLL A Register
+} AT91S_CKGR, *AT91PS_CKGR;
+#else
+
+#endif
+// -------- CKGR_UCKR : (CKGR Offset: 0x0) UTMI Clock Configuration Register -------- 
+// -------- CKGR_MOR : (CKGR Offset: 0x4) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (CKGR Offset: 0x8) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLAR : (CKGR Offset: 0xc) PLL A Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RSTC {
+	AT91C_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91C_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91C_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91C_REG	 Reserved0[60]; 	// 
+	AT91C_REG	 RSTC_VER; 	// Version Register
+} AT91S_RSTC, *AT91PS_RSTC;
+#else
+#define RSTC_RCR        (AT91C_CAST(AT91C_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
+#define RSTC_RSR        (AT91C_CAST(AT91C_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
+#define RSTC_RMR        (AT91C_CAST(AT91C_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
+#define RSTC_VER        (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (RSTC_VER) Version Register
+
+#endif
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_ICERST     (0x1 <<  1) // (RSTC) ICE Interface Reset
+#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        (0xA5 << 24) // (RSTC) Password, 8 bits
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Shut Down Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SHDWC {
+	AT91C_REG	 SHDWC_SHCR; 	// Shut Down Control Register
+	AT91C_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
+	AT91C_REG	 SHDWC_SHSR; 	// Shut Down Status Register
+} AT91S_SHDWC, *AT91PS_SHDWC;
+#else
+#define SHDWC_SHCR      (AT91C_CAST(AT91C_REG *) 	0x00000000) // (SHDWC_SHCR) Shut Down Control Register
+#define SHDWC_SHMR      (AT91C_CAST(AT91C_REG *) 	0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
+#define SHDWC_SHSR      (AT91C_CAST(AT91C_REG *) 	0x00000008) // (SHDWC_SHSR) Shut Down Status Register
+
+#endif
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- 
+#define AT91C_SHDWC_SHDW      (0x1 <<  0) // (SHDWC) Processor Reset
+#define AT91C_SHDWC_KEY       (0xA5 << 24) // (SHDWC) Shut down KEY Password
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- 
+#define AT91C_SHDWC_WKMODE0   (0x3 <<  0) // (SHDWC) Wake Up 0 Mode Selection
+#define 	AT91C_SHDWC_WKMODE0_NONE                 (0x0) // (SHDWC) None. No detection is performed on the wake up input.
+#define 	AT91C_SHDWC_WKMODE0_HIGH                 (0x1) // (SHDWC) High Level.
+#define 	AT91C_SHDWC_WKMODE0_LOW                  (0x2) // (SHDWC) Low Level.
+#define 	AT91C_SHDWC_WKMODE0_ANYLEVEL             (0x3) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK0    (0xF <<  4) // (SHDWC) Counter On Wake Up 0
+#define AT91C_SHDWC_WKMODE1   (0x3 <<  8) // (SHDWC) Wake Up 1 Mode Selection
+#define 	AT91C_SHDWC_WKMODE1_NONE                 (0x0 <<  8) // (SHDWC) None. No detection is performed on the wake up input.
+#define 	AT91C_SHDWC_WKMODE1_HIGH                 (0x1 <<  8) // (SHDWC) High Level.
+#define 	AT91C_SHDWC_WKMODE1_LOW                  (0x2 <<  8) // (SHDWC) Low Level.
+#define 	AT91C_SHDWC_WKMODE1_ANYLEVEL             (0x3 <<  8) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK1    (0xF << 12) // (SHDWC) Counter On Wake Up 1
+#define AT91C_SHDWC_RTTWKEN   (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
+#define AT91C_SHDWC_RTCWKEN   (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- 
+#define AT91C_SHDWC_WAKEUP0   (0x1 <<  0) // (SHDWC) Wake Up 0 Status
+#define AT91C_SHDWC_WAKEUP1   (0x1 <<  1) // (SHDWC) Wake Up 1 Status
+#define AT91C_SHDWC_FWKUP     (0x1 <<  2) // (SHDWC) Force Wake Up Status
+#define AT91C_SHDWC_RTTWK     (0x1 << 16) // (SHDWC) Real Time Timer wake Up
+#define AT91C_SHDWC_RTCWK     (0x1 << 17) // (SHDWC) Real Time Clock wake Up
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RTTC {
+	AT91C_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91C_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91C_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91C_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+#else
+#define RTTC_RTMR       (AT91C_CAST(AT91C_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
+#define RTTC_RTAR       (AT91C_CAST(AT91C_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
+#define RTTC_RTVR       (AT91C_CAST(AT91C_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
+#define RTTC_RTSR       (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
+
+#endif
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PITC {
+	AT91C_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91C_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91C_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91C_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+#else
+#define PITC_PIMR       (AT91C_CAST(AT91C_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
+#define PITC_PISR       (AT91C_CAST(AT91C_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
+#define PITC_PIVR       (AT91C_CAST(AT91C_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
+#define PITC_PIIR       (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
+
+#endif
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int)0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_WDTC {
+	AT91C_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91C_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91C_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+#else
+#define WDTC_WDCR       (AT91C_CAST(AT91C_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
+#define WDTC_WDMR       (AT91C_CAST(AT91C_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
+#define WDTC_WDSR       (AT91C_CAST(AT91C_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
+
+#endif
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RTC {
+	AT91C_REG	 RTC_CR; 	// Control Register
+	AT91C_REG	 RTC_MR; 	// Mode Register
+	AT91C_REG	 RTC_TIMR; 	// Time Register
+	AT91C_REG	 RTC_CALR; 	// Calendar Register
+	AT91C_REG	 RTC_TIMALR; 	// Time Alarm Register
+	AT91C_REG	 RTC_CALALR; 	// Calendar Alarm Register
+	AT91C_REG	 RTC_SR; 	// Status Register
+	AT91C_REG	 RTC_SCCR; 	// Status Clear Command Register
+	AT91C_REG	 RTC_IER; 	// Interrupt Enable Register
+	AT91C_REG	 RTC_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 RTC_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 RTC_VER; 	// Valid Entry Register
+} AT91S_RTC, *AT91PS_RTC;
+#else
+#define RTC_CR          (AT91C_CAST(AT91C_REG *) 	0x00000000) // (RTC_CR) Control Register
+#define RTC_MR          (AT91C_CAST(AT91C_REG *) 	0x00000004) // (RTC_MR) Mode Register
+#define RTC_TIMR        (AT91C_CAST(AT91C_REG *) 	0x00000008) // (RTC_TIMR) Time Register
+#define RTC_CALR        (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (RTC_CALR) Calendar Register
+#define RTC_TIMALR      (AT91C_CAST(AT91C_REG *) 	0x00000010) // (RTC_TIMALR) Time Alarm Register
+#define RTC_CALALR      (AT91C_CAST(AT91C_REG *) 	0x00000014) // (RTC_CALALR) Calendar Alarm Register
+#define RTC_SR          (AT91C_CAST(AT91C_REG *) 	0x00000018) // (RTC_SR) Status Register
+#define RTC_SCCR        (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (RTC_SCCR) Status Clear Command Register
+#define RTC_IER         (AT91C_CAST(AT91C_REG *) 	0x00000020) // (RTC_IER) Interrupt Enable Register
+#define RTC_IDR         (AT91C_CAST(AT91C_REG *) 	0x00000024) // (RTC_IDR) Interrupt Disable Register
+#define RTC_IMR         (AT91C_CAST(AT91C_REG *) 	0x00000028) // (RTC_IMR) Interrupt Mask Register
+#define RTC_VER         (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (RTC_VER) Valid Entry Register
+
+#endif
+// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- 
+#define AT91C_RTC_UPDTIM      (0x1 <<  0) // (RTC) Update Request Time Register
+#define AT91C_RTC_UPDCAL      (0x1 <<  1) // (RTC) Update Request Calendar Register
+#define AT91C_RTC_TIMEVSEL    (0x3 <<  8) // (RTC) Time Event Selection
+#define 	AT91C_RTC_TIMEVSEL_MINUTE               (0x0 <<  8) // (RTC) Minute change.
+#define 	AT91C_RTC_TIMEVSEL_HOUR                 (0x1 <<  8) // (RTC) Hour change.
+#define 	AT91C_RTC_TIMEVSEL_DAY24                (0x2 <<  8) // (RTC) Every day at midnight.
+#define 	AT91C_RTC_TIMEVSEL_DAY12                (0x3 <<  8) // (RTC) Every day at noon.
+#define AT91C_RTC_CALEVSEL    (0x3 << 16) // (RTC) Calendar Event Selection
+#define 	AT91C_RTC_CALEVSEL_WEEK                 (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).
+#define 	AT91C_RTC_CALEVSEL_MONTH                (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
+#define 	AT91C_RTC_CALEVSEL_YEAR                 (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).
+// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- 
+#define AT91C_RTC_HRMOD       (0x1 <<  0) // (RTC) 12-24 hour Mode
+// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- 
+#define AT91C_RTC_SEC         (0x7F <<  0) // (RTC) Current Second
+#define AT91C_RTC_MIN         (0x7F <<  8) // (RTC) Current Minute
+#define AT91C_RTC_HOUR        (0x3F << 16) // (RTC) Current Hour
+#define AT91C_RTC_AMPM        (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
+// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- 
+#define AT91C_RTC_CENT        (0x3F <<  0) // (RTC) Current Century
+#define AT91C_RTC_YEAR        (0xFF <<  8) // (RTC) Current Year
+#define AT91C_RTC_MONTH       (0x1F << 16) // (RTC) Current Month
+#define AT91C_RTC_DAY         (0x7 << 21) // (RTC) Current Day
+#define AT91C_RTC_DATE        (0x3F << 24) // (RTC) Current Date
+// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- 
+#define AT91C_RTC_SECEN       (0x1 <<  7) // (RTC) Second Alarm Enable
+#define AT91C_RTC_MINEN       (0x1 << 15) // (RTC) Minute Alarm
+#define AT91C_RTC_HOUREN      (0x1 << 23) // (RTC) Current Hour
+// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- 
+#define AT91C_RTC_MONTHEN     (0x1 << 23) // (RTC) Month Alarm Enable
+#define AT91C_RTC_DATEEN      (0x1 << 31) // (RTC) Date Alarm Enable
+// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- 
+#define AT91C_RTC_ACKUPD      (0x1 <<  0) // (RTC) Acknowledge for Update
+#define AT91C_RTC_ALARM       (0x1 <<  1) // (RTC) Alarm Flag
+#define AT91C_RTC_SECEV       (0x1 <<  2) // (RTC) Second Event
+#define AT91C_RTC_TIMEV       (0x1 <<  3) // (RTC) Time Event
+#define AT91C_RTC_CALEV       (0x1 <<  4) // (RTC) Calendar event
+// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- 
+// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- 
+// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- 
+// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- 
+// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- 
+#define AT91C_RTC_NVTIM       (0x1 <<  0) // (RTC) Non valid Time
+#define AT91C_RTC_NVCAL       (0x1 <<  1) // (RTC) Non valid Calendar
+#define AT91C_RTC_NVTIMALR    (0x1 <<  2) // (RTC) Non valid time Alarm
+#define AT91C_RTC_NVCALALR    (0x1 <<  3) // (RTC) Nonvalid Calendar Alarm
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TC {
+	AT91C_REG	 TC_CCR; 	// Channel Control Register
+	AT91C_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91C_REG	 Reserved0[2]; 	// 
+	AT91C_REG	 TC_CV; 	// Counter Value
+	AT91C_REG	 TC_RA; 	// Register A
+	AT91C_REG	 TC_RB; 	// Register B
+	AT91C_REG	 TC_RC; 	// Register C
+	AT91C_REG	 TC_SR; 	// Status Register
+	AT91C_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91C_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+#else
+#define TC_CCR          (AT91C_CAST(AT91C_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
+#define TC_CMR          (AT91C_CAST(AT91C_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (AT91C_CAST(AT91C_REG *) 	0x00000010) // (TC_CV) Counter Value
+#define TC_RA           (AT91C_CAST(AT91C_REG *) 	0x00000014) // (TC_RA) Register A
+#define TC_RB           (AT91C_CAST(AT91C_REG *) 	0x00000018) // (TC_RB) Register B
+#define TC_RC           (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (TC_RC) Register C
+#define TC_SR           (AT91C_CAST(AT91C_REG *) 	0x00000020) // (TC_SR) Status Register
+#define TC_IER          (AT91C_CAST(AT91C_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
+#define TC_IDR          (AT91C_CAST(AT91C_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
+#define TC_IMR          (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
+
+#endif
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         (0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91C_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91C_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91C_REG	 Reserved2[4]; 	// 
+	AT91C_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91C_REG	 TCB_BMR; 	// TC Block Mode Register
+	AT91C_REG	 Reserved3[9]; 	// 
+	AT91C_REG	 TCB_ADDRSIZE; 	// TC ADDRSIZE REGISTER 
+	AT91C_REG	 TCB_IPNAME1; 	// TC IPNAME1 REGISTER 
+	AT91C_REG	 TCB_IPNAME2; 	// TC IPNAME2 REGISTER 
+	AT91C_REG	 TCB_FEATURES; 	// TC FEATURES REGISTER 
+	AT91C_REG	 TCB_VER; 	//  Version Register
+} AT91S_TCB, *AT91PS_TCB;
+#else
+#define TCB_BCR         (AT91C_CAST(AT91C_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
+#define TCB_BMR         (AT91C_CAST(AT91C_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
+#define TC_ADDRSIZE     (AT91C_CAST(AT91C_REG *) 	0x000000EC) // (TC_ADDRSIZE) TC ADDRSIZE REGISTER 
+#define TC_IPNAME1      (AT91C_CAST(AT91C_REG *) 	0x000000F0) // (TC_IPNAME1) TC IPNAME1 REGISTER 
+#define TC_IPNAME2      (AT91C_CAST(AT91C_REG *) 	0x000000F4) // (TC_IPNAME2) TC IPNAME2 REGISTER 
+#define TC_FEATURES     (AT91C_CAST(AT91C_REG *) 	0x000000F8) // (TC_FEATURES) TC FEATURES REGISTER 
+#define TC_VER          (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (TC_VER)  Version Register
+
+#endif
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MCI {
+	AT91C_REG	 MCI_CR; 	// MCI Control Register
+	AT91C_REG	 MCI_MR; 	// MCI Mode Register
+	AT91C_REG	 MCI_DTOR; 	// MCI Data Timeout Register
+	AT91C_REG	 MCI_SDCR; 	// MCI SD/SDIO Card Register
+	AT91C_REG	 MCI_ARGR; 	// MCI Argument Register
+	AT91C_REG	 MCI_CMDR; 	// MCI Command Register
+	AT91C_REG	 MCI_BLKR; 	// MCI Block Register
+	AT91C_REG	 MCI_CSTOR; 	// MCI Completion Signal Timeout Register
+	AT91C_REG	 MCI_RSPR[4]; 	// MCI Response Register
+	AT91C_REG	 MCI_RDR; 	// MCI Receive Data Register
+	AT91C_REG	 MCI_TDR; 	// MCI Transmit Data Register
+	AT91C_REG	 Reserved0[2]; 	// 
+	AT91C_REG	 MCI_SR; 	// MCI Status Register
+	AT91C_REG	 MCI_IER; 	// MCI Interrupt Enable Register
+	AT91C_REG	 MCI_IDR; 	// MCI Interrupt Disable Register
+	AT91C_REG	 MCI_IMR; 	// MCI Interrupt Mask Register
+	AT91C_REG	 MCI_DMA; 	// MCI DMA Configuration Register
+	AT91C_REG	 MCI_CFG; 	// MCI Configuration Register
+	AT91C_REG	 Reserved1[35]; 	// 
+	AT91C_REG	 MCI_WPCR; 	// MCI Write Protection Control Register
+	AT91C_REG	 MCI_WPSR; 	// MCI Write Protection Status Register
+	AT91C_REG	 MCI_ADDRSIZE; 	// MCI ADDRSIZE REGISTER 
+	AT91C_REG	 MCI_IPNAME1; 	// MCI IPNAME1 REGISTER 
+	AT91C_REG	 MCI_IPNAME2; 	// MCI IPNAME2 REGISTER 
+	AT91C_REG	 MCI_FEATURES; 	// MCI FEATURES REGISTER 
+	AT91C_REG	 MCI_VER; 	// MCI VERSION REGISTER 
+	AT91C_REG	 MCI_RPR; 	// Receive Pointer Register
+	AT91C_REG	 MCI_RCR; 	// Receive Counter Register
+	AT91C_REG	 MCI_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 MCI_TCR; 	// Transmit Counter Register
+	AT91C_REG	 MCI_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 MCI_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 MCI_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 MCI_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 MCI_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 MCI_PTSR; 	// PDC Transfer Status Register
+	AT91C_REG	 Reserved2[54]; 	// 
+	AT91C_REG	 MCI_FIFO; 	// MCI FIFO Aperture Register
+} AT91S_MCI, *AT91PS_MCI;
+#else
+#define MCI_CR          (AT91C_CAST(AT91C_REG *) 	0x00000000) // (MCI_CR) MCI Control Register
+#define MCI_MR          (AT91C_CAST(AT91C_REG *) 	0x00000004) // (MCI_MR) MCI Mode Register
+#define MCI_DTOR        (AT91C_CAST(AT91C_REG *) 	0x00000008) // (MCI_DTOR) MCI Data Timeout Register
+#define MCI_SDCR        (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (MCI_SDCR) MCI SD/SDIO Card Register
+#define MCI_ARGR        (AT91C_CAST(AT91C_REG *) 	0x00000010) // (MCI_ARGR) MCI Argument Register
+#define MCI_CMDR        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (MCI_CMDR) MCI Command Register
+#define MCI_BLKR        (AT91C_CAST(AT91C_REG *) 	0x00000018) // (MCI_BLKR) MCI Block Register
+#define MCI_CSTOR       (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (MCI_CSTOR) MCI Completion Signal Timeout Register
+#define MCI_RSPR        (AT91C_CAST(AT91C_REG *) 	0x00000020) // (MCI_RSPR) MCI Response Register
+#define MCI_RDR         (AT91C_CAST(AT91C_REG *) 	0x00000030) // (MCI_RDR) MCI Receive Data Register
+#define MCI_TDR         (AT91C_CAST(AT91C_REG *) 	0x00000034) // (MCI_TDR) MCI Transmit Data Register
+#define MCI_SR          (AT91C_CAST(AT91C_REG *) 	0x00000040) // (MCI_SR) MCI Status Register
+#define MCI_IER         (AT91C_CAST(AT91C_REG *) 	0x00000044) // (MCI_IER) MCI Interrupt Enable Register
+#define MCI_IDR         (AT91C_CAST(AT91C_REG *) 	0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
+#define MCI_IMR         (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
+#define MCI_DMA         (AT91C_CAST(AT91C_REG *) 	0x00000050) // (MCI_DMA) MCI DMA Configuration Register
+#define MCI_CFG         (AT91C_CAST(AT91C_REG *) 	0x00000054) // (MCI_CFG) MCI Configuration Register
+#define MCI_WPCR        (AT91C_CAST(AT91C_REG *) 	0x000000E4) // (MCI_WPCR) MCI Write Protection Control Register
+#define MCI_WPSR        (AT91C_CAST(AT91C_REG *) 	0x000000E8) // (MCI_WPSR) MCI Write Protection Status Register
+#define MCI_ADDRSIZE    (AT91C_CAST(AT91C_REG *) 	0x000000EC) // (MCI_ADDRSIZE) MCI ADDRSIZE REGISTER 
+#define MCI_IPNAME1     (AT91C_CAST(AT91C_REG *) 	0x000000F0) // (MCI_IPNAME1) MCI IPNAME1 REGISTER 
+#define MCI_IPNAME2     (AT91C_CAST(AT91C_REG *) 	0x000000F4) // (MCI_IPNAME2) MCI IPNAME2 REGISTER 
+#define MCI_FEATURES    (AT91C_CAST(AT91C_REG *) 	0x000000F8) // (MCI_FEATURES) MCI FEATURES REGISTER 
+#define MCI_VER         (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (MCI_VER) MCI VERSION REGISTER 
+#define MCI_FIFO        (AT91C_CAST(AT91C_REG *) 	0x00000200) // (MCI_FIFO) MCI FIFO Aperture Register
+
+#endif
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
+#define AT91C_MCI_MCIEN       (0x1 <<  0) // (MCI) Multimedia Interface Enable
+#define 	AT91C_MCI_MCIEN_0                    (0x0) // (MCI) No effect
+#define 	AT91C_MCI_MCIEN_1                    (0x1) // (MCI) Enable the MultiMedia Interface if MCIDIS is 0
+#define AT91C_MCI_MCIDIS      (0x1 <<  1) // (MCI) Multimedia Interface Disable
+#define 	AT91C_MCI_MCIDIS_0                    (0x0 <<  1) // (MCI) No effect
+#define 	AT91C_MCI_MCIDIS_1                    (0x1 <<  1) // (MCI) Disable the MultiMedia Interface
+#define AT91C_MCI_PWSEN       (0x1 <<  2) // (MCI) Power Save Mode Enable
+#define 	AT91C_MCI_PWSEN_0                    (0x0 <<  2) // (MCI) No effect
+#define 	AT91C_MCI_PWSEN_1                    (0x1 <<  2) // (MCI) Enable the Power-saving mode if PWSDIS is 0.
+#define AT91C_MCI_PWSDIS      (0x1 <<  3) // (MCI) Power Save Mode Disable
+#define 	AT91C_MCI_PWSDIS_0                    (0x0 <<  3) // (MCI) No effect
+#define 	AT91C_MCI_PWSDIS_1                    (0x1 <<  3) // (MCI) Disable the Power-saving mode.
+#define AT91C_MCI_IOWAITEN    (0x1 <<  4) // (MCI) SDIO Read Wait Enable
+#define 	AT91C_MCI_IOWAITEN_0                    (0x0 <<  4) // (MCI) No effect
+#define 	AT91C_MCI_IOWAITEN_1                    (0x1 <<  4) // (MCI) Enables the SDIO Read Wait Operation.
+#define AT91C_MCI_IOWAITDIS   (0x1 <<  5) // (MCI) SDIO Read Wait Disable
+#define 	AT91C_MCI_IOWAITDIS_0                    (0x0 <<  5) // (MCI) No effect
+#define 	AT91C_MCI_IOWAITDIS_1                    (0x1 <<  5) // (MCI) Disables the SDIO Read Wait Operation.
+#define AT91C_MCI_SWRST       (0x1 <<  7) // (MCI) MCI Software reset
+#define 	AT91C_MCI_SWRST_0                    (0x0 <<  7) // (MCI) No effect
+#define 	AT91C_MCI_SWRST_1                    (0x1 <<  7) // (MCI) Resets the MCI
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
+#define AT91C_MCI_CLKDIV      (0xFF <<  0) // (MCI) Clock Divider
+#define AT91C_MCI_PWSDIV      (0x7 <<  8) // (MCI) Power Saving Divider
+#define AT91C_MCI_RDPROOF     (0x1 << 11) // (MCI) Read Proof Enable
+#define 	AT91C_MCI_RDPROOF_DISABLE              (0x0 << 11) // (MCI) Disables Read Proof
+#define 	AT91C_MCI_RDPROOF_ENABLE               (0x1 << 11) // (MCI) Enables Read Proof
+#define AT91C_MCI_WRPROOF     (0x1 << 12) // (MCI) Write Proof Enable
+#define 	AT91C_MCI_WRPROOF_DISABLE              (0x0 << 12) // (MCI) Disables Write Proof
+#define 	AT91C_MCI_WRPROOF_ENABLE               (0x1 << 12) // (MCI) Enables Write Proof
+#define AT91C_MCI_PDCFBYTE    (0x1 << 13) // (MCI) PDC Force Byte Transfer
+#define 	AT91C_MCI_PDCFBYTE_DISABLE              (0x0 << 13) // (MCI) Disables PDC Force Byte Transfer
+#define 	AT91C_MCI_PDCFBYTE_ENABLE               (0x1 << 13) // (MCI) Enables PDC Force Byte Transfer
+#define AT91C_MCI_PDCPADV     (0x1 << 14) // (MCI) PDC Padding Value
+#define AT91C_MCI_PDCMODE     (0x1 << 15) // (MCI) PDC Oriented Mode
+#define 	AT91C_MCI_PDCMODE_DISABLE              (0x0 << 15) // (MCI) Disables PDC Transfer
+#define 	AT91C_MCI_PDCMODE_ENABLE               (0x1 << 15) // (MCI) Enables PDC Transfer
+#define AT91C_MCI_BLKLEN      (0xFFFF << 16) // (MCI) Data Block Length
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
+#define AT91C_MCI_DTOCYC      (0xF <<  0) // (MCI) Data Timeout Cycle Number
+#define AT91C_MCI_DTOMUL      (0x7 <<  4) // (MCI) Data Timeout Multiplier
+#define 	AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1
+#define 	AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16
+#define 	AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128
+#define 	AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256
+#define 	AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024
+#define 	AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096
+#define 	AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536
+#define 	AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
+#define AT91C_MCI_SCDSEL      (0x3 <<  0) // (MCI) SD Card/SDIO Selector
+#define 	AT91C_MCI_SCDSEL_SLOTA                (0x0) // (MCI) Slot A selected
+#define 	AT91C_MCI_SCDSEL_SLOTB                (0x1) // (MCI) Slot B selected
+#define 	AT91C_MCI_SCDSEL_SLOTC                (0x2) // (MCI) Slot C selected
+#define 	AT91C_MCI_SCDSEL_SLOTD                (0x3) // (MCI) Slot D selected
+#define AT91C_MCI_SCDBUS      (0x3 <<  6) // (MCI) SDCard/SDIO Bus Width
+#define 	AT91C_MCI_SCDBUS_1BIT                 (0x0 <<  6) // (MCI) 1-bit data bus
+#define 	AT91C_MCI_SCDBUS_4BITS                (0x2 <<  6) // (MCI) 4-bits data bus
+#define 	AT91C_MCI_SCDBUS_8BITS                (0x3 <<  6) // (MCI) 8-bits data bus
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
+#define AT91C_MCI_CMDNB       (0x3F <<  0) // (MCI) Command Number
+#define AT91C_MCI_RSPTYP      (0x3 <<  6) // (MCI) Response Type
+#define 	AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response
+#define 	AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response
+#define 	AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response
+#define 	AT91C_MCI_RSPTYP_R1B                  (0x3 <<  6) // (MCI) R1b response
+#define AT91C_MCI_SPCMD       (0x7 <<  8) // (MCI) Special CMD
+#define 	AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD
+#define 	AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD
+#define 	AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD
+#define 	AT91C_MCI_SPCMD_CE_ATA               (0x3 <<  8) // (MCI) CE-ATA Completion Signal disable CMD
+#define 	AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command
+#define 	AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response
+#define AT91C_MCI_OPDCMD      (0x1 << 11) // (MCI) Open Drain Command
+#define 	AT91C_MCI_OPDCMD_PUSHPULL             (0x0 << 11) // (MCI) Push/pull command
+#define 	AT91C_MCI_OPDCMD_OPENDRAIN            (0x1 << 11) // (MCI) Open drain command
+#define AT91C_MCI_MAXLAT      (0x1 << 12) // (MCI) Maximum Latency for Command to respond
+#define 	AT91C_MCI_MAXLAT_5                    (0x0 << 12) // (MCI) 5 cycles maximum latency
+#define 	AT91C_MCI_MAXLAT_64                   (0x1 << 12) // (MCI) 64 cycles maximum latency
+#define AT91C_MCI_TRCMD       (0x3 << 16) // (MCI) Transfer CMD
+#define 	AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer
+#define 	AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer
+#define 	AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer
+#define AT91C_MCI_TRDIR       (0x1 << 18) // (MCI) Transfer Direction
+#define 	AT91C_MCI_TRDIR_WRITE                (0x0 << 18) // (MCI) Write
+#define 	AT91C_MCI_TRDIR_READ                 (0x1 << 18) // (MCI) Read
+#define AT91C_MCI_TRTYP       (0x7 << 19) // (MCI) Transfer Type
+#define 	AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
+#define 	AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
+#define 	AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) MMC Stream transfer type
+#define 	AT91C_MCI_TRTYP_SDIO_BYTE            (0x4 << 19) // (MCI) SDIO Byte transfer type
+#define 	AT91C_MCI_TRTYP_SDIO_BLOCK           (0x5 << 19) // (MCI) SDIO Block transfer type
+#define AT91C_MCI_IOSPCMD     (0x3 << 24) // (MCI) SDIO Special Command
+#define 	AT91C_MCI_IOSPCMD_NONE                 (0x0 << 24) // (MCI) NOT a special command
+#define 	AT91C_MCI_IOSPCMD_SUSPEND              (0x1 << 24) // (MCI) SDIO Suspend Command
+#define 	AT91C_MCI_IOSPCMD_RESUME               (0x2 << 24) // (MCI) SDIO Resume Command
+#define AT91C_MCI_ATACS       (0x1 << 26) // (MCI) ATA with command completion signal
+#define 	AT91C_MCI_ATACS_NORMAL               (0x0 << 26) // (MCI) normal operation mode
+#define 	AT91C_MCI_ATACS_COMPLETION           (0x1 << 26) // (MCI) completion signal is expected within MCI_CSTOR
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- 
+#define AT91C_MCI_BCNT        (0xFFFF <<  0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
+// -------- MCI_CSTOR : (MCI Offset: 0x1c) MCI Completion Signal Timeout Register -------- 
+#define AT91C_MCI_CSTOCYC     (0xF <<  0) // (MCI) Completion Signal Timeout Cycle Number
+#define AT91C_MCI_CSTOMUL     (0x7 <<  4) // (MCI) Completion Signal Timeout Multiplier
+#define 	AT91C_MCI_CSTOMUL_1                    (0x0 <<  4) // (MCI) CSTOCYC x 1
+#define 	AT91C_MCI_CSTOMUL_16                   (0x1 <<  4) // (MCI) CSTOCYC x  16
+#define 	AT91C_MCI_CSTOMUL_128                  (0x2 <<  4) // (MCI) CSTOCYC x  128
+#define 	AT91C_MCI_CSTOMUL_256                  (0x3 <<  4) // (MCI) CSTOCYC x  256
+#define 	AT91C_MCI_CSTOMUL_1024                 (0x4 <<  4) // (MCI) CSTOCYC x  1024
+#define 	AT91C_MCI_CSTOMUL_4096                 (0x5 <<  4) // (MCI) CSTOCYC x  4096
+#define 	AT91C_MCI_CSTOMUL_65536                (0x6 <<  4) // (MCI) CSTOCYC x  65536
+#define 	AT91C_MCI_CSTOMUL_1048576              (0x7 <<  4) // (MCI) CSTOCYC x  1048576
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
+#define AT91C_MCI_CMDRDY      (0x1 <<  0) // (MCI) Command Ready flag
+#define AT91C_MCI_RXRDY       (0x1 <<  1) // (MCI) RX Ready flag
+#define AT91C_MCI_TXRDY       (0x1 <<  2) // (MCI) TX Ready flag
+#define AT91C_MCI_BLKE        (0x1 <<  3) // (MCI) Data Block Transfer Ended flag
+#define AT91C_MCI_DTIP        (0x1 <<  4) // (MCI) Data Transfer in Progress flag
+#define AT91C_MCI_NOTBUSY     (0x1 <<  5) // (MCI) Data Line Not Busy flag
+#define AT91C_MCI_ENDRX       (0x1 <<  6) // (MCI) End of RX Buffer flag
+#define AT91C_MCI_ENDTX       (0x1 <<  7) // (MCI) End of TX Buffer flag
+#define AT91C_MCI_SDIOIRQA    (0x1 <<  8) // (MCI) SDIO Interrupt for Slot A
+#define AT91C_MCI_SDIOIRQB    (0x1 <<  9) // (MCI) SDIO Interrupt for Slot B
+#define AT91C_MCI_SDIOIRQC    (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
+#define AT91C_MCI_SDIOIRQD    (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
+#define AT91C_MCI_SDIOWAIT    (0x1 << 12) // (MCI) SDIO Read Wait operation flag
+#define AT91C_MCI_CSRCV       (0x1 << 13) // (MCI) CE-ATA Completion Signal flag
+#define AT91C_MCI_RXBUFF      (0x1 << 14) // (MCI) RX Buffer Full flag
+#define AT91C_MCI_TXBUFE      (0x1 << 15) // (MCI) TX Buffer Empty flag
+#define AT91C_MCI_RINDE       (0x1 << 16) // (MCI) Response Index Error flag
+#define AT91C_MCI_RDIRE       (0x1 << 17) // (MCI) Response Direction Error flag
+#define AT91C_MCI_RCRCE       (0x1 << 18) // (MCI) Response CRC Error flag
+#define AT91C_MCI_RENDE       (0x1 << 19) // (MCI) Response End Bit Error flag
+#define AT91C_MCI_RTOE        (0x1 << 20) // (MCI) Response Time-out Error flag
+#define AT91C_MCI_DCRCE       (0x1 << 21) // (MCI) data CRC Error flag
+#define AT91C_MCI_DTOE        (0x1 << 22) // (MCI) Data timeout Error flag
+#define AT91C_MCI_CSTOE       (0x1 << 23) // (MCI) Completion Signal timeout Error flag
+#define AT91C_MCI_BLKOVRE     (0x1 << 24) // (MCI) DMA Block Overrun Error flag
+#define AT91C_MCI_DMADONE     (0x1 << 25) // (MCI) DMA Transfer Done flag
+#define AT91C_MCI_FIFOEMPTY   (0x1 << 26) // (MCI) FIFO Empty flag
+#define AT91C_MCI_XFRDONE     (0x1 << 27) // (MCI) Transfer Done flag
+#define AT91C_MCI_OVRE        (0x1 << 30) // (MCI) Overrun flag
+#define AT91C_MCI_UNRE        (0x1 << 31) // (MCI) Underrun flag
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
+// -------- MCI_DMA : (MCI Offset: 0x50) MCI DMA Configuration Register -------- 
+#define AT91C_MCI_OFFSET      (0x3 <<  0) // (MCI) DMA Write Buffer Offset
+#define AT91C_MCI_CHKSIZE     (0x7 <<  4) // (MCI) DMA Channel Read/Write Chunk Size
+#define 	AT91C_MCI_CHKSIZE_1                    (0x0 <<  4) // (MCI) Number of data transferred is 1
+#define 	AT91C_MCI_CHKSIZE_4                    (0x1 <<  4) // (MCI) Number of data transferred is 4
+#define 	AT91C_MCI_CHKSIZE_8                    (0x2 <<  4) // (MCI) Number of data transferred is 8
+#define 	AT91C_MCI_CHKSIZE_16                   (0x3 <<  4) // (MCI) Number of data transferred is 16
+#define 	AT91C_MCI_CHKSIZE_32                   (0x4 <<  4) // (MCI) Number of data transferred is 32
+#define AT91C_MCI_DMAEN       (0x1 <<  8) // (MCI) DMA Hardware Handshaking Enable
+#define 	AT91C_MCI_DMAEN_DISABLE              (0x0 <<  8) // (MCI) DMA interface is disabled
+#define 	AT91C_MCI_DMAEN_ENABLE               (0x1 <<  8) // (MCI) DMA interface is enabled
+// -------- MCI_CFG : (MCI Offset: 0x54) MCI Configuration Register -------- 
+#define AT91C_MCI_FIFOMODE    (0x1 <<  0) // (MCI) MCI Internal FIFO Control Mode
+#define 	AT91C_MCI_FIFOMODE_AMOUNTDATA           (0x0) // (MCI) A write transfer starts when a sufficient amount of datas is written into the FIFO
+#define 	AT91C_MCI_FIFOMODE_ONEDATA              (0x1) // (MCI) A write transfer starts as soon as one data is written into the FIFO
+#define AT91C_MCI_FERRCTRL    (0x1 <<  4) // (MCI) Flow Error Flag Reset Control Mode
+#define 	AT91C_MCI_FERRCTRL_RWCMD                (0x0 <<  4) // (MCI) When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag
+#define 	AT91C_MCI_FERRCTRL_READSR               (0x1 <<  4) // (MCI) When an underflow/overflow condition flag is set, a read status resets the flag
+#define AT91C_MCI_HSMODE      (0x1 <<  8) // (MCI) High Speed Mode
+#define 	AT91C_MCI_HSMODE_DISABLE              (0x0 <<  8) // (MCI) Default Bus Timing Mode
+#define 	AT91C_MCI_HSMODE_ENABLE               (0x1 <<  8) // (MCI) High Speed Mode
+#define AT91C_MCI_LSYNC       (0x1 << 12) // (MCI) Synchronize on last block
+#define 	AT91C_MCI_LSYNC_CURRENT              (0x0 << 12) // (MCI) Pending command sent at end of current data block
+#define 	AT91C_MCI_LSYNC_INFINITE             (0x1 << 12) // (MCI) Pending command sent at end of block transfer when transfer length is not infinite
+// -------- MCI_WPCR : (MCI Offset: 0xe4) Write Protection Control Register -------- 
+#define AT91C_MCI_WP_EN       (0x1 <<  0) // (MCI) Write Protection Enable
+#define 	AT91C_MCI_WP_EN_DISABLE              (0x0) // (MCI) Write Operation is disabled (if WP_KEY corresponds)
+#define 	AT91C_MCI_WP_EN_ENABLE               (0x1) // (MCI) Write Operation is enabled (if WP_KEY corresponds)
+#define AT91C_MCI_WP_KEY      (0xFFFFFF <<  8) // (MCI) Write Protection Key
+// -------- MCI_WPSR : (MCI Offset: 0xe8) Write Protection Status Register -------- 
+#define AT91C_MCI_WP_VS       (0xF <<  0) // (MCI) Write Protection Violation Status
+#define 	AT91C_MCI_WP_VS_NO_VIOLATION         (0x0) // (MCI) No Write Protection Violation detected since last read
+#define 	AT91C_MCI_WP_VS_ON_WRITE             (0x1) // (MCI) Write Protection Violation detected since last read
+#define 	AT91C_MCI_WP_VS_ON_RESET             (0x2) // (MCI) Software Reset Violation detected since last read
+#define 	AT91C_MCI_WP_VS_ON_BOTH              (0x3) // (MCI) Write Protection and Software Reset Violation detected since last read
+#define AT91C_MCI_WP_VSRC     (0xF <<  8) // (MCI) Write Protection Violation Source
+#define 	AT91C_MCI_WP_VSRC_NO_VIOLATION         (0x0 <<  8) // (MCI) No Write Protection Violation detected since last read
+#define 	AT91C_MCI_WP_VSRC_MCI_MR               (0x1 <<  8) // (MCI) Write Protection Violation detected on MCI_MR since last read
+#define 	AT91C_MCI_WP_VSRC_MCI_DTOR             (0x2 <<  8) // (MCI) Write Protection Violation detected on MCI_DTOR since last read
+#define 	AT91C_MCI_WP_VSRC_MCI_SDCR             (0x3 <<  8) // (MCI) Write Protection Violation detected on MCI_SDCR since last read
+#define 	AT91C_MCI_WP_VSRC_MCI_CSTOR            (0x4 <<  8) // (MCI) Write Protection Violation detected on MCI_CSTOR since last read
+#define 	AT91C_MCI_WP_VSRC_MCI_DMA              (0x5 <<  8) // (MCI) Write Protection Violation detected on MCI_DMA since last read
+#define 	AT91C_MCI_WP_VSRC_MCI_CFG              (0x6 <<  8) // (MCI) Write Protection Violation detected on MCI_CFG since last read
+#define 	AT91C_MCI_WP_VSRC_MCI_DEL              (0x7 <<  8) // (MCI) Write Protection Violation detected on MCI_DEL since last read
+// -------- MCI_VER : (MCI Offset: 0xfc)  VERSION  Register -------- 
+#define AT91C_MCI_VER         (0xF <<  0) // (MCI)  VERSION  Register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TWI {
+	AT91C_REG	 TWI_CR; 	// Control Register
+	AT91C_REG	 TWI_MMR; 	// Master Mode Register
+	AT91C_REG	 TWI_SMR; 	// Slave Mode Register
+	AT91C_REG	 TWI_IADR; 	// Internal Address Register
+	AT91C_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91C_REG	 Reserved0[3]; 	// 
+	AT91C_REG	 TWI_SR; 	// Status Register
+	AT91C_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91C_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91C_REG	 TWI_THR; 	// Transmit Holding Register
+	AT91C_REG	 Reserved1[45]; 	// 
+	AT91C_REG	 TWI_ADDRSIZE; 	// TWI ADDRSIZE REGISTER 
+	AT91C_REG	 TWI_IPNAME1; 	// TWI IPNAME1 REGISTER 
+	AT91C_REG	 TWI_IPNAME2; 	// TWI IPNAME2 REGISTER 
+	AT91C_REG	 TWI_FEATURES; 	// TWI FEATURES REGISTER 
+	AT91C_REG	 TWI_VER; 	// Version Register
+	AT91C_REG	 TWI_RPR; 	// Receive Pointer Register
+	AT91C_REG	 TWI_RCR; 	// Receive Counter Register
+	AT91C_REG	 TWI_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 TWI_TCR; 	// Transmit Counter Register
+	AT91C_REG	 TWI_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 TWI_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 TWI_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 TWI_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 TWI_PTSR; 	// PDC Transfer Status Register
+} AT91S_TWI, *AT91PS_TWI;
+#else
+#define TWI_CR          (AT91C_CAST(AT91C_REG *) 	0x00000000) // (TWI_CR) Control Register
+#define TWI_MMR         (AT91C_CAST(AT91C_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
+#define TWI_SMR         (AT91C_CAST(AT91C_REG *) 	0x00000008) // (TWI_SMR) Slave Mode Register
+#define TWI_IADR        (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
+#define TWI_CWGR        (AT91C_CAST(AT91C_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
+#define TWI_SR          (AT91C_CAST(AT91C_REG *) 	0x00000020) // (TWI_SR) Status Register
+#define TWI_IER         (AT91C_CAST(AT91C_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
+#define TWI_IDR         (AT91C_CAST(AT91C_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
+#define TWI_IMR         (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
+#define TWI_RHR         (AT91C_CAST(AT91C_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
+#define TWI_THR         (AT91C_CAST(AT91C_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
+#define TWI_ADDRSIZE    (AT91C_CAST(AT91C_REG *) 	0x000000EC) // (TWI_ADDRSIZE) TWI ADDRSIZE REGISTER 
+#define TWI_IPNAME1     (AT91C_CAST(AT91C_REG *) 	0x000000F0) // (TWI_IPNAME1) TWI IPNAME1 REGISTER 
+#define TWI_IPNAME2     (AT91C_CAST(AT91C_REG *) 	0x000000F4) // (TWI_IPNAME2) TWI IPNAME2 REGISTER 
+#define TWI_FEATURES    (AT91C_CAST(AT91C_REG *) 	0x000000F8) // (TWI_FEATURES) TWI FEATURES REGISTER 
+#define TWI_VER         (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (TWI_VER) Version Register
+
+#endif
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN        (0x1 <<  4) // (TWI) TWI Slave mode Enabled
+#define AT91C_TWI_SVDIS       (0x1 <<  5) // (TWI) TWI Slave mode Disabled
+#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internalcf  device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
+#define AT91C_TWI_SADR        (0x7F << 16) // (TWI) Slave Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_TXCOMP_MASTER (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY_MASTER (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_TXRDY_SLAVE (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD      (0x1 <<  3) // (TWI) Slave READ (used only in Slave mode)
+#define AT91C_TWI_SVACC       (0x1 <<  4) // (TWI) Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_GACC        (0x1 <<  5) // (TWI) General Call ACcess (used only in Slave mode)
+#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
+#define AT91C_TWI_NACK_SLAVE  (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_NACK_MASTER (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 <<  9) // (TWI) Arbitration Lost (used only in Multimaster mode)
+#define AT91C_TWI_SCLWS       (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
+#define AT91C_TWI_EOSACC      (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) RXBUFF Interrupt
+#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) TXBUFE Interrupt
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_USART {
+	AT91C_REG	 US_CR; 	// Control Register
+	AT91C_REG	 US_MR; 	// Mode Register
+	AT91C_REG	 US_IER; 	// Interrupt Enable Register
+	AT91C_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 US_CSR; 	// Channel Status Register
+	AT91C_REG	 US_RHR; 	// Receiver Holding Register
+	AT91C_REG	 US_THR; 	// Transmitter Holding Register
+	AT91C_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91C_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91C_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91C_REG	 Reserved0[5]; 	// 
+	AT91C_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91C_REG	 US_NER; 	// Nb Errors Register
+	AT91C_REG	 Reserved1[1]; 	// 
+	AT91C_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91C_REG	 US_MAN; 	// Manchester Encoder Decoder Register
+	AT91C_REG	 Reserved2[38]; 	// 
+	AT91C_REG	 US_ADDRSIZE; 	// US ADDRSIZE REGISTER 
+	AT91C_REG	 US_IPNAME1; 	// US IPNAME1 REGISTER 
+	AT91C_REG	 US_IPNAME2; 	// US IPNAME2 REGISTER 
+	AT91C_REG	 US_FEATURES; 	// US FEATURES REGISTER 
+	AT91C_REG	 US_VER; 	// VERSION Register
+	AT91C_REG	 US_RPR; 	// Receive Pointer Register
+	AT91C_REG	 US_RCR; 	// Receive Counter Register
+	AT91C_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 US_TCR; 	// Transmit Counter Register
+	AT91C_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+#else
+#define US_CR           (AT91C_CAST(AT91C_REG *) 	0x00000000) // (US_CR) Control Register
+#define US_MR           (AT91C_CAST(AT91C_REG *) 	0x00000004) // (US_MR) Mode Register
+#define US_IER          (AT91C_CAST(AT91C_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
+#define US_IDR          (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
+#define US_IMR          (AT91C_CAST(AT91C_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
+#define US_CSR          (AT91C_CAST(AT91C_REG *) 	0x00000014) // (US_CSR) Channel Status Register
+#define US_RHR          (AT91C_CAST(AT91C_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
+#define US_THR          (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
+#define US_BRGR         (AT91C_CAST(AT91C_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
+#define US_RTOR         (AT91C_CAST(AT91C_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
+#define US_TTGR         (AT91C_CAST(AT91C_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
+#define US_FIDI         (AT91C_CAST(AT91C_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
+#define US_NER          (AT91C_CAST(AT91C_REG *) 	0x00000044) // (US_NER) Nb Errors Register
+#define US_IF           (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
+#define US_MAN          (AT91C_CAST(AT91C_REG *) 	0x00000050) // (US_MAN) Manchester Encoder Decoder Register
+#define US_ADDRSIZE     (AT91C_CAST(AT91C_REG *) 	0x000000EC) // (US_ADDRSIZE) US ADDRSIZE REGISTER 
+#define US_IPNAME1      (AT91C_CAST(AT91C_REG *) 	0x000000F0) // (US_IPNAME1) US IPNAME1 REGISTER 
+#define US_IPNAME2      (AT91C_CAST(AT91C_REG *) 	0x000000F4) // (US_IPNAME2) US IPNAME2 REGISTER 
+#define US_FEATURES     (AT91C_CAST(AT91C_REG *) 	0x000000F8) // (US_FEATURES) US FEATURES REGISTER 
+#define US_VER          (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (US_VER) VERSION Register
+
+#endif
+// -------- US_CR : (USART Offset: 0x0)  Control Register -------- 
+#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4)  Mode Register -------- 
+#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock, MCK
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1, MCK/DIV (DIV=8)
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_VAR_SYNC     (0x1 << 22) // (USART) Variable synchronization of command/data sync Start Frame Delimiter
+#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
+#define AT91C_US_MANMODE      (0x1 << 29) // (USART) Manchester Encoder/Decoder Enable
+#define AT91C_US_MODSYNC      (0x1 << 30) // (USART) Manchester Synchronization mode
+#define AT91C_US_ONEBIT       (0x1 << 31) // (USART) Start Frame Delimiter selector
+// -------- US_IER : (USART Offset: 0x8)  Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
+#define AT91C_US_MANE         (0x1 << 20) // (USART) Manchester Error Interrupt
+// -------- US_IDR : (USART Offset: 0xc)  Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10)  Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14)  Channel Status Register -------- 
+#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
+#define AT91C_US_MANERR       (0x1 << 24) // (USART) Manchester Error
+// -------- US_MAN : (USART Offset: 0x50) Manchester Encoder Decoder Register -------- 
+#define AT91C_US_TX_PL        (0xF <<  0) // (USART) Transmitter Preamble Length
+#define AT91C_US_TX_PP        (0x3 <<  8) // (USART) Transmitter Preamble Pattern
+#define 	AT91C_US_TX_PP_ALL_ONE              (0x0 <<  8) // (USART) ALL_ONE
+#define 	AT91C_US_TX_PP_ALL_ZERO             (0x1 <<  8) // (USART) ALL_ZERO
+#define 	AT91C_US_TX_PP_ZERO_ONE             (0x2 <<  8) // (USART) ZERO_ONE
+#define 	AT91C_US_TX_PP_ONE_ZERO             (0x3 <<  8) // (USART) ONE_ZERO
+#define AT91C_US_TX_MPOL      (0x1 << 12) // (USART) Transmitter Manchester Polarity
+#define AT91C_US_RX_PL        (0xF << 16) // (USART) Receiver Preamble Length
+#define AT91C_US_RX_PP        (0x3 << 24) // (USART) Receiver Preamble Pattern detected
+#define 	AT91C_US_RX_PP_ALL_ONE              (0x0 << 24) // (USART) ALL_ONE
+#define 	AT91C_US_RX_PP_ALL_ZERO             (0x1 << 24) // (USART) ALL_ZERO
+#define 	AT91C_US_RX_PP_ZERO_ONE             (0x2 << 24) // (USART) ZERO_ONE
+#define 	AT91C_US_RX_PP_ONE_ZERO             (0x3 << 24) // (USART) ONE_ZERO
+#define AT91C_US_RX_MPOL      (0x1 << 28) // (USART) Receiver Manchester Polarity
+#define AT91C_US_DRIFT        (0x1 << 30) // (USART) Drift compensation
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SSC {
+	AT91C_REG	 SSC_CR; 	// Control Register
+	AT91C_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91C_REG	 Reserved0[2]; 	// 
+	AT91C_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91C_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91C_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91C_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91C_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91C_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91C_REG	 Reserved1[2]; 	// 
+	AT91C_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91C_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91C_REG	 Reserved2[2]; 	// 
+	AT91C_REG	 SSC_SR; 	// Status Register
+	AT91C_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91C_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 Reserved3[39]; 	// 
+	AT91C_REG	 SSC_ADDRSIZE; 	// SSC ADDRSIZE REGISTER 
+	AT91C_REG	 SSC_IPNAME1; 	// SSC IPNAME1 REGISTER 
+	AT91C_REG	 SSC_IPNAME2; 	// SSC IPNAME2 REGISTER 
+	AT91C_REG	 SSC_FEATURES; 	// SSC FEATURES REGISTER 
+	AT91C_REG	 SSC_VER; 	// Version Register
+	AT91C_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91C_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91C_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91C_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+#else
+#define SSC_CR          (AT91C_CAST(AT91C_REG *) 	0x00000000) // (SSC_CR) Control Register
+#define SSC_CMR         (AT91C_CAST(AT91C_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
+#define SSC_RCMR        (AT91C_CAST(AT91C_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
+#define SSC_RFMR        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
+#define SSC_TCMR        (AT91C_CAST(AT91C_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
+#define SSC_TFMR        (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
+#define SSC_RHR         (AT91C_CAST(AT91C_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
+#define SSC_THR         (AT91C_CAST(AT91C_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
+#define SSC_RSHR        (AT91C_CAST(AT91C_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
+#define SSC_TSHR        (AT91C_CAST(AT91C_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
+#define SSC_SR          (AT91C_CAST(AT91C_REG *) 	0x00000040) // (SSC_SR) Status Register
+#define SSC_IER         (AT91C_CAST(AT91C_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
+#define SSC_IDR         (AT91C_CAST(AT91C_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
+#define SSC_IMR         (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
+#define SSC_ADDRSIZE    (AT91C_CAST(AT91C_REG *) 	0x000000EC) // (SSC_ADDRSIZE) SSC ADDRSIZE REGISTER 
+#define SSC_IPNAME1     (AT91C_CAST(AT91C_REG *) 	0x000000F0) // (SSC_IPNAME1) SSC IPNAME1 REGISTER 
+#define SSC_IPNAME2     (AT91C_CAST(AT91C_REG *) 	0x000000F4) // (SSC_IPNAME2) SSC IPNAME2 REGISTER 
+#define SSC_FEATURES    (AT91C_CAST(AT91C_REG *) 	0x000000F8) // (SSC_FEATURES) SSC FEATURES REGISTER 
+#define SSC_VER         (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (SSC_VER) Version Register
+
+#endif
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG         (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
+#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define 	AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STOP        (0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0         (0x1 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_CP1         (0x1 <<  9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PWMC_CH {
+	AT91C_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91C_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91C_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91C_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91C_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91C_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+#else
+#define PWMC_CMR        (AT91C_CAST(AT91C_REG *) 	0x00000000) // (PWMC_CMR) Channel Mode Register
+#define PWMC_CDTYR      (AT91C_CAST(AT91C_REG *) 	0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
+#define PWMC_CPRDR      (AT91C_CAST(AT91C_REG *) 	0x00000008) // (PWMC_CPRDR) Channel Period Register
+#define PWMC_CCNTR      (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (PWMC_CCNTR) Channel Counter Register
+#define PWMC_CUPDR      (AT91C_CAST(AT91C_REG *) 	0x00000010) // (PWMC_CUPDR) Channel Update Register
+#define Reserved        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (Reserved) Reserved
+
+#endif
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       (0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       (0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       (0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       (0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       (0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PWMC {
+	AT91C_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91C_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91C_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91C_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91C_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91C_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91C_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91C_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91C_REG	 Reserved0[55]; 	// 
+	AT91C_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91C_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[32]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+#else
+#define PWMC_MR         (AT91C_CAST(AT91C_REG *) 	0x00000000) // (PWMC_MR) PWMC Mode Register
+#define PWMC_ENA        (AT91C_CAST(AT91C_REG *) 	0x00000004) // (PWMC_ENA) PWMC Enable Register
+#define PWMC_DIS        (AT91C_CAST(AT91C_REG *) 	0x00000008) // (PWMC_DIS) PWMC Disable Register
+#define PWMC_SR         (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (PWMC_SR) PWMC Status Register
+#define PWMC_IER        (AT91C_CAST(AT91C_REG *) 	0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
+#define PWMC_IDR        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
+#define PWMC_IMR        (AT91C_CAST(AT91C_REG *) 	0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
+#define PWMC_ISR        (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
+#define PWMC_VR         (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (PWMC_VR) PWMC Version Register
+
+#endif
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       (0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      (0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      (0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      (0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      (0x1 <<  3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4      (0x1 <<  4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5      (0x1 <<  5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6      (0x1 <<  6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7      (0x1 <<  7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SPI {
+	AT91C_REG	 SPI_CR; 	// Control Register
+	AT91C_REG	 SPI_MR; 	// Mode Register
+	AT91C_REG	 SPI_RDR; 	// Receive Data Register
+	AT91C_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91C_REG	 SPI_SR; 	// Status Register
+	AT91C_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91C_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 Reserved0[4]; 	// 
+	AT91C_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91C_REG	 Reserved1[48]; 	// 
+	AT91C_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91C_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91C_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91C_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+#else
+#define SPI_CR          (AT91C_CAST(AT91C_REG *) 	0x00000000) // (SPI_CR) Control Register
+#define SPI_MR          (AT91C_CAST(AT91C_REG *) 	0x00000004) // (SPI_MR) Mode Register
+#define SPI_RDR         (AT91C_CAST(AT91C_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
+#define SPI_TDR         (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
+#define SPI_SR          (AT91C_CAST(AT91C_REG *) 	0x00000010) // (SPI_SR) Status Register
+#define SPI_IER         (AT91C_CAST(AT91C_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
+#define SPI_IDR         (AT91C_CAST(AT91C_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
+#define SPI_IMR         (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
+#define SPI_CSR         (AT91C_CAST(AT91C_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
+
+#endif
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR TSADC
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TSADC {
+	AT91C_REG	 TSADC_CR; 	// Control Register
+	AT91C_REG	 TSADC_MR; 	// Mode Register
+	AT91C_REG	 TSADC_TRGR; 	// Trigger Register
+	AT91C_REG	 TSADC_TSR; 	// Touch Screen Register
+	AT91C_REG	 TSADC_CHER; 	// Channel Enable Register
+	AT91C_REG	 TSADC_CHDR; 	// Channel Disable Register
+	AT91C_REG	 TSADC_CHSR; 	// Channel Status Register
+	AT91C_REG	 TSADC_SR; 	// Status Register
+	AT91C_REG	 TSADC_LCDR; 	// Last Converted Register
+	AT91C_REG	 TSADC_IER; 	// Interrupt Enable Register
+	AT91C_REG	 TSADC_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 TSADC_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 TSADC_CDR0; 	// Channel Data Register 0
+	AT91C_REG	 TSADC_CDR1; 	// Channel Data Register 1
+	AT91C_REG	 TSADC_CDR2; 	// Channel Data Register 2
+	AT91C_REG	 TSADC_CDR3; 	// Channel Data Register 3
+	AT91C_REG	 TSADC_CDR4; 	// Channel Data Register 4
+	AT91C_REG	 TSADC_CDR5; 	// Channel Data Register 5
+	AT91C_REG	 TSADC_CDR6; 	// Channel Data Register 6
+	AT91C_REG	 TSADC_CDR7; 	// Channel Data Register 7
+    //Cheney change:
+	//AT91C_REG	 Reserved0[44]; 	// 
+    AT91C_REG	 Reserved0[37]; 	// 
+	AT91C_REG	 TSADC_WPMR; 	// Write Protection Mode Register
+	AT91C_REG	 TSADC_WPSR; 	// Write Protection Status Register
+    AT91C_REG	 Reserved1[5]; 	// 
+    
+	AT91C_REG	 TSADC_RPR; 	// Receive Pointer Register
+	AT91C_REG	 TSADC_RCR; 	// Receive Counter Register
+	AT91C_REG	 TSADC_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 TSADC_TCR; 	// Transmit Counter Register
+	AT91C_REG	 TSADC_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 TSADC_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 TSADC_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 TSADC_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 TSADC_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 TSADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_TSADC, *AT91PS_TSADC;
+#else
+#define TSADC_CR        (AT91C_CAST(AT91C_REG *) 	0x00000000) // (TSADC_CR) Control Register
+#define TSADC_MR        (AT91C_CAST(AT91C_REG *) 	0x00000004) // (TSADC_MR) Mode Register
+#define TSADC_TRGR      (AT91C_CAST(AT91C_REG *) 	0x00000008) // (TSADC_TRGR) Trigger Register
+#define TSADC_TSR       (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (TSADC_TSR) Touch Screen Register
+#define TSADC_CHER      (AT91C_CAST(AT91C_REG *) 	0x00000010) // (TSADC_CHER) Channel Enable Register
+#define TSADC_CHDR      (AT91C_CAST(AT91C_REG *) 	0x00000014) // (TSADC_CHDR) Channel Disable Register
+#define TSADC_CHSR      (AT91C_CAST(AT91C_REG *) 	0x00000018) // (TSADC_CHSR) Channel Status Register
+#define TSADC_SR        (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (TSADC_SR) Status Register
+#define TSADC_LCDR      (AT91C_CAST(AT91C_REG *) 	0x00000020) // (TSADC_LCDR) Last Converted Register
+#define TSADC_IER       (AT91C_CAST(AT91C_REG *) 	0x00000024) // (TSADC_IER) Interrupt Enable Register
+#define TSADC_IDR       (AT91C_CAST(AT91C_REG *) 	0x00000028) // (TSADC_IDR) Interrupt Disable Register
+#define TSADC_IMR       (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (TSADC_IMR) Interrupt Mask Register
+#define TSADC_CDR0      (AT91C_CAST(AT91C_REG *) 	0x00000030) // (TSADC_CDR0) Channel Data Register 0
+#define TSADC_CDR1      (AT91C_CAST(AT91C_REG *) 	0x00000034) // (TSADC_CDR1) Channel Data Register 1
+#define TSADC_CDR2      (AT91C_CAST(AT91C_REG *) 	0x00000038) // (TSADC_CDR2) Channel Data Register 2
+#define TSADC_CDR3      (AT91C_CAST(AT91C_REG *) 	0x0000003C) // (TSADC_CDR3) Channel Data Register 3
+#define TSADC_CDR4      (AT91C_CAST(AT91C_REG *) 	0x00000040) // (TSADC_CDR4) Channel Data Register 4
+#define TSADC_CDR5      (AT91C_CAST(AT91C_REG *) 	0x00000044) // (TSADC_CDR5) Channel Data Register 5
+#define TSADC_CDR6      (AT91C_CAST(AT91C_REG *) 	0x00000048) // (TSADC_CDR6) Channel Data Register 6
+#define TSADC_CDR7      (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (TSADC_CDR7) Channel Data Register 7
+
+#endif
+// -------- TSADC_CR : (TSADC Offset: 0x0) Control Register -------- 
+#define AT91C_TSADC_SWRST     (0x1 <<  0) // (TSADC) Software Reset
+#define AT91C_TSADC_START     (0x1 <<  1) // (TSADC) Start Conversion
+// -------- TSADC_MR : (TSADC Offset: 0x4) Mode Register -------- 
+#define AT91C_TSADC_TSAMOD    (0x3 <<  0) // (TSADC) Touch Screen ADC Mode
+#define 	AT91C_TSADC_TSAMOD_ADC_ONLY_MODE        (0x0) // (TSADC) ADC Mode
+#define 	AT91C_TSADC_TSAMOD_TS_ONLY_MODE         (0x1) // (TSADC) Touch Screen Only Mode
+#define AT91C_TSADC_LOWRES    (0x1 <<  4) // (TSADC) ADC Resolution
+#define AT91C_TSADC_SLEEP     (0x1 <<  5) // (TSADC) Sleep Mode
+#define AT91C_TSADC_PENDET    (0x1 <<  6) // (TSADC) Pen Detect Selection
+#define AT91C_TSADC_PRESCAL   (0xFF <<  8) // (TSADC) Prescaler Rate Selection
+#define AT91C_TSADC_STARTUP   (0x7F << 16) // (TSADC) Startup Time
+#define AT91C_TSADC_SHTIM     (0xF << 24) // (TSADC) Sample and Hold Time for ADC Channels
+#define AT91C_TSADC_PENDBC    (0xF << 28) // (TSADC) Pen Detect Debouncing Period
+// -------- TSADC_TRGR : (TSADC Offset: 0x8) Trigger Register -------- 
+#define AT91C_TSADC_TRGMOD    (0x7 <<  0) // (TSADC) Trigger Mode
+#define 	AT91C_TSADC_TRGMOD_NO_TRIGGER           (0x0) // (TSADC) No Trigger
+#define 	AT91C_TSADC_TRGMOD_EXTERNAL_TRIGGER_RE  (0x1) // (TSADC) External Trigger Rising Edge
+#define 	AT91C_TSADC_TRGMOD_EXTERNAL_TRIGGER_FE  (0x2) // (TSADC) External Trigger Falling Edge
+#define 	AT91C_TSADC_TRGMOD_EXTERNAL_TRIGGER_AE  (0x3) // (TSADC) External Trigger Any Edge
+#define 	AT91C_TSADC_TRGMOD_PENDET_TRIGGER       (0x4) // (TSADC) Pen Detect Trigger (only if PENDET is set and in Touch Screen mode only)
+#define 	AT91C_TSADC_TRGMOD_PERIODIC_TRIGGER     (0x5) // (TSADC) Periodic Trigger (wrt TRGPER)
+#define 	AT91C_TSADC_TRGMOD_CONT_TRIGGER         (0x6) // (TSADC) Continuous Trigger
+#define AT91C_TSADC_TRGPER    (0xFFFF << 16) // (TSADC) Trigger Period
+// -------- TSADC_TSR : (TSADC Offset: 0xc) Touch Screen Register -------- 
+#define AT91C_TSADC_TSSHTIM   (0xF << 24) // (TSADC) Sample and Hold Time for Touch Screen Channels
+// -------- TSADC_CHER : (TSADC Offset: 0x10) Channel Enable Register -------- 
+#define AT91C_TSADC_CHENA0    (0x1 <<  0) // (TSADC) Channel 0 Enable
+#define AT91C_TSADC_CHENA1    (0x1 <<  1) // (TSADC) Channel 1 Enable
+#define AT91C_TSADC_CHENA2    (0x1 <<  2) // (TSADC) Channel 2 Enable
+#define AT91C_TSADC_CHENA3    (0x1 <<  3) // (TSADC) Channel 3 Enable
+#define AT91C_TSADC_CHENA4    (0x1 <<  4) // (TSADC) Channel 4 Enable
+#define AT91C_TSADC_CHENA5    (0x1 <<  5) // (TSADC) Channel 5 Enable
+#define AT91C_TSADC_CHENA6    (0x1 <<  6) // (TSADC) Channel 6 Enable
+#define AT91C_TSADC_CHENA7    (0x1 <<  7) // (TSADC) Channel 7 Enable
+// -------- TSADC_CHDR : (TSADC Offset: 0x14) Channel Disable Register -------- 
+#define AT91C_TSADC_CHDIS0    (0x1 <<  0) // (TSADC) Channel 0 Disable
+#define AT91C_TSADC_CHDIS1    (0x1 <<  1) // (TSADC) Channel 1 Disable
+#define AT91C_TSADC_CHDIS2    (0x1 <<  2) // (TSADC) Channel 2 Disable
+#define AT91C_TSADC_CHDIS3    (0x1 <<  3) // (TSADC) Channel 3 Disable
+#define AT91C_TSADC_CHDIS4    (0x1 <<  4) // (TSADC) Channel 4 Disable
+#define AT91C_TSADC_CHDIS5    (0x1 <<  5) // (TSADC) Channel 5 Disable
+#define AT91C_TSADC_CHDIS6    (0x1 <<  6) // (TSADC) Channel 6 Disable
+#define AT91C_TSADC_CHDIS7    (0x1 <<  7) // (TSADC) Channel 7 Disable
+// -------- TSADC_CHSR : (TSADC Offset: 0x18) Channel Status Register -------- 
+#define AT91C_TSADC_CHS0      (0x1 <<  0) // (TSADC) Channel 0 Status
+#define AT91C_TSADC_CHS1      (0x1 <<  1) // (TSADC) Channel 1 Status
+#define AT91C_TSADC_CHS2      (0x1 <<  2) // (TSADC) Channel 2 Status
+#define AT91C_TSADC_CHS3      (0x1 <<  3) // (TSADC) Channel 3 Status
+#define AT91C_TSADC_CHS4      (0x1 <<  4) // (TSADC) Channel 4 Status
+#define AT91C_TSADC_CHS5      (0x1 <<  5) // (TSADC) Channel 5 Status
+#define AT91C_TSADC_CHS6      (0x1 <<  6) // (TSADC) Channel 6 Status
+#define AT91C_TSADC_CHS7      (0x1 <<  7) // (TSADC) Channel 7 Status
+// -------- TSADC_SR : (TSADC Offset: 0x1c) Status Register -------- 
+#define AT91C_TSADC_EOC0      (0x1 <<  0) // (TSADC) Channel 0 End Of Conversion
+#define AT91C_TSADC_EOC1      (0x1 <<  1) // (TSADC) Channel 1 End Of Conversion
+#define AT91C_TSADC_EOC2      (0x1 <<  2) // (TSADC) Channel 2 End Of Conversion
+#define AT91C_TSADC_EOC3      (0x1 <<  3) // (TSADC) Channel 3 End Of Conversion
+#define AT91C_TSADC_EOC4      (0x1 <<  4) // (TSADC) Channel 4 End Of Conversion
+#define AT91C_TSADC_EOC5      (0x1 <<  5) // (TSADC) Channel 5 End Of Conversion
+#define AT91C_TSADC_EOC6      (0x1 <<  6) // (TSADC) Channel 6 End Of Conversion
+#define AT91C_TSADC_EOC7      (0x1 <<  7) // (TSADC) Channel 7 End Of Conversion
+#define AT91C_TSADC_OVRE0     (0x1 <<  8) // (TSADC) Channel 0 Overrun Error
+#define AT91C_TSADC_OVRE1     (0x1 <<  9) // (TSADC) Channel 1 Overrun Error
+#define AT91C_TSADC_OVRE2     (0x1 << 10) // (TSADC) Channel 2 Overrun Error
+#define AT91C_TSADC_OVRE3     (0x1 << 11) // (TSADC) Channel 3 Overrun Error
+#define AT91C_TSADC_OVRE4     (0x1 << 12) // (TSADC) Channel 4 Overrun Error
+#define AT91C_TSADC_OVRE5     (0x1 << 13) // (TSADC) Channel 5 Overrun Error
+#define AT91C_TSADC_OVRE6     (0x1 << 14) // (TSADC) Channel 6 Overrun Error
+#define AT91C_TSADC_OVRE7     (0x1 << 15) // (TSADC) Channel 7 Overrun Error
+#define AT91C_TSADC_DRDY      (0x1 << 16) // (TSADC) Data Ready
+#define AT91C_TSADC_GOVRE     (0x1 << 17) // (TSADC) General Overrun Error
+#define AT91C_TSADC_ENDRX     (0x1 << 18) // (TSADC) End of RX Buffer
+#define AT91C_TSADC_RXBUFF    (0x1 << 19) // (TSADC) RX Buffer Full
+#define AT91C_TSADC_PENCNT    (0x1 << 20) // (TSADC) Pen Contact
+#define AT91C_TSADC_NOCNT     (0x1 << 21) // (TSADC) No Contact
+// -------- TSADC_LCDR : (TSADC Offset: 0x20) Last Converted Data Register -------- 
+#define AT91C_TSADC_LDATA     (0x3FF <<  0) // (TSADC) Last Converted Data
+// -------- TSADC_IER : (TSADC Offset: 0x24) Interrupt Enable Register -------- 
+#define AT91C_TSADC_IENAEOC0  (0x1 <<  0) // (TSADC) Channel 0 End Of Conversion Interrupt Enable
+#define AT91C_TSADC_IENAEOC1  (0x1 <<  1) // (TSADC) Channel 1 End Of Conversion Interrupt Enable
+#define AT91C_TSADC_IENAEOC2  (0x1 <<  2) // (TSADC) Channel 2 End Of Conversion Interrupt Enable
+#define AT91C_TSADC_IENAEOC3  (0x1 <<  3) // (TSADC) Channel 3 End Of Conversion Interrupt Enable
+#define AT91C_TSADC_IENAEOC4  (0x1 <<  4) // (TSADC) Channel 4 End Of Conversion Interrupt Enable
+#define AT91C_TSADC_IENAEOC5  (0x1 <<  5) // (TSADC) Channel 5 End Of Conversion Interrupt Enable
+#define AT91C_TSADC_IENAEOC6  (0x1 <<  6) // (TSADC) Channel 6 End Of Conversion Interrupt Enable
+#define AT91C_TSADC_IENAEOC7  (0x1 <<  7) // (TSADC) Channel 7 End Of Conversion Interrupt Enable
+#define AT91C_TSADC_IENAOVRE0 (0x1 <<  8) // (TSADC) Channel 0 Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENAOVRE1 (0x1 <<  9) // (TSADC) Channel 1 Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENAOVRE2 (0x1 << 10) // (TSADC) Channel 2 Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENAOVRE3 (0x1 << 11) // (TSADC) Channel 3 Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENAOVRE4 (0x1 << 12) // (TSADC) Channel 4 Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENAOVRE5 (0x1 << 13) // (TSADC) Channel 5 Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENAOVRE6 (0x1 << 14) // (TSADC) Channel 6 Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENAOVRE7 (0x1 << 15) // (TSADC) Channel 7 Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENADRDY  (0x1 << 16) // (TSADC) Data Ready Interrupt Enable
+#define AT91C_TSADC_IENAGOVRE (0x1 << 17) // (TSADC) General Overrun Error Interrupt Enable
+#define AT91C_TSADC_IENAENDRX (0x1 << 18) // (TSADC) End of RX Buffer Interrupt Enable
+#define AT91C_TSADC_IENARXBUFF (0x1 << 19) // (TSADC) RX Buffer Full Interrupt Enable
+#define AT91C_TSADC_IENAPENCNT (0x1 << 20) // (TSADC) Pen Contact Interrupt Enable
+#define AT91C_TSADC_IENANOCNT (0x1 << 21) // (TSADC) No Contact Interrupt Enable
+// -------- TSADC_IDR : (TSADC Offset: 0x28) Interrupt Disable Register -------- 
+#define AT91C_TSADC_IDISEOC0  (0x1 <<  0) // (TSADC) Channel 0 End Of Conversion Interrupt Disable
+#define AT91C_TSADC_IDISEOC1  (0x1 <<  1) // (TSADC) Channel 1 End Of Conversion Interrupt Disable
+#define AT91C_TSADC_IDISEOC2  (0x1 <<  2) // (TSADC) Channel 2 End Of Conversion Interrupt Disable
+#define AT91C_TSADC_IDISEOC3  (0x1 <<  3) // (TSADC) Channel 3 End Of Conversion Interrupt Disable
+#define AT91C_TSADC_IDISEOC4  (0x1 <<  4) // (TSADC) Channel 4 End Of Conversion Interrupt Disable
+#define AT91C_TSADC_IDISEOC5  (0x1 <<  5) // (TSADC) Channel 5 End Of Conversion Interrupt Disable
+#define AT91C_TSADC_IDISEOC6  (0x1 <<  6) // (TSADC) Channel 6 End Of Conversion Interrupt Disable
+#define AT91C_TSADC_IDISEOC7  (0x1 <<  7) // (TSADC) Channel 7 End Of Conversion Interrupt Disable
+#define AT91C_TSADC_IDISOVRE0 (0x1 <<  8) // (TSADC) Channel 0 Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISOVRE1 (0x1 <<  9) // (TSADC) Channel 1 Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISOVRE2 (0x1 << 10) // (TSADC) Channel 2 Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISOVRE3 (0x1 << 11) // (TSADC) Channel 3 Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISOVRE4 (0x1 << 12) // (TSADC) Channel 4 Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISOVRE5 (0x1 << 13) // (TSADC) Channel 5 Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISOVRE6 (0x1 << 14) // (TSADC) Channel 6 Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISOVRE7 (0x1 << 15) // (TSADC) Channel 7 Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISDRDY  (0x1 << 16) // (TSADC) Data Ready Interrupt Disable
+#define AT91C_TSADC_IDISGOVRE (0x1 << 17) // (TSADC) General Overrun Error Interrupt Disable
+#define AT91C_TSADC_IDISENDRX (0x1 << 18) // (TSADC) End of RX Buffer Interrupt Disable
+#define AT91C_TSADC_IDISRXBUFF (0x1 << 19) // (TSADC) RX Buffer Full Interrupt Disable
+#define AT91C_TSADC_IDISPENCNT (0x1 << 20) // (TSADC) Pen Contact Interrupt Disable
+#define AT91C_TSADC_IDISNOCNT (0x1 << 21) // (TSADC) No Contact Interrupt Disable
+// -------- TSADC_IMR : (TSADC Offset: 0x2c) Interrupt Mask Register -------- 
+#define AT91C_TSADC_IMSKEOC0  (0x1 <<  0) // (TSADC) Channel 0 End Of Conversion Interrupt Mask
+#define AT91C_TSADC_IMSKEOC1  (0x1 <<  1) // (TSADC) Channel 1 End Of Conversion Interrupt Mask
+#define AT91C_TSADC_IMSKEOC2  (0x1 <<  2) // (TSADC) Channel 2 End Of Conversion Interrupt Mask
+#define AT91C_TSADC_IMSKEOC3  (0x1 <<  3) // (TSADC) Channel 3 End Of Conversion Interrupt Mask
+#define AT91C_TSADC_IMSKEOC4  (0x1 <<  4) // (TSADC) Channel 4 End Of Conversion Interrupt Mask
+#define AT91C_TSADC_IMSKEOC5  (0x1 <<  5) // (TSADC) Channel 5 End Of Conversion Interrupt Mask
+#define AT91C_TSADC_IMSKEOC6  (0x1 <<  6) // (TSADC) Channel 6 End Of Conversion Interrupt Mask
+#define AT91C_TSADC_IMSKEOC7  (0x1 <<  7) // (TSADC) Channel 7 End Of Conversion Interrupt Mask
+#define AT91C_TSADC_IMSKOVRE0 (0x1 <<  8) // (TSADC) Channel 0 Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKOVRE1 (0x1 <<  9) // (TSADC) Channel 1 Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKOVRE2 (0x1 << 10) // (TSADC) Channel 2 Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKOVRE3 (0x1 << 11) // (TSADC) Channel 3 Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKOVRE4 (0x1 << 12) // (TSADC) Channel 4 Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKOVRE5 (0x1 << 13) // (TSADC) Channel 5 Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKOVRE6 (0x1 << 14) // (TSADC) Channel 6 Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKOVRE7 (0x1 << 15) // (TSADC) Channel 7 Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKDRDY  (0x1 << 16) // (TSADC) Data Ready Interrupt Mask
+#define AT91C_TSADC_IMSKGOVRE (0x1 << 17) // (TSADC) General Overrun Error Interrupt Mask
+#define AT91C_TSADC_IMSKENDRX (0x1 << 18) // (TSADC) End of RX Buffer Interrupt Mask
+#define AT91C_TSADC_IMSKRXBUFF (0x1 << 19) // (TSADC) RX Buffer Full Interrupt Mask
+#define AT91C_TSADC_IMSKPENCNT (0x1 << 20) // (TSADC) Pen Contact Interrupt Mask
+#define AT91C_TSADC_IMSKNOCNT (0x1 << 21) // (TSADC) No Contact Interrupt Mask
+// -------- TSADC_CDR0 : (TSADC Offset: 0x30) Channel 0 Data Register -------- 
+#define AT91C_TSADC_DATA0     (0x3FF <<  0) // (TSADC) Channel 0 Data
+// -------- TSADC_CDR1 : (TSADC Offset: 0x34) Channel 1 Data Register -------- 
+#define AT91C_TSADC_DATA1     (0x3FF <<  0) // (TSADC) Channel 1 Data
+// -------- TSADC_CDR2 : (TSADC Offset: 0x38) Channel 2 Data Register -------- 
+#define AT91C_TSADC_DATA2     (0x3FF <<  0) // (TSADC) Channel 2 Data
+// -------- TSADC_CDR3 : (TSADC Offset: 0x3c) Channel 3 Data Register -------- 
+#define AT91C_TSADC_DATA3     (0x3FF <<  0) // (TSADC) Channel 3 Data
+// -------- TSADC_CDR4 : (TSADC Offset: 0x40) Channel 4 Data Register -------- 
+#define AT91C_TSADC_DATA4     (0x3FF <<  0) // (TSADC) Channel 4 Data
+// -------- TSADC_CDR5 : (TSADC Offset: 0x44) Channel 5 Data Register -------- 
+#define AT91C_TSADC_DATA5     (0x3FF <<  0) // (TSADC) Channel 5 Data
+// -------- TSADC_CDR6 : (TSADC Offset: 0x48) Channel 6 Data Register -------- 
+#define AT91C_TSADC_DATA6     (0x3FF <<  0) // (TSADC) Channel 6 Data
+// -------- TSADC_CDR7 : (TSADC Offset: 0x4c) Channel 7 Data Register -------- 
+#define AT91C_TSADC_DATA7     (0x3FF <<  0) // (TSADC) Channel 7 Data
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR UDPHS Enpoint FIFO data register
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDPHS_EPTFIFO {
+	AT91C_REG	 UDPHS_READEPT0[16384]; 	// FIFO Endpoint Data Register 0
+	AT91C_REG	 UDPHS_READEPT1[16384]; 	// FIFO Endpoint Data Register 1
+	AT91C_REG	 UDPHS_READEPT2[16384]; 	// FIFO Endpoint Data Register 2
+	AT91C_REG	 UDPHS_READEPT3[16384]; 	// FIFO Endpoint Data Register 3
+	AT91C_REG	 UDPHS_READEPT4[16384]; 	// FIFO Endpoint Data Register 4
+	AT91C_REG	 UDPHS_READEPT5[16384]; 	// FIFO Endpoint Data Register 5
+	AT91C_REG	 UDPHS_READEPT6[16384]; 	// FIFO Endpoint Data Register 6
+} AT91S_UDPHS_EPTFIFO, *AT91PS_UDPHS_EPTFIFO;
+#else
+#define UDPHS_READEPT0  (AT91C_CAST(AT91C_REG *) 	0x00000000) // (UDPHS_READEPT0) FIFO Endpoint Data Register 0
+#define UDPHS_READEPT1  (AT91C_CAST(AT91C_REG *) 	0x00010000) // (UDPHS_READEPT1) FIFO Endpoint Data Register 1
+#define UDPHS_READEPT2  (AT91C_CAST(AT91C_REG *) 	0x00020000) // (UDPHS_READEPT2) FIFO Endpoint Data Register 2
+#define UDPHS_READEPT3  (AT91C_CAST(AT91C_REG *) 	0x00030000) // (UDPHS_READEPT3) FIFO Endpoint Data Register 3
+#define UDPHS_READEPT4  (AT91C_CAST(AT91C_REG *) 	0x00040000) // (UDPHS_READEPT4) FIFO Endpoint Data Register 4
+#define UDPHS_READEPT5  (AT91C_CAST(AT91C_REG *) 	0x00050000) // (UDPHS_READEPT5) FIFO Endpoint Data Register 5
+#define UDPHS_READEPT6  (AT91C_CAST(AT91C_REG *) 	0x00060000) // (UDPHS_READEPT6) FIFO Endpoint Data Register 6
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR UDPHS Endpoint struct
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDPHS_EPT {
+	AT91C_REG	 UDPHS_EPTCFG; 	// UDPHS Endpoint Config Register
+	AT91C_REG	 UDPHS_EPTCTLENB; 	// UDPHS Endpoint Control Enable Register
+	AT91C_REG	 UDPHS_EPTCTLDIS; 	// UDPHS Endpoint Control Disable Register
+	AT91C_REG	 UDPHS_EPTCTL; 	// UDPHS Endpoint Control Register
+	AT91C_REG	 Reserved0[1]; 	// 
+	AT91C_REG	 UDPHS_EPTSETSTA; 	// UDPHS Endpoint Set Status Register
+	AT91C_REG	 UDPHS_EPTCLRSTA; 	// UDPHS Endpoint Clear Status Register
+	AT91C_REG	 UDPHS_EPTSTA; 	// UDPHS Endpoint Status Register
+} AT91S_UDPHS_EPT, *AT91PS_UDPHS_EPT;
+#else
+#define UDPHS_EPTCFG    (AT91C_CAST(AT91C_REG *) 	0x00000000) // (UDPHS_EPTCFG) UDPHS Endpoint Config Register
+#define UDPHS_EPTCTLENB (AT91C_CAST(AT91C_REG *) 	0x00000004) // (UDPHS_EPTCTLENB) UDPHS Endpoint Control Enable Register
+#define UDPHS_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 	0x00000008) // (UDPHS_EPTCTLDIS) UDPHS Endpoint Control Disable Register
+#define UDPHS_EPTCTL    (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (UDPHS_EPTCTL) UDPHS Endpoint Control Register
+#define UDPHS_EPTSETSTA (AT91C_CAST(AT91C_REG *) 	0x00000014) // (UDPHS_EPTSETSTA) UDPHS Endpoint Set Status Register
+#define UDPHS_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 	0x00000018) // (UDPHS_EPTCLRSTA) UDPHS Endpoint Clear Status Register
+#define UDPHS_EPTSTA    (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (UDPHS_EPTSTA) UDPHS Endpoint Status Register
+
+#endif
+// -------- UDPHS_EPTCFG : (UDPHS_EPT Offset: 0x0) UDPHS Endpoint Config Register -------- 
+#define AT91C_UDPHS_EPT_SIZE  (0x7 <<  0) // (UDPHS_EPT) Endpoint Size
+#define 	AT91C_UDPHS_EPT_SIZE_8                    (0x0) // (UDPHS_EPT)    8 bytes
+#define 	AT91C_UDPHS_EPT_SIZE_16                   (0x1) // (UDPHS_EPT)   16 bytes
+#define 	AT91C_UDPHS_EPT_SIZE_32                   (0x2) // (UDPHS_EPT)   32 bytes
+#define 	AT91C_UDPHS_EPT_SIZE_64                   (0x3) // (UDPHS_EPT)   64 bytes
+#define 	AT91C_UDPHS_EPT_SIZE_128                  (0x4) // (UDPHS_EPT)  128 bytes
+#define 	AT91C_UDPHS_EPT_SIZE_256                  (0x5) // (UDPHS_EPT)  256 bytes (if possible)
+#define 	AT91C_UDPHS_EPT_SIZE_512                  (0x6) // (UDPHS_EPT)  512 bytes (if possible)
+#define 	AT91C_UDPHS_EPT_SIZE_1024                 (0x7) // (UDPHS_EPT) 1024 bytes (if possible)
+#define AT91C_UDPHS_EPT_DIR   (0x1 <<  3) // (UDPHS_EPT) Endpoint Direction 0:OUT, 1:IN
+#define 	AT91C_UDPHS_EPT_DIR_OUT                  (0x0 <<  3) // (UDPHS_EPT) Direction OUT
+#define 	AT91C_UDPHS_EPT_DIR_IN                   (0x1 <<  3) // (UDPHS_EPT) Direction IN
+#define AT91C_UDPHS_EPT_TYPE  (0x3 <<  4) // (UDPHS_EPT) Endpoint Type
+#define 	AT91C_UDPHS_EPT_TYPE_CTL_EPT              (0x0 <<  4) // (UDPHS_EPT) Control endpoint
+#define 	AT91C_UDPHS_EPT_TYPE_ISO_EPT              (0x1 <<  4) // (UDPHS_EPT) Isochronous endpoint
+#define 	AT91C_UDPHS_EPT_TYPE_BUL_EPT              (0x2 <<  4) // (UDPHS_EPT) Bulk endpoint
+#define 	AT91C_UDPHS_EPT_TYPE_INT_EPT              (0x3 <<  4) // (UDPHS_EPT) Interrupt endpoint
+#define AT91C_UDPHS_BK_NUMBER (0x3 <<  6) // (UDPHS_EPT) Number of Banks
+#define 	AT91C_UDPHS_BK_NUMBER_0                    (0x0 <<  6) // (UDPHS_EPT) Zero Bank, the EndPoint is not mapped in memory
+#define 	AT91C_UDPHS_BK_NUMBER_1                    (0x1 <<  6) // (UDPHS_EPT) One Bank (Bank0)
+#define 	AT91C_UDPHS_BK_NUMBER_2                    (0x2 <<  6) // (UDPHS_EPT) Double bank (Ping-Pong : Bank0 / Bank1)
+#define 	AT91C_UDPHS_BK_NUMBER_3                    (0x3 <<  6) // (UDPHS_EPT) Triple Bank (Bank0 / Bank1 / Bank2) (if possible)
+#define AT91C_UDPHS_NB_TRANS  (0x3 <<  8) // (UDPHS_EPT) Number Of Transaction per Micro-Frame (High-Bandwidth iso only)
+#define AT91C_UDPHS_EPT_MAPD  (0x1 << 31) // (UDPHS_EPT) Endpoint Mapped (read only
+// -------- UDPHS_EPTCTLENB : (UDPHS_EPT Offset: 0x4) UDPHS Endpoint Control Enable Register -------- 
+#define AT91C_UDPHS_EPT_ENABL (0x1 <<  0) // (UDPHS_EPT) Endpoint Enable
+#define AT91C_UDPHS_AUTO_VALID (0x1 <<  1) // (UDPHS_EPT) Packet Auto-Valid Enable/Disable
+#define AT91C_UDPHS_INTDIS_DMA (0x1 <<  3) // (UDPHS_EPT) Endpoint Interrupts DMA Request Enable/Disable
+#define AT91C_UDPHS_NYET_DIS  (0x1 <<  4) // (UDPHS_EPT) NYET Enable/Disable
+#define AT91C_UDPHS_DATAX_RX  (0x1 <<  6) // (UDPHS_EPT) DATAx Interrupt Enable/Disable
+#define AT91C_UDPHS_MDATA_RX  (0x1 <<  7) // (UDPHS_EPT) MDATA Interrupt Enabled/Disable
+#define AT91C_UDPHS_ERR_OVFLW (0x1 <<  8) // (UDPHS_EPT) OverFlow Error Interrupt Enable/Disable/Status
+#define AT91C_UDPHS_RX_BK_RDY (0x1 <<  9) // (UDPHS_EPT) Received OUT Data
+#define AT91C_UDPHS_TX_COMPLT (0x1 << 10) // (UDPHS_EPT) Transmitted IN Data Complete Interrupt Enable/Disable or Transmitted IN Data Complete (clear)
+#define AT91C_UDPHS_ERR_TRANS (0x1 << 11) // (UDPHS_EPT) Transaction Error Interrupt Enable/Disable
+#define AT91C_UDPHS_TX_PK_RDY (0x1 << 11) // (UDPHS_EPT) TX Packet Ready Interrupt Enable/Disable
+#define AT91C_UDPHS_RX_SETUP  (0x1 << 12) // (UDPHS_EPT) Received SETUP Interrupt Enable/Disable
+#define AT91C_UDPHS_ERR_FL_ISO (0x1 << 12) // (UDPHS_EPT) Error Flow Clear/Interrupt Enable/Disable
+#define AT91C_UDPHS_STALL_SNT (0x1 << 13) // (UDPHS_EPT) Stall Sent Clear
+#define AT91C_UDPHS_ERR_CRISO (0x1 << 13) // (UDPHS_EPT) CRC error / Error NB Trans / Interrupt Enable/Disable
+#define AT91C_UDPHS_NAK_IN    (0x1 << 14) // (UDPHS_EPT) NAKIN ERROR FLUSH / Clear / Interrupt Enable/Disable
+#define AT91C_UDPHS_NAK_OUT   (0x1 << 15) // (UDPHS_EPT) NAKOUT / Clear / Interrupt Enable/Disable
+#define AT91C_UDPHS_BUSY_BANK (0x1 << 18) // (UDPHS_EPT) Busy Bank Interrupt Enable/Disable
+#define AT91C_UDPHS_SHRT_PCKT (0x1 << 31) // (UDPHS_EPT) Short Packet / Interrupt Enable/Disable
+// -------- UDPHS_EPTCTLDIS : (UDPHS_EPT Offset: 0x8) UDPHS Endpoint Control Disable Register -------- 
+#define AT91C_UDPHS_EPT_DISABL (0x1 <<  0) // (UDPHS_EPT) Endpoint Disable
+// -------- UDPHS_EPTCTL : (UDPHS_EPT Offset: 0xc) UDPHS Endpoint Control Register -------- 
+// -------- UDPHS_EPTSETSTA : (UDPHS_EPT Offset: 0x14) UDPHS Endpoint Set Status Register -------- 
+#define AT91C_UDPHS_FRCESTALL (0x1 <<  5) // (UDPHS_EPT) Stall Handshake Request Set/Clear/Status
+#define AT91C_UDPHS_KILL_BANK (0x1 <<  9) // (UDPHS_EPT) KILL Bank
+// -------- UDPHS_EPTCLRSTA : (UDPHS_EPT Offset: 0x18) UDPHS Endpoint Clear Status Register -------- 
+#define AT91C_UDPHS_TOGGLESQ  (0x1 <<  6) // (UDPHS_EPT) Data Toggle Clear
+// -------- UDPHS_EPTSTA : (UDPHS_EPT Offset: 0x1c) UDPHS Endpoint Status Register -------- 
+#define AT91C_UDPHS_TOGGLESQ_STA (0x3 <<  6) // (UDPHS_EPT) Toggle Sequencing
+#define 	AT91C_UDPHS_TOGGLESQ_STA_00                   (0x0 <<  6) // (UDPHS_EPT) Data0
+#define 	AT91C_UDPHS_TOGGLESQ_STA_01                   (0x1 <<  6) // (UDPHS_EPT) Data1
+#define 	AT91C_UDPHS_TOGGLESQ_STA_10                   (0x2 <<  6) // (UDPHS_EPT) Data2 (only for High-Bandwidth Isochronous EndPoint)
+#define 	AT91C_UDPHS_TOGGLESQ_STA_11                   (0x3 <<  6) // (UDPHS_EPT) MData (only for High-Bandwidth Isochronous EndPoint)
+#define AT91C_UDPHS_CONTROL_DIR (0x3 << 16) // (UDPHS_EPT) 
+#define 	AT91C_UDPHS_CONTROL_DIR_00                   (0x0 << 16) // (UDPHS_EPT) Bank 0
+#define 	AT91C_UDPHS_CONTROL_DIR_01                   (0x1 << 16) // (UDPHS_EPT) Bank 1
+#define 	AT91C_UDPHS_CONTROL_DIR_10                   (0x2 << 16) // (UDPHS_EPT) Bank 2
+#define 	AT91C_UDPHS_CONTROL_DIR_11                   (0x3 << 16) // (UDPHS_EPT) Invalid
+#define AT91C_UDPHS_CURRENT_BANK (0x3 << 16) // (UDPHS_EPT) 
+#define 	AT91C_UDPHS_CURRENT_BANK_00                   (0x0 << 16) // (UDPHS_EPT) Bank 0
+#define 	AT91C_UDPHS_CURRENT_BANK_01                   (0x1 << 16) // (UDPHS_EPT) Bank 1
+#define 	AT91C_UDPHS_CURRENT_BANK_10                   (0x2 << 16) // (UDPHS_EPT) Bank 2
+#define 	AT91C_UDPHS_CURRENT_BANK_11                   (0x3 << 16) // (UDPHS_EPT) Invalid
+#define AT91C_UDPHS_BUSY_BANK_STA (0x3 << 18) // (UDPHS_EPT) Busy Bank Number
+#define 	AT91C_UDPHS_BUSY_BANK_STA_00                   (0x0 << 18) // (UDPHS_EPT) All banks are free
+#define 	AT91C_UDPHS_BUSY_BANK_STA_01                   (0x1 << 18) // (UDPHS_EPT) 1 busy bank
+#define 	AT91C_UDPHS_BUSY_BANK_STA_10                   (0x2 << 18) // (UDPHS_EPT) 2 busy banks
+#define 	AT91C_UDPHS_BUSY_BANK_STA_11                   (0x3 << 18) // (UDPHS_EPT) 3 busy banks (if possible)
+#define AT91C_UDPHS_BYTE_COUNT (0x7FF << 20) // (UDPHS_EPT) UDPHS Byte Count
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR UDPHS DMA struct
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDPHS_DMA {
+	AT91C_REG	 UDPHS_DMANXTDSC; 	// UDPHS DMA Channel Next Descriptor Address
+	AT91C_REG	 UDPHS_DMAADDRESS; 	// UDPHS DMA Channel Address Register
+	AT91C_REG	 UDPHS_DMACONTROL; 	// UDPHS DMA Channel Control Register
+	AT91C_REG	 UDPHS_DMASTATUS; 	// UDPHS DMA Channel Status Register
+} AT91S_UDPHS_DMA, *AT91PS_UDPHS_DMA;
+#else
+#define UDPHS_DMANXTDSC (AT91C_CAST(AT91C_REG *) 	0x00000000) // (UDPHS_DMANXTDSC) UDPHS DMA Channel Next Descriptor Address
+#define UDPHS_DMAADDRESS (AT91C_CAST(AT91C_REG *) 	0x00000004) // (UDPHS_DMAADDRESS) UDPHS DMA Channel Address Register
+#define UDPHS_DMACONTROL (AT91C_CAST(AT91C_REG *) 	0x00000008) // (UDPHS_DMACONTROL) UDPHS DMA Channel Control Register
+#define UDPHS_DMASTATUS (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (UDPHS_DMASTATUS) UDPHS DMA Channel Status Register
+
+#endif
+// -------- UDPHS_DMANXTDSC : (UDPHS_DMA Offset: 0x0) UDPHS DMA Next Descriptor Address Register -------- 
+#define AT91C_UDPHS_NXT_DSC_ADD (0xFFFFFFF <<  4) // (UDPHS_DMA) next Channel Descriptor
+// -------- UDPHS_DMAADDRESS : (UDPHS_DMA Offset: 0x4) UDPHS DMA Channel Address Register -------- 
+#define AT91C_UDPHS_BUFF_ADD  (0x0 <<  0) // (UDPHS_DMA) starting address of a DMA Channel transfer
+// -------- UDPHS_DMACONTROL : (UDPHS_DMA Offset: 0x8) UDPHS DMA Channel Control Register -------- 
+#define AT91C_UDPHS_CHANN_ENB (0x1 <<  0) // (UDPHS_DMA) Channel Enabled
+#define AT91C_UDPHS_LDNXT_DSC (0x1 <<  1) // (UDPHS_DMA) Load Next Channel Transfer Descriptor Enable
+#define AT91C_UDPHS_END_TR_EN (0x1 <<  2) // (UDPHS_DMA) Buffer Close Input Enable
+#define AT91C_UDPHS_END_B_EN  (0x1 <<  3) // (UDPHS_DMA) End of DMA Buffer Packet Validation
+#define AT91C_UDPHS_END_TR_IT (0x1 <<  4) // (UDPHS_DMA) End Of Transfer Interrupt Enable
+#define AT91C_UDPHS_END_BUFFIT (0x1 <<  5) // (UDPHS_DMA) End Of Channel Buffer Interrupt Enable
+#define AT91C_UDPHS_DESC_LD_IT (0x1 <<  6) // (UDPHS_DMA) Descriptor Loaded Interrupt Enable
+#define AT91C_UDPHS_BURST_LCK (0x1 <<  7) // (UDPHS_DMA) Burst Lock Enable
+#define AT91C_UDPHS_BUFF_LENGTH (0xFFFF << 16) // (UDPHS_DMA) Buffer Byte Length (write only)
+// -------- UDPHS_DMASTATUS : (UDPHS_DMA Offset: 0xc) UDPHS DMA Channelx Status Register -------- 
+#define AT91C_UDPHS_CHANN_ACT (0x1 <<  1) // (UDPHS_DMA) 
+#define AT91C_UDPHS_END_TR_ST (0x1 <<  4) // (UDPHS_DMA) 
+#define AT91C_UDPHS_END_BF_ST (0x1 <<  5) // (UDPHS_DMA) 
+#define AT91C_UDPHS_DESC_LDST (0x1 <<  6) // (UDPHS_DMA) 
+#define AT91C_UDPHS_BUFF_COUNT (0xFFFF << 16) // (UDPHS_DMA) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR UDPHS High Speed Device Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDPHS {
+	AT91C_REG	 UDPHS_CTRL; 	// UDPHS Control Register
+	AT91C_REG	 UDPHS_FNUM; 	// UDPHS Frame Number Register
+	AT91C_REG	 Reserved0[2]; 	// 
+	AT91C_REG	 UDPHS_IEN; 	// UDPHS Interrupt Enable Register
+	AT91C_REG	 UDPHS_INTSTA; 	// UDPHS Interrupt Status Register
+	AT91C_REG	 UDPHS_CLRINT; 	// UDPHS Clear Interrupt Register
+	AT91C_REG	 UDPHS_EPTRST; 	// UDPHS Endpoints Reset Register
+	AT91C_REG	 Reserved1[44]; 	// 
+	AT91C_REG	 UDPHS_TSTSOFCNT; 	// UDPHS Test SOF Counter Register
+	AT91C_REG	 UDPHS_TSTCNTA; 	// UDPHS Test A Counter Register
+	AT91C_REG	 UDPHS_TSTCNTB; 	// UDPHS Test B Counter Register
+	AT91C_REG	 UDPHS_TSTMODREG; 	// UDPHS Test Mode Register
+	AT91C_REG	 UDPHS_TST; 	// UDPHS Test Register
+	AT91C_REG	 Reserved2[2]; 	// 
+	AT91C_REG	 UDPHS_RIPPADDRSIZE; 	// UDPHS PADDRSIZE Register
+	AT91C_REG	 UDPHS_RIPNAME1; 	// UDPHS Name1 Register
+	AT91C_REG	 UDPHS_RIPNAME2; 	// UDPHS Name2 Register
+	AT91C_REG	 UDPHS_IPFEATURES; 	// UDPHS Features Register
+	AT91C_REG	 UDPHS_IPVERSION; 	// UDPHS Version Register
+	AT91S_UDPHS_EPT	 UDPHS_EPT[7]; 	// UDPHS Endpoint struct
+	AT91C_REG	 Reserved3[72]; 	// 
+	AT91S_UDPHS_DMA	 UDPHS_DMA[7]; 	// UDPHS DMA channel struct (not use [0])
+} AT91S_UDPHS, *AT91PS_UDPHS;
+#else
+#define UDPHS_CTRL      (AT91C_CAST(AT91C_REG *) 	0x00000000) // (UDPHS_CTRL) UDPHS Control Register
+#define UDPHS_FNUM      (AT91C_CAST(AT91C_REG *) 	0x00000004) // (UDPHS_FNUM) UDPHS Frame Number Register
+#define UDPHS_IEN       (AT91C_CAST(AT91C_REG *) 	0x00000010) // (UDPHS_IEN) UDPHS Interrupt Enable Register
+#define UDPHS_INTSTA    (AT91C_CAST(AT91C_REG *) 	0x00000014) // (UDPHS_INTSTA) UDPHS Interrupt Status Register
+#define UDPHS_CLRINT    (AT91C_CAST(AT91C_REG *) 	0x00000018) // (UDPHS_CLRINT) UDPHS Clear Interrupt Register
+#define UDPHS_EPTRST    (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (UDPHS_EPTRST) UDPHS Endpoints Reset Register
+#define UDPHS_TSTSOFCNT (AT91C_CAST(AT91C_REG *) 	0x000000D0) // (UDPHS_TSTSOFCNT) UDPHS Test SOF Counter Register
+#define UDPHS_TSTCNTA   (AT91C_CAST(AT91C_REG *) 	0x000000D4) // (UDPHS_TSTCNTA) UDPHS Test A Counter Register
+#define UDPHS_TSTCNTB   (AT91C_CAST(AT91C_REG *) 	0x000000D8) // (UDPHS_TSTCNTB) UDPHS Test B Counter Register
+#define UDPHS_TSTMODREG (AT91C_CAST(AT91C_REG *) 	0x000000DC) // (UDPHS_TSTMODREG) UDPHS Test Mode Register
+#define UDPHS_TST       (AT91C_CAST(AT91C_REG *) 	0x000000E0) // (UDPHS_TST) UDPHS Test Register
+#define UDPHS_RIPPADDRSIZE (AT91C_CAST(AT91C_REG *) 	0x000000EC) // (UDPHS_RIPPADDRSIZE) UDPHS PADDRSIZE Register
+#define UDPHS_RIPNAME1  (AT91C_CAST(AT91C_REG *) 	0x000000F0) // (UDPHS_RIPNAME1) UDPHS Name1 Register
+#define UDPHS_RIPNAME2  (AT91C_CAST(AT91C_REG *) 	0x000000F4) // (UDPHS_RIPNAME2) UDPHS Name2 Register
+#define UDPHS_IPFEATURES (AT91C_CAST(AT91C_REG *) 	0x000000F8) // (UDPHS_IPFEATURES) UDPHS Features Register
+#define UDPHS_IPVERSION (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (UDPHS_IPVERSION) UDPHS Version Register
+
+#endif
+// -------- UDPHS_CTRL : (UDPHS Offset: 0x0) UDPHS Control Register -------- 
+#define AT91C_UDPHS_DEV_ADDR  (0x7F <<  0) // (UDPHS) UDPHS Address
+#define AT91C_UDPHS_FADDR_EN  (0x1 <<  7) // (UDPHS) Function Address Enable
+#define AT91C_UDPHS_EN_UDPHS  (0x1 <<  8) // (UDPHS) UDPHS Enable
+#define AT91C_UDPHS_DETACH    (0x1 <<  9) // (UDPHS) Detach Command
+#define AT91C_UDPHS_REWAKEUP  (0x1 << 10) // (UDPHS) Send Remote Wake Up
+#define AT91C_UDPHS_PULLD_DIS (0x1 << 11) // (UDPHS) PullDown Disable
+// -------- UDPHS_FNUM : (UDPHS Offset: 0x4) UDPHS Frame Number Register -------- 
+#define AT91C_UDPHS_MICRO_FRAME_NUM (0x7 <<  0) // (UDPHS) Micro Frame Number
+#define AT91C_UDPHS_FRAME_NUMBER (0x7FF <<  3) // (UDPHS) Frame Number as defined in the Packet Field Formats
+#define AT91C_UDPHS_FNUM_ERR  (0x1 << 31) // (UDPHS) Frame Number CRC Error
+// -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- 
+#define AT91C_UDPHS_DET_SUSPD (0x1 <<  1) // (UDPHS) Suspend Interrupt Enable/Clear/Status
+#define AT91C_UDPHS_MICRO_SOF (0x1 <<  2) // (UDPHS) Micro-SOF Interrupt Enable/Clear/Status
+#define AT91C_UDPHS_IEN_SOF   (0x1 <<  3) // (UDPHS) SOF Interrupt Enable/Clear/Status
+#define AT91C_UDPHS_ENDRESET  (0x1 <<  4) // (UDPHS) End Of Reset Interrupt Enable/Clear/Status
+#define AT91C_UDPHS_WAKE_UP   (0x1 <<  5) // (UDPHS) Wake Up CPU Interrupt Enable/Clear/Status
+#define AT91C_UDPHS_ENDOFRSM  (0x1 <<  6) // (UDPHS) End Of Resume Interrupt Enable/Clear/Status
+#define AT91C_UDPHS_UPSTR_RES (0x1 <<  7) // (UDPHS) Upstream Resume Interrupt Enable/Clear/Status
+#define AT91C_UDPHS_EPT_INT_0 (0x1 <<  8) // (UDPHS) Endpoint 0 Interrupt Enable/Status
+#define AT91C_UDPHS_EPT_INT_1 (0x1 <<  9) // (UDPHS) Endpoint 1 Interrupt Enable/Status
+#define AT91C_UDPHS_EPT_INT_2 (0x1 << 10) // (UDPHS) Endpoint 2 Interrupt Enable/Status
+#define AT91C_UDPHS_EPT_INT_3 (0x1 << 11) // (UDPHS) Endpoint 3 Interrupt Enable/Status
+#define AT91C_UDPHS_EPT_INT_4 (0x1 << 12) // (UDPHS) Endpoint 4 Interrupt Enable/Status
+#define AT91C_UDPHS_EPT_INT_5 (0x1 << 13) // (UDPHS) Endpoint 5 Interrupt Enable/Status
+#define AT91C_UDPHS_EPT_INT_6 (0x1 << 14) // (UDPHS) Endpoint 6 Interrupt Enable/Status
+#define AT91C_UDPHS_DMA_INT_1 (0x1 << 25) // (UDPHS) DMA Channel 1 Interrupt Enable/Status
+#define AT91C_UDPHS_DMA_INT_2 (0x1 << 26) // (UDPHS) DMA Channel 2 Interrupt Enable/Status
+#define AT91C_UDPHS_DMA_INT_3 (0x1 << 27) // (UDPHS) DMA Channel 3 Interrupt Enable/Status
+#define AT91C_UDPHS_DMA_INT_4 (0x1 << 28) // (UDPHS) DMA Channel 4 Interrupt Enable/Status
+#define AT91C_UDPHS_DMA_INT_5 (0x1 << 29) // (UDPHS) DMA Channel 5 Interrupt Enable/Status
+#define AT91C_UDPHS_DMA_INT_6 (0x1 << 30) // (UDPHS) DMA Channel 6 Interrupt Enable/Status
+// -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- 
+#define AT91C_UDPHS_SPEED     (0x1 <<  0) // (UDPHS) Speed Status
+// -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- 
+// -------- UDPHS_EPTRST : (UDPHS Offset: 0x1c) UDPHS Endpoints Reset Register -------- 
+#define AT91C_UDPHS_RST_EPT_0 (0x1 <<  0) // (UDPHS) Endpoint Reset 0
+#define AT91C_UDPHS_RST_EPT_1 (0x1 <<  1) // (UDPHS) Endpoint Reset 1
+#define AT91C_UDPHS_RST_EPT_2 (0x1 <<  2) // (UDPHS) Endpoint Reset 2
+#define AT91C_UDPHS_RST_EPT_3 (0x1 <<  3) // (UDPHS) Endpoint Reset 3
+#define AT91C_UDPHS_RST_EPT_4 (0x1 <<  4) // (UDPHS) Endpoint Reset 4
+#define AT91C_UDPHS_RST_EPT_5 (0x1 <<  5) // (UDPHS) Endpoint Reset 5
+#define AT91C_UDPHS_RST_EPT_6 (0x1 <<  6) // (UDPHS) Endpoint Reset 6
+// -------- UDPHS_TSTSOFCNT : (UDPHS Offset: 0xd0) UDPHS Test SOF Counter Register -------- 
+#define AT91C_UDPHS_SOFCNTMAX (0x3 <<  0) // (UDPHS) SOF Counter Max Value
+#define AT91C_UDPHS_SOFCTLOAD (0x1 <<  7) // (UDPHS) SOF Counter Load
+// -------- UDPHS_TSTCNTA : (UDPHS Offset: 0xd4) UDPHS Test A Counter Register -------- 
+#define AT91C_UDPHS_CNTAMAX   (0x7FFF <<  0) // (UDPHS) A Counter Max Value
+#define AT91C_UDPHS_CNTALOAD  (0x1 << 15) // (UDPHS) A Counter Load
+// -------- UDPHS_TSTCNTB : (UDPHS Offset: 0xd8) UDPHS Test B Counter Register -------- 
+#define AT91C_UDPHS_CNTBMAX   (0x7FFF <<  0) // (UDPHS) B Counter Max Value
+#define AT91C_UDPHS_CNTBLOAD  (0x1 << 15) // (UDPHS) B Counter Load
+// -------- UDPHS_TSTMODREG : (UDPHS Offset: 0xdc) UDPHS Test Mode Register -------- 
+#define AT91C_UDPHS_TSTMODE   (0x1F <<  1) // (UDPHS) UDPHS Core TestModeReg
+// -------- UDPHS_TST : (UDPHS Offset: 0xe0) UDPHS Test Register -------- 
+#define AT91C_UDPHS_SPEED_CFG (0x3 <<  0) // (UDPHS) Speed Configuration
+#define 	AT91C_UDPHS_SPEED_CFG_NM                   (0x0) // (UDPHS) Normal Mode
+#define 	AT91C_UDPHS_SPEED_CFG_RS                   (0x1) // (UDPHS) Reserved
+#define 	AT91C_UDPHS_SPEED_CFG_HS                   (0x2) // (UDPHS) Force High Speed
+#define 	AT91C_UDPHS_SPEED_CFG_FS                   (0x3) // (UDPHS) Force Full-Speed
+#define AT91C_UDPHS_TST_J     (0x1 <<  2) // (UDPHS) TestJMode
+#define AT91C_UDPHS_TST_K     (0x1 <<  3) // (UDPHS) TestKMode
+#define AT91C_UDPHS_TST_PKT   (0x1 <<  4) // (UDPHS) TestPacketMode
+#define AT91C_UDPHS_OPMODE2   (0x1 <<  5) // (UDPHS) OpMode2
+// -------- UDPHS_RIPPADDRSIZE : (UDPHS Offset: 0xec) UDPHS PADDRSIZE Register -------- 
+#define AT91C_UDPHS_IPPADDRSIZE (0x0 <<  0) // (UDPHS) 2^UDPHSDEV_PADDR_SIZE
+// -------- UDPHS_RIPNAME1 : (UDPHS Offset: 0xf0) UDPHS Name Register -------- 
+#define AT91C_UDPHS_IPNAME1   (0x0 <<  0) // (UDPHS) ASCII string HUSB
+// -------- UDPHS_RIPNAME2 : (UDPHS Offset: 0xf4) UDPHS Name Register -------- 
+#define AT91C_UDPHS_IPNAME2   (0x0 <<  0) // (UDPHS) ASCII string 2DEV
+// -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xf8) UDPHS Features Register -------- 
+#define AT91C_UDPHS_EPT_NBR_MAX (0xF <<  0) // (UDPHS) Max Number of Endpoints
+#define AT91C_UDPHS_DMA_CHANNEL_NBR (0x7 <<  4) // (UDPHS) Number of DMA Channels
+#define AT91C_UDPHS_DMA_B_SIZ (0x1 <<  7) // (UDPHS) DMA Buffer Size
+#define AT91C_UDPHS_DMA_FIFO_WORD_DEPTH (0xF <<  8) // (UDPHS) DMA FIFO Depth in words
+#define AT91C_UDPHS_FIFO_MAX_SIZE (0x7 << 12) // (UDPHS) DPRAM size
+#define AT91C_UDPHS_BW_DPRAM  (0x1 << 15) // (UDPHS) DPRAM byte write capability
+#define AT91C_UDPHS_DATAB16_8 (0x1 << 16) // (UDPHS) UTMI DataBus16_8
+#define AT91C_UDPHS_ISO_EPT_1 (0x1 << 17) // (UDPHS) Endpoint 1 High Bandwidth Isochronous Capability
+#define AT91C_UDPHS_ISO_EPT_2 (0x1 << 18) // (UDPHS) Endpoint 2 High Bandwidth Isochronous Capability
+#define AT91C_UDPHS_ISO_EPT_5 (0x1 << 21) // (UDPHS) Endpoint 5 High Bandwidth Isochronous Capability
+#define AT91C_UDPHS_ISO_EPT_6 (0x1 << 22) // (UDPHS) Endpoint 6 High Bandwidth Isochronous Capability
+// -------- UDPHS_IPVERSION : (UDPHS Offset: 0xfc) UDPHS Version Register -------- 
+#define AT91C_UDPHS_VERSION_NUM (0xFFFF <<  0) // (UDPHS) Give the IP version
+#define AT91C_UDPHS_METAL_FIX_NUM (0x7 << 16) // (UDPHS) Give the number of metal fixes
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR AC97 Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_AC97C {
+	AT91C_REG	 Reserved0[2]; 	// 
+	AT91C_REG	 AC97C_MR; 	// Mode Register
+	AT91C_REG	 Reserved1[1]; 	// 
+	AT91C_REG	 AC97C_ICA; 	// Input Channel AssignementRegister
+	AT91C_REG	 AC97C_OCA; 	// Output Channel Assignement Register
+	AT91C_REG	 Reserved2[2]; 	// 
+	AT91C_REG	 AC97C_CARHR; 	// Channel A Receive Holding Register
+	AT91C_REG	 AC97C_CATHR; 	// Channel A Transmit Holding Register
+	AT91C_REG	 AC97C_CASR; 	// Channel A Status Register
+	AT91C_REG	 AC97C_CAMR; 	// Channel A Mode Register
+	AT91C_REG	 AC97C_CBRHR; 	// Channel B Receive Holding Register (optional)
+	AT91C_REG	 AC97C_CBTHR; 	// Channel B Transmit Holding Register (optional)
+	AT91C_REG	 AC97C_CBSR; 	// Channel B Status Register
+	AT91C_REG	 AC97C_CBMR; 	// Channel B Mode Register
+	AT91C_REG	 AC97C_CORHR; 	// COdec Transmit Holding Register
+	AT91C_REG	 AC97C_COTHR; 	// COdec Transmit Holding Register
+	AT91C_REG	 AC97C_COSR; 	// CODEC Status Register
+	AT91C_REG	 AC97C_COMR; 	// CODEC Mask Status Register
+	AT91C_REG	 AC97C_SR; 	// Status Register
+	AT91C_REG	 AC97C_IER; 	// Interrupt Enable Register
+	AT91C_REG	 AC97C_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 AC97C_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 Reserved3[39]; 	// 
+	AT91C_REG	 AC97C_VERSION; 	// Version Register
+	AT91C_REG	 AC97C_RPR; 	// Receive Pointer Register
+	AT91C_REG	 AC97C_RCR; 	// Receive Counter Register
+	AT91C_REG	 AC97C_TPR; 	// Transmit Pointer Register
+	AT91C_REG	 AC97C_TCR; 	// Transmit Counter Register
+	AT91C_REG	 AC97C_RNPR; 	// Receive Next Pointer Register
+	AT91C_REG	 AC97C_RNCR; 	// Receive Next Counter Register
+	AT91C_REG	 AC97C_TNPR; 	// Transmit Next Pointer Register
+	AT91C_REG	 AC97C_TNCR; 	// Transmit Next Counter Register
+	AT91C_REG	 AC97C_PTCR; 	// PDC Transfer Control Register
+	AT91C_REG	 AC97C_PTSR; 	// PDC Transfer Status Register
+} AT91S_AC97C, *AT91PS_AC97C;
+#else
+#define AC97C_MR        (AT91C_CAST(AT91C_REG *) 	0x00000008) // (AC97C_MR) Mode Register
+#define AC97C_ICA       (AT91C_CAST(AT91C_REG *) 	0x00000010) // (AC97C_ICA) Input Channel AssignementRegister
+#define AC97C_OCA       (AT91C_CAST(AT91C_REG *) 	0x00000014) // (AC97C_OCA) Output Channel Assignement Register
+#define AC97C_CARHR     (AT91C_CAST(AT91C_REG *) 	0x00000020) // (AC97C_CARHR) Channel A Receive Holding Register
+#define AC97C_CATHR     (AT91C_CAST(AT91C_REG *) 	0x00000024) // (AC97C_CATHR) Channel A Transmit Holding Register
+#define AC97C_CASR      (AT91C_CAST(AT91C_REG *) 	0x00000028) // (AC97C_CASR) Channel A Status Register
+#define AC97C_CAMR      (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (AC97C_CAMR) Channel A Mode Register
+#define AC97C_CBRHR     (AT91C_CAST(AT91C_REG *) 	0x00000030) // (AC97C_CBRHR) Channel B Receive Holding Register (optional)
+#define AC97C_CBTHR     (AT91C_CAST(AT91C_REG *) 	0x00000034) // (AC97C_CBTHR) Channel B Transmit Holding Register (optional)
+#define AC97C_CBSR      (AT91C_CAST(AT91C_REG *) 	0x00000038) // (AC97C_CBSR) Channel B Status Register
+#define AC97C_CBMR      (AT91C_CAST(AT91C_REG *) 	0x0000003C) // (AC97C_CBMR) Channel B Mode Register
+#define AC97C_CORHR     (AT91C_CAST(AT91C_REG *) 	0x00000040) // (AC97C_CORHR) COdec Transmit Holding Register
+#define AC97C_COTHR     (AT91C_CAST(AT91C_REG *) 	0x00000044) // (AC97C_COTHR) COdec Transmit Holding Register
+#define AC97C_COSR      (AT91C_CAST(AT91C_REG *) 	0x00000048) // (AC97C_COSR) CODEC Status Register
+#define AC97C_COMR      (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (AC97C_COMR) CODEC Mask Status Register
+#define AC97C_SR        (AT91C_CAST(AT91C_REG *) 	0x00000050) // (AC97C_SR) Status Register
+#define AC97C_IER       (AT91C_CAST(AT91C_REG *) 	0x00000054) // (AC97C_IER) Interrupt Enable Register
+#define AC97C_IDR       (AT91C_CAST(AT91C_REG *) 	0x00000058) // (AC97C_IDR) Interrupt Disable Register
+#define AC97C_IMR       (AT91C_CAST(AT91C_REG *) 	0x0000005C) // (AC97C_IMR) Interrupt Mask Register
+#define AC97C_VERSION   (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (AC97C_VERSION) Version Register
+
+#endif
+// -------- AC97C_MR : (AC97C Offset: 0x8) AC97C Mode Register -------- 
+#define AT91C_AC97C_ENA       (0x1 <<  0) // (AC97C) AC97 Controller Global Enable
+#define AT91C_AC97C_WRST      (0x1 <<  1) // (AC97C) Warm Reset
+#define AT91C_AC97C_VRA       (0x1 <<  2) // (AC97C) Variable RAte (for Data Slots)
+// -------- AC97C_ICA : (AC97C Offset: 0x10) AC97C Input Channel Assignement Register -------- 
+#define AT91C_AC97C_CHID3     (0x7 <<  0) // (AC97C) Channel Id for the input slot 3
+#define 	AT91C_AC97C_CHID3_NONE                 (0x0) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID3_CA                   (0x1) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID3_CB                   (0x2) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID3_CC                   (0x3) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID4     (0x7 <<  3) // (AC97C) Channel Id for the input slot 4
+#define 	AT91C_AC97C_CHID4_NONE                 (0x0 <<  3) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID4_CA                   (0x1 <<  3) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID4_CB                   (0x2 <<  3) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID4_CC                   (0x3 <<  3) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID5     (0x7 <<  6) // (AC97C) Channel Id for the input slot 5
+#define 	AT91C_AC97C_CHID5_NONE                 (0x0 <<  6) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID5_CA                   (0x1 <<  6) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID5_CB                   (0x2 <<  6) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID5_CC                   (0x3 <<  6) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID6     (0x7 <<  9) // (AC97C) Channel Id for the input slot 6
+#define 	AT91C_AC97C_CHID6_NONE                 (0x0 <<  9) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID6_CA                   (0x1 <<  9) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID6_CB                   (0x2 <<  9) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID6_CC                   (0x3 <<  9) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID7     (0x7 << 12) // (AC97C) Channel Id for the input slot 7
+#define 	AT91C_AC97C_CHID7_NONE                 (0x0 << 12) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID7_CA                   (0x1 << 12) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID7_CB                   (0x2 << 12) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID7_CC                   (0x3 << 12) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID8     (0x7 << 15) // (AC97C) Channel Id for the input slot 8
+#define 	AT91C_AC97C_CHID8_NONE                 (0x0 << 15) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID8_CA                   (0x1 << 15) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID8_CB                   (0x2 << 15) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID8_CC                   (0x3 << 15) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID9     (0x7 << 18) // (AC97C) Channel Id for the input slot 9
+#define 	AT91C_AC97C_CHID9_NONE                 (0x0 << 18) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID9_CA                   (0x1 << 18) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID9_CB                   (0x2 << 18) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID9_CC                   (0x3 << 18) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID10    (0x7 << 21) // (AC97C) Channel Id for the input slot 10
+#define 	AT91C_AC97C_CHID10_NONE                 (0x0 << 21) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID10_CA                   (0x1 << 21) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID10_CB                   (0x2 << 21) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID10_CC                   (0x3 << 21) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID11    (0x7 << 24) // (AC97C) Channel Id for the input slot 11
+#define 	AT91C_AC97C_CHID11_NONE                 (0x0 << 24) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID11_CA                   (0x1 << 24) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID11_CB                   (0x2 << 24) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID11_CC                   (0x3 << 24) // (AC97C) Channel C data will be transmitted during this slot
+#define AT91C_AC97C_CHID12    (0x7 << 27) // (AC97C) Channel Id for the input slot 12
+#define 	AT91C_AC97C_CHID12_NONE                 (0x0 << 27) // (AC97C) No data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID12_CA                   (0x1 << 27) // (AC97C) Channel A data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID12_CB                   (0x2 << 27) // (AC97C) Channel B data will be transmitted during this slot
+#define 	AT91C_AC97C_CHID12_CC                   (0x3 << 27) // (AC97C) Channel C data will be transmitted during this slot
+// -------- AC97C_OCA : (AC97C Offset: 0x14) AC97C Output Channel Assignement Register -------- 
+// -------- AC97C_CARHR : (AC97C Offset: 0x20) AC97C Channel A Receive Holding Register -------- 
+#define AT91C_AC97C_RDATA     (0xFFFFF <<  0) // (AC97C) Receive data
+// -------- AC97C_CATHR : (AC97C Offset: 0x24) AC97C Channel A Transmit Holding Register -------- 
+#define AT91C_AC97C_TDATA     (0xFFFFF <<  0) // (AC97C) Transmit data
+// -------- AC97C_CASR : (AC97C Offset: 0x28) AC97C Channel A Status Register -------- 
+#define AT91C_AC97C_TXRDY     (0x1 <<  0) // (AC97C) 
+#define AT91C_AC97C_TXEMPTY   (0x1 <<  1) // (AC97C) 
+#define AT91C_AC97C_UNRUN     (0x1 <<  2) // (AC97C) 
+#define AT91C_AC97C_RXRDY     (0x1 <<  4) // (AC97C) 
+#define AT91C_AC97C_OVRUN     (0x1 <<  5) // (AC97C) 
+#define AT91C_AC97C_ENDTX     (0x1 << 10) // (AC97C) 
+#define AT91C_AC97C_TXBUFE    (0x1 << 11) // (AC97C) 
+#define AT91C_AC97C_ENDRX     (0x1 << 14) // (AC97C) 
+#define AT91C_AC97C_RXBUFF    (0x1 << 15) // (AC97C) 
+// -------- AC97C_CAMR : (AC97C Offset: 0x2c) AC97C Channel A Mode Register -------- 
+#define AT91C_AC97C_SIZE      (0x3 << 16) // (AC97C) 
+#define 	AT91C_AC97C_SIZE_20_BITS              (0x0 << 16) // (AC97C) Data size is 20 bits
+#define 	AT91C_AC97C_SIZE_18_BITS              (0x1 << 16) // (AC97C) Data size is 18 bits
+#define 	AT91C_AC97C_SIZE_16_BITS              (0x2 << 16) // (AC97C) Data size is 16 bits
+#define 	AT91C_AC97C_SIZE_10_BITS              (0x3 << 16) // (AC97C) Data size is 10 bits
+#define AT91C_AC97C_CEM       (0x1 << 18) // (AC97C) 
+#define AT91C_AC97C_CEN       (0x1 << 21) // (AC97C) 
+#define AT91C_AC97C_PDCEN     (0x1 << 22) // (AC97C) 
+// -------- AC97C_CBRHR : (AC97C Offset: 0x30) AC97C Channel B Receive Holding Register -------- 
+// -------- AC97C_CBTHR : (AC97C Offset: 0x34) AC97C Channel B Transmit Holding Register -------- 
+// -------- AC97C_CBSR : (AC97C Offset: 0x38) AC97C Channel B Status Register -------- 
+// -------- AC97C_CBMR : (AC97C Offset: 0x3c) AC97C Channel B Mode Register -------- 
+// -------- AC97C_CORHR : (AC97C Offset: 0x40) AC97C Codec Channel Receive Holding Register -------- 
+#define AT91C_AC97C_SDATA     (0xFFFF <<  0) // (AC97C) Status Data
+// -------- AC97C_COTHR : (AC97C Offset: 0x44) AC97C Codec Channel Transmit Holding Register -------- 
+#define AT91C_AC97C_CDATA     (0xFFFF <<  0) // (AC97C) Command Data
+#define AT91C_AC97C_CADDR     (0x7F << 16) // (AC97C) COdec control register index
+#define AT91C_AC97C_READ      (0x1 << 23) // (AC97C) Read/Write command
+// -------- AC97C_COSR : (AC97C Offset: 0x48) AC97C CODEC Status Register -------- 
+// -------- AC97C_COMR : (AC97C Offset: 0x4c) AC97C CODEC Mode Register -------- 
+// -------- AC97C_SR : (AC97C Offset: 0x50) AC97C Status Register -------- 
+#define AT91C_AC97C_SOF       (0x1 <<  0) // (AC97C) 
+#define AT91C_AC97C_WKUP      (0x1 <<  1) // (AC97C) 
+#define AT91C_AC97C_COEVT     (0x1 <<  2) // (AC97C) 
+#define AT91C_AC97C_CAEVT     (0x1 <<  3) // (AC97C) 
+#define AT91C_AC97C_CBEVT     (0x1 <<  4) // (AC97C) 
+// -------- AC97C_IER : (AC97C Offset: 0x54) AC97C Interrupt Enable Register -------- 
+// -------- AC97C_IDR : (AC97C Offset: 0x58) AC97C Interrupt Disable Register -------- 
+// -------- AC97C_IMR : (AC97C Offset: 0x5c) AC97C Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR LCD Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_LCDC {
+	AT91C_REG	 LCDC_BA1; 	// DMA Base Address Register 1
+	AT91C_REG	 LCDC_BA2; 	// DMA Base Address Register 2
+	AT91C_REG	 LCDC_FRMP1; 	// DMA Frame Pointer Register 1
+	AT91C_REG	 LCDC_FRMP2; 	// DMA Frame Pointer Register 2
+	AT91C_REG	 LCDC_FRMA1; 	// DMA Frame Address Register 1
+	AT91C_REG	 LCDC_FRMA2; 	// DMA Frame Address Register 2
+	AT91C_REG	 LCDC_FRMCFG; 	// DMA Frame Configuration Register
+	AT91C_REG	 LCDC_DMACON; 	// DMA Control Register
+	AT91C_REG	 LCDC_DMA2DCFG; 	// DMA 2D addressing configuration
+	AT91C_REG	 Reserved0[503]; 	// 
+	AT91C_REG	 LCDC_LCDCON1; 	// LCD Control 1 Register
+	AT91C_REG	 LCDC_LCDCON2; 	// LCD Control 2 Register
+	AT91C_REG	 LCDC_TIM1; 	// LCD Timing Config 1 Register
+	AT91C_REG	 LCDC_TIM2; 	// LCD Timing Config 2 Register
+	AT91C_REG	 LCDC_LCDFRCFG; 	// LCD Frame Config Register
+	AT91C_REG	 LCDC_FIFO; 	// LCD FIFO Register
+	AT91C_REG	 LCDC_MVAL; 	// LCD Mode Toggle Rate Value Register
+	AT91C_REG	 LCDC_DP1_2; 	// Dithering Pattern DP1_2 Register
+	AT91C_REG	 LCDC_DP4_7; 	// Dithering Pattern DP4_7 Register
+	AT91C_REG	 LCDC_DP3_5; 	// Dithering Pattern DP3_5 Register
+	AT91C_REG	 LCDC_DP2_3; 	// Dithering Pattern DP2_3 Register
+	AT91C_REG	 LCDC_DP5_7; 	// Dithering Pattern DP5_7 Register
+	AT91C_REG	 LCDC_DP3_4; 	// Dithering Pattern DP3_4 Register
+	AT91C_REG	 LCDC_DP4_5; 	// Dithering Pattern DP4_5 Register
+	AT91C_REG	 LCDC_DP6_7; 	// Dithering Pattern DP6_7 Register
+	AT91C_REG	 LCDC_PWRCON; 	// Power Control Register
+	AT91C_REG	 LCDC_CTRSTCON; 	// Contrast Control Register
+	AT91C_REG	 LCDC_CTRSTVAL; 	// Contrast Value Register
+	AT91C_REG	 LCDC_IER; 	// Interrupt Enable Register
+	AT91C_REG	 LCDC_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 LCDC_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 LCDC_ISR; 	// Interrupt Enable Register
+	AT91C_REG	 LCDC_ICR; 	// Interrupt Clear Register
+	AT91C_REG	 LCDC_GPR; 	// General Purpose Register
+	AT91C_REG	 LCDC_ITR; 	// Interrupts Test Register
+	AT91C_REG	 LCDC_IRR; 	// Interrupts Raw Status Register
+	AT91C_REG	 Reserved1[230]; 	// 
+	AT91C_REG	 LCDC_LUT_ENTRY[256]; 	// LUT Entries Register
+} AT91S_LCDC, *AT91PS_LCDC;
+#else
+#define LCDC_BA1        (AT91C_CAST(AT91C_REG *) 	0x00000000) // (LCDC_BA1) DMA Base Address Register 1
+#define LCDC_BA2        (AT91C_CAST(AT91C_REG *) 	0x00000004) // (LCDC_BA2) DMA Base Address Register 2
+#define LCDC_FRMP1      (AT91C_CAST(AT91C_REG *) 	0x00000008) // (LCDC_FRMP1) DMA Frame Pointer Register 1
+#define LCDC_FRMP2      (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (LCDC_FRMP2) DMA Frame Pointer Register 2
+#define LCDC_FRMA1      (AT91C_CAST(AT91C_REG *) 	0x00000010) // (LCDC_FRMA1) DMA Frame Address Register 1
+#define LCDC_FRMA2      (AT91C_CAST(AT91C_REG *) 	0x00000014) // (LCDC_FRMA2) DMA Frame Address Register 2
+#define LCDC_FRMCFG     (AT91C_CAST(AT91C_REG *) 	0x00000018) // (LCDC_FRMCFG) DMA Frame Configuration Register
+#define LCDC_DMACON     (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (LCDC_DMACON) DMA Control Register
+#define LCDC_DMA2DCFG   (AT91C_CAST(AT91C_REG *) 	0x00000020) // (LCDC_DMA2DCFG) DMA 2D addressing configuration
+#define LCDC_LCDCON1    (AT91C_CAST(AT91C_REG *) 	0x00000800) // (LCDC_LCDCON1) LCD Control 1 Register
+#define LCDC_LCDCON2    (AT91C_CAST(AT91C_REG *) 	0x00000804) // (LCDC_LCDCON2) LCD Control 2 Register
+#define LCDC_TIM1       (AT91C_CAST(AT91C_REG *) 	0x00000808) // (LCDC_TIM1) LCD Timing Config 1 Register
+#define LCDC_TIM2       (AT91C_CAST(AT91C_REG *) 	0x0000080C) // (LCDC_TIM2) LCD Timing Config 2 Register
+#define LCDC_LCDFRCFG   (AT91C_CAST(AT91C_REG *) 	0x00000810) // (LCDC_LCDFRCFG) LCD Frame Config Register
+#define LCDC_FIFO       (AT91C_CAST(AT91C_REG *) 	0x00000814) // (LCDC_FIFO) LCD FIFO Register
+#define LCDC_MVAL       (AT91C_CAST(AT91C_REG *) 	0x00000818) // (LCDC_MVAL) LCD Mode Toggle Rate Value Register
+#define LCDC_DP1_2      (AT91C_CAST(AT91C_REG *) 	0x0000081C) // (LCDC_DP1_2) Dithering Pattern DP1_2 Register
+#define LCDC_DP4_7      (AT91C_CAST(AT91C_REG *) 	0x00000820) // (LCDC_DP4_7) Dithering Pattern DP4_7 Register
+#define LCDC_DP3_5      (AT91C_CAST(AT91C_REG *) 	0x00000824) // (LCDC_DP3_5) Dithering Pattern DP3_5 Register
+#define LCDC_DP2_3      (AT91C_CAST(AT91C_REG *) 	0x00000828) // (LCDC_DP2_3) Dithering Pattern DP2_3 Register
+#define LCDC_DP5_7      (AT91C_CAST(AT91C_REG *) 	0x0000082C) // (LCDC_DP5_7) Dithering Pattern DP5_7 Register
+#define LCDC_DP3_4      (AT91C_CAST(AT91C_REG *) 	0x00000830) // (LCDC_DP3_4) Dithering Pattern DP3_4 Register
+#define LCDC_DP4_5      (AT91C_CAST(AT91C_REG *) 	0x00000834) // (LCDC_DP4_5) Dithering Pattern DP4_5 Register
+#define LCDC_DP6_7      (AT91C_CAST(AT91C_REG *) 	0x00000838) // (LCDC_DP6_7) Dithering Pattern DP6_7 Register
+#define LCDC_PWRCON     (AT91C_CAST(AT91C_REG *) 	0x0000083C) // (LCDC_PWRCON) Power Control Register
+#define LCDC_CTRSTCON   (AT91C_CAST(AT91C_REG *) 	0x00000840) // (LCDC_CTRSTCON) Contrast Control Register
+#define LCDC_CTRSTVAL   (AT91C_CAST(AT91C_REG *) 	0x00000844) // (LCDC_CTRSTVAL) Contrast Value Register
+#define LCDC_IER        (AT91C_CAST(AT91C_REG *) 	0x00000848) // (LCDC_IER) Interrupt Enable Register
+#define LCDC_IDR        (AT91C_CAST(AT91C_REG *) 	0x0000084C) // (LCDC_IDR) Interrupt Disable Register
+#define LCDC_IMR        (AT91C_CAST(AT91C_REG *) 	0x00000850) // (LCDC_IMR) Interrupt Mask Register
+#define LCDC_ISR        (AT91C_CAST(AT91C_REG *) 	0x00000854) // (LCDC_ISR) Interrupt Enable Register
+#define LCDC_ICR        (AT91C_CAST(AT91C_REG *) 	0x00000858) // (LCDC_ICR) Interrupt Clear Register
+#define LCDC_GPR        (AT91C_CAST(AT91C_REG *) 	0x0000085C) // (LCDC_GPR) General Purpose Register
+#define LCDC_ITR        (AT91C_CAST(AT91C_REG *) 	0x00000860) // (LCDC_ITR) Interrupts Test Register
+#define LCDC_IRR        (AT91C_CAST(AT91C_REG *) 	0x00000864) // (LCDC_IRR) Interrupts Raw Status Register
+#define LCDC_LUT_ENTRY  (AT91C_CAST(AT91C_REG *) 	0x00000C00) // (LCDC_LUT_ENTRY) LUT Entries Register
+
+#endif
+// -------- LCDC_FRMP1 : (LCDC Offset: 0x8) DMA Frame Pointer 1 Register -------- 
+#define AT91C_LCDC_FRMPT1     (0x3FFFFF <<  0) // (LCDC) Frame Pointer Address 1
+// -------- LCDC_FRMP2 : (LCDC Offset: 0xc) DMA Frame Pointer 2 Register -------- 
+#define AT91C_LCDC_FRMPT2     (0x1FFFFF <<  0) // (LCDC) Frame Pointer Address 2
+// -------- LCDC_FRMCFG : (LCDC Offset: 0x18) DMA Frame Config Register -------- 
+#define AT91C_LCDC_FRSIZE     (0x7FFFFF <<  0) // (LCDC) FRAME SIZE
+#define AT91C_LCDC_BLENGTH    (0x7F << 24) // (LCDC) BURST LENGTH
+// -------- LCDC_DMACON : (LCDC Offset: 0x1c) DMA Control Register -------- 
+#define AT91C_LCDC_DMAEN      (0x1 <<  0) // (LCDC) DAM Enable
+#define AT91C_LCDC_DMARST     (0x1 <<  1) // (LCDC) DMA Reset (WO)
+#define AT91C_LCDC_DMABUSY    (0x1 <<  2) // (LCDC) DMA Reset (WO)
+#define AT91C_LCDC_DMAUPDT    (0x1 <<  3) // (LCDC) DMA Configuration Update
+#define AT91C_LCDC_DMA2DEN    (0x1 <<  4) // (LCDC) 2D Addressing Enable
+// -------- LCDC_DMA2DCFG : (LCDC Offset: 0x20) DMA 2D addressing configuration Register -------- 
+#define AT91C_LCDC_ADDRINC    (0xFFFF <<  0) // (LCDC) Number of 32b words that the DMA must jump when going to the next line
+#define AT91C_LCDC_PIXELOFF   (0x1F << 24) // (LCDC) Offset (in bits) of the first pixel of the screen in the memory word which contain it
+// -------- LCDC_LCDCON1 : (LCDC Offset: 0x800) LCD Control 1 Register -------- 
+#define AT91C_LCDC_BYPASS     (0x1 <<  0) // (LCDC) Bypass lcd_pccklk divider
+#define AT91C_LCDC_CLKVAL     (0x1FF << 12) // (LCDC) 9-bit Divider for pixel clock frequency
+#define AT91C_LCDC_LINCNT     (0x7FF << 21) // (LCDC) Line Counter (RO)
+// -------- LCDC_LCDCON2 : (LCDC Offset: 0x804) LCD Control 2 Register -------- 
+#define AT91C_LCDC_DISTYPE    (0x3 <<  0) // (LCDC) Display Type
+#define 	AT91C_LCDC_DISTYPE_STNMONO              (0x0) // (LCDC) STN Mono
+#define 	AT91C_LCDC_DISTYPE_STNCOLOR             (0x1) // (LCDC) STN Color
+#define 	AT91C_LCDC_DISTYPE_TFT                  (0x2) // (LCDC) TFT
+#define AT91C_LCDC_SCANMOD    (0x1 <<  2) // (LCDC) Scan Mode
+#define 	AT91C_LCDC_SCANMOD_SINGLESCAN           (0x0 <<  2) // (LCDC) Single Scan
+#define 	AT91C_LCDC_SCANMOD_DUALSCAN             (0x1 <<  2) // (LCDC) Dual Scan
+#define AT91C_LCDC_IFWIDTH    (0x3 <<  3) // (LCDC) Interface Width
+#define 	AT91C_LCDC_IFWIDTH_FOURBITSWIDTH        (0x0 <<  3) // (LCDC) 4 Bits
+#define 	AT91C_LCDC_IFWIDTH_EIGTHBITSWIDTH       (0x1 <<  3) // (LCDC) 8 Bits
+#define 	AT91C_LCDC_IFWIDTH_SIXTEENBITSWIDTH     (0x2 <<  3) // (LCDC) 16 Bits
+#define AT91C_LCDC_PIXELSIZE  (0x7 <<  5) // (LCDC) Bits per pixel
+#define 	AT91C_LCDC_PIXELSIZE_ONEBITSPERPIXEL      (0x0 <<  5) // (LCDC) 1 Bits
+#define 	AT91C_LCDC_PIXELSIZE_TWOBITSPERPIXEL      (0x1 <<  5) // (LCDC) 2 Bits
+#define 	AT91C_LCDC_PIXELSIZE_FOURBITSPERPIXEL     (0x2 <<  5) // (LCDC) 4 Bits
+#define 	AT91C_LCDC_PIXELSIZE_EIGTHBITSPERPIXEL    (0x3 <<  5) // (LCDC) 8 Bits
+#define 	AT91C_LCDC_PIXELSIZE_SIXTEENBITSPERPIXEL  (0x4 <<  5) // (LCDC) 16 Bits
+#define 	AT91C_LCDC_PIXELSIZE_TWENTYFOURBITSPERPIXEL (0x5 <<  5) // (LCDC) 24 Bits
+#define AT91C_LCDC_INVVD      (0x1 <<  8) // (LCDC) lcd datas polarity
+#define 	AT91C_LCDC_INVVD_NORMALPOL            (0x0 <<  8) // (LCDC) Normal Polarity
+#define 	AT91C_LCDC_INVVD_INVERTEDPOL          (0x1 <<  8) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_INVFRAME   (0x1 <<  9) // (LCDC) lcd vsync polarity
+#define 	AT91C_LCDC_INVFRAME_NORMALPOL            (0x0 <<  9) // (LCDC) Normal Polarity
+#define 	AT91C_LCDC_INVFRAME_INVERTEDPOL          (0x1 <<  9) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_INVLINE    (0x1 << 10) // (LCDC) lcd hsync polarity
+#define 	AT91C_LCDC_INVLINE_NORMALPOL            (0x0 << 10) // (LCDC) Normal Polarity
+#define 	AT91C_LCDC_INVLINE_INVERTEDPOL          (0x1 << 10) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_INVCLK     (0x1 << 11) // (LCDC) lcd pclk polarity
+#define 	AT91C_LCDC_INVCLK_NORMALPOL            (0x0 << 11) // (LCDC) Normal Polarity
+#define 	AT91C_LCDC_INVCLK_INVERTEDPOL          (0x1 << 11) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_INVDVAL    (0x1 << 12) // (LCDC) lcd dval polarity
+#define 	AT91C_LCDC_INVDVAL_NORMALPOL            (0x0 << 12) // (LCDC) Normal Polarity
+#define 	AT91C_LCDC_INVDVAL_INVERTEDPOL          (0x1 << 12) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_CLKMOD     (0x1 << 15) // (LCDC) lcd pclk Mode
+#define 	AT91C_LCDC_CLKMOD_ACTIVEONLYDISP       (0x0 << 15) // (LCDC) Active during display period
+#define 	AT91C_LCDC_CLKMOD_ALWAYSACTIVE         (0x1 << 15) // (LCDC) Always Active
+#define AT91C_LCDC_MEMOR      (0x3 << 30) // (LCDC) Memory Ordering Format
+#define 	AT91C_LCDC_MEMOR_BIGIND               (0x0 << 30) // (LCDC) Big Endian
+#define 	AT91C_LCDC_MEMOR_LITTLEIND            (0x2 << 30) // (LCDC) Little Endian
+// -------- LCDC_TIM1 : (LCDC Offset: 0x808) LCDC Timing Config 1 Register -------- 
+#define AT91C_LCDC_VFP        (0xFF <<  0) // (LCDC) Vertical Front Porch
+#define AT91C_LCDC_VBP        (0xFF <<  8) // (LCDC) Vertical Back Porch
+#define AT91C_LCDC_VPW        (0x3F << 16) // (LCDC) Vertical Synchronization Pulse Width
+#define AT91C_LCDC_VHDLY      (0xF << 24) // (LCDC) Vertical to Horizontal Delay
+// -------- LCDC_TIM2 : (LCDC Offset: 0x80c) LCDC Timing Config 2 Register -------- 
+#define AT91C_LCDC_HBP        (0xFF <<  0) // (LCDC) Horizontal Back Porch
+#define AT91C_LCDC_HPW        (0x3F <<  8) // (LCDC) Horizontal Synchronization Pulse Width
+#define AT91C_LCDC_HFP        (0x7FF << 21) // (LCDC) Horizontal Front Porch
+// -------- LCDC_LCDFRCFG : (LCDC Offset: 0x810) LCD Frame Config Register -------- 
+#define AT91C_LCDC_LINEVAL    (0x7FF <<  0) // (LCDC) Vertical Size of LCD Module
+#define AT91C_LCDC_HOZVAL     (0x7FF << 21) // (LCDC) Horizontal Size of LCD Module
+// -------- LCDC_FIFO : (LCDC Offset: 0x814) LCD FIFO Register -------- 
+#define AT91C_LCDC_FIFOTH     (0xFFFF <<  0) // (LCDC) FIFO Threshold
+// -------- LCDC_MVAL : (LCDC Offset: 0x818) LCD Mode Toggle Rate Value Register -------- 
+#define AT91C_LCDC_MVALUE     (0xFF <<  0) // (LCDC) Toggle Rate Value
+#define AT91C_LCDC_MMODE      (0x1 << 31) // (LCDC) Toggle Rate Sel
+#define 	AT91C_LCDC_MMODE_EACHFRAME            (0x0 << 31) // (LCDC) Each Frame
+#define 	AT91C_LCDC_MMODE_MVALDEFINED          (0x1 << 31) // (LCDC) Defined by MVAL
+// -------- LCDC_DP1_2 : (LCDC Offset: 0x81c) Dithering Pattern 1/2 -------- 
+#define AT91C_LCDC_DP1_2_FIELD (0xFF <<  0) // (LCDC) Ratio
+// -------- LCDC_DP4_7 : (LCDC Offset: 0x820) Dithering Pattern 4/7 -------- 
+#define AT91C_LCDC_DP4_7_FIELD (0xFFFFFFF <<  0) // (LCDC) Ratio
+// -------- LCDC_DP3_5 : (LCDC Offset: 0x824) Dithering Pattern 3/5 -------- 
+#define AT91C_LCDC_DP3_5_FIELD (0xFFFFF <<  0) // (LCDC) Ratio
+// -------- LCDC_DP2_3 : (LCDC Offset: 0x828) Dithering Pattern 2/3 -------- 
+#define AT91C_LCDC_DP2_3_FIELD (0xFFF <<  0) // (LCDC) Ratio
+// -------- LCDC_DP5_7 : (LCDC Offset: 0x82c) Dithering Pattern 5/7 -------- 
+#define AT91C_LCDC_DP5_7_FIELD (0xFFFFFFF <<  0) // (LCDC) Ratio
+// -------- LCDC_DP3_4 : (LCDC Offset: 0x830) Dithering Pattern 3/4 -------- 
+#define AT91C_LCDC_DP3_4_FIELD (0xFFFF <<  0) // (LCDC) Ratio
+// -------- LCDC_DP4_5 : (LCDC Offset: 0x834) Dithering Pattern 4/5 -------- 
+#define AT91C_LCDC_DP4_5_FIELD (0xFFFFF <<  0) // (LCDC) Ratio
+// -------- LCDC_DP6_7 : (LCDC Offset: 0x838) Dithering Pattern 6/7 -------- 
+#define AT91C_LCDC_DP6_7_FIELD (0xFFFFFFF <<  0) // (LCDC) Ratio
+// -------- LCDC_PWRCON : (LCDC Offset: 0x83c) LCDC Power Control Register -------- 
+#define AT91C_LCDC_PWR        (0x1 <<  0) // (LCDC) LCD Module Power Control
+#define AT91C_LCDC_GUARDT     (0x7F <<  1) // (LCDC) Delay in Frame Period
+#define AT91C_LCDC_BUSY       (0x1 << 31) // (LCDC) Read Only : 1 indicates that LCDC is busy
+#define 	AT91C_LCDC_BUSY_LCDNOTBUSY           (0x0 << 31) // (LCDC) LCD is Not Busy
+#define 	AT91C_LCDC_BUSY_LCDBUSY              (0x1 << 31) // (LCDC) LCD is Busy
+// -------- LCDC_CTRSTCON : (LCDC Offset: 0x840) LCDC Contrast Control Register -------- 
+#define AT91C_LCDC_PS         (0x3 <<  0) // (LCDC) LCD Contrast Counter Prescaler
+#define 	AT91C_LCDC_PS_NOTDIVIDED           (0x0) // (LCDC) Counter Freq is System Freq.
+#define 	AT91C_LCDC_PS_DIVIDEDBYTWO         (0x1) // (LCDC) Counter Freq is System Freq divided by 2.
+#define 	AT91C_LCDC_PS_DIVIDEDBYFOUR        (0x2) // (LCDC) Counter Freq is System Freq divided by 4.
+#define 	AT91C_LCDC_PS_DIVIDEDBYEIGHT       (0x3) // (LCDC) Counter Freq is System Freq divided by 8.
+#define AT91C_LCDC_POL        (0x1 <<  2) // (LCDC) Polarity of output Pulse
+#define 	AT91C_LCDC_POL_NEGATIVEPULSE        (0x0 <<  2) // (LCDC) Negative Pulse
+#define 	AT91C_LCDC_POL_POSITIVEPULSE        (0x1 <<  2) // (LCDC) Positive Pulse
+#define AT91C_LCDC_ENA        (0x1 <<  3) // (LCDC) PWM generator Control
+#define 	AT91C_LCDC_ENA_PWMGEMDISABLED       (0x0 <<  3) // (LCDC) PWM Generator Disabled
+#define 	AT91C_LCDC_ENA_PWMGEMENABLED        (0x1 <<  3) // (LCDC) PWM Generator Disabled
+// -------- LCDC_CTRSTVAL : (LCDC Offset: 0x844) Contrast Value Register -------- 
+#define AT91C_LCDC_CVAL       (0xFF <<  0) // (LCDC) PWM Compare Value
+// -------- LCDC_IER : (LCDC Offset: 0x848) LCDC Interrupt Enable Register -------- 
+#define AT91C_LCDC_LNI        (0x1 <<  0) // (LCDC) Line Interrupt
+#define AT91C_LCDC_LSTLNI     (0x1 <<  1) // (LCDC) Last Line Interrupt
+#define AT91C_LCDC_EOFI       (0x1 <<  2) // (LCDC) End Of Frame Interrupt
+#define AT91C_LCDC_UFLWI      (0x1 <<  4) // (LCDC) FIFO Underflow Interrupt
+#define AT91C_LCDC_OWRI       (0x1 <<  5) // (LCDC) Over Write Interrupt
+#define AT91C_LCDC_MERI       (0x1 <<  6) // (LCDC) Memory Error  Interrupt
+// -------- LCDC_IDR : (LCDC Offset: 0x84c) LCDC Interrupt Disable Register -------- 
+// -------- LCDC_IMR : (LCDC Offset: 0x850) LCDC Interrupt Mask Register -------- 
+// -------- LCDC_ISR : (LCDC Offset: 0x854) LCDC Interrupt Status Register -------- 
+// -------- LCDC_ICR : (LCDC Offset: 0x858) LCDC Interrupt Clear Register -------- 
+// -------- LCDC_GPR : (LCDC Offset: 0x85c) LCDC General Purpose Register -------- 
+#define AT91C_LCDC_GPRBUS     (0xFF <<  0) // (LCDC) 8 bits available
+// -------- LCDC_ITR : (LCDC Offset: 0x860) Interrupts Test Register -------- 
+// -------- LCDC_IRR : (LCDC Offset: 0x864) Interrupts Raw Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR HDMA Channel structure
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_HDMA_CH {
+	AT91C_REG	 HDMA_SADDR; 	// HDMA Channel Source Address Register
+	AT91C_REG	 HDMA_DADDR; 	// HDMA Channel Destination Address Register
+	AT91C_REG	 HDMA_DSCR; 	// HDMA Channel Descriptor Address Register
+	AT91C_REG	 HDMA_CTRLA; 	// HDMA Channel Control A Register
+	AT91C_REG	 HDMA_CTRLB; 	// HDMA Channel Control B Register
+	AT91C_REG	 HDMA_CFG; 	// HDMA Channel Configuration Register
+	AT91C_REG	 HDMA_SPIP; 	// HDMA Channel Source Picture in Picture Configuration Register
+	AT91C_REG	 HDMA_DPIP; 	// HDMA Channel Destination Picture in Picture Configuration Register
+	AT91C_REG	 HDMA_BDSCR; 	// HDMA Reserved
+	AT91C_REG	 HDMA_CADDR; 	// HDMA Reserved
+} AT91S_HDMA_CH, *AT91PS_HDMA_CH;
+#else
+#define HDMA_SADDR      (AT91C_CAST(AT91C_REG *) 	0x00000000) // (HDMA_SADDR) HDMA Channel Source Address Register
+#define HDMA_DADDR      (AT91C_CAST(AT91C_REG *) 	0x00000004) // (HDMA_DADDR) HDMA Channel Destination Address Register
+#define HDMA_DSCR       (AT91C_CAST(AT91C_REG *) 	0x00000008) // (HDMA_DSCR) HDMA Channel Descriptor Address Register
+#define HDMA_CTRLA      (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (HDMA_CTRLA) HDMA Channel Control A Register
+#define HDMA_CTRLB      (AT91C_CAST(AT91C_REG *) 	0x00000010) // (HDMA_CTRLB) HDMA Channel Control B Register
+#define HDMA_CFG        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (HDMA_CFG) HDMA Channel Configuration Register
+#define HDMA_SPIP       (AT91C_CAST(AT91C_REG *) 	0x00000018) // (HDMA_SPIP) HDMA Channel Source Picture in Picture Configuration Register
+#define HDMA_DPIP       (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (HDMA_DPIP) HDMA Channel Destination Picture in Picture Configuration Register
+#define HDMA_BDSCR      (AT91C_CAST(AT91C_REG *) 	0x00000020) // (HDMA_BDSCR) HDMA Reserved
+#define HDMA_CADDR      (AT91C_CAST(AT91C_REG *) 	0x00000024) // (HDMA_CADDR) HDMA Reserved
+
+#endif
+// -------- HDMA_SADDR : (HDMA_CH Offset: 0x0)  -------- 
+#define AT91C_SADDR           (0x0 <<  0) // (HDMA_CH) 
+// -------- HDMA_DADDR : (HDMA_CH Offset: 0x4)  -------- 
+#define AT91C_DADDR           (0x0 <<  0) // (HDMA_CH) 
+// -------- HDMA_DSCR : (HDMA_CH Offset: 0x8)  -------- 
+#define AT91C_HDMA_DSCR_IF    (0x3 <<  0) // (HDMA_CH) Select AHB-Lite Interface for current channel
+#define 	AT91C_HDMA_DSCR_IF_0                    (0x0) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 0.
+#define 	AT91C_HDMA_DSCR_IF_1                    (0x1) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 1.
+#define 	AT91C_HDMA_DSCR_IF_2                    (0x2) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 2.
+#define 	AT91C_HDMA_DSCR_IF_3                    (0x3) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 3.
+#define AT91C_HDMA_DSCR       (0x3FFFFFFF <<  2) // (HDMA_CH) Buffer Transfer descriptor address. This address is word aligned.
+// -------- HDMA_CTRLA : (HDMA_CH Offset: 0xc)  -------- 
+#define AT91C_HDMA_BTSIZE     (0xFFFF <<  0) // (HDMA_CH) Buffer Transfer Size.
+#define AT91C_HDMA_SCSIZE     (0x7 << 16) // (HDMA_CH) Source Chunk Transfer Size.
+#define 	AT91C_HDMA_SCSIZE_1                    (0x0 << 16) // (HDMA_CH) 1.
+#define 	AT91C_HDMA_SCSIZE_4                    (0x1 << 16) // (HDMA_CH) 4.
+#define 	AT91C_HDMA_SCSIZE_8                    (0x2 << 16) // (HDMA_CH) 8.
+#define 	AT91C_HDMA_SCSIZE_16                   (0x3 << 16) // (HDMA_CH) 16.
+#define 	AT91C_HDMA_SCSIZE_32                   (0x4 << 16) // (HDMA_CH) 32.
+#define 	AT91C_HDMA_SCSIZE_64                   (0x5 << 16) // (HDMA_CH) 64.
+#define 	AT91C_HDMA_SCSIZE_128                  (0x6 << 16) // (HDMA_CH) 128.
+#define 	AT91C_HDMA_SCSIZE_256                  (0x7 << 16) // (HDMA_CH) 256.
+#define AT91C_HDMA_DCSIZE     (0x7 << 20) // (HDMA_CH) Destination Chunk Transfer Size
+#define 	AT91C_HDMA_DCSIZE_1                    (0x0 << 20) // (HDMA_CH) 1.
+#define 	AT91C_HDMA_DCSIZE_4                    (0x1 << 20) // (HDMA_CH) 4.
+#define 	AT91C_HDMA_DCSIZE_8                    (0x2 << 20) // (HDMA_CH) 8.
+#define 	AT91C_HDMA_DCSIZE_16                   (0x3 << 20) // (HDMA_CH) 16.
+#define 	AT91C_HDMA_DCSIZE_32                   (0x4 << 20) // (HDMA_CH) 32.
+#define 	AT91C_HDMA_DCSIZE_64                   (0x5 << 20) // (HDMA_CH) 64.
+#define 	AT91C_HDMA_DCSIZE_128                  (0x6 << 20) // (HDMA_CH) 128.
+#define 	AT91C_HDMA_DCSIZE_256                  (0x7 << 20) // (HDMA_CH) 256.
+#define AT91C_HDMA_SRC_WIDTH  (0x3 << 24) // (HDMA_CH) Source Single Transfer Size
+#define 	AT91C_HDMA_SRC_WIDTH_BYTE                 (0x0 << 24) // (HDMA_CH) BYTE.
+#define 	AT91C_HDMA_SRC_WIDTH_HALFWORD             (0x1 << 24) // (HDMA_CH) HALF-WORD.
+#define 	AT91C_HDMA_SRC_WIDTH_WORD                 (0x2 << 24) // (HDMA_CH) WORD.
+#define AT91C_HDMA_DST_WIDTH  (0x3 << 28) // (HDMA_CH) Destination Single Transfer Size
+#define 	AT91C_HDMA_DST_WIDTH_BYTE                 (0x0 << 28) // (HDMA_CH) BYTE.
+#define 	AT91C_HDMA_DST_WIDTH_HALFWORD             (0x1 << 28) // (HDMA_CH) HALF-WORD.
+#define 	AT91C_HDMA_DST_WIDTH_WORD                 (0x2 << 28) // (HDMA_CH) WORD.
+#define AT91C_HDMA_DONE       (0x1 << 31) // (HDMA_CH) 
+// -------- HDMA_CTRLB : (HDMA_CH Offset: 0x10)  -------- 
+#define AT91C_HDMA_SIF        (0x3 <<  0) // (HDMA_CH) Source Interface Selection Field.
+#define 	AT91C_HDMA_SIF_0                    (0x0) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 0.
+#define 	AT91C_HDMA_SIF_1                    (0x1) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 1.
+#define 	AT91C_HDMA_SIF_2                    (0x2) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 2.
+#define 	AT91C_HDMA_SIF_3                    (0x3) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 3.
+#define AT91C_HDMA_DIF        (0x3 <<  4) // (HDMA_CH) Destination Interface Selection Field.
+#define 	AT91C_HDMA_DIF_0                    (0x0 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 0.
+#define 	AT91C_HDMA_DIF_1                    (0x1 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 1.
+#define 	AT91C_HDMA_DIF_2                    (0x2 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 2.
+#define 	AT91C_HDMA_DIF_3                    (0x3 <<  4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 3.
+#define AT91C_HDMA_SRC_PIP    (0x1 <<  8) // (HDMA_CH) Source Picture-in-Picture Mode
+#define 	AT91C_HDMA_SRC_PIP_DISABLE              (0x0 <<  8) // (HDMA_CH) Source Picture-in-Picture mode is disabled.
+#define 	AT91C_HDMA_SRC_PIP_ENABLE               (0x1 <<  8) // (HDMA_CH) Source Picture-in-Picture mode is enabled.
+#define AT91C_HDMA_DST_PIP    (0x1 << 12) // (HDMA_CH) Destination Picture-in-Picture Mode
+#define 	AT91C_HDMA_DST_PIP_DISABLE              (0x0 << 12) // (HDMA_CH) Destination Picture-in-Picture mode is disabled.
+#define 	AT91C_HDMA_DST_PIP_ENABLE               (0x1 << 12) // (HDMA_CH) Destination Picture-in-Picture mode is enabled.
+#define AT91C_HDMA_SRC_DSCR   (0x1 << 16) // (HDMA_CH) Source Buffer Descriptor Fetch operation
+#define 	AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM       (0x0 << 16) // (HDMA_CH) Source address is updated when the descriptor is fetched from the memory.
+#define 	AT91C_HDMA_SRC_DSCR_FETCH_DISABLE        (0x1 << 16) // (HDMA_CH) Buffer Descriptor Fetch operation is disabled for the Source.
+#define AT91C_HDMA_DST_DSCR   (0x1 << 20) // (HDMA_CH) Destination Buffer Descriptor operation
+#define 	AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM       (0x0 << 20) // (HDMA_CH) Destination address is updated when the descriptor is fetched from the memory.
+#define 	AT91C_HDMA_DST_DSCR_FETCH_DISABLE        (0x1 << 20) // (HDMA_CH) Buffer Descriptor Fetch operation is disabled for the destination.
+#define AT91C_HDMA_FC         (0x7 << 21) // (HDMA_CH) This field defines which devices controls the size of the buffer transfer, also referred as to the Flow Controller.
+#define 	AT91C_HDMA_FC_MEM2MEM              (0x0 << 21) // (HDMA_CH) Memory-to-Memory (DMA Controller).
+#define 	AT91C_HDMA_FC_MEM2PER              (0x1 << 21) // (HDMA_CH) Memory-to-Peripheral (DMA Controller).
+#define 	AT91C_HDMA_FC_PER2MEM              (0x2 << 21) // (HDMA_CH) Peripheral-to-Memory (DMA Controller).
+#define 	AT91C_HDMA_FC_PER2PER              (0x3 << 21) // (HDMA_CH) Peripheral-to-Peripheral (DMA Controller).
+#define 	AT91C_HDMA_FC_PER2MEM_PER          (0x4 << 21) // (HDMA_CH) Peripheral-to-Memory (Peripheral).
+#define 	AT91C_HDMA_FC_MEM2PER_PER          (0x5 << 21) // (HDMA_CH) Memory-to-Peripheral (Peripheral).
+#define 	AT91C_HDMA_FC_PER2PER_PER          (0x6 << 21) // (HDMA_CH) Peripheral-to-Peripheral (Source Peripheral).
+#define AT91C_HDMA_SRC_ADDRESS_MODE (0x3 << 24) // (HDMA_CH) Type of addressing mode
+#define 	AT91C_HDMA_SRC_ADDRESS_MODE_INCR                 (0x0 << 24) // (HDMA_CH) Incrementing Mode.
+#define 	AT91C_HDMA_SRC_ADDRESS_MODE_DECR                 (0x1 << 24) // (HDMA_CH) Decrementing Mode.
+#define 	AT91C_HDMA_SRC_ADDRESS_MODE_FIXED                (0x2 << 24) // (HDMA_CH) Fixed Mode.
+#define AT91C_HDMA_DST_ADDRESS_MODE (0x3 << 28) // (HDMA_CH) Type of addressing mode
+#define 	AT91C_HDMA_DST_ADDRESS_MODE_INCR                 (0x0 << 28) // (HDMA_CH) Incrementing Mode.
+#define 	AT91C_HDMA_DST_ADDRESS_MODE_DECR                 (0x1 << 28) // (HDMA_CH) Decrementing Mode.
+#define 	AT91C_HDMA_DST_ADDRESS_MODE_FIXED                (0x2 << 28) // (HDMA_CH) Fixed Mode.
+#define AT91C_HDMA_AUTO       (0x1 << 31) // (HDMA_CH) Automatic multiple buffer transfer enable
+#define 	AT91C_HDMA_AUTO_DISABLE              (0x0 << 31) // (HDMA_CH) Automatic multiple buffer transfer is disabled.
+#define 	AT91C_HDMA_AUTO_ENABLE               (0x1 << 31) // (HDMA_CH) Automatic multiple buffer transfer is enabled. This enables replay mode or contiguous mode when several buffers are transferred.
+// -------- HDMA_CFG : (HDMA_CH Offset: 0x14)  -------- 
+#define AT91C_HDMA_SRC_PER    (0xF <<  0) // (HDMA_CH) Channel Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.
+#define 	AT91C_HDMA_SRC_PER_0                    (0x0) // (HDMA_CH) HW Handshaking Interface number 0.
+#define 	AT91C_HDMA_SRC_PER_1                    (0x1) // (HDMA_CH) HW Handshaking Interface number 1.
+#define 	AT91C_HDMA_SRC_PER_2                    (0x2) // (HDMA_CH) HW Handshaking Interface number 2.
+#define 	AT91C_HDMA_SRC_PER_3                    (0x3) // (HDMA_CH) HW Handshaking Interface number 3.
+#define 	AT91C_HDMA_SRC_PER_4                    (0x4) // (HDMA_CH) HW Handshaking Interface number 4.
+#define 	AT91C_HDMA_SRC_PER_5                    (0x5) // (HDMA_CH) HW Handshaking Interface number 5.
+#define 	AT91C_HDMA_SRC_PER_6                    (0x6) // (HDMA_CH) HW Handshaking Interface number 6.
+#define 	AT91C_HDMA_SRC_PER_7                    (0x7) // (HDMA_CH) HW Handshaking Interface number 7.
+#define 	AT91C_HDMA_SRC_PER_8                    (0x8) // (HDMA_CH) HW Handshaking Interface number 8.
+#define 	AT91C_HDMA_SRC_PER_9                    (0x9) // (HDMA_CH) HW Handshaking Interface number 9.
+#define 	AT91C_HDMA_SRC_PER_10                   (0xA) // (HDMA_CH) HW Handshaking Interface number 10.
+#define 	AT91C_HDMA_SRC_PER_11                   (0xB) // (HDMA_CH) HW Handshaking Interface number 11.
+#define 	AT91C_HDMA_SRC_PER_12                   (0xC) // (HDMA_CH) HW Handshaking Interface number 12.
+#define 	AT91C_HDMA_SRC_PER_13                   (0xD) // (HDMA_CH) HW Handshaking Interface number 13.
+#define 	AT91C_HDMA_SRC_PER_14                   (0xE) // (HDMA_CH) HW Handshaking Interface number 14.
+#define 	AT91C_HDMA_SRC_PER_15                   (0xF) // (HDMA_CH) HW Handshaking Interface number 15.
+#define AT91C_HDMA_DST_PER    (0xF <<  4) // (HDMA_CH) Channel Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.
+#define 	AT91C_HDMA_DST_PER_0                    (0x0 <<  4) // (HDMA_CH) HW Handshaking Interface number 0.
+#define 	AT91C_HDMA_DST_PER_1                    (0x1 <<  4) // (HDMA_CH) HW Handshaking Interface number 1.
+#define 	AT91C_HDMA_DST_PER_2                    (0x2 <<  4) // (HDMA_CH) HW Handshaking Interface number 2.
+#define 	AT91C_HDMA_DST_PER_3                    (0x3 <<  4) // (HDMA_CH) HW Handshaking Interface number 3.
+#define 	AT91C_HDMA_DST_PER_4                    (0x4 <<  4) // (HDMA_CH) HW Handshaking Interface number 4.
+#define 	AT91C_HDMA_DST_PER_5                    (0x5 <<  4) // (HDMA_CH) HW Handshaking Interface number 5.
+#define 	AT91C_HDMA_DST_PER_6                    (0x6 <<  4) // (HDMA_CH) HW Handshaking Interface number 6.
+#define 	AT91C_HDMA_DST_PER_7                    (0x7 <<  4) // (HDMA_CH) HW Handshaking Interface number 7.
+#define 	AT91C_HDMA_DST_PER_8                    (0x8 <<  4) // (HDMA_CH) HW Handshaking Interface number 8.
+#define 	AT91C_HDMA_DST_PER_9                    (0x9 <<  4) // (HDMA_CH) HW Handshaking Interface number 9.
+#define 	AT91C_HDMA_DST_PER_10                   (0xA <<  4) // (HDMA_CH) HW Handshaking Interface number 10.
+#define 	AT91C_HDMA_DST_PER_11                   (0xB <<  4) // (HDMA_CH) HW Handshaking Interface number 11.
+#define 	AT91C_HDMA_DST_PER_12                   (0xC <<  4) // (HDMA_CH) HW Handshaking Interface number 12.
+#define 	AT91C_HDMA_DST_PER_13                   (0xD <<  4) // (HDMA_CH) HW Handshaking Interface number 13.
+#define 	AT91C_HDMA_DST_PER_14                   (0xE <<  4) // (HDMA_CH) HW Handshaking Interface number 14.
+#define 	AT91C_HDMA_DST_PER_15                   (0xF <<  4) // (HDMA_CH) HW Handshaking Interface number 15.
+#define AT91C_HDMA_SRC_REP    (0x1 <<  8) // (HDMA_CH) Source Replay Mode
+#define 	AT91C_HDMA_SRC_REP_CONTIGUOUS_ADDR      (0x0 <<  8) // (HDMA_CH) When automatic mode is activated, source address is contiguous between two buffers.
+#define 	AT91C_HDMA_SRC_REP_RELOAD_ADDR          (0x1 <<  8) // (HDMA_CH) When automatic mode is activated, the source address and the control register are reloaded from previous transfer..
+#define AT91C_HDMA_SRC_H2SEL  (0x1 <<  9) // (HDMA_CH) Source Handshaking Mode
+#define 	AT91C_HDMA_SRC_H2SEL_SW                   (0x0 <<  9) // (HDMA_CH) Software handshaking interface is used to trigger a transfer request.
+#define 	AT91C_HDMA_SRC_H2SEL_HW                   (0x1 <<  9) // (HDMA_CH) Hardware handshaking interface is used to trigger a transfer request.
+#define AT91C_HDMA_DST_REP    (0x1 << 12) // (HDMA_CH) Destination Replay Mode
+#define 	AT91C_HDMA_DST_REP_CONTIGUOUS_ADDR      (0x0 << 12) // (HDMA_CH) When automatic mode is activated, destination address is contiguous between two buffers.
+#define 	AT91C_HDMA_DST_REP_RELOAD_ADDR          (0x1 << 12) // (HDMA_CH) When automatic mode is activated, the destination address and the control register are reloaded from previous transfer..
+#define AT91C_HDMA_DST_H2SEL  (0x1 << 13) // (HDMA_CH) Destination Handshaking Mode
+#define 	AT91C_HDMA_DST_H2SEL_SW                   (0x0 << 13) // (HDMA_CH) Software handshaking interface is used to trigger a transfer request.
+#define 	AT91C_HDMA_DST_H2SEL_HW                   (0x1 << 13) // (HDMA_CH) Hardware handshaking interface is used to trigger a transfer request.
+#define AT91C_HDMA_SOD        (0x1 << 16) // (HDMA_CH) STOP ON DONE
+#define 	AT91C_HDMA_SOD_DISABLE              (0x0 << 16) // (HDMA_CH) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
+#define 	AT91C_HDMA_SOD_ENABLE               (0x1 << 16) // (HDMA_CH) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
+#define AT91C_HDMA_LOCK_IF    (0x1 << 20) // (HDMA_CH) Interface Lock
+#define 	AT91C_HDMA_LOCK_IF_DISABLE              (0x0 << 20) // (HDMA_CH) Interface Lock capability is disabled.
+#define 	AT91C_HDMA_LOCK_IF_ENABLE               (0x1 << 20) // (HDMA_CH) Interface Lock capability is enabled.
+#define AT91C_HDMA_LOCK_B     (0x1 << 21) // (HDMA_CH) AHB Bus Lock
+#define 	AT91C_HDMA_LOCK_B_DISABLE              (0x0 << 21) // (HDMA_CH) AHB Bus Locking capability is disabled.
+#define 	AT91C_HDMA_LOCK_B_ENABLE               (0x1 << 21) // (HDMA_CH) AHB Bus Locking capability is enabled.
+#define AT91C_HDMA_LOCK_IF_L  (0x1 << 22) // (HDMA_CH) Master Interface Arbiter Lock
+#define 	AT91C_HDMA_LOCK_IF_L_CHUNK                (0x0 << 22) // (HDMA_CH) The Master Interface Arbiter is locked by the channel x for a chunk transfer.
+#define 	AT91C_HDMA_LOCK_IF_L_BUFFER               (0x1 << 22) // (HDMA_CH) The Master Interface Arbiter is locked by the channel x for a buffer transfer.
+#define AT91C_HDMA_AHB_PROT   (0x7 << 24) // (HDMA_CH) AHB Prot
+#define AT91C_HDMA_FIFOCFG    (0x3 << 28) // (HDMA_CH) FIFO Request Configuration
+#define 	AT91C_HDMA_FIFOCFG_LARGESTBURST         (0x0 << 28) // (HDMA_CH) The largest defined length AHB burst is performed on the destination AHB interface.
+#define 	AT91C_HDMA_FIFOCFG_HALFFIFO             (0x1 << 28) // (HDMA_CH) When half fifo size is available/filled a source/destination request is serviced.
+#define 	AT91C_HDMA_FIFOCFG_ENOUGHSPACE          (0x2 << 28) // (HDMA_CH) When there is enough space/data available to perfom a single AHB access then the request is serviced.
+// -------- HDMA_SPIP : (HDMA_CH Offset: 0x18)  -------- 
+#define AT91C_SPIP_HOLE       (0xFFFF <<  0) // (HDMA_CH) This field indicates the value to add to the address when the programmable boundary has been reached.
+#define AT91C_SPIP_BOUNDARY   (0x3FF << 16) // (HDMA_CH) This field indicates the number of source transfers to perform before the automatic address increment operation.
+// -------- HDMA_DPIP : (HDMA_CH Offset: 0x1c)  -------- 
+#define AT91C_DPIP_HOLE       (0xFFFF <<  0) // (HDMA_CH) This field indicates the value to add to the address when the programmable boundary has been reached.
+#define AT91C_DPIP_BOUNDARY   (0x3FF << 16) // (HDMA_CH) This field indicates the number of source transfers to perform before the automatic address increment operation.
+// -------- HDMA_BDSCR : (HDMA_CH Offset: 0x20)  -------- 
+// -------- HDMA_CADDR : (HDMA_CH Offset: 0x24)  -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR HDMA controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_HDMA {
+	AT91C_REG	 HDMA_GCFG; 	// HDMA Global Configuration Register
+	AT91C_REG	 HDMA_EN; 	// HDMA Controller Enable Register
+	AT91C_REG	 HDMA_SREQ; 	// HDMA Software Single Request Register
+	AT91C_REG	 HDMA_CREQ; 	// HDMA Software Chunk Transfer Request Register
+	AT91C_REG	 HDMA_LAST; 	// HDMA Software Last Transfer Flag Register
+	AT91C_REG	 HDMA_SYNC; 	// HDMA Request Synchronization Register
+	AT91C_REG	 HDMA_EBCIER; 	// HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register
+	AT91C_REG	 HDMA_EBCIDR; 	// HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register
+	AT91C_REG	 HDMA_EBCIMR; 	// HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register
+	AT91C_REG	 HDMA_EBCISR; 	// HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register
+	AT91C_REG	 HDMA_CHER; 	// HDMA Channel Handler Enable Register
+	AT91C_REG	 HDMA_CHDR; 	// HDMA Channel Handler Disable Register
+	AT91C_REG	 HDMA_CHSR; 	// HDMA Channel Handler Status Register
+	AT91C_REG	 HDMA_RSVD0; 	// HDMA Reserved
+	AT91C_REG	 HDMA_RSVD1; 	// HDMA Reserved
+	AT91S_HDMA_CH	 HDMA_CH[8]; 	// HDMA Channel structure
+} AT91S_HDMA, *AT91PS_HDMA;
+#else
+#define HDMA_GCFG       (AT91C_CAST(AT91C_REG *) 	0x00000000) // (HDMA_GCFG) HDMA Global Configuration Register
+#define HDMA_EN         (AT91C_CAST(AT91C_REG *) 	0x00000004) // (HDMA_EN) HDMA Controller Enable Register
+#define HDMA_SREQ       (AT91C_CAST(AT91C_REG *) 	0x00000008) // (HDMA_SREQ) HDMA Software Single Request Register
+#define HDMA_CREQ       (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (HDMA_CREQ) HDMA Software Chunk Transfer Request Register
+#define HDMA_LAST       (AT91C_CAST(AT91C_REG *) 	0x00000010) // (HDMA_LAST) HDMA Software Last Transfer Flag Register
+#define HDMA_SYNC       (AT91C_CAST(AT91C_REG *) 	0x00000014) // (HDMA_SYNC) HDMA Request Synchronization Register
+#define HDMA_EBCIER     (AT91C_CAST(AT91C_REG *) 	0x00000018) // (HDMA_EBCIER) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register
+#define HDMA_EBCIDR     (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (HDMA_EBCIDR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register
+#define HDMA_EBCIMR     (AT91C_CAST(AT91C_REG *) 	0x00000020) // (HDMA_EBCIMR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register
+#define HDMA_EBCISR     (AT91C_CAST(AT91C_REG *) 	0x00000024) // (HDMA_EBCISR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register
+#define HDMA_CHER       (AT91C_CAST(AT91C_REG *) 	0x00000028) // (HDMA_CHER) HDMA Channel Handler Enable Register
+#define HDMA_CHDR       (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (HDMA_CHDR) HDMA Channel Handler Disable Register
+#define HDMA_CHSR       (AT91C_CAST(AT91C_REG *) 	0x00000030) // (HDMA_CHSR) HDMA Channel Handler Status Register
+#define HDMA_RSVD0      (AT91C_CAST(AT91C_REG *) 	0x00000034) // (HDMA_RSVD0) HDMA Reserved
+#define HDMA_RSVD1      (AT91C_CAST(AT91C_REG *) 	0x00000038) // (HDMA_RSVD1) HDMA Reserved
+
+#endif
+// -------- HDMA_GCFG : (HDMA Offset: 0x0)  -------- 
+#define AT91C_HDMA_IF0_BIGEND (0x1 <<  0) // (HDMA) AHB-Lite Interface 0 endian mode.
+#define 	AT91C_HDMA_IF0_BIGEND_IS_LITTLE_ENDIAN     (0x0) // (HDMA) AHB-Lite Interface 0 is little endian.
+#define 	AT91C_HDMA_IF0_BIGEND_IS_BIG_ENDIAN        (0x1) // (HDMA) AHB-Lite Interface 0 is big endian.
+#define AT91C_HDMA_IF1_BIGEND (0x1 <<  1) // (HDMA) AHB-Lite Interface 1 endian mode.
+#define 	AT91C_HDMA_IF1_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  1) // (HDMA) AHB-Lite Interface 1 is little endian.
+#define 	AT91C_HDMA_IF1_BIGEND_IS_BIG_ENDIAN        (0x1 <<  1) // (HDMA) AHB-Lite Interface 1 is big endian.
+#define AT91C_HDMA_IF2_BIGEND (0x1 <<  2) // (HDMA) AHB-Lite Interface 2 endian mode.
+#define 	AT91C_HDMA_IF2_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  2) // (HDMA) AHB-Lite Interface 2 is little endian.
+#define 	AT91C_HDMA_IF2_BIGEND_IS_BIG_ENDIAN        (0x1 <<  2) // (HDMA) AHB-Lite Interface 2 is big endian.
+#define AT91C_HDMA_IF3_BIGEND (0x1 <<  3) // (HDMA) AHB-Lite Interface 3 endian mode.
+#define 	AT91C_HDMA_IF3_BIGEND_IS_LITTLE_ENDIAN     (0x0 <<  3) // (HDMA) AHB-Lite Interface 3 is little endian.
+#define 	AT91C_HDMA_IF3_BIGEND_IS_BIG_ENDIAN        (0x1 <<  3) // (HDMA) AHB-Lite Interface 3 is big endian.
+#define AT91C_HDMA_ARB_CFG    (0x1 <<  4) // (HDMA) Arbiter mode.
+#define 	AT91C_HDMA_ARB_CFG_FIXED                (0x0 <<  4) // (HDMA) Fixed priority arbiter.
+#define 	AT91C_HDMA_ARB_CFG_ROUND_ROBIN          (0x1 <<  4) // (HDMA) Modified round robin arbiter.
+// -------- HDMA_EN : (HDMA Offset: 0x4)  -------- 
+#define AT91C_HDMA_ENABLE     (0x1 <<  0) // (HDMA) 
+#define 	AT91C_HDMA_ENABLE_DISABLE              (0x0) // (HDMA) Disables HDMA.
+#define 	AT91C_HDMA_ENABLE_ENABLE               (0x1) // (HDMA) Enables HDMA.
+// -------- HDMA_SREQ : (HDMA Offset: 0x8)  -------- 
+#define AT91C_HDMA_SSREQ0     (0x1 <<  0) // (HDMA) Request a source single transfer on channel 0
+#define 	AT91C_HDMA_SSREQ0_0                    (0x0) // (HDMA) No effect.
+#define 	AT91C_HDMA_SSREQ0_1                    (0x1) // (HDMA) Request a source single transfer on channel 0.
+#define AT91C_HDMA_DSREQ0     (0x1 <<  1) // (HDMA) Request a destination single transfer on channel 0
+#define 	AT91C_HDMA_DSREQ0_0                    (0x0 <<  1) // (HDMA) No effect.
+#define 	AT91C_HDMA_DSREQ0_1                    (0x1 <<  1) // (HDMA) Request a destination single transfer on channel 0.
+#define AT91C_HDMA_SSREQ1     (0x1 <<  2) // (HDMA) Request a source single transfer on channel 1
+#define 	AT91C_HDMA_SSREQ1_0                    (0x0 <<  2) // (HDMA) No effect.
+#define 	AT91C_HDMA_SSREQ1_1                    (0x1 <<  2) // (HDMA) Request a source single transfer on channel 1.
+#define AT91C_HDMA_DSREQ1     (0x1 <<  3) // (HDMA) Request a destination single transfer on channel 1
+#define 	AT91C_HDMA_DSREQ1_0                    (0x0 <<  3) // (HDMA) No effect.
+#define 	AT91C_HDMA_DSREQ1_1                    (0x1 <<  3) // (HDMA) Request a destination single transfer on channel 1.
+#define AT91C_HDMA_SSREQ2     (0x1 <<  4) // (HDMA) Request a source single transfer on channel 2
+#define 	AT91C_HDMA_SSREQ2_0                    (0x0 <<  4) // (HDMA) No effect.
+#define 	AT91C_HDMA_SSREQ2_1                    (0x1 <<  4) // (HDMA) Request a source single transfer on channel 2.
+#define AT91C_HDMA_DSREQ2     (0x1 <<  5) // (HDMA) Request a destination single transfer on channel 2
+#define 	AT91C_HDMA_DSREQ2_0                    (0x0 <<  5) // (HDMA) No effect.
+#define 	AT91C_HDMA_DSREQ2_1                    (0x1 <<  5) // (HDMA) Request a destination single transfer on channel 2.
+#define AT91C_HDMA_SSREQ3     (0x1 <<  6) // (HDMA) Request a source single transfer on channel 3
+#define 	AT91C_HDMA_SSREQ3_0                    (0x0 <<  6) // (HDMA) No effect.
+#define 	AT91C_HDMA_SSREQ3_1                    (0x1 <<  6) // (HDMA) Request a source single transfer on channel 3.
+#define AT91C_HDMA_DSREQ3     (0x1 <<  7) // (HDMA) Request a destination single transfer on channel 3
+#define 	AT91C_HDMA_DSREQ3_0                    (0x0 <<  7) // (HDMA) No effect.
+#define 	AT91C_HDMA_DSREQ3_1                    (0x1 <<  7) // (HDMA) Request a destination single transfer on channel 3.
+#define AT91C_HDMA_SSREQ4     (0x1 <<  8) // (HDMA) Request a source single transfer on channel 4
+#define 	AT91C_HDMA_SSREQ4_0                    (0x0 <<  8) // (HDMA) No effect.
+#define 	AT91C_HDMA_SSREQ4_1                    (0x1 <<  8) // (HDMA) Request a source single transfer on channel 4.
+#define AT91C_HDMA_DSREQ4     (0x1 <<  9) // (HDMA) Request a destination single transfer on channel 4
+#define 	AT91C_HDMA_DSREQ4_0                    (0x0 <<  9) // (HDMA) No effect.
+#define 	AT91C_HDMA_DSREQ4_1                    (0x1 <<  9) // (HDMA) Request a destination single transfer on channel 4.
+#define AT91C_HDMA_SSREQ5     (0x1 << 10) // (HDMA) Request a source single transfer on channel 5
+#define 	AT91C_HDMA_SSREQ5_0                    (0x0 << 10) // (HDMA) No effect.
+#define 	AT91C_HDMA_SSREQ5_1                    (0x1 << 10) // (HDMA) Request a source single transfer on channel 5.
+#define AT91C_HDMA_DSREQ6     (0x1 << 11) // (HDMA) Request a destination single transfer on channel 5
+#define 	AT91C_HDMA_DSREQ6_0                    (0x0 << 11) // (HDMA) No effect.
+#define 	AT91C_HDMA_DSREQ6_1                    (0x1 << 11) // (HDMA) Request a destination single transfer on channel 5.
+#define AT91C_HDMA_SSREQ6     (0x1 << 12) // (HDMA) Request a source single transfer on channel 6
+#define 	AT91C_HDMA_SSREQ6_0                    (0x0 << 12) // (HDMA) No effect.
+#define 	AT91C_HDMA_SSREQ6_1                    (0x1 << 12) // (HDMA) Request a source single transfer on channel 6.
+#define AT91C_HDMA_SSREQ7     (0x1 << 14) // (HDMA) Request a source single transfer on channel 7
+#define 	AT91C_HDMA_SSREQ7_0                    (0x0 << 14) // (HDMA) No effect.
+#define 	AT91C_HDMA_SSREQ7_1                    (0x1 << 14) // (HDMA) Request a source single transfer on channel 7.
+#define AT91C_HDMA_DSREQ7     (0x1 << 15) // (HDMA) Request a destination single transfer on channel 7
+#define 	AT91C_HDMA_DSREQ7_0                    (0x0 << 15) // (HDMA) No effect.
+#define 	AT91C_HDMA_DSREQ7_1                    (0x1 << 15) // (HDMA) Request a destination single transfer on channel 7.
+// -------- HDMA_CREQ : (HDMA Offset: 0xc)  -------- 
+#define AT91C_HDMA_SCREQ0     (0x1 <<  0) // (HDMA) Request a source chunk transfer on channel 0
+#define 	AT91C_HDMA_SCREQ0_0                    (0x0) // (HDMA) No effect.
+#define 	AT91C_HDMA_SCREQ0_1                    (0x1) // (HDMA) Request a source chunk transfer on channel 0.
+#define AT91C_HDMA_DCREQ0     (0x1 <<  1) // (HDMA) Request a destination chunk transfer on channel 0
+#define 	AT91C_HDMA_DCREQ0_0                    (0x0 <<  1) // (HDMA) No effect.
+#define 	AT91C_HDMA_DCREQ0_1                    (0x1 <<  1) // (HDMA) Request a destination chunk transfer on channel 0.
+#define AT91C_HDMA_SCREQ1     (0x1 <<  2) // (HDMA) Request a source chunk transfer on channel 1
+#define 	AT91C_HDMA_SCREQ1_0                    (0x0 <<  2) // (HDMA) No effect.
+#define 	AT91C_HDMA_SCREQ1_1                    (0x1 <<  2) // (HDMA) Request a source chunk transfer on channel 1.
+#define AT91C_HDMA_DCREQ1     (0x1 <<  3) // (HDMA) Request a destination chunk transfer on channel 1
+#define 	AT91C_HDMA_DCREQ1_0                    (0x0 <<  3) // (HDMA) No effect.
+#define 	AT91C_HDMA_DCREQ1_1                    (0x1 <<  3) // (HDMA) Request a destination chunk transfer on channel 1.
+#define AT91C_HDMA_SCREQ2     (0x1 <<  4) // (HDMA) Request a source chunk transfer on channel 2
+#define 	AT91C_HDMA_SCREQ2_0                    (0x0 <<  4) // (HDMA) No effect.
+#define 	AT91C_HDMA_SCREQ2_1                    (0x1 <<  4) // (HDMA) Request a source chunk transfer on channel 2.
+#define AT91C_HDMA_DCREQ2     (0x1 <<  5) // (HDMA) Request a destination chunk transfer on channel 2
+#define 	AT91C_HDMA_DCREQ2_0                    (0x0 <<  5) // (HDMA) No effect.
+#define 	AT91C_HDMA_DCREQ2_1                    (0x1 <<  5) // (HDMA) Request a destination chunk transfer on channel 2.
+#define AT91C_HDMA_SCREQ3     (0x1 <<  6) // (HDMA) Request a source chunk transfer on channel 3
+#define 	AT91C_HDMA_SCREQ3_0                    (0x0 <<  6) // (HDMA) No effect.
+#define 	AT91C_HDMA_SCREQ3_1                    (0x1 <<  6) // (HDMA) Request a source chunk transfer on channel 3.
+#define AT91C_HDMA_DCREQ3     (0x1 <<  7) // (HDMA) Request a destination chunk transfer on channel 3
+#define 	AT91C_HDMA_DCREQ3_0                    (0x0 <<  7) // (HDMA) No effect.
+#define 	AT91C_HDMA_DCREQ3_1                    (0x1 <<  7) // (HDMA) Request a destination chunk transfer on channel 3.
+#define AT91C_HDMA_SCREQ4     (0x1 <<  8) // (HDMA) Request a source chunk transfer on channel 4
+#define 	AT91C_HDMA_SCREQ4_0                    (0x0 <<  8) // (HDMA) No effect.
+#define 	AT91C_HDMA_SCREQ4_1                    (0x1 <<  8) // (HDMA) Request a source chunk transfer on channel 4.
+#define AT91C_HDMA_DCREQ4     (0x1 <<  9) // (HDMA) Request a destination chunk transfer on channel 4
+#define 	AT91C_HDMA_DCREQ4_0                    (0x0 <<  9) // (HDMA) No effect.
+#define 	AT91C_HDMA_DCREQ4_1                    (0x1 <<  9) // (HDMA) Request a destination chunk transfer on channel 4.
+#define AT91C_HDMA_SCREQ5     (0x1 << 10) // (HDMA) Request a source chunk transfer on channel 5
+#define 	AT91C_HDMA_SCREQ5_0                    (0x0 << 10) // (HDMA) No effect.
+#define 	AT91C_HDMA_SCREQ5_1                    (0x1 << 10) // (HDMA) Request a source chunk transfer on channel 5.
+#define AT91C_HDMA_DCREQ6     (0x1 << 11) // (HDMA) Request a destination chunk transfer on channel 5
+#define 	AT91C_HDMA_DCREQ6_0                    (0x0 << 11) // (HDMA) No effect.
+#define 	AT91C_HDMA_DCREQ6_1                    (0x1 << 11) // (HDMA) Request a destination chunk transfer on channel 5.
+#define AT91C_HDMA_SCREQ6     (0x1 << 12) // (HDMA) Request a source chunk transfer on channel 6
+#define 	AT91C_HDMA_SCREQ6_0                    (0x0 << 12) // (HDMA) No effect.
+#define 	AT91C_HDMA_SCREQ6_1                    (0x1 << 12) // (HDMA) Request a source chunk transfer on channel 6.
+#define AT91C_HDMA_SCREQ7     (0x1 << 14) // (HDMA) Request a source chunk transfer on channel 7
+#define 	AT91C_HDMA_SCREQ7_0                    (0x0 << 14) // (HDMA) No effect.
+#define 	AT91C_HDMA_SCREQ7_1                    (0x1 << 14) // (HDMA) Request a source chunk transfer on channel 7.
+#define AT91C_HDMA_DCREQ7     (0x1 << 15) // (HDMA) Request a destination chunk transfer on channel 7
+#define 	AT91C_HDMA_DCREQ7_0                    (0x0 << 15) // (HDMA) No effect.
+#define 	AT91C_HDMA_DCREQ7_1                    (0x1 << 15) // (HDMA) Request a destination chunk transfer on channel 7.
+// -------- HDMA_LAST : (HDMA Offset: 0x10)  -------- 
+#define AT91C_HDMA_SLAST0     (0x1 <<  0) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 0
+#define 	AT91C_HDMA_SLAST0_0                    (0x0) // (HDMA) No effect.
+#define 	AT91C_HDMA_SLAST0_1                    (0x1) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 0.
+#define AT91C_HDMA_DLAST0     (0x1 <<  1) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 0
+#define 	AT91C_HDMA_DLAST0_0                    (0x0 <<  1) // (HDMA) No effect.
+#define 	AT91C_HDMA_DLAST0_1                    (0x1 <<  1) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 0.
+#define AT91C_HDMA_SLAST1     (0x1 <<  2) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 1
+#define 	AT91C_HDMA_SLAST1_0                    (0x0 <<  2) // (HDMA) No effect.
+#define 	AT91C_HDMA_SLAST1_1                    (0x1 <<  2) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 1.
+#define AT91C_HDMA_DLAST1     (0x1 <<  3) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 1
+#define 	AT91C_HDMA_DLAST1_0                    (0x0 <<  3) // (HDMA) No effect.
+#define 	AT91C_HDMA_DLAST1_1                    (0x1 <<  3) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 1.
+#define AT91C_HDMA_SLAST2     (0x1 <<  4) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 2
+#define 	AT91C_HDMA_SLAST2_0                    (0x0 <<  4) // (HDMA) No effect.
+#define 	AT91C_HDMA_SLAST2_1                    (0x1 <<  4) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 2.
+#define AT91C_HDMA_DLAST2     (0x1 <<  5) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 2
+#define 	AT91C_HDMA_DLAST2_0                    (0x0 <<  5) // (HDMA) No effect.
+#define 	AT91C_HDMA_DLAST2_1                    (0x1 <<  5) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 2.
+#define AT91C_HDMA_SLAST3     (0x1 <<  6) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 3
+#define 	AT91C_HDMA_SLAST3_0                    (0x0 <<  6) // (HDMA) No effect.
+#define 	AT91C_HDMA_SLAST3_1                    (0x1 <<  6) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 3.
+#define AT91C_HDMA_DLAST3     (0x1 <<  7) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 3
+#define 	AT91C_HDMA_DLAST3_0                    (0x0 <<  7) // (HDMA) No effect.
+#define 	AT91C_HDMA_DLAST3_1                    (0x1 <<  7) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 3.
+#define AT91C_HDMA_SLAST4     (0x1 <<  8) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 4
+#define 	AT91C_HDMA_SLAST4_0                    (0x0 <<  8) // (HDMA) No effect.
+#define 	AT91C_HDMA_SLAST4_1                    (0x1 <<  8) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 4.
+#define AT91C_HDMA_DLAST4     (0x1 <<  9) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 4
+#define 	AT91C_HDMA_DLAST4_0                    (0x0 <<  9) // (HDMA) No effect.
+#define 	AT91C_HDMA_DLAST4_1                    (0x1 <<  9) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 4.
+#define AT91C_HDMA_SLAST5     (0x1 << 10) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 5
+#define 	AT91C_HDMA_SLAST5_0                    (0x0 << 10) // (HDMA) No effect.
+#define 	AT91C_HDMA_SLAST5_1                    (0x1 << 10) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 5.
+#define AT91C_HDMA_DLAST6     (0x1 << 11) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 5
+#define 	AT91C_HDMA_DLAST6_0                    (0x0 << 11) // (HDMA) No effect.
+#define 	AT91C_HDMA_DLAST6_1                    (0x1 << 11) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 5.
+#define AT91C_HDMA_SLAST6     (0x1 << 12) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 6
+#define 	AT91C_HDMA_SLAST6_0                    (0x0 << 12) // (HDMA) No effect.
+#define 	AT91C_HDMA_SLAST6_1                    (0x1 << 12) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 6.
+#define AT91C_HDMA_SLAST7     (0x1 << 14) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 7
+#define 	AT91C_HDMA_SLAST7_0                    (0x0 << 14) // (HDMA) No effect.
+#define 	AT91C_HDMA_SLAST7_1                    (0x1 << 14) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 7.
+#define AT91C_HDMA_DLAST7     (0x1 << 15) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 7
+#define 	AT91C_HDMA_DLAST7_0                    (0x0 << 15) // (HDMA) No effect.
+#define 	AT91C_HDMA_DLAST7_1                    (0x1 << 15) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 7.
+// -------- HDMA_SYNC : (HDMA Offset: 0x14)  -------- 
+#define AT91C_SYNC_REQ        (0xFFFF <<  0) // (HDMA) 
+// -------- HDMA_EBCIER : (HDMA Offset: 0x18) Buffer Transfer Completed/Chained Buffer Transfer Completed/Access Error Interrupt Enable Register -------- 
+#define AT91C_HDMA_BTC0       (0x1 <<  0) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_BTC1       (0x1 <<  1) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_BTC2       (0x1 <<  2) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_BTC3       (0x1 <<  3) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_BTC4       (0x1 <<  4) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_BTC5       (0x1 <<  5) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_BTC6       (0x1 <<  6) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_BTC7       (0x1 <<  7) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_CBTC0      (0x1 <<  8) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_CBTC1      (0x1 <<  9) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_CBTC2      (0x1 << 10) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_CBTC3      (0x1 << 11) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_CBTC4      (0x1 << 12) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_CBTC5      (0x1 << 13) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_CBTC6      (0x1 << 14) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_CBTC7      (0x1 << 15) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_ERR0       (0x1 << 16) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_ERR1       (0x1 << 17) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_ERR2       (0x1 << 18) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_ERR3       (0x1 << 19) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_ERR4       (0x1 << 20) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_ERR5       (0x1 << 21) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_ERR6       (0x1 << 22) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register
+#define AT91C_HDMA_ERR7       (0x1 << 23) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register
+// -------- HDMA_EBCIDR : (HDMA Offset: 0x1c)  -------- 
+// -------- HDMA_EBCIMR : (HDMA Offset: 0x20)  -------- 
+// -------- HDMA_EBCISR : (HDMA Offset: 0x24)  -------- 
+// -------- HDMA_CHER : (HDMA Offset: 0x28)  -------- 
+#define AT91C_HDMA_ENA0       (0x1 <<  0) // (HDMA) When set, channel 0 enabled.
+#define 	AT91C_HDMA_ENA0_0                    (0x0) // (HDMA) No effect.
+#define 	AT91C_HDMA_ENA0_1                    (0x1) // (HDMA) Channel 0 enabled.
+#define AT91C_HDMA_ENA1       (0x1 <<  1) // (HDMA) When set, channel 1 enabled.
+#define 	AT91C_HDMA_ENA1_0                    (0x0 <<  1) // (HDMA) No effect.
+#define 	AT91C_HDMA_ENA1_1                    (0x1 <<  1) // (HDMA) Channel 1 enabled.
+#define AT91C_HDMA_ENA2       (0x1 <<  2) // (HDMA) When set, channel 2 enabled.
+#define 	AT91C_HDMA_ENA2_0                    (0x0 <<  2) // (HDMA) No effect.
+#define 	AT91C_HDMA_ENA2_1                    (0x1 <<  2) // (HDMA) Channel 2 enabled.
+#define AT91C_HDMA_ENA3       (0x1 <<  3) // (HDMA) When set, channel 3 enabled.
+#define 	AT91C_HDMA_ENA3_0                    (0x0 <<  3) // (HDMA) No effect.
+#define 	AT91C_HDMA_ENA3_1                    (0x1 <<  3) // (HDMA) Channel 3 enabled.
+#define AT91C_HDMA_ENA4       (0x1 <<  4) // (HDMA) When set, channel 4 enabled.
+#define 	AT91C_HDMA_ENA4_0                    (0x0 <<  4) // (HDMA) No effect.
+#define 	AT91C_HDMA_ENA4_1                    (0x1 <<  4) // (HDMA) Channel 4 enabled.
+#define AT91C_HDMA_ENA5       (0x1 <<  5) // (HDMA) When set, channel 5 enabled.
+#define 	AT91C_HDMA_ENA5_0                    (0x0 <<  5) // (HDMA) No effect.
+#define 	AT91C_HDMA_ENA5_1                    (0x1 <<  5) // (HDMA) Channel 5 enabled.
+#define AT91C_HDMA_ENA6       (0x1 <<  6) // (HDMA) When set, channel 6 enabled.
+#define 	AT91C_HDMA_ENA6_0                    (0x0 <<  6) // (HDMA) No effect.
+#define 	AT91C_HDMA_ENA6_1                    (0x1 <<  6) // (HDMA) Channel 6 enabled.
+#define AT91C_HDMA_ENA7       (0x1 <<  7) // (HDMA) When set, channel 7 enabled.
+#define 	AT91C_HDMA_ENA7_0                    (0x0 <<  7) // (HDMA) No effect.
+#define 	AT91C_HDMA_ENA7_1                    (0x1 <<  7) // (HDMA) Channel 7 enabled.
+#define AT91C_HDMA_SUSP0      (0x1 <<  8) // (HDMA) When set, channel 0 freezed and its current context.
+#define 	AT91C_HDMA_SUSP0_0                    (0x0 <<  8) // (HDMA) No effect.
+#define 	AT91C_HDMA_SUSP0_1                    (0x1 <<  8) // (HDMA) Channel 0 freezed.
+#define AT91C_HDMA_SUSP1      (0x1 <<  9) // (HDMA) When set, channel 1 freezed and its current context.
+#define 	AT91C_HDMA_SUSP1_0                    (0x0 <<  9) // (HDMA) No effect.
+#define 	AT91C_HDMA_SUSP1_1                    (0x1 <<  9) // (HDMA) Channel 1 freezed.
+#define AT91C_HDMA_SUSP2      (0x1 << 10) // (HDMA) When set, channel 2 freezed and its current context.
+#define 	AT91C_HDMA_SUSP2_0                    (0x0 << 10) // (HDMA) No effect.
+#define 	AT91C_HDMA_SUSP2_1                    (0x1 << 10) // (HDMA) Channel 2 freezed.
+#define AT91C_HDMA_SUSP3      (0x1 << 11) // (HDMA) When set, channel 3 freezed and its current context.
+#define 	AT91C_HDMA_SUSP3_0                    (0x0 << 11) // (HDMA) No effect.
+#define 	AT91C_HDMA_SUSP3_1                    (0x1 << 11) // (HDMA) Channel 3 freezed.
+#define AT91C_HDMA_SUSP4      (0x1 << 12) // (HDMA) When set, channel 4 freezed and its current context.
+#define 	AT91C_HDMA_SUSP4_0                    (0x0 << 12) // (HDMA) No effect.
+#define 	AT91C_HDMA_SUSP4_1                    (0x1 << 12) // (HDMA) Channel 4 freezed.
+#define AT91C_HDMA_SUSP5      (0x1 << 13) // (HDMA) When set, channel 5 freezed and its current context.
+#define 	AT91C_HDMA_SUSP5_0                    (0x0 << 13) // (HDMA) No effect.
+#define 	AT91C_HDMA_SUSP5_1                    (0x1 << 13) // (HDMA) Channel 5 freezed.
+#define AT91C_HDMA_SUSP6      (0x1 << 14) // (HDMA) When set, channel 6 freezed and its current context.
+#define 	AT91C_HDMA_SUSP6_0                    (0x0 << 14) // (HDMA) No effect.
+#define 	AT91C_HDMA_SUSP6_1                    (0x1 << 14) // (HDMA) Channel 6 freezed.
+#define AT91C_HDMA_SUSP7      (0x1 << 15) // (HDMA) When set, channel 7 freezed and its current context.
+#define 	AT91C_HDMA_SUSP7_0                    (0x0 << 15) // (HDMA) No effect.
+#define 	AT91C_HDMA_SUSP7_1                    (0x1 << 15) // (HDMA) Channel 7 freezed.
+#define AT91C_HDMA_KEEP0      (0x1 << 24) // (HDMA) When set, it resumes the channel 0 from an automatic stall state.
+#define 	AT91C_HDMA_KEEP0_0                    (0x0 << 24) // (HDMA) No effect.
+#define 	AT91C_HDMA_KEEP0_1                    (0x1 << 24) // (HDMA) Resumes the channel 0.
+#define AT91C_HDMA_KEEP1      (0x1 << 25) // (HDMA) When set, it resumes the channel 1 from an automatic stall state.
+#define 	AT91C_HDMA_KEEP1_0                    (0x0 << 25) // (HDMA) No effect.
+#define 	AT91C_HDMA_KEEP1_1                    (0x1 << 25) // (HDMA) Resumes the channel 1.
+#define AT91C_HDMA_KEEP2      (0x1 << 26) // (HDMA) When set, it resumes the channel 2 from an automatic stall state.
+#define 	AT91C_HDMA_KEEP2_0                    (0x0 << 26) // (HDMA) No effect.
+#define 	AT91C_HDMA_KEEP2_1                    (0x1 << 26) // (HDMA) Resumes the channel 2.
+#define AT91C_HDMA_KEEP3      (0x1 << 27) // (HDMA) When set, it resumes the channel 3 from an automatic stall state.
+#define 	AT91C_HDMA_KEEP3_0                    (0x0 << 27) // (HDMA) No effect.
+#define 	AT91C_HDMA_KEEP3_1                    (0x1 << 27) // (HDMA) Resumes the channel 3.
+#define AT91C_HDMA_KEEP4      (0x1 << 28) // (HDMA) When set, it resumes the channel 4 from an automatic stall state.
+#define 	AT91C_HDMA_KEEP4_0                    (0x0 << 28) // (HDMA) No effect.
+#define 	AT91C_HDMA_KEEP4_1                    (0x1 << 28) // (HDMA) Resumes the channel 4.
+#define AT91C_HDMA_KEEP5      (0x1 << 29) // (HDMA) When set, it resumes the channel 5 from an automatic stall state.
+#define 	AT91C_HDMA_KEEP5_0                    (0x0 << 29) // (HDMA) No effect.
+#define 	AT91C_HDMA_KEEP5_1                    (0x1 << 29) // (HDMA) Resumes the channel 5.
+#define AT91C_HDMA_KEEP6      (0x1 << 30) // (HDMA) When set, it resumes the channel 6 from an automatic stall state.
+#define 	AT91C_HDMA_KEEP6_0                    (0x0 << 30) // (HDMA) No effect.
+#define 	AT91C_HDMA_KEEP6_1                    (0x1 << 30) // (HDMA) Resumes the channel 6.
+#define AT91C_HDMA_KEEP7      (0x1 << 31) // (HDMA) When set, it resumes the channel 7 from an automatic stall state.
+#define 	AT91C_HDMA_KEEP7_0                    (0x0 << 31) // (HDMA) No effect.
+#define 	AT91C_HDMA_KEEP7_1                    (0x1 << 31) // (HDMA) Resumes the channel 7.
+// -------- HDMA_CHDR : (HDMA Offset: 0x2c)  -------- 
+#define AT91C_HDMA_DIS0       (0x1 <<  0) // (HDMA) Write one to this field to disable the channel 0.
+#define 	AT91C_HDMA_DIS0_0                    (0x0) // (HDMA) No effect.
+#define 	AT91C_HDMA_DIS0_1                    (0x1) // (HDMA) Disables the channel 0.
+#define AT91C_HDMA_DIS1       (0x1 <<  1) // (HDMA) Write one to this field to disable the channel 1.
+#define 	AT91C_HDMA_DIS1_0                    (0x0 <<  1) // (HDMA) No effect.
+#define 	AT91C_HDMA_DIS1_1                    (0x1 <<  1) // (HDMA) Disables the channel 1.
+#define AT91C_HDMA_DIS2       (0x1 <<  2) // (HDMA) Write one to this field to disable the channel 2.
+#define 	AT91C_HDMA_DIS2_0                    (0x0 <<  2) // (HDMA) No effect.
+#define 	AT91C_HDMA_DIS2_1                    (0x1 <<  2) // (HDMA) Disables the channel 2.
+#define AT91C_HDMA_DIS3       (0x1 <<  3) // (HDMA) Write one to this field to disable the channel 3.
+#define 	AT91C_HDMA_DIS3_0                    (0x0 <<  3) // (HDMA) No effect.
+#define 	AT91C_HDMA_DIS3_1                    (0x1 <<  3) // (HDMA) Disables the channel 3.
+#define AT91C_HDMA_DIS4       (0x1 <<  4) // (HDMA) Write one to this field to disable the channel 4.
+#define 	AT91C_HDMA_DIS4_0                    (0x0 <<  4) // (HDMA) No effect.
+#define 	AT91C_HDMA_DIS4_1                    (0x1 <<  4) // (HDMA) Disables the channel 4.
+#define AT91C_HDMA_DIS5       (0x1 <<  5) // (HDMA) Write one to this field to disable the channel 5.
+#define 	AT91C_HDMA_DIS5_0                    (0x0 <<  5) // (HDMA) No effect.
+#define 	AT91C_HDMA_DIS5_1                    (0x1 <<  5) // (HDMA) Disables the channel 5.
+#define AT91C_HDMA_DIS6       (0x1 <<  6) // (HDMA) Write one to this field to disable the channel 6.
+#define 	AT91C_HDMA_DIS6_0                    (0x0 <<  6) // (HDMA) No effect.
+#define 	AT91C_HDMA_DIS6_1                    (0x1 <<  6) // (HDMA) Disables the channel 6.
+#define AT91C_HDMA_DIS7       (0x1 <<  7) // (HDMA) Write one to this field to disable the channel 7.
+#define 	AT91C_HDMA_DIS7_0                    (0x0 <<  7) // (HDMA) No effect.
+#define 	AT91C_HDMA_DIS7_1                    (0x1 <<  7) // (HDMA) Disables the channel 7.
+#define AT91C_HDMA_RES0       (0x1 <<  8) // (HDMA) Write one to this field to resume the channel 0 transfer restoring its context.
+#define 	AT91C_HDMA_RES0_0                    (0x0 <<  8) // (HDMA) No effect.
+#define 	AT91C_HDMA_RES0_1                    (0x1 <<  8) // (HDMA) Resumes the channel 0.
+#define AT91C_HDMA_RES1       (0x1 <<  9) // (HDMA) Write one to this field to resume the channel 1 transfer restoring its context.
+#define 	AT91C_HDMA_RES1_0                    (0x0 <<  9) // (HDMA) No effect.
+#define 	AT91C_HDMA_RES1_1                    (0x1 <<  9) // (HDMA) Resumes the channel 1.
+#define AT91C_HDMA_RES2       (0x1 << 10) // (HDMA) Write one to this field to resume the channel 2 transfer restoring its context.
+#define 	AT91C_HDMA_RES2_0                    (0x0 << 10) // (HDMA) No effect.
+#define 	AT91C_HDMA_RES2_1                    (0x1 << 10) // (HDMA) Resumes the channel 2.
+#define AT91C_HDMA_RES3       (0x1 << 11) // (HDMA) Write one to this field to resume the channel 3 transfer restoring its context.
+#define 	AT91C_HDMA_RES3_0                    (0x0 << 11) // (HDMA) No effect.
+#define 	AT91C_HDMA_RES3_1                    (0x1 << 11) // (HDMA) Resumes the channel 3.
+#define AT91C_HDMA_RES4       (0x1 << 12) // (HDMA) Write one to this field to resume the channel 4 transfer restoring its context.
+#define 	AT91C_HDMA_RES4_0                    (0x0 << 12) // (HDMA) No effect.
+#define 	AT91C_HDMA_RES4_1                    (0x1 << 12) // (HDMA) Resumes the channel 4.
+#define AT91C_HDMA_RES5       (0x1 << 13) // (HDMA) Write one to this field to resume the channel 5 transfer restoring its context.
+#define 	AT91C_HDMA_RES5_0                    (0x0 << 13) // (HDMA) No effect.
+#define 	AT91C_HDMA_RES5_1                    (0x1 << 13) // (HDMA) Resumes the channel 5.
+#define AT91C_HDMA_RES6       (0x1 << 14) // (HDMA) Write one to this field to resume the channel 6 transfer restoring its context.
+#define 	AT91C_HDMA_RES6_0                    (0x0 << 14) // (HDMA) No effect.
+#define 	AT91C_HDMA_RES6_1                    (0x1 << 14) // (HDMA) Resumes the channel 6.
+#define AT91C_HDMA_RES7       (0x1 << 15) // (HDMA) Write one to this field to resume the channel 7 transfer restoring its context.
+#define 	AT91C_HDMA_RES7_0                    (0x0 << 15) // (HDMA) No effect.
+#define 	AT91C_HDMA_RES7_1                    (0x1 << 15) // (HDMA) Resumes the channel 7.
+// -------- HDMA_CHSR : (HDMA Offset: 0x30)  -------- 
+#define AT91C_HDMA_EMPT0      (0x1 << 16) // (HDMA) When set, channel 0 is empty.
+#define 	AT91C_HDMA_EMPT0_0                    (0x0 << 16) // (HDMA) No effect.
+#define 	AT91C_HDMA_EMPT0_1                    (0x1 << 16) // (HDMA) Channel 0 empty.
+#define AT91C_HDMA_EMPT1      (0x1 << 17) // (HDMA) When set, channel 1 is empty.
+#define 	AT91C_HDMA_EMPT1_0                    (0x0 << 17) // (HDMA) No effect.
+#define 	AT91C_HDMA_EMPT1_1                    (0x1 << 17) // (HDMA) Channel 1 empty.
+#define AT91C_HDMA_EMPT2      (0x1 << 18) // (HDMA) When set, channel 2 is empty.
+#define 	AT91C_HDMA_EMPT2_0                    (0x0 << 18) // (HDMA) No effect.
+#define 	AT91C_HDMA_EMPT2_1                    (0x1 << 18) // (HDMA) Channel 2 empty.
+#define AT91C_HDMA_EMPT3      (0x1 << 19) // (HDMA) When set, channel 3 is empty.
+#define 	AT91C_HDMA_EMPT3_0                    (0x0 << 19) // (HDMA) No effect.
+#define 	AT91C_HDMA_EMPT3_1                    (0x1 << 19) // (HDMA) Channel 3 empty.
+#define AT91C_HDMA_EMPT4      (0x1 << 20) // (HDMA) When set, channel 4 is empty.
+#define 	AT91C_HDMA_EMPT4_0                    (0x0 << 20) // (HDMA) No effect.
+#define 	AT91C_HDMA_EMPT4_1                    (0x1 << 20) // (HDMA) Channel 4 empty.
+#define AT91C_HDMA_EMPT5      (0x1 << 21) // (HDMA) When set, channel 5 is empty.
+#define 	AT91C_HDMA_EMPT5_0                    (0x0 << 21) // (HDMA) No effect.
+#define 	AT91C_HDMA_EMPT5_1                    (0x1 << 21) // (HDMA) Channel 5 empty.
+#define AT91C_HDMA_EMPT6      (0x1 << 22) // (HDMA) When set, channel 6 is empty.
+#define 	AT91C_HDMA_EMPT6_0                    (0x0 << 22) // (HDMA) No effect.
+#define 	AT91C_HDMA_EMPT6_1                    (0x1 << 22) // (HDMA) Channel 6 empty.
+#define AT91C_HDMA_EMPT7      (0x1 << 23) // (HDMA) When set, channel 7 is empty.
+#define 	AT91C_HDMA_EMPT7_0                    (0x0 << 23) // (HDMA) No effect.
+#define 	AT91C_HDMA_EMPT7_1                    (0x1 << 23) // (HDMA) Channel 7 empty.
+#define AT91C_HDMA_STAL0      (0x1 << 24) // (HDMA) When set, channel 0 is stalled.
+#define 	AT91C_HDMA_STAL0_0                    (0x0 << 24) // (HDMA) No effect.
+#define 	AT91C_HDMA_STAL0_1                    (0x1 << 24) // (HDMA) Channel 0 stalled.
+#define AT91C_HDMA_STAL1      (0x1 << 25) // (HDMA) When set, channel 1 is stalled.
+#define 	AT91C_HDMA_STAL1_0                    (0x0 << 25) // (HDMA) No effect.
+#define 	AT91C_HDMA_STAL1_1                    (0x1 << 25) // (HDMA) Channel 1 stalled.
+#define AT91C_HDMA_STAL2      (0x1 << 26) // (HDMA) When set, channel 2 is stalled.
+#define 	AT91C_HDMA_STAL2_0                    (0x0 << 26) // (HDMA) No effect.
+#define 	AT91C_HDMA_STAL2_1                    (0x1 << 26) // (HDMA) Channel 2 stalled.
+#define AT91C_HDMA_STAL3      (0x1 << 27) // (HDMA) When set, channel 3 is stalled.
+#define 	AT91C_HDMA_STAL3_0                    (0x0 << 27) // (HDMA) No effect.
+#define 	AT91C_HDMA_STAL3_1                    (0x1 << 27) // (HDMA) Channel 3 stalled.
+#define AT91C_HDMA_STAL4      (0x1 << 28) // (HDMA) When set, channel 4 is stalled.
+#define 	AT91C_HDMA_STAL4_0                    (0x0 << 28) // (HDMA) No effect.
+#define 	AT91C_HDMA_STAL4_1                    (0x1 << 28) // (HDMA) Channel 4 stalled.
+#define AT91C_HDMA_STAL5      (0x1 << 29) // (HDMA) When set, channel 5 is stalled.
+#define 	AT91C_HDMA_STAL5_0                    (0x0 << 29) // (HDMA) No effect.
+#define 	AT91C_HDMA_STAL5_1                    (0x1 << 29) // (HDMA) Channel 5 stalled.
+#define AT91C_HDMA_STAL6      (0x1 << 30) // (HDMA) When set, channel 6 is stalled.
+#define 	AT91C_HDMA_STAL6_0                    (0x0 << 30) // (HDMA) No effect.
+#define 	AT91C_HDMA_STAL6_1                    (0x1 << 30) // (HDMA) Channel 6 stalled.
+#define AT91C_HDMA_STAL7      (0x1 << 31) // (HDMA) When set, channel 7 is stalled.
+#define 	AT91C_HDMA_STAL7_0                    (0x0 << 31) // (HDMA) No effect.
+#define 	AT91C_HDMA_STAL7_1                    (0x1 << 31) // (HDMA) Channel 7 stalled.
+// -------- HDMA_RSVD : (HDMA Offset: 0x34)  -------- 
+// -------- HDMA_RSVD : (HDMA Offset: 0x38)  -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Error Correction Code controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ECC {
+	AT91C_REG	 ECC_CR; 	//  ECC reset register
+	AT91C_REG	 ECC_MR; 	//  ECC Page size register
+	AT91C_REG	 ECC_SR1; 	//  ECC Status register
+	AT91C_REG	 ECC_PR0; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR1; 	//  ECC Parity register
+	AT91C_REG	 ECC_SR2; 	//  ECC Status register
+	AT91C_REG	 ECC_PR2; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR3; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR4; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR5; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR6; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR7; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR8; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR9; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR10; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR11; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR12; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR13; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR14; 	//  ECC Parity register
+	AT91C_REG	 ECC_PR15; 	//  ECC Parity register
+} AT91S_ECC, *AT91PS_ECC;
+#else
+#define ECC_CR          (AT91C_CAST(AT91C_REG *) 	0x00000000) // (ECC_CR)  ECC reset register
+#define ECC_MR          (AT91C_CAST(AT91C_REG *) 	0x00000004) // (ECC_MR)  ECC Page size register
+#define ECC_SR          (AT91C_CAST(AT91C_REG *) 	0x00000008) // (ECC_SR)  ECC Status register
+#define ECC_PR          (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (ECC_PR)  ECC Parity register
+#define ECC_NPR         (AT91C_CAST(AT91C_REG *) 	0x00000010) // (ECC_NPR)  ECC Parity N register
+#define ECC_VR          (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (ECC_VR)  ECC Version register
+
+#endif
+// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- 
+#define AT91C_ECC_RST         (0x1 <<  0) // (ECC) ECC reset parity
+#define AT91C_ECC_SRST        (0x1 <<  1) // (ECC) ECC Soft reset
+// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- 
+#define AT91C_ECC_PAGE_SIZE   (0x3 <<  0) // (ECC) Nand Flash page size
+//Cheney: Document is conflict, some times, it said that it is word, sometimes, it said that is byte. need testing.
+#define AT91C_ECC_PAGE_SIZE_528_Words   (0x0 <<  0) // (ECC) Nand Flash page size is 528 words ?? Or byte??
+#define AT91C_ECC_PAGE_SIZE_1056_Words   (0x1 <<  0) // (ECC) Nand Flash page size is 1056 words
+#define AT91C_ECC_PAGE_SIZE_2112_Words   (0x2 <<  0) // (ECC) Nand Flash page size is 2112 words
+#define AT91C_ECC_PAGE_SIZE_4224_Words   (0x3 <<  0) // (ECC) Nand Flash page size is 4224 words
+#define AT91C_ECC_TYPECORRECT            (0x3 <<  4) // (ECC) Nand Flash correct type
+#define AT91C_ECC_TYPCORRECT_ONE_EVERY_PAGE  (0x0 <<  4) // (ECC) 1 ECC per page
+#define AT91C_ECC_TYPCORRECT_ONE_EVERY_256_BYTES  (0x1 <<  4) // (ECC) 1 ECC per 256 bytes, only support 8 bit width bus.
+#define AT91C_ECC_TYPCORRECT_ONE_EVERY_512_BYTES  (0x2 <<  4) // (ECC) 1 ECC per 512 bytes, only support 8 bit width bus.
+// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- 
+#define AT91C_ECC_RECERR      (0x1 <<  0) // (ECC) ECC error
+#define AT91C_ECC_ECCERR      (0x1 <<  1) // (ECC) ECC single error
+#define AT91C_ECC_MULERR      (0x1 <<  2) // (ECC) ECC_MULERR
+// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- 
+#define AT91C_ECC_BITADDR     (0xF <<  0) // (ECC) Bit address error
+#define AT91C_ECC_WORDADDR    (0xFFF <<  4) // (ECC) address of the failing bit
+#define AT91C_ECC_BITADDR_512ECC     (0x7 <<  0) // (ECC) Bit address error
+#define AT91C_ECC_WORDADDR_512ECC    (0x1FF <<  3) // (ECC) address of the failing bit
+#define AT91C_ECC_BITADDR_256ECC     (0x7 <<  0) // (ECC) Bit address error
+#define AT91C_ECC_WORDADDR_256ECC    (0xFF <<  3) // (ECC) address of the failing bit
+// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- 
+#define AT91C_ECC_NPARITY     (0xFFFF <<  0) // (ECC) ECC parity N 
+// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- 
+#define AT91C_ECC_VR          (0xF <<  0) // (ECC) ECC version register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EMAC {
+	AT91C_REG	 EMAC_NCR; 	// Network Control Register
+	AT91C_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91C_REG	 EMAC_NSR; 	// Network Status Register
+	AT91C_REG	 Reserved0[2]; 	// 
+	AT91C_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91C_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91C_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91C_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91C_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91C_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91C_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91C_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91C_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91C_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91C_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91C_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91C_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91C_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91C_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91C_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91C_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91C_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91C_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91C_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91C_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91C_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91C_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91C_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91C_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91C_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91C_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91C_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91C_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91C_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91C_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91C_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91C_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91C_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91C_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91C_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91C_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91C_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91C_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91C_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91C_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91C_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91C_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91C_REG	 Reserved1[13]; 	// 
+	AT91C_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+#else
+#define EMAC_NCR        (AT91C_CAST(AT91C_REG *) 	0x00000000) // (EMAC_NCR) Network Control Register
+#define EMAC_NCFGR      (AT91C_CAST(AT91C_REG *) 	0x00000004) // (EMAC_NCFGR) Network Configuration Register
+#define EMAC_NSR        (AT91C_CAST(AT91C_REG *) 	0x00000008) // (EMAC_NSR) Network Status Register
+#define EMAC_TSR        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (EMAC_TSR) Transmit Status Register
+#define EMAC_RBQP       (AT91C_CAST(AT91C_REG *) 	0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
+#define EMAC_TBQP       (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
+#define EMAC_RSR        (AT91C_CAST(AT91C_REG *) 	0x00000020) // (EMAC_RSR) Receive Status Register
+#define EMAC_ISR        (AT91C_CAST(AT91C_REG *) 	0x00000024) // (EMAC_ISR) Interrupt Status Register
+#define EMAC_IER        (AT91C_CAST(AT91C_REG *) 	0x00000028) // (EMAC_IER) Interrupt Enable Register
+#define EMAC_IDR        (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (EMAC_IDR) Interrupt Disable Register
+#define EMAC_IMR        (AT91C_CAST(AT91C_REG *) 	0x00000030) // (EMAC_IMR) Interrupt Mask Register
+#define EMAC_MAN        (AT91C_CAST(AT91C_REG *) 	0x00000034) // (EMAC_MAN) PHY Maintenance Register
+#define EMAC_PTR        (AT91C_CAST(AT91C_REG *) 	0x00000038) // (EMAC_PTR) Pause Time Register
+#define EMAC_PFR        (AT91C_CAST(AT91C_REG *) 	0x0000003C) // (EMAC_PFR) Pause Frames received Register
+#define EMAC_FTO        (AT91C_CAST(AT91C_REG *) 	0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
+#define EMAC_SCF        (AT91C_CAST(AT91C_REG *) 	0x00000044) // (EMAC_SCF) Single Collision Frame Register
+#define EMAC_MCF        (AT91C_CAST(AT91C_REG *) 	0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
+#define EMAC_FRO        (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (EMAC_FRO) Frames Received OK Register
+#define EMAC_FCSE       (AT91C_CAST(AT91C_REG *) 	0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
+#define EMAC_ALE        (AT91C_CAST(AT91C_REG *) 	0x00000054) // (EMAC_ALE) Alignment Error Register
+#define EMAC_DTF        (AT91C_CAST(AT91C_REG *) 	0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
+#define EMAC_LCOL       (AT91C_CAST(AT91C_REG *) 	0x0000005C) // (EMAC_LCOL) Late Collision Register
+#define EMAC_ECOL       (AT91C_CAST(AT91C_REG *) 	0x00000060) // (EMAC_ECOL) Excessive Collision Register
+#define EMAC_TUND       (AT91C_CAST(AT91C_REG *) 	0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
+#define EMAC_CSE        (AT91C_CAST(AT91C_REG *) 	0x00000068) // (EMAC_CSE) Carrier Sense Error Register
+#define EMAC_RRE        (AT91C_CAST(AT91C_REG *) 	0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
+#define EMAC_ROV        (AT91C_CAST(AT91C_REG *) 	0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
+#define EMAC_RSE        (AT91C_CAST(AT91C_REG *) 	0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
+#define EMAC_ELE        (AT91C_CAST(AT91C_REG *) 	0x00000078) // (EMAC_ELE) Excessive Length Errors Register
+#define EMAC_RJA        (AT91C_CAST(AT91C_REG *) 	0x0000007C) // (EMAC_RJA) Receive Jabbers Register
+#define EMAC_USF        (AT91C_CAST(AT91C_REG *) 	0x00000080) // (EMAC_USF) Undersize Frames Register
+#define EMAC_STE        (AT91C_CAST(AT91C_REG *) 	0x00000084) // (EMAC_STE) SQE Test Error Register
+#define EMAC_RLE        (AT91C_CAST(AT91C_REG *) 	0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
+#define EMAC_TPF        (AT91C_CAST(AT91C_REG *) 	0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
+#define EMAC_HRB        (AT91C_CAST(AT91C_REG *) 	0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
+#define EMAC_HRT        (AT91C_CAST(AT91C_REG *) 	0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
+#define EMAC_SA1L       (AT91C_CAST(AT91C_REG *) 	0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H       (AT91C_CAST(AT91C_REG *) 	0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L       (AT91C_CAST(AT91C_REG *) 	0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H       (AT91C_CAST(AT91C_REG *) 	0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L       (AT91C_CAST(AT91C_REG *) 	0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H       (AT91C_CAST(AT91C_REG *) 	0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L       (AT91C_CAST(AT91C_REG *) 	0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H       (AT91C_CAST(AT91C_REG *) 	0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID        (AT91C_CAST(AT91C_REG *) 	0x000000B8) // (EMAC_TID) Type ID Checking Register
+#define EMAC_TPQ        (AT91C_CAST(AT91C_REG *) 	0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
+#define EMAC_USRIO      (AT91C_CAST(AT91C_REG *) 	0x000000C0) // (EMAC_USRIO) USER Input/Output Register
+#define EMAC_WOL        (AT91C_CAST(AT91C_REG *) 	0x000000C4) // (EMAC_WOL) Wake On LAN Register
+#define EMAC_REV        (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (EMAC_REV) Revision Register
+
+#endif
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        (0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         (0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         (0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        (0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    (0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    (0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         (0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     (0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      (0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       (0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        (0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         (0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     (0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        (0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        (0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        (0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        (0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        (0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        (0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       (0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      (0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       (0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        (0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        (0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        (0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      (0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      (0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      (0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      (0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       (0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       (0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      (0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_WOLEV      (0x1 << 14) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       (0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       (0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       (0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         (0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        (0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       (0x1 <<  0) // (EMAC) Reduce MII
+#define AT91C_EMAC_CLKEN      (0x1 <<  1) // (EMAC) Clock Enable
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         (0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    (0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Image Sensor Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ISI {
+	AT91C_REG	 ISI_CFG1; 	// Configuration Register 1
+	AT91C_REG	 ISI_CFG2; 	// Configuration Register 2
+	AT91C_REG	 ISI_PSIZE; 	// Preview Size Register
+	AT91C_REG	 ISI_PDECF; 	// Preview Decimation Factor Register
+	AT91C_REG	 ISI_Y2RSET0; 	// Color Space Conversion YCrCb to RGB Register
+	AT91C_REG	 ISI_Y2RSET1; 	// Color Space Conversion YCrCb to RGB Register
+	AT91C_REG	 ISI_R2YSET0; 	// Color Space Conversion RGB to YCrCb Register
+	AT91C_REG	 ISI_R2YSET1; 	// Color Space Conversion RGB to YCrCb Register
+	AT91C_REG	 ISI_R2YSET2; 	// Color Space Conversion RGB to YCrCb Register
+	AT91C_REG	 ISI_CTRL; 	// Control Register
+	AT91C_REG	 ISI_SR; 	// Status Register
+	AT91C_REG	 ISI_IER; 	// Interrupt Enable Register
+	AT91C_REG	 ISI_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 ISI_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 ISI_DMACHER; 	// DMA Channel Enable Register
+	AT91C_REG	 ISI_DMACHDR; 	// DMA Channel Disable Register
+	AT91C_REG	 ISI_DMACHSR; 	// DMA Channel Status Register
+	AT91C_REG	 ISI_DMAPADDR; 	// DMA Preview Base Address Register
+	AT91C_REG	 ISI_DMAPCTRL; 	// DMA Preview Control Register
+	AT91C_REG	 ISI_DMAPDSCR; 	// DMA Preview Descriptor Address Register
+	AT91C_REG	 ISI_DMACADDR; 	// DMA Codec Base Address Register
+	AT91C_REG	 ISI_DMACCTRL; 	// DMA Codec Control Register
+	AT91C_REG	 ISI_DMACDSCR; 	// DMA Codec Descriptor Address Register
+	AT91C_REG	 Reserved0[34]; 	// 
+	AT91C_REG	 ISI_WPCR; 	// Write Protection Control Register
+	AT91C_REG	 ISI_WPSR; 	// Write Protection Status Register
+	AT91C_REG	 Reserved1[4]; 	// 
+	AT91C_REG	 ISI_VER; 	// Version Register
+} AT91S_ISI, *AT91PS_ISI;
+#else
+#define ISI_CFG1        (AT91C_CAST(AT91C_REG *) 	0x00000000) // (ISI_CFG1) Configuration Register 1
+#define ISI_CFG2        (AT91C_CAST(AT91C_REG *) 	0x00000004) // (ISI_CFG2) Configuration Register 2
+#define ISI_PSIZE       (AT91C_CAST(AT91C_REG *) 	0x00000008) // (ISI_PSIZE) Preview Size Register
+#define ISI_PDECF       (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (ISI_PDECF) Preview Decimation Factor Register
+#define ISI_Y2RSET0     (AT91C_CAST(AT91C_REG *) 	0x00000010) // (ISI_Y2RSET0) Color Space Conversion YCrCb to RGB Register
+#define ISI_Y2RSET1     (AT91C_CAST(AT91C_REG *) 	0x00000014) // (ISI_Y2RSET1) Color Space Conversion YCrCb to RGB Register
+#define ISI_R2YSET0     (AT91C_CAST(AT91C_REG *) 	0x00000018) // (ISI_R2YSET0) Color Space Conversion RGB to YCrCb Register
+#define ISI_R2YSET1     (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (ISI_R2YSET1) Color Space Conversion RGB to YCrCb Register
+#define ISI_R2YSET2     (AT91C_CAST(AT91C_REG *) 	0x00000020) // (ISI_R2YSET2) Color Space Conversion RGB to YCrCb Register
+#define ISI_CTRL        (AT91C_CAST(AT91C_REG *) 	0x00000024) // (ISI_CTRL) Control Register
+#define ISI_SR          (AT91C_CAST(AT91C_REG *) 	0x00000028) // (ISI_SR) Status Register
+#define ISI_IER         (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (ISI_IER) Interrupt Enable Register
+#define ISI_IDR         (AT91C_CAST(AT91C_REG *) 	0x00000030) // (ISI_IDR) Interrupt Disable Register
+#define ISI_IMR         (AT91C_CAST(AT91C_REG *) 	0x00000034) // (ISI_IMR) Interrupt Mask Register
+#define ISI_DMACHER     (AT91C_CAST(AT91C_REG *) 	0x00000038) // (ISI_DMACHER) DMA Channel Enable Register
+#define ISI_DMACHDR     (AT91C_CAST(AT91C_REG *) 	0x0000003C) // (ISI_DMACHDR) DMA Channel Disable Register
+#define ISI_DMACHSR     (AT91C_CAST(AT91C_REG *) 	0x00000040) // (ISI_DMACHSR) DMA Channel Status Register
+#define ISI_DMAPADDR    (AT91C_CAST(AT91C_REG *) 	0x00000044) // (ISI_DMAPADDR) DMA Preview Base Address Register
+#define ISI_DMAPCTRL    (AT91C_CAST(AT91C_REG *) 	0x00000048) // (ISI_DMAPCTRL) DMA Preview Control Register
+#define ISI_DMAPDSCR    (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (ISI_DMAPDSCR) DMA Preview Descriptor Address Register
+#define ISI_DMACADDR    (AT91C_CAST(AT91C_REG *) 	0x00000050) // (ISI_DMACADDR) DMA Codec Base Address Register
+#define ISI_DMACCTRL    (AT91C_CAST(AT91C_REG *) 	0x00000054) // (ISI_DMACCTRL) DMA Codec Control Register
+#define ISI_DMACDSCR    (AT91C_CAST(AT91C_REG *) 	0x00000058) // (ISI_DMACDSCR) DMA Codec Descriptor Address Register
+#define ISI_WPCR        (AT91C_CAST(AT91C_REG *) 	0x000000E4) // (ISI_WPCR) Write Protection Control Register
+#define ISI_WPSR        (AT91C_CAST(AT91C_REG *) 	0x000000E8) // (ISI_WPSR) Write Protection Status Register
+#define ISI_VER         (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (ISI_VER) Version Register
+
+#endif
+// -------- ISI_CFG1 : (ISI Offset: 0x0) ISI Configuration Register 1 -------- 
+#define AT91C_ISI_HSYNC_POL   (0x1 <<  2) // (ISI) Horizontal synchronization polarity
+#define 	AT91C_ISI_HSYNC_POL_ACTIVE_HIGH          (0x0 <<  2) // (ISI) HSYNC active high.
+#define 	AT91C_ISI_HSYNC_POL_ACTIVE_LOW           (0x1 <<  2) // (ISI) HSYNC active low.
+#define AT91C_ISI_VSYNC_POL   (0x1 <<  3) // (ISI) Vertical synchronization polarity
+#define 	AT91C_ISI_VSYNC_POL_ACTIVE_HIGH          (0x0 <<  3) // (ISI) VSYNC active high.
+#define 	AT91C_ISI_VSYNC_POL_ACTIVE_LOW           (0x1 <<  3) // (ISI) VSYNC active low.
+#define AT91C_ISI_PIXCLK_POL  (0x1 <<  4) // (ISI) Pixel Clock Polarity
+#define 	AT91C_ISI_PIXCLK_POL_RISING_EDGE          (0x0 <<  4) // (ISI) Data is sampled on rising edge of pixel clock.
+#define 	AT91C_ISI_PIXCLK_POL_FALLING_EDGE         (0x1 <<  4) // (ISI) Data is sampled on falling edge of pixel clock.
+#define AT91C_ISI_EMB_SYNC    (0x1 <<  6) // (ISI) Embedded synchronisation
+#define 	AT91C_ISI_EMB_SYNC_HSYNC_VSYNC          (0x0 <<  6) // (ISI) Synchronization by HSYNC, VSYNC.
+#define 	AT91C_ISI_EMB_SYNC_SAV_EAV              (0x1 <<  6) // (ISI) Synchronisation by Embedded Synchronization Sequence SAV/EAV.
+#define AT91C_ISI_CRC_SYNC    (0x1 <<  7) // (ISI) CRC correction
+#define 	AT91C_ISI_CRC_SYNC_CORRECTION_OFF       (0x0 <<  7) // (ISI) No CRC correction performed on embedded synchronization.
+#define 	AT91C_ISI_CRC_SYNC_CORRECTION_ON        (0x1 <<  7) // (ISI) CRC correction is performed.
+#define AT91C_ISI_FRATE       (0x7 <<  8) // (ISI) Frame rate capture
+#define AT91C_ISI_FULL        (0x1 << 12) // (ISI) Full mode is allowed
+#define 	AT91C_ISI_FULL_MODE_DISABLE         (0x0 << 12) // (ISI) Full mode disabled.
+#define 	AT91C_ISI_FULL_MODE_ENABLE          (0x1 << 12) // (ISI) both codec and preview datapath are working simultaneously.
+#define AT91C_ISI_THMASK      (0x3 << 13) // (ISI) DMA Burst Mask
+#define 	AT91C_ISI_THMASK_4_BURST              (0x0 << 13) // (ISI) Only 4 beats AHB bursts are allowed
+#define 	AT91C_ISI_THMASK_4_8_BURST            (0x1 << 13) // (ISI) Only 4 and 8 beats AHB bursts are allowed
+#define 	AT91C_ISI_THMASK_4_8_16_BURST         (0x2 << 13) // (ISI) 4, 8 and 16 beats AHB bursts are allowed
+#define AT91C_ISI_SLD         (0xFF << 16) // (ISI) Start of Line Delay
+#define AT91C_ISI_SFD         (0xFF << 24) // (ISI) Start of frame Delay
+// -------- ISI_CFG2 : (ISI Offset: 0x4) ISI Control Register 2 -------- 
+#define AT91C_ISI_IM_VSIZE    (0x7FF <<  0) // (ISI) Vertical size of the Image sensor [0..2047]
+#define AT91C_ISI_GS_MODE     (0x1 << 11) // (ISI) Grayscale Memory Mode
+#define 	AT91C_ISI_GS_MODE_2_PIXELS             (0x0 << 11) // (ISI) 2 pixels per word.
+#define 	AT91C_ISI_GS_MODE_1_PIXEL              (0x1 << 11) // (ISI) 1 pixel per word.
+#define AT91C_ISI_RGB_MODE    (0x1 << 12) // (ISI) RGB mode
+#define 	AT91C_ISI_RGB_MODE_RGB_888              (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
+#define 	AT91C_ISI_RGB_MODE_RGB_565              (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
+#define AT91C_ISI_GRAYSCALE   (0x1 << 13) // (ISI) Grayscale Mode
+#define 	AT91C_ISI_GRAYSCALE_DISABLE              (0x0 << 13) // (ISI) Grayscale mode is disabled
+#define 	AT91C_ISI_GRAYSCALE_ENABLE               (0x1 << 13) // (ISI) Input image is assumed to be grayscale coded
+#define AT91C_ISI_RGB_SWAP    (0x1 << 14) // (ISI) RGB Swap
+#define 	AT91C_ISI_RGB_SWAP_DISABLE              (0x0 << 14) // (ISI) D7 -> R7
+#define 	AT91C_ISI_RGB_SWAP_ENABLE               (0x1 << 14) // (ISI) D0 -> R7
+#define AT91C_ISI_COL_SPACE   (0x1 << 15) // (ISI) Color space for the image data
+#define 	AT91C_ISI_COL_SPACE_YCBCR                (0x0 << 15) // (ISI) YCbCr
+#define 	AT91C_ISI_COL_SPACE_RGB                  (0x1 << 15) // (ISI) RGB
+#define AT91C_ISI_IM_HSIZE    (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
+#define AT91C_ISI_YCC_SWAP    (0x3 << 28) // (ISI) Ycc swap
+#define 	AT91C_ISI_YCC_SWAP_YCC_DEFAULT          (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
+#define 	AT91C_ISI_YCC_SWAP_YCC_MODE1            (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
+#define 	AT91C_ISI_YCC_SWAP_YCC_MODE2            (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
+#define 	AT91C_ISI_YCC_SWAP_YCC_MODE3            (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
+#define AT91C_ISI_RGB_CFG     (0x3 << 30) // (ISI) RGB configuration
+#define 	AT91C_ISI_RGB_CFG_RGB_DEFAULT          (0x0 << 30) // (ISI) R/G(MSB)  G(LSB)/B  R/G(MSB)  G(LSB)/B
+#define 	AT91C_ISI_RGB_CFG_RGB_MODE1            (0x1 << 30) // (ISI) B/G(MSB)  G(LSB)/R  B/G(MSB)  G(LSB)/R
+#define 	AT91C_ISI_RGB_CFG_RGB_MODE2            (0x2 << 30) // (ISI) G(LSB)/R  B/G(MSB)  G(LSB)/R  B/G(MSB)
+#define 	AT91C_ISI_RGB_CFG_RGB_MODE3            (0x3 << 30) // (ISI) G(LSB)/B  R/G(MSB)  G(LSB)/B  R/G(MSB)
+// -------- ISI_PSIZE : (ISI Offset: 0x8) ISI Preview Register -------- 
+#define AT91C_ISI_PREV_VSIZE  (0x3FF <<  0) // (ISI) Vertical size for the preview path
+#define AT91C_ISI_PREV_HSIZE  (0x3FF << 16) // (ISI) Horizontal size for the preview path
+// -------- ISI_PDECF : (ISI Offset: 0xc) ISI Preview Decimation Factor Register -------- 
+#define AT91C_ISI_DEC_FACTOR  (0xFF <<  0) // (ISI) Decimation factor
+// -------- ISI_Y2RSET0 : (ISI Offset: 0x10) Color Space Conversion YCrCb to RGB Register -------- 
+#define AT91C_ISI_Y2R_C0      (0xFF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C0
+#define AT91C_ISI_Y2R_C1      (0xFF <<  8) // (ISI) Color Space Conversion Matrix Coefficient C1
+#define AT91C_ISI_Y2R_C2      (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
+#define AT91C_ISI_Y2R_C3      (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
+// -------- ISI_Y2RSET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- 
+#define AT91C_ISI_Y2R_C4      (0x1FF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C4
+#define AT91C_ISI_Y2R_YOFF    (0x1 << 12) // (ISI) Color Space Conversion Luninance default offset
+#define 	AT91C_ISI_Y2R_YOFF_0                    (0x0 << 12) // (ISI) Offset is 0
+#define 	AT91C_ISI_Y2R_YOFF_128                  (0x1 << 12) // (ISI) Offset is 128
+#define AT91C_ISI_Y2R_CROFF   (0x1 << 13) // (ISI) Color Space Conversion Red Chrominance default offset
+#define 	AT91C_ISI_Y2R_CROFF_0                    (0x0 << 13) // (ISI) Offset is 0
+#define 	AT91C_ISI_Y2R_CROFF_16                   (0x1 << 13) // (ISI) Offset is 16
+#define AT91C_ISI_Y2R_CBOFF   (0x1 << 14) // (ISI) Color Space Conversion Blue Chrominance default offset
+#define 	AT91C_ISI_Y2R_CBOFF_0                    (0x0 << 14) // (ISI) Offset is 0
+#define 	AT91C_ISI_Y2R_CBOFF_16                   (0x1 << 14) // (ISI) Offset is 16
+// -------- ISI_R2YSET0 : (ISI Offset: 0x18) Color Space Conversion RGB to YCrCb set 0 register -------- 
+#define AT91C_ISI_R2Y_C0      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
+#define AT91C_ISI_R2Y_C1      (0x7F <<  8) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
+#define AT91C_ISI_R2Y_C2      (0x7F << 16) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
+#define AT91C_ISI_R2Y_ROFF    (0x1 << 24) // (ISI) Color Space Conversion Red component offset
+#define 	AT91C_ISI_R2Y_ROFF_0                    (0x0 << 24) // (ISI) Offset is 0
+#define 	AT91C_ISI_R2Y_ROFF_16                   (0x1 << 24) // (ISI) Offset is 16
+// -------- ISI_R2YSET1 : (ISI Offset: 0x1c) Color Space Conversion RGB to YCrCb set 1 register -------- 
+#define AT91C_ISI_R2Y_C3      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
+#define AT91C_ISI_R2Y_C4      (0x7F <<  8) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
+#define AT91C_ISI_R2Y_C5      (0x7F << 16) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
+#define AT91C_ISI_R2Y_GOFF    (0x1 << 24) // (ISI) Color Space Conversion Green component offset
+#define 	AT91C_ISI_R2Y_GOFF_0                    (0x0 << 24) // (ISI) Offset is 0
+#define 	AT91C_ISI_R2Y_GOFF_128                  (0x1 << 24) // (ISI) Offset is 128
+// -------- ISI_R2YSET2 : (ISI Offset: 0x20) Color Space Conversion RGB to YCrCb set 2 register -------- 
+#define AT91C_ISI_R2Y_C6      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
+#define AT91C_ISI_R2Y_C7      (0x7F <<  8) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
+#define AT91C_ISI_R2Y_C8      (0x7F << 16) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
+#define AT91C_ISI_R2Y_BOFF    (0x1 << 24) // (ISI) Color Space Conversion Blue component offset
+#define 	AT91C_ISI_R2Y_BOFF_0                    (0x0 << 24) // (ISI) Offset is 0
+#define 	AT91C_ISI_R2Y_BOFF_128                  (0x1 << 24) // (ISI) Offset is 128
+// -------- ISI_CTRL : (ISI Offset: 0x24) ISI Control Register -------- 
+#define AT91C_ISI_EN          (0x1 <<  0) // (ISI) Image Sensor Interface Enable Request
+#define 	AT91C_ISI_EN_0                    (0x0) // (ISI) No effect
+#define 	AT91C_ISI_EN_1                    (0x1) // (ISI) Enable the module and the capture
+#define AT91C_ISI_DIS         (0x1 <<  1) // (ISI) Image Sensor Interface Disable Request
+#define 	AT91C_ISI_DIS_0                    (0x0 <<  1) // (ISI) No effect
+#define 	AT91C_ISI_DIS_1                    (0x1 <<  1) // (ISI) Disable the module and the capture
+#define AT91C_ISI_SRST        (0x1 <<  2) // (ISI) Software Reset Request
+#define 	AT91C_ISI_SRST_0                    (0x0 <<  2) // (ISI) No effect
+#define 	AT91C_ISI_SRST_1                    (0x1 <<  2) // (ISI) Reset the module
+#define AT91C_ISI_CDC         (0x1 <<  8) // (ISI) Codec Request
+#define 	AT91C_ISI_CDC_0                    (0x0 <<  8) // (ISI) No effect
+#define 	AT91C_ISI_CDC_1                    (0x1 <<  8) // (ISI) Enable the Codec
+// -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- 
+#define AT91C_ISI_VSYNC       (0x1 << 10) // (ISI) Vertical Synchronization
+#define 	AT91C_ISI_VSYNC_0                    (0x0 << 10) // (ISI) No effect
+#define 	AT91C_ISI_VSYNC_1                    (0x1 << 10) // (ISI) Indicates that a Vertical Synchronization has been detected since last read
+#define AT91C_ISI_PXFR_DONE   (0x1 << 16) // (ISI) Preview DMA transfer terminated
+#define 	AT91C_ISI_PXFR_DONE_0                    (0x0 << 16) // (ISI) No effect
+#define 	AT91C_ISI_PXFR_DONE_1                    (0x1 << 16) // (ISI) Indicates that DATA transfer on preview channel has completed since last read
+#define AT91C_ISI_CXFR_DONE   (0x1 << 17) // (ISI) Codec DMA transfer terminated
+#define 	AT91C_ISI_CXFR_DONE_0                    (0x0 << 17) // (ISI) No effect
+#define 	AT91C_ISI_CXFR_DONE_1                    (0x1 << 17) // (ISI) Indicates that DATA transfer on preview channel has completed since last read
+#define AT91C_ISI_SIP         (0x1 << 19) // (ISI) Synchronization In Progress
+#define 	AT91C_ISI_SIP_0                    (0x0 << 19) // (ISI) No effect
+#define 	AT91C_ISI_SIP_1                    (0x1 << 19) // (ISI) Indicates that Synchronization is in progress
+#define AT91C_ISI_P_OVR       (0x1 << 24) // (ISI) Fifo Preview Overflow 
+#define 	AT91C_ISI_P_OVR_0                    (0x0 << 24) // (ISI) No error
+#define 	AT91C_ISI_P_OVR_1                    (0x1 << 24) // (ISI) An overrun condition has occurred in input FIFO on the preview path
+#define AT91C_ISI_C_OVR       (0x1 << 25) // (ISI) Fifo Codec Overflow 
+#define 	AT91C_ISI_C_OVR_0                    (0x0 << 25) // (ISI) No error
+#define 	AT91C_ISI_C_OVR_1                    (0x1 << 25) // (ISI) An overrun condition has occurred in input FIFO on the codec path
+#define AT91C_ISI_CRC_ERR     (0x1 << 26) // (ISI) CRC synchronisation error
+#define 	AT91C_ISI_CRC_ERR_0                    (0x0 << 26) // (ISI) No error
+#define 	AT91C_ISI_CRC_ERR_1                    (0x1 << 26) // (ISI) CRC_SYNC is enabled in the control register and an error has been detected and not corrected. The frame is discarded and the ISI waits for a new one.
+#define AT91C_ISI_FR_OVR      (0x1 << 27) // (ISI) Frame rate overun
+#define 	AT91C_ISI_FR_OVR_0                    (0x0 << 27) // (ISI) No error
+#define 	AT91C_ISI_FR_OVR_1                    (0x1 << 27) // (ISI) Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs.
+// -------- ISI_IER : (ISI Offset: 0x2c) ISI Interrupt Enable Register -------- 
+// -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- 
+// -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- 
+// -------- ISI_DMACHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- 
+#define AT91C_ISI_P_CH_EN     (0x1 <<  0) // (ISI) Preview Channel Enable
+#define 	AT91C_ISI_P_CH_EN_0                    (0x0) // (ISI) No effect
+#define 	AT91C_ISI_P_CH_EN_1                    (0x1) // (ISI) Enable the Preview Channel
+#define AT91C_ISI_C_CH_EN     (0x1 <<  1) // (ISI) Codec Channel Enable
+#define 	AT91C_ISI_C_CH_EN_0                    (0x0 <<  1) // (ISI) No effect
+#define 	AT91C_ISI_C_CH_EN_1                    (0x1 <<  1) // (ISI) Enable the Codec Channel
+// -------- ISI_DMACHDR : (ISI Offset: 0x3c) DMA Channel Enable Register -------- 
+#define AT91C_ISI_P_CH_DIS    (0x1 <<  0) // (ISI) Preview Channel Disable
+#define 	AT91C_ISI_P_CH_DIS_0                    (0x0) // (ISI) No effect
+#define 	AT91C_ISI_P_CH_DIS_1                    (0x1) // (ISI) Disable the Preview Channel
+#define AT91C_ISI_C_CH_DIS    (0x1 <<  1) // (ISI) Codec Channel Disable
+#define 	AT91C_ISI_C_CH_DIS_0                    (0x0 <<  1) // (ISI) No effect
+#define 	AT91C_ISI_C_CH_DIS_1                    (0x1 <<  1) // (ISI) Disable the Codec Channel
+// -------- ISI_DMACHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- 
+#define AT91C_ISI_P_CH_S      (0x1 <<  0) // (ISI) Preview Channel Disable
+#define 	AT91C_ISI_P_CH_S_0                    (0x0) // (ISI) Preview Channel is disabled
+#define 	AT91C_ISI_P_CH_S_1                    (0x1) // (ISI) Preview Channel is enabled
+#define AT91C_ISI_C_CH_S      (0x1 <<  1) // (ISI) Codec Channel Disable
+#define 	AT91C_ISI_C_CH_S_0                    (0x0 <<  1) // (ISI) Codec Channel is disabled
+#define 	AT91C_ISI_C_CH_S_1                    (0x1 <<  1) // (ISI) Codec Channel is enabled
+// -------- ISI_DMAPCTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- 
+#define AT91C_ISI_P_FETCH     (0x1 <<  0) // (ISI) Preview Descriptor Fetch Control Field
+#define 	AT91C_ISI_P_FETCH_DISABLE              (0x0) // (ISI) Preview Channel Fetch Operation is disabled
+#define 	AT91C_ISI_P_FETCH_ENABLE               (0x1) // (ISI) Preview Channel Fetch Operation is enabled
+#define AT91C_ISI_P_DONE      (0x1 <<  1) // (ISI) Preview Transfer Done Flag
+#define 	AT91C_ISI_P_DONE_0                    (0x0 <<  1) // (ISI) Preview Transfer has not been performed
+#define 	AT91C_ISI_P_DONE_1                    (0x1 <<  1) // (ISI) Preview Transfer has completed
+// -------- ISI_DMACCTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- 
+#define AT91C_ISI_C_FETCH     (0x1 <<  0) // (ISI) Codec Descriptor Fetch Control Field
+#define 	AT91C_ISI_C_FETCH_DISABLE              (0x0) // (ISI) Codec Channel Fetch Operation is disabled
+#define 	AT91C_ISI_C_FETCH_ENABLE               (0x1) // (ISI) Codec Channel Fetch Operation is enabled
+#define AT91C_ISI_C_DONE      (0x1 <<  1) // (ISI) Codec Transfer Done Flag
+#define 	AT91C_ISI_C_DONE_0                    (0x0 <<  1) // (ISI) Codec Transfer has not been performed
+#define 	AT91C_ISI_C_DONE_1                    (0x1 <<  1) // (ISI) Codec Transfer has completed
+// -------- ISI_WPCR : (ISI Offset: 0xe4) Write Protection Control Register -------- 
+#define AT91C_ISI_WP_EN       (0x1 <<  0) // (ISI) Write Protection Enable
+#define 	AT91C_ISI_WP_EN_DISABLE              (0x0) // (ISI) Write Operation is disabled (if WP_KEY corresponds)
+#define 	AT91C_ISI_WP_EN_ENABLE               (0x1) // (ISI) Write Operation is enabled (if WP_KEY corresponds)
+#define AT91C_ISI_WP_KEY      (0xFFFFFF <<  8) // (ISI) Write Protection Key
+// -------- ISI_WPSR : (ISI Offset: 0xe8) Write Protection Status Register -------- 
+#define AT91C_ISI_WP_VS       (0xF <<  0) // (ISI) Write Protection Violation Status
+#define 	AT91C_ISI_WP_VS_NO_VIOLATION         (0x0) // (ISI) No Write Protection Violation detected since last read
+#define 	AT91C_ISI_WP_VS_ON_WRITE             (0x1) // (ISI) Write Protection Violation detected since last read
+#define 	AT91C_ISI_WP_VS_ON_RESET             (0x2) // (ISI) Software Reset Violation detected since last read
+#define 	AT91C_ISI_WP_VS_ON_BOTH              (0x3) // (ISI) Write Protection and Software Reset Violation detected since last read
+#define AT91C_ISI_WP_VSRC     (0xF <<  8) // (ISI) Write Protection Violation Source
+#define 	AT91C_ISI_WP_VSRC_NO_VIOLATION         (0x0 <<  8) // (ISI) No Write Protection Violation detected since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_CFG1             (0x1 <<  8) // (ISI) Write Protection Violation detected on ISI_CFG1 since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_CFG2             (0x2 <<  8) // (ISI) Write Protection Violation detected on ISI_CFG2 since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_PSIZE            (0x3 <<  8) // (ISI) Write Protection Violation detected on ISI_PSIZE since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_PDECF            (0x4 <<  8) // (ISI) Write Protection Violation detected on ISI_PDECF since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_Y2RSET0          (0x5 <<  8) // (ISI) Write Protection Violation detected on ISI_Y2RSET0 since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_Y2RSET1          (0x6 <<  8) // (ISI) Write Protection Violation detected on ISI_Y2RSET1 since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_R2YSET0          (0x7 <<  8) // (ISI) Write Protection Violation detected on ISI_R2YSET0 since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_R2YSET1          (0x8 <<  8) // (ISI) Write Protection Violation detected on ISI_R2YSET1 since last read
+#define 	AT91C_ISI_WP_VSRC_ISI_R2YSET2          (0x9 <<  8) // (ISI) Write Protection Violation detected on ISI_R2YSET2 since last read
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Host Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UHPHS_OHCI {
+	AT91C_REG	 UHPHS_OHCI_HcRevision; 	// Revision
+	AT91C_REG	 UHPHS_OHCI_HcControl; 	// Operating modes for the Host Controller
+	AT91C_REG	 UHPHS_OHCI_HcCommandStatus; 	// Command & status Register
+	AT91C_REG	 UHPHS_OHCI_HcInterruptStatus; 	// Interrupt Status Register
+	AT91C_REG	 UHPHS_OHCI_HcInterruptEnable; 	// Interrupt Enable Register
+	AT91C_REG	 UHPHS_OHCI_HcInterruptDisable; 	// Interrupt Disable Register
+	AT91C_REG	 UHPHS_OHCI_HcHCCA; 	// Pointer to the Host Controller Communication Area
+	AT91C_REG	 UHPHS_OHCI_HcPeriodCurrentED; 	// Current Isochronous or Interrupt Endpoint Descriptor
+	AT91C_REG	 UHPHS_OHCI_HcControlHeadED; 	// First Endpoint Descriptor of the Control list
+	AT91C_REG	 UHPHS_OHCI_HcControlCurrentED; 	// Endpoint Control and Status Register
+	AT91C_REG	 UHPHS_OHCI_HcBulkHeadED; 	// First endpoint register of the Bulk list
+	AT91C_REG	 UHPHS_OHCI_HcBulkCurrentED; 	// Current endpoint of the Bulk list
+	AT91C_REG	 UHPHS_OHCI_HcBulkDoneHead; 	// Last completed transfer descriptor
+	AT91C_REG	 UHPHS_OHCI_HcFmInterval; 	// Bit time between 2 consecutive SOFs
+	AT91C_REG	 UHPHS_OHCI_HcFmRemaining; 	// Bit time remaining in the current Frame
+	AT91C_REG	 UHPHS_OHCI_HcFmNumber; 	// Frame number
+	AT91C_REG	 UHPHS_OHCI_HcPeriodicStart; 	// Periodic Start
+	AT91C_REG	 UHPHS_OHCI_HcLSThreshold; 	// LS Threshold
+	AT91C_REG	 UHPHS_OHCI_HcRhDescriptorA; 	// Root Hub characteristics A
+	AT91C_REG	 UHPHS_OHCI_HcRhDescriptorB; 	// Root Hub characteristics B
+	AT91C_REG	 UHPHS_OHCI_HcRhStatus; 	// Root Hub Status register
+	AT91C_REG	 UHPHS_OHCI_HcRhPortStatus[2]; 	// Root Hub Port Status Register
+} AT91S_UHPHS_OHCI, *AT91PS_UHPHS_OHCI;
+#else
+#define HcRevision      (AT91C_CAST(AT91C_REG *) 	0x00000000) // (HcRevision) Revision
+#define HcControl       (AT91C_CAST(AT91C_REG *) 	0x00000004) // (HcControl) Operating modes for the Host Controller
+#define HcCommandStatus (AT91C_CAST(AT91C_REG *) 	0x00000008) // (HcCommandStatus) Command & status Register
+#define HcInterruptStatus (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (HcInterruptStatus) Interrupt Status Register
+#define HcInterruptEnable (AT91C_CAST(AT91C_REG *) 	0x00000010) // (HcInterruptEnable) Interrupt Enable Register
+#define HcInterruptDisable (AT91C_CAST(AT91C_REG *) 	0x00000014) // (HcInterruptDisable) Interrupt Disable Register
+#define HcHCCA          (AT91C_CAST(AT91C_REG *) 	0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
+#define HcPeriodCurrentED (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
+#define HcControlHeadED (AT91C_CAST(AT91C_REG *) 	0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
+#define HcControlCurrentED (AT91C_CAST(AT91C_REG *) 	0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
+#define HcBulkHeadED    (AT91C_CAST(AT91C_REG *) 	0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
+#define HcBulkCurrentED (AT91C_CAST(AT91C_REG *) 	0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
+#define HcBulkDoneHead  (AT91C_CAST(AT91C_REG *) 	0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
+#define HcFmInterval    (AT91C_CAST(AT91C_REG *) 	0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
+#define HcFmRemaining   (AT91C_CAST(AT91C_REG *) 	0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
+#define HcFmNumber      (AT91C_CAST(AT91C_REG *) 	0x0000003C) // (HcFmNumber) Frame number
+#define HcPeriodicStart (AT91C_CAST(AT91C_REG *) 	0x00000040) // (HcPeriodicStart) Periodic Start
+#define HcLSThreshold   (AT91C_CAST(AT91C_REG *) 	0x00000044) // (HcLSThreshold) LS Threshold
+#define HcRhDescriptorA (AT91C_CAST(AT91C_REG *) 	0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
+#define HcRhDescriptorB (AT91C_CAST(AT91C_REG *) 	0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
+#define HcRhStatus      (AT91C_CAST(AT91C_REG *) 	0x00000050) // (HcRhStatus) Root Hub Status register
+#define HcRhPortStatus  (AT91C_CAST(AT91C_REG *) 	0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Host Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UHPHS_EHCI {
+	AT91C_REG	 UHPHS_EHCI_VERSION; 	// 
+	AT91C_REG	 UHPHS_EHCI_HCSPARAMS; 	// 
+	AT91C_REG	 UHPHS_EHCI_HCCPARAMS; 	// 
+	AT91C_REG	 UHPHS_EHCI_HCSPPORTROUTE; 	// 
+	AT91C_REG	 UHPHS_EHCI_USBCMD; 	// 
+	AT91C_REG	 UHPHS_EHCI_USBSTS; 	// 
+	AT91C_REG	 UHPHS_EHCI_USBINTR; 	// 
+	AT91C_REG	 UHPHS_EHCI_FRINDEX; 	// 
+	AT91C_REG	 UHPHS_EHCI_CTRLDSSEGMENT; 	// 
+	AT91C_REG	 UHPHS_EHCI_PERIODICLISTBASE; 	// 
+	AT91C_REG	 UHPHS_EHCI_ASYNCLISTADDR; 	// 
+	AT91C_REG	 Reserved0[9]; 	// 
+	AT91C_REG	 UHPHS_EHCI_CONFIGFLAG; 	// 
+	AT91C_REG	 UHPHS_EHCI_PORTSC[2]; 	// 
+	AT91C_REG	 Reserved1[13]; 	// 
+	AT91C_REG	 UHPHS_EHCI_INSNREG00; 	// 
+	AT91C_REG	 UHPHS_EHCI_INSNREG01; 	// 
+	AT91C_REG	 UHPHS_EHCI_INSNREG02; 	// 
+	AT91C_REG	 UHPHS_EHCI_INSNREG03; 	// 
+	AT91C_REG	 UHPHS_EHCI_INSNREG04; 	// 
+	AT91C_REG	 UHPHS_EHCI_INSNREG05; 	// 
+} AT91S_UHPHS_EHCI, *AT91PS_UHPHS_EHCI;
+#else
+#define VERSION         (AT91C_CAST(AT91C_REG *) 	0x00000000) // (VERSION) 
+#define HCSPARAMS       (AT91C_CAST(AT91C_REG *) 	0x00000004) // (HCSPARAMS) 
+#define HCCPARAMS       (AT91C_CAST(AT91C_REG *) 	0x00000008) // (HCCPARAMS) 
+#define HCSPPORTROUTE   (AT91C_CAST(AT91C_REG *) 	0x0000000C) // (HCSPPORTROUTE) 
+#define USBCMD          (AT91C_CAST(AT91C_REG *) 	0x00000010) // (USBCMD) 
+#define USBSTS          (AT91C_CAST(AT91C_REG *) 	0x00000014) // (USBSTS) 
+#define USBINTR         (AT91C_CAST(AT91C_REG *) 	0x00000018) // (USBINTR) 
+#define FRINDEX         (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (FRINDEX) 
+#define CTRLDSSEGMENT   (AT91C_CAST(AT91C_REG *) 	0x00000020) // (CTRLDSSEGMENT) 
+#define PERIODICLISTBASE (AT91C_CAST(AT91C_REG *) 	0x00000024) // (PERIODICLISTBASE) 
+#define ASYNCLISTADDR   (AT91C_CAST(AT91C_REG *) 	0x00000028) // (ASYNCLISTADDR) 
+#define CONFIGFLAG      (AT91C_CAST(AT91C_REG *) 	0x00000050) // (CONFIGFLAG) 
+#define PORTSC          (AT91C_CAST(AT91C_REG *) 	0x00000054) // (PORTSC) 
+#define INSNREG00       (AT91C_CAST(AT91C_REG *) 	0x00000090) // (INSNREG00) 
+#define INSNREG01       (AT91C_CAST(AT91C_REG *) 	0x00000094) // (INSNREG01) 
+#define INSNREG02       (AT91C_CAST(AT91C_REG *) 	0x00000098) // (INSNREG02) 
+#define INSNREG03       (AT91C_CAST(AT91C_REG *) 	0x0000009C) // (INSNREG03) 
+#define INSNREG04       (AT91C_CAST(AT91C_REG *) 	0x000000A0) // (INSNREG04) 
+#define INSNREG05       (AT91C_CAST(AT91C_REG *) 	0x000000A4) // (INSNREG05) 
+
+#endif
+// -------- VERSION : (UHPHS_EHCI Offset: 0x0)  -------- 
+#define AT91C_UHPHS_CAPLENGTH (0xFF <<  0) // (UHPHS_EHCI) CapLength : Offset for control registers
+#define AT91C_UHPHS_HCIVERSION (0xFF << 16) // (UHPHS_EHCI) Hci Version
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR True Random Generator
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TRNG {
+	AT91C_REG	 TRNG_CR; 	// Control Register
+	AT91C_REG	 Reserved0[3]; 	// 
+	AT91C_REG	 TRNG_IER; 	// Interrupt Enable Register
+	AT91C_REG	 TRNG_IDR; 	// Interrupt Disable Register
+	AT91C_REG	 TRNG_IMR; 	// Interrupt Mask Register
+	AT91C_REG	 TRNG_ISR; 	// Interrupt Status Register
+	AT91C_REG	 Reserved1[12]; 	// 
+	AT91C_REG	 TRNG_ODATA; 	// Output Data Register
+	AT91C_REG	 Reserved2[42]; 	// 
+	AT91C_REG	 TRNG_VERSION; 	// TRNG Version Register
+} AT91S_TRNG, *AT91PS_TRNG;
+#else
+#define TRNG_CR         (AT91C_CAST(AT91C_REG *) 	0x00000000) // (TRNG_CR) Control Register
+#define TRNG_IER        (AT91C_CAST(AT91C_REG *) 	0x00000010) // (TRNG_IER) Interrupt Enable Register
+#define TRNG_IDR        (AT91C_CAST(AT91C_REG *) 	0x00000014) // (TRNG_IDR) Interrupt Disable Register
+#define TRNG_IMR        (AT91C_CAST(AT91C_REG *) 	0x00000018) // (TRNG_IMR) Interrupt Mask Register
+#define TRNG_ISR        (AT91C_CAST(AT91C_REG *) 	0x0000001C) // (TRNG_ISR) Interrupt Status Register
+#define TRNG_ODATA      (AT91C_CAST(AT91C_REG *) 	0x00000050) // (TRNG_ODATA) Output Data Register
+#define TRNG_VERSION    (AT91C_CAST(AT91C_REG *) 	0x000000FC) // (TRNG_VERSION) TRNG Version Register
+
+#endif
+// -------- TRNG_CR : (TRNG Offset: 0x0) Control Register -------- 
+#define AT91C_TRNG_ENABLE     (0x1 <<  0) // (TRNG) Enable TRNG
+// -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TRNG_DATRDY     (0x1 <<  0) // (TRNG) DATRDY
+// -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TRNG_ISR : (TRNG Offset: 0x1c) Interrupt Status Register -------- 
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM9G45
+// *****************************************************************************
+// ========== Register definition for SFR peripheral ========== 
+#define AT91C_SFR_INT   (AT91C_CAST(AT91C_REG *) 	0xFFF74014) // (SFR) OHCI suspend Interrupt status
+#define AT91C_SFR_DDRCFG (AT91C_CAST(AT91C_REG *) 	0xFFF74004) // (SFR) DDR2 SSTL18 control
+#define AT91C_SFR_UTMICFG (AT91C_CAST(AT91C_REG *) 	0xFFF74010) // (SFR) UTMI Software Reset, and OHCI suspend interrupt control
+#define AT91C_SFR_EBIDELAY (AT91C_CAST(AT91C_REG *) 	0xFFF7400C) // (SFR) EBI DDR controller clock delay
+#define AT91C_SFR_DDRDELAY (AT91C_CAST(AT91C_REG *) 	0xFFF74008) // (SFR) DDR2 controller clock delay
+#define AT91C_SFR_EMA   (AT91C_CAST(AT91C_REG *) 	0xFFF74000) // (SFR) memory Extra Margin Adjustment control
+// ========== Register definition for SYS peripheral ========== 
+#define AT91C_SYS_SLCKSEL (AT91C_CAST(AT91C_REG *) 	0xFFFFFD50) // (SYS) Slow Clock Selection Register
+#define AT91C_SYS_GPBR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFD60) // (SYS) General Purpose Register
+// ========== Register definition for EBI peripheral ========== 
+#define AT91C_EBI_DUMMY (AT91C_CAST(AT91C_REG *) 	0xFFFFE200) // (EBI) Dummy register - Do not use
+// ========== Register definition for DDR2CP1 peripheral ========== 
+#define AT91C_DDR2CP1_DELAY2 (AT91C_CAST(AT91C_REG *) 	0xFFFFE434) // (DDR2CP1) Pad delay2 Register
+#define AT91C_DDR2CP1_T3PR (AT91C_CAST(AT91C_REG *) 	0xFFFFE418) // (DDR2CP1) Timing3 Register
+#define AT91C_DDR2CP1_RTR (AT91C_CAST(AT91C_REG *) 	0xFFFFE404) // (DDR2CP1) Refresh Timer Register
+#define AT91C_DDR2CP1_T0PR (AT91C_CAST(AT91C_REG *) 	0xFFFFE40C) // (DDR2CP1) Timing0 Register
+#define AT91C_DDR2CP1_WPSR (AT91C_CAST(AT91C_REG *) 	0xFFFFE4E8) // (DDR2CP1) High Speed Register
+#define AT91C_DDR2CP1_DELAY8 (AT91C_CAST(AT91C_REG *) 	0xFFFFE44C) // (DDR2CP1) Pad delay8 Register
+#define AT91C_DDR2CP1_LPR (AT91C_CAST(AT91C_REG *) 	0xFFFFE41C) // (DDR2CP1) Low-power Register
+#define AT91C_DDR2CP1_VER (AT91C_CAST(AT91C_REG *) 	0xFFFFE428) // (DDR2CP1) DLL Version Register
+#define AT91C_DDR2CP1_DELAY7 (AT91C_CAST(AT91C_REG *) 	0xFFFFE448) // (DDR2CP1) Pad delay7 Register
+#define AT91C_DDR2CP1_CR (AT91C_CAST(AT91C_REG *) 	0xFFFFE408) // (DDR2CP1) Configuration Register
+#define AT91C_DDR2CP1_WPCR (AT91C_CAST(AT91C_REG *) 	0xFFFFE4E4) // (DDR2CP1) High Speed Register
+#define AT91C_DDR2CP1_MR (AT91C_CAST(AT91C_REG *) 	0xFFFFE400) // (DDR2CP1) Mode Register
+#define AT91C_DDR2CP1_DELAY5 (AT91C_CAST(AT91C_REG *) 	0xFFFFE440) // (DDR2CP1) Pad delay5 Register
+#define AT91C_DDR2CP1_T2PR (AT91C_CAST(AT91C_REG *) 	0xFFFFE414) // (DDR2CP1) Timing2 Register
+#define AT91C_DDR2CP1_HS (AT91C_CAST(AT91C_REG *) 	0xFFFFE42C) // (DDR2CP1) High Speed Register
+#define AT91C_DDR2CP1_MDR (AT91C_CAST(AT91C_REG *) 	0xFFFFE420) // (DDR2CP1) Memory Device Register
+#define AT91C_DDR2CP1_DELAY4 (AT91C_CAST(AT91C_REG *) 	0xFFFFE43C) // (DDR2CP1) Pad delay4 Register
+#define AT91C_DDR2CP1_DELAY1 (AT91C_CAST(AT91C_REG *) 	0xFFFFE430) // (DDR2CP1) Pad delay1 Register
+#define AT91C_DDR2CP1_DELAY6 (AT91C_CAST(AT91C_REG *) 	0xFFFFE444) // (DDR2CP1) Pad delay6 Register
+#define AT91C_DDR2CP1_DLL (AT91C_CAST(AT91C_REG *) 	0xFFFFE424) // (DDR2CP1) DLL Information Register
+#define AT91C_DDR2CP1_DELAY3 (AT91C_CAST(AT91C_REG *) 	0xFFFFE438) // (DDR2CP1) Pad delay3 Register
+#define AT91C_DDR2CP1_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFFE4FC) // (DDR2CP1) Version Register
+#define AT91C_DDR2CP1_T1PR (AT91C_CAST(AT91C_REG *) 	0xFFFFE410) // (DDR2CP1) Timing1 Register
+// ========== Register definition for DDR2C peripheral ========== 
+#define AT91C_DDR2C_DELAY8 (AT91C_CAST(AT91C_REG *) 	0xFFFFE64C) // (DDR2C) Pad delay8 Register
+#define AT91C_DDR2C_VER (AT91C_CAST(AT91C_REG *) 	0xFFFFE628) // (DDR2C) DLL Version Register
+#define AT91C_DDR2C_RTR (AT91C_CAST(AT91C_REG *) 	0xFFFFE604) // (DDR2C) Refresh Timer Register
+#define AT91C_DDR2C_T0PR (AT91C_CAST(AT91C_REG *) 	0xFFFFE60C) // (DDR2C) Timing0 Register
+#define AT91C_DDR2C_DELAY5 (AT91C_CAST(AT91C_REG *) 	0xFFFFE640) // (DDR2C) Pad delay5 Register
+#define AT91C_DDR2C_LPR (AT91C_CAST(AT91C_REG *) 	0xFFFFE61C) // (DDR2C) Low-power Register
+#define AT91C_DDR2C_HS  (AT91C_CAST(AT91C_REG *) 	0xFFFFE62C) // (DDR2C) High Speed Register
+#define AT91C_DDR2C_DELAY2 (AT91C_CAST(AT91C_REG *) 	0xFFFFE634) // (DDR2C) Pad delay2 Register
+#define AT91C_DDR2C_T2PR (AT91C_CAST(AT91C_REG *) 	0xFFFFE614) // (DDR2C) Timing2 Register
+#define AT91C_DDR2C_DELAY1 (AT91C_CAST(AT91C_REG *) 	0xFFFFE630) // (DDR2C) Pad delay1 Register
+#define AT91C_DDR2C_T1PR (AT91C_CAST(AT91C_REG *) 	0xFFFFE610) // (DDR2C) Timing1 Register
+#define AT91C_DDR2C_MDR (AT91C_CAST(AT91C_REG *) 	0xFFFFE620) // (DDR2C) Memory Device Register
+#define AT91C_DDR2C_DELAY6 (AT91C_CAST(AT91C_REG *) 	0xFFFFE644) // (DDR2C) Pad delay6 Register
+#define AT91C_DDR2C_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFFE6FC) // (DDR2C) Version Register
+#define AT91C_DDR2C_MR  (AT91C_CAST(AT91C_REG *) 	0xFFFFE600) // (DDR2C) Mode Register
+#define AT91C_DDR2C_DLL (AT91C_CAST(AT91C_REG *) 	0xFFFFE624) // (DDR2C) DLL Information Register
+#define AT91C_DDR2C_DELAY4 (AT91C_CAST(AT91C_REG *) 	0xFFFFE63C) // (DDR2C) Pad delay4 Register
+#define AT91C_DDR2C_WPCR (AT91C_CAST(AT91C_REG *) 	0xFFFFE6E4) // (DDR2C) High Speed Register
+#define AT91C_DDR2C_CR  (AT91C_CAST(AT91C_REG *) 	0xFFFFE608) // (DDR2C) Configuration Register
+#define AT91C_DDR2C_DELAY3 (AT91C_CAST(AT91C_REG *) 	0xFFFFE638) // (DDR2C) Pad delay3 Register
+#define AT91C_DDR2C_WPSR (AT91C_CAST(AT91C_REG *) 	0xFFFFE6E8) // (DDR2C) High Speed Register
+#define AT91C_DDR2C_DELAY7 (AT91C_CAST(AT91C_REG *) 	0xFFFFE648) // (DDR2C) Pad delay7 Register
+#define AT91C_DDR2C_T3PR (AT91C_CAST(AT91C_REG *) 	0xFFFFE618) // (DDR2C) Timing3 Register
+// ========== Register definition for SMC peripheral ========== 
+#define AT91C_SMC_PULSE7 (AT91C_CAST(AT91C_REG *) 	0xFFFFE874) // (SMC)  Pulse Register for CS 7
+#define AT91C_SMC_DELAY1 (AT91C_CAST(AT91C_REG *) 	0xFFFFE8C0) // (SMC) SMC Delay Control Register
+#define AT91C_SMC_CYCLE2 (AT91C_CAST(AT91C_REG *) 	0xFFFFE828) // (SMC)  Cycle Register for CS 2
+#define AT91C_SMC_DELAY5 (AT91C_CAST(AT91C_REG *) 	0xFFFFE8D0) // (SMC) SMC Delay Control Register
+#define AT91C_SMC_DELAY6 (AT91C_CAST(AT91C_REG *) 	0xFFFFE8D4) // (SMC) SMC Delay Control Register
+#define AT91C_SMC_PULSE2 (AT91C_CAST(AT91C_REG *) 	0xFFFFE824) // (SMC)  Pulse Register for CS 2
+#define AT91C_SMC_SETUP6 (AT91C_CAST(AT91C_REG *) 	0xFFFFE860) // (SMC)  Setup Register for CS 6
+#define AT91C_SMC_SETUP5 (AT91C_CAST(AT91C_REG *) 	0xFFFFE850) // (SMC)  Setup Register for CS 5
+#define AT91C_SMC_CYCLE6 (AT91C_CAST(AT91C_REG *) 	0xFFFFE868) // (SMC)  Cycle Register for CS 6
+#define AT91C_SMC_PULSE6 (AT91C_CAST(AT91C_REG *) 	0xFFFFE864) // (SMC)  Pulse Register for CS 6
+#define AT91C_SMC_CTRL5 (AT91C_CAST(AT91C_REG *) 	0xFFFFE85C) // (SMC)  Control Register for CS 5
+#define AT91C_SMC_CTRL3 (AT91C_CAST(AT91C_REG *) 	0xFFFFE83C) // (SMC)  Control Register for CS 3
+#define AT91C_SMC_DELAY7 (AT91C_CAST(AT91C_REG *) 	0xFFFFE8D8) // (SMC) SMC Delay Control Register
+#define AT91C_SMC_DELAY3 (AT91C_CAST(AT91C_REG *) 	0xFFFFE8C8) // (SMC) SMC Delay Control Register
+#define AT91C_SMC_CYCLE0 (AT91C_CAST(AT91C_REG *) 	0xFFFFE808) // (SMC)  Cycle Register for CS 0
+#define AT91C_SMC_SETUP1 (AT91C_CAST(AT91C_REG *) 	0xFFFFE810) // (SMC)  Setup Register for CS 1
+#define AT91C_SMC_PULSE5 (AT91C_CAST(AT91C_REG *) 	0xFFFFE854) // (SMC)  Pulse Register for CS 5
+#define AT91C_SMC_SETUP7 (AT91C_CAST(AT91C_REG *) 	0xFFFFE870) // (SMC)  Setup Register for CS 7
+#define AT91C_SMC_CTRL4 (AT91C_CAST(AT91C_REG *) 	0xFFFFE84C) // (SMC)  Control Register for CS 4
+#define AT91C_SMC_DELAY2 (AT91C_CAST(AT91C_REG *) 	0xFFFFE8C4) // (SMC) SMC Delay Control Register
+#define AT91C_SMC_PULSE3 (AT91C_CAST(AT91C_REG *) 	0xFFFFE834) // (SMC)  Pulse Register for CS 3
+#define AT91C_SMC_CYCLE4 (AT91C_CAST(AT91C_REG *) 	0xFFFFE848) // (SMC)  Cycle Register for CS 4
+#define AT91C_SMC_CTRL1 (AT91C_CAST(AT91C_REG *) 	0xFFFFE81C) // (SMC)  Control Register for CS 1
+#define AT91C_SMC_SETUP3 (AT91C_CAST(AT91C_REG *) 	0xFFFFE830) // (SMC)  Setup Register for CS 3
+#define AT91C_SMC_CTRL0 (AT91C_CAST(AT91C_REG *) 	0xFFFFE80C) // (SMC)  Control Register for CS 0
+#define AT91C_SMC_CYCLE7 (AT91C_CAST(AT91C_REG *) 	0xFFFFE878) // (SMC)  Cycle Register for CS 7
+#define AT91C_SMC_DELAY4 (AT91C_CAST(AT91C_REG *) 	0xFFFFE8CC) // (SMC) SMC Delay Control Register
+#define AT91C_SMC_CYCLE1 (AT91C_CAST(AT91C_REG *) 	0xFFFFE818) // (SMC)  Cycle Register for CS 1
+#define AT91C_SMC_SETUP2 (AT91C_CAST(AT91C_REG *) 	0xFFFFE820) // (SMC)  Setup Register for CS 2
+#define AT91C_SMC_PULSE1 (AT91C_CAST(AT91C_REG *) 	0xFFFFE814) // (SMC)  Pulse Register for CS 1
+#define AT91C_SMC_DELAY8 (AT91C_CAST(AT91C_REG *) 	0xFFFFE8DC) // (SMC) SMC Delay Control Register
+#define AT91C_SMC_CTRL2 (AT91C_CAST(AT91C_REG *) 	0xFFFFE82C) // (SMC)  Control Register for CS 2
+#define AT91C_SMC_PULSE4 (AT91C_CAST(AT91C_REG *) 	0xFFFFE844) // (SMC)  Pulse Register for CS 4
+#define AT91C_SMC_SETUP4 (AT91C_CAST(AT91C_REG *) 	0xFFFFE840) // (SMC)  Setup Register for CS 4
+#define AT91C_SMC_CYCLE3 (AT91C_CAST(AT91C_REG *) 	0xFFFFE838) // (SMC)  Cycle Register for CS 3
+#define AT91C_SMC_SETUP0 (AT91C_CAST(AT91C_REG *) 	0xFFFFE800) // (SMC)  Setup Register for CS 0
+#define AT91C_SMC_CYCLE5 (AT91C_CAST(AT91C_REG *) 	0xFFFFE858) // (SMC)  Cycle Register for CS 5
+#define AT91C_SMC_PULSE0 (AT91C_CAST(AT91C_REG *) 	0xFFFFE804) // (SMC)  Pulse Register for CS 0
+#define AT91C_SMC_CTRL6 (AT91C_CAST(AT91C_REG *) 	0xFFFFE86C) // (SMC)  Control Register for CS 6
+#define AT91C_SMC_CTRL7 (AT91C_CAST(AT91C_REG *) 	0xFFFFE87C) // (SMC)  Control Register for CS 7
+// ========== Register definition for MATRIX peripheral ========== 
+#define AT91C_MATRIX_SCFG1 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA44) // (MATRIX)  Slave Configuration Register 1 : SRAM S1
+#define AT91C_MATRIX_MRCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEB00) // (MATRIX)  Master Remap Control Register 
+#define AT91C_MATRIX_PRAS2 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA90) // (MATRIX)  PRAS2 : SRAM S2
+#define AT91C_MATRIX_PRAS1 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA88) // (MATRIX)  PRAS1 : SRAM S1
+#define AT91C_MATRIX_PRAS0 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA80) // (MATRIX)  PRAS0 : SRAM S0
+#define AT91C_MATRIX_MCFG8 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA20) // (MATRIX)  Master Configuration Register 8 : eMAC
+#define AT91C_MATRIX_MCFG2 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA08) // (MATRIX)  Master Configuration Register 2 : pdc
+#define AT91C_MATRIX_EBICSA (AT91C_CAST(AT91C_REG *) 	0xFFFFEB28) // (MATRIX)  EBI Chip Select Assignment Register 
+#define AT91C_MATRIX_PRAS4 (AT91C_CAST(AT91C_REG *) 	0xFFFFEAA0) // (MATRIX)  PRAS4 : ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+#define AT91C_MATRIX_MCFG3 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA0C) // (MATRIX)  Master Configuration Register 3 : USB Host OHCI
+#define AT91C_MATRIX_SCFG0 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA40) // (MATRIX)  Slave Configuration Register 0 : SRAM S0
+#define AT91C_MATRIX_MCFG7 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA1C) // (MATRIX)  Master Configuration Register 7 : lcdc
+#define AT91C_MATRIX_PRAS6 (AT91C_CAST(AT91C_REG *) 	0xFFFFEAB0) // (MATRIX)  PRAS6 : DDR2 S1
+#define AT91C_MATRIX_SCFG7 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA5C) // (MATRIX)  Slave Configuration Register 7 : DDR2 S2
+#define AT91C_MATRIX_PRAS7 (AT91C_CAST(AT91C_REG *) 	0xFFFFEAB8) // (MATRIX)  PRAS7 : DDR2 S2
+#define AT91C_MATRIX_SCFG2 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA48) // (MATRIX)  Slave Configuration Register 2 : SRAM S2
+#define AT91C_MATRIX_WRPROTST (AT91C_CAST(AT91C_REG *) 	0xFFFFEBE8) // (MATRIX)  Write Protection Status Register 
+#define AT91C_MATRIX_PRBS0 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA84) // (MATRIX)  PRBS0 : SRAM S0
+#define AT91C_MATRIX_PRBS2 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA94) // (MATRIX)  PRBS2 : SRAM S2
+#define AT91C_MATRIX_MCFG4 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA10) // (MATRIX)  Master Configuration Register 4 : DMA0
+#define AT91C_MATRIX_SCFG5 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA54) // (MATRIX)  Slave Configuration Register 5 : DDR2 S0
+#define AT91C_MATRIX_PRBS6 (AT91C_CAST(AT91C_REG *) 	0xFFFFEAB4) // (MATRIX)  PRBS6 : DDR2 S1
+#define AT91C_MATRIX_MCFG1 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA04) // (MATRIX)  Master Configuration Register 1 ; ARM-D
+#define AT91C_MATRIX_SCFG6 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA58) // (MATRIX)  Slave Configuration Register 6 : DDR2 S1
+#define AT91C_MATRIX_SCFG4 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA50) // (MATRIX)  Slave Configuration Register 4 ; ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+#define AT91C_MATRIX_PRBS1 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA8C) // (MATRIX)  PRBS1 : SRAM S1
+#define AT91C_MATRIX_PRBS3 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA9C) // (MATRIX)  PRBS3 : SRAM S3
+#define AT91C_MATRIX_WRPROTEN (AT91C_CAST(AT91C_REG *) 	0xFFFFEBE4) // (MATRIX)  Write Protection Control Register 
+#define AT91C_MATRIX_TCMR (AT91C_CAST(AT91C_REG *) 	0xFFFFEB10) // (MATRIX)  Bus Matrix TCM Configuration Register 
+#define AT91C_MATRIX_MCFG0 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA00) // (MATRIX)  Master Configuration Register 0 : ARM-I
+#define AT91C_MATRIX_PRAS5 (AT91C_CAST(AT91C_REG *) 	0xFFFFEAA8) // (MATRIX)  PRAS5 : DDR2 S0
+#define AT91C_MATRIX_DDRMPR (AT91C_CAST(AT91C_REG *) 	0xFFFFEB18) // (MATRIX)  DDR Multi-Port Register 
+#define AT91C_MATRIX_PRBS4 (AT91C_CAST(AT91C_REG *) 	0xFFFFEAA4) // (MATRIX)  PRBS4 : ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder
+#define AT91C_MATRIX_MCFG6 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA18) // (MATRIX)  Master Configuration Register 6 : hisi
+#define AT91C_MATRIX_PRBS5 (AT91C_CAST(AT91C_REG *) 	0xFFFFEAAC) // (MATRIX)  PRBS5 : DDR2 S0
+#define AT91C_MATRIX_MCFG9 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA24) // (MATRIX)  Master Configuration Register 9 : USB Device
+#define AT91C_MATRIX_MCFG5 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA14) // (MATRIX)  Master Configuration Register 5 : DMA1
+#define AT91C_MATRIX_PRBS7 (AT91C_CAST(AT91C_REG *) 	0xFFFFEABC) // (MATRIX)  PRBS7 : DDR2 S2
+#define AT91C_MATRIX_MCFG10 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA28) // (MATRIX)  Master Configuration Register 10 : USB Host EHCI
+#define AT91C_MATRIX_PRAS3 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA98) // (MATRIX)  PRAS3 : SRAM S3
+#define AT91C_MATRIX_SCFG3 (AT91C_CAST(AT91C_REG *) 	0xFFFFEA4C) // (MATRIX)  Slave Configuration Register 3 : SRAM S3
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   (AT91C_CAST(AT91C_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   (AT91C_CAST(AT91C_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   (AT91C_CAST(AT91C_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   (AT91C_CAST(AT91C_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (AT91C_CAST(AT91C_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   (AT91C_CAST(AT91C_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   (AT91C_CAST(AT91C_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   (AT91C_CAST(AT91C_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   (AT91C_CAST(AT91C_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_PTCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEF20) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_RCR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEF04) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_TCR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEF0C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEF14) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_TNPR (AT91C_CAST(AT91C_REG *) 	0xFFFFEF18) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_RNPR (AT91C_CAST(AT91C_REG *) 	0xFFFFEF10) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_PTSR (AT91C_CAST(AT91C_REG *) 	0xFFFFEF24) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_RPR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEF00) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_TPR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEF08) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_TNCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEF1C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_BRGR (AT91C_CAST(AT91C_REG *) 	0xFFFFEE20) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_CR   (AT91C_CAST(AT91C_REG *) 	0xFFFFEE00) // (DBGU) Control Register
+#define AT91C_DBGU_THR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEE1C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEE0C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_EXID (AT91C_CAST(AT91C_REG *) 	0xFFFFEE44) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEE10) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_FNTR (AT91C_CAST(AT91C_REG *) 	0xFFFFEE48) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFFEE08) // (DBGU) Interrupt Enable Register
+#define AT91C_DBGU_CSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEE14) // (DBGU) Channel Status Register
+#define AT91C_DBGU_MR   (AT91C_CAST(AT91C_REG *) 	0xFFFFEE04) // (DBGU) Mode Register
+#define AT91C_DBGU_RHR  (AT91C_CAST(AT91C_REG *) 	0xFFFFEE18) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_CIDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEE40) // (DBGU) Chip ID Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_OWDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF2A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_DELAY3 (AT91C_CAST(AT91C_REG *) 	0xFFFFF2C8) // (PIOA) PIO Delay Control Register
+#define AT91C_PIOA_ISR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF24C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF204) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_OSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF218) // (PIOA) Output Status Register
+#define AT91C_PIOA_ABSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF278) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_DELAY2 (AT91C_CAST(AT91C_REG *) 	0xFFFFF2C4) // (PIOA) PIO Delay Control Register
+#define AT91C_PIOA_PDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF23C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_BSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF274) // (PIOA) Select B Register
+#define AT91C_PIOA_DELAY1 (AT91C_CAST(AT91C_REG *) 	0xFFFFF2C0) // (PIOA) PIO Delay Control Register
+#define AT91C_PIOA_PPUER (AT91C_CAST(AT91C_REG *) 	0xFFFFF264) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF210) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF200) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFFF2FC) // (PIOA) PIO Version Register
+#define AT91C_PIOA_PPUDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF260) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_ODSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF238) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 	0xFFFFF2B0) // (PIOA) PIO Slewrate Control Register
+#define AT91C_PIOA_MDDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF254) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_IFSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF228) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_CODR (AT91C_CAST(AT91C_REG *) 	0xFFFFF234) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_ASR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF270) // (PIOA) Select A Register
+#define AT91C_PIOA_OWSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF2A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF248) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PPUSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF268) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_MDER (AT91C_CAST(AT91C_REG *) 	0xFFFFF250) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_IFDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF224) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_SODR (AT91C_CAST(AT91C_REG *) 	0xFFFFF230) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_OWER (AT91C_CAST(AT91C_REG *) 	0xFFFFF2A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF244) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_IFER (AT91C_CAST(AT91C_REG *) 	0xFFFFF220) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF240) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_ODR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF214) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_MDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF258) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_DELAY4 (AT91C_CAST(AT91C_REG *) 	0xFFFFF2CC) // (PIOA) PIO Delay Control Register
+#define AT91C_PIOA_PSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF208) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_ODR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF414) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_DELAY4 (AT91C_CAST(AT91C_REG *) 	0xFFFFF4CC) // (PIOB) PIO Delay Control Register
+#define AT91C_PIOB_SODR (AT91C_CAST(AT91C_REG *) 	0xFFFFF430) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF44C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ABSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF478) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF448) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_MDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF458) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_PPUSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF468) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_PDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF43C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_DELAY3 (AT91C_CAST(AT91C_REG *) 	0xFFFFF4C8) // (PIOB) PIO Delay Control Register
+#define AT91C_PIOB_MDDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF454) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_CODR (AT91C_CAST(AT91C_REG *) 	0xFFFFF434) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_MDER (AT91C_CAST(AT91C_REG *) 	0xFFFFF450) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF404) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_IFSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF428) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF408) // (PIOB) PIO Status Register
+#define AT91C_PIOB_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 	0xFFFFF4B0) // (PIOB) PIO Slewrate Control Register
+#define AT91C_PIOB_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF440) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_PPUDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF460) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF400) // (PIOB) PIO Enable Register
+#define AT91C_PIOB_IFDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF424) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF444) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF4A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_ODSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF438) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_DELAY2 (AT91C_CAST(AT91C_REG *) 	0xFFFFF4C4) // (PIOB) PIO Delay Control Register
+#define AT91C_PIOB_OWSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF4A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_BSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF474) // (PIOB) Select B Register
+#define AT91C_PIOB_IFER (AT91C_CAST(AT91C_REG *) 	0xFFFFF420) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_OWER (AT91C_CAST(AT91C_REG *) 	0xFFFFF4A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_PPUER (AT91C_CAST(AT91C_REG *) 	0xFFFFF464) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_OSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF418) // (PIOB) Output Status Register
+#define AT91C_PIOB_ASR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF470) // (PIOB) Select A Register
+#define AT91C_PIOB_OER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF410) // (PIOB) Output Enable Register
+#define AT91C_PIOB_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFFF4FC) // (PIOB) PIO Version Register
+#define AT91C_PIOB_DELAY1 (AT91C_CAST(AT91C_REG *) 	0xFFFFF4C0) // (PIOB) PIO Delay Control Register
+// ========== Register definition for PIOC peripheral ========== 
+#define AT91C_PIOC_OWDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF6A4) // (PIOC) Output Write Disable Register
+#define AT91C_PIOC_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF648) // (PIOC) Interrupt Mask Register
+#define AT91C_PIOC_ASR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF670) // (PIOC) Select A Register
+#define AT91C_PIOC_PPUDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF660) // (PIOC) Pull-up Disable Register
+#define AT91C_PIOC_CODR (AT91C_CAST(AT91C_REG *) 	0xFFFFF634) // (PIOC) Clear Output Data Register
+#define AT91C_PIOC_OWER (AT91C_CAST(AT91C_REG *) 	0xFFFFF6A0) // (PIOC) Output Write Enable Register
+#define AT91C_PIOC_ABSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF678) // (PIOC) AB Select Status Register
+#define AT91C_PIOC_IFDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF624) // (PIOC) Input Filter Disable Register
+#define AT91C_PIOC_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFFF6FC) // (PIOC) PIO Version Register
+#define AT91C_PIOC_ODR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF614) // (PIOC) Output Disable Registerr
+#define AT91C_PIOC_PPUER (AT91C_CAST(AT91C_REG *) 	0xFFFFF664) // (PIOC) Pull-up Enable Register
+#define AT91C_PIOC_SODR (AT91C_CAST(AT91C_REG *) 	0xFFFFF630) // (PIOC) Set Output Data Register
+#define AT91C_PIOC_ISR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF64C) // (PIOC) Interrupt Status Register
+#define AT91C_PIOC_OSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF618) // (PIOC) Output Status Register
+#define AT91C_PIOC_MDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF658) // (PIOC) Multi-driver Status Register
+#define AT91C_PIOC_IFER (AT91C_CAST(AT91C_REG *) 	0xFFFFF620) // (PIOC) Input Filter Enable Register
+#define AT91C_PIOC_DELAY2 (AT91C_CAST(AT91C_REG *) 	0xFFFFF6C4) // (PIOC) PIO Delay Control Register
+#define AT91C_PIOC_MDER (AT91C_CAST(AT91C_REG *) 	0xFFFFF650) // (PIOC) Multi-driver Enable Register
+#define AT91C_PIOC_PPUSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF668) // (PIOC) Pull-up Status Register
+#define AT91C_PIOC_PSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF608) // (PIOC) PIO Status Register
+#define AT91C_PIOC_DELAY4 (AT91C_CAST(AT91C_REG *) 	0xFFFFF6CC) // (PIOC) PIO Delay Control Register
+#define AT91C_PIOC_DELAY3 (AT91C_CAST(AT91C_REG *) 	0xFFFFF6C8) // (PIOC) PIO Delay Control Register
+#define AT91C_PIOC_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF640) // (PIOC) Interrupt Enable Register
+#define AT91C_PIOC_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 	0xFFFFF6B0) // (PIOC) PIO Slewrate Control Register
+#define AT91C_PIOC_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF644) // (PIOC) Interrupt Disable Register
+#define AT91C_PIOC_PDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF63C) // (PIOC) Pin Data Status Register
+#define AT91C_PIOC_DELAY1 (AT91C_CAST(AT91C_REG *) 	0xFFFFF6C0) // (PIOC) PIO Delay Control Register
+#define AT91C_PIOC_PDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF604) // (PIOC) PIO Disable Register
+#define AT91C_PIOC_OWSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF6A8) // (PIOC) Output Write Status Register
+#define AT91C_PIOC_IFSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF628) // (PIOC) Input Filter Status Register
+#define AT91C_PIOC_ODSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF638) // (PIOC) Output Data Status Register
+#define AT91C_PIOC_OER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF610) // (PIOC) Output Enable Register
+#define AT91C_PIOC_MDDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF654) // (PIOC) Multi-driver Disable Register
+#define AT91C_PIOC_BSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF674) // (PIOC) Select B Register
+#define AT91C_PIOC_PER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF600) // (PIOC) PIO Enable Register
+// ========== Register definition for PIOD peripheral ========== 
+#define AT91C_PIOD_DELAY1 (AT91C_CAST(AT91C_REG *) 	0xFFFFF8C0) // (PIOD) PIO Delay Control Register
+#define AT91C_PIOD_OWDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF8A4) // (PIOD) Output Write Disable Register
+#define AT91C_PIOD_SODR (AT91C_CAST(AT91C_REG *) 	0xFFFFF830) // (PIOD) Set Output Data Register
+#define AT91C_PIOD_PPUER (AT91C_CAST(AT91C_REG *) 	0xFFFFF864) // (PIOD) Pull-up Enable Register
+#define AT91C_PIOD_CODR (AT91C_CAST(AT91C_REG *) 	0xFFFFF834) // (PIOD) Clear Output Data Register
+#define AT91C_PIOD_DELAY4 (AT91C_CAST(AT91C_REG *) 	0xFFFFF8CC) // (PIOD) PIO Delay Control Register
+#define AT91C_PIOD_PSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF808) // (PIOD) PIO Status Register
+#define AT91C_PIOD_PDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF804) // (PIOD) PIO Disable Register
+#define AT91C_PIOD_ODR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF814) // (PIOD) Output Disable Registerr
+#define AT91C_PIOD_PPUSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF868) // (PIOD) Pull-up Status Register
+#define AT91C_PIOD_IFSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF828) // (PIOD) Input Filter Status Register
+#define AT91C_PIOD_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF848) // (PIOD) Interrupt Mask Register
+#define AT91C_PIOD_ASR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF870) // (PIOD) Select A Register
+#define AT91C_PIOD_DELAY2 (AT91C_CAST(AT91C_REG *) 	0xFFFFF8C4) // (PIOD) PIO Delay Control Register
+#define AT91C_PIOD_OWSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF8A8) // (PIOD) Output Write Status Register
+#define AT91C_PIOD_PER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF800) // (PIOD) PIO Enable Register
+#define AT91C_PIOD_MDER (AT91C_CAST(AT91C_REG *) 	0xFFFFF850) // (PIOD) Multi-driver Enable Register
+#define AT91C_PIOD_PDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF83C) // (PIOD) Pin Data Status Register
+#define AT91C_PIOD_MDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF858) // (PIOD) Multi-driver Status Register
+#define AT91C_PIOD_OWER (AT91C_CAST(AT91C_REG *) 	0xFFFFF8A0) // (PIOD) Output Write Enable Register
+#define AT91C_PIOD_BSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF874) // (PIOD) Select B Register
+#define AT91C_PIOD_IFDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF824) // (PIOD) Input Filter Disable Register
+#define AT91C_PIOD_DELAY3 (AT91C_CAST(AT91C_REG *) 	0xFFFFF8C8) // (PIOD) PIO Delay Control Register
+#define AT91C_PIOD_ABSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF878) // (PIOD) AB Select Status Register
+#define AT91C_PIOD_OER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF810) // (PIOD) Output Enable Register
+#define AT91C_PIOD_MDDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF854) // (PIOD) Multi-driver Disable Register
+#define AT91C_PIOD_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF844) // (PIOD) Interrupt Disable Register
+#define AT91C_PIOD_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFFF840) // (PIOD) Interrupt Enable Register
+#define AT91C_PIOD_PPUDR (AT91C_CAST(AT91C_REG *) 	0xFFFFF860) // (PIOD) Pull-up Disable Register
+#define AT91C_PIOD_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFFF8FC) // (PIOD) PIO Version Register
+#define AT91C_PIOD_ISR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF84C) // (PIOD) Interrupt Status Register
+#define AT91C_PIOD_ODSR (AT91C_CAST(AT91C_REG *) 	0xFFFFF838) // (PIOD) Output Data Status Register
+#define AT91C_PIOD_OSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFF818) // (PIOD) Output Status Register
+#define AT91C_PIOD_IFER (AT91C_CAST(AT91C_REG *) 	0xFFFFF820) // (PIOD) Input Filter Enable Register
+#define AT91C_PIOD_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 	0xFFFFF8B0) // (PIOD) PIO Slewrate Control Register
+// ========== Register definition for PIOE peripheral ========== 
+#define AT91C_PIOE_ODSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA38) // (PIOE) Output Data Status Register
+#define AT91C_PIOE_ABSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA78) // (PIOE) AB Select Status Register
+#define AT91C_PIOE_PSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA08) // (PIOE) PIO Status Register
+#define AT91C_PIOE_PPUDR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA60) // (PIOE) Pull-up Disable Register
+#define AT91C_PIOE_OER  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA10) // (PIOE) Output Enable Register
+#define AT91C_PIOE_IFSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA28) // (PIOE) Input Filter Status Register
+#define AT91C_PIOE_IFER (AT91C_CAST(AT91C_REG *) 	0xFFFFFA20) // (PIOE) Input Filter Enable Register
+#define AT91C_PIOE_DELAY3 (AT91C_CAST(AT91C_REG *) 	0xFFFFFAC8) // (PIOE) PIO Delay Control Register
+#define AT91C_PIOE_ODR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA14) // (PIOE) Output Disable Registerr
+#define AT91C_PIOE_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA44) // (PIOE) Interrupt Disable Register
+#define AT91C_PIOE_DELAY1 (AT91C_CAST(AT91C_REG *) 	0xFFFFFAC0) // (PIOE) PIO Delay Control Register
+#define AT91C_PIOE_OSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA18) // (PIOE) Output Status Register
+#define AT91C_PIOE_CODR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA34) // (PIOE) Clear Output Data Register
+#define AT91C_PIOE_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFFFAFC) // (PIOE) PIO Version Register
+#define AT91C_PIOE_MDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA58) // (PIOE) Multi-driver Status Register
+#define AT91C_PIOE_PDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA04) // (PIOE) PIO Disable Register
+#define AT91C_PIOE_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA40) // (PIOE) Interrupt Enable Register
+#define AT91C_PIOE_OWSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFAA8) // (PIOE) Output Write Status Register
+#define AT91C_PIOE_BSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA74) // (PIOE) Select B Register
+#define AT91C_PIOE_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 	0xFFFFFAB0) // (PIOE) PIO Slewrate Control Register
+#define AT91C_PIOE_DELAY4 (AT91C_CAST(AT91C_REG *) 	0xFFFFFACC) // (PIOE) PIO Delay Control Register
+#define AT91C_PIOE_PER  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA00) // (PIOE) PIO Enable Register
+#define AT91C_PIOE_OWDR (AT91C_CAST(AT91C_REG *) 	0xFFFFFAA4) // (PIOE) Output Write Disable Register
+#define AT91C_PIOE_IFDR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA24) // (PIOE) Input Filter Disable Register
+#define AT91C_PIOE_PPUSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA68) // (PIOE) Pull-up Status Register
+#define AT91C_PIOE_PDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA3C) // (PIOE) Pin Data Status Register
+#define AT91C_PIOE_PPUER (AT91C_CAST(AT91C_REG *) 	0xFFFFFA64) // (PIOE) Pull-up Enable Register
+#define AT91C_PIOE_MDDR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA54) // (PIOE) Multi-driver Disable Register
+#define AT91C_PIOE_ISR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA4C) // (PIOE) Interrupt Status Register
+#define AT91C_PIOE_DELAY2 (AT91C_CAST(AT91C_REG *) 	0xFFFFFAC4) // (PIOE) PIO Delay Control Register
+#define AT91C_PIOE_SODR (AT91C_CAST(AT91C_REG *) 	0xFFFFFA30) // (PIOE) Set Output Data Register
+#define AT91C_PIOE_ASR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA70) // (PIOE) Select A Register
+#define AT91C_PIOE_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFA48) // (PIOE) Interrupt Mask Register
+#define AT91C_PIOE_OWER (AT91C_CAST(AT91C_REG *) 	0xFFFFFAA0) // (PIOE) Output Write Enable Register
+#define AT91C_PIOE_MDER (AT91C_CAST(AT91C_REG *) 	0xFFFFFA50) // (PIOE) Multi-driver Enable Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFFFFCEC) // (PMC) 
+#define AT91C_PMC_PCER  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock 0 Register
+#define AT91C_PMC_MCKR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_PLLAR (AT91C_CAST(AT91C_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
+#define AT91C_PMC_NAME2 (AT91C_CAST(AT91C_REG *) 	0xFFFFFCF4) // (PMC) 
+#define AT91C_PMC_PCDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_MCFR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFFFFCF8) // (PMC) 
+#define AT91C_PMC_PLLICPR (AT91C_CAST(AT91C_REG *) 	0xFFFFFC80) // (PMC) PLL Charge Pump Current Register
+#define AT91C_PMC_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   (AT91C_CAST(AT91C_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_UCKR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC1C) // (PMC) UTMI Clock Configuration Register
+#define AT91C_PMC_USB   (AT91C_CAST(AT91C_REG *) 	0xFFFFFC38) // (PMC) USB clock register
+#define AT91C_PMC_MOR   (AT91C_CAST(AT91C_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_NAME1 (AT91C_CAST(AT91C_REG *) 	0xFFFFFCF0) // (PMC) 
+#define AT91C_PMC_SCDR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_SCER  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFFFCFC) // (PMC) 
+#define AT91C_PMC_SR    (AT91C_CAST(AT91C_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_MCFR (AT91C_CAST(AT91C_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+#define AT91C_CKGR_PLLAR (AT91C_CAST(AT91C_REG *) 	0xFFFFFC28) // (CKGR) PLL A Register
+#define AT91C_CKGR_UCKR (AT91C_CAST(AT91C_REG *) 	0xFFFFFC1C) // (CKGR) UTMI Clock Configuration Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_VER  (AT91C_CAST(AT91C_REG *) 	0xFFFFFDFC) // (RSTC) Version Register
+#define AT91C_RSTC_RMR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for SHDWC peripheral ========== 
+#define AT91C_SHDWC_SHSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD18) // (SHDWC) Shut Down Status Register
+#define AT91C_SHDWC_SHMR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD14) // (SHDWC) Shut Down Mode Register
+#define AT91C_SHDWC_SHCR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD10) // (SHDWC) Shut Down Control Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (AT91C_CAST(AT91C_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for RTC peripheral ========== 
+#define AT91C_RTC_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFFFFDD4) // (RTC) Interrupt Disable Register
+#define AT91C_RTC_SR    (AT91C_CAST(AT91C_REG *) 	0xFFFFFDC8) // (RTC) Status Register
+#define AT91C_RTC_MR    (AT91C_CAST(AT91C_REG *) 	0xFFFFFDB4) // (RTC) Mode Register
+#define AT91C_RTC_IER   (AT91C_CAST(AT91C_REG *) 	0xFFFFFDD0) // (RTC) Interrupt Enable Register
+#define AT91C_RTC_TIMALR (AT91C_CAST(AT91C_REG *) 	0xFFFFFDC0) // (RTC) Time Alarm Register
+#define AT91C_RTC_CALALR (AT91C_CAST(AT91C_REG *) 	0xFFFFFDC4) // (RTC) Calendar Alarm Register
+#define AT91C_RTC_CR    (AT91C_CAST(AT91C_REG *) 	0xFFFFFDB0) // (RTC) Control Register
+#define AT91C_RTC_TIMR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFDB8) // (RTC) Time Register
+#define AT91C_RTC_CALR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFDBC) // (RTC) Calendar Register
+#define AT91C_RTC_VER   (AT91C_CAST(AT91C_REG *) 	0xFFFFFDDC) // (RTC) Valid Entry Register
+#define AT91C_RTC_SCCR  (AT91C_CAST(AT91C_REG *) 	0xFFFFFDCC) // (RTC) Status Clear Command Register
+#define AT91C_RTC_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFFFFDD8) // (RTC) Interrupt Mask Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_IER   (AT91C_CAST(AT91C_REG *) 	0xFFF7C024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C02C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_CCR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C000) // (TC0) Channel Control Register
+#define AT91C_TC0_RB    (AT91C_CAST(AT91C_REG *) 	0xFFF7C018) // (TC0) Register B
+#define AT91C_TC0_CV    (AT91C_CAST(AT91C_REG *) 	0xFFF7C010) // (TC0) Counter Value
+#define AT91C_TC0_SR    (AT91C_CAST(AT91C_REG *) 	0xFFF7C020) // (TC0) Status Register
+#define AT91C_TC0_CMR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_RA    (AT91C_CAST(AT91C_REG *) 	0xFFF7C014) // (TC0) Register A
+#define AT91C_TC0_RC    (AT91C_CAST(AT91C_REG *) 	0xFFF7C01C) // (TC0) Register C
+#define AT91C_TC0_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C028) // (TC0) Interrupt Disable Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_IER   (AT91C_CAST(AT91C_REG *) 	0xFFF7C064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_SR    (AT91C_CAST(AT91C_REG *) 	0xFFF7C060) // (TC1) Status Register
+#define AT91C_TC1_RC    (AT91C_CAST(AT91C_REG *) 	0xFFF7C05C) // (TC1) Register C
+#define AT91C_TC1_CV    (AT91C_CAST(AT91C_REG *) 	0xFFF7C050) // (TC1) Counter Value
+#define AT91C_TC1_RA    (AT91C_CAST(AT91C_REG *) 	0xFFF7C054) // (TC1) Register A
+#define AT91C_TC1_CMR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_RB    (AT91C_CAST(AT91C_REG *) 	0xFFF7C058) // (TC1) Register B
+#define AT91C_TC1_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C06C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CCR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C040) // (TC1) Channel Control Register
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_SR    (AT91C_CAST(AT91C_REG *) 	0xFFF7C0A0) // (TC2) Status Register
+#define AT91C_TC2_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C0AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER   (AT91C_CAST(AT91C_REG *) 	0xFFF7C0A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_CV    (AT91C_CAST(AT91C_REG *) 	0xFFF7C090) // (TC2) Counter Value
+#define AT91C_TC2_RB    (AT91C_CAST(AT91C_REG *) 	0xFFF7C098) // (TC2) Register B
+#define AT91C_TC2_CCR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C080) // (TC2) Channel Control Register
+#define AT91C_TC2_CMR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_RA    (AT91C_CAST(AT91C_REG *) 	0xFFF7C094) // (TC2) Register A
+#define AT91C_TC2_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFF7C0A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_RC    (AT91C_CAST(AT91C_REG *) 	0xFFF7C09C) // (TC2) Register C
+// ========== Register definition for TC3 peripheral ========== 
+#define AT91C_TC3_SR    (AT91C_CAST(AT91C_REG *) 	0xFFFD4020) // (TC3) Status Register
+#define AT91C_TC3_RC    (AT91C_CAST(AT91C_REG *) 	0xFFFD401C) // (TC3) Register C
+#define AT91C_TC3_IER   (AT91C_CAST(AT91C_REG *) 	0xFFFD4024) // (TC3) Interrupt Enable Register
+#define AT91C_TC3_CV    (AT91C_CAST(AT91C_REG *) 	0xFFFD4010) // (TC3) Counter Value
+#define AT91C_TC3_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFFD4028) // (TC3) Interrupt Disable Register
+#define AT91C_TC3_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFFD402C) // (TC3) Interrupt Mask Register
+#define AT91C_TC3_CMR   (AT91C_CAST(AT91C_REG *) 	0xFFFD4004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC3_RB    (AT91C_CAST(AT91C_REG *) 	0xFFFD4018) // (TC3) Register B
+#define AT91C_TC3_CCR   (AT91C_CAST(AT91C_REG *) 	0xFFFD4000) // (TC3) Channel Control Register
+#define AT91C_TC3_RA    (AT91C_CAST(AT91C_REG *) 	0xFFFD4014) // (TC3) Register A
+// ========== Register definition for TC4 peripheral ========== 
+#define AT91C_TC4_CV    (AT91C_CAST(AT91C_REG *) 	0xFFFD4050) // (TC4) Counter Value
+#define AT91C_TC4_RA    (AT91C_CAST(AT91C_REG *) 	0xFFFD4054) // (TC4) Register A
+#define AT91C_TC4_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFFD4068) // (TC4) Interrupt Disable Register
+#define AT91C_TC4_SR    (AT91C_CAST(AT91C_REG *) 	0xFFFD4060) // (TC4) Status Register
+#define AT91C_TC4_CMR   (AT91C_CAST(AT91C_REG *) 	0xFFFD4044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC4_CCR   (AT91C_CAST(AT91C_REG *) 	0xFFFD4040) // (TC4) Channel Control Register
+#define AT91C_TC4_RB    (AT91C_CAST(AT91C_REG *) 	0xFFFD4058) // (TC4) Register B
+#define AT91C_TC4_RC    (AT91C_CAST(AT91C_REG *) 	0xFFFD405C) // (TC4) Register C
+#define AT91C_TC4_IER   (AT91C_CAST(AT91C_REG *) 	0xFFFD4064) // (TC4) Interrupt Enable Register
+#define AT91C_TC4_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFFD406C) // (TC4) Interrupt Mask Register
+// ========== Register definition for TC5 peripheral ========== 
+#define AT91C_TC5_IER   (AT91C_CAST(AT91C_REG *) 	0xFFFD40A4) // (TC5) Interrupt Enable Register
+#define AT91C_TC5_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFFD40A8) // (TC5) Interrupt Disable Register
+#define AT91C_TC5_RA    (AT91C_CAST(AT91C_REG *) 	0xFFFD4094) // (TC5) Register A
+#define AT91C_TC5_RB    (AT91C_CAST(AT91C_REG *) 	0xFFFD4098) // (TC5) Register B
+#define AT91C_TC5_CCR   (AT91C_CAST(AT91C_REG *) 	0xFFFD4080) // (TC5) Channel Control Register
+#define AT91C_TC5_SR    (AT91C_CAST(AT91C_REG *) 	0xFFFD40A0) // (TC5) Status Register
+#define AT91C_TC5_CV    (AT91C_CAST(AT91C_REG *) 	0xFFFD4090) // (TC5) Counter Value
+#define AT91C_TC5_RC    (AT91C_CAST(AT91C_REG *) 	0xFFFD409C) // (TC5) Register C
+#define AT91C_TC5_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFFD40AC) // (TC5) Interrupt Mask Register
+#define AT91C_TC5_CMR   (AT91C_CAST(AT91C_REG *) 	0xFFFD4084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
+// ========== Register definition for TCB0 peripheral ========== 
+#define AT91C_TCB0_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF7C0F0) // (TCB0) TC IPNAME1 REGISTER 
+#define AT91C_TCB0_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF7C0F4) // (TCB0) TC IPNAME2 REGISTER 
+#define AT91C_TCB0_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF7C0F8) // (TCB0) TC FEATURES REGISTER 
+#define AT91C_TCB0_BCR  (AT91C_CAST(AT91C_REG *) 	0xFFF7C0C0) // (TCB0) TC Block Control Register
+#define AT91C_TCB0_VER  (AT91C_CAST(AT91C_REG *) 	0xFFF7C0FC) // (TCB0)  Version Register
+#define AT91C_TCB0_BMR  (AT91C_CAST(AT91C_REG *) 	0xFFF7C0C4) // (TCB0) TC Block Mode Register
+#define AT91C_TCB0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF7C0EC) // (TCB0) TC ADDRSIZE REGISTER 
+// ========== Register definition for TCB1 peripheral ========== 
+#define AT91C_TCB1_VER  (AT91C_CAST(AT91C_REG *) 	0xFFFD40FC) // (TCB1)  Version Register
+#define AT91C_TCB1_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFFD40F4) // (TCB1) TC IPNAME2 REGISTER 
+#define AT91C_TCB1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFFD40EC) // (TCB1) TC ADDRSIZE REGISTER 
+#define AT91C_TCB1_BMR  (AT91C_CAST(AT91C_REG *) 	0xFFFD40C4) // (TCB1) TC Block Mode Register
+#define AT91C_TCB1_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFFD40F8) // (TCB1) TC FEATURES REGISTER 
+#define AT91C_TCB1_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFFD40F0) // (TCB1) TC IPNAME1 REGISTER 
+#define AT91C_TCB1_BCR  (AT91C_CAST(AT91C_REG *) 	0xFFFD40C0) // (TCB1) TC Block Control Register
+// ========== Register definition for MCI0 peripheral ========== 
+#define AT91C_MCI0_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFF8004C) // (MCI0) MCI Interrupt Mask Register
+#define AT91C_MCI0_MR   (AT91C_CAST(AT91C_REG *) 	0xFFF80004) // (MCI0) MCI Mode Register
+#define AT91C_MCI0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF800EC) // (MCI0) MCI ADDRSIZE REGISTER 
+#define AT91C_MCI0_CR   (AT91C_CAST(AT91C_REG *) 	0xFFF80000) // (MCI0) MCI Control Register
+#define AT91C_MCI0_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF800F4) // (MCI0) MCI IPNAME2 REGISTER 
+#define AT91C_MCI0_IER  (AT91C_CAST(AT91C_REG *) 	0xFFF80044) // (MCI0) MCI Interrupt Enable Register
+#define AT91C_MCI0_FIFO (AT91C_CAST(AT91C_REG *) 	0xFFF80200) // (MCI0) MCI FIFO Aperture Register
+#define AT91C_MCI0_DTOR (AT91C_CAST(AT91C_REG *) 	0xFFF80008) // (MCI0) MCI Data Timeout Register
+#define AT91C_MCI0_SDCR (AT91C_CAST(AT91C_REG *) 	0xFFF8000C) // (MCI0) MCI SD/SDIO Card Register
+#define AT91C_MCI0_BLKR (AT91C_CAST(AT91C_REG *) 	0xFFF80018) // (MCI0) MCI Block Register
+#define AT91C_MCI0_VER  (AT91C_CAST(AT91C_REG *) 	0xFFF800FC) // (MCI0) MCI VERSION REGISTER 
+#define AT91C_MCI0_WPSR (AT91C_CAST(AT91C_REG *) 	0xFFF800E8) // (MCI0) MCI Write Protection Status Register
+#define AT91C_MCI0_CMDR (AT91C_CAST(AT91C_REG *) 	0xFFF80014) // (MCI0) MCI Command Register
+#define AT91C_MCI0_CSTOR (AT91C_CAST(AT91C_REG *) 	0xFFF8001C) // (MCI0) MCI Completion Signal Timeout Register
+#define AT91C_MCI0_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF800F0) // (MCI0) MCI IPNAME1 REGISTER 
+#define AT91C_MCI0_DMA  (AT91C_CAST(AT91C_REG *) 	0xFFF80050) // (MCI0) MCI DMA Configuration Register
+#define AT91C_MCI0_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF800F8) // (MCI0) MCI FEATURES REGISTER 
+#define AT91C_MCI0_RDR  (AT91C_CAST(AT91C_REG *) 	0xFFF80030) // (MCI0) MCI Receive Data Register
+#define AT91C_MCI0_SR   (AT91C_CAST(AT91C_REG *) 	0xFFF80040) // (MCI0) MCI Status Register
+#define AT91C_MCI0_TDR  (AT91C_CAST(AT91C_REG *) 	0xFFF80034) // (MCI0) MCI Transmit Data Register
+#define AT91C_MCI0_CFG  (AT91C_CAST(AT91C_REG *) 	0xFFF80054) // (MCI0) MCI Configuration Register
+#define AT91C_MCI0_ARGR (AT91C_CAST(AT91C_REG *) 	0xFFF80010) // (MCI0) MCI Argument Register
+#define AT91C_MCI0_RSPR (AT91C_CAST(AT91C_REG *) 	0xFFF80020) // (MCI0) MCI Response Register
+#define AT91C_MCI0_WPCR (AT91C_CAST(AT91C_REG *) 	0xFFF800E4) // (MCI0) MCI Write Protection Control Register
+#define AT91C_MCI0_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFF80048) // (MCI0) MCI Interrupt Disable Register
+// ========== Register definition for MCI1 peripheral ========== 
+#define AT91C_MCI1_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFFD00F0) // (MCI1) MCI IPNAME1 REGISTER 
+#define AT91C_MCI1_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFD0048) // (MCI1) MCI Interrupt Disable Register
+#define AT91C_MCI1_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFFD00F4) // (MCI1) MCI IPNAME2 REGISTER 
+#define AT91C_MCI1_MR   (AT91C_CAST(AT91C_REG *) 	0xFFFD0004) // (MCI1) MCI Mode Register
+#define AT91C_MCI1_SR   (AT91C_CAST(AT91C_REG *) 	0xFFFD0040) // (MCI1) MCI Status Register
+#define AT91C_MCI1_DTOR (AT91C_CAST(AT91C_REG *) 	0xFFFD0008) // (MCI1) MCI Data Timeout Register
+#define AT91C_MCI1_WPCR (AT91C_CAST(AT91C_REG *) 	0xFFFD00E4) // (MCI1) MCI Write Protection Control Register
+#define AT91C_MCI1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFFD00EC) // (MCI1) MCI ADDRSIZE REGISTER 
+#define AT91C_MCI1_ARGR (AT91C_CAST(AT91C_REG *) 	0xFFFD0010) // (MCI1) MCI Argument Register
+#define AT91C_MCI1_FIFO (AT91C_CAST(AT91C_REG *) 	0xFFFD0200) // (MCI1) MCI FIFO Aperture Register
+#define AT91C_MCI1_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFD0044) // (MCI1) MCI Interrupt Enable Register
+#define AT91C_MCI1_SDCR (AT91C_CAST(AT91C_REG *) 	0xFFFD000C) // (MCI1) MCI SD/SDIO Card Register
+#define AT91C_MCI1_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFFD00F8) // (MCI1) MCI FEATURES REGISTER 
+#define AT91C_MCI1_CR   (AT91C_CAST(AT91C_REG *) 	0xFFFD0000) // (MCI1) MCI Control Register
+#define AT91C_MCI1_CSTOR (AT91C_CAST(AT91C_REG *) 	0xFFFD001C) // (MCI1) MCI Completion Signal Timeout Register
+#define AT91C_MCI1_RSPR (AT91C_CAST(AT91C_REG *) 	0xFFFD0020) // (MCI1) MCI Response Register
+#define AT91C_MCI1_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFD004C) // (MCI1) MCI Interrupt Mask Register
+#define AT91C_MCI1_DMA  (AT91C_CAST(AT91C_REG *) 	0xFFFD0050) // (MCI1) MCI DMA Configuration Register
+#define AT91C_MCI1_BLKR (AT91C_CAST(AT91C_REG *) 	0xFFFD0018) // (MCI1) MCI Block Register
+#define AT91C_MCI1_RDR  (AT91C_CAST(AT91C_REG *) 	0xFFFD0030) // (MCI1) MCI Receive Data Register
+#define AT91C_MCI1_CFG  (AT91C_CAST(AT91C_REG *) 	0xFFFD0054) // (MCI1) MCI Configuration Register
+#define AT91C_MCI1_WPSR (AT91C_CAST(AT91C_REG *) 	0xFFFD00E8) // (MCI1) MCI Write Protection Status Register
+#define AT91C_MCI1_CMDR (AT91C_CAST(AT91C_REG *) 	0xFFFD0014) // (MCI1) MCI Command Register
+#define AT91C_MCI1_TDR  (AT91C_CAST(AT91C_REG *) 	0xFFFD0034) // (MCI1) MCI Transmit Data Register
+#define AT91C_MCI1_VER  (AT91C_CAST(AT91C_REG *) 	0xFFFD00FC) // (MCI1) MCI VERSION REGISTER 
+// ========== Register definition for TWI0 peripheral ========== 
+#define AT91C_TWI0_RHR  (AT91C_CAST(AT91C_REG *) 	0xFFF84030) // (TWI0) Receive Holding Register
+#define AT91C_TWI0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF840EC) // (TWI0) TWI ADDRSIZE REGISTER 
+#define AT91C_TWI0_SMR  (AT91C_CAST(AT91C_REG *) 	0xFFF84008) // (TWI0) Slave Mode Register
+#define AT91C_TWI0_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFF84028) // (TWI0) Interrupt Disable Register
+#define AT91C_TWI0_CWGR (AT91C_CAST(AT91C_REG *) 	0xFFF84010) // (TWI0) Clock Waveform Generator Register
+#define AT91C_TWI0_IER  (AT91C_CAST(AT91C_REG *) 	0xFFF84024) // (TWI0) Interrupt Enable Register
+#define AT91C_TWI0_THR  (AT91C_CAST(AT91C_REG *) 	0xFFF84034) // (TWI0) Transmit Holding Register
+#define AT91C_TWI0_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF840F4) // (TWI0) TWI IPNAME2 REGISTER 
+#define AT91C_TWI0_CR   (AT91C_CAST(AT91C_REG *) 	0xFFF84000) // (TWI0) Control Register
+#define AT91C_TWI0_MMR  (AT91C_CAST(AT91C_REG *) 	0xFFF84004) // (TWI0) Master Mode Register
+#define AT91C_TWI0_SR   (AT91C_CAST(AT91C_REG *) 	0xFFF84020) // (TWI0) Status Register
+#define AT91C_TWI0_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFF8402C) // (TWI0) Interrupt Mask Register
+#define AT91C_TWI0_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF840F8) // (TWI0) TWI FEATURES REGISTER 
+#define AT91C_TWI0_IADR (AT91C_CAST(AT91C_REG *) 	0xFFF8400C) // (TWI0) Internal Address Register
+#define AT91C_TWI0_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF840F0) // (TWI0) TWI IPNAME1 REGISTER 
+#define AT91C_TWI0_VER  (AT91C_CAST(AT91C_REG *) 	0xFFF840FC) // (TWI0) Version Register
+// ========== Register definition for TWI1 peripheral ========== 
+#define AT91C_TWI1_VER  (AT91C_CAST(AT91C_REG *) 	0xFFF880FC) // (TWI1) Version Register
+#define AT91C_TWI1_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFF8802C) // (TWI1) Interrupt Mask Register
+#define AT91C_TWI1_THR  (AT91C_CAST(AT91C_REG *) 	0xFFF88034) // (TWI1) Transmit Holding Register
+#define AT91C_TWI1_IER  (AT91C_CAST(AT91C_REG *) 	0xFFF88024) // (TWI1) Interrupt Enable Register
+#define AT91C_TWI1_MMR  (AT91C_CAST(AT91C_REG *) 	0xFFF88004) // (TWI1) Master Mode Register
+#define AT91C_TWI1_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF880F0) // (TWI1) TWI IPNAME1 REGISTER 
+#define AT91C_TWI1_CR   (AT91C_CAST(AT91C_REG *) 	0xFFF88000) // (TWI1) Control Register
+#define AT91C_TWI1_SR   (AT91C_CAST(AT91C_REG *) 	0xFFF88020) // (TWI1) Status Register
+#define AT91C_TWI1_CWGR (AT91C_CAST(AT91C_REG *) 	0xFFF88010) // (TWI1) Clock Waveform Generator Register
+#define AT91C_TWI1_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF880F4) // (TWI1) TWI IPNAME2 REGISTER 
+#define AT91C_TWI1_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFF88028) // (TWI1) Interrupt Disable Register
+#define AT91C_TWI1_RHR  (AT91C_CAST(AT91C_REG *) 	0xFFF88030) // (TWI1) Receive Holding Register
+#define AT91C_TWI1_IADR (AT91C_CAST(AT91C_REG *) 	0xFFF8800C) // (TWI1) Internal Address Register
+#define AT91C_TWI1_SMR  (AT91C_CAST(AT91C_REG *) 	0xFFF88008) // (TWI1) Slave Mode Register
+#define AT91C_TWI1_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF880F8) // (TWI1) TWI FEATURES REGISTER 
+#define AT91C_TWI1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF880EC) // (TWI1) TWI ADDRSIZE REGISTER 
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_PTSR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_PTCR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_RNCR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_RCR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_TNCR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C11C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TCR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C10C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RNPR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_RPR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_TPR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C108) // (PDC_US0) Transmit Pointer Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_MAN   (AT91C_CAST(AT91C_REG *) 	0xFFF8C050) // (US0) Manchester Encoder Decoder Register
+#define AT91C_US0_MR    (AT91C_CAST(AT91C_REG *) 	0xFFF8C004) // (US0) Mode Register
+#define AT91C_US0_RHR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C018) // (US0) Receiver Holding Register
+#define AT91C_US0_CSR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C014) // (US0) Channel Status Register
+#define AT91C_US0_CR    (AT91C_CAST(AT91C_REG *) 	0xFFF8C000) // (US0) Control Register
+#define AT91C_US0_VER   (AT91C_CAST(AT91C_REG *) 	0xFFF8C0FC) // (US0) VERSION Register
+#define AT91C_US0_IER   (AT91C_CAST(AT91C_REG *) 	0xFFF8C008) // (US0) Interrupt Enable Register
+#define AT91C_US0_BRGR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF8C0F8) // (US0) US FEATURES REGISTER 
+#define AT91C_US0_RTOR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C024) // (US0) Receiver Time-out Register
+#define AT91C_US0_THR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C01C) // (US0) Transmitter Holding Register
+#define AT91C_US0_NER   (AT91C_CAST(AT91C_REG *) 	0xFFF8C044) // (US0) Nb Errors Register
+#define AT91C_US0_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF8C0F0) // (US0) US IPNAME1 REGISTER 
+#define AT91C_US0_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C010) // (US0) Interrupt Mask Register
+#define AT91C_US0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF8C0EC) // (US0) US ADDRSIZE REGISTER 
+#define AT91C_US0_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFF8C00C) // (US0) Interrupt Disable Register
+#define AT91C_US0_FIDI  (AT91C_CAST(AT91C_REG *) 	0xFFF8C040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF8C0F4) // (US0) US IPNAME2 REGISTER 
+#define AT91C_US0_TTGR  (AT91C_CAST(AT91C_REG *) 	0xFFF8C028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_IF    (AT91C_CAST(AT91C_REG *) 	0xFFF8C04C) // (US0) IRDA_FILTER Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_PTCR  (AT91C_CAST(AT91C_REG *) 	0xFFF90120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TNCR  (AT91C_CAST(AT91C_REG *) 	0xFFF9011C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RCR   (AT91C_CAST(AT91C_REG *) 	0xFFF90104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RPR   (AT91C_CAST(AT91C_REG *) 	0xFFF90100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TPR   (AT91C_CAST(AT91C_REG *) 	0xFFF90108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_TCR   (AT91C_CAST(AT91C_REG *) 	0xFFF9010C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RNPR  (AT91C_CAST(AT91C_REG *) 	0xFFF90110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TNPR  (AT91C_CAST(AT91C_REG *) 	0xFFF90118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RNCR  (AT91C_CAST(AT91C_REG *) 	0xFFF90114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTSR  (AT91C_CAST(AT91C_REG *) 	0xFFF90124) // (PDC_US1) PDC Transfer Status Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF900F8) // (US1) US FEATURES REGISTER 
+#define AT91C_US1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF900EC) // (US1) US ADDRSIZE REGISTER 
+#define AT91C_US1_NER   (AT91C_CAST(AT91C_REG *) 	0xFFF90044) // (US1) Nb Errors Register
+#define AT91C_US1_RHR   (AT91C_CAST(AT91C_REG *) 	0xFFF90018) // (US1) Receiver Holding Register
+#define AT91C_US1_IF    (AT91C_CAST(AT91C_REG *) 	0xFFF9004C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_CR    (AT91C_CAST(AT91C_REG *) 	0xFFF90000) // (US1) Control Register
+#define AT91C_US1_TTGR  (AT91C_CAST(AT91C_REG *) 	0xFFF90028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_MR    (AT91C_CAST(AT91C_REG *) 	0xFFF90004) // (US1) Mode Register
+#define AT91C_US1_FIDI  (AT91C_CAST(AT91C_REG *) 	0xFFF90040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_RTOR  (AT91C_CAST(AT91C_REG *) 	0xFFF90024) // (US1) Receiver Time-out Register
+#define AT91C_US1_IER   (AT91C_CAST(AT91C_REG *) 	0xFFF90008) // (US1) Interrupt Enable Register
+#define AT91C_US1_MAN   (AT91C_CAST(AT91C_REG *) 	0xFFF90050) // (US1) Manchester Encoder Decoder Register
+#define AT91C_US1_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF900F4) // (US1) US IPNAME2 REGISTER 
+#define AT91C_US1_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFF90010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFF9000C) // (US1) Interrupt Disable Register
+#define AT91C_US1_CSR   (AT91C_CAST(AT91C_REG *) 	0xFFF90014) // (US1) Channel Status Register
+#define AT91C_US1_BRGR  (AT91C_CAST(AT91C_REG *) 	0xFFF90020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_THR   (AT91C_CAST(AT91C_REG *) 	0xFFF9001C) // (US1) Transmitter Holding Register
+#define AT91C_US1_VER   (AT91C_CAST(AT91C_REG *) 	0xFFF900FC) // (US1) VERSION Register
+#define AT91C_US1_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF900F0) // (US1) US IPNAME1 REGISTER 
+// ========== Register definition for PDC_US2 peripheral ========== 
+#define AT91C_US2_RNCR  (AT91C_CAST(AT91C_REG *) 	0xFFF94114) // (PDC_US2) Receive Next Counter Register
+#define AT91C_US2_PTCR  (AT91C_CAST(AT91C_REG *) 	0xFFF94120) // (PDC_US2) PDC Transfer Control Register
+#define AT91C_US2_TNPR  (AT91C_CAST(AT91C_REG *) 	0xFFF94118) // (PDC_US2) Transmit Next Pointer Register
+#define AT91C_US2_TNCR  (AT91C_CAST(AT91C_REG *) 	0xFFF9411C) // (PDC_US2) Transmit Next Counter Register
+#define AT91C_US2_TPR   (AT91C_CAST(AT91C_REG *) 	0xFFF94108) // (PDC_US2) Transmit Pointer Register
+#define AT91C_US2_RCR   (AT91C_CAST(AT91C_REG *) 	0xFFF94104) // (PDC_US2) Receive Counter Register
+#define AT91C_US2_PTSR  (AT91C_CAST(AT91C_REG *) 	0xFFF94124) // (PDC_US2) PDC Transfer Status Register
+#define AT91C_US2_TCR   (AT91C_CAST(AT91C_REG *) 	0xFFF9410C) // (PDC_US2) Transmit Counter Register
+#define AT91C_US2_RPR   (AT91C_CAST(AT91C_REG *) 	0xFFF94100) // (PDC_US2) Receive Pointer Register
+#define AT91C_US2_RNPR  (AT91C_CAST(AT91C_REG *) 	0xFFF94110) // (PDC_US2) Receive Next Pointer Register
+// ========== Register definition for US2 peripheral ========== 
+#define AT91C_US2_TTGR  (AT91C_CAST(AT91C_REG *) 	0xFFF94028) // (US2) Transmitter Time-guard Register
+#define AT91C_US2_IER   (AT91C_CAST(AT91C_REG *) 	0xFFF94008) // (US2) Interrupt Enable Register
+#define AT91C_US2_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF940EC) // (US2) US ADDRSIZE REGISTER 
+#define AT91C_US2_NER   (AT91C_CAST(AT91C_REG *) 	0xFFF94044) // (US2) Nb Errors Register
+#define AT91C_US2_CR    (AT91C_CAST(AT91C_REG *) 	0xFFF94000) // (US2) Control Register
+#define AT91C_US2_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFF9400C) // (US2) Interrupt Disable Register
+#define AT91C_US2_VER   (AT91C_CAST(AT91C_REG *) 	0xFFF940FC) // (US2) VERSION Register
+#define AT91C_US2_THR   (AT91C_CAST(AT91C_REG *) 	0xFFF9401C) // (US2) Transmitter Holding Register
+#define AT91C_US2_BRGR  (AT91C_CAST(AT91C_REG *) 	0xFFF94020) // (US2) Baud Rate Generator Register
+#define AT91C_US2_CSR   (AT91C_CAST(AT91C_REG *) 	0xFFF94014) // (US2) Channel Status Register
+#define AT91C_US2_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF940F4) // (US2) US IPNAME2 REGISTER 
+#define AT91C_US2_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFF94010) // (US2) Interrupt Mask Register
+#define AT91C_US2_RHR   (AT91C_CAST(AT91C_REG *) 	0xFFF94018) // (US2) Receiver Holding Register
+#define AT91C_US2_MR    (AT91C_CAST(AT91C_REG *) 	0xFFF94004) // (US2) Mode Register
+#define AT91C_US2_FIDI  (AT91C_CAST(AT91C_REG *) 	0xFFF94040) // (US2) FI_DI_Ratio Register
+#define AT91C_US2_MAN   (AT91C_CAST(AT91C_REG *) 	0xFFF94050) // (US2) Manchester Encoder Decoder Register
+#define AT91C_US2_IF    (AT91C_CAST(AT91C_REG *) 	0xFFF9404C) // (US2) IRDA_FILTER Register
+#define AT91C_US2_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF940F8) // (US2) US FEATURES REGISTER 
+#define AT91C_US2_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF940F0) // (US2) US IPNAME1 REGISTER 
+#define AT91C_US2_RTOR  (AT91C_CAST(AT91C_REG *) 	0xFFF94024) // (US2) Receiver Time-out Register
+// ========== Register definition for PDC_US3 peripheral ========== 
+#define AT91C_US3_PTSR  (AT91C_CAST(AT91C_REG *) 	0xFFF98124) // (PDC_US3) PDC Transfer Status Register
+#define AT91C_US3_TCR   (AT91C_CAST(AT91C_REG *) 	0xFFF9810C) // (PDC_US3) Transmit Counter Register
+#define AT91C_US3_RNPR  (AT91C_CAST(AT91C_REG *) 	0xFFF98110) // (PDC_US3) Receive Next Pointer Register
+#define AT91C_US3_RNCR  (AT91C_CAST(AT91C_REG *) 	0xFFF98114) // (PDC_US3) Receive Next Counter Register
+#define AT91C_US3_TNPR  (AT91C_CAST(AT91C_REG *) 	0xFFF98118) // (PDC_US3) Transmit Next Pointer Register
+#define AT91C_US3_RPR   (AT91C_CAST(AT91C_REG *) 	0xFFF98100) // (PDC_US3) Receive Pointer Register
+#define AT91C_US3_TPR   (AT91C_CAST(AT91C_REG *) 	0xFFF98108) // (PDC_US3) Transmit Pointer Register
+#define AT91C_US3_RCR   (AT91C_CAST(AT91C_REG *) 	0xFFF98104) // (PDC_US3) Receive Counter Register
+#define AT91C_US3_TNCR  (AT91C_CAST(AT91C_REG *) 	0xFFF9811C) // (PDC_US3) Transmit Next Counter Register
+#define AT91C_US3_PTCR  (AT91C_CAST(AT91C_REG *) 	0xFFF98120) // (PDC_US3) PDC Transfer Control Register
+// ========== Register definition for US3 peripheral ========== 
+#define AT91C_US3_VER   (AT91C_CAST(AT91C_REG *) 	0xFFF980FC) // (US3) VERSION Register
+#define AT91C_US3_BRGR  (AT91C_CAST(AT91C_REG *) 	0xFFF98020) // (US3) Baud Rate Generator Register
+#define AT91C_US3_TTGR  (AT91C_CAST(AT91C_REG *) 	0xFFF98028) // (US3) Transmitter Time-guard Register
+#define AT91C_US3_RTOR  (AT91C_CAST(AT91C_REG *) 	0xFFF98024) // (US3) Receiver Time-out Register
+#define AT91C_US3_MAN   (AT91C_CAST(AT91C_REG *) 	0xFFF98050) // (US3) Manchester Encoder Decoder Register
+#define AT91C_US3_NER   (AT91C_CAST(AT91C_REG *) 	0xFFF98044) // (US3) Nb Errors Register
+#define AT91C_US3_CR    (AT91C_CAST(AT91C_REG *) 	0xFFF98000) // (US3) Control Register
+#define AT91C_US3_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFF9800C) // (US3) Interrupt Disable Register
+#define AT91C_US3_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF980EC) // (US3) US ADDRSIZE REGISTER 
+#define AT91C_US3_CSR   (AT91C_CAST(AT91C_REG *) 	0xFFF98014) // (US3) Channel Status Register
+#define AT91C_US3_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF980F4) // (US3) US IPNAME2 REGISTER 
+#define AT91C_US3_IER   (AT91C_CAST(AT91C_REG *) 	0xFFF98008) // (US3) Interrupt Enable Register
+#define AT91C_US3_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF980F8) // (US3) US FEATURES REGISTER 
+#define AT91C_US3_MR    (AT91C_CAST(AT91C_REG *) 	0xFFF98004) // (US3) Mode Register
+#define AT91C_US3_IF    (AT91C_CAST(AT91C_REG *) 	0xFFF9804C) // (US3) IRDA_FILTER Register
+#define AT91C_US3_THR   (AT91C_CAST(AT91C_REG *) 	0xFFF9801C) // (US3) Transmitter Holding Register
+#define AT91C_US3_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFF98010) // (US3) Interrupt Mask Register
+#define AT91C_US3_FIDI  (AT91C_CAST(AT91C_REG *) 	0xFFF98040) // (US3) FI_DI_Ratio Register
+#define AT91C_US3_RHR   (AT91C_CAST(AT91C_REG *) 	0xFFF98018) // (US3) Receiver Holding Register
+#define AT91C_US3_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF980F0) // (US3) US IPNAME1 REGISTER 
+// ========== Register definition for PDC_SSC0 peripheral ========== 
+#define AT91C_SSC0_TNPR (AT91C_CAST(AT91C_REG *) 	0xFFF9C118) // (PDC_SSC0) Transmit Next Pointer Register
+#define AT91C_SSC0_PTSR (AT91C_CAST(AT91C_REG *) 	0xFFF9C124) // (PDC_SSC0) PDC Transfer Status Register
+#define AT91C_SSC0_TNCR (AT91C_CAST(AT91C_REG *) 	0xFFF9C11C) // (PDC_SSC0) Transmit Next Counter Register
+#define AT91C_SSC0_RNCR (AT91C_CAST(AT91C_REG *) 	0xFFF9C114) // (PDC_SSC0) Receive Next Counter Register
+#define AT91C_SSC0_TPR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C108) // (PDC_SSC0) Transmit Pointer Register
+#define AT91C_SSC0_RCR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C104) // (PDC_SSC0) Receive Counter Register
+#define AT91C_SSC0_PTCR (AT91C_CAST(AT91C_REG *) 	0xFFF9C120) // (PDC_SSC0) PDC Transfer Control Register
+#define AT91C_SSC0_RNPR (AT91C_CAST(AT91C_REG *) 	0xFFF9C110) // (PDC_SSC0) Receive Next Pointer Register
+#define AT91C_SSC0_TCR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C10C) // (PDC_SSC0) Transmit Counter Register
+#define AT91C_SSC0_RPR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C100) // (PDC_SSC0) Receive Pointer Register
+// ========== Register definition for SSC0 peripheral ========== 
+#define AT91C_SSC0_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF9C0F4) // (SSC0) SSC IPNAME2 REGISTER 
+#define AT91C_SSC0_SR   (AT91C_CAST(AT91C_REG *) 	0xFFF9C040) // (SSC0) Status Register
+#define AT91C_SSC0_TSHR (AT91C_CAST(AT91C_REG *) 	0xFFF9C034) // (SSC0) Transmit Sync Holding Register
+#define AT91C_SSC0_TCMR (AT91C_CAST(AT91C_REG *) 	0xFFF9C018) // (SSC0) Transmit Clock Mode Register
+#define AT91C_SSC0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF9C0EC) // (SSC0) SSC ADDRSIZE REGISTER 
+#define AT91C_SSC0_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C04C) // (SSC0) Interrupt Mask Register
+#define AT91C_SSC0_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C048) // (SSC0) Interrupt Disable Register
+#define AT91C_SSC0_CR   (AT91C_CAST(AT91C_REG *) 	0xFFF9C000) // (SSC0) Control Register
+#define AT91C_SSC0_VER  (AT91C_CAST(AT91C_REG *) 	0xFFF9C0FC) // (SSC0) Version Register
+#define AT91C_SSC0_RHR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C020) // (SSC0) Receive Holding Register
+#define AT91C_SSC0_THR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C024) // (SSC0) Transmit Holding Register
+#define AT91C_SSC0_CMR  (AT91C_CAST(AT91C_REG *) 	0xFFF9C004) // (SSC0) Clock Mode Register
+#define AT91C_SSC0_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF9C0F8) // (SSC0) SSC FEATURES REGISTER 
+#define AT91C_SSC0_RCMR (AT91C_CAST(AT91C_REG *) 	0xFFF9C010) // (SSC0) Receive Clock ModeRegister
+#define AT91C_SSC0_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF9C0F0) // (SSC0) SSC IPNAME1 REGISTER 
+#define AT91C_SSC0_RSHR (AT91C_CAST(AT91C_REG *) 	0xFFF9C030) // (SSC0) Receive Sync Holding Register
+#define AT91C_SSC0_IER  (AT91C_CAST(AT91C_REG *) 	0xFFF9C044) // (SSC0) Interrupt Enable Register
+#define AT91C_SSC0_TFMR (AT91C_CAST(AT91C_REG *) 	0xFFF9C01C) // (SSC0) Transmit Frame Mode Register
+#define AT91C_SSC0_RFMR (AT91C_CAST(AT91C_REG *) 	0xFFF9C014) // (SSC0) Receive Frame Mode Register
+// ========== Register definition for PDC_SSC1 peripheral ========== 
+#define AT91C_SSC1_RNPR (AT91C_CAST(AT91C_REG *) 	0xFFFA0110) // (PDC_SSC1) Receive Next Pointer Register
+#define AT91C_SSC1_TCR  (AT91C_CAST(AT91C_REG *) 	0xFFFA010C) // (PDC_SSC1) Transmit Counter Register
+#define AT91C_SSC1_TNCR (AT91C_CAST(AT91C_REG *) 	0xFFFA011C) // (PDC_SSC1) Transmit Next Counter Register
+#define AT91C_SSC1_RCR  (AT91C_CAST(AT91C_REG *) 	0xFFFA0104) // (PDC_SSC1) Receive Counter Register
+#define AT91C_SSC1_RNCR (AT91C_CAST(AT91C_REG *) 	0xFFFA0114) // (PDC_SSC1) Receive Next Counter Register
+#define AT91C_SSC1_PTCR (AT91C_CAST(AT91C_REG *) 	0xFFFA0120) // (PDC_SSC1) PDC Transfer Control Register
+#define AT91C_SSC1_TPR  (AT91C_CAST(AT91C_REG *) 	0xFFFA0108) // (PDC_SSC1) Transmit Pointer Register
+#define AT91C_SSC1_RPR  (AT91C_CAST(AT91C_REG *) 	0xFFFA0100) // (PDC_SSC1) Receive Pointer Register
+#define AT91C_SSC1_PTSR (AT91C_CAST(AT91C_REG *) 	0xFFFA0124) // (PDC_SSC1) PDC Transfer Status Register
+#define AT91C_SSC1_TNPR (AT91C_CAST(AT91C_REG *) 	0xFFFA0118) // (PDC_SSC1) Transmit Next Pointer Register
+// ========== Register definition for SSC1 peripheral ========== 
+#define AT91C_SSC1_SR   (AT91C_CAST(AT91C_REG *) 	0xFFFA0040) // (SSC1) Status Register
+#define AT91C_SSC1_TFMR (AT91C_CAST(AT91C_REG *) 	0xFFFA001C) // (SSC1) Transmit Frame Mode Register
+#define AT91C_SSC1_IPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFFA00F0) // (SSC1) SSC IPNAME1 REGISTER 
+#define AT91C_SSC1_CMR  (AT91C_CAST(AT91C_REG *) 	0xFFFA0004) // (SSC1) Clock Mode Register
+#define AT91C_SSC1_THR  (AT91C_CAST(AT91C_REG *) 	0xFFFA0024) // (SSC1) Transmit Holding Register
+#define AT91C_SSC1_FEATURES (AT91C_CAST(AT91C_REG *) 	0xFFFA00F8) // (SSC1) SSC FEATURES REGISTER 
+#define AT91C_SSC1_TSHR (AT91C_CAST(AT91C_REG *) 	0xFFFA0034) // (SSC1) Transmit Sync Holding Register
+#define AT91C_SSC1_RCMR (AT91C_CAST(AT91C_REG *) 	0xFFFA0010) // (SSC1) Receive Clock ModeRegister
+#define AT91C_SSC1_RHR  (AT91C_CAST(AT91C_REG *) 	0xFFFA0020) // (SSC1) Receive Holding Register
+#define AT91C_SSC1_VER  (AT91C_CAST(AT91C_REG *) 	0xFFFA00FC) // (SSC1) Version Register
+#define AT91C_SSC1_TCMR (AT91C_CAST(AT91C_REG *) 	0xFFFA0018) // (SSC1) Transmit Clock Mode Register
+#define AT91C_SSC1_CR   (AT91C_CAST(AT91C_REG *) 	0xFFFA0000) // (SSC1) Control Register
+#define AT91C_SSC1_RSHR (AT91C_CAST(AT91C_REG *) 	0xFFFA0030) // (SSC1) Receive Sync Holding Register
+#define AT91C_SSC1_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFA0044) // (SSC1) Interrupt Enable Register
+#define AT91C_SSC1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFFA00EC) // (SSC1) SSC ADDRSIZE REGISTER 
+#define AT91C_SSC1_RFMR (AT91C_CAST(AT91C_REG *) 	0xFFFA0014) // (SSC1) Receive Frame Mode Register
+#define AT91C_SSC1_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFA004C) // (SSC1) Interrupt Mask Register
+#define AT91C_SSC1_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFA0048) // (SSC1) Interrupt Disable Register
+#define AT91C_SSC1_IPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFFA00F4) // (SSC1) SSC IPNAME2 REGISTER 
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_CCNTR (AT91C_CAST(AT91C_REG *) 	0xFFFB820C) // (PWMC_CH0) Channel Counter Register
+#define AT91C_PWMC_CH0_CPRDR (AT91C_CAST(AT91C_REG *) 	0xFFFB8208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CUPDR (AT91C_CAST(AT91C_REG *) 	0xFFFB8210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CDTYR (AT91C_CAST(AT91C_REG *) 	0xFFFB8204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR (AT91C_CAST(AT91C_REG *) 	0xFFFB8200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_Reserved (AT91C_CAST(AT91C_REG *) 	0xFFFB8214) // (PWMC_CH0) Reserved
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_CCNTR (AT91C_CAST(AT91C_REG *) 	0xFFFB822C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR (AT91C_CAST(AT91C_REG *) 	0xFFFB8224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR (AT91C_CAST(AT91C_REG *) 	0xFFFB8220) // (PWMC_CH1) Channel Mode Register
+#define AT91C_PWMC_CH1_CPRDR (AT91C_CAST(AT91C_REG *) 	0xFFFB8228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_Reserved (AT91C_CAST(AT91C_REG *) 	0xFFFB8234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR (AT91C_CAST(AT91C_REG *) 	0xFFFB8230) // (PWMC_CH1) Channel Update Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_CUPDR (AT91C_CAST(AT91C_REG *) 	0xFFFB8250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CMR (AT91C_CAST(AT91C_REG *) 	0xFFFB8240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_Reserved (AT91C_CAST(AT91C_REG *) 	0xFFFB8254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CPRDR (AT91C_CAST(AT91C_REG *) 	0xFFFB8248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CDTYR (AT91C_CAST(AT91C_REG *) 	0xFFFB8244) // (PWMC_CH2) Channel Duty Cycle Register
+#define AT91C_PWMC_CH2_CCNTR (AT91C_CAST(AT91C_REG *) 	0xFFFB824C) // (PWMC_CH2) Channel Counter Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CPRDR (AT91C_CAST(AT91C_REG *) 	0xFFFB8268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_Reserved (AT91C_CAST(AT91C_REG *) 	0xFFFB8274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CUPDR (AT91C_CAST(AT91C_REG *) 	0xFFFB8270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_CDTYR (AT91C_CAST(AT91C_REG *) 	0xFFFB8264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR (AT91C_CAST(AT91C_REG *) 	0xFFFB826C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR (AT91C_CAST(AT91C_REG *) 	0xFFFB8260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFB8014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_MR   (AT91C_CAST(AT91C_REG *) 	0xFFFB8000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_VR   (AT91C_CAST(AT91C_REG *) 	0xFFFB80FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFB8018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_SR   (AT91C_CAST(AT91C_REG *) 	0xFFFB800C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_ISR  (AT91C_CAST(AT91C_REG *) 	0xFFFB801C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_ENA  (AT91C_CAST(AT91C_REG *) 	0xFFFB8004) // (PWMC) PWMC Enable Register
+#define AT91C_PWMC_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFB8010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_DIS  (AT91C_CAST(AT91C_REG *) 	0xFFFB8008) // (PWMC) PWMC Disable Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_TPR  (AT91C_CAST(AT91C_REG *) 	0xFFFA4108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_PTCR (AT91C_CAST(AT91C_REG *) 	0xFFFA4120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_RNPR (AT91C_CAST(AT91C_REG *) 	0xFFFA4110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_TNCR (AT91C_CAST(AT91C_REG *) 	0xFFFA411C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_TCR  (AT91C_CAST(AT91C_REG *) 	0xFFFA410C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  (AT91C_CAST(AT91C_REG *) 	0xFFFA4104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_RNCR (AT91C_CAST(AT91C_REG *) 	0xFFFA4114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR (AT91C_CAST(AT91C_REG *) 	0xFFFA4118) // (PDC_SPI0) Transmit Next Pointer Register
+#define AT91C_SPI0_RPR  (AT91C_CAST(AT91C_REG *) 	0xFFFA4100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_PTSR (AT91C_CAST(AT91C_REG *) 	0xFFFA4124) // (PDC_SPI0) PDC Transfer Status Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_RNCR (AT91C_CAST(AT91C_REG *) 	0xFFFA8114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_TCR  (AT91C_CAST(AT91C_REG *) 	0xFFFA810C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  (AT91C_CAST(AT91C_REG *) 	0xFFFA8104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_TNPR (AT91C_CAST(AT91C_REG *) 	0xFFFA8118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_RNPR (AT91C_CAST(AT91C_REG *) 	0xFFFA8110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RPR  (AT91C_CAST(AT91C_REG *) 	0xFFFA8100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR (AT91C_CAST(AT91C_REG *) 	0xFFFA811C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  (AT91C_CAST(AT91C_REG *) 	0xFFFA8108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_PTSR (AT91C_CAST(AT91C_REG *) 	0xFFFA8124) // (PDC_SPI1) PDC Transfer Status Register
+#define AT91C_SPI1_PTCR (AT91C_CAST(AT91C_REG *) 	0xFFFA8120) // (PDC_SPI1) PDC Transfer Control Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_MR   (AT91C_CAST(AT91C_REG *) 	0xFFFA4004) // (SPI0) Mode Register
+#define AT91C_SPI0_RDR  (AT91C_CAST(AT91C_REG *) 	0xFFFA4008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CR   (AT91C_CAST(AT91C_REG *) 	0xFFFA4000) // (SPI0) Control Register
+#define AT91C_SPI0_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFA4014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_TDR  (AT91C_CAST(AT91C_REG *) 	0xFFFA400C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFA4018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CSR  (AT91C_CAST(AT91C_REG *) 	0xFFFA4030) // (SPI0) Chip Select Register
+#define AT91C_SPI0_SR   (AT91C_CAST(AT91C_REG *) 	0xFFFA4010) // (SPI0) Status Register
+#define AT91C_SPI0_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFA401C) // (SPI0) Interrupt Mask Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_CSR  (AT91C_CAST(AT91C_REG *) 	0xFFFA8030) // (SPI1) Chip Select Register
+#define AT91C_SPI1_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFA8014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_RDR  (AT91C_CAST(AT91C_REG *) 	0xFFFA8008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFA8018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_MR   (AT91C_CAST(AT91C_REG *) 	0xFFFA8004) // (SPI1) Mode Register
+#define AT91C_SPI1_CR   (AT91C_CAST(AT91C_REG *) 	0xFFFA8000) // (SPI1) Control Register
+#define AT91C_SPI1_SR   (AT91C_CAST(AT91C_REG *) 	0xFFFA8010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  (AT91C_CAST(AT91C_REG *) 	0xFFFA800C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFA801C) // (SPI1) Interrupt Mask Register
+// ========== Register definition for PDC_TSADC peripheral ========== 
+#define AT91C_TSADC_TCR (AT91C_CAST(AT91C_REG *) 	0xFFFB010C) // (PDC_TSADC) Transmit Counter Register
+#define AT91C_TSADC_PTCR (AT91C_CAST(AT91C_REG *) 	0xFFFB0120) // (PDC_TSADC) PDC Transfer Control Register
+#define AT91C_TSADC_RNCR (AT91C_CAST(AT91C_REG *) 	0xFFFB0114) // (PDC_TSADC) Receive Next Counter Register
+#define AT91C_TSADC_PTSR (AT91C_CAST(AT91C_REG *) 	0xFFFB0124) // (PDC_TSADC) PDC Transfer Status Register
+#define AT91C_TSADC_TNCR (AT91C_CAST(AT91C_REG *) 	0xFFFB011C) // (PDC_TSADC) Transmit Next Counter Register
+#define AT91C_TSADC_RNPR (AT91C_CAST(AT91C_REG *) 	0xFFFB0110) // (PDC_TSADC) Receive Next Pointer Register
+#define AT91C_TSADC_RCR (AT91C_CAST(AT91C_REG *) 	0xFFFB0104) // (PDC_TSADC) Receive Counter Register
+#define AT91C_TSADC_TPR (AT91C_CAST(AT91C_REG *) 	0xFFFB0108) // (PDC_TSADC) Transmit Pointer Register
+#define AT91C_TSADC_TNPR (AT91C_CAST(AT91C_REG *) 	0xFFFB0118) // (PDC_TSADC) Transmit Next Pointer Register
+#define AT91C_TSADC_RPR (AT91C_CAST(AT91C_REG *) 	0xFFFB0100) // (PDC_TSADC) Receive Pointer Register
+// ========== Register definition for TSADC peripheral ========== 
+#define AT91C_TSADC_CHSR (AT91C_CAST(AT91C_REG *) 	0xFFFB0018) // (TSADC) Channel Status Register
+#define AT91C_TSADC_CDR5 (AT91C_CAST(AT91C_REG *) 	0xFFFB0044) // (TSADC) Channel Data Register 5
+#define AT91C_TSADC_CR  (AT91C_CAST(AT91C_REG *) 	0xFFFB0000) // (TSADC) Control Register
+#define AT91C_TSADC_IMR (AT91C_CAST(AT91C_REG *) 	0xFFFB002C) // (TSADC) Interrupt Mask Register
+#define AT91C_TSADC_CHDR (AT91C_CAST(AT91C_REG *) 	0xFFFB0014) // (TSADC) Channel Disable Register
+#define AT91C_TSADC_LCDR (AT91C_CAST(AT91C_REG *) 	0xFFFB0020) // (TSADC) Last Converted Register
+#define AT91C_TSADC_IER (AT91C_CAST(AT91C_REG *) 	0xFFFB0024) // (TSADC) Interrupt Enable Register
+#define AT91C_TSADC_TSR (AT91C_CAST(AT91C_REG *) 	0xFFFB000C) // (TSADC) Touch Screen Register
+#define AT91C_TSADC_CDR2 (AT91C_CAST(AT91C_REG *) 	0xFFFB0038) // (TSADC) Channel Data Register 2
+#define AT91C_TSADC_CDR4 (AT91C_CAST(AT91C_REG *) 	0xFFFB0040) // (TSADC) Channel Data Register 4
+#define AT91C_TSADC_CHER (AT91C_CAST(AT91C_REG *) 	0xFFFB0010) // (TSADC) Channel Enable Register
+#define AT91C_TSADC_TRGR (AT91C_CAST(AT91C_REG *) 	0xFFFB0008) // (TSADC) Trigger Register
+#define AT91C_TSADC_CDR3 (AT91C_CAST(AT91C_REG *) 	0xFFFB003C) // (TSADC) Channel Data Register 3
+#define AT91C_TSADC_SR  (AT91C_CAST(AT91C_REG *) 	0xFFFB001C) // (TSADC) Status Register
+#define AT91C_TSADC_CDR0 (AT91C_CAST(AT91C_REG *) 	0xFFFB0030) // (TSADC) Channel Data Register 0
+#define AT91C_TSADC_CDR6 (AT91C_CAST(AT91C_REG *) 	0xFFFB0048) // (TSADC) Channel Data Register 6
+#define AT91C_TSADC_IDR (AT91C_CAST(AT91C_REG *) 	0xFFFB0028) // (TSADC) Interrupt Disable Register
+#define AT91C_TSADC_MR  (AT91C_CAST(AT91C_REG *) 	0xFFFB0004) // (TSADC) Mode Register
+#define AT91C_TSADC_CDR7 (AT91C_CAST(AT91C_REG *) 	0xFFFB004C) // (TSADC) Channel Data Register 7
+#define AT91C_TSADC_CDR1 (AT91C_CAST(AT91C_REG *) 	0xFFFB0034) // (TSADC) Channel Data Register 1
+// ========== Register definition for UDPHS_EPTFIFO peripheral ========== 
+#define AT91C_UDPHS_EPTFIFO_READEPT3 (AT91C_CAST(AT91C_REG *) 	0x00630000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 3
+#define AT91C_UDPHS_EPTFIFO_READEPT5 (AT91C_CAST(AT91C_REG *) 	0x00650000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 5
+#define AT91C_UDPHS_EPTFIFO_READEPT1 (AT91C_CAST(AT91C_REG *) 	0x00610000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 1
+#define AT91C_UDPHS_EPTFIFO_READEPT0 (AT91C_CAST(AT91C_REG *) 	0x00600000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 0
+#define AT91C_UDPHS_EPTFIFO_READEPT6 (AT91C_CAST(AT91C_REG *) 	0x00660000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 6
+#define AT91C_UDPHS_EPTFIFO_READEPT2 (AT91C_CAST(AT91C_REG *) 	0x00620000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 2
+#define AT91C_UDPHS_EPTFIFO_READEPT4 (AT91C_CAST(AT91C_REG *) 	0x00640000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 4
+// ========== Register definition for UDPHS_EPT_0 peripheral ========== 
+#define AT91C_UDPHS_EPT_0_EPTSTA (AT91C_CAST(AT91C_REG *) 	0xFFF7811C) // (UDPHS_EPT_0) UDPHS Endpoint Status Register
+#define AT91C_UDPHS_EPT_0_EPTCTL (AT91C_CAST(AT91C_REG *) 	0xFFF7810C) // (UDPHS_EPT_0) UDPHS Endpoint Control Register
+#define AT91C_UDPHS_EPT_0_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 	0xFFF78108) // (UDPHS_EPT_0) UDPHS Endpoint Control Disable Register
+#define AT91C_UDPHS_EPT_0_EPTCFG (AT91C_CAST(AT91C_REG *) 	0xFFF78100) // (UDPHS_EPT_0) UDPHS Endpoint Config Register
+#define AT91C_UDPHS_EPT_0_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78118) // (UDPHS_EPT_0) UDPHS Endpoint Clear Status Register
+#define AT91C_UDPHS_EPT_0_EPTSETSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78114) // (UDPHS_EPT_0) UDPHS Endpoint Set Status Register
+#define AT91C_UDPHS_EPT_0_EPTCTLENB (AT91C_CAST(AT91C_REG *) 	0xFFF78104) // (UDPHS_EPT_0) UDPHS Endpoint Control Enable Register
+// ========== Register definition for UDPHS_EPT_1 peripheral ========== 
+#define AT91C_UDPHS_EPT_1_EPTCTLENB (AT91C_CAST(AT91C_REG *) 	0xFFF78124) // (UDPHS_EPT_1) UDPHS Endpoint Control Enable Register
+#define AT91C_UDPHS_EPT_1_EPTCFG (AT91C_CAST(AT91C_REG *) 	0xFFF78120) // (UDPHS_EPT_1) UDPHS Endpoint Config Register
+#define AT91C_UDPHS_EPT_1_EPTCTL (AT91C_CAST(AT91C_REG *) 	0xFFF7812C) // (UDPHS_EPT_1) UDPHS Endpoint Control Register
+#define AT91C_UDPHS_EPT_1_EPTSTA (AT91C_CAST(AT91C_REG *) 	0xFFF7813C) // (UDPHS_EPT_1) UDPHS Endpoint Status Register
+#define AT91C_UDPHS_EPT_1_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78138) // (UDPHS_EPT_1) UDPHS Endpoint Clear Status Register
+#define AT91C_UDPHS_EPT_1_EPTSETSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78134) // (UDPHS_EPT_1) UDPHS Endpoint Set Status Register
+#define AT91C_UDPHS_EPT_1_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 	0xFFF78128) // (UDPHS_EPT_1) UDPHS Endpoint Control Disable Register
+// ========== Register definition for UDPHS_EPT_2 peripheral ========== 
+#define AT91C_UDPHS_EPT_2_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78158) // (UDPHS_EPT_2) UDPHS Endpoint Clear Status Register
+#define AT91C_UDPHS_EPT_2_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 	0xFFF78148) // (UDPHS_EPT_2) UDPHS Endpoint Control Disable Register
+#define AT91C_UDPHS_EPT_2_EPTSTA (AT91C_CAST(AT91C_REG *) 	0xFFF7815C) // (UDPHS_EPT_2) UDPHS Endpoint Status Register
+#define AT91C_UDPHS_EPT_2_EPTSETSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78154) // (UDPHS_EPT_2) UDPHS Endpoint Set Status Register
+#define AT91C_UDPHS_EPT_2_EPTCTL (AT91C_CAST(AT91C_REG *) 	0xFFF7814C) // (UDPHS_EPT_2) UDPHS Endpoint Control Register
+#define AT91C_UDPHS_EPT_2_EPTCFG (AT91C_CAST(AT91C_REG *) 	0xFFF78140) // (UDPHS_EPT_2) UDPHS Endpoint Config Register
+#define AT91C_UDPHS_EPT_2_EPTCTLENB (AT91C_CAST(AT91C_REG *) 	0xFFF78144) // (UDPHS_EPT_2) UDPHS Endpoint Control Enable Register
+// ========== Register definition for UDPHS_EPT_3 peripheral ========== 
+#define AT91C_UDPHS_EPT_3_EPTCTL (AT91C_CAST(AT91C_REG *) 	0xFFF7816C) // (UDPHS_EPT_3) UDPHS Endpoint Control Register
+#define AT91C_UDPHS_EPT_3_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78178) // (UDPHS_EPT_3) UDPHS Endpoint Clear Status Register
+#define AT91C_UDPHS_EPT_3_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 	0xFFF78168) // (UDPHS_EPT_3) UDPHS Endpoint Control Disable Register
+#define AT91C_UDPHS_EPT_3_EPTSTA (AT91C_CAST(AT91C_REG *) 	0xFFF7817C) // (UDPHS_EPT_3) UDPHS Endpoint Status Register
+#define AT91C_UDPHS_EPT_3_EPTSETSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78174) // (UDPHS_EPT_3) UDPHS Endpoint Set Status Register
+#define AT91C_UDPHS_EPT_3_EPTCTLENB (AT91C_CAST(AT91C_REG *) 	0xFFF78164) // (UDPHS_EPT_3) UDPHS Endpoint Control Enable Register
+#define AT91C_UDPHS_EPT_3_EPTCFG (AT91C_CAST(AT91C_REG *) 	0xFFF78160) // (UDPHS_EPT_3) UDPHS Endpoint Config Register
+// ========== Register definition for UDPHS_EPT_4 peripheral ========== 
+#define AT91C_UDPHS_EPT_4_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78198) // (UDPHS_EPT_4) UDPHS Endpoint Clear Status Register
+#define AT91C_UDPHS_EPT_4_EPTCTL (AT91C_CAST(AT91C_REG *) 	0xFFF7818C) // (UDPHS_EPT_4) UDPHS Endpoint Control Register
+#define AT91C_UDPHS_EPT_4_EPTCTLENB (AT91C_CAST(AT91C_REG *) 	0xFFF78184) // (UDPHS_EPT_4) UDPHS Endpoint Control Enable Register
+#define AT91C_UDPHS_EPT_4_EPTSTA (AT91C_CAST(AT91C_REG *) 	0xFFF7819C) // (UDPHS_EPT_4) UDPHS Endpoint Status Register
+#define AT91C_UDPHS_EPT_4_EPTSETSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78194) // (UDPHS_EPT_4) UDPHS Endpoint Set Status Register
+#define AT91C_UDPHS_EPT_4_EPTCFG (AT91C_CAST(AT91C_REG *) 	0xFFF78180) // (UDPHS_EPT_4) UDPHS Endpoint Config Register
+#define AT91C_UDPHS_EPT_4_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 	0xFFF78188) // (UDPHS_EPT_4) UDPHS Endpoint Control Disable Register
+// ========== Register definition for UDPHS_EPT_5 peripheral ========== 
+#define AT91C_UDPHS_EPT_5_EPTSTA (AT91C_CAST(AT91C_REG *) 	0xFFF781BC) // (UDPHS_EPT_5) UDPHS Endpoint Status Register
+#define AT91C_UDPHS_EPT_5_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 	0xFFF781B8) // (UDPHS_EPT_5) UDPHS Endpoint Clear Status Register
+#define AT91C_UDPHS_EPT_5_EPTCTLENB (AT91C_CAST(AT91C_REG *) 	0xFFF781A4) // (UDPHS_EPT_5) UDPHS Endpoint Control Enable Register
+#define AT91C_UDPHS_EPT_5_EPTSETSTA (AT91C_CAST(AT91C_REG *) 	0xFFF781B4) // (UDPHS_EPT_5) UDPHS Endpoint Set Status Register
+#define AT91C_UDPHS_EPT_5_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 	0xFFF781A8) // (UDPHS_EPT_5) UDPHS Endpoint Control Disable Register
+#define AT91C_UDPHS_EPT_5_EPTCFG (AT91C_CAST(AT91C_REG *) 	0xFFF781A0) // (UDPHS_EPT_5) UDPHS Endpoint Config Register
+#define AT91C_UDPHS_EPT_5_EPTCTL (AT91C_CAST(AT91C_REG *) 	0xFFF781AC) // (UDPHS_EPT_5) UDPHS Endpoint Control Register
+// ========== Register definition for UDPHS_EPT_6 peripheral ========== 
+#define AT91C_UDPHS_EPT_6_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 	0xFFF781D8) // (UDPHS_EPT_6) UDPHS Endpoint Clear Status Register
+#define AT91C_UDPHS_EPT_6_EPTCTLENB (AT91C_CAST(AT91C_REG *) 	0xFFF781C4) // (UDPHS_EPT_6) UDPHS Endpoint Control Enable Register
+#define AT91C_UDPHS_EPT_6_EPTCTL (AT91C_CAST(AT91C_REG *) 	0xFFF781CC) // (UDPHS_EPT_6) UDPHS Endpoint Control Register
+#define AT91C_UDPHS_EPT_6_EPTSETSTA (AT91C_CAST(AT91C_REG *) 	0xFFF781D4) // (UDPHS_EPT_6) UDPHS Endpoint Set Status Register
+#define AT91C_UDPHS_EPT_6_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 	0xFFF781C8) // (UDPHS_EPT_6) UDPHS Endpoint Control Disable Register
+#define AT91C_UDPHS_EPT_6_EPTSTA (AT91C_CAST(AT91C_REG *) 	0xFFF781DC) // (UDPHS_EPT_6) UDPHS Endpoint Status Register
+#define AT91C_UDPHS_EPT_6_EPTCFG (AT91C_CAST(AT91C_REG *) 	0xFFF781C0) // (UDPHS_EPT_6) UDPHS Endpoint Config Register
+// ========== Register definition for UDPHS_DMA_1 peripheral ========== 
+#define AT91C_UDPHS_DMA_1_DMASTATUS (AT91C_CAST(AT91C_REG *) 	0xFFF7831C) // (UDPHS_DMA_1) UDPHS DMA Channel Status Register
+#define AT91C_UDPHS_DMA_1_DMANXTDSC (AT91C_CAST(AT91C_REG *) 	0xFFF78310) // (UDPHS_DMA_1) UDPHS DMA Channel Next Descriptor Address
+#define AT91C_UDPHS_DMA_1_DMACONTROL (AT91C_CAST(AT91C_REG *) 	0xFFF78318) // (UDPHS_DMA_1) UDPHS DMA Channel Control Register
+#define AT91C_UDPHS_DMA_1_DMAADDRESS (AT91C_CAST(AT91C_REG *) 	0xFFF78314) // (UDPHS_DMA_1) UDPHS DMA Channel Address Register
+// ========== Register definition for UDPHS_DMA_2 peripheral ========== 
+#define AT91C_UDPHS_DMA_2_DMACONTROL (AT91C_CAST(AT91C_REG *) 	0xFFF78328) // (UDPHS_DMA_2) UDPHS DMA Channel Control Register
+#define AT91C_UDPHS_DMA_2_DMASTATUS (AT91C_CAST(AT91C_REG *) 	0xFFF7832C) // (UDPHS_DMA_2) UDPHS DMA Channel Status Register
+#define AT91C_UDPHS_DMA_2_DMAADDRESS (AT91C_CAST(AT91C_REG *) 	0xFFF78324) // (UDPHS_DMA_2) UDPHS DMA Channel Address Register
+#define AT91C_UDPHS_DMA_2_DMANXTDSC (AT91C_CAST(AT91C_REG *) 	0xFFF78320) // (UDPHS_DMA_2) UDPHS DMA Channel Next Descriptor Address
+// ========== Register definition for UDPHS_DMA_3 peripheral ========== 
+#define AT91C_UDPHS_DMA_3_DMAADDRESS (AT91C_CAST(AT91C_REG *) 	0xFFF78334) // (UDPHS_DMA_3) UDPHS DMA Channel Address Register
+#define AT91C_UDPHS_DMA_3_DMANXTDSC (AT91C_CAST(AT91C_REG *) 	0xFFF78330) // (UDPHS_DMA_3) UDPHS DMA Channel Next Descriptor Address
+#define AT91C_UDPHS_DMA_3_DMACONTROL (AT91C_CAST(AT91C_REG *) 	0xFFF78338) // (UDPHS_DMA_3) UDPHS DMA Channel Control Register
+#define AT91C_UDPHS_DMA_3_DMASTATUS (AT91C_CAST(AT91C_REG *) 	0xFFF7833C) // (UDPHS_DMA_3) UDPHS DMA Channel Status Register
+// ========== Register definition for UDPHS_DMA_4 peripheral ========== 
+#define AT91C_UDPHS_DMA_4_DMANXTDSC (AT91C_CAST(AT91C_REG *) 	0xFFF78340) // (UDPHS_DMA_4) UDPHS DMA Channel Next Descriptor Address
+#define AT91C_UDPHS_DMA_4_DMAADDRESS (AT91C_CAST(AT91C_REG *) 	0xFFF78344) // (UDPHS_DMA_4) UDPHS DMA Channel Address Register
+#define AT91C_UDPHS_DMA_4_DMACONTROL (AT91C_CAST(AT91C_REG *) 	0xFFF78348) // (UDPHS_DMA_4) UDPHS DMA Channel Control Register
+#define AT91C_UDPHS_DMA_4_DMASTATUS (AT91C_CAST(AT91C_REG *) 	0xFFF7834C) // (UDPHS_DMA_4) UDPHS DMA Channel Status Register
+// ========== Register definition for UDPHS_DMA_5 peripheral ========== 
+#define AT91C_UDPHS_DMA_5_DMASTATUS (AT91C_CAST(AT91C_REG *) 	0xFFF7835C) // (UDPHS_DMA_5) UDPHS DMA Channel Status Register
+#define AT91C_UDPHS_DMA_5_DMACONTROL (AT91C_CAST(AT91C_REG *) 	0xFFF78358) // (UDPHS_DMA_5) UDPHS DMA Channel Control Register
+#define AT91C_UDPHS_DMA_5_DMANXTDSC (AT91C_CAST(AT91C_REG *) 	0xFFF78350) // (UDPHS_DMA_5) UDPHS DMA Channel Next Descriptor Address
+#define AT91C_UDPHS_DMA_5_DMAADDRESS (AT91C_CAST(AT91C_REG *) 	0xFFF78354) // (UDPHS_DMA_5) UDPHS DMA Channel Address Register
+// ========== Register definition for UDPHS_DMA_6 peripheral ========== 
+#define AT91C_UDPHS_DMA_6_DMANXTDSC (AT91C_CAST(AT91C_REG *) 	0xFFF78360) // (UDPHS_DMA_6) UDPHS DMA Channel Next Descriptor Address
+#define AT91C_UDPHS_DMA_6_DMACONTROL (AT91C_CAST(AT91C_REG *) 	0xFFF78368) // (UDPHS_DMA_6) UDPHS DMA Channel Control Register
+#define AT91C_UDPHS_DMA_6_DMASTATUS (AT91C_CAST(AT91C_REG *) 	0xFFF7836C) // (UDPHS_DMA_6) UDPHS DMA Channel Status Register
+#define AT91C_UDPHS_DMA_6_DMAADDRESS (AT91C_CAST(AT91C_REG *) 	0xFFF78364) // (UDPHS_DMA_6) UDPHS DMA Channel Address Register
+// ========== Register definition for UDPHS peripheral ========== 
+#define AT91C_UDPHS_IEN (AT91C_CAST(AT91C_REG *) 	0xFFF78010) // (UDPHS) UDPHS Interrupt Enable Register
+#define AT91C_UDPHS_TSTSOFCNT (AT91C_CAST(AT91C_REG *) 	0xFFF780D0) // (UDPHS) UDPHS Test SOF Counter Register
+#define AT91C_UDPHS_IPFEATURES (AT91C_CAST(AT91C_REG *) 	0xFFF780F8) // (UDPHS) UDPHS Features Register
+#define AT91C_UDPHS_TST (AT91C_CAST(AT91C_REG *) 	0xFFF780E0) // (UDPHS) UDPHS Test Register
+#define AT91C_UDPHS_FNUM (AT91C_CAST(AT91C_REG *) 	0xFFF78004) // (UDPHS) UDPHS Frame Number Register
+#define AT91C_UDPHS_TSTCNTB (AT91C_CAST(AT91C_REG *) 	0xFFF780D8) // (UDPHS) UDPHS Test B Counter Register
+#define AT91C_UDPHS_RIPPADDRSIZE (AT91C_CAST(AT91C_REG *) 	0xFFF780EC) // (UDPHS) UDPHS PADDRSIZE Register
+#define AT91C_UDPHS_INTSTA (AT91C_CAST(AT91C_REG *) 	0xFFF78014) // (UDPHS) UDPHS Interrupt Status Register
+#define AT91C_UDPHS_EPTRST (AT91C_CAST(AT91C_REG *) 	0xFFF7801C) // (UDPHS) UDPHS Endpoints Reset Register
+#define AT91C_UDPHS_TSTCNTA (AT91C_CAST(AT91C_REG *) 	0xFFF780D4) // (UDPHS) UDPHS Test A Counter Register
+#define AT91C_UDPHS_RIPNAME2 (AT91C_CAST(AT91C_REG *) 	0xFFF780F4) // (UDPHS) UDPHS Name2 Register
+#define AT91C_UDPHS_RIPNAME1 (AT91C_CAST(AT91C_REG *) 	0xFFF780F0) // (UDPHS) UDPHS Name1 Register
+#define AT91C_UDPHS_TSTMODREG (AT91C_CAST(AT91C_REG *) 	0xFFF780DC) // (UDPHS) UDPHS Test Mode Register
+#define AT91C_UDPHS_CLRINT (AT91C_CAST(AT91C_REG *) 	0xFFF78018) // (UDPHS) UDPHS Clear Interrupt Register
+#define AT91C_UDPHS_IPVERSION (AT91C_CAST(AT91C_REG *) 	0xFFF780FC) // (UDPHS) UDPHS Version Register
+#define AT91C_UDPHS_CTRL (AT91C_CAST(AT91C_REG *) 	0xFFF78000) // (UDPHS) UDPHS Control Register
+// ========== Register definition for PDC_AC97C peripheral ========== 
+#define AT91C_AC97C_PTSR (AT91C_CAST(AT91C_REG *) 	0xFFFAC124) // (PDC_AC97C) PDC Transfer Status Register
+#define AT91C_AC97C_RPR (AT91C_CAST(AT91C_REG *) 	0xFFFAC100) // (PDC_AC97C) Receive Pointer Register
+#define AT91C_AC97C_RNCR (AT91C_CAST(AT91C_REG *) 	0xFFFAC114) // (PDC_AC97C) Receive Next Counter Register
+#define AT91C_AC97C_RCR (AT91C_CAST(AT91C_REG *) 	0xFFFAC104) // (PDC_AC97C) Receive Counter Register
+#define AT91C_AC97C_PTCR (AT91C_CAST(AT91C_REG *) 	0xFFFAC120) // (PDC_AC97C) PDC Transfer Control Register
+#define AT91C_AC97C_TPR (AT91C_CAST(AT91C_REG *) 	0xFFFAC108) // (PDC_AC97C) Transmit Pointer Register
+#define AT91C_AC97C_RNPR (AT91C_CAST(AT91C_REG *) 	0xFFFAC110) // (PDC_AC97C) Receive Next Pointer Register
+#define AT91C_AC97C_TNPR (AT91C_CAST(AT91C_REG *) 	0xFFFAC118) // (PDC_AC97C) Transmit Next Pointer Register
+#define AT91C_AC97C_TCR (AT91C_CAST(AT91C_REG *) 	0xFFFAC10C) // (PDC_AC97C) Transmit Counter Register
+#define AT91C_AC97C_TNCR (AT91C_CAST(AT91C_REG *) 	0xFFFAC11C) // (PDC_AC97C) Transmit Next Counter Register
+// ========== Register definition for AC97C peripheral ========== 
+#define AT91C_AC97C_IER (AT91C_CAST(AT91C_REG *) 	0xFFFAC054) // (AC97C) Interrupt Enable Register
+#define AT91C_AC97C_COTHR (AT91C_CAST(AT91C_REG *) 	0xFFFAC044) // (AC97C) COdec Transmit Holding Register
+#define AT91C_AC97C_IDR (AT91C_CAST(AT91C_REG *) 	0xFFFAC058) // (AC97C) Interrupt Disable Register
+#define AT91C_AC97C_ICA (AT91C_CAST(AT91C_REG *) 	0xFFFAC010) // (AC97C) Input Channel AssignementRegister
+#define AT91C_AC97C_CATHR (AT91C_CAST(AT91C_REG *) 	0xFFFAC024) // (AC97C) Channel A Transmit Holding Register
+#define AT91C_AC97C_CBSR (AT91C_CAST(AT91C_REG *) 	0xFFFAC038) // (AC97C) Channel B Status Register
+#define AT91C_AC97C_CAMR (AT91C_CAST(AT91C_REG *) 	0xFFFAC02C) // (AC97C) Channel A Mode Register
+#define AT91C_AC97C_SR  (AT91C_CAST(AT91C_REG *) 	0xFFFAC050) // (AC97C) Status Register
+#define AT91C_AC97C_CBTHR (AT91C_CAST(AT91C_REG *) 	0xFFFAC034) // (AC97C) Channel B Transmit Holding Register (optional)
+#define AT91C_AC97C_CASR (AT91C_CAST(AT91C_REG *) 	0xFFFAC028) // (AC97C) Channel A Status Register
+#define AT91C_AC97C_COSR (AT91C_CAST(AT91C_REG *) 	0xFFFAC048) // (AC97C) CODEC Status Register
+#define AT91C_AC97C_MR  (AT91C_CAST(AT91C_REG *) 	0xFFFAC008) // (AC97C) Mode Register
+#define AT91C_AC97C_OCA (AT91C_CAST(AT91C_REG *) 	0xFFFAC014) // (AC97C) Output Channel Assignement Register
+#define AT91C_AC97C_CORHR (AT91C_CAST(AT91C_REG *) 	0xFFFAC040) // (AC97C) COdec Transmit Holding Register
+#define AT91C_AC97C_CBRHR (AT91C_CAST(AT91C_REG *) 	0xFFFAC030) // (AC97C) Channel B Receive Holding Register (optional)
+#define AT91C_AC97C_IMR (AT91C_CAST(AT91C_REG *) 	0xFFFAC05C) // (AC97C) Interrupt Mask Register
+#define AT91C_AC97C_COMR (AT91C_CAST(AT91C_REG *) 	0xFFFAC04C) // (AC97C) CODEC Mask Status Register
+#define AT91C_AC97C_CARHR (AT91C_CAST(AT91C_REG *) 	0xFFFAC020) // (AC97C) Channel A Receive Holding Register
+#define AT91C_AC97C_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFAC0FC) // (AC97C) Version Register
+#define AT91C_AC97C_CBMR (AT91C_CAST(AT91C_REG *) 	0xFFFAC03C) // (AC97C) Channel B Mode Register
+// ========== Register definition for LCDC peripheral ========== 
+#define AT91C_LCDC_MVAL (AT91C_CAST(AT91C_REG *) 	0x00500818) // (LCDC) LCD Mode Toggle Rate Value Register
+#define AT91C_LCDC_PWRCON (AT91C_CAST(AT91C_REG *) 	0x0050083C) // (LCDC) Power Control Register
+#define AT91C_LCDC_ISR  (AT91C_CAST(AT91C_REG *) 	0x00500854) // (LCDC) Interrupt Enable Register
+#define AT91C_LCDC_FRMP1 (AT91C_CAST(AT91C_REG *) 	0x00500008) // (LCDC) DMA Frame Pointer Register 1
+#define AT91C_LCDC_CTRSTVAL (AT91C_CAST(AT91C_REG *) 	0x00500844) // (LCDC) Contrast Value Register
+#define AT91C_LCDC_ICR  (AT91C_CAST(AT91C_REG *) 	0x00500858) // (LCDC) Interrupt Clear Register
+#define AT91C_LCDC_TIM1 (AT91C_CAST(AT91C_REG *) 	0x00500808) // (LCDC) LCD Timing Config 1 Register
+#define AT91C_LCDC_DMACON (AT91C_CAST(AT91C_REG *) 	0x0050001C) // (LCDC) DMA Control Register
+#define AT91C_LCDC_ITR  (AT91C_CAST(AT91C_REG *) 	0x00500860) // (LCDC) Interrupts Test Register
+#define AT91C_LCDC_IDR  (AT91C_CAST(AT91C_REG *) 	0x0050084C) // (LCDC) Interrupt Disable Register
+#define AT91C_LCDC_DP4_7 (AT91C_CAST(AT91C_REG *) 	0x00500820) // (LCDC) Dithering Pattern DP4_7 Register
+#define AT91C_LCDC_DP5_7 (AT91C_CAST(AT91C_REG *) 	0x0050082C) // (LCDC) Dithering Pattern DP5_7 Register
+#define AT91C_LCDC_IRR  (AT91C_CAST(AT91C_REG *) 	0x00500864) // (LCDC) Interrupts Raw Status Register
+#define AT91C_LCDC_DP3_4 (AT91C_CAST(AT91C_REG *) 	0x00500830) // (LCDC) Dithering Pattern DP3_4 Register
+#define AT91C_LCDC_IMR  (AT91C_CAST(AT91C_REG *) 	0x00500850) // (LCDC) Interrupt Mask Register
+#define AT91C_LCDC_LCDFRCFG (AT91C_CAST(AT91C_REG *) 	0x00500810) // (LCDC) LCD Frame Config Register
+#define AT91C_LCDC_CTRSTCON (AT91C_CAST(AT91C_REG *) 	0x00500840) // (LCDC) Contrast Control Register
+#define AT91C_LCDC_DP1_2 (AT91C_CAST(AT91C_REG *) 	0x0050081C) // (LCDC) Dithering Pattern DP1_2 Register
+#define AT91C_LCDC_FRMP2 (AT91C_CAST(AT91C_REG *) 	0x0050000C) // (LCDC) DMA Frame Pointer Register 2
+#define AT91C_LCDC_LCDCON1 (AT91C_CAST(AT91C_REG *) 	0x00500800) // (LCDC) LCD Control 1 Register
+#define AT91C_LCDC_DP4_5 (AT91C_CAST(AT91C_REG *) 	0x00500834) // (LCDC) Dithering Pattern DP4_5 Register
+#define AT91C_LCDC_FRMA2 (AT91C_CAST(AT91C_REG *) 	0x00500014) // (LCDC) DMA Frame Address Register 2
+#define AT91C_LCDC_BA1  (AT91C_CAST(AT91C_REG *) 	0x00500000) // (LCDC) DMA Base Address Register 1
+#define AT91C_LCDC_DMA2DCFG (AT91C_CAST(AT91C_REG *) 	0x00500020) // (LCDC) DMA 2D addressing configuration
+#define AT91C_LCDC_LUT_ENTRY (AT91C_CAST(AT91C_REG *) 	0x00500C00) // (LCDC) LUT Entries Register
+#define AT91C_LCDC_DP6_7 (AT91C_CAST(AT91C_REG *) 	0x00500838) // (LCDC) Dithering Pattern DP6_7 Register
+#define AT91C_LCDC_FRMCFG (AT91C_CAST(AT91C_REG *) 	0x00500018) // (LCDC) DMA Frame Configuration Register
+#define AT91C_LCDC_TIM2 (AT91C_CAST(AT91C_REG *) 	0x0050080C) // (LCDC) LCD Timing Config 2 Register
+#define AT91C_LCDC_DP3_5 (AT91C_CAST(AT91C_REG *) 	0x00500824) // (LCDC) Dithering Pattern DP3_5 Register
+#define AT91C_LCDC_FRMA1 (AT91C_CAST(AT91C_REG *) 	0x00500010) // (LCDC) DMA Frame Address Register 1
+#define AT91C_LCDC_IER  (AT91C_CAST(AT91C_REG *) 	0x00500848) // (LCDC) Interrupt Enable Register
+#define AT91C_LCDC_DP2_3 (AT91C_CAST(AT91C_REG *) 	0x00500828) // (LCDC) Dithering Pattern DP2_3 Register
+#define AT91C_LCDC_FIFO (AT91C_CAST(AT91C_REG *) 	0x00500814) // (LCDC) LCD FIFO Register
+#define AT91C_LCDC_BA2  (AT91C_CAST(AT91C_REG *) 	0x00500004) // (LCDC) DMA Base Address Register 2
+#define AT91C_LCDC_LCDCON2 (AT91C_CAST(AT91C_REG *) 	0x00500804) // (LCDC) LCD Control 2 Register
+#define AT91C_LCDC_GPR  (AT91C_CAST(AT91C_REG *) 	0x0050085C) // (LCDC) General Purpose Register
+// ========== Register definition for LCDC_16B_TFT peripheral ========== 
+#define AT91C_TFT_MVAL  (AT91C_CAST(AT91C_REG *) 	0x00500818) // (LCDC_16B_TFT) LCD Mode Toggle Rate Value Register
+#define AT91C_TFT_PWRCON (AT91C_CAST(AT91C_REG *) 	0x0050083C) // (LCDC_16B_TFT) Power Control Register
+#define AT91C_TFT_ISR   (AT91C_CAST(AT91C_REG *) 	0x00500854) // (LCDC_16B_TFT) Interrupt Enable Register
+#define AT91C_TFT_FRMP1 (AT91C_CAST(AT91C_REG *) 	0x00500008) // (LCDC_16B_TFT) DMA Frame Pointer Register 1
+#define AT91C_TFT_CTRSTVAL (AT91C_CAST(AT91C_REG *) 	0x00500844) // (LCDC_16B_TFT) Contrast Value Register
+#define AT91C_TFT_ICR   (AT91C_CAST(AT91C_REG *) 	0x00500858) // (LCDC_16B_TFT) Interrupt Clear Register
+#define AT91C_TFT_TIM1  (AT91C_CAST(AT91C_REG *) 	0x00500808) // (LCDC_16B_TFT) LCD Timing Config 1 Register
+#define AT91C_TFT_DMACON (AT91C_CAST(AT91C_REG *) 	0x0050001C) // (LCDC_16B_TFT) DMA Control Register
+#define AT91C_TFT_ITR   (AT91C_CAST(AT91C_REG *) 	0x00500860) // (LCDC_16B_TFT) Interrupts Test Register
+#define AT91C_TFT_IDR   (AT91C_CAST(AT91C_REG *) 	0x0050084C) // (LCDC_16B_TFT) Interrupt Disable Register
+#define AT91C_TFT_DP4_7 (AT91C_CAST(AT91C_REG *) 	0x00500820) // (LCDC_16B_TFT) Dithering Pattern DP4_7 Register
+#define AT91C_TFT_DP5_7 (AT91C_CAST(AT91C_REG *) 	0x0050082C) // (LCDC_16B_TFT) Dithering Pattern DP5_7 Register
+#define AT91C_TFT_IRR   (AT91C_CAST(AT91C_REG *) 	0x00500864) // (LCDC_16B_TFT) Interrupts Raw Status Register
+#define AT91C_TFT_DP3_4 (AT91C_CAST(AT91C_REG *) 	0x00500830) // (LCDC_16B_TFT) Dithering Pattern DP3_4 Register
+#define AT91C_TFT_IMR   (AT91C_CAST(AT91C_REG *) 	0x00500850) // (LCDC_16B_TFT) Interrupt Mask Register
+#define AT91C_TFT_LCDFRCFG (AT91C_CAST(AT91C_REG *) 	0x00500810) // (LCDC_16B_TFT) LCD Frame Config Register
+#define AT91C_TFT_CTRSTCON (AT91C_CAST(AT91C_REG *) 	0x00500840) // (LCDC_16B_TFT) Contrast Control Register
+#define AT91C_TFT_DP1_2 (AT91C_CAST(AT91C_REG *) 	0x0050081C) // (LCDC_16B_TFT) Dithering Pattern DP1_2 Register
+#define AT91C_TFT_FRMP2 (AT91C_CAST(AT91C_REG *) 	0x0050000C) // (LCDC_16B_TFT) DMA Frame Pointer Register 2
+#define AT91C_TFT_LCDCON1 (AT91C_CAST(AT91C_REG *) 	0x00500800) // (LCDC_16B_TFT) LCD Control 1 Register
+#define AT91C_TFT_DP4_5 (AT91C_CAST(AT91C_REG *) 	0x00500834) // (LCDC_16B_TFT) Dithering Pattern DP4_5 Register
+#define AT91C_TFT_FRMA2 (AT91C_CAST(AT91C_REG *) 	0x00500014) // (LCDC_16B_TFT) DMA Frame Address Register 2
+#define AT91C_TFT_BA1   (AT91C_CAST(AT91C_REG *) 	0x00500000) // (LCDC_16B_TFT) DMA Base Address Register 1
+#define AT91C_TFT_DMA2DCFG (AT91C_CAST(AT91C_REG *) 	0x00500020) // (LCDC_16B_TFT) DMA 2D addressing configuration
+#define AT91C_TFT_LUT_ENTRY (AT91C_CAST(AT91C_REG *) 	0x00500C00) // (LCDC_16B_TFT) LUT Entries Register
+#define AT91C_TFT_DP6_7 (AT91C_CAST(AT91C_REG *) 	0x00500838) // (LCDC_16B_TFT) Dithering Pattern DP6_7 Register
+#define AT91C_TFT_FRMCFG (AT91C_CAST(AT91C_REG *) 	0x00500018) // (LCDC_16B_TFT) DMA Frame Configuration Register
+#define AT91C_TFT_TIM2  (AT91C_CAST(AT91C_REG *) 	0x0050080C) // (LCDC_16B_TFT) LCD Timing Config 2 Register
+#define AT91C_TFT_DP3_5 (AT91C_CAST(AT91C_REG *) 	0x00500824) // (LCDC_16B_TFT) Dithering Pattern DP3_5 Register
+#define AT91C_TFT_FRMA1 (AT91C_CAST(AT91C_REG *) 	0x00500010) // (LCDC_16B_TFT) DMA Frame Address Register 1
+#define AT91C_TFT_IER   (AT91C_CAST(AT91C_REG *) 	0x00500848) // (LCDC_16B_TFT) Interrupt Enable Register
+#define AT91C_TFT_DP2_3 (AT91C_CAST(AT91C_REG *) 	0x00500828) // (LCDC_16B_TFT) Dithering Pattern DP2_3 Register
+#define AT91C_TFT_FIFO  (AT91C_CAST(AT91C_REG *) 	0x00500814) // (LCDC_16B_TFT) LCD FIFO Register
+#define AT91C_TFT_BA2   (AT91C_CAST(AT91C_REG *) 	0x00500004) // (LCDC_16B_TFT) DMA Base Address Register 2
+#define AT91C_TFT_LCDCON2 (AT91C_CAST(AT91C_REG *) 	0x00500804) // (LCDC_16B_TFT) LCD Control 2 Register
+#define AT91C_TFT_GPR   (AT91C_CAST(AT91C_REG *) 	0x0050085C) // (LCDC_16B_TFT) General Purpose Register
+// ========== Register definition for HDMA_CH_0 peripheral ========== 
+#define AT91C_HDMA_CH_0_BDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC5C) // (HDMA_CH_0) HDMA Reserved
+#define AT91C_HDMA_CH_0_DADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC40) // (HDMA_CH_0) HDMA Channel Destination Address Register
+#define AT91C_HDMA_CH_0_DPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFEC58) // (HDMA_CH_0) HDMA Channel Destination Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_0_DSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC44) // (HDMA_CH_0) HDMA Channel Descriptor Address Register
+#define AT91C_HDMA_CH_0_CFG (AT91C_CAST(AT91C_REG *) 	0xFFFFEC50) // (HDMA_CH_0) HDMA Channel Configuration Register
+#define AT91C_HDMA_CH_0_SPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFEC54) // (HDMA_CH_0) HDMA Channel Source Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_0_CADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC60) // (HDMA_CH_0) HDMA Reserved
+#define AT91C_HDMA_CH_0_CTRLA (AT91C_CAST(AT91C_REG *) 	0xFFFFEC48) // (HDMA_CH_0) HDMA Channel Control A Register
+#define AT91C_HDMA_CH_0_CTRLB (AT91C_CAST(AT91C_REG *) 	0xFFFFEC4C) // (HDMA_CH_0) HDMA Channel Control B Register
+#define AT91C_HDMA_CH_0_SADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC3C) // (HDMA_CH_0) HDMA Channel Source Address Register
+// ========== Register definition for HDMA_CH_1 peripheral ========== 
+#define AT91C_HDMA_CH_1_CADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC88) // (HDMA_CH_1) HDMA Reserved
+#define AT91C_HDMA_CH_1_DPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFEC80) // (HDMA_CH_1) HDMA Channel Destination Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_1_CTRLB (AT91C_CAST(AT91C_REG *) 	0xFFFFEC74) // (HDMA_CH_1) HDMA Channel Control B Register
+#define AT91C_HDMA_CH_1_SADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC64) // (HDMA_CH_1) HDMA Channel Source Address Register
+#define AT91C_HDMA_CH_1_BDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC84) // (HDMA_CH_1) HDMA Reserved
+#define AT91C_HDMA_CH_1_CFG (AT91C_CAST(AT91C_REG *) 	0xFFFFEC78) // (HDMA_CH_1) HDMA Channel Configuration Register
+#define AT91C_HDMA_CH_1_DSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC6C) // (HDMA_CH_1) HDMA Channel Descriptor Address Register
+#define AT91C_HDMA_CH_1_DADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC68) // (HDMA_CH_1) HDMA Channel Destination Address Register
+#define AT91C_HDMA_CH_1_CTRLA (AT91C_CAST(AT91C_REG *) 	0xFFFFEC70) // (HDMA_CH_1) HDMA Channel Control A Register
+#define AT91C_HDMA_CH_1_SPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFEC7C) // (HDMA_CH_1) HDMA Channel Source Picture in Picture Configuration Register
+// ========== Register definition for HDMA_CH_2 peripheral ========== 
+#define AT91C_HDMA_CH_2_SADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC8C) // (HDMA_CH_2) HDMA Channel Source Address Register
+#define AT91C_HDMA_CH_2_BDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFECAC) // (HDMA_CH_2) HDMA Reserved
+#define AT91C_HDMA_CH_2_DPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFECA8) // (HDMA_CH_2) HDMA Channel Destination Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_2_SPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFECA4) // (HDMA_CH_2) HDMA Channel Source Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_2_DADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC90) // (HDMA_CH_2) HDMA Channel Destination Address Register
+#define AT91C_HDMA_CH_2_DSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC94) // (HDMA_CH_2) HDMA Channel Descriptor Address Register
+#define AT91C_HDMA_CH_2_CTRLA (AT91C_CAST(AT91C_REG *) 	0xFFFFEC98) // (HDMA_CH_2) HDMA Channel Control A Register
+#define AT91C_HDMA_CH_2_CADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFECB0) // (HDMA_CH_2) HDMA Reserved
+#define AT91C_HDMA_CH_2_CFG (AT91C_CAST(AT91C_REG *) 	0xFFFFECA0) // (HDMA_CH_2) HDMA Channel Configuration Register
+#define AT91C_HDMA_CH_2_CTRLB (AT91C_CAST(AT91C_REG *) 	0xFFFFEC9C) // (HDMA_CH_2) HDMA Channel Control B Register
+// ========== Register definition for HDMA_CH_3 peripheral ========== 
+#define AT91C_HDMA_CH_3_SPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFECCC) // (HDMA_CH_3) HDMA Channel Source Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_3_CTRLA (AT91C_CAST(AT91C_REG *) 	0xFFFFECC0) // (HDMA_CH_3) HDMA Channel Control A Register
+#define AT91C_HDMA_CH_3_DPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFECD0) // (HDMA_CH_3) HDMA Channel Destination Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_3_CTRLB (AT91C_CAST(AT91C_REG *) 	0xFFFFECC4) // (HDMA_CH_3) HDMA Channel Control B Register
+#define AT91C_HDMA_CH_3_BDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFECD4) // (HDMA_CH_3) HDMA Reserved
+#define AT91C_HDMA_CH_3_DSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFECBC) // (HDMA_CH_3) HDMA Channel Descriptor Address Register
+#define AT91C_HDMA_CH_3_CADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFECD8) // (HDMA_CH_3) HDMA Reserved
+#define AT91C_HDMA_CH_3_CFG (AT91C_CAST(AT91C_REG *) 	0xFFFFECC8) // (HDMA_CH_3) HDMA Channel Configuration Register
+#define AT91C_HDMA_CH_3_DADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFECB8) // (HDMA_CH_3) HDMA Channel Destination Address Register
+#define AT91C_HDMA_CH_3_SADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFECB4) // (HDMA_CH_3) HDMA Channel Source Address Register
+// ========== Register definition for HDMA_CH_4 peripheral ========== 
+#define AT91C_HDMA_CH_4_CFG (AT91C_CAST(AT91C_REG *) 	0xFFFFECF0) // (HDMA_CH_4) HDMA Channel Configuration Register
+#define AT91C_HDMA_CH_4_BDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFECFC) // (HDMA_CH_4) HDMA Reserved
+#define AT91C_HDMA_CH_4_CADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED00) // (HDMA_CH_4) HDMA Reserved
+#define AT91C_HDMA_CH_4_DADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFECE0) // (HDMA_CH_4) HDMA Channel Destination Address Register
+#define AT91C_HDMA_CH_4_CTRLA (AT91C_CAST(AT91C_REG *) 	0xFFFFECE8) // (HDMA_CH_4) HDMA Channel Control A Register
+#define AT91C_HDMA_CH_4_SADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFECDC) // (HDMA_CH_4) HDMA Channel Source Address Register
+#define AT91C_HDMA_CH_4_CTRLB (AT91C_CAST(AT91C_REG *) 	0xFFFFECEC) // (HDMA_CH_4) HDMA Channel Control B Register
+#define AT91C_HDMA_CH_4_DSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFECE4) // (HDMA_CH_4) HDMA Channel Descriptor Address Register
+#define AT91C_HDMA_CH_4_SPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFECF4) // (HDMA_CH_4) HDMA Channel Source Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_4_DPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFECF8) // (HDMA_CH_4) HDMA Channel Destination Picture in Picture Configuration Register
+// ========== Register definition for HDMA_CH_5 peripheral ========== 
+#define AT91C_HDMA_CH_5_CTRLB (AT91C_CAST(AT91C_REG *) 	0xFFFFED14) // (HDMA_CH_5) HDMA Channel Control B Register
+#define AT91C_HDMA_CH_5_DADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED08) // (HDMA_CH_5) HDMA Channel Destination Address Register
+#define AT91C_HDMA_CH_5_SPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFED1C) // (HDMA_CH_5) HDMA Channel Source Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_5_DSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFED0C) // (HDMA_CH_5) HDMA Channel Descriptor Address Register
+#define AT91C_HDMA_CH_5_DPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFED20) // (HDMA_CH_5) HDMA Channel Destination Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_5_CFG (AT91C_CAST(AT91C_REG *) 	0xFFFFED18) // (HDMA_CH_5) HDMA Channel Configuration Register
+#define AT91C_HDMA_CH_5_CADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED28) // (HDMA_CH_5) HDMA Reserved
+#define AT91C_HDMA_CH_5_SADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED04) // (HDMA_CH_5) HDMA Channel Source Address Register
+#define AT91C_HDMA_CH_5_BDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFED24) // (HDMA_CH_5) HDMA Reserved
+#define AT91C_HDMA_CH_5_CTRLA (AT91C_CAST(AT91C_REG *) 	0xFFFFED10) // (HDMA_CH_5) HDMA Channel Control A Register
+// ========== Register definition for HDMA_CH_6 peripheral ========== 
+#define AT91C_HDMA_CH_6_SADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED2C) // (HDMA_CH_6) HDMA Channel Source Address Register
+#define AT91C_HDMA_CH_6_BDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFED4C) // (HDMA_CH_6) HDMA Reserved
+#define AT91C_HDMA_CH_6_CADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED50) // (HDMA_CH_6) HDMA Reserved
+#define AT91C_HDMA_CH_6_SPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFED44) // (HDMA_CH_6) HDMA Channel Source Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_6_CTRLB (AT91C_CAST(AT91C_REG *) 	0xFFFFED3C) // (HDMA_CH_6) HDMA Channel Control B Register
+#define AT91C_HDMA_CH_6_DSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFED34) // (HDMA_CH_6) HDMA Channel Descriptor Address Register
+#define AT91C_HDMA_CH_6_CFG (AT91C_CAST(AT91C_REG *) 	0xFFFFED40) // (HDMA_CH_6) HDMA Channel Configuration Register
+#define AT91C_HDMA_CH_6_DPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFED48) // (HDMA_CH_6) HDMA Channel Destination Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_6_DADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED30) // (HDMA_CH_6) HDMA Channel Destination Address Register
+#define AT91C_HDMA_CH_6_CTRLA (AT91C_CAST(AT91C_REG *) 	0xFFFFED38) // (HDMA_CH_6) HDMA Channel Control A Register
+// ========== Register definition for HDMA_CH_7 peripheral ========== 
+#define AT91C_HDMA_CH_7_CADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED78) // (HDMA_CH_7) HDMA Reserved
+#define AT91C_HDMA_CH_7_CFG (AT91C_CAST(AT91C_REG *) 	0xFFFFED68) // (HDMA_CH_7) HDMA Channel Configuration Register
+#define AT91C_HDMA_CH_7_DADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED58) // (HDMA_CH_7) HDMA Channel Destination Address Register
+#define AT91C_HDMA_CH_7_CTRLB (AT91C_CAST(AT91C_REG *) 	0xFFFFED64) // (HDMA_CH_7) HDMA Channel Control B Register
+#define AT91C_HDMA_CH_7_DSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFED5C) // (HDMA_CH_7) HDMA Channel Descriptor Address Register
+#define AT91C_HDMA_CH_7_DPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFED70) // (HDMA_CH_7) HDMA Channel Destination Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_7_CTRLA (AT91C_CAST(AT91C_REG *) 	0xFFFFED60) // (HDMA_CH_7) HDMA Channel Control A Register
+#define AT91C_HDMA_CH_7_BDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFFED74) // (HDMA_CH_7) HDMA Reserved
+#define AT91C_HDMA_CH_7_SPIP (AT91C_CAST(AT91C_REG *) 	0xFFFFED6C) // (HDMA_CH_7) HDMA Channel Source Picture in Picture Configuration Register
+#define AT91C_HDMA_CH_7_SADDR (AT91C_CAST(AT91C_REG *) 	0xFFFFED54) // (HDMA_CH_7) HDMA Channel Source Address Register
+// ========== Register definition for HDMA peripheral ========== 
+#define AT91C_HDMA_EBCIDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC1C) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register
+#define AT91C_HDMA_LAST (AT91C_CAST(AT91C_REG *) 	0xFFFFEC10) // (HDMA) HDMA Software Last Transfer Flag Register
+#define AT91C_HDMA_SREQ (AT91C_CAST(AT91C_REG *) 	0xFFFFEC08) // (HDMA) HDMA Software Single Request Register
+#define AT91C_HDMA_RSVD0 (AT91C_CAST(AT91C_REG *) 	0xFFFFEC34) // (HDMA) HDMA Reserved
+#define AT91C_HDMA_EBCIER (AT91C_CAST(AT91C_REG *) 	0xFFFFEC18) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register
+#define AT91C_HDMA_GCFG (AT91C_CAST(AT91C_REG *) 	0xFFFFEC00) // (HDMA) HDMA Global Configuration Register
+#define AT91C_HDMA_CHER (AT91C_CAST(AT91C_REG *) 	0xFFFFEC28) // (HDMA) HDMA Channel Handler Enable Register
+#define AT91C_HDMA_RSVD1 (AT91C_CAST(AT91C_REG *) 	0xFFFFEC38) // (HDMA) HDMA Reserved
+#define AT91C_HDMA_CHDR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC2C) // (HDMA) HDMA Channel Handler Disable Register
+#define AT91C_HDMA_EBCIMR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC20) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register
+#define AT91C_HDMA_CREQ (AT91C_CAST(AT91C_REG *) 	0xFFFFEC0C) // (HDMA) HDMA Software Chunk Transfer Request Register
+#define AT91C_HDMA_SYNC (AT91C_CAST(AT91C_REG *) 	0xFFFFEC14) // (HDMA) HDMA Request Synchronization Register
+#define AT91C_HDMA_EN   (AT91C_CAST(AT91C_REG *) 	0xFFFFEC04) // (HDMA) HDMA Controller Enable Register
+#define AT91C_HDMA_EBCISR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC24) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register
+#define AT91C_HDMA_CHSR (AT91C_CAST(AT91C_REG *) 	0xFFFFEC30) // (HDMA) HDMA Channel Handler Status Register
+// ========== Register definition for HECC peripheral ========== 
+#define AT91C_HECC_VR   (AT91C_CAST(AT91C_REG *) 	0xFFFFE2FC) // (HECC)  ECC Version register
+#define AT91C_HECC_SR   (AT91C_CAST(AT91C_REG *) 	0xFFFFE208) // (HECC)  ECC Status register
+#define AT91C_HECC_CR   (AT91C_CAST(AT91C_REG *) 	0xFFFFE200) // (HECC)  ECC reset register
+#define AT91C_HECC_NPR  (AT91C_CAST(AT91C_REG *) 	0xFFFFE210) // (HECC)  ECC Parity N register
+#define AT91C_HECC_PR   (AT91C_CAST(AT91C_REG *) 	0xFFFFE20C) // (HECC)  ECC Parity register
+#define AT91C_HECC_MR   (AT91C_CAST(AT91C_REG *) 	0xFFFFE204) // (HECC)  ECC Page size register
+// ========== Register definition for EMACB peripheral ========== 
+#define AT91C_EMACB_ALE (AT91C_CAST(AT91C_REG *) 	0xFFFBC054) // (EMACB) Alignment Error Register
+#define AT91C_EMACB_RRE (AT91C_CAST(AT91C_REG *) 	0xFFFBC06C) // (EMACB) Receive Ressource Error Register
+#define AT91C_EMACB_SA4H (AT91C_CAST(AT91C_REG *) 	0xFFFBC0B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMACB_TPQ (AT91C_CAST(AT91C_REG *) 	0xFFFBC0BC) // (EMACB) Transmit Pause Quantum Register
+#define AT91C_EMACB_RJA (AT91C_CAST(AT91C_REG *) 	0xFFFBC07C) // (EMACB) Receive Jabbers Register
+#define AT91C_EMACB_SA2H (AT91C_CAST(AT91C_REG *) 	0xFFFBC0A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMACB_TPF (AT91C_CAST(AT91C_REG *) 	0xFFFBC08C) // (EMACB) Transmitted Pause Frames Register
+#define AT91C_EMACB_ROV (AT91C_CAST(AT91C_REG *) 	0xFFFBC070) // (EMACB) Receive Overrun Errors Register
+#define AT91C_EMACB_SA4L (AT91C_CAST(AT91C_REG *) 	0xFFFBC0B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMACB_MAN (AT91C_CAST(AT91C_REG *) 	0xFFFBC034) // (EMACB) PHY Maintenance Register
+#define AT91C_EMACB_TID (AT91C_CAST(AT91C_REG *) 	0xFFFBC0B8) // (EMACB) Type ID Checking Register
+#define AT91C_EMACB_TBQP (AT91C_CAST(AT91C_REG *) 	0xFFFBC01C) // (EMACB) Transmit Buffer Queue Pointer
+#define AT91C_EMACB_SA3L (AT91C_CAST(AT91C_REG *) 	0xFFFBC0A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMACB_DTF (AT91C_CAST(AT91C_REG *) 	0xFFFBC058) // (EMACB) Deferred Transmission Frame Register
+#define AT91C_EMACB_PTR (AT91C_CAST(AT91C_REG *) 	0xFFFBC038) // (EMACB) Pause Time Register
+#define AT91C_EMACB_CSE (AT91C_CAST(AT91C_REG *) 	0xFFFBC068) // (EMACB) Carrier Sense Error Register
+#define AT91C_EMACB_ECOL (AT91C_CAST(AT91C_REG *) 	0xFFFBC060) // (EMACB) Excessive Collision Register
+#define AT91C_EMACB_STE (AT91C_CAST(AT91C_REG *) 	0xFFFBC084) // (EMACB) SQE Test Error Register
+#define AT91C_EMACB_MCF (AT91C_CAST(AT91C_REG *) 	0xFFFBC048) // (EMACB) Multiple Collision Frame Register
+#define AT91C_EMACB_IER (AT91C_CAST(AT91C_REG *) 	0xFFFBC028) // (EMACB) Interrupt Enable Register
+#define AT91C_EMACB_ELE (AT91C_CAST(AT91C_REG *) 	0xFFFBC078) // (EMACB) Excessive Length Errors Register
+#define AT91C_EMACB_USRIO (AT91C_CAST(AT91C_REG *) 	0xFFFBC0C0) // (EMACB) USER Input/Output Register
+#define AT91C_EMACB_PFR (AT91C_CAST(AT91C_REG *) 	0xFFFBC03C) // (EMACB) Pause Frames received Register
+#define AT91C_EMACB_FCSE (AT91C_CAST(AT91C_REG *) 	0xFFFBC050) // (EMACB) Frame Check Sequence Error Register
+#define AT91C_EMACB_SA1L (AT91C_CAST(AT91C_REG *) 	0xFFFBC098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMACB_NCR (AT91C_CAST(AT91C_REG *) 	0xFFFBC000) // (EMACB) Network Control Register
+#define AT91C_EMACB_HRT (AT91C_CAST(AT91C_REG *) 	0xFFFBC094) // (EMACB) Hash Address Top[63:32]
+#define AT91C_EMACB_NCFGR (AT91C_CAST(AT91C_REG *) 	0xFFFBC004) // (EMACB) Network Configuration Register
+#define AT91C_EMACB_SCF (AT91C_CAST(AT91C_REG *) 	0xFFFBC044) // (EMACB) Single Collision Frame Register
+#define AT91C_EMACB_LCOL (AT91C_CAST(AT91C_REG *) 	0xFFFBC05C) // (EMACB) Late Collision Register
+#define AT91C_EMACB_SA3H (AT91C_CAST(AT91C_REG *) 	0xFFFBC0AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMACB_HRB (AT91C_CAST(AT91C_REG *) 	0xFFFBC090) // (EMACB) Hash Address Bottom[31:0]
+#define AT91C_EMACB_ISR (AT91C_CAST(AT91C_REG *) 	0xFFFBC024) // (EMACB) Interrupt Status Register
+#define AT91C_EMACB_IMR (AT91C_CAST(AT91C_REG *) 	0xFFFBC030) // (EMACB) Interrupt Mask Register
+#define AT91C_EMACB_WOL (AT91C_CAST(AT91C_REG *) 	0xFFFBC0C4) // (EMACB) Wake On LAN Register
+#define AT91C_EMACB_USF (AT91C_CAST(AT91C_REG *) 	0xFFFBC080) // (EMACB) Undersize Frames Register
+#define AT91C_EMACB_TSR (AT91C_CAST(AT91C_REG *) 	0xFFFBC014) // (EMACB) Transmit Status Register
+#define AT91C_EMACB_FRO (AT91C_CAST(AT91C_REG *) 	0xFFFBC04C) // (EMACB) Frames Received OK Register
+#define AT91C_EMACB_IDR (AT91C_CAST(AT91C_REG *) 	0xFFFBC02C) // (EMACB) Interrupt Disable Register
+#define AT91C_EMACB_SA1H (AT91C_CAST(AT91C_REG *) 	0xFFFBC09C) // (EMACB) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMACB_RLE (AT91C_CAST(AT91C_REG *) 	0xFFFBC088) // (EMACB) Receive Length Field Mismatch Register
+#define AT91C_EMACB_TUND (AT91C_CAST(AT91C_REG *) 	0xFFFBC064) // (EMACB) Transmit Underrun Error Register
+#define AT91C_EMACB_RSR (AT91C_CAST(AT91C_REG *) 	0xFFFBC020) // (EMACB) Receive Status Register
+#define AT91C_EMACB_SA2L (AT91C_CAST(AT91C_REG *) 	0xFFFBC0A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMACB_FTO (AT91C_CAST(AT91C_REG *) 	0xFFFBC040) // (EMACB) Frames Transmitted OK Register
+#define AT91C_EMACB_RSE (AT91C_CAST(AT91C_REG *) 	0xFFFBC074) // (EMACB) Receive Symbol Errors Register
+#define AT91C_EMACB_NSR (AT91C_CAST(AT91C_REG *) 	0xFFFBC008) // (EMACB) Network Status Register
+#define AT91C_EMACB_RBQP (AT91C_CAST(AT91C_REG *) 	0xFFFBC018) // (EMACB) Receive Buffer Queue Pointer
+#define AT91C_EMACB_REV (AT91C_CAST(AT91C_REG *) 	0xFFFBC0FC) // (EMACB) Revision Register
+// ========== Register definition for ISI peripheral ========== 
+#define AT91C_ISI_DMACHDR (AT91C_CAST(AT91C_REG *) 	0xFFFB403C) // (ISI) DMA Channel Disable Register
+#define AT91C_ISI_IMR   (AT91C_CAST(AT91C_REG *) 	0xFFFB4034) // (ISI) Interrupt Mask Register
+#define AT91C_ISI_R2YSET1 (AT91C_CAST(AT91C_REG *) 	0xFFFB401C) // (ISI) Color Space Conversion RGB to YCrCb Register
+#define AT91C_ISI_PDECF (AT91C_CAST(AT91C_REG *) 	0xFFFB400C) // (ISI) Preview Decimation Factor Register
+#define AT91C_ISI_CFG2  (AT91C_CAST(AT91C_REG *) 	0xFFFB4004) // (ISI) Configuration Register 2
+#define AT91C_ISI_DMACCTRL (AT91C_CAST(AT91C_REG *) 	0xFFFB4054) // (ISI) DMA Codec Control Register
+#define AT91C_ISI_CTRL  (AT91C_CAST(AT91C_REG *) 	0xFFFB4024) // (ISI) Control Register
+#define AT91C_ISI_Y2RSET0 (AT91C_CAST(AT91C_REG *) 	0xFFFB4010) // (ISI) Color Space Conversion YCrCb to RGB Register
+#define AT91C_ISI_WPSR  (AT91C_CAST(AT91C_REG *) 	0xFFFB40E8) // (ISI) Write Protection Status Register
+#define AT91C_ISI_DMACHER (AT91C_CAST(AT91C_REG *) 	0xFFFB4038) // (ISI) DMA Channel Enable Register
+#define AT91C_ISI_DMACHSR (AT91C_CAST(AT91C_REG *) 	0xFFFB4040) // (ISI) DMA Channel Status Register
+#define AT91C_ISI_IDR   (AT91C_CAST(AT91C_REG *) 	0xFFFB4030) // (ISI) Interrupt Disable Register
+#define AT91C_ISI_VER   (AT91C_CAST(AT91C_REG *) 	0xFFFB40FC) // (ISI) Version Register
+#define AT91C_ISI_Y2RSET1 (AT91C_CAST(AT91C_REG *) 	0xFFFB4014) // (ISI) Color Space Conversion YCrCb to RGB Register
+#define AT91C_ISI_R2YSET2 (AT91C_CAST(AT91C_REG *) 	0xFFFB4020) // (ISI) Color Space Conversion RGB to YCrCb Register
+#define AT91C_ISI_SR    (AT91C_CAST(AT91C_REG *) 	0xFFFB4028) // (ISI) Status Register
+#define AT91C_ISI_DMACDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFB4058) // (ISI) DMA Codec Descriptor Address Register
+#define AT91C_ISI_IER   (AT91C_CAST(AT91C_REG *) 	0xFFFB402C) // (ISI) Interrupt Enable Register
+#define AT91C_ISI_WPCR  (AT91C_CAST(AT91C_REG *) 	0xFFFB40E4) // (ISI) Write Protection Control Register
+#define AT91C_ISI_DMACADDR (AT91C_CAST(AT91C_REG *) 	0xFFFB4050) // (ISI) DMA Codec Base Address Register
+#define AT91C_ISI_CFG1  (AT91C_CAST(AT91C_REG *) 	0xFFFB4000) // (ISI) Configuration Register 1
+#define AT91C_ISI_R2YSET0 (AT91C_CAST(AT91C_REG *) 	0xFFFB4018) // (ISI) Color Space Conversion RGB to YCrCb Register
+#define AT91C_ISI_PSIZE (AT91C_CAST(AT91C_REG *) 	0xFFFB4008) // (ISI) Preview Size Register
+#define AT91C_ISI_DMAPDSCR (AT91C_CAST(AT91C_REG *) 	0xFFFB404C) // (ISI) DMA Preview Descriptor Address Register
+#define AT91C_ISI_DMAPADDR (AT91C_CAST(AT91C_REG *) 	0xFFFB4044) // (ISI) DMA Preview Base Address Register
+#define AT91C_ISI_DMAPCTRL (AT91C_CAST(AT91C_REG *) 	0xFFFB4048) // (ISI) DMA Preview Control Register
+// ========== Register definition for UHPHS_OHCI peripheral ========== 
+#define AT91C_OHCI_HcRhPortStatus (AT91C_CAST(AT91C_REG *) 	0x00700054) // (UHPHS_OHCI) Root Hub Port Status Register
+#define AT91C_OHCI_HcFmRemaining (AT91C_CAST(AT91C_REG *) 	0x00700038) // (UHPHS_OHCI) Bit time remaining in the current Frame
+#define AT91C_OHCI_HcInterruptEnable (AT91C_CAST(AT91C_REG *) 	0x00700010) // (UHPHS_OHCI) Interrupt Enable Register
+#define AT91C_OHCI_HcControl (AT91C_CAST(AT91C_REG *) 	0x00700004) // (UHPHS_OHCI) Operating modes for the Host Controller
+#define AT91C_OHCI_HcPeriodicStart (AT91C_CAST(AT91C_REG *) 	0x00700040) // (UHPHS_OHCI) Periodic Start
+#define AT91C_OHCI_HcInterruptStatus (AT91C_CAST(AT91C_REG *) 	0x0070000C) // (UHPHS_OHCI) Interrupt Status Register
+#define AT91C_OHCI_HcRhDescriptorB (AT91C_CAST(AT91C_REG *) 	0x0070004C) // (UHPHS_OHCI) Root Hub characteristics B
+#define AT91C_OHCI_HcInterruptDisable (AT91C_CAST(AT91C_REG *) 	0x00700014) // (UHPHS_OHCI) Interrupt Disable Register
+#define AT91C_OHCI_HcPeriodCurrentED (AT91C_CAST(AT91C_REG *) 	0x0070001C) // (UHPHS_OHCI) Current Isochronous or Interrupt Endpoint Descriptor
+#define AT91C_OHCI_HcRhDescriptorA (AT91C_CAST(AT91C_REG *) 	0x00700048) // (UHPHS_OHCI) Root Hub characteristics A
+#define AT91C_OHCI_HcRhStatus (AT91C_CAST(AT91C_REG *) 	0x00700050) // (UHPHS_OHCI) Root Hub Status register
+#define AT91C_OHCI_HcBulkCurrentED (AT91C_CAST(AT91C_REG *) 	0x0070002C) // (UHPHS_OHCI) Current endpoint of the Bulk list
+#define AT91C_OHCI_HcControlHeadED (AT91C_CAST(AT91C_REG *) 	0x00700020) // (UHPHS_OHCI) First Endpoint Descriptor of the Control list
+#define AT91C_OHCI_HcLSThreshold (AT91C_CAST(AT91C_REG *) 	0x00700044) // (UHPHS_OHCI) LS Threshold
+#define AT91C_OHCI_HcRevision (AT91C_CAST(AT91C_REG *) 	0x00700000) // (UHPHS_OHCI) Revision
+#define AT91C_OHCI_HcBulkDoneHead (AT91C_CAST(AT91C_REG *) 	0x00700030) // (UHPHS_OHCI) Last completed transfer descriptor
+#define AT91C_OHCI_HcFmNumber (AT91C_CAST(AT91C_REG *) 	0x0070003C) // (UHPHS_OHCI) Frame number
+#define AT91C_OHCI_HcFmInterval (AT91C_CAST(AT91C_REG *) 	0x00700034) // (UHPHS_OHCI) Bit time between 2 consecutive SOFs
+#define AT91C_OHCI_HcBulkHeadED (AT91C_CAST(AT91C_REG *) 	0x00700028) // (UHPHS_OHCI) First endpoint register of the Bulk list
+#define AT91C_OHCI_HcHCCA (AT91C_CAST(AT91C_REG *) 	0x00700018) // (UHPHS_OHCI) Pointer to the Host Controller Communication Area
+#define AT91C_OHCI_HcCommandStatus (AT91C_CAST(AT91C_REG *) 	0x00700008) // (UHPHS_OHCI) Command & status Register
+#define AT91C_OHCI_HcControlCurrentED (AT91C_CAST(AT91C_REG *) 	0x00700024) // (UHPHS_OHCI) Endpoint Control and Status Register
+// ========== Register definition for UHPHS_EHCI peripheral ========== 
+#define AT91C_EHCI_USBSTS (AT91C_CAST(AT91C_REG *) 	0x00800014) // (UHPHS_EHCI) 
+#define AT91C_EHCI_INSNREG03 (AT91C_CAST(AT91C_REG *) 	0x0080009C) // (UHPHS_EHCI) 
+#define AT91C_EHCI_INSNREG00 (AT91C_CAST(AT91C_REG *) 	0x00800090) // (UHPHS_EHCI) 
+#define AT91C_EHCI_HCSPPORTROUTE (AT91C_CAST(AT91C_REG *) 	0x0080000C) // (UHPHS_EHCI) 
+#define AT91C_EHCI_FRINDEX (AT91C_CAST(AT91C_REG *) 	0x0080001C) // (UHPHS_EHCI) 
+#define AT91C_EHCI_CONFIGFLAG (AT91C_CAST(AT91C_REG *) 	0x00800050) // (UHPHS_EHCI) 
+#define AT91C_EHCI_HCCPARAMS (AT91C_CAST(AT91C_REG *) 	0x00800008) // (UHPHS_EHCI) 
+#define AT91C_EHCI_USBINTR (AT91C_CAST(AT91C_REG *) 	0x00800018) // (UHPHS_EHCI) 
+#define AT91C_EHCI_PORTSC (AT91C_CAST(AT91C_REG *) 	0x00800054) // (UHPHS_EHCI) 
+#define AT91C_EHCI_CTRLDSSEGMENT (AT91C_CAST(AT91C_REG *) 	0x00800020) // (UHPHS_EHCI) 
+#define AT91C_EHCI_VERSION (AT91C_CAST(AT91C_REG *) 	0x00800000) // (UHPHS_EHCI) 
+#define AT91C_EHCI_USBCMD (AT91C_CAST(AT91C_REG *) 	0x00800010) // (UHPHS_EHCI) 
+#define AT91C_EHCI_INSNREG04 (AT91C_CAST(AT91C_REG *) 	0x008000A0) // (UHPHS_EHCI) 
+#define AT91C_EHCI_PERIODICLISTBASE (AT91C_CAST(AT91C_REG *) 	0x00800024) // (UHPHS_EHCI) 
+#define AT91C_EHCI_INSNREG01 (AT91C_CAST(AT91C_REG *) 	0x00800094) // (UHPHS_EHCI) 
+#define AT91C_EHCI_HCSPARAMS (AT91C_CAST(AT91C_REG *) 	0x00800004) // (UHPHS_EHCI) 
+#define AT91C_EHCI_INSNREG05 (AT91C_CAST(AT91C_REG *) 	0x008000A4) // (UHPHS_EHCI) 
+#define AT91C_EHCI_ASYNCLISTADDR (AT91C_CAST(AT91C_REG *) 	0x00800028) // (UHPHS_EHCI) 
+#define AT91C_EHCI_INSNREG02 (AT91C_CAST(AT91C_REG *) 	0x00800098) // (UHPHS_EHCI) 
+// ========== Register definition for TRNG peripheral ========== 
+#define AT91C_TRNG_IDR  (AT91C_CAST(AT91C_REG *) 	0xFFFCC014) // (TRNG) Interrupt Disable Register
+#define AT91C_TRNG_IER  (AT91C_CAST(AT91C_REG *) 	0xFFFCC010) // (TRNG) Interrupt Enable Register
+#define AT91C_TRNG_VERSION (AT91C_CAST(AT91C_REG *) 	0xFFFCC0FC) // (TRNG) TRNG Version Register
+#define AT91C_TRNG_ISR  (AT91C_CAST(AT91C_REG *) 	0xFFFCC01C) // (TRNG) Interrupt Status Register
+#define AT91C_TRNG_CR   (AT91C_CAST(AT91C_REG *) 	0xFFFCC000) // (TRNG) Control Register
+#define AT91C_TRNG_ODATA (AT91C_CAST(AT91C_REG *) 	0xFFFCC050) // (TRNG) Output Data Register
+#define AT91C_TRNG_IMR  (AT91C_CAST(AT91C_REG *) 	0xFFFCC018) // (TRNG) Interrupt Mask Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM9G45
+// *****************************************************************************
+#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_MCI0_CK  (AT91C_PIO_PA0) //  
+#define AT91C_PA0_TCLK3    (AT91C_PIO_PA0) //  
+#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_MCI0_CDA (AT91C_PIO_PA1) //  
+#define AT91C_PA1_TIOA3    (AT91C_PIO_PA1) //  
+#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_ETX0     (AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_ETX1     (AT91C_PIO_PA11) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_ERX0     (AT91C_PIO_PA12) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_ERX1     (AT91C_PIO_PA13) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_ETXEN    (AT91C_PIO_PA14) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_ERXDV    (AT91C_PIO_PA15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_ERXER    (AT91C_PIO_PA16) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_ETXCK_EREFCK (AT91C_PIO_PA17) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_EMDC     (AT91C_PIO_PA18) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_EMDIO    (AT91C_PIO_PA19) //  Ethernet MAC Management Data Input/Output
+#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_MCI0_DA0 (AT91C_PIO_PA2) //  
+#define AT91C_PA2_TIOB3    (AT91C_PIO_PA2) //  
+#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_TWD0     (AT91C_PIO_PA20) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TWCK0    (AT91C_PIO_PA21) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_MCI1_CDA (AT91C_PIO_PA22) //  
+#define AT91C_PA22_SCK3     (AT91C_PIO_PA22) //  
+#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_MCI1_DA0 (AT91C_PIO_PA23) //  
+#define AT91C_PA23_RTS3     (AT91C_PIO_PA23) //  
+#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_MCI1_DA1 (AT91C_PIO_PA24) //  
+#define AT91C_PA24_CTS3     (AT91C_PIO_PA24) //  
+#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_MCI1_DA2 (AT91C_PIO_PA25) //  
+#define AT91C_PA25_PWM3     (AT91C_PIO_PA25) //  
+#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_MCI1_DA3 (AT91C_PIO_PA26) //  
+#define AT91C_PA26_TIOB2    (AT91C_PIO_PA26) //  
+#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_MCI1_DA4 (AT91C_PIO_PA27) //  
+#define AT91C_PA27_ETXER    (AT91C_PIO_PA27) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_MCI1_DA5 (AT91C_PIO_PA28) //  
+#define AT91C_PA28_ERXCK    (AT91C_PIO_PA28) //  Ethernet MAC Receive Clock
+#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_MCI1_DA6 (AT91C_PIO_PA29) //  
+#define AT91C_PA29_ECRS     (AT91C_PIO_PA29) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_MCI0_DA1 (AT91C_PIO_PA3) //  
+#define AT91C_PA3_TCLK4    (AT91C_PIO_PA3) //  
+#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_MCI1_DA7 (AT91C_PIO_PA30) //  
+#define AT91C_PA30_ECOL     (AT91C_PIO_PA30) //  Ethernet MAC Collision Detected
+#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_MCI1_CK  (AT91C_PIO_PA31) //  
+#define AT91C_PA31_PCK0     (AT91C_PIO_PA31) //  
+#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_MCI0_DA2 (AT91C_PIO_PA4) //  
+#define AT91C_PA4_TIOA4    (AT91C_PIO_PA4) //  
+#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_MCI0_DA3 (AT91C_PIO_PA5) //  
+#define AT91C_PA5_TIOB4    (AT91C_PIO_PA5) //  
+#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_MCI0_DA4 (AT91C_PIO_PA6) //  
+#define AT91C_PA6_ETX2     (AT91C_PIO_PA6) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_MCI0_DA5 (AT91C_PIO_PA7) //  
+#define AT91C_PA7_ETX3     (AT91C_PIO_PA7) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_MCI0_DA6 (AT91C_PIO_PA8) //  
+#define AT91C_PA8_ERX2     (AT91C_PIO_PA8) //  Ethernet MAC Receive Data 2
+#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_MCI0_DA7 (AT91C_PIO_PA9) //  
+#define AT91C_PA9_ERX3     (AT91C_PIO_PA9) //  Ethernet MAC Receive Data 3
+#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_SPI0_MISO (AT91C_PIO_PB0) //  SPI 0 Master In Slave
+#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_SPI0_MOSI (AT91C_PIO_PB1) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_TWD1     (AT91C_PIO_PB10) //  
+#define AT91C_PB10_ISI_D10  (AT91C_PIO_PB10) //  
+#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_TWCK1    (AT91C_PIO_PB11) //  
+#define AT91C_PB11_ISI_D11  (AT91C_PIO_PB11) //  
+#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_DRXD     (AT91C_PIO_PB12) //  
+#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_DTXD     (AT91C_PIO_PB13) //  
+#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_SPI1_MISO (AT91C_PIO_PB14) //  
+#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_SPI1_MOSI (AT91C_PIO_PB15) //  
+#define AT91C_PB15_CTS0     (AT91C_PIO_PB15) //  
+#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_SPI1_SPCK (AT91C_PIO_PB16) //  
+#define AT91C_PB16_SCK0     (AT91C_PIO_PB16) //  
+#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_SPI1_NPCS0 (AT91C_PIO_PB17) //  
+#define AT91C_PB17_RTS0     (AT91C_PIO_PB17) //  
+#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_RXD0     (AT91C_PIO_PB18) //  
+#define AT91C_PB18_SPI0_NPCS1 (AT91C_PIO_PB18) //  
+#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_TXD0     (AT91C_PIO_PB19) //  
+#define AT91C_PB19_SPI0_NPCS2 (AT91C_PIO_PB19) //  
+#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_SPI0_SPCK (AT91C_PIO_PB2) //  SPI 0 Serial Clock
+#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_ISI_D0   (AT91C_PIO_PB20) //  
+#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_ISI_D1   (AT91C_PIO_PB21) //  
+#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_ISI_D2   (AT91C_PIO_PB22) //  
+#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_ISI_D3   (AT91C_PIO_PB23) //  
+#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_ISI_D4   (AT91C_PIO_PB24) //  
+#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_ISI_D5   (AT91C_PIO_PB25) //  
+#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_ISI_D6   (AT91C_PIO_PB26) //  
+#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_ISI_D7   (AT91C_PIO_PB27) //  
+#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_ISI_PCK  (AT91C_PIO_PB28) //  
+#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) //  
+#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_SPI0_NPCS0 (AT91C_PIO_PB3) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) //  
+#define AT91C_PIO_PB31       (1 << 31) // Pin Controlled by PB31
+#define AT91C_PB31_         (AT91C_PIO_PB31) //  
+#define AT91C_PB31_PCK1     (AT91C_PIO_PB31) //  
+#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_TXD1     (AT91C_PIO_PB4) //  USART 1 Transmit Data
+#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_RXD1     (AT91C_PIO_PB5) //  USART 1 Receive Data
+#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_TXD2     (AT91C_PIO_PB6) //  USART 2 Transmit Data
+#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_RXD2     (AT91C_PIO_PB7) //  USART 2 Receive Data
+#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_TXD3     (AT91C_PIO_PB8) //  USART 3 Transmit Data
+#define AT91C_PB8_ISI_D8   (AT91C_PIO_PB8) //  
+#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_RXD3     (AT91C_PIO_PB9) //  USART 3 Receive Data
+#define AT91C_PB9_ISI_D9   (AT91C_PIO_PB9) //  
+#define AT91C_PIO_PC0        (1 <<  0) // Pin Controlled by PC0
+#define AT91C_PC0_DQM2     (AT91C_PIO_PC0) //  DQM2
+#define AT91C_PIO_PC1        (1 <<  1) // Pin Controlled by PC1
+#define AT91C_PC1_DQM3     (AT91C_PIO_PC1) //  DQM3
+#define AT91C_PIO_PC10       (1 << 10) // Pin Controlled by PC10
+#define AT91C_PC10_NCS4_CFCS0 (AT91C_PIO_PC10) //  
+#define AT91C_PC10_TCLK2    (AT91C_PIO_PC10) //  
+#define AT91C_PIO_PC11       (1 << 11) // Pin Controlled by PC11
+#define AT91C_PC11_NCS5_CFCS1 (AT91C_PIO_PC11) //  
+#define AT91C_PC11_CTS2     (AT91C_PIO_PC11) //  
+#define AT91C_PIO_PC12       (1 << 12) // Pin Controlled by PC12
+#define AT91C_PC12_A25_CFRNW (AT91C_PIO_PC12) //  
+#define AT91C_PIO_PC13       (1 << 13) // Pin Controlled by PC13
+#define AT91C_PC13_NCS2     (AT91C_PIO_PC13) //  
+#define AT91C_PIO_PC14       (1 << 14) // Pin Controlled by PC14
+#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) //  
+#define AT91C_PIO_PC15       (1 << 15) // Pin Controlled by PC15
+#define AT91C_PC15_NWAIT    (AT91C_PIO_PC15) //  
+#define AT91C_PIO_PC16       (1 << 16) // Pin Controlled by PC16
+#define AT91C_PC16_D16      (AT91C_PIO_PC16) //  
+#define AT91C_PIO_PC17       (1 << 17) // Pin Controlled by PC17
+#define AT91C_PC17_D17      (AT91C_PIO_PC17) //  
+#define AT91C_PIO_PC18       (1 << 18) // Pin Controlled by PC18
+#define AT91C_PC18_D18      (AT91C_PIO_PC18) //  
+#define AT91C_PIO_PC19       (1 << 19) // Pin Controlled by PC19
+#define AT91C_PC19_D19      (AT91C_PIO_PC19) //  
+#define AT91C_PIO_PC2        (1 <<  2) // Pin Controlled by PC2
+#define AT91C_PC2_A19      (AT91C_PIO_PC2) //  
+#define AT91C_PIO_PC20       (1 << 20) // Pin Controlled by PC20
+#define AT91C_PC20_D20      (AT91C_PIO_PC20) //  
+#define AT91C_PIO_PC21       (1 << 21) // Pin Controlled by PC21
+#define AT91C_PC21_D21      (AT91C_PIO_PC21) //  
+#define AT91C_PIO_PC22       (1 << 22) // Pin Controlled by PC22
+#define AT91C_PC22_D22      (AT91C_PIO_PC22) //  
+#define AT91C_PIO_PC23       (1 << 23) // Pin Controlled by PC23
+#define AT91C_PC23_D23      (AT91C_PIO_PC23) //  
+#define AT91C_PIO_PC24       (1 << 24) // Pin Controlled by PC24
+#define AT91C_PC24_D24      (AT91C_PIO_PC24) //  
+#define AT91C_PIO_PC25       (1 << 25) // Pin Controlled by PC25
+#define AT91C_PC25_D25      (AT91C_PIO_PC25) //  
+#define AT91C_PIO_PC26       (1 << 26) // Pin Controlled by PC26
+#define AT91C_PC26_D26      (AT91C_PIO_PC26) //  
+#define AT91C_PIO_PC27       (1 << 27) // Pin Controlled by PC27
+#define AT91C_PC27_D27      (AT91C_PIO_PC27) //  
+#define AT91C_PIO_PC28       (1 << 28) // Pin Controlled by PC28
+#define AT91C_PC28_D28      (AT91C_PIO_PC28) //  
+#define AT91C_PIO_PC29       (1 << 29) // Pin Controlled by PC29
+#define AT91C_PC29_D29      (AT91C_PIO_PC29) //  
+#define AT91C_PIO_PC3        (1 <<  3) // Pin Controlled by PC3
+#define AT91C_PC3_A20      (AT91C_PIO_PC3) //  
+#define AT91C_PIO_PC30       (1 << 30) // Pin Controlled by PC30
+#define AT91C_PC30_D30      (AT91C_PIO_PC30) //  
+#define AT91C_PIO_PC31       (1 << 31) // Pin Controlled by PC31
+#define AT91C_PC31_D31      (AT91C_PIO_PC31) //  
+#define AT91C_PIO_PC4        (1 <<  4) // Pin Controlled by PC4
+#define AT91C_PC4_A21_NANDALE (AT91C_PIO_PC4) //  
+#define AT91C_PIO_PC5        (1 <<  5) // Pin Controlled by PC5
+#define AT91C_PC5_A22_NANDCLE (AT91C_PIO_PC5) //  
+#define AT91C_PIO_PC6        (1 <<  6) // Pin Controlled by PC6
+#define AT91C_PC6_A23      (AT91C_PIO_PC6) //  
+#define AT91C_PIO_PC7        (1 <<  7) // Pin Controlled by PC7
+#define AT91C_PC7_A24      (AT91C_PIO_PC7) //  
+#define AT91C_PIO_PC8        (1 <<  8) // Pin Controlled by PC8
+#define AT91C_PC8_CFCE1    (AT91C_PIO_PC8) //  
+#define AT91C_PIO_PC9        (1 <<  9) // Pin Controlled by PC9
+#define AT91C_PC9_CFCE2    (AT91C_PIO_PC9) //  
+#define AT91C_PC9_RTS2     (AT91C_PIO_PC9) //  
+#define AT91C_PIO_PD0        (1 <<  0) // Pin Controlled by PD0
+#define AT91C_PD0_TK0      (AT91C_PIO_PD0) //  
+#define AT91C_PD0_PWM3     (AT91C_PIO_PD0) //  
+#define AT91C_PIO_PD1        (1 <<  1) // Pin Controlled by PD1
+#define AT91C_PD1_TF0      (AT91C_PIO_PD1) //  
+#define AT91C_PIO_PD10       (1 << 10) // Pin Controlled by PD10
+#define AT91C_PD10_TD1      (AT91C_PIO_PD10) //  
+#define AT91C_PIO_PD11       (1 << 11) // Pin Controlled by PD11
+#define AT91C_PD11_RD1      (AT91C_PIO_PD11) //  
+#define AT91C_PIO_PD12       (1 << 12) // Pin Controlled by PD12
+#define AT91C_PD12_TK1      (AT91C_PIO_PD12) //  
+#define AT91C_PD12_PCK0     (AT91C_PIO_PD12) //  
+#define AT91C_PIO_PD13       (1 << 13) // Pin Controlled by PD13
+#define AT91C_PD13_RK1      (AT91C_PIO_PD13) //  
+#define AT91C_PIO_PD14       (1 << 14) // Pin Controlled by PD14
+#define AT91C_PD14_TF1      (AT91C_PIO_PD14) //  
+#define AT91C_PIO_PD15       (1 << 15) // Pin Controlled by PD15
+#define AT91C_PD15_RF1      (AT91C_PIO_PD15) //  
+#define AT91C_PIO_PD16       (1 << 16) // Pin Controlled by PD16
+#define AT91C_PD16_RTS1     (AT91C_PIO_PD16) //  
+#define AT91C_PIO_PD17       (1 << 17) // Pin Controlled by PD17
+#define AT91C_PD17_CTS1     (AT91C_PIO_PD17) //  
+#define AT91C_PIO_PD18       (1 << 18) // Pin Controlled by PD18
+#define AT91C_PD18_SPI1_NPCS2 (AT91C_PIO_PD18) //  
+#define AT91C_PD18_IRQ      (AT91C_PIO_PD18) //  
+#define AT91C_PIO_PD19       (1 << 19) // Pin Controlled by PD19
+#define AT91C_PD19_SPI1_NPCS3 (AT91C_PIO_PD19) //  
+#define AT91C_PD19_FIQ      (AT91C_PIO_PD19) //  
+#define AT91C_PIO_PD2        (1 <<  2) // Pin Controlled by PD2
+#define AT91C_PD2_TD0      (AT91C_PIO_PD2) //  
+#define AT91C_PIO_PD20       (1 << 20) // Pin Controlled by PD20
+#define AT91C_PD20_TIOA0    (AT91C_PIO_PD20) //  
+#define AT91C_PIO_PD21       (1 << 21) // Pin Controlled by PD21
+#define AT91C_PD21_TIOA1    (AT91C_PIO_PD21) //  
+#define AT91C_PIO_PD22       (1 << 22) // Pin Controlled by PD22
+#define AT91C_PD22_TIOA2    (AT91C_PIO_PD22) //  
+#define AT91C_PIO_PD23       (1 << 23) // Pin Controlled by PD23
+#define AT91C_PD23_TCLK0    (AT91C_PIO_PD23) //  
+#define AT91C_PIO_PD24       (1 << 24) // Pin Controlled by PD24
+#define AT91C_PD24_SPI0_NPCS1 (AT91C_PIO_PD24) //  
+#define AT91C_PD24_PWM0     (AT91C_PIO_PD24) //  
+#define AT91C_PIO_PD25       (1 << 25) // Pin Controlled by PD25
+#define AT91C_PD25_SPI0_NPCS2 (AT91C_PIO_PD25) //  
+#define AT91C_PD25_PWM1     (AT91C_PIO_PD25) //  
+#define AT91C_PIO_PD26       (1 << 26) // Pin Controlled by PD26
+#define AT91C_PD26_PCK0     (AT91C_PIO_PD26) //  
+#define AT91C_PD26_PWM2     (AT91C_PIO_PD26) //  
+#define AT91C_PIO_PD27       (1 << 27) // Pin Controlled by PD27
+#define AT91C_PD27_PCK1     (AT91C_PIO_PD27) //  
+#define AT91C_PD27_SPI0_NPCS3 (AT91C_PIO_PD27) //  
+#define AT91C_PIO_PD28       (1 << 28) // Pin Controlled by PD28
+#define AT91C_PD28_TSADTRG  (AT91C_PIO_PD28) //  
+#define AT91C_PD28_SPI1_NPCS1 (AT91C_PIO_PD28) //  
+#define AT91C_PIO_PD29       (1 << 29) // Pin Controlled by PD29
+#define AT91C_PD29_TCLK1    (AT91C_PIO_PD29) //  
+#define AT91C_PD29_SCK1     (AT91C_PIO_PD29) //  
+#define AT91C_PIO_PD3        (1 <<  3) // Pin Controlled by PD3
+#define AT91C_PD3_RD0      (AT91C_PIO_PD3) //  
+#define AT91C_PIO_PD30       (1 << 30) // Pin Controlled by PD30
+#define AT91C_PD30_TIOB0    (AT91C_PIO_PD30) //  
+#define AT91C_PD30_SCK2     (AT91C_PIO_PD30) //  
+#define AT91C_PIO_PD31       (1 << 31) // Pin Controlled by PD31
+#define AT91C_PD31_TIOB1    (AT91C_PIO_PD31) //  
+#define AT91C_PD31_PWM1     (AT91C_PIO_PD31) //  
+#define AT91C_PIO_PD4        (1 <<  4) // Pin Controlled by PD4
+#define AT91C_PD4_RK0      (AT91C_PIO_PD4) //  
+#define AT91C_PIO_PD5        (1 <<  5) // Pin Controlled by PD5
+#define AT91C_PD5_RF0      (AT91C_PIO_PD5) //  
+#define AT91C_PIO_PD6        (1 <<  6) // Pin Controlled by PD6
+#define AT91C_PD6_AC97RX   (AT91C_PIO_PD6) //  
+#define AT91C_PIO_PD7        (1 <<  7) // Pin Controlled by PD7
+#define AT91C_PD7_AC97TX   (AT91C_PIO_PD7) //  
+#define AT91C_PD7_TIOA5    (AT91C_PIO_PD7) //  
+#define AT91C_PIO_PD8        (1 <<  8) // Pin Controlled by PD8
+#define AT91C_PD8_AC97FS   (AT91C_PIO_PD8) //  
+#define AT91C_PD8_TIOB5    (AT91C_PIO_PD8) //  
+#define AT91C_PIO_PD9        (1 <<  9) // Pin Controlled by PD9
+#define AT91C_PD9_AC97CK   (AT91C_PIO_PD9) //  
+#define AT91C_PD9_TCLK5    (AT91C_PIO_PD9) //  
+#define AT91C_PIO_PE0        (1 <<  0) // Pin Controlled by PE0
+#define AT91C_PE0_LCDPWR   (AT91C_PIO_PE0) //  
+#define AT91C_PE0_PCK0     (AT91C_PIO_PE0) //  
+#define AT91C_PIO_PE1        (1 <<  1) // Pin Controlled by PE1
+#define AT91C_PE1_LCDMOD   (AT91C_PIO_PE1) //  
+#define AT91C_PIO_PE10       (1 << 10) // Pin Controlled by PE10
+#define AT91C_PE10_LCDD3    (AT91C_PIO_PE10) //  
+#define AT91C_PE10_LCDD5    (AT91C_PIO_PE10) //  
+#define AT91C_PIO_PE11       (1 << 11) // Pin Controlled by PE11
+#define AT91C_PE11_LCDD4    (AT91C_PIO_PE11) //  
+#define AT91C_PE11_LCDD6    (AT91C_PIO_PE11) //  
+#define AT91C_PIO_PE12       (1 << 12) // Pin Controlled by PE12
+#define AT91C_PE12_LCDD5    (AT91C_PIO_PE12) //  
+#define AT91C_PE12_LCDD7    (AT91C_PIO_PE12) //  
+#define AT91C_PIO_PE13       (1 << 13) // Pin Controlled by PE13
+#define AT91C_PE13_LCDD6    (AT91C_PIO_PE13) //  
+#define AT91C_PE13_LCDD10   (AT91C_PIO_PE13) //  
+#define AT91C_PIO_PE14       (1 << 14) // Pin Controlled by PE14
+#define AT91C_PE14_LCDD7    (AT91C_PIO_PE14) //  
+#define AT91C_PE14_LCDD11   (AT91C_PIO_PE14) //  
+#define AT91C_PIO_PE15       (1 << 15) // Pin Controlled by PE15
+#define AT91C_PE15_LCDD8    (AT91C_PIO_PE15) //  
+#define AT91C_PE15_LCDD12   (AT91C_PIO_PE15) //  
+#define AT91C_PIO_PE16       (1 << 16) // Pin Controlled by PE16
+#define AT91C_PE16_LCDD9    (AT91C_PIO_PE16) //  
+#define AT91C_PE16_LCDD13   (AT91C_PIO_PE16) //  
+#define AT91C_PIO_PE17       (1 << 17) // Pin Controlled by PE17
+#define AT91C_PE17_LCDD10   (AT91C_PIO_PE17) //  
+#define AT91C_PE17_LCDD14   (AT91C_PIO_PE17) //  
+#define AT91C_PIO_PE18       (1 << 18) // Pin Controlled by PE18
+#define AT91C_PE18_LCDD11   (AT91C_PIO_PE18) //  
+#define AT91C_PE18_LCDD15   (AT91C_PIO_PE18) //  
+#define AT91C_PIO_PE19       (1 << 19) // Pin Controlled by PE19
+#define AT91C_PE19_LCDD12   (AT91C_PIO_PE19) //  
+#define AT91C_PE19_LCDD18   (AT91C_PIO_PE19) //  
+#define AT91C_PIO_PE2        (1 <<  2) // Pin Controlled by PE2
+#define AT91C_PE2_LCDCC    (AT91C_PIO_PE2) //  
+#define AT91C_PIO_PE20       (1 << 20) // Pin Controlled by PE20
+#define AT91C_PE20_LCDD13   (AT91C_PIO_PE20) //  
+#define AT91C_PE20_LCDD19   (AT91C_PIO_PE20) //  
+#define AT91C_PIO_PE21       (1 << 21) // Pin Controlled by PE21
+#define AT91C_PE21_LCDD14   (AT91C_PIO_PE21) //  
+#define AT91C_PE21_LCDD20   (AT91C_PIO_PE21) //  
+#define AT91C_PIO_PE22       (1 << 22) // Pin Controlled by PE22
+#define AT91C_PE22_LCDD15   (AT91C_PIO_PE22) //  
+#define AT91C_PE22_LCDD21   (AT91C_PIO_PE22) //  
+#define AT91C_PIO_PE23       (1 << 23) // Pin Controlled by PE23
+#define AT91C_PE23_LCDD16   (AT91C_PIO_PE23) //  
+#define AT91C_PE23_LCDD22   (AT91C_PIO_PE23) //  
+#define AT91C_PIO_PE24       (1 << 24) // Pin Controlled by PE24
+#define AT91C_PE24_LCDD17   (AT91C_PIO_PE24) //  
+#define AT91C_PE24_LCDD23   (AT91C_PIO_PE24) //  
+#define AT91C_PIO_PE25       (1 << 25) // Pin Controlled by PE25
+#define AT91C_PE25_LCDD18   (AT91C_PIO_PE25) //  
+#define AT91C_PIO_PE26       (1 << 26) // Pin Controlled by PE26
+#define AT91C_PE26_LCDD19   (AT91C_PIO_PE26) //  
+#define AT91C_PIO_PE27       (1 << 27) // Pin Controlled by PE27
+#define AT91C_PE27_LCDD20   (AT91C_PIO_PE27) //  
+#define AT91C_PIO_PE28       (1 << 28) // Pin Controlled by PE28
+#define AT91C_PE28_LCDD21   (AT91C_PIO_PE28) //  
+#define AT91C_PIO_PE29       (1 << 29) // Pin Controlled by PE29
+#define AT91C_PE29_LCDD22   (AT91C_PIO_PE29) //  
+#define AT91C_PIO_PE3        (1 <<  3) // Pin Controlled by PE3
+#define AT91C_PE3_LCDVSYNC (AT91C_PIO_PE3) //  
+#define AT91C_PIO_PE30       (1 << 30) // Pin Controlled by PE30
+#define AT91C_PE30_LCDD23   (AT91C_PIO_PE30) //  
+#define AT91C_PIO_PE31       (1 << 31) // Pin Controlled by PE31
+#define AT91C_PE31_PWM2     (AT91C_PIO_PE31) //  
+#define AT91C_PE31_PCK1     (AT91C_PIO_PE31) //  
+#define AT91C_PIO_PE4        (1 <<  4) // Pin Controlled by PE4
+#define AT91C_PE4_LCDHSYNC (AT91C_PIO_PE4) //  
+#define AT91C_PIO_PE5        (1 <<  5) // Pin Controlled by PE5
+#define AT91C_PE5_LCDDOTCK (AT91C_PIO_PE5) //  
+#define AT91C_PIO_PE6        (1 <<  6) // Pin Controlled by PE6
+#define AT91C_PE6_LCDDEN   (AT91C_PIO_PE6) //  
+#define AT91C_PIO_PE7        (1 <<  7) // Pin Controlled by PE7
+#define AT91C_PE7_LCDD0    (AT91C_PIO_PE7) //  
+#define AT91C_PE7_LCDD2    (AT91C_PIO_PE7) //  
+#define AT91C_PIO_PE8        (1 <<  8) // Pin Controlled by PE8
+#define AT91C_PE8_LCDD1    (AT91C_PIO_PE8) //  
+#define AT91C_PE8_LCDD3    (AT91C_PIO_PE8) //  
+#define AT91C_PIO_PE9        (1 <<  9) // Pin Controlled by PE9
+#define AT91C_PE9_LCDD2    (AT91C_PIO_PE9) //  
+#define AT91C_PE9_LCDD4    (AT91C_PIO_PE9) //  
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM9G45
+// *****************************************************************************
+#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ( 1) // System Controller
+#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
+#define AT91C_ID_PIOC   ( 4) // Parallel IO Controller C
+#define AT91C_ID_PIOD_E ( 5) // Parallel IO Controller D and E
+#define AT91C_ID_TRNG   ( 6) // True Random Number Generator
+#define AT91C_ID_US0    ( 7) // USART 0
+#define AT91C_ID_US1    ( 8) // USART 1
+#define AT91C_ID_US2    ( 9) // USART 2
+#define AT91C_ID_US3    (10) // USART 2
+#define AT91C_ID_MCI0   (11) // Multimedia Card Interface 0
+#define AT91C_ID_TWI0   (12) // TWI 0
+#define AT91C_ID_TWI1   (13) // TWI 1
+#define AT91C_ID_SPI0   (14) // Serial Peripheral Interface
+#define AT91C_ID_SPI1   (15) // Serial Peripheral Interface
+#define AT91C_ID_SSC0   (16) // Serial Synchronous Controller 0
+#define AT91C_ID_SSC1   (17) // Serial Synchronous Controller 1
+#define AT91C_ID_TC     (18) // Timer Counter 0, 1, 2, 3, 4, 5
+#define AT91C_ID_PWMC   (19) // Pulse Width Modulation Controller
+#define AT91C_ID_TSADC  (20) // Touch Screen Controller
+#define AT91C_ID_HDMA   (21) // HDMA
+#define AT91C_ID_UHPHS  (22) // USB Host High Speed
+#define AT91C_ID_LCDC   (23) // LCD Controller
+#define AT91C_ID_AC97C  (24) // AC97 Controller
+#define AT91C_ID_EMAC   (25) // Ethernet MAC
+#define AT91C_ID_ISI    (26) // Image Sensor Interface
+#define AT91C_ID_UDPHS  (27) // USB Device HS
+#define AT91C_ID_MCI1   (29) // Multimedia Card Interface 1
+#define AT91C_ID_VDEC   (30) // Video Decoder
+#define AT91C_ID_IRQ0   (31) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ALL_INT   (0xEFFFFFFF) // ALL VALID INTERRUPTS
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM9G45
+// *****************************************************************************
+#define AT91C_BASE_SFR       (AT91C_CAST(AT91PS_SFR) 	0xFFF74000) // (SFR) Base Address
+#define AT91C_BASE_SYS       (AT91C_CAST(AT91PS_SYS) 	0xFFFFC000) // (SYS) Base Address
+#define AT91C_BASE_EBI       (AT91C_CAST(AT91PS_EBI) 	0xFFFFE200) // (EBI) Base Address
+#define AT91C_BASE_DDR2CP1   (AT91C_CAST(AT91PS_HDDRSDRC2) 	0xFFFFE400) // (DDR2CP1) Base Address
+#define AT91C_BASE_DDR2C     (AT91C_CAST(AT91PS_HDDRSDRC2) 	0xFFFFE600) // (DDR2C) Base Address
+#define AT91C_BASE_SMC       (AT91C_CAST(AT91PS_SMC) 	0xFFFFE800) // (SMC) Base Address
+#define AT91C_BASE_MATRIX    (AT91C_CAST(AT91PS_MATRIX) 	0xFFFFEA00) // (MATRIX) Base Address
+#define AT91C_BASE_AIC       (AT91C_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  (AT91C_CAST(AT91PS_PDC) 	0xFFFFEF00) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      (AT91C_CAST(AT91PS_DBGU) 	0xFFFFEE00) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      (AT91C_CAST(AT91PS_PIO) 	0xFFFFF200) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      (AT91C_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOB) Base Address
+#define AT91C_BASE_PIOC      (AT91C_CAST(AT91PS_PIO) 	0xFFFFF600) // (PIOC) Base Address
+#define AT91C_BASE_PIOD      (AT91C_CAST(AT91PS_PIO) 	0xFFFFF800) // (PIOD) Base Address
+#define AT91C_BASE_PIOE      (AT91C_CAST(AT91PS_PIO) 	0xFFFFFA00) // (PIOE) Base Address
+#define AT91C_BASE_PMC       (AT91C_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_CKGR      (AT91C_CAST(AT91PS_CKGR) 	0xFFFFFC1C) // (CKGR) Base Address
+#define AT91C_BASE_RSTC      (AT91C_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_SHDWC     (AT91C_CAST(AT91PS_SHDWC) 	0xFFFFFD10) // (SHDWC) Base Address
+#define AT91C_BASE_RTTC      (AT91C_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      (AT91C_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      (AT91C_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_RTC       (AT91C_CAST(AT91PS_RTC) 	0xFFFFFDB0) // (RTC) Base Address
+#define AT91C_BASE_TC0       (AT91C_CAST(AT91PS_TC) 	0xFFF7C000) // (TC0) Base Address
+#define AT91C_BASE_TC1       (AT91C_CAST(AT91PS_TC) 	0xFFF7C040) // (TC1) Base Address
+#define AT91C_BASE_TC2       (AT91C_CAST(AT91PS_TC) 	0xFFF7C080) // (TC2) Base Address
+#define AT91C_BASE_TC3       (AT91C_CAST(AT91PS_TC) 	0xFFFD4000) // (TC3) Base Address
+#define AT91C_BASE_TC4       (AT91C_CAST(AT91PS_TC) 	0xFFFD4040) // (TC4) Base Address
+#define AT91C_BASE_TC5       (AT91C_CAST(AT91PS_TC) 	0xFFFD4080) // (TC5) Base Address
+#define AT91C_BASE_TCB0      (AT91C_CAST(AT91PS_TCB) 	0xFFF7C000) // (TCB0) Base Address
+#define AT91C_BASE_TCB1      (AT91C_CAST(AT91PS_TCB) 	0xFFFD4000) // (TCB1) Base Address
+#define AT91C_BASE_MCI0      (AT91C_CAST(AT91PS_MCI) 	0xFFF80000) // (MCI0) Base Address
+#define AT91C_BASE_MCI1      (AT91C_CAST(AT91PS_MCI) 	0xFFFD0000) // (MCI1) Base Address
+#define AT91C_BASE_TWI0      (AT91C_CAST(AT91PS_TWI) 	0xFFF84000) // (TWI0) Base Address
+#define AT91C_BASE_TWI1      (AT91C_CAST(AT91PS_TWI) 	0xFFF88000) // (TWI1) Base Address
+#define AT91C_BASE_PDC_US0   (AT91C_CAST(AT91PS_PDC) 	0xFFF8C100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       (AT91C_CAST(AT91PS_USART) 	0xFFF8C000) // (US0) Base Address
+#define AT91C_BASE_PDC_US1   (AT91C_CAST(AT91PS_PDC) 	0xFFF90100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       (AT91C_CAST(AT91PS_USART) 	0xFFF90000) // (US1) Base Address
+#define AT91C_BASE_PDC_US2   (AT91C_CAST(AT91PS_PDC) 	0xFFF94100) // (PDC_US2) Base Address
+#define AT91C_BASE_US2       (AT91C_CAST(AT91PS_USART) 	0xFFF94000) // (US2) Base Address
+#define AT91C_BASE_PDC_US3   (AT91C_CAST(AT91PS_PDC) 	0xFFF98100) // (PDC_US3) Base Address
+#define AT91C_BASE_US3       (AT91C_CAST(AT91PS_USART) 	0xFFF98000) // (US3) Base Address
+#define AT91C_BASE_PDC_SSC0  (AT91C_CAST(AT91PS_PDC) 	0xFFF9C100) // (PDC_SSC0) Base Address
+#define AT91C_BASE_SSC0      (AT91C_CAST(AT91PS_SSC) 	0xFFF9C000) // (SSC0) Base Address
+#define AT91C_BASE_PDC_SSC1  (AT91C_CAST(AT91PS_PDC) 	0xFFFA0100) // (PDC_SSC1) Base Address
+#define AT91C_BASE_SSC1      (AT91C_CAST(AT91PS_SSC) 	0xFFFA0000) // (SSC1) Base Address
+#define AT91C_BASE_PWMC_CH0  (AT91C_CAST(AT91PS_PWMC_CH) 	0xFFFB8200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC_CH1  (AT91C_CAST(AT91PS_PWMC_CH) 	0xFFFB8220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH2  (AT91C_CAST(AT91PS_PWMC_CH) 	0xFFFB8240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH3  (AT91C_CAST(AT91PS_PWMC_CH) 	0xFFFB8260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC      (AT91C_CAST(AT91PS_PWMC) 	0xFFFB8000) // (PWMC) Base Address
+#define AT91C_BASE_PDC_SPI0  (AT91C_CAST(AT91PS_PDC) 	0xFFFA4100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_PDC_SPI1  (AT91C_CAST(AT91PS_PDC) 	0xFFFA8100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI0      (AT91C_CAST(AT91PS_SPI) 	0xFFFA4000) // (SPI0) Base Address
+#define AT91C_BASE_SPI1      (AT91C_CAST(AT91PS_SPI) 	0xFFFA8000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_TSADC (AT91C_CAST(AT91PS_PDC) 	0xFFFB0100) // (PDC_TSADC) Base Address
+#define AT91C_BASE_TSADC     (AT91C_CAST(AT91PS_TSADC) 	0xFFFB0000) // (TSADC) Base Address
+#define AT91C_BASE_UDPHS_EPTFIFO (AT91C_CAST(AT91PS_UDPHS_EPTFIFO) 	0x00600000) // (UDPHS_EPTFIFO) Base Address
+#define AT91C_BASE_UDPHS_EPT_0 (AT91C_CAST(AT91PS_UDPHS_EPT) 	0xFFF78100) // (UDPHS_EPT_0) Base Address
+#define AT91C_BASE_UDPHS_EPT_1 (AT91C_CAST(AT91PS_UDPHS_EPT) 	0xFFF78120) // (UDPHS_EPT_1) Base Address
+#define AT91C_BASE_UDPHS_EPT_2 (AT91C_CAST(AT91PS_UDPHS_EPT) 	0xFFF78140) // (UDPHS_EPT_2) Base Address
+#define AT91C_BASE_UDPHS_EPT_3 (AT91C_CAST(AT91PS_UDPHS_EPT) 	0xFFF78160) // (UDPHS_EPT_3) Base Address
+#define AT91C_BASE_UDPHS_EPT_4 (AT91C_CAST(AT91PS_UDPHS_EPT) 	0xFFF78180) // (UDPHS_EPT_4) Base Address
+#define AT91C_BASE_UDPHS_EPT_5 (AT91C_CAST(AT91PS_UDPHS_EPT) 	0xFFF781A0) // (UDPHS_EPT_5) Base Address
+#define AT91C_BASE_UDPHS_EPT_6 (AT91C_CAST(AT91PS_UDPHS_EPT) 	0xFFF781C0) // (UDPHS_EPT_6) Base Address
+#define AT91C_BASE_UDPHS_DMA_1 (AT91C_CAST(AT91PS_UDPHS_DMA) 	0xFFF78310) // (UDPHS_DMA_1) Base Address
+#define AT91C_BASE_UDPHS_DMA_2 (AT91C_CAST(AT91PS_UDPHS_DMA) 	0xFFF78320) // (UDPHS_DMA_2) Base Address
+#define AT91C_BASE_UDPHS_DMA_3 (AT91C_CAST(AT91PS_UDPHS_DMA) 	0xFFF78330) // (UDPHS_DMA_3) Base Address
+#define AT91C_BASE_UDPHS_DMA_4 (AT91C_CAST(AT91PS_UDPHS_DMA) 	0xFFF78340) // (UDPHS_DMA_4) Base Address
+#define AT91C_BASE_UDPHS_DMA_5 (AT91C_CAST(AT91PS_UDPHS_DMA) 	0xFFF78350) // (UDPHS_DMA_5) Base Address
+#define AT91C_BASE_UDPHS_DMA_6 (AT91C_CAST(AT91PS_UDPHS_DMA) 	0xFFF78360) // (UDPHS_DMA_6) Base Address
+#define AT91C_BASE_UDPHS     (AT91C_CAST(AT91PS_UDPHS) 	0xFFF78000) // (UDPHS) Base Address
+#define AT91C_BASE_PDC_AC97C (AT91C_CAST(AT91PS_PDC) 	0xFFFAC100) // (PDC_AC97C) Base Address
+#define AT91C_BASE_AC97C     (AT91C_CAST(AT91PS_AC97C) 	0xFFFAC000) // (AC97C) Base Address
+#define AT91C_BASE_LCDC      (AT91C_CAST(AT91PS_LCDC) 	0x00500000) // (LCDC) Base Address
+#define AT91C_BASE_LCDC_16B_TFT (AT91C_CAST(AT91PS_LCDC) 	0x00500000) // (LCDC_16B_TFT) Base Address
+#define AT91C_BASE_HDMA_CH_0 (AT91C_CAST(AT91PS_HDMA_CH) 	0xFFFFEC3C) // (HDMA_CH_0) Base Address
+#define AT91C_BASE_HDMA_CH_1 (AT91C_CAST(AT91PS_HDMA_CH) 	0xFFFFEC64) // (HDMA_CH_1) Base Address
+#define AT91C_BASE_HDMA_CH_2 (AT91C_CAST(AT91PS_HDMA_CH) 	0xFFFFEC8C) // (HDMA_CH_2) Base Address
+#define AT91C_BASE_HDMA_CH_3 (AT91C_CAST(AT91PS_HDMA_CH) 	0xFFFFECB4) // (HDMA_CH_3) Base Address
+#define AT91C_BASE_HDMA_CH_4 (AT91C_CAST(AT91PS_HDMA_CH) 	0xFFFFECDC) // (HDMA_CH_4) Base Address
+#define AT91C_BASE_HDMA_CH_5 (AT91C_CAST(AT91PS_HDMA_CH) 	0xFFFFED04) // (HDMA_CH_5) Base Address
+#define AT91C_BASE_HDMA_CH_6 (AT91C_CAST(AT91PS_HDMA_CH) 	0xFFFFED2C) // (HDMA_CH_6) Base Address
+#define AT91C_BASE_HDMA_CH_7 (AT91C_CAST(AT91PS_HDMA_CH) 	0xFFFFED54) // (HDMA_CH_7) Base Address
+#define AT91C_BASE_HDMA      (AT91C_CAST(AT91PS_HDMA) 	0xFFFFEC00) // (HDMA) Base Address
+#define AT91C_BASE_HECC      (AT91C_CAST(AT91PS_ECC) 	0xFFFFE200) // (HECC) Base Address
+#define AT91C_BASE_EMACB     (AT91C_CAST(AT91PS_EMAC) 	0xFFFBC000) // (EMACB) Base Address
+#define AT91C_BASE_ISI       (AT91C_CAST(AT91PS_ISI) 	0xFFFB4000) // (ISI) Base Address
+#define AT91C_BASE_UHPHS_OHCI (AT91C_CAST(AT91PS_UHPHS_OHCI) 	0x00700000) // (UHPHS_OHCI) Base Address
+#define AT91C_BASE_UHPHS_EHCI (AT91C_CAST(AT91PS_UHPHS_EHCI) 	0x00800000) // (UHPHS_EHCI) Base Address
+#define AT91C_BASE_TRNG      (AT91C_CAST(AT91PS_TRNG) 	0xFFFCC000) // (TRNG) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM9G45
+// *****************************************************************************
+// ITCM
+#define AT91C_ITCM 	 (0x00100000) // Maximum ITCM Area base address
+// DTCM
+#define AT91C_DTCM 	 (0x00200000) // Maximum DTCM Area base address
+// IRAM
+#define AT91C_IRAM 	 (0x00300000) // Maximum Internal SRAM base address
+#define AT91C_IRAM_SIZE	 (0x00010000) // Maximum Internal SRAM size in byte (64 Kbytes)
+// IRAM_MIN
+#define AT91C_IRAM_MIN	 (0x00300000) // Minimum Internal RAM base address
+#define AT91C_IRAM_MIN_SIZE	 (0x00004000) // Minimum Internal RAM size in byte (16 Kbytes)
+// IROM
+#define AT91C_IROM 	 (0x00400000) // Internal ROM base address
+#define AT91C_IROM_SIZE	 (0x00010000) // Internal ROM size in byte (64 Kbytes)
+// EBI_CS0
+#define AT91C_EBI_CS0	 (0x10000000) // EBI Chip Select 0 base address
+#define AT91C_EBI_CS0_SIZE	 (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
+// EBI_CS1
+#define AT91C_EBI_CS1	 (0x20000000) // EBI Chip Select 1 base address
+#define AT91C_EBI_CS1_SIZE	 (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM
+#define AT91C_EBI_SDRAM	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_SIZE	 (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM_16BIT
+#define AT91C_EBI_SDRAM_16BIT	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_16BIT_SIZE	 (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
+// EBI_SDRAM_32BIT
+#define AT91C_EBI_SDRAM_32BIT	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_32BIT_SIZE	 (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
+// EBI_CS2
+#define AT91C_EBI_CS2	 (0x30000000) // EBI Chip Select 2 base address
+#define AT91C_EBI_CS2_SIZE	 (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
+// EBI_CS3
+#define AT91C_EBI_CS3	 (0x40000000) // EBI Chip Select 3 base address
+#define AT91C_EBI_CS3_SIZE	 (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
+// EBI_SM
+#define AT91C_EBI_SM	 (0x40000000) // NANDFLASH on EBI Chip Select 3 base address
+#define AT91C_EBI_SM_SIZE	 (0x10000000) // NANDFLASH on EBI Chip Select 3 size in byte (262144 Kbytes)
+// EBI_CS4
+#define AT91C_EBI_CS4	 (0x50000000) // EBI Chip Select 4 base address
+#define AT91C_EBI_CS4_SIZE	 (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CF0
+#define AT91C_EBI_CF0	 (0x50000000) // CompactFlash 0 on EBI Chip Select 4 base address
+#define AT91C_EBI_CF0_SIZE	 (0x10000000) // CompactFlash 0 on EBI Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CS5
+#define AT91C_EBI_CS5	 (0x60000000) // EBI Chip Select 5 base address
+#define AT91C_EBI_CS5_SIZE	 (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CF1
+#define AT91C_EBI_CF1	 (0x60000000) // CompactFlash 1 on EBIChip Select 5 base address
+#define AT91C_EBI_CF1_SIZE	 (0x10000000) // CompactFlash 1 on EBIChip Select 5 size in byte (262144 Kbytes)
+// DDR2
+#define AT91C_DDR2 	 (0x70000000) // DDR2/LPDDR space base address
+#define AT91C_DDR2_SIZE	 (0x10000000) // DDR2/LPDDR space size in byte (262144 Kbytes)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtthread.h>
+#include "io.h"
+#include "irq.h"
+#include "gpio.h"
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+extern struct clk *clk_get(const char *id);
+extern rt_uint32_t clk_get_rate(struct clk *clk);
+extern void rt_hw_clock_init(void);
+
+#define AT91C_SLOW_CLOCK		32768		/* slow clock */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at91sam9g45/platform/gpio.h b/bsp/at91sam9g45/platform/gpio.h
new file mode 100644
index 0000000000..f0c53b5271
--- /dev/null
+++ b/bsp/at91sam9g45/platform/gpio.h
@@ -0,0 +1,208 @@
+/*
+ * File      : gpio.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety       first version
+ */
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+#include <rtthread.h>
+
+#define PIN_BASE		AIC_IRQS
+
+#define MAX_GPIO_BANKS		5
+
+#define PIN_IRQS	(MAX_GPIO_BANKS*32)
+
+/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
+
+#define	AT91C_PIN_PA0	(PIN_BASE + 0x00 + 0)
+#define	AT91C_PIN_PA1	(PIN_BASE + 0x00 + 1)
+#define	AT91C_PIN_PA2	(PIN_BASE + 0x00 + 2)
+#define	AT91C_PIN_PA3	(PIN_BASE + 0x00 + 3)
+#define	AT91C_PIN_PA4	(PIN_BASE + 0x00 + 4)
+#define	AT91C_PIN_PA5	(PIN_BASE + 0x00 + 5)
+#define	AT91C_PIN_PA6	(PIN_BASE + 0x00 + 6)
+#define	AT91C_PIN_PA7	(PIN_BASE + 0x00 + 7)
+#define	AT91C_PIN_PA8	(PIN_BASE + 0x00 + 8)
+#define	AT91C_PIN_PA9	(PIN_BASE + 0x00 + 9)
+#define	AT91C_PIN_PA10	(PIN_BASE + 0x00 + 10)
+#define	AT91C_PIN_PA11	(PIN_BASE + 0x00 + 11)
+#define	AT91C_PIN_PA12	(PIN_BASE + 0x00 + 12)
+#define	AT91C_PIN_PA13	(PIN_BASE + 0x00 + 13)
+#define	AT91C_PIN_PA14	(PIN_BASE + 0x00 + 14)
+#define	AT91C_PIN_PA15	(PIN_BASE + 0x00 + 15)
+#define	AT91C_PIN_PA16	(PIN_BASE + 0x00 + 16)
+#define	AT91C_PIN_PA17	(PIN_BASE + 0x00 + 17)
+#define	AT91C_PIN_PA18	(PIN_BASE + 0x00 + 18)
+#define	AT91C_PIN_PA19	(PIN_BASE + 0x00 + 19)
+#define	AT91C_PIN_PA20	(PIN_BASE + 0x00 + 20)
+#define	AT91C_PIN_PA21	(PIN_BASE + 0x00 + 21)
+#define	AT91C_PIN_PA22	(PIN_BASE + 0x00 + 22)
+#define	AT91C_PIN_PA23	(PIN_BASE + 0x00 + 23)
+#define	AT91C_PIN_PA24	(PIN_BASE + 0x00 + 24)
+#define	AT91C_PIN_PA25	(PIN_BASE + 0x00 + 25)
+#define	AT91C_PIN_PA26	(PIN_BASE + 0x00 + 26)
+#define	AT91C_PIN_PA27	(PIN_BASE + 0x00 + 27)
+#define	AT91C_PIN_PA28	(PIN_BASE + 0x00 + 28)
+#define	AT91C_PIN_PA29	(PIN_BASE + 0x00 + 29)
+#define	AT91C_PIN_PA30	(PIN_BASE + 0x00 + 30)
+#define	AT91C_PIN_PA31	(PIN_BASE + 0x00 + 31)
+
+#define	AT91C_PIN_PB0	(PIN_BASE + 0x20 + 0)
+#define	AT91C_PIN_PB1	(PIN_BASE + 0x20 + 1)
+#define	AT91C_PIN_PB2	(PIN_BASE + 0x20 + 2)
+#define	AT91C_PIN_PB3	(PIN_BASE + 0x20 + 3)
+#define	AT91C_PIN_PB4	(PIN_BASE + 0x20 + 4)
+#define	AT91C_PIN_PB5	(PIN_BASE + 0x20 + 5)
+#define	AT91C_PIN_PB6	(PIN_BASE + 0x20 + 6)
+#define	AT91C_PIN_PB7	(PIN_BASE + 0x20 + 7)
+#define	AT91C_PIN_PB8	(PIN_BASE + 0x20 + 8)
+#define	AT91C_PIN_PB9	(PIN_BASE + 0x20 + 9)
+#define	AT91C_PIN_PB10	(PIN_BASE + 0x20 + 10)
+#define	AT91C_PIN_PB11	(PIN_BASE + 0x20 + 11)
+#define	AT91C_PIN_PB12	(PIN_BASE + 0x20 + 12)
+#define	AT91C_PIN_PB13	(PIN_BASE + 0x20 + 13)
+#define	AT91C_PIN_PB14	(PIN_BASE + 0x20 + 14)
+#define	AT91C_PIN_PB15	(PIN_BASE + 0x20 + 15)
+#define	AT91C_PIN_PB16	(PIN_BASE + 0x20 + 16)
+#define	AT91C_PIN_PB17	(PIN_BASE + 0x20 + 17)
+#define	AT91C_PIN_PB18	(PIN_BASE + 0x20 + 18)
+#define	AT91C_PIN_PB19	(PIN_BASE + 0x20 + 19)
+#define	AT91C_PIN_PB20	(PIN_BASE + 0x20 + 20)
+#define	AT91C_PIN_PB21	(PIN_BASE + 0x20 + 21)
+#define	AT91C_PIN_PB22	(PIN_BASE + 0x20 + 22)
+#define	AT91C_PIN_PB23	(PIN_BASE + 0x20 + 23)
+#define	AT91C_PIN_PB24	(PIN_BASE + 0x20 + 24)
+#define	AT91C_PIN_PB25	(PIN_BASE + 0x20 + 25)
+#define	AT91C_PIN_PB26	(PIN_BASE + 0x20 + 26)
+#define	AT91C_PIN_PB27	(PIN_BASE + 0x20 + 27)
+#define	AT91C_PIN_PB28	(PIN_BASE + 0x20 + 28)
+#define	AT91C_PIN_PB29	(PIN_BASE + 0x20 + 29)
+#define	AT91C_PIN_PB30	(PIN_BASE + 0x20 + 30)
+#define	AT91C_PIN_PB31	(PIN_BASE + 0x20 + 31)
+
+#define	AT91C_PIN_PC0	(PIN_BASE + 0x40 + 0)
+#define	AT91C_PIN_PC1	(PIN_BASE + 0x40 + 1)
+#define	AT91C_PIN_PC2	(PIN_BASE + 0x40 + 2)
+#define	AT91C_PIN_PC3	(PIN_BASE + 0x40 + 3)
+#define	AT91C_PIN_PC4	(PIN_BASE + 0x40 + 4)
+#define	AT91C_PIN_PC5	(PIN_BASE + 0x40 + 5)
+#define	AT91C_PIN_PC6	(PIN_BASE + 0x40 + 6)
+#define	AT91C_PIN_PC7	(PIN_BASE + 0x40 + 7)
+#define	AT91C_PIN_PC8	(PIN_BASE + 0x40 + 8)
+#define	AT91C_PIN_PC9	(PIN_BASE + 0x40 + 9)
+#define	AT91C_PIN_PC10	(PIN_BASE + 0x40 + 10)
+#define	AT91C_PIN_PC11	(PIN_BASE + 0x40 + 11)
+#define	AT91C_PIN_PC12	(PIN_BASE + 0x40 + 12)
+#define	AT91C_PIN_PC13	(PIN_BASE + 0x40 + 13)
+#define	AT91C_PIN_PC14	(PIN_BASE + 0x40 + 14)
+#define	AT91C_PIN_PC15	(PIN_BASE + 0x40 + 15)
+#define	AT91C_PIN_PC16	(PIN_BASE + 0x40 + 16)
+#define	AT91C_PIN_PC17	(PIN_BASE + 0x40 + 17)
+#define	AT91C_PIN_PC18	(PIN_BASE + 0x40 + 18)
+#define	AT91C_PIN_PC19	(PIN_BASE + 0x40 + 19)
+#define	AT91C_PIN_PC20	(PIN_BASE + 0x40 + 20)
+#define	AT91C_PIN_PC21	(PIN_BASE + 0x40 + 21)
+#define	AT91C_PIN_PC22	(PIN_BASE + 0x40 + 22)
+#define	AT91C_PIN_PC23	(PIN_BASE + 0x40 + 23)
+#define	AT91C_PIN_PC24	(PIN_BASE + 0x40 + 24)
+#define	AT91C_PIN_PC25	(PIN_BASE + 0x40 + 25)
+#define	AT91C_PIN_PC26	(PIN_BASE + 0x40 + 26)
+#define	AT91C_PIN_PC27	(PIN_BASE + 0x40 + 27)
+#define	AT91C_PIN_PC28	(PIN_BASE + 0x40 + 28)
+#define	AT91C_PIN_PC29	(PIN_BASE + 0x40 + 29)
+#define	AT91C_PIN_PC30	(PIN_BASE + 0x40 + 30)
+#define	AT91C_PIN_PC31	(PIN_BASE + 0x40 + 31)
+
+#define	AT91C_PIN_PD0	(PIN_BASE + 0x60 + 0)
+#define	AT91C_PIN_PD1	(PIN_BASE + 0x60 + 1)
+#define	AT91C_PIN_PD2	(PIN_BASE + 0x60 + 2)
+#define	AT91C_PIN_PD3	(PIN_BASE + 0x60 + 3)
+#define	AT91C_PIN_PD4	(PIN_BASE + 0x60 + 4)
+#define	AT91C_PIN_PD5	(PIN_BASE + 0x60 + 5)
+#define	AT91C_PIN_PD6	(PIN_BASE + 0x60 + 6)
+#define	AT91C_PIN_PD7	(PIN_BASE + 0x60 + 7)
+#define	AT91C_PIN_PD8	(PIN_BASE + 0x60 + 8)
+#define	AT91C_PIN_PD9	(PIN_BASE + 0x60 + 9)
+#define	AT91C_PIN_PD10	(PIN_BASE + 0x60 + 10)
+#define	AT91C_PIN_PD11	(PIN_BASE + 0x60 + 11)
+#define	AT91C_PIN_PD12	(PIN_BASE + 0x60 + 12)
+#define	AT91C_PIN_PD13	(PIN_BASE + 0x60 + 13)
+#define	AT91C_PIN_PD14	(PIN_BASE + 0x60 + 14)
+#define	AT91C_PIN_PD15	(PIN_BASE + 0x60 + 15)
+#define	AT91C_PIN_PD16	(PIN_BASE + 0x60 + 16)
+#define	AT91C_PIN_PD17	(PIN_BASE + 0x60 + 17)
+#define	AT91C_PIN_PD18	(PIN_BASE + 0x60 + 18)
+#define	AT91C_PIN_PD19	(PIN_BASE + 0x60 + 19)
+#define	AT91C_PIN_PD20	(PIN_BASE + 0x60 + 20)
+#define	AT91C_PIN_PD21	(PIN_BASE + 0x60 + 21)
+#define	AT91C_PIN_PD22	(PIN_BASE + 0x60 + 22)
+#define	AT91C_PIN_PD23	(PIN_BASE + 0x60 + 23)
+#define	AT91C_PIN_PD24	(PIN_BASE + 0x60 + 24)
+#define	AT91C_PIN_PD25	(PIN_BASE + 0x60 + 25)
+#define	AT91C_PIN_PD26	(PIN_BASE + 0x60 + 26)
+#define	AT91C_PIN_PD27	(PIN_BASE + 0x60 + 27)
+#define	AT91C_PIN_PD28	(PIN_BASE + 0x60 + 28)
+#define	AT91C_PIN_PD29	(PIN_BASE + 0x60 + 29)
+#define	AT91C_PIN_PD30	(PIN_BASE + 0x60 + 30)
+#define	AT91C_PIN_PD31	(PIN_BASE + 0x60 + 31)
+
+#define	AT91C_PIN_PE0	(PIN_BASE + 0x80 + 0)
+#define	AT91C_PIN_PE1	(PIN_BASE + 0x80 + 1)
+#define	AT91C_PIN_PE2	(PIN_BASE + 0x80 + 2)
+#define	AT91C_PIN_PE3	(PIN_BASE + 0x80 + 3)
+#define	AT91C_PIN_PE4	(PIN_BASE + 0x80 + 4)
+#define	AT91C_PIN_PE5	(PIN_BASE + 0x80 + 5)
+#define	AT91C_PIN_PE6	(PIN_BASE + 0x80 + 6)
+#define	AT91C_PIN_PE7	(PIN_BASE + 0x80 + 7)
+#define	AT91C_PIN_PE8	(PIN_BASE + 0x80 + 8)
+#define	AT91C_PIN_PE9	(PIN_BASE + 0x80 + 9)
+#define	AT91C_PIN_PE10	(PIN_BASE + 0x80 + 10)
+#define	AT91C_PIN_PE11	(PIN_BASE + 0x80 + 11)
+#define	AT91C_PIN_PE12	(PIN_BASE + 0x80 + 12)
+#define	AT91C_PIN_PE13	(PIN_BASE + 0x80 + 13)
+#define	AT91C_PIN_PE14	(PIN_BASE + 0x80 + 14)
+#define	AT91C_PIN_PE15	(PIN_BASE + 0x80 + 15)
+#define	AT91C_PIN_PE16	(PIN_BASE + 0x80 + 16)
+#define	AT91C_PIN_PE17	(PIN_BASE + 0x80 + 17)
+#define	AT91C_PIN_PE18	(PIN_BASE + 0x80 + 18)
+#define	AT91C_PIN_PE19	(PIN_BASE + 0x80 + 19)
+#define	AT91C_PIN_PE20	(PIN_BASE + 0x80 + 20)
+#define	AT91C_PIN_PE21	(PIN_BASE + 0x80 + 21)
+#define	AT91C_PIN_PE22	(PIN_BASE + 0x80 + 22)
+#define	AT91C_PIN_PE23	(PIN_BASE + 0x80 + 23)
+#define	AT91C_PIN_PE24	(PIN_BASE + 0x80 + 24)
+#define	AT91C_PIN_PE25	(PIN_BASE + 0x80 + 25)
+#define	AT91C_PIN_PE26	(PIN_BASE + 0x80 + 26)
+#define	AT91C_PIN_PE27	(PIN_BASE + 0x80 + 27)
+#define	AT91C_PIN_PE28	(PIN_BASE + 0x80 + 28)
+#define	AT91C_PIN_PE29	(PIN_BASE + 0x80 + 29)
+#define	AT91C_PIN_PE30	(PIN_BASE + 0x80 + 30)
+#define	AT91C_PIN_PE31	(PIN_BASE + 0x80 + 31)
+
+rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
+{
+	return gpio;
+}
+
+#endif
diff --git a/bsp/at91sam9g45/platform/interrupt.c b/bsp/at91sam9g45/platform/interrupt.c
new file mode 100644
index 0000000000..b19bcb3bde
--- /dev/null
+++ b/bsp/at91sam9g45/platform/interrupt.c
@@ -0,0 +1,453 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      first version
+ */
+
+#include <rthw.h>
+#include "at91sam9g45.h"
+#include "interrupt.h"
+
+#define AIC_IRQS	32
+#define MAX_HANDLERS    (AIC_IRQS + PIN_IRQS)
+
+extern rt_uint32_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+rt_uint32_t at91_extern_irq;
+
+#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
+
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static rt_uint32_t at91sam9g45_default_irq_priority[MAX_HANDLERS] = {
+    7,  /* Advanced Interrupt Controller - FIQ    */
+    7,  /* System Controller Interrupt            */
+    1,  /* Parallel I/O Controller A,             */
+    1,  /* Parallel I/O Controller B              */
+    1,  /* Parallel I/O Controller C              */
+    0,  /* Parallel I/O Controller D/E            */
+    5,  /* True Random Number Generator           */
+    5,  /* USART 0                                */
+    5,  /* USART 1                                */
+    0,  /* USART 2                                */
+    2,  /* USART 3                                */
+    6,  /* High Speed Multimedia Card Interface 0 */
+    5,  /* Two-Wire Interface 0                   */
+    5,  /* Two-Wire Interface 1                   */
+    5,  /* Serial Peripheral Interface            */
+    0,  /* Serial Peripheral Interface            */
+    0,  /* Synchronous Serial Controller 0        */
+    0,  /* Synchronous Serial Controller 1        */
+    0,  /* Timer Counter 0,1,2,3,4,5              */
+    0,  /* Pulse Width Modulation Controller      */
+    2,  /* Touch Screen ADC Controller            */
+    3,  /* DMA Controller                         */
+    0,  /* USB Host High Speed                    */
+    5,  /* LCD Controller                         */
+    5,  /* AC97 Controller                        */
+    5,  /* Ethernet MAC                           */
+    0,  /* Image Sensor Interface                 */
+    0,  /* USB Device High Speed                  */
+    0,  /* N/A                                    */
+    0,  /* High Speed Multimedia Card Interface 1 */
+    0,  /* Reserved                               */
+    0,  /* Advanced Interrupt Controller - IRQ    */
+};
+
+/**
+ * @addtogroup AT91SAM9G45
+ */
+/*@{*/
+
+void rt_hw_interrupt_mask(int irq);
+void rt_hw_interrupt_umask(int irq);
+
+rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    return RT_NULL;
+}
+
+rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param)
+{
+    rt_uint32_t isr, irq_n;
+	AT91PS_PIO pio;
+    void *parameter;
+
+    switch (bank)
+    {
+	case 0: pio = AT91C_BASE_PIOA; break;
+	case 1: pio = AT91C_BASE_PIOB; break;
+	case 2: pio = AT91C_BASE_PIOC; break;
+	case 3: pio = AT91C_BASE_PIOD; break;
+	case 4: pio = AT91C_BASE_PIOE; break;
+	default: return RT_NULL;
+    }
+    irq_n = AIC_IRQS + 32*bank;
+    isr = readl(pio->PIO_ISR);
+    isr &= readl(pio->PIO_IMR);
+    while (isr)
+    {
+        if (isr & 1)
+        {
+            parameter = irq_desc[irq_n].param;
+            irq_desc[irq_n].handler(irq_n, parameter);
+        }
+        isr >>= 1;
+        irq_n++;
+    }
+
+    return RT_NULL;
+}
+
+unsigned int SpuriousCount = 0;
+static void DefaultSpuriousHandler( void )
+{
+	SpuriousCount++;
+	rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount);
+	return ;
+}
+
+static void DefaultFiqHandler(void)
+{
+	rt_kprintf("Unhandled FIQ occured!!!\n");
+	while (1);
+}
+
+static void DefaultIrqHandler(void)
+{
+	rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR);
+	while (1);
+}
+
+/*
+ * Initialize the AIC interrupt controller.
+ */
+void at91_aic_init(rt_uint32_t *priority)
+{
+    rt_uint32_t i;
+
+    /*
+     * The IVR is used by macro get_irqnr_and_base to read and verify.
+     * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
+     */
+    AT91C_BASE_AIC->AIC_SVR[0] = (rt_uint32_t)DefaultFiqHandler;
+    for (i = 1; i < AIC_IRQS; i++) {
+        /* Put irq number in Source Vector Register: */
+        AT91C_BASE_AIC->AIC_SVR[i] = (rt_uint32_t)DefaultIrqHandler; // no-used
+        /* Active Low interrupt, with the specified priority */
+        AT91C_BASE_AIC->AIC_SMR[i] = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | priority[i];
+        //AT91C_AIC_SRCTYPE_FALLING
+    }
+
+    /*
+     * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
+     * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
+     */
+    AT91C_BASE_AIC->AIC_SPU = (rt_uint32_t)DefaultSpuriousHandler;
+
+    /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
+    for (i = 0; i < 8; i++)
+        AT91C_BASE_AIC->AIC_EOICR = 0;
+
+    /* No debugging in AIC: Debug (Protect) Control Register */
+    AT91C_BASE_AIC->AIC_DCR = 0;
+
+    /* Disable and clear all interrupts initially */
+    AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
+    AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
+}
+
+
+static void at91_gpio_irq_init()
+{
+    int i, idx;
+    char *name[] = {"PIOA", "PIOB", "PIOC", "PIODE"};
+    rt_uint32_t aic_pids[] = { AT91C_ID_PIOA, AT91C_ID_PIOB, AT91C_ID_PIOC, AT91C_ID_PIOD_E };
+
+    AT91C_BASE_PIOA->PIO_IDR = 0xffffffff;
+    AT91C_BASE_PIOB->PIO_IDR = 0xffffffff;
+    AT91C_BASE_PIOC->PIO_IDR = 0xffffffff;
+    AT91C_BASE_PIOD->PIO_IDR = 0xffffffff;
+    AT91C_BASE_PIOE->PIO_IDR = 0xffffffff;
+
+    for (i = 0; i < 4; i++)
+    {
+        idx = aic_pids[i];
+        irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle;
+        irq_desc[idx].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
+        irq_desc[idx].counter = 0;
+#endif
+
+        rt_hw_interrupt_umask(idx);
+    }
+}
+
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    register rt_uint32_t idx;
+    rt_uint32_t *priority = at91sam9g45_default_irq_priority;
+
+    at91_extern_irq = (1UL << AT91C_ID_IRQ0);
+
+    /* Initialize the AIC interrupt controller */
+    at91_aic_init(priority);
+
+    /* init exceptions table */
+    for(idx=0; idx < MAX_HANDLERS; idx++)
+    {
+        irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+        irq_desc[idx].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx].counter = 0;
+#endif
+    }
+
+    at91_gpio_irq_init();
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+static void at91_gpio_irq_mask(int irq)
+{
+    rt_uint32_t pin, bank;
+    AT91PS_PIO pio;
+
+    bank = (irq - AIC_IRQS)>>5;
+
+    switch (bank)
+    {
+    case 0: pio = AT91C_BASE_PIOA; break;
+    case 1: pio = AT91C_BASE_PIOB; break;
+    case 2: pio = AT91C_BASE_PIOC; break;
+    case 3: pio = AT91C_BASE_PIOD; break;
+    case 4: pio = AT91C_BASE_PIOE; break;
+    default: return;
+    }
+    pin = 1 << ((irq - AIC_IRQS) & 31);
+    pio->PIO_IDR = pin;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param irq   the interrupt number
+ */
+void rt_hw_interrupt_mask(int irq)
+{
+    if (irq >= AIC_IRQS)
+    {
+        at91_gpio_irq_mask(irq);
+    }
+    else
+    {
+        /* Disable interrupt on AIC */
+        AT91C_BASE_AIC->AIC_IDCR = 1 << irq;
+    }
+}
+
+static void at91_gpio_irq_umask(int irq)
+{
+    rt_uint32_t pin, bank;
+    AT91PS_PIO pio;
+
+    bank = (irq - AIC_IRQS)>>5;
+
+    switch (bank)
+    {
+    case 0: pio = AT91C_BASE_PIOA; break;
+    case 1: pio = AT91C_BASE_PIOB; break;
+    case 2: pio = AT91C_BASE_PIOC; break;
+    case 3: pio = AT91C_BASE_PIOD; break;
+    case 4: pio = AT91C_BASE_PIOE; break;
+    default: return;
+    }
+    pin = 1 << ((irq - AIC_IRQS) & 31);
+    pio->PIO_IER = pin;
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int irq)
+{
+    if (irq >= AIC_IRQS)
+    {
+        at91_gpio_irq_umask(irq);
+    }
+    else
+    {
+        /* Enable interrupt on AIC */
+        AT91C_BASE_AIC->AIC_IECR = 1 << irq;
+    }
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param handler the interrupt service routine to be installed
+ * @param param the interrupt service function parameter
+ * @param name the interrupt name
+ * @return old handler
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                    void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[vector].param = param;
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
+			irq_desc[vector].counter = 0;
+#endif
+        }
+    }
+
+    return old_handler;
+}
+
+/*@}*/
+
+/*
+static int at91_aic_set_type(unsigned irq, unsigned type)
+{
+    unsigned int smr, srctype;
+
+    switch (type) {
+    case AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL:
+        srctype = AT91C_AIC_SRCTYPE_HIGH;
+        break;
+    case AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE:
+        srctype = AT91C_AIC_SRCTYPE_RISING;
+        break;
+    case AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE:
+        // only supported on external interrupts
+        if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq))
+            srctype = AT91C_AIC_SRCTYPE_LOW;
+        else
+            return -1;
+        break;
+    case AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED:
+        // only supported on external interrupts
+        if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq))
+            srctype = AT91C_AIC_SRCTYPE_FALLING;
+        else
+            return -1;
+        break;
+    default:
+        return -1;
+    }
+
+    smr = readl(AT91C_AIC_SMR(irq)) & ~AT91C_AIC_SRCTYPE;
+    AT91C_BASE_AIC->AIC_SMR[irq] = smr | srctype;
+    return 0;
+}
+*/
+rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
+{
+
+    //volatile rt_uint32_t irqstat;
+    rt_uint32_t id;
+    if (fiq_irq == INT_FIQ)
+        return 0;
+
+    //IRQ
+    /* AIC need this dummy read */
+    readl(AT91C_AIC_IVR);
+    /* clear pending register */
+    id = readl(AT91C_AIC_ISR);
+
+    return id;
+}
+
+void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
+{
+    /* new FIQ generation */
+    if (fiq_irq == INT_FIQ)
+        return;
+
+    /* new IRQ generation */
+    // EIOCR must be write any value after interrupt,
+    // or else can't response next interrupt
+    AT91C_BASE_AIC->AIC_EOICR = 0x0;
+}
+
+#ifdef RT_USING_FINSH
+#ifdef RT_USING_INTERRUPT_INFO
+void list_irq(void)
+{
+	int irq;
+
+	rt_kprintf("number\tcount\tname\n");
+	for (irq = 0; irq < MAX_HANDLERS; irq++)
+	{
+		if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
+		{
+			rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
+		}
+	}
+}
+
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT(list_irq, list system irq);
+
+#ifdef FINSH_USING_MSH
+int cmd_list_irq(int argc, char** argv)
+{
+    list_irq();
+    return 0;
+}
+FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
+
+#endif
+#endif
+#endif
+
+
diff --git a/bsp/at91sam9g45/platform/interrupt.h b/bsp/at91sam9g45/platform/interrupt.h
new file mode 100644
index 0000000000..7780e7a3a8
--- /dev/null
+++ b/bsp/at91sam9g45/platform/interrupt.h
@@ -0,0 +1,31 @@
+/*
+ * File      : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+
+#endif
diff --git a/bsp/at91sam9g45/platform/io.h b/bsp/at91sam9g45/platform/io.h
new file mode 100644
index 0000000000..80919c52cb
--- /dev/null
+++ b/bsp/at91sam9g45/platform/io.h
@@ -0,0 +1,39 @@
+/*
+ * File      : io.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      first version
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT		0xFFFFFFFF
+
+#define readb(a)	(*(volatile unsigned char  *)(a))
+#define readw(a)	(*(volatile unsigned short *)(a))
+#define readl(a)	(*(volatile unsigned int   *)(a))
+
+#define writeb(v,a)	(*(volatile unsigned char  *)(a) = (v))
+#define writew(v,a)	(*(volatile unsigned short *)(a) = (v))
+#define writel(v,a)	(*(volatile unsigned int   *)(a) = (v))
+
+#endif
+
diff --git a/bsp/at91sam9g45/platform/irq.h b/bsp/at91sam9g45/platform/irq.h
new file mode 100644
index 0000000000..fe1fea41d0
--- /dev/null
+++ b/bsp/at91sam9g45/platform/irq.h
@@ -0,0 +1,52 @@
+/*
+ * File      : irq.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      first version
+ */
+ 
+#ifndef __IRQ_H__
+#define __IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * IRQ line status.
+ *
+ * Bits 0-7 are reserved 
+ *
+ * IRQ types
+ */
+#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
+#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
+#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
+#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
+#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
+#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at91sam9g45/platform/reset.c b/bsp/at91sam9g45/platform/reset.c
new file mode 100644
index 0000000000..2e7bec1e5d
--- /dev/null
+++ b/bsp/at91sam9g45/platform/reset.c
@@ -0,0 +1,68 @@
+/*
+ * File      : reset.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      modified from mini2440
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "at91sam9g45.h"
+
+/**
+ * @addtogroup AT91SAM926X
+ */
+/*@{*/
+
+void machine_reset(void)
+{
+	AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST;
+}
+
+void machine_shutdown(void)
+{
+	AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW;
+}
+
+#ifdef RT_USING_FINSH
+
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
+
+#ifdef FINSH_USING_MSH
+int cmd_reset(int argc, char** argv)
+{
+	rt_hw_cpu_reset();
+	return 0;
+}
+
+int cmd_shutdown(int argc, char** argv)
+{
+	rt_hw_cpu_shutdown();
+	return 0;
+}
+
+FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
+FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.);
+
+#endif
+#endif
+
+/*@}*/
diff --git a/bsp/at91sam9g45/platform/rt_low_level_init.c b/bsp/at91sam9g45/platform/rt_low_level_init.c
new file mode 100644
index 0000000000..5df468d771
--- /dev/null
+++ b/bsp/at91sam9g45/platform/rt_low_level_init.c
@@ -0,0 +1,63 @@
+/*
+ * File      : rt_low_level_init.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-04-14     ArdaFu      first version
+ */
+ 
+/* write register a=address, v=value */
+#define write_reg(a,v)	    (*(volatile unsigned int *)(a) = (v))
+/* Processor Reset */
+#define AT91C_RSTC_PROCRST   (1 << 0)
+#define AT91C_RSTC_PERRST    (1 << 2)
+#define AT91C_RSTC_KEY       (0xa5 << 24)
+#define AT91C_MATRIX_BASE    (0XFFFFEE00)
+/* Master Remap Control Register */
+#define AT91C_MATRIX_MRCR    (AT91C_MATRIX_BASE + 0x100)
+/* Remap Command for AHB Master 0 (ARM926EJ-S InSTRuction Master) */
+#define AT91C_MATRIX_RCB0    (1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91C_MATRIX_RCB1    (1 << 1)
+
+#define AT91C_AIC_BASE       (0XFFFFF000)
+/* Interrupt DisaBLe Command Register */
+#define AT91C_AIC_IDCR       (AT91C_AIC_BASE + 0x124)
+/* Interrupt Clear Command Register */
+#define AT91C_AIC_ICCR       (AT91C_AIC_BASE + 0x128)
+
+#define AT91C_WDT_BASE       (0XFFFFFD40)
+#define AT91C_WDT_CR         (AT91C_WDT_BASE + 0x00)
+#define AT91C_WDT_CR_KEY     (0xA5000000)
+#define AT91C_WDT_CR_WDRSTT  (0x00000001)
+#define AT91C_WDT_MR         (AT91C_WDT_BASE + 0x04)
+#define AT91C_WDT_MR_WDDIS   (0x00008000)
+
+void rt_low_level_init(void)
+{
+    // Mask all IRQs by clearing all bits in the INTMRS
+    write_reg(AT91C_AIC_IDCR, 0xFFFFFFFF);
+    write_reg(AT91C_AIC_ICCR, 0xFFFFFFFF);
+    // Remap internal ram to 0x00000000 Address
+    write_reg(AT91C_MATRIX_MRCR, AT91C_MATRIX_RCB0 | AT91C_MATRIX_RCB1);
+    // Disable the watchdog
+    //write_reg(AT91C_WDT_CR, AT91C_WDT_CR_KEY|AT91C_WDT_CR_WDRSTT);
+    //write_reg(AT91C_WDT_MR, AT91C_WDT_MR_WDDIS);
+}
+
diff --git a/bsp/at91sam9g45/platform/rt_low_level_init.h b/bsp/at91sam9g45/platform/rt_low_level_init.h
new file mode 100644
index 0000000000..86dcfb59dc
--- /dev/null
+++ b/bsp/at91sam9g45/platform/rt_low_level_init.h
@@ -0,0 +1,35 @@
+/*
+ * File      : rt_low_level_init.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-06-04     ArdaFu      first version
+ */
+#ifndef __RT_LOW_LEVEL_INIT_H__
+#define __RT_LOW_LEVEL_INIT_H__
+ 
+/*-------- Stack size of CPU modes -------------------------------------------*/
+#define UND_STK_SIZE 512
+#define SVC_STK_SIZE 4096
+#define ABT_STK_SIZE 512
+#define IRQ_STK_SIZE 1024
+#define FIQ_STK_SIZE 1024
+#define SYS_STK_SIZE 512
+#define Heap_Size    512
+#endif
diff --git a/bsp/at91sam9g45/platform/system_clock.c b/bsp/at91sam9g45/platform/system_clock.c
new file mode 100644
index 0000000000..59c3c320ab
--- /dev/null
+++ b/bsp/at91sam9g45/platform/system_clock.c
@@ -0,0 +1,270 @@
+/*
+ * File      : clock.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety       first version
+ */
+
+#include <rtthread.h>
+#include "at91sam9g45.h"
+
+static rt_list_t clocks;
+
+struct clk {
+	char name[32];
+	rt_uint32_t rate_hz;
+	struct clk *parent;
+	rt_list_t  node;
+};
+
+static struct clk clk32k = {
+	"clk32k",
+	AT91C_SLOW_CLOCK,
+	RT_NULL,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk main_clk = {
+	"main",
+	0,
+	RT_NULL,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk plla = {
+	"plla",
+	0,
+	&main_clk,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk mck = {
+	"mck",
+	0,
+	NULL,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk upllck = {
+	"upllck",
+	480*1000*1000,
+	&main_clk,
+	{RT_NULL, RT_NULL},
+};
+
+static struct clk *const standard_pmc_clocks[] = {
+	/* four primary clocks */
+	&clk32k,
+	&main_clk,
+	&plla,
+
+	/* MCK */
+	&mck
+};
+
+/* clocks cannot be de-registered no refcounting necessary */
+struct clk *clk_get(const char *id)
+{
+	struct clk *clk;
+	rt_list_t *list;
+	
+	for (list = (&clocks)->next; list != &clocks; list = list->next)
+	{
+		clk = (struct clk *)rt_list_entry(list, struct clk, node);
+		if (rt_strcmp(id, clk->name) == 0)
+			return clk;
+	}
+
+	return RT_NULL;
+}
+
+rt_uint32_t clk_get_rate(struct clk *clk)
+{
+	rt_uint32_t	rate;
+
+	for (;;) {
+		rate = clk->rate_hz;
+		if (rate || !clk->parent)
+			break;
+		clk = clk->parent;
+	}
+	return rate;
+}
+
+static void at91_upllck_init(rt_uint32_t main_clock)
+{
+	// EHCI USB use fixed 480MHz clock
+}
+
+static struct clk *at91_css_to_clk(unsigned long css)
+{
+	switch (css) {
+		case AT91C_PMC_CSS_SLOW_CLK:
+			return &clk32k;
+		case AT91C_PMC_CSS_MAIN_CLK:
+			return &main_clk;
+		case AT91C_PMC_CSS_PLLA_CLK:
+			return &plla;
+		case AT91C_PMC_CSS_UPLL_CLK:
+			return &upllck;
+	}
+
+	return RT_NULL;
+}
+
+// TODO: how to auto-set register value by OSC and MCK
+/* Settings at 400/133MHz */
+// In datasheet, ATMEL says 12MHz main crystal startup time less than 2ms, so we
+// configure OSC startup timeout to 64*8/32768=15.6ms, should enough
+#define BOARD_OSCOUNT			(AT91C_CKGR_OSCOUNT & (64 << 8))
+// MAINCK => Divider(DIVA) => PLLA(MULA, OUTA) => /1/2 Divider(PLLADIV2) => PLLACK
+// pls. refer to doc6438G figure 24-6 on pg294.		ICPLLA in reg PMC_PLLICPR
+// 12MHz / 3 * (199 + 1) = 800MHz
+// OUTA/ICPLLA can as ICPLLA:OUTA[1]:OUTA[0] = (800-PLLAOUT(MHz))/50
+// PLLACOUNT field occupy bit[13:8], max value is 0x3F, then about 19.2ms
+#define BOARD_CKGR_PLLA			(AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0)
+#define BOARD_PLLACOUNT			(0x3F << 8)
+#define BOARD_MULA				(AT91C_CKGR_MULA & (199 << 16))
+#define BOARD_DIVA				(AT91C_CKGR_DIVA & 3)
+// Clock Source => select(CCS) => Prescaler(PRES) => Master Clock Divider(MDIV) => MCK
+//                                                => Processor Clock Divider => PCK
+// Master clock can refer to doc6438G figure 25-2 on pg298
+// PLLADIV2=1(div 2, 400MHz), PRES=0(no div, 400MHz),
+// MDIV=3(Master Clock divided by 3, 133MHz), CSS=0(still Slow Clock)
+#define BOARD_PRESCALER			(0x00001300) //400/133MHz
+
+#define MHz(n)		((n) * 1000 * 1000)
+#define OSC_FREQ	MHz(12)
+#define PLLA_FREQ	MHz(800)
+
+static void at91_plla_init(void)
+{
+	rt_uint32_t pllar, mckr;
+
+	// Code refer to doc6438G, 25.10 Programming Sequence
+	/* Initialize main oscillator
+	 ****************************/
+	// enable main OSC and wait OSC startup time timeout.
+	AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
+	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
+
+	/* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */
+	pllar = (MHz(800) - PLLA_FREQ) / MHz(50);		// please refer to Table 46-15 of doc 6438G
+	AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1;	// ICPLLA
+	pllar = (pllar & 3) << 14;	// OUTA
+	pllar |= BOARD_DIVA;		// PLLA input clock as 4MHz
+	pllar |= BOARD_MULA;		// PLLA output clock as 800MHz
+	pllar |= BOARD_PLLACOUNT;
+	pllar |= AT91C_CKGR_SRCA;	// I don't known what means, but seems must set it
+	AT91C_BASE_PMC->PMC_PLLAR = pllar;
+
+	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
+
+	/* Wait for the master clock if it was already initialized */
+	// make sure Master clock in READY status before operate it
+	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+	/* Switch to fast clock
+	 **********************/
+	/* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */
+	mckr = AT91C_BASE_PMC->PMC_MCKR;
+	if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV))
+	{
+		mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV);
+		AT91C_BASE_PMC->PMC_MCKR = mckr;
+		while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+	}
+
+	/* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */
+	if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK)
+	{
+		mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK;
+		AT91C_BASE_PMC->PMC_MCKR = mckr;
+		while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+	}
+
+	plla.rate_hz = PLLA_FREQ;
+}
+    
+#define false 0
+#define true  1
+int at91_clock_init(rt_uint32_t main_clock)
+{
+	unsigned tmp, freq, mckr, mdiv;
+	int i;
+
+	/*
+	 * When the bootloader initialized the main oscillator correctly,
+	 * there's no problem using the cycle counter.  But if it didn't,
+	 * or when using oscillator bypass mode, we must be told the speed
+	 * of the main clock.
+	 */
+	if (!main_clock) {
+		do {
+			tmp = readl(AT91C_CKGR_MCFR);
+		} while (!(tmp & AT91C_CKGR_MAINRDY));
+		main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16);
+	}
+	main_clk.rate_hz = main_clock;
+
+	at91_plla_init();
+
+	at91_upllck_init(main_clock);
+
+	/*
+	 * MCK and CPU derive from one of those primary clocks.
+	 * For now, assume this parentage won't change.
+	 */
+	mckr = readl(AT91C_PMC_MCKR);
+	mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS);
+	freq = mck.parent->rate_hz;
+	freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2));	/* prescale */
+	mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8);
+	if (mdiv == 8) mdiv = 3;
+	freq /= mdiv;			/* mdiv */
+	if (mckr & AT91C_PMC_PLLADIV2) freq /= 2;	/* plla_div2 */
+	mck.rate_hz = freq;	
+
+	/* Register the PMC's standard clocks */
+	rt_list_init(&clocks);
+	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+		rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+
+	rt_list_insert_after(&clocks, &upllck.node);
+
+	/* MCK and CPU clock are "always on" */
+	//clk_enable(&mck);
+
+	/*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+		freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+		(unsigned) main_clock / 1000000,
+		((unsigned) main_clock % 1000000) / 1000);*///cause blocked
+
+	return 0;
+}
+
+/**
+ * @brief System Clock Configuration
+ */
+void rt_hw_clock_init(void)
+{
+	at91_clock_init(MHz(12));
+}
+
diff --git a/bsp/at91sam9g45/rtconfig.h b/bsp/at91sam9g45/rtconfig.h
new file mode 100644
index 0000000000..5d638ce1c9
--- /dev/null
+++ b/bsp/at91sam9g45/rtconfig.h
@@ -0,0 +1,159 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_IDEL_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_INTERRUPT_INFO
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "dbgu"
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+#define RT_USING_CPLUSPLUS
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_PTHREADS
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* light weight TCP/IP stack */
+
+
+/* Modbus master and slave stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* sample package */
+
+/* samples: kernel and components samples */
+
+
+/* example package: hello */
+
+#define RT_USING_DBGU
+#define RT_USING_LED
+
+#endif
diff --git a/bsp/at91sam9g45/rtconfig.py b/bsp/at91sam9g45/rtconfig.py
new file mode 100644
index 0000000000..3684b54578
--- /dev/null
+++ b/bsp/at91sam9g45/rtconfig.py
@@ -0,0 +1,138 @@
+import os
+ARCH     = 'arm'
+CPU      = 'arm926'
+# toolchains options
+CROSS_TOOL 	= 'gcc'
+
+#------- toolchains path -------------------------------------------------------
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH = r'D:\arm-2013.11\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	EXEC_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+#BUILD = 'debug'
+BUILD = 'release'
+
+CORE = 'arm926ej-s'
+MAP_FILE = 'rtthread_at91sam9g45.map'
+LINK_FILE = 'link_scripts/at91sam9g45_ram'
+TARGET_NAME = 'rtthread.bin'
+
+#------- GCC settings ----------------------------------------------------------
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=arm926ej-s'
+    CFLAGS = DEVICE
+    AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
+    AFLAGS += ' -Iplatform'
+    LFLAGS = DEVICE
+    LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
+    LFLAGS += ' -T ' + LINK_FILE + '.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' 
+    POST_ACTION += SIZE + ' $TARGET\n'
+#------- Keil settings ---------------------------------------------------------
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+    EXEC_PATH += '/arm/armcc/bin/'
+
+    DEVICE = ' --cpu=' + CORE
+    CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870'
+    AFLAGS = DEVICE + ' -Iplatform'
+    LFLAGS = DEVICE + ' --strict'
+    LFLAGS += ' --info sizes --info totals --info unused --info veneers'
+    LFLAGS += ' --list ' + MAP_FILE
+    LFLAGS += ' --scatter  ' + LINK_FILE + '.scat'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n'
+    POST_ACTION += 'fromelf -z $TARGET\n'
+#------- IAR settings ----------------------------------------------------------
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = CORE
+
+    CFLAGS = '--cpu=' + DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=none'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = '--cpu '+ DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --fpu none'
+    AFLAGS += ' -S'
+    AFLAGS += ' -Iplatform'
+    
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = '--config ' + LINK_FILE +'.icf'
+    LFLAGS += ' --entry __iar_program_start'
+    LFLAGS += ' --map ' + MAP_FILE
+    LFLAGS += ' --silent'
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool  --silent --bin $TARGET ' + TARGET_NAME
diff --git a/bsp/at91sam9g45/template.ewp b/bsp/at91sam9g45/template.ewp
new file mode 100644
index 0000000000..5f2fa0e0a9
--- /dev/null
+++ b/bsp/at91sam9g45/template.ewp
@@ -0,0 +1,1914 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>24</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>build\rtthread\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>build\rtthread\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>build\rtthread\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting, without multibyte support.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting, without multibyte support.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>7.40.3.8937</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.40.3.8937</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>AT91SAM9G45	Atmel AT91SAM9G45</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>22</version>
+          <state>12</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>22</version>
+          <state>12</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state>AT91SAM9G45	Atmel AT91SAM9G45</state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>22</version>
+          <state>12</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCDefines</name>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>00000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCNoLiteralPool</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategySlave</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCGuardCalls</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>9</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
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+        <option>
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+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
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+        <option>
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+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state>$PROJ_DIR$\platform</state>
+        </option>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
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+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>3</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>rtthread.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+        <hasPrio>0</hasPrio>
+      </data>
+    </settings>
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+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
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+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+          <state>1</state>
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+          <name>XLinkMisraHandler</name>
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+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOutputFile</name>
+          <state>rtthread.out</state>
+        </option>
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+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
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+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogFile</name>
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+          <name>IlinkLogInitialization</name>
+          <state>0</state>
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+          <name>IlinkLogModule</name>
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+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
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+          <name>IlinkLogVeneer</name>
+          <state>0</state>
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+          <name>IlinkIcfOverride</name>
+          <state>1</state>
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+          <state>$PROJ_DIR$\link_scripts\at91sam9g45_ram.icf</state>
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+          <name>IlinkIcfFileSlave</name>
+          <state></state>
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+          <state>0</state>
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+          <name>IlinkSuppressDiags</name>
+          <state></state>
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+          <name>IlinkTreatAsRem</name>
+          <state></state>
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+          <name>IlinkTreatAsWarn</name>
+          <state></state>
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+          <name>IlinkTreatAsErr</name>
+          <state></state>
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+          <name>IlinkWarningsAreErrors</name>
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+          <state>0</state>
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+          <state></state>
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+          <state>1</state>
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+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
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+          <name>IlinkAdditionalLibs</name>
+          <state></state>
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+          <state>__iar_program_start</state>
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+          <name>CrcInitialValue</name>
+          <state>0x0</state>
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+          <name>DoCrc</name>
+          <state>0</state>
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+          <state>1</state>
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+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+          <state>0</state>
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+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+          <state>0</state>
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+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+          <name>CrcUnitSize</name>
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+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
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+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>IarchiveInputs</name>
+          <state></state>
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+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+    <settings>
+      <name>BILINK</name>
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+          <version>0</version>
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+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+          <name>GFPUCoreSlave2</name>
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+          <state>0</state>
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+          <state>.text</state>
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+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCNoLiteralPool</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategySlave</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCGuardCalls</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>9</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state>$PROJ_DIR$\platform</state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>3</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>c.srec</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+        <hasPrio>0</hasPrio>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>16</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>rtthread.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\link_scripts\at91sam9g45_ram.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+</project>
+
+
diff --git a/bsp/at91sam9g45/template.eww b/bsp/at91sam9g45/template.eww
new file mode 100644
index 0000000000..bd036bb4c9
--- /dev/null
+++ b/bsp/at91sam9g45/template.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
diff --git a/bsp/at91sam9g45/template.uvopt b/bsp/at91sam9g45/template.uvopt
new file mode 100644
index 0000000000..2dca5102b8
--- /dev/null
+++ b/bsp/at91sam9g45/template.uvopt
@@ -0,0 +1,174 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>18432000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>16</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ATMEL\AT91SAM9260_DS.PDF</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Summary</Title>
+          <Path>DATASHTS\ATMEL\AT91SAM9260_DC.PDF</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>5</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\jlink\at91sam9260.ini</tIfile>
+        <pMon>Segger\JLTAgdi.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JLTAgdi</Key>
+          <Name>-O558 -J1 -Y1000 -Z1 -FO0 -FD200000 -FC800 -FN0</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2ARM</Key>
+          <Name>-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
diff --git a/bsp/at91sam9g45/template.uvproj b/bsp/at91sam9g45/template.uvproj
new file mode 100644
index 0000000000..ea6226f101
--- /dev/null
+++ b/bsp/at91sam9g45/template.uvproj
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>AT91SAM9260</Device>
+          <Vendor>Atmel</Vendor>
+          <Cpu>IRAM(0x200000-0x200FFF) IRAM2(0x300000-0x300FFF) IROM(0x100000-0x107FFF) CLOCK(18432000) CPUTYPE(ARM926EJ-S)</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\Atmel\SAM9260.s" ("Atmel AT91SAM9260 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2ARM(-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)</FlashDriverDll>
+          <DeviceId>4210</DeviceId>
+          <RegisterFile>AT91SAM9260.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Atmel\SAM9260\</RegisterFilePath>
+          <DBRegisterFilePath>Atmel\SAM9260\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARM.DLL</SimDllName>
+          <SimDllArguments>-cAT91SAM9260</SimDllArguments>
+          <SimDlgDll>DARMATS9.DLL</SimDlgDll>
+          <SimDlgDllArguments>-p91SAM9260</SimDlgDllArguments>
+          <TargetDllName>SARM.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMATS9.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-p91SAM9260</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>5</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\jlink\at91sam9260.ini</InitializationFile>
+            <Driver>Segger\JLTAgdi.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2ARM.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4>.\jlink\at91sam9260.ini</Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>ARM926EJ-S</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>1</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>1</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x1000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x100000</StartAddress>
+                <Size>0x8000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x800000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x100000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x20800000</StartAddress>
+                <Size>0x1800000</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x300000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>RT_USING_INTERRUPT_INFO</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\platform</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x20000000</TextAddressRange>
+            <DataAddressRange>0x20800000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\link_scripts\at91sam9g45_ram.scat</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/libcpu/arm/arm926/start_rvds.S b/libcpu/arm/arm926/start_rvds.S
index 9f789b97f7..aca0e4577f 100644
--- a/libcpu/arm/arm926/start_rvds.S
+++ b/libcpu/arm/arm926/start_rvds.S
@@ -25,7 +25,14 @@
 ; * 2015-06-04     aozima     Align stack address to 8 byte.
 ; */
 
-#include "rt_low_level_init.h"
+;#include "rt_low_level_init.h"
+UND_STK_SIZE EQU 512
+SVC_STK_SIZE EQU 4096
+ABT_STK_SIZE EQU 512
+IRQ_STK_SIZE EQU 1024
+FIQ_STK_SIZE EQU 1024
+SYS_STK_SIZE EQU 512
+Heap_Size    EQU 512
 
 S_FRAME_SIZE    EQU     (18*4)   ;72
 ;S_SPSR          EQU     (17*4)   ;SPSR
-- 
cgit v1.3.1


From 86c76b0e8a4486dec13d61ee3ca68379b947dfb5 Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Fri, 28 Dec 2018 09:06:32 +0800
Subject: add k210 SMP support

---
 bsp/k210/.config                   |  36 +--------
 bsp/k210/driver/board.c            |  22 ++---
 bsp/k210/rtconfig.h                | 159 +++++++++++++++++++++++++++++++++++++
 bsp/k210/rtconfig.py               |   5 +-
 libcpu/risc-v/common/context_gcc.S | 100 ++++++++++++++++++++++-
 libcpu/risc-v/common/cpuport.c     |  24 ++++++
 libcpu/risc-v/k210/cpuport_smp.c   |  80 +++++++++++++++++++
 libcpu/risc-v/k210/interrupt.c     | 104 +++++++++++++++++++-----
 libcpu/risc-v/k210/interrupt_gcc.S |   9 +++
 libcpu/risc-v/k210/startup_gcc.S   |  31 ++++----
 10 files changed, 489 insertions(+), 81 deletions(-)
 create mode 100644 libcpu/risc-v/k210/cpuport_smp.c

(limited to 'libcpu')

diff --git a/bsp/k210/.config b/bsp/k210/.config
index a9737f1c80..65164c210d 100644
--- a/bsp/k210/.config
+++ b/bsp/k210/.config
@@ -7,7 +7,8 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
-# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=2
 CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@@ -326,39 +327,6 @@ CONFIG_PKG_KENDRYTE_SDK_VER="v0.5.2"
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
-# CONFIG_PKG_USING_KENDRYTE_DEMO_V001 is not set
-# CONFIG_PKG_USING_KENDRYTE_DEMO_LATEST_VERSION is not set
-# CONFIG_KENDRYTE_DEMO_NONE is not set
-# CONFIG_KENDRYTE_DEMO_AES_128_TEST is not set
-# CONFIG_KENDRYTE_DEMO_AES_192_TEST is not set
-# CONFIG_KENDRYTE_DEMO_AES_256_TEST is not set
-# CONFIG_KENDRYTE_DEMO_AI_DEMO_SIM is not set
-# CONFIG_KENDRYTE_DEMO_DVP_OV is not set
-# CONFIG_KENDRYTE_DEMO_FACE_DETECT is not set
-# CONFIG_KENDRYTE_DEMO_FFT_TEST is not set
-# CONFIG_KENDRYTE_DEMO_FLASH_W25QXX is not set
-# CONFIG_KENDRYTE_DEMO_FLASH_W25QXX_DMA_TEST is not set
-# CONFIG_KENDRYTE_DEMO_FLASH_W25QXX_TEST is not set
-# CONFIG_KENDRYTE_DEMO_GPIOHS_LED is not set
-# CONFIG_KENDRYTE_DEMO_GPIO_LED is not set
-# CONFIG_KENDRYTE_DEMO_HELLO_WORLD is not set
-# CONFIG_KENDRYTE_DEMO_I2C_SLAVE is not set
-# CONFIG_KENDRYTE_DEMO_KPU is not set
-# CONFIG_KENDRYTE_DEMO_LCD is not set
-# CONFIG_KENDRYTE_DEMO_MIC_PLAY is not set
-# CONFIG_KENDRYTE_DEMO_PLAY_PCM is not set
-# CONFIG_KENDRYTE_DEMO_PWM is not set
-# CONFIG_KENDRYTE_DEMO_RTC is not set
-# CONFIG_KENDRYTE_DEMO_RTC_SD3068 is not set
-# CONFIG_KENDRYTE_DEMO_SD_CARD is not set
-# CONFIG_KENDRYTE_DEMO_SERVO is not set
-# CONFIG_KENDRYTE_DEMO_SHA256_TEST is not set
-# CONFIG_KENDRYTE_DEMO_TIMER is not set
-# CONFIG_KENDRYTE_DEMO_UART is not set
-# CONFIG_KENDRYTE_DEMO_UART_DMA is not set
-# CONFIG_KENDRYTE_DEMO_UART_DMA_IRQ is not set
-# CONFIG_KENDRYTE_DEMO_UART_INTERRUPT is not set
-# CONFIG_KENDRYTE_DEMO_WATCHDOG is not set
 
 #
 # samples: kernel and components samples
diff --git a/bsp/k210/driver/board.c b/bsp/k210/driver/board.c
index aac2adbc49..1b2b4c34e8 100644
--- a/bsp/k210/driver/board.c
+++ b/bsp/k210/driver/board.c
@@ -37,21 +37,14 @@ void init_bss(void)
     }
 }
 
-void cpu_entry(int cpuid)
+void primary_cpu_entry(void)
 {
     extern void entry(void);
 
     /* disable global interrupt */
+    init_bss();
     rt_hw_interrupt_disable();
-    if (cpuid == 0)
-    {
-        init_bss();
-        entry();
-    }
-    else
-    {
-        while (1) ;
-    }
+    entry();
 }
 
 #include <clint.h>
@@ -85,6 +78,10 @@ int freq(void)
 }
 MSH_CMD_EXPORT(freq, show freq info);
 
+#ifdef RT_USING_SMP
+extern int rt_hw_clint_ipi_enable(void);
+#endif
+
 void rt_hw_board_init(void)
 {
     /* Init FPIOA */
@@ -96,8 +93,13 @@ void rt_hw_board_init(void)
     rt_hw_interrupt_init();
     /* initialize hardware interrupt */
     rt_hw_uart_init();
+
     rt_hw_tick_init();
 
+#ifdef RT_USING_SMP
+    rt_hw_clint_ipi_enable();
+#endif
+
 #ifdef RT_USING_CONSOLE
     /* set console device */
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
diff --git a/bsp/k210/rtconfig.h b/bsp/k210/rtconfig.h
index b5fe0dfd48..94844cbf88 100644
--- a/bsp/k210/rtconfig.h
+++ b/bsp/k210/rtconfig.h
@@ -7,8 +7,12 @@
 /* RT-Thread Kernel */
 
 #define RT_NAME_MAX 8
+#define RT_USING_SMP
+#define RT_CPUS_NR 2
 #define RT_ALIGN_SIZE 8
+/* RT_THREAD_PRIORITY_8 is not set */
 #define RT_THREAD_PRIORITY_32
+/* RT_THREAD_PRIORITY_256 is not set */
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
@@ -16,9 +20,19 @@
 #define RT_USING_IDLE_HOOK
 #define RT_IDEL_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 1024
+/* RT_USING_TIMER_SOFT is not set */
 #define RT_DEBUG
 #define RT_DEBUG_INIT_CONFIG
 #define RT_DEBUG_INIT 1
+/* RT_DEBUG_THREAD_CONFIG is not set */
+/* RT_DEBUG_SCHEDULER_CONFIG is not set */
+/* RT_DEBUG_IPC_CONFIG is not set */
+/* RT_DEBUG_TIMER_CONFIG is not set */
+/* RT_DEBUG_IRQ_CONFIG is not set */
+/* RT_DEBUG_MEM_CONFIG is not set */
+/* RT_DEBUG_SLAB_CONFIG is not set */
+/* RT_DEBUG_MEMHEAP_CONFIG is not set */
+/* RT_DEBUG_MODULE_CONFIG is not set */
 
 /* Inter-Thread communication */
 
@@ -27,16 +41,23 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
+/* RT_USING_SIGNALS is not set */
 
 /* Memory Management */
 
 #define RT_USING_MEMPOOL
+/* RT_USING_MEMHEAP is not set */
+/* RT_USING_NOHEAP is not set */
 #define RT_USING_SMALL_MEM
+/* RT_USING_SLAB is not set */
+/* RT_USING_MEMTRACE is not set */
 #define RT_USING_HEAP
 
 /* Kernel Device Object */
 
 #define RT_USING_DEVICE
+/* RT_USING_DEVICE_OPS is not set */
+/* RT_USING_INTERRUPT_INFO is not set */
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uarths"
@@ -44,6 +65,7 @@
 #define ARCH_CPU_64BIT
 #define ARCH_RISCV
 #define ARCH_RISCV64
+/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
 
 /* RT-Thread Components */
 
@@ -54,6 +76,7 @@
 
 /* C++ features */
 
+/* RT_USING_CPLUSPLUS is not set */
 
 /* Command shell */
 
@@ -63,9 +86,11 @@
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
+/* FINSH_ECHO_DISABLE_DEFAULT is not set */
 #define FINSH_THREAD_PRIORITY 20
 #define FINSH_THREAD_STACK_SIZE 16384
 #define FINSH_CMD_SIZE 80
+/* FINSH_USING_AUTH is not set */
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
 #define FINSH_USING_MSH_ONLY
@@ -78,7 +103,13 @@
 #define DFS_FILESYSTEMS_MAX 4
 #define DFS_FILESYSTEM_TYPES_MAX 4
 #define DFS_FD_MAX 16
+/* RT_USING_DFS_MNTTABLE is not set */
+/* RT_USING_DFS_ELMFAT is not set */
 #define RT_USING_DFS_DEVFS
+/* RT_USING_DFS_ROMFS is not set */
+/* RT_USING_DFS_RAMFS is not set */
+/* RT_USING_DFS_UFFS is not set */
+/* RT_USING_DFS_JFFS2 is not set */
 
 /* Device Drivers */
 
@@ -86,87 +117,215 @@
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
 #define RT_SERIAL_USING_DMA
+/* RT_USING_CAN is not set */
+/* RT_USING_HWTIMER is not set */
+/* RT_USING_CPUTIME is not set */
+/* RT_USING_I2C is not set */
+/* RT_USING_PIN is not set */
+/* RT_USING_ADC is not set */
+/* RT_USING_PWM is not set */
+/* RT_USING_MTD_NOR is not set */
+/* RT_USING_MTD_NAND is not set */
+/* RT_USING_MTD is not set */
+/* RT_USING_PM is not set */
+/* RT_USING_RTC is not set */
+/* RT_USING_SDIO is not set */
+/* RT_USING_SPI is not set */
+/* RT_USING_WDT is not set */
+/* RT_USING_AUDIO is not set */
 
 /* Using WiFi */
 
+/* RT_USING_WIFI is not set */
 
 /* Using USB */
 
+/* RT_USING_USB_HOST is not set */
+/* RT_USING_USB_DEVICE is not set */
 
 /* POSIX layer and C standard library */
 
 #define RT_USING_LIBC
+/* RT_USING_PTHREADS is not set */
 #define RT_USING_POSIX
+/* RT_USING_POSIX_MMAP is not set */
+/* RT_USING_POSIX_TERMIOS is not set */
+/* RT_USING_POSIX_AIO is not set */
+/* RT_USING_MODULE is not set */
 
 /* Network */
 
 /* Socket abstraction layer */
 
+/* RT_USING_SAL is not set */
 
 /* light weight TCP/IP stack */
 
+/* RT_USING_LWIP is not set */
 
 /* Modbus master and slave stack */
 
+/* RT_USING_MODBUS is not set */
 
 /* AT commands */
 
+/* RT_USING_AT is not set */
 
 /* VBUS(Virtual Software BUS) */
 
+/* RT_USING_VBUS is not set */
 
 /* Utilities */
 
+/* RT_USING_LOGTRACE is not set */
+/* RT_USING_RYM is not set */
+/* RT_USING_ULOG is not set */
+/* RT_USING_UTEST is not set */
 
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
 
+/* PKG_USING_PAHOMQTT is not set */
+/* PKG_USING_WEBCLIENT is not set */
+/* PKG_USING_WEBNET is not set */
+/* PKG_USING_MONGOOSE is not set */
+/* PKG_USING_WEBTERMINAL is not set */
+/* PKG_USING_CJSON is not set */
+/* PKG_USING_JSMN is not set */
+/* PKG_USING_LJSON is not set */
+/* PKG_USING_EZXML is not set */
+/* PKG_USING_NANOPB is not set */
 
 /* Wi-Fi */
 
 /* Marvell WiFi */
 
+/* PKG_USING_WLANMARVELL is not set */
 
 /* Wiced WiFi */
 
+/* PKG_USING_WLAN_WICED is not set */
+/* PKG_USING_COAP is not set */
+/* PKG_USING_NOPOLL is not set */
+/* PKG_USING_NETUTILS is not set */
+/* PKG_USING_AT_DEVICE is not set */
+/* PKG_USING_WIZNET is not set */
 
 /* IoT Cloud */
 
+/* PKG_USING_ONENET is not set */
+/* PKG_USING_GAGENT_CLOUD is not set */
+/* PKG_USING_ALI_IOTKIT is not set */
+/* PKG_USING_AZURE is not set */
+/* PKG_USING_TENCENT_IOTKIT is not set */
 
 /* security packages */
 
+/* PKG_USING_MBEDTLS is not set */
+/* PKG_USING_libsodium is not set */
+/* PKG_USING_TINYCRYPT is not set */
 
 /* language packages */
 
+/* PKG_USING_LUA is not set */
+/* PKG_USING_JERRYSCRIPT is not set */
+/* PKG_USING_MICROPYTHON is not set */
 
 /* multimedia packages */
 
+/* PKG_USING_OPENMV is not set */
+/* PKG_USING_MUPDF is not set */
 
 /* tools packages */
 
+/* PKG_USING_CMBACKTRACE is not set */
+/* PKG_USING_EASYFLASH is not set */
+/* PKG_USING_EASYLOGGER is not set */
+/* PKG_USING_SYSTEMVIEW is not set */
+/* PKG_USING_RDB is not set */
+/* PKG_USING_QRCODE is not set */
+/* PKG_USING_ULOG_EASYFLASH is not set */
 
 /* system packages */
 
+/* PKG_USING_GUIENGINE is not set */
+/* PKG_USING_CAIRO is not set */
+/* PKG_USING_PIXMAN is not set */
+/* PKG_USING_LWEXT4 is not set */
+/* PKG_USING_PARTITION is not set */
+/* PKG_USING_FAL is not set */
+/* PKG_USING_SQLITE is not set */
+/* PKG_USING_RTI is not set */
+/* PKG_USING_LITTLEVGL2RTT is not set */
+/* PKG_USING_CMSIS is not set */
+/* PKG_USING_DFS_YAFFS is not set */
+/* PKG_USING_LITTLEFS is not set */
 
 /* peripheral libraries and drivers */
 
+/* PKG_USING_REALTEK_AMEBA is not set */
+/* PKG_USING_SHT2X is not set */
+/* PKG_USING_AHT10 is not set */
+/* PKG_USING_AP3216C is not set */
+/* PKG_USING_STM32_SDIO is not set */
+/* PKG_USING_ICM20608 is not set */
+/* PKG_USING_U8G2 is not set */
+/* PKG_USING_BUTTON is not set */
+/* PKG_USING_MPU6XXX is not set */
+/* PKG_USING_PCF8574 is not set */
 #define PKG_USING_KENDRYTE_SDK
 #define PKG_USING_KENDRYTE_SDK_V052
+/* PKG_USING_KENDRYTE_SDK_LATEST_VERSION is not set */
 
 /* miscellaneous packages */
 
+/* PKG_USING_LIBCSV is not set */
+/* PKG_USING_OPTPARSE is not set */
+/* PKG_USING_FASTLZ is not set */
+/* PKG_USING_MINILZO is not set */
+/* PKG_USING_QUICKLZ is not set */
+/* PKG_USING_MULTIBUTTON is not set */
+/* PKG_USING_CANFESTIVAL is not set */
+/* PKG_USING_ZLIB is not set */
+/* PKG_USING_DSTR is not set */
+/* PKG_USING_TINYFRAME is not set */
+/* PKG_USING_KENDRYTE_DEMO is not set */
 
 /* samples: kernel and components samples */
 
+/* PKG_USING_KERNEL_SAMPLES is not set */
+/* PKG_USING_FILESYSTEM_SAMPLES is not set */
+/* PKG_USING_NETWORK_SAMPLES is not set */
+/* PKG_USING_PERIPHERAL_SAMPLES is not set */
+/* PKG_USING_HELLO is not set */
 
 /* Privated Packages of RealThread */
 
+/* PKG_USING_CODEC is not set */
+/* PKG_USING_PLAYER is not set */
+/* PKG_USING_PERSIMMON_SRC is not set */
+/* PKG_USING_JS_PERSIMMON is not set */
+/* PKG_USING_JERRYSCRIPT_WIN32 is not set */
 
 /* Network Utilities */
 
+/* PKG_USING_WICED is not set */
+/* PKG_USING_CLOUDSDK is not set */
+/* PKG_USING_COREMARK is not set */
+/* PKG_USING_POWER_MANAGER is not set */
+/* PKG_USING_RT_OTA is not set */
+/* PKG_USING_RDBD_SRC is not set */
+/* PKG_USING_RTINSIGHT is not set */
+/* PKG_USING_SMARTCONFIG is not set */
+/* PKG_USING_RTX is not set */
 #define BOARD_K210_EVB
 #define BSP_USING_UART_HS
+/* BSP_USING_UART1 is not set */
+/* BSP_USING_UART2 is not set */
+/* BSP_USING_UART3 is not set */
+/* BSP_USING_I2C1 is not set */
+/* BSP_USING_SPI1 is not set */
 #define __STACKSIZE__ 4096
 
 #endif
diff --git a/bsp/k210/rtconfig.py b/bsp/k210/rtconfig.py
index 418c1d7456..4610f85adc 100644
--- a/bsp/k210/rtconfig.py
+++ b/bsp/k210/rtconfig.py
@@ -15,7 +15,7 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM    = 'gcc'
-    EXEC_PATH   = r'/opt/riscv64-unknown-elf-gcc-2018.07.0-x86_64-linux-ubuntu14/bin'
+    EXEC_PATH   = r'/opt/riscv64-unknown-elf/bin'
 else:
     print('Please make sure your toolchains is GNU GCC!')
     exit(0)
@@ -27,8 +27,7 @@ BUILD = 'release'
 
 if PLATFORM == 'gcc':
     # toolchains
-    PREFIX  = 'riscv-none-embed-'
-    # PREFIX  = 'riscv64-unknown-elf-'
+    PREFIX  = 'riscv64-unknown-elf-'
     CC      = PREFIX + 'gcc'
     CXX     = PREFIX + 'g++'
     AS      = PREFIX + 'gcc'
diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S
index 94ae5d9df4..62e64d8104 100644
--- a/libcpu/risc-v/common/context_gcc.S
+++ b/libcpu/risc-v/common/context_gcc.S
@@ -6,10 +6,16 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018/10/28     Bernard      The unify RISC-V porting implementation
+ * 2018/12/27     Jesven       Add SMP support
  */
 
 #include "cpuport.h"
 
+#ifdef RT_USING_SMP
+#define rt_hw_interrupt_disable rt_hw_local_irq_disable
+#define rt_hw_interrupt_enable  rt_hw_local_irq_enable
+#endif
+
 /*
  * rt_base_t rt_hw_interrupt_disable(void);
  */
@@ -27,13 +33,23 @@ rt_hw_interrupt_enable:
     ret
 
 /*
- * void rt_hw_context_switch_to(rt_ubase_t to)
+ * #ifdef RT_USING_SMP
+ * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
+ * #else
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * #endif
  * a0 --> to
+ * a1 --> to_thread
  */
     .globl rt_hw_context_switch_to
 rt_hw_context_switch_to:
     LOAD sp, (a0)
 
+#ifdef RT_USING_SMP
+    mv   a0,   a1
+    jal  rt_cpus_lock_status_restore
+#endif
+
     /* load epc from stack */
     LOAD a0,   0 * REGBYTES(sp)
     csrw mepc, a0
@@ -74,9 +90,15 @@ rt_hw_context_switch_to:
     mret
 
 /*
- * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
+ * #ifdef RT_USING_SMP
+ * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
+ * #else
+ * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
+ * #endif
+ *
  * a0 --> from
  * a1 --> to
+ * a2 --> to_thread
  */
     .globl rt_hw_context_switch
 rt_hw_context_switch:
@@ -136,6 +158,78 @@ save_mpie:
      */
     LOAD sp,  (a1)
 
+#ifdef RT_USING_SMP
+    mv   a0,   a2
+    jal  rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+
+    /* resw ra to mepc */
+    LOAD a1,   0 * REGBYTES(sp)
+    csrw mepc, a1
+    LOAD x1,   1 * REGBYTES(sp)
+
+    /* force to machin mode(MPP=11) */
+    li a1, 0x00001800;
+    csrs mstatus, a1
+    LOAD a1,   2 * REGBYTES(sp)
+    csrs mstatus, a1
+
+    LOAD x4,   4 * REGBYTES(sp)
+    LOAD x5,   5 * REGBYTES(sp)
+    LOAD x6,   6 * REGBYTES(sp)
+    LOAD x7,   7 * REGBYTES(sp)
+    LOAD x8,   8 * REGBYTES(sp)
+    LOAD x9,   9 * REGBYTES(sp)
+    LOAD x10, 10 * REGBYTES(sp)
+    LOAD x11, 11 * REGBYTES(sp)
+    LOAD x12, 12 * REGBYTES(sp)
+    LOAD x13, 13 * REGBYTES(sp)
+    LOAD x14, 14 * REGBYTES(sp)
+    LOAD x15, 15 * REGBYTES(sp)
+    LOAD x16, 16 * REGBYTES(sp)
+    LOAD x17, 17 * REGBYTES(sp)
+    LOAD x18, 18 * REGBYTES(sp)
+    LOAD x19, 19 * REGBYTES(sp)
+    LOAD x20, 20 * REGBYTES(sp)
+    LOAD x21, 21 * REGBYTES(sp)
+    LOAD x22, 22 * REGBYTES(sp)
+    LOAD x23, 23 * REGBYTES(sp)
+    LOAD x24, 24 * REGBYTES(sp)
+    LOAD x25, 25 * REGBYTES(sp)
+    LOAD x26, 26 * REGBYTES(sp)
+    LOAD x27, 27 * REGBYTES(sp)
+    LOAD x28, 28 * REGBYTES(sp)
+    LOAD x29, 29 * REGBYTES(sp)
+    LOAD x30, 30 * REGBYTES(sp)
+    LOAD x31, 31 * REGBYTES(sp)
+
+    addi sp,  sp, 32 * REGBYTES
+    mret
+
+#ifdef RT_USING_SMP
+/*
+ * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
+ *
+ * a0 --> context
+ * a1 --> from
+ * a2 --> to
+ * a3 --> to_thread
+ */
+    .globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+
+    STORE a0, 0(a1)
+
+    csrr  a1, mepc
+    STORE a1, 0 * REGBYTES(a0)
+
+    csrr  a1, mstatus
+    STORE a1, 2 * REGBYTES(a0)
+
+    LOAD  sp, 0(a2)
+    move  a0, a3
+    call rt_cpus_lock_status_restore
+
     /* resw ra to mepc */
     LOAD a1,   0 * REGBYTES(sp)
     csrw mepc, a1
@@ -178,3 +272,5 @@ save_mpie:
 
     addi sp,  sp, 32 * REGBYTES
     mret
+
+#endif
diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c
index 2ad77b99c5..a44dc40f79 100644
--- a/libcpu/risc-v/common/cpuport.c
+++ b/libcpu/risc-v/common/cpuport.c
@@ -13,9 +13,11 @@
 
 #include "cpuport.h"
 
+#ifndef RT_USING_SMP
 volatile rt_ubase_t  rt_interrupt_from_thread = 0;
 volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
 volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
+#endif
 
 struct rt_hw_stack_frame
 {
@@ -93,6 +95,14 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
     return stk;
 }
 
+/*
+ * #ifdef RT_USING_SMP
+ * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
+ * #else
+ * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
+ * #endif
+ */
+#ifndef RT_USING_SMP
 void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
 {
     if (rt_thread_switch_interrupt_flag == 0)
@@ -103,3 +113,17 @@ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
 
     return ;
 }
+#endif /* end of RT_USING_SMP */
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
diff --git a/libcpu/risc-v/k210/cpuport_smp.c b/libcpu/risc-v/k210/cpuport_smp.c
new file mode 100644
index 0000000000..a31314a13f
--- /dev/null
+++ b/libcpu/risc-v/k210/cpuport_smp.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/12/23     Bernard      The first version
+ * 2018/12/27     Jesven       Add secondary cpu boot
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <stdint.h>
+
+#include "board.h"
+#include <encoding.h>
+#include <clint.h>
+#include <atomic.h>
+
+#ifdef RT_USING_SMP
+
+int rt_hw_cpu_id(void)
+{
+    return read_csr(mhartid);
+}
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    spinlock_lock((spinlock_t *)lock);
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    spinlock_unlock((spinlock_t *)lock);
+}
+
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+{
+    int idx;
+
+    for (idx = 0; idx < RT_CPUS_NR; idx ++)
+    {
+        if (cpu_mask & (1 << idx))
+        {
+            clint_ipi_send(idx);
+        }
+    }
+}
+
+extern rt_base_t secondary_boot_flag;
+void rt_hw_secondary_cpu_up(void)
+{
+    mb();
+    secondary_boot_flag = 0xa55a;
+}
+
+extern void rt_hw_scondary_interrupt_init(void);
+extern int rt_hw_tick_init(void);
+extern int rt_hw_clint_ipi_enable(void);
+
+void secondary_cpu_c_start(void)
+{
+    rt_hw_spin_lock(&_cpus_lock);
+
+    /* initialize interrupt controller */
+    rt_hw_scondary_interrupt_init();
+
+    rt_hw_tick_init();
+
+    rt_hw_clint_ipi_enable();
+
+    rt_system_scheduler_start();
+}
+
+void rt_hw_secondary_cpu_idle_exec(void)
+{
+    asm volatile ("wfi");
+}
+#endif /*RT_USING_SMP*/
diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c
index f9c3eb5a67..3d30e69ed2 100644
--- a/libcpu/risc-v/k210/interrupt.c
+++ b/libcpu/risc-v/k210/interrupt.c
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018/10/01     Bernard      The first version
+ * 2018/12/27     Jesven       Change irq enable/disable to cpu0
  */
 
 #include <rthw.h>
@@ -19,7 +20,7 @@
 #define CPU_NUM         2
 #define MAX_HANDLERS    IRQN_MAX
 
-static struct rt_irq_desc irq_desc[CPU_NUM][MAX_HANDLERS];
+static struct rt_irq_desc irq_desc[MAX_HANDLERS];
 
 static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
 {
@@ -27,6 +28,52 @@ static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
     return RT_NULL;
 }
 
+int rt_hw_clint_ipi_enable(void)
+{
+    /* Set the Machine-Software bit in MIE */
+    set_csr(mie, MIP_MSIP);
+    return 0;
+}
+
+int rt_hw_clint_ipi_disable(void)
+{
+    /* Clear the Machine-Software bit in MIE */
+    clear_csr(mie, MIP_MSIP);
+    return 0;
+}
+
+int rt_hw_plic_irq_enable(plic_irq_t irq_number)
+{
+    unsigned long core_id = 0;
+
+    /* Check parameters */
+    if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number)
+        return -1;
+    /* Get current enable bit array by IRQ number */
+    uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32];
+    /* Set enable bit in enable bit array */
+    current |= (uint32_t)1 << (irq_number % 32);
+    /* Write back the enable bit array */
+    plic->target_enables.target[core_id].enable[irq_number / 32] = current;
+    return 0;
+}
+
+int rt_hw_plic_irq_disable(plic_irq_t irq_number)
+{
+    unsigned long core_id = 0;
+
+    /* Check parameters */
+    if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number)
+        return -1;
+    /* Get current enable bit array by IRQ number */
+    uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32];
+    /* Clear enable bit in enable bit array */
+    current &= ~((uint32_t)1 << (irq_number % 32));
+    /* Write back the enable bit array */
+    plic->target_enables.target[core_id].enable[irq_number / 32] = current;
+    return 0;
+}
+
 /**
  * This function will initialize hardware interrupt
  */
@@ -52,11 +99,11 @@ void rt_hw_interrupt_init(void)
     for (idx = 0; idx < MAX_HANDLERS; idx++)
     {
         rt_hw_interrupt_mask(idx);
-        irq_desc[cpuid][idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
-        irq_desc[cpuid][idx].param = RT_NULL;
+        irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+        irq_desc[idx].param = RT_NULL;
 #ifdef RT_USING_INTERRUPT_INFO
-        rt_snprintf(irq_desc[cpuid][idx].name, RT_NAME_MAX - 1, "default");
-        irq_desc[idx][cpuid].counter = 0;
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx].counter = 0;
 #endif
     }
 
@@ -64,13 +111,31 @@ void rt_hw_interrupt_init(void)
     set_csr(mie, MIP_MEIP);
 }
 
+void rt_hw_scondary_interrupt_init(void)
+{
+    int idx;
+    int cpuid;
+
+    cpuid = current_coreid();
+
+    /* Disable all interrupts for the current core. */
+    for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++)
+        plic->target_enables.target[cpuid].enable[idx] = 0;
+
+    /* Set the threshold to zero. */
+    plic->targets.target[cpuid].priority_threshold = 0;
+
+    /* Enable machine external interrupts. */
+    set_csr(mie, MIP_MEIP);
+}
+
 /**
  * This function will mask a interrupt.
  * @param vector the interrupt number
  */
 void rt_hw_interrupt_mask(int vector)
 {
-    plic_irq_disable(vector);
+    rt_hw_plic_irq_disable(vector);
 }
 
 /**
@@ -80,7 +145,7 @@ void rt_hw_interrupt_mask(int vector)
 void rt_hw_interrupt_umask(int vector)
 {
     plic_set_priority(vector, 1);
-    plic_irq_enable(vector);
+    rt_hw_plic_irq_enable(vector);
 }
 
 /**
@@ -92,21 +157,18 @@ void rt_hw_interrupt_umask(int vector)
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
         void *param, const char *name)
 {
-    int cpuid;
     rt_isr_handler_t old_handler = RT_NULL;
 
-    cpuid = current_coreid();
-
     if(vector < MAX_HANDLERS)
     {
-        old_handler = irq_desc[cpuid][vector].handler;
+        old_handler = irq_desc[vector].handler;
         if (handler != RT_NULL)
         {
-            irq_desc[cpuid][vector].handler = (rt_isr_handler_t)handler;
-            irq_desc[cpuid][vector].param = param;
+            irq_desc[vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[vector].param = param;
 #ifdef RT_USING_INTERRUPT_INFO
-            rt_snprintf(irq_desc[cpuid][vector].name, RT_NAME_MAX - 1, "%s", name);
-            irq_desc[cpuid][vector].counter = 0;
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
+            irq_desc[vector].counter = 0;
 #endif
         }
     }
@@ -149,14 +211,14 @@ uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
         /* Disable software interrupt and timer interrupt */
         clear_csr(mie, MIP_MTIP | MIP_MSIP);
 
-        if (irq_desc[core_id][int_num].handler == (rt_isr_handler_t)rt_hw_interrupt_handle)
+        if (irq_desc[int_num].handler == (rt_isr_handler_t)rt_hw_interrupt_handle)
         {
             /* default handler, route to kendryte bsp plic driver */
             plic_irq_handle(int_num);
         }
-        else if (irq_desc[core_id][int_num].handler)
+        else if (irq_desc[int_num].handler)
         {
-            irq_desc[core_id][int_num].handler(int_num, irq_desc[core_id][int_num].param);
+            irq_desc[int_num].handler(int_num, irq_desc[int_num].param);
         }
 
         /* Perform IRQ complete */
@@ -185,6 +247,12 @@ uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
         switch (cause)
         {
             case IRQ_M_SOFT:
+                {
+                    uint64_t core_id = current_coreid();
+
+                    clint_ipi_clear(core_id);
+                    rt_schedule();
+                }
                 break;
             case IRQ_M_EXT:
                 handle_irq_m_ext(mcause, epc);
diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S
index 5783322237..5d3e8368b1 100644
--- a/libcpu/risc-v/k210/interrupt_gcc.S
+++ b/libcpu/risc-v/k210/interrupt_gcc.S
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018/10/02     Bernard      The first version
+ * 2018/12/27     Jesven       Add SMP schedule
  */
 
 #include "cpuport.h"
@@ -72,6 +73,13 @@ trap_entry:
     call  handle_trap
     call  rt_interrupt_leave
 
+#ifdef RT_USING_SMP
+    /* s0 --> sp */
+    mv  a0, s0
+    call rt_scheduler_do_irq_switch
+    mv  sp, s0
+#else
+
     /* switch to from_thread stack */
     move  sp, s0
 
@@ -94,6 +102,7 @@ trap_entry:
 
     LOAD  a0,  0 * REGBYTES(sp)
     csrw  mepc, a0
+#endif
 
 spurious_interrupt:
     LOAD  x1,   1 * REGBYTES(sp)
diff --git a/libcpu/risc-v/k210/startup_gcc.S b/libcpu/risc-v/k210/startup_gcc.S
index 2e69c5021e..f5c0d8fa94 100644
--- a/libcpu/risc-v/k210/startup_gcc.S
+++ b/libcpu/risc-v/k210/startup_gcc.S
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018/10/01     Bernard      The first version
+ * 2018/12/27     Jesven       Add SMP support
  */
 
 #define MSTATUS_FS      0x00006000U /* initial state of FPU     */
@@ -114,20 +115,22 @@ _start:
   add  sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
 
   /* other cpu core, jump to cpu entry directly */
-  bnez a0, _cpu_entry
+  bnez a0, secondary_cpu_entry
+  j primary_cpu_entry
 
-#if 0
-  /* clear bss section */
-  la a0, __bss_start
-  la a1, __bss_end
-  bgeu a0, a1, 2f
-1:
-  sw zero, (a0)
-  addi a0, a0, REGBYTES
-  bltu a0, a1, 1b
-2:
+secondary_cpu_entry:
+#ifdef RT_USING_SMP
+  la a0, secondary_boot_flag
+  ld a0, 0(a0)
+  li a1, 0xa55a
+  beq a0, a1, secondary_cpu_c_start
 #endif
+  j secondary_cpu_entry
 
-_cpu_entry:
-  csrr a0, mhartid
-  j cpu_entry
+#ifdef RT_USING_SMP
+.data
+.global secondary_boot_flag
+.align 3
+secondary_boot_flag:
+    .dword 0
+#endif
-- 
cgit v1.3.1


From bde47018b8327fb8106c68e84a719a97243a1653 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Mon, 7 Jan 2019 06:09:45 +0800
Subject: [libcpu] Add SConscript in libcpu.

---
 bsp/qemu-vexpress-a9/SConstruct       |   1 +
 bsp/qemu-vexpress-gemini/SConstruct   |   9 +--
 bsp/realview-a8/SConstruct            |   9 +--
 libcpu/SConscript                     |  41 +++--------
 libcpu/arm/AT91SAM7S/SConscript       |  23 ++++++
 libcpu/arm/AT91SAM7S/context_rvds.S   | 130 ++++++++++++++++------------------
 libcpu/arm/AT91SAM7X/SConscript       |  23 ++++++
 libcpu/arm/AT91SAM7X/context_rvds.S   |  22 +++---
 libcpu/arm/SConscript                 |  18 +++++
 libcpu/arm/am335x/SConscript          |  23 ++++++
 libcpu/arm/arm926/SConscript          |  25 +++++++
 libcpu/arm/arm926/context_gcc.S       |  18 +----
 libcpu/arm/arm926/context_iar.S       |  34 +++------
 libcpu/arm/arm926/context_rvds.S      |  22 ++----
 libcpu/arm/arm926/start_iar.S         |  18 +----
 libcpu/arm/arm926/start_rvds.S        |  37 +---------
 libcpu/arm/armv6/SConscript           |  23 ++++++
 libcpu/arm/common/SConscript          |  23 ++++++
 libcpu/arm/common/backtrace.c         |  58 +++++++--------
 libcpu/arm/cortex-a/SConscript        |  23 ++++++
 libcpu/arm/cortex-m0/SConscript       |  23 ++++++
 libcpu/arm/cortex-m0/context_iar.S    |   8 +--
 libcpu/arm/cortex-m0/context_rvds.S   |   8 +--
 libcpu/arm/cortex-m3/SConscript       |  23 ++++++
 libcpu/arm/cortex-m3/context_iar.S    |   8 +--
 libcpu/arm/cortex-m3/context_rvds.S   |   8 +--
 libcpu/arm/cortex-m4/SConscript       |  23 ++++++
 libcpu/arm/cortex-m4/context_iar.S    |   8 +--
 libcpu/arm/cortex-m7/SConscript       |  23 ++++++
 libcpu/arm/cortex-m7/context_iar.S    |   8 +--
 libcpu/arm/cortex-m7/context_rvds.S   |   8 +--
 libcpu/arm/cortex-r4/SConscript       |  23 ++++++
 libcpu/arm/cortex-r4/context_ccs.asm  |  10 +--
 libcpu/arm/dm36x/SConscript           |  23 ++++++
 libcpu/arm/dm36x/context_rvds.S       |  18 +----
 libcpu/arm/lpc214x/SConscript         |  23 ++++++
 libcpu/arm/lpc214x/context_rvds.S     |   8 +--
 libcpu/arm/lpc24xx/SConscript         |  23 ++++++
 libcpu/arm/lpc24xx/context_rvds.S     |   8 +--
 libcpu/arm/realview-a8-vmm/SConscript |  22 +++---
 libcpu/arm/s3c24x0/SConscript         |  23 ++++++
 libcpu/arm/s3c24x0/context_rvds.S     |   8 +--
 libcpu/arm/s3c44b0/SConscript         |  23 ++++++
 libcpu/arm/s3c44b0/context_rvds.S     |   8 +--
 libcpu/arm/sep4020/SConscript         |  23 ++++++
 libcpu/arm/sep4020/context_rvds.S     |   8 +--
 libcpu/arm/zynq7000/SConscript        |  22 +++---
 libcpu/arm/zynq7000/context_gcc.S     |  20 ++----
 libcpu/arm/zynq7000/cp15.h            |  25 +++----
 libcpu/arm/zynq7000/gic.c             |  20 ++----
 libcpu/arm/zynq7000/gic.h             |  20 ++----
 libcpu/arm/zynq7000/interrupt.h       |  25 +++----
 libcpu/arm/zynq7000/mmu.c             |  20 ++----
 libcpu/arm/zynq7000/trap.c            |  20 ++----
 libcpu/avr32/SConscript               |  15 ++++
 libcpu/avr32/uc3/SConscript           |  14 ++++
 libcpu/blackfin/SConscript            |  15 ++++
 libcpu/blackfin/bf53x/SConscript      |  14 ++++
 libcpu/c-sky/SConscript               |  18 +++++
 libcpu/c-sky/ck802/SConscript         |  14 ++++
 libcpu/c-sky/common/SConscript        |  14 ++++
 libcpu/ia32/SConscript                |  14 ++++
 libcpu/m16c/SConscript                |  15 ++++
 libcpu/m16c/m16c62p/SConscript        |  14 ++++
 libcpu/mips/SConscript                |  18 +++++
 libcpu/mips/common/SConscript         |  14 ++++
 libcpu/mips/loongson_1b/SConscript    |  14 ++++
 libcpu/mips/loongson_1c/SConscript    |  14 ++++
 libcpu/mips/pic32/SConscript          |  14 ++++
 libcpu/mips/x1000/SConscript          |  14 ++++
 libcpu/mips/xburst/SConscript.1       |  14 ++++
 libcpu/nios/SConscript                |  15 ++++
 libcpu/nios/nios_ii/SConscript        |  14 ++++
 libcpu/ppc/SConscript                 |  18 +++++
 libcpu/ppc/common/SConscript          |  14 ++++
 libcpu/ppc/common/ptrace.h            |  28 ++++----
 libcpu/ppc/ppc405/SConscript          |  14 ++++
 libcpu/risc-v/SConscript              |  18 +++++
 libcpu/risc-v/common/SConscript       |  12 ++++
 libcpu/risc-v/e310/SConscript         |  13 ++--
 libcpu/risc-v/k210/SConscript         |  14 ++++
 libcpu/risc-v/rv32m1/SConscript       |  14 ++++
 libcpu/rx/SConscript                  |  14 ++++
 libcpu/sim/SConscript                 |  15 ++++
 libcpu/sim/posix/SConscript           |  14 ++++
 libcpu/sim/win32/SConscript           |  14 ++++
 libcpu/ti-dsp/SConscript              |  15 ++++
 libcpu/ti-dsp/c28x/SConscript         |  14 ++++
 libcpu/unicore32/SConscript           |  15 ++++
 libcpu/unicore32/sep6200/SConscript   |  14 ++++
 libcpu/v850/70f34/SConscript          |  14 ++++
 libcpu/v850/SConscript                |  15 ++++
 libcpu/xilinx/SConscript              |  15 ++++
 libcpu/xilinx/microblaze/SConscript   |  14 ++++
 94 files changed, 1249 insertions(+), 498 deletions(-)
 create mode 100644 libcpu/arm/AT91SAM7S/SConscript
 create mode 100644 libcpu/arm/AT91SAM7X/SConscript
 create mode 100644 libcpu/arm/SConscript
 create mode 100644 libcpu/arm/am335x/SConscript
 create mode 100644 libcpu/arm/arm926/SConscript
 create mode 100644 libcpu/arm/armv6/SConscript
 create mode 100644 libcpu/arm/common/SConscript
 create mode 100644 libcpu/arm/cortex-a/SConscript
 create mode 100644 libcpu/arm/cortex-m0/SConscript
 create mode 100644 libcpu/arm/cortex-m3/SConscript
 create mode 100644 libcpu/arm/cortex-m4/SConscript
 create mode 100644 libcpu/arm/cortex-m7/SConscript
 create mode 100644 libcpu/arm/cortex-r4/SConscript
 create mode 100644 libcpu/arm/dm36x/SConscript
 create mode 100644 libcpu/arm/lpc214x/SConscript
 create mode 100644 libcpu/arm/lpc24xx/SConscript
 create mode 100644 libcpu/arm/s3c24x0/SConscript
 create mode 100644 libcpu/arm/s3c44b0/SConscript
 create mode 100644 libcpu/arm/sep4020/SConscript
 create mode 100644 libcpu/avr32/SConscript
 create mode 100644 libcpu/avr32/uc3/SConscript
 create mode 100644 libcpu/blackfin/SConscript
 create mode 100644 libcpu/blackfin/bf53x/SConscript
 create mode 100644 libcpu/c-sky/SConscript
 create mode 100644 libcpu/c-sky/ck802/SConscript
 create mode 100644 libcpu/c-sky/common/SConscript
 create mode 100644 libcpu/ia32/SConscript
 create mode 100644 libcpu/m16c/SConscript
 create mode 100644 libcpu/m16c/m16c62p/SConscript
 create mode 100644 libcpu/mips/SConscript
 create mode 100644 libcpu/mips/common/SConscript
 create mode 100644 libcpu/mips/loongson_1b/SConscript
 create mode 100644 libcpu/mips/loongson_1c/SConscript
 create mode 100644 libcpu/mips/pic32/SConscript
 create mode 100644 libcpu/mips/x1000/SConscript
 create mode 100644 libcpu/mips/xburst/SConscript.1
 create mode 100644 libcpu/nios/SConscript
 create mode 100644 libcpu/nios/nios_ii/SConscript
 create mode 100644 libcpu/ppc/SConscript
 create mode 100644 libcpu/ppc/common/SConscript
 create mode 100644 libcpu/ppc/ppc405/SConscript
 create mode 100644 libcpu/risc-v/SConscript
 create mode 100644 libcpu/risc-v/common/SConscript
 create mode 100644 libcpu/risc-v/k210/SConscript
 create mode 100644 libcpu/risc-v/rv32m1/SConscript
 create mode 100644 libcpu/rx/SConscript
 create mode 100644 libcpu/sim/SConscript
 create mode 100644 libcpu/sim/posix/SConscript
 create mode 100644 libcpu/sim/win32/SConscript
 create mode 100644 libcpu/ti-dsp/SConscript
 create mode 100644 libcpu/ti-dsp/c28x/SConscript
 create mode 100644 libcpu/unicore32/SConscript
 create mode 100644 libcpu/unicore32/sep6200/SConscript
 create mode 100644 libcpu/v850/70f34/SConscript
 create mode 100644 libcpu/v850/SConscript
 create mode 100644 libcpu/xilinx/SConscript
 create mode 100644 libcpu/xilinx/microblaze/SConscript

(limited to 'libcpu')

diff --git a/bsp/qemu-vexpress-a9/SConstruct b/bsp/qemu-vexpress-a9/SConstruct
index 61af0ee620..638311d697 100644
--- a/bsp/qemu-vexpress-a9/SConstruct
+++ b/bsp/qemu-vexpress-a9/SConstruct
@@ -19,6 +19,7 @@ env = Environment(tools = ['mingw'],
     AR   = rtconfig.AR, ARFLAGS = '-rc',
     LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
 
 Export('RTT_ROOT')
 Export('rtconfig')
diff --git a/bsp/qemu-vexpress-gemini/SConstruct b/bsp/qemu-vexpress-gemini/SConstruct
index 6fa1553e4d..765abd555a 100644
--- a/bsp/qemu-vexpress-gemini/SConstruct
+++ b/bsp/qemu-vexpress-gemini/SConstruct
@@ -13,11 +13,12 @@ from building import *
 TARGET = 'rtthread-vexpress.' + rtconfig.TARGET_EXT
 
 env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
 
 Export('RTT_ROOT')
 Export('rtconfig')
diff --git a/bsp/realview-a8/SConstruct b/bsp/realview-a8/SConstruct
index 67ae413023..0885dbfc0e 100644
--- a/bsp/realview-a8/SConstruct
+++ b/bsp/realview-a8/SConstruct
@@ -13,11 +13,12 @@ from building import *
 TARGET = 'rtthread-realview.' + rtconfig.TARGET_EXT
 
 env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
 
 Export('RTT_ROOT')
 Export('rtconfig')
diff --git a/libcpu/SConscript b/libcpu/SConscript
index 568da67cc9..774e7f4043 100644
--- a/libcpu/SConscript
+++ b/libcpu/SConscript
@@ -1,38 +1,15 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-arch = rtconfig.ARCH
-comm = rtconfig.ARCH + '/common'
-path = rtconfig.ARCH + '/' + rtconfig.CPU
-src  = []
-ASFLAGS = ''
-
-# The set of source files associated with this SConscript file.
-if rtconfig.PLATFORM == 'armcc':
-    src += Glob(path + '/*.c') + Glob(path + '/*_rvds.S') 
-    src += Glob(comm + '/*.c') + Glob(comm + '/*_rvds.S')
-
-if rtconfig.PLATFORM == 'gcc':
-    src += Glob(path + '/*_init.S')
-    src += Glob(path + '/*.c') + Glob(path + '/*_gcc.S') 
-    src += Glob(comm + '/*.c') + Glob(comm + '/*_gcc.S')
+# RT-Thread building script for bridge
 
-if rtconfig.PLATFORM == 'iar':
-    src += Glob(path + '/*.c') + Glob(path + '/*_iar.S')
-    src += Glob(comm + '/*.c') + Glob(comm + '/*_iar.S')
-
-if rtconfig.PLATFORM == 'cl':
-    src = Glob(path + '/*.c')
-
-if rtconfig.PLATFORM == 'mingw':
-    src = Glob(path + '/*.c')
+import os
+from building import *
 
-if rtconfig.PLATFORM == 'armcc' and rtconfig.ARCH == 'arm' and rtconfig.CPU == 'arm926':
-    ASFLAGS = ' --cpreproc'
+Import('rtconfig')
 
-CPPPATH = [RTT_ROOT + '/libcpu/' + arch + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + arch + '/common']
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
 
-group = DefineGroup(rtconfig.CPU.upper(), src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+if rtconfig.ARCH in list:
+    group = group + SConscript(os.path.join(cwd, rtconfig.ARCH, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/arm/AT91SAM7S/SConscript b/libcpu/arm/AT91SAM7S/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/AT91SAM7S/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/AT91SAM7S/context_rvds.S b/libcpu/arm/AT91SAM7S/context_rvds.S
index 641ec7a6b1..78e3df9736 100644
--- a/libcpu/arm/AT91SAM7S/context_rvds.S
+++ b/libcpu/arm/AT91SAM7S/context_rvds.S
@@ -1,43 +1,39 @@
-;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date           Author       Notes
-; * 2009-01-20     Bernard      first version
-; */
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-20     Bernard      first version
+ */
 
 NOINT	EQU		0xc0	; disable interrupt in psr
 
-	AREA |.text|, CODE, READONLY, ALIGN=2
-	ARM
-	REQUIRE8
-	PRESERVE8
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    ARM
+    REQUIRE8
+    PRESERVE8
 
 ;/*
 ; * rt_base_t rt_hw_interrupt_disable();
 ; */
 rt_hw_interrupt_disable	PROC
-	EXPORT rt_hw_interrupt_disable
-	MRS r0, cpsr
-	ORR r1, r0, #NOINT
-	MSR cpsr_c, r1
-	BX	lr
-	ENDP
+    EXPORT rt_hw_interrupt_disable
+    MRS r0, cpsr
+    ORR r1, r0, #NOINT
+    MSR cpsr_c, r1
+    BX	lr
+    ENDP
 
 ;/*
 ; * void rt_hw_interrupt_enable(rt_base_t level);
 ; */
 rt_hw_interrupt_enable	PROC
-	EXPORT rt_hw_interrupt_enable
-	MSR cpsr_c, r0
-	BX	lr
-	ENDP
+    EXPORT rt_hw_interrupt_enable
+    MSR cpsr_c, r0
+    BX	lr
+    ENDP
 
 ;/*
 ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
@@ -45,63 +41,63 @@ rt_hw_interrupt_enable	PROC
 ; * r1 --> to
 ; */
 rt_hw_context_switch	PROC
-	EXPORT rt_hw_context_switch
-	STMFD	sp!, {lr}			; push pc (lr should be pushed in place of PC)
-	STMFD	sp!, {r0-r12, lr}	; push lr & register file
+    EXPORT rt_hw_context_switch
+    STMFD	sp!, {lr}			; push pc (lr should be pushed in place of PC)
+    STMFD	sp!, {r0-r12, lr}	; push lr & register file
 
-	MRS		r4, cpsr
-	STMFD	sp!, {r4}			; push cpsr
-	MRS		r4, spsr
-	STMFD	sp!, {r4}			; push spsr
+    MRS		r4, cpsr
+    STMFD	sp!, {r4}			; push cpsr
+    MRS		r4, spsr
+    STMFD	sp!, {r4}			; push spsr
 
-	STR	sp, [r0]				; store sp in preempted tasks TCB
-	LDR	sp, [r1]				; get new task stack pointer
+    STR	sp, [r0]				; store sp in preempted tasks TCB
+    LDR	sp, [r1]				; get new task stack pointer
 
-	LDMFD	sp!, {r4}			; pop new task spsr
-	MSR	spsr_cxsf, r4
-	LDMFD	sp!, {r4}			; pop new task cpsr
-	MSR	cpsr_cxsf, r4
+    LDMFD	sp!, {r4}			; pop new task spsr
+    MSR	spsr_cxsf, r4
+    LDMFD	sp!, {r4}			; pop new task cpsr
+    MSR	cpsr_cxsf, r4
 
-	LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
-	ENDP
+    LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
+    ENDP
 
 ;/*
 ; * void rt_hw_context_switch_to(rt_uint32 to);
 ; * r0 --> to
 ; */
 rt_hw_context_switch_to	PROC
-	EXPORT rt_hw_context_switch_to
-	LDR	sp, [r0]				; get new task stack pointer
+    EXPORT rt_hw_context_switch_to
+    LDR	sp, [r0]				; get new task stack pointer
 
-	LDMFD	sp!, {r4}			; pop new task spsr
-	MSR	spsr_cxsf, r4
-	LDMFD	sp!, {r4}			; pop new task cpsr
-	MSR	cpsr_cxsf, r4
+    LDMFD	sp!, {r4}			; pop new task spsr
+    MSR	spsr_cxsf, r4
+    LDMFD	sp!, {r4}			; pop new task cpsr
+    MSR	cpsr_cxsf, r4
 
-	LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
-	ENDP
+    LDMFD	sp!, {r0-r12, lr, pc}	; pop new task r0-r12, lr & pc
+    ENDP
 
 ;/*
 ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
 ; */
-	IMPORT rt_thread_switch_interrupt_flag
-	IMPORT rt_interrupt_from_thread
-	IMPORT rt_interrupt_to_thread
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
 
 rt_hw_context_switch_interrupt	PROC
-	EXPORT rt_hw_context_switch_interrupt
-	LDR r2, =rt_thread_switch_interrupt_flag
-	LDR r3, [r2]
-	CMP r3, #1
-	BEQ _reswitch
-	MOV r3, #1							; set rt_thread_switch_interrupt_flag to 1
-	STR r3, [r2]
-	LDR r2, =rt_interrupt_from_thread	; set rt_interrupt_from_thread
-	STR r0, [r2]
+    EXPORT rt_hw_context_switch_interrupt
+    LDR r2, =rt_thread_switch_interrupt_flag
+    LDR r3, [r2]
+    CMP r3, #1
+    BEQ _reswitch
+    MOV r3, #1							; set rt_thread_switch_interrupt_flag to 1
+    STR r3, [r2]
+    LDR r2, =rt_interrupt_from_thread	; set rt_interrupt_from_thread
+    STR r0, [r2]
 _reswitch
-	LDR r2, =rt_interrupt_to_thread		; set rt_interrupt_to_thread
-	STR r1, [r2]
-	BX	lr
-	ENDP
+    LDR r2, =rt_interrupt_to_thread		; set rt_interrupt_to_thread
+    STR r1, [r2]
+    BX	lr
+    ENDP
 
-	END
\ No newline at end of file
+    END
\ No newline at end of file
diff --git a/libcpu/arm/AT91SAM7X/SConscript b/libcpu/arm/AT91SAM7X/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/AT91SAM7X/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/AT91SAM7X/context_rvds.S b/libcpu/arm/AT91SAM7X/context_rvds.S
index 641ec7a6b1..0d8bf56237 100644
--- a/libcpu/arm/AT91SAM7X/context_rvds.S
+++ b/libcpu/arm/AT91SAM7X/context_rvds.S
@@ -1,16 +1,12 @@
-;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date           Author       Notes
-; * 2009-01-20     Bernard      first version
-; */
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-20     Bernard      first version
+ */
 
 NOINT	EQU		0xc0	; disable interrupt in psr
 
diff --git a/libcpu/arm/SConscript b/libcpu/arm/SConscript
new file mode 100644
index 0000000000..36a214327b
--- /dev/null
+++ b/libcpu/arm/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/arm/am335x/SConscript b/libcpu/arm/am335x/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/am335x/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/arm926/SConscript b/libcpu/arm/arm926/SConscript
new file mode 100644
index 0000000000..00785a135b
--- /dev/null
+++ b/libcpu/arm/arm926/SConscript
@@ -0,0 +1,25 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+    ASFLAGS = ' --cpreproc'
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/arm/arm926/context_gcc.S b/libcpu/arm/arm926/context_gcc.S
index 5152618d24..b6b7863679 100644
--- a/libcpu/arm/arm926/context_gcc.S
+++ b/libcpu/arm/arm926/context_gcc.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/arm926/context_iar.S b/libcpu/arm/arm926/context_iar.S
index 14110e5220..902552734e 100644
--- a/libcpu/arm/arm926/context_iar.S
+++ b/libcpu/arm/arm926/context_iar.S
@@ -1,27 +1,13 @@
-;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
-; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-; *
-; * Change Logs:
-; * Date           Author       Notes
-; * 2011-08-14     weety      copy from mini2440
-; * 2015-04-15     ArdaFu     convert from context_gcc.s
-; */
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-08-14     weety    copy from mini2440
+ * 2015-04-15     ArdaFu     convert from context_gcc.s
+ */
 
 #define NOINT            0xc0
 
diff --git a/libcpu/arm/arm926/context_rvds.S b/libcpu/arm/arm926/context_rvds.S
index 32bd235fef..03eff68d4c 100644
--- a/libcpu/arm/arm926/context_rvds.S
+++ b/libcpu/arm/arm926/context_rvds.S
@@ -1,24 +1,10 @@
 ;/*
-; * file      : context_rvds.s
-; * this file is part of rt-thread rtos
-; * copyright (c) 2006, rt-thread development team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  this program is free software; you can redistribute it and/or modify
-; *  it under the terms of the gnu general public license as published by
-; *  the free software foundation; either version 2 of the license, or
-; *  (at your option) any later version.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
-; *  this program is distributed in the hope that it will be useful,
-; *  but without any warranty; without even the implied warranty of
-; *  merchantability or fitness for a particular purpose.  see the
-; *  gnu general public license for more details.
-; *
-; *  you should have received a copy of the gnu general public license along
-; *  with this program; if not, write to the free software foundation, inc.,
-; *  51 franklin street, fifth floor, boston, ma 02110-1301 usa.
-; *
-; * change logs:
-; * date           author       notes
+; * Change Logs:
+; * Date           Author       Notes
 ; * 2011-08-14     weety    copy from mini2440
 ; */
 
diff --git a/libcpu/arm/arm926/start_iar.S b/libcpu/arm/arm926/start_iar.S
index 880f2d9706..080acd57b6 100644
--- a/libcpu/arm/arm926/start_iar.S
+++ b/libcpu/arm/arm926/start_iar.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : start.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/arm926/start_rvds.S b/libcpu/arm/arm926/start_rvds.S
index aca0e4577f..fc7e84ffaa 100644
--- a/libcpu/arm/arm926/start_rvds.S
+++ b/libcpu/arm/arm926/start_rvds.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : start_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
@@ -25,7 +11,6 @@
 ; * 2015-06-04     aozima     Align stack address to 8 byte.
 ; */
 
-;#include "rt_low_level_init.h"
 UND_STK_SIZE EQU 512
 SVC_STK_SIZE EQU 4096
 ABT_STK_SIZE EQU 512
@@ -35,25 +20,7 @@ SYS_STK_SIZE EQU 512
 Heap_Size    EQU 512
 
 S_FRAME_SIZE    EQU     (18*4)   ;72
-;S_SPSR          EQU     (17*4)   ;SPSR
-;S_CPSR          EQU     (16*4)   ;CPSR
 S_PC            EQU     (15*4)   ;R15
-;S_LR            EQU     (14*4)   ;R14
-;S_SP            EQU     (13*4)   ;R13
-
-;S_IP            EQU     (12*4)   ;R12
-;S_FP            EQU     (11*4)   ;R11
-;S_R10           EQU     (10*4)
-;S_R9            EQU     (9*4)
-;S_R8            EQU     (8*4)
-;S_R7            EQU     (7*4)
-;S_R6            EQU     (6*4)
-;S_R5            EQU     (5*4)
-;S_R4            EQU     (4*4)
-;S_R3            EQU     (3*4)
-;S_R2            EQU     (2*4)
-;S_R1            EQU     (1*4)
-;S_R0            EQU     (0*4)
 
 MODE_USR        EQU     0X10
 MODE_FIQ        EQU     0X11
diff --git a/libcpu/arm/armv6/SConscript b/libcpu/arm/armv6/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/armv6/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/common/SConscript b/libcpu/arm/common/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/common/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c
index f61c69ef01..4fc87b20d1 100644
--- a/libcpu/arm/common/backtrace.c
+++ b/libcpu/arm/common/backtrace.c
@@ -13,51 +13,51 @@
 #ifdef __GNUC__
 /*
 -->High Address,Stack Top
-PC<-----|
-LR	 	 |
-IP	 	 |
-FP	 	 |
-......		 |
-PC<-|	 |
-LR	 |	 |
-IP	 |	 |
+PC<------|
+LR       |
+IP       |
+FP       |
+......   |
+PC <-|   |
+LR   |   |
+IP   |   |
 FP---|-- |
-......	 |
-PC	 |
-LR	 |
-IP 	 |
+......   |
+PC       |
+LR       |
+IP       |
 FP---
 -->Low Address,Stack Bottom
 */
 void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
 {
-	rt_uint32_t i, pc, func_entry;
+    rt_uint32_t i, pc, func_entry;
 
-	pc = *fp;
-	rt_kprintf("[0x%x]\n", pc-0xC);
+    pc = *fp;
+    rt_kprintf("[0x%x]\n", pc-0xC);
 
-	for(i=0; i<10; i++)
-	{
-		fp = (rt_uint32_t *)*(fp - 3);
-		pc = *fp ;
+    for(i=0; i<10; i++)
+    {
+        fp = (rt_uint32_t *)*(fp - 3);
+        pc = *fp ;
 
-		func_entry = pc - 0xC;
+        func_entry = pc - 0xC;
 
-		if(func_entry <= 0x30000000) break;
+        if(func_entry <= 0x30000000) break;
 
-		if(func_entry == thread_entry)
-		{
-			rt_kprintf("EntryPoint:0x%x\n", func_entry);
+        if(func_entry == thread_entry)
+        {
+            rt_kprintf("EntryPoint:0x%x\n", func_entry);
 
-			break;
-		}
+            break;
+        }
 
-		rt_kprintf("[0x%x]\n", func_entry);
-	}
+        rt_kprintf("[0x%x]\n", func_entry);
+    }
 }
 #else
 void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
 {
-	/* old compiler implementation */
+    /* old compiler implementation */
 }
 #endif
diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/cortex-a/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m0/SConscript b/libcpu/arm/cortex-m0/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/cortex-m0/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S
index 67ea808d8c..50d3781359 100644
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S
index bf68592e63..fb9ce9b4bf 100644
--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m3/SConscript b/libcpu/arm/cortex-m3/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/cortex-m3/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m3/context_iar.S b/libcpu/arm/cortex-m3/context_iar.S
index 95dee8062d..91645c48b3 100644
--- a/libcpu/arm/cortex-m3/context_iar.S
+++ b/libcpu/arm/cortex-m3/context_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S
index 9a7ff10abe..a2a7f41a27 100644
--- a/libcpu/arm/cortex-m3/context_rvds.S
+++ b/libcpu/arm/cortex-m3/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m4/SConscript b/libcpu/arm/cortex-m4/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/cortex-m4/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S
index bf707d0d53..06b8c7f884 100644
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m7/SConscript b/libcpu/arm/cortex-m7/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/cortex-m7/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m7/context_iar.S b/libcpu/arm/cortex-m7/context_iar.S
index bf707d0d53..06b8c7f884 100644
--- a/libcpu/arm/cortex-m7/context_iar.S
+++ b/libcpu/arm/cortex-m7/context_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-m7/context_rvds.S b/libcpu/arm/cortex-m7/context_rvds.S
index 1abe477eab..ea9e9cb8b3 100644
--- a/libcpu/arm/cortex-m7/context_rvds.S
+++ b/libcpu/arm/cortex-m7/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/cortex-r4/SConscript b/libcpu/arm/cortex-r4/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/cortex-r4/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-r4/context_ccs.asm b/libcpu/arm/cortex-r4/context_ccs.asm
index 2b459f8238..9463556743 100644
--- a/libcpu/arm/cortex-r4/context_ccs.asm
+++ b/libcpu/arm/cortex-r4/context_ccs.asm
@@ -1,14 +1,10 @@
 ;/*
-; * File      : context_ccs.asm
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
-; * Date       Author       Notes
+; * Date           Author       Notes
 ; * 2009-01-20     Bernard      first version
 ; * 2011-07-22     Bernard      added thumb mode porting
 ; * 2013-05-24     Grissiom     port to CCS
diff --git a/libcpu/arm/dm36x/SConscript b/libcpu/arm/dm36x/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/dm36x/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/dm36x/context_rvds.S b/libcpu/arm/dm36x/context_rvds.S
index 631da83372..8e0fc4465b 100644
--- a/libcpu/arm/dm36x/context_rvds.S
+++ b/libcpu/arm/dm36x/context_rvds.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/lpc214x/SConscript b/libcpu/arm/lpc214x/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/lpc214x/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/lpc214x/context_rvds.S b/libcpu/arm/lpc214x/context_rvds.S
index 762b67d42e..47ca31cd1f 100644
--- a/libcpu/arm/lpc214x/context_rvds.S
+++ b/libcpu/arm/lpc214x/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/lpc24xx/SConscript b/libcpu/arm/lpc24xx/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/lpc24xx/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/lpc24xx/context_rvds.S b/libcpu/arm/lpc24xx/context_rvds.S
index ecd20e4bbe..0d9915f4f1 100644
--- a/libcpu/arm/lpc24xx/context_rvds.S
+++ b/libcpu/arm/lpc24xx/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/realview-a8-vmm/SConscript b/libcpu/arm/realview-a8-vmm/SConscript
index 61057c04cc..9ff30a796b 100644
--- a/libcpu/arm/realview-a8-vmm/SConscript
+++ b/libcpu/arm/realview-a8-vmm/SConscript
@@ -1,17 +1,23 @@
-Import('rtconfig')
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src	= Glob('*.c')
+src     = Glob('*.c') + Glob('*.cpp')
 CPPPATH = [cwd]
 
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
 if rtconfig.PLATFORM == 'iar':
-        src += Glob('*_iar.S')
-elif rtconfig.PLATFORM == 'gcc':
-        src += Glob('*_gcc.S')
-elif rtconfig.PLATFORM == 'armcc':
-        src += Glob('*_rvds.S')
+    src += Glob('*_iar.S')
 
-group = DefineGroup('AM335x', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/libcpu/arm/s3c24x0/SConscript b/libcpu/arm/s3c24x0/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/s3c24x0/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/s3c24x0/context_rvds.S b/libcpu/arm/s3c24x0/context_rvds.S
index 54d655afe1..9078f6173a 100644
--- a/libcpu/arm/s3c24x0/context_rvds.S
+++ b/libcpu/arm/s3c24x0/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/s3c44b0/SConscript b/libcpu/arm/s3c44b0/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/s3c44b0/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/s3c44b0/context_rvds.S b/libcpu/arm/s3c44b0/context_rvds.S
index 641ec7a6b1..27ebf8f5e3 100644
--- a/libcpu/arm/s3c44b0/context_rvds.S
+++ b/libcpu/arm/s3c44b0/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/sep4020/SConscript b/libcpu/arm/sep4020/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/sep4020/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/sep4020/context_rvds.S b/libcpu/arm/sep4020/context_rvds.S
index 641ec7a6b1..27ebf8f5e3 100644
--- a/libcpu/arm/sep4020/context_rvds.S
+++ b/libcpu/arm/sep4020/context_rvds.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2018, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript
index 2ad51b573e..9ff30a796b 100644
--- a/libcpu/arm/zynq7000/SConscript
+++ b/libcpu/arm/zynq7000/SConscript
@@ -1,17 +1,23 @@
-Import('rtconfig')
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src	= Glob('*.c')
+src     = Glob('*.c') + Glob('*.cpp')
 CPPPATH = [cwd]
 
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
 if rtconfig.PLATFORM == 'iar':
-        src += Glob('*_iar.S')
-elif rtconfig.PLATFORM == 'gcc':
-        src += Glob('*_gcc.S')
-elif rtconfig.PLATFORM == 'armcc':
-        src += Glob('*_rvds.S')
+    src += Glob('*_iar.S')
 
-group = DefineGroup('AM1808', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/libcpu/arm/zynq7000/context_gcc.S b/libcpu/arm/zynq7000/context_gcc.S
index 3dbf3c861d..98f98a0244 100644
--- a/libcpu/arm/zynq7000/context_gcc.S
+++ b/libcpu/arm/zynq7000/context_gcc.S
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, Shanghai Real-Thread Technology Co., Ltd
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-20     Bernard      first version
  */
 
 #define NOINT           0xc0
diff --git a/libcpu/arm/zynq7000/cp15.h b/libcpu/arm/zynq7000/cp15.h
index bd6a23f1b2..75d81736ab 100644
--- a/libcpu/arm/zynq7000/cp15.h
+++ b/libcpu/arm/zynq7000/cp15.h
@@ -1,25 +1,16 @@
-#ifndef __CP15_H__
-#define __CP15_H__
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
+#ifndef __CP15_H__
+#define __CP15_H__
+
 unsigned long rt_cpu_get_smp_id(void);
 
 void rt_cpu_mmu_disable(void);
diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c
index 498446db43..e23a359e6e 100644
--- a/libcpu/arm/zynq7000/gic.c
+++ b/libcpu/arm/zynq7000/gic.c
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
 #include <rtthread.h>
diff --git a/libcpu/arm/zynq7000/gic.h b/libcpu/arm/zynq7000/gic.h
index 4b89538948..8fcdf05f6f 100644
--- a/libcpu/arm/zynq7000/gic.h
+++ b/libcpu/arm/zynq7000/gic.h
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
 #ifndef __GIC_H__
diff --git a/libcpu/arm/zynq7000/interrupt.h b/libcpu/arm/zynq7000/interrupt.h
index 07eafc84e5..da266c42a2 100644
--- a/libcpu/arm/zynq7000/interrupt.h
+++ b/libcpu/arm/zynq7000/interrupt.h
@@ -1,25 +1,16 @@
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
 void rt_hw_interrupt_clear(int vector);
 
 #endif /* end of include guard: __INTERRUPT_H__ */
diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c
index 2a58fabe4f..fbdacca10f 100644
--- a/libcpu/arm/zynq7000/mmu.c
+++ b/libcpu/arm/zynq7000/mmu.c
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
 #include <rtthread.h>
diff --git a/libcpu/arm/zynq7000/trap.c b/libcpu/arm/zynq7000/trap.c
index 9bf58f916c..6243ea82b4 100644
--- a/libcpu/arm/zynq7000/trap.c
+++ b/libcpu/arm/zynq7000/trap.c
@@ -1,21 +1,11 @@
 /*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
  */
 
 #include <rtthread.h>
diff --git a/libcpu/avr32/SConscript b/libcpu/avr32/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/avr32/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/avr32/uc3/SConscript b/libcpu/avr32/uc3/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/avr32/uc3/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/blackfin/SConscript b/libcpu/blackfin/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/blackfin/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/blackfin/bf53x/SConscript b/libcpu/blackfin/bf53x/SConscript
new file mode 100644
index 0000000000..af9ba4bc81
--- /dev/null
+++ b/libcpu/blackfin/bf53x/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_vdsp.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/c-sky/SConscript b/libcpu/c-sky/SConscript
new file mode 100644
index 0000000000..36a214327b
--- /dev/null
+++ b/libcpu/c-sky/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/c-sky/ck802/SConscript b/libcpu/c-sky/ck802/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/c-sky/ck802/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/c-sky/common/SConscript b/libcpu/c-sky/common/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/c-sky/common/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/ia32/SConscript b/libcpu/ia32/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/ia32/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/m16c/SConscript b/libcpu/m16c/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/m16c/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/m16c/m16c62p/SConscript b/libcpu/m16c/m16c62p/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/m16c/m16c62p/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/SConscript b/libcpu/mips/SConscript
new file mode 100644
index 0000000000..ced01a4b3e
--- /dev/null
+++ b/libcpu/mips/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/mips/common/SConscript b/libcpu/mips/common/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/common/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/loongson_1b/SConscript b/libcpu/mips/loongson_1b/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/loongson_1b/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/loongson_1c/SConscript b/libcpu/mips/loongson_1c/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/loongson_1c/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/pic32/SConscript b/libcpu/mips/pic32/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/pic32/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/x1000/SConscript b/libcpu/mips/x1000/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/x1000/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/xburst/SConscript.1 b/libcpu/mips/xburst/SConscript.1
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/xburst/SConscript.1
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/nios/SConscript b/libcpu/nios/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/nios/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/nios/nios_ii/SConscript b/libcpu/nios/nios_ii/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/nios/nios_ii/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/ppc/SConscript b/libcpu/ppc/SConscript
new file mode 100644
index 0000000000..36a214327b
--- /dev/null
+++ b/libcpu/ppc/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/ppc/common/SConscript b/libcpu/ppc/common/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/ppc/common/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h
index d60e7fdcef..72ef31bfbc 100644
--- a/libcpu/ppc/common/ptrace.h
+++ b/libcpu/ppc/common/ptrace.h
@@ -21,20 +21,20 @@
 #define PPC_REG unsigned long
 
 struct pt_regs {
-	PPC_REG gpr[32];
-	PPC_REG nip;
-	PPC_REG msr;
-	PPC_REG orig_gpr3;	/* Used for restarting system calls */
-	PPC_REG ctr;
-	PPC_REG link;
-	PPC_REG xer;
-	PPC_REG ccr;
-	PPC_REG mq;		/* 601 only (not used at present) */
-				    /* Used on APUS to hold IPL value. */
-	PPC_REG trap;		/* Reason for being here */
-	PPC_REG dar;		/* Fault registers */
-	PPC_REG dsisr;
-	PPC_REG result;		/* Result of a system call */
+    PPC_REG gpr[32];
+    PPC_REG nip;
+    PPC_REG msr;
+    PPC_REG orig_gpr3;	/* Used for restarting system calls */
+    PPC_REG ctr;
+    PPC_REG link;
+    PPC_REG xer;
+    PPC_REG ccr;
+    PPC_REG mq;		/* 601 only (not used at present) */
+                    /* Used on APUS to hold IPL value. */
+    PPC_REG trap;		/* Reason for being here */
+    PPC_REG dar;		/* Fault registers */
+    PPC_REG dsisr;
+    PPC_REG result;		/* Result of a system call */
 }__attribute__((packed)) CELL_STACK_FRAME_t;
 #endif
 
diff --git a/libcpu/ppc/ppc405/SConscript b/libcpu/ppc/ppc405/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/ppc/ppc405/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
new file mode 100644
index 0000000000..36a214327b
--- /dev/null
+++ b/libcpu/risc-v/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/risc-v/common/SConscript b/libcpu/risc-v/common/SConscript
new file mode 100644
index 0000000000..2f698f530a
--- /dev/null
+++ b/libcpu/risc-v/common/SConscript
@@ -0,0 +1,12 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/e310/SConscript b/libcpu/risc-v/e310/SConscript
index 4e4bc0c3d9..b0ae20ba02 100644
--- a/libcpu/risc-v/e310/SConscript
+++ b/libcpu/risc-v/e310/SConscript
@@ -1,13 +1,14 @@
-Import('rtconfig')
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src     = Glob('*.c')
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
 CPPPATH = [cwd]
+ASFLAGS = ''
 
-if rtconfig.PLATFORM == 'gcc':
-    src += Glob('*_gcc.S')
-
-group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
 
 Return('group')
diff --git a/libcpu/risc-v/k210/SConscript b/libcpu/risc-v/k210/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/risc-v/k210/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/rv32m1/SConscript b/libcpu/risc-v/rv32m1/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/risc-v/rv32m1/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/rx/SConscript b/libcpu/rx/SConscript
new file mode 100644
index 0000000000..e5890498c9
--- /dev/null
+++ b/libcpu/rx/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_iar.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/sim/SConscript b/libcpu/sim/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/sim/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/sim/posix/SConscript b/libcpu/sim/posix/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/sim/posix/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/sim/win32/SConscript b/libcpu/sim/win32/SConscript
new file mode 100644
index 0000000000..afab42d47c
--- /dev/null
+++ b/libcpu/sim/win32/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/ti-dsp/SConscript b/libcpu/ti-dsp/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/ti-dsp/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/ti-dsp/c28x/SConscript b/libcpu/ti-dsp/c28x/SConscript
new file mode 100644
index 0000000000..08b274341b
--- /dev/null
+++ b/libcpu/ti-dsp/c28x/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.s')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/unicore32/SConscript b/libcpu/unicore32/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/unicore32/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/unicore32/sep6200/SConscript b/libcpu/unicore32/sep6200/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/unicore32/sep6200/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/v850/70f34/SConscript b/libcpu/v850/70f34/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/v850/70f34/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/v850/SConscript b/libcpu/v850/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/v850/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/xilinx/SConscript b/libcpu/xilinx/SConscript
new file mode 100644
index 0000000000..ebdd1357ee
--- /dev/null
+++ b/libcpu/xilinx/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/xilinx/microblaze/SConscript b/libcpu/xilinx/microblaze/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/xilinx/microblaze/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
-- 
cgit v1.3.1


From 4c0aafb57f508db9bba73eae7ab9c6a4c1adf231 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Mon, 7 Jan 2019 09:20:30 +0800
Subject: [libcpu] Fix the SCoscript issue in cpu/MIPS.

---
 libcpu/mips/SConscript | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/SConscript b/libcpu/mips/SConscript
index ced01a4b3e..36a214327b 100644
--- a/libcpu/mips/SConscript
+++ b/libcpu/mips/SConscript
@@ -3,7 +3,7 @@
 import os
 from building import *
 
-import('rtconfig')
+Import('rtconfig')
 
 cwd   = GetCurrentDir()
 group = []
-- 
cgit v1.3.1


From 3a3c6c51f890fd4ee5fac446778c6beea24ebd26 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Mon, 7 Jan 2019 21:16:05 +0800
Subject: [libcpu] remove cache.h from mips/common folder.

---
 libcpu/mips/common/cache.h | 232 ---------------------------------------------
 1 file changed, 232 deletions(-)
 delete mode 100644 libcpu/mips/common/cache.h

(limited to 'libcpu')

diff --git a/libcpu/mips/common/cache.h b/libcpu/mips/common/cache.h
deleted file mode 100644
index 1c7cf41324..0000000000
--- a/libcpu/mips/common/cache.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Cache operations for the cache instruction.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
- * (C) Copyright 1999 Silicon Graphics, Inc.
- */
-#ifndef __CACHE_H__
-#define __CACHE_H__
-
-
-#define KUSEG           		0x00000000
-#define KSEG0           		0x80000000
-#define KSEG1           		0xa0000000
-#define KSEG2           		0xc0000000
-#define KSEG3           		0xe0000000
-
-/*
- * Cache Operations available on all MIPS processors with R4000-style caches
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Writeback_Inv_D		0x15
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-
-/*
- *The lock state is cleared by executing an Index
-Invalidate, Index Writeback Invalidate, Hit
-Invalidate, or Hit Writeback Invalidate
-operation to the locked line, or via an Index
-Store Tag operation with the lock bit reset in
-the TagLo register.
- */
-#define Fetch_And_Lock_I  		0x1c
-#define Fetch_And_Lock_D  		0x1d
-/*
- * R4000-specific cacheops
- */
-#define Create_Dirty_Excl_D		0x0d
-#define Fill					0x14
-
-/*
- * R4000SC and R4400SC-specific cacheops
- */
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_SD		0x1b
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-/*
- * R5000-specific cacheops
- */
-#define R5K_Page_Invalidate_S	0x17
-
-/*
- * RM7000-specific cacheops
- */
-#define Page_Invalidate_T		0x16
-
-/*
- * R1000-specific cacheops
- *
- * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
- * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
- */
-#define Index_Writeback_Inv_S	0x03
-#define Index_Load_Tag_S		0x07
-#define Index_Store_Tag_S		0x0B
-#define Hit_Invalidate_S		0x13
-#define Cache_Barrier			0x14
-#define Hit_Writeback_Inv_S		0x17
-#define Index_Load_Data_I		0x18
-#define Index_Load_Data_D		0x19
-#define Index_Load_Data_S		0x1b
-#define Index_Store_Data_I		0x1c
-#define Index_Store_Data_D		0x1d
-#define Index_Store_Data_S		0x1f
-
-
-#ifndef __ASSEMBLER__
-
-#ifndef dcache_size
-#define dcache_size	(g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
-#endif
-
-#ifndef icache_size
-#define icache_size	(g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
-#endif
-
-#ifndef cpu_dcache_line_size
-#define cpu_dcache_line_size()	g_mips_core.icache_line_size
-#endif
-
-#ifndef cpu_icache_line_size
-#define cpu_icache_line_size()	g_mips_core.icache_line_size
-#endif
-
-#define cache_op(op, addr)						\
-	__asm__ __volatile__(						\
-	"	.set	noreorder				\n"	\
-	"	.set	mips3\n\t				\n"	\
-	"	cache	%0, %1					\n"	\
-	"	.set	mips0					\n"	\
-	"	.set	reorder"					\
-	:								\
-	: "i" (op), "m" (*(unsigned char *)(addr)))
-
-#define cache16_unroll32(base, op)					\
-	__asm__ __volatile__(						\
-	"	.set noreorder					\n"	\
-	"	.set mips3					\n"	\
-	"	cache %1, 0x000(%0); cache %1, 0x010(%0)	\n"	\
-	"	cache %1, 0x020(%0); cache %1, 0x030(%0)	\n"	\
-	"	cache %1, 0x040(%0); cache %1, 0x050(%0)	\n"	\
-	"	cache %1, 0x060(%0); cache %1, 0x070(%0)	\n"	\
-	"	cache %1, 0x080(%0); cache %1, 0x090(%0)	\n"	\
-	"	cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)	\n"	\
-	"	cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)	\n"	\
-	"	cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)	\n"	\
-	"	cache %1, 0x100(%0); cache %1, 0x110(%0)	\n"	\
-	"	cache %1, 0x120(%0); cache %1, 0x130(%0)	\n"	\
-	"	cache %1, 0x140(%0); cache %1, 0x150(%0)	\n"	\
-	"	cache %1, 0x160(%0); cache %1, 0x170(%0)	\n"	\
-	"	cache %1, 0x180(%0); cache %1, 0x190(%0)	\n"	\
-	"	cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)	\n"	\
-	"	cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)	\n"	\
-	"	cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)	\n"	\
-	"	.set mips0					\n"	\
-	"	.set reorder					\n"	\
-		:							\
-		: "r" (base),						\
-		  "i" (op));
-
-
-static inline void flush_icache_line_indexed(rt_ubase_t addr)
-{
-	cache_op(Index_Invalidate_I, addr);
-}
-
-static inline void flush_dcache_line_indexed(rt_ubase_t addr)
-{
-	cache_op(Index_Writeback_Inv_D, addr);
-}
-
-static inline void flush_icache_line(rt_ubase_t addr)
-{
-	cache_op(Hit_Invalidate_I, addr);
-}
-
-static inline void lock_icache_line(rt_ubase_t addr)
-{
-	cache_op(Fetch_And_Lock_I, addr);
-}
-
-static inline void lock_dcache_line(rt_ubase_t addr)
-{
-	cache_op(Fetch_And_Lock_D, addr);
-}
-
-static inline void flush_dcache_line(rt_ubase_t addr)
-{
-	cache_op(Hit_Writeback_Inv_D, addr);
-}
-
-static inline void invalidate_dcache_line(rt_ubase_t addr)
-{
-	cache_op(Hit_Invalidate_D, addr);
-}
-
-static inline void blast_dcache16(void)
-{
-	rt_ubase_t start = KSEG0;
-	rt_ubase_t end = start + dcache_size;
-	rt_ubase_t addr;
-
-	for (addr = start; addr < end; addr += 0x200)
-		cache16_unroll32(addr, Index_Writeback_Inv_D);
-}
-
-static inline void inv_dcache16(void)
-{
-	rt_ubase_t start = KSEG0;
-	rt_ubase_t end = start + dcache_size;
-	rt_ubase_t addr;
-
-	for (addr = start; addr < end; addr += 0x200)
-		cache16_unroll32(addr, Hit_Invalidate_D);
-}
-
-static inline void blast_icache16(void)
-{
-	rt_ubase_t start = KSEG0;
-	rt_ubase_t end = start + icache_size;
-	rt_ubase_t addr;
-
-	for (addr = start; addr < end; addr += 0x200)
-		cache16_unroll32(addr, Index_Invalidate_I);
-}
-
-
-
-void r4k_cache_init(void);
-void r4k_cache_flush_all(void);
-void r4k_icache_flush_all(void);
-void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
-void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
-void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
-void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
-
-#endif /*end of __ASSEMBLER__ */
-
-#endif /* end of __CACHE_H__ */
-- 
cgit v1.3.1


From d8aa99a29c47da520986dcd79fff9861d97ca6ed Mon Sep 17 00:00:00 2001
From: Wayne Ren <wei.ren@synopsys.com>
Date: Wed, 23 Jan 2019 17:29:54 +0800
Subject: [bsp][synopsys] add the support of synopsys arc emsk

* the initial support of synopsys designware arc processor
* the initial support of synospsy ARC EM Starter Kit
* the bsp code is based on embarc which is a common SDK for
all synopsys ARC-based boards
* use "scons --gdb" to debug emsk with em9d configuration
* for detailed board information, pls go embarc.org

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
---
 bsp/synopsys/embarc/SConscript                     |   28 +
 bsp/synopsys/embarc/arc/arc_cache.c                |  420 ++++++
 bsp/synopsys/embarc/arc/arc_exc_asm.S              |  201 +++
 bsp/synopsys/embarc/arc/arc_exception.c            |  501 +++++++
 bsp/synopsys/embarc/arc/arc_timer.c                |  211 +++
 bsp/synopsys/embarc/arc/startup/arc_cxx_support.c  |  168 +++
 bsp/synopsys/embarc/arc/startup/arc_startup.S      |  262 ++++
 .../embarc/device/designware/gpio/dw_gpio.c        |  481 ++++++
 .../embarc/device/designware/gpio/dw_gpio.h        |  145 ++
 bsp/synopsys/embarc/device/designware/iic/dw_iic.c | 1584 ++++++++++++++++++++
 bsp/synopsys/embarc/device/designware/iic/dw_iic.h |  242 +++
 .../embarc/device/designware/iic/dw_iic_hal.h      |  186 +++
 .../embarc/device/designware/iic/dw_iic_hal_cfg.h  |   82 +
 bsp/synopsys/embarc/device/designware/spi/dw_spi.c | 1337 +++++++++++++++++
 bsp/synopsys/embarc/device/designware/spi/dw_spi.h |  190 +++
 .../embarc/device/designware/spi/dw_spi_hal.h      |  141 ++
 .../embarc/device/designware/spi/dw_spi_hal_cfg.h  |   58 +
 .../embarc/device/designware/uart/dw_uart.c        |  956 ++++++++++++
 .../embarc/device/designware/uart/dw_uart.h        |  141 ++
 .../embarc/device/designware/uart/dw_uart_hal.h    |  253 ++++
 .../embarc/device/device_hal/inc/dev_common.h      |  173 +++
 .../embarc/device/device_hal/inc/dev_gpio.h        |  424 ++++++
 .../embarc/device/device_hal/inc/dev_iic.h         |  526 +++++++
 .../embarc/device/device_hal/inc/dev_spi.h         |  577 +++++++
 .../embarc/device/device_hal/inc/dev_uart.h        |  475 ++++++
 bsp/synopsys/embarc/inc/arc/arc.h                  |  436 ++++++
 bsp/synopsys/embarc/inc/arc/arc_asm_common.h       |  541 +++++++
 bsp/synopsys/embarc/inc/arc/arc_builtin.h          |  301 ++++
 bsp/synopsys/embarc/inc/arc/arc_cache.h            |  321 ++++
 bsp/synopsys/embarc/inc/arc/arc_em.h               |  133 ++
 bsp/synopsys/embarc/inc/arc/arc_exception.h        |  461 ++++++
 bsp/synopsys/embarc/inc/arc/arc_feature_config.h   |  397 +++++
 bsp/synopsys/embarc/inc/arc/arc_timer.h            |   99 ++
 bsp/synopsys/embarc/inc/embARC_debug.h             |   94 ++
 bsp/synopsys/embarc/inc/embARC_error.h             |  156 ++
 bsp/synopsys/embarc/inc/embARC_toolchain.h         |  121 ++
 bsp/synopsys/emsk_em9d/.config                     |  402 +++++
 bsp/synopsys/emsk_em9d/Kconfig                     |   26 +
 bsp/synopsys/emsk_em9d/SConscript                  |   18 +
 bsp/synopsys/emsk_em9d/SConstruct                  |   52 +
 bsp/synopsys/emsk_em9d/applications/SConscript     |   11 +
 bsp/synopsys/emsk_em9d/applications/application.c  |   29 +
 bsp/synopsys/emsk_em9d/applications/startup.c      |   71 +
 bsp/synopsys/emsk_em9d/drivers/Kconfig             |   10 +
 bsp/synopsys/emsk_em9d/drivers/SConscript          |   15 +
 bsp/synopsys/emsk_em9d/drivers/arc_core_config.h   |  229 +++
 bsp/synopsys/emsk_em9d/drivers/board.c             |  283 ++++
 bsp/synopsys/emsk_em9d/drivers/board.h             |   28 +
 bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c       |  324 ++++
 bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h       |   51 +
 bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c       |  210 +++
 bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h       |   52 +
 bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h |   39 +
 bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h     |   85 ++
 bsp/synopsys/emsk_em9d/drivers/mux.c               |   67 +
 bsp/synopsys/emsk_em9d/drivers/mux.h               |  147 ++
 bsp/synopsys/emsk_em9d/drivers/mux_hal.h           |   29 +
 bsp/synopsys/emsk_em9d/emsk_em9d.ld                |  114 ++
 bsp/synopsys/emsk_em9d/openocd.log                 |    9 +
 bsp/synopsys/emsk_em9d/rtconfig.h                  |  142 ++
 bsp/synopsys/emsk_em9d/rtconfig.py                 |   60 +
 libcpu/arc/SConscript                              |   17 +
 libcpu/arc/common/SConscript                       |   10 +
 libcpu/arc/em/SConscript                           |   17 +
 libcpu/arc/em/contex_gcc.S                         |  266 ++++
 libcpu/arc/em/cpuport.c                            |   69 +
 66 files changed, 15704 insertions(+)
 create mode 100644 bsp/synopsys/embarc/SConscript
 create mode 100644 bsp/synopsys/embarc/arc/arc_cache.c
 create mode 100644 bsp/synopsys/embarc/arc/arc_exc_asm.S
 create mode 100644 bsp/synopsys/embarc/arc/arc_exception.c
 create mode 100644 bsp/synopsys/embarc/arc/arc_timer.c
 create mode 100644 bsp/synopsys/embarc/arc/startup/arc_cxx_support.c
 create mode 100644 bsp/synopsys/embarc/arc/startup/arc_startup.S
 create mode 100644 bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c
 create mode 100644 bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h
 create mode 100644 bsp/synopsys/embarc/device/designware/iic/dw_iic.c
 create mode 100644 bsp/synopsys/embarc/device/designware/iic/dw_iic.h
 create mode 100644 bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h
 create mode 100644 bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h
 create mode 100644 bsp/synopsys/embarc/device/designware/spi/dw_spi.c
 create mode 100644 bsp/synopsys/embarc/device/designware/spi/dw_spi.h
 create mode 100644 bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h
 create mode 100644 bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h
 create mode 100644 bsp/synopsys/embarc/device/designware/uart/dw_uart.c
 create mode 100644 bsp/synopsys/embarc/device/designware/uart/dw_uart.h
 create mode 100644 bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h
 create mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_common.h
 create mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h
 create mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h
 create mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h
 create mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h
 create mode 100644 bsp/synopsys/embarc/inc/arc/arc.h
 create mode 100644 bsp/synopsys/embarc/inc/arc/arc_asm_common.h
 create mode 100644 bsp/synopsys/embarc/inc/arc/arc_builtin.h
 create mode 100644 bsp/synopsys/embarc/inc/arc/arc_cache.h
 create mode 100644 bsp/synopsys/embarc/inc/arc/arc_em.h
 create mode 100644 bsp/synopsys/embarc/inc/arc/arc_exception.h
 create mode 100644 bsp/synopsys/embarc/inc/arc/arc_feature_config.h
 create mode 100644 bsp/synopsys/embarc/inc/arc/arc_timer.h
 create mode 100644 bsp/synopsys/embarc/inc/embARC_debug.h
 create mode 100644 bsp/synopsys/embarc/inc/embARC_error.h
 create mode 100644 bsp/synopsys/embarc/inc/embARC_toolchain.h
 create mode 100644 bsp/synopsys/emsk_em9d/.config
 create mode 100644 bsp/synopsys/emsk_em9d/Kconfig
 create mode 100644 bsp/synopsys/emsk_em9d/SConscript
 create mode 100644 bsp/synopsys/emsk_em9d/SConstruct
 create mode 100644 bsp/synopsys/emsk_em9d/applications/SConscript
 create mode 100644 bsp/synopsys/emsk_em9d/applications/application.c
 create mode 100644 bsp/synopsys/emsk_em9d/applications/startup.c
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/Kconfig
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/SConscript
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/arc_core_config.h
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/board.c
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/board.h
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/mux.c
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/mux.h
 create mode 100644 bsp/synopsys/emsk_em9d/drivers/mux_hal.h
 create mode 100644 bsp/synopsys/emsk_em9d/emsk_em9d.ld
 create mode 100644 bsp/synopsys/emsk_em9d/openocd.log
 create mode 100644 bsp/synopsys/emsk_em9d/rtconfig.h
 create mode 100644 bsp/synopsys/emsk_em9d/rtconfig.py
 create mode 100644 libcpu/arc/SConscript
 create mode 100644 libcpu/arc/common/SConscript
 create mode 100644 libcpu/arc/em/SConscript
 create mode 100644 libcpu/arc/em/contex_gcc.S
 create mode 100644 libcpu/arc/em/cpuport.c

(limited to 'libcpu')

diff --git a/bsp/synopsys/embarc/SConscript b/bsp/synopsys/embarc/SConscript
new file mode 100644
index 0000000000..9e086739af
--- /dev/null
+++ b/bsp/synopsys/embarc/SConscript
@@ -0,0 +1,28 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+embarc_arc_hal_SRCS = Split("""
+arc/arc_cache.c
+arc/arc_exc_asm.S
+arc/arc_exception.c
+arc/arc_timer.c
+arc/startup/arc_cxx_support.c
+arc/startup/arc_startup.S
+device/designware/uart/dw_uart.c
+device/designware/gpio/dw_gpio.c
+""")
+
+
+ASFLAGS = ' -I' + cwd
+
+src = embarc_arc_hal_SRCS
+
+path = [cwd,
+	cwd + '/arc',
+	cwd + '/arc/startup'
+	]
+
+group = DefineGroup('embarc', src, depend = [], CPPPATH = path, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/bsp/synopsys/embarc/arc/arc_cache.c b/bsp/synopsys/embarc/arc/arc_cache.c
new file mode 100644
index 0000000000..632a3e3291
--- /dev/null
+++ b/bsp/synopsys/embarc/arc/arc_cache.c
@@ -0,0 +1,420 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_MISC_CACHE
+ * \brief implementation of cache related functions
+ */
+
+#include "inc/arc/arc_cache.h"
+
+#define DIV_ROUND_UP(x, y)  (((x) + (y) - 1) / (y))
+
+
+struct cache_config {
+	uint8_t ver;			/* version */
+	uint8_t assoc;			/* Cache Associativity */
+	uint16_t line; 			/* cache line/block size */
+	uint32_t capacity;		/* capacity */
+};
+
+
+static struct cache_config icache_config, dcache_config;
+
+/**
+ * \brief invalidate multi instruction cache lines
+ *
+ * \param[in] start_addr start address in instruction cache
+ * \param[in] size  the bytes to be invalidated
+ * \return 0, succeeded, -1, failed
+ */
+int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size)
+{
+	if (!icache_available()) return -1;
+
+	if ((size == 0) || (size > icache_config.capacity)) {
+		return -1;
+	}
+
+	uint32_t end_addr;
+	uint32_t line_size;
+	uint32_t status;
+
+	line_size = (uint32_t)(icache_config.line);
+	end_addr = start_addr + size - 1;
+	start_addr &= (uint32_t)(~(line_size - 1));
+
+	status = cpu_lock_save();
+	do {
+		_arc_aux_write(AUX_IC_IVIL, start_addr);
+		Asm("nop_s");
+		Asm("nop_s");
+		Asm("nop_s");
+		start_addr += line_size;
+	} while (start_addr <= end_addr);
+	cpu_unlock_restore(status);
+
+	return 0;
+}
+
+/**
+ * \brief lock multi lines in instruction cache
+ *
+ * \param[in] start_addr start address in instruction cache
+ * \param[in] size  the bytes to be locked
+ * \return 0, succeeded, -1, failed (cache already locked or other reasons)
+ */
+int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size)
+{
+	if (!icache_available()) return -1;
+
+	if ((size == 0) || (size > icache_config.capacity)) {
+		return -1;
+	}
+
+	uint32_t end_addr;
+	uint32_t line_size;
+	uint32_t status;
+	int32_t ercd = 0;
+
+	line_size = (uint32_t)(icache_config.line);
+	end_addr = start_addr + size - 1;
+	start_addr &= (uint32_t)(~(line_size - 1));
+
+	status = cpu_lock_save();
+	do {
+		_arc_aux_write(AUX_IC_LIL, start_addr);
+		if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
+			start_addr += line_size;
+		} else {
+			ercd = -1;	/* the operation failed */
+			break;
+		}
+	} while (start_addr <= end_addr);
+	cpu_unlock_restore(status);
+
+	return ercd;
+}
+
+/**
+ * \brief directly write icache internal ram
+ *
+ * \param[in] cache_addr, icache internal address(way+index+offset)
+ * \param[in] tag	cache tag to write (tag+lock bit+valid bit)
+ * \param[in] data	cache data to write
+ * \return 0, succeeded, -1, failed
+ */
+int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data)
+{
+	if (!icache_available()) return -1;
+
+	if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) {
+		return -1;
+	}
+	_arc_aux_write(AUX_IC_RAM_ADDR, cache_addr);
+	_arc_aux_write(AUX_IC_TAG, tag );
+	_arc_aux_write(AUX_IC_DATA, data);
+
+	return 0;
+}
+
+/**
+ * \brief directly read icache internal ram
+ *
+ * \param[in] cache_addr, icache internal address(way+index+offset)
+ * \param[out] tag	cache tag to read (tag+index+lock bit+valid bit)
+ * \param[out] data	cache data to read
+ * \return 0, succeeded, -1, failed
+ */
+int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data)
+{
+	if (!icache_available()) return -1;
+
+	if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) {
+		return -1;
+	}
+	_arc_aux_write(AUX_IC_RAM_ADDR, cache_addr);
+	*tag = _arc_aux_read(AUX_IC_TAG);
+	*data = _arc_aux_read(AUX_IC_DATA);
+
+	return 0;
+}
+
+/**
+ * \brief indirectly read icache internal ram
+ *
+ * \param[in] mem_addr, memory address
+ * \param[out] tag	cache tag to read
+ * \param[out] data	cache data to read
+ * \return 0, succeeded, -1, failed
+ */
+int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data)
+{
+	if (!icache_available()) return -1;
+
+	if (!(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS)) {
+		return -1;
+	}
+	_arc_aux_write(AUX_IC_RAM_ADDR, mem_addr);
+	if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
+		*tag = _arc_aux_read(AUX_IC_TAG);
+		*data = _arc_aux_read(AUX_IC_DATA);
+	} else {
+		return -1;	/* the specified memory is not in icache */
+	}
+	return 0;
+ }
+
+/**
+ * \brief invalidate multi data cache lines
+ *
+ * \param[in] start_addr start address in data cache
+ * \param[in] size  the bytes to be invalidated
+ * \return 0, succeeded, -1, failed
+ */
+int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size)
+{
+	if (!dcache_available()) return -1;
+
+	uint32_t end_addr;
+	uint32_t line_size;
+	uint32_t status;
+
+	if ((size == 0) || (size > dcache_config.capacity)) {
+		return -1;
+	}
+
+	line_size = (uint32_t)(dcache_config.line);
+	end_addr = start_addr + size - 1;
+	start_addr &= (uint32_t)(~(line_size - 1));
+
+	status = cpu_lock_save();
+	do {
+		_arc_aux_write(AUX_DC_IVDL, start_addr);
+		Asm("nop_s");
+		Asm("nop_s");
+		Asm("nop_s");
+		/* wait for flush completion */
+		while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
+		start_addr += line_size;
+	} while (start_addr <= end_addr);
+	cpu_unlock_restore(status);
+
+	return 0;
+
+}
+
+/**
+ * \brief flush multi lines in data cache
+ *
+ * \param[in] start_addr start address
+ * \param[in] size	the bytes to be flushed
+ * \return 0, succeeded, -1, failed
+ */
+int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size)
+{
+	if (!dcache_available()) return -1;
+
+	if ((size == 0) || (size > dcache_config.capacity)) {
+		return -1;
+	}
+
+	uint32_t end_addr;
+	uint32_t line_size;
+	uint32_t status;
+
+	line_size = (uint32_t)(dcache_config.line);
+	end_addr = start_addr + size - 1;
+	start_addr &= (uint32_t)(~(line_size - 1));
+
+	status = cpu_lock_save();
+	do {
+		_arc_aux_write(AUX_DC_FLDL, start_addr);
+		Asm("nop_s");
+		Asm("nop_s");
+		Asm("nop_s");
+		/* wait for flush completion */
+		while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
+		start_addr += line_size;
+	} while (start_addr <= end_addr);
+	cpu_unlock_restore(status);
+
+	return 0;
+}
+
+/**
+ * \brief lock multi lines in data cache
+ *
+ * \param[in] start_addr start address in data cache
+ * \param[in] size  the bytes to be locked
+ * \return 0, succeeded, -1, failed
+ */
+int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size)
+{
+	if (!dcache_available()) return -1;
+
+	if ((size == 0) || (size > dcache_config.capacity)) {
+		return -1;
+	}
+
+	uint32_t end_addr;
+	uint32_t line_size;
+	uint32_t status;
+	int32_t ercd = 0;
+
+	line_size = (uint32_t)(dcache_config.line);
+	end_addr = start_addr + size - 1;
+	start_addr &= (uint32_t)(~(line_size - 1));
+
+	status = cpu_lock_save();
+	do {
+		_arc_aux_write(AUX_DC_LDL, start_addr);
+		Asm("nop_s");
+		if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
+			start_addr += line_size;
+		} else {
+			ercd = -1;	/* the operation failed */
+			break;
+		}
+	} while (start_addr <= end_addr);
+	cpu_unlock_restore(status);
+
+	return ercd;
+}
+
+/**
+ * \brief directly write dcache internal ram
+ *
+ * \param[in] cache_addr, dcache internal address(way+index+offset)
+ * \param[in] tag	cache tag to write
+ * \param[in] data	cache data to write
+ * \return 0, succeeded, -1, failed
+ */
+int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data)
+{
+	if (!dcache_available()) return -1;
+
+	if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) {
+		return -1;
+	}
+	_arc_aux_write(AUX_DC_RAM_ADDR, cache_addr);
+	_arc_aux_write(AUX_DC_TAG, tag);
+	_arc_aux_write(AUX_DC_DATA, data);
+
+	return 0;
+}
+
+/**
+ * \brief directly read dcache internal ram
+ *
+ * \param[in] cache_addr, dcache internal address(way+index+offset)
+ * \param[out] tag	cache tag to read
+ * \param[out] data	cache data to read
+ * \return 0, succeeded, -1, failed
+ */
+int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data)
+{
+	if (!dcache_available()) return -1;
+
+	if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) {
+		return -1;
+	}
+	_arc_aux_write(AUX_DC_RAM_ADDR, cache_addr);
+	*tag = _arc_aux_read(AUX_DC_TAG);
+	*data = _arc_aux_read(AUX_DC_DATA);
+
+	return 0;
+}
+
+/**
+ * \brief indirectly read dcache internal ram
+ *
+ * \param[in] mem_addr, memory address(tag+index+offset)
+ * \param[out] tag	cache tag to read
+ * \param[out] data	cache data to read
+ * \return 0, succeeded, -1, failed
+ */
+int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data)
+{
+	if (!dcache_available()) return -1;
+
+	if (!(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS)) {
+		return -1;
+	}
+	_arc_aux_write(AUX_DC_RAM_ADDR, mem_addr);
+	if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
+		*tag = _arc_aux_read(AUX_DC_TAG);
+		*data = _arc_aux_read(AUX_DC_DATA);
+	} else {
+		return -1;	/* the specified memory is not in dcache */
+	}
+	return 0;
+ }
+
+/**
+ * \brief  initialize cache
+ * 1. invalidate icache and dcache
+ * 2. Only support ARCv2 cache
+ */
+void arc_cache_init(void)
+{
+	uint32_t build_cfg;
+
+	build_cfg = _arc_aux_read(AUX_BCR_D_CACHE);
+
+	dcache_config.ver = build_cfg & 0xff;
+
+	if (dcache_config.ver >= 0x04) { /* ARCv2 */
+		dcache_enable(DC_CTRL_DISABLE_FLUSH_LOCKED |
+			DC_CTRL_INDIRECT_ACCESS | DC_CTRL_INVALID_FLUSH);
+		dcache_invalidate();
+		dcache_config.assoc = 1 << ((build_cfg >> 8) & 0xf);
+		dcache_config.capacity = 512 << ((build_cfg >> 12) & 0xf);
+		dcache_config.line = 16 << ((build_cfg >> 16) & 0xf);
+	}
+
+	build_cfg = _arc_aux_read(AUX_BCR_I_CACHE);
+
+	icache_config.ver = build_cfg & 0xff;
+
+	if (icache_config.ver >= 0x04) { /* ARCv2 */
+		icache_config.assoc = 1 << ((build_cfg >> 8) & 0xf);
+		icache_config.capacity = 512 << ((build_cfg >> 12) & 0xf);
+		icache_config.line = 8 << ((build_cfg >> 16) & 0xf);
+
+		icache_enable(IC_CTRL_IC_ENABLE);
+		icache_invalidate();
+	}
+
+}
diff --git a/bsp/synopsys/embarc/arc/arc_exc_asm.S b/bsp/synopsys/embarc/arc/arc_exc_asm.S
new file mode 100644
index 0000000000..7410db3154
--- /dev/null
+++ b/bsp/synopsys/embarc/arc/arc_exc_asm.S
@@ -0,0 +1,201 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_EXCEPTION_CPU
+ * \brief  assembly part of exception and interrupt processing
+ */
+
+/**
+ * \addtogroup ARC_HAL_EXCEPTION_CPU
+ * @{
+ */
+
+/* function documentation */
+/**
+ * \fn void exc_entry_cpu(void)
+ * \brief default entry of CPU exceptions, such as TLB miss and swap.
+ *
+ * \fn void exc_entry_int(void)
+ * \brief normal interrupt exception entry.
+ * 	In default, all interrupt exceptions are installed with normal entry.
+ * 	If FIRQ is required, exc_entry_firq should be the entry.
+ *
+ * \fn void exc_entry_firq(void)
+ * \brief firq exception entry
+ */
+/** }@ */
+
+/** @cond EXCEPTION_ASM */
+
+#define __ASSEMBLY__
+#include "inc/arc/arc.h"
+#include "inc/arc/arc_asm_common.h"
+
+	.file "arc_exc_asm.S"
+
+/* entry for cpu exception handling */
+	.text
+	.global exc_entry_cpu
+	.weak exc_entry_cpu
+	.align 4
+exc_entry_cpu:
+
+	EXCEPTION_PROLOGUE
+
+	mov	r3, sp					/* as exception handler's para(exc_frame) */
+
+/* exc_nest_count +1 */
+	ld	r0, [exc_nest_count]
+	add	r0, r0, 1
+	st	r0, [exc_nest_count]
+
+/* find the exception cause */
+	lr	r0, [AUX_ECR]
+	lsr	r0, r0, 16
+	bmsk	r0, r0, 7
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]
+
+	mov	r0, r3
+	jl	[r2]					/* jump to exception handler where interrupts are not allowed! */
+
+/* interrupts are not allowed */
+exc_return:
+
+/* exc_nest_count -1 */
+	ld	r0, [exc_nest_count]
+	sub	r0, r0, 1
+	st	r0, [exc_nest_count]
+
+	EXCEPTION_EPILOGUE
+	rtie
+
+
+/****** entry for normal interrupt exception handling ******/
+	.global exc_entry_int
+	.weak exc_entry_int
+	.align 4
+exc_entry_int:
+	clri						/* disable interrupt */
+
+#if ARC_FEATURE_FIRQ == 1
+#if ARC_FEATURE_RGF_NUM_BANKS > 1
+	lr	r0, [AUX_IRQ_ACT]			/*  check whether it is P0 interrupt */
+	btst	r0, 0
+	bnz	exc_entry_firq
+#else
+	PUSH	r10
+	lr	r10, [AUX_IRQ_ACT]
+	btst	r10, 0
+	POP	r10
+	bnz	exc_entry_firq
+#endif
+#endif
+	INTERRUPT_PROLOGUE			/* save scratch regs, this will be affected  */
+
+
+/* exc_nest_count +1 */
+	ld	r0, [exc_nest_count]
+	add	r0, r0, 1
+	st	r0, [exc_nest_count]
+
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]				/* r2 = _kernel_exc_tbl + irqno *4 */
+
+/* for the case of software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d	irq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+irq_hint_handled:
+	seti						/* enable higher priority interrupt */
+
+	mov	r0, sp
+	jl	[r2]					/* jump to interrupt handler */
+
+/* no interrupts are allowed from here */
+int_return:
+	clri						/* disable interrupt */
+
+/* exc_nest_count -1 */
+	ld	r0, [exc_nest_count]
+	sub	r0, r0, 1
+	st	r0, [exc_nest_count]
+
+	INTERRUPT_EPILOGUE
+	rtie
+
+/****** entry for fast irq exception handling ******/
+	.global exc_entry_firq
+	.weak exc_entry_firq
+	.align 4
+exc_entry_firq:
+	clri						/* disable interrupt */
+	SAVE_FIQ_EXC_REGS
+
+/* exc_nest_count +1 */
+	ld	r0, [exc_nest_count]
+	add	r0, r0, 1
+	st	r0, [exc_nest_count]
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]				/* r2 = _kernel_exc_tbl + irqno *4 */
+
+/* for the case of software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d	firq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+firq_hint_handled:
+
+	jl	[r2]					/* jump to interrupt handler */
+
+/* no interrupts are allowed from here */
+firq_return:
+
+/* exc_nest_count -1 */
+	ld	r0, [exc_nest_count]
+	sub	r0, r0, 1
+	st	r0, [exc_nest_count]
+
+	RESTORE_FIQ_EXC_REGS
+	rtie
+
+/** @endcond */
diff --git a/bsp/synopsys/embarc/arc/arc_exception.c b/bsp/synopsys/embarc/arc/arc_exception.c
new file mode 100644
index 0000000000..a256b0b394
--- /dev/null
+++ b/bsp/synopsys/embarc/arc/arc_exception.c
@@ -0,0 +1,501 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
+ * \brief C Implementation of exception and interrupt management
+ */
+#include "inc/arc/arc_exception.h"
+#include "inc/arc/arc_cache.h"
+
+//#define	 DBG_LESS
+//#include "embARC_debug.h"
+
+/**
+ * \addtogroup ARC_HAL_EXCEPTION_CPU
+ * @{
+ * \var exc_entry_table
+ * \brief exception entry table
+ *
+ * install exception entry table to ARC_AUX_INT_VECT_BASE in startup.
+ * According to ARCv2 ISA, vectors are fetched in instruction space and thus
+ * may be present in ICCM, Instruction Cache, or
+ * main memory accessed by instruction fetch logic.
+ * So it is put into a specific section .vector.
+ *
+ * Please note that the exc_entry_table maybe cached in ARC. Some functions is
+ * defined in .s files.
+ *
+ */
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_CPU
+ * \brief  default cpu exception handler
+ * \param p_excinf pointer to the exception frame
+ */
+static void exc_handler_default(void *p_excinf)
+{
+	// uint32_t excpt_cause_reg = 0;
+	// uint32_t excpt_ret_reg = 0;
+	// uint32_t exc_no = 0;
+
+	// excpt_cause_reg = _arc_aux_read(AUX_ECR);
+	// excpt_ret_reg = _arc_aux_read(AUX_ERRET);
+	// exc_no = (excpt_cause_reg >> 16) & 0xff;
+
+	Asm("kflag 1");
+}
+
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_INTERRUPT
+ * \brief  default interrupt handler
+ * \param[in] p_excinf	information for interrupt handler
+ */
+static void int_handler_default(void *p_excinf)
+{
+	// uint32_t int_cause_reg = 0;
+
+	// int_cause_reg = _arc_aux_read(AUX_IRQ_CAUSE);
+	Asm("kflag 1");
+}
+
+__attribute__ ((aligned(1024), section(".vector")))
+EXC_ENTRY exc_entry_table[NUM_EXC_ALL] = {
+ 	[0] = _arc_reset,
+ 	[1 ... NUM_EXC_CPU-1] = exc_entry_cpu,
+	[NUM_EXC_CPU ... NUM_EXC_ALL-1] = exc_entry_int
+ };
+/**
+ * \var exc_int_handler_table
+ * \brief the cpu exception and interrupt exception handler table
+ * called in exc_entry_default and exc_entry_int
+ */
+EXC_HANDLER exc_int_handler_table[NUM_EXC_ALL] = {
+	 [0 ... NUM_EXC_CPU-1] = exc_handler_default,
+	 [NUM_EXC_CPU ... NUM_EXC_ALL-1] = int_handler_default
+};
+
+/**
+ * \var exc_nest_count
+ * \brief the counter for exc/int processing, =0 no int/exc
+ * >1 in int/exc processing
+ * @}
+ */
+uint32_t exc_nest_count;
+
+typedef struct aux_irq_ctrl_field {
+	/* note: little endian */
+	uint32_t save_nr_gpr_pairs: 5;	/** Indicates number of general-purpose register pairs saved, from 0 to 8/16 */
+	uint32_t res: 4;		/** Reserved */
+	uint32_t save_blink: 1;		/** Indicates whether to save and restore BLINK */
+	uint32_t save_lp_regs: 1;	/** Indicates whether to save and restore loop registers (LP_COUNT, LP_START, LP_END) */
+	uint32_t save_u_to_u: 1;	/** Indicates if user context is saved to user stack */
+	uint32_t res2: 1;		/** Reserved */
+	uint32_t save_idx_regs: 1;	/** Indicates whether to save and restore code-density registers (EI_BASE, JLI_BASE, LDI_BASE) */
+	uint32_t res3: 18;		/** Reserved */
+} aux_irq_ctrl_field_t;
+
+typedef union {
+	aux_irq_ctrl_field_t bits;
+	uint32_t value;
+} aux_irq_ctrl_t;
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
+ * \brief  intialize the exception and interrupt handling
+ */
+void exc_int_init(void)
+{
+	uint32_t i;
+	uint32_t status;
+	aux_irq_ctrl_t ictrl;
+
+	ictrl.value = 0;
+
+#ifndef ARC_FEATURE_RF16
+	ictrl.bits.save_nr_gpr_pairs = 6;	/* r0 to r11 (r12 saved manually) */
+#else
+	ictrl.bits.save_nr_gpr_pairs = 3;	/* r0 to r3, r10, r11  */
+#endif
+	ictrl.bits.save_blink = 1;
+	ictrl.bits.save_lp_regs = 1;		/* LP_COUNT, LP_START, LP_END */
+	ictrl.bits.save_u_to_u = 0;		/* user ctxt saved on kernel stack */
+	ictrl.bits.save_idx_regs = 1;		/* JLI, LDI, EI */
+
+	status = arc_lock_save();
+	for (i = NUM_EXC_CPU; i < NUM_EXC_ALL; i++) {
+		/* interrupt level triggered, disabled, priority is the lowest */
+		_arc_aux_write(AUX_IRQ_SELECT, i);
+		_arc_aux_write(AUX_IRQ_ENABLE, 0);
+		_arc_aux_write(AUX_IRQ_TRIGGER, 0);
+#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2)
+		_arc_aux_write(AUX_IRQ_PRIORITY, (1 << AUX_IRQ_PRIORITY_BIT_S)|(INT_PRI_MAX - INT_PRI_MIN));
+#else
+		_arc_aux_write(AUX_IRQ_PRIORITY, INT_PRI_MAX - INT_PRI_MIN);
+#endif
+	}
+	_arc_aux_write(AUX_IRQ_CTRL, ictrl.value);
+
+	arc_unlock_restore(status);
+
+	/** ipm should be set after cpu unlock restore to avoid reset of the status32 value */
+	arc_int_ipm_set((INT_PRI_MAX - INT_PRI_MIN));
+}
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_CPU
+ * \brief  install a CPU exception entry
+ * \param[in] excno exception number
+ * \param[in] entry the entry of exception to install
+ */
+int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY entry)
+{
+	uint32_t status;
+
+	EXC_ENTRY *table = (EXC_ENTRY *)_arc_aux_read(AUX_INT_VECT_BASE);
+
+	if (excno < NUM_EXC_ALL && entry != NULL
+		&& table[excno] != entry) {
+		status = cpu_lock_save();
+		/* directly write to mem, as arc gets exception handler from mem not from cache */
+		/* FIXME, here maybe icache is dirty, need to be invalidated */
+		table[excno] = entry;
+
+		if (_arc_aux_read(AUX_BCR_D_CACHE) > 0x2) {
+		/* dcache is available */
+			dcache_flush_line((uint32_t)&table[excno]);
+		}
+
+		if (_arc_aux_read(AUX_BCR_D_CACHE) > 0x2) {
+		/* icache is available */
+			icache_invalidate_line((uint32_t)&table[excno]);
+		}
+		cpu_unlock_restore(status);
+		return 0;
+	}
+	return -1;
+}
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_CPU
+ * \brief  get the installed CPU exception entry
+ * \param[in] excno exception number
+ * \return the installed CPU exception entry
+ */
+EXC_ENTRY exc_entry_get(const uint32_t excno)
+{
+	if (excno < NUM_EXC_ALL) {
+		return exc_entry_table[excno];
+	}
+	return NULL;
+}
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_CPU
+ * \brief  install an exception handler
+ * \param[in] excno	exception number
+ * \param[in] handler the handler of exception to install
+ */
+int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER handler)
+{
+	if (excno < NUM_EXC_ALL && handler != NULL) {
+		exc_int_handler_table[excno] = handler;
+		return 0;
+	}
+
+	return -1;
+}
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_CPU
+ * \brief  get the installed exception handler
+ * \param[in] excno	exception number
+ * \return the installed exception handler or NULL
+ */
+EXC_HANDLER exc_handler_get(const uint32_t excno)
+{
+	if (excno < NUM_EXC_ALL) {
+		return exc_int_handler_table[excno];
+	}
+
+	return NULL;
+}
+
+
+#ifndef EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT
+/**
+ * \brief disable the specific interrupt
+ *
+ * \param[in] intno interrupt number
+ */
+int32_t int_disable(const uint32_t intno)
+{
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		arc_int_disable(intno);
+		return 0;
+	}
+
+	return -1;
+}
+
+/**
+ * \brief  enable the specific int
+ *
+ * \param[in] intno interrupt number
+ */
+int32_t int_enable(const uint32_t intno)
+{
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		arc_int_enable(intno);
+		return 0;
+	}
+
+	return -1;
+}
+
+/**
+ * \brief  check whether the specific int is enabled
+ *
+ * \param[in] intno interrupt number
+ * \return 0 disabled, 1 enabled, < 0 error
+ */
+int32_t int_enabled(const uint32_t intno)
+{
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		_arc_aux_write(AUX_IRQ_SELECT, intno);
+		return _arc_aux_read(AUX_IRQ_ENABLE);
+	}
+
+	return -1;
+}
+
+/**
+ * \brief  get the interrupt priority mask
+ *
+ * \returns interrupt priority mask, negative num
+ */
+int32_t int_ipm_get(void)
+{
+	return ((int32_t)arc_int_ipm_get() + INT_PRI_MIN);
+}
+
+
+/**
+ * \brief  set the interrupt priority mask
+ *
+ * \param[in] intpri interrupt priority
+ */
+int32_t int_ipm_set(int32_t intpri)
+{
+	if (intpri >= INT_PRI_MIN && intpri <= INT_PRI_MAX) {
+		intpri = intpri - INT_PRI_MIN;
+		arc_int_ipm_set(intpri);
+		return 0;
+	}
+
+	return  -1;
+}
+
+
+/**
+ * \brief  get current interrupt priority mask
+ *
+ * \param[in] intno interrupt number
+ * \return  <0 interrupt priority, 0 error
+ */
+int32_t int_pri_get(const uint32_t intno)
+{
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		return (int32_t)arc_int_pri_get(intno) + INT_PRI_MIN;
+	}
+
+	return 0;
+}
+
+
+/**
+ * \brief set interrupt priority
+ *
+ * \param[in] intno interrupt number
+ * \param[in] intpri interrupt priority
+ * \return  <0 error, 0 ok
+ */
+int32_t int_pri_set(const uint32_t intno, int32_t intpri)
+{
+	uint32_t status;
+
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		status = cpu_lock_save();
+		intpri = intpri - INT_PRI_MIN;
+		arc_int_pri_set(intno,(uint32_t)intpri);
+		cpu_unlock_restore(status);
+		return 0;
+	}
+	return -1;
+}
+
+/**
+ * \brief set interrupt secure or not secure
+ * This function is valid in secureshield v2
+ * \param[in] intno interrupt number
+ * \param[in] secure, 0 for normal, >0 for secure
+ * \return <0 error, 0 ok
+ */
+int32_t int_secure_set(const uint32_t intno, uint32_t secure)
+{
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		arc_int_secure_set(intno, secure);
+		return 0;
+	}
+	return -1;
+
+}
+
+
+/**
+ * \brief  probe the pending status of interrupt
+ *
+ * \param[in] intno interrupt number
+ *
+ * \returns 1 pending, 0 no pending, -1 error
+ */
+int32_t int_probe(const uint32_t intno)
+{
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		return arc_int_probe(intno);
+	}
+	return -1;
+}
+
+
+/**
+ * \brief  trigger the interrupt in software
+ *
+ * \param[in] intno interrupt number
+ * \return 0 ok, -1 error
+ */
+int32_t int_sw_trigger(const uint32_t intno)
+{
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		arc_int_sw_trigger(intno);
+		return 0;
+	}
+	return -1;
+}
+
+/**
+ * \brief  config the interrupt level triggered or pulse triggered
+ *
+ * \param[in] intno interrupt number
+ * \param[in] level, 0-level trigger, 1-pulse triggered
+ * \return 0 ok, -1 error
+ */
+int32_t int_level_config(const uint32_t intno, const uint32_t level)
+{
+	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
+		arc_int_level_config(intno, level);
+		return 0;
+	}
+	return -1;
+}
+
+
+/**
+ * \brief  lock cpu, disable interrupts
+ */
+void cpu_lock(void)
+{
+	arc_lock();
+}
+
+/**
+ * \brief  unlock cpu, enable interrupts to happen
+ */
+void cpu_unlock(void)
+{
+	arc_unlock();
+}
+
+/**
+ * \brief  lock cpu and return status
+ *
+ * \returns cpu status
+ */
+uint32_t cpu_lock_save(void)
+{
+	return arc_lock_save();
+}
+
+/**
+ * \brief  unlock cpu with the specific status
+ *
+ * \param[in] status  cpu status saved by cpu_lock_save
+ */
+void cpu_unlock_restore(const uint32_t status)
+{
+	arc_unlock_restore(status);
+}
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_INTERRUPT
+ * \brief  install an interrupt handler
+ * \param[in] intno	interrupt number
+ * \param[in] handler interrupt handler to install
+ */
+int32_t int_handler_install(const uint32_t intno, INT_HANDLER handler)
+{
+	/*!< \todo parameter check ? */
+	if (intno >= NUM_EXC_CPU) {
+		return exc_handler_install(intno, handler);
+	}
+
+	return -1;
+}
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_INTERRUPT
+ * \brief  get the installed an interrupt handler
+ * \param[in] intno interrupt number
+ * \return the installed interrupt handler or NULL
+ */
+INT_HANDLER int_handler_get(const uint32_t intno)
+{
+	if (intno >= NUM_EXC_CPU) {
+		return exc_handler_get(intno);
+	}
+
+	return NULL;
+}
+#endif /* EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT */
diff --git a/bsp/synopsys/embarc/arc/arc_timer.c b/bsp/synopsys/embarc/arc/arc_timer.c
new file mode 100644
index 0000000000..3d0c4b4f83
--- /dev/null
+++ b/bsp/synopsys/embarc/arc/arc_timer.c
@@ -0,0 +1,211 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	ARC_HAL_MISC_TIMER
+ * \brief  implementation of internal timer related functions
+ * \todo RTC support should be improved if RTC is enabled
+ */
+#include "inc/arc/arc_timer.h"
+#include "inc/arc/arc.h"
+#include "inc/arc/arc_builtin.h"
+
+/**
+ * \brief  check whether the specific timer present
+ * \param[in] no timer number
+ * \retval 1 present
+ * \retval 0 not present
+ */
+int32_t arc_timer_present(const uint32_t no)
+{
+	uint32_t bcr = _arc_aux_read(AUX_BCR_TIMERS);
+	switch (no) {
+		case TIMER_0:
+			bcr = (bcr >> 8) & 1;
+			break;
+		case TIMER_1:
+			bcr = (bcr >> 9) & 1;
+			break;
+		case TIMER_RTC:
+			bcr = (bcr >> 10) & 1;
+			break;
+		default:
+			bcr = 0;
+			/* illegal argument so return false */
+			break;
+		}
+
+	return (int)bcr;
+}
+
+/**
+ * \brief  start the specific timer
+ * \param[in] no	timer number
+ * \param[in] mode	timer mode
+ * \param[in] val	timer limit value (not for RTC)
+ * \return 0 success, -1 failure
+ */
+int32_t arc_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val)
+{
+	if (arc_timer_present(no) == 0) {
+		return -1;
+	}
+
+	switch (no) {
+		case TIMER_0:
+			_arc_aux_write(AUX_TIMER0_CTRL, 0);
+			_arc_aux_write(AUX_TIMER0_LIMIT, val);
+			_arc_aux_write(AUX_TIMER0_CTRL, mode);
+			_arc_aux_write(AUX_TIMER0_CNT, 0);
+			break;
+		case TIMER_1:
+			_arc_aux_write(AUX_TIMER1_CTRL, 0);
+			_arc_aux_write(AUX_TIMER1_LIMIT, val);
+			_arc_aux_write(AUX_TIMER1_CTRL, mode);
+			_arc_aux_write(AUX_TIMER1_CNT, 0);
+			break;
+		case TIMER_RTC:
+			_arc_aux_write(AUX_RTC_CTRL, mode);
+			break;
+		default:
+			return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * \brief  stop and clear the specific timer
+ *
+ * \param[in] no timer number
+ * \return 0 success, -1 failure
+ */
+int32_t arc_timer_stop(const uint32_t no)
+{
+	if (arc_timer_present(no) == 0) {
+		return -1;
+	}
+
+	switch (no) {
+		case TIMER_0 :
+			_arc_aux_write(AUX_TIMER0_CTRL, 0);
+			_arc_aux_write(AUX_TIMER0_LIMIT,0);
+			_arc_aux_write(AUX_TIMER0_CNT, 0);
+			break;
+		case TIMER_1:
+			_arc_aux_write(AUX_TIMER1_CTRL, 0);
+			_arc_aux_write(AUX_TIMER1_LIMIT,0);
+			_arc_aux_write(AUX_TIMER1_CNT, 0);
+			break;
+		case TIMER_RTC:
+			_arc_aux_write(AUX_RTC_CTRL, TIMER_RTC_CLEAR);
+			break;
+		default:
+			return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * \brief  get timer current tick
+ *
+ * \param[in] no timer number
+ * \param[out] val, timer value
+ * \return 0 success, -1 failure
+ */
+int32_t arc_timer_current(const uint32_t no, void *val)
+{
+	if (arc_timer_present(no) == 0) {
+		return -1;
+	}
+
+	switch (no) {
+		case TIMER_0 :
+			*((uint32_t *)val) = _arc_aux_read(AUX_TIMER0_CNT);
+			break;
+		case TIMER_1 :
+			*((uint32_t *)val) = _arc_aux_read(AUX_TIMER1_CNT);
+			break;
+		case TIMER_RTC:
+			*((uint64_t *)val) = _arc_aux_read(AUX_RTC_LOW);
+			break;
+		default :
+			return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * \brief  clear the interrupt pending bit of timer
+ *
+ * \param[in] no timer number
+ * \return 0 success, -1 failure
+ */
+int32_t arc_timer_int_clear(const uint32_t no)
+{
+	uint32_t val;
+
+	if (arc_timer_present(no) == 0) {
+		return -1;
+	}
+
+	switch (no) {
+		case TIMER_0 :
+			val = _arc_aux_read(AUX_TIMER0_CTRL);
+			val &= ~TIMER_CTRL_IP;
+			_arc_aux_write(AUX_TIMER0_CTRL, val);
+			break;
+		case TIMER_1 :
+			val = _arc_aux_read(AUX_TIMER1_CTRL);
+			val &= ~TIMER_CTRL_IP;
+			_arc_aux_write(AUX_TIMER1_CTRL, val);
+			break;
+		default :
+			return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * \brief  init internal timer
+ */
+void arc_timer_init(void)
+{
+	arc_timer_stop(TIMER_0);
+	arc_timer_stop(TIMER_1);
+	arc_timer_stop(TIMER_RTC);
+}
diff --git a/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c b/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c
new file mode 100644
index 0000000000..af842fddc6
--- /dev/null
+++ b/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2012-2014 Wind River Systems, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ------------------------------------------
+ * Copyright (c) 2015, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2016-03-02
+ * \author Wayne Ren(wei.ren@synopsys.com)
+--------------------------------------------- */
+#include "embARC_BSP_config.h"
+#if defined(__GNU__)
+/* embARC's GNU C++ support takes reference from Zephyr (cpp_xxx.c) */
+
+/**
+ * @file - Constructor module
+ * @brief
+ * The ctors section contains a list of function pointers that execute the
+ * C++ constructors of static global objects. These must be executed before
+ * the application's main() routine.
+ *
+ * NOTE: Not all compilers put those function pointers into the ctors section;
+ * some put them into the init_array section instead.
+ */
+
+/* What a constructor function pointer looks like */
+
+typedef void (*CtorFuncPtr)(void);
+
+/* Constructor function pointer list is generated by the linker script. */
+
+extern CtorFuncPtr __CTOR_LIST__[];
+extern CtorFuncPtr __CTOR_END__[];
+
+/**
+ *
+ * @brief Invoke all C++ style global object constructors
+ *
+ * This routine is invoked before the execution of the
+ * application's main().
+ */
+void __do_global_ctors_aux(void)
+{
+	unsigned int nCtors;
+
+	nCtors = (unsigned int)__CTOR_LIST__[0];
+
+	while (nCtors >= 1) {
+		__CTOR_LIST__[nCtors--]();
+	}
+}
+
+typedef void (*DtorFuncPtr)(void);
+
+extern DtorFuncPtr __DTOR_LIST__[];
+extern DtorFuncPtr __DTOR_END__[];
+
+/**
+ *
+ * @brief Invoke all C++ style global object destructors
+ *
+ * This routine is invoked after the execution of the
+ * application's main().
+ */
+void __do_global_dtors_aux(void)
+{
+	unsigned int nDtors;
+	unsigned int i;
+
+	nDtors = (unsigned int)__DTOR_LIST__[0];
+	i = 0;
+
+	while (i <= nDtors) {
+		__DTOR_LIST__[i++]();
+	}
+}
+
+void *__dso_handle = 0;
+
+/**
+ * @brief Register destructor for a global object
+ *
+ * @param destructor the global object destructor function
+ * @param objptr global object pointer
+ * @param dso Dynamic Shared Object handle for shared libraries
+ *
+ * Function does nothing at the moment, assuming the global objects
+ * do not need to be deleted
+ *
+ * @return N/A
+ */
+int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso)
+{
+	return 0;
+}
+
+typedef void (*func_ptr)(void);
+
+extern func_ptr __init_array_start[0];
+extern func_ptr __init_array_end[0];
+
+/**
+ * @brief Execute initialization routines referenced in .init_array section
+ *
+ * @return N/A
+ */
+void __do_init_array_aux(void)
+{
+	for (func_ptr *func = __init_array_start;
+		func < __init_array_end;
+		func++) {
+		(*func)();
+	}
+}
+
+/**
+ * @brief Stub for pure virtual functions
+ *
+ * This routine is needed for linking C++ code that uses pure virtual
+ * functions.
+ *
+ * @return N/A
+ */
+void __cxa_pure_virtual(void)
+{
+	while (1) {
+		;
+	}
+}
+#endif
diff --git a/bsp/synopsys/embarc/arc/startup/arc_startup.S b/bsp/synopsys/embarc/arc/startup/arc_startup.S
new file mode 100644
index 0000000000..26a6fdb519
--- /dev/null
+++ b/bsp/synopsys/embarc/arc/startup/arc_startup.S
@@ -0,0 +1,262 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_STARTUP
+ * \brief assembly part of startup process
+ */
+
+/**
+ * \addtogroup ARC_HAL_STARTUP
+ * @{
+ */
+/** @cond STARTUP_ASM */
+
+#define __ASSEMBLY__
+#include "embARC_BSP_config.h"
+#include "inc/arc/arc.h"
+
+	.file "arc_startup.S"
+
+.weak	_f_sdata		/* start of small data, defined in link script */
+.weak	init_hardware_hook	/* app hardware init hook */
+.weak	init_software_hook	/* app software init hook */
+
+.extern	board_main
+.extern exc_entry_table
+
+/* initial vector table */
+	.section .init_vector, "a"
+	.long _arc_reset
+	.section .init_bootstrap, "ax"
+	.global _arc_reset
+	.global _start
+	.align 4
+_start:
+_arc_reset:
+_arc_reset_stage1:
+	kflag	STATUS32_RESET_VALUE
+
+/* STAGE 1 */
+
+/* necessary hardware should be done first to speed up initialization
+	1. system clk
+	2. mem controller must be initialized before any access to external
+	mem.
+	3. others
+*/
+_arc_cache_init_start:
+	lr	r0, [AUX_BCR_D_CACHE]
+	cmp	r0, 2
+	/* invalidate dcache */
+	jle	_arc_icache_init
+	mov	r0, 1
+	sr	r0, [AUX_DC_IVDC]
+	sr	r0, [AUX_DC_CTRL]
+_arc_icache_init:
+	lr	r0, [AUX_BCR_I_CACHE]
+	cmp	r0, 2
+	jle	_arc_cache_init_end
+	/* invalidate icache */
+	mov	r0, 1
+	sr	r0, [AUX_IC_IVIC]
+	nop_s
+	nop_s
+	nop_s
+	sr	r0, [AUX_IC_CTRL]
+
+_arc_cache_init_end:
+	mov	r0, init_hardware_hook
+	cmp	r0, 0
+	jlne	[r0]
+
+/* STAGE 2: init necessary registers */
+
+_arc_reset_stage2:
+	mov	r0, 0
+
+/* interrupt related init */
+	sr	r0, [AUX_IRQ_ACT]
+	sr	r0, [AUX_IRQ_CTRL]
+	sr	r0, [AUX_IRQ_HINT]
+
+/* use the new vector table to replace the old one */
+#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2)
+	sr	exc_entry_table, [AUX_INT_VECT_BASE_S]
+#else
+	sr	exc_entry_table, [AUX_INT_VECT_BASE]
+#endif
+
+/* init stack */
+#if ARC_FEATURE_RGF_BANKED_REGS >= 16 && ARC_FEATURE_RGF_BANKED_REGS > 1 && ARC_FEATURE_FIRQ == 1
+#if _STACKSIZE < 512
+#error "not enough stack size for irq and firq"
+#endif
+
+/* switch to register bank1 */
+	lr      r0, [AUX_STATUS32]
+	bic     r0, r0, 0x70000
+	or      r0, r0, 0x10000
+	kflag   r0
+/* set sp, gp, fp in bank1 */
+	mov     sp, _e_stack
+	mov     gp, _f_sdata
+	mov     fp, 0
+/* come back to bank0 */
+	lr      r0, [AUX_STATUS32]
+	bic     r0, r0, 0x70000
+	kflag   r0
+	mov	sp, _e_stack-256
+#else
+	mov	sp, _e_stack	/* init stack pointer */
+#endif
+	mov	gp, _f_sdata	/* init small-data base register */
+	mov	fp, 0		/* init fp register */
+
+_arc_reset_stage3:
+_s3_copy_text:
+	mov	r0, _f_text
+	mov	r1, _load_addr_text
+	cmp	r0, r1
+
+/* if load addr == run addr, no need to copy */
+	jeq	_s3_copy_rodata
+	mov	r3, _e_text
+_s3_copy_text_loop:
+	ld.ab	r2, [r1, 4]
+	st.ab	r2, [r0, 4]
+	cmp	r0, r3
+	jlt	_s3_copy_text_loop
+_s3_copy_rodata:
+	mov	r0, _f_rodata
+	mov	r1, _load_addr_rodata
+	cmp	r0, r1
+
+/* if load addr == run addr, no need to copy */
+	jeq	_s3_copy_data
+	mov	r3, _e_rodata
+_s3_copy_rodata_loop:
+	ld.ab	r2, [r1, 4]
+	st.ab	r2, [r0, 4]
+	cmp	r0, r3
+	jlt	_s3_copy_rodata_loop
+_s3_copy_data:
+	mov	r0, _f_data
+	mov	r1, _load_addr_data
+	cmp	r0, r1
+	jeq	_s3_clear_bss
+
+/* if load addr == run addr, no need to copy */
+	mov	r3, _e_data
+_s3_copy_data_loop:
+	ld.ab	r2, [r1, 4]
+	st.ab	r2, [r0, 4]
+	cmp	r0, r3
+	jlt	_s3_copy_data_loop
+_s3_clear_bss:
+	mov	r0, _f_bss
+	mov	r1, _e_bss
+	cmp	r0, r1
+	jge	_arc_reset_call_main
+	mov	r2, 0
+_s3_clear_bss_loop:
+	st.ab	r2, [r0, 4]
+	cmp	r0, r1
+	jlt	_s3_clear_bss_loop
+
+/* STAGE 3: go to main */
+
+_arc_reset_call_main:
+
+/* \todo add cpp init here */
+	mov	r0, init_software_hook
+	cmp	r0, 0
+	jlne	[r0]
+/* board level library init */
+/* early init of interrupt and exception */
+	jl	exc_int_init
+/* init cache */
+	jl	arc_cache_init
+#if defined(__MW__)
+	jl	_init
+#elif defined(__GNU__)
+	jl	__do_global_ctors_aux
+	jl	__do_init_array_aux
+#endif
+	jl	board_main	/* board-level main */
+#if defined(__MW__)
+	jl	_fini
+#elif defined(__GNU__)
+	jl	__do_global_dtors_aux
+#endif
+	.global _exit_loop
+	.global _exit_halt
+	.align 4
+_exit_halt:
+_exit_loop:
+	flag	0x1
+	nop
+	nop
+	nop
+	b	_exit_loop
+
+#if defined(__MW__)
+	.global _init, _fini
+	.section ".init",text
+_init:
+	.cfa_bf	_init
+	push	%blink
+	.cfa_push	{%blink}
+
+	.section ".init$999999", text, 1, 2, check_text_align=0
+	pop	%blink
+	.cfa_pop	{%blink}
+	j	[%blink]
+	.cfa_ef
+
+	.section ".fini", text
+_fini:
+	.cfa_bf	_fini
+	push	%blink
+	.cfa_push	{%blink}
+
+	.section ".fini$999999", text, 1, 2, check_text_align=0
+	pop	%blink
+	.cfa_pop	{%blink}
+	j	[%blink]
+	.cfa_ef
+#endif
+/** @endcond */
+
+/** }@*/
diff --git a/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c b/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c
new file mode 100644
index 0000000000..ce79414fc6
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c
@@ -0,0 +1,481 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-22
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_DW_GPIO	Designware GPIO Driver
+ * \ingroup	DEVICE_DW
+ * \brief	Designware GPIO Driver Implementation
+ */
+
+/**
+ * \file
+ * \brief	designware gpio driver
+ * \ingroup	DEVICE_DW_GPIO
+ * \brief	Designware GPIO driver
+ */
+#include "inc/embARC_toolchain.h"
+#include "inc/embARC_error.h"
+#include "inc/arc/arc_exception.h"
+
+#include "device/designware/gpio/dw_gpio.h"
+
+/** check expressions used in DesignWare GPIO driver implementation */
+#define DW_GPIO_CHECK_EXP(EXPR, ERROR_CODE)		CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
+
+#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
+/** valid check of uart info object */
+#define VALID_CHK_GPIO_INFO_OBJECT(gpioinfo_obj_ptr)		{				\
+			DW_GPIO_CHECK_EXP((gpioinfo_obj_ptr)!=NULL, E_OBJ);			\
+			DW_GPIO_CHECK_EXP(((gpioinfo_obj_ptr)->gpio_ctrl)!=NULL, E_OBJ);	\
+ 		}
+#endif
+
+/**
+ * \defgroup	DEVICE_DW_GPIO_STATIC	DesignWare GPIO Driver Static Functions
+ * \ingroup	DEVICE_DW_GPIO
+ * \brief	Static or inline functions, variables for DesignWare GPIO handle gpio operations,
+ * 	only used in this file
+ * @{
+ */
+Inline uint32_t dw_gpio_read_ext(DW_GPIO_PORT_PTR port)
+{
+	return  port->regs->EXT_PORTS[port->no];
+}
+
+Inline uint32_t dw_gpio_read_dir(DW_GPIO_PORT_PTR port)
+{
+	return port->regs->SWPORTS[port->no].DDR;
+}
+
+Inline uint32_t dw_gpio_read_dr(DW_GPIO_PORT_PTR port)
+{
+	return port->regs->SWPORTS[port->no].DR;
+}
+
+Inline uint32_t dw_gpio_read_mthd(DW_GPIO_PORT_PTR port)
+{
+	return port->regs->INTEN;
+}
+
+Inline void dw_gpio_int_enable(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
+{
+	port->regs->INTEN |= bit_mask;
+}
+
+Inline void dw_gpio_int_disable(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
+{
+	port->regs->INTEN &= (~bit_mask);
+}
+
+Inline void dw_gpio_int_mask(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
+{
+	port->regs->INTMASK |= bit_mask;
+}
+
+Inline void dw_gpio_int_unmask(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
+{
+	port->regs->INTMASK &= (~bit_mask);
+}
+
+Inline uint32_t dw_gpio_int_read_level(DW_GPIO_PORT_PTR port)
+{
+	return port->regs->INTTYPE_LEVEL;
+}
+
+Inline uint32_t dw_gpio_int_read_polarity(DW_GPIO_PORT_PTR port)
+{
+	return port->regs->INT_POLARITY;
+}
+
+Inline uint32_t dw_gpio_int_read_debounce(DW_GPIO_PORT_PTR port)
+{
+	return port->regs->DEBOUNCE;
+}
+
+Inline uint32_t dw_gpio_int_read_status(DW_GPIO_PORT_PTR port)
+{
+	return port->regs->INTSTATUS;
+}
+
+Inline void dw_gpio_int_clear(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
+{
+	port->regs->PORTA_EOI = bit_mask;
+}
+
+static void dw_gpio_int_write_level(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_level)
+{
+	uint32_t reg_val;
+
+	reg_val = port->regs->INTTYPE_LEVEL;
+	reg_val &= (~bit_mask);
+	bit_level &= bit_mask;
+	reg_val |= bit_level;
+
+	port->regs->INTTYPE_LEVEL = reg_val;
+}
+
+static void dw_gpio_int_write_polarity(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_polarity)
+{
+	uint32_t reg_val;
+
+	reg_val = port->regs->INT_POLARITY;
+
+	reg_val &= (~bit_mask);
+	bit_polarity &= bit_mask;
+	reg_val |= bit_polarity;
+
+	port->regs->INT_POLARITY = reg_val;
+}
+
+static void dw_gpio_int_write_debounce(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_debounce)
+{
+	uint32_t reg_val;
+
+	reg_val = port->regs->DEBOUNCE;
+
+	reg_val &= (~bit_mask);
+	bit_debounce &= bit_mask;
+	reg_val |= bit_debounce;
+
+	port->regs->DEBOUNCE = reg_val;
+}
+
+static void dw_gpio_set_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg)
+{
+	dw_gpio_int_write_level(port, int_cfg->int_bit_mask, int_cfg->int_bit_type);
+	dw_gpio_int_write_polarity(port, int_cfg->int_bit_mask, int_cfg->int_bit_polarity);
+	dw_gpio_int_write_debounce(port, int_cfg->int_bit_mask, int_cfg->int_bit_debounce);
+}
+
+static void dw_gpio_get_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg)
+{
+	int_cfg->int_bit_type = dw_gpio_int_read_level(port) & int_cfg->int_bit_mask;
+	int_cfg->int_bit_polarity = dw_gpio_int_read_polarity(port) & int_cfg->int_bit_mask;
+	int_cfg->int_bit_debounce = dw_gpio_int_read_debounce(port) & int_cfg->int_bit_mask;
+}
+
+static void dw_gpio_write_dr(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val)
+{
+	uint32_t temp_reg;
+
+	temp_reg = port->regs->SWPORTS[port->no].DR;
+	temp_reg &= ~bit_mask;
+	val &= bit_mask;
+	temp_reg |= val;
+
+	port->regs->SWPORTS[port->no].DR = temp_reg;
+}
+
+static void dw_gpio_write_dir(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val)
+{
+	uint32_t temp_reg;
+
+	temp_reg = port->regs->SWPORTS[port->no].DDR;
+	temp_reg &= ~bit_mask;
+	val &= bit_mask;
+	temp_reg |= val;
+
+	port->regs->SWPORTS[port->no].DDR = temp_reg;
+}
+
+static uint32_t dw_gpio_read_val(DW_GPIO_PORT_PTR port)
+{
+	uint32_t val;
+
+	val = dw_gpio_read_ext(port) & (~dw_gpio_read_dir(port));
+	val |= dw_gpio_read_dr(port) & dw_gpio_read_dir(port);
+
+	return val;
+}
+
+/** @} end of group DEVICE_DW_GPIO_STATIC */
+
+/* interface for DEV_GPIO */
+/** Open designware gpio device with specified io direction configuration */
+int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir)
+{
+	int32_t ercd = E_OK;
+	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
+	/* END OF ERROR CHECK */
+
+	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
+	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
+
+	port_info_ptr->opn_cnt ++;
+	if (port_info_ptr->opn_cnt > 1) { /* opened before */
+		if (dir == port_info_ptr->direction) { /* direction is the same */
+			return E_OK;
+		} else { /* open with different direction */
+			return E_OPNED;
+		}
+	}
+
+	dw_gpio_write_dir(port, port->valid_bit_mask, dir);
+
+	if (port->no == DW_GPIO_PORT_A) {
+		dw_gpio_int_clear(port, DW_GPIO_MASK_ALL);
+		dw_gpio_int_disable(port, DW_GPIO_MASK_ALL);
+		dw_gpio_int_unmask(port, DW_GPIO_MASK_ALL);
+		/* install gpio interrupt handler */
+		int_handler_install(port->intno, port->int_handler);
+		int_disable(port->intno);
+		/** Set int type, int polarity and debounce configuration to default settings of device gpio */
+		dw_gpio_set_int_cfg(port, (DEV_GPIO_INT_CFG *)(&gpio_int_cfg_default));
+		port_info_ptr->method = dw_gpio_read_mthd(port);
+	} else {
+		port_info_ptr->method = DEV_GPIO_BITS_MTHD_DEFAULT;
+	}
+
+	dw_gpio_write_dr(port, port->valid_bit_mask, 0);
+
+	port_info_ptr->direction = dir;
+	port_info_ptr->extra = NULL;
+
+error_exit:
+	return ercd;
+}
+
+/** Close designware gpio device */
+int32_t dw_gpio_close(DEV_GPIO *gpio_obj)
+{
+	int32_t ercd = E_OK;
+	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
+	/* END OF ERROR CHECK */
+
+	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
+	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
+
+	DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_OK);
+
+	port_info_ptr->opn_cnt --;
+	if (port_info_ptr->opn_cnt == 0) {
+		dw_gpio_write_dr(port, port->valid_bit_mask, 0);
+		dw_gpio_write_dir(port, port->valid_bit_mask, 0);
+		if (port->no == DW_GPIO_PORT_A) {
+			dw_gpio_int_clear(port, DW_GPIO_MASK_ALL);
+			dw_gpio_int_disable(port, DW_GPIO_MASK_ALL);
+			int_disable(port->intno);
+		}
+
+		port_info_ptr->direction = 0;
+		port_info_ptr->method = 0;
+		port_info_ptr->extra = NULL;
+	} else {
+		ercd = E_OPNED;
+	}
+
+error_exit:
+	return ercd;
+}
+
+/** Read designware gpio device value */
+int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask)
+{
+	int32_t ercd = E_OK;
+	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
+	/* END OF ERROR CHECK */
+
+	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
+	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
+	DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
+
+	DW_GPIO_CHECK_EXP(val!=NULL, E_PAR);
+
+	//*val = dw_gpio_read_ext(port) & mask;
+	*val = dw_gpio_read_val(port) & mask;
+
+error_exit:
+	return ercd;
+}
+
+/** Write designware gpio device value */
+int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask)
+{
+	int32_t ercd = E_OK;
+	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
+	/* END OF ERROR CHECK */
+
+	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
+	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
+	DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
+
+	dw_gpio_write_dr(port, mask, val);
+
+error_exit:
+	return ercd;
+}
+
+/** Control designware gpio device */
+int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param)
+{
+	int32_t ercd = E_OK;
+	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
+	/* END OF ERROR CHECK */
+
+	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
+	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
+	DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
+
+	uint32_t val32;	/** to receive unsigned int value */
+
+	if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_INPUT) {
+		val32 = (uint32_t)param;
+		dw_gpio_write_dir(port, val32, DW_GPIO_INPUT_ALL);
+		port_info_ptr->direction = dw_gpio_read_dir(port);
+	} else if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_OUTPUT) {
+		val32 = (uint32_t)param;
+		dw_gpio_write_dir(port, val32, DW_GPIO_OUTPUT_ALL);
+		port_info_ptr->direction = dw_gpio_read_dir(port);
+	} else if (ctrl_cmd == GPIO_CMD_GET_BIT_DIR) {
+		DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+		port_info_ptr->direction = dw_gpio_read_dir(port);
+		*((int32_t *)param) = port_info_ptr->direction;
+	} else {
+		DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT);
+		/* output pin cannot be used as interrupt */
+		DEV_GPIO_INT_CFG *gpio_int_cfg;
+		DEV_GPIO_BIT_ISR *port_bit_isr;
+
+		switch (ctrl_cmd) {
+			case GPIO_CMD_SET_BIT_INT_CFG:
+				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+				gpio_int_cfg = (DEV_GPIO_INT_CFG *)param;
+				dw_gpio_set_int_cfg(port, gpio_int_cfg);
+				break;
+			case GPIO_CMD_GET_BIT_INT_CFG:
+				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+				gpio_int_cfg = (DEV_GPIO_INT_CFG *)param;
+				/** read configuration, each bit stands for different configuration */
+				dw_gpio_get_int_cfg(port, gpio_int_cfg);
+				break;
+			case GPIO_CMD_SET_BIT_ISR:
+				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+				port_bit_isr = (DEV_GPIO_BIT_ISR *)param;
+				if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) {
+					port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs] = port_bit_isr->int_bit_handler;
+				} else {
+					ercd = E_PAR;
+				}
+				break;
+			case GPIO_CMD_GET_BIT_ISR:
+				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+				port_bit_isr = (DEV_GPIO_BIT_ISR *)param;
+				if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) {
+					port_bit_isr->int_bit_handler = port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs];
+				} else {
+					ercd = E_PAR;
+				}
+				break;
+			case GPIO_CMD_ENA_BIT_INT:
+				val32 = (uint32_t)param;
+				dw_gpio_int_enable(port, val32);
+				port_info_ptr->method = dw_gpio_read_mthd(port);
+				if (port_info_ptr->method) {
+					int_enable(port->intno);
+				}
+				break;
+			case GPIO_CMD_DIS_BIT_INT:
+				val32 = (uint32_t)param;
+				dw_gpio_int_disable(port, val32);
+				port_info_ptr->method = dw_gpio_read_mthd(port);
+				if (port_info_ptr->method == 0) {
+					int_disable(port->intno);
+				}
+				break;
+			case GPIO_CMD_GET_BIT_MTHD:
+				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+				port_info_ptr->method = dw_gpio_read_mthd(port);
+				*((int32_t *)param) = port_info_ptr->method;
+				break;
+			default:
+				ercd = E_NOSPT;
+				break;
+		}
+	}
+error_exit:
+	return ercd;
+}
+
+/** designware gpio interrupt process */
+int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr)
+{
+	int32_t ercd = E_OK;
+	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
+	/* END OF ERROR CHECK */
+
+	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
+	DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT);
+
+	uint32_t i, gpio_bit_isr_state;
+	uint32_t max_int_bit_count = 0;
+
+	/** read interrupt status */
+	gpio_bit_isr_state = dw_gpio_int_read_status(port);
+
+	if (port->gpio_bit_isr) {
+		max_int_bit_count = (port->gpio_bit_isr->int_bit_max_cnt);
+	} else {
+		dw_gpio_int_clear(port, gpio_bit_isr_state);
+	}
+
+	for (i=0; i<max_int_bit_count; i++) {
+		if (gpio_bit_isr_state & (1<<i)) {
+			/* this bit interrupt enabled */
+			if (port->gpio_bit_isr->int_bit_handler_ptr[i]) {
+				port->gpio_bit_isr->int_bit_handler_ptr[i](gpio_obj);
+			}
+			dw_gpio_int_clear(port, (1<<i)); /** clear this bit interrupt */
+		}
+	}
+
+error_exit:
+	return ercd;
+}
diff --git a/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h b/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h
new file mode 100644
index 0000000000..c087975f82
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h
@@ -0,0 +1,145 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-22
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \brief	designware gpio driver
+ * \ingroup	DEVICE_DW_GPIO
+ * \brief	Designware GPIO driver header file
+ */
+
+#ifndef _DW_GPIO_H_
+#define _DW_GPIO_H_
+
+#include "device/device_hal/inc/dev_gpio.h"
+
+#include "inc/arc/arc_exception.h"
+
+#define DW_GPIO_PORT_A	(0x00)
+#define DW_GPIO_PORT_B	(0x01)
+#define DW_GPIO_PORT_C	(0x02)
+#define DW_GPIO_PORT_D	(0x03)
+
+#define DW_GPIO_INT_ACT_LOW			GPIO_INT_ACTIVE_LOW
+#define DW_GPIO_INT_ACT_HIGH			GPIO_INT_ACTIVE_HIGH
+
+#define DW_GPIO_INT_LEVEL_TRIG			GPIO_INT_LEVEL_TRIG
+#define DW_GPIO_INT_EDGE_TRIG			GPIO_INT_EDGE_TRIG
+
+#define DW_GPIO_INT_NO_DEBOUNCE			GPIO_INT_NO_DEBOUNCE
+#define DW_GPIO_INT_DEBOUNCE			GPIO_INT_DEBOUNCE
+
+#define DW_GPIO_ALL_ZERO			(0x0)
+#define DW_GPIO_ALL_ONE				(0xffffffff)
+#define DW_GPIO_MASK_ALL			(0xffffffff)
+#define DW_GPIO_INPUT_ALL			(0x0)
+#define DW_GPIO_OUTPUT_ALL			(0xffffffff)
+
+/**
+ * \name	DesignWare GPIO Register Structure
+ * \brief	contains definitions of DesignWare GPIO register structure.
+ * @{
+ */
+typedef struct port_ctrl {
+	uint32_t DR;
+	uint32_t DDR;
+	uint32_t CTRL;
+} PORT_CTRL;
+
+/* DW GPIO PORTS Registers */
+typedef volatile struct dw_gpio_reg {
+	PORT_CTRL SWPORTS[4];
+	uint32_t INTEN;		/*!< (0x30) */
+	uint32_t INTMASK;	/*!< (0x34) */
+	uint32_t INTTYPE_LEVEL;	/*!< (0x38) */
+	uint32_t INT_POLARITY;	/*!< (0x3c) */
+	uint32_t INTSTATUS;	/*!< (0x40) */
+	uint32_t RAW_INTSTATUS;	/*!< (0x44) */
+	uint32_t DEBOUNCE;	/*!< (0x48) */
+	uint32_t PORTA_EOI;	/*!< (0x4c) */
+	uint32_t EXT_PORTS[4];	/*!< (0x50) -A
+				     (0x54) -B
+				     (0x58) -C
+				     (0x5c) -D */
+	uint32_t LS_SYNC;	/*!< (0x60) */
+	uint32_t ID_CODE;	/*!< (0x64) */
+	uint32_t RESERVED_3;	/*!< (0x68) */
+	uint32_t VER_ID_CODE;	/*!< (0x6c) */
+	uint32_t CONFIG_REG2;	/*!< (0x70) */
+	uint32_t CONFIG_REG1;	/*!< (0x74) */
+} DW_GPIO_REG, *DW_GPIO_REG_PTR;
+/** @} */
+
+/** interrupt handler for each port bit */
+typedef struct dw_gpio_bit_isr {
+	uint32_t int_bit_max_cnt;		/*!< max bit count for each port */
+	DEV_GPIO_HANDLER *int_bit_handler_ptr;	/*!< interrupt handler pointer */
+} DW_GPIO_BIT_ISR, * DW_GPIO_BIT_ISR_PTR;
+
+/**
+ * \brief	DesignWare GPIO control structure definition
+ * \details	implement of dev_gpio_info::gpio_ctrl
+ */
+typedef struct dw_gpio_port {
+	uint32_t no;				/*!< gpio port number */
+	DW_GPIO_REG_PTR	regs;			/*!< gpio port register */
+	uint32_t intno;				/*!< gpio interrupt vector number */
+	uint32_t valid_bit_mask;		/*!< valid bit mask of gpio port */
+	INT_HANDLER int_handler;		/*!< gpio interrupt handler */
+	DW_GPIO_BIT_ISR_PTR gpio_bit_isr;	/*!< gpio bit handler struct */
+} DW_GPIO_PORT, *DW_GPIO_PORT_PTR;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name	DesignWare GPIO Function Declaration
+ * \brief	contains declarations of designware gpio functions.
+ * \details	This are only used in gpio object implementation source file
+ * @{
+ */
+extern int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir);
+extern int32_t dw_gpio_close(DEV_GPIO *gpio_obj);
+extern int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask);
+extern int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask);
+extern int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param);
+extern int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* _DW_GPIO_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic.c b/bsp/synopsys/embarc/device/designware/iic/dw_iic.c
new file mode 100644
index 0000000000..abef37ace2
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/iic/dw_iic.c
@@ -0,0 +1,1584 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-06-30
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_DW_IIC	Designware IIC Driver
+ * \ingroup	DEVICE_DW
+ * \brief	Designware IIC Driver Implementation
+ */
+
+/**
+ * \file
+ * \brief	Designware iic driver
+ * \ingroup	DEVICE_DW_IIC
+ */
+#include <string.h>
+
+#include "inc/embARC_toolchain.h"
+#include "inc/embARC_error.h"
+
+#include "inc/arc/arc_exception.h"
+
+#include "device/designware/iic/dw_iic_hal.h"
+#include "device/designware/iic/dw_iic.h"
+
+/** check expressions used in DesignWare IIC driver implementation */
+#define DW_IIC_CHECK_EXP(EXPR, ERROR_CODE)		CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
+
+#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
+/** valid check of iic info object */
+#define VALID_CHK_IIC_INFO_OBJECT(iicinfo_obj_ptr)		{			\
+			DW_IIC_CHECK_EXP((iicinfo_obj_ptr)!=NULL, E_OBJ);		\
+			DW_IIC_CHECK_EXP(((iicinfo_obj_ptr)->iic_ctrl)!=NULL, E_OBJ);	\
+ 		}
+#endif
+
+/**
+ * \name	DesignWare IIC Interrupt Callback Routine Select Marcos
+ * \brief	DesignWare IIC interrupt callback routines select macros definitions
+ * @{
+ */
+#define DW_IIC_RDY_SND					(1U)	/*!< ready to send callback */
+#define DW_IIC_RDY_RCV					(2U)	/*!< ready to receive callback */
+/** @} */
+
+/**
+ * \defgroup	DEVICE_DW_IIC_STATIC	DesignWare IIC Driver Static Functions
+ * \ingroup	DEVICE_DW_IIC
+ * \brief	Static or inline functions, variables for DesignWare IIC handle iic operations,
+ * 	only used in this file.
+ * @{
+ */
+/** Disable designware iic device */
+Inline void dw_iic_disable(DW_IIC_REG *iic_reg_ptr)
+{
+	iic_reg_ptr->IC_ENABLE = DW_IIC_DISABLE;
+}
+/** Enable designware iic device */
+Inline void dw_iic_enable(DW_IIC_REG *iic_reg_ptr)
+{
+	iic_reg_ptr->IC_ENABLE = DW_IIC_ENABLE;
+}
+
+/** Clear all designware iic interrupt */
+Inline void dw_iic_clear_interrupt_all(DW_IIC_REG *iic_reg_ptr)
+{
+	(void)iic_reg_ptr->IC_CLR_INTR;
+}
+
+/** test whether iic is ready to write, 1 ready, 0 not ready */
+Inline int32_t dw_iic_putready(DW_IIC_REG *iic_reg_ptr)
+{
+	return ((iic_reg_ptr->IC_STATUS & IC_STATUS_TFNF) != 0);
+}
+/** test whether iic is ready to receive, 1 ready, 0 not ready */
+Inline int32_t dw_iic_getready(DW_IIC_REG *iic_reg_ptr)
+{
+	return ((iic_reg_ptr->IC_STATUS & IC_STATUS_RFNE) != 0);
+}
+/** Write data into IIC TX FIFO with STOP/RESTART Condition, and R/W bit */
+Inline void dw_iic_putdata(DW_IIC_REG *iic_reg_ptr, uint32_t data)
+{
+	iic_reg_ptr->IC_DATA_CMD = data;
+}
+
+/** Read Data from IIC RX FIFO */
+Inline uint32_t dw_iic_getdata(DW_IIC_REG *iic_reg_ptr)
+{
+	return (iic_reg_ptr->IC_DATA_CMD) & 0xff;
+}
+
+/** Enable designware iic bit interrupt with mask */
+Inline void dw_iic_unmask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask)
+{
+	iic_reg_ptr->IC_INTR_MASK |= mask;
+}
+
+/** Disable designware iic bit interrupt with mask */
+Inline void dw_iic_mask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask)
+{
+	iic_reg_ptr->IC_INTR_MASK &= ~mask;
+}
+
+/** Get TX FIFO Length */
+Inline uint32_t dw_iic_get_txfifo_len(DW_IIC_REG *iic_reg_ptr)
+{
+	uint32_t txfifolen;
+
+	txfifolen = ((iic_reg_ptr->IC_COMP_PARAM_1 >> 16) & 0xff) + 1;
+
+	return txfifolen;
+}
+
+/** Get RX FIFO Length */
+Inline uint32_t dw_iic_get_rxfifo_len(DW_IIC_REG *iic_reg_ptr)
+{
+	uint32_t rxfifolen;
+
+	rxfifolen = ((iic_reg_ptr->IC_COMP_PARAM_1 >> 8) & 0xff) + 1;
+
+	return rxfifolen;
+}
+
+/** Set designware iic transfer in 7bit of 10bit addressing mode as a master */
+Inline void dw_iic_set_mstaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode)
+{
+#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
+	if (mode == IIC_7BIT_ADDRESS) {
+		iic_reg_ptr->IC_TAR &= ~IC_10BITADDR_MASTER;
+	} else {
+		iic_reg_ptr->IC_TAR |= IC_10BITADDR_MASTER;
+	}
+#else
+	dw_iic_disable(iic_reg_ptr);
+	if (mode == IIC_7BIT_ADDRESS) {
+		iic_reg_ptr->IC_CON &= ~MST_10_BIT_ADDR_MODE;
+	} else {
+		iic_reg_ptr->IC_CON |= MST_10_BIT_ADDR_MODE;
+	}
+	dw_iic_enable(iic_reg_ptr);
+#endif
+}
+
+/** Set designware iic transfer in 7bit of 10bit addressing mode as a slave */
+Inline void dw_iic_set_slvaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode)
+{
+	dw_iic_disable(iic_reg_ptr);
+	if (mode == IIC_7BIT_ADDRESS) {
+		iic_reg_ptr->IC_CON &= ~SLV_10_BIT_ADDR_MODE;
+	} else {
+		iic_reg_ptr->IC_CON |= SLV_10_BIT_ADDR_MODE;
+	}
+	dw_iic_enable(iic_reg_ptr);
+}
+
+/** Set designware iic transfer target address for addressing any iic slave device as a master */
+Inline void dw_iic_set_taraddr(DW_IIC_REG *iic_reg_ptr, uint32_t address)
+{
+#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
+	iic_reg_ptr->IC_TAR &= ~(IC_TAR_10BIT_ADDR_MASK);
+	iic_reg_ptr->IC_TAR |= (IC_TAR_10BIT_ADDR_MASK & address);
+#else
+	dw_iic_disable(iic_reg_ptr);
+	iic_reg_ptr->IC_TAR &= ~(IC_TAR_10BIT_ADDR_MASK);
+	iic_reg_ptr->IC_TAR |= (IC_TAR_10BIT_ADDR_MASK & address);
+	dw_iic_enable(iic_reg_ptr);
+#endif
+}
+
+/** Set designware iic slave address as a slave */
+Inline void dw_iic_set_slvaddr(DW_IIC_REG *iic_reg_ptr, uint32_t address)
+{
+	dw_iic_disable(iic_reg_ptr);
+	iic_reg_ptr->IC_SAR &= ~(IC_SAR_10BIT_ADDR_MASK);
+	iic_reg_ptr->IC_SAR |= (IC_SAR_10BIT_ADDR_MASK & address);
+	dw_iic_enable(iic_reg_ptr);
+}
+
+/** Select speed mode, and return proper speed mode configuration */
+Inline uint32_t dw_iic_select_speedmode(uint32_t speedmode)
+{
+	uint32_t speedcfg;
+
+	if (speedmode == IIC_SPEED_STANDARD) {
+		speedcfg = IC_CON_SPEED_STANDARD;
+	} else if (speedmode == IIC_SPEED_FAST) {
+		speedcfg = IC_CON_SPEED_FAST;
+	} else if (speedmode == IIC_SPEED_FASTPLUS) {
+		speedcfg = IC_CON_SPEED_FAST;
+	} else if (speedmode == IIC_SPEED_HIGH) {
+		speedcfg = IC_CON_SPEED_HIGH;
+	} else {
+		speedcfg = IC_CON_SPEED_HIGH;
+	}
+	return speedcfg;
+}
+/** Set designware iic speed mode */
+Inline void dw_iic_set_speedmode(DW_IIC_REG *iic_reg_ptr, uint32_t speedmode)
+{
+	uint32_t ic_con_val;
+
+	dw_iic_disable(iic_reg_ptr);
+	ic_con_val = iic_reg_ptr->IC_CON & (~IC_CON_SPEED_MASK);
+	ic_con_val |= dw_iic_select_speedmode(speedmode);
+	iic_reg_ptr->IC_CON = ic_con_val;
+	dw_iic_enable(iic_reg_ptr);
+}
+
+/** Set designware working mode as master or slave */
+Inline void dw_iic_set_working_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode)
+{
+	uint32_t ic_con_val;
+	dw_iic_disable(iic_reg_ptr);
+	ic_con_val = iic_reg_ptr->IC_CON & (~IC_CON_MST_SLV_MODE_MASK);
+	if (mode == DEV_MASTER_MODE) {
+		ic_con_val |= IC_CON_ENA_MASTER_MODE;
+	} else {
+		ic_con_val |= IC_CON_ENA_SLAVE_MODE;
+	}
+	dw_iic_enable(iic_reg_ptr);
+}
+
+/** Set IC_CLK frequency by configuration the *CNT registers for different speed modes */
+Inline void dw_iic_set_scl_cnt(DW_IIC_REG *iic_reg_ptr, DW_IIC_SCL_CNT *scl_cnt)
+{
+	dw_iic_disable(iic_reg_ptr);
+	iic_reg_ptr->IC_SS_SCL_HCNT = scl_cnt->ss_scl_hcnt;
+	iic_reg_ptr->IC_SS_SCL_LCNT = scl_cnt->ss_scl_lcnt;
+	iic_reg_ptr->IC_FS_SCL_HCNT = scl_cnt->fs_scl_hcnt;
+	iic_reg_ptr->IC_FS_SCL_LCNT = scl_cnt->fs_scl_lcnt;
+	iic_reg_ptr->IC_HS_SCL_HCNT = scl_cnt->hs_scl_hcnt;
+	iic_reg_ptr->IC_HS_SCL_LCNT = scl_cnt->hs_scl_lcnt;
+	dw_iic_enable(iic_reg_ptr);
+}
+
+/** Set spike suppression configuration */
+Inline void dw_iic_set_spike_len(DW_IIC_REG *iic_reg_ptr, DW_IIC_SPKLEN *spklen)
+{
+	dw_iic_disable(iic_reg_ptr);
+	iic_reg_ptr->IC_FS_SPKLEN = spklen->fs_spklen;
+	iic_reg_ptr->IC_HS_SPKLEN = spklen->hs_spklen;
+	dw_iic_enable(iic_reg_ptr);
+}
+
+Inline void dw_iic_flush_tx(DW_IIC_REG *iic_reg_ptr)
+{
+	(void)iic_reg_ptr->IC_CLR_INTR;
+}
+
+Inline void dw_iic_flush_rx(DW_IIC_REG *iic_reg_ptr)
+{
+}
+
+static uint32_t dw_iic_get_slv_state(DW_IIC_REG *iic_reg_ptr)
+{
+	uint32_t status;
+	uint32_t slv_state = IIC_SLAVE_STATE_FREE;
+
+	status = iic_reg_ptr->IC_RAW_INTR_STAT;
+	if (status & IC_INTR_STAT_GEN_CALL) {
+	/* General Call address is received and it is acknowledged */
+		slv_state |= IIC_SLAVE_STATE_GC_REQ;
+	}
+	if (status & IC_INTR_STAT_RX_FULL) {
+	/* master is attempting to write data to this slave */
+		slv_state |= IIC_SLAVE_STATE_WR_REQ;
+	}
+	if (status & IC_INTR_STAT_RD_REQ) {
+	/* master is attempting to read data from this slave */
+		slv_state |= IIC_SLAVE_STATE_RD_REQ;
+	}
+	if (status & IC_INTR_STAT_RX_DONE) {
+	/* master does not acknowledge a transmitted byte, and transmission is done */
+		slv_state |= IIC_SLAVE_STATE_RD_DONE;
+		status = iic_reg_ptr->IC_CLR_RX_DONE;
+	}
+	if (status & IC_INTR_STAT_START_DET) {
+	/* a START or RESTART condition has occurred */
+		slv_state |= IIC_SLAVE_STATE_START;
+		status = iic_reg_ptr->IC_CLR_START_DET; /* Clear it when read */
+	}
+	if (status & IC_INTR_STAT_STOP_DET) {
+	/* a STOP condition has occurred */
+		slv_state |= IIC_SLAVE_STATE_STOP;
+		status = iic_reg_ptr->IC_CLR_STOP_DET;  /* Clear it when read */
+	}
+	if (status & (IC_INTR_STAT_TX_ABRT|IC_INTR_STAT_TX_OVER\
+		|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
+	/* error case */
+		slv_state |= IIC_SLAVE_STATE_ERROR;
+		status = iic_reg_ptr->IC_CLR_TX_ABRT;  /* Clear it when read */
+		status = iic_reg_ptr->IC_CLR_TX_OVER;
+		status = iic_reg_ptr->IC_CLR_RX_OVER;
+		status = iic_reg_ptr->IC_CLR_RX_UNDER;
+	}
+
+	return slv_state;
+}
+
+/** Init Designware IIC Device into Master mode */
+static void dw_iic_master_init(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t speed_mode, uint32_t addr_mode, uint32_t tar_addr)
+{
+	uint32_t ic_con_val = 0;
+	DW_IIC_REG *iic_reg_ptr = iic_ctrl_ptr->dw_iic_regs;
+
+	dw_iic_disable(iic_reg_ptr);
+
+	/* disable all iic interrupt */
+	iic_reg_ptr->IC_INTR_MASK = IC_INT_DISABLE_ALL;
+
+	/* Set to 7bit addressing and update target address */
+	iic_reg_ptr->IC_TAR = (tar_addr & IC_TAR_10BIT_ADDR_MASK) | IC_TAR_SPECIAL | IC_TAR_GC_OR_START;
+	/* master mode, restart enabled */
+	ic_con_val = dw_iic_select_speedmode(speed_mode) | IC_CON_ENA_MASTER_MODE | IC_CON_RESTART_EN;
+
+#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
+	if (addr_mode == IIC_10BIT_ADDRESS) {
+		iic_reg_ptr->IC_TAR |= MST_10_BIT_ADDR_MODE;
+	}
+#else
+	if (addr_mode == IIC_10BIT_ADDRESS) {
+		ic_con_val |= MST_10_BIT_ADDR_MODE;
+	}
+#endif
+	/* Set final IC_CON value */
+	iic_reg_ptr->IC_CON = ic_con_val;
+	/* FIFO threshold settings */
+	iic_reg_ptr->IC_TX_TL = IIC_TX_THRESHOLD;
+	iic_reg_ptr->IC_RX_TL = IIC_RX_THRESHOLD;
+	/* Master code settings */
+	iic_reg_ptr->IC_HS_MADDR = iic_ctrl_ptr->iic_master_code;
+	dw_iic_enable(iic_reg_ptr);
+
+	/* Clock Settings */
+	dw_iic_set_scl_cnt(iic_reg_ptr, &(iic_ctrl_ptr->iic_scl_cnt));
+	dw_iic_set_spike_len(iic_reg_ptr, &(iic_ctrl_ptr->iic_spklen));
+}
+
+/** Init Designware IIC Device into Slave mode */
+static void dw_iic_slave_init(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t addr_mode, uint32_t slv_addr)
+{
+	uint32_t ic_con_val = 0;
+	DW_IIC_REG *iic_reg_ptr = iic_ctrl_ptr->dw_iic_regs;
+
+	dw_iic_disable(iic_reg_ptr);
+
+	/* disable all iic interrupt */
+	iic_reg_ptr->IC_INTR_MASK = IC_INT_DISABLE_ALL;
+
+	/* Set slave device address as a slave */
+	iic_reg_ptr->IC_SAR = slv_addr & IC_SAR_10BIT_ADDR_MASK;
+	/* slave mode, 7 bit slave address */
+	ic_con_val = IC_CON_ENA_SLAVE_MODE;
+	/* If addr mode select to be 10 bit address mode */
+	if (addr_mode == IIC_10BIT_ADDRESS) {
+		ic_con_val |= SLV_10_BIT_ADDR_MODE;
+	}
+
+	/* Set final IC_CON value */
+	iic_reg_ptr->IC_CON = ic_con_val;
+	/* FIFO threshold settings */
+	iic_reg_ptr->IC_TX_TL = IIC_TX_THRESHOLD;
+	iic_reg_ptr->IC_RX_TL = IIC_RX_THRESHOLD;
+
+	dw_iic_enable(iic_reg_ptr);
+}
+
+/** Check error for IIC master device */
+static int32_t dw_iic_mst_chkerr(DW_IIC_CTRL *iic_ctrl_ptr)
+{
+	uint32_t status;
+	int32_t ercd = IIC_ERR_NONE;
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	status = iic_reg_ptr->IC_RAW_INTR_STAT;
+	if (status & IC_INTR_STAT_TX_ABRT) {
+		status = iic_reg_ptr->IC_TX_ABRT_SOURCE;
+		if (status & IIC_MST_ABRT_LOST_BUS) {
+			ercd = IIC_ERR_LOST_BUS;
+		} else if (status & IIC_MST_ABRT_ADDR_NOACK) {
+			ercd = IIC_ERR_ADDR_NOACK;
+		} else if (status & IIC_MST_ABRT_DATA_NOACK) {
+			ercd = IIC_ERR_DATA_NOACK;
+		} else {
+			ercd = IIC_ERR_UNDEF;
+		}
+		status = iic_reg_ptr->IC_CLR_TX_ABRT;
+	} else {
+		if (status & IC_INTR_STAT_TX_OVER) {
+			iic_ctrl_ptr->iic_tx_over ++;
+			status = iic_reg_ptr->IC_CLR_TX_OVER;
+		}
+		if (status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
+			iic_ctrl_ptr->iic_rx_over ++;
+			status = iic_reg_ptr->IC_CLR_RX_OVER;
+			status = iic_reg_ptr->IC_CLR_RX_UNDER;
+		}
+	}
+	return ercd;
+}
+
+/** Check error for IIC slave device */
+static int32_t dw_iic_slv_chkerr(DW_IIC_CTRL *iic_ctrl_ptr)
+{
+	uint32_t status;
+	int32_t ercd = IIC_ERR_NONE;
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	status = iic_reg_ptr->IC_RAW_INTR_STAT;
+	if (status & IC_INTR_STAT_TX_ABRT) {
+		status = iic_reg_ptr->IC_TX_ABRT_SOURCE;
+		if (status & IIC_SLV_ABRT_LOST_BUS) {
+			ercd = IIC_ERR_LOST_BUS;
+		} else if (status & IC_TX_ABRT_SLVFLUSH_TXFIFO) {
+			/* Flush tx fifo */
+			status = iic_reg_ptr->IC_TX_ABRT_SOURCE;
+		} else {
+			ercd = IIC_ERR_UNDEF;
+		}
+		status = iic_reg_ptr->IC_CLR_TX_ABRT;
+	} else {
+		if (status & IC_INTR_STAT_TX_OVER) {
+			iic_ctrl_ptr->iic_tx_over ++;
+			status = iic_reg_ptr->IC_CLR_TX_OVER;
+		}
+		if (status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
+			iic_ctrl_ptr->iic_rx_over ++;
+			status = iic_reg_ptr->IC_CLR_RX_OVER;
+			status = iic_reg_ptr->IC_CLR_RX_UNDER;
+		}
+	}
+	return ercd;
+}
+
+/** enable designware iic */
+static void dw_iic_enable_device(DEV_IIC_INFO *iic_info_ptr)
+{
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	if ((iic_info_ptr->status & DEV_ENABLED) == 0) {
+		dw_iic_enable(iic_reg_ptr);
+		iic_info_ptr->status |= DEV_ENABLED;
+	}
+}
+
+/** disable designware iic */
+static void dw_iic_disable_device(DEV_IIC_INFO *iic_info_ptr)
+{
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+	uint32_t i;
+
+	for (i=0; i<DW_IIC_DISABLE_MAX_T_POLL_CNT; i++) {
+		dw_iic_disable(iic_reg_ptr);
+		if ((iic_reg_ptr->IC_ENABLE_STATUS & IC_ENABLE_STATUS_IC_EN) == 0) {
+			break;
+		}
+	}
+	iic_info_ptr->status &= ~DEV_ENABLED;
+}
+
+static void dw_iic_reset_device(DEV_IIC_INFO *iic_info_ptr)
+{
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	dw_iic_disable_device(iic_info_ptr);
+	dw_iic_clear_interrupt_all(iic_reg_ptr);
+	iic_info_ptr->next_cond = IIC_MODE_STOP;
+	iic_info_ptr->cur_state = IIC_FREE;
+	iic_info_ptr->err_state = IIC_ERR_NONE;
+	iic_ctrl_ptr->iic_tx_over = 0;
+	iic_ctrl_ptr->iic_rx_over = 0;
+	dw_iic_enable_device(iic_info_ptr);
+}
+
+/** Disable iic master interrupt for transmit or receive */
+static void dw_iic_mst_dis_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn)
+{
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	switch (cbrtn) {
+		case DW_IIC_RDY_SND:
+			dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_MST_TX_ENABLE);
+			iic_ctrl_ptr->int_status &= ~DW_IIC_TXINT_ENABLE;
+			break;
+		case DW_IIC_RDY_RCV:
+			dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_MST_RX_ENABLE);
+			iic_ctrl_ptr->int_status &= ~DW_IIC_RXINT_ENABLE;
+			break;
+		default:
+			break;
+	}
+}
+
+/** Disable iic slave interrupt for transmit or receive */
+static void dw_iic_slv_dis_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn)
+{
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	switch (cbrtn) {
+		case DW_IIC_RDY_SND:
+			dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_SLV_TX_ENABLE);
+			iic_ctrl_ptr->int_status &= ~DW_IIC_TXINT_ENABLE;
+			break;
+		case DW_IIC_RDY_RCV:
+			dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_SLV_RX_ENABLE);
+			iic_ctrl_ptr->int_status &= ~DW_IIC_RXINT_ENABLE;
+			break;
+		default:
+			break;
+	}
+}
+
+/** Enable iic master interrupt for transmit or receive */
+static void dw_iic_mst_ena_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn)
+{
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	switch (cbrtn) {
+		case DW_IIC_RDY_SND:
+			iic_ctrl_ptr->int_status |= DW_IIC_TXINT_ENABLE;
+			dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_MST_TX_ENABLE);
+			break;
+		case DW_IIC_RDY_RCV:
+			iic_ctrl_ptr->int_status |= DW_IIC_RXINT_ENABLE;
+			dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_MST_RX_ENABLE);
+			break;
+		default:
+			break;
+	}
+}
+
+/** Enable iic slave interrupt for transmit or receive */
+static void dw_iic_slv_ena_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn)
+{
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	switch (cbrtn) {
+		case DW_IIC_RDY_SND:
+			iic_ctrl_ptr->int_status |= DW_IIC_TXINT_ENABLE;
+			dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_SLV_TX_ENABLE);
+			break;
+		case DW_IIC_RDY_RCV:
+			iic_ctrl_ptr->int_status |= DW_IIC_RXINT_ENABLE;
+			dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_SLV_RX_ENABLE);
+			break;
+		default:
+			break;
+	}
+}
+
+/**
+ * \brief	disable designware iic send or receive interrupt
+ * \param[in]	DEV_IIC_INFO 	*iic_info_ptr
+ * \param[in]	cbrtn		control code of callback routine of send or receive
+ */
+static void dw_iic_dis_cbr(DEV_IIC_INFO *iic_info_ptr, uint32_t cbrtn)
+{
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+
+	if (iic_info_ptr->mode == DEV_MASTER_MODE) {
+		dw_iic_mst_dis_cbr(iic_ctrl_ptr, cbrtn);
+	} else {
+		dw_iic_slv_dis_cbr(iic_ctrl_ptr, cbrtn);
+	}
+
+	if (iic_ctrl_ptr->int_status & DW_IIC_GINT_ENABLE) {
+		if ((iic_ctrl_ptr->int_status & (DW_IIC_RXINT_ENABLE|DW_IIC_TXINT_ENABLE)) == 0) {
+			int_disable(iic_ctrl_ptr->intno);
+			iic_ctrl_ptr->int_status &= ~DW_IIC_GINT_ENABLE;
+		}
+	}
+}
+
+/**
+ * \brief	enable DesignWare IIC send or receive interrupt
+ * \param[in]	DEV_IIC_INFO 	*iic_info_ptr
+ * \param[in]	cbrtn		control code of callback routine of send or receive
+ */
+static void dw_iic_ena_cbr(DEV_IIC_INFO *iic_info_ptr, uint32_t cbrtn)
+{
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+
+	if (iic_info_ptr->mode == DEV_MASTER_MODE) {
+		dw_iic_mst_ena_cbr(iic_ctrl_ptr, cbrtn);
+	} else {
+		dw_iic_slv_ena_cbr(iic_ctrl_ptr, cbrtn);
+	}
+
+	if ((iic_ctrl_ptr->int_status & DW_IIC_GINT_ENABLE) == 0) {
+		if (iic_ctrl_ptr->int_status & (DW_IIC_RXINT_ENABLE|DW_IIC_TXINT_ENABLE)) {
+			iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE;
+			int_enable(iic_ctrl_ptr->intno);
+		}
+	}
+}
+
+/**
+ * \brief	enable designware iic interrupt
+ * \param	iic_info_ptr	iic information structure pointer
+ */
+static void dw_iic_enable_interrupt(DEV_IIC_INFO *iic_info_ptr)
+{
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+
+	int_handler_install(iic_ctrl_ptr->intno, iic_ctrl_ptr->dw_iic_int_handler);
+	iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE;
+	int_enable(iic_ctrl_ptr->intno);	/** enable iic interrupt */
+}
+/**
+ * \brief	disable designware iic interrupt
+ * \param	iic_info_ptr	iic information structure pointer
+ */
+static void dw_iic_disable_interrupt(DEV_IIC_INFO *iic_info_ptr)
+{
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+
+	/** disable iic send&receive interrupt after disable iic interrupt */
+	dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
+	dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
+	/* disable iic interrupt */
+	int_disable(iic_ctrl_ptr->intno);
+	iic_ctrl_ptr->int_status &= ~(DW_IIC_GINT_ENABLE|DW_IIC_TXINT_ENABLE|DW_IIC_RXINT_ENABLE);
+}
+
+/** abort current interrupt transmit transfer */
+static void dw_iic_abort_tx(DEV_IIC *iic_obj)
+{
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+
+	if (iic_ctrl_ptr->int_status & DW_IIC_TXINT_ENABLE) {
+		dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
+		iic_info_ptr->status |= DEV_IN_TX_ABRT;
+		if (iic_info_ptr->iic_cbs.tx_cb != NULL) {
+			iic_info_ptr->iic_cbs.tx_cb(iic_obj);
+		}
+		iic_info_ptr->status &= ~(DEV_IN_TX_ABRT);
+	}
+}
+
+/** abort current interrupt receive transfer */
+static void dw_iic_abort_rx(DEV_IIC *iic_obj)
+{
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+
+	if (iic_ctrl_ptr->int_status & DW_IIC_RXINT_ENABLE) {
+		dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
+		iic_info_ptr->status |= DEV_IN_RX_ABRT;
+		if (iic_info_ptr->iic_cbs.rx_cb != NULL) {
+			iic_info_ptr->iic_cbs.rx_cb(iic_obj);
+		}
+		iic_info_ptr->status &= ~(DEV_IN_RX_ABRT);
+	}
+}
+
+/** Get available transmit fifo count */
+static int32_t dw_iic_get_txavail(DW_IIC_CTRL *iic_ctrl_ptr)
+{
+	int32_t tx_avail = 0;
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	if (iic_ctrl_ptr->tx_fifo_len <= 1) {
+		if (dw_iic_putready(iic_reg_ptr) == 1) {
+			tx_avail = 1;
+		} else {
+			tx_avail = 0;
+		}
+	} else {
+		tx_avail = iic_ctrl_ptr->tx_fifo_len - iic_reg_ptr->IC_TXFLR;
+	}
+	return tx_avail;
+}
+
+/** Get available receive fifo count */
+static int32_t dw_iic_get_rxavail(DW_IIC_CTRL *iic_ctrl_ptr)
+{
+	int32_t rx_avail = 0;
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	if (iic_ctrl_ptr->rx_fifo_len <= 1) {
+		if (dw_iic_getready(iic_reg_ptr) == 1) {
+			rx_avail = 1;
+		} else {
+			rx_avail = 0;
+		}
+	} else {
+		rx_avail = iic_reg_ptr->IC_RXFLR;
+	}
+	return rx_avail;
+}
+
+/**
+ * IIC Master device transmit 1 data,
+ * next_cond can be \ref IC_DATA_CMD_STOP,
+ * \ref IC_DATA_CMD_RESTART and ref IC_DATA_CMD_NONE
+ */
+static int32_t dw_iic_mst_write_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t data, uint32_t next_cond)
+{
+	uint32_t i = 0;
+	int32_t ercd = IIC_ERR_NONE;
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	while (dw_iic_putready(iic_reg_ptr) == 0) {
+		if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT;
+		ercd = dw_iic_mst_chkerr(iic_ctrl_ptr);
+		if (ercd != IIC_ERR_NONE) return ercd;
+	}
+	dw_iic_putdata(iic_reg_ptr, data|IC_DATA_CMD_WRITE_REQ|next_cond);
+
+	return ercd;
+}
+
+/** IIC Slave device transmit 1 data */
+static int32_t dw_iic_slv_write_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t data)
+{
+	uint32_t i = 0;
+	int32_t ercd = IIC_ERR_NONE;
+	uint32_t slv_state, temp;
+	uint32_t ready2send = 0;
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	for (i = 0; i < iic_ctrl_ptr->retry_cnt; i++) {
+		ercd = dw_iic_slv_chkerr(iic_ctrl_ptr);
+		if (ercd != IIC_ERR_NONE) return ercd;
+		slv_state = iic_reg_ptr->IC_RAW_INTR_STAT;
+		if (slv_state & IC_INTR_STAT_RD_REQ) {
+			if (dw_iic_putready(iic_reg_ptr)) {
+				temp = iic_reg_ptr->IC_CLR_RD_REQ;
+				ready2send = 1;
+				break;
+			}
+		} else if (slv_state & IC_INTR_STAT_RX_DONE) { /* Put RX Done before STOP */
+			temp = iic_reg_ptr->IC_CLR_RX_DONE;
+			return IIC_ERR_MSTSTOP;
+		} else if (slv_state & IC_INTR_STAT_STOP_DET) {
+			temp = iic_reg_ptr->IC_CLR_STOP_DET;
+			return IIC_ERR_MSTSTOP;
+		}
+	}
+	if (ready2send) {
+		dw_iic_putdata(iic_reg_ptr, data|IC_DATA_CMD_WRITE_REQ);
+	} else {
+		ercd = IIC_ERR_TIMEOUT;
+	}
+
+	return ercd;
+}
+
+/**
+ * IIC Master device receive 1 data,
+ * next_cond can be \ref IC_DATA_CMD_STOP,
+ * \ref IC_DATA_CMD_RESTART and ref IC_DATA_CMD_NONE
+ */
+static int32_t dw_iic_mst_read_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t *data, uint32_t next_cond)
+{
+	uint32_t i = 0;
+	int32_t ercd = IIC_ERR_NONE;
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	/* Issue a read request */
+	while (dw_iic_putready(iic_reg_ptr) == 0) {
+		if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT;
+		ercd = dw_iic_mst_chkerr(iic_ctrl_ptr);
+		if (ercd != IIC_ERR_NONE) return ercd;
+	}
+	dw_iic_putdata(iic_reg_ptr, next_cond|IC_DATA_CMD_READ_REQ);
+	/* Wait to read data */
+	i = 0;
+	while (dw_iic_getready(iic_reg_ptr) == 0) {
+		if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT;
+		ercd = dw_iic_mst_chkerr(iic_ctrl_ptr);
+		if (ercd != IIC_ERR_NONE) return ercd;
+	}
+	*data = dw_iic_getdata(iic_reg_ptr);
+	return ercd;
+}
+
+/** IIC Slave device receive 1 data */
+static int32_t dw_iic_slv_read_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t *data)
+{
+	uint32_t i = 0;
+	int32_t ercd = IIC_ERR_NONE;
+	uint32_t slv_state, temp;
+	uint32_t ready2read = 0;
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	for (i = 0; i < iic_ctrl_ptr->retry_cnt; i++) {
+		ercd = dw_iic_slv_chkerr(iic_ctrl_ptr);
+		if (ercd != IIC_ERR_NONE) return ercd;
+		slv_state = iic_reg_ptr->IC_RAW_INTR_STAT;
+		if (slv_state & IC_INTR_STAT_START_DET) {
+			temp = iic_reg_ptr->IC_CLR_START_DET;
+		}
+		if (slv_state & IC_INTR_STAT_RX_FULL) {
+			if (dw_iic_getready(iic_reg_ptr)) {
+				ready2read = 1;
+				break;
+			}
+		} else if (slv_state & IC_INTR_STAT_STOP_DET) {
+			temp = iic_reg_ptr->IC_CLR_STOP_DET;
+			return IIC_ERR_MSTSTOP;
+		}
+	}
+	if (ready2read) {
+		*data = dw_iic_getdata(iic_reg_ptr);
+	} else {
+		ercd = IIC_ERR_TIMEOUT;
+	}
+
+	return ercd;
+}
+
+/** IIC Master transmit called in interrupt */
+static void dw_iic_mst_int_write(DEV_IIC *iic_obj)
+{
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs);
+	uint32_t iic_int_status; /** iic interrupt status */
+	uint32_t last_cond, xmit_data, xmit_end = 0;
+	DEV_BUFFER *buf_ptr;
+	uint8_t *p_charbuf;
+
+	if (iic_info_ptr->next_cond == IIC_MODE_STOP) {
+		last_cond = IC_DATA_CMD_STOP;
+	} else {
+		last_cond = IC_DATA_CMD_RESTART;
+	}
+	iic_int_status = (iic_reg_ptr->IC_INTR_STAT);
+	buf_ptr = &(iic_info_ptr->tx_buf);
+	p_charbuf = (uint8_t *)buf_ptr->buf;
+	if (p_charbuf) {
+		if (iic_int_status & IC_INTR_STAT_TX_EMPTY) {
+			xmit_end = 0;
+			while (dw_iic_putready(iic_reg_ptr)) {
+				xmit_data = (uint32_t)(p_charbuf[buf_ptr->ofs])|IC_DATA_CMD_WRITE_REQ;
+				if (buf_ptr->ofs == (buf_ptr->len-1)) {
+					xmit_end = 1;
+					xmit_data |= last_cond;
+				} else {
+					xmit_data |= IC_DATA_CMD_NONE;
+				}
+				buf_ptr->ofs ++;
+				dw_iic_putdata(iic_reg_ptr, xmit_data);
+				if (xmit_end) {
+					dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
+					iic_info_ptr->cur_state = IIC_FREE;
+					if (iic_info_ptr->iic_cbs.tx_cb) {
+						iic_info_ptr->iic_cbs.tx_cb(iic_obj);
+					}
+					/* clear the send buffer pointer */
+					memset(buf_ptr, 0, sizeof(DEV_BUFFER));
+					break;
+				}
+			}
+		}
+		if (iic_int_status & IC_INTR_STAT_TX_OVER) {
+			iic_ctrl_ptr->iic_tx_over ++;
+		}
+		if (iic_int_status & IC_INTR_STAT_TX_ABRT) {
+			iic_info_ptr->err_state = dw_iic_mst_chkerr(iic_ctrl_ptr);
+			if (iic_info_ptr->err_state != IIC_ERR_NONE) {
+				dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
+				iic_info_ptr->cur_state = IIC_FREE;
+				if (iic_info_ptr->iic_cbs.err_cb) {
+					iic_info_ptr->iic_cbs.err_cb(iic_obj);
+				}
+				/* clear the send buffer pointer */
+				memset(buf_ptr, 0, sizeof(DEV_BUFFER));
+			}
+		}
+	} else {
+		dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
+		iic_info_ptr->cur_state = IIC_FREE;
+	}
+	/* Clear Interrupt */
+	iic_int_status = iic_reg_ptr->IC_CLR_INTR;
+}
+
+/** IIC Master receive called in interrupt */
+static void dw_iic_mst_int_read(DEV_IIC *iic_obj)
+{
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs);
+	uint32_t iic_int_status; /** iic interrupt status */
+	uint32_t last_cond, xmit_data;
+	DEV_BUFFER *buf_ptr;
+	DW_IIC_BUFFER *dw_iic_rxbuf_ptr;
+	uint8_t *p_charbuf;
+
+	if (iic_info_ptr->next_cond == IIC_MODE_STOP) {
+		last_cond = IC_DATA_CMD_STOP;
+	} else {
+		last_cond = IC_DATA_CMD_RESTART;
+	}
+	iic_int_status = (iic_reg_ptr->IC_INTR_STAT);
+	buf_ptr = &(iic_info_ptr->rx_buf);
+	p_charbuf = (uint8_t *)buf_ptr->buf;
+	if (p_charbuf) {
+		dw_iic_rxbuf_ptr = &(iic_ctrl_ptr->dw_iic_rxbuf);
+		if (iic_int_status & IC_INTR_STAT_TX_EMPTY) {
+			while (dw_iic_putready(iic_reg_ptr)) {
+				if (dw_iic_rxbuf_ptr->ofs >= dw_iic_rxbuf_ptr->len) {
+					dw_iic_mask_interrupt(iic_reg_ptr, IC_INTR_STAT_TX_EMPTY);
+					break;
+				}
+				xmit_data = IC_DATA_CMD_READ_REQ;
+				if (dw_iic_rxbuf_ptr->ofs == (dw_iic_rxbuf_ptr->len-1)) {
+					xmit_data |= last_cond;
+				} else {
+					xmit_data |= IC_DATA_CMD_NONE;
+				}
+				dw_iic_rxbuf_ptr->ofs ++;
+				dw_iic_putdata(iic_reg_ptr, xmit_data);
+			}
+		}
+		if (iic_int_status & IC_INTR_STAT_RX_FULL) {
+			while (dw_iic_getready(iic_reg_ptr)) {
+				p_charbuf[buf_ptr->ofs] = dw_iic_getdata(iic_reg_ptr);
+				buf_ptr->ofs ++;
+				if (buf_ptr->ofs >= buf_ptr->len) {
+					dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
+					iic_info_ptr->cur_state = IIC_FREE;
+					if (iic_info_ptr->iic_cbs.rx_cb) {
+						iic_info_ptr->iic_cbs.rx_cb(iic_obj);
+					}
+					/* clear the send buffer pointer */
+					memset(buf_ptr, 0, sizeof(DEV_BUFFER));
+					dw_iic_rxbuf_ptr->ofs = 0;
+					dw_iic_rxbuf_ptr->len = 0;
+					break;
+				}
+			}
+		}
+		if (iic_int_status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
+			iic_ctrl_ptr->iic_rx_over ++;
+		}
+		if (iic_int_status & IC_INTR_STAT_TX_ABRT) {
+			iic_info_ptr->err_state = dw_iic_mst_chkerr(iic_ctrl_ptr);
+			if (iic_info_ptr->err_state != IIC_ERR_NONE) {
+				dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
+				iic_info_ptr->cur_state = IIC_FREE;
+				if (iic_info_ptr->iic_cbs.err_cb) {
+					iic_info_ptr->iic_cbs.err_cb(iic_obj);
+				}
+				/* clear the send buffer pointer */
+				memset(buf_ptr, 0, sizeof(DEV_BUFFER));
+				dw_iic_rxbuf_ptr->ofs = 0;
+				dw_iic_rxbuf_ptr->len = 0;
+			}
+		}
+	} else {
+		dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
+		iic_info_ptr->cur_state = IIC_FREE;
+	}
+	/* Clear Interrupt */
+	iic_int_status = iic_reg_ptr->IC_CLR_INTR;
+}
+
+/** IIC Slave transmit called in interrupt */
+static void dw_iic_slv_int_process(DEV_IIC *iic_obj)
+{
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs);
+	uint32_t iic_int_status; /** iic interrupt status */
+
+	iic_int_status = (iic_reg_ptr->IC_INTR_STAT);
+	if (iic_int_status & IC_INTR_STAT_RD_REQ) { /* Read request from master */
+		if (iic_info_ptr->iic_cbs.tx_cb) {
+			iic_info_ptr->iic_cbs.tx_cb(iic_obj);
+		} else { /* When tx callback function is not set disable this tx int for slave */
+			dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
+		}
+	}
+	if (iic_int_status & IC_INTR_STAT_RX_FULL) { /* Write request from master */
+		if (iic_info_ptr->iic_cbs.rx_cb) {
+			iic_info_ptr->iic_cbs.rx_cb(iic_obj);
+		} else { /* When rx callback function is not set disable this rx int for slave */
+			dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
+		}
+	}
+	if (iic_int_status & IC_INTR_STAT_TX_OVER) {
+		iic_ctrl_ptr->iic_tx_over ++;
+	}
+	if (iic_int_status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
+		iic_ctrl_ptr->iic_rx_over ++;
+	}
+	if (iic_int_status & IC_INTR_STAT_TX_ABRT) {
+		iic_info_ptr->err_state = dw_iic_slv_chkerr(iic_ctrl_ptr);
+		if (iic_info_ptr->err_state != IIC_ERR_NONE) {
+			if (iic_info_ptr->iic_cbs.err_cb) {
+				iic_info_ptr->iic_cbs.err_cb(iic_obj);
+			}
+		}
+	}
+	/* Clear Interrupt */
+	iic_int_status = iic_reg_ptr->IC_CLR_INTR;
+}
+
+/** @} end of group DEVICE_DW_IIC_STATIC */
+
+/**
+ * \defgroup	DEVICE_DW_IIC_IMPLEMENT	DesignWare IIC Driver Function API Implement
+ * \ingroup	DEVICE_DW_IIC
+ * \brief	implement device hal iic api with DesignWare IIC
+ * @{
+ */
+
+/**
+ * \brief	open a designware iic device
+ * \param[in]	iic_obj	iic device object pointer
+ * \param[in]	mode	iic working mode (master or slave)
+ * \param[in]	param	When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_iic_info::speed_mode "speed mode",
+ *			when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_iic_info::slv_addr "slave device 7bit address"
+ * \retval	E_OK	Open successfully without any issues
+ * \retval	E_OPNED	If device was opened before with different parameters,
+ *			then just increase the \ref dev_iic_info::opn_cnt "opn_cnt" and return \ref E_OPNED
+ * \retval	E_OBJ	Device object is not valid
+ * \retval	E_SYS	Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first.
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_NOSPT	Open settings are not supported
+ */
+int32_t dw_iic_open (DEV_IIC *iic_obj, uint32_t mode, uint32_t param)
+{
+	int32_t ercd = E_OK;
+	uint32_t support_modes;
+	uint32_t param2check;
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
+	DW_IIC_CHECK_EXP((mode==DEV_MASTER_MODE)||(mode==DEV_SLAVE_MODE), E_PAR);
+	if (mode == DEV_MASTER_MODE) {
+		DW_IIC_CHECK_EXP((param>=IIC_SPEED_STANDARD) && (param<=IIC_SPEED_ULTRA), E_PAR);
+	}
+	/* END OF ERROR CHECK */
+
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+
+	/* Check supported modes, master or slave */
+	support_modes = iic_ctrl_ptr->support_modes;
+	DW_IIC_CHECK_EXP( (((support_modes)&DW_IIC_MASTER_SUPPORTED)&&(mode == DEV_MASTER_MODE)) || \
+				(((support_modes)&DW_IIC_SLAVE_SUPPORTED)&&(mode == DEV_SLAVE_MODE)), E_NOSPT);
+
+	/** Check opened before use case */
+	if (iic_info_ptr->opn_cnt > 0) {
+		if (mode != iic_info_ptr->mode) {
+			/* current working mode is different from passing mode */
+			return E_SYS;
+		}
+		if (mode == DEV_MASTER_MODE) { /* param is speed_mode when as master */
+			param2check = iic_info_ptr->speed_mode;
+		} else { /* param is slv_addr when as slave */
+			param2check = iic_info_ptr->slv_addr;
+		}
+		iic_info_ptr->opn_cnt ++;
+		if (param != param2check) { /* open with different speed mode */
+			return E_OPNED;
+		} else {
+			return E_OK;
+		}
+	}
+	/* auto increase open count */
+	iic_info_ptr->opn_cnt ++;
+
+	iic_info_ptr->mode = mode;
+	if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) {
+		iic_info_ptr->tar_addr &= IIC_7BIT_ADDRESS_MASK;
+		iic_info_ptr->slv_addr &= IIC_7BIT_ADDRESS_MASK;
+	} else {
+		iic_info_ptr->addr_mode = IIC_10BIT_ADDRESS;
+		iic_info_ptr->tar_addr &= IIC_10BIT_ADDRESS_MASK;
+		iic_info_ptr->slv_addr &= IIC_10BIT_ADDRESS_MASK;
+	}
+
+/* Do FIFO Length get before init */
+#if DW_IIC_CALC_FIFO_LEN_ENABLE
+	iic_ctrl_ptr->tx_fifo_len = dw_iic_get_txfifo_len(iic_ctrl_ptr->dw_iic_regs);
+	iic_ctrl_ptr->rx_fifo_len = dw_iic_get_rxfifo_len(iic_ctrl_ptr->dw_iic_regs);
+#endif
+
+	/* Disable device before init it */
+	dw_iic_disable_device(iic_info_ptr);
+
+	if (mode == DEV_MASTER_MODE) {
+		iic_info_ptr->speed_mode = param;
+		dw_iic_master_init(iic_ctrl_ptr, param, iic_info_ptr->addr_mode, iic_info_ptr->tar_addr);
+	} else {
+		iic_info_ptr->slv_addr = param;
+		dw_iic_slave_init(iic_ctrl_ptr, iic_info_ptr->addr_mode, param);
+	}
+	iic_info_ptr->status = DEV_ENABLED;
+	iic_info_ptr->cur_state = IIC_FREE;
+	iic_info_ptr->err_state = IIC_ERR_NONE;
+	iic_info_ptr->next_cond = IIC_MODE_STOP;
+	iic_info_ptr->extra = NULL;
+
+	iic_ctrl_ptr->iic_tx_over = 0;
+	iic_ctrl_ptr->iic_rx_over = 0;
+	iic_ctrl_ptr->int_status = 0;
+	memset(&(iic_ctrl_ptr->dw_iic_rxbuf), 0, sizeof(DW_IIC_BUFFER));
+	iic_ctrl_ptr->dw_iic_rxbuf.buf = &(iic_info_ptr->rx_buf);
+	/** install iic interrupt into system */
+	dw_iic_disable_interrupt(iic_info_ptr);
+	int_handler_install(iic_ctrl_ptr->intno, iic_ctrl_ptr->dw_iic_int_handler);
+	memset(&(iic_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER));
+	memset(&(iic_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER));
+	memset(&(iic_info_ptr->iic_cbs), 0, sizeof(DEV_IIC_CBS));
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	Close a DesignWare IIC device
+ * \param[in]	iic_obj	iic device object pointer
+ * \retval	E_OK	Close successfully without any issues(including secenary that device is already closed)
+ * \retval	E_OPNED	Device is still opened, the device \ref dev_iic_info::opn_cnt "opn_cnt" decreased by 1
+ * \retval	E_OBJ	Device object is not valid
+ */
+int32_t dw_iic_close (DEV_IIC *iic_obj)
+{
+	int32_t ercd = E_OK;
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
+	DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_OK);
+	/* END OF ERROR CHECK */
+
+	iic_info_ptr->opn_cnt --;
+	if (iic_info_ptr->opn_cnt == 0) {
+		dw_iic_disable_interrupt(iic_info_ptr);
+		dw_iic_abort_tx(iic_obj);
+		dw_iic_abort_rx(iic_obj);
+		memset(&(iic_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER));
+		memset(&(iic_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER));
+		memset(&(iic_info_ptr->iic_cbs), 0, sizeof(DEV_IIC_CBS));
+		dw_iic_disable_device(iic_info_ptr);
+		iic_info_ptr->status = DEV_DISABLED;
+		iic_info_ptr->next_cond = IIC_MODE_STOP;
+		iic_info_ptr->extra = NULL;
+	} else {
+		ercd = E_OPNED;
+	}
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	Control iic by ctrl command
+ * \param[in]	iic_obj	iic device object pointer
+ * \param[in]		ctrl_cmd	\ref DEVICE_HAL_IIC_CTRLCMD "control command", to change or get some thing related to iic
+ * \param[in,out]	param		parameters that maybe argument of the command,
+ * 					or return values of the command, must not be NULL
+ * \retval	E_OK	Control device successfully
+ * \retval	E_CLSED	Device is not opened
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
+ * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
+ * \retval	E_NOSPT	Control command is not supported or not valid
+ */
+int32_t dw_iic_control (DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param)
+{
+	int32_t ercd = E_OK;
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
+	DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED);
+	/* END OF ERROR CHECK */
+
+	uint32_t val32; /** to receive unsigned int value */
+	DEV_BUFFER *devbuf;
+
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
+	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
+
+	/* check whether current device is disabled */
+	if ((iic_info_ptr->status & DEV_ENABLED) == 0) {
+		/** When device is disabled,
+		 * only IIC_CMD_ENA_DEV, IIC_CMD_DIS_DEV, IIC_CMD_GET_STATUS, IIC_CMD_RESET
+		 * are available, other commands will return E_SYS
+		 */
+		if ((ctrl_cmd != IIC_CMD_ENA_DEV) && \
+			(ctrl_cmd != IIC_CMD_DIS_DEV) && \
+			(ctrl_cmd != IIC_CMD_GET_STATUS) && \
+			(ctrl_cmd != IIC_CMD_RESET) ) {
+			return E_SYS;
+		}
+	}
+
+	switch (ctrl_cmd) {
+		/* Commmon commands for both master and slave mode */
+		case IIC_CMD_GET_STATUS:
+			DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = iic_info_ptr->status;
+			break;
+		case IIC_CMD_ENA_DEV:
+			dw_iic_enable_device(iic_info_ptr);
+			break;
+		case IIC_CMD_DIS_DEV:
+			dw_iic_disable_device(iic_info_ptr);
+			break;
+		case IIC_CMD_RESET:
+			dw_iic_reset_device(iic_info_ptr);
+			break;
+		case IIC_CMD_FLUSH_TX:
+			dw_iic_flush_tx(iic_reg_ptr);
+			break;
+		case IIC_CMD_FLUSH_RX:
+			dw_iic_flush_rx(iic_reg_ptr);
+			break;
+		case IIC_CMD_SET_ADDR_MODE:
+			val32 = (uint32_t)param;
+			DW_IIC_CHECK_EXP((val32==IIC_7BIT_ADDRESS) || (val32==IIC_10BIT_ADDRESS), E_PAR);
+			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
+				dw_iic_set_mstaddr_mode(iic_reg_ptr, val32);
+			} else {
+				dw_iic_set_slvaddr_mode(iic_reg_ptr, val32);
+			}
+			iic_info_ptr->addr_mode = val32;
+			break;
+		case IIC_CMD_GET_RXAVAIL:
+			DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = dw_iic_get_rxavail(iic_ctrl_ptr);
+			break;
+		case IIC_CMD_GET_TXAVAIL:
+			DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = dw_iic_get_txavail(iic_ctrl_ptr);
+			break;
+		case IIC_CMD_SET_TXCB:
+			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			iic_info_ptr->iic_cbs.tx_cb = param;
+			break;
+		case IIC_CMD_SET_RXCB:
+			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			iic_info_ptr->iic_cbs.rx_cb = param;
+			break;
+		case IIC_CMD_SET_ERRCB:
+			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			iic_info_ptr->iic_cbs.err_cb = param;
+			break;
+		case IIC_CMD_ABORT_TX:
+			dw_iic_abort_tx(iic_obj);
+			if ((iic_info_ptr->mode == DEV_MASTER_MODE) \
+				&& (iic_info_ptr->cur_state == IIC_IN_TX)) {
+				iic_info_ptr->cur_state = IIC_FREE;
+			}
+			break;
+		case IIC_CMD_ABORT_RX:
+			dw_iic_abort_rx(iic_obj);
+			if ((iic_info_ptr->mode == DEV_MASTER_MODE) \
+				&& (iic_info_ptr->cur_state == IIC_IN_RX)) {
+				iic_info_ptr->cur_state = IIC_FREE;
+			}
+			break;
+		case IIC_CMD_SET_TXINT:
+			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
+				DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_RX, E_CTX);
+			}
+			val32 = (uint32_t)param;
+			if (val32 == 0) {
+				dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
+				iic_info_ptr->cur_state = IIC_FREE;
+			} else {
+				iic_info_ptr->cur_state = IIC_IN_TX;
+				dw_iic_ena_cbr(iic_info_ptr, DW_IIC_RDY_SND);
+			}
+			break;
+		case IIC_CMD_SET_RXINT:
+			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
+				DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_TX, E_CTX);
+			}
+			val32 = (uint32_t)param;
+			if (val32 == 0) {
+				iic_info_ptr->cur_state = IIC_FREE;
+				dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
+			} else {
+				iic_info_ptr->cur_state = IIC_IN_RX;
+				dw_iic_ena_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
+			}
+			break;
+		case IIC_CMD_SET_TXINT_BUF:
+			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
+				DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_TX, E_CTX);
+			}
+			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			if (param != NULL) {
+				devbuf = (DEV_BUFFER *)param;
+				iic_info_ptr->tx_buf = *devbuf;
+				iic_info_ptr->tx_buf.ofs = 0;
+			} else {
+				iic_info_ptr->tx_buf.buf = NULL;
+				iic_info_ptr->tx_buf.len = 0;
+				iic_info_ptr->tx_buf.ofs = 0;
+			}
+			break;
+		case IIC_CMD_SET_RXINT_BUF:
+			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
+				DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_RX, E_CTX);
+			}
+			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			if (param != NULL) {
+				devbuf = (DEV_BUFFER *)param;
+				iic_info_ptr->rx_buf = *devbuf;
+				iic_info_ptr->rx_buf.ofs = 0;
+				iic_ctrl_ptr->dw_iic_rxbuf.ofs = 0;
+				iic_ctrl_ptr->dw_iic_rxbuf.len = devbuf->len;
+			} else {
+				iic_info_ptr->rx_buf.buf = NULL;
+				iic_info_ptr->rx_buf.len = 0;
+				iic_info_ptr->rx_buf.ofs = 0;
+				iic_ctrl_ptr->dw_iic_rxbuf.ofs = 0;
+				iic_ctrl_ptr->dw_iic_rxbuf.len = 0;
+			}
+			break;
+
+		/* Master mode only commands */
+		case IIC_CMD_MST_SET_SPEED_MODE:
+			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
+			val32 = (uint32_t)param;
+			DW_IIC_CHECK_EXP((val32>=IIC_SPEED_STANDARD) && (val32<=IIC_SPEED_ULTRA), E_PAR);
+			dw_iic_set_speedmode(iic_reg_ptr, val32);
+			iic_info_ptr->speed_mode = val32;
+			break;
+		case IIC_CMD_MST_SET_TAR_ADDR:
+			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
+			if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) {
+				val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK;
+			} else {
+				val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK;
+			}
+			if (val32 != iic_info_ptr->tar_addr) {
+				dw_iic_set_taraddr(iic_reg_ptr, val32);
+				iic_info_ptr->tar_addr = val32;
+			}
+			break;
+		case IIC_CMD_MST_SET_NEXT_COND:
+			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
+			val32 = (uint32_t)param;
+			DW_IIC_CHECK_EXP((val32==IIC_MODE_STOP) || (val32==IIC_MODE_RESTART), E_PAR);
+			iic_info_ptr->next_cond = (uint32_t)param;
+			break;
+
+		/* Slave mode only commands */
+		case IIC_CMD_SLV_SET_SLV_ADDR:
+			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_SLAVE_MODE, E_NOSPT);
+			if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) {
+				val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK;
+			} else {
+				val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK;
+			}
+			dw_iic_set_slvaddr(iic_reg_ptr, val32);
+			iic_info_ptr->slv_addr = val32;
+			break;
+		case IIC_CMD_SLV_GET_SLV_STATE:
+			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_SLAVE_MODE, E_NOSPT);
+			DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((uint32_t *)param) = dw_iic_get_slv_state(iic_reg_ptr);
+			break;
+
+		default:
+			ercd = E_NOSPT;
+			break;
+	}
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	poll transmit data through DesignWare IIC as master or slave
+ * \param[in]	iic_obj	iic device object pointer
+ * \param[in]	data	data that need to send (data must be uint8_t type)
+ * \param[in]	len	data length need to send
+ * \retval	>0	Byte count that was successfully sent for poll method,
+ * 			it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state".
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_CTX	Device is still in transfer state
+ * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
+ */
+int32_t dw_iic_write (DEV_IIC *iic_obj, const void *data, uint32_t len)
+{
+	int32_t ercd = E_OK;
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
+	DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED);
+	DW_IIC_CHECK_EXP(iic_info_ptr->status & DEV_ENABLED, E_SYS);
+	DW_IIC_CHECK_EXP(data!=NULL, E_PAR);
+	DW_IIC_CHECK_EXP(len>0, E_PAR);
+	/* END OF ERROR CHECK */
+
+	int32_t i = 0;
+	uint32_t last_cond = 0; /* Last data for transmit, STOP or RESTART */
+	int32_t error_state = IIC_ERR_NONE;
+	const uint8_t *p_charbuf = (const uint8_t *)data;
+
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
+
+	if (iic_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode transmit data */
+		if (iic_info_ptr->next_cond == IIC_MODE_STOP) {
+			last_cond = IC_DATA_CMD_STOP;
+		} else {
+			last_cond = IC_DATA_CMD_RESTART;
+		}
+
+		/* Try to transmit 0 -> (len-1) data */
+		len = len - 1; /* Last data write differently */
+		while (i < len) {
+			error_state = dw_iic_mst_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[i]), IC_DATA_CMD_NONE);
+			if (error_state != IIC_ERR_NONE) {
+				break;
+			}
+			i ++;
+		}
+		/* Try to transmit the last data with STOP or RESTART condition */
+		if (error_state == IIC_ERR_NONE) {
+			error_state = dw_iic_mst_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[len]), last_cond);
+			if (error_state == IIC_ERR_NONE) {
+				i = i + 1; /* Add last data into send count */
+			}
+		}
+	} else { /* Slave mode transmit data */
+		while (i < len) {
+			error_state = dw_iic_slv_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[i]));
+			if (error_state != IIC_ERR_NONE) {
+				break;
+			}
+			i ++;
+		}
+	}
+	iic_info_ptr->err_state = error_state;
+	ercd = i;
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	read data through DesignWare IIC
+ * \param[in]	iic_obj	iic device object pointer
+ * \param[out]	data	data that need to read (data must be uint8_t type)
+ * \param[in]	len	data count need to read
+ * \retval	>0	Byte count that was successfully received for poll method,
+ * 			it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state".
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_CTX	Device is still in transfer state
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
+ */
+int32_t dw_iic_read (DEV_IIC *iic_obj, void *data, uint32_t len)
+{
+	int32_t ercd = E_OK;
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
+	DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED);
+	DW_IIC_CHECK_EXP(iic_info_ptr->status & DEV_ENABLED, E_SYS);
+	DW_IIC_CHECK_EXP(data!=NULL, E_PAR);
+	DW_IIC_CHECK_EXP(len>0, E_PAR);
+	/* END OF ERROR CHECK */
+
+	int32_t i = 0;
+	uint32_t last_cond = 0; /* Last data for receive, STOP or RESTART */
+	uint32_t val32 = 0;
+	int32_t error_state = IIC_ERR_NONE;
+	uint8_t *p_charbuf = (uint8_t *)data;
+
+	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
+
+	if (iic_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode receive data */
+		if (iic_info_ptr->next_cond == IIC_MODE_STOP) {
+			last_cond = IC_DATA_CMD_STOP;
+		} else {
+			last_cond = IC_DATA_CMD_RESTART;
+		}
+
+		/* Try to receive 0 -> (len-1) data */
+		len = len - 1; /* Last data write differently */
+		while (i < len) {
+			error_state = dw_iic_mst_read_data(iic_ctrl_ptr, &val32, IC_DATA_CMD_NONE);
+			if (error_state != IIC_ERR_NONE) {
+				break;
+			} else {
+				p_charbuf[i] = (uint8_t)val32;
+			}
+			i ++;
+		}
+		/* Try to receive the last data with STOP or RESTART condition */
+		if (error_state == IIC_ERR_NONE) {
+			error_state = dw_iic_mst_read_data(iic_ctrl_ptr, &val32, last_cond);
+			if (error_state == IIC_ERR_NONE) {
+				p_charbuf[len] = (uint8_t)val32;
+				i = i + 1; /* Add last data into send count */
+			}
+		}
+	} else { /* Slave mode receive data */
+		while (i < len) {
+			error_state = dw_iic_slv_read_data(iic_ctrl_ptr, &val32);
+			if (error_state != IIC_ERR_NONE) {
+				break;
+			} else {
+				p_charbuf[i] = (uint8_t)val32;
+			}
+			i ++;
+		}
+	}
+	iic_info_ptr->err_state = error_state;
+	ercd = i;
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	DesignWare IIC interrupt processing routine
+ * \param[in]	iic_info_ptr	DEV_IIC *iic_obj
+ * \param[in]	ptr		extra information
+ */
+void dw_iic_isr(DEV_IIC *iic_obj, void *ptr)
+{
+	int32_t ercd = E_OK;
+	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
+	/* END OF ERROR CHECK */
+
+	if (iic_info_ptr->mode == DEV_MASTER_MODE) {
+		if (iic_info_ptr->cur_state == IIC_IN_TX) {
+			dw_iic_mst_int_write(iic_obj);
+		} else {
+			dw_iic_mst_int_read(iic_obj);
+		}
+	} else {
+		dw_iic_slv_int_process(iic_obj);
+	}
+
+error_exit:
+	return;
+}
+/** @} end of group DEVICE_DW_IIC_IMPLEMENT */
diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic.h
new file mode 100644
index 0000000000..55c551a67e
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/iic/dw_iic.h
@@ -0,0 +1,242 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-06-30
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \brief	designware iic driver header file
+ * \ingroup	DEVICE_DW_IIC
+ */
+
+#ifndef _DW_IIC_H_
+#define _DW_IIC_H_
+
+#include "device/device_hal/inc/dev_iic.h"
+
+#include "inc/arc/arc_exception.h"
+
+
+/**
+ * If this header file is included,
+ * will indicate that this designware iic device
+ * is used
+ */
+#define DEVICE_USE_DESIGNWARE_IIC
+
+/**
+ * \defgroup	DEVICE_DW_IIC_INFO	DesignWare IIC Related Information
+ * \ingroup	DEVICE_DW_IIC
+ * \brief	Defines some macros of DesignWare IIC need.
+ * \details	macros like, iic number
+ * @{
+ */
+#define DW_IIC_MASTER_SUPPORTED		(0x1)	/*!< Support Designware IIC Master Mode */
+#define DW_IIC_SLAVE_SUPPORTED		(0x2)	/*!< Support Designware IIC Slave Mode */
+/*!< Support Designware IIC Both Master and Slave Mode */
+#define DW_IIC_BOTH_SUPPORTED		(DW_IIC_MASTER_SUPPORTED|DW_IIC_SLAVE_SUPPORTED)
+/** @} */
+
+/**
+ * \defgroup	DEVICE_DW_IIC_REGSTRUCT		DesignWare IIC Register Structure
+ * \ingroup	DEVICE_DW_IIC
+ * \brief	contains definitions of DesignWare IIC register structure.
+ * \details	detailed description of DesignWare IIC register information
+ * @{
+ */
+/**
+ * \brief	DesignWare IIC register structure
+ * \details	Detailed struct description of DesignWare IIC
+ *	block register information, implementation of dev_iic_info::iic_regs
+ */
+typedef volatile struct dw_iic_reg {
+	uint32_t IC_CON;		/*!< (0x00) : IIC control */
+	uint32_t IC_TAR;		/*!< (0x04) : IIC target address */
+	uint32_t IC_SAR;		/*!< (0x08) : IIC slave address */
+	uint32_t IC_HS_MADDR;		/*!< (0x0c) : IIC HS Master Mode Code address */
+	uint32_t IC_DATA_CMD;		/*!< (0x10) : IIC Rx/Tx Data Buffer and Command */
+	uint32_t IC_SS_SCL_HCNT;	/*!< (0x14) : Standard Speed IIC clock SCL High Count */
+	uint32_t IC_SS_SCL_LCNT;	/*!< (0x18) : Standard Speed IIC clock SCL Low Count */
+	uint32_t IC_FS_SCL_HCNT;	/*!< (0x1c) : Fast Speed IIC clock SCL Low Count */
+	uint32_t IC_FS_SCL_LCNT;	/*!< (0x20) : Fast Speed IIC clock SCL Low Count */
+	uint32_t IC_HS_SCL_HCNT;	/*!< (0x24) : High Speed IIC clock SCL Low Count */
+	uint32_t IC_HS_SCL_LCNT;	/*!< (0x28) : High Speed IIC clock SCL Low Count */
+	uint32_t IC_INTR_STAT;		/*!< (0x2c) : IIC Interrupt Status */
+	uint32_t IC_INTR_MASK;		/*!< (0x30) : IIC Interrupt Mask */
+	uint32_t IC_RAW_INTR_STAT;	/*!< (0x34) : IIC Raw Interrupt Status */
+	uint32_t IC_RX_TL;		/*!< (0x38) : IIC Receive FIFO Threshold */
+	uint32_t IC_TX_TL;		/*!< (0x3c) : IIC Transmit FIFO Threshold */
+	uint32_t IC_CLR_INTR;		/*!< (0x40) : Clear combined and Individual Interrupts */
+	uint32_t IC_CLR_RX_UNDER;	/*!< (0x44) : Clear RX_UNDER Interrupt */
+	uint32_t IC_CLR_RX_OVER;	/*!< (0x48) : Clear RX_OVER Interrupt */
+	uint32_t IC_CLR_TX_OVER;	/*!< (0x4c) : Clear TX_OVER Interrupt */
+	uint32_t IC_CLR_RD_REQ;		/*!< (0x50) : Clear RQ_REQ Interrupt */
+	uint32_t IC_CLR_TX_ABRT;	/*!< (0x54) : Clear TX_ABRT Interrupt */
+	uint32_t IC_CLR_RX_DONE;	/*!< (0x58) : Clear RX_DONE Interrupt */
+	uint32_t IC_CLR_ACTIVITY;	/*!< (0x5c) : Clear ACTIVITY Interrupt */
+	uint32_t IC_CLR_STOP_DET;	/*!< (0x60) : Clear STOP_DET Interrupt */
+	uint32_t IC_CLR_START_DET;	/*!< (0x64) : Clear START_DET Interrupt */
+	uint32_t IC_CLR_GEN_CALL;	/*!< (0x68) : Clear GEN_CALL Interrupt */
+	uint32_t IC_ENABLE;		/*!< (0x6c) : IIC Enable */
+	uint32_t IC_STATUS;		/*!< (0x70) : IIC Status */
+	uint32_t IC_TXFLR;		/*!< (0x74) : Transmit FIFO Level Register */
+	uint32_t IC_RXFLR;		/*!< (0x78) : Receive FIFO Level Register */
+	uint32_t IC_SDA_HOLD;		/*!< (0x7c) : SDA Hold Time Length Reg */
+	uint32_t IC_TX_ABRT_SOURCE;	/*!< (0x80) : IIC Transmit Abort Status Reg */
+	uint32_t IC_SLV_DATA_NACK_ONLY;	/*!< (0x84) : Generate SLV_DATA_NACK Register */
+	uint32_t IC_DMA_CR;		/*!< (0x88) : DMA Control Register */
+	uint32_t IC_DMA_TDLR;		/*!< (0x8c) : DMA Transmit Data Level */
+	uint32_t IC_DMA_RDLR;		/*!< (0x90) : DMA Receive Data Level */
+	uint32_t IC_SDA_SETUP;		/*!< (0x94) : SDA Setup Register */
+	uint32_t IC_ACK_GENERAL_CALL;	/*!< (0x98) : ACK General Call Register */
+	uint32_t IC_ENABLE_STATUS;	/*!< (0x9c) : Enable Status Register */
+	uint32_t IC_FS_SPKLEN;		/*!< (0xa0) : ISS and FS spike suppression limit */
+	uint32_t IC_HS_SPKLEN;		/*!< (0xa4) : HS spike suppression limit */
+	uint32_t RESERVED[19];		/*!< (0xa8) : Reserved */
+	uint32_t IC_COMP_PARAM_1;	/*!< (0xf4) : Component Parameter Register */
+	uint32_t IC_COMP_VERSION;	/*!< (0xf8) : Component Version ID Reg */
+	uint32_t IC_COMP_TYPE;		/*!< (0xfc) : Component Type Reg */
+} DW_IIC_REG, *DW_IIC_REG_PTR;
+/** @} */
+
+/** Spike Suppression Limit Configurations */
+typedef struct dw_iic_spklen {
+	uint32_t fs_spklen;	/*!< value for IC_FS_SPKLEN, Tsp for fast mode is 50ns */
+	uint32_t hs_spklen;	/*!< value for IC_HS_SPKLEN, Tsp for high-speed mode is 10ns */
+} DW_IIC_SPKLEN, *DW_IIC_SPKLEN_PTR;
+
+/** IIC Clock SCL High and Low Count Configurations for Different Speed */
+typedef struct dw_iic_scl_cnt {
+	uint32_t ss_scl_hcnt;	/*!< value for IC_SS_SCL_HCNT */
+	uint32_t ss_scl_lcnt;	/*!< value for IC_SS_SCL_LCNT */
+	uint32_t fs_scl_hcnt;	/*!< value for IC_FS_SCL_HCNT */
+	uint32_t fs_scl_lcnt;	/*!< value for IC_FS_SCL_LCNT */
+	uint32_t hs_scl_hcnt;	/*!< value for IC_HS_SCL_HCNT */
+	uint32_t hs_scl_lcnt;	/*!< value for IC_HS_SCL_LCNT */
+} DW_IIC_SCL_CNT, *DW_IIC_SCL_CNT_PTR;
+
+#define DW_IIC_GINT_DISABLED		(0)		/*!< designware interrupt disabled for control iic irq/fiq */
+#define DW_IIC_GINT_ENABLE		(1<<0)		/*!< designware interrupt enabled for control iic irq/fiq */
+#define DW_IIC_TXINT_ENABLE		(1<<1)		/*!< designware interrupt enabled for control transmit process */
+#define DW_IIC_RXINT_ENABLE		(1<<2)		/*!< designware interrupt enabled for control transmit process */
+
+typedef struct dw_iic_buffer {
+	DEV_BUFFER *buf;
+	uint32_t ofs;
+	uint32_t len;
+} DW_IIC_BUFFER, *DW_IIC_BUFFER_PTR;
+
+/**
+ * \brief	DesignWare IIC control structure definition
+ * \details	implement of dev_iic_info::iic_ctrl
+ */
+typedef struct dw_iic_ctrl {
+	DW_IIC_REG *dw_iic_regs;	/*!< iic device registers */
+	/* Variables which should be set during object implementation */
+	uint32_t support_modes;		/*!< supported iic modes */
+	uint32_t tx_fifo_len;		/*!< transmit fifo length */
+	uint32_t rx_fifo_len;		/*!< receive fifo length */
+	uint32_t iic_master_code;	/*!< value for IC_HS_MADDR */
+	uint32_t retry_cnt;		/*!< retry count for TX or RX */
+	uint32_t intno;			/*!< iic interrupt vector number */
+	INT_HANDLER dw_iic_int_handler;	/*!< iic interrupt handler */
+	DW_IIC_SPKLEN iic_spklen;	/*!< iic spike suppression length settings */
+	DW_IIC_SCL_CNT iic_scl_cnt;	/*!< iic scl count settings */
+	/* Variables which always change during iic operation */
+	uint32_t int_status;		/*!< iic interrupt status */
+	uint32_t iic_tx_over;		/*!< iic tx overflow count */
+	uint32_t iic_rx_over;		/*!< iic rx overflow count */
+	DW_IIC_BUFFER dw_iic_rxbuf;	/*!< iic read buffer for receive data */
+} DW_IIC_CTRL, *DW_IIC_CTRL_PTR;
+
+/*!< One possible value for \ref dw_iic_ctrl::retry_cnt */
+#define DW_IIC_MAX_RETRY_COUNT		(100000)
+
+#if DW_IIC_USE_IC_CLK_MHZ == 100 /*!< 100MHz */
+/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
+static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
+
+/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
+#if DW_IIC_USE_HS_BUS_LOADING_100PF
+static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10};
+#else
+static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20};
+#endif
+
+#elif DW_IIC_USE_IC_CLK_MHZ == 50 /* 50MHz */
+/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
+static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
+
+/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
+#if DW_IIC_USE_HS_BUS_LOADING_100PF
+static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x8};
+#else
+static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x10};
+#endif
+
+#else /* Default 100MHz */
+/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
+static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
+
+/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
+#if DW_IIC_USE_HS_BUS_LOADING_100PF
+static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10};
+#else
+static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20};
+#endif
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup	DEVICE_DW_IIC_FUNCDLR	DesignWare IIC Function Declaration
+ * \ingroup	DEVICE_DW_IIC
+ * \brief	Contains declarations of designware iic functions.
+ * \details	This are only used in iic object implementation source file
+ * @{
+ */
+extern int32_t dw_iic_open (DEV_IIC *iic_obj, uint32_t mode, uint32_t param);
+extern int32_t dw_iic_close (DEV_IIC *iic_obj);
+extern int32_t dw_iic_control (DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param);
+extern int32_t dw_iic_write (DEV_IIC *iic_obj, const void *data, uint32_t len);
+extern int32_t dw_iic_read (DEV_IIC *iic_obj, void *data, uint32_t len);
+extern void dw_iic_isr(DEV_IIC *iic_obj, void *ptr);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* _DW_IIC_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h
new file mode 100644
index 0000000000..f7ec0d27a2
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h
@@ -0,0 +1,186 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-06-30
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	DEVICE_DW_IIC
+ * \brief	DesignWare IIC driver hardware description related header file
+ * \details	detailed hardware related definitions of DesignWare IIC driver
+ */
+
+#ifndef _DEVICE_DW_IIC_HAL_H_
+#define _DEVICE_DW_IIC_HAL_H_
+
+#include "device/designware/iic/dw_iic_hal_cfg.h"
+
+/** Enable Designware IIC */
+#define DW_IIC_ENABLE			(1)
+/** Disable Designware IIC */
+#define DW_IIC_DISABLE			(0)
+
+/** Stop Condition issue after this byte */
+#define IC_DATA_CMD_STOP		(1 << 9)
+/** Restart Condition issue after this byte */
+#define IC_DATA_CMD_RESTART		(1 << 10)
+/** No Restart or stop condition after this byte */
+#define IC_DATA_CMD_NONE		(0)
+
+/** Perform a write request */
+#define IC_DATA_CMD_WRITE_REQ		(0)
+/** Perform a read request */
+#define IC_DATA_CMD_READ_REQ		(1 << 8)
+
+/** Fields of IC_CON register */
+/* DW_APB I2C IP Config Dependencies. */
+#if DW_IIC_ALLOW_RESTART
+#define IC_CON_RESTART_EN		(1 << 5)
+#else
+#define IC_CON_RESTART_EN		(0x00)
+#endif
+
+/* Master Addressing Mode Config */
+#if DW_IIC_MST_10_BIT_ADDR_SUPPORT
+#define MST_10_BIT_ADDR_MODE		(1 << 4)
+#define IC_10BITADDR_MASTER		(1 << 12)
+#else
+#define MST_10_BIT_ADDR_MODE		(0x00)
+#define IC_10BITADDR_MASTER		(0x00)
+#endif
+
+/* Slave Addressing Mode Config */
+#if DW_IIC_SLV_10_BIT_ADDR_SUPPORT
+#define SLV_10_BIT_ADDR_MODE		(1 << 3)
+#else
+#define SLV_10_BIT_ADDR_MODE		(0x00)
+#endif
+
+#if DW_IIC_SPECIAL_START_BYTE
+#define IC_TAR_SPECIAL			(1 << 11)
+#define IC_TAR_GC_OR_START		(1 << 10)
+#else
+#define IC_TAR_SPECIAL			(0x00)
+#define IC_TAR_GC_OR_START		(0x00)
+#endif
+
+/** 7bit IIC address mask for target address register */
+#define IC_TAR_7BIT_ADDR_MASK		(0x7F)
+/** 7bit IIC address mask for slave address register */
+#define IC_SAR_7BIT_ADDR_MASK		(0x7F)
+/** 10bit IIC address mask for target address register */
+#define IC_TAR_10BIT_ADDR_MASK		(0x3FF)
+/** 10bit IIC address mask for slave address register */
+#define IC_SAR_10BIT_ADDR_MASK		(0x3FF)
+
+/** Speed modes of IC_CON */
+#define IC_CON_SPEED_MASK		(0x6)
+#define IC_CON_SPEED_STANDARD		(0x2)
+#define IC_CON_SPEED_FAST		(0x4)
+#define IC_CON_SPEED_HIGH		(0x6)
+/** Working mode of IC_CON */
+#define IC_CON_MST_SLV_MODE_MASK	(0x41)
+#define IC_CON_ENA_MASTER_MODE		(0x41)
+#define IC_CON_ENA_SLAVE_MODE		(0)
+
+/* IIC interrupt control */
+#define IC_INT_DISABLE_ALL		(0x0)
+#define IC_INT_ENABLE_ALL		(0x7FF)
+/* Interrupt Register Fields */
+#define IC_INTR_STAT_GEN_CALL		(1 << 11)
+#define IC_INTR_STAT_START_DET		(1 << 10)
+#define IC_INTR_STAT_STOP_DET		(1 << 9)
+#define IC_INTR_STAT_ACTIVITY		(1 << 8)
+#define IC_INTR_STAT_RX_DONE		(1 << 7)
+#define IC_INTR_STAT_TX_ABRT		(1 << 6)
+#define IC_INTR_STAT_RD_REQ		(1 << 5)
+#define IC_INTR_STAT_TX_EMPTY		(1 << 4)
+#define IC_INTR_STAT_TX_OVER		(1 << 3)
+#define IC_INTR_STAT_RX_FULL		(1 << 2)
+#define IC_INTR_STAT_RX_OVER		(1 << 1)
+#define IC_INTR_STAT_RX_UNDER		(1 << 0)
+
+/* Interrupt enable mask as master */
+#define IC_INT_MST_TX_ENABLE		(IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_TX_OVER|IC_INTR_STAT_TX_ABRT)
+#define IC_INT_MST_RX_ENABLE		(IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER|IC_INTR_STAT_TX_ABRT)
+
+/* Interrupt enable mask as master */
+#define IC_INT_SLV_COMMON_ENABLE	(IC_INTR_STAT_START_DET|IC_INTR_STAT_STOP_DET)
+#define IC_INT_SLV_TX_ENABLE		(IC_INTR_STAT_RD_REQ|IC_INTR_STAT_TX_ABRT)
+#define IC_INT_SLV_RX_ENABLE		(IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)
+
+/* IC_ENABLE_STATUS Bits */
+#define IC_ENABLE_STATUS_IC_EN		(1 << 0)
+#define IC_ENABLE_STATUS_SLV_DIS	(1 << 1)
+#define IC_ENABLE_STATUS_SLV_RX_LOST	(1 << 2)
+
+/* IIC TX & RX threshold settings */
+#define IIC_TX_THRESHOLD		(0)
+#define IIC_RX_THRESHOLD		(0)
+
+/* DW_APB IIC (DW_IC_STATUS) Status Register Fields. */
+#define IC_STATUS_ACTIVITY		(0x01)
+#define IC_STATUS_TFNF			(0x02) /* (1 << 1) */
+#define IC_STATUS_TFE			(0x04) /* (1 << 2) */
+#define IC_STATUS_RFNE			(0x08) /* (1 << 3) */
+#define IC_STATUS_RFF			(0x10) /* (1 << 4) */
+#define IC_STATUS_MASTER_ACT		(0x20) /* (1 << 5) */
+#define IC_STATUS_SLAVE_ACT		(0x40) /* (1 << 6) */
+
+/* IC_TX_ABRT_SOURCE Register Bit Fields */
+#define IC_TX_ABRT_7B_ADDR_NOACK	(1 << 0)
+#define IC_TX_ABRT_10ADDR1_NOACK	(1 << 1)
+#define IC_TX_ABRT_10ADDR2_NOACK	(1 << 2)
+#define IC_TX_ABRT_TXDATA_NOACK		(1 << 3)
+#define IC_TX_ABRT_GCALL_NOACK		(1 << 4)
+#define IC_TX_ABRT_GCALL_READ		(1 << 5)
+#define IC_TX_ABRT_HS_ACKDET		(1 << 6)
+#define IC_TX_ABRT_SBYTE_ACKDET		(1 << 7)
+#define IC_TX_ABRT_HS_NORSTRT		(1 << 8)
+#define IC_TX_ABRT_SBYTE_NORSTRT	(1 << 9)
+#define IC_TX_ABRT_10B_RD_NORSTRT	(1 << 10)
+#define IC_TX_ABRT_MASTER_DIS		(1 << 11)
+#define IC_TX_ABRT_ARB_LOST		(1 << 12)
+#define IC_TX_ABRT_SLVFLUSH_TXFIFO	(1 << 13)
+#define IC_TX_ABRT_SLV_ARBLOST		(1 << 14)
+#define IC_TX_ABRT_SLVRD_INTX		(1 << 15)
+
+/* Combined bits for iic abort source as master */
+#define IIC_MST_ABRT_ADDR_NOACK		(IC_TX_ABRT_7B_ADDR_NOACK|IC_TX_ABRT_10ADDR1_NOACK|IC_TX_ABRT_10ADDR1_NOACK)
+#define IIC_MST_ABRT_LOST_BUS		(IC_TX_ABRT_ARB_LOST)
+#define IIC_MST_ABRT_DATA_NOACK		(IC_TX_ABRT_TXDATA_NOACK)
+
+/* Combined bits for iic abort source as slave */
+#define IIC_SLV_ABRT_LOST_BUS		(IC_TX_ABRT_ARB_LOST|IC_TX_ABRT_SLV_ARBLOST)
+
+/** @} */
+
+#endif /* _DEVICE_DW_IIC_HAL_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h
new file mode 100644
index 0000000000..1073162176
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h
@@ -0,0 +1,82 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-07-01
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	DEVICE_DW_IIC
+ * \brief	DesignWare IIC driver hardware description
+ * 	related header file configuration file
+ * \details	configuration file to enable or disable some function of iic
+ */
+
+#ifndef _DEVICE_DW_IIC_HAL_CFG_H_
+#define _DEVICE_DW_IIC_HAL_CFG_H_
+
+#ifndef DW_IIC_ALLOW_RESTART
+#define DW_IIC_ALLOW_RESTART			(1)	/*!< allow restart configuration */
+#endif
+
+#ifdef DW_IIC_SPECIAL_START_BYTE
+#define DW_IIC_SPECIAL_START_BYTE		(0)	/*!< SPECIAL bit enable in IC_TAR */
+#endif
+
+#ifndef DW_IIC_MST_10_BIT_ADDR_SUPPORT
+#define DW_IIC_MST_10_BIT_ADDR_SUPPORT		(1)	/*!< enable 10-bit address mode */
+#endif
+
+#ifdef DW_IIC_SLV_10_BIT_ADDR_SUPPORT
+#define DW_IIC_SLV_10_BIT_ADDR_SUPPORT		(1)	/*!< slave 10-bit addressing mode */
+#endif
+
+#ifndef DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
+#define DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT	(0)	/*!< Dynamic target address update support */
+#endif
+
+#ifndef DW_IIC_DISABLE_MAX_T_POLL_CNT
+#define DW_IIC_DISABLE_MAX_T_POLL_CNT		(1250)	/*!< Timeout count, approximate to be 25us in 50MHz CPU @ Standard mode */
+#endif
+
+#ifndef DW_IIC_CALC_FIFO_LEN_ENABLE
+#define DW_IIC_CALC_FIFO_LEN_ENABLE		(1)	/*!< Default enable calculate fifo length */
+#endif
+
+#ifndef DW_IIC_USE_IC_CLK_MHZ
+#define DW_IIC_USE_IC_CLK_MHZ			(50)	/*!< Default use 50MHz IC_CLK */
+#endif
+
+#ifndef DW_IIC_USE_HS_BUS_LOADING_100PF
+#define DW_IIC_USE_HS_BUS_LOADING_100PF		(1)	/*!< Use bus loading 100pf */
+#endif
+
+#endif /* _DEVICE_DW_IIC_HAL_CFG_H_ */
+
diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi.c b/bsp/synopsys/embarc/device/designware/spi/dw_spi.c
new file mode 100644
index 0000000000..bea413b411
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/spi/dw_spi.c
@@ -0,0 +1,1337 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-06-25
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_DW_SPI	Designware SPI Driver
+ * \ingroup	DEVICE_DW
+ * \brief	Designware SPI Driver Implementation
+ */
+
+/**
+ * \file
+ * \brief	DesignWare SPI driver implementation based on device hal layer definition (\ref dev_spi.h)
+ * \ingroup	DEVICE_DW_SPI
+ */
+#include <string.h>
+
+#include "inc/embARC_toolchain.h"
+#include "inc/embARC_error.h"
+
+#include "inc/arc/arc_exception.h"
+
+#include "device/designware/spi/dw_spi_hal.h"
+#include "device/designware/spi/dw_spi.h"
+
+/**
+ * \defgroup	DEVICE_DW_SPI_DEFINES	DesignWare SPI Driver Macros
+ * \ingroup	DEVICE_DW_SPI
+ * \brief	DesignWare SPI driver macros used in spi driver
+ * @{
+ */
+/** check expressions used in DesignWare SPI driver implementation */
+#define DW_SPI_CHECK_EXP(EXPR, ERROR_CODE)		CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
+
+/** convert DesignWare frequence to divisor */
+#define DW_SPI_FREQ2DV(perifreq, spifreq)		((perifreq) / (spifreq))
+
+#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
+/** valid check of spi info object */
+#define VALID_CHK_SPI_INFO_OBJECT(spiinfo_obj_ptr)		{			\
+			DW_SPI_CHECK_EXP((spiinfo_obj_ptr)!=NULL, E_OBJ);		\
+			DW_SPI_CHECK_EXP(((spiinfo_obj_ptr)->spi_ctrl)!=NULL, E_OBJ);	\
+ 		}
+#endif
+
+/**
+ * \defgroup	DEVICE_DW_SPI_DEF_CBR	DesignWare SPI Interrupt Callback Routine Select Marcos
+ * \ingroup	DEVICE_DW_SPI_DEFINES
+ * \brief	DesignWare SPI interrupt callback routines select macros definitions
+ * @{
+ */
+#define DW_SPI_RDY_SND					(1U)	/*!< ready to send callback */
+#define DW_SPI_RDY_RCV					(2U)	/*!< ready to receive callback */
+#define DW_SPI_RDY_XFER					(3U)	/*!< ready to transfer callback */
+/** @} */
+
+/** @} */
+
+/**
+ * \defgroup	DEVICE_DW_SPI_STATIC	DesignWare SPI Driver Static Functions
+ * \ingroup	DEVICE_DW_SPI
+ * \brief	Static or inline functions, variables for DesignWare SPI handle spi operations,
+ * 	only used in this file.
+ * @{
+ */
+
+/** Disable designware spi device */
+Inline void dw_spi_disable(DW_SPI_REG *spi_reg_ptr)
+{
+/** disable spi operations, then program spi control regs is possible */
+	spi_reg_ptr->SSIENR = DW_SPI_SSI_DISABLE;
+}
+/** Enable designware spi device */
+Inline void dw_spi_enable(DW_SPI_REG *spi_reg_ptr)
+{
+	spi_reg_ptr->SSIENR = DW_SPI_SSI_ENABLE;
+}
+
+/** Clear all designware spi interrupt */
+Inline void dw_spi_clear_interrupt_all(DW_SPI_REG *spi_reg_ptr)
+{
+	(void)spi_reg_ptr->ICR;
+}
+
+/** test whether spi is busy, busy return 1, else 0 */
+Inline int32_t dw_spi_busy(DW_SPI_REG *spi_reg_ptr)
+{
+	return ((spi_reg_ptr->SR & DW_SPI_SR_BUSY) != 0);
+}
+/** test whether spi is ready to send, 1 ready, 0 not ready */
+Inline int32_t dw_spi_putready(DW_SPI_REG *spi_reg_ptr)
+{
+	return ((spi_reg_ptr->SR & DW_SPI_SR_TFNF) != 0);
+}
+/** test whether spi is read to receive, 1 ready, 0 not ready */
+Inline int32_t dw_spi_getready(DW_SPI_REG *spi_reg_ptr)
+{
+	return ((spi_reg_ptr->SR & DW_SPI_SR_RFNE) != 0);
+}
+/** write data to spi send fifo */
+Inline void dw_spi_putdata(DW_SPI_REG *spi_reg_ptr, int32_t data)
+{
+	spi_reg_ptr->DATAREG = (uint32_t)data;
+}
+/** read data from spi receive fifo, return data received */
+Inline int32_t dw_spi_getdata(DW_SPI_REG *spi_reg_ptr)
+{
+	return (int32_t)spi_reg_ptr->DATAREG;
+}
+/**
+ * \brief	send data by spi when available,
+ * 	mostly used in interrupt method, non-blocked function
+ * \param[in]	spi_reg_ptr	spi register structure pointer
+ * \param[in]	data		data to be sent
+ * \retval	E_OK		send successfully
+ * \retval	E_OBJ		not ready to send data
+ */
+Inline int32_t dw_spi_snd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data)
+{
+	if (dw_spi_putready(spi_reg_ptr)) {
+		dw_spi_putdata(spi_reg_ptr, data);
+		return E_OK;
+	}
+	return E_OBJ;
+}
+/**
+ * \brief	receive one char from spi,
+ * 	mostly used in interrupt routine, non-blocked function
+ * \param[in]	spi_reg_ptr	spi register structure pointer
+ * \return	data received by the spi
+ */
+Inline int32_t dw_spi_rcv_dat(DW_SPI_REG *spi_reg_ptr)
+{
+	return dw_spi_getdata(spi_reg_ptr);
+}
+/**
+ * \brief	send char by spi in poll method, blocked function
+ * \param[in]	spi_reg_ptr	spi register structure pointer
+ * \param[in]	data		data to be sent
+ */
+Inline void dw_spi_psnd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data)
+{
+	/** wait until spi is ready to send */
+	while (!dw_spi_putready(spi_reg_ptr)); /* blocked */
+	/** send char */
+	dw_spi_putdata(spi_reg_ptr, data);
+}
+/**
+ * \brief	receive one char from spi in poll method, blocked function
+ * \param[in]	spi_reg_ptr	spi register structure pointer
+ * \return	data received by the spi
+ */
+Inline int32_t dw_spi_prcv_dat(DW_SPI_REG *spi_reg_ptr)
+{
+	/** wait until spi is ready to receive */
+	while (!dw_spi_getready(spi_reg_ptr)); /* blocked */
+	/** receive data */
+	return dw_spi_getdata(spi_reg_ptr);
+}
+
+/** Reset designware FIFO by disable spi device, then enable device */
+Inline void dw_spi_reset_fifo(DW_SPI_REG *spi_reg_ptr)
+{
+	dw_spi_disable(spi_reg_ptr);
+	dw_spi_enable(spi_reg_ptr);
+}
+
+/** Enable designware spi bit interrupt with mask */
+Inline void dw_spi_unmask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask)
+{
+	spi_reg_ptr->IMR |= mask;
+}
+
+/** Disable designware spi bit interrupt with mask */
+Inline void dw_spi_mask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask)
+{
+	spi_reg_ptr->IMR &= ~mask;
+}
+
+/** Set designware spi device frequency */
+Inline void dw_spi_set_freq(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t freq)
+{
+	uint32_t sck_divisor;
+	DW_SPI_REG *spi_reg_ptr = spi_ctrl_ptr->dw_spi_regs;
+
+	dw_spi_disable(spi_reg_ptr);
+
+	sck_divisor = DW_SPI_FREQ2DV(spi_ctrl_ptr->dw_apb_bus_freq, freq);
+	spi_reg_ptr->BAUDR = sck_divisor;
+	dw_spi_enable(spi_reg_ptr);
+}
+
+/** Set designware spi device data frame size */
+static int32_t dw_spi_set_dfs(DW_SPI_REG *spi_reg_ptr, uint32_t dfs)
+{
+	uint32_t ctrl0_reg;
+	if ((dfs <= 3) || (dfs > 16)) return -1;
+
+	dw_spi_disable(spi_reg_ptr);
+	ctrl0_reg = spi_reg_ptr->CTRLR0;
+	ctrl0_reg &= ~(DW_SPI_CTRLR0_DFS_MASK);
+	spi_reg_ptr->CTRLR0 = ctrl0_reg | (dfs-1);
+	dw_spi_enable(spi_reg_ptr);
+
+	return 0;
+}
+
+/** Choose proper designware spi clock mode setting value */
+Inline uint32_t dw_spi_select_clockmode(uint32_t clk_mode)
+{
+	return (clk_mode << DW_SPI_CTRLR0_SC_OFS);
+}
+
+/** Set designware spi clock mode */
+Inline int32_t dw_spi_set_clockmode(DW_SPI_REG *spi_reg_ptr, uint32_t clk_mode)
+{
+	if (clk_mode > SPI_CPOL_1_CPHA_1) {
+		return -1;
+	}
+	dw_spi_disable(spi_reg_ptr);
+	spi_reg_ptr->CTRLR0 &= ~(DW_SPI_CTRLR0_SC_MASK);
+	spi_reg_ptr->CTRLR0 |= dw_spi_select_clockmode(clk_mode);
+	dw_spi_enable(spi_reg_ptr);
+	return 0;
+}
+
+/** Select a spi slave with slv_line */
+Inline int32_t dw_spi_select_slave(DW_SPI_REG *spi_reg_ptr, uint32_t slv_line)
+{
+	/* check if spi busy */
+	if (dw_spi_busy(spi_reg_ptr)) return -1;
+
+	spi_reg_ptr->SER = 1<<slv_line;
+	return 0;
+}
+
+/** Deselect a spi device */
+Inline int32_t dw_spi_deselect_slave(DW_SPI_REG *spi_reg_ptr, uint32_t slv_line)
+{
+	/* check if spi busy */
+	if (dw_spi_busy(spi_reg_ptr)) return -1;
+
+	spi_reg_ptr->SER = 0;
+	return 0;
+}
+
+Inline void dw_spi_flush_tx(DW_SPI_REG *spi_reg_ptr)
+{
+	dw_spi_reset_fifo(spi_reg_ptr);
+}
+
+Inline void dw_spi_flush_rx(DW_SPI_REG *spi_reg_ptr)
+{
+	dw_spi_reset_fifo(spi_reg_ptr);
+}
+
+/** Get TX FIFO Length.
+ *    calculate spi fifo length using fifo threshold method
+ *  If you attempt to set bits [7:0] of this register to
+ *  a value greater than or equal to the depth of the FIFO,
+ *  this field is not written and retains its current value.
+ */
+static uint32_t dw_spi_get_txfifo_len(DW_SPI_REG *spi_reg_ptr)
+{
+	uint32_t fifo_thr_lev_tmp, left, right, i;
+
+	fifo_thr_lev_tmp = spi_reg_ptr->TXFTLR;
+
+	if (fifo_thr_lev_tmp != 0) {
+		left = fifo_thr_lev_tmp;
+	} else {
+		left = DW_SPI_MIN_FIFO_LENGTH;
+	}
+	right = DW_SPI_MAX_FIFO_LENGTH + 1;
+
+	for (i = left; i <= right; i++) {
+		spi_reg_ptr->TXFTLR = i;
+		if (spi_reg_ptr->TXFTLR != i) {
+			break;
+		}
+	}
+	spi_reg_ptr->TXFTLR = fifo_thr_lev_tmp; /* restore old fifo threshold */
+
+	return (i);
+}
+
+/** Get RX FIFO Length */
+static uint32_t dw_spi_get_rxfifo_len(DW_SPI_REG *spi_reg_ptr)
+{
+	uint32_t fifo_thr_lev_tmp, left, right, i;
+
+	fifo_thr_lev_tmp = spi_reg_ptr->RXFTLR;
+
+	if (fifo_thr_lev_tmp != 0) {
+		left = fifo_thr_lev_tmp;
+	} else {
+		left = DW_SPI_MIN_FIFO_LENGTH;
+	}
+	right = DW_SPI_MAX_FIFO_LENGTH + 1;
+
+	for (i = left; i <= right; i++) {
+		spi_reg_ptr->RXFTLR = i;
+		if (spi_reg_ptr->RXFTLR != i) {
+			break;
+		}
+	}
+	spi_reg_ptr->RXFTLR = fifo_thr_lev_tmp; /* restore old fifo threshold */
+
+	return (i);
+}
+
+/** Init Designware SPI Hardware */
+static void dw_spi_hw_init(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t clk_mode, uint32_t dfs)
+{
+	uint32_t ctrl0_reg = 0;
+	DW_SPI_REG *spi_reg_ptr = spi_ctrl_ptr->dw_spi_regs;
+
+	dw_spi_disable(spi_reg_ptr);
+
+	/* Clear interrupts */
+	ctrl0_reg = spi_reg_ptr->ICR;
+	/* Mask all interrupts */
+	spi_reg_ptr->IMR = 0;
+
+	ctrl0_reg = DW_SPI_CTRLR0_FRF_MOTOROLA | DW_SPI_TMOD_TRANSMIT_RECEIVE \
+			| dw_spi_select_clockmode(clk_mode) | (dfs - 1) | DW_SPI_CTRLR0_SLV_OE_ENABLE;
+	spi_reg_ptr->CTRLR0 = ctrl0_reg;
+	spi_reg_ptr->CTRLR1 = 0;
+
+	/* deselect slaves */
+	spi_reg_ptr->SER = 0;
+
+	/* Set threshold values for both tx and rx */
+	spi_reg_ptr->TXFTLR = 0;
+	spi_reg_ptr->RXFTLR = 0;
+
+	dw_spi_enable(spi_reg_ptr);
+}
+
+/** enable designware spi */
+static void dw_spi_enable_device(DEV_SPI_INFO *spi_info_ptr)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+
+	if ((spi_info_ptr->status & DEV_ENABLED) == 0) {
+		dw_spi_enable(spi_reg_ptr);
+		spi_info_ptr->status |= DEV_ENABLED;
+	}
+}
+
+/** disable designware spi */
+static void dw_spi_disable_device(DEV_SPI_INFO *spi_info_ptr)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+
+	dw_spi_disable(spi_reg_ptr);
+	spi_info_ptr->status &= ~DEV_ENABLED;
+}
+
+
+/**
+ * \brief	disable designware spi send or receive interrupt
+ * \param[in]	DEV_SPI_INFO 	*spi_info_ptr
+ * \param[in]	cbrtn		control code of callback routine of send or receive
+ */
+static int32_t dw_spi_dis_cbr(DEV_SPI_INFO *spi_info_ptr, uint32_t cbrtn)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+	int32_t ercd = E_OK;
+
+	if ((spi_info_ptr->status & DW_SPI_IN_XFER) != 0) { /* only in transfer need do check */
+		switch (cbrtn) {
+			case DW_SPI_RDY_SND:
+				DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX, E_CTX);
+				spi_info_ptr->status &= ~(DW_SPI_IN_TX);
+				break;
+			case DW_SPI_RDY_RCV:
+				DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX, E_CTX);
+				spi_info_ptr->status &= ~(DW_SPI_IN_RX);
+				break;
+			case DW_SPI_RDY_XFER:
+				DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER, E_CTX);
+				spi_info_ptr->status &= ~(DW_SPI_IN_XFER);
+				break;
+			default:
+				break;
+		}
+	}
+
+	dw_spi_mask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER);
+
+	if (spi_ctrl_ptr->int_status & DW_SPI_GINT_ENABLE) {
+		int_disable(spi_ctrl_ptr->intno);
+		spi_ctrl_ptr->int_status &= ~DW_SPI_GINT_ENABLE;
+	}
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	enable DesignWare SPI send or receive interrupt
+ * \param[in]	DEV_SPI_INFO 	*spi_info_ptr
+ * \param[in]	cbrtn		control code of callback routine of send or receive
+ */
+static int32_t dw_spi_ena_cbr(DEV_SPI_INFO *spi_info_ptr, uint32_t cbrtn)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+	int32_t ercd = E_OK;
+
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == 0, E_CTX);
+	switch (cbrtn) {
+		case DW_SPI_RDY_SND:
+			spi_info_ptr->status |= DW_SPI_IN_TX;
+			break;
+		case DW_SPI_RDY_RCV:
+			spi_info_ptr->status |= DW_SPI_IN_RX;
+			break;
+		case DW_SPI_RDY_XFER:
+			spi_info_ptr->status |= DW_SPI_IN_XFER;
+			break;
+		default:
+			break;
+	}
+	dw_spi_unmask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER);
+
+	if ((spi_ctrl_ptr->int_status & DW_SPI_GINT_ENABLE) == 0) {
+		spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE;
+		int_enable(spi_ctrl_ptr->intno);
+	}
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	enable designware spi interrupt
+ * \param	spi_info_ptr	spi information structure pointer
+ */
+static void dw_spi_enable_interrupt(DEV_SPI_INFO *spi_info_ptr)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+
+	int_handler_install(spi_ctrl_ptr->intno, spi_ctrl_ptr->dw_spi_int_handler);
+	spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE;
+	int_enable(spi_ctrl_ptr->intno);	/** enable spi interrupt */
+}
+/**
+ * \brief	disable designware spi interrupt
+ * \param	spi_info_ptr	spi information structure pointer
+ */
+static void dw_spi_disable_interrupt(DEV_SPI_INFO *spi_info_ptr)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+
+	/** disable spi send&receive interrupt after disable spi interrupt */
+	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND);
+	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
+	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
+	/* disable spi interrupt */
+	dw_spi_mask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER);
+	spi_info_ptr->status &= ~DW_SPI_IN_XFER;
+	int_disable(spi_ctrl_ptr->intno);
+	spi_ctrl_ptr->int_status &= ~(DW_SPI_GINT_ENABLE);
+}
+
+static void dw_spi_reset_device(DEV_SPI_INFO *spi_info_ptr)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+
+	dw_spi_disable_device(spi_info_ptr);
+	dw_spi_disable_interrupt(spi_info_ptr);
+	dw_spi_clear_interrupt_all(spi_reg_ptr);
+	dw_spi_enable_device(spi_info_ptr);
+}
+
+/** abort current interrupt transmit transfer */
+static int32_t dw_spi_abort_tx(DEV_SPI *spi_obj)
+{
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+	int32_t ercd = E_OK;
+
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK);
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX, E_CTX);
+
+	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND);
+	spi_info_ptr->status |= DEV_IN_TX_ABRT;
+	if (spi_info_ptr->spi_cbs.tx_cb != NULL) {
+		spi_info_ptr->spi_cbs.tx_cb(spi_obj);
+	}
+	spi_info_ptr->status &= ~(DEV_IN_TX_ABRT);
+
+error_exit:
+	return ercd;
+}
+
+/** abort current interrupt receive transfer */
+static int32_t dw_spi_abort_rx(DEV_SPI *spi_obj)
+{
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+	int32_t ercd = E_OK;
+
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK);
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX, E_CTX);
+
+	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
+	spi_info_ptr->status |= DEV_IN_RX_ABRT;
+	if (spi_info_ptr->spi_cbs.rx_cb != NULL) {
+		spi_info_ptr->spi_cbs.rx_cb(spi_obj);
+	}
+	spi_info_ptr->status &= ~(DEV_IN_RX_ABRT);
+
+error_exit:
+	return ercd;
+}
+
+/** abort current interrupt transfer */
+static int32_t dw_spi_abort_xfer(DEV_SPI *spi_obj)
+{
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+	int32_t ercd = E_OK;
+
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK);
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER, E_CTX);
+
+	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
+	spi_info_ptr->status |= DEV_IN_XFER_ABRT;
+	if (spi_info_ptr->spi_cbs.xfer_cb != NULL) {
+		spi_info_ptr->spi_cbs.xfer_cb(spi_obj);
+	}
+	spi_info_ptr->status &= ~(DEV_IN_XFER_ABRT);
+
+error_exit:
+	return ercd;
+}
+
+/** Get available transmit fifo count */
+static int32_t dw_spi_get_txavail(DW_SPI_CTRL *spi_ctrl_ptr)
+{
+	int32_t tx_avail = 0;
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+
+#if DW_SPI_CALC_FIFO_LEN_ENABLE
+	if (spi_ctrl_ptr->tx_fifo_len <= 1) {
+		if (dw_spi_putready(spi_reg_ptr) == 1) {
+			tx_avail = 1;
+		} else {
+			tx_avail = 0;
+		}
+	} else
+#endif
+	{
+		tx_avail = spi_ctrl_ptr->tx_fifo_len - spi_reg_ptr->TXFLR;
+	}
+	return tx_avail;
+}
+
+/** Get available receive fifo count */
+static int32_t dw_spi_get_rxavail(DW_SPI_CTRL *spi_ctrl_ptr)
+{
+	int32_t rx_avail = 0;
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+
+#if DW_SPI_CALC_FIFO_LEN_ENABLE
+	if (spi_ctrl_ptr->rx_fifo_len <= 1) {
+		if (dw_spi_getready(spi_reg_ptr) == 1) {
+			rx_avail = 1;
+		} else {
+			rx_avail = 0;
+		}
+	} else
+#endif
+	{
+		rx_avail = spi_reg_ptr->RXFLR;
+	}
+	return rx_avail;
+}
+
+static uint32_t dw_spi_tx_max(DW_SPI_CTRL *spi_ctrl_ptr)
+{
+	uint32_t tx_left, tx_room;
+	DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer);
+
+	tx_left = (xfer->xfer_len - xfer->tx_idx) / xfer->nbytes;
+	tx_room = dw_spi_get_txavail(spi_ctrl_ptr);
+
+	return (tx_left < tx_room) ? tx_left : tx_room;
+}
+
+static uint32_t dw_spi_rx_max(DW_SPI_CTRL *spi_ctrl_ptr)
+{
+	uint32_t rx_left, rx_room;
+	DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer);
+
+	rx_left = (xfer->xfer_len - xfer->rx_idx) / xfer->nbytes;
+	rx_room = dw_spi_get_rxavail(spi_ctrl_ptr);
+
+	return (rx_left < rx_room) ? rx_left : rx_room;
+}
+
+Inline int32_t dw_spi_rx_end(DW_SPI_CTRL *spi_ctrl_ptr)
+{
+	DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer);
+
+	return (xfer->rx_idx >= xfer->xfer_len);
+}
+
+Inline int32_t dw_spi_tx_end(DW_SPI_CTRL *spi_ctrl_ptr)
+{
+	DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer);
+
+	return (xfer->tx_idx >= xfer->xfer_len);
+}
+
+/** 1 for end, 0 for not end */
+Inline int32_t dw_spi_xfer_end(DW_SPI_CTRL *spi_ctrl_ptr)
+{
+	return (dw_spi_tx_end(spi_ctrl_ptr) && dw_spi_rx_end(spi_ctrl_ptr));
+}
+
+static int32_t dw_spi_writer(DEV_SPI_INFO *spi_info_ptr)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
+	DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer);
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+	uint32_t tx_max = dw_spi_tx_max(spi_ctrl_ptr);
+	int32_t tx_w;
+	uint32_t tx_cnt = tx_max;
+
+	if (dw_xfer->tx_xfer == NULL) {
+		return 0;
+	}
+	while (tx_max) {
+		if (dw_xfer->tx_xfer->tx_idx >= dw_xfer->tx_xfer->tot_len) {
+			dw_xfer->tx_xfer = dw_xfer->tx_xfer->next;
+			if (dw_xfer->tx_xfer == NULL) {
+				break;
+			}
+		}
+		if ( (dw_xfer->tx_xfer->tx_idx >= dw_xfer->tx_xfer->tx_ofs) \
+			&& (dw_xfer->tx_xfer->tx_idx < dw_xfer->tx_xfer->tx_totlen)) {
+			if (dw_xfer->nbytes == 1) {
+				tx_w = (int32_t)(*(int8_t *)(dw_xfer->tx_xfer->tx_buf));
+			} else {
+				tx_w = (int32_t)(*(int16_t *)(dw_xfer->tx_xfer->tx_buf));
+			}
+			dw_xfer->tx_xfer->tx_buf += dw_xfer->nbytes;
+		} else {
+			tx_w = spi_info_ptr->dummy;
+		}
+		dw_spi_putdata(spi_reg_ptr, tx_w);
+		dw_xfer->tx_xfer->tx_idx += dw_xfer->nbytes;
+		dw_xfer->tx_idx += dw_xfer->nbytes;
+		tx_max --;
+	}
+	return ((tx_cnt-tx_max) * dw_xfer->nbytes);
+}
+
+static int32_t dw_spi_reader(DEV_SPI_INFO *spi_info_ptr)
+{
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
+	DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer);
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+	uint32_t rx_max = dw_spi_rx_max(spi_ctrl_ptr);
+	int32_t rx_w;
+	uint32_t rx_cnt = rx_max;
+
+	if (dw_xfer->rx_xfer == NULL) {
+		return 0;
+	}
+	while (rx_max) {
+		if (dw_xfer->rx_xfer->rx_idx >= dw_xfer->rx_xfer->tot_len) {
+			dw_xfer->rx_xfer = dw_xfer->rx_xfer->next;
+			if (dw_xfer->rx_xfer == NULL) {
+				break;
+			}
+		}
+		rx_w = dw_spi_getdata(spi_reg_ptr);
+		if ( (dw_xfer->rx_xfer->rx_idx >= dw_xfer->rx_xfer->rx_ofs) \
+			&& (dw_xfer->rx_xfer->rx_idx < dw_xfer->rx_xfer->rx_totlen) ) {
+			if (dw_xfer->nbytes == 1) {
+				*(int8_t *)(dw_xfer->rx_xfer->rx_buf) = rx_w;
+			} else {
+				*(int16_t *)(dw_xfer->rx_xfer->rx_buf) = rx_w;
+			}
+			dw_xfer->rx_xfer->rx_buf += dw_xfer->nbytes;
+		}
+		dw_xfer->rx_xfer->rx_idx += dw_xfer->nbytes;
+		dw_xfer->rx_idx += dw_xfer->nbytes;
+		rx_max --;
+	}
+	return ((rx_cnt-rx_max) * dw_xfer->nbytes);
+}
+
+Inline uint32_t dw_spi_nbytes(uint32_t dfs)
+{
+	uint32_t nbytes = 1;
+
+	if (dfs > 8) nbytes = 2;
+	return nbytes;
+}
+
+static void dw_spi_init_transfer(DW_SPI_CTRL *spi_ctrl_ptr, DEV_SPI_TRANSFER *xfer, uint32_t dfs)
+{
+	DW_SPI_TRANSFER *dw_xfer= &(spi_ctrl_ptr->dw_xfer);
+	uint32_t tot_len = 0;
+
+	dw_xfer->tx_xfer = xfer;
+	dw_xfer->rx_xfer = xfer;
+	dw_xfer->tx_idx = 0;
+	dw_xfer->rx_idx = 0;
+	dw_xfer->nbytes = dw_spi_nbytes(dfs);
+
+	/** Calculate all transfer length */
+	while (xfer) {
+		DEV_SPI_XFER_INIT(xfer);
+		tot_len += xfer->tot_len;
+		xfer = xfer->next;
+	}
+	dw_xfer->xfer_len = tot_len;
+}
+
+/* Check buffer align status, 0 for aligned, -1 for not-aligned */
+static int32_t dw_spi_chk_xfer_aligned(DEV_SPI_TRANSFER *xfer, uint32_t dfs)
+{
+	uint32_t align_bytes = 1;
+	if (xfer == NULL) return -1;
+
+	if (dfs > 8) {
+		align_bytes = 2;
+	} else {
+		return 0;
+	}
+
+	while (xfer) {
+		/* check tx buffer align status */
+		if (xfer->tx_len != 0) {
+			if (xfer->tx_len % align_bytes) return -1;
+			if (xfer->tx_ofs % align_bytes) return -1;
+			if (!CHECK_ALIGN_BYTES(xfer->tx_buf, align_bytes)) return -1;
+		}
+		/* check tx buffer align status */
+		if (xfer->rx_len != 0) {
+			if (xfer->rx_len % align_bytes) return -1;
+			if (xfer->rx_ofs % align_bytes) return -1;
+			if (!CHECK_ALIGN_BYTES(xfer->rx_buf, align_bytes)) return -1;
+		}
+		xfer = xfer->next;
+	}
+	return 0;
+}
+
+static uint32_t dw_spi_poll_transfer(DEV_SPI_INFO *spi_info_ptr)
+{
+	uint32_t len = 0;
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
+
+	spi_info_ptr->status |= DEV_IN_XFER;
+	while (!dw_spi_xfer_end(spi_ctrl_ptr)) {
+		len += dw_spi_writer(spi_info_ptr);
+		len += dw_spi_reader(spi_info_ptr);
+	}
+	spi_info_ptr->status &= ~DEV_IN_XFER;
+
+	return len>>1;
+}
+
+/** @} */
+
+/**
+ * \brief	open a designware spi device
+ * \param[in]	spi_obj	spi object pointer
+ * \param[in]	mode	spi working mode (master or slave)
+ * \param[in]	param	parameter, for master, param is the freq, for slave, param is dfs
+ * \retval	E_OK	Open successfully without any issues
+ * \retval	E_OPNED	If device was opened before with different parameters,
+ *			then just increase the \ref dev_spi_info::opn_cnt "opn_cnt" and return \ref E_OPNED
+ * \retval	E_OBJ	Device object is not valid
+ * \retval	E_SYS	Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first.
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_NOSPT	Open settings are not supported
+ */
+int32_t dw_spi_open (DEV_SPI *spi_obj, uint32_t mode, uint32_t param)
+{
+	int32_t ercd = E_OK;
+	uint32_t param2check;
+	uint32_t clk_mode, dfs_val;
+	uint32_t support_modes;
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
+	DW_SPI_CHECK_EXP((mode==DEV_MASTER_MODE)||(mode==DEV_SLAVE_MODE), E_PAR);
+	if (mode == DEV_SLAVE_MODE) { /* clock mode should be in the enum structure */
+		DW_SPI_CHECK_EXP((param>=SPI_CPOL_0_CPHA_0) && (param<=SPI_CPOL_1_CPHA_1), E_PAR);
+	} else { /* frequence should > 0 */
+		DW_SPI_CHECK_EXP(param>0, E_PAR);
+	}
+	/* END OF ERROR CHECK */
+
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
+
+	/* Check supported modes, master or slave */
+	support_modes = spi_ctrl_ptr->support_modes;
+	DW_SPI_CHECK_EXP( (((support_modes)&DW_SPI_MASTER_SUPPORTED)&&(mode == DEV_MASTER_MODE)) || \
+				(((support_modes)&DW_SPI_SLAVE_SUPPORTED)&&(mode == DEV_SLAVE_MODE)), E_NOSPT);
+
+	/** Check opened before use case */
+	if (spi_info_ptr->opn_cnt > 0) {
+		if (mode != spi_info_ptr->mode) {
+			/* current working mode is different from passing mode */
+			return E_SYS;
+		}
+		if (mode == DEV_MASTER_MODE) { /* param is freq when as master */
+			param2check = spi_info_ptr->freq;
+		} else { /* param is clk_mode when as slave */
+			param2check = spi_info_ptr->clk_mode;
+		}
+		spi_info_ptr->opn_cnt ++;
+		if (param != param2check) { /* open with different speed mode */
+			return E_OPNED;
+		} else {
+			return E_OK;
+		}
+	}
+	/* auto increase open count */
+	spi_info_ptr->opn_cnt ++;
+
+	/* Do FIFO Length get before init */
+#if DW_SPI_CALC_FIFO_LEN_ENABLE
+	spi_ctrl_ptr->tx_fifo_len = dw_spi_get_txfifo_len(spi_ctrl_ptr->dw_spi_regs);
+	spi_ctrl_ptr->rx_fifo_len = dw_spi_get_rxfifo_len(spi_ctrl_ptr->dw_spi_regs);
+#endif
+	/* hardware init */
+	spi_info_ptr->mode = mode;
+	clk_mode = SPI_CLK_MODE_DEFAULT;
+	dfs_val = SPI_DFS_DEFAULT;
+	if (mode == DEV_SLAVE_MODE) {
+		clk_mode = param;
+	}
+	spi_info_ptr->dfs = dfs_val;
+	spi_info_ptr->clk_mode = clk_mode;
+	dw_spi_hw_init(spi_ctrl_ptr, clk_mode, dfs_val);
+	if (mode == DEV_MASTER_MODE) { /* Deselect all slaves, and set frequence */
+		dw_spi_deselect_slave(spi_ctrl_ptr->dw_spi_regs, 0);
+		dw_spi_set_freq(spi_ctrl_ptr, param);
+		spi_info_ptr->freq = param;
+	}
+
+	spi_info_ptr->status = DEV_ENABLED;
+	spi_info_ptr->extra = NULL;
+	spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED;
+	spi_info_ptr->dummy = 0xff;
+
+	spi_ctrl_ptr->int_status = 0;
+	dw_spi_init_transfer(spi_ctrl_ptr, NULL, dfs_val);
+
+	/** install spi interrupt into system */
+	dw_spi_disable_interrupt(spi_info_ptr);
+	int_handler_install(spi_ctrl_ptr->intno, spi_ctrl_ptr->dw_spi_int_handler);
+	memset(&(spi_info_ptr->xfer), 0, sizeof(DEV_SPI_TRANSFER));
+	memset(&(spi_info_ptr->spi_cbs), 0, sizeof(DEV_SPI_CBS));
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	close a DesignWare SPI device
+ * \param[in]	spi_obj	spi object pointer
+ * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
+ * \retval	E_OPNED	Device is still opened, the device \ref dev_spi_info::opn_cnt "opn_cnt" decreased by 1
+ * \retval	E_OBJ	Device object is not valid
+ */
+int32_t dw_spi_close (DEV_SPI *spi_obj)
+{
+	int32_t ercd = E_OK;
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
+	DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_OK);
+	/* END OF ERROR CHECK */
+
+	spi_info_ptr->opn_cnt --;
+	if (spi_info_ptr->opn_cnt == 0) {
+		DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+
+		dw_spi_disable_interrupt(spi_info_ptr);
+		dw_spi_abort_tx(spi_obj);
+		dw_spi_abort_rx(spi_obj);
+		memset(&(spi_info_ptr->xfer), 0, sizeof(DEV_SPI_TRANSFER));
+		memset(&(spi_info_ptr->spi_cbs), 0, sizeof(DEV_SPI_CBS));
+		memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER));
+		dw_spi_disable_device(spi_info_ptr);
+		spi_info_ptr->status = DEV_DISABLED;
+		spi_info_ptr->extra = NULL;
+	} else {
+		ercd = E_OPNED;
+	}
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	control spi by ctrl command
+ * \param[in]		spi_obj		spi object pointer
+ * \param[in]		ctrl_cmd	control command code to do specific spi work
+ * \param[in,out]	param		parameters used to control spi or return something
+ * \retval	E_OK	Control device successfully
+ * \retval	E_CLSED	Device is not opened
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
+ * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
+ * \retval	E_NOSPT	Control command is not supported or not valid
+ */
+int32_t dw_spi_control (DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param)
+{
+	int32_t ercd = E_OK;
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
+	DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED);
+	/* END OF ERROR CHECK */
+
+	uint32_t val32; /** to receive unsigned int value */
+	DEV_BUFFER *devbuf;
+
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+	DEV_SPI_TRANSFER *spi_xfer = &(spi_info_ptr->xfer);
+
+	/* check whether current device is disabled */
+	if ((spi_info_ptr->status & DEV_ENABLED) == 0) {
+		/** When device is disabled,
+		 * only SPI_CMD_ENA_DEV, SPI_CMD_DIS_DEV, SPI_CMD_GET_STATUS, SPI_CMD_RESET
+		 * are available, other commands will return E_SYS
+		 */
+		if ((ctrl_cmd != SPI_CMD_ENA_DEV) && \
+			(ctrl_cmd != SPI_CMD_DIS_DEV) && \
+			(ctrl_cmd != SPI_CMD_GET_STATUS) && \
+			(ctrl_cmd != SPI_CMD_RESET) ) {
+			return E_SYS;
+		}
+	}
+
+	switch (ctrl_cmd) {
+		/* Commmon commands for both master and slave mode */
+		case SPI_CMD_GET_STATUS:
+			DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = spi_info_ptr->status;
+			break;
+		case SPI_CMD_SET_CLK_MODE:
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			val32 = (uint32_t)param;
+			DW_SPI_CHECK_EXP((val32>=SPI_CPOL_0_CPHA_0) && (val32<=SPI_CPOL_1_CPHA_1), E_PAR);
+			if (dw_spi_set_clockmode(spi_reg_ptr, val32) == 0) {
+				spi_info_ptr->clk_mode = val32;
+			} else {
+				ercd = E_SYS;
+			}
+			break;
+		case SPI_CMD_ENA_DEV:
+			dw_spi_enable_device(spi_info_ptr);
+			break;
+		case SPI_CMD_DIS_DEV:
+			dw_spi_disable_device(spi_info_ptr);
+			break;
+		case SPI_CMD_RESET:
+			dw_spi_reset_device(spi_info_ptr);
+			break;
+		case SPI_CMD_FLUSH_TX:
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			dw_spi_flush_tx(spi_reg_ptr);
+			break;
+		case SPI_CMD_FLUSH_RX:
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			dw_spi_flush_rx(spi_reg_ptr);
+			break;
+		case SPI_CMD_SET_DFS:
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			val32 = (uint32_t)param;
+			DW_SPI_CHECK_EXP(val32>0, E_PAR);
+			if (dw_spi_set_dfs(spi_reg_ptr, val32) == 0) {
+				spi_info_ptr->dfs = val32;
+			} else {
+				ercd = E_SYS;
+			}
+			break;
+		case SPI_CMD_SET_DUMMY_DATA:
+			val32 = (uint32_t)param;
+			spi_info_ptr->dummy = val32;
+			break;
+		case SPI_CMD_GET_RXAVAIL: /* Notice in bytes unit */
+			DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = dw_spi_get_rxavail(spi_ctrl_ptr) * dw_spi_nbytes(spi_info_ptr->dfs);
+			break;
+		case SPI_CMD_GET_TXAVAIL: /* Notice in bytes unit */
+			DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = dw_spi_get_txavail(spi_ctrl_ptr) * dw_spi_nbytes(spi_info_ptr->dfs);
+			break;
+		case SPI_CMD_SET_TXCB:
+			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			spi_info_ptr->spi_cbs.tx_cb = param;
+			break;
+		case SPI_CMD_SET_RXCB:
+			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			spi_info_ptr->spi_cbs.rx_cb = param;
+			break;
+		case SPI_CMD_SET_XFERCB:
+			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			spi_info_ptr->spi_cbs.xfer_cb = param;
+			break;
+		case SPI_CMD_SET_ERRCB:
+			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			spi_info_ptr->spi_cbs.err_cb = param;
+			break;
+		case SPI_CMD_ABORT_TX:
+			ercd = dw_spi_abort_tx(spi_obj);
+			break;
+		case SPI_CMD_ABORT_RX:
+			ercd = dw_spi_abort_rx(spi_obj);
+			break;
+		case SPI_CMD_ABORT_XFER:
+			ercd = dw_spi_abort_xfer(spi_obj);
+			break;
+		case SPI_CMD_SET_TXINT:
+			val32 = (uint32_t)param;
+			if (val32 == 0) {
+				ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND);
+			} else {
+				ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_SND);
+			}
+			break;
+		case SPI_CMD_SET_RXINT:
+			val32 = (uint32_t)param;
+			if (val32 == 0) {
+				ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
+			} else {
+				ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
+			}
+			break;
+		case SPI_CMD_SET_TXINT_BUF:
+			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			if (param != NULL) {
+				devbuf = (DEV_BUFFER *)param;
+				DEV_SPI_XFER_SET_TXBUF(spi_xfer, devbuf->buf, 0, devbuf->len);
+				DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, devbuf->len, 0);
+				DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL);
+				DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(spi_xfer, spi_info_ptr->dfs) == 0, E_PAR);
+				dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs);
+			} else {
+				DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, 0, 0);
+				DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, 0, 0);
+				DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL);
+				dw_spi_init_transfer(spi_ctrl_ptr, NULL, spi_info_ptr->dfs);
+			}
+			break;
+		case SPI_CMD_SET_RXINT_BUF:
+			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			if (param != NULL) {
+				devbuf = (DEV_BUFFER *)param;
+				DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, devbuf->len, 0);
+				DEV_SPI_XFER_SET_RXBUF(spi_xfer, devbuf->buf, 0, devbuf->len);
+				DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL);
+				/* Check transfer align */
+				DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(spi_xfer, spi_info_ptr->dfs) == 0, E_PAR);
+				dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs);
+			} else {
+				DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, 0, 0);
+				DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, 0, 0);
+				DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL);
+				dw_spi_init_transfer(spi_ctrl_ptr, NULL, spi_info_ptr->dfs);
+			}
+			break;
+		case SPI_CMD_TRANSFER_POLLING:
+			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			if (param != NULL) {
+				/* Check transfer align */
+				DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned((DEV_SPI_TRANSFER *)param, spi_info_ptr->dfs) == 0, E_PAR);
+				*spi_xfer = *((DEV_SPI_TRANSFER *)param);
+				dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs);
+				/* Transfer data by poll */
+				dw_spi_poll_transfer(spi_info_ptr);
+			} else {
+				ercd = E_PAR;
+			}
+			break;
+		case SPI_CMD_TRANSFER_INT:
+			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			if (param != NULL) {
+				DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+				/* Check transfer align */
+				DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned((DEV_SPI_TRANSFER *)param, spi_info_ptr->dfs) == 0, E_PAR);
+				*spi_xfer = *((DEV_SPI_TRANSFER *)param);
+				dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs);
+				/* Transfer data by interrupt */
+				ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
+			} else {
+				ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
+			}
+			break;
+
+		/* Master mode only commands */
+		case SPI_CMD_MST_SET_FREQ:
+			DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			val32 = (uint32_t)param;
+			DW_SPI_CHECK_EXP(val32>0, E_PAR);
+			dw_spi_set_freq(spi_ctrl_ptr, val32);
+			spi_info_ptr->freq = val32;
+			break;
+		case SPI_CMD_MST_SEL_DEV:
+			DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			val32 = (uint32_t)param;
+			if (dw_spi_select_slave(spi_reg_ptr, val32) == 0) {
+				spi_info_ptr->slave = val32;
+			} else {
+				ercd = E_SYS;
+			}
+			break;
+		case SPI_CMD_MST_DSEL_DEV:
+			DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
+			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+			val32 = (uint32_t)param;
+			if (dw_spi_deselect_slave(spi_reg_ptr, val32) == 0) {
+				spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED;
+			} else {
+				ercd = E_SYS;
+			}
+			break;
+
+		/* Slave mode only commands */
+
+
+		default:
+			ercd = E_NOSPT;
+			break;
+	}
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	send data through DesignWare SPI
+ * \param[in]	spi_obj	spi object pointer
+ * \param[in]	data	pointer to data need to send by spi
+ * \param[in]	len	length of data to be sent
+ * \retval	>0	Byte count that was successfully sent for poll method
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_CTX	Device is still in transfer state
+ * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
+ */
+int32_t dw_spi_write (DEV_SPI *spi_obj, const void *data, uint32_t len)
+{
+	int32_t ercd = E_OK;
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
+	DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED);
+	DW_SPI_CHECK_EXP(spi_info_ptr->status & DEV_ENABLED, E_SYS);
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+	DW_SPI_CHECK_EXP(data!=NULL, E_PAR);
+	DW_SPI_CHECK_EXP(len>0, E_PAR);
+	/* END OF ERROR CHECK */
+
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
+	DEV_SPI_TRANSFER spi_xfer;
+
+	/* Master and Slave transmit */
+	DEV_SPI_XFER_SET_TXBUF(&spi_xfer, data, 0, len);
+	DEV_SPI_XFER_SET_RXBUF(&spi_xfer, NULL, len, 0);
+	DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL);
+
+	/* Check transfer align */
+	DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(&spi_xfer, spi_info_ptr->dfs) == 0, E_PAR);
+
+	dw_spi_init_transfer(spi_ctrl_ptr, &spi_xfer, spi_info_ptr->dfs);
+
+	ercd = dw_spi_poll_transfer(spi_info_ptr);
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	read data through DesignWare SPI
+ * \param[in]	spi_info_ptr	spi information structure pointer
+ * \param[out]	data		data that need to read (data must be char type)
+ * \param[in]	len		data count need to read
+ * \retval	>=0		data have been read
+ * \retval	E_PAR		arguments passed was wrong
+ * \retval	E_OBJ		spi has something error, nothing can be done
+ * \retval	E_CLSED		spi was closed, not available for control
+ * \retval	<0		other error code not defined here
+ */
+int32_t dw_spi_read (DEV_SPI *spi_obj, void *data, uint32_t len)
+{
+	int32_t ercd = E_OK;
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
+	DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED);
+	DW_SPI_CHECK_EXP(spi_info_ptr->status & DEV_ENABLED, E_SYS);
+	DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
+	DW_SPI_CHECK_EXP(data!=NULL, E_PAR);
+	DW_SPI_CHECK_EXP(len>0, E_PAR);
+	/* END OF ERROR CHECK */
+
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
+	DEV_SPI_TRANSFER spi_xfer;
+
+	/* Master and Slave transmit */
+	DEV_SPI_XFER_SET_TXBUF(&spi_xfer, NULL, len, 0);
+	DEV_SPI_XFER_SET_RXBUF(&spi_xfer, data, 0, len);
+	DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL);
+
+	/* Check transfer align */
+	DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(&spi_xfer, spi_info_ptr->dfs) == 0, E_PAR);
+
+	dw_spi_init_transfer(spi_ctrl_ptr, &spi_xfer, spi_info_ptr->dfs);
+
+	ercd = dw_spi_poll_transfer(spi_info_ptr);
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	DesignWare SPI interrupt processing routine
+ * \param[in]	spi_info_ptr	DEV_SPI_INFO *spi_info_ptr
+ * \param[in]	ptr		extra information
+ */
+void dw_spi_isr(DEV_SPI *spi_obj, void *ptr)
+{
+	int32_t ercd = E_OK;
+	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
+	/* END OF ERROR CHECK */
+
+	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
+	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
+
+	uint32_t isr_status;
+
+	isr_status = spi_reg_ptr->ISR;
+
+	if (!isr_status) return;
+	if (spi_ctrl_ptr->dw_xfer.xfer_len == 0) {
+		dw_spi_disable_interrupt(spi_info_ptr);
+	} else {
+		if (isr_status & (DW_SPI_IMR_TXOIM|DW_SPI_IMR_RXOIM|DW_SPI_IMR_RXUIM)) {
+			dw_spi_clear_interrupt_all(spi_reg_ptr);
+			dw_spi_disable_interrupt(spi_info_ptr);
+			if (spi_info_ptr->spi_cbs.err_cb) {
+				spi_info_ptr->spi_cbs.err_cb(spi_obj);
+			}
+			memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER));
+		}
+		dw_spi_reader(spi_info_ptr);
+		if (isr_status & DW_SPI_IMR_TXEIM) {
+			dw_spi_writer(spi_info_ptr);
+		}
+		if (dw_spi_xfer_end(spi_ctrl_ptr)) {
+			if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX) {
+				dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND);
+				if (spi_info_ptr->spi_cbs.tx_cb) {
+					spi_info_ptr->spi_cbs.tx_cb(spi_obj);
+				}
+			} else if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX) {
+				dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
+				if (spi_info_ptr->spi_cbs.rx_cb) {
+					spi_info_ptr->spi_cbs.rx_cb(spi_obj);
+				}
+			} else if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER) {
+				dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
+				if (spi_info_ptr->spi_cbs.xfer_cb) {
+					spi_info_ptr->spi_cbs.xfer_cb(spi_obj);
+				}
+			} else {
+				dw_spi_disable_interrupt(spi_info_ptr);
+			}
+			memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER));
+		}
+	}
+
+error_exit:
+	return;
+}
+/** @} */ /* DEVICE_DW_SPI_IMPLEMENT */
+
+/** @} */ /* DEVICE_DW_SPI */
diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi.h
new file mode 100644
index 0000000000..ef2faa90e6
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/spi/dw_spi.h
@@ -0,0 +1,190 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-06-25
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \brief	DesignWare SPI driver header file
+ * \ingroup	DEVICE_DW_SPI
+ */
+
+#ifndef _DEVICE_DW_SPI_H_
+#define _DEVICE_DW_SPI_H_
+
+#include "device/device_hal/inc/dev_spi.h"
+
+/**
+ * if this header file is included,
+ * will indicate that this designware spi device
+ * is used
+ */
+#define DEVICE_USE_DESIGNWARE_SPI
+
+#define DW_SPI_IN_FREE			(0)					/*!< Currently not in spi transfer */
+#define DW_SPI_IN_XFER			(DEV_IN_TX|DEV_IN_RX|DEV_IN_XFER)	/*!< Currently in spi transfer */
+#define DW_SPI_IN_TX			(DEV_IN_TX|DEV_IN_XFER)			/*!< Currently in spi tx */
+#define DW_SPI_IN_RX			(DEV_IN_RX|DEV_IN_XFER)			/*!< Currently in spi rx */
+
+#define DW_SPI_GINT_DISABLED		(0)		/*!< designware interrupt disabled for control iic irq/fiq */
+#define DW_SPI_GINT_ENABLE		(1<<0)		/*!< designware interrupt enabled for control iic irq/fiq */
+
+#define DW_SPI_MASTER_SUPPORTED		(0x1)	/*!< Support Designware SPI Master Mode */
+#define DW_SPI_SLAVE_SUPPORTED		(0x2)	/*!< Support Designware SPI Slave Mode */
+/*!< Support Designware SPI Both Master and Slave Mode */
+#define DW_SPI_BOTH_SUPPORTED		(DW_SPI_MASTER_SUPPORTED|DW_SPI_SLAVE_SUPPORTED)
+
+/**
+ * \defgroup	DEVICE_DW_SPI_REGSTRUCT		DesignWare SPI Register Structure
+ * \ingroup	DEVICE_DW_SPI
+ * \brief	contains definitions of DesignWare SPI register structure.
+ * \details	detailed description of DesignWare SPI register information
+ * @{
+ */
+/**
+ * \brief	DesignWare SPI register structure
+ * \details	Detailed struct description of DesignWare SPI
+ * 	block register information, implementation of dev_spi_info::spi_regs
+ */
+typedef volatile struct dw_spi_reg
+{
+	/*!< Control Register */
+	/*!< SPI Control Register 0  (0x0) */
+	uint32_t CTRLR0;
+	/*!< SPI Control Register 1  (0x4) */
+	uint32_t CTRLR1;
+	/*!< Enable Register */
+	/*!< SPI Enable Register  (0x8) */
+	uint32_t SSIENR;
+	/*!< SPI Microwire Control Register  (0xC) */
+	uint32_t MWCR;
+	/*!< SPI Slave Enable Register  (0x10) */
+	uint32_t SER;
+	/*!< SPI Baud Rate Select Register  (0x14) */
+	uint32_t BAUDR;
+	/*!< TX and RX FIFO Control Register */
+	/*!< SPI Transmit FIFO Threshold Level Register  (0x18) */
+	uint32_t TXFTLR;
+	/*!< SPI Receive  FIFO Threshold Level Register  (0x1C) */
+	uint32_t RXFTLR;
+	/*!< SPI Transmit FIFO Level Register  (0x20) */
+	uint32_t TXFLR;
+	/*!< SPI Receive  FIFO Level Register  (0x24) */
+	uint32_t RXFLR;
+	/*!< SPI Status   Register  (0x28) */
+	uint32_t SR;
+	/*!< Interrupt Enable/Disable/Control Registers */
+	/*!< SPI Interrupt Mask Register  (0x2C) */
+	uint32_t IMR;
+	/*!< SPI Interrupt Status Register  (0x30) */
+	uint32_t ISR;
+	/*!< SPI Raw Interrupt Status Register (0x34) */
+	uint32_t RISR;
+	/*!< SPI Transmit FIFO Overflow Interrupt Clear Register  (0x38) */
+	uint32_t TXOICR;
+	/*!< SPI Receive  FIFO Overflow Interrupt Clear Register  (0x3C) */
+	uint32_t RXOICR;
+	/*!< SPI Receive FIFO Underflow Interrupt Clear Register  (0x40) */
+	uint32_t RXUICR;
+	/*!< SPI Multi-Master Interrupt Clear Register  (0x44) */
+	uint32_t MSTICR;
+	/*!< SPI Interrupt Clear Register  (0x48) */
+	uint32_t ICR;
+	/*!< DMA Control Register  (0x4C) */
+	uint32_t DMACR;
+	/*!< DMA Transmit Data Level  (0x50) */
+	uint32_t DMATDLR;
+	/*!< DMA Receive Data Level  (0x54) */
+	uint32_t DMARDLR;
+	/*!< SPI Identification Register  (0x58) */
+	uint32_t IDR;
+	/*!< SPI CoreKit ID Register (Value after Reset : 0x3332322A)  (0x5C) */
+	uint32_t SSI_VER_ID;
+	/*!< Data Register */
+	/*!< SPI DATA Register for both Read and Write  (0x60) */
+	uint32_t DATAREG;
+} DW_SPI_REG, *DW_SPI_REG_PTR;
+/** @} */
+
+/** Designware SPI Message Transfer */
+typedef struct dw_spi_transfer {
+	uint32_t xfer_len;
+	uint32_t tx_idx;
+	uint32_t rx_idx;
+	uint32_t nbytes;
+	DEV_SPI_TRANSFER *tx_xfer;
+	DEV_SPI_TRANSFER *rx_xfer;
+} DW_SPI_TRANSFER, *DW_SPI_TRANSFER_PTR;
+
+/**
+ * \brief	DesignWare SPI control structure definition
+ * \details	implement of dev_spi_info::dev_spi_info
+ */
+typedef struct dw_spi_ctrl {
+	DW_SPI_REG *dw_spi_regs;	/*!< spi register */
+	/* Variables which should be set during object implementation */
+	uint32_t support_modes;		/*!< supported spi modes */
+	uint32_t intno;			/*!< interrupt no */
+	uint32_t dw_apb_bus_freq;	/*!< spi ip apb bus frequency */
+	uint32_t tx_fifo_len;		/*!< transmit fifo length */
+	uint32_t rx_fifo_len;		/*!< receive fifo length */
+	INT_HANDLER dw_spi_int_handler;	/*!< spi interrupt handler */
+	/* Variables which always change during iic operation */
+	uint32_t int_status;		/*!< iic interrupt status */
+	DW_SPI_TRANSFER dw_xfer;	/*!< designware spi transfer */
+} DW_SPI_CTRL, *DW_SPI_CTRL_PTR;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup	DEVICE_DW_SPI_FUNCDLR		DesignWare SPI Function Declaration
+ * \ingroup	DEVICE_DW_SPI
+ * \brief	contains declarations of designware spi functions.
+ * \details	This are only used in \ref dw_spi_obj.c
+ * @{
+ */
+extern int32_t dw_spi_open (DEV_SPI *spi_obj, uint32_t mode, uint32_t param);
+extern int32_t dw_spi_close (DEV_SPI *spi_obj);
+extern int32_t dw_spi_control (DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param);
+extern int32_t dw_spi_write (DEV_SPI *spi_obj, const void *data, uint32_t len);
+extern int32_t dw_spi_read (DEV_SPI *spi_obj, void *data, uint32_t len);
+extern void dw_spi_isr(DEV_SPI *spi_obj, void *ptr);
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* _DEVICE_DW_SPI_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h
new file mode 100644
index 0000000000..b1a233c699
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h
@@ -0,0 +1,141 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-06-25
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	DEVICE_DW_SPI
+ * \brief	DesignWare SPI driver hardware description related header file
+ * \details	detailed hardware related definitions of DesignWare SPI driver
+ */
+
+#ifndef _DEVICE_DW_SPI_HAL_H_
+#define _DEVICE_DW_SPI_HAL_H_
+
+#include "device/designware/spi/dw_spi_hal_cfg.h"
+
+/* DW APB SPI bit definitions */
+
+/**
+ * \name	DesignWare SPI HAL CTRL0 Macros
+ * \brief	DesignWare SPI hal ctrl0 macros,
+ * 	include dfs, scph, scppl, tmod, etc
+ * @{
+ */
+#define DW_SPI_CTRLR0_DFS_MASK			(0xf)
+
+#define DW_SPI_CTRLR0_SC_OFS			(6)
+#define DW_SPI_CTRLR0_SC_MASK			(0xC0)
+#define DW_SPI_CTRLR0_SCPH_HIGH			(0x40)
+#define DW_SPI_CTRLR0_SCPH_LOW			(0)
+#define DW_SPI_CTRLR0_SCPOL_HIGH		(0x80)
+#define DW_SPI_CTRLR0_SCPOL_LOW			(0)
+
+#define DW_SPI_CTRLR0_TMOD_MASK			(0x300)
+#define DW_SPI_TMOD_TRANSMIT_RECEIVE		(0)
+#define DW_SPI_TMOD_TRANSMIT_ONLY		(0x100)
+#define DW_SPI_TMOD_RECEIVE_ONLY		(0x200)
+#define DW_SPI_TMOD_EEPROM_READ_ONLY		(0x300)
+
+#define DW_SPI_CTRLR0_FRF_MOTOROLA		(0x0)
+#define DW_SPI_CTRLR0_FRF_TI			(0x10)
+#define DW_SPI_CTRLR0_FRF_MICROWIRE		(0x20)
+
+#define DW_SPI_CTRLR0_SLV_OE_DISABLE		(1<<10)
+#define DW_SPI_CTRLR0_SLV_OE_ENABLE		(0)
+
+
+/** @} */
+
+/**
+ * \name	DesignWare SPI HAL ISR Flags
+ * \brief	DesignWare SPI hal Interrupt Status Flags
+ * @{
+ */
+#define DW_SPI_TX_OVERFLOW_ERROR		(0x2)
+#define DW_SPI_RX_UNDERFLOW_ERROR		(0x4)
+#define DW_SPI_RX_OVERFLOW_ERROR		(0x8)
+
+#define DW_SPI_ISR_RX_FIFO_INT_MASK		(0x10)
+#define DW_SPI_ISR_TX_FIFO_INT_MASK		(0x1)
+#define DW_SPI_ISR_TX_OVERFLOW_INT_MASK		(0x2)
+#define DW_SPI_ISR_RX_UNDERFLOW_INT_MASK	(0x4)
+#define DW_SPI_ISR_RX_OVERFLOW_INT_MASK		(0x8)
+/** @} */
+
+/**
+ * \name	DesignWare SPI HAL SR Flags
+ * \brief	DesignWare SPI hal Status Flags
+ * @{
+ */
+#define DW_SPI_SR_DCOL				(0x40)
+#define DW_SPI_SR_TXE				(0x20)
+#define DW_SPI_SR_RFF				(0x10)
+#define DW_SPI_SR_RFNE				(0x8)
+#define DW_SPI_SR_TFE				(0x4)
+#define DW_SPI_SR_TFNF				(0x2)
+#define DW_SPI_SR_BUSY				(0x1)
+/** @} */
+
+/**
+ * \name	DesignWare SPI HAL SSI Enable Macros
+ * \brief	DesignWare SPI hal ssi enable macros
+ * @{
+ */
+/* Macros */
+#define DW_SPI_SSI_ENABLE			(1)	/*!< SSI Enable */
+#define DW_SPI_SSI_DISABLE			(0)	/*!< SSI Disable */
+/** @} */
+
+/**
+ * \name	DesignWare SPI HAL IMR Macros
+ * \brief	DesignWare SPI hal interrupt mask macros
+ * @{
+ */
+#define DW_SPI_IMR_MSTIM			(0x20)	/*!< Multi-Master Contention Interrupt Mask */
+#define DW_SPI_IMR_RXFIM			(0x10)	/*!< Receive FIFO Full Interrupt Mask */
+#define DW_SPI_IMR_RXOIM			(0x08)	/*!< Receive FIFO Overflow Interrupt Mask */
+#define DW_SPI_IMR_RXUIM			(0x04)	/*!< Receive FIFO Underflow Interrupt Mask */
+#define DW_SPI_IMR_TXOIM			(0x02)	/*!< Transmit FIFO Overflow Interrupt Mask */
+#define DW_SPI_IMR_TXEIM			(0x01)	/*!< Transmit FIFO Empty Interrupt Mask */
+
+#define DW_SPI_IMR_XFER				(DW_SPI_IMR_TXEIM|DW_SPI_IMR_RXFIM|DW_SPI_IMR_TXOIM|DW_SPI_IMR_RXOIM|DW_SPI_IMR_RXUIM)
+/** @} */
+
+#define DW_SPI_SSI_IDLE				(1)
+#define DW_SPI_SPI_TRANSMIT			(1)
+#define DW_SPI_SPI_RECEIVE			(2)
+#define DW_SPI_SSI_MASTER			(1)
+#define DW_SPI_SSI_SLAVE			(0)
+
+
+#endif /* _DEVICE_DW_SPI_HAL_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h
new file mode 100644
index 0000000000..d6caf71466
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h
@@ -0,0 +1,58 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2015-09-09
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	DEVICE_DW_SPI
+ * \brief	DesignWare SPI driver hardware description
+ * 	related header file configuration file
+ * \details	configuration file to enable or disable some function of spi
+ */
+
+#ifndef _DEVICE_DW_SPI_HAL_CFG_H_
+#define _DEVICE_DW_SPI_HAL_CFG_H_
+
+#ifndef DW_SPI_CALC_FIFO_LEN_ENABLE
+#define DW_SPI_CALC_FIFO_LEN_ENABLE		(1)	/*!< Defaultly enable calculate fifo length */
+#endif
+
+#ifndef DW_SPI_MAX_FIFO_LENGTH
+#define DW_SPI_MAX_FIFO_LENGTH			(256)	/*!< Max FIFO depth for designware SPI device */
+#endif
+
+#ifndef DW_SPI_MIN_FIFO_LENGTH
+#define DW_SPI_MIN_FIFO_LENGTH			(2)	/*!< Min FIFO depth for designware SPI device */
+#endif
+
+#endif /* _DEVICE_DW_SPI_HAL_CFG_H_ */
+
diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart.c b/bsp/synopsys/embarc/device/designware/uart/dw_uart.c
new file mode 100644
index 0000000000..999ee751e0
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/uart/dw_uart.c
@@ -0,0 +1,956 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-20
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_DW_UART	Designware UART Driver
+ * \ingroup	DEVICE_DW
+ * \brief	Designware UART Driver Implementation
+ */
+
+/**
+ * \file
+ * \ingroup	DEVICE_DW_UART
+ * \brief	DesignWare UART driver implementation based on device hal layer definition (\ref dev_uart.h)
+ */
+#include <string.h>
+
+#include "inc/embARC_toolchain.h"
+#include "inc/embARC_error.h"
+
+#include "inc/arc/arc_exception.h"
+
+#include "device/designware/uart/dw_uart_hal.h"
+#include "device/designware/uart/dw_uart.h"
+
+
+/**
+ * \name	DesignWare UART Driver Macros
+ * \brief	DesignWare UART driver macros used in uart driver
+ * @{
+ */
+/** check expressions used in DesignWare UART driver implementation */
+#define DW_UART_CHECK_EXP(EXPR, ERROR_CODE)		CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
+
+#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
+/** valid check of uart info object */
+#define VALID_CHK_UART_INFO_OBJECT(uartinfo_obj_ptr)		{				\
+			DW_UART_CHECK_EXP((uartinfo_obj_ptr)!=NULL, E_OBJ);			\
+			DW_UART_CHECK_EXP(((uartinfo_obj_ptr)->uart_ctrl)!=NULL, E_OBJ);	\
+ 		}
+#endif
+
+/** convert DesignWare baudrate to divisor */
+#define DW_UART_BAUD2DIV(perifreq, baud)		((perifreq) / ((baud)*16))
+
+/**
+ * \name	DesignWare UART Interrupt Callback Routine Select Marcos
+ * \brief	DesignWare UART interrupt callback routines select macros definitions
+ * @{
+ */
+#define DW_UART_RDY_SND					(1U)	/*!< ready to send callback */
+#define DW_UART_RDY_RCV					(2U)	/*!< ready to receive callback */
+/** @} */
+
+/** @} */
+
+/**
+ * \defgroup	DEVICE_DW_UART_STATIC	DesignWare UART Driver Static Functions
+ * \ingroup	DEVICE_DW_UART
+ * \brief	Static or inline functions, variables for DesignWare UART handle uart operations,
+ * 	only used in this file
+ * @{
+ */
+const uint8_t dw_uart_databits[] = { \
+	DW_UART_LCR_WORD_LEN5, DW_UART_LCR_WORD_LEN6, \
+	DW_UART_LCR_WORD_LEN7, DW_UART_LCR_WORD_LEN8};
+const uint8_t dw_uart_parity[] = {
+	DW_UART_LCR_PARITY_NONE, DW_UART_LCR_PARITY_ODD,
+	DW_UART_LCR_PARITY_EVEN, DW_UART_LCR_PARITY_MASK,
+	DW_UART_LCR_PARITY_SPACE
+};
+const uint8_t dw_uart_stopbits[] = {
+	DW_UART_LCR_1_STOP_BIT, DW_UART_LCR_1D5_STOP_BIT,
+	DW_UART_LCR_2_STOP_BIT
+};
+
+/** test whether uart is ready to send, 1 ready, 0 not ready */
+Inline int32_t dw_uart_putready(DW_UART_REG *uart_reg_ptr)
+{
+	return ((uart_reg_ptr->USR & DW_UART_USR_TFNF) != 0);
+}
+/** test whether uart is ready to receive, 1 ready, 0 not ready */
+Inline int32_t dw_uart_getready(DW_UART_REG *uart_reg_ptr)
+{
+	return ((uart_reg_ptr->USR & DW_UART_USR_RFNE) != 0);
+}
+/** write char to uart send fifo */
+Inline void dw_uart_putchar(DW_UART_REG *uart_reg_ptr, char chr)
+{
+	uart_reg_ptr->DATA = chr;
+}
+/** read data from uart receive fifo, return data received */
+Inline int32_t dw_uart_getchar(DW_UART_REG *uart_reg_ptr)
+{
+	return (int32_t)uart_reg_ptr->DATA;
+}
+/**
+ * \brief	send char by uart when available,
+ * 	mostly used in interrupt method, non-blocked function
+ * \param[in]	uart_reg_ptr	uart register structure pointer
+ * \param[in]	chr		char to be sent
+ * \retval	0		send successfully
+ * \retval	-1		not ready to send data
+ */
+Inline int32_t dw_uart_snd_chr(DW_UART_REG *uart_reg_ptr, char chr)
+{
+	if (dw_uart_putready(uart_reg_ptr)) {
+		dw_uart_putchar(uart_reg_ptr, chr);
+		return 0;
+	}
+	return -1;
+}
+/**
+ * \brief	receive one char from uart,
+ * 	mostly used in interrupt routine, non-blocked function
+ * \param[in]	uart_reg_ptr	uart register structure pointer
+ * \return	data received by the uart
+ */
+Inline int32_t dw_uart_rcv_chr(DW_UART_REG *uart_reg_ptr)
+{
+	return dw_uart_getchar(uart_reg_ptr);
+}
+/**
+ * \brief	send char by uart in poll method, blocked function
+ * \param[in]	uart_reg_ptr	uart register structure pointer
+ * \param[in]	chr		char to be sent
+ */
+Inline void dw_uart_psnd_chr(DW_UART_REG *uart_reg_ptr, char chr)
+{
+	/** wait until uart is ready to send */
+	while (!dw_uart_putready(uart_reg_ptr)); /* blocked */
+	/** send char */
+	dw_uart_putchar(uart_reg_ptr, chr);
+}
+/**
+ * \brief	receive one char from uart in poll method, blocked function
+ * \param[in]	uart_reg_ptr	uart register structure pointer
+ * \return	data received by the uart
+ */
+Inline int32_t dw_uart_prcv_chr(DW_UART_REG *uart_reg_ptr)
+{
+	/** wait until uart is ready to receive */
+	while (!dw_uart_getready(uart_reg_ptr)); /* blocked */
+	/** receive data */
+	return dw_uart_getchar(uart_reg_ptr);
+}
+
+/** Get TX FIFO Length */
+Inline uint32_t dw_uart_get_txfifo_len(DW_UART_REG *uart_reg_ptr)
+{
+	uint32_t txfifolen;
+	uint32_t uart_cpr;
+
+	uart_cpr = uart_reg_ptr->CPR;
+	if (uart_cpr & DW_UART_CPR_FIFO_STAT) {
+		txfifolen = ((uart_cpr & DW_UART_CPR_FIFO_MODE) >> DW_UART_CPR_FIFO_MODE_OFS) << 4;
+	} else {
+		txfifolen = 0;
+	}
+
+	return txfifolen;
+}
+
+/** Get RX FIFO Length */
+Inline uint32_t dw_uart_get_rxfifo_len(DW_UART_REG *uart_reg_ptr)
+{
+	uint32_t rxfifolen;
+	uint32_t uart_cpr;
+
+	uart_cpr = uart_reg_ptr->CPR;
+	if (uart_cpr & DW_UART_CPR_FIFO_STAT) {
+		rxfifolen = ((uart_cpr & DW_UART_CPR_FIFO_MODE) >> DW_UART_CPR_FIFO_MODE_OFS) << 4;
+	} else {
+		rxfifolen = 0;
+	}
+
+	return rxfifolen;
+}
+
+/**
+ * \brief	set designware uart DPS value
+ * \param	uart_reg_ptr	uart register structure
+ * \param	dps		data bits/parity bit/stop bits parameter
+ * \retval	0	Set ok
+ * \retval	!0	Set failed
+ */
+static int32_t dw_uart_set_dps(DW_UART_REG *uart_reg_ptr, UART_DPS_FORMAT *dps)
+{
+	uint32_t dps_value = 0;
+
+	if (dps == NULL) return -1;
+	/* data bits check */
+	if ((dps->databits < 5) || (dps->databits > 8)) return -1;
+	/* stop bits check */
+	if (dps->stopbits > UART_STPBITS_TWO) return -1;
+	/* parity bit type check */
+	if (dps->parity > UART_PARITY_SPACE) return -1;
+
+	dps_value |= (uint32_t)dw_uart_databits[dps->databits-5];
+	dps_value |= (uint32_t)dw_uart_stopbits[dps->stopbits];
+	dps_value |= (uint32_t)dw_uart_parity[dps->parity];
+
+	/* clear dps bits */
+	uart_reg_ptr->LCR &= (~DW_UART_LCR_DPS_MASK);
+	/* set dps bits */
+	uart_reg_ptr->LCR |= dps_value;
+
+	return 0;
+}
+
+/**
+ * \brief	set designware uart baudrate
+ * \param	uart_reg_ptr	uart register structure
+ * \param	baud_divisor	uart baudrate divisor
+ */
+static void dw_uart_set_baud(DW_UART_REG *uart_reg_ptr, uint32_t baud_divisor)
+{
+	/* enable uart baudrate update */
+	uart_reg_ptr->LCR |= DW_UART_LCR_DLAB;
+	/**
+	 * setting uart baudrate registers
+	 */
+	uart_reg_ptr->DATA = baud_divisor & 0xff;	/*!< DLL */
+	uart_reg_ptr->IER = (baud_divisor>>8) & 0xff;	/*!< DLH */
+	/** disable DLAB */
+	uart_reg_ptr->LCR &= ~(DW_UART_LCR_DLAB);
+}
+
+/**
+ * \brief	Do uart software reset
+ * \param	uart_reg_ptr	uart register structure
+ */
+Inline void dw_uart_software_reset(DW_UART_REG *uart_reg_ptr)
+{
+	uart_reg_ptr->SRR = DW_UART_SRR_UR|DW_UART_SRR_RFR|DW_UART_SRR_XFR;
+	while(uart_reg_ptr->USR & DW_UART_USR_BUSY); /* wait until software reset completed */
+}
+
+/**
+ * \brief	set designware uart baudrate
+ * \param	uart_reg_ptr	uart register structure
+ * \param	hwfc		uart hardware flow control type
+ * \note	Need to set corresponding pin functions
+ */
+static void dw_uart_set_hwfc(DW_UART_REG *uart_reg_ptr, UART_HW_FLOW_CONTROL hwfc)
+{
+	if (hwfc == UART_FC_NONE) {
+		uart_reg_ptr->MCR &= ~(DW_UART_MCR_AFCE|DW_UART_MCR_RTS);
+	}
+	if ((hwfc == UART_FC_RTS) || (hwfc == UART_FC_BOTH)) {
+		uart_reg_ptr->MCR |= (DW_UART_MCR_AFCE|DW_UART_MCR_RTS);
+	}
+	if ((hwfc == UART_FC_CTS) || (hwfc == UART_FC_BOTH)) {
+		uart_reg_ptr->MCR |= (DW_UART_MCR_AFCE);
+	}
+}
+
+Inline void dw_uart_set_break(DW_UART_REG *uart_reg_ptr)
+{
+	uart_reg_ptr->LCR |= DW_UART_LCR_BREAK;
+}
+
+Inline void dw_uart_clr_break(DW_UART_REG *uart_reg_ptr)
+{
+	uart_reg_ptr->LCR &= ~DW_UART_LCR_BREAK;
+}
+
+/**
+ * \brief	init designware uart with selected baud
+ * \param[in]	uart_reg_ptr	uart register structure pointer
+ * \param[in]	baud_divisor	baudrate divisor
+ */
+static void dw_uart_init(DW_UART_REG *uart_reg_ptr, uint32_t baud_divisor, UART_DPS_FORMAT *dps, UART_HW_FLOW_CONTROL hwfc)
+{
+	dw_uart_software_reset(uart_reg_ptr);
+
+	dw_uart_set_hwfc(uart_reg_ptr, hwfc);
+	dw_uart_set_dps(uart_reg_ptr, dps);
+	dw_uart_set_baud(uart_reg_ptr, baud_divisor);
+
+	uart_reg_ptr->IIR = 0x1;	/** enable uart fifo (FCR IIR is the same) */
+	uart_reg_ptr->IER = 0x0;	/** disable all uart interrupt */
+}
+
+/**
+ * \brief	set designware uart baudrate
+ * \param	uart_info_ptr	uart information structure pointer
+ */
+static void dw_uart_flush_output(DEV_UART_INFO *uart_info_ptr)
+{
+	uint32_t i;
+	char *p_charbuf;
+
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	if (uart_info_ptr->tx_buf.buf != NULL) {
+		p_charbuf = (char *)(uart_info_ptr->tx_buf.buf);
+		for (i = uart_info_ptr->tx_buf.ofs; i < uart_info_ptr->tx_buf.len; i ++) {
+			dw_uart_psnd_chr(uart_reg_ptr, p_charbuf[i]);
+		}
+		/* clear transmit buffer */
+		uart_info_ptr->tx_buf.buf = NULL;
+		uart_info_ptr->tx_buf.len = 0;
+		uart_info_ptr->tx_buf.ofs = 0;
+	}
+	/* wait until transmit fifo is empty */
+	while ((uart_reg_ptr->USR & DW_UART_USR_TFE) == 0);
+	while (uart_reg_ptr->USR & DW_UART_USR_BUSY);
+}
+
+/**
+ * \brief	disable designware uart send or receive interrupt
+ * \param[in]	DEV_UART_INFO 	*uart_info_ptr
+ * \param[in]	cbrtn		control code of callback routine of send or receive
+ */
+static void dw_uart_dis_cbr(DEV_UART_INFO *uart_info_ptr, uint32_t cbrtn)
+{
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	switch (cbrtn) {
+		case DW_UART_RDY_SND:
+			uart_reg_ptr->IER &= ~DW_UART_IER_XMIT_EMPTY;
+			uart_ctrl_ptr->int_status &= ~DW_UART_TXINT_ENABLE;
+			break;
+		case DW_UART_RDY_RCV:
+			uart_reg_ptr->IER &= ~DW_UART_IER_DATA_AVAIL;
+			uart_ctrl_ptr->int_status &= ~DW_UART_RXINT_ENABLE;
+			break;
+		default:
+			break;
+	}
+	if (uart_ctrl_ptr->int_status & DW_UART_GINT_ENABLE) {
+		if ((uart_ctrl_ptr->int_status & (DW_UART_RXINT_ENABLE|DW_UART_TXINT_ENABLE)) == 0) {
+			int_disable(uart_ctrl_ptr->intno);
+			uart_ctrl_ptr->int_status &= ~DW_UART_GINT_ENABLE;
+		}
+	}
+}
+
+/**
+ * \brief	enable DesignWare UART send or receive interrupt
+ * \param[in]	DEV_UART_INFO 	*uart_info_ptr
+ * \param[in]	cbrtn		control code of callback routine of send or receive
+ */
+static void dw_uart_ena_cbr(DEV_UART_INFO *uart_info_ptr, uint32_t cbrtn)
+{
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	switch (cbrtn) {
+		case DW_UART_RDY_SND:
+			uart_ctrl_ptr->int_status |= DW_UART_TXINT_ENABLE;
+			uart_reg_ptr->IER |= DW_UART_IER_XMIT_EMPTY;
+			break;
+		case DW_UART_RDY_RCV:
+			uart_ctrl_ptr->int_status |= DW_UART_RXINT_ENABLE;
+			uart_reg_ptr->IER |= DW_UART_IER_DATA_AVAIL;
+			break;
+		default:
+			break;
+	}
+	if ((uart_ctrl_ptr->int_status & DW_UART_GINT_ENABLE) == 0) {
+		if (uart_ctrl_ptr->int_status & (DW_UART_RXINT_ENABLE|DW_UART_TXINT_ENABLE)) {
+			uart_ctrl_ptr->int_status |= DW_UART_GINT_ENABLE;
+			int_enable(uart_ctrl_ptr->intno);
+		}
+	}
+}
+
+/**
+ * \brief	enable designware uart interrupt
+ * \param	uart_info_ptr	uart information structure pointer
+ */
+static void dw_uart_enable_interrupt(DEV_UART_INFO *uart_info_ptr)
+{
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+
+	int_handler_install(uart_ctrl_ptr->intno, uart_ctrl_ptr->dw_uart_int_handler);
+	uart_ctrl_ptr->int_status |= DW_UART_GINT_ENABLE;
+	int_enable(uart_ctrl_ptr->intno);	/** enable uart interrupt */
+}
+/**
+ * \brief	disable designware uart interrupt
+ * \param	uart_info_ptr	uart information structure pointer
+ */
+static void dw_uart_disable_interrupt(DEV_UART_INFO *uart_info_ptr)
+{
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+
+	/** disable uart send&receive interrupt after disable uart interrupt */
+	dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND);
+	dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV);
+	/* disable uart interrupt */
+	int_disable(uart_ctrl_ptr->intno);
+	uart_ctrl_ptr->int_status &= ~(DW_UART_GINT_ENABLE|DW_UART_TXINT_ENABLE|DW_UART_RXINT_ENABLE);
+}
+
+/** enable designware uart */
+static void dw_uart_enable_device(DEV_UART_INFO *uart_info_ptr)
+{
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	if ((uart_info_ptr->status & DEV_ENABLED) == 0) {
+		dw_uart_set_baud(uart_reg_ptr, uart_info_ptr->baudrate);
+		uart_info_ptr->status |= DEV_ENABLED;
+	}
+}
+
+/** disable designware uart */
+static void dw_uart_disable_device(DEV_UART_INFO *uart_info_ptr)
+{
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	if ((uart_info_ptr->status & DEV_ENABLED) == DEV_ENABLED) {
+		dw_uart_set_baud(uart_reg_ptr, 0);
+		uart_info_ptr->status &= ~DEV_ENABLED;
+	}
+}
+
+/** abort current interrupt transmit transfer */
+static void dw_uart_abort_tx(DEV_UART *uart_obj)
+{
+	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+
+	if (uart_ctrl_ptr->int_status & DW_UART_TXINT_ENABLE) {
+		dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND);
+		uart_info_ptr->status |= DEV_IN_TX_ABRT;
+		if (uart_info_ptr->uart_cbs.tx_cb != NULL) {
+			uart_info_ptr->uart_cbs.tx_cb(uart_obj);
+		}
+		uart_info_ptr->status &= ~(DEV_IN_TX_ABRT);
+	}
+}
+
+/** abort current interrupt receive transfer */
+static void dw_uart_abort_rx(DEV_UART *uart_obj)
+{
+	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+
+	if (uart_ctrl_ptr->int_status & DW_UART_RXINT_ENABLE) {
+		dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV);
+		uart_info_ptr->status |= DEV_IN_RX_ABRT;
+		if (uart_info_ptr->uart_cbs.rx_cb != NULL) {
+			uart_info_ptr->uart_cbs.rx_cb(uart_obj);
+		}
+		uart_info_ptr->status &= ~(DEV_IN_RX_ABRT);
+	}
+}
+
+/** Get available transmit fifo count */
+static int32_t dw_uart_get_txavail(DW_UART_CTRL *uart_ctrl_ptr)
+{
+	int32_t tx_avail = 0;
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG *)(uart_ctrl_ptr->dw_uart_regbase);
+
+	if (uart_ctrl_ptr->tx_fifo_len <= 1) {
+		if (dw_uart_putready(uart_reg_ptr) == 1) {
+			tx_avail = 1;
+		} else {
+			tx_avail = 0;
+		}
+	} else {
+		tx_avail = uart_ctrl_ptr->tx_fifo_len - uart_reg_ptr->TFL;
+	}
+	return tx_avail;
+}
+
+/** Get available receive fifo count */
+static int32_t dw_uart_get_rxavail(DW_UART_CTRL *uart_ctrl_ptr)
+{
+	int32_t rx_avail = 0;
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG *)(uart_ctrl_ptr->dw_uart_regbase);
+
+	if (uart_ctrl_ptr->rx_fifo_len <= 1) {
+		if (dw_uart_getready(uart_reg_ptr) == 1) {
+			rx_avail = 1;
+		} else {
+			rx_avail = 0;
+		}
+	} else {
+		rx_avail = uart_reg_ptr->RFL;
+	}
+	return rx_avail;
+}
+
+
+/** @} end of group DEVICE_DW_UART_STATIC */
+
+/**
+ * \brief	open a designware uart device
+ * \param[in]	uart_obj	uart object structure pointer
+ * \param[in]	baud		baudrate to initialized
+ * \retval	E_OK	Open successfully without any issues
+ * \retval	E_OPNED	If device was opened before with different baudrate, then return E_OPNED
+ * \retval	E_OBJ	Device object is not valid
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_NOSPT	Open settings are not supported
+ */
+int32_t dw_uart_open (DEV_UART *uart_obj, uint32_t baud)
+{
+	int32_t ercd = E_OK;
+	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
+	DW_UART_CHECK_EXP(baud>0, E_PAR);
+	/* END OF ERROR CHECK */
+
+	uart_info_ptr->opn_cnt ++;
+	if (uart_info_ptr->opn_cnt > 1) { /* opened before */
+		if (baud == uart_info_ptr->baudrate) { /* baudrate is the same */
+			return E_OK;
+		} else { /* open with different baudrate */
+			return E_OPNED;
+		}
+	}
+
+	int32_t baud_divisor = 0;
+
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	/* Get FIFO Length */
+	uart_ctrl_ptr->tx_fifo_len = dw_uart_get_txfifo_len(uart_reg_ptr);
+	uart_ctrl_ptr->rx_fifo_len = dw_uart_get_rxfifo_len(uart_reg_ptr);
+
+	/** init uart */
+	uart_info_ptr->baudrate = baud;
+	baud_divisor = DW_UART_BAUD2DIV(uart_ctrl_ptr->dw_apb_bus_freq, baud);
+	uart_info_ptr->dps_format = dps_format_default;
+	uart_info_ptr->hwfc = hwfc_default;
+	dw_uart_init(uart_reg_ptr, baud_divisor, &(uart_info_ptr->dps_format), uart_info_ptr->hwfc);
+
+	uart_info_ptr->status = DEV_ENABLED;
+	uart_info_ptr->extra = NULL;
+
+	/**
+	 * uart interrupt related init
+	 */
+	dw_uart_disable_interrupt(uart_info_ptr);
+	/** install uart interrupt into system */
+	int_handler_install(uart_ctrl_ptr->intno, uart_ctrl_ptr->dw_uart_int_handler);
+
+	memset(&(uart_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER));
+	memset(&(uart_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER));
+	memset(&(uart_info_ptr->uart_cbs), 0, sizeof(DEV_UART_CBS));
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	close a DesignWare UART device
+ * \param[in]	uart_obj	uart object structure pointer
+ * \retval	E_OK	Open successfully without any issues
+ * \retval	E_OPNED	Device is still opened, the device opn_cnt decreased by 1
+ * \retval	E_OBJ	Device object is not valid
+ */
+int32_t dw_uart_close (DEV_UART *uart_obj)
+{
+	int32_t ercd = E_OK;
+	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
+	DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_OK);
+	/* END OF ERROR CHECK */
+
+	uart_info_ptr->opn_cnt --;
+	if (uart_info_ptr->opn_cnt == 0) {
+		dw_uart_disable_interrupt(uart_info_ptr);
+		dw_uart_abort_tx(uart_obj);
+		dw_uart_abort_rx(uart_obj);
+		dw_uart_flush_output(uart_info_ptr);
+		memset(&(uart_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER));
+		memset(&(uart_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER));
+		memset(&(uart_info_ptr->uart_cbs), 0, sizeof(DEV_UART_CBS));
+		dw_uart_disable_device(uart_info_ptr);
+		uart_info_ptr->status = 0;
+		uart_info_ptr->extra = NULL;
+	} else {
+		ercd = E_OPNED;
+	}
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	control uart by ctrl command
+ * \param[in]	uart_obj	uart object structure pointer
+ * \param[in]	ctrl_cmd	control command code to do specific uart work
+ * \param[in,out]	param	parameters used to control uart or return something
+ * \retval	E_OK	Control device successfully
+ * \retval	E_CLSED	Device is not opened
+ * \retval	E_DIS	Device is disabled
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Control device failed, due to hardware issues
+ * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
+ * \retval	E_NOSPT	Control command is not supported or not valid
+ */
+int32_t dw_uart_control (DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param)
+{
+	int32_t ercd = E_OK;
+	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
+	DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED);
+	/* END OF ERROR CHECK */
+
+	uint32_t val32; /** to receive unsigned int value */
+	int32_t baud_divisor = 0;
+	DEV_BUFFER *devbuf;
+	UART_DPS_FORMAT *dps_ptr;
+	UART_HW_FLOW_CONTROL hwfc_local;
+
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	/* check whether current device is disabled */
+	if ((uart_info_ptr->status & DEV_ENABLED) == 0) {
+		/** When device is disabled,
+		 * only UART_CMD_ENA_DEV, UART_CMD_DIS_DEV, UART_CMD_GET_STATUS
+		 * are available, other commands will return E_SYS
+		 */
+		if ((ctrl_cmd != UART_CMD_ENA_DEV) && \
+			(ctrl_cmd != UART_CMD_DIS_DEV) && \
+			(ctrl_cmd != UART_CMD_GET_STATUS) ) {
+			return E_SYS;
+		}
+	}
+
+	switch (ctrl_cmd) {
+		case UART_CMD_SET_BAUD:
+			val32 = (uint32_t)param;
+			DW_UART_CHECK_EXP(val32>0, E_PAR);
+			if (val32 != uart_info_ptr->baudrate) {
+				baud_divisor = DW_UART_BAUD2DIV(uart_ctrl_ptr->dw_apb_bus_freq, val32);
+				dw_uart_set_baud(uart_reg_ptr, baud_divisor);
+				uart_info_ptr->baudrate = val32;
+			}
+			break;
+		case UART_CMD_GET_STATUS:
+			DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = uart_info_ptr->status;
+			break;
+		case UART_CMD_ENA_DEV:
+			dw_uart_enable_device(uart_info_ptr);
+			break;
+		case UART_CMD_DIS_DEV:
+			dw_uart_disable_device(uart_info_ptr);
+			break;
+		case UART_CMD_FLUSH_OUTPUT:
+			dw_uart_flush_output(uart_info_ptr);
+			break;
+		case UART_CMD_GET_RXAVAIL:
+			DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = dw_uart_get_rxavail(uart_ctrl_ptr);
+			break;
+		case UART_CMD_GET_TXAVAIL:
+			DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
+			*((int32_t *)param) = dw_uart_get_txavail(uart_ctrl_ptr);
+			break;
+		case UART_CMD_BREAK_SET:
+			dw_uart_set_break(uart_reg_ptr);
+			break;
+		case UART_CMD_BREAK_CLR:
+			dw_uart_clr_break(uart_reg_ptr);
+			break;
+		case UART_CMD_SET_DPS_FORMAT:
+			DW_UART_CHECK_EXP(param!=NULL, E_PAR);
+			dps_ptr = (UART_DPS_FORMAT *)param;
+			if (dw_uart_set_dps(uart_reg_ptr, dps_ptr) == 0) {
+				uart_info_ptr->dps_format = *dps_ptr;
+			} else {
+				ercd = E_PAR;
+			}
+			break;
+		case UART_CMD_SET_HWFC:
+			hwfc_local = (UART_HW_FLOW_CONTROL)param;
+			DW_UART_CHECK_EXP(((hwfc_local>=UART_FC_NONE) && (hwfc_local<=UART_FC_BOTH)), E_PAR);
+			dw_uart_set_hwfc(uart_reg_ptr, hwfc_local);
+			uart_info_ptr->hwfc = hwfc_local;
+			break;
+		case UART_CMD_SET_TXCB:
+			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			uart_info_ptr->uart_cbs.tx_cb = param;
+			break;
+		case UART_CMD_SET_RXCB:
+			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			uart_info_ptr->uart_cbs.rx_cb = param;
+			break;
+		case UART_CMD_SET_ERRCB:
+			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			uart_info_ptr->uart_cbs.err_cb = param;
+			break;
+		case UART_CMD_ABORT_TX:
+			dw_uart_abort_tx(uart_obj);
+			break;
+		case UART_CMD_ABORT_RX:
+			dw_uart_abort_rx(uart_obj);
+			break;
+		case UART_CMD_SET_TXINT:
+			val32 = (uint32_t)param;
+			if (val32 == 0) {
+				dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND);
+			} else {
+				dw_uart_ena_cbr(uart_info_ptr, DW_UART_RDY_SND);
+			}
+			break;
+		case UART_CMD_SET_RXINT:
+			val32 = (uint32_t)param;
+			if (val32 == 0) {
+				dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV);
+			} else {
+				dw_uart_ena_cbr(uart_info_ptr, DW_UART_RDY_RCV);
+			}
+			break;
+		case UART_CMD_SET_TXINT_BUF:
+			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			if (param != NULL) {
+				devbuf = (DEV_BUFFER *)param;
+				uart_info_ptr->tx_buf = *devbuf;
+				uart_info_ptr->tx_buf.ofs = 0;
+			} else {
+				uart_info_ptr->tx_buf.buf = NULL;
+				uart_info_ptr->tx_buf.len = 0;
+				uart_info_ptr->tx_buf.ofs = 0;
+			}
+			break;
+		case UART_CMD_SET_RXINT_BUF:
+			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
+			if (param != NULL) {
+				devbuf = (DEV_BUFFER *)param;
+				uart_info_ptr->rx_buf = *devbuf;
+				uart_info_ptr->rx_buf.ofs = 0;
+			} else {
+				uart_info_ptr->rx_buf.buf = NULL;
+				uart_info_ptr->rx_buf.len = 0;
+				uart_info_ptr->rx_buf.ofs = 0;
+			}
+			break;
+		default:
+			ercd = E_NOSPT;
+			break;
+	}
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	send data through DesignWare UART
+ * \param[in]	uart_obj	uart object structure pointer
+ * \param[in]	data		data that need to send (data must be char type)
+ * \param[in]	len		data length need to send
+ * \retval	>0	Byte count that was successfully sent for poll method
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Can't write data to hardware due to hardware issues
+ */
+int32_t dw_uart_write (DEV_UART *uart_obj, const void *data, uint32_t len)
+{
+	int32_t ercd = E_OK;
+	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
+	DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED);
+	DW_UART_CHECK_EXP(uart_info_ptr->status & DEV_ENABLED, E_SYS);
+	DW_UART_CHECK_EXP(data!=NULL, E_PAR);
+	DW_UART_CHECK_EXP(len>0, E_PAR);
+	/* END OF ERROR CHECK */
+
+	int32_t i = 0;
+	const char *p_charbuf = (const char *)data;
+
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	while (i < len) {
+		dw_uart_psnd_chr(uart_reg_ptr, p_charbuf[i++]);
+	}
+	ercd = i;
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	read data through DesignWare UART
+ * \param[in]	uart_obj	uart object structure pointer
+ * \param[out]	data		data that need to read (data must be char type)
+ * \param[in]	len		data count need to read
+ * \retval	>0	Byte count that was successfully sent for poll method
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
+ */
+int32_t dw_uart_read (DEV_UART *uart_obj, void *data, uint32_t len)
+{
+	int32_t ercd = E_OK;
+	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
+	DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED);
+	DW_UART_CHECK_EXP(uart_info_ptr->status & DEV_ENABLED, E_SYS);
+	DW_UART_CHECK_EXP(data!=NULL, E_PAR);
+	DW_UART_CHECK_EXP(len>0, E_PAR);
+	/* END OF ERROR CHECK */
+
+	int32_t i = 0;
+	char *p_charbuf = (char *)data;
+
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	while (i < len) {
+		p_charbuf[i++] = dw_uart_prcv_chr(uart_reg_ptr);
+	}
+	ercd = i;
+
+error_exit:
+	return ercd;
+}
+
+/**
+ * \brief	DesignWare UART interrupt processing routine
+ * \param[in]	uart_obj	uart object structure pointer
+ * \param[in]	ptr		extra information
+ */
+void dw_uart_isr (DEV_UART *uart_obj, void *ptr)
+{
+	int32_t ercd = E_OK;
+	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
+
+	/* START ERROR CHECK */
+	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
+	/* END OF ERROR CHECK */
+
+	uint32_t uart_int_status; /** uart interrupt status */
+	volatile uint32_t temp; /** read error status to clear interrupt */
+	DEV_BUFFER *buf_ptr;
+	char *p_charbuf;
+
+	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
+	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
+
+	/** get uart interrupt status */
+	uart_int_status = (uart_reg_ptr->IIR) & DW_UART_IIR_INT_ID_MASK;
+
+	switch (uart_int_status) {
+		case DW_UART_IIR_MDM_STATUS:
+			temp = (volatile uint32_t)(uart_reg_ptr->MSR);
+			break;
+		case DW_UART_IIR_LINE_STATUS:
+			if (uart_info_ptr->uart_cbs.err_cb) {
+				uart_info_ptr->uart_cbs.err_cb(uart_info_ptr);
+			}
+			temp = (volatile uint32_t)(uart_reg_ptr->LSR);
+			break;
+		case DW_UART_IIR_XMIT_EMPTY:
+			buf_ptr = &(uart_info_ptr->tx_buf);
+			p_charbuf = (char *)buf_ptr->buf;
+			if (p_charbuf != NULL) {
+				while (dw_uart_putready(uart_reg_ptr)) {
+					dw_uart_putchar(uart_reg_ptr, p_charbuf[buf_ptr->ofs]);
+					buf_ptr->ofs ++;
+					if (buf_ptr->ofs >= buf_ptr->len) {
+						dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND);
+						if (uart_info_ptr->uart_cbs.tx_cb) {
+							uart_info_ptr->uart_cbs.tx_cb(uart_obj);
+						}
+						/* clear the send buffer pointer */
+						memset(buf_ptr, 0, sizeof(DEV_BUFFER));
+						break;
+					}
+				}
+			} else {
+				if (uart_info_ptr->uart_cbs.tx_cb) {
+					uart_info_ptr->uart_cbs.tx_cb(uart_obj);
+				}
+			}
+			break;
+		case DW_UART_IIR_RX_TIMEOUT:
+			temp = dw_uart_getchar(uart_reg_ptr);
+			break;
+		case DW_UART_IIR_DATA_AVAIL:
+			buf_ptr = &(uart_info_ptr->rx_buf);
+			p_charbuf = (char *)buf_ptr->buf;
+			if (p_charbuf != NULL) {
+				while (dw_uart_getready(uart_reg_ptr)) {
+					p_charbuf[buf_ptr->ofs] = (char)dw_uart_getchar(uart_reg_ptr);
+					buf_ptr->ofs ++;
+					if (buf_ptr->ofs >= buf_ptr->len) {
+						dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV);
+						if (uart_info_ptr->uart_cbs.rx_cb) {
+							uart_info_ptr->uart_cbs.rx_cb(uart_obj);
+						}
+						/* clear the send buffer pointer */
+						memset(buf_ptr, 0, sizeof(DEV_BUFFER));
+						break;
+					}
+				}
+			} else {
+				if (uart_info_ptr->uart_cbs.rx_cb) {
+					uart_info_ptr->uart_cbs.rx_cb(uart_obj);
+				}
+			}
+			break;
+		default:
+			temp = (volatile uint32_t)(uart_reg_ptr->USR);
+			break;
+	}
+
+error_exit:
+	return;
+}
diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart.h b/bsp/synopsys/embarc/device/designware/uart/dw_uart.h
new file mode 100644
index 0000000000..366c4fccc2
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/uart/dw_uart.h
@@ -0,0 +1,141 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-20
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	DEVICE_DW_UART
+ * \brief	DesignWare UART driver header file
+ * \details     detailed definitions of designware uart driver
+ */
+
+#ifndef _DW_UART_H_
+#define _DW_UART_H_
+
+#include "device/device_hal/inc/dev_uart.h"
+
+#include "inc/arc/arc_exception.h"
+
+/**
+ * if this header file is included,
+ * will indicate that this designware uart device
+ * is used
+ */
+#define DEVICE_USE_DESIGNWARE_UART
+
+/**
+ * \name	DesignWare UART Register Structure
+ * \brief	contains definitions of DesignWare UART register structure.
+ * @{
+ */
+/**
+ * \brief	DesignWare UART register structure
+ * \details	Detailed struct description of DesignWare UART
+ * 	block register information, implementation of dev_uart_info::uart_regs
+ */
+typedef volatile struct dw_uart_reg {
+	uint32_t DATA;		/*!< data in/out and DLL */
+	uint32_t IER;		/*!< Interrupt enable register and DLH */
+	uint32_t IIR;		/*!< Interrupt Id register and FCR */
+	uint32_t LCR;		/*!< Line control Register */
+	uint32_t MCR;		/*!< Modem control register */
+	uint32_t LSR;		/*!< Line Status Register */
+	uint32_t MSR;		/*!< Modem status Register */
+	uint32_t SCRATCHPAD;	/*!< Uart scratch pad register */
+	uint32_t LPDLL;		/*!< Low Power Divisor Latch (Low) Reg */
+	uint32_t LPDLH;		/*!< Low Power Divisor Latch (High) Reg */
+	uint32_t RES1[2];	/*!< Reserved */
+	uint32_t SHR[16];	/*!< Shadow data register(SRBR and STHR) */
+	uint32_t FAR;		/*!< FIFO Access register */
+	uint32_t TFR;		/*!< Transmit FIFO Read */
+	uint32_t RFW;		/*!< Receive FIFO write */
+	uint32_t USR;		/*!< UART status register */
+	uint32_t TFL;		/*!< Transmit FIFO level */
+	uint32_t RFL;		/*!< Receive FIFO level */
+	uint32_t SRR;		/*!< Software reset register */
+	uint32_t SRTS;		/*!< Shadow request to send */
+	uint32_t SBCR;		/*!< Shadow break control */
+	uint32_t SDMAM;		/*!< Shadow DMA mode */
+	uint32_t SFE;		/*!< Shadow FIFO enable */
+	uint32_t SRT;		/*!< Shadow RCVR Trigger */
+	uint32_t STET;		/*!< Shadow TX empty register */
+	uint32_t HTX;		/*!< Halt TX */
+	uint32_t DMASA;		/*!< DMA Software ACK */
+	uint32_t RES2[18];	/*!< Reserved */
+	uint32_t CPR;		/*!< Camponent parameter register */
+	uint32_t UCV;		/*!< UART Component Version */
+	uint32_t CTR;		/*!< Component typw register */
+} DW_UART_REG, *DW_UART_REG_PTR;
+/** @} */
+
+#define DW_UART_GINT_DISABLED	(0)		/*!< designware interrupt disabled for control uart irq/fiq */
+#define DW_UART_GINT_ENABLE	(1<<0)		/*!< designware interrupt enabled for control uart irq/fiq */
+#define DW_UART_TXINT_ENABLE	(1<<1)		/*!< designware interrupt enabled for control transmit process */
+#define DW_UART_RXINT_ENABLE	(1<<2)		/*!< designware interrupt enabled for control transmit process */
+
+/**
+ * \brief	DesignWare UART control structure definition
+ * \details	implement of dev_uart_info::uart_ctrl
+ */
+typedef struct dw_uart_ctrl {
+	uint32_t dw_uart_regbase;		/*!< uart ip register base */
+	uint32_t dw_apb_bus_freq;		/*!< uart ip apb bus frequency */
+	uint32_t intno;				/*!< uart interrupt vector number */
+	INT_HANDLER dw_uart_int_handler;	/*!< uart interrupt handler */
+	uint32_t tx_fifo_len;			/*!< transmit fifo length, set by user in object implementation */
+	uint32_t rx_fifo_len;			/*!< receive fifo length, set by user in object implementation */
+	uint32_t int_status;			/*!< interrupt status for designware uart */
+} DW_UART_CTRL, *DW_UART_CTRL_PTR;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name	DesignWare UART Function Declaration
+ * \brief	contains declarations of designware uart functions.
+ * \details	This are only used in uart object implementation source file
+ * @{
+ */
+extern int32_t dw_uart_open (DEV_UART *uart_obj, uint32_t baud);
+extern int32_t dw_uart_close (DEV_UART *uart_obj);
+extern int32_t dw_uart_control (DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param);
+extern int32_t dw_uart_write (DEV_UART *uart_obj, const void *data, uint32_t len);
+extern int32_t dw_uart_read (DEV_UART *uart_obj, void *data, uint32_t len);
+extern void dw_uart_isr(DEV_UART *uart_obj, void *ptr);
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DW_UART_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h b/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h
new file mode 100644
index 0000000000..367894df99
--- /dev/null
+++ b/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h
@@ -0,0 +1,253 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-20
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	DEVICE_DW_IIC
+ * \brief	DesignWare UART driver hardware description related header file
+ * \details	detailed hardware related definitions of DesignWare UART driver
+ */
+
+#ifndef _DEVICE_DW_UART_HAL_H_
+#define _DEVICE_DW_UART_HAL_H_
+
+/* DW APB UART bit definitions */
+
+/**
+ * \name	DesignWare UART HAL IER Marcos
+ * \brief	DesignWare UART hal IER related macros
+ * @{
+ */
+/* IER */
+#define DW_UART_IER_DATA_AVAIL			(0x01)
+#define DW_UART_IER_XMIT_EMPTY			(0x02)
+#define DW_UART_IER_LINE_STATUS			(0x04)
+#define DW_UART_IER_MDM_STATUS			(0x08)
+#define DW_UART_IER_PTIME			(0x80)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL IIR Marcos
+ * \brief	DesignWare UART hal IIR related macros
+ * @{
+ */
+/* IIR */
+/* IIR READ */
+#define DW_UART_IIR_IP				(0x01)
+#define DW_UART_IIR_MASK			(0x0E)
+#define DW_UART_IIR_READ_FIFO_ENABLE		(0xC0)
+
+/* Possible interrupt IIR_MASK values */
+#define DW_UART_IIR_MDM_STATUS			(0x00)
+#define DW_UART_IIR_XMIT_EMPTY			(0x02)
+#define DW_UART_IIR_DATA_AVAIL			(0x04)
+#define DW_UART_IIR_LINE_STATUS			(0x06)
+#define DW_UART_IIR_RX_TIMEOUT			(0x0C)
+#define DW_UART_IIR_INT_ID_MASK			(0x0f)
+
+/* IIR WRITE */
+#define DW_UART_IIR_FIFO_ENABLE			(0x01)
+#define DW_UART_IIR_RCVR_FIFO_RESET		(0x02)
+#define DW_UART_IIR_XMIT_FIFO_RESET		(0x04)
+#define DW_UART_IIR_DMA_MODE_SELECT		(0x08)
+#define DW_UART_IIR_RCV_TRIGGER_MASK		(0xC0)
+
+/* Values for IIR receive trigger */
+#define DW_UART_IIR_TRIGGER_LEVEL_1_CHAR	(0x00)
+#define DW_UART_IIR_TRIGGER_LEVEL_1_4_FULL	(0x40)
+#define DW_UART_IIR_TRIGGER_LEVEL_1_2_FULL	(0x80)
+#define DW_UART_IIR_TRIGGER_LEVEL_2_LESS_FULL	(0xC0)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL LCR Marcos
+ * \brief	DesignWare UART hal LCR related macros
+ * @{
+ */
+/* LCR */
+#define DW_UART_LCR_WORD_LEN_MASK		(0x03)
+#define DW_UART_LCR_STOP_BIT_MASK		(0x04)
+#define DW_UART_LCR_PARITY_MASK			(0x38)
+#define DW_UART_LCR_DPS_MASK			(0x3F)
+#define DW_UART_LCR_STICK_PARITY		(0x20)
+#define DW_UART_LCR_BREAK			(0x40)
+#define DW_UART_LCR_DLAB			(0x80)
+
+/* Word length values */
+#define DW_UART_LCR_WORD_LEN5			(0x00)
+#define DW_UART_LCR_WORD_LEN6			(0x01)
+#define DW_UART_LCR_WORD_LEN7			(0x02)
+#define DW_UART_LCR_WORD_LEN8			(0x03)
+
+/* stop bit values */
+#define DW_UART_LCR_1_STOP_BIT			(0x00)
+#define DW_UART_LCR_1D5_STOP_BIT		(0x04)
+#define DW_UART_LCR_2_STOP_BIT			(0x04)
+
+/* Parity bit values */
+#define DW_UART_LCR_PARITY_NONE			(0x00)
+#define DW_UART_LCR_PARITY_ODD			(0x08)
+#define DW_UART_LCR_PARITY_EVEN			(0x18)
+#define DW_UART_LCR_PARITY_MARK			(0x28)
+#define DW_UART_LCR_PARITY_SPACE		(0x38)
+
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL MCR Marcos
+ * \brief	DesignWare UART hal MCR related macros
+ * @{
+ */
+/* MCR */
+#define DW_UART_MCR_DTR				(0x01)
+#define DW_UART_MCR_RTS				(0x02)
+#define DW_UART_MCR_LOOPBACK			(0x10)
+#define DW_UART_MCR_AFCE			(0x20)
+#define DW_UART_MCR_SIRE			(0x40)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL LSR Marcos
+ * \brief	DesignWare UART hal LSR related macros
+ * @{
+ */
+/* LSR */
+#define DW_UART_LSR_DR				(0x01)
+#define DW_UART_LSR_OVERRUN			(0x02)
+#define DW_UART_LSR_PARITYERR			(0x04)
+#define DW_UART_LSR_FRAMEERR			(0x08)
+#define DW_UART_LSR_BREAKRCVD			(0x10)
+#define DW_UART_LSR_TXD_EMPTY			(0x20)
+#define DW_UART_LSR_TX_STATUS			(0x40)
+#define DW_UART_LSR_RX_FIFOERR			(0x80)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL MSR Marcos
+ * \brief	DesignWare UART hal MSR related macros
+ * @{
+ */
+/* MSR */
+#define DW_UART_MSR_DCTS			(0x01)
+#define DW_UART_MSR_DDSR			(0x02)
+#define DW_UART_MSR_TERI			(0x04)
+#define DW_UART_MSR_DDCD			(0x08)
+#define DW_UART_MSR_CTS				(0x10)
+#define DW_UART_MSR_DSR				(0x20)
+#define DW_UART_MSR_RIC				(0x40)
+#define DW_UART_MSR_DCD				(0x80)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL FCR Marcos
+ * \brief	DesignWare UART hal FCR related macros
+ * @{
+ */
+/* FCR */
+#define DW_UART_FCR_FEN				(0x01)
+#define DW_UART_FCR_RFR				(0x02)
+#define DW_UART_FCR_TFR				(0x04)
+#define DW_UART_FCR_DMS				(0x08)
+#define DW_UART_FCR_RTL				(0xC0)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL USR Marcos
+ * \brief	DesignWare UART hal USR related macros
+ * @{
+ */
+/* USR */
+#define DW_UART_USR_BUSY			(0x01)
+#define DW_UART_USR_TFNF			(0x02)
+#define DW_UART_USR_TFE				(0x04)
+#define DW_UART_USR_RFNE			(0x08)
+#define DW_UART_USR_RFF				(0x10)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL SFE Marcos
+ * \brief	DesignWare UART hal SFE related macros
+ * @{
+ */
+/* SFE */
+#define DW_UART_SFE_SHADOW_FIFO_ENABLE		(0x01)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL SRR Marcos
+ * \brief	DesignWare UART hal SRR related macros
+ * @{
+ */
+/* SRR */
+#define DW_UART_SRR_UR				(0x01)
+#define DW_UART_SRR_RFR				(0x02)
+#define DW_UART_SRR_XFR				(0x04)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL SRT Marcos
+ * \brief	DesignWare UART hal SRT related macros
+ * @{
+ */
+/* SRT */
+#define DW_UART_SRT_TRIGGER_LEVEL_1_CHAR	(0x00)
+#define DW_UART_SRT_TRIGGER_LEVEL_1_4_FULL	(0x01)
+#define DW_UART_SRT_TRIGGER_LEVEL_1_2_FULL	(0x02)
+#define DW_UART_SRT_TRIGGER_LEVEL_2_LESS_FULL	(0x03)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL STET Marcos
+ * \brief	DesignWare UART hal STET related macros
+ * @{
+ */
+/* STET*/
+#define DW_UART_STET_FIFO_EMPTY			(0x00)
+#define DW_UART_STET_2_CHARS_IN_FIFO		(0x01)
+#define DW_UART_STET_1_4_FULL			(0x02)
+#define DW_UART_STET_1_2_FULL			(0x03)
+/** @} */
+
+/**
+ * \name	DesignWare UART HAL CPR Marcos
+ * \brief	DesignWare UART hal CPR related macros
+ * @{
+ */
+/* CPR*/
+#define DW_UART_CPR_FIFO_STAT			(1<<10)
+#define DW_UART_CPR_FIFO_MODE_OFS		(16)
+#define DW_UART_CPR_FIFO_MODE_MASK		(0xFF)
+#define DW_UART_CPR_FIFO_MODE			(0xFF0000)
+/** @} */
+
+#endif /* _DEVICE_DW_UART_HAL_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h
new file mode 100644
index 0000000000..623d54a611
--- /dev/null
+++ b/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h
@@ -0,0 +1,173 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-16
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_HAL_COMMON	Common Device Layer Definitions
+ * \ingroup	DEVICE_HAL_DEF
+ * \brief	common definitions for device layer (\ref dev_common.h)
+ *
+ * @{
+ *
+ * \file
+ * \brief	header file to define common definitions for device layer
+ * \details	Here in this file provide definitions that need by other
+ * 	devices in device layer
+ */
+
+#ifndef _DEVICE_HAL_COMMON_H_
+#define _DEVICE_HAL_COMMON_H_
+
+#include <stdint.h>
+
+/**
+ * \defgroup	DEVICE_HAL_COMMON_DEVSTATE	Common Device State
+ * \ingroup	DEVICE_HAL_COMMON
+ * \brief	definitions for device state
+ * \details	here defines macros for device open/close,
+ * 	device working good/error, used in
+ * 	\ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
+ * 	\ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO
+ * @{
+ */
+/*
+ * macros for device open and close state
+ */
+#define DEV_CLOSED				(0)	/*!< Indicate that device was closed */
+#define DEV_OPENED				(1)	/*!< Indicate that the device was opened */
+
+/*
+ * macros for device good and error state
+ */
+#define DEV_GOOD				(0)	/*!< Indicate device is good */
+#define DEV_ERROR				(1)	/*!< Indicate device error */
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_COMMON_DEVMTHD	Common Device Working Method
+ * \ingroup	DEVICE_HAL_COMMON
+ * \brief	definitions for device working method(interrupt or poll)
+ * \details	here defines macros for working method,
+ * 	interrupt or poll method,used in
+ * 	\ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
+ * 	\ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO
+ * @{
+ */
+/*
+ * macros for device working method
+ */
+#define DEV_POLL_METHOD				(0)	/*!< Indicate that the device running in poll method */
+#define DEV_INTERRUPT_METHOD			(1)	/*!< Indicate that the device running in interrupt method */
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_COMMON_DEVMODE	Common Device Working Mode
+ * \ingroup	DEVICE_HAL_COMMON
+ * \brief	definitions for device working mode(master or slave)
+ * \details	here defines macros for working mode,
+ * 	Master or Slave mode,used in
+ * 	\ref DEV_HAL_IIC, \ref DEV_HAL_SPI.
+ * @{
+ */
+/*
+ * macros for device working mode
+ */
+#define DEV_MASTER_MODE				(0)	/*!< Indicate that the device working as master */
+#define DEV_SLAVE_MODE				(1)	/*!< Indicate that the device working as slave */
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_COMMON_DEVSTATUS	Common Device Status
+ * \ingroup	DEVICE_HAL_COMMON
+ * \brief	definitions for device status, 1 bit for 1 function
+ * @{
+ */
+#define DEV_DISABLED				(0)	/*!< Bit 0 for device enabled state, disabled */
+#define DEV_ENABLED				(1<<0)	/*!< Bit 0 for device enabled state, enabled */
+#define DEV_IN_TX				(1<<1)	/*!< Bit 1 for device in transmit state */
+#define DEV_IN_RX				(1<<2)	/*!< Bit 2 for device in receive state */
+#define DEV_IN_XFER				(1<<3)	/*!< Bit 3 for device in transfer state */
+#define DEV_IN_TX_ABRT				(1<<4)	/*!< Bit 4 for device in transmit abort state */
+#define DEV_IN_RX_ABRT				(1<<5)	/*!< Bit 5 for device in receive abort state */
+#define DEV_IN_XFER_ABRT			(1<<6)	/*!< Bit 6 for device in transfer abort state */
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_COMMON_DEFCMD	Common Device Defining Command
+ * \ingroup	DEVICE_HAL_COMMON
+ * \brief	definitions for defining command code
+ * \details	here defines macros to define command code,
+ * 	in system code, use \ref DEV_SET_SYSCMD to define command code.
+ * 	in user code, use \ref DEV_SET_USRCMD to define command code.
+ * 	So that there will be no conflicts in system and user defined command code.
+ * 	this used used in
+ * 	\ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
+ * 	\ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO,
+ *     	and in user code
+ * @{
+ */
+/*
+ * macros for control command base
+ */
+#define DEV_SYS_CMDBSE				(0x00000000)		/*!< default system device control command base(defined by embARC) */
+#define DEV_USR_CMDBSE				(0x80000000)		/*!< default user device control command base(defined by user) in user implementing */
+#define DEV_SET_SYSCMD(cmd)			(DEV_SYS_CMDBSE|(cmd))	/*!< set device system control command */
+#define DEV_SET_USRCMD(cmd)			(DEV_USR_CMDBSE|(cmd))	/*!< set device user control command */
+
+#define CONV2VOID(param)			((void *)(param))	/*!< convert param into void * type */
+/** @} */
+
+/**
+ * Common Device Buffer Structure
+ */
+typedef struct dev_buffer {
+	void *buf;	/*!< buffer pointer */
+	uint32_t len;	/*!< buffer length in bytes */
+	uint32_t ofs;	/*!< current offset in buffer */
+} DEV_BUFFER;
+
+/** Init device buffer */
+#define DEV_BUFFER_INIT(devbuf, buffer, size)	{		\
+					(devbuf)->buf = (void *)(buffer);	\
+					(devbuf)->len = (uint32_t)(size);	\
+					(devbuf)->ofs = (uint32_t)(0);		\
+				}
+
+/**
+ *   Device callback function typedef.
+ * This is usually used in device callback settings,
+ * and \ptr should be the device object pointer,
+ * such as DEV_IIC * */
+typedef void (*DEV_CALLBACK) (void *ptr);
+
+/** @} */
+#endif /* _DEVICE_HAL_COMMON_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h
new file mode 100644
index 0000000000..290fd313a2
--- /dev/null
+++ b/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h
@@ -0,0 +1,424 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-17
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_HAL_GPIO		GPIO Device HAL Interface
+ * \ingroup	DEVICE_HAL_DEF
+ * \brief	definitions for gpio device hardware layer (\ref dev_gpio.h)
+ * \details	provide interfaces for gpio driver to implement
+ *  Here is a diagram for the gpio interface.
+ *
+ *  \htmlonly
+ *  <div class="imagebox">
+ *      <div style="width: 600px">
+ *          <img src="pic/dev_gpio_hal.jpg" alt="GPIO Device HAL Interface Diagram"/>
+ *          <p>GPIO Device HAL Interface Diagram</p>
+ *      </div>
+ *  </div>
+ *  \endhtmlonly
+ *
+ * @{
+ *
+ * \file
+ * \brief	gpio device hardware layer definitions
+ * \details	Provide common definitions for gpio device,
+ * 	then the software developer can develop gpio driver
+ * 	following these definitions, and the applications
+ * 	can directly call this definition to realize functions
+ *
+ */
+
+#ifndef _DEVICE_HAL_GPIO_H_
+#define _DEVICE_HAL_GPIO_H_
+
+#include "device/device_hal/inc/dev_common.h"
+
+/**
+ * \defgroup	DEVICE_HAL_GPIO_DEFDIR	GPIO Port Direction Definition
+ * \ingroup	DEVICE_HAL_GPIO
+ * \brief	Define macros to indicate gpio directions
+ * @{
+ */
+/*
+ * defines for gpio directions
+ */
+#define GPIO_DIR_INPUT				(0)		/*!< gpio works as input */
+#define GPIO_DIR_OUTPUT				(1)		/*!< gpio works as output */
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_GPIO_CTRLCMD		GPIO Device Control Commands
+ * \ingroup	DEVICE_HAL_GPIO
+ * \brief	Definitions for gpio control command, used in \ref dev_gpio::gpio_control "GPIO IO Control"
+ * \details	These commands defined here can be used in user code directly.
+ * - Parameters Usage
+ *   - For passing parameters like integer, just use uint32_t/int32_t to directly pass values
+ *   - For passing parameters for a structure, please use pointer to pass values
+ *   - For getting some data, please use pointer to store the return data
+ * - Common Return Values
+ *   - \ref E_OK,	Control device successfully
+ *   - \ref E_CLSED,	Device is not opened
+ *   - \ref E_OBJ,	Device object is not valid or not exists
+ *   - \ref E_PAR,	Parameter is not valid for current control command
+ *   - \ref E_SYS,	Control device failed, due to hardware issues such as device is disabled
+ *   - \ref E_NOSPT,	Control command is not supported or not valid
+ * @{
+ */
+/**
+ * Set the \ref dev_gpio_info::direction "direction" of masked bits of gpio port into \ref GPIO_DIR_INPUT "input"
+ * - Param type : uint32_t
+ * - Param usage : 1 in each bit will be masked.
+ * - Return value explanation :
+ */
+#define GPIO_CMD_SET_BIT_DIR_INPUT			DEV_SET_SYSCMD(0)
+/**
+ * Set the \ref dev_gpio_info::direction "direction" of masked bits of gpio port into \ref GPIO_DIR_OUTPUT "output"
+ * - Param type : uint32_t
+ * - Param usage : 1 in each bit will be masked.
+ * - Return value explanation :
+ */
+#define GPIO_CMD_SET_BIT_DIR_OUTPUT			DEV_SET_SYSCMD(1)
+/**
+ * Get \ref dev_gpio_info::direction "gpio port direction".
+ * - Param type : uint32_t
+ * - Param usage : 1 bit for 1 bit of gpio port, 0 for input, 1 for output
+ * - Return value explanation :
+ */
+#define GPIO_CMD_GET_BIT_DIR				DEV_SET_SYSCMD(2)
+/**
+ * Set gpio interrupt configuration for each bit.
+ * - Param type : \ref DEV_GPIO_INT_CFG *
+ * - Param usage : store gpio interrupt configuration for each bit.
+ * - Return value explanation :
+ */
+#define GPIO_CMD_SET_BIT_INT_CFG			DEV_SET_SYSCMD(3)
+/**
+ * Get gpio interrupt configuration for each bit.
+ * - Param type : \ref DEV_GPIO_INT_CFG *
+ * - Param usage : First set int_bit_mask in DEV_GPIO_INT_CFG structure to
+ * the mask of which bit of GPIO you want to get. And the interrupt configuration
+ * will be stored in the structure DEV_GPIO_INT_CFG, each bit stand for each bit of port.
+ * - Return value explanation :
+ */
+#define GPIO_CMD_GET_BIT_INT_CFG			DEV_SET_SYSCMD(4)
+/**
+ * Set gpio service routine for each bit.
+ * - Param type : \ref DEV_GPIO_BIT_ISR *
+ * - Param usage : store gpio handler information for each bit, int handler's param will be DEV_GPIO *.
+ * - Return value explanation :
+ */
+#define GPIO_CMD_SET_BIT_ISR				DEV_SET_SYSCMD(5)
+/**
+ * Get gpio service routine for each bit.
+ * - Param type : \ref DEV_GPIO_BIT_ISR *
+ * - Param usage : By passing int_bit_ofs in DEV_GPIO_BIT_ISR,
+ * it will return interrupt handler for this bit and store it in int_bit_handler.
+ * - Return value explanation :
+ */
+#define GPIO_CMD_GET_BIT_ISR				DEV_SET_SYSCMD(6)
+/**
+ * Enable gpio interrupt of the masked bits.
+ * - Param type : uint32_t
+ * - Param usage : 1 in each bit will be masked.
+ * - Return value explanation :
+ */
+#define GPIO_CMD_ENA_BIT_INT				DEV_SET_SYSCMD(7)
+/**
+ * Disable gpio interrupt of the masked bits.
+ * - Param type : uint32_t
+ * - Param usage : 1 in each bit will be masked.
+ * - Return value explanation :
+ */
+#define GPIO_CMD_DIS_BIT_INT				DEV_SET_SYSCMD(8)
+/**
+ * Get \ref dev_gpio_info::method "gpio interrupt enable status".
+ * - Param type : uint32_t *
+ * - Param usage : 1 bit for 1 bit of gpio port, 0 for poll, 1 for interrupt
+ * - Return value explanation :
+ */
+#define GPIO_CMD_GET_BIT_MTHD				DEV_SET_SYSCMD(9)
+/* @} */
+
+/**
+ * \defgroup	DEVICE_HAL_GPIO_INT_CFG_SET	GPIO Device Int Configuration Settings
+ * \ingroup	DEVICE_HAL_GPIO
+ * \brief	definition of gpio interrupt type
+ * @{
+ */
+
+/* GPIO Mask Defintions */
+/** Mask none bits of the max 32bits */
+#define GPIO_BITS_MASK_NONE			(0)
+/** Mask all bits of the max 32bits */
+#define GPIO_BITS_MASK_ALL			(0XFFFFFFFF)
+
+/* GPIO Interrupt Type Related Definitions */
+
+/** Level sensitive interrupt type for 1 bit */
+#define GPIO_INT_LEVEL_TRIG			(0)
+/** Edge sensitive interrupt type for 1 bit */
+#define GPIO_INT_EDGE_TRIG			(1)
+/** Level sensitive interrupt type for all 32 bits */
+#define GPIO_INT_LEVEL_TRIG_ALL			(0)
+/** Edge sensitive interrupt type for all 32 bits */
+#define GPIO_INT_EDGE_TRIG_ALL			(0XFFFFFFFF)
+
+/* For bit settings */
+/** Set bit interrupt type of gpio into level sensitive */
+#define GPIO_INT_BIT_LEVEL_TRIG(bit_ofs)	(GPIO_INT_LEVEL_TRIG<<(bit_ofs))
+/** Set bit interrupt type of gpio into edge sensitive */
+#define GPIO_INT_BIT_EDGE_TRIG(bit_ofs)		(GPIO_INT_EDGE_TRIG<<(bit_ofs))
+/* For bits settings */
+/** Set interrupt type of masked bits of gpio into level sensitive */
+#define GPIO_INT_BITS_LEVEL_TRIG(bit_mask)	(GPIO_INT_LEVEL_TRIG_ALL&(bit_mask))
+/** Set bit interrupt type of gpio into edge sensitive */
+#define GPIO_INT_BITS_EDGE_TRIG(bit_mask)	(GPIO_INT_EDGE_TRIG_ALL&(bit_mask))
+
+/* GPIO Interrupt Polarity Related Definitions */
+
+/** GPIO Interrupt polarity type enum */
+typedef enum gpio_int_polarity {
+	/* Polarity for 1 bit */
+	GPIO_INT_ACTIVE_LOW   = 0, /*!< Active low for level-sensitive interrupt for 1 bit */
+	GPIO_INT_FALLING_EDGE = 0, /*!< Falling-edge for edge-sensitive interrupt for 1 bit */
+	GPIO_INT_ACTIVE_HIGH =  1, /*!< Active high for level-sensitive interrupt for 1 bit */
+	GPIO_INI_RISING_EDGE = 1, /*!< Rising-edge for edge-sensitive interrupt for 1 bit */
+	/* Polartiy for all 32 bits */
+	GPIO_INT_ACTIVE_LOW_ALL   = 0, /*!< Active low for level-sensitive interrupt for all bits */
+	GPIO_INT_FALLING_EDGE_ALL = 0, /*!< Falling-edge for edge-sensitive interrupt for all bits */
+	GPIO_INT_ACTIVE_HIGH_ALL =  0XFFFFFFFF, /*!< Active high for level-sensitive interrupt for all bits */
+	GPIO_INI_RISING_EDGE_ALL = 0XFFFFFFFF /*!< Rising-edge for edge-sensitive interrupt for all bits */
+} GPIO_INT_POLARITY;
+
+/* For bit settings */
+/** Set bit polarity of gpio into active low */
+#define GPIO_INT_BIT_POL_ACT_LOW(bit_ofs)	(GPIO_INT_ACTIVE_LOW<<(bit_ofs))
+/** Set bit polarity of gpio into active high */
+#define GPIO_INT_BIT_POL_ACT_HIGH(bit_ofs)	(GPIO_INT_ACTIVE_HIGH<<(bit_ofs))
+/** Set bit polarity of gpio into falling edge */
+#define GPIO_INT_BIT_POL_FALL_EDGE(bit_ofs)	(GPIO_INT_FALLING_EDGE<<(bit_ofs))
+/** Set bit polarity of gpio into rising edge */
+#define GPIO_INT_BIT_POL_RISE_EDGE(bit_ofs)	(GPIO_INI_RISING_EDGE<<(bit_ofs))
+
+/* For bits settings */
+/** Set polarity of masked bits of gpio into active low */
+#define GPIO_INT_BITS_POL_ACT_LOW(bit_mask)	(GPIO_INT_ACTIVE_LOW_ALL&(bit_mask))
+/** Set polarity of masked bits of gpio into active high */
+#define GPIO_INT_BITS_POL_ACT_HIGH(bit_mask)	(GPIO_INT_ACTIVE_HIGH_ALL&(bit_mask))
+/** Set polarity of masked bits of gpio into falling edge */
+#define GPIO_INT_BITS_POL_FALL_EDGE(bit_mask)	(GPIO_INT_FALLING_EDGE_ALL&(bit_mask))
+/** Set polarity of masked bits of gpio into rising edge */
+#define GPIO_INT_BITS_POL_RISE_EDGE(bit_mask)	(GPIO_INI_RISING_EDGE_ALL&(bit_mask))
+
+/* GPIO Interrupt Debounce Related Definitions */
+
+/* For bit settings */
+/** Disable debounce circuitry for 1 bit */
+#define GPIO_INT_NO_DEBOUNCE			(0)
+/** Enable debounce circuitry for 1 bit */
+#define GPIO_INT_DEBOUNCE			(1)
+
+/* For bits settings */
+/** Disable debounce circuitry for all bits */
+#define GPIO_INT_NO_DEBOUNCE_ALL		(0)
+/** Enable debounce circuitry for all bits */
+#define GPIO_INT_DEBOUNCE_ALL			(0XFFFFFFFF)
+
+/* For bit settings */
+/** Set bit interrupt debounce of gpio into enabled */
+#define GPIO_INT_BIT_ENA_DEBOUNCE(bit_ofs)	(GPIO_INT_DEBOUNCE<<(bit_ofs))
+/** Set bit interrupt debounce of gpio into disabled */
+#define GPIO_INT_BIT_DIS_DEBOUNCE(bit_ofs)	(GPIO_INT_NO_DEBOUNCE<<(bit_ofs))
+/* For bits settings */
+/** Set bit interrupt debounce of gpio into enabled */
+#define GPIO_INT_BITS_ENA_DEBOUNCE(bit_mask)	(GPIO_INT_DEBOUNCE_ALL&(bit_mask))
+/** Set bit interrupt debounce of gpio into disabled */
+#define GPIO_INT_BITS_DIS_DEBOUNCE(bit_mask)	(GPIO_INT_NO_DEBOUNCE_ALL&(bit_mask))
+
+/** GPIO interrupt configuration */
+typedef struct dev_gpio_int_cfg {
+	uint32_t int_bit_mask;		/*!< interrupt bit mask for gpio */
+	uint32_t int_bit_type;		/*!< \ref GPIO_INT_LEVEL_TRIG "level sensitive" or \ref GPIO_INT_EDGE_TRIG "edge sensitive" for each gpio bit */
+	uint32_t int_bit_polarity;	/*!< active high or low, refer to \ref GPIO_INT_POLARITY for each gpio bit */
+	uint32_t int_bit_debounce;	/*!< \ref GPIO_INT_DEBOUNCE "enable" or \ref GPIO_INT_NO_DEBOUNCE "disable" debounce logic for each gpio bit */
+} DEV_GPIO_INT_CFG, * DEV_GPIO_INT_CFG_PTR;
+
+/** Default interrupt configuration for all gpio bits */
+static const DEV_GPIO_INT_CFG gpio_int_cfg_default = \
+	{GPIO_BITS_MASK_ALL, GPIO_INT_LEVEL_TRIG_ALL, \
+		GPIO_INT_ACTIVE_LOW_ALL, GPIO_INT_NO_DEBOUNCE_ALL};
+
+/** GPIO interrupt handler or Interrupt Service Routine(ISR) */
+typedef void (*DEV_GPIO_HANDLER) (void *ptr);
+
+/** interrupt handler for each port bit */
+typedef struct dev_gpio_bit_isr {
+	uint32_t int_bit_ofs;			/*!< int bit offset */
+	DEV_GPIO_HANDLER int_bit_handler;	/*!< interrupt handler */
+} DEV_GPIO_BIT_ISR, * DEV_GPIO_BIT_ISR_PTR;
+/* @} */
+
+/**
+ * \defgroup	DEVICE_HAL_GPIO_DEVSTRUCT	GPIO Device Interface Definition
+ * \ingroup	DEVICE_HAL_GPIO
+ * \brief	contains definitions of gpio device structure.
+ * \details	This structure will be used in user implemented code, which was called
+ *     \ref DEVICE_IMPL "Device Driver Implement Layer" for gpio to use in implementation code.
+ *     Application developer should use the GPIO API provided here to access to GPIO devices.
+ *     BSP developer should follow the API definition to implement GPIO device drivers.
+ * @{
+ */
+/**
+ * \brief	gpio information struct definition
+ * \details	informations about gpio open count, working status
+ * 	gpio registers and control block, gpio io direction and interrupt/poll for each bit of gpio
+ * \note	Only available for gpio with max 32bits
+ */
+typedef struct dev_gpio_info {
+	void *gpio_ctrl;	/*!< gpio control related pointer, implemented by bsp developer, and this should be set during gpio object implementation */
+	uint32_t opn_cnt;	/*!< gpio open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */
+	uint32_t direction;	/*!< each bit direction of this GPIO, default all \ref GPIO_DIR_INPUT "input" for first open */
+	uint32_t method;	/*!< int/poll method for each bit of GPIO, 0 for poll, 1 for interrupt, default all \ref DEV_POLL_METHOD "poll" for first open */
+	void * extra;		/*!< a extra pointer to get hook to applications which should not used by bsp developer,
+					this should be NULL for first open and you can \ref DEV_GPIO_INFO_SET_EXTRA_OBJECT "set"
+					or \ref DEV_GPIO_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */
+} DEV_GPIO_INFO, * DEV_GPIO_INFO_PTR;
+/** Set extra information pointer of gpio info */
+#define DEV_GPIO_INFO_SET_EXTRA_OBJECT(gpio_info_ptr, extra_info)	(gpio_info_ptr)->extra = (void *)(extra_info)
+/** Get extra information pointer of gpio info */
+#define DEV_GPIO_INFO_GET_EXTRA_OBJECT(gpio_info_ptr)			((gpio_info_ptr)->extra)
+
+/** Method of all gpio bits set to poll */
+#define DEV_GPIO_BITS_MTHD_POLL			(0)
+/** Method of all gpio bits set to interrupt */
+#define DEV_GPIO_BITS_MTHD_INTERRUPT		(0xFFFFFFFF)
+/** Default method of all gpio bits should be poll for first open */
+#define DEV_GPIO_BITS_MTHD_DEFAULT		(DEV_GPIO_BITS_MTHD_POLL)
+
+/**
+ * \brief	gpio device interface definition
+ * \details	define gpio device interface, like gpio information structure,
+ * 	fuctions to open/close/control gpio, write or read data via gpio
+ * \note	all this details are implemented by user in user porting code
+ */
+typedef struct dev_gpio {
+	DEV_GPIO_INFO gpio_info;		/*!< gpio device information */
+	int32_t (*gpio_open) (uint32_t dir);	/*!< open gpio device with pre-defined gpio direction */
+	int32_t (*gpio_close) (void);		/*!< close gpio device */
+	int32_t (*gpio_control) (uint32_t ctrl_cmd, void *param);	/*!< control gpio device */
+	int32_t (*gpio_write) (uint32_t val, uint32_t mask);	/*!< write gpio device with val, only write the masked bits */
+	int32_t (*gpio_read) (uint32_t *val, uint32_t mask);	/*!< read gpio device val, only read the masked bits */
+} DEV_GPIO, * DEV_GPIO_PTR;
+
+/**
+ * \fn		int32_t (* dev_gpio::gpio_open) (uint32_t dir)
+ * \details	Open a gpio device with pre-defined io direction.
+ * \param[in]	dir	gpio direction for each bit
+ * \retval	E_OK	Open successfully without any issues
+ * \retval	E_OPNED	If device was opened before with different parameters,
+ *			then just increase the \ref dev_gpio_info::opn_cnt "opn_cnt" and return \ref E_OPNED
+ * \retval	E_OBJ	Device object is not valid
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_NOSPT	Open settings are not supported
+ */
+
+/**
+ * \fn		int32_t (* dev_gpio::gpio_close) (void)
+ * \details	Close an gpio device, just decrease the \ref dev_gpio_info::opn_cnt "opn_cnt",
+ *      if \ref dev_gpio_info::opn_cnt "opn_cnt" equals 0, then close the device
+ * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
+ * \retval	E_OPNED	Device is still opened, the device \ref dev_gpio_info::opn_cnt "opn_cnt" decreased by 1
+ * \retval	E_OBJ	Device object is not valid
+ */
+
+/**
+ * \fn		int32_t (* dev_gpio::gpio_control) (uint32_t ctrl_cmd, void *param)
+ * \details	Control an gpio device by \ref ctrl_cmd, with passed \ref param.
+ * 	you can control gpio device using predefined gpio control commands defined using \ref DEV_SET_SYSCMD
+ * 	(which must be implemented by bsp developer), such as \ref GPIO_CMD_SET_BIT_DIR_INPUT
+ * 	"change masked gpio direction to input", and \ref DEVICE_HAL_GPIO_CTRLCMD "more".
+ * 	And you can also control gpio device using your own specified commands defined using \ref DEV_SET_USRCMD,
+ * 	but these specified commands should be defined in your own gpio device driver implementation.
+ * \param[in]		ctrl_cmd	\ref DEVICE_HAL_GPIO_CTRLCMD "control command", to change or get some thing related to gpio
+ * \param[in,out]	param		parameters that maybe argument of the command, or return values of the command
+ * \retval	E_OK	Control device successfully
+ * \retval	E_CLSED	Device is not opened
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Control device failed, due to hardware issues
+ * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
+ * \retval	E_NOSPT	Control command is not supported or not valid, such as interrupt is not supported
+ */
+
+/**
+ * \fn		int32_t (* dev_gpio::gpio_write) (uint32_t val, uint32_t mask)
+ * \details	Write gpio with \ref val, and only change the masked bits of gpio.
+ * \param[in]	val	the data that need to write to gpio
+ * \param[in]	mask	gpio bit mask
+ * \retval	E_OK	Write gpio with specified value successfully
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid
+ */
+
+/**
+ * \fn		int32_t (* dev_gpio::gpio_read) (uint32_t *val, uint32_t mask)
+ * \details	Read the masked gpio value
+ * \param[out]	val	pointer to data need to read from gpio
+ * \param[in]	mask	gpio bit mask
+ * \retval	E_OK	Read gpio data successfully
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid
+ */
+
+/** @} */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief	get an \ref dev_gpio "gpio device" by gpio device id.
+ * 	For how to use gpio device hal refer to \ref dev_gpio "Functions in gpio device structure"
+ * \param[in]	gpio_id	id of gpio, defined by user
+ * \retval	!NULL	pointer to an \ref dev_gpio "gpio device structure"
+ * \retval	NULL	failed to find the gpio device by \ref gpio_id
+ * \note	need to implemented by user in user code
+ */
+extern DEV_GPIO_PTR gpio_get_dev(int32_t gpio_id);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif /* _DEVICE_HAL_GPIO_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h
new file mode 100644
index 0000000000..14106671ff
--- /dev/null
+++ b/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h
@@ -0,0 +1,526 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-06-16
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_HAL_IIC	IIC Device HAL Interface
+ * \ingroup	DEVICE_HAL_DEF
+ * \brief	definitions for iic device hardware layer (\ref dev_iic.h)
+ * \details	provide interfaces for iic driver to implement
+ *  Here is a diagram for the iic interface.
+ *
+ *  \htmlonly
+ *  <div class="imagebox">
+ *      <div style="width: 600px">
+ *          <img src="pic/dev_iic_hal.jpg" alt="IIC Device HAL Interface Diagram"/>
+ *          <p>IIC Device HAL Interface Diagram</p>
+ *      </div>
+ *  </div>
+ *  \endhtmlonly
+ *
+ * @{
+ *
+ * \file
+ * \brief	iic device hardware layer definitions
+ * \details	provide common definitions for iic device,
+ * 	then software developer can develop iic driver
+ * 	following this definitions, and the applications
+ * 	can directly call this definition to realize functions
+ */
+
+#ifndef _DEVICE_HAL_IIC_H_
+#define _DEVICE_HAL_IIC_H_
+
+#include "device/device_hal/inc/dev_common.h"
+
+/**
+ * \defgroup	DEVICE_HAL_IIC_CFG	IIC Related Configurations
+ * \ingroup	DEVICE_HAL_IIC
+ * \brief	Macros for IIC device related configurations.
+ * @{
+ */
+/** IIC Bus possible speed modes */
+typedef enum iic_speed_mode {
+	IIC_SPEED_STANDARD = 0,	/*!< Bidirectional, Standard-mode (Sm), with a bit rate up to 100 kbit/s */
+	IIC_SPEED_FAST     = 1,	/*!< Bidirectional, Fast-mode (Fm), with a bit rate up to 400 kbit/s */
+	IIC_SPEED_FASTPLUS = 2,	/*!< Bidirectional, Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s */
+	IIC_SPEED_HIGH     = 3,	/*!< Bidirectional, High-speed mode (Hs-mode), with a bit rate up to 3.4 Mbit/s */
+	IIC_SPEED_ULTRA    = 4	/*!< Unidirectional(Write only), Ultra Fast-mode (UFm), with a bit rate up to 5 Mbit/s */
+} IIC_SPEED_MODE;
+
+/** IIC next Condition */
+typedef enum iic_next_condtion {
+	IIC_MODE_STOP    = 0,	/*!< Send a STOP condition after write/read operation */
+	IIC_MODE_RESTART = 1	/*!< Send a RESTART condition after write/read operation */
+} IIC_NEXT_CONDTION;
+
+/** IIC Error State */
+typedef enum iic_error_state {
+	IIC_ERR_NONE       = 0,	/*!< Currently in iic device free state */
+	IIC_ERR_LOST_BUS   = 1,	/*!< Master or slave lost bus during operation */
+	IIC_ERR_ADDR_NOACK = 2,	/*!< Slave address is sent but not addressed by any slave devices */
+	IIC_ERR_DATA_NOACK = 3,	/*!< Data in transfer is not acked when it should be acked */
+	IIC_ERR_TIMEOUT    = 4,	/*!< Transfer timeout, no more data is received or sent */
+	IIC_ERR_MSTSTOP    = 5,	/*!< Slave received a STOP condition from master device */
+	IIC_ERR_UNDEF      = 6	/*!< Undefined error cases */
+} IIC_ERROR_STATE;
+
+/** IIC Working State */
+typedef enum iic_working_state {
+	IIC_FREE  = 0,	/*!< Currently in iic device free state */
+	IIC_IN_TX = 1,	/*!< Currently in iic master transmit state */
+	IIC_IN_RX = 2	/*!< Currently in iic master receive state */
+} IIC_WORKING_STATE;
+
+/** IIC Addressing Mode */
+typedef enum iic_address_mode {
+	IIC_7BIT_ADDRESS  = 0,	/*!< Use 7bit address mode */
+	IIC_10BIT_ADDRESS = 1	/*!< Use 10bit address mode */
+} IIC_ADDRESS_MODE;
+
+/** IIC Slave State */
+typedef enum iic_slave_state {
+	IIC_SLAVE_STATE_FREE     = 0,		/*!< None state, in free */
+	IIC_SLAVE_STATE_START    = (1<<1),	/*!< Start or Restart condition, clear it when read */
+	IIC_SLAVE_STATE_STOP     = (1<<2),	/*!< Stop condition, clear it when read */
+	IIC_SLAVE_STATE_RD_REQ   = (1<<3),	/*!< Read request from master, this will trigger the slave transmit callback */
+	IIC_SLAVE_STATE_RD_DONE  = (1<<4),	/*!< Read request done from master, clear it when read */
+	IIC_SLAVE_STATE_WR_REQ   = (1<<5),	/*!< Write request from master, this will trigger the slave receive callback */
+	IIC_SLAVE_STATE_GC_REQ   = (1<<6),	/*!< General call request from master */
+	IIC_SLAVE_STATE_ERROR    = (1<<7)	/*!< Error, clear it when read */
+} IIC_SLAVE_STATE;
+
+/** 7bit IIC address mask */
+#define IIC_7BIT_ADDRESS_MASK		(0x7F)
+/** 10bit IIC address mask */
+#define IIC_10BIT_ADDRESS_MASK		(0x3FF)
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_IIC_CTRLCMD		IIC Device Control Commands
+ * \ingroup	DEVICE_HAL_IIC
+ * \brief	Definitions for iic control command, used in \ref dev_iic::iic_control "IIC IO Control"
+ * \details	These commands defined here can be used in user code directly.
+ * - Parameters Usage
+ *   - For passing parameters like integer, just use uint32_t/int32_t to directly pass values
+ *   - For passing parameters for a structure, please use pointer to pass values
+ *   - For getting some data, please use pointer to store the return data
+ * - Common Return Values
+ *   - \ref E_OK,	Control device successfully
+ *   - \ref E_CLSED,	Device is not opened
+ *   - \ref E_OBJ,	Device object is not valid or not exists
+ *   - \ref E_PAR,	Parameter is not valid for current control command
+ *   - \ref E_SYS,	Control device failed, due to hardware issues such as device is disabled
+ *   - \ref E_CTX,	Control device failed, due to different reasons like in transfer state
+ *   - \ref E_NOSPT,	Control command is not supported or not valid
+ * @{
+ */
+
+/** Define IIC control commands for common usage */
+#define DEV_SET_IIC_SYSCMD(cmd)		DEV_SET_SYSCMD((cmd))
+/** Define IIC control commands for master usage */
+#define DEV_SET_IIC_MST_SYSCMD(cmd)	DEV_SET_SYSCMD(0x00004000|(cmd))
+/** Define IIC control commands for slave usage */
+#define DEV_SET_IIC_SLV_SYSCMD(cmd)	DEV_SET_SYSCMD(0x00008000|(cmd))
+
+/* ++++ Common commands for IIC Device ++++ */
+/**
+ * Get \ref dev_iic_info::status "current device status"
+ * - Param type : uint32_t *
+ * - Param usage : store result of current status
+ * - Return value explanation :
+ */
+#define IIC_CMD_GET_STATUS			DEV_SET_IIC_SYSCMD(0)
+/**
+ * Set \ref dev_iic_info::addr_mode "iic addressing mode".
+ * - Param type : uint32_t
+ * - Param usage : iic addressing mode, possible values can be found \ref IIC_ADDRESS_MODE "here"
+ * - Return value explanation :
+ */
+#define IIC_CMD_SET_ADDR_MODE			DEV_SET_IIC_SYSCMD(1)
+/**
+ * Set \ref dev_iic_cbs::tx_cb "iic transmit success callback" function
+ * when all required bytes are transmitted for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : transmit success callback function for iic
+ * - Return value explanation :
+ */
+#define IIC_CMD_SET_TXCB			DEV_SET_IIC_SYSCMD(2)
+/**
+ * Set \ref dev_iic_cbs::rx_cb "iic receive success callback" function
+ * when all required bytes are received for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : receive success callback function for iic
+ * - Return value explanation :
+ */
+#define IIC_CMD_SET_RXCB			DEV_SET_IIC_SYSCMD(3)
+/**
+ * Set \ref dev_iic_cbs::err_cb "iic transfer error callback" function
+ * when something error happened for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : transfer error callback function for iic
+ * - Return value explanation :
+ */
+#define IIC_CMD_SET_ERRCB			DEV_SET_IIC_SYSCMD(4)
+/**
+ * Set buffer for interrupt transmit, and it will set \ref dev_iic_info::tx_buf "tx_buf".
+ * - IIC master mode use case  \n
+ *    For master mode, if you set tx buffer to NULL, when tx interrupt is enabled and entered into tx interrupt,
+ * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the
+ * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt
+ * and call tx callback function if available.
+ * - IIC slave mode use case   \n
+ *    For slave mode, the tx buffer is not used, only tx callback function is used, and if tx callback is not set,
+ * then it will automatically disable the tx interrupt, if tx callback is set, it will call the tx callback function
+ * and you need to write or read in the tx callback function, to avoid meaningless waiting, you can use control command
+ * \ref IIC_CMD_GET_TXAVAIL to get how many bytes space existing in transmit fifo, and use iic_write to send the available
+ * bytes.
+ * - Param type : DEV_BUFFER * or NULL
+ * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL
+ * - Return value explanation :
+ */
+#define IIC_CMD_SET_TXINT_BUF			DEV_SET_IIC_SYSCMD(5)
+/**
+ * Set buffer for interrupt receive, and it will set \ref dev_iic_info::rx_buf "rx_buf"
+ * - IIC master mode use case  \n
+ *   Similar to \ref IIC_CMD_SET_TXINT_BUF
+ * - IIC slave mode use case   \n
+ *   Similiar to \ref IIC_CMD_SET_TXINT_BUF
+ * - Param type : DEV_BUFFER * or NULL
+ * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL
+ * - Return value explanation :
+ */
+#define IIC_CMD_SET_RXINT_BUF			DEV_SET_IIC_SYSCMD(6)
+/**
+ * Enable or disable transmit interrupt,
+ * for master mode, only one of tx and rx interrupt can be enabled,
+ * if tx interrupt is enabled, then rx interrupt can't be changed.
+ * - Param type : uint32_t
+ * - Param usage : enable(none-zero) or disable(zero) flag
+ * - Return value explanation :
+ */
+#define IIC_CMD_SET_TXINT			DEV_SET_IIC_SYSCMD(7)
+/**
+ * Enable or disable receive interrupt,
+ * for master mode, only one of tx and rx interrupt can be enabled,
+ * if rx interrupt is enabled, then tx interrupt can't be changed.
+ * - Param type : uint32_t
+ * - Param usage : enable(none-zero) or disable(zero) flag
+ * - Return value explanation :
+ */
+#define IIC_CMD_SET_RXINT			DEV_SET_IIC_SYSCMD(8)
+/**
+ * Abort current interrupt transmit operation if tx interrupt enabled,
+ * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT
+ * in \ref dev_iic_info::status "status" variable,
+ * and call the transmit callback function, when tx callback is finished,
+ * it will clear \ref DEV_IN_TX_ABRT and return
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define IIC_CMD_ABORT_TX			DEV_SET_IIC_SYSCMD(9)
+/**
+ * Abort current interrupt receive operation if rx interrupt enabled,
+ * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT
+ * in \ref dev_iic_info::status "status" variable,
+ * and call the receive callback function, when rx callback is finished,
+ * it will clear \ref DEV_IN_TX_ABRT and return
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define IIC_CMD_ABORT_RX			DEV_SET_IIC_SYSCMD(10)
+/**
+ * Do a software reset for IIC device, it will stop current transfer,
+ * and clear error state and bring device to normal state, set next condition to STOP
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define IIC_CMD_RESET				DEV_SET_IIC_SYSCMD(11)
+/**
+ * Flush iic device transmit buffer or fifo
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define IIC_CMD_FLUSH_TX			DEV_SET_IIC_SYSCMD(12)
+/**
+ * Flush iic device receive buffer or fifo
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define IIC_CMD_FLUSH_RX			DEV_SET_IIC_SYSCMD(13)
+/**
+ * Enable iic device
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define IIC_CMD_ENA_DEV				DEV_SET_IIC_SYSCMD(14)
+/**
+ * Disable iic device, when device is disabled,
+ * only \ref IIC_CMD_ENA_DEV, \ref IIC_CMD_DIS_DEV,
+ * \ref IIC_CMD_GET_STATUS and \ref IIC_CMD_RESET
+ * commands can be executed, other commands will return \ref E_SYS
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define IIC_CMD_DIS_DEV				DEV_SET_IIC_SYSCMD(15)
+/**
+ * Get how many bytes space in iic are available to transmit,
+ * this can be used in interrupt callback functions,
+ * cooperate with \ref dev_iic::iic_write "iic_write" API to realize non-blocked write
+ * - Param type : int32_t *
+ * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available
+ * - Return value explaination :
+ */
+#define IIC_CMD_GET_TXAVAIL			DEV_SET_IIC_SYSCMD(16)
+/**
+ * Get how many bytes in iic are available to receive,
+ * this can be used in interrupt callback functions,
+ * cooperate with \ref dev_iic::iic_read "iic_read" API to realize non-blocked read
+ * - Param type : int32_t *
+ * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available
+ * - Return value explanation :
+ */
+#define IIC_CMD_GET_RXAVAIL			DEV_SET_IIC_SYSCMD(17)
+
+/* ++++ Master only commands for IIC Device ++++ */
+/**
+ * Set \ref dev_iic_info::speed_mode "iic speed mode".
+ * - Param type : uint32_t
+ * - Param usage : iic speed mode, possible values can be found \ref IIC_SPEED_MODE "here",
+ * and if passing mode is not supported, it will choose a lower supported speed mode
+ * - Return value explanation :
+ */
+#define IIC_CMD_MST_SET_SPEED_MODE		DEV_SET_IIC_MST_SYSCMD(0)
+/**
+ * Set next condition for following transmit or receive operation.
+ * For example, you can change next condition before iic_read or iic_write,
+ * then in iic_read/iic_write operation, it will send a STOP/RESTART condition
+ * after the last byte of this operation. For interrupt, this is similar.
+ * - Param type : uint32_t
+ * - Param usage : next condition can be \ref IIC_NEXT_CONDTION
+ * - Return value explanation :
+ */
+#define IIC_CMD_MST_SET_NEXT_COND		DEV_SET_IIC_MST_SYSCMD(1)
+/**
+ * Set target slave device address for selecting slave device
+ * - Param type : uint32_t
+ * - Param usage : target slave address value
+ * - Return value explanation :
+ */
+#define IIC_CMD_MST_SET_TAR_ADDR		DEV_SET_IIC_MST_SYSCMD(2)
+
+
+/* ++++ Slave only commands for IIC Device ++++ */
+/**
+ * Set slave address when working as slave iic device
+ * - Param type : uint32_t
+ * - Param usage : slave address value
+ * - Return value explanation :
+ */
+#define IIC_CMD_SLV_SET_SLV_ADDR		DEV_SET_IIC_SLV_SYSCMD(0)
+/**
+ * Get \ref iic_slave_state "slave state" when working as slave iic device
+ * - Param type : uint32_t *
+ * - Param usage : slave state
+ * - Return value explanation :
+ */
+#define IIC_CMD_SLV_GET_SLV_STATE		DEV_SET_IIC_SLV_SYSCMD(1)
+
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_IIC_CALLBACK	IIC Interrupt callback functions
+ * \ingroup	DEVICE_HAL_IIC
+ * \brief	callback function structure for IIC device
+ * @{
+ */
+typedef struct dev_iic_cbs {
+	DEV_CALLBACK tx_cb;	/*!< iic data transmit success required bytes callback */
+	DEV_CALLBACK rx_cb;	/*!< iic data receive success required bytes callback */
+	DEV_CALLBACK err_cb;	/*!< iic error callback */
+} DEV_IIC_CBS, *DEV_IIC_CBS_PTR;
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_IIC_DEVSTRUCT	IIC Device Structure
+ * \ingroup	DEVICE_HAL_IIC
+ * \brief	contains definitions of iic device structure.
+ * \details	this structure will be used in user implemented code, which was called
+ *     Device Driver Implement Layer for iic to realize in user code.
+ * @{
+ */
+/**
+ * \brief	iic information struct definition
+ * \details	informations about iic open state, working state,
+ * 	baurate, iic registers, working method, interrupt number
+ */
+typedef struct dev_iic_info {
+	void *iic_ctrl;		/*!< iic control related pointer, implemented by bsp developer, and this should be set during iic object implementation */
+	uint32_t opn_cnt;	/*!< iic open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */
+	uint32_t status;	/*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */
+	uint32_t mode;		/*!< current working mode, which can be \ref DEV_MASTER_MODE "master mode" or \ref DEV_SLAVE_MODE "slave mode" */
+	uint32_t speed_mode;	/*!< current working \ref IIC_SPEED_MODE "iic speed mode" */
+	uint32_t cur_state;	/*!< \ref IIC_WORKING_STATE "current working state for iic device", this should be \ref IIC_FREE for first open */
+	uint32_t err_state;	/*!< \ref IIC_ERROR_STATE "current error state for iic device", this should be \ref IIC_ERR_NONE for first open */
+	uint32_t addr_mode;	/*!< \ref IIC_ADDRESS_MODE "current addressing mode", this should be \ref IIC_7BIT_ADDRESS for first open */
+	uint32_t slv_addr;	/*!< slave address when working as slave iic device, this should be 0 for first open */
+	uint32_t tar_addr;	/*!< target slave device address when addressing that slave device, this should be 0 for first open */
+	uint32_t next_cond;	/*!< \ref IIC_NEXT_CONDTION "next condition for master transmit or receive", \
+					possible values are STOP or RESTART, it should be STOP for first open */
+	DEV_BUFFER tx_buf;	/*!< transmit buffer via interrupt, this should be all zero for first open */
+	DEV_BUFFER rx_buf;	/*!< receive buffer via interrupt, this should be all zero for first open */
+	DEV_IIC_CBS iic_cbs;	/*!< iic callbacks, for both master and slave mode, this should be all NULL for first open */
+	void *extra;		/*!< a extra pointer to get hook to applications which should not used by bsp developer,
+					this should be NULL for first open and you can \ref DEV_IIC_INFO_SET_EXTRA_OBJECT "set"
+					or \ref DEV_IIC_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */
+} DEV_IIC_INFO, * DEV_IIC_INFO_PTR;
+
+/** Set extra information pointer of iic info */
+#define DEV_IIC_INFO_SET_EXTRA_OBJECT(iic_info_ptr, extra_info)		(iic_info_ptr)->extra = (void *)(extra_info)
+/** Get extra information pointer of iic info */
+#define DEV_IIC_INFO_GET_EXTRA_OBJECT(iic_info_ptr)			((iic_info_ptr)->extra)
+
+/**
+ * \brief	iic device interface definition
+ * \details	define iic device interface, like iic information structure,
+ * 	fuctions to get iic info, open/close/control iic, send/receive data by iic
+ * \note	all this details are implemented by user in user porting code
+ */
+typedef struct dev_iic {
+	DEV_IIC_INFO iic_info;					/*!< iic device information */
+	int32_t (*iic_open) (uint32_t mode, uint32_t param);	/*!< open iic device in master/slave mode, \
+									when in master mode, param stands for speed mode, \
+									when in slave mode, param stands for slave address */
+	int32_t (*iic_close) (void);				/*!< close iic device */
+	int32_t (*iic_control) (uint32_t ctrl_cmd, void *param);/*!< control iic device */
+	int32_t (*iic_write) (const void *data, uint32_t len);	/*!< send data by iic device (blocking method) */
+	int32_t (*iic_read) (void *data, uint32_t len);		/*!< read data from iic device (blocking method) */
+} DEV_IIC, * DEV_IIC_PTR;
+
+/**
+ * \fn		int32_t (* dev_iic::iic_open) (uint32_t mode, uint32_t param)
+ * \details	open an iic device with selected mode (master or slave) with defined \ref param
+ * \param[in]	mode	working mode (\ref DEV_MASTER_MODE "master" or \ref DEV_SLAVE_MODE "slave")
+ * \param[in]	param	When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_iic_info::speed_mode "speed mode",
+ * 			when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_iic_info::slv_addr "slave device 7bit address"
+ * \retval	E_OK	Open successfully without any issues
+ * \retval	E_OPNED	If device was opened before with different parameters,
+ *			then just increase the \ref dev_iic_info::opn_cnt "opn_cnt" and return \ref E_OPNED
+ * \retval	E_OBJ	Device object is not valid
+ * \retval	E_SYS	Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first.
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_NOSPT	Open settings are not supported
+ */
+
+/**
+ * \fn		int32_t (* dev_iic::iic_close) (void)
+ * \details	close an iic device, just decrease the \ref dev_iic_info::opn_cnt "opn_cnt",
+ *      if \ref dev_iic_info::opn_cnt "opn_cnt" equals 0, then close the device
+ * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
+ * \retval	E_OPNED	Device is still opened, the device \ref dev_iic_info::opn_cnt "opn_cnt" decreased by 1
+ * \retval	E_OBJ	Device object is not valid
+ */
+
+/**
+ * \fn		int32_t (* dev_iic::iic_control) (uint32_t ctrl_cmd, void *param)
+ * \details	control an iic device by \ref ctrl_cmd, with passed \ref param.
+ * 	you can control iic device using predefined iic control commands defined using \ref DEV_SET_SYSCMD
+ * 	(which must be implemented by bsp developer), such as \ref IIC_CMD_SET_SPEED "set iic speed mode",
+ * 	\ref IIC_CMD_FLUSH_TX "flush tx" and \ref DEVICE_HAL_IIC_CTRLCMD "more".
+ * 	And you can also control iic device using your own specified commands defined using \ref DEV_SET_USRCMD,
+ * 	but these specified commands should be defined in your own iic device driver implementation.
+ * \param[in]		ctrl_cmd	\ref DEVICE_HAL_IIC_CTRLCMD "control command", to change or get some thing related to iic
+ * \param[in,out]	param		parameters that maybe argument of the command,
+ * 					or return values of the command, must not be NULL
+ * \retval	E_OK	Control device successfully
+ * \retval	E_CLSED	Device is not opened
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
+ * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
+ * \retval	E_NOSPT	Control command is not supported or not valid
+ */
+
+/**
+ * \fn		int32_t (* dev_iic::iic_write) (const void *data, uint32_t len)
+ * \details	send \ref data through iic with defined \ref len to slave device which slave address is \ref slv_addr.
+ * \param[in]	data	pointer to data need to send by iic
+ * \param[in]	len	length of data to be sent
+ * \retval	>0	Byte count that was successfully sent for poll method,
+ * 			it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state".
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_CTX	Device is still in transfer state
+ * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
+ */
+
+/**
+ * \fn		int32_t (* dev_iic::iic_read) (void *data, uint32_t len)
+ * \details	receive \ref data of defined \ref len through iic from slave device which slave address is \ref slv_addr.
+ * \param[out]	data	pointer to data need to received by iic
+ * \param[in]	len	length of data to be received
+ * \retval	>0	Byte count that was successfully received for poll method,
+ * 			it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state".
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_CTX	Device is still in transfer state
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
+ */
+/** @} */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief	get an \ref dev_iic "iic device" by iic device id.
+ * 	For how to use iic device hal refer to \ref DEVICE_HAL_IIC_DEVSTRUCT "Functions in iic device structure"
+ * \param[in]	iic_id	id of iic, defined by user
+ * \retval	!NULL	pointer to an \ref dev_iic "iic device structure"
+ * \retval	NULL	failed to find the iic device by \ref iic_id
+ * \note	need to implemented by user in user code
+ */
+extern DEV_IIC_PTR iic_get_dev(int32_t iic_id);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif /* _DEVICE_HAL_IIC_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h
new file mode 100644
index 0000000000..4469654e54
--- /dev/null
+++ b/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h
@@ -0,0 +1,577 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-06-16
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_HAL_SPI	SPI Device HAL Interface
+ * \ingroup	DEVICE_HAL_DEF
+ * \brief	definitions for spi device hardware layer (\ref dev_spi.h)
+ * \details	provide interfaces for spi driver to implement
+ *  Here is a diagram for the spi interface.
+ *
+ *  \htmlonly
+ *  <div class="imagebox">
+ *      <div style="width: 600px">
+ *          <img src="pic/dev_spi_hal.jpg" alt="SPI Device HAL Interface Diagram"/>
+ *          <p>SPI Device HAL Interface Diagram</p>
+ *      </div>
+ *  </div>
+ *  \endhtmlonly
+ *
+ * @{
+ *
+ * \file
+ * \brief	spi device hardware layer definitions
+ * \details	provide common definitions for spi device,
+ * 	then software developer can develop spi driver
+ * 	following this definitions, and the applications
+ * 	can directly call this definition to realize functions
+ */
+
+#ifndef _DEVICE_HAL_SPI_H_
+#define _DEVICE_HAL_SPI_H_
+
+#include "device/device_hal/inc/dev_common.h"
+
+
+/**
+ * \defgroup	DEVICE_HAL_SPI_CTRLCMD		SPI Device Control Commands
+ * \ingroup	DEVICE_HAL_SPI
+ * \brief	Definitions for spi control command, used in \ref dev_spi::spi_control "SPI IO Control"
+ * \details	These commands defined here can be used in user code directly.
+ * - Parameters Usage
+ *   - For passing parameters like integer, just use uint32_t/int32_t to directly pass values
+ *   - For passing parameters for a structure, please use pointer to pass values
+ *   - For getting some data, please use pointer to store the return data
+ * - Common Return Values
+ *   - \ref E_OK,	Control device successfully
+ *   - \ref E_CLSED,	Device is not opened
+ *   - \ref E_OBJ,	Device object is not valid or not exists
+ *   - \ref E_PAR,	Parameter is not valid for current control command
+ *   - \ref E_SYS,	Control device failed, due to hardware issues such as device is disabled
+ *   - \ref E_CTX,	Control device failed, due to different reasons like in transfer state
+ *   - \ref E_NOSPT,	Control command is not supported or not valid
+ * - Usage Comment
+ *   - For SPI poll or interrupt read/write/transfer operations, only 1 operation can be triggered.
+ *     If there is a operation is running, any other operation will return \ref E_CTX
+ *   - If SPI is in transfer, then the following operations may return \ref E_CTX. Like
+ *     \ref SPI_CMD_SET_CLK_MODE, \ref SPI_CMD_SET_TXINT_BUF, \ref SPI_CMD_SET_RXINT_BUF,
+ *     \ref SPI_CMD_SET_TXINT, \ref SPI_CMD_SET_RXINT, \ref SPI_CMD_ABORT_TX, \ref SPI_CMD_ABORT_RX,
+ *     \ref SPI_CMD_FLUSH_TX, \ref SPI_CMD_FLUSH_RX, \ref SPI_CMD_SET_DFS, \ref SPI_CMD_TRANSFER_POLLING,
+ *     \ref SPI_CMD_TRANSFER_INT, \ref SPI_CMD_ABORT_XFER, \ref SPI_CMD_MST_SEL_DEV, \ref SPI_CMD_MST_DSEL_DEV,
+ *     \ref SPI_CMD_MST_SET_FREQ and \ref dev_spi::spi_write "SPI Poll Write" or \ref dev_spi::spi_read "SPI Poll Read".
+ * @{
+ */
+
+/** Define SPI control commands for common usage */
+#define DEV_SET_SPI_SYSCMD(cmd)		DEV_SET_SYSCMD((cmd))
+/** Define SPI control commands for master usage */
+#define DEV_SET_SPI_MST_SYSCMD(cmd)	DEV_SET_SYSCMD(0x00001000|(cmd))
+/** Define SPI control commands for slave usage */
+#define DEV_SET_SPI_SLV_SYSCMD(cmd)	DEV_SET_SYSCMD(0x00002000|(cmd))
+
+
+/* ++++ Common commands for SPI Device ++++ */
+/**
+ * Get \ref dev_spi_info::status "current device status"
+ * - Param type : uint32_t *
+ * - Param usage : store result of current status
+ * - Return value explanation :
+ */
+#define SPI_CMD_GET_STATUS			DEV_SET_SPI_SYSCMD(0)
+/**
+ * set the \ref dev_spi_info::clk_mode "clock mode" of spi transfer
+ * - Param type : uint32_t
+ * - Param usage : spi clock mode to choose clock phase and clock polarity
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_CLK_MODE			DEV_SET_SPI_SYSCMD(1)
+/**
+ * set spi \ref dev_spi_info::dfs "data frame size"
+ * - Param type : uint32_t
+ * - Param usage : should > 0
+ * - Return value explanation : If dfs is not supported, then return \ref E_SYS
+ */
+#define SPI_CMD_SET_DFS				DEV_SET_SPI_SYSCMD(2)
+/**
+ * set the \ref dev_spi_info::dummy "dummy data" during spi transfer
+ * - Param type : uint32_t
+ * - Param usage : dummy data to transfer
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_DUMMY_DATA			DEV_SET_SPI_SYSCMD(3)
+/**
+ * Set \ref dev_spi_cbs::tx_cb "spi transmit success callback" function
+ * when all required bytes are transmitted for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : transmit success callback function for spi
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_TXCB			DEV_SET_SPI_SYSCMD(4)
+/**
+ * Set \ref dev_spi_cbs::rx_cb "spi receive success callback" function
+ * when all required bytes are received for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : receive success callback function for spi
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_RXCB			DEV_SET_SPI_SYSCMD(5)
+/**
+ * Set \ref dev_spi_cbs::xfer_cb "spi transfer success callback" function
+ * when all required transfer are done for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : transfer success callback function for spi
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_XFERCB			DEV_SET_SPI_SYSCMD(6)
+/**
+ * Set \ref dev_spi_cbs::err_cb "spi transfer error callback" function
+ * when something error happened for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : transfer error callback function for spi
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_ERRCB			DEV_SET_SPI_SYSCMD(7)
+/**
+ * Set buffer in interrupt transmit, and it will set \ref dev_spi_info::xfer "spi tranfer".
+ * - SPI master and slave mode use case  \n
+ *    For both master and slave mode, if you set tx buffer to NULL, when tx interrupt is enabled and entered into tx interrupt,
+ * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the
+ * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt
+ * and call tx callback function if available.
+ * - Param type : DEV_BUFFER * or NULL
+ * - Param usage : buffer structure pointer, if param is NULL, then it will set xfer to empty
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_TXINT_BUF			DEV_SET_SPI_SYSCMD(8)
+/**
+ * Set buffer in interrupt receive, and it will set \ref dev_spi_info::xfer "spi tranfer".
+ * - SPI master mode use case  \n
+ *   Similar to \ref SPI_CMD_SET_TXINT_BUF
+ * - SPI slave mode use case   \n
+ *   Similiar to \ref SPI_CMD_SET_TXINT_BUF
+ * - Param type : DEV_BUFFER * or NULL
+ * - Param usage : buffer structure pointer, if param is NULL, then it will set xfer to empty
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_RXINT_BUF			DEV_SET_SPI_SYSCMD(9)
+/**
+ * Enable or disable transmit interrupt,
+ * for master mode, only one of tx and rx interrupt can be enabled,
+ * if tx interrupt is enabled, then rx interrupt can't be enabled.
+ * - Param type : uint32_t
+ * - Param usage : enable(none-zero) or disable(zero) flag
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_TXINT			DEV_SET_SPI_SYSCMD(10)
+/**
+ * Enable or disable receive interrupt,
+ * for master mode, only one of tx and rx interrupt can be enabled,
+ * if rx interrupt is enabled, then tx interrupt can't be enabled.
+ * - Param type : uint32_t
+ * - Param usage : enable(none-zero) or disable(zero) flag
+ * - Return value explanation :
+ */
+#define SPI_CMD_SET_RXINT			DEV_SET_SPI_SYSCMD(11)
+/**
+ * start the transfer by polling
+ * - Param type : \ref DEV_SPI_TRANSFER *
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define SPI_CMD_TRANSFER_POLLING		DEV_SET_SPI_SYSCMD(12)
+/**
+ * start the transfer by interrupt
+ * - Param type : \ref DEV_SPI_TRANSFER * or NULL
+ * - Param usage : If NULL, it will disable transfer interrupt, if not NULL, it will enable transfer interrupt
+ * - Return value explanation :
+ */
+#define SPI_CMD_TRANSFER_INT			DEV_SET_SPI_SYSCMD(13)
+/**
+ * Abort current interrupt transmit operation if tx interrupt enabled,
+ * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT
+ * in \ref dev_spi_info::status "status" variable,
+ * and call the transmit callback function, when tx callback is finished,
+ * it will clear \ref DEV_IN_TX_ABRT and return
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define SPI_CMD_ABORT_TX			DEV_SET_SPI_SYSCMD(14)
+/**
+ * Abort current interrupt receive operation if rx interrupt enabled,
+ * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT
+ * in \ref dev_spi_info::status "status" variable,
+ * and call the receive callback function, when rx callback is finished,
+ * it will clear \ref DEV_IN_TX_ABRT and return
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define SPI_CMD_ABORT_RX			DEV_SET_SPI_SYSCMD(15)
+/**
+ * Abort current interrupt transfer operation if transfer is issued,
+ * it will disable transfer interrupt, and set \ref DEV_IN_XFER_ABRT
+ * in \ref dev_spi_info::status "status" variable,
+ * and call the transfer callback function, when xfer callback is finished,
+ * it will clear \ref DEV_IN_XFER_ABRT and return
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define SPI_CMD_ABORT_XFER			DEV_SET_SPI_SYSCMD(16)
+/**
+ * Do a software reset for SPI device, it will stop current transfer,
+ * and clear error state and bring device to normal state, set next condition to STOP
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define SPI_CMD_RESET				DEV_SET_SPI_SYSCMD(17)
+/**
+ * Flush spi tx fifo, this will clear the data in tx fifo
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define SPI_CMD_FLUSH_TX			DEV_SET_SPI_SYSCMD(18)
+/**
+ * Flush spi rx fifo, this will clear the data in rx fifo
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define SPI_CMD_FLUSH_RX			DEV_SET_SPI_SYSCMD(19)
+/**
+ * Enable spi device
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define SPI_CMD_ENA_DEV				DEV_SET_SPI_SYSCMD(20)
+/**
+ * Disable spi device, when device is disabled,
+ * only \ref SPI_CMD_ENA_DEV, \ref SPI_CMD_DIS_DEV,
+ * \ref SPI_CMD_GET_STATUS and \ref SPI_CMD_RESET
+ * commands can be executed, other commands will return \ref E_SYS
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define SPI_CMD_DIS_DEV				DEV_SET_SPI_SYSCMD(21)
+/**
+ * Get how many bytes space in spi are available to transmit,
+ * this can be used in interrupt callback functions,
+ * cooperate with \ref dev_spi::spi_write "spi_write" API to realize non-blocked write
+ * - Param type : int32_t *
+ * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available
+ * - Return value explanation :
+ */
+#define SPI_CMD_GET_TXAVAIL			DEV_SET_SPI_SYSCMD(22)
+/**
+ * Get how many bytes in spi are available to receive,
+ * this can be used in interrupt callback functions,
+ * cooperate with \ref dev_spi::spi_read "spi_read" API to realize non-blocked read
+ * - Param type : int32_t *
+ * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available
+ * - Return value explanation :
+ */
+#define SPI_CMD_GET_RXAVAIL			DEV_SET_SPI_SYSCMD(23)
+
+
+/* ++++ Master only commands for SPI Device ++++ */
+/**
+ *  select spi slave device
+ * - Param type : uint32_t
+ * - Param usage : the number of spi slave device to select
+ * - Return value explanation : return \ref E_SYS when selection can't be done, return \ref E_CTX during transfer
+ */
+#define SPI_CMD_MST_SEL_DEV			DEV_SET_SPI_MST_SYSCMD(0)
+/**
+ *  de-select spi slave device
+ * - Param type : uint32_t
+ * - Param usage : the number of spi slave device to de-select
+ * - Return value explanation : return \ref E_SYS when selection can't be done, return \ref E_CTX during transfer
+ */
+#define SPI_CMD_MST_DSEL_DEV			DEV_SET_SPI_MST_SYSCMD(1)
+ /**
+ * Set \ref dev_spi_info::freq "spi frequency".
+ * - Param type : uint32_t
+ * - Param usage : spi freq
+ * - Return value explanation : no return
+ */
+#define SPI_CMD_MST_SET_FREQ			DEV_SET_SPI_MST_SYSCMD(2)
+
+
+/* ++++ Slave only commands for SPI Device ++++ */
+
+/* \todo add spi slave related CMDs */
+
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_SPI_CALLBACK	SPI Interrupt callback functions
+ * \ingroup	DEVICE_HAL_SPI
+ * \brief	callback function structure for SPI device
+ * @{
+ */
+typedef struct dev_spi_cbs {
+	DEV_CALLBACK tx_cb;	/*!< spi data transmit success required bytes callback */
+	DEV_CALLBACK rx_cb;	/*!< spi data receive success required bytes callback */
+	DEV_CALLBACK err_cb;	/*!< spi error callback */
+	DEV_CALLBACK xfer_cb;	/*!< transfer callback */
+} DEV_SPI_CBS, *DEV_SPI_CBS_PTR;
+/** @} */
+
+/** SPI Clock Mode */
+typedef enum spi_clk_mode {
+	SPI_CPOL_0_CPHA_0 = 0,	/*!< Inactive state of serial clock is low, serial clock toggles in middle of first data bit */
+	SPI_CPOL_0_CPHA_1 = 1,	/*!< Inactive state of serial clock is low, serial clock toggles at start of first data bit  */
+	SPI_CPOL_1_CPHA_0 = 2,	/*!< Inactive state of serial clock is high, serial clock toggles in middle of first data bit */
+	SPI_CPOL_1_CPHA_1 = 3,	/*!< Inactive state of serial clock is high, serial clock toggles at start of first data bit */
+
+	SPI_CLK_MODE_0    = SPI_CPOL_0_CPHA_0,	/*!< Equal to \ref SPI_CPOL_0_CPHA_0 */
+	SPI_CLK_MODE_1    = SPI_CPOL_0_CPHA_1,	/*!< Equal to \ref SPI_CPOL_0_CPHA_1 */
+	SPI_CLK_MODE_2    = SPI_CPOL_1_CPHA_0,	/*!< Equal to \ref SPI_CPOL_1_CPHA_0 */
+	SPI_CLK_MODE_3    = SPI_CPOL_1_CPHA_1	/*!< Equal to \ref SPI_CPOL_1_CPHA_1 */
+} SPI_CLK_MODE;
+
+#define SPI_CLK_MODE_DEFAULT	SPI_CPOL_0_CPHA_0	/*!< Default SPI device clock mode */
+
+/**
+ * \defgroup	DEVICE_HAL_SPI_DEVSTRUCT	SPI Device Structure
+ * \ingroup	DEVICE_HAL_SPI
+ * \brief	contains definitions of spi device structure.
+ * \details	this structure will be used in user implemented code, which was called
+ * 	Device Driver Implement Layer for spi to realize in user code.
+ * @{
+ */
+typedef struct dev_spi_transfer DEV_SPI_TRANSFER, *DEV_SPI_TRANSFER_PTR;
+/**
+ * \brief	spi read and write data structure used by \ref SPI_CMD_TRANSFER
+ * 	spi write then read data
+ *
+ */
+struct dev_spi_transfer {
+	DEV_SPI_TRANSFER *next;
+	/* Calc by software */
+	/** tot_len = (tx_totlen>rx_totlen)?tx_totlen:rx_totlen */
+	uint32_t tot_len;
+	/* Set by user */
+	uint8_t *tx_buf;
+	uint32_t tx_ofs;
+	uint32_t tx_len;
+	uint8_t *rx_buf;
+	uint32_t rx_ofs;
+	uint32_t rx_len;
+	/* Should auto set to proper value during set buffer value */
+	uint32_t tx_idx;
+	uint32_t tx_totlen;	/** tx_totlen = tx_len + tx_ofs */
+	uint32_t rx_idx;
+	uint32_t rx_totlen;	/** rx_totlen = rx_len + rx_ofs */
+};
+
+/** Set tx buffer of device spi transfer */
+#define DEV_SPI_XFER_SET_TXBUF(xfer, buf, ofs, len)		{		\
+					(xfer)->tx_buf = (uint8_t *)(buf);	\
+					(xfer)->tx_len = (uint32_t)(len);	\
+					(xfer)->tx_ofs = (uint32_t)(ofs);	\
+					(xfer)->tx_idx = 0;			\
+					(xfer)->tx_totlen = ( (uint32_t)(len) 	\
+							+ (uint32_t)(ofs) ) ;	\
+				}
+
+/** Set rx buffer of device spi transfer */
+#define DEV_SPI_XFER_SET_RXBUF(xfer, buf, ofs, len)		{		\
+					(xfer)->rx_buf = (uint8_t *)(buf);	\
+					(xfer)->rx_len = (uint32_t)(len);	\
+					(xfer)->rx_ofs = (uint32_t)(ofs);	\
+					(xfer)->rx_idx = 0;			\
+					(xfer)->rx_totlen = ( (uint32_t)(len) 	\
+							+ (uint32_t)(ofs) ) ;	\
+				}
+
+/** Calculate total length of current transfer without next transfer */
+#define DEV_SPI_XFER_CALC_TOTLEN(xfer)		(xfer)->tot_len =	\
+				((xfer)->tx_totlen > (xfer)->rx_totlen) ? (xfer)->tx_totlen : (xfer)->rx_totlen ;
+
+/** Set next SPI transfer */
+#define DEV_SPI_XFER_SET_NEXT(xfer, next_xfer)	(xfer)->next = (next_xfer);
+
+/** Init spi transfer */
+#define DEV_SPI_XFER_INIT(xfer)					{		\
+					(xfer)->tx_idx = 0;			\
+					(xfer)->rx_idx = 0;			\
+					(xfer)->tx_totlen = ((xfer)->tx_len  	\
+							+ (xfer)->tx_ofs) ;	\
+					(xfer)->rx_totlen = ((xfer)->rx_len  	\
+							+ (xfer)->rx_ofs) ;	\
+					DEV_SPI_XFER_CALC_TOTLEN(xfer);		\
+				}
+/**
+ * \brief	spi information struct definition
+ * \details	informations about spi open state, working state,
+ * 	frequency, spi registers, working method, interrupt number
+ */
+typedef struct dev_spi_info {
+	void *spi_ctrl;		/*!< spi control related */
+	uint32_t status;	/*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */
+	uint32_t freq;		/*!< spi working baudrate */
+	uint8_t mode;		/*!< spi working mode (master/slave) */
+	uint8_t clk_mode;	/*!< spi clock phase and polarity, this should be \ref SPI_CLK_MODE_DEFAULT for first open */
+	uint8_t opn_cnt;	/*!< spi open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */
+	uint8_t slave;		/*!< current selected slave device no, start from 0, this should be \ref SPI_SLAVE_NOT_SELECTED for first open */
+	uint8_t dfs;		/*!< data frame size, this should be \ref SPI_DFS_DEFAULT for first open */
+
+	DEV_SPI_TRANSFER xfer;	/*!< spi transfer, this should be set to all zero for first open */
+	DEV_SPI_CBS spi_cbs;	/*!< spi callbacks, for both master and slave mode, this should be all NULL for first open */
+	void *extra;		/*!< a extra pointer to get hook to applications which should not used by bsp developer,
+					this should be NULL for first open and you can \ref DEV_SPI_INFO_SET_EXTRA_OBJECT "set"
+					or \ref DEV_SPI_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */
+	uint32_t dummy;		/*!< dummy write data when send and receive, this should be \ref SPI_DUMMY_DEFAULT for first open */
+} DEV_SPI_INFO, * DEV_SPI_INFO_PTR;
+
+/** Set extra information pointer of spi info */
+#define DEV_SPI_INFO_SET_EXTRA_OBJECT(spi_info_ptr, extra_info)		(spi_info_ptr)->extra = (void *)(extra_info)
+/** Get extra information pointer of spi info */
+#define DEV_SPI_INFO_GET_EXTRA_OBJECT(spi_info_ptr)			((spi_info_ptr)->extra)
+
+#define SPI_DFS_DEFAULT				8		/*!< Default spi data frame size */
+#define SPI_SLAVE_NOT_SELECTED			(0xFF)		/*!< Slave is not selected */
+#define SPI_DUMMY_DEFAULT			(0xFF)		/*!< default dummy value for first open */
+
+/**
+ * \brief	spi device interface definition
+ * \details	define spi device interface, like spi information structure,
+ * 	fuctions to get spi info, open/close/control spi, send/receive data by spi
+ * \note	all this details are implemented by user in user porting code
+ */
+typedef struct dev_spi {
+	DEV_SPI_INFO spi_info;						/*!< spi device information */
+	int32_t (*spi_open) (uint32_t mode, uint32_t param);		/*!< open spi device in master/slave mode, \
+									when in master mode, param stands for frequency, \
+									when in slave mode, param stands for clock mode */
+	int32_t (*spi_close) (void);					/*!< close spi device */
+	int32_t (*spi_control) (uint32_t ctrl_cmd, void *param);	/*!< control spi device */
+	int32_t (*spi_write) (const void *data, uint32_t len);		/*!< send data to spi device (blocking method) */
+	int32_t (*spi_read) (void *data, uint32_t len);			/*!< read data from spi device (blocking method) */
+} DEV_SPI, * DEV_SPI_PTR;
+
+/**
+ * \fn		int32_t (* dev_spi::spi_open) (uint32_t mode, uint32_t param)
+ * \details	open an spi device with selected mode (master or slave) with defined \ref param
+ * \param[in]	mode	working mode (\ref DEV_MASTER_MODE "master" or \ref DEV_SLAVE_MODE "slave")
+ * \param[in]	param	When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_spi_info::freq "frequency",
+ * 			when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_spi_info::clk_mode "slave clock mode"
+ * \retval	E_OK	Open successfully without any issues
+ * \retval	E_OPNED	If device was opened before with different parameters,
+ *			then just increase the \ref dev_spi_info::opn_cnt "opn_cnt" and return \ref E_OPNED
+ * \retval	E_OBJ	Device object is not valid
+ * \retval	E_SYS	Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first.
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_NOSPT	Open settings are not supported
+ */
+
+/**
+ * \fn		int32_t (* dev_spi::spi_close) (void)
+ * \details	close an spi device, just decrease the \ref dev_spi_info::opn_cnt "opn_cnt",
+ *      if \ref dev_spi_info::opn_cnt "opn_cnt" equals 0, then close the device
+ * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
+ * \retval	E_OPNED	Device is still opened, the device \ref dev_spi_info::opn_cnt "opn_cnt" decreased by 1
+ * \retval	E_OBJ	Device object is not valid
+ */
+
+/**
+ * \fn		int32_t (* dev_spi::spi_control) (uint32_t ctrl_cmd, void *param)
+ * \details	control an spi device by \ref ctrl_cmd, with passed \ref param.
+ * 	you can control spi device using predefined spi control commands defined using \ref DEV_SET_SYSCMD
+ * 	(which must be implemented by bsp developer), such as \ref SPI_CMD_MST_SET_FREQ "set spi master frequency",
+ * 	\ref SPI_CMD_FLUSH_TX "flush tx" and \ref DEVICE_HAL_SPI_CTRLCMD "more".
+ * 	And you can also control spi device using your own specified commands defined using \ref DEV_SET_USRCMD,
+ * 	but these specified commands should be defined in your own spi device driver implementation.
+ * \param[in]		ctrl_cmd	\ref DEVICE_HAL_SPI_CTRLCMD "control command", to change or get some thing related to spi
+ * \param[in,out]	param		parameters that maybe argument of the command,
+ * 					or return values of the command, must not be NULL
+ * \retval	E_OK	Control device successfully
+ * \retval	E_CLSED	Device is not opened
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
+ * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
+ * \retval	E_NOSPT	Control command is not supported or not valid
+ */
+
+/**
+ * \fn		int32_t (* dev_spi::spi_write) (const void *data, uint32_t len)
+ * \details	send \ref data through spi with defined \ref len to slave device .
+ * \param[in]	data	pointer to data need to send by spi
+ * \param[in]	len	length of data to be sent
+ * \retval	>0	Byte count that was successfully sent for poll method
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_CTX	Device is still in transfer state
+ * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
+ */
+
+/**
+ * \fn		int32_t (* dev_spi::spi_read) (void *data, uint32_t len)
+ * \details	receive \ref data of defined \ref len through spi from slave device .
+ * \param[out]	data	pointer to data need to received by spi
+ * \param[in]	len	length of data to be received
+ * \retval	>0	Byte count that was successfully received for poll method
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_CTX	Device is still in transfer state
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
+ */
+/** @} */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief	get an \ref dev_spi "spi device" by spi device id.
+ * 	For how to use spi device hal refer to \ref dev_spi "Functions in spi device structure"
+ * \param[in]	spi_id	id of spi, defined by user
+ * \retval	!NULL	pointer to an \ref dev_spi "spi device structure"
+ * \retval	NULL	failed to find the spi device by \ref spi_id
+ * \note	need to implemented by user in user code
+ */
+extern DEV_SPI_PTR spi_get_dev(int32_t spi_id);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif /* _DEVICE_HAL_SPI_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h
new file mode 100644
index 0000000000..c8e17d6421
--- /dev/null
+++ b/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h
@@ -0,0 +1,475 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-16
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \defgroup	DEVICE_HAL_UART		UART Device HAL Interface
+ * \ingroup	DEVICE_HAL_DEF
+ * \brief	Definitions for uart device hardware layer (\ref dev_uart.h)
+ * \details	Provide unified APIs for uart driver to implement.
+ *  Here is a diagram for the uart interface.
+ *
+ *  \htmlonly
+ *  <div class="imagebox">
+ *      <div style="width: 600px">
+ *          <img src="pic/dev_uart_hal.jpg" alt="UART Device HAL Interface Diagram"/>
+ *          <p>UART Device HAL Interface Diagram</p>
+ *      </div>
+ *  </div>
+ *  \endhtmlonly
+ *
+ * ### Reference Links
+ *     * [Serial Port](https://en.wikipedia.org/wiki/Serial_port)
+ *
+ * @{6
+ *
+ * \file
+ * \brief	uart device hardware layer definitions
+ * \details	Provide common definitions for uart device,
+ * 	then software developer can develop uart driver
+ * 	following this definitions, and the applications
+ * 	can directly call this definition to realize functions
+ *
+ */
+
+#ifndef _DEVICE_HAL_UART_H_
+#define _DEVICE_HAL_UART_H_
+
+#include "device/device_hal/inc/dev_common.h"
+
+/**
+ * \defgroup	DEVICE_HAL_UART_BAUD	UART Device Baudrate Definitions
+ * \ingroup	DEVICE_HAL_UART
+ * \brief	Macros for uart baudrate.
+ * \details	Definitions for baudrate from 4800 to 115200bps.
+ * @{
+ */
+/*
+ * defines for uart baudrates
+ */
+#define UART_BAUDRATE_110			(110)		/*!< uart baudrate 110bps */
+#define UART_BAUDRATE_300			(300)		/*!< uart baudrate 300bps */
+#define UART_BAUDRATE_600			(600)		/*!< uart baudrate 600bps */
+#define UART_BAUDRATE_1200			(1200)		/*!< uart baudrate 1200bps */
+#define UART_BAUDRATE_2400			(2400)		/*!< uart baudrate 2400bps */
+#define UART_BAUDRATE_4800			(4800)		/*!< uart baudrate 4800bps */
+#define UART_BAUDRATE_9600			(9600)		/*!< uart baudrate 9600bps */
+#define UART_BAUDRATE_14400			(14400)		/*!< uart baudrate 14400bps */
+#define UART_BAUDRATE_19200			(19200)		/*!< uart baudrate 19200bps */
+#define UART_BAUDRATE_38400			(38400)		/*!< uart baudrate 38400bps */
+#define UART_BAUDRATE_57600			(57600)		/*!< uart baudrate 57600bps */
+#define UART_BAUDRATE_115200			(115200)	/*!< uart baudrate 115200bps */
+#define UART_BAUDRATE_230400			(230400)	/*!< uart baudrate 230400bps */
+#define UART_BAUDRATE_460800			(460800)	/*!< uart baudrate 460800bps */
+#define UART_BAUDRATE_921600			(921600)	/*!< uart baudrate 921600bps */
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_UART_FORMAT	UART Device Format Definitions
+ * \ingroup	DEVICE_HAL_UART
+ * \brief	Macros for uart format.
+ * \details	Definitions for uart format like databits, parity, stopbits.
+ * @{
+ */
+/**
+ * UART Device Parity Types Enum
+ */
+typedef enum {
+	UART_PARITY_NONE  = 0,	/*!< no parity bit */
+	UART_PARITY_ODD   = 1,	/*!< odd parity bit */
+	UART_PARITY_EVEN  = 2,	/*!< even parity bit */
+	UART_PARITY_MARK  = 3,	/*!< mark parity bit, always logical 1 */
+	UART_PARITY_SPACE = 4	/*!< space parity bit, always logical 0 */
+} UART_PARITY;
+
+/**
+ * UART Device Stop Bits Enum
+ */
+typedef enum {
+	UART_STPBITS_ONE     = 0,	/*!< 1 stop bit */
+	UART_STPBITS_ONEHALF = 1,	/*!< 1.5 stop bits */
+	UART_STPBITS_TWO     = 2	/*!< 2 stop bits */
+} UART_STOPBITS;
+
+/**
+ * UART DPS Format: databits/parity/stopbits
+ */
+typedef struct uart_dps_format {
+	uint32_t databits;	/*!< data bits */
+	UART_PARITY parity;	/*!< parity bit type */
+	UART_STOPBITS stopbits;	/*!< stop bits */
+} UART_DPS_FORMAT;
+
+#define UART_DATABITS_DEFAULT	8	/*!< default data bits */
+
+/** Default UART DPS format */
+static const UART_DPS_FORMAT dps_format_default = {UART_DATABITS_DEFAULT, UART_PARITY_NONE, UART_STPBITS_ONE};
+/** @} */
+
+/**
+ * UART Device Hardware Flow Control Types Enum
+ */
+typedef enum {
+	UART_FC_NONE = 0,	/*!< Non hardware flow control */
+	UART_FC_RTS  = 1,	/*!< Request To Send */
+	UART_FC_CTS  = 2,	/*!< Clear To Send */
+	UART_FC_BOTH = 3	/*!< Both hardware flow control methods */
+} UART_HW_FLOW_CONTROL;
+/** Default hardware flow control method */
+static const UART_HW_FLOW_CONTROL hwfc_default = UART_FC_NONE;
+
+/**
+ * \defgroup	DEVICE_HAL_UART_CTRLCMD		UART Device Control Commands
+ * \ingroup	DEVICE_HAL_UART
+ * \brief	Definitions for uart control command, used in \ref dev_uart::uart_control "UART IO Control"
+ * \details	These commands defined here can be used in user code directly.
+ * - Parameters Usage
+ *   - For passing parameters like integer, just use uint32_t/int32_t to directly pass values
+ *   - For passing parameters for a structure, please use pointer to pass values
+ *   - For getting some data, please use pointer to store the return data
+ * - Common Return Values
+ *   - \ref E_OK,	Control device successfully
+ *   - \ref E_CLSED,	Device is not opened
+ *   - \ref E_OBJ,	Device object is not valid or not exists
+ *   - \ref E_PAR,	Parameter is not valid for current control command
+ *   - \ref E_SYS,	Control device failed, due to hardware issues such as device is disabled
+ *   - \ref E_CTX,	Control device failed, due to different reasons like in transfer state
+ *   - \ref E_NOSPT,	Control command is not supported or not valid
+ * @{
+ */
+/**
+ * Set \ref dev_uart_info::baudrate "uart baudrate".
+ * - Param type : uint32_t
+ * - Param usage : uart baudrate, must above zero. Here is a list of \ref DEVICE_HAL_UART_BAUD "possible baudrates"
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_BAUD			DEV_SET_SYSCMD(0)
+/**
+ * Get \ref dev_uart_info::status "current device status"
+ * - Param type : uint32_t *
+ * - Param usage : store result of current status
+ * - Return value explanation :
+ */
+#define UART_CMD_GET_STATUS			DEV_SET_SYSCMD(1)
+/**
+ * Enable uart device
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define UART_CMD_ENA_DEV			DEV_SET_SYSCMD(2)
+/**
+ * Disable uart device, when device is disabled,
+ * only \ref UART_CMD_ENA_DEV, \ref UART_CMD_DIS_DEV and
+ * \ref UART_CMD_GET_STATUS commands can be executed,
+ * other commands will return \ref E_SYS
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define UART_CMD_DIS_DEV			DEV_SET_SYSCMD(3)
+/**
+ * Flush uart device output
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define UART_CMD_FLUSH_OUTPUT			DEV_SET_SYSCMD(4)
+/**
+ * Get how many bytes space in uart are available to transmit,
+ * this can be used in interrupt callback functions,
+ * cooperate with \ref dev_uart::uart_write "uart_write" API to realize non-blocked write
+ * - Param type : int32_t *
+ * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available
+ * - Return value explanation :
+ */
+#define UART_CMD_GET_TXAVAIL			DEV_SET_SYSCMD(5)
+/**
+ * Get how many bytes in uart are available to receive,
+ * this can be used in interrupt callback functions,
+ * cooperate with \ref dev_uart::uart_read "uart_read" API to realize non-blocked read
+ * - Param type : int32_t *
+ * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available
+ * - Return value explanation :
+ */
+#define UART_CMD_GET_RXAVAIL			DEV_SET_SYSCMD(6)
+/**
+ * Cause a break condition to be transmitted to the receiving device
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define UART_CMD_BREAK_SET			DEV_SET_SYSCMD(7)
+/**
+ * Clear break condition and return to normal
+ * - Param type : NULL
+ * - Param usage : param is not required
+ * - Return value explanation :
+ */
+#define UART_CMD_BREAK_CLR			DEV_SET_SYSCMD(8)
+/**
+ * Change uart \ref dev_uart_info::dps_format "D/P/S(Data/Parity/Stop) format"
+ * - Param type : \ref UART_DPS_FORMAT *
+ * - Param usage : uart dps format including databits, parity and stopbits
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_DPS_FORMAT			DEV_SET_SYSCMD(9)
+/**
+ * Set uart device \ref dev_uart_info::hwfc "hardware flow control"
+ * - Param type : \ref UART_HW_FLOW_CONTROL
+ * - Param usage : uart dps format including databits, parity and stopbits
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_HWFC			DEV_SET_SYSCMD(10)
+/**
+ * Set \ref dev_uart_cbs::tx_cb "uart transmit success callback" function
+ * when all required bytes are transmitted for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : transmit success callback function for uart
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_TXCB			DEV_SET_SYSCMD(11)
+/**
+ * Set \ref dev_uart_cbs::rx_cb "uart receive success callback" function
+ * when all required bytes are received for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : receive success callback function for uart
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_RXCB			DEV_SET_SYSCMD(12)
+/**
+ * Set \ref dev_uart_cbs::err_cb "uart transfer error callback" function
+ * when something error happened for interrupt method
+ * - Param type : \ref DEV_CALLBACK * or NULL
+ * - Param usage : transfer error callback function for uart
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_ERRCB			DEV_SET_SYSCMD(13)
+/**
+ * Set transmit buffer via interrupt, and it will set \ref dev_uart_info::tx_buf "tx_buf"
+ * - Param type : DEV_BUFFER * or NULL
+ * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_TXINT_BUF			DEV_SET_SYSCMD(14)
+/**
+ * Set receive buffer via interrupt, and it will set \ref dev_uart_info::rx_buf "rx_buf"
+ * - Param type : DEV_BUFFER * or NULL
+ * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_RXINT_BUF			DEV_SET_SYSCMD(15)
+/**
+ * Enable or disable transmit interrupt
+ * - Param type : uint32_t
+ * - Param usage : enable(none-zero) or disable(zero) flag
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_TXINT			DEV_SET_SYSCMD(16)
+/**
+ * Enable or disable receive interrupt
+ * - Param type : uint32_t
+ * - Param usage : enable(none-zero) or disable(zero) flag
+ * - Return value explanation :
+ */
+#define UART_CMD_SET_RXINT			DEV_SET_SYSCMD(17)
+/**
+ * Abort current interrupt transmit operation if tx interrupt enabled,
+ * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT
+ * in \ref dev_uart_info::status "status" variable,
+ * and call the transmit callback function, when tx callback is finished,
+ * it will clear \ref DEV_IN_TX_ABRT and return
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define UART_CMD_ABORT_TX			DEV_SET_SYSCMD(18)
+/**
+ * Abort current interrupt receive operation if rx interrupt enabled,
+ * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT
+ * in \ref dev_uart_info::status "status" variable,
+ * and call the receive callback function, when rx callback is finished,
+ * it will clear \ref DEV_IN_TX_ABRT and return
+ * - Param type : NULL
+ * - Param usage :
+ * - Return value explanation :
+ */
+#define UART_CMD_ABORT_RX			DEV_SET_SYSCMD(19)
+
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_UART_CALLBACK	UART Interrupt callback functions
+ * \ingroup	DEVICE_HAL_UART
+ * \brief	callback function structure for UART device
+ * @{
+ */
+typedef struct dev_uart_cbs {
+	DEV_CALLBACK tx_cb;	/*!< uart data transmit success required bytes callback */
+	DEV_CALLBACK rx_cb;	/*!< uart data receive success required bytes callback */
+	DEV_CALLBACK err_cb;	/*!< uart error callback */
+} DEV_UART_CBS, *DEV_UART_CBS_PTR;
+/** @} */
+
+/**
+ * \defgroup	DEVICE_HAL_UART_DEVSTRUCT	UART Device Interface Definition
+ * \ingroup	DEVICE_HAL_UART
+ * \brief	Contains definitions of uart device interface structure.
+ * \details	This structure will be used in user implemented code, which was called
+ *     \ref DEVICE_IMPL "Device Driver Implement Layer" for uart to use in implementation code.
+ *     Application developer should use the UART API provided here to access to UART devices.
+ *     BSP developer should follow the API definition to implement UART device drivers.
+ * @{
+ */
+/**
+ * \brief	UART information struct definition
+ * \details	informations about uart open count, working status,
+ *     baudrate, uart registers and ctrl structure, uart dps format
+ */
+typedef struct dev_uart_info {
+	void *uart_ctrl;	/*!< uart control related pointer, implemented by bsp developer, and this should be set during uart object implementation */
+	uint32_t opn_cnt;	/*!< uart open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */
+	uint32_t status;	/*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */
+	uint32_t baudrate;	/*!< uart baud rate, this should be the value of baud passing by uart_open if first successfully opened */
+	UART_DPS_FORMAT dps_format;	/*!< D/P/S format settings for uart device, here is \ref dps_format_default "default settings for first open" */
+	UART_HW_FLOW_CONTROL hwfc;	/*!< UART hardware flow control, here is \ref hwfc_default "default hardware flow control settings for first open" */
+	DEV_BUFFER tx_buf;	/*!< transmit buffer via interrupt, this should be all zero for first open */
+	DEV_BUFFER rx_buf;	/*!< receive buffer via interrupt, this should be all zero for first open */
+	DEV_UART_CBS uart_cbs;	/*!< uart callbacks, callback arguments should be \ref DEV_UART * or NULL, this should be all NULL for first open */
+	void *extra;		/*!< a extra pointer to get hook to applications which should not used by bsp developer,
+					this should be NULL for first open and you can \ref DEV_UART_INFO_SET_EXTRA_OBJECT "set"
+					or \ref DEV_UART_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */
+} DEV_UART_INFO, * DEV_UART_INFO_PTR;
+
+/** Set extra information pointer of uart info */
+#define DEV_UART_INFO_SET_EXTRA_OBJECT(uart_info_ptr, extra_info)	(uart_info_ptr)->extra = (void *)(extra_info)
+/** Get extra information pointer of uart info */
+#define DEV_UART_INFO_GET_EXTRA_OBJECT(uart_info_ptr)			((uart_info_ptr)->extra)
+
+/**
+ * \brief	UART device interface definition
+ * \details	Define uart device interface, like uart information structure,
+ * 	provide functions to open/close/control uart, send/receive data by uart
+ * \note	All this details are implemented by user in user porting code
+ */
+typedef struct dev_uart {
+	DEV_UART_INFO uart_info;				/*!< UART device information */
+	int32_t (*uart_open) (uint32_t baud);			/*!< Open uart device */
+	int32_t (*uart_close) (void);				/*!< Close uart device */
+	int32_t (*uart_control) (uint32_t ctrl_cmd, void *param);	/*!< Control uart device */
+	int32_t (*uart_write) (const void *data, uint32_t len);	/*!< Send data by uart device(blocked) */
+	int32_t (*uart_read) (void *data, uint32_t len);	/*!< Read data from uart device(blocked) */
+} DEV_UART, * DEV_UART_PTR;
+
+/**
+ * \fn		int32_t (* dev_uart::uart_open) (uint32_t baud)
+ * \details	open an uart device with defined baudrate
+ * \param[in]	baud	\ref DEVICE_HAL_UART_BAUD "initial baudrate of uart", must > 0
+ * \retval	E_OK	Open successfully without any issues
+ * \retval	E_OPNED	If device was opened before with different parameters,
+ *			then just increase the \ref dev_uart_info::opn_cnt "opn_cnt" and return \ref E_OPNED
+ * \retval	E_OBJ	Device object is not valid
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_NOSPT	Open settings are not supported
+ */
+
+/**
+ * \fn		int32_t (* dev_uart::uart_close) (void)
+ * \details	close an uart device, just decrease the \ref dev_uart_info::opn_cnt "opn_cnt",
+ *      if \ref dev_uart_info::opn_cnt "opn_cnt" equals 0, then close the device
+ * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
+ * \retval	E_OPNED	Device is still opened, the device \ref dev_uart_info::opn_cnt "opn_cnt" decreased by 1
+ * \retval	E_OBJ	Device object is not valid
+ */
+
+/**
+ * \fn		int32_t (* dev_uart::uart_control) (uint32_t ctrl_cmd, void *param)
+ * \details	control an uart device by \ref ctrl_cmd, with passed \ref param.
+ * 	you can control uart device using predefined uart control commands defined using \ref DEV_SET_SYSCMD
+ * 	(which must be implemented by bsp developer), such as \ref UART_CMD_SET_BAUD "change baudrate",
+ * 	\ref UART_CMD_FLUSH_OUTPUT "flush output" and \ref DEVICE_HAL_UART_CTRLCMD "more".
+ * 	And you can also control uart device using your own specified commands defined using \ref DEV_SET_USRCMD,
+ * 	but these specified commands should be defined in your own uart device driver implementation.
+ * \param[in]		ctrl_cmd	\ref DEVICE_HAL_UART_CTRLCMD "control command", to change or get some thing related to uart
+ * \param[in,out]	param		parameters that maybe argument of the command, or return values of the command
+ * \retval	E_OK	Control device successfully
+ * \retval	E_CLSED	Device is not opened
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid for current control command
+ * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
+ * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
+ * \retval	E_NOSPT	Control command is not supported or not valid
+ */
+
+/**
+ * \fn		int32_t (* dev_uart::uart_write) (const void *data, uint32_t len)
+ * \details	send \ref data through uart with defined \ref len(blocked).
+ * \param[in]	data	pointer to data need to send by uart, must not be NULL
+ * \param[in]	len	length of data to be sent, must > 0
+ * \retval	>0	Byte count that was successfully sent for poll method
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
+ */
+
+/**
+ * \fn		int32_t (* dev_uart::uart_read) (void *data, uint32_t len)
+ * \details	receive \ref data of defined \ref len through uart(blocked).
+ * \param[out]	data	pointer to data need to received by uart, must not be NULL
+ * \param[in]	len	length of data to be received, must > 0
+ * \retval	>0	Byte count that was successfully received for poll method
+ * \retval	E_OBJ	Device object is not valid or not exists
+ * \retval	E_PAR	Parameter is not valid
+ * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
+ */
+/** @} */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief	get an \ref dev_uart "uart device" by uart device id.
+ * 	For how to use uart device hal refer to \ref DEVICE_HAL_UART_DEVSTRUCT "Functions in uart device structure"
+ * \param[in]	uart_id	id of uart, defined by user
+ * \retval	!NULL	pointer to an \ref dev_uart "uart device structure"
+ * \retval	NULL	failed to find the uart device by \ref uart_id
+ * \note	need to implemented by user in user code
+ */
+extern DEV_UART_PTR uart_get_dev(int32_t uart_id);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif /* _DEVICE_HAL_UART_H_ */
diff --git a/bsp/synopsys/embarc/inc/arc/arc.h b/bsp/synopsys/embarc/inc/arc/arc.h
new file mode 100644
index 0000000000..91c0a3850e
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/arc/arc.h
@@ -0,0 +1,436 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-20
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_CORE_COMM
+ * \brief  header file including common core definitions
+ */
+
+ /**
+  * \addtogroup ARC_HAL_CORE_COMM
+  * @{
+  */
+
+
+#ifndef _ARC_HAL_CORE_H_
+#define _ARC_HAL_CORE_H_
+
+#include "inc/arc/arc_feature_config.h"
+
+/**
+ * \name exception number definitions
+ * @{
+ */
+
+/* ARC exception number */
+#define EXC_NO_RESET			(0)	/*!< reset vector, the entry of power up and reset */
+#define EXC_NO_MEM_ERR			(1)	/*!< external memory bus error */
+#define EXC_NO_INS_ERR			(2)	/*!< illegal instruction or illegal instruction sequence */
+#define EXC_NO_MAC_CHK			(3)	/*!< machine check error */
+#define EXC_NO_TLB_MISS_I		(4)	/*!< instruction TLB missing exception, useless without MMU */
+#define EXC_NO_TLB_MISS_D		(5)	/*!< data TLB missing exception, useless without MMU */
+#define EXC_NO_PRO_VIO			(6)	/*!< protection violation */
+#define EXC_NO_PRI_VIO			(7)	/*!< privilege violation */
+#define EXC_NO_SWI			(8)	/*!< software interrupt */
+#define EXC_NO_TRAP			(9)	/*!< trap */
+#define EXC_NO_EXT			(10)	/*!< extension exception */
+#define EXC_NO_DIV_ZER0			(11)	/*!< divide by zero */
+#define EXC_NO_DC_ERR			(12)	/*!< data cache consistency error */
+#define EXC_NO_MAL_ALIGN		(13)	/*!< misaligned data access */
+#define EXC_NO_RESERVE0			(14)	/*!< reserved */
+#define EXC_NO_RESERVE1			(15)	/*!< reserved */
+
+/* extension interrupts */
+#define EXC_NO_16			(16)	/*!< interrupt vector 16 */
+#define EXC_NO_17			(17)	/*!< interrupt vector 17 */
+#define EXC_NO_18			(18)	/*!< interrupt vector 18 */
+#define EXC_NO_19			(19)	/*!< interrupt vector 19 */
+#define EXC_NO_20			(20)	/*!< interrupt vector 20 */
+#define EXC_NO_21			(21)	/*!< interrupt vector 21 */
+#define EXC_NO_22			(22)	/*!< interrupt vector 22 */
+#define EXC_NO_23			(23)	/*!< interrupt vector 23 */
+#define EXC_NO_24			(24)	/*!< interrupt vector 24 */
+#define EXC_NO_25			(25)	/*!< interrupt vector 25 */
+#define EXC_NO_26			(26)	/*!< interrupt vector 26 */
+#define EXC_NO_27			(27)	/*!< interrupt vector 27 */
+#define EXC_NO_28			(28)	/*!< interrupt vector 28 */
+#define EXC_NO_29			(29)	/*!< interrupt vector 29 */
+#define EXC_NO_30			(30)	/*!< interrupt vector 30 */
+#define EXC_NO_31			(31)	/*!< interrupt vector 31 */
+/* ... ARC supports 255 interrupt vectors at most */
+#define EXC_NO_255			(255)	/*!< interrupt vector 255 */
+
+/** @} */
+
+/**
+ * \name exception vector offset
+ * @{
+ */
+#define EXC_NO_TO_OFFSET(no)	(no << 2)
+
+/* ARC exception vector offset */
+#define EXC_VECTOR_RESET		(0x00)	/*!< EXC_NO_RESET offset */
+#define EXC_VECTOR_MEM_ERR		(0x04)	/*!< EXC_NO_MEM_ERR offset */
+#define EXC_VECTOR_INS_ERR		(0x08)	/*!< EXC_NO_INS_ERR offset */
+#define EXC_VECTOR_MAC_CHK		(0x0c)	/*!< EXC_NO_MAC_CHK offset */
+#define EXC_VECTOR_TLB_MISS_I		(0x10)	/*!< EXC_NO_TLB_MISS_I offset */
+#define EXC_VECTOR_TLB_MISS_D		(0x14)	/*!< EXC_NO_TLB_MISS_D offset */
+#define EXC_VECTOR_PRO_VIO		(0x18)	/*!< EXC_NO_PRO_VIO offset */
+#define EXC_VECTOR_PRI_VIO		(0x1c)	/*!< EXC_NO_PRI_VIO offset */
+#define EXC_VECTOR_SWI			(0x20)	/*!< EXC_NO_SWI offset */
+#define EXC_VECTOR_TRAP			(0x24)	/*!< EXC_NO_TRAP offset */
+#define EXC_VECTOR_EXT			(0x28)	/*!< EXC_NO_EXT offset */
+#define EXC_VECTOR_DIV_ZER0		(0x2c)	/*!< EXC_NO_DIV_ZER0 offset */
+#define EXC_VECTOR_DC_ERR		(0x30)	/*!< EXC_NO_DC_ERR offset */
+#define EXC_VECTOR_MAL_ALIGN		(0x34)	/*!< EXC_NO_MAL_ALIGN offset */
+#define EXC_VECTOR_RESERVE0		(0x38)	/*!< EXC_NO_RESERVE0 offset */
+#define EXC_VECTOR_RESERVE1		(0x3c)	/*!< EXC_NO_RESERVE1 offset */
+/** @} */
+
+/**
+ * \name build configuration register
+ * @{
+ */
+#define AUX_BCR_VER			(0x60)	/*!< build configuration register version */
+#define AUX_BCR_BTA			(0x63)	/*!< build configuration for BTA LINK */
+#define AUX_BCR_VECBASE			(0x68)	/*!< build configuration for interrupt vector base */
+#define AUX_BCR_MPU			(0x6d)	/*!< build configuration for memory protection unit */
+#define AUX_BCR_RF			(0x6e)	/*!< build configuration for core registers */
+#define AUX_BCR_D_CACHE			(0x72)	/*!< build configuration for data cache */
+#define AUX_BCR_DCCM			(0x74)	/*!< build configuration for DCCM */
+#define AUX_BCR_TIMERS			(0x75)	/*!< build configuration for processor timers */
+#define AUX_BCR_AP 			(0x76)	/*!< build configuration for actionpoints */
+#define AUX_BCR_I_CACHE			(0x77)	/*!< build configuration for instruction cache */
+#define AUX_BCR_ICCM			(0x78)	/*!< build configuration for ICCM */
+#define AUX_BCR_DSP			(0x7a)	/*!< build configuration for DSP */
+#define AUX_BCR_MUL			(0x7b)	/*!< build configuration for multiply */
+#define AUX_BCR_SWAP			(0x7c)	/*!< build configuration for swap */
+#define AUX_BCR_NORM			(0x7d)	/*!< build configuration for normalize */
+#define AUX_BCR_MIXMAX			(0x7e)	/*!< build configuration for MIN/MAX */
+#define AUX_BCR_BARREL			(0x7f)	/*!< build configuration for barrel shift */
+#define AUX_BCR_ISA			(0xc1)	/*!< build configuration for ISA configuration */
+#define AUX_BCR_STACK			(0xc5)	/*!< build configuration for stack region */
+#define AUX_BCR_ERP			(0xc7)	/*!< build configuration for error protection */
+#define AUX_BCR_FPU			(0xc8)	/*!< build configuration for floating-point unit */
+#define AUX_BCR_CPORT			(0xc9)	/*!< build configuration for code protection */
+#define AUX_BCR_BS			(0xcb)	/*!< build configuration for bitstream */
+#define AUX_BCR_AGU			(0xcc)	/*!< build configuration for address generate unit */
+#define AUX_BCR_DMAC			(0xcd)	/*!< build configuration for DMA */
+#define AUX_BCR_CONNECT_SYSTEM		(0xd0)	/*!< build configuration for arc connect */
+#define AUX_BCR_CONNECT_SEMA		(0xd1)	/*!< build configuration for inter-core semaphore */
+#define AUX_BCR_CONNECT_MESSAGE		(0xd2)	/*!< build configuration for inter-code message */
+#define AUX_BCR_CONNECT_PMU		(0xd3)	/*!< build configuration for power management unit */
+#define AUX_BCR_CONNECT_GFRC		(0xd6)	/*!< build configuration for global free running counter */
+#define AUX_BCR_CAL_STORE		(0xd9)	/*!< build configuration for calibration parameter storage */
+#define AUX_BCR_CONNECT_ICI		(0xe0)	/*!< build configuration for inter-core interrupt unit */
+#define AUX_BCR_CONNECT_ICD		(0xe1)	/*!< build configuration for inter-core debug unit */
+#define AUX_BCR_CONNECT_PDM		(0xe3)	/*!< build configuration for power domain management unit*/
+#define AUX_BCR_RTT			(0xf2)	/*!< build configuration for real-time trace */
+#define AUX_BCR_IRQ			(0xf3)	/*!< build configuration for interrupt */
+#define AUX_BCR_PCT			(0xf5)	/*!< build configuration for performance counters */
+#define AUX_BCR_CC			(0xf6)	/*!< build configuration for performance counters */
+#define AUX_BCR_PDM_DVFS		(0xf7)	/*!< build configuration for PDM and DVFS */
+
+#define AUX_BCR_SEC_BUILD		(0xdb)
+
+/* from 0xF5 and 0xF6 */
+
+#define AUX_BCR_IFQUEUE			(0xfe)	/*!< build configuration for instruction fetch queue */
+#define AUX_BCR_SMART			(0xff)   /*!< build configuration for SmaRT debug feature */
+/** @} */
+
+
+#define	AUX_SEC_STAT			(0x9)
+#define AUX_SEC_STAT_BIT_SSC		(0)
+#define AUX_SEC_STAT_BIT_NSRT		(1)
+#define AUX_SEC_STAT_BIT_NSRU		(2)
+#define AUX_SEC_STAT_BIT_IRM		(3)
+#define AUX_SEC_STAT_BIT_SUE		(4)
+#define AUX_SEC_STAT_BIT_NIC		(5)
+
+/**
+ * \name status register STATUS32
+ * @{
+ */
+#define AUX_STATUS32			(0xa)
+#define AUX_STATUS32_P0			(0xb)
+
+/* STATUS32 bit-field definition */
+#define AUX_STATUS_BIT_AE		(5)	/*!< processor is in an exception */
+#define AUX_STATUS_BIT_DE		(6)	/*!< delayed branch is pending */
+#define AUX_STATUS_BIT_U		(7)	/*!< user mode */
+#define AUX_STATUS_BIT_L		(12)	/*!< zero-overhead loop enable */
+#define AUX_STATUS_BIT_IE		(31)	/*!< interrupt enable */
+
+/* masks correspond to STATUS32 bit-field */
+#define AUX_STATUS_MASK_AE		(1<<AUX_STATUS_BIT_AE)	/*!< mask of AUX_STATUS_BIT_AE */
+#define AUX_STATUS_MASK_DE		(1<<AUX_STATUS_BIT_DE)	/*!< mask of AUX_STATUS_BIT_DE */
+#define AUX_STATUS_MASK_U		(1<<AUX_STATUS_BIT_U)	/*!< mask of AUX_STATUS_BIT_U */
+#define AUX_STATUS_MASK_L		(1<<AUX_STATUS_BIT_L)	/*!< mask of AUX_STATUS_BIT_L */
+#define AUX_STATUS_MASK_IE		(1<<AUX_STATUS_BIT_IE)	/*!< mask of AUX_STATUS_BIT_IE */
+/** @} */
+
+/**
+ * \name zero overhead loop auxiliary register
+ * @{
+ */
+#define AUX_LP_START			(0x2) 	/*!< loop start address (32-bit) */
+#define AUX_LP_END			(0x3) 	/*!< loop end address (32-bit) */
+/** @} */
+
+#define AUX_USER_SP			(0xd)	/*!< user-mode stack pointer */
+/* added in silverstone */
+#define AUX_KERNEL_SP			(0x38)	/*!< kernel-mode stack pointer */
+#define AUX_SEC_U_SP			(0x39)	/*!< secure user-mode stack pointer */
+#define AUX_SEC_K_SP			(0x3a)	/*!< secure kernel-mode stack pointer */
+
+/* additional stack checkingh registers for secure mode */
+#define AUX_S_USTACK_BASE		(0x263)
+#define AUX_S_USTACK_TOP		(0x262)
+
+#define AUX_S_KSTACK_BASE		(0x267)
+#define AUX_S_KSTACK_TOP		(0x266)
+
+/**
+ * \name auxiliary register for hardware counter 0 and 1
+ * @{
+ */
+#define AUX_TIMER0_LIMIT		(0x23)	/*!< timer 0 limit value */
+#define AUX_TIMER0_CTRL			(0x22)	/*!< timer 0 control value */
+#define AUX_TIMER0_CNT			(0x21)	/*!< timer 0 count value */
+#define AUX_TIMER1_LIMIT		(0x102)	/*!< timer 1 limit value */
+#define AUX_TIMER1_CTRL			(0x101)	/*!< timer 1 control value */
+#define AUX_TIMER1_CNT			(0x100)	/*!< timer 1 count value */
+/** @} */
+
+#define AUX_SECURE_TIMER0_CNT		(0x106) /*!< secure timer 0 count value */
+#define AUX_SECURE_TIMER0_CTRL		(0x107) /*!< secure timer 0 control value */
+#define AUX_SECURE_TIMER0_LIMIT		(0x108) /*!< secure timer 0 limit value */
+#define AUX_SECURE_TIMER1_CNT		(0x109) /*!< secure timer 1 count value */
+#define AUX_SECURE_TIMER1_CTRL		(0x10a) /*!< secure timer 1 control value */
+#define AUX_SECURE_TIMER1_LIMIT		(0x10b) /*!< secure timer 1 limit value */
+
+
+/**
+ * \name auxiliary register for real-time counter
+ * @{
+ */
+#define AUX_RTC_CTRL			(0x103)	/*!< real-time counter control register */
+#define AUX_RTC_LOW			(0x104)	/*!< real-time counter count low register */
+#define AUX_RTC_HIGH			(0x105)	/*!< real-time counter count high register */
+/** @} */
+
+/**
+ * \name indexed table auxiliary register
+ * @{
+ */
+#define AUX_JLI_BASE			(0x290)	/*!< jump and link indexed base address */
+#define AUX_LDI_BASE			(0x291)	/*!< load indexed base address */
+#define AUX_EI_BASE			(0x292)	/*!< execute indexed base address */
+/** @} */
+
+/**
+ * \name baseline auxiliary register set
+ * @{
+ */
+/* to be added */
+#define AUX_ERRET			(0x400)	/*!< exception return address */
+#define AUX_ERBTA			(0x401)	/*!< BTA saved on exception entry */
+#define AUX_ERSTATUS			(0x402)	/*!< STATUS32 saved on exception */
+#define AUX_ECR				(0x403)	/*!< exception cause register */
+#define AUX_EFA				(0x404) /*!< exception fault address */
+#define AUX_BTA				(0x412)	/*!< branch target address */
+/** @} */
+
+/* New register to control which exceptions can be handled in NS mode */
+#define AUX_ERSEC_STAT			(0x406)
+#define AUX_ERSEC_STAT_BIT_ERM		31
+#define AUX_SEC_EXCEPT			(0x407)
+
+/**
+ * \name MPU register set
+ * @{
+ */
+#define AUX_MPU_EN      		(0x409)	/*!< MPU enable register  */
+#define AUX_MPU_ECR			(0x420)	/*!< MPU exception cause */
+#define AUX_MPU_RDB0    		(0x422)	/*!< MPU region descriptor base 0 */
+#define AUX_MPU_RDP0    		(0x423)	/*!< MPU region descriptor permission 0 */
+
+/* MPU register set in silverstone */
+#define AUX_MPU_INDEX			(0x448)
+#define AUX_MPU_INDEX_BIT_D		(31)
+#define AUX_MPU_RSTART			(0x449)
+#define AUX_MPU_REND			(0x44a)
+#define AUX_MPU_RPER			(0x44b)
+#define AUX_MPU_RPER_BIT_S		(15)
+#define AUX_MPU_PROBE			(0x44c)
+#define AUX_MPU_ECR			(0x420)
+
+#define AUX_NSC_TABLE_BASE		(0x269)
+#define AUX_NSC_TABLE_TOP		(0x268)
+
+/** @} */
+
+/**
+ * \name exception cause register (ECR) bit-field definition
+ * @{
+ */
+#define AUX_ECR_VEC_MASK		(0xff0000)	/*!< [23:16] = exception vector */
+#define AUX_ECR_CODE_MASK		(0x00ff00)	/*!< [15: 8] = exception cause code */
+#define AUX_ECR_PARAM_MASK		(0x0000ff)	/*!< [ 7: 0] = exception parameters */
+/** @} */
+
+/**
+ * \name exception vector number and cause code
+ * @{
+ */
+#define AUX_ECR_V_INSN_ERR		(0x02)	/*!< vector number of illegal instruction */
+#define AUX_ECR_V_MACH_CHK		(0x03)	/*!< vector number of machine check */
+#define AUX_ECR_V_ITLB_MISS		(0x04)	/*!< vector number of instruction TLB missing exception */
+#define AUX_ECR_V_DTLB_MISS		(0x05)	/*!< vector number of data TLB missing exception */
+#define AUX_ECR_V_PROTV			(0x06)	/*!< vector number of protection violation */
+#define AUX_ECR_V_TRAP			(0x09)	/*!< vector number of trap */
+#define AUX_ECR_V_MISALIG_DATA 		(0x0d)	/*!< vector number of misaligned data access */
+
+#define AUX_ECR_C_PROTV_INST_FETCH	(0x00)	/*!< cause code of instruction fetch (protection violation) */
+#define AUX_ECR_C_PROTV_LOAD		(0x01)	/*!< cause code related memory read (protection violation) */
+#define AUX_ECR_C_PROTV_STORE		(0x02)	/*!< cause code related memory write (protection violation) */
+#define AUX_ECR_C_PROTV_XCHG		(0x03)	/*!< cause code related read-modify-write (protection violation) */
+
+#define AUX_ECR_C_MCHK_DUP_TLB		(0x01)	/*!< \todo definition is to be added. */
+
+#define AUX_ECR_C_BIT_DTLB_LD_MISS	(8)	/*!< \todo definition is to be added. */
+#define AUX_ECR_C_BIT_DTLB_ST_MISS	(9)	/*!< \todo definition is to be added. */
+/** @} */
+
+/**
+ * \name interrupt related auxiliary register
+ * @{
+ */
+#define AUX_IRQ_CTRL			(0xe)	/*!< interrupt context saving control register */
+#define AUX_INT_VECT_BASE		(0x25)	/*!< interrupt vector base register */
+#define AUX_INT_VECT_BASE_S		(0x26)	/*!< secure interrupt vector based register */
+#define AUX_IRQ_ACT			(0x43)	/*!< active interrupts register */
+#define AUX_IRQ_CAUSE			(0x40a)	/*!< interrupt cause register */
+#define AUX_IRQ_SELECT			(0x40b)	/*!< interrupt select register */
+#define AUX_IRQ_PRIORITY		(0x206)	/*!< interrupt priority register */
+#define AUX_IRQ_PRIORITY_BIT_S		(0x8)	/*!< S bit offset in interrupt priority register */
+#define AUX_IRQ_ENABLE			(0x40c)	/*!< interrupt enable register */
+#define AUX_IRQ_TRIGGER			(0x40d)	/*!< interrupt trigger: level or pulse */
+#define AUX_IRQ_PENDING			(0x416)	/*!< interrupt pending register */
+#define AUX_IRQ_PLUSE_CLR		(0x415)	/*!< interrupt pulse cancel register */
+#define AUX_IRQ_STATUS			(0x40f)	/*!< interrupt status register */
+#define AUX_IRQ_PRI_PENDING		(0x200)	/*!< interrupt priority pending register */
+#define AUX_IRQ_HINT			(0x201)	/*!< software interrupt trigger */
+/** @} */
+
+/**
+ * \name cache related auxiliary register
+ * @{
+ */
+#define AUX_IC_IVIC			(0x10)	/*!< invalidate instruction cache */
+#define AUX_IC_CTRL			(0x11)	/*!< instruction cache control register */
+#define AUX_IC_LIL			(0x13)	/*!< lock instruction cache line */
+#define AUX_IC_IVIL			(0x19)	/*!< invalidate instruction cache line */
+#define AUX_IC_RAM_ADDR			(0x1a)	/*!< instruction cache external access address */
+#define AUX_IC_TAG			(0x1b)	/*!< instruction cache tag access */
+#define AUX_IC_DATA			(0x1d)	/*!< instruction cache data access */
+#define AUX_DC_IVDC			(0x47)	/*!< invalidate data cache */
+#define AUX_DC_CTRL			(0x48)	/*!< data cache control register */
+#define AUX_DC_LDL			(0x49)	/*!< lock data cache line */
+#define AUX_DC_IVDL			(0x4a)	/*!< invalidate data cache line */
+#define AUX_DC_FLSH			(0x4b)	/*!< flush data cache */
+#define AUX_DC_FLDL			(0x4c)	/*!< flush data line */
+#define AUX_DC_RAM_ADDR			(0x58)	/*!< data cache external access address */
+#define AUX_DC_TAG			(0x59)	/*!< data cache tag access */
+#define AUX_DC_DATA			(0x5b)	/*!< data cache data access */
+/** @} */
+
+/**
+ * \name dmac related auxiliary register
+ * @{
+ */
+#define AUX_DMACTRL			(0x680)	/*!< DMA control register */
+#define AUX_DMACENB			(0x681)	/*!< DMA channel enable register */
+#define AUX_DMACDSB			(0x682)	/*!< DMA channel disable register */
+#define AUX_DMACHPRI			(0x683)	/*!< DMA channel high priority level register */
+#define AUX_DMACNPRI			(0x684)	/*!< DMA channel normal priority level register */
+#define AUX_DMACREQ			(0x685)	/*!< DMA channel transfer request register */
+#define AUX_DMACSTAT0			(0x686)	/*!< DMA channel status register 0 */
+#define AUX_DMACSTAT1			(0x687)	/*!< DMA channel status register 1 */
+#define AUX_DMACIRQ			(0x688)	/*!< DMA channel interrupt request status/clear register */
+#define AUX_DMACBASE			(0x689)	/*!< DMA channel structure register base address */
+#define AUX_DMACRST			(0x68A)	/*!< DMA channel reset register base address */
+
+#define AUX_DMACTRL0			(0x690)	/*!< DMA channel 0 control register when mapped in aux */
+#define AUX_DMASAR0			(0x691)	/*!< DMA channel 0 source address register when mapped in aux */
+#define AUX_DMADAR0			(0x692)	/*!< DMA channel 0 destination register when mapped in aux */
+#define AUX_DMACTRLx			(AUX_DMACTRL0)	/*!< DMA channel 0 control register when mapped in aux */
+#define AUX_DMASARx			(AUX_DMASAR0)	/*!< DMA channel 0 source address register when mapped in aux */
+#define AUX_DMADARx			(AUX_DMADAR0)	/*!< DMA channel 0 destination register when mapped in aux */
+/** @} */
+
+
+
+/**
+ * \name other auxiliary register
+ * @{
+ */
+#define AUX_IDENTITY			(0x4) 	/*!< identity register */
+#define AUX_DMP_PERIPHERAL		(0x20a) /*!< peripheral memory region */
+#define AUX_XFLAGS			(0x44f) /*!< user extension flags register */
+#define AUX_MCIP_CMD			(0x600) /*!< \todo definition is to be added. */
+#define AUX_MCIP_WDATA			(0x601) /*!< \todo definition is to be added. */
+#define AUX_MCIP_READBACK		(0x602) /*!< \todo definition is to be added. */
+#define AUX_SMART_CONTROL		(0x700) /*!< \todo definition is to be added. */
+#define AUX_SMART_DATA			(0x701) /*!< \todo definition is to be added. */
+
+/** @} */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __ASSEMBLY__
+/* add type definition and function declaration here */
+#endif	/* assembly */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif	/* _ARC_HAL_CORE_H_ */
+
+ /**  @} */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_asm_common.h b/bsp/synopsys/embarc/inc/arc/arc_asm_common.h
new file mode 100644
index 0000000000..68d9ca4e67
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/arc/arc_asm_common.h
@@ -0,0 +1,541 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_MISC
+ * \brief common macro definitions for assembly file
+ */
+/** @cond ARC_HAL_ASM_COMMON */
+
+#ifndef _ARC_HAL_ASM_COMMON_H_
+#define _ARC_HAL_ASM_COMMON_H_
+
+#include "embARC_BSP_config.h"
+#include "arc_feature_config.h"
+
+/* Note on the LD/ST addr modes with addr reg wback
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+#if defined(__GNU__)
+.macro PUSH reg
+	st.a	\reg, [sp, -4]
+.endm
+
+.macro PUSHAX aux
+	lr	r10, [\aux]
+	PUSH	r10
+.endm
+
+.macro POP reg
+	ld.ab	\reg, [sp, 4]
+.endm
+
+.macro POPAX aux
+	POP	r10
+	sr	r10, [\aux]
+.endm
+#else
+.macro PUSH, reg
+	st.a	reg, [sp, -4]
+.endm
+
+.macro PUSHAX, aux
+	lr	r10, [aux]
+	PUSH	r10
+.endm
+
+.macro POP, reg
+    ld.ab   reg, [sp, 4]
+.endm
+
+.macro POPAX, aux
+	POP	r10
+	sr	r10, [aux]
+.endm
+#endif
+
+/*--------------------------------------------------------------
+ * Helpers to save/restore callee-saved regs:
+ * used by several macros below
+ *-------------------------------------------------------------*/
+.macro SAVE_CALLEE_REGS
+	PUSH	r13
+	PUSH	r14
+	PUSH	r15
+#ifndef ARC_FEATURE_RF16
+	PUSH	r16
+	PUSH	r17
+	PUSH	r18
+	PUSH	r19
+	PUSH	r20
+	PUSH	r21
+	PUSH	r22
+	PUSH	r23
+	PUSH	r24
+	PUSH	r25
+#endif
+.endm
+
+.macro RESTORE_CALLEE_REGS
+#ifndef ARC_FEATURE_RF16
+	POP	r25
+	POP	r24
+	POP	r23
+	POP	r22
+	POP	r21
+	POP	r20
+	POP	r19
+	POP	r18
+	POP	r17
+	POP	r16
+#endif
+	POP	r15
+	POP	r14
+	POP	r13
+.endm
+
+.macro CLEAR_CALLEE_REGS
+#ifndef ARC_FEATURE_RF16
+	mov	r25, 0
+	mov	r24, 0
+	mov	r23, 0
+	mov	r22, 0
+	mov	r21, 0
+	mov	r20, 0
+	mov	r19, 0
+	mov	r18, 0
+	mov	r17, 0
+	mov	r16, 0
+#endif
+	mov	r15, 0
+	mov	r14, 0
+	mov	r13, 0
+.endm
+
+.macro CLEAR_SCRATCH_REGS
+	mov	r1, 0
+	mov 	r2, 0
+	mov	r3, 0
+	mov	r4, 0
+	mov	r5, 0
+	mov	r6, 0
+	mov	r7, 0
+	mov	r8, 0
+	mov 	r9, 0
+	mov	r10, 0
+	mov	r11, 0
+	mov	r12, 0
+
+	mov 	fp, 0
+	mov 	r29, 0
+	mov 	r30, 0
+.endm
+
+
+.macro SAVE_LP_REGS
+	PUSH	r60
+	PUSHAX	AUX_LP_START
+	PUSHAX	AUX_LP_END
+.endm
+
+.macro RESTORE_LP_REGS
+	POPAX	AUX_LP_END
+	POPAX	AUX_LP_START
+	POP	r10
+/* must not use the LP_COUNT register(r60) as the destination of multi-cycle instruction */
+	mov	r60, r10
+
+.endm
+
+.macro SAVE_R0_TO_R12
+	PUSH    r0
+	PUSH    r1
+	PUSH    r2
+	PUSH    r3
+#ifndef ARC_FEATURE_RF16
+ 	PUSH    r4
+ 	PUSH    r5
+ 	PUSH    r6
+ 	PUSH    r7
+ 	PUSH    r8
+ 	PUSH    r9
+#endif
+	PUSH    r10
+	PUSH    r11
+	PUSH    r12
+.endm
+
+.macro RESTORE_R0_TO_R12
+	POP	r12
+	POP	r11
+	POP	r10
+#ifndef ARC_FEATURE_RF16
+	POP	r9
+	POP	r8
+	POP	r7
+	POP	r6
+	POP	r5
+	POP	r4
+#endif
+	POP	r3
+	POP	r2
+	POP	r1
+	POP	r0
+.endm
+
+.macro SAVE_CODE_DENSITY
+	PUSHAX	AUX_JLI_BASE
+	PUSHAX	AUX_LDI_BASE
+	PUSHAX	AUX_EI_BASE
+.endm
+
+.macro RESTORE_CODE_DENSITY
+	POPAX	AUX_EI_BASE
+	POPAX	AUX_LDI_BASE
+	POPAX	AUX_JLI_BASE
+.endm
+
+/* todo: check the contents of NON_SCRATCH_REGS in debug */
+.macro SAVE_NONSCRATCH_REGS
+/* r0-r12 are saved by caller function */
+	PUSH	gp
+	PUSH	fp
+	PUSH	blink
+	SAVE_CALLEE_REGS
+.endm
+
+.macro RESTORE_NONSCRATCH_REGS
+	RESTORE_CALLEE_REGS
+	POP	blink
+	POP	fp
+	POP	gp
+.endm
+
+
+.macro SAVE_FIQ_EXC_REGS
+#ifndef ARC_FEATURE_RGF_BANKED_REGS
+	SAVE_R0_TO_R12
+
+	PUSH	gp
+	PUSH	fp
+	PUSH	r30		/* general purpose */
+	PUSH	blink
+
+#else
+#if ARC_FEATURE_RGF_BANKED_REGS != 4 && ARC_FEATURE_RGF_BANKED_REGS != 8 && \
+	ARC_FEATURE_RGF_BANKED_REGS != 16  && ARC_FEATURE_RGF_BANKED_REGS != 32
+#error	"unsupported ARC_FEATURE_RGF_BANKED_REGS"
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 || \
+	ARC_FEATURE_RGF_BANKED_REGS == 16
+	PUSH	r4
+	PUSH	r5
+	PUSH	r6
+	PUSH	r7
+	PUSH	r8
+	PUSH	r9
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8
+	PUSH	r10
+	PUSH	r11
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4
+	PUSH	r12
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8
+	PUSH	gp
+	PUSH	fp
+	PUSH	r30		/* general purpose */
+	PUSH	blink
+#endif
+
+#endif /* #ifndef ARC_FEATURE_RGF_BANKED_REGS */
+
+#ifdef ARC_FEATURE_CODE_DENSITY
+	SAVE_CODE_DENSITY
+#endif
+	SAVE_LP_REGS
+.endm
+
+.macro RESTORE_FIQ_EXC_REGS
+	RESTORE_LP_REGS
+#ifdef	ARC_FEATURE_CODE_DENSITY
+	RESTORE_CODE_DENSITY
+#endif
+
+#ifndef ARC_FEATURE_RGF_BANKED_REGS
+	POP	blink
+	POP	r30
+	POP	fp
+	POP	gp
+
+	RESTORE_R0_TO_R12
+#else
+
+#if ARC_FEATURE_RGF_BANKED_REGS != 4 && ARC_FEATURE_RGF_BANKED_REGS != 8 && \
+	ARC_FEATURE_RGF_BANKED_REGS != 16 && ARC_FEATURE_RGF_BANKED_REGS != 32
+#error	"unsupported ARC_FEATURE_RGF_BANKED_REGS"
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8
+	POP	blink
+	POP	r30
+	POP	fp
+	POP	gp
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4
+	POP	r12
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8
+	POP		r11
+	POP		r10
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 || \
+	ARC_FEATURE_RGF_BANKED_REGS == 16
+	POP		r9
+	POP		r8
+	POP		r7
+	POP		r6
+	POP		r5
+	POP		r4
+#endif
+
+#endif  /* #ifndef ARC_FEATURE_RGF_BANKED_REGS */
+.endm
+
+/* normal interrupt prologue, pc, status and r0-r11 are saved by hardware */
+.macro INTERRUPT_PROLOGUE
+	PUSH	r12
+	PUSH	gp
+	PUSH	fp
+	PUSH	ilink
+	PUSH	r30
+
+	sub	sp, sp, 4 /* skip bta */
+.endm
+
+
+/* normal interrupt epilogue, pc, status and r0-r11 are restored by hardware */
+.macro INTERRUPT_EPILOGUE
+	add	sp, sp, 4 /* skip bta */
+
+	POP	r30
+	POP	ilink
+	POP	fp
+	POP	gp
+	POP	r12
+.endm
+
+#if SECURESHIELD_VERSION == 2
+/* exception prologue, create the same frame of interrupt manually */
+.macro EXCEPTION_PROLOGUE
+	st.as	r10, [sp, -6]	/* save r10 first, free up a register*/
+
+	PUSHAX	AUX_ERSTATUS
+	sub 	sp, sp, 4 /* slot for SEC_STAT */
+	PUSHAX	AUX_ERRET
+
+	PUSH	blink
+
+	PUSH	r11
+	sub	sp, sp, 4 /* r10 is  pushed before */
+#ifndef ARC_FEATURE_RF16
+	PUSH	r9
+	PUSH	r8
+	PUSH	r7
+	PUSH	r6
+	PUSH	r5
+	PUSH	r4
+#endif
+	PUSH	r3
+	PUSH	r2
+	PUSH	r1
+	PUSH	r0
+
+#ifdef ARC_FEATURE_CODE_DENSITY
+	SAVE_CODE_DENSITY
+#endif
+	SAVE_LP_REGS
+
+	PUSH	r12
+	PUSH	gp
+	PUSH	fp
+	PUSH	ilink
+	PUSH	r30
+
+	PUSHAX	AUX_ERBTA
+.endm
+
+/* exception epilogue, restore the same frame of interrupt manually */
+.macro EXCEPTION_EPILOGUE
+	POPAX	AUX_ERBTA
+
+	POP	r30
+	POP	ilink
+	POP	fp
+	POP	gp
+	POP	r12
+
+	RESTORE_LP_REGS
+
+#ifdef ARC_FEATURE_CODE_DENSITY
+	RESTORE_CODE_DENSITY
+#endif
+	POP	r0
+	POP	r1
+	POP	r2
+	POP	r3
+#ifndef ARC_FEATURE_RF16
+	POP	r4
+	POP	r5
+	POP	r6
+	POP	r7
+	POP	r8
+	POP	r9
+#endif
+	add	sp, sp, 4 /* r10 will be popped finally */
+	POP	r11
+
+	POP	blink
+
+
+	POPAX	AUX_ERRET
+	add 	sp, sp, 4  /* slot for SEC_STAT */
+	POPAX	AUX_ERSTATUS
+
+	ld.as	r10, [sp, -6]	/* restore r10 */
+.endm
+#else /* normal version */
+/* exception prologue, create the same frame of interrupt manually */
+.macro EXCEPTION_PROLOGUE
+#ifdef	ARC_FEATURE_CODE_DENSITY
+	st.as	r10, [sp, -11]	/* save r10 first, free up a register*/
+#else
+	st.as	r10, [sp, -8]
+#endif
+	PUSHAX	AUX_ERSTATUS
+	PUSHAX	AUX_ERRET
+
+#ifdef ARC_FEATURE_CODE_DENSITY
+	SAVE_CODE_DENSITY
+#endif
+	SAVE_LP_REGS
+
+	PUSH	blink
+
+	PUSH	r11
+	sub	sp, sp, 4 /* r10 is  pushed before */
+#ifndef ARC_FEATURE_RF16
+	PUSH	r9
+	PUSH	r8
+	PUSH	r7
+	PUSH	r6
+	PUSH	r5
+	PUSH	r4
+#endif
+	PUSH	r3
+	PUSH	r2
+	PUSH	r1
+	PUSH	r0
+
+	PUSH	r12
+	PUSH	gp
+	PUSH	fp
+	PUSH	ilink
+	PUSH	r30
+
+	PUSHAX	AUX_ERBTA
+.endm
+
+/* exception epilogue, restore the same frame of interrupt manually */
+.macro EXCEPTION_EPILOGUE
+	POPAX	AUX_ERBTA
+
+	POP	r30
+	POP	ilink
+	POP	fp
+	POP	gp
+	POP	r12
+
+	POP	r0
+	POP	r1
+	POP	r2
+	POP	r3
+#ifndef ARC_FEATURE_RF16
+	POP	r4
+	POP	r5
+	POP	r6
+	POP	r7
+	POP	r8
+	POP	r9
+#endif
+	add	sp, sp, 4 /* r10 will be popped finally */
+	POP	r11
+
+	POP	blink
+
+	RESTORE_LP_REGS
+
+#ifdef ARC_FEATURE_CODE_DENSITY
+	RESTORE_CODE_DENSITY
+#endif
+
+	POPAX	AUX_ERRET
+	POPAX	AUX_ERSTATUS
+
+#ifdef	ARC_FEATURE_CODE_DENSITY
+	ld.as	r10, [sp, -11]	/* restore r10 */
+#else
+	ld.as	r10, [sp, -8]
+#endif
+.endm
+
+#endif /* SECURESHIELD_VERSION == 2 */
+
+#endif	/* _ARC_HAL_ASM_COMMON_H */
+/** @endcond */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_builtin.h b/bsp/synopsys/embarc/inc/arc/arc_builtin.h
new file mode 100644
index 0000000000..d9b76124ff
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/arc/arc_builtin.h
@@ -0,0 +1,301 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-12
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_BUILTIN
+ * \brief header file of builtin and helper functions
+ *
+ * The Metaware toolchain and the GNU toolchain are supported. The details please go to see the file.
+ */
+
+/**
+ * \addtogroup	ARC_HAL_BUILTIN
+ * @{
+ */
+
+#ifndef _ARC_HAL_BUILTIN_H_
+#define _ARC_HAL_BUILTIN_H_
+
+#include "inc/embARC_toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__MW__)	/* Metaware toolchain */
+
+#define _arc_nop			_nop 	/*!< no operation, generate a nop instruction produces a single NOP instruction in the compiled code */
+
+#define _arc_brk			_brk 	/*!< generate a brk instruction */
+
+#define _arc_clri			_clri  	/*!< generate a clri instruction */
+
+#define _arc_seti(c)			_seti(c) /*!< generate a seti instruction */
+
+#define	_arc_core_write(regno, val)	_core_write(val, regno)	/*!< write core register */
+
+#define _arc_core_read(regno)		_core_read(regno)	/*!< read core register */
+
+#define _arc_lr_reg(aux)		_lr(aux)	/*!< read auxiliary register */
+
+#define _arc_sr_reg(aux, val)		_sr(val, aux)	/*!< write auxiliary register */
+
+#define _arc_sleep(a)			_sleep(a)	/*!< generate a sleep instruction */
+
+#define _arc_flag(a)			_flag(a)	/*!< generate a flag instruction */
+
+#define _arc_kflag(a)
+
+#define _arc_sync			_sync 		/*!< generate a sync instruction */
+
+/*
+ * !< _arc_usually (expr) evaluates expression expr and
+ * informs the compiler that the value is usually true.
+ */
+#define _arc_usually(a)			_Usually((a))
+
+/*
+ * !< _arc_rarely (expr) evaluates expression expr and
+ * informs the compiler that the value is rarely true.
+ */
+#define _arc_rarely(a)			_Rarely((a))
+
+#if 0
+/**
+ * \brief 	Reverses the byte order of the 16-bit operand,
+ *  		reversing the endianness of the value.
+ *    		Not for ARC HS family
+ */
+#define _arc_swap16(a)			_swap16(a)
+/**
+ * \brief 	Reverses the byte order of the 32-bit operand,
+ *  		reversing the endianness of the value.
+ *    		Not for ARC HS family
+ */
+#define _arc_swap32(a)			_swap32(a)
+#else
+Inline uint32_t _arc_swap32(uint32_t val) {
+	register uint32_t v;
+	__asm__ volatile ("swape %0, %1" :"=r"(v): "r"(val));
+	return v;
+}
+
+Inline uint16_t _arc_swap16(uint32_t val) {
+	register uint32_t temp;
+	register uint32_t v;
+	__asm__ volatile ("swape %0, %1" :"=r"(temp): "r"(val));
+	__asm__ volatile ("lsr16 %0, %1" :"=r"(v): "r"(temp));
+	return (unsigned short)v;
+}
+#endif
+
+/**
+ * \brief 	Each call to _swi() generates one
+ * 			software interrupt instruction (SWI) for processors
+ * 			to support the SWI instruction.
+ */
+#define _arc_swi				_swi
+
+/* \todo add more builtin functions of metaware tool */
+
+#elif defined (__GNU__) /* GNU toolchain */
+
+#define _arc_nop				__builtin_arc_nop
+#define _arc_brk				__builtin_arc_brk
+#define _arc_seti(c)				__builtin_arc_seti(c)
+#define _arc_core_write(regno, val)		__builtin_arc_core_write(regno,val)
+#define _arc_core_read(regno)			__builtin_arc_core_read(regno)
+#define _arc_flag(a)				__builtin_arc_flag(a)
+#define _arc_kflag(a)				__builtin_arc_kflag(a)
+#define _arc_lr_reg(aux)			__builtin_arc_lr(aux)
+/* don't uncomment this now */
+//#define _arc_sr_reg(aux, val)			__builtin_arc_sr(aux, val)
+#define _arc_sleep(a)				__builtin_arc_sleep(a)
+//#define _arc_sync				__builtin_arc_sync
+
+/**
+ * \brief _arc_usually (expr) evaluates expression expr and
+ * 		  informs the compiler that the value is usually true.
+ */
+#define _arc_usually(a)				__builtin_expect((int)(a), 1)
+
+/**
+ * \brief _arc_rarely (expr) evaluates expression expr and
+ *	informs the compiler that the value is rarely true.
+ */
+#define _arc_rarely(a)				__builtin_expect((int)(a), 0)
+
+/**
+ * \brief 	Each call to _swi() generates one
+ * 			software interrupt instruction (SWI) for processors
+ * 			to support the SWI instruction.
+ */
+#define _arc_swi 				__builtin_arc_swi
+
+Inline uint32_t _arc_clri(void) {
+	register uint32_t v;
+	__asm__ volatile ("clri %0" :"=r"(v));
+	return v;
+
+}
+/* \todo add more builtin functions of gnu tool */
+
+Inline uint32_t _arc_swap32(uint32_t val) {
+	register uint32_t v;
+	__asm__ volatile ("swape %0, %1" :"=r"(v): "r"(val));
+	return v;
+}
+
+Inline uint16_t _arc_swap16(uint32_t val) {
+	register uint32_t temp;
+	register uint32_t v;
+	__asm__ volatile ("swape %0, %1" :"=r"(temp): "r"(val));
+	__asm__ volatile ("lsr16 %0, %1" :"=r"(v): "r"(temp));
+	return (unsigned short)v;
+}
+
+Inline void _arc_sync(void) {
+	__asm__ volatile ("sync");
+}
+
+/**
+ * \note Following is a workaround for arc gcc
+ *       built-in function __builtin_arc_sr.
+ *       But it is wrong in GCC arc-4.8-R3-rc3 and shouldn't be used.
+ */
+
+/*
+ * The auxiliary register address is specified as a long immediate operand by caller.
+ * e.g.
+ *    write_aux_reg(0x69, some_val);
+ * This generates the tightest code.
+ */
+#define write_aux_reg(reg_imm, val)	\
+({					\
+	Asm(		\
+	"	sr   %0, [%1]	\n"	\
+	:				\
+	: "ir"(val), "r"(reg_imm));	\
+})
+
+#define _arc_sr_reg(aux, val)			write_aux_reg(aux, val)
+
+#endif
+
+/* \todo add more helper functions here, such as memory operation */
+
+#define _arc_aux_read(aux)			_arc_lr_reg(aux)
+#define _arc_aux_write(aux, val)		_arc_sr_reg(aux, val)
+
+/**
+ * \name cache related helper function
+ * @{
+ */
+
+/**
+ * \brief  read memory and bypass the cache
+ * \param[in] ptr memory address
+ * \return value in the memory
+ */
+Inline uint32_t _arc_read_uncached_32(void *ptr)
+{
+	uint32_t __ret;
+	Asm("ld.di %0, [%1]":"=r"(__ret):"r"(ptr));
+	return __ret;
+}
+
+/**
+ * \brief  write memory and bypass the cache
+ * \param[in] ptr memory address
+ * \param[in] data  vaule to be written
+ */
+Inline void _arc_write_uncached_32(void *ptr, uint32_t data)
+{
+	Asm("st.di %0, [%1]":: "r"(data), "r"(ptr));
+}
+
+/**
+ * \brief  read memory with cache
+ * \param[in] ptr memory address
+ * \returns value in the memory
+ */
+Inline uint32_t _arc_read_cached_32(void *ptr)
+{
+	uint32_t __ret;
+	Asm("ld %0, [%1]":"=r"(__ret):"r"(ptr));
+	return __ret;
+}
+
+/**
+ * \brief  read memory with cache
+ * \param[in] ptr memory address
+ * \param[in] data vaule to be written
+ * \return description
+ */
+Inline void _arc_write_cached_32(void *ptr, uint32_t data)
+{
+	Asm("st %0, [%1]":: "r"(data), "r"(ptr));
+}
+
+/**
+ * \brief go to main function with proper arguments
+ * \param  argc argument count
+ * \param  argv argument content array
+ * \retval return value of main function
+ */
+Inline int32_t _arc_goto_main(int argc, char **argv) {
+	int __ret;
+	__asm__ volatile(
+		"mov %%r0, %1\n"
+		"mov %%r1, %2\n"
+		"push_s %%blink\n"
+		"jl main\n"
+		"pop_s %%blink\n"
+		"mov %0, %%r0"
+		:"=r"(__ret): "r"(argc), "r"(argv));
+	return (int)__ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#if defined(LIB_SECURESHIELD) && defined(LIB_SECURESHIELD_OVERRIDES) && (SECURESHIELD_VERSION == 1)
+#define OVERRIDE_ARC_HAL_BUILTIN_H
+#include "secureshield_overrides.h"
+#endif
+
+/** @} */
+#endif /* _ARC_HAL_BUILTIN_H_ */
+/** @} */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_cache.h b/bsp/synopsys/embarc/inc/arc/arc_cache.h
new file mode 100644
index 0000000000..dfbc7df9a5
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/arc/arc_cache.h
@@ -0,0 +1,321 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	ARC_HAL_MISC_CACHE
+ * \brief header file of cache module
+ */
+
+#ifndef _ARC_HAL_CACHE_H_
+#define _ARC_HAL_CACHE_H_
+
+#include "inc/embARC_toolchain.h"
+#include "inc/arc/arc.h"
+#include "inc/arc/arc_builtin.h"
+#include "inc/arc/arc_exception.h"
+
+/**
+ * \name instruction cache control register related definition
+ * \todo this definitions will be reviewed.
+ * @{
+ */
+#define IC_CTRL_IC_ENABLE			0x0	/*!< enable instruction cache */
+#define IC_CTRL_IC_DISABLE			0x1	/*!< disable instruction cache */
+#define IC_CTRL_DIRECT_ACCESS			0x0	/*!< direct access mode */
+#define IC_CTRL_INDIRECT_ACCESS			0x20	/*!< indirect access mode */
+#define IC_CTRL_OP_SUCCEEDED			0x8	/*!< instruction cache operation succeeded */
+/** @} */
+
+/**
+ * \name data cache control register related definition
+ * \todo this definition will be reviewed.
+ * @{
+ */
+#define IC_CTRL_I
+#define DC_CTRL_DC_ENABLE			0x0	/*!< enable data cache */
+#define DC_CTRL_DC_DISABLE			0x1	/*!< disable data cache */
+#define DC_CTRL_INVALID_ONLY			0x0	/*!< invalid data cache only */
+#define DC_CTRL_INVALID_FLUSH			0x40	/*!< invalid and flush data cache */
+#define DC_CTRL_ENABLE_FLUSH_LOCKED		0x80	/*!< the locked data cache can be flushed */
+#define DC_CTRL_DISABLE_FLUSH_LOCKED		0x0	/*!< the locked data cache cannot be flushed */
+#define DC_CTRL_FLUSH_STATUS			0x100	/*!< flush status */
+#define DC_CTRL_DIRECT_ACCESS			0x0	/*!< direct access mode  */
+#define DC_CTRL_INDIRECT_ACCESS			0x20	/*!< indirect access mode */
+#define DC_CTRL_OP_SUCCEEDED			0x4	/*!< data cache operation succeeded */
+/** @} */
+
+/**
+ * \name instruction cache related inline function
+ * @{
+ */
+
+/**
+ * \brief  check whether instruction cache is available,
+ * 0 for not available, >0 for available
+ */
+Inline uint8_t icache_available(void)
+{
+	return (_arc_aux_read(AUX_BCR_I_CACHE) & 0xF);
+}
+
+/**
+ * \brief  enable instruction cache
+ * \param[in] icache_en_mask operation mask
+ */
+Inline void icache_enable(uint32_t icache_en_mask)
+{
+	if (!icache_available()) return;
+	_arc_aux_write(AUX_IC_CTRL, icache_en_mask);
+}
+
+/**
+ * \brief  disable instruction cache
+ */
+Inline void icache_disable(void)
+{
+	if (!icache_available()) return;
+	_arc_aux_write(AUX_IC_CTRL, IC_CTRL_IC_DISABLE);
+}
+
+/**
+ * \brief  invalidate the entire instruction cache
+ */
+Inline void icache_invalidate(void)
+{
+	if (!icache_available()) return;
+	/* invalidate the entire icache */
+	_arc_aux_write(AUX_IC_IVIC, 0);
+	Asm("nop_s");
+	Asm("nop_s");
+	Asm("nop_s");
+}
+
+/**
+ * \brief  invalidate specific cache line
+ * \param[in] address memory address
+ */
+Inline void icache_invalidate_line(uint32_t address)
+{
+	if (!icache_available()) return;
+	_arc_aux_write(AUX_IC_IVIL, address);
+	/* the 3 nops are required by ARCv2 ISA */
+	Asm("nop_s");
+	Asm("nop_s");
+	Asm("nop_s");
+}
+
+/**
+ * \brief  lock specific cache line
+ * \param[in] address memory address
+ * \return 0, succeeded, -1, failed
+ */
+Inline int32_t icache_lock_line(uint32_t address)
+{
+	if (!icache_available()) return -1;
+	_arc_aux_write(AUX_IC_LIL, address);
+	if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+/**
+ * \brief  set icache access mode
+ * \param[in] mode, access mode, 1: indirect access 0:direct access
+ */
+Inline void icache_access_mode(uint32_t mode)
+{
+	if (!icache_available()) return;
+	if (mode) {
+		_arc_aux_write(AUX_IC_CTRL, _arc_aux_read(AUX_IC_CTRL) | IC_CTRL_INDIRECT_ACCESS);
+	} else {
+		_arc_aux_write(AUX_IC_CTRL, _arc_aux_read(AUX_IC_CTRL) & (~IC_CTRL_INDIRECT_ACCESS));
+	}
+}
+
+
+/** @} */
+
+/**
+ * \name data cache related inline functions
+ * @{
+ */
+
+/**
+ * \brief  check whether data cache is available,
+ * 0 for not available, >0 for available
+ */
+Inline uint8_t dcache_available(void)
+{
+	return (_arc_aux_read(AUX_BCR_D_CACHE) & 0xF);
+}
+
+/**
+ * \brief 	invalidate the entire data cache
+ */
+Inline void dcache_invalidate(void)
+{
+	if (!dcache_available()) return;
+	uint32_t status;
+
+	status = cpu_lock_save();
+	_arc_aux_write(AUX_DC_IVDC, 1);
+	/* wait for flush completion */
+	while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
+	cpu_unlock_restore(status);
+}
+
+/**
+ * \brief invalidate the specific cache line
+ * \param[in] address memory address
+ */
+Inline void dcache_invalidate_line(uint32_t address)
+{
+	if (!dcache_available()) return;
+	_arc_aux_write(AUX_DC_IVDL, address);
+	Asm("nop_s");
+	Asm("nop_s");
+	Asm("nop_s");
+}
+
+/**
+ * \brief enable data cache
+ * \param[in] dcache_en_mask operation mask
+ */
+Inline void dcache_enable(uint32_t dcache_en_mask)
+{
+	if (!dcache_available()) return;
+	_arc_aux_write(AUX_DC_CTRL, dcache_en_mask);
+}
+
+/**
+ * \brief disable data cache
+ */
+Inline void dcache_disable(void)
+{
+	if (!dcache_available()) return;
+	_arc_aux_write(AUX_DC_CTRL, DC_CTRL_DC_DISABLE);
+}
+
+/**
+ * \brief flush data cache
+ */
+Inline void dcache_flush(void)
+{
+	if (!dcache_available()) return;
+	uint32_t status;
+
+	status = cpu_lock_save();
+	_arc_aux_write(AUX_DC_FLSH, 1);
+	/* wait for flush completion */
+	while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
+	cpu_unlock_restore(status);
+}
+
+/**
+ * \brief  flush the specific data cache line
+ * \param[in] address memory address
+ */
+Inline void dcache_flush_line(uint32_t address)
+{
+	if (!dcache_available()) return;
+
+	uint32_t status;
+
+	status = cpu_lock_save();
+	_arc_aux_write(AUX_DC_FLDL, address);
+	while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
+	cpu_unlock_restore(status);
+}
+
+/**
+ * \brief  lock the specific data cache line
+ * \param[in] address memory address
+ * \return 0, succeeded, -1, failed
+ */
+Inline int dcache_lock_line(uint32_t address)
+{
+	if (!dcache_available()) return -1;
+	_arc_aux_write(AUX_DC_LDL, address);
+	if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+/**
+ * \brief  set dcache access mode
+ * \param[in] mode, access mode, 1: indirect access 0:direct access
+ */
+Inline void dcache_access_mode(uint32_t mode)
+{
+	if (!dcache_available()) return;
+	if (mode) {
+		_arc_aux_write(AUX_DC_CTRL, _arc_aux_read(AUX_DC_CTRL) | DC_CTRL_INDIRECT_ACCESS);
+	} else {
+		_arc_aux_write(AUX_DC_CTRL, _arc_aux_read(AUX_DC_CTRL) & (~DC_CTRL_INDIRECT_ACCESS));
+	}
+}
+
+/** @} */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name declarations of cache related functions
+ * @{
+ */
+extern int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size);
+extern int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size);
+extern int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data);
+extern int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data);
+extern int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data);
+extern int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size);
+extern int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size);
+extern int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size);
+extern int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data);
+extern int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data);
+extern int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data);
+extern void arc_cache_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif	/* _ARC_HAL_CACHE_H_ */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_em.h b/bsp/synopsys/embarc/inc/arc/arc_em.h
new file mode 100644
index 0000000000..cfb9636449
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/arc/arc_em.h
@@ -0,0 +1,133 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-06-12
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_CORE_EM
+ * \brief header file of EM series
+ */
+
+/**
+ * \addtogroup ARC_HAL_CORE_EM
+ * @{
+ */
+
+#ifndef _ARC_HAL_EM_H_
+#define _ARC_HAL_EM_H_
+
+#include "inc/arc/arc.h"
+
+#define AUX_ACC0_LO		(0x580)
+#define AUX_ACC0_GLO		(0x581)
+#define AUX_ACC0_HI		(0x582)
+#define AUX_ACC0_GHI		(0x583)
+#define AUX_DSP_BFLY0		(0x598)
+#define AUX_DSP_FFT_CTRL	(0x59e)
+#define AUX_DSP_CTRL		(0x59f)
+
+#define AUX_AGU_AUX_AP0		(0x5c0)
+#define AUX_AGU_AUX_AP1		(0x5c1)
+#define AUX_AGU_AUX_AP2		(0x5c2)
+#define AUX_AGU_AUX_AP3		(0x5c3)
+#define AUX_AGU_AUX_AP4		(0x5c4)
+#define AUX_AGU_AUX_AP5		(0x5c5)
+#define AUX_AGU_AUX_AP6		(0x5c6)
+#define AUX_AGU_AUX_AP7		(0x5c7)
+#define AUX_AGU_AUX_AP8		(0x5c8)
+#define AUX_AGU_AUX_AP9		(0x5c9)
+#define AUX_AGU_AUX_AP10	(0x5ca)
+#define AUX_AGU_AUX_AP11	(0x5cb)
+#define AUX_AGU_AUX_AP12	(0x5cc)
+#define AUX_AGU_AUX_AP13	(0x5cd)
+#define AUX_AGU_AUX_AP14	(0x5ce)
+#define AUX_AGU_AUX_AP15	(0x5cf)
+
+#define AUX_AGU_AXU_OS0		(0x5d0)
+#define AUX_AGU_AXU_OS1		(0x5d1)
+#define AUX_AGU_AXU_OS2		(0x5d2)
+#define AUX_AGU_AXU_OS3		(0x5d3)
+#define AUX_AGU_AXU_OS4		(0x5d4)
+#define AUX_AGU_AXU_OS5		(0x5d5)
+#define AUX_AGU_AXU_OS6		(0x5d6)
+#define AUX_AGU_AXU_OS7		(0x5d7)
+#define AUX_AGU_AXU_OS8		(0x5d8)
+#define AUX_AGU_AXU_OS9		(0x5d9)
+#define AUX_AGU_AXU_OS10	(0x5da)
+#define AUX_AGU_AXU_OS11	(0x5db)
+#define AUX_AGU_AXU_OS12	(0x5dc)
+#define AUX_AGU_AXU_OS13	(0x5dd)
+#define AUX_AGU_AXU_OS14	(0x5de)
+#define AUX_AGU_AXU_OS15	(0x5df)
+
+#define	AUX_AGU_AUX_MOD0	(0x5e0)
+#define	AUX_AGU_AUX_MOD1	(0x5e1)
+#define	AUX_AGU_AUX_MOD2	(0x5e2)
+#define	AUX_AGU_AUX_MOD3	(0x5e3)
+#define	AUX_AGU_AUX_MOD4	(0x5e4)
+#define	AUX_AGU_AUX_MOD5	(0x5e5)
+#define	AUX_AGU_AUX_MOD6	(0x5e6)
+#define	AUX_AGU_AUX_MOD7	(0x5e7)
+#define	AUX_AGU_AUX_MOD8	(0x5e8)
+#define	AUX_AGU_AUX_MOD9	(0x5e9)
+#define	AUX_AGU_AUX_MOD10	(0x5ea)
+#define	AUX_AGU_AUX_MOD11	(0x5eb)
+#define	AUX_AGU_AUX_MOD12	(0x5ec)
+#define	AUX_AGU_AUX_MOD13	(0x5ed)
+#define	AUX_AGU_AUX_MOD14	(0x5ee)
+#define	AUX_AGU_AUX_MOD15	(0x5ef)
+#define	AUX_AGU_AUX_MOD16	(0x5f0)
+#define	AUX_AGU_AUX_MOD17	(0x5f1)
+#define	AUX_AGU_AUX_MOD18	(0x5f2)
+#define	AUX_AGU_AUX_MOD19	(0x5f3)
+#define	AUX_AGU_AUX_MOD20	(0x5f4)
+#define	AUX_AGU_AUX_MOD21	(0x5f5)
+#define	AUX_AGU_AUX_MOD22	(0x5f6)
+#define	AUX_AGU_AUX_MOD23	(0x5f7)
+
+#define AUX_XCCM_BASE		(0x5f8)
+#define AUX_YCCM_BASE		(0x5f9)
+
+
+/** \todo add em series specific definitions here */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ARC_HAL_EM_H_ */
+
+/** @} */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_exception.h b/bsp/synopsys/embarc/inc/arc/arc_exception.h
new file mode 100644
index 0000000000..e485b159c3
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/arc/arc_exception.h
@@ -0,0 +1,461 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
+ * \brief header file of exception and interrupt management module
+ */
+
+#ifndef _ARC_HAL_EXCEPTION_H_
+#define _ARC_HAL_EXCEPTION_H_
+
+#include "inc/embARC_toolchain.h"
+#include "inc/arc/arc.h"
+#include "inc/arc/arc_builtin.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup ARC_HAL_EXCEPTION_CPU
+ * @{
+ * \todo need a conf.h from application or board to define the
+ * features of processor, such as number of exception, code
+ * density and FIQ.
+ */
+#ifndef NUM_EXC_CPU
+#define NUM_EXC_CPU	16	/*!< number of CPU exceptions */
+#endif
+
+#ifndef NUM_EXC_INT
+#define NUM_EXC_INT	9	/*!< number of interrupt exceptions, defined by users*/
+#endif
+
+#define NUM_EXC_ALL	(NUM_EXC_CPU + NUM_EXC_INT) /*!< total number of exceptions */
+
+
+
+#ifdef ARC_FEATURE_SEC_PRESENT
+typedef struct int_exc_frame {
+	uint32_t erbta;
+
+	uint32_t r30;	/* r30 is useless, skipped? */
+	uint32_t ilink;	/* r29 is useless, skipped?*/
+	/* r28 is sp, saved other place */
+	uint32_t fp;	/* r27 */
+	uint32_t gp;	/* r26 */
+
+	uint32_t r12;
+
+	uint32_t lp_end, lp_start, lp_count;
+
+#ifdef ARC_FEATURE_CODE_DENSITY
+	uint32_t ei, ldi, jli;
+#endif
+
+	uint32_t r0, r1, r2, r3;
+#ifndef ARC_FEATURE_RF16
+	uint32_t r4, r5, r6, r7, r8, r9;
+#endif
+	uint32_t r10, r11;
+
+	uint32_t blink;	/* r31 */
+	uint32_t ret;
+	uint32_t sec_stat;
+	uint32_t status32;
+} EMBARC_PACKED INT_EXC_FRAME;
+#else
+typedef struct int_exc_frame {
+	uint32_t erbta;
+
+	uint32_t r30;	/* r30 is useless, skipped? */
+	uint32_t ilink;	/* r29 is useless, skipped?*/
+	/* r28 is sp, saved other place */
+	uint32_t fp;	/* r27 */
+	uint32_t gp;	/* r26 */
+
+	uint32_t r12;
+
+	uint32_t r0, r1, r2, r3;
+#ifndef ARC_FEATURE_RF16
+	uint32_t r4, r5, r6, r7, r8, r9;
+#endif
+	uint32_t r10, r11;
+
+	uint32_t blink;	/* r31 */
+
+	uint32_t lp_end, lp_start, lp_count;
+
+#ifdef ARC_FEATURE_CODE_DENSITY
+	uint32_t ei, ldi, jli;
+#endif
+
+	uint32_t ret;
+	uint32_t status32;
+} EMBARC_PACKED INT_EXC_FRAME;
+#endif
+
+typedef struct callee_frame {
+#ifndef ARC_FEATURE_RF16
+	uint32_t r25;
+	uint32_t r24;
+	uint32_t r23;
+	uint32_t r22;
+	uint32_t r21;
+	uint32_t r20;
+	uint32_t r19;
+	uint32_t r18;
+	uint32_t r17;
+	uint32_t r16;
+#endif
+	uint32_t r15;
+	uint32_t r14;
+	uint32_t r13;
+} EMBARC_PACKED CALLEE_FRAME;
+
+typedef struct processor_frame {
+	CALLEE_FRAME callee_regs;
+	INT_EXC_FRAME exc_frame;
+} EMBARC_PACKED PROCESSOR_FRAME;
+
+#define ARC_PROCESSOR_FRAME_SIZE	(sizeof(PROCESSOR_FRAME) / sizeof(uint32_t))
+#define ARC_EXC_FRAME_SIZE		(sizeof(INT_EXC_FRAME) / sizeof(uint32_t))
+#define ARC_CALLEE_FRAME_SIZE		(sizeof(CALLEE_FRAME) / sizeof(uint32_t))
+
+
+extern uint32_t exc_nest_count;
+
+/**
+ * \brief write the exception vector base
+ *
+ * \param[in] vec_base the target vector base
+ */
+Inline void arc_vector_base_write(const void * vec_base)
+{
+	_arc_aux_write(AUX_INT_VECT_BASE, (uint32_t)vec_base);
+}
+
+/**
+ * \brief read current exception vector base
+ *
+ * \returns exception vector base (uint32_t)
+ */
+Inline uint32_t arc_vector_base_read(void)
+{
+	return _arc_aux_read(AUX_INT_VECT_BASE);
+}
+
+/**
+ * \brief  sense whether in exc/interrupt processing
+ *
+ * \retval 0	not in exc/interrupt processing
+ * \retval 1	in exc/interrupt processing
+ */
+Inline uint32_t exc_sense(void)
+{
+	return (exc_nest_count > 0U);
+}
+
+/** @}*/
+
+/**
+ * \addtogroup ARC_HAL_EXCEPTION_INTERRUPT
+ * @{
+ */
+#ifndef INT_PRI_MIN
+#define INT_PRI_MIN	(-2)		/*!< the minimum interrupt priority */
+#endif
+
+#define INT_PRI_MAX (-1)		/*!< the maximum interrupt priority */
+/**
+ * \brief disable the specific interrupt
+ *
+ * \param[in] intno interrupt number
+ */
+Inline void arc_int_disable(const uint32_t intno)
+{
+	_arc_aux_write(AUX_IRQ_SELECT, intno);
+	_arc_aux_write(AUX_IRQ_ENABLE, 0);
+}
+
+/**
+ * \brief  enable the specific int
+ *
+ * \param[in] intno interrupt number
+ */
+Inline void arc_int_enable(const uint32_t intno)
+{
+	_arc_aux_write(AUX_IRQ_SELECT, intno);
+	_arc_aux_write(AUX_IRQ_ENABLE, 1);
+}
+
+/**
+ * \brief  check whether the specific int is enabled
+ *
+ * \param[in] intno interrupt number
+ * \return 0 disabled, 1 enabled
+ */
+Inline uint32_t arc_int_enabled(const uint32_t intno)
+{
+	_arc_aux_write(AUX_IRQ_SELECT, intno);
+	return _arc_aux_read(AUX_IRQ_ENABLE);
+}
+
+/**
+ * \brief  get the interrupt priority mask
+ *
+ * \returns interrupt priority mask, negative num
+ */
+Inline uint32_t arc_int_ipm_get(void)
+{
+	return ((_arc_aux_read(AUX_STATUS32) >> 1) & 0x0f);
+}
+
+/**
+ * \brief  set the interrupt priority mask
+ *
+ * \param[in] intpri interrupt priority
+ */
+Inline void arc_int_ipm_set(uint32_t intpri)
+{
+	volatile uint32_t status;
+	status = _arc_aux_read(AUX_STATUS32) & ~0x1e;
+
+	status = status | ((intpri << 1) & 0x1e);
+	/* sr cannot write AUX_STATUS32 */
+	Asm("kflag %0"::"ir"(status));
+}
+
+/**
+ * \brief  get current interrupt priority mask
+ *
+ * \param[in] intno interrupt number
+ */
+Inline uint32_t arc_int_pri_get(const uint32_t intno)
+{
+	_arc_aux_write(AUX_IRQ_SELECT, intno);
+	return _arc_aux_read(AUX_IRQ_PRIORITY);
+}
+
+/**
+ * \brief set interrupt priority
+ *
+ * \param[in] intno interrupt number
+ * \param[in] intpri interrupt priority
+ */
+Inline void arc_int_pri_set(const uint32_t intno, uint32_t intpri)
+{
+	_arc_aux_write(AUX_IRQ_SELECT, intno);
+	_arc_aux_write(AUX_IRQ_PRIORITY, intpri | (_arc_aux_read(AUX_IRQ_PRIORITY) & 0xfffffff0));
+}
+
+/**
+ * \brief set interrupt secure or not secure
+ *
+ * \param[in] intno interrupt number
+ * \param[in] secure, 0 for normal, >0 for secure
+ */
+Inline void arc_int_secure_set(const uint32_t intno, uint32_t secure)
+{
+
+	_arc_aux_write(AUX_IRQ_SELECT, intno);
+
+	if (secure) {
+		_arc_aux_write(AUX_IRQ_PRIORITY, _arc_aux_read(AUX_IRQ_PRIORITY) |
+			(1 << AUX_IRQ_PRIORITY_BIT_S));
+	} else {
+		_arc_aux_write(AUX_IRQ_PRIORITY, _arc_aux_read(AUX_IRQ_PRIORITY) & 0xf);
+	}
+
+}
+
+/**
+ * \brief  probe the pending status of interrupt
+ *
+ * \param[in] intno interrupt number
+ *
+ * \returns 1 pending, 0 no pending
+ */
+Inline uint32_t arc_int_probe(const uint32_t intno)
+{
+	_arc_aux_write(AUX_IRQ_SELECT, intno);
+	return _arc_aux_read(AUX_IRQ_PENDING);
+}
+
+/**
+ * \brief  trigger the interrupt in software
+ *
+ * \param[in] intno interrupt number
+ */
+Inline void arc_int_sw_trigger(const uint32_t intno)
+{
+	_arc_aux_write(AUX_IRQ_HINT, intno);
+}
+
+/**
+ * \brief  config the interrupt level triggered or pulse triggered
+ *
+ * \param[in] intno interrupt number
+ * \param[in] level, 0-level trigger, 1-pluse triggered
+ */
+Inline void arc_int_level_config(const uint32_t intno, const uint32_t level)
+{
+	_arc_aux_write(AUX_IRQ_SELECT, intno);
+	_arc_aux_write(AUX_IRQ_TRIGGER, level);
+}
+
+/**
+ * \brief  lock cpu, disable interrupts
+ */
+Inline void arc_lock(void)
+{
+	Asm("clri");
+	Asm("":::"memory");
+}
+
+/**
+ * \brief  unlock cpu, enable interrupts to happen
+ */
+Inline void arc_unlock(void)
+{
+	Asm("":::"memory");
+	Asm("seti");
+}
+
+/**
+ * \brief  lock cpu and staus
+ *
+ * \returns cpu status
+ */
+Inline uint32_t arc_lock_save(void)
+{
+	return _arc_clri();
+}
+
+/**
+ * \brief  unlock cpu with the specific status
+ *
+ * \param[in] status  cpu status saved by cpu_lock_save
+ */
+Inline void arc_unlock_restore(const uint32_t status)
+{
+	_arc_seti(status);
+}
+/** @}*/
+
+/**
+ * \addtogroup ARC_HAL_EXCEPTION_CPU
+ * @{
+ */
+/**
+ * \typedef EXC_ENTRY
+ * \brief  the data type for exception entry
+ */
+typedef void (*EXC_ENTRY) (void);
+/**
+ * \typedef EXC_HANDLER
+ * \brief  the data type for exception handler
+ */
+typedef	void (*EXC_HANDLER) (void *exc_frame);
+/** @}*/
+
+
+/**
+ * \ingroup ARC_HAL_EXCEPTION_INTERRUPT
+ * \typedef INT_HANDLER
+ * \brief  the data type for interrupt handler
+ */
+typedef void (*INT_HANDLER) (void *ptr);
+
+extern EXC_ENTRY exc_entry_table[NUM_EXC_ALL];
+extern EXC_HANDLER exc_int_handler_table[NUM_EXC_ALL];
+
+/** \ingroup ARC_HAL_EXCEPTION_CPU
+ * @{
+ */
+/**
+ * \fn _arc_reset
+ * \brief the reset entry
+ */
+extern void _arc_reset(void);
+/**
+ * \fn exc_entry_cpu
+ * \brief the default CPU exception entry
+ */
+extern void exc_entry_cpu(void);
+
+/**
+ * \fn exc_entry_firq
+ * \brief the fast interrupt exception entry
+ */
+extern void exc_entry_firq(void);
+/**
+ * \fn exc_entry_int
+ * \brief the interrupt exception entry
+ */
+extern void exc_entry_int(void);
+/** @}*/
+
+/* excetpion related apis */
+extern void exc_int_init(void);
+extern int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY entry);
+extern EXC_ENTRY exc_entry_get(const uint32_t excno);
+extern int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER handler);
+extern EXC_HANDLER exc_handler_get(const uint32_t excno);
+
+/* interrupt related apis */
+extern int32_t int_disable(const uint32_t intno);
+extern int32_t int_enable(const uint32_t intno);
+extern int32_t int_enabled(const uint32_t intno);
+extern int32_t int_ipm_get(void);
+extern int32_t int_ipm_set(int32_t intpri);
+extern int32_t int_pri_get(const uint32_t intno);
+extern int32_t int_pri_set(const uint32_t intno, int32_t intpri);
+extern int32_t int_probe(const uint32_t intno);
+extern int32_t int_sw_trigger(const uint32_t intno);
+extern int32_t int_level_config(const uint32_t intno, const uint32_t level);
+extern void cpu_lock(void);
+extern void cpu_unlock(void);
+extern uint32_t cpu_lock_save(void);
+extern void cpu_unlock_restore(const uint32_t status);
+extern int32_t int_handler_install(const uint32_t intno, INT_HANDLER handler);
+extern INT_HANDLER int_handler_get(const uint32_t intno);
+extern int32_t int_secure_set(const uint32_t intno, uint32_t secure);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ARC_HAL_EXCEPTION_H_*/
diff --git a/bsp/synopsys/embarc/inc/arc/arc_feature_config.h b/bsp/synopsys/embarc/inc/arc/arc_feature_config.h
new file mode 100644
index 0000000000..87b1913df5
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/arc/arc_feature_config.h
@@ -0,0 +1,397 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2016-09-08
+ * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_MISC
+ * \brief header file for arc feature configuration
+ */
+
+/**
+ * \addtogroup ARC_HAL_MISC
+ * @{
+ */
+
+#ifndef _ARC_FEATURE_CONFIG_H_
+#define _ARC_FEATURE_CONFIG_H_
+
+// Enable core_config.h in EMSK OSP
+//#ifdef EMBARC_TCF_GENERATED
+#include "arc_core_config.h"
+//#endif
+
+/** ARC baseline instruction set version number */
+#if !defined(_ARCVER)
+#if defined(core_config_cir_identity_arcver)
+#define _ARCVER				core_config_cir_identity_arcver
+#else
+#define _ARCVER				0x42
+#endif
+#endif
+
+/** ARC CPU Clock Frequency in Hz unit */
+#if !defined(ARC_FEATURE_CPU_CLOCK_FREQ)
+#if defined(core_config_clock_speed)
+#define ARC_FEATURE_CPU_CLOCK_FREQ	(core_config_clock_speed*1000000)
+#endif
+#endif
+
+/** ARC PC size */
+#if !defined(ARC_FEATURE_PC_SIZE)
+#if defined(core_config_pc_size)
+#define ARC_FEATURE_PC_SIZE		core_config_pc_size
+#else
+#define ARC_FEATURE_PC_SIZE		32
+#endif
+#endif
+
+/** ARC LPC size */
+#if !defined(ARC_FEATURE_LPC_SIZE)
+#if defined(core_config_lpc_size)
+#define ARC_FEATURE_LPC_SIZE		core_config_lpc_size
+#else
+#define ARC_FEATURE_LPC_SIZE		32
+#endif
+#endif
+
+/** ARC Addr size */
+#if !defined(ARC_FEATURE_ADDR_SIZE)
+#if defined(core_config_addr_size)
+#define ARC_FEATURE_ADDR_SIZE		core_config_addr_size
+#else
+#define ARC_FEATURE_ADDR_SIZE		32
+#endif
+#endif
+
+/** ARC Endian/Byte Order */
+#define ARC_FEATURE_LITTLE_ENDIAN	1234
+#define ARC_FEATURE_BIG_ENDIAN		4321
+
+#if !defined(ARC_FEATURE_BYTE_ORDER)
+#if defined(core_config_bcr_isa_config_b)
+#if core_config_bcr_isa_config_b == 0
+#define ARC_FEATURE_BYTE_ORDER		ARC_FEATURE_LITTLE_ENDIAN
+#else
+#define ARC_FEATURE_BYTE_ORDER		ARC_FEATURE_BIG_ENDIAN
+#endif
+#else
+#define ARC_FEATURE_BYTE_ORDER		ARC_FEATURE_LITTLE_ENDIAN
+#endif
+#endif
+
+/** Reduced register option, if enabled, ARC_FEATURE_RF16 will be defined */
+#if !defined(ARC_FEATURE_RF16)
+#if defined(core_config_bcr_rf_build_e) && core_config_bcr_rf_build_e == 1
+#define ARC_FEATURE_RF16
+#endif
+#endif
+
+/** Unaligned access option, if enabled, ARC_FEATURE_UNALIGNED will be defined */
+#if !defined(ARC_FEATURE_UNALIGNED)
+#if defined(core_config_unaligned) && core_config_unaligned == 1
+#define ARC_FEATURE_UNALIGNED
+#endif
+#endif
+
+
+/** Code density option, if enabled, ARC_FEATURE_CODE_DENSITY will be defined */
+#if !defined(ARC_FEATURE_CODE_DENSITY)
+#if defined(core_config_code_density) && core_config_code_density == 1
+#define ARC_FEATURE_CODE_DENSITY
+#endif
+#endif
+
+/** The number of register file banks */
+#if !defined(ARC_FEATURE_RGF_NUM_BANKS)
+#if defined(core_config_rgf_num_banks)
+#define ARC_FEATURE_RGF_NUM_BANKS	core_config_rgf_num_banks
+#else
+#define ARC_FEATURE_RGF_NUM_BANKS	1
+#endif
+#endif
+
+/** The number of registers replicated per register bank */
+#if !defined(ARC_FEATURE_RGF_BANKED_REGS)
+#if defined(core_config_rgf_banked_regs)
+#define ARC_FEATURE_RGF_BANKED_REGS	core_config_rgf_banked_regs
+#endif
+#endif
+
+/** Interrupt unit presence */
+#if !defined(ARC_FEATURE_INTERRUPTS_PRESENT)
+#if defined(core_config_interrupts_present)
+#define ARC_FEATURE_INTERRUPTS_PRESENT	core_config_interrupts_present
+#endif
+#endif
+
+/** FIRQ_OPTION configuration option, 1 for enabled, 0 for disabled */
+#if !defined(ARC_FEATURE_FIRQ)
+#if defined(core_config_bcr_irq_build_f)
+#define ARC_FEATURE_FIRQ		core_config_bcr_irq_build_f
+#else
+#define ARC_FEATURE_FIRQ		0
+#endif
+#endif
+
+/** The number of interrupts */
+#if !defined(NUM_EXC_INT)
+#if defined(core_config_interrupts_number)
+#define NUM_EXC_INT			core_config_interrupts_number
+#endif
+#endif
+
+/** The number of external interrupts */
+#if !defined(NUM_EXC_EXT_INT)
+#if defined(core_config_interrupts_externals)
+#define NUM_EXC_EXT_INT			core_config_interrupts_externals
+#endif
+#endif
+
+/** The interrupt priority levels */
+#if !defined(INT_PRI_MIN)
+#if defined(core_config_interrupts_priorities)
+#define INT_PRI_MIN			(-core_config_interrupts_priorities)
+#endif
+#endif
+
+// ARC TIMER_BUILD
+/** Timer0 present or not */
+#if !defined(ARC_FEATURE_TIMER0_PRESENT)
+#if defined(core_config_timer0)
+#define ARC_FEATURE_TIMER0_PRESENT	core_config_timer0
+#define ARC_FEATURE_TIMER0_LEVEL	(core_config_timer0_level-core_config_interrupts_priorities)
+#define ARC_FEATURE_TIMER0_VECTOR	core_config_timer0_vector
+#endif
+#endif
+
+/** Timer1 present or not */
+#if !defined(ARC_FEATURE_TIMER1_PRESENT)
+#if defined(core_config_timer1)
+#define ARC_FEATURE_TIMER1_PRESENT	core_config_timer1
+#define ARC_FEATURE_TIMER1_LEVEL	(core_config_timer1_level-core_config_interrupts_priorities)
+#define ARC_FEATURE_TIMER1_VECTOR	core_config_timer1_vector
+#endif
+#endif
+
+/** Secure Timer0 present or not */
+#if !defined(ARC_FEATURE_SEC_TIMER0_PRESENT)
+#if defined(core_config_sec_timer0)
+#define ARC_FEATURE_SEC_TIMER0_PRESENT	core_config_sec_timer0
+#define ARC_FEATURE_SEC_TIMER0_LEVEL	(core_config_sec_timer0_level-core_config_interrupts_priorities)
+#define ARC_FEATURE_SEC_TIMER0_VECTOR	20
+#endif
+#endif
+
+/** Secure Timer1 present or not */
+#if !defined(ARC_FEATURE_SEC_TIMER1_PRESENT)
+#if defined(core_config_sec_timer1)
+#define ARC_FEATURE_SEC_TIMER1_PRESENT	core_config_sec_timer1
+#define ARC_FEATURE_SEC_TIMER1_LEVEL	(core_config_sec_timer1_level-core_config_interrupts_priorities)
+#define ARC_FEATURE_SEC_TIMER1_VECTOR	21
+#endif
+#endif
+
+
+/** 64bit RTC present or not */
+#if !defined(ARC_FEATURE_RTC_PRESENT)
+#if defined(core_config_rtc)
+#define ARC_FEATURE_RTC_PRESENT		core_config_rtc
+#endif
+#endif
+
+// Memory related definitions
+/** ICCM Presence, base address and size */
+#if !defined(ARC_FEATURE_ICCM_PRESENT)
+#if defined(core_config_iccm_present) && core_config_iccm_present == 1
+#define ARC_FEATURE_ICCM_PRESENT	1
+#define ARC_FEATURE_ICCM_BASE		core_config_iccm_base
+#define ARC_FEATURE_ICCM_SIZE		core_config_iccm_size
+#endif
+#endif
+
+/** ICCM0 Presence, base address and size */
+#if !defined(ARC_FEATURE_ICCM0_PRESENT)
+#if defined(core_config_iccm0_present) && core_config_iccm0_present == 1
+#define ARC_FEATURE_ICCM0_PRESENT	1
+#define ARC_FEATURE_ICCM0_BASE		core_config_iccm0_base
+#define ARC_FEATURE_ICCM0_SIZE		core_config_iccm0_size
+#endif
+#endif
+
+/** ICCM1 Presence, base address and size */
+#if !defined(ARC_FEATURE_ICCM1_PRESENT)
+#if defined(core_config_iccm1_present) && core_config_iccm1_present == 1
+#define ARC_FEATURE_ICCM1_PRESENT	1
+#define ARC_FEATURE_ICCM1_BASE		core_config_iccm1_base
+#define ARC_FEATURE_ICCM1_SIZE		core_config_iccm1_size
+#endif
+#endif
+
+/** DCCM Presence, base address and size */
+#if !defined(ARC_FEATURE_DCCM_PRESENT)
+#if defined(core_config_dccm_present) && core_config_dccm_present == 1
+#define ARC_FEATURE_DCCM_PRESENT	1
+#define ARC_FEATURE_DCCM_BASE		core_config_dccm_base
+#define ARC_FEATURE_DCCM_SIZE		core_config_dccm_size
+#ifdef core_config_dccm_interleave
+#define ARC_FEATURE_DCCM_INTERLEAVE	core_config_dccm_interleave
+#endif
+#endif
+#endif
+
+/** Peripheral memory region(DMP) base address, if dmp configured, this macro will be defined as base address */
+#if !defined(ARC_FEATURE_DMP_PERIPHERAL)
+#if defined(core_config_cir_dmp_peripheral)
+#define ARC_FEATURE_DMP_PERIPHERAL	core_config_cir_dmp_peripheral
+#endif
+#endif
+
+/** MPU options */
+#if !defined(ARC_FEATURE_MPU_PRESENT)
+#if defined(core_config_mpu_present) && core_config_mpu_present == 1
+#define ARC_FEATURE_MPU_PRESENT		1
+#define ARC_FEATURE_MPU_VERSION		core_config_bcr_mpu_build_version
+#define ARC_FEATURE_MPU_REGIONS		core_config_mpu_regions
+#ifdef core_config_bcr_mpu_build_i
+#define ARC_FEATURE_MPU_BUILD_I		core_config_bcr_mpu_build_i
+#endif
+#ifdef core_config_bcr_mpu_build_s
+#define ARC_FEATURE_MPU_BUILD_S		core_config_bcr_mpu_build_s
+#endif
+#endif
+#endif
+
+/** Secure BCR SEC_BUILD BCR */
+#if !defined(ARC_FEATURE_SEC_PRESENT)
+#if defined(core_config_bcr_sec_build)
+#define ARC_FEATURE_SEC_PRESENT		1
+#define ARC_FEATURE_SEC_VERSION		core_config_bcr_sec_build_version
+#define	ARC_FEATURE_SEC_BUILD_DSM	core_config_bcr_sec_build_dsm
+#define	ARC_FEATURE_SEC_BUILD_NSM	core_config_bcr_sec_build_nsm
+#define	ARC_FEATURE_SEC_BUILD_I1SM	core_config_bcr_sec_build_i1sm
+#define	ARC_FEATURE_SEC_BUILD_I0SM	core_config_bcr_sec_build_i0sm
+#define	ARC_FEATURE_SEC_BUILD_S		core_config_bcr_sec_build_s
+#define	ARC_FEATURE_SEC_BUILD_EI	core_config_bcr_sec_build_ei
+#define	ARC_FEATURE_SEC_BUILD_ED	core_config_bcr_sec_build_ed
+#endif
+#endif
+
+#if !defined(ARC_FEATURE_SEC_MODES)
+#if defined(core_config_sec_modes)
+#define ARC_FEATURE_SEC_MODES		core_config_sec_modes
+#endif
+#endif
+
+/** Data Cache options */
+#if !defined(ARC_FEATURE_DCACHE_PRESENT)
+#if defined(core_config_dcache_present) && core_config_dcache_present == 1
+#define ARC_FEATURE_DCACHE_PRESENT		1
+#define ARC_FEATURE_DCACHE_BUILD		core_config_bcr_d_cache_build
+#define ARC_FEATURE_DCACHE_BUILD_VERSION	core_config_bcr_d_cache_build_version
+#define ARC_FEATURE_DCACHE_BUILD_ASSOC		core_config_bcr_d_cache_build_assoc
+#define ARC_FEATURE_DCACHE_BUILD_CAPACITY	core_config_bcr_d_cache_build_capacity
+#define ARC_FEATURE_DCACHE_BUILD_BSIZE		core_config_bcr_d_cache_build_bsize
+#define ARC_FEATURE_DCACHE_BUILD_FL		core_config_bcr_d_cache_build_fl
+#define ARC_FEATURE_DCACHE_BUILD_U		core_config_bcr_d_cache_build_u
+#define ARC_FEATURE_DCACHE_SIZE			core_config_dcache_size
+#define ARC_FEATURE_DCACHE_LINE_SIZE		core_config_dcache_line_size
+#define ARC_FEATURE_DCACHE_WAYS			core_config_dcache_ways
+#define ARC_FEATURE_DCACHE_FEATURE		core_config_dcache_feature
+#endif
+#endif
+
+/** Instruction Cache options */
+#if !defined(ARC_FEATURE_ICACHE_PRESENT)
+#if defined(core_config_icache_present) && core_config_icache_present == 1
+#define ARC_FEATURE_ICACHE_PRESENT		1
+#define ARC_FEATURE_ICACHE_BUILD		core_config_bcr_i_cache_build
+#define ARC_FEATURE_ICACHE_BUILD_VERSION	core_config_bcr_i_cache_build_version
+#define ARC_FEATURE_ICACHE_BUILD_ASSOC		core_config_bcr_i_cache_build_assoc
+#define ARC_FEATURE_ICACHE_BUILD_CAPACITY	core_config_bcr_i_cache_build_capacity
+#define ARC_FEATURE_ICACHE_BUILD_BSIZE		core_config_bcr_i_cache_build_bsize
+#define ARC_FEATURE_ICACHE_BUILD_FL		core_config_bcr_i_cache_build_fl
+#define ARC_FEATURE_ICACHE_BUILD_D		core_config_bcr_i_cache_build_d
+#define ARC_FEATURE_ICACHE_SIZE			core_config_icache_size
+#define ARC_FEATURE_ICACHE_LINE_SIZE		core_config_icache_line_size
+#define ARC_FEATURE_ICACHE_WAYS			core_config_icache_ways
+#define ARC_FEATURE_ICACHE_FEATURE		core_config_icache_feature
+#endif
+#endif
+
+/** ARC uDMA options */
+#if !defined(ARC_FEATURE_DMAC)
+#if defined(core_config_dmac)
+#define ARC_FEATURE_DMAC		core_config_dmac
+#define CORE_DMAC_CHANNELS		core_config_dmac_channels
+#define CORE_DMAC_REGISTERS		core_config_dmac_registers
+#if core_config_bcr_dmac_build_int_cfg == 2 && core_config_bcr_dmac_build_int_cfg == 4
+#define DMA_MULTI_IRQ			1
+#else
+#define DMA_MULTI_IRQ			0
+#endif
+#define ARC_FEATURE_DMAC_PRESENT	core_config_dmac
+#define ARC_FEATURE_DMAC_VERSION	core_config_bcr_dmac_build_version
+#define ARC_FEATURE_DMAC_CHANNELS	core_config_dmac_channels
+#define ARC_FEATURE_DMAC_REGISTERS	core_config_dmac_registers
+#define ARC_FEATURE_DMAC_INT_CFG	core_config_bcr_dmac_build_int_cfg
+#define ARC_FEATURE_DMAC_FIFO_DEPTH	core_config_dmac_fifo_depth
+
+#ifdef ARC_FEATURE_SEC_TIMER0_PRESENT
+#define DMA_IRQ_NUM_START		22
+#define ARC_FEATURE_DMAC_VECTOR_START	22
+#else
+#define DMA_IRQ_NUM_START		20
+#define ARC_FEATURE_DMAC_VECTOR_START	20
+#endif
+
+#endif
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef ARC_FEATURE_UNALIGNED
+#define STATUS32_RESET_VALUE		(1<<19)
+#else
+#define STATUS32_RESET_VALUE		(0)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ARC_FEATURE_CONFIG_H_ */
+
+/** @} */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_timer.h b/bsp/synopsys/embarc/inc/arc/arc_timer.h
new file mode 100644
index 0000000000..b5237f31a9
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/arc/arc_timer.h
@@ -0,0 +1,99 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-07-15
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup ARC_HAL_MISC_TIMER
+ * \brief header file of ARC internal timer
+ */
+
+/**
+ * \addtogroup ARC_HAL_MISC_TIMER
+ * @{
+ */
+
+#ifndef _ARC_HAL_TIMER_H_
+#define _ARC_HAL_TIMER_H_
+#include "inc/arc/arc.h"
+#include "inc/embARC_toolchain.h"
+
+/**
+ * \name arc internal timers names
+ * @{
+ */
+#define TIMER_0		0 	/*!< macro name for arc internal timer 0 */
+#define TIMER_1		1 	/*!< macro name for arc internal timer 1 */
+#define TIMER_RTC	2 	/*!< macro name for arc internal RTC */
+
+/** @} */
+
+/**
+ * \name bit definition of RTC CTRL reg
+ * @{
+ */
+
+#define TIMER_RTC_ENABLE	0x01	   /*!< enable RTC */
+#define TIMER_RTC_CLEAR		0x02	   /* clears the AUX_RTC_LOW and AUX_RTC_HIGH */
+#define TIMER_RTC_STATUS_A0	0x40000000 /*!< track bit of atomicity of reads of RTC */
+#define TIMER_RTC_STATUS_A1	0x80000000 /*!< track bit of atomicity of reads of RTC */
+
+/** @} */
+
+/**
+ * \name bit definition of timer CTRL reg
+ * @{
+ */
+#define TIMER_CTRL_IE		(1 << 0)	/*!< Interrupt when count reaches limit */
+#define TIMER_CTRL_NH		(1 << 1)	/*!< Count only when CPU NOT halted */
+#define TIMER_CTRL_W		(1 << 2)	/*!< watchdog enable */
+#define TIMER_CTRL_IP		(1 << 3)	/*!< interrupt pending */
+
+/** @} */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int32_t arc_timer_present(const uint32_t no);
+extern int32_t arc_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val);
+extern int32_t arc_timer_stop(const uint32_t no);
+extern int32_t arc_timer_current(const uint32_t no, void* val);
+extern int32_t arc_timer_int_clear(const uint32_t no);
+extern void arc_timer_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* _ARC_HAL_TIMER_H_ */
+/** }@*/
diff --git a/bsp/synopsys/embarc/inc/embARC_debug.h b/bsp/synopsys/embarc/inc/embARC_debug.h
new file mode 100644
index 0000000000..092374622d
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/embARC_debug.h
@@ -0,0 +1,94 @@
+/* ------------------------------------------
+ * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2017.03
+ * \date 2014-12-26
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup EMBARC_DEBUG
+ * \brief necessary definitions of debug
+ */
+
+#ifndef _EMBARC_DEBUG_H_
+#define _EMBARC_DEBUG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef EMBARC_PRINTF
+	#include "common/xprintf.h"
+	#define EMBARC_PRINTF xprintf
+#endif
+
+/*
+ * if you want to use DBG or dbg_printf,
+ * please define DEBUG or DBG_LESS or DBG_MORE before include embARC_debug.h
+ * DEBUG: enable debug print
+ * DBG_LESS: enable less debug msg
+ * DBG_MORE: enable more debug msg
+ **/
+
+#if defined(DEBUG)
+#if defined(DEBUG_HOSTLINK)
+#include <stdio.h>
+#define DBG(fmt, ...)	printf(fmt, ##__VA_ARGS__)
+#else
+#define DBG(fmt, ...)	EMBARC_PRINTF(fmt, ##__VA_ARGS__)
+#endif
+#else
+#define DBG(fmt, ...)
+#endif
+
+#define DBG_LESS_INFO	0x01    /* less debug  messages */
+#define DBG_MORE_INFO	0x02    /* more debug  messages */
+
+
+#if defined (DBG_LESS)
+#define DBG_TYPE		(DBG_LESS_INFO)
+#elif defined (DBG_MORE)
+#define DBG_TYPE		((DBG_LESS_INFO) | (DBG_MORE_INFO))
+#else
+#define DBG_TYPE 		0
+#endif
+
+#if DBG_TYPE > 0
+#define dbg_printf(type, fmt, ...) \
+		if (((type) & DBG_TYPE))  { EMBARC_PRINTF(fmt, ##__VA_ARGS__); }
+#else
+#define dbg_printf(type, fmt, ...)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DEBUG_H_ */
diff --git a/bsp/synopsys/embarc/inc/embARC_error.h b/bsp/synopsys/embarc/inc/embARC_error.h
new file mode 100644
index 0000000000..9bd9c318aa
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/embARC_error.h
@@ -0,0 +1,156 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-12-25
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	EMBARC_ERROR
+ * \brief	header file to define common definitions error management
+ */
+
+/**
+ * \addtogroup	EMBARC_ERROR
+ * @{
+ */
+
+#ifndef _EMBARC_ERROR_H_
+#define _EMBARC_ERROR_H_
+
+#include <stdint.h>
+#include "inc/arc/arc_builtin.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * \name	Main Error Code Definitions
+ * @{
+ */
+#define E_OK		(0)		/*!< ok */
+#define E_SYS		(-5)		/*!< system error */
+#define E_NOSPT		(-9)		/*!< unsupported features */
+#define E_RSFN		(-10)		/*!< reserved function code */
+#define E_RSATR		(-11)		/*!< reserved attribute */
+#define E_PAR		(-17)		/*!< parameter error */
+#define E_ID		(-18)		/*!< invalid ID number */
+#define E_CTX		(-25)		/*!< context error */
+#define E_MACV		(-26)		/*!< memory access violation */
+#define E_OACV		(-27)		/*!< object access violation */
+#define E_ILUSE		(-28)		/*!< illegal service call use */
+#define E_NOMEM		(-33)		/*!< insufficient memory */
+#define E_NOID		(-34)		/*!< no ID number available */
+#define E_NORES		(-35)		/*!< no resource available */
+#define E_OBJ		(-41)		/*!< object state error */
+#define E_NOEXS		(-42)		/*!< non-existent object */
+#define E_QOVR		(-43)		/*!< queue overflow */
+#define E_RLWAI		(-49)		/*!< forced release from waiting */
+#define E_TMOUT		(-50)		/*!< polling failure or timeout */
+#define E_DLT		(-51)		/*!< waiting object deleted */
+#define E_CLS		(-52)		/*!< waiting object state changed */
+#define E_WBLK		(-57)		/*!< non-blocking accepted */
+#define E_BOVR		(-58)		/*!< buffer overflow */
+#define E_OPNED		(-6)		/*!< device is opened */
+#define E_CLSED		(-7)		/*!< device is closed */
+/** @} end of name */
+
+/**
+ * \name	Generate And Decompose Error Code
+ * @{
+ */
+#ifndef ERCD
+/** generate error code using main error code and sub error code */
+#define ERCD(mercd, sercd) \
+		((uint32_t)((((uint32_t) sercd) << 8) | (((uint32_t) mercd) & 0xffU)))
+#endif /* ERCD */
+
+#ifndef MERCD
+#ifdef INT8_MAX
+/** get main error code from error code */
+#define MERCD(ercd)		((uint32_t)((int8_t)(ercd)))
+#else /* INT8_MAX */
+/** get main error code from error code */
+#define MERCD(ercd)		((uint32_t)(((uint32_t) ercd) | ~0xffU))
+#endif /* INT8_MAX */
+#endif /* MERCD */
+
+#ifndef SERCD
+/** get sub error code from error code */
+#define SERCD(ercd)		((uint32_t)((ercd) >> 8))
+#endif /* SERCD */
+/** @} end of name */
+
+/**
+ * \name	Check Error
+ * @{
+ */
+/**
+ * \brief   check an expression to see if it is right, and when error
+ * 	set the ercd, and goto exit_label
+ * \param   EXPR	the expression that need to be checked (==0 failed)
+ * \param   ERCD	MUST pass a variable to here to get the error code
+ * \param   ERROR_CODE error code that pass to ERCD
+ * \param   EXIT_LABEL a label to go when error happens
+ */
+#define CHECK_EXP(EXPR, ERCD, ERROR_CODE, EXIT_LABEL) 	{	\
+		if (_arc_rarely(!(EXPR))) { 			\
+			ERCD = (ERROR_CODE);			\
+			goto EXIT_LABEL;			\
+		}						\
+	}
+/**
+ * \brief   check an expression to see if it is right, and when error
+ * 			directly goto exit_label
+ * \param   EXPR       the expression that need to be checked (==0 failed)
+ * \param   EXIT_LABEL a label to go when error happens
+ * \retval
+ */
+#define CHECK_EXP_NOERCD(EXPR, EXIT_LABEL) {			\
+		if (_arc_rarely(!(EXPR))) { 			\
+			goto EXIT_LABEL;			\
+		}						\
+	}
+/** check cnt bytes align, 1 for aligned, 0 for not-aligned */
+#define CHECK_ALIGN_BYTES(pointer, cnt)		((((uint32_t)(pointer)) & (cnt-1)) == 0)
+/** check 2 bytes align, 1 for aligned, 0 for not-aligned */
+#define CHECK_ALIGN_2BYTES(pointer)		((((uint32_t)(pointer)) & 0x1) == 0)
+/** check 4 bytes align, 1 for aligned, 0 for not-aligned */
+#define CHECK_ALIGN_4BYTES(pointer)		((((uint32_t)(pointer)) & 0x3) == 0)
+/** check 8 bytes align, 1 for aligned, 0 for not-aligned */
+#define CHECK_ALIGN_8BYTES(pointer)		((((uint32_t)(pointer)) & 0x7) == 0)
+/** @} end of name */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _EMBARC_ERROR_H_ */
+/** @} end of group EMBARC_ERROR */
diff --git a/bsp/synopsys/embarc/inc/embARC_toolchain.h b/bsp/synopsys/embarc/inc/embARC_toolchain.h
new file mode 100644
index 0000000000..37aef66064
--- /dev/null
+++ b/bsp/synopsys/embarc/inc/embARC_toolchain.h
@@ -0,0 +1,121 @@
+/* ------------------------------------------
+ * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+
+ * 1) Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+
+ * 2) Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+
+ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \version 2016.05
+ * \date 2014-12-25
+ * \author Wayne Ren(Wei.Ren@synopsys.com)
+--------------------------------------------- */
+
+/**
+ * \file
+ * \ingroup	TOOLCHAIN
+ * \brief toolchain dependent definitions
+ */
+
+#include <stdint.h>	/* C99 standard lib */
+#include <limits.h>	/* C99 standard lib */
+#include <stddef.h>	/* C99 standard lib */
+#include <stdbool.h> 	/* C99 standard lib */
+
+#include "embARC_BSP_config.h"
+
+/**
+ * \addtogroup TOOLCHAIN
+ * @{
+ */
+
+#ifndef _EMBARC_TOOLCHAIN_H_
+#define _EMBARC_TOOLCHAIN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  macro definitions of compiler extend function
+ */
+#ifndef __cplusplus				/* C++ supports inline */
+#if __STDC_VERSION__ < 199901L			/* C99 supports inline */
+#ifndef inline
+#define inline	__inline__			/* inline function */
+#endif
+#endif /* __STDC_VERSION__ < 199901L */
+#endif /* __cplusplus */
+
+#ifndef Inline
+#define Inline	static __inline__		/* inline function */
+#endif
+
+#ifndef __cplusplus				/* C++ supports asm */
+#ifndef asm
+#define asm	__asm__				/* inline asm */
+#endif
+#endif /* __cplusplus */
+
+#ifndef Asm
+#define Asm	__asm__ volatile		/* inline asm (no optimization) */
+#endif
+
+/* compiler attributes */
+#define EMBARC_FORCEINLINE	__attribute__((always_inline))
+#define EMBARC_NOINLINE		__attribute__((noinline))
+#define EMBARC_PACKED		__attribute__((packed))
+#define EMBARC_WEAK		__attribute__((weak))
+#define EMBARC_ALIAS(f)		__attribute__((weak, alias (#f)))
+#define EMBARC_LINKTO(f)	__attribute__((alias (#f)))
+#define EMBARC_NORETURN		__attribute__((noreturn))
+#define EMBARC_NAKED		__attribute__((naked))	/* function without return */
+#define EMBARC_ALIGNED(x)	__attribute__((aligned(x)))
+
+
+/* array count macro */
+#define EMBARC_ARRAY_COUNT(x) (sizeof(x)/sizeof(x[0]))
+
+/* convert macro argument to string */
+/* note: this needs one level of indirection, accomplished with the helper macro
+ *       __EMBARC_TO_STRING */
+#define __EMBARC_TO_STRING(x) #x
+#define EMBARC_TO_STRING(x)   __EMBARC_TO_STRING(x)
+
+#if defined(__GNU__)
+/* GNU tool specific definitions */
+
+#elif defined(__MW__)
+/* Metaware tool specific definitions */
+/* Metaware toolchain related definitions */
+
+#else
+#error "unsupported toolchain"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _EMBARC_TOOLCHAIN_H_ */
+/** }@ */
diff --git a/bsp/synopsys/emsk_em9d/.config b/bsp/synopsys/emsk_em9d/.config
new file mode 100644
index 0000000000..55759f136a
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/.config
@@ -0,0 +1,402 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+# CONFIG_RT_USING_USER_MAIN is not set
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+
+#
+# Using WiFi
+#
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_POSIX is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+CONFIG_RT_USING_SAL=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+CONFIG_SAL_USING_AT=y
+# CONFIG_SAL_USING_POSIX is not set
+CONFIG_SAL_SOCKETS_NUM=16
+CONFIG_SAL_PROTO_FAMILIES_NUM=4
+
+#
+# light weight TCP/IP stack
+#
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+CONFIG_RT_USING_LWIP202=y
+# CONFIG_RT_USING_LWIP210 is not set
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.1.30"
+CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+# CONFIG_RT_LWIP_RAW is not set
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=8
+CONFIG_RT_LWIP_PBUF_NUM=16
+CONFIG_RT_LWIP_RAW_PCB_NUM=4
+CONFIG_RT_LWIP_UDP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_SEG_NUM=40
+CONFIG_RT_LWIP_TCP_SND_BUF=8196
+CONFIG_RT_LWIP_TCP_WND=8196
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
+# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=0
+# CONFIG_RT_LWIP_STATS is not set
+# CONFIG_RT_LWIP_DEBUG is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+CONFIG_RT_USING_AT=y
+# CONFIG_AT_DEBUG is not set
+# CONFIG_AT_USING_SERVER is not set
+CONFIG_AT_USING_CLIENT=y
+CONFIG_AT_CLIENT_NUM_MAX=1
+CONFIG_AT_USING_SOCKET=y
+CONFIG_AT_USING_CLI=y
+# CONFIG_AT_PRINT_RAW_CMD is not set
+CONFIG_AT_SW_VERSION_NUM=0x10200
+# CONFIG_LWIP_USING_DHCPD is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+CONFIG_PKG_USING_AT_DEVICE=y
+CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device"
+CONFIG_PKG_AT_INIT_BY_THREAD=y
+# CONFIG_AT_DEVICE_M26 is not set
+# CONFIG_AT_DEVICE_EC20 is not set
+CONFIG_AT_DEVICE_ESP8266=y
+# CONFIG_AT_DEVICE_NOT_SELECTED is not set
+CONFIG_AT_DEVICE_SOCKETS_NUM=5
+CONFIG_AT_DEVICE_NAME="uart0"
+CONFIG_AT_DEVICE_RECV_BUFF_LEN=512
+CONFIG_AT_DEVICE_WIFI_SSID="embarc"
+CONFIG_AT_DEVICE_WIFI_PASSWORD="qazwsxedc"
+CONFIG_PKG_USING_AT_DEVICE_LATEST_VERSION=y
+# CONFIG_PKG_USING_AT_DEVICE_V100 is not set
+# CONFIG_PKG_USING_AT_DEVICE_V110 is not set
+CONFIG_PKG_AT_DEVICE_VER="latest"
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_STM32F4_HAL is not set
+# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_SOC_EMSK=y
+CONFIG_EMSK_USING_UART0=y
+CONFIG_EMSK_USING_UART1=y
diff --git a/bsp/synopsys/emsk_em9d/Kconfig b/bsp/synopsys/emsk_em9d/Kconfig
new file mode 100644
index 0000000000..1748a1e8ae
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/Kconfig
@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_EMSK
+    bool
+    select ARCH_ARC_EM
+    default y
+
+source "$BSP_DIR/drivers/Kconfig"
diff --git a/bsp/synopsys/emsk_em9d/SConscript b/bsp/synopsys/emsk_em9d/SConscript
new file mode 100644
index 0000000000..86b6c891cd
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/SConscript
@@ -0,0 +1,18 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+objs = objs + SConscript(os.path.join(cwd, '../embarc/SConscript'))
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/synopsys/emsk_em9d/SConstruct b/bsp/synopsys/emsk_em9d/SConstruct
new file mode 100644
index 0000000000..a93d89ee74
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/SConstruct
@@ -0,0 +1,52 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread_snps_emsk_em9d.' + rtconfig.TARGET_EXT
+
+# use scons --gdb to debug emsk
+AddOption('--gdb',
+        dest = 'gdb',
+        action = 'store_true',
+        default = False,
+        help = 'use gdb to debug the elf')
+
+if GetOption('gdb'):
+        if os.path.isfile(rtconfig.TARGET):
+            os.system(rtconfig.DBG + rtconfig.DBG_HW_FLAGS + rtconfig.TARGET)
+        else:
+            print rtconfig.TARGET + 'not exist, please build first!!'
+        exit(0)
+
+env = Environment(tools = ['mingw'],
+        AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+        CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        AR = rtconfig.AR, ARFLAGS = '-rc',
+        LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# if the linker script changed, relink the target
+Depends(TARGET, rtconfig.LINK_SCRIPT)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/synopsys/emsk_em9d/applications/SConscript b/bsp/synopsys/emsk_em9d/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/synopsys/emsk_em9d/applications/application.c b/bsp/synopsys/emsk_em9d/applications/application.c
new file mode 100644
index 0000000000..3e12c0ba76
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/applications/application.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rtthread.h>
+
+/* thread phase init */
+static void rt_init_thread_entry(void *parameter)
+{
+    /* do component initialization */
+    rt_components_init();
+
+    /* add your initialization here */
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048,
+                            RT_THREAD_PRIORITY_MAX/3, 20);
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+
+    return 0;
+}
+
diff --git a/bsp/synopsys/emsk_em9d/applications/startup.c b/bsp/synopsys/emsk_em9d/applications/startup.c
new file mode 100644
index 0000000000..f561436272
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/applications/startup.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <board.h>
+
+extern int rt_application_init(void);
+
+void rt_hw_interrupt_init(void)
+{
+    /* rt-thread specific interrupt and exception init */
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
+
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show RT-Thread version */
+    rt_show_version();
+
+    /* initialize memory system */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize system timer */
+    rt_system_timer_init();
+
+    /* initialize soft timer thread */
+    rt_system_timer_thread_init();
+
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int board_main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* invoke rtthread_startup */
+    rtthread_startup();
+
+    return 0;
+}
+
diff --git a/bsp/synopsys/emsk_em9d/drivers/Kconfig b/bsp/synopsys/emsk_em9d/drivers/Kconfig
new file mode 100644
index 0000000000..3cc4d3470d
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/Kconfig
@@ -0,0 +1,10 @@
+
+config EMSK_USING_UART0
+    bool "Using UART0"
+    select RT_USING_SERIAL
+    default y
+
+config EMSK_USING_UART1
+    bool "Using UART1"
+    select RT_USING_SERIAL
+    default y
\ No newline at end of file
diff --git a/bsp/synopsys/emsk_em9d/drivers/SConscript b/bsp/synopsys/emsk_em9d/drivers/SConscript
new file mode 100644
index 0000000000..29272aa88e
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/SConscript
@@ -0,0 +1,15 @@
+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+ASFLAGS = ' -I' + cwd
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h b/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h
new file mode 100644
index 0000000000..8340e94091
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h
@@ -0,0 +1,229 @@
+/* This file is automatically generated from tcf file. DO NOT EDIT */
+#ifndef __core_config_h
+	#define __core_config_h  1
+	#define	core_config_cir_identity	0x00000042
+	#define	core_config_cir_identity_chipid	0
+	#define	core_config_cir_identity_arcnum	0
+	#define	core_config_cir_identity_arcver	66
+	#define	core_config_cir_identity_family	4
+	#define	core_config_cir_identity_corever	2
+	#define	core_config_cir_aux_dccm	0x80000000
+	#define	core_config_bcr_bcr_ver	0x00000002
+	#define	core_config_bcr_bcr_ver_version	2
+	#define	core_config_bcr_vecbase_ac_build	0x00000010
+	#define	core_config_bcr_rf_build	0x0000c902
+	#define	core_config_bcr_rf_build_version	2
+	#define	core_config_bcr_rf_build_p	1
+	#define	core_config_bcr_rf_build_e	0
+	#define	core_config_bcr_rf_build_r	0
+	#define	core_config_bcr_rf_build_b	1
+	#define	core_config_bcr_rf_build_d	3
+	#define	core_config_bcr_dccm_build	0x00010904
+	#define	core_config_bcr_dccm_build_cycles	0
+	#define	core_config_bcr_dccm_build_interleave	1
+	#define	core_config_bcr_dccm_build_size1	0
+	#define	core_config_bcr_dccm_build_size0	9
+	#define	core_config_bcr_dccm_build_version	4
+	#define	core_config_bcr_timer_build	0x00010304
+	#define	core_config_bcr_timer_build_sp1	0
+	#define	core_config_bcr_timer_build_sp0	0
+	#define	core_config_bcr_timer_build_p1	0
+	#define	core_config_bcr_timer_build_p0	1
+	#define	core_config_bcr_timer_build_st1	0
+	#define	core_config_bcr_timer_build_st0	0
+	#define	core_config_bcr_timer_build_rtc	0
+	#define	core_config_bcr_timer_build_rtsc_ver	1
+	#define	core_config_bcr_timer_build_rtsc	0
+	#define	core_config_bcr_timer_build_t0	1
+	#define	core_config_bcr_timer_build_t1	1
+	#define	core_config_bcr_timer_build_version	4
+	#define	core_config_bcr_ap_build	0x00000405
+	#define	core_config_bcr_ap_build_version	5
+	#define	core_config_bcr_ap_build_type	4
+	#define	core_config_bcr_iccm_build	0x00000a04
+	#define	core_config_bcr_iccm_build_iccm1_size1	0
+	#define	core_config_bcr_iccm_build_iccm0_size1	0
+	#define	core_config_bcr_iccm_build_iccm1_size0	0
+	#define	core_config_bcr_iccm_build_iccm0_size0	10
+	#define	core_config_bcr_iccm_build_version	4
+	#define	core_config_bcr_xy_build	0x00001620
+	#define	core_config_bcr_xy_build_memsize	1
+	#define	core_config_bcr_xy_build_interleaved	1
+	#define	core_config_bcr_xy_build_config	2
+	#define	core_config_bcr_xy_build_version	32
+	#define	core_config_bcr_dsp_build	0x00003521
+	#define	core_config_bcr_dsp_build_wide	0
+	#define	core_config_bcr_dsp_build_itu_pa	1
+	#define	core_config_bcr_dsp_build_acc_shift	2
+	#define	core_config_bcr_dsp_build_comp	1
+	#define	core_config_bcr_dsp_build_divsqrt	1
+	#define	core_config_bcr_dsp_build_version	33
+	#define	core_config_bcr_multiply_build	0x00022a06
+	#define	core_config_bcr_multiply_build_version16x16	2
+	#define	core_config_bcr_multiply_build_dsp	2
+	#define	core_config_bcr_multiply_build_cyc	2
+	#define	core_config_bcr_multiply_build_type	2
+	#define	core_config_bcr_multiply_build_version32x32	6
+	#define	core_config_bcr_swap_build	0x00000003
+	#define	core_config_bcr_swap_build_version	3
+	#define	core_config_bcr_norm_build	0x00000003
+	#define	core_config_bcr_norm_build_version	3
+	#define	core_config_bcr_minmax_build	0x00000002
+	#define	core_config_bcr_minmax_build_version	2
+	#define	core_config_bcr_barrel_build	0x00000303
+	#define	core_config_bcr_barrel_build_version	3
+	#define	core_config_bcr_barrel_build_shift_option	3
+	#define	core_config_bcr_isa_config	0x12447402
+	#define	core_config_bcr_isa_config_d	1
+	#define	core_config_bcr_isa_config_c	2
+	#define	core_config_bcr_isa_config_l	0
+	#define	core_config_bcr_isa_config_n	1
+	#define	core_config_bcr_isa_config_a	0
+	#define	core_config_bcr_isa_config_b	0
+	#define	core_config_bcr_isa_config_addr_size	4
+	#define	core_config_bcr_isa_config_lpc_size	7
+	#define	core_config_bcr_isa_config_pc_size	4
+	#define	core_config_bcr_isa_config_version	2
+	#define	core_config_bcr_stack_region_build	0x00000002
+	#define	core_config_bcr_fpu_build	0x00000f02
+	#define	core_config_bcr_fpu_build_da	0
+	#define	core_config_bcr_fpu_build_dd	0
+	#define	core_config_bcr_fpu_build_dc	0
+	#define	core_config_bcr_fpu_build_df	0
+	#define	core_config_bcr_fpu_build_dp	0
+	#define	core_config_bcr_fpu_build_fd	0
+	#define	core_config_bcr_fpu_build_fm	0
+	#define	core_config_bcr_fpu_build_sd	1
+	#define	core_config_bcr_fpu_build_sc	1
+	#define	core_config_bcr_fpu_build_sf	1
+	#define	core_config_bcr_fpu_build_sp	1
+	#define	core_config_bcr_fpu_build_version	2
+	#define	core_config_bcr_bs_build	0x00000001
+	#define	core_config_bcr_bs_build_version	1
+	#define	core_config_bcr_agu_build	0x01988c01
+	#define	core_config_bcr_agu_build_accordian	1
+	#define	core_config_bcr_agu_build_wb_size	4
+	#define	core_config_bcr_agu_build_num_modifier	24
+	#define	core_config_bcr_agu_build_num_offset	8
+	#define	core_config_bcr_agu_build_num_addr	12
+	#define	core_config_bcr_agu_build_version	1
+	#define	core_config_bcr_dmac_build	0x000a0101
+	#define	core_config_bcr_dmac_build_int_cfg	1
+	#define	core_config_bcr_dmac_build_fifo	1
+	#define	core_config_bcr_dmac_build_chan_mem	0
+	#define	core_config_bcr_dmac_build_channels	1
+	#define	core_config_bcr_dmac_build_version	1
+	#define	core_config_bcr_core_config	0x00000101
+	#define	core_config_bcr_core_config_turbo_boost	1
+	#define	core_config_bcr_core_config_version	1
+	#define	core_config_bcr_irq_build	0x13101401
+	#define	core_config_bcr_irq_build_raz	0
+	#define	core_config_bcr_irq_build_f	1
+	#define	core_config_bcr_irq_build_p	3
+	#define	core_config_bcr_irq_build_exts	16
+	#define	core_config_bcr_irq_build_irqs	20
+	#define	core_config_bcr_irq_build_version	1
+	#define	core_config_bcr_pct_build	0x08080102
+	#define	core_config_bcr_pct_build_version	2
+	#define	core_config_bcr_pct_build_s	1
+	#define	core_config_bcr_pct_build_i	0
+	#define	core_config_bcr_pct_build_c	8
+	#define	core_config_bcr_cc_build	0x006f0004
+	#define	core_config_bcr_cc_build_version	4
+	#define	core_config_bcr_cc_build_cc	111
+	#define	core_config_bcr_ifqueue_build	0x00000002
+	#define	core_config_bcr_ifqueue_build_bd	0
+	#define	core_config_bcr_ifqueue_build_version	2
+	#define	core_config_bcr_smart_build	0x00002003
+	#define	core_config_bcr_smart_build_version	3
+	#define	core_config_bcr_smart_build_stack_size	8
+	#define	core_config_cir_aux_iccm	0x00000000
+	#define	core_config_cir_dmp_peripheral	0xf0000000
+	#define	core_config_cir_xccm_base	0xc0000000
+	#define	core_config_cir_yccm_base	0xe0000000
+	#define	core_config_family	4
+	#define	core_config_core_version	2
+	#define	core_config_family_name	"arcv2em"
+	#define	core_config_rgf_num_banks	2
+	#define	core_config_rgf_banked_regs	32
+	#define	core_config_rgf_num_wr_ports	2
+	#define	core_config_endian	"little"
+	#define	core_config_endian_little	1
+	#define	core_config_endian_big	0
+	#define	core_config_lpc_size	32
+	#define	core_config_pc_size	32
+	#define	core_config_addr_size	32
+	#define	core_config_unaligned	1
+	#define	core_config_code_density	1
+	#define	core_config_div_rem	"radix2"
+	#define	core_config_div_rem_radix2	1
+	#define	core_config_turbo_boost	1
+	#define	core_config_swap	1
+	#define	core_config_bitscan	1
+	#define	core_config_mpy_option	"mpyd"
+	#define	core_config_mpy_option_num	8
+	#define	core_config_shift_assist	1
+	#define	core_config_barrel_shifter	1
+	#define	core_config_dsp	1
+	#define	core_config_dsp2	1
+	#define	core_config_dsp_complex	1
+	#define	core_config_dsp_divsqrt	"radix2"
+	#define	core_config_dsp_divsqrt_radix2	1
+	#define	core_config_dsp_itu	1
+	#define	core_config_dsp_accshift	"full"
+	#define	core_config_dsp_accshift_full	1
+	#define	core_config_agu_large	1
+	#define	core_config_agu_wb_depth	4
+	#define	core_config_agu_accord	1
+	#define	core_config_xy	1
+	#define	core_config_xy_config	"dccm_x_y"
+	#define	core_config_xy_config_dccm_x_y	1
+	#define	core_config_xy_size	8192
+	#define	core_config_xy_size_KM	"8K"
+	#define	core_config_xy_interleave	1
+	#define	core_config_xy_x_base	0xc0000000
+	#define	core_config_xy_y_base	0xe0000000
+	#define	core_config_bitstream	1
+	#define	core_config_fpus_div	1
+	#define	core_config_fpu_mac	1
+	#define	core_config_fpus_mpy_slow	1
+	#define	core_config_fpus_div_slow	1
+	#define	core_config_timer0	1
+	#define	core_config_timer0_level	1
+	#define	core_config_timer0_vector	16
+	#define	core_config_timer1	1
+	#define	core_config_timer1_level	0
+	#define	core_config_timer1_vector	17
+	#define	core_config_action_points	2
+	#define	core_config_stack_check	1
+	#define	core_config_smart_stack_entries	8
+	#define	core_config_ifq_present	1
+	#define	core_config_ifq_entries	1
+	#define	core_config_interrupts_present	1
+	#define	core_config_interrupts_number	20
+	#define	core_config_interrupts_priorities	4
+	#define	core_config_interrupts_externals	16
+	#define	core_config_interrupts	20
+	#define	core_config_interrupt_priorities	4
+	#define	core_config_ext_interrupts	16
+	#define	core_config_interrupts_firq	1
+	#define	core_config_interrupts_base	0x0
+	#define	core_config_dccm_present	1
+	#define	core_config_dccm_size	0x20000
+	#define	core_config_dccm_base	0x80000000
+	#define	core_config_dccm_interleave	1
+	#define	core_config_iccm_present	1
+	#define	core_config_iccm0_present	1
+	#define	core_config_iccm_size	0x40000
+	#define	core_config_iccm0_size	0x40000
+	#define	core_config_iccm_base	0x00000000
+	#define	core_config_iccm0_base	0x00000000
+	#define	core_config_pct_counters	8
+	#define	core_config_dmac	1
+	#define	core_config_dmac_channels	2
+	#define	core_config_dmac_registers	0
+	#define	core_config_dmac_fifo_depth	2
+	#define	core_config_dmac_int_config	"single_internal"
+	#define	core_config_clock_speed	20
+#endif /* __core_config_h */
+
diff --git a/bsp/synopsys/emsk_em9d/drivers/board.c b/bsp/synopsys/emsk_em9d/drivers/board.c
new file mode 100644
index 0000000000..449360f3a5
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/board.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <rtdevice.h>
+#include <drivers/serial.h>
+
+#include "board.h"
+#include "inc/arc/arc_timer.h"
+#include "inc/arc/arc_exception.h"
+
+#include "inc/embARC_error.h"
+#include "mux.h"
+#include "dw_uart_obj.h"
+
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    arc_timer_int_clear(BOARD_OS_TIMER_ID);
+    rt_tick_increase();
+}
+
+static void emsk_mux_init(void)
+{
+    MUX_REG *mux_regs;
+
+    mux_regs = (MUX_REG *)(PERIPHERAL_BASE|REL_REGBASE_PINMUX);
+    mux_init(mux_regs);
+
+    /**
+     * + Please refer to corresponding EMSK User Guide for detailed information
+     *   -> Appendix: A  Hardware Functional Description
+     *      -> Pmods Configuration summary
+     * + Set up pin-multiplexer of all PMOD connections
+     *   - PM1 J1: Upper row as UART 0, lower row as SPI Slave
+     *   - PM2 J2: IIC 0 and run/halt signals
+     *   - PM3 J3: GPIO Port A and Port C
+     *   - PM4 J4: IIC 1 and Port D
+     *   - PM5 J5: Upper row as SPI Master, lower row as Port A
+     *   - PM6 J6: Upper row as SPI Master, lower row as Port A
+     */
+    set_pmod_mux(mux_regs, PM1_UR_UART_0 | PM1_LR_SPI_S \
+                | PM2_I2C_HRI           \
+                | PM3_GPIO_AC           \
+                | PM4_I2C_GPIO_D        \
+                | PM5_UR_SPI_M1 | PM5_LR_GPIO_A \
+                | PM6_UR_SPI_M0 | PM6_LR_GPIO_A );
+
+    /**
+     * PM1 upper row as UART
+     * UM4:RXD, UM3:TXD
+     * UM2:RTS_N, UM1:CTS_N
+     */
+    set_uart_map(mux_regs, 0xe4);
+}
+
+static struct rt_serial_device _emsk_uart0;  //abstracted serial for RTT
+static struct rt_serial_device _emsk_uart1;
+
+static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    DEV_UART_PTR uart;
+    unsigned int id;
+    int ret;
+
+    id = (unsigned int)(serial->parent.user_data);
+
+    uart = uart_get_dev(id);
+
+    ret = uart->uart_control(UART_CMD_SET_BAUD, (void *)(cfg->baud_rate));
+
+    if (ret != E_OK) {
+        return RT_ERROR;
+    }
+
+
+    return RT_EOK;
+}
+
+static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    DEV_UART_PTR uart;
+    unsigned int id;
+
+    id = (unsigned int)(serial->parent.user_data);
+    uart = uart_get_dev(id);
+
+    switch (cmd) {
+        case RT_DEVICE_CTRL_CLR_INT:
+            uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
+            break;
+        case RT_DEVICE_CTRL_SET_INT:
+            uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
+            break;
+        case RT_DEVICE_CTRL_SUSPEND:
+            uart->uart_control(UART_CMD_DIS_DEV, (void *)0);
+            break;
+        case RT_DEVICE_CTRL_RESUME:
+            uart->uart_control(UART_CMD_ENA_DEV, (void *)0);
+            break;
+
+        default:
+            return  RT_ERROR;
+            break;
+    }
+
+    return RT_EOK;
+}
+
+static int _putc(struct rt_serial_device *serial, char c)
+{
+    DEV_UART_PTR uart;
+    unsigned int id;
+    int ret;
+
+    id = (unsigned int)(serial->parent.user_data);
+
+    uart = uart_get_dev(id);
+
+    ret = uart->uart_write(&c, 1);
+
+    if (ret < 0) {
+        return -1;
+    } else {
+        return 1;
+    }
+}
+
+static int _getc(struct rt_serial_device *serial)
+{
+    DEV_UART_PTR uart;
+    unsigned int id;
+    unsigned int data;
+    int ret;
+    int rd_avail = 0;
+
+    id = (unsigned int)(serial->parent.user_data);
+    uart = uart_get_dev(id);
+
+    uart->uart_control(UART_CMD_GET_RXAVAIL, (void *)(&rd_avail));
+
+    if (rd_avail > 0) {
+        ret = uart->uart_read(&data, 1);
+    } else {
+        return -1;
+    }
+
+    if (ret < 0) {
+        return -1;
+    } else {
+        return data;
+    }
+
+}
+
+static void _emsk_uart0_isr(void *ptr)
+{
+    rt_hw_serial_isr((struct rt_serial_device*)&_emsk_uart0, RT_SERIAL_EVENT_RX_IND);
+}
+
+static const struct rt_uart_ops _emsk_uart0_ops =
+{
+    _configure,
+    _control,
+    _putc,
+    _getc,
+};
+
+static void _emsk_uart1_isr(void *ptr)
+{
+    rt_hw_serial_isr((struct rt_serial_device*)&_emsk_uart1, RT_SERIAL_EVENT_RX_IND);
+}
+
+static const struct rt_uart_ops _emsk_uart1_ops =
+{
+    _configure,
+    _control,
+    _putc,
+    _getc,
+};
+
+int rt_hw_uart_init(void)
+{
+    DEV_UART_PTR uart;
+    struct serial_configure config;
+    int ret;
+
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
+
+    _emsk_uart0.ops    = &_emsk_uart0_ops;
+    _emsk_uart0.config = config;
+
+    _emsk_uart1.ops    = &_emsk_uart1_ops;
+    _emsk_uart1.config = config;
+
+    /* open UART1 for USB-UART interface */
+    uart = uart_get_dev(DW_UART_1_ID);
+    /* default format: 8bits, no parity, 1 stop bits */
+    ret = uart->uart_open(config.baud_rate);
+
+    if (ret != E_OPNED && ret != E_OK) {
+        return RT_ERROR;
+    }
+
+    /* enable rx int */
+    uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
+    /* use customized int isr */
+    uart->uart_control(UART_CMD_SET_RXCB, _emsk_uart1_isr);
+    uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
+
+    rt_hw_serial_register(&_emsk_uart1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          (void *)DW_UART_1_ID);
+
+     /* open UART0 in PMOD A*/
+    uart = uart_get_dev(DW_UART_0_ID);
+    /* default format: 8bits, no parity, 1 stop bits */
+    ret = uart->uart_open(config.baud_rate);
+
+    if (ret != E_OPNED && ret != E_OK) {
+        return RT_ERROR;
+    }
+
+    /* enable rx int */
+    uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
+    /* use customized int isr */
+    uart->uart_control(UART_CMD_SET_RXCB, _emsk_uart0_isr);
+    uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
+
+    rt_hw_serial_register(&_emsk_uart0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          (void *)DW_UART_0_ID);
+
+    return RT_EOK;
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while(*str != '\0')
+    {
+        if (*str == '\n') {
+            _putc(&_emsk_uart1,'\r');
+        }
+        _putc(&_emsk_uart1,*str);
+        str++;
+    }
+}
+
+int rt_hw_timer_init(void)
+{
+
+    unsigned int cyc = BOARD_CPU_CLOCK / RT_TICK_PER_SECOND;
+
+    int_disable(BOARD_OS_TIMER_INTNO); /* disable os timer interrupt */
+    arc_timer_stop(BOARD_OS_TIMER_ID);
+    arc_timer_start(BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc);
+
+    int_handler_install(BOARD_OS_TIMER_INTNO, (INT_HANDLER)rt_hw_timer_isr);
+    int_enable(BOARD_OS_TIMER_INTNO);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+void rt_hw_board_init()
+{
+    emsk_mux_init();
+
+    rt_hw_uart_init();
+    rt_components_board_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
diff --git a/bsp/synopsys/emsk_em9d/drivers/board.h b/bsp/synopsys/emsk_em9d/drivers/board.h
new file mode 100644
index 0000000000..aebf88bd42
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/board.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "emsk_hardware.h"
+
+#define BOARD_OS_TIMER_ID       0
+#define BOARD_OS_TIMER_INTNO    16
+#define BOARD_CPU_CLOCK         25000000
+
+#if defined(__GNUC__)
+extern int __start_heap;
+#define HEAP_BEGIN      ((void*)&__start_heap)
+#endif
+
+extern int __end_heap;
+#define HEAP_END        (void*)(&__end_heap)
+
+void rt_hw_board_init();
+
+int rt_hw_uart_init(void);
+
+#endif
diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c b/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c
new file mode 100644
index 0000000000..8701a0e9c7
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "inc/arc/arc.h"
+#include "inc/arc/arc_builtin.h"
+
+#include "dw_gpio_obj.h"
+
+#include "emsk_hardware.h"
+/*
+ * Uncomment this to enable default
+ * gpio bit handler output message
+ * by uart
+ */
+
+#ifdef ARC_FEATURE_DMP_PERIPHERAL
+#define PERIPHERAL_BASE     ARC_FEATURE_DMP_PERIPHERAL
+#else
+#define PERIPHERAL_BASE     _arc_aux_read(AUX_DMP_PERIPHERAL)
+#endif
+
+#if (USE_DW_GPIO_PORT_A)
+static DEV_GPIO     port_a;
+static DW_GPIO_PORT dw_gpio_port_a;
+static DEV_GPIO_HANDLER dw_gpio_bit_handler_a[EMSK_GPIO_A_INT_MAX_COUNT];
+static DW_GPIO_BIT_ISR dw_gpio_bit_isr_a = {
+    EMSK_GPIO_A_INT_MAX_COUNT, dw_gpio_bit_handler_a
+};
+
+static int32_t porta_open(uint32_t dir)
+{
+    return dw_gpio_open(&port_a, dir);
+}
+
+static int32_t porta_close(void)
+{
+    return dw_gpio_close(&port_a);
+}
+
+static int32_t porta_control(uint32_t ctrl_cmd, void *param)
+{
+    return dw_gpio_control(&port_a, ctrl_cmd, param);
+}
+
+static int32_t porta_write(uint32_t val, uint32_t mask)
+{
+    return dw_gpio_write(&port_a, val, mask);
+}
+
+static int32_t porta_read(uint32_t *val, uint32_t mask)
+{
+    return dw_gpio_read(&port_a, val, mask);
+}
+
+static void porta_isr(void *ptr)
+{
+    dw_gpio_isr_handler(&port_a, ptr);
+}
+
+static void porta_install(void)
+{
+    uint32_t i;
+    DEV_GPIO_PTR port_ptr = &port_a;
+    DEV_GPIO_INFO_PTR info_ptr = &(port_a.gpio_info);
+    DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_a);
+
+    info_ptr->gpio_ctrl = (void *)dw_port_ptr;
+    info_ptr->opn_cnt = 0;
+    info_ptr->method = 0;
+    info_ptr->direction = 0;
+    info_ptr->extra = 0;
+
+    dw_port_ptr->no = DW_GPIO_PORT_A;
+    dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0);
+    dw_port_ptr->valid_bit_mask = EMSK_GPIO_A_VALID_MASK;
+    dw_port_ptr->intno = INTNO_GPIO;
+    dw_port_ptr->int_handler = porta_isr;
+
+    for (i=0; i<dw_gpio_bit_isr_a.int_bit_max_cnt; i++) {
+        dw_gpio_bit_isr_a.int_bit_handler_ptr[i] = NULL;
+    }
+    dw_port_ptr->gpio_bit_isr = &dw_gpio_bit_isr_a;
+
+    port_ptr->gpio_open = porta_open;
+    port_ptr->gpio_close = porta_close;
+    port_ptr->gpio_control = porta_control;
+    port_ptr->gpio_write = porta_write;
+    port_ptr->gpio_read = porta_read;
+}
+#endif
+
+#if (USE_DW_GPIO_PORT_B)
+static DEV_GPIO     port_b;
+static DW_GPIO_PORT dw_gpio_port_b;
+
+static int32_t portb_open(uint32_t dir)
+{
+    return dw_gpio_open(&port_b, dir);
+}
+
+static int32_t portb_close(void)
+{
+    return dw_gpio_close(&port_b);
+}
+
+static int32_t portb_control(uint32_t ctrl_cmd, void *param)
+{
+    return dw_gpio_control(&port_b, ctrl_cmd, param);
+}
+
+static int32_t portb_write(uint32_t val, uint32_t mask)
+{
+    return dw_gpio_write(&port_b, val, mask);
+}
+
+static int32_t portb_read(uint32_t *val, uint32_t mask)
+{
+    return dw_gpio_read(&port_b, val, mask);
+}
+
+static void portb_isr(void *ptr)
+{
+    dw_gpio_isr_handler(&port_b, ptr);
+}
+
+static void portb_install(void)
+{
+    DEV_GPIO_PTR port_ptr = &port_b;
+    DEV_GPIO_INFO_PTR info_ptr = &(port_b.gpio_info);
+    DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_b);
+
+    info_ptr->gpio_ctrl = (void *)dw_port_ptr;
+    info_ptr->opn_cnt = 0;
+    info_ptr->method = 0;
+    info_ptr->direction = 0;
+    info_ptr->extra = 0;
+
+    dw_port_ptr->no = DW_GPIO_PORT_B;
+    dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0);
+    dw_port_ptr->valid_bit_mask = EMSK_GPIO_B_VALID_MASK;
+
+    dw_port_ptr->intno = INTNO_GPIO;
+    dw_port_ptr->int_handler = portb_isr;
+    dw_port_ptr->gpio_bit_isr = NULL;
+
+    port_ptr->gpio_open = portb_open;
+    port_ptr->gpio_close = portb_close;
+    port_ptr->gpio_control = portb_control;
+    port_ptr->gpio_write = portb_write;
+    port_ptr->gpio_read = portb_read;
+}
+#endif
+
+
+#if (USE_DW_GPIO_PORT_C)
+static DEV_GPIO     port_c;
+static DW_GPIO_PORT dw_gpio_port_c;
+
+static int32_t portc_open(uint32_t dir)
+{
+    return dw_gpio_open(&port_c, dir);
+}
+
+static int32_t portc_close(void)
+{
+    return dw_gpio_close(&port_c);
+}
+
+static int32_t portc_control(uint32_t ctrl_cmd, void *param)
+{
+    return dw_gpio_control(&port_c, ctrl_cmd, param);
+}
+
+static int32_t portc_write(uint32_t val, uint32_t mask)
+{
+    return dw_gpio_write(&port_c, val, mask);
+}
+
+static int32_t portc_read(uint32_t *val, uint32_t mask)
+{
+    return dw_gpio_read(&port_c, val, mask);
+}
+
+static void portc_isr(void *ptr)
+{
+    dw_gpio_isr_handler(&port_c, ptr);
+}
+
+static void portc_install(void)
+{
+    DEV_GPIO_PTR port_ptr = &port_c;
+    DEV_GPIO_INFO_PTR info_ptr = &(port_c.gpio_info);
+    DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_c);
+
+    info_ptr->gpio_ctrl = (void *)dw_port_ptr;
+    info_ptr->opn_cnt = 0;
+    info_ptr->method = 0;
+    info_ptr->direction = 0;
+    info_ptr->extra = 0;
+
+    dw_port_ptr->no = DW_GPIO_PORT_C;
+    dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0);
+    dw_port_ptr->valid_bit_mask = EMSK_GPIO_C_VALID_MASK;
+
+    dw_port_ptr->intno = INTNO_GPIO;
+    dw_port_ptr->int_handler = portc_isr;
+    dw_port_ptr->gpio_bit_isr = NULL;
+
+    port_ptr->gpio_open = portc_open;
+    port_ptr->gpio_close = portc_close;
+    port_ptr->gpio_control = portc_control;
+    port_ptr->gpio_write = portc_write;
+    port_ptr->gpio_read = portc_read;
+}
+#endif
+
+#if (USE_DW_GPIO_PORT_D)
+static DEV_GPIO     port_d;
+static DW_GPIO_PORT dw_gpio_port_d;
+
+static int32_t portd_open(uint32_t dir)
+{
+    return dw_gpio_open(&port_d, dir);
+}
+
+static int32_t portd_close(void)
+{
+    return dw_gpio_close(&port_d);
+}
+
+static int32_t portd_control(uint32_t ctrl_cmd, void *param)
+{
+    return dw_gpio_control(&port_d, ctrl_cmd, param);
+}
+
+static int32_t portd_write(uint32_t val, uint32_t mask)
+{
+    return dw_gpio_write(&port_d, val, mask);
+}
+
+static int32_t portd_read(uint32_t *val, uint32_t mask)
+{
+    return dw_gpio_read(&port_d, val, mask);
+}
+
+static void portd_isr(void *ptr)
+{
+    dw_gpio_isr_handler(&port_d, ptr);
+}
+
+static void portd_install(void)
+{
+    DEV_GPIO_PTR port_ptr = &port_d;
+    DEV_GPIO_INFO_PTR info_ptr = &(port_d.gpio_info);
+    DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_d);
+
+    info_ptr->gpio_ctrl = (void *)dw_port_ptr;
+    info_ptr->opn_cnt = 0;
+    info_ptr->method = 0;
+    info_ptr->direction = 0;
+    info_ptr->extra = 0;
+
+    dw_port_ptr->no = DW_GPIO_PORT_D;
+    dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0);
+    dw_port_ptr->valid_bit_mask = EMSK_GPIO_D_VALID_MASK;
+
+    dw_port_ptr->intno = INTNO_GPIO;
+    dw_port_ptr->int_handler = portd_isr;
+    dw_port_ptr->gpio_bit_isr = NULL;
+
+    port_ptr->gpio_open = portd_open;
+    port_ptr->gpio_close = portd_close;
+    port_ptr->gpio_control = portd_control;
+    port_ptr->gpio_write = portd_write;
+    port_ptr->gpio_read = portd_read;
+}
+#endif
+
+DEV_GPIO_PTR gpio_get_dev(int32_t gpio_id)
+{
+    static uint32_t install_flag = 0;
+
+    /* intall device objects */
+    if (install_flag == 0) {
+        install_flag = 1;
+        dw_gpio_all_install();
+    }
+
+    switch (gpio_id) {
+#if (USE_DW_GPIO_PORT_A)
+        case DW_GPIO_PORT_A: return &port_a;
+#endif
+#if (USE_DW_GPIO_PORT_B)
+        case DW_GPIO_PORT_B: return &port_b;
+#endif
+#if (USE_DW_GPIO_PORT_C)
+        case DW_GPIO_PORT_C: return &port_c;
+#endif
+#if (USE_DW_GPIO_PORT_D)
+        case DW_GPIO_PORT_D: return &port_d;
+#endif
+        default:
+            break;
+    }
+    return NULL;
+}
+
+void dw_gpio_all_install(void)
+{
+#if (USE_DW_GPIO_PORT_A)
+    porta_install();
+#endif
+#if (USE_DW_GPIO_PORT_B)
+    portb_install();
+#endif
+#if (USE_DW_GPIO_PORT_C)
+    portc_install();
+#endif
+#if (USE_DW_GPIO_PORT_D)
+    portd_install();
+#endif
+}
diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h b/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h
new file mode 100644
index 0000000000..d39a09159d
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _DW_GPIO_OBJ_H_
+#define _DW_GPIO_OBJ_H_
+
+#include "device/designware/gpio/dw_gpio.h"
+
+/**
+ * \name    Designware GPIO Port Bank Control Macros
+ * @{
+ */
+#define USE_DW_GPIO_PORT_A      1
+#define USE_DW_GPIO_PORT_B      1
+#define USE_DW_GPIO_PORT_C      1
+#define USE_DW_GPIO_PORT_D      1
+/** @} end of name */
+
+/**
+ * \name    Designware GPIO Port Interrupt Available Number Macros
+ * @{
+ */
+#define EMSK_GPIO_A_INT_MAX_COUNT   32
+#define EMSK_GPIO_B_INT_MAX_COUNT   0
+#define EMSK_GPIO_C_INT_MAX_COUNT   0
+#define EMSK_GPIO_D_INT_MAX_COUNT   0
+/** @} end of name */
+
+/**
+ * \name    Designware GPIO Port Available Bits Macros
+ * @{
+ */
+#define EMSK_GPIO_A_VALID_MASK      DW_GPIO_MASK_ALL
+#define EMSK_GPIO_B_VALID_MASK      DW_GPIO_MASK_ALL
+#define EMSK_GPIO_C_VALID_MASK      DW_GPIO_MASK_ALL
+#define EMSK_GPIO_D_VALID_MASK      DW_GPIO_MASK_ALL
+/** @} end of name */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void dw_gpio_all_install(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DW_GPIO_OBJ_H_*/
diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c b/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c
new file mode 100644
index 0000000000..9e3ebd3db9
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "inc/arc/arc.h"
+#include "inc/arc/arc_builtin.h"
+#include "inc/embARC_toolchain.h"
+#include "inc/embARC_error.h"
+
+#include "inc/arc/arc_exception.h"
+#include "device/designware/uart/dw_uart.h"
+#include "dw_uart_obj.h"
+
+#include "emsk_hardware.h"
+
+#define DW_UART_FIFO_LEN    32
+
+/**
+ * \name    EMSK DesignWare UART 0 Object Instantiation
+ * @{
+ */
+#if (USE_DW_UART_0)
+static void dw_uart_0_isr(void *ptr);
+#define DW_UART_0_RELBASE   (REL_REGBASE_UART0) /*!< designware uart 0 relative baseaddr */
+#define DW_UART_0_INTNO     (INTNO_UART0)       /*!< designware uart 0 interrupt number  */
+
+DEV_UART        dw_uart_0;          /*!< designware uart object */
+DW_UART_CTRL    dw_uart_0_ctrl = {          /*!< designware uart 0 ctrl */
+    0, CLK_BUS_APB, DW_UART_0_INTNO, (INT_HANDLER)dw_uart_0_isr,
+    DW_UART_FIFO_LEN, DW_UART_FIFO_LEN, 0
+};
+
+/** designware uart 0 open */
+static int32_t dw_uart_0_open (uint32_t baud)
+{
+    return dw_uart_open(&dw_uart_0, baud);
+}
+/** designware uart 0 close */
+static int32_t dw_uart_0_close (void)
+{
+    return dw_uart_close(&dw_uart_0);
+}
+/** designware uart 0 control */
+static int32_t dw_uart_0_control (uint32_t ctrl_cmd, void *param)
+{
+    return dw_uart_control(&dw_uart_0, ctrl_cmd, param);
+}
+/** designware uart 0 write */
+static int32_t dw_uart_0_write (const void *data, uint32_t len)
+{
+    return dw_uart_write(&dw_uart_0, data, len);
+}
+/** designware uart 0 close */
+static int32_t dw_uart_0_read (void *data, uint32_t len)
+{
+    return dw_uart_read(&dw_uart_0, data, len);
+}
+/** designware uart 0 interrupt rountine */
+static void dw_uart_0_isr(void *ptr)
+{
+    dw_uart_isr(&dw_uart_0, ptr);
+}
+/** install designware uart 0 to system */
+static void dw_uart_0_install(void)
+{
+    uint32_t uart_abs_base = 0;
+    DEV_UART *dw_uart_ptr = &dw_uart_0;
+    DEV_UART_INFO *dw_uart_info_ptr = &(dw_uart_0.uart_info);
+    DW_UART_CTRL *dw_uart_ctrl_ptr = &dw_uart_0_ctrl;
+
+    /**
+     * get absolute designware base address
+     */
+    uart_abs_base = (uint32_t)PERIPHERAL_BASE + DW_UART_0_RELBASE;
+    dw_uart_ctrl_ptr->dw_uart_regbase = uart_abs_base;
+
+    /** uart info init */
+    dw_uart_info_ptr->uart_ctrl = (void *)dw_uart_ctrl_ptr;
+    dw_uart_info_ptr->opn_cnt = 0;
+    dw_uart_info_ptr->status = 0;
+    dw_uart_info_ptr->baudrate = UART_BAUDRATE_115200;  /* default 115200bps */
+
+    /** uart dev init */
+    dw_uart_ptr->uart_open = dw_uart_0_open;
+    dw_uart_ptr->uart_close = dw_uart_0_close;
+    dw_uart_ptr->uart_control = dw_uart_0_control;
+    dw_uart_ptr->uart_write = dw_uart_0_write;
+    dw_uart_ptr->uart_read = dw_uart_0_read;
+
+}
+#endif /* USE_DW_UART_0 */
+/** @} end of name */
+
+/**
+ * \name    EMSK DesignWare UART 1 Object Instantiation
+ * @{
+ */
+#if (USE_DW_UART_1)
+static void dw_uart_1_isr(void *ptr);
+#define DW_UART_1_RELBASE   (REL_REGBASE_UART1) /*!< designware uart 1 relative baseaddr */
+#define DW_UART_1_INTNO     (INTNO_UART1)       /*!< designware uart 1 interrupt number  */
+
+DEV_UART        dw_uart_1;          /*!< designware uart 1 object */
+DW_UART_CTRL    dw_uart_1_ctrl = {          /*!< designware uart 1 ctrl */
+    0, CLK_BUS_APB, DW_UART_1_INTNO, (INT_HANDLER)dw_uart_1_isr,
+    DW_UART_FIFO_LEN, DW_UART_FIFO_LEN, 0
+};
+
+/** designware uart 1 open */
+static int32_t dw_uart_1_open (uint32_t baud)
+{
+    return dw_uart_open(&dw_uart_1, baud);
+}
+/** designware uart 1 close */
+static int32_t dw_uart_1_close (void)
+{
+    return dw_uart_close(&dw_uart_1);
+}
+/** designware uart 1 control */
+static int32_t dw_uart_1_control (uint32_t ctrl_cmd, void *param)
+{
+    return dw_uart_control(&dw_uart_1, ctrl_cmd, param);
+}
+/** designware uart 1 write */
+static int32_t dw_uart_1_write (const void *data, uint32_t len)
+{
+    return dw_uart_write(&dw_uart_1, data, len);
+}
+/** designware uart 1 close */
+static int32_t dw_uart_1_read (void *data, uint32_t len)
+{
+    return dw_uart_read(&dw_uart_1, data, len);
+}
+/** designware uart 1 interrupt routine */
+static void dw_uart_1_isr(void *ptr)
+{
+    dw_uart_isr(&dw_uart_1, ptr);
+}
+/** install designware uart 1 to system */
+static void dw_uart_1_install(void)
+{
+    uint32_t uart_abs_base = 0;
+    DEV_UART *dw_uart_ptr = &dw_uart_1;
+    DEV_UART_INFO *dw_uart_info_ptr = &(dw_uart_1.uart_info);
+    DW_UART_CTRL *dw_uart_ctrl_ptr = &dw_uart_1_ctrl;
+
+    /**
+     * get absolute designware base address
+     */
+    uart_abs_base = (uint32_t)PERIPHERAL_BASE + DW_UART_1_RELBASE;
+    dw_uart_ctrl_ptr->dw_uart_regbase = uart_abs_base;
+
+    /** uart info init */
+    dw_uart_info_ptr->uart_ctrl = (void *)dw_uart_ctrl_ptr;
+    dw_uart_info_ptr->opn_cnt = 0;
+    dw_uart_info_ptr->status = 0;
+    dw_uart_info_ptr->baudrate = UART_BAUDRATE_115200;  /* default 115200bps */
+
+    /** uart dev init */
+    dw_uart_ptr->uart_open = dw_uart_1_open;
+    dw_uart_ptr->uart_close = dw_uart_1_close;
+    dw_uart_ptr->uart_control = dw_uart_1_control;
+    dw_uart_ptr->uart_write = dw_uart_1_write;
+    dw_uart_ptr->uart_read = dw_uart_1_read;
+}
+#endif /* USE_DW_UART_1 */
+/** @} end of name */
+
+/** get one designware device structure */
+DEV_UART_PTR uart_get_dev(int32_t uart_id)
+{
+    static uint32_t install_flag = 0;
+
+    /* intall device objects */
+    if (install_flag == 0) {
+        install_flag = 1;
+        dw_uart_all_install();
+    }
+
+    switch (uart_id) {
+#if (USE_DW_UART_0)
+        case DW_UART_0_ID:
+            return &dw_uart_0;
+            break;
+#endif
+#if (USE_DW_UART_1)
+        case DW_UART_1_ID:
+            return &dw_uart_1;
+            break;
+#endif
+        default:
+            break;
+    }
+    return NULL;
+}
+
+/**
+ * \brief   install all uart objects
+ * \note    \b MUST be called during system init
+ */
+void dw_uart_all_install(void)
+{
+#if (USE_DW_UART_0)
+    dw_uart_0_install();
+#endif
+#if (USE_DW_UART_1)
+    dw_uart_1_install();
+#endif
+}
diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h b/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h
new file mode 100644
index 0000000000..7a63880fab
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _DW_UART_OBJ_H_
+#define _DW_UART_OBJ_H_
+
+#include "device/device_hal/inc/dev_uart.h"
+
+/**
+ * \name    DesignWare UART Object Number
+ * @{
+ */
+#define DW_UART_NUM (2) /*!< DesignWare UART valid number */
+/** @} end of name */
+
+/**
+ * \name    Designware UART Object ID Macros
+ * @{
+ */
+#define DW_UART_0_ID    0   /*!< uart 0 id macro */
+#define DW_UART_1_ID    1   /*!< uart 1 id macro */
+/** @} end of name */
+
+/**
+ * \name    Designware UART Object Control Macros
+ * @{
+ */
+#define USE_DW_UART_0   1   /*!< enable use designware uart 0 */
+#define USE_DW_UART_1   1   /*!< enable use designware uart 1 */
+/** @} end of name */
+
+/**
+ * \name    Designware UART Ringbuffer Size Control Macros
+ * @{
+ */
+#define MAX_SNDBUF_SIZE 256 /*!< max size of uart send buffer */
+#define MAX_RCVBUF_SIZE 10  /*!< max size of uart recv buffer */
+/** @} end of name */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void dw_uart_all_install(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DW_UART_OBJ_H_ */
diff --git a/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h b/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h
new file mode 100644
index 0000000000..706aac94c4
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _EMBARC_BSP_CONFIG_H_
+#define _EMBARC_BSP_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BOARD_EMSK
+/****************************************************************************
+ * BSP Definitions
+ ****************************************************************************/
+/**
+ *  Toolchain Definition for MetaWare or GNU
+ */
+//#define __MW__
+#define __GNU__
+
+/**
+ *  Must be set.
+ *  If changed, modify .lcf file for
+ *  .stack ALIGN(4) SIZE(524288): {}
+ *  .heap? ALIGN(4) SIZE(524288): {}
+ */
+#define _STACKSIZE      (4 * 1024)
+#define _HEAPSZ         (32 * 1024)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _EMBARC_CONFIG_BSP_H_ */
diff --git a/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h b/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h
new file mode 100644
index 0000000000..d60e314389
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _EMSK_HARDWARE_H_
+#define _EMSK_HARDWARE_H_
+
+#include "inc/arc/arc_feature_config.h"
+
+/** CPU Clock Frequency definition */
+#if defined(BOARD_CPU_FREQ)
+        /*!< Get cpu clock frequency definition from build system */
+        #define CLK_CPU                 (BOARD_CPU_FREQ)
+#elif defined(ARC_FEATURE_CPU_CLOCK_FREQ)
+        /*!< Get cpu clock frequency definition from tcf file */
+        #define CLK_CPU                 (ARC_FEATURE_CPU_CLOCK_FREQ)
+#else
+        /*!< Default cpu clock frequency */
+        #define CLK_CPU                 (20000000)
+#endif
+
+/** Peripheral Bus Reference Clock definition */
+#ifdef BOARD_DEV_FREQ
+        /*!< Get peripheral bus reference clock defintion from build system */
+        #define CLK_BUS_APB             (BOARD_DEV_FREQ)
+#else
+        /*!< Default peripheral bus reference clock defintion */
+        #define CLK_BUS_APB             (50000000U)
+#endif
+
+#ifdef ARC_FEATURE_DMP_PERIPHERAL
+#define PERIPHERAL_BASE         ARC_FEATURE_DMP_PERIPHERAL
+#else
+#define PERIPHERAL_BASE         _arc_aux_read(AUX_DMP_PERIPHERAL)
+#endif
+
+/* Device Register Base Address */
+#define REL_REGBASE_PINMUX              (0x00000000U)           /*!< PINMUX */
+#define REL_REGBASE_SPI_MST_CS_CTRL     (0x00000014U)           /*!< SPI Master Select Ctrl */
+#define REL_REGBASE_GPIO0               (0x00002000U)           /*!< GPIO 0 Onboard */
+#define REL_REGBASE_TIMERS              (0x00003000U)           /*!< DW TIMER */
+#define REL_REGBASE_I2C0                (0x00004000U)           /*!< I2C 0 */
+#define REL_REGBASE_I2C1                (0x00005000U)           /*!< I2C 1 */
+#define REL_REGBASE_SPI0                (0x00006000U)           /*!< SPI Master  */
+#define REL_REGBASE_SPI1                (0x00007000U)           /*!< SPI Slave   */
+#define REL_REGBASE_UART0               (0x00008000U)           /*!< UART0 is connected to PMOD */
+#define REL_REGBASE_UART1               (0x00009000U)           /*!< UART1 is USB-UART�� use UART1 as default */
+#define REL_REGBASE_UART2               (0x0000A000U)           /*!< UART2 */
+#define REL_REGBASE_WDT                 (0x0000B000U)           /*!< WDT  */
+// #define REL_REGBASE_I2S_MASTER_IN    (0x0000C000U)           /*!< I2S Master In  */
+// #define REL_REGBASE_I2S_MASTER_OUT   (0x0000D000U)           /*!< I2S Master Out  */
+// #define REL_REGBASE_GMAC             (0x0000E000U)           /*!< GMAC  */
+
+/* Interrupt Connection */
+#define INTNO_TIMER0                    16                      /*!< ARC Timer0 */
+#define INTNO_TIMER1                    17                      /*!< ARC Timer1 */
+#define INTNO_SECURE_TIMER0             20                      /*!< Core Secure Timer 0 */
+#define INTNO_DMA_START                 22                      /*!< Core DMA Controller */
+#define INTNO_DMA_COMPLETE              22                      /*!< Core DMA Controller Complete */
+#define INTNO_DMA_ERROR                 23                      /*!< Core DMA Controller Error */
+#define INTNO_GPIO                      24                      /*!< GPIO controller */
+#define INTNO_I2C0                      25                      /*!< I2C_0 controller */
+#define INTNO_I2C1                      26                      /*!< I2C_1 controller */
+#define INTNO_SPI_MASTER                27                      /*!< SPI Master controller */
+#define INTNO_SPI_SLAVE                 28                      /*!< SPI Slave controller */
+#define INTNO_UART0                     29                      /*!< UART0 */
+#define INTNO_UART1                     30                      /*!< UART1 */
+#define INTNO_UART2                     31                      /*!< UART2 */
+#define INTNO_DW_WDT                    32                      /*!< WDT */
+#define INTNO_DW_TMR0                   33                      /*!< DW Timer 0 */
+#define INTNO_DW_TMR1                   34                      /*!< DW Timer 1 */
+// #define INTNO_I2S_Master_In          33                      /*!< I2S Master In */
+// #define INTNO_I2S_Master_Out         34                      /*!< I2S Master Out */
+// #define INTNO_GMAC                   35                      /*!< GMAC */
+
+/* SPI Mater Signals Usage */
+#define EMSK_SPI_LINE_0                 0                       /*!< CS0 -- Pmod 6 pin1 */
+#define EMSK_SPI_LINE_1                 1                       /*!< CS1 -- Pmod 5 pin1 or Pmod 6 pin 7 */
+#define EMSK_SPI_LINE_2                 2                       /*!< CS2 -- Pmod 6 pin8 */
+#define EMSK_SPI_LINE_SDCARD            3                       /*!< CS3 -- On-board SD card  */
+#define EMSK_SPI_LINE_SPISLAVE          4                       /*!< CS4 -- Internal SPI slave */
+#define EMSK_SPI_LINE_SFLASH            5                       /*!< CS5 -- On-board SPI Flash memory */
+
+#endif  /* _EMSK_HARDWARE_H_ */
diff --git a/bsp/synopsys/emsk_em9d/drivers/mux.c b/bsp/synopsys/emsk_em9d/drivers/mux.c
new file mode 100644
index 0000000000..a56cb15212
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/mux.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "mux_hal.h"
+#include "mux.h"
+
+static MUX_REG *mux_ctrl_regs = (MUX_REG *)0;
+
+/** initialize i2c controller and set slave device address */
+void mux_init(MUX_REG *mux_regs)
+{
+    // Initialize Mux controller registers by default values
+    mux_regs[PMOD_MUX_CTRL] = PMOD_MUX_CTRL_DEFAULT;
+    mux_regs[SPI_MAP_CTRL] =  SPI_MAP_CTRL_DEFAULT;
+    mux_regs[UART_MAP_CTRL] = UART_MAP_CTRL_DEFAULT;
+    mux_ctrl_regs = mux_regs;
+}
+
+/** Get mux ctrl register pointer, only valid after mux_init */
+MUX_REG *get_mux_regs(void)
+{
+    return mux_ctrl_regs;
+}
+
+/** set PMOD muxer scheme */
+void set_pmod_mux(MUX_REG *mux_regs, uint32_t val)
+{
+    mux_regs[PMOD_MUX_CTRL] = val;
+}
+
+/** get PMOD muxer scheme */
+uint32_t get_pmod_mux(MUX_REG *mux_regs)
+{
+    return (uint32_t) mux_regs[PMOD_MUX_CTRL];
+}
+
+/** set PMOD muxer scheme */
+void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits)
+{
+    mux_regs[PMOD_MUX_CTRL] = ((mux_regs[PMOD_MUX_CTRL] & ~change_bits) | val);
+}
+
+/** set SPI connection scheme */
+void set_spi_map(MUX_REG *mux_regs, uint32_t val)
+{
+    mux_regs[SPI_MAP_CTRL] = val;
+}
+
+/** get SPI connection scheme */
+uint32_t get_spi_map(MUX_REG *mux_regs)
+{
+    return (uint32_t) mux_regs[SPI_MAP_CTRL];
+}
+
+/** set UART connection scheme */
+void set_uart_map(MUX_REG *mux_regs, uint32_t val)
+{
+    mux_regs[UART_MAP_CTRL] = val;
+}
+
+/** get UART connection scheme */
+uint32_t get_uart_map(MUX_REG *mux_regs)
+{
+    return (uint32_t) mux_regs[UART_MAP_CTRL];
+}
diff --git a/bsp/synopsys/emsk_em9d/drivers/mux.h b/bsp/synopsys/emsk_em9d/drivers/mux.h
new file mode 100644
index 0000000000..47f796bebe
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/mux.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _MUX_H_
+#define _MUX_H_
+
+#include "inc/embARC_toolchain.h"
+
+#define BIT0			(0)
+#define BIT1			(1)
+#define BIT2			(2)
+#define BIT3			(3)
+#define PM1_OFFSET		(0)
+#define PM2_OFFSET		(4)
+#define PM3_OFFSET		(8)
+#define PM4_OFFSET		(12)
+#define PM5_OFFSET		(16)
+#define PM6_OFFSET		(20)
+#define PM7_OFFSET		(24)
+
+#define PM1_MASK		(0xf << PM1_OFFSET)
+#define PM2_MASK		(0xf << PM2_OFFSET)
+#define PM3_MASK		(0xf << PM3_OFFSET)
+#define PM4_MASK		(0xf << PM4_OFFSET)
+#define PM5_MASK		(0xf << PM5_OFFSET)
+#define PM6_MASK		(0xf << PM6_OFFSET)
+#define PM7_MASK		(0xf << PM7_OFFSET)
+
+
+#define SPI_MAP_NORMAL		(0)
+#define SPI_MAP_LOOPBACK	(1)
+
+#define UART_MAP_TYPE4		(0xE4)
+#define UART_MAP_TYPE3		(0x6C)
+
+/**
+ * \name	Default pin muxer settings
+ * @{
+ */
+#define PMOD_MUX_CTRL_DEFAULT	(0)			/*!< all pins are configured as GPIO inputs */
+#define SPI_MAP_CTRL_DEFAULT	(SPI_MAP_NORMAL)	/*!< normal SPI mode */
+#define UART_MAP_CTRL_DEFAULT	(UART_MAP_TYPE4)	/*!< TYPE4 PMOD compatible */
+/** @} end of name */
+
+/**
+ * \name	PMOD 1 Multiplexor
+ * @{
+ */
+#define PM1_UR_GPIO_C		((0 << BIT0) << PM1_OFFSET)	/*!< Pmod1[4:1] are connected to DW GPIO Port C[11:8] */
+#define PM1_UR_UART_0		((1 << BIT0) << PM1_OFFSET)	/*!< Pmod1[4:1] are connected to DW UART0 signals */
+
+#define PM1_LR_GPIO_A		((0 << BIT2) << PM1_OFFSET)	/*!< Pmod1[10:7] are connected to DW GPIO Port A[11:8] */
+#define PM1_LR_SPI_S		((1 << BIT2) << PM1_OFFSET)	/*!< Pmod1[10:7] are connected to DW SPI Slave signals */
+/** @} end of name */
+
+
+/**
+ * \name	PMOD 2 Multiplexor
+ * @{
+ */
+#define PM2_GPIO_AC		((0 << BIT0) << PM2_OFFSET)	/*!< Pmod2[4:1]	 are connected to DW GPIO Port C[15:12],
+									Pmod2[10:7] are connected to DW GPIO Port A[15:12]  */
+
+#define PM2_I2C_HRI		((1 << BIT0) << PM2_OFFSET)	/*!< connect I2C to Pmod2[4:1] and halt/run interface to Pmod2[10:7] */
+/** @} end of name */
+
+
+/**
+ * \name	PMOD 3 Multiplexor
+ * @{
+ */
+#define PM3_GPIO_AC		((0 << BIT0) << PM3_OFFSET)	/*!< Pmod3[4:1]  are connected to DW GPIO Port C[19:16],
+									Pmod3[10:7] are connected to DW GPIO Port A[19:16]  */
+
+#define PM3_I2C_GPIO_D		((1 << BIT0) << PM3_OFFSET)	/*!< Pmod3[4:3]  are connected to DW I2C signals,
+									Pmod3[2:1]  are connected to DW GPIO Port D[1:0],
+									Pmod3[10:7] are connected to DW GPIO Port D[3:2] */
+/** @} end of name */
+
+
+/**
+ * \name	PMOD 4 Multiplexor
+ * @{
+ */
+#define PM4_GPIO_AC		((0 << BIT0) << PM4_OFFSET)	/*!< Pmod4[4:1]  are connected to DW GPIO Port C[23:20],
+									Pmod4[10:7] are connected to DW GPIO Port A[23:20] */
+
+#define PM4_I2C_GPIO_D		((1 << BIT0) << PM4_OFFSET)	/*!< Pmod4[4:3]  are connected to DW I2C signals,
+									Pmod4[2:1]  are connected to DW GPIO Port D[5:4],
+									Pmod4[10:7] are connected to DW GPIO Port D[7:6] */
+/** @} end of name */
+
+/**
+ * \name	PMOD 5 Multiplexor
+ * @{
+ */
+#define PM5_UR_GPIO_C		((0 << BIT0) << PM5_OFFSET)	/*!< Pmod5[4:1] are connected to DW GPIO Port C[27:24] */
+#define PM5_UR_SPI_M1		((1 << BIT0) << PM5_OFFSET)	/*!< Pmod5[4:1] are connected to DW SPI Master signals using CS1_N */
+
+#define PM5_LR_GPIO_A		((0 << BIT2) << PM5_OFFSET)	/*!< Pmod5[10:7] are connected to DW GPIO Port A[27:24] */
+#define PM5_LR_SPI_M2		((1 << BIT2) << PM5_OFFSET)	/*!< Pmod5[10:7] are connected to DW SPI Master signals using CS2_N */
+/** @} end of name */
+
+
+/**
+ * \name	PMOD 6 Multiplexor
+ * @{
+ */
+#define PM6_UR_GPIO_C		((0 << BIT0) << PM6_OFFSET)	/*!< Pmod6[4:1] are connected to DW GPIO Port C[31:28] */
+#define PM6_UR_SPI_M0		((1 << BIT0) << PM6_OFFSET)	/*!< Pmod6[4:1] are connected to DW SPI Master signals using CS0_N */
+
+#define PM6_LR_GPIO_A		((0 << BIT2) << PM6_OFFSET)	/*!< Pmod6[10:7] are connected to DW GPIO Port A[31:28] */
+
+#define PM6_LR_CSS_STAT 	((1 << BIT2) << PM6_OFFSET)	/*!< Pmod6[8:7] are connected to the DW SPI Master chip select signals CS1_N and CS2_N,
+									Pmod6[6:5] are connected to the ARC EM halt and sleep status signals */
+/** @} end of name */
+
+/**
+ * \name	PMOD 7 Multiplexor
+ * @{
+ */
+#define PM7_GPIO_D		((0 << BIT0) << PM7_OFFSET)	/*!< Pmod7[4:1] are connected to DW GPIO Port D[11:8] */
+#define PM7_STAT		((1 << BIT0) << PM7_OFFSET)	/*!< Pmod7[4:1] are connected to the ARC EM sleep status signals */
+/** @} end of name */
+typedef volatile uint32_t MUX_REG;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void mux_init(MUX_REG *mux_regs);
+extern MUX_REG *get_mux_regs(void);
+extern void set_pmod_mux(MUX_REG *mux_regs, uint32_t val);
+extern uint32_t get_pmod_mux(MUX_REG *mux_regs);
+extern void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits);
+extern void set_spi_map(MUX_REG *mux_regs, uint32_t val);
+extern uint32_t get_spi_map(MUX_REG *mux_regs);
+extern void set_uart_map(MUX_REG *mux_regs, uint32_t val);
+extern uint32_t get_uart_map(MUX_REG *mux_regs);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MUX_H_ */
diff --git a/bsp/synopsys/emsk_em9d/drivers/mux_hal.h b/bsp/synopsys/emsk_em9d/drivers/mux_hal.h
new file mode 100644
index 0000000000..9a5c8c14b9
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/drivers/mux_hal.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _MUX_HAL_H_
+#define _MUX_HAL_H_
+
+/**
+ * \name	Mux Control Register Index
+ * @{
+ */
+#define PMOD_MUX_CTRL	0	/*!< 32-bits, offset 0x0,
+					This register controls mapping of the peripheral device signals on Pmod connectors */
+
+#define I2C_MAP_CTRL	1	/*!< 32-bits, offset 0x4 */
+
+#define SPI_MAP_CTRL	2	/*!< 32-bits, offset 0x8,
+					SPI_MAP_CTRL[0] selects the mode of operation of the SPI Slave:
+					- Normal operation, SPI_MAP_CTRL[0]=0: SPI Slave is connected to Pmod1 at connector J1.
+					- Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to the SPI Master inside the FPGA using CS4.
+							 */
+
+#define UART_MAP_CTRL	3	/*!< 32-bits, offset 0x8,
+					This register controls the mapping of the UART signals on the Pmod1 connector. */
+/** @} end of name */
+
+
+#endif	/* _MUX_HAL_H_ */
diff --git a/bsp/synopsys/emsk_em9d/emsk_em9d.ld b/bsp/synopsys/emsk_em9d/emsk_em9d.ld
new file mode 100644
index 0000000000..849ecf6329
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/emsk_em9d.ld
@@ -0,0 +1,114 @@
+MEMORY
+{
+ ICCM : ORIGIN = 0x00000000, LENGTH = 0x40000
+ DCCM : ORIGIN = 0x80000000, LENGTH = 0x20000
+ EXT_RAM : ORIGIN = 0x10000000, LENGTH = 0x8000000
+}
+ENTRY(_start)
+SECTIONS
+{
+ .init :
+ {
+  _f_init = .;
+  KEEP (*(.init_vector))
+  KEEP (*(.init_bootstrap))
+  _e_init = .;
+ } > EXT_RAM
+ .vector : ALIGN(1024)
+ {
+  _f_vector = .;
+  *(.vector)
+  _e_vector = .;
+ } > EXT_RAM
+ .text : ALIGN(4)
+ {
+  _f_text = .;
+  *(.text .text.* .gnu.linkonce.t.*)
+  _e_text = .;
+ } > EXT_RAM
+ .rodata : ALIGN(4)
+ {
+  _f_rodata = .;
+
+  /* section information for finsh shell */
+  . = ALIGN(4);
+  __fsymtab_start = .;
+  KEEP(*(FSymTab))
+  __fsymtab_end = .;
+  . = ALIGN(4);
+  __vsymtab_start = .;
+  KEEP(*(VSymTab))
+  __vsymtab_end = .;
+
+  . = ALIGN(4);
+  __rt_init_start = .;
+  KEEP(*(SORT(.rti_fn*)))
+   __rt_init_end = .;
+  . = ALIGN(4);
+
+
+  __CTOR_LIST__ = .;
+  LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+  KEEP(*(SORT_BY_NAME(".ctors*")))
+  LONG(0)
+  __CTOR_END__ = .;
+  . = ALIGN(4);
+  __init_array_start = .;
+  KEEP(*(SORT_BY_NAME(".init_array*")))
+  __init_array_end = .;
+  . = ALIGN(4);
+  __DTOR_LIST__ = .;
+  LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+  KEEP(*(SORT_BY_NAME(".dtors*")))
+  LONG(0)
+  __DTOR_END__ = .;
+  *(.rodata .rodata.* .gnu.linkonce.r.*)
+  _e_rodata = .;
+ } > EXT_RAM
+ .data : ALIGN(4)
+ {
+  _f_data = .;
+  *(.data .data.* .gnu.linkonce.d.*)
+  _f_sdata = .;
+  __SDATA_BEGIN__ = .;
+  *(.sdata .sdata.* .gnu.linkonce.s.*)
+  _e_sdata = .;
+  _e_data = .;
+ } > EXT_RAM
+ .bss (NOLOAD) : ALIGN(8)
+ {
+  PROVIDE (__sbss_start = .);
+  PROVIDE (___sbss_start = .);
+  _f_bss = .;
+  _f_sbss = .;
+  *(.dynsbss)
+  *(.sbss .sbss.* .gnu.linkonce.sb.*)
+  *(.scommon)
+  _e_sbss = .;
+  PROVIDE (__sbss_end = .);
+  PROVIDE (___sbss_end = .);
+  *(.dynbss)
+  *(.bss .bss.* .gnu.linkonce.b.*)
+  *(COMMON)
+  _e_bss = .;
+ } > EXT_RAM
+ .stack (NOLOAD) :
+ {
+  . = ALIGN(4);
+  _f_stack = .;
+  . = . + 4096;
+  _e_stack = .;
+ } > EXT_RAM
+ .heap (NOLOAD) :
+ {
+  . = ALIGN(4);
+  __start_heap = . ;
+  _f_heap = .;
+  . = . + 0x8000;
+  _e_heap = .;
+  __end_heap = . ;
+ } > EXT_RAM
+ _load_addr_text = LOADADDR(.text);
+ _load_addr_rodata = LOADADDR(.rodata);
+ _load_addr_data = LOADADDR(.data);
+}
diff --git a/bsp/synopsys/emsk_em9d/openocd.log b/bsp/synopsys/emsk_em9d/openocd.log
new file mode 100644
index 0000000000..4ef893515e
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/openocd.log
@@ -0,0 +1,9 @@
+Warn : deprecated option: -p/--pipe. Use '-c "gdb_port pipe; log_output openocd.log"' instead.
+adapter speed: 5000 kHz
+Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
+Info : clock speed 5000 kHz
+Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2)
+Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2)
+target state: halted
+Info : accepting 'gdb' connection from pipe
+Info : dropped 'gdb' connection
diff --git a/bsp/synopsys/emsk_em9d/rtconfig.h b/bsp/synopsys/emsk_em9d/rtconfig.h
new file mode 100644
index 0000000000..865e753ae5
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/rtconfig.h
@@ -0,0 +1,142 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX	6
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE	4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX	32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="1000" />
+#define RT_TICK_PER_SECOND	1000
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE	512
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
+// #define RT_THREAD_DEBUG
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+// #define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO	4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE	512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND	10
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+// #define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_MEMHEAP_AS_HEAP" description="Using Memory Heap Object as system heap" default="true" />
+// #define RT_USING_MEMHEAP_AS_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    64
+// <bool name=RT_USING_INTERRUPT_INFO description="Using interrupt information description" default="true" />
+#define RT_USING_INTERRUPT_INFO
+// </section>
+
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME	"uart1"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_MSH" description="Using module shell" default="true" />
+#define FINSH_USING_MSH
+// <bool name="FINSH_USING_MSH_DEFAULT" description="The default shell is msh" default="true" />
+#define FINSH_USING_MSH_DEFAULT
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE	4096
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_LIBC" description="Using C library" default="true" />
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+#define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+// #define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+// #define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX	2
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX	4
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN1">1</item>
+// <item description="LFN1">2</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN	1
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
+#define RT_DFS_ELM_MAX_LFN	64
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+// #define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
+// #define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
+#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+// </section>
+// </RDTConfigurator>
+
+
+#endif
diff --git a/bsp/synopsys/emsk_em9d/rtconfig.py b/bsp/synopsys/emsk_em9d/rtconfig.py
new file mode 100644
index 0000000000..7ba12867fd
--- /dev/null
+++ b/bsp/synopsys/emsk_em9d/rtconfig.py
@@ -0,0 +1,60 @@
+import os
+
+# toolchains options
+ARCH='arc'
+CPU='em'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# only support GNU GCC compiler
+PLATFORM 	= 'gcc'
+EXEC_PATH 	= 'C:/arc/gnu/bin'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arc-elf32-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    DBG = PREFIX + 'gdb'
+    DEVICE = ' -mno-sdata -Wall -mcpu=em4_fpus -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter -mfpu=fpus_all'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LINK_SCRIPT = 'emsk_em9d.ld'
+    LFLAGS = DEVICE + ' -mno-sdata -nostartfiles -Wl,--gc-sections,-Map=emsk_em9d.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT
+
+    OPENOCD_SCRIPT_ROOT = 'C:/arc/gnu/share/openocd/scripts'
+    OPENOCD_CFG_FILE = OPENOCD_SCRIPT_ROOT + '/board/snps_em_sk_v2.2.cfg'
+
+    OPENOCD_OPTIONS  = '-s %s -f %s' % (OPENOCD_SCRIPT_ROOT, OPENOCD_CFG_FILE)
+
+    DBG_HW_FLAGS = ''' -ex "target remote | openocd --pipe %s" -ex "load" ''' % OPENOCD_OPTIONS
+
+
+    TARGET = 'rtthread_snps_emsk_em9d.' + TARGET_EXT
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
+            SIZE + ' $TARGET \n'
+    #POST_ACTION = DBG + DBG_HW_FLAGS + TARGET
diff --git a/libcpu/arc/SConscript b/libcpu/arc/SConscript
new file mode 100644
index 0000000000..cbec0b5ec1
--- /dev/null
+++ b/libcpu/arc/SConscript
@@ -0,0 +1,17 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+
+# add common code files
+group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/arc/common/SConscript b/libcpu/arc/common/SConscript
new file mode 100644
index 0000000000..1c77347e61
--- /dev/null
+++ b/libcpu/arc/common/SConscript
@@ -0,0 +1,10 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+
+group = DefineGroup('cpu', src, depend = [], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arc/em/SConscript b/libcpu/arc/em/SConscript
new file mode 100644
index 0000000000..49c32b689d
--- /dev/null
+++ b/libcpu/arc/em/SConscript
@@ -0,0 +1,17 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_gcc.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arc/em/contex_gcc.S b/libcpu/arc/em/contex_gcc.S
new file mode 100644
index 0000000000..a8abe089bf
--- /dev/null
+++ b/libcpu/arc/em/contex_gcc.S
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define __ASSEMBLY__
+#include "inc/arc/arc.h"
+#include "inc/arc/arc_asm_common.h"
+
+.global rt_interrupt_enter; .type rt_interrupt_enter, %function
+.global rt_interrupt_leave; .type rt_interrupt_leave, %function
+.global context_switch_reqflg; .type context_switch_reqflg, %object
+.global rt_interrupt_from_thread; .type rt_interrupt_from_thread, %object
+.global rt_interrupt_to_thread; .type rt_interrupt_to_thread, %object
+
+	.text
+	.align 4
+dispatcher:
+	st sp, [r0]
+	ld sp, [r1]
+	pop r0
+	j [r0]
+
+/* return routine when task dispatch happened in task context */
+dispatch_r:
+	RESTORE_NONSCRATCH_REGS
+	j	[blink]
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.global rt_hw_interrupt_disable
+.type rt_hw_interrupt_disable, %function
+rt_hw_interrupt_disable:
+ 	clri r0
+ 	j [blink]
+
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.global rt_hw_interrupt_enable
+.type rt_hw_interrupt_enable, %function
+rt_hw_interrupt_enable:
+	seti r0
+	j [blink]
+
+
+.global rt_hw_context_switch_interrupt
+.type rt_hw_context_switch_interrupt, %function
+rt_hw_context_switch_interrupt:
+	st r0, [rt_interrupt_from_thread]
+	st r1, [rt_interrupt_to_thread]
+	mov r0, 1
+	st r0, [context_switch_reqflg]
+	j [blink]
+
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.global rt_hw_context_switch
+.type rt_hw_context_switch, %function
+rt_hw_context_switch:
+	SAVE_NONSCRATCH_REGS
+	mov r2, dispatch_r
+	push r2
+	b dispatcher
+
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.global rt_hw_context_switch_to
+.type rt_hw_context_switch_to, %function
+rt_hw_context_switch_to:
+	ld sp, [r0]
+	pop r0
+	j [r0]
+
+.global start_r
+.type start_r, %function
+start_r:
+	pop blink;
+	pop r1
+	pop r2
+	pop r0
+
+	j_s.d [r1]
+	kflag r2
+
+/****** exceptions and interrupts handing ******/
+/****** entry for exception handling ******/
+	.global exc_entry_cpu
+	.align 4
+exc_entry_cpu:
+
+	EXCEPTION_PROLOGUE
+
+	mov	blink,	sp
+	mov	r3, sp		/* as exception handler's para(p_excinfo) */
+
+	ld	r0, [exc_nest_count]
+	add	r1, r0, 1
+	st	r1, [exc_nest_count]
+	cmp	r0, 0
+	bne	exc_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+exc_handler_1:
+	PUSH	blink
+
+	lr	r0, [AUX_ECR]
+	lsr	r0, r0, 16
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]
+
+	mov	r0, r3
+	jl	[r2]
+
+/* interrupts are not allowed */
+ret_exc:
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	cmp	r0, 0
+	bne.d	ret_exc_1
+	st	r0, [r1]
+
+	ld	r0, [context_switch_reqflg]
+	cmp	r0, 0
+	bne	ret_exc_2
+ret_exc_1:	/* return from non-task context, interrupts or exceptions are nested */
+	EXCEPTION_EPILOGUE
+	rtie
+
+/* there is a dispatch request */
+ret_exc_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+
+	/* clear exception bit to do exception exit by SW */
+	lr	r0, [AUX_STATUS32]
+	bclr	r0, r0, AUX_STATUS_BIT_AE
+	kflag	r0
+
+	mov	r1, ret_exc_r	/* save return address */
+	PUSH	r1
+
+	ld 	r0, [rt_interrupt_from_thread]
+	ld 	r1, [rt_interrupt_to_thread]
+	b	dispatcher
+
+ret_exc_r:
+	/* recover exception status */
+	lr	r0, [AUX_STATUS32]
+	bset	r0, r0, AUX_STATUS_BIT_AE
+	kflag	r0
+
+	RESTORE_CALLEE_REGS
+	EXCEPTION_EPILOGUE
+	rtie
+
+/****** entry for normal interrupt exception handling ******/
+	.global exc_entry_int	/* entry for interrupt handling */
+	.align 4
+exc_entry_int:
+#if ARC_FEATURE_FIRQ == 1
+/*  check whether it is P0 interrupt */
+#if ARC_FEATURE_RGF_NUM_BANKS > 1
+	lr	r0, [AUX_IRQ_ACT]
+	btst	r0, 0
+	jnz	exc_entry_firq
+#else
+	PUSH	r10
+	lr	r10, [AUX_IRQ_ACT]
+	btst	r10, 0
+	POP	r10
+	jnz	exc_entry_firq
+#endif
+#endif
+	INTERRUPT_PROLOGUE
+
+	mov	blink, sp
+
+	clri	/* disable interrupt */
+	ld	r3, [exc_nest_count]
+	add	r2, r3, 1
+	st	r2, [exc_nest_count]
+	seti	/* enable higher priority interrupt */
+
+	cmp	r3, 0
+	bne	irq_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+irq_handler_1:
+	PUSH	blink
+
+	jl 	rt_interrupt_enter
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	sr	r0, [AUX_IRQ_SELECT]
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
+/* handle software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d irq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+irq_hint_handled:
+	lr	r3, [AUX_IRQ_PRIORITY]
+	PUSH	r3		/* save irq priority */
+
+	jl	[r2]		/* jump to interrupt handler */
+	jl	rt_interrupt_leave
+ret_int:
+	clri			/* disable interrupt */
+	POP	r3		/* irq priority */
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	cmp	r0, 0
+	bne.d	ret_int_1
+	st	r0, [r1]
+
+	ld	r0, [context_switch_reqflg]
+	cmp	r0, 0
+	bne	ret_int_2
+ret_int_1:	/* return from non-task context */
+	INTERRUPT_EPILOGUE
+	rtie
+/* there is a dispatch request */
+ret_int_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	/* interrupt return by SW */
+	lr	r10, [AUX_IRQ_ACT]
+	PUSH	r10
+	bclr	r10, r10, r3	/* clear related bits in IRQ_ACT */
+	sr	r10, [AUX_IRQ_ACT]
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+	mov	r1, ret_int_r	/* save return address */
+	PUSH	r1
+
+	ld 	r0, [rt_interrupt_from_thread]
+	ld 	r1, [rt_interrupt_to_thread]
+	b	dispatcher
+
+ret_int_r:
+	RESTORE_CALLEE_REGS
+	/* recover AUX_IRQ_ACT to restore the interrup status */
+	POPAX	AUX_IRQ_ACT
+	INTERRUPT_EPILOGUE
+	rtie
\ No newline at end of file
diff --git a/libcpu/arc/em/cpuport.c b/libcpu/arc/em/cpuport.c
new file mode 100644
index 0000000000..88c2e12f9b
--- /dev/null
+++ b/libcpu/arc/em/cpuport.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <rtthread.h>
+
+#include "inc/arc/arc_exception.h"
+
+/* enable interrupt and set interrupt priority mask */
+#define ARC_INIT_STATUS (AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1))
+
+
+extern void start_r(void);
+
+
+rt_uint32_t context_switch_reqflg;
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+
+struct init_stack_frame {
+	rt_uint32_t pc;
+	rt_uint32_t blink;
+	rt_uint32_t task;
+	rt_uint32_t status32;
+	rt_uint32_t r0;
+};
+
+/**
+ * shutdown CPU
+ */
+void rt_hw_cpu_shutdown(void)
+{
+
+}
+
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct init_stack_frame *stack_frame;
+    rt_uint8_t         *stk;
+
+    stk  = stack_addr + sizeof(rt_uint32_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
+    stk -= sizeof(struct init_stack_frame);
+
+    stack_frame = (struct init_stack_frame *)stk;
+
+    stack_frame->pc = (rt_uint32_t)start_r;
+    stack_frame->blink = (rt_uint32_t)texit;
+    stack_frame->task = (rt_uint32_t)tentry;
+    stack_frame->status32 = ARC_INIT_STATUS;
+	stack_frame->r0 = (rt_uint32_t)parameter;
+
+    return stk;
+}
+
+
+/**
+ * This function set the hook, which is invoked on fault exception handling.
+ *
+ * @param exception_handle the exception handling hook function.
+ */
+void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
+{
+    exception_handle = exception_handle;
+}
\ No newline at end of file
-- 
cgit v1.3.1


From 159def753f719e18e65110de47c8a4385cb33e3f Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Thu, 14 Mar 2019 15:45:20 +0800
Subject: arm926内容整理
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/arm/arm926/context_gcc.S |   1 +
 libcpu/arm/arm926/cpuport.c     |  44 ++--
 libcpu/arm/arm926/machine.c     |  41 +++
 libcpu/arm/arm926/mmu.c         |  40 +--
 libcpu/arm/arm926/mmu.h         |   5 +-
 libcpu/arm/arm926/stack.c       |   2 +-
 libcpu/arm/arm926/start_gcc.S   | 557 +++++++++++++++++++++-------------------
 libcpu/arm/arm926/trap.c        |  91 +++----
 8 files changed, 420 insertions(+), 361 deletions(-)
 create mode 100644 libcpu/arm/arm926/machine.c

(limited to 'libcpu')

diff --git a/libcpu/arm/arm926/context_gcc.S b/libcpu/arm/arm926/context_gcc.S
index b6b7863679..f69aa9f5ba 100644
--- a/libcpu/arm/arm926/context_gcc.S
+++ b/libcpu/arm/arm926/context_gcc.S
@@ -10,6 +10,7 @@
 
 #define NOINT   0xC0
 
+.text
 ;/*
 ; * rt_base_t rt_hw_interrupt_disable();
 ; */
diff --git a/libcpu/arm/arm926/cpuport.c b/libcpu/arm/arm926/cpuport.c
index 1efb23e896..035e97d543 100644
--- a/libcpu/arm/arm926/cpuport.c
+++ b/libcpu/arm/arm926/cpuport.c
@@ -23,30 +23,30 @@ rt_inline rt_uint32_t cp15_rd(void)
 {
     rt_uint32_t i;
 
-    __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
     return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
     __asm volatile(\
-                         "mrc  p15,0,r0,c1,c0,0\n\t"    \
-                         "orr  r0,r0,%0\n\t"            \
-                         "mcr  p15,0,r0,c1,c0,0"        \
-                         :                              \
-                         :"r" (bit)                     \
-                         :"memory");
+                   "mrc  p15,0,r0,c1,c0,0\n\t"    \
+                   "orr  r0,r0,%0\n\t"            \
+                   "mcr  p15,0,r0,c1,c0,0"        \
+                   :                              \
+                   : "r"(bit)                     \
+                   : "memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
     __asm volatile(\
-                         "mrc  p15,0,r0,c1,c0,0\n\t"    \
-                         "bic  r0,r0,%0\n\t"            \
-                         "mcr  p15,0,r0,c1,c0,0"        \
-                         :                              \
-                         :"r" (bit)                     \
-                         :"memory");
+                   "mrc  p15,0,r0,c1,c0,0\n\t"    \
+                   "bic  r0,r0,%0\n\t"            \
+                   "mcr  p15,0,r0,c1,c0,0"        \
+                   :                              \
+                   : "r"(bit)                     \
+                   : "memory");
 }
 #endif
 
@@ -152,7 +152,7 @@ void rt_hw_cpu_reset()
     rt_kprintf("Restarting system...\n");
     machine_reset();
 
-    while(1);    /* loop forever and wait for reset to happen */
+    while (1);   /* loop forever and wait for reset to happen */
 
     /* NEVER REACHED */
 }
@@ -206,21 +206,7 @@ int __rt_ffs(int value)
 #elif defined(__GNUC__) || defined(__ICCARM__)
 int __rt_ffs(int value)
 {
-    register rt_uint32_t x;
-
-    if (value == 0)
-        return value;
-
-    __asm
-    (
-        "rsb %[temp], %[val], #0\n"
-        "and %[temp], %[temp], %[val]\n"
-        "clz %[temp], %[temp]\n"
-        "rsb %[temp], %[temp], #32\n"
-        :[temp] "=r"(x)
-        :[val] "r"(value)
-    );
-    return x;
+    return __builtin_ffs(value);
 }
 #endif
 
diff --git a/libcpu/arm/arm926/machine.c b/libcpu/arm/arm926/machine.c
new file mode 100644
index 0000000000..23953dea42
--- /dev/null
+++ b/libcpu/arm/arm926/machine.c
@@ -0,0 +1,41 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+RT_WEAK void machine_reset(void)
+{
+    rt_kprintf("reboot system...\n");
+    rt_hw_interrupt_disable();
+    while (1);
+}
+
+RT_WEAK void machine_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+    rt_hw_interrupt_disable();
+    while (1);
+}
+
diff --git a/libcpu/arm/arm926/mmu.c b/libcpu/arm/arm926/mmu.c
index f1e475189b..19d70b9b0b 100644
--- a/libcpu/arm/arm926/mmu.c
+++ b/libcpu/arm/arm926/mmu.c
@@ -140,7 +140,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-    while(ptr < buffer + size)
+    while (ptr < buffer + size)
     {
         __asm volatile { MCR p15, 0, ptr, c7, c14, 1 }
         ptr += CACHE_LINE_SIZE;
@@ -211,18 +211,18 @@ void mmu_setttbase(register rt_uint32_t i)
      * set by page table entry
      */
     value = 0;
-    asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+    asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
     value = 0x55555555;
-    asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+    asm volatile("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
 
-    asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+    asm volatile("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-    asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm volatile("mcr p15,0, %0, c3, c0,  0": :"r"(i));
 }
 
 void mmu_enable()
@@ -321,7 +321,7 @@ void mmu_disable_alignfault()
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-    asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm volatile("mcr p15, 0, %0, c7, c14, 2": :"r"(index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -330,9 +330,9 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-    while(ptr < buffer + size)
+    while (ptr < buffer + size)
     {
-        asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+        asm volatile("mcr p15, 0, %0, c7, c14, 1": :"r"(ptr));
 
         ptr += CACHE_LINE_SIZE;
     }
@@ -347,7 +347,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while (ptr < buffer + size)
     {
-        asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        asm volatile("mcr p15, 0, %0, c7, c10, 1": :"r"(ptr));
 
         ptr += CACHE_LINE_SIZE;
     }
@@ -361,7 +361,7 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while (ptr < buffer + size)
     {
-        asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        asm volatile("mcr p15, 0, %0, c7, c6, 1": :"r"(ptr));
 
         ptr += CACHE_LINE_SIZE;
     }
@@ -369,19 +369,19 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 void mmu_invalidate_tlb()
 {
-    asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm volatile("mcr p15, 0, %0, c8, c7, 0": :"r"(0));
 
 }
 
 void mmu_invalidate_icache()
 {
-    asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm volatile("mcr p15, 0, %0, c7, c5, 0": :"r"(0));
 
 }
 
 void mmu_invalidate_dcache_all()
 {
-    asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
+    asm volatile("mcr p15, 0, %0, c7, c6, 0": :"r"(0));
 
 }
 #endif
@@ -389,10 +389,10 @@ void mmu_invalidate_dcache_all()
 /* level1 page table */
 #if defined(__ICCARM__)
 #pragma data_alignment=(16*1024)
-static volatile rt_uint32_t _page_table[4*1024];
+static volatile rt_uint32_t _page_table[4 * 1024];
 #else
-static volatile rt_uint32_t _page_table[4*1024] \
-    __attribute__((aligned(16*1024)));
+static volatile rt_uint32_t _page_table[4 * 1024] \
+__attribute__((aligned(16 * 1024)));
 #endif
 
 void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
@@ -401,11 +401,11 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
     volatile rt_uint32_t *pTT;
     volatile int nSec;
     int i = 0;
-    pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
-    nSec=(vaddrEnd>>20)-(vaddrStart>>20);
-    for(i=0; i<=nSec; i++)
+    pTT = (rt_uint32_t *)_page_table + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for (i = 0; i <= nSec; i++)
     {
-        *pTT = attr |(((paddrStart>>20)+i)<<20);
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
         pTT++;
     }
 }
diff --git a/libcpu/arm/arm926/mmu.h b/libcpu/arm/arm926/mmu.h
index 7b930f5358..36fdbeacd8 100644
--- a/libcpu/arm/arm926/mmu.h
+++ b/libcpu/arm/arm926/mmu.h
@@ -5,6 +5,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
  */
 
 #ifndef __MMU_H__
@@ -45,5 +46,7 @@ struct mem_desc
 };
 
 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
-
+void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size);
+void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
+void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
 #endif
diff --git a/libcpu/arm/arm926/stack.c b/libcpu/arm/arm926/stack.c
index fa98feb824..f90bfa8c22 100644
--- a/libcpu/arm/arm926/stack.c
+++ b/libcpu/arm/arm926/stack.c
@@ -38,7 +38,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
 
     stack_addr += sizeof(rt_uint32_t);
     stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
-    stk      = (rt_uint32_t *)stack_addr;
+    stk  = (rt_uint32_t *)stack_addr;
 
     *(--stk) = (rt_uint32_t)tentry;         /* entry point */
     *(--stk) = (rt_uint32_t)texit;          /* lr */
diff --git a/libcpu/arm/arm926/start_gcc.S b/libcpu/arm/arm926/start_gcc.S
index fee8e018cb..35c1f1722e 100644
--- a/libcpu/arm/arm926/start_gcc.S
+++ b/libcpu/arm/arm926/start_gcc.S
@@ -11,295 +11,320 @@
  * 2015-06-04     aozima     Align stack address to 8 byte.
  */
 
-#include "rt_low_level_init.h"
-
-#define S_FRAME_SIZE    (18*4)   //72
-
-@#define S_SPSR          (17*4)   //SPSR
-@#define S_CPSR          (16*4)   //CPSR
-#define S_PC            (15*4)   //R15
-@#define S_LR            (14*4)   //R14
-@#define S_SP            (13*4)   //R13
-
-@#define S_IP            (12*4)   //R12
-@#define S_FP            (11*4)   //R11
-@#define S_R10           (10*4)
-@#define S_R9            (9*4)
-@#define S_R8            (8*4)
-@#define S_R7            (7*4)
-@#define S_R6            (6*4)
-@#define S_R5            (5*4)
-@#define S_R4            (4*4)
-@#define S_R3            (3*4)
-@#define S_R2            (2*4)
-@#define S_R1            (1*4)
-@#define S_R0            (0*4)
-
-#define MODE_SYS        0x1F
-#define MODE_FIQ        0x11
-#define MODE_IRQ        0x12
-#define MODE_SVC        0x13
-#define MODE_ABT        0x17
-#define MODE_UND        0x1B
-#define MODEMASK        0x1F
-
-#define NOINT           0xC0
-
-@;----------------------- Stack and Heap Definitions ---------------------------
-    .section .nobss, "w"
-
-    .space UND_STK_SIZE
+.equ MODE_USR,        0x10
+.equ MODE_FIQ,        0x11
+.equ MODE_IRQ,        0x12
+.equ MODE_SVC,        0x13
+.equ MODE_ABT,        0x17
+.equ MODE_UND,        0x1B
+.equ MODE_SYS,        0x1F
+.equ MODEMASK,        0x1F
+.equ NOINT,           0xC0
+
+.equ I_BIT,           0x80
+.equ F_BIT,           0x40
+
+.equ UND_STACK_SIZE,  0x00000100
+.equ SVC_STACK_SIZE,  0x00000100
+.equ ABT_STACK_SIZE,  0x00000100
+.equ FIQ_STACK_SIZE,  0x00000100
+.equ IRQ_STACK_SIZE,  0x00000100
+.equ SYS_STACK_SIZE,  0x00000100
+
+ /*
+ ***************************************
+ * Interrupt vector table
+ ***************************************
+ */
+.section .vectors
+.code 32
+
+.global system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+_vector_reset:
+    .word reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl    16,0xdeadbeef
+
+ /*
+ ***************************************
+ *  Stack and Heap Definitions 
+ ***************************************
+ */
+    .section .data
+    .space UND_STACK_SIZE
     .align 3
-    .global UND_STACK_START
-UND_STACK_START:
+    .global und_stack_start
+und_stack_start:
 
-    .space ABT_STK_SIZE
+    .space ABT_STACK_SIZE
     .align 3
-    .global ABT_STACK_START
-ABT_STACK_START:
+    .global abt_stack_start
+abt_stack_start:
 
-    .space FIQ_STK_SIZE
+    .space FIQ_STACK_SIZE
     .align 3
-    .global FIQ_STACK_START
-FIQ_STACK_START:
+    .global fiq_stack_start
+fiq_stack_start:
 
-    .space IRQ_STK_SIZE
+    .space IRQ_STACK_SIZE
     .align 3
-    .global IRQ_STACK_START
-IRQ_STACK_START:
+    .global irq_stack_start
+irq_stack_start:
 
-    .skip SYS_STK_SIZE
+    .skip SYS_STACK_SIZE
     .align 3
-    .global SYS_STACK_START
-SYS_STACK_START:
+    .global sys_stack_start
+sys_stack_start:
 
-    .space SVC_STK_SIZE
+    .space SVC_STACK_SIZE
     .align 3
-    .global SVC_STACK_START
-SVC_STACK_START:
-
-@;--------------Jump vector table-----------------------------------------------
-    .section .init, "ax"
-    .arm
-
-    .global start
-start:
-    LDR     PC, vector_reset
-    LDR     PC, vector_undef
-    LDR     PC, vector_swi
-    LDR     PC, vector_pabt
-    LDR     PC, vector_dabt
-    LDR     PC, vector_resv
-    LDR     PC, vector_irq
-    LDR     PC, vector_fiq
-
-vector_reset:
-    .word  Reset_Handler
-vector_undef:
-    .word  Undef_Handler
-vector_swi:
-    .word  SWI_Handler
-vector_pabt:
-    .word  PAbt_Handler
-vector_dabt:
-    .word  DAbt_Handler
-vector_resv:
-    .word  Resv_Handler
-vector_irq:
-    .word  IRQ_Handler
-vector_fiq:
-    .word  FIQ_Handler
-
-    .balignl     16,0xdeadbeef
-
-@;----------------- Reset Handler ---------------------------------------------
-    .global rt_low_level_init
-    .global main
-    .global Reset_Handler
-Reset_Handler:
-    @; Set the cpu to SVC32 mode
-    MRS     R0, CPSR
-    BIC     R0, R0, #MODEMASK
-    ORR     R0, R0, #MODE_SVC|NOINT
-    MSR     CPSR_cxsf, R0
+    .global svc_stack_start
+svc_stack_start:
+
+/*
+ ***************************************
+ * Startup Code 
+ ***************************************
+ */
+    .section .text
+    .global reset
+reset:
+    /* Enter svc mode and mask interrupts */
+    mrs r0, cpsr
+    bic r0, r0, #MODEMASK
+    orr r0, r0, #MODE_SVC|NOINT
+    msr cpsr_cxsf, r0
+
+    /* init cpu  */
+    bl  cpu_init_crit
+    
+    /* todo:copyself to link address */
+    
+    /* Copy vector to the correct address */
+    ldr r0, =system_vectors
+    mrc p15, 0, r2, c1, c0, 0
+    ands r2, r2, #(1 << 13)
+    ldreq r1, =0x00000000
+    ldrne r1, =0xffff0000
+    ldmia r0!, {r2-r8, r10}
+    stmia r1!, {r2-r8, r10}
+    ldmia r0!, {r2-r8, r10}
+    stmia r1!, {r2-r8, r10}
+
+    /* turn off the watchdog */
+    ldr r0, =0x01C20CB8
+    mov     r1, #0x0
+    str     r1, [r0]
+
+    /* mask all IRQs source */
+    ldr r1, =0xffffffff
+    ldr r0, =0x01C20430
+    str r1, [r0], #0x04
+    str r1, [r0]
+    
+    /* Call low level init function */
+    ldr     sp, =svc_stack_start
+    ldr     r0, =rt_low_level_init
+    blx     r0
+    
+    /* init stack */
+    bl stack_setup
     
-    @; Set CO-Processor
-    @; little-end锛宒isbale I/D Cache MMU, vector table is 0x00000000
-    MRC     P15, 0, R0, C1, C0, 0   @; Read CP15
-    LDR     R1, =0x00003085         @; set clear bits
-    BIC     R0, R0, R1
-    MCR     P15, 0, R0, C1, C0, 0   @; Write CP15
-
-    @; Call low level init function,
-    @; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
-    LDR     SP, =SVC_STACK_START
-    LDR     R0, =rt_low_level_init
-    BLX     R0
-
-Setup_Stack:
-    @; Setup Stack for each mode
-    MRS     R0, CPSR
-    BIC     R0, R0, #MODEMASK
-
-    ORR     R1, R0, #MODE_UND|NOINT
-    MSR     CPSR_cxsf, R1            @; Undef mode
-    LDR     SP, =UND_STACK_START
-
-    ORR     R1, R0, #MODE_ABT|NOINT
-    MSR     CPSR_cxsf, R1            @; Abort mode
-    LDR     SP, =ABT_STACK_START
-
-    ORR     R1, R0, #MODE_IRQ|NOINT
-    MSR     CPSR_cxsf, R1            @; IRQ mode
-    LDR     SP, =IRQ_STACK_START
-
-    ORR     R1, R0, #MODE_FIQ|NOINT
-    MSR     CPSR_cxsf, R1            @; FIQ mode
-    LDR     SP, =FIQ_STACK_START
-
-    ORR     R1, R0, #MODE_SYS|NOINT
-    MSR     CPSR_cxsf,R1             @; SYS/User mode
-    LDR     SP, =SYS_STACK_START
-
-    ORR     R1, R0, #MODE_SVC|NOINT
-    MSR     CPSR_cxsf, R1            @; SVC mode
-    LDR     SP, =SVC_STACK_START
-
-    @; clear .bss
-    MOV     R0, #0                   @; get a zero
-    LDR     R1, =__bss_start__       @; bss start
-    LDR     R2, =__bss_end__         @; bss end
+    /* clear bss */
+    mov     r0, #0
+    ldr     r1, =__bss_start
+    ldr     r2, =__bss_end
 
 bss_clear_loop:
-    CMP     R1, R2                   @; check if data to clear
-    STRLO   R0, [R1], #4             @; clear 4 bytes
-    BLO     bss_clear_loop           @; loop until done
-
-    @; call C++ constructors of global objects
-    LDR     R0, =__ctors_start__
-    LDR     R1, =__ctors_end__
+    cmp     r1, r2
+    strlo   r0, [r1], #4
+    blo     bss_clear_loop
+       
+    /* call c++ constructors of global objects */
+    /*
+    ldr     r0, =__ctors_start__
+    ldr     r1, =__ctors_end__
 
 ctor_loop:
-    CMP     R0, R1
-    BEQ     ctor_end
-    LDR     R2, [R0], #4
-    STMFD   SP!, {R0-R1}
-    MOV     LR, PC
-    BX      R2
-    LDMFD   SP!, {R0-R1}
-    B       ctor_loop
+    cmp     r0, r1
+    beq     ctor_end
+    ldr     r2, [r0], #4
+    stmfd   sp!, {r0-r1}
+    mov     lr, pc
+    bx      r2
+    ldmfd   sp!, {r0-r1}
+    b       ctor_loop
 ctor_end:
+    */
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word  rtthread_startup
+
+
+
+cpu_init_crit:
+    /* invalidate I/D caches */
+    mov r0, #0
+    mcr p15, 0, r0, c7, c7, 0
+    mcr p15, 0, r0, c8, c7, 0
+
+    /* disable MMU stuff and caches */
+    mrc p15, 0, r0, c1, c0, 0
+    bic r0, r0, #0x00002300
+    bic r0, r0, #0x00000087
+    orr r0, r0, #0x00000002
+    orr r0, r0, #0x00001000
+    mcr p15, 0, r0, c1, c0, 0
+
+    bx lr
+ 
+stack_setup:
+    /* Setup Stack for each mode */
+    mrs     r0, cpsr
+    bic     r0, r0, #MODEMASK
+
+    orr     r1, r0, #MODE_UND|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =und_stack_start
+
+    orr     r1, r0, #MODE_ABT|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =abt_stack_start
+
+    orr     r1, r0, #MODE_IRQ|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =irq_stack_start
+
+    orr     r1, r0, #MODE_FIQ|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =fiq_stack_start
+
+    orr     r1, r0, #MODE_SYS|NOINT
+    msr     cpsr_cxsf,r1
+    ldr     sp, =sys_stack_start
+
+    orr     r1, r0, #MODE_SVC|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =svc_stack_start
+
+    bx      lr
+ 
+/*
+ ***************************************
+ * exception handlers 
+ ***************************************
+ */
+    /* Interrupt */
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
 
-    @; Enter the C code
-    LDR     R0, =rtthread_startup
-    BLX     R0
-
-@;----------------- Exception Handler -----------------------------------------
-    .global rt_hw_trap_udef
-    .global rt_hw_trap_swi
-    .global rt_hw_trap_pabt
-    .global rt_hw_trap_dabt
-    .global rt_hw_trap_resv
-    .global rt_hw_trap_irq
-    .global rt_hw_trap_fiq
-
-    .global rt_interrupt_enter
-    .global rt_interrupt_leave
-    .global rt_thread_switch_interrupt_flag
-    .global rt_interrupt_from_thread
-    .global rt_interrupt_to_thread
-    
-    .align  5
-Undef_Handler:
-    SUB     SP, SP, #S_FRAME_SIZE
-    STMIA   SP, {R0 - R12}          @; Calling R0-R12
-    ADD     R8, SP, #S_PC
-    STMDB   R8, {SP, LR}            @; Calling SP, LR
-    STR     LR, [R8, #0]            @; Save calling PC
-    MRS     R6, SPSR
-    STR     R6, [R8, #4]            @; Save CPSR
-    STR     R0, [R8, #8]            @; Save SPSR
-    MOV     R0, SP
-    BL      rt_hw_trap_udef
-    
-    .align  5
-SWI_Handler:
-    BL      rt_hw_trap_swi
-    
-    .align  5
-PAbt_Handler:
-    BL      rt_hw_trap_pabt
-
-    .align  5
-DAbt_Handler:
-    SUB     SP, SP, #S_FRAME_SIZE
-    STMIA   SP, {R0 - R12}          @; Calling R0-R12
-    ADD     R8, SP, #S_PC
-    STMDB   R8, {SP, LR}            @; Calling SP, LR
-    STR     LR, [R8, #0]            @; Save calling PC
-    MRS     R6, SPSR
-    STR     R6, [R8, #4]            @; Save CPSR
-    STR     R0, [R8, #8]            @; Save SPSR
-    MOV     R0, SP
-    BL      rt_hw_trap_dabt
-
-    .align  5
-Resv_Handler:
-    BL      rt_hw_trap_resv
-
-    .align  5
-FIQ_Handler:
-    STMFD   SP!, {R0-R7,LR}
-    BL      rt_hw_trap_fiq
-    LDMFD   SP!, {R0-R7,LR}
-    SUBS    PC, LR, #4
-
-    .align  5
-IRQ_Handler:
-    STMFD   SP!, {R0-R12,LR}
-    BL      rt_interrupt_enter
-    BL      rt_hw_trap_irq
-    BL      rt_interrupt_leave
-
-    @; If rt_thread_switch_interrupt_flag set,
-    @; jump to rt_hw_context_switch_interrupt_do and don't return
-    LDR     R0, =rt_thread_switch_interrupt_flag
-    LDR     R1, [R0]
-    CMP     R1, #1
-    BEQ     rt_hw_context_switch_interrupt_do
-
-    LDMFD   SP!, {R0-R12,LR}
-    SUBS    PC, LR, #4
-
-@;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) -----------------
-rt_hw_context_switch_interrupt_do:
-    MOV     R1,  #0                 @; Clear flag
-    STR     R1,  [R0]               @; Save to flag variable
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
 
-    LDMFD   SP!, {R0-R12,LR}        @; Reload saved registers
-    STMFD   SP, {R0-R2}             @; Save R0-R2
-    SUB     R1,  SP, #4*3           @; Save old task's SP to R1
-    SUB     R2,  LR, #4             @; Save old task's PC to R2
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
 
-    MRS     R0,  SPSR               @; Get CPSR of interrupt thread
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
 
-    MSR     CPSR_c, #MODE_SVC|NOINT @; Switch to SVC mode and no interrupt
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         
+    str     r1,  [r0]
+
+    mov     r1, sp          
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}
+    mrs     r0,  spsr       
+    sub     r2,  lr, #4     
+
+    msr     cpsr_c, #I_BIT|F_BIT|MODE_SVC
+
+    stmfd   sp!, {r2}       
+    stmfd   sp!, {r4-r12,lr}
+    ldmfd   r1,  {r1-r4}    
+    stmfd   sp!, {r1-r4}    
+    stmfd   sp!, {r0}       
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       
+
+    ldmfd   sp!, {r4}       
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ 
+
+    /* Exception */
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4
+    stmia   sp, {r0 - r12} 
+    mov     r0, sp
+    mrs     r6, spsr       
+    str     lr, [r0, #15*4]
+    str     r6, [r0, #16*4]
+    str     sp, [r0, #13*4]
+    str     lr, [r0, #14*4]
+.endm
 
-    STMFD   SP!, {R2}               @; Push old task's PC
-    STMFD   SP!, {R3-R12,LR}        @; Push old task's LR,R12-R3
-    LDMFD   R1, {R1-R3}
-    STMFD   SP!, {R1-R3}            @; Push old task's R2-R0
-    STMFD   SP!, {R0}               @; Push old task's CPSR
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
 
-    LDR     R4,  =rt_interrupt_from_thread
-    LDR     R5,  [R4]               @; R5 = stack ptr in old tasks's TCB
-    STR     SP,  [R5]               @; Store SP in preempted tasks's TCB
+vector_undef:
+    push_svc_reg
+    bl      rt_hw_trap_udef
+    b       .
 
-    LDR     R6,  =rt_interrupt_to_thread
-    LDR     R6,  [R6]               @; R6 = stack ptr in new tasks's TCB
-    LDR     SP,  [R6]               @; Get new task's stack pointer
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
 
-    LDMFD   SP!, {R4}               @; Pop new task's SPSR
-    MSR     SPSR_cxsf, R4
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
 
-    LDMFD   SP!, {R0-R12,LR,PC}^    @; pop new task's R0-R12,LR & PC SPSR 2 CPSR
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .
diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c
index 054cc2741a..de04c3f8cb 100644
--- a/libcpu/arm/arm926/trap.c
+++ b/libcpu/arm/arm926/trap.c
@@ -41,14 +41,18 @@ struct rt_hw_register
     rt_uint32_t cpsr;
     rt_uint32_t ORIG_r0;
 };
-
+static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
+void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
+{
+    rt_exception_hook = exception_handle;
+}
 /**
  * this function will show registers of CPU
  *
  * @param regs the registers point
  */
 
-void rt_hw_show_register (struct rt_hw_register *regs)
+void rt_hw_show_register(struct rt_hw_register *regs)
 {
     rt_kprintf("Execption:\n");
     rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n",
@@ -74,6 +78,13 @@ void rt_hw_show_register (struct rt_hw_register *regs)
  */
 void rt_hw_trap_udef(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_hw_show_register(regs);
 
     rt_kprintf("undefined instruction\n");
@@ -96,6 +107,13 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_hw_show_register(regs);
 
     rt_kprintf("software interrupt\n");
@@ -112,6 +130,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_hw_show_register(regs);
 
     rt_kprintf("prefetch abort\n");
@@ -133,6 +158,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_hw_show_register(regs);
 
     rt_kprintf("data abort\n");
@@ -153,55 +185,26 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_resv(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_kprintf("not used\n");
     rt_hw_show_register(regs);
     rt_hw_cpu_shutdown();
 }
 
-extern struct rt_irq_desc irq_desc[];
-extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
-extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id);
-    
-void rt_hw_trap_irq()
-{
-    rt_isr_handler_t isr_func;
-    rt_uint32_t irq;
-    void *param;
-
-    /* get irq number */
-    irq = rt_hw_interrupt_get_active(INT_IRQ);
+extern void rt_interrupt_dispatch(void);
 
-    /* get interrupt service routine */
-    isr_func = irq_desc[irq].handler;
-    param = irq_desc[irq].param;
-
-    /* turn to interrupt service routine */
-    isr_func(irq, param);
-
-    rt_hw_interrupt_ack(INT_IRQ, irq);
-#ifdef RT_USING_INTERRUPT_INFO
-    irq_desc[irq].counter ++;
-#endif
+void rt_hw_trap_irq(void)
+{
+    rt_interrupt_dispatch();
 }
 
-void rt_hw_trap_fiq()
+void rt_hw_trap_fiq(void)
 {
-    rt_isr_handler_t isr_func;
-    rt_uint32_t irq;
-    void *param;
-
-    /* get irq number */
-    irq = rt_hw_interrupt_get_active(INT_FIQ);
-
-    /* get interrupt service routine */
-    isr_func = irq_desc[irq].handler;
-    param = irq_desc[irq].param;
-
-    /* turn to interrupt service routine */
-    isr_func(irq, param);
-
-    rt_hw_interrupt_ack(INT_FIQ, irq);
-#ifdef RT_USING_INTERRUPT_INFO
-    irq_desc[irq].counter ++;
-#endif
+    rt_interrupt_dispatch();
 }
-- 
cgit v1.3.1


From 29264edde8a0fedec9edae6518e8520a9913fd88 Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Thu, 14 Mar 2019 17:54:21 +0800
Subject: 修改arm926中machine.c的协议声明
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/arm/arm926/machine.c | 18 ++----------------
 1 file changed, 2 insertions(+), 16 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/arm926/machine.c b/libcpu/arm/arm926/machine.c
index 23953dea42..aa26d10ec6 100644
--- a/libcpu/arm/arm926/machine.c
+++ b/libcpu/arm/arm926/machine.c
@@ -1,21 +1,7 @@
 /*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
-- 
cgit v1.3.1


From 3dd72f956bfa1f68a4ee69ccc823fb93c607f312 Mon Sep 17 00:00:00 2001
From: ZYH <lymz@foxmail.com>
Date: Wed, 20 Mar 2019 12:01:44 +0800
Subject: [libcpu][k210]add description of exception

---
 libcpu/risc-v/k210/interrupt.c | 49 +++++++++++++++++++++++++++++++++++++-----
 1 file changed, 44 insertions(+), 5 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c
index 3d30e69ed2..f6424ab5ef 100644
--- a/libcpu/risc-v/k210/interrupt.c
+++ b/libcpu/risc-v/k210/interrupt.c
@@ -230,10 +230,6 @@ uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
         /* Restore primitive IRQ threshold */
         plic->targets.target[core_id].priority_threshold = int_threshold;
     }
-    else
-    {
-        rt_kprintf("unhandled trap!\n");
-    }
 
     return epc;
 }
@@ -270,8 +266,51 @@ uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
         rt_hw_interrupt_disable();
 
         tid = rt_thread_self();
+        rt_kprintf("\nException:\n");
+        switch (cause)
+        {
+            case CAUSE_MISALIGNED_FETCH:
+                rt_kprintf("Instruction address misaligned");
+                break;
+            case CAUSE_FAULT_FETCH:
+                rt_kprintf("Instruction access fault");
+                break;
+            case CAUSE_ILLEGAL_INSTRUCTION:
+                rt_kprintf("Illegal instruction");
+                break;
+            case CAUSE_BREAKPOINT:
+                rt_kprintf("Breakpoint");
+                break;
+            case CAUSE_MISALIGNED_LOAD:
+                rt_kprintf("Load address misaligned");
+                break;
+            case CAUSE_FAULT_LOAD:
+                rt_kprintf("Load access fault");
+                break;
+            case CAUSE_MISALIGNED_STORE:
+                rt_kprintf("Store address misaligned");
+                break;
+            case CAUSE_FAULT_STORE:
+                rt_kprintf("Store access fault");
+                break;
+            case CAUSE_USER_ECALL:
+                rt_kprintf("Environment call from U-mode");
+                break;
+            case CAUSE_SUPERVISOR_ECALL:
+                rt_kprintf("Environment call from S-mode");
+                break;
+            case CAUSE_HYPERVISOR_ECALL:
+                rt_kprintf("Environment call from H-mode");
+                break;
+            case CAUSE_MACHINE_ECALL:
+                rt_kprintf("Environment call from M-mode");
+                break;
+            default:
+                rt_kprintf("Uknown exception : %08lX", cause);
+                break;
+        }
         rt_kprintf("\n");
-        rt_kprintf("unhandled trap, epc => 0x%08x, INT[%d]\n", epc, rt_interrupt_get_nest());
+        rt_kprintf("exception pc => 0x%08x\n", epc);
         rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name);
 #ifdef RT_USING_FINSH
         list_thread();
-- 
cgit v1.3.1


From c41bf3120f5704f08a90f96ab068bfb4850ad692 Mon Sep 17 00:00:00 2001
From: ZYH <lymz@foxmail.com>
Date: Thu, 21 Mar 2019 15:07:58 +0800
Subject: [libcpu][k210]add stack info printf

---
 libcpu/risc-v/k210/interrupt.c     | 77 +++++++++++++++++++++++++++++++++++++-
 libcpu/risc-v/k210/interrupt_gcc.S |  2 +-
 2 files changed, 77 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c
index f6424ab5ef..45b437c099 100644
--- a/libcpu/risc-v/k210/interrupt.c
+++ b/libcpu/risc-v/k210/interrupt.c
@@ -233,8 +233,82 @@ uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
 
     return epc;
 }
+struct exception_stack_frame
+{
+    uint64_t x1;
+    uint64_t x2;
+    uint64_t x3;
+    uint64_t x4;
+    uint64_t x5;
+    uint64_t x6;
+    uint64_t x7;
+    uint64_t x8;
+    uint64_t x9;
+    uint64_t x10;
+    uint64_t x11;
+    uint64_t x12;
+    uint64_t x13;
+    uint64_t x14;
+    uint64_t x15;
+    uint64_t x16;
+    uint64_t x17;
+    uint64_t x18;
+    uint64_t x19;
+    uint64_t x20;
+    uint64_t x21;
+    uint64_t x22;
+    uint64_t x23;
+    uint64_t x24;
+    uint64_t x25;
+    uint64_t x26;
+    uint64_t x27;
+    uint64_t x28;
+    uint64_t x29;
+    uint64_t x30;
+    uint64_t x31;
+};
+
+void print_stack_frame(uintptr_t * sp)
+{
+    struct exception_stack_frame * esf = (struct exception_stack_frame *)sp;
+
+    rt_kprintf("\n=================================================================\n");
+    rt_kprintf("x1 (ra   : Return address                ) ==> 0x%08x%08x\n", esf->x1 >> 32  , esf->x1 & UINT32_MAX);
+    rt_kprintf("x2 (sp   : Stack pointer                 ) ==> 0x%08x%08x\n", esf->x2 >> 32  , esf->x2 & UINT32_MAX);
+    rt_kprintf("x3 (gp   : Global pointer                ) ==> 0x%08x%08x\n", esf->x3 >> 32  , esf->x3 & UINT32_MAX);
+    rt_kprintf("x4 (tp   : Thread pointer                ) ==> 0x%08x%08x\n", esf->x4 >> 32  , esf->x4 & UINT32_MAX);
+    rt_kprintf("x5 (t0   : Temporary                     ) ==> 0x%08x%08x\n", esf->x5 >> 32  , esf->x5 & UINT32_MAX);
+    rt_kprintf("x6 (t1   : Temporary                     ) ==> 0x%08x%08x\n", esf->x6 >> 32  , esf->x6 & UINT32_MAX);
+    rt_kprintf("x7 (t2   : Temporary                     ) ==> 0x%08x%08x\n", esf->x7 >> 32  , esf->x7 & UINT32_MAX);
+    rt_kprintf("x8 (s0/fp: Save register,frame pointer   ) ==> 0x%08x%08x\n", esf->x8 >> 32  , esf->x8 & UINT32_MAX);
+    rt_kprintf("x9 (s1   : Save register                 ) ==> 0x%08x%08x\n", esf->x9 >> 32  , esf->x9 & UINT32_MAX);
+    rt_kprintf("x10(a0   : Function argument,return value) ==> 0x%08x%08x\n", esf->x10 >> 32 , esf->x10 & UINT32_MAX);
+    rt_kprintf("x11(a1   : Function argument,return value) ==> 0x%08x%08x\n", esf->x11 >> 32 , esf->x11 & UINT32_MAX);
+    rt_kprintf("x12(a2   : Function argument             ) ==> 0x%08x%08x\n", esf->x12 >> 32 , esf->x12 & UINT32_MAX);
+    rt_kprintf("x13(a3   : Function argument             ) ==> 0x%08x%08x\n", esf->x13 >> 32 , esf->x13 & UINT32_MAX);
+    rt_kprintf("x14(a4   : Function argument             ) ==> 0x%08x%08x\n", esf->x14 >> 32 , esf->x14 & UINT32_MAX);
+    rt_kprintf("x15(a5   : Function argument             ) ==> 0x%08x%08x\n", esf->x15 >> 32 , esf->x15 & UINT32_MAX);
+    rt_kprintf("x16(a6   : Function argument             ) ==> 0x%08x%08x\n", esf->x16 >> 32 , esf->x16 & UINT32_MAX);
+    rt_kprintf("x17(a7   : Function argument             ) ==> 0x%08x%08x\n", esf->x17 >> 32 , esf->x17 & UINT32_MAX);
+    rt_kprintf("x18(s2   : Save register                 ) ==> 0x%08x%08x\n", esf->x18 >> 32 , esf->x18 & UINT32_MAX);
+    rt_kprintf("x19(s3   : Save register                 ) ==> 0x%08x%08x\n", esf->x19 >> 32 , esf->x19 & UINT32_MAX);
+    rt_kprintf("x20(s4   : Save register                 ) ==> 0x%08x%08x\n", esf->x20 >> 32 , esf->x20 & UINT32_MAX);
+    rt_kprintf("x21(s5   : Save register                 ) ==> 0x%08x%08x\n", esf->x21 >> 32 , esf->x21 & UINT32_MAX);
+    rt_kprintf("x22(s6   : Save register                 ) ==> 0x%08x%08x\n", esf->x22 >> 32 , esf->x22 & UINT32_MAX);
+    rt_kprintf("x23(s7   : Save register                 ) ==> 0x%08x%08x\n", esf->x23 >> 32 , esf->x23 & UINT32_MAX);
+    rt_kprintf("x24(s8   : Save register                 ) ==> 0x%08x%08x\n", esf->x24 >> 32 , esf->x24 & UINT32_MAX);
+    rt_kprintf("x25(s9   : Save register                 ) ==> 0x%08x%08x\n", esf->x25 >> 32 , esf->x25 & UINT32_MAX);
+    rt_kprintf("x26(s10  : Save register                 ) ==> 0x%08x%08x\n", esf->x26 >> 32 , esf->x26 & UINT32_MAX);
+    rt_kprintf("x27(s11  : Save register                 ) ==> 0x%08x%08x\n", esf->x27 >> 32 , esf->x27 & UINT32_MAX);
+    rt_kprintf("x28(t3   : Temporary                     ) ==> 0x%08x%08x\n", esf->x28 >> 32 , esf->x28 & UINT32_MAX);
+    rt_kprintf("x29(t4   : Temporary                     ) ==> 0x%08x%08x\n", esf->x29 >> 32 , esf->x29 & UINT32_MAX);
+    rt_kprintf("x30(t5   : Temporary                     ) ==> 0x%08x%08x\n", esf->x30 >> 32 , esf->x30 & UINT32_MAX);
+    rt_kprintf("x31(t6   : Temporary                     ) ==> 0x%08x%08x\n", esf->x31 >> 32 , esf->x31 & UINT32_MAX);
+    rt_kprintf("=================================================================\n");
+}
+
 
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc, uintptr_t * sp)
 {
     int cause = mcause & CAUSE_MACHINE_IRQ_REASON_MASK;
 
@@ -310,6 +384,7 @@ uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
                 break;
         }
         rt_kprintf("\n");
+        print_stack_frame(sp);
         rt_kprintf("exception pc => 0x%08x\n", epc);
         rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name);
 #ifdef RT_USING_FINSH
diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S
index 5d3e8368b1..aeda72ab31 100644
--- a/libcpu/risc-v/k210/interrupt_gcc.S
+++ b/libcpu/risc-v/k210/interrupt_gcc.S
@@ -69,7 +69,7 @@ trap_entry:
     call  rt_interrupt_enter
     csrr  a0, mcause
     csrr  a1, mepc
-    mv    a2, sp
+    mv    a2, s0
     call  handle_trap
     call  rt_interrupt_leave
 
-- 
cgit v1.3.1


From e6d153732776c2e1950f3adfbce2dde2761bff60 Mon Sep 17 00:00:00 2001
From: tangyuxin <462747508@qq.com>
Date: Mon, 25 Mar 2019 15:18:09 +0800
Subject: 移除 SConscript.1 临时文件
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/mips/xburst/SConscript.1 | 14 --------------
 1 file changed, 14 deletions(-)
 delete mode 100644 libcpu/mips/xburst/SConscript.1

(limited to 'libcpu')

diff --git a/libcpu/mips/xburst/SConscript.1 b/libcpu/mips/xburst/SConscript.1
deleted file mode 100644
index b0ae20ba02..0000000000
--- a/libcpu/mips/xburst/SConscript.1
+++ /dev/null
@@ -1,14 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ''
-
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')
-- 
cgit v1.3.1


From 2eb1bef773e099ac93ec74dba7ec216bdf61597c Mon Sep 17 00:00:00 2001
From: qz721 <295354721@qq.com>
Date: Mon, 25 Mar 2019 20:03:49 +0800
Subject: Make 'qemu-vexpress-a9' and 'imx6ul' use the same libcpu code.

---
 bsp/imx6ul/.config                           | 358 +++++++++++++++++++++
 bsp/imx6ul/drivers/board.c                   |  19 +-
 bsp/imx6ul/platform/SConscript               |   4 +-
 bsp/imx6ul/platform/cpu/gic.c                | 243 ---------------
 bsp/imx6ul/platform/cpu/mmu.c                | 285 -----------------
 bsp/imx6ul/platform/cpu/mmu.h                | 157 ----------
 bsp/imx6ul/platform/cpu/platform.h           |  96 ++++++
 bsp/imx6ul/platform/include/gic.h            | 183 -----------
 bsp/imx6ul/platform/include/interrupt.h      | 101 ------
 bsp/imx6ul/rtconfig.py                       |   2 +-
 bsp/qemu-vexpress-a9/.config                 |   1 +
 bsp/qemu-vexpress-a9/SConstruct              |   4 +-
 bsp/qemu-vexpress-a9/cpu/SConscript          |  17 -
 bsp/qemu-vexpress-a9/cpu/armv7.h             |  64 ----
 bsp/qemu-vexpress-a9/cpu/context_gcc.S       | 198 ------------
 bsp/qemu-vexpress-a9/cpu/cp15.h              |  12 -
 bsp/qemu-vexpress-a9/cpu/cp15_gcc.S          | 140 ---------
 bsp/qemu-vexpress-a9/cpu/cpuport.c           |  83 -----
 bsp/qemu-vexpress-a9/cpu/gic.c               | 299 ------------------
 bsp/qemu-vexpress-a9/cpu/gic.h               |  33 --
 bsp/qemu-vexpress-a9/cpu/interrupt.c         | 108 -------
 bsp/qemu-vexpress-a9/cpu/interrupt.h         |  25 --
 bsp/qemu-vexpress-a9/cpu/mmu.c               | 207 -------------
 bsp/qemu-vexpress-a9/cpu/pmu.c               |  12 -
 bsp/qemu-vexpress-a9/cpu/pmu.h               | 151 ---------
 bsp/qemu-vexpress-a9/cpu/stack.c             |  71 -----
 bsp/qemu-vexpress-a9/cpu/start_gcc.S         | 447 ---------------------------
 bsp/qemu-vexpress-a9/cpu/trap.c              | 190 ------------
 bsp/qemu-vexpress-a9/cpu/vector_gcc.S        |  65 ----
 bsp/qemu-vexpress-a9/drivers/board.c         |   9 +
 bsp/qemu-vexpress-a9/platform/SConscript     |  13 +
 bsp/qemu-vexpress-a9/platform/cpu/platform.h |  37 +++
 bsp/qemu-vexpress-a9/rtconfig.h              | 149 +++++++++
 bsp/qemu-vexpress-a9/rtconfig.py             |   5 +-
 components/lwp/SConscript                    |   2 +-
 components/lwp/arch/arm/cortex-a/lwp_gcc.S   |  70 +++++
 libcpu/arm/cortex-a/context_gcc.S            |  92 ++++++
 libcpu/arm/cortex-a/cp15.h                   |   4 +
 libcpu/arm/cortex-a/cp15_gcc.S               |  15 +-
 libcpu/arm/cortex-a/cpu.c                    |  68 +++-
 libcpu/arm/cortex-a/gic.c                    | 301 ++++++++++++++++++
 libcpu/arm/cortex-a/gic.h                    |  35 +++
 libcpu/arm/cortex-a/interrupt.c              | 119 +++----
 libcpu/arm/cortex-a/interrupt.h              |  32 ++
 libcpu/arm/cortex-a/mmu.c                    |  49 +--
 libcpu/arm/cortex-a/mmu.h                    |  48 +++
 libcpu/arm/cortex-a/stack.c                  |   6 +-
 libcpu/arm/cortex-a/start_gcc.S              | 112 ++++++-
 libcpu/arm/cortex-a/trap.c                   |  70 +++--
 49 files changed, 1541 insertions(+), 3270 deletions(-)
 create mode 100644 bsp/imx6ul/.config
 delete mode 100644 bsp/imx6ul/platform/cpu/gic.c
 delete mode 100644 bsp/imx6ul/platform/cpu/mmu.c
 delete mode 100644 bsp/imx6ul/platform/cpu/mmu.h
 create mode 100644 bsp/imx6ul/platform/cpu/platform.h
 delete mode 100644 bsp/imx6ul/platform/include/gic.h
 delete mode 100644 bsp/imx6ul/platform/include/interrupt.h
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/SConscript
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/armv7.h
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/context_gcc.S
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/cp15.h
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/cp15_gcc.S
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/cpuport.c
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/gic.c
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/gic.h
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/interrupt.c
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/interrupt.h
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/mmu.c
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/pmu.c
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/pmu.h
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/stack.c
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/start_gcc.S
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/trap.c
 delete mode 100644 bsp/qemu-vexpress-a9/cpu/vector_gcc.S
 create mode 100644 bsp/qemu-vexpress-a9/platform/SConscript
 create mode 100644 bsp/qemu-vexpress-a9/platform/cpu/platform.h
 create mode 100644 components/lwp/arch/arm/cortex-a/lwp_gcc.S
 create mode 100644 libcpu/arm/cortex-a/gic.c
 create mode 100644 libcpu/arm/cortex-a/gic.h
 create mode 100644 libcpu/arm/cortex-a/interrupt.h
 create mode 100644 libcpu/arm/cortex-a/mmu.h

(limited to 'libcpu')

diff --git a/bsp/imx6ul/.config b/bsp/imx6ul/.config
new file mode 100644
index 0000000000..a9299a366b
--- /dev/null
+++ b/bsp/imx6ul/.config
@@ -0,0 +1,358 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+CONFIG_BOARD_IMX6UL=y
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40001
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_A=y
+CONFIG_ARCH_ARM_CORTEX_A7=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+
+#
+# Using WiFi
+#
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_RT_USING_UART0 is not set
+CONFIG_RT_USING_UART1=y
diff --git a/bsp/imx6ul/drivers/board.c b/bsp/imx6ul/drivers/board.c
index e53e2405b6..015a3709c1 100644
--- a/bsp/imx6ul/drivers/board.c
+++ b/bsp/imx6ul/drivers/board.c
@@ -20,6 +20,15 @@
 #include <epit.h>
 #include <cortex_a.h>
 
+#include <mmu.h>
+
+struct mem_desc platform_mem_desc[] = {
+    {0x00000000, 0x80000000, 0x00000000, DEVICE_MEM},
+    {0x80000000, 0xFFF00000, 0x80000000, NORMAL_MEM}
+};
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
+
 static void rt_hw_timer_isr(int vector, void *param)
 {
     rt_tick_increase();
@@ -32,17 +41,17 @@ int rt_hw_timer_init(void)
 
     // Make sure the timer is off.
     HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0;
-    
+
     HW_ARMGLOBALTIMER_CONTROL.B.FCR0 =1;
-    
+
     HW_ARMGLOBALTIMER_CONTROL.B.FCR1 =0;
-    
+
     HW_ARMGLOBALTIMER_CONTROL.B.DBG_ENABLE =0;
-    
+
     // Clear counter.
     HW_ARMGLOBALTIMER_COUNTER_HI_WR(0);
     HW_ARMGLOBALTIMER_COUNTER_LO_WR(0);
-    
+
     // Now turn on the timer.
     HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1;
 
diff --git a/bsp/imx6ul/platform/SConscript b/bsp/imx6ul/platform/SConscript
index 34834e6391..9ba43b1483 100644
--- a/bsp/imx6ul/platform/SConscript
+++ b/bsp/imx6ul/platform/SConscript
@@ -8,14 +8,12 @@ drivers/imx_timer.c
 drivers/imx_i2c.c
 drivers/imx_uart.c
 cpu/armv7_cache.c
-cpu/gic.c
 cpu/ccm_pll2.c
-cpu/mmu.c
 cpu/cortex_a_gcc.S
 ''')
 
 CPPPATH = [ cwd + '/cpu',
-cwd + '/include', 
+cwd + '/include',
 cwd + '/include/mx6ul',
 cwd + '/include/mx6ul/registers'
 ]
diff --git a/bsp/imx6ul/platform/cpu/gic.c b/bsp/imx6ul/platform/cpu/gic.c
deleted file mode 100644
index 2f140e02c6..0000000000
--- a/bsp/imx6ul/platform/cpu/gic.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright (c) 2012, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <assert.h>
-#include "gic.h"
-#include "gic_registers.h"
-#include "cortex_a.h"
-
-////////////////////////////////////////////////////////////////////////////////
-// Prototypes
-////////////////////////////////////////////////////////////////////////////////
-
-static inline gicd_t * gic_get_gicd(void);
-static inline gicc_t * gic_get_gicc(void);
-static inline uint32_t irq_get_register_offset(uint32_t irqID);
-static inline uint32_t irq_get_bit_offset(uint32_t irqID);
-static inline uint32_t irq_get_bit_mask(uint32_t irqID);
-
-////////////////////////////////////////////////////////////////////////////////
-// Code
-////////////////////////////////////////////////////////////////////////////////
-
-static inline gicd_t * gic_get_gicd(void)
-{
-    uint32_t base = get_arm_private_peripheral_base() + kGICDBaseOffset;
-    return (gicd_t *)base;
-}
-
-static inline gicc_t * gic_get_gicc(void)
-{
-    uint32_t base = get_arm_private_peripheral_base() + kGICCBaseOffset;
-    return (gicc_t *)base;
-}
-
-static inline uint32_t irq_get_register_offset(uint32_t irqID)
-{
-    return irqID / 32;
-}
-
-static inline uint32_t irq_get_bit_offset(uint32_t irqID)
-{
-    return irqID & 0x1f;
-}
-
-static inline uint32_t irq_get_bit_mask(uint32_t irqID)
-{
-    return 1 << irq_get_bit_offset(irqID);    
-}
-
-void gic_enable(bool enableIt)
-{
-    gicd_t * gicd = gic_get_gicd();
-    
-    if (enableIt)
-    {
-        // Enable both secure and non-secure.
-        gicd->CTLR |= kBM_GICD_CTLR_EnableGrp0 | kBM_GICD_CTLR_EnableGrp1;
-    }
-    else
-    {
-        // Clear the enable bits.
-        gicd->CTLR &= ~(kBM_GICD_CTLR_EnableGrp0 | kBM_GICD_CTLR_EnableGrp1);
-    }
-}
-
-void gic_set_irq_security(uint32_t irqID, bool isSecure)
-{
-    gicd_t * gicd = gic_get_gicd();
-    
-    uint32_t reg = irq_get_register_offset(irqID);
-    uint32_t mask = irq_get_bit_mask(irqID);
-    
-    uint32_t value = gicd->IGROUPRn[reg];
-    if (!isSecure)
-    {
-        value &= ~mask;
-    }
-    else
-    {
-        value |= mask;
-    }
-    gicd->IGROUPRn[reg] = value;
-}
-
-void gic_enable_irq(uint32_t irqID, bool isEnabled)
-{
-    gicd_t * gicd = gic_get_gicd();
-    
-    uint32_t reg = irq_get_register_offset(irqID);
-    uint32_t mask = irq_get_bit_mask(irqID);
-    
-    // Select set-enable or clear-enable register based on enable flag.
-    if (isEnabled)
-    {
-        gicd->ISENABLERn[reg] = mask;
-    }
-    else
-    {
-        gicd->ICENABLERn[reg] = mask;
-    }
-}
-
-void gic_set_irq_priority(uint32_t ID, uint32_t priority)
-{
-    gicd_t * gicd = gic_get_gicd();
-    
-    // Update the priority register. The priority registers are byte accessible, and the register
-    // struct has the priority registers as a byte array, so we can just index directly by the
-    // interrupt ID.
-    gicd->IPRIORITYRn[ID] = priority & 0xff;
-}
-
-void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt)
-{
-    // Make sure the CPU number is valid.
-    assert(cpuNumber <= 7);
-    
-    gicd_t * gicd = gic_get_gicd();
-    uint8_t cpuMask = 1 << cpuNumber;
-    
-    // Like the priority registers, the target registers are byte accessible, and the register
-    // struct has the them as a byte array, so we can just index directly by the
-    // interrupt ID.
-    if (enableIt)
-    {
-        gicd->ITARGETSRn[irqID] |= (cpuMask & 0xff);
-    }
-    else
-    {
-        gicd->ITARGETSRn[irqID] &= ~(cpuMask & 0xff);
-    }
-}
-
-void gic_send_sgi(uint32_t irqID, uint32_t target_list, uint32_t filter_list)
-{
-    gicd_t * gicd = gic_get_gicd();
-    
-    gicd->SGIR = (filter_list << kBP_GICD_SGIR_TargetListFilter)
-                    | (target_list << kBP_GICD_SGIR_CPUTargetList)
-                    | (irqID & 0xf);
-}
-
-void gic_cpu_enable(bool enableIt)
-{
-    gicc_t * gicc = gic_get_gicc();
-    
-    if (enableIt)
-    {
-        gicc->CTLR |= kBM_GICC_CTLR_EnableS | kBM_GICC_CTLR_EnableNS;
-    }
-    else
-    {
-        gicc->CTLR &= ~(kBM_GICC_CTLR_EnableS | kBM_GICC_CTLR_EnableNS);
-    }
-}
-
-void gic_set_cpu_priority_mask(uint32_t priority)
-{
-    gicc_t * gicc = gic_get_gicc();
-    gicc->PMR = priority & 0xff;    
-}
-
-uint32_t gic_read_irq_ack(void)
-{
-    gicc_t * gicc = gic_get_gicc();
-    return gicc->IAR;
-}
-
-void gic_write_end_of_irq(uint32_t irqID)
-{
-    gicc_t * gicc = gic_get_gicc();
-    gicc->EOIR = irqID;
-}
-
-void gic_init(void)
-{
-    gicd_t * gicd = gic_get_gicd();
-
-    // First disable the distributor.
-    gic_enable(false);
-    
-    // Clear all pending interrupts.
-    int i;
-    for (i = 0; i < 32; ++i)
-    {
-        gicd->ICPENDRn[i] = 0xffffffff;
-    }
-    
-    // Set all interrupts to secure.
-    for (i = 0; i < 8; ++i)
-    {
-        gicd->IGROUPRn[i] = 0;
-    }
-
-    // Init the GIC CPU interface.
-    gic_init_cpu();
-    
-    // Now enable the distributor.
-    gic_enable(true);
-}
-
-void gic_init_cpu(void)
-{
-    // Init the GIC CPU interface.
-    gic_set_cpu_priority_mask(0xff);
-
-    // Disable preemption.
-    gicc_t * gicc = gic_get_gicc();
-    gicc->BPR = 7;
-
-    // Enable signaling the CPU.
-    gic_cpu_enable(true);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-// EOF
-////////////////////////////////////////////////////////////////////////////////
diff --git a/bsp/imx6ul/platform/cpu/mmu.c b/bsp/imx6ul/platform/cpu/mmu.c
deleted file mode 100644
index 0cf20c9942..0000000000
--- a/bsp/imx6ul/platform/cpu/mmu.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*!
- * @file  mmu.c
- * @brief System memory arangement.
- */
-#include "cortex_a.h"
-#include "mmu.h"
-#include "arm_cp_registers.h"
-
-////////////////////////////////////////////////////////////////////////////////
-// Definitions
-////////////////////////////////////////////////////////////////////////////////
-
-//! @brief Size in bytes of the first-level page table.
-#define MMU_L1_PAGE_TABLE_SIZE (16 * 1024)
-
-//! @brief First-level 1MB section descriptor entry.
-typedef union mmu_l1_section {
-    uint32_t u;
-    struct {
-        uint32_t id:2;  //!< ID
-        uint32_t b:1;   //!< Bufferable
-        uint32_t c:1;   //!< Cacheable
-        uint32_t xn:1;  //!< Execute-not
-        uint32_t domain:4;  //!< Domain
-        uint32_t _impl_defined:1;   //!< Implementation defined, should be zero.
-        uint32_t ap1_0:2;  //!< Access permissions AP[1:0]
-        uint32_t tex:3; //!< TEX remap
-        uint32_t ap2:1; //!< Access permissions AP[2] 
-        uint32_t s:1;   //!< Shareable
-        uint32_t ng:1;  //!< Not-global
-        uint32_t _zero:1;   //!< Should be zero.
-        uint32_t ns:1;  //!< Non-secure
-        uint32_t address:12;   //!< Physical base address
-    };
-} mmu_l1_section_t;
-
-enum {
-    kMMU_L1_Section_ID = 2,  //!< ID value for a 1MB section first-level entry.
-    kMMU_L1_Section_Address_Shift = 20  //!< Bit offset of the physical base address field.
-};
-
-////////////////////////////////////////////////////////////////////////////////
-// Externs
-////////////////////////////////////////////////////////////////////////////////
-
-extern char __l1_page_table_start;
-
-////////////////////////////////////////////////////////////////////////////////
-// Code
-////////////////////////////////////////////////////////////////////////////////
-
-void mmu_enable()
-{
-    // invalidate all tlb 
-    arm_unified_tlb_invalidate();
-
-    // read SCTLR 
-    uint32_t sctlr;
-    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
-    
-    // set MMU enable bit 
-    sctlr |= BM_SCTLR_M;
-
-    // write modified SCTLR
-    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
-}
-
-void mmu_disable()
-{
-    // read current SCTLR 
-    uint32_t sctlr;
-    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
-    
-    // clear MMU enable bit 
-    sctlr &=~ BM_SCTLR_M;
-
-    // write modified SCTLR
-    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
-}
-
-void mmu_init()
-{
-    // Get the L1 page table base address.
-    uint32_t * table = (uint32_t *)&__l1_page_table_start;
-    uint32_t share_attr = kShareable;
-
-    // write table address to TTBR0
-    _ARM_MCR(15, 0, table, 2, 0, 0);
-
-    // set Client mode for all Domains
-    uint32_t dacr = 0x55555555; 
-    _ARM_MCR(15, 0, dacr, 3, 0, 0); // MCR p15, 0, <Rd>, c3, c0, 0 ; Write DACR
-
-    // Clear the L1 table.
-    bzero(table, MMU_L1_PAGE_TABLE_SIZE);
-    
-    // Create default mappings.
-    mmu_map_l1_range(0x00000000, 0x00000000, 0x00900000, kStronglyOrdered, kShareable, kRWAccess); // ROM and peripherals
-    mmu_map_l1_range(0x00900000, 0x00900000, 0x00100000, kStronglyOrdered, kShareable, kRWAccess); // OCRAM
-    mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kStronglyOrdered, kShareable, kRWAccess); // More peripherals
-   
-    // Check whether SMP is enabled. If it is not, then we don't want to make SDRAM shareable.
-    uint32_t actlr = 0x0;
-    _ARM_MRC(15, 0, actlr, 1, 0, 1);
-    if (actlr & BM_ACTLR_SMP)
-    {
-        share_attr = kShareable;
-    }
-    else
-    {
-        share_attr = kNonshareable;
-    }
-
-#if defined(CHIP_MX6DQ) || defined(CHIP_MX6SDL)
-    mmu_map_l1_range(0x10000000, 0x10000000, 0x80000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 2GB DDR
-#elif defined(CHIP_MX6SL) || defined(CHIP_MX6UL)
-    mmu_map_l1_range(0x80000000, 0x80000000, 0x40000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 1GB DDR
-#else
-#error Unknown chip type!
-#endif
-}
-
-void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access)
-{
-    register mmu_l1_section_t entry;
-    entry.u = 0;
-    
-    // Set constant attributes.
-    entry.id = kMMU_L1_Section_ID;
-    entry.xn = 0; // Allow execution
-    entry.domain = 0; // Domain 0
-    entry.ng = 0; // Global
-    entry.ns = 0; // Secure
-    
-    // Set attributes based on the selected memory type.
-    switch (memoryType)
-    {
-        case kStronglyOrdered:
-            entry.c = 0;
-            entry.b = 0;
-            entry.tex = 0;
-            entry.s = 1; // Ignored
-            break;
-        case kDevice:
-            if (isShareable)
-            {
-                entry.c = 0;
-                entry.b = 1;
-                entry.tex = 0;
-                entry.s = 1; // Ignored
-            }
-            else
-            {
-                entry.c = 0;
-                entry.b = 0;
-                entry.tex = 2;
-                entry.s = 0; // Ignored
-            }
-            break;
-        case kOuterInner_WB_WA:
-            entry.c = 1;
-            entry.b = 1;
-            entry.tex = 1;
-            entry.s = isShareable;
-            break;
-        case kOuterInner_WT:
-            entry.c = 1;
-            entry.b = 0;
-            entry.tex = 0;
-            entry.s = isShareable;
-            break;
-        case kNoncacheable:
-            entry.c = 0;
-            entry.b = 0;
-            entry.tex = 1;
-            entry.s = isShareable;
-            break;
-    }
-    
-    // Set attributes from specified access mode.
-    switch (access)
-    {
-        case kNoAccess:
-            entry.ap2 = 0;
-            entry.ap1_0 = 0;
-            break;
-        case kROAccess:
-            entry.ap2 = 1;
-            entry.ap1_0 = 3;
-            break;
-        case kRWAccess:
-            entry.ap2 = 0;
-            entry.ap1_0 = 3;
-            break;
-    }
-    
-    // Get the L1 page table base address.
-    uint32_t * table = (uint32_t *)&__l1_page_table_start;
-    
-    // Convert addresses to 12-bit bases.
-    uint32_t vbase = va >> kMMU_L1_Section_Address_Shift;
-    uint32_t pbase = pa >> kMMU_L1_Section_Address_Shift;
-    uint32_t entries = length >> kMMU_L1_Section_Address_Shift;
-
-    // Fill in L1 page table entries.
-    for (; entries > 0; ++pbase, ++vbase, --entries)
-    {
-        entry.address = pbase;
-        table[vbase] = entry.u;
-    }
-    
-    // Invalidate TLB
-    arm_unified_tlb_invalidate();
-}
-
-bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress)
-{
-    uint32_t pa = 0;
-    
-    // VA to PA translation with privileged read permission check  
-    _ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 0);
-    
-    // Read PA register 
-    _ARM_MRC(15, 0, pa, 7, 4, 0);
-    
-    // First bit of returned value is Result of conversion (0 is successful translation) 
-    if (pa & 1)
-    {
-        // We can try write permission also 
-        // VA to PA translation with privileged write permission check  
-        _ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 1);
-        
-        // Read PA register 
-        _ARM_MRC(15, 0, pa, 7, 4, 0);
-        
-        // First bit of returned value is Result of conversion (0 is successful translation) 
-        if (pa & 1)
-        {
-            return false;
-        }
-    }
-    
-    if (physicalAddress)
-    {
-        // complete address returning base + offset
-        pa = (pa & 0xfffff000) | (virtualAddress & 0x00000fff);
-        *physicalAddress = pa;
-    }
-    
-    return true;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-// EOF
-////////////////////////////////////////////////////////////////////////////////
diff --git a/bsp/imx6ul/platform/cpu/mmu.h b/bsp/imx6ul/platform/cpu/mmu.h
deleted file mode 100644
index 961c17f541..0000000000
--- a/bsp/imx6ul/platform/cpu/mmu.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-//! @addtogroup diag_mmu
-//! @{
-
-/*!
- * @file  mmu.h
- * @brief System memory arrangement.
- */
-
-#ifndef _MMU_H_
-#define _MMU_H_
-
-#include "sdk.h"
-
-////////////////////////////////////////////////////////////////////////////////
-// Definitions
-////////////////////////////////////////////////////////////////////////////////
-
-//! @brief Memory region attributes.
-typedef enum _mmu_memory_type
-{
-    kStronglyOrdered,
-    kDevice,
-    kOuterInner_WB_WA,
-    kOuterInner_WT,
-    kNoncacheable,
-} mmu_memory_type_t;
-
-//! @brief Memory region shareability options.
-typedef enum _mmu_shareability
-{
-    kShareable = 1,
-    kNonshareable = 0
-} mmu_shareability_t;
-
-//! @brief Access permissions for a memory region.
-typedef enum _mmu_access
-{
-    kNoAccess,
-    kROAccess,
-    kRWAccess
-} mmu_access_t;
-
-////////////////////////////////////////////////////////////////////////////////
-// Prototypes
-////////////////////////////////////////////////////////////////////////////////
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Enable the MMU.
- *
- * The L1 page tables and MMU settings must have already been configured by
- * calling mmu_init() before the MMU is enabled.
- */
-void mmu_enable();
-
-/*!
- * @brief Disable the MMU.
- */
-void mmu_disable();
-
-/*!
- * @brief Set up the default first-level page table.
- *
- * Initializes the L1 page table with the following regions:
- *  - 0x00000000...0x00900000 : ROM and peripherals, strongly-ordered
- *  - 0x00900000...0x00a00000 : OCRAM, strongly-ordered
- *  - For MX6DQ or MX6SDL: 0x10000000...0x90000000 : DDR, normal, outer inner, write-back, write-allocate
- *  - For MX6SL: 0x80000000...0xc0000000 : DDR, normal, outer inner, write-back, write-allocate
- *
- * If the CPU is participating in SMP, then the DDR regions are made shareable. Otherwise they
- * are marked as non-shareable.
- *
- * The TTBR0 register is set to the base of the L1 table.
- *
- * All memory domains are configured to allow client access. However, note that only domain 0 is
- * used by mmu_map_l1_range().
- */
-void mmu_init();
-
-/*!
- * @brief Maps a range of memory in the first-level page table.
- *
- * Entries in the first-level page table are filled in for the range of virtual addresses
- * starting at @a va and continuing for @a length bytes. These virtual addreses are mapped
- * to the physical addresses starting at @a pa and continuing for @a length bytes. All table
- * entries for the range of mapped memory have the same attributes, which are selected with
- * the @a memoryType, @a isShareable, and @a access parameters.
- *
- * @param pa The base physical address of the range to which the virtual address will be mapped.
- * @param va The base virtual address of the range.
- * @param length The size of the range to be mapped, in bytes. This value must be divisible by 1MB.
- * @param memoryType The type of the memory region. This controls caching, buffering, ordering of
- *      memory accesses, and other attributes of the region.
- * @param isShareable The shareability of the physical memory. Ignored for strongly-ordered memory.
- * @param access Access permissions.
- */
-void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access);
-
-/*!
- * @brief Convert virtual address to physical.
- *
- * First attempts a priviledged read translation for the current security mode. If that fails,
- * a priviledged write translation, also for the current security mode, is attempted. If this
- * second attempt at translation fails, then false will be returned.
- *
- * @param virtualAddress Virtual address to convert to a physical address.
- * @param[out] physicalAddress This parameter is filled in with the physical address corresponding
- *      to the virtual address passed in @a virtualAddress.
- * @retval true The address returned through @a physicalAddress is valid.
- * @retval false The conversion failed for some reason.
- */
-bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress);
-
-#if defined(__cplusplus)
-}
-#endif
-
-//! @}
-
-#endif // _MMU_H_
-////////////////////////////////////////////////////////////////////////////////
-// EOF
-////////////////////////////////////////////////////////////////////////////////
-
diff --git a/bsp/imx6ul/platform/cpu/platform.h b/bsp/imx6ul/platform/cpu/platform.h
new file mode 100644
index 0000000000..f6a3995bc5
--- /dev/null
+++ b/bsp/imx6ul/platform/cpu/platform.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-22     quanzhao     first version
+ */
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+/* SOC-relative definitions */
+//#include "realview.h"
+#include "gic_registers.h"
+#include "irq_numbers.h"
+
+/* the maximum number of gic */
+# define ARM_GIC_MAX_NR 1
+
+/* the maximum number of interrupts */
+#define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT
+
+/* the maximum entries of the interrupt table */
+#define MAX_HANDLERS IMX_INTERRUPT_COUNT
+
+/* the basic constants needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    rt_uint32_t gic_base;
+    asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
+    return gic_base + kGICDBaseOffset;
+}
+
+rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
+{
+    rt_uint32_t gic_base;
+    asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
+    return gic_base + kGICCBaseOffset;
+}
+
+#define GIC_IRQ_START   0
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+/* the definition needed by gic.c */
+#define __REG32(x)  (*((volatile unsigned int *)(x)))
+
+/* keep compatible with platform SDK */
+typedef enum {
+    CPU_0,
+    CPU_1,
+    CPU_2,
+    CPU_3,
+} cpuid_e;
+
+enum _gicd_sgi_filter
+{
+    //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
+    kGicSgiFilter_UseTargetList = 0,
+
+    //! Forward the interrupt to all CPU interfaces except that of the processor that requested
+    //! the interrupt.
+    kGicSgiFilter_AllOtherCPUs = 1,
+
+    //! Forward the interrupt only to the CPU interface of the processor that requested the
+    //! interrupt.
+    kGicSgiFilter_OnlyThisCPU = 2
+};
+
+typedef void (*irq_hdlr_t) (void);
+
+extern void rt_hw_interrupt_mask(int vector);
+extern void rt_hw_interrupt_umask(int vector);
+extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+    void *param, const char *name);
+
+rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
+{
+    rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
+}
+
+rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
+{
+    rt_hw_interrupt_umask(irq_id);
+}
+
+rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
+{
+    rt_hw_interrupt_mask(irq_id);
+}
+
+#endif  /* __PLATFORM_H__ */
diff --git a/bsp/imx6ul/platform/include/gic.h b/bsp/imx6ul/platform/include/gic.h
deleted file mode 100644
index f3eee8499c..0000000000
--- a/bsp/imx6ul/platform/include/gic.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __GIC_H__
-#define __GIC_H__
-
-#include "sdk_types.h"
-
-//! @addtogroup gic
-//! @{
-
-////////////////////////////////////////////////////////////////////////////////
-// Definitions
-////////////////////////////////////////////////////////////////////////////////
-
-//! @brief Options for sending a software generated interrupt.
-//!
-//! These options are used for the @a filter_list parameter of the gic_send_sgi()
-//! function. They control how to select which CPUs that the interrupt is
-//! sent to.
-enum _gicd_sgi_filter
-{
-    //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
-    kGicSgiFilter_UseTargetList = 0,
-    
-    //! Forward the interrupt to all CPU interfaces except that of the processor that requested
-    //! the interrupt.
-    kGicSgiFilter_AllOtherCPUs = 1,
-    
-    //! Forward the interrupt only to the CPU interface of the processor that requested the
-    //! interrupt.
-    kGicSgiFilter_OnlyThisCPU = 2
-};
-
-////////////////////////////////////////////////////////////////////////////////
-// API
-////////////////////////////////////////////////////////////////////////////////
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-//! @name Initialization
-//@{
-//! @brief Init interrupt handling.
-//!
-//! This function is intended to be called only by the primary CPU init code, so it will
-//! only be called once during system bootup.
-//!
-//! Also inits the current CPU. You don't need to call gic_init_cpu() separately.
-//!
-//! @post The interrupt distributor and the current CPU interface are enabled. All interrupts
-//!     that were pending are cleared, and all interrupts are made secure (group 0).
-void gic_init(void);
-
-//! @brief Init the current CPU's GIC interface.
-//!
-//! @post Enables the CPU interface and sets the priority mask to 255. Interrupt preemption
-//!     is disabled by setting the Binary Point to a value of 7.
-void gic_init_cpu(void);
-//@}
-
-//! @name GIC Interrupt Distributor Functions
-//@{
-//! @brief Enable or disable the GIC Distributor.
-//!
-//! Enables or disables the GIC distributor passing both secure (group 0) and non-secure
-//! (group 1) interrupts to the CPU interfaces.
-//!
-//! @param enableIt Pass true to enable or false to disable.
-void gic_enable(bool enableIt);
-
-//! @brief Set the security mode for an interrupt.
-//!
-//! @param irqID The interrupt number.
-//! @param isSecure Whether the interrupt is taken to secure mode.
-void gic_set_irq_security(uint32_t irqID, bool isSecure);
-
-//! @brief Enable or disable an interrupt.
-//!
-//! @param irqID The number of the interrupt to control.
-//! @param isEnabled Pass true to enable or false to disable.
-void gic_enable_irq(uint32_t irqID, bool isEnabled);
-
-//! @brief Set whether a CPU will receive a particular interrupt.
-//!
-//! @param irqID The interrupt number.
-//! @param cpuNumber The CPU number. The first CPU core is 0.
-//! @param enableIt Whether to send the interrupt to the specified CPU. Pass true to enable
-//!     or false to disable.
-void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt);
-
-//! @brief Set an interrupt's priority.
-//!
-//! @param irq_id The interrupt number.
-//! @param priority The priority for the interrupt. In the range of 0 through 0xff, with
-//!     0 being the highest priority.
-void gic_set_irq_priority(uint32_t irq_id, uint32_t priority);
-
-//! @brief Send a software generated interrupt to a specific CPU.
-//!
-//! @param irq_id The interrupt number to send.
-//! @param target_list Each bit indicates a CPU to which the interrupt will be forwarded.
-//!     Bit 0 is CPU 0, bit 1 is CPU 1, and so on. If the value is 0, then the interrupt
-//!     will not be forwarded to any CPUs. This parameter is only used if @a filter_list
-//!     is set to #kGicSgiFilter_UseTargetList.
-//! @param filter_list One of the enums of the #_gicd_sgi_filter enumeration. The selected
-//!     option determines which CPUs the interrupt will be sent to. If the value
-//!     is #kGicSgiFilter_UseTargetList, then the @a target_list parameter is used.
-void gic_send_sgi(uint32_t irq_id, uint32_t target_list, uint32_t filter_list);
-//@}
-
-//! @name GIC CPU Interface Functions
-//@{
-//! @brief Enable or disable the interface to the GIC for the current CPU.
-//!
-//! @param enableIt Pass true to enable or false to disable.
-void gic_cpu_enable(bool enableIt);
-
-//! @brief Set the mask of which interrupt priorities the CPU will receive.
-//!
-//! @param priority The lowest priority that will be passed to the current CPU. Pass 0xff to
-//!     allow all priority interrupts to signal the CPU.
-void gic_set_cpu_priority_mask(uint32_t priority);
-
-//! @brief Acknowledge starting of interrupt handling and get the interrupt number.
-//!
-//! Normally, this function is called at the beginning of the IRQ handler. It tells the GIC
-//! that you are starting to handle an interupt, and returns the number of the interrupt you
-//! need to handle. After the interrupt is handled, you should call gic_write_end_of_irq()
-//! to signal that the interrupt is completely handled.
-//!
-//! In some cases, a spurious interrupt might happen. One possibility is if another CPU handles
-//! the interrupt. When a spurious interrupt occurs, the end of the interrupt should be indicated
-//! but nothing else.
-//!
-//! @return The number for the highest priority interrupt available for the calling CPU. If
-//!     the return value is 1022 or 1023, a spurious interrupt has occurred.
-uint32_t gic_read_irq_ack(void);
-
-//! @brief Signal the end of handling an interrupt.
-//!
-//! @param irq_id The number of the interrupt for which handling has finished.
-void gic_write_end_of_irq(uint32_t irq_id);
-//@}
-
-
-#if defined(__cplusplus)
-}
-#endif
-
-//! @}
-
-#endif // __GIC_H__
-////////////////////////////////////////////////////////////////////////////////
-// EOF
-////////////////////////////////////////////////////////////////////////////////
diff --git a/bsp/imx6ul/platform/include/interrupt.h b/bsp/imx6ul/platform/include/interrupt.h
deleted file mode 100644
index 318e34f3bd..0000000000
--- a/bsp/imx6ul/platform/include/interrupt.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (c) 2009-2012, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-#include "sdk_types.h"
-#include "irq_numbers.h"
-
-//! @addtogroup diag_interrupt
-//! @{
-
-/*!
- * @file interrupt.h
- * @brief Interface for the interrupt manager.
- */
-
-////////////////////////////////////////////////////////////////////////////////
-// Definitions
-////////////////////////////////////////////////////////////////////////////////
-
-//! @brief
-typedef enum {
-    CPU_0,
-    CPU_1,
-    CPU_2,
-    CPU_3,
-} cpuid_e;
-
-//! @brief Interrupt service routine.
-typedef void (*irq_hdlr_t) (void);
-
-////////////////////////////////////////////////////////////////////////////////
-// API
-////////////////////////////////////////////////////////////////////////////////
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-//! @brief Enable an interrupt.
-//!
-//! Sets the interrupt priority and makes it non-secure. Then the interrupt is
-//! enabled on the CPU specified by @a cpu_id.
-//!
-//! @param irq_id The interrupt number to enable.
-//! @param cpu_id The index of the CPU for which the interrupt will be enabled.
-//! @param priority The interrupt priority, from 0-255. Lower numbers have higher priority.
-void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority);
-
-//! @brief Disable an interrupt on the specified CPU.
-//!
-//! @param irq_id The interrupt number to disabled.
-//! @param cpu_id The index of the CPU for which the interrupt will be disabled.
-void disable_interrupt(uint32_t irq_id, uint32_t cpu_id);
-
-//! @brief Set the interrupt service routine for the specified interrupt.
-//!
-//! @param irq_id The interrupt number.
-//! @param isr Function that will be called to handle the interrupt.
-void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr);
-
-//! @brief Interrupt handler that simply prints a message.
-void default_interrupt_routine(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-//! @}
-
-#endif
-////////////////////////////////////////////////////////////////////////////////
-// EOF
-////////////////////////////////////////////////////////////////////////////////
diff --git a/bsp/imx6ul/rtconfig.py b/bsp/imx6ul/rtconfig.py
index 2c08665920..0a9ea3dce3 100644
--- a/bsp/imx6ul/rtconfig.py
+++ b/bsp/imx6ul/rtconfig.py
@@ -10,7 +10,7 @@ if os.getenv('RTT_CC'):
 
 # only support GNU GCC compiler.
 PLATFORM  = 'gcc'
-EXEC_PATH = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+EXEC_PATH = '/usr/bin'
 
 if os.getenv('RTT_EXEC_PATH'):
     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
diff --git a/bsp/qemu-vexpress-a9/.config b/bsp/qemu-vexpress-a9/.config
index c8814d366a..6fde000858 100644
--- a/bsp/qemu-vexpress-a9/.config
+++ b/bsp/qemu-vexpress-a9/.config
@@ -322,6 +322,7 @@ CONFIG_RT_USING_LWP=y
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
 # CONFIG_PKG_USING_LJSON is not set
 # CONFIG_PKG_USING_EZXML is not set
 # CONFIG_PKG_USING_NANOPB is not set
diff --git a/bsp/qemu-vexpress-a9/SConstruct b/bsp/qemu-vexpress-a9/SConstruct
index 638311d697..d618790dec 100644
--- a/bsp/qemu-vexpress-a9/SConstruct
+++ b/bsp/qemu-vexpress-a9/SConstruct
@@ -5,7 +5,7 @@ import rtconfig
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..')
 
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
@@ -25,7 +25,7 @@ Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
+objs = PrepareBuilding(env, RTT_ROOT)
 
 # make a building
 DoBuilding(TARGET, objs)
diff --git a/bsp/qemu-vexpress-a9/cpu/SConscript b/bsp/qemu-vexpress-a9/cpu/SConscript
deleted file mode 100644
index b45f95cc1a..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/SConscript
+++ /dev/null
@@ -1,17 +0,0 @@
-Import('rtconfig')
-from building import *
-
-cwd     = GetCurrentDir()
-src	= Glob('*.c')
-CPPPATH = [cwd]
-
-if rtconfig.PLATFORM == 'iar':
-        src += Glob('*_iar.S')
-elif rtconfig.PLATFORM == 'gcc':
-        src += Glob('*_gcc.S')
-elif rtconfig.PLATFORM == 'armcc':
-        src += Glob('*_rvds.S')
-
-group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/qemu-vexpress-a9/cpu/armv7.h b/bsp/qemu-vexpress-a9/cpu/armv7.h
deleted file mode 100644
index 69c556eb3c..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/armv7.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef __ARMV7_H__
-#define __ARMV7_H__
-
-/* the exception stack without VFP registers */
-struct rt_hw_exp_stack
-{
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
-};
-
-struct rt_hw_stack
-{
-	unsigned long cpsr;
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long lr;
-	unsigned long pc;
-};
-
-#define USERMODE    0x10
-#define FIQMODE     0x11
-#define IRQMODE     0x12
-#define SVCMODE     0x13
-#define MONITORMODE 0x16
-#define ABORTMODE   0x17
-#define HYPMODE     0x1b
-#define UNDEFMODE   0x1b
-#define MODEMASK    0x1f
-#define NOINT       0xc0
-
-#define T_Bit       (1<<5)
-#define F_Bit       (1<<6)
-#define I_Bit       (1<<7)
-#define A_Bit       (1<<8)
-#define E_Bit       (1<<9)
-#define J_Bit       (1<<24)
-
-#endif
diff --git a/bsp/qemu-vexpress-a9/cpu/context_gcc.S b/bsp/qemu-vexpress-a9/cpu/context_gcc.S
deleted file mode 100644
index 0aad0200d5..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/context_gcc.S
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * File      : context.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- * 2018-11-22     Jesven       in the smp version, using macro to
- *                             define rt_hw_interrupt_enable and rt_hw_interrupt_disable
- *                             rt_hw_context_switch_interrupt switches to the new thread directly
- */
-
-#include "rtconfig.h"
-.section .text, "ax"
-
-#ifdef RT_USING_SMP
-#define rt_hw_interrupt_disable rt_hw_local_irq_disable
-#define rt_hw_interrupt_enable  rt_hw_local_irq_enable
-#endif
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mrs r0, cpsr
-    cpsid i
-    bx  lr
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    msr cpsr, r0
-    bx  lr
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
- */
-.globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    ldr sp, [r0]            @ get new task stack pointer
-
-#ifdef RT_USING_SMP
-    mov     r0, r1
-    bl      rt_cpus_lock_status_restore
-#endif /*RT_USING_SMP*/
-
-#ifdef RT_USING_LWP
-    ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr
-    add sp, #8
-#endif
-
-    ldmfd sp!, {r4}         @ pop new task spsr
-    msr spsr_cxsf, r4
-
-    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
-
-.section .bss.share.isr
-_guest_switch_lvl:
-    .word 0
-
-.section .text.isr, "ax"
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r0 --> from
- * r1 --> to
- */
-.globl rt_hw_context_switch
-rt_hw_context_switch:
-    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
-    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
-
-    mrs r4, cpsr
-    tst lr, #0x01
-    orrne r4, r4, #0x20     @ it's thumb code
-
-    stmfd sp!, {r4}         @ push cpsr
-
-#ifdef RT_USING_LWP
-    stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
-    sub sp, #8
-#endif
-
-    str sp, [r0]            @ store sp in preempted tasks TCB
-    ldr sp, [r1]            @ get new task stack pointer
-
-#ifdef RT_USING_SMP
-    mov     r0, r2
-    bl      rt_cpus_lock_status_restore
-#endif /*RT_USING_SMP*/
-
-#ifdef RT_USING_LWP
-    ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr
-    add sp, #8
-#endif
-
-    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
-    msr spsr_cxsf, r4
-    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
-
-/*
- * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
- */
-.equ Mode_USR,        0x10
-.equ Mode_FIQ,        0x11
-.equ Mode_IRQ,        0x12
-.equ Mode_SVC,        0x13
-.equ Mode_ABT,        0x17
-.equ Mode_UND,        0x1B
-.equ Mode_SYS,        0x1F
-
-.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
-.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
-
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-#ifdef RT_USING_SMP
-    /* r0 :irq_mod context
-     * r1 :addr of from_thread's sp
-     * r2 :addr of to_thread's sp
-     * r3 :to_thread's tcb
-     */
-
-    @ r0 point to {r0-r3} in stack
-    push    {r1 - r3}
-    mov     r1, r0
-    add     r0, r0, #4*4
-    ldmfd   r0!, {r4-r12,lr}@ reload saved registers
-    mrs     r3,  spsr       @ get cpsr of interrupt thread
-    sub     r2,  lr, #4     @ save old task's pc to r2
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
-    stmfd   sp!, {r2}       @ push old task's pc
-    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
-    ldmfd   r1,  {r4-r7}    @ restore r0-r3 of the interrupt thread
-    stmfd   sp!, {r4-r7}    @ push old task's r0-r3
-    stmfd   sp!, {r3}       @ push old task's cpsr
-
-#ifdef RT_USING_LWP
-    stmfd sp, {r13,r14}^    @push usr_sp usr_lr
-    sub sp, #8
-#endif
-
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ
-    pop     {r1 - r3}
-    mov     sp, r0
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
-    str     sp, [r1]
-
-    ldr     sp, [r2]
-    mov     r0, r3
-    bl      rt_cpus_lock_status_restore
-
-#ifdef RT_USING_LWP
-    ldmfd sp, {r13,r14}^  @pop usr_sp usr_lr
-    add sp, #8
-#endif
-
-    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
-    msr     spsr_cxsf, r4
-
-    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
-
-#else /*RT_USING_SMP*/
-    ldr r2, =rt_thread_switch_interrupt_flag
-    ldr r3, [r2]
-    cmp r3, #1
-    beq _reswitch
-    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
-    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
-    str r0, [ip]
-    str r3, [r2]
-_reswitch:
-    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
-    str r1, [r2]
-    bx  lr
-#endif /*RT_USING_SMP*/
diff --git a/bsp/qemu-vexpress-a9/cpu/cp15.h b/bsp/qemu-vexpress-a9/cpu/cp15.h
deleted file mode 100644
index ebea3f0fe3..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/cp15.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __CP15_H__
-#define __CP15_H__
-
-unsigned long rt_cpu_get_smp_id(void);
-
-void rt_cpu_mmu_disable(void);
-void rt_cpu_mmu_enable(void);
-void rt_cpu_tlb_set(volatile unsigned long*);
-
-void rt_cpu_vector_set_base(unsigned int addr);
-
-#endif
diff --git a/bsp/qemu-vexpress-a9/cpu/cp15_gcc.S b/bsp/qemu-vexpress-a9/cpu/cp15_gcc.S
deleted file mode 100644
index f1ed6492aa..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/cp15_gcc.S
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * File      : cp15_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- * http://www.rt-thread.org
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.globl rt_cpu_get_smp_id
-rt_cpu_get_smp_id:
-    mrc     p15, #0, r0, c0, c0, #5
-    bx      lr
-
-.globl rt_cpu_vector_set_base
-rt_cpu_vector_set_base:
-    mcr     p15, #0, r0, c12, c0, #0
-    dsb
-    bx      lr
-
-.globl rt_hw_cpu_dcache_enable
-rt_hw_cpu_dcache_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0,  r0, #0x00000004
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-.globl rt_hw_cpu_icache_enable
-rt_hw_cpu_icache_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0,  r0, #0x00001000
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-_FLD_MAX_WAY:
-   .word  0x3ff
-_FLD_MAX_IDX:
-   .word  0x7ff
-
-.globl rt_cpu_dcache_clean_flush
-rt_cpu_dcache_clean_flush:
-    push    {r4-r11}
-    dmb
-    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
-    ands    r3, r0, #0x7000000       @ get level of coherency
-    mov     r3, r3, lsr #23
-    beq     finished
-    mov     r10, #0
-loop1:
-    add     r2, r10, r10, lsr #1
-    mov     r1, r0, lsr r2
-    and     r1, r1, #7
-    cmp     r1, #2
-    blt     skip
-    mcr     p15, #2, r10, c0, c0, #0
-    isb
-    mrc     p15, #1, r1, c0, c0, #0
-    and     r2, r1, #7
-    add     r2, r2, #4
-    ldr     r4, _FLD_MAX_WAY
-    ands    r4, r4, r1, lsr #3
-    clz     r5, r4
-    ldr     r7, _FLD_MAX_IDX
-    ands    r7, r7, r1, lsr #13
-loop2:
-    mov     r9, r4
-loop3:
-    orr     r11, r10, r9, lsl r5
-    orr     r11, r11, r7, lsl r2
-    mcr     p15, #0, r11, c7, c14, #2
-    subs    r9, r9, #1
-    bge     loop3
-    subs    r7, r7, #1
-    bge     loop2
-skip:
-    add     r10, r10, #2
-    cmp     r3, r10
-    bgt     loop1
-
-finished:
-    dsb
-    isb
-    pop     {r4-r11}
-    bx      lr
-
-.globl rt_hw_cpu_dcache_disable
-rt_hw_cpu_dcache_disable:
-    push    {r4-r11, lr}
-    bl      rt_cpu_dcache_clean_flush
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0,  r0, #0x00000004
-    mcr     p15, #0, r0, c1, c0, #0
-    pop     {r4-r11, lr}
-    bx      lr
-
-.globl rt_hw_cpu_icache_disable
-rt_hw_cpu_icache_disable:
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0,  r0, #0x00001000
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-.globl rt_cpu_mmu_disable
-rt_cpu_mmu_disable:
-    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0, r0, #1
-    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
-    dsb
-    bx      lr
-
-.globl rt_cpu_mmu_enable
-rt_cpu_mmu_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0, r0, #0x001
-    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
-    dsb
-    bx      lr
-
-.globl rt_cpu_tlb_set
-rt_cpu_tlb_set:
-    mcr     p15, #0, r0, c2, c0, #0
-    dmb
-    bx      lr
diff --git a/bsp/qemu-vexpress-a9/cpu/cpuport.c b/bsp/qemu-vexpress-a9/cpu/cpuport.c
deleted file mode 100644
index 6b129f89ee..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/cpuport.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- * 2018-11-22     Jesven       add rt_hw_cpu_id()
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <board.h>
-
-#ifdef RT_USING_SMP
-int rt_hw_cpu_id(void)
-{
-    int cpu_id;
-    __asm__ volatile (
-            "mrc p15, 0, %0, c0, c0, 5"
-            :"=r"(cpu_id)
-            );
-    cpu_id &= 0xf;
-    return cpu_id;
-};
-
-void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
-{
-    unsigned long tmp;
-    unsigned long newval;
-    rt_hw_spinlock_t lockval;
-
-    __asm__ __volatile__(
-            "pld [%0]"
-            ::"r"(&lock->slock)
-            );
-
-    __asm__ __volatile__(
-            "1: ldrex   %0, [%3]\n"
-            "   add %1, %0, %4\n"
-            "   strex   %2, %1, [%3]\n"
-            "   teq %2, #0\n"
-            "   bne 1b"
-            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
-            : "r" (&lock->slock), "I" (1 << 16)
-            : "cc");
-
-    while (lockval.tickets.next != lockval.tickets.owner) {
-        __asm__ __volatile__("wfe":::"memory");
-        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
-    }
-
-    __asm__ volatile ("dmb":::"memory");
-}
-
-void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
-{
-    __asm__ volatile ("dmb":::"memory");
-    lock->tickets.owner++;
-    __asm__ volatile ("dsb ishst\nsev":::"memory");
-}
-#endif /*RT_USING_SMP*/
-
-/**
- * @addtogroup ARM CPU
- */
-/*@{*/
-
-/** shutdown CPU */
-void rt_hw_cpu_shutdown()
-{
-    rt_uint32_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}
-
-/*@}*/
diff --git a/bsp/qemu-vexpress-a9/cpu/gic.c b/bsp/qemu-vexpress-a9/cpu/gic.c
deleted file mode 100644
index 66876518ce..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/gic.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * File      : gic.c, ARM Generic Interrupt Controller
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-20     Bernard      first version
- * 2014-04-03     Grissiom     many enhancements
- * 2018-11-22     Jesven       add rt_hw_ipi_send()
- *                             add rt_hw_ipi_handler_install()
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <board.h>
-
-#include "gic.h"
-#include "cp15.h"
-
-struct arm_gic
-{
-    rt_uint32_t offset;
-
-    rt_uint32_t dist_hw_base;
-    rt_uint32_t cpu_hw_base;
-};
-static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
-
-#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
-#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
-#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
-#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
-#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
-#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
-#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
-
-#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
-#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
-#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
-#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
-#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
-#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
-#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
-#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
-#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
-#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
-#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
-#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
-#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
-#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
-#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
-
-static unsigned int _gic_max_irq;
-
-int arm_gic_get_active_irq(rt_uint32_t index)
-{
-    int irq;
-
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
-    irq += _gic_table[index].offset;
-    return irq;
-}
-
-void arm_gic_ack(rt_uint32_t index, int irq)
-{
-    rt_uint32_t mask = 1 << (irq % 32);
-
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    irq = irq - _gic_table[index].offset;
-    RT_ASSERT(irq >= 0);
-
-    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
-    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
-    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_mask(rt_uint32_t index, int irq)
-{
-    rt_uint32_t mask = 1 << (irq % 32);
-
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    irq = irq - _gic_table[index].offset;
-    RT_ASSERT(irq >= 0);
-
-    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_clear_pending(rt_uint32_t index, int irq)
-{
-    rt_uint32_t mask = 1 << (irq % 32);
-
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    irq = irq - _gic_table[index].offset;
-    RT_ASSERT(irq >= 0);
-
-    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_clear_active(rt_uint32_t index, int irq)
-{
-    rt_uint32_t mask = 1 << (irq % 32);
-
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    irq = irq - _gic_table[index].offset;
-    RT_ASSERT(irq >= 0);
-
-    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
-{
-    rt_uint32_t old_tgt;
-
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    irq = irq - _gic_table[index].offset;
-    RT_ASSERT(irq >= 0);
-
-    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
-
-    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
-    old_tgt |=   cpumask << ((irq % 4)*8);
-
-    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
-}
-
-void arm_gic_umask(rt_uint32_t index, int irq)
-{
-    rt_uint32_t mask = 1 << (irq % 32);
-
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    irq = irq - _gic_table[index].offset;
-    RT_ASSERT(irq >= 0);
-
-    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_dump_type(rt_uint32_t index)
-{
-    unsigned int gic_type;
-
-    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
-    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
-               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
-               _gic_table[index].dist_hw_base,
-               _gic_max_irq,
-               gic_type & (1 << 10) ? "has" : "no",
-               gic_type);
-}
-
-void arm_gic_dump(rt_uint32_t index)
-{
-    unsigned int i, k;
-
-    k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
-    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
-    rt_kprintf("--- hw mask ---\n");
-    for (i = 0; i < _gic_max_irq / 32; i++)
-    {
-        rt_kprintf("0x%08x, ",
-                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
-                                       i * 32));
-    }
-    rt_kprintf("\n--- hw pending ---\n");
-    for (i = 0; i < _gic_max_irq / 32; i++)
-    {
-        rt_kprintf("0x%08x, ",
-                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
-                                        i * 32));
-    }
-    rt_kprintf("\n--- hw active ---\n");
-    for (i = 0; i < _gic_max_irq / 32; i++)
-    {
-        rt_kprintf("0x%08x, ",
-                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
-                                       i * 32));
-    }
-    rt_kprintf("\n");
-}
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
-#endif
-
-int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
-{
-    unsigned int gic_type, i;
-    rt_uint32_t cpumask = 1 << 0;
-
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    _gic_table[index].dist_hw_base = dist_base;
-    _gic_table[index].offset = irq_start;
-
-    /* Find out how many interrupts are supported. */
-    gic_type = GIC_DIST_TYPE(dist_base);
-    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
-
-    /*
-     * The GIC only supports up to 1020 interrupt sources.
-     * Limit this to either the architected maximum, or the
-     * platform maximum.
-     */
-    if (_gic_max_irq > 1020)
-        _gic_max_irq = 1020;
-    if (_gic_max_irq > ARM_GIC_NR_IRQS)
-        _gic_max_irq = ARM_GIC_NR_IRQS;
-
-    cpumask |= cpumask << 8;
-    cpumask |= cpumask << 16;
-
-    GIC_DIST_CTRL(dist_base) = 0x0;
-
-    /* Set all global interrupts to be level triggered, active low. */
-    for (i = 32; i < _gic_max_irq; i += 16)
-        GIC_DIST_CONFIG(dist_base, i) = 0x0;
-
-    /* Set all global interrupts to this CPU only. */
-    for (i = 32; i < _gic_max_irq; i += 4)
-        GIC_DIST_TARGET(dist_base, i) = cpumask;
-
-    /* Set priority on all interrupts. */
-    for (i = 0; i < _gic_max_irq; i += 4)
-        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
-
-    /* Disable all interrupts. */
-    for (i = 0; i < _gic_max_irq; i += 32)
-        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
-
-#if 0
-    /* All interrupts defaults to IGROUP1(IRQ). */
-    for (i = 0; i < _gic_max_irq; i += 32)
-        GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
-#endif
-
-    /* Enable group0 and group1 interrupt forwarding. */
-    GIC_DIST_CTRL(dist_base) = 0x03;
-
-    return 0;
-}
-
-int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
-{
-    RT_ASSERT(index < ARM_GIC_MAX_NR);
-
-    _gic_table[index].cpu_hw_base = cpu_base;
-
-    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
-    /* Enable CPU interrupt */
-    GIC_CPU_CTRL(cpu_base) = 0x01;
-
-    return 0;
-}
-
-void arm_gic_set_group(rt_uint32_t index, int vector, int group)
-{
-    /* As for GICv2, there are only group0 and group1. */
-    RT_ASSERT(group <= 1);
-    RT_ASSERT(vector < _gic_max_irq);
-
-    if (group == 0)
-    {
-        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
-                        vector) &= ~(1 << (vector % 32));
-    }
-    else if (group == 1)
-    {
-        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
-                        vector) |=  (1 << (vector % 32));
-    }
-}
-
-#ifdef RT_USING_SMP
-void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
- {
-     /* note: ipi_vector maybe different with irq_vector */
-     GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector;
-}
-#endif
-
-#ifdef RT_USING_SMP
-void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
-{
-    /* note: ipi_vector maybe different with irq_vector */
-    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
-}
-#endif
diff --git a/bsp/qemu-vexpress-a9/cpu/gic.h b/bsp/qemu-vexpress-a9/cpu/gic.h
deleted file mode 100644
index 9d0368ec94..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/gic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * File      : gic.h, ARM Generic Interrupt Controller
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-20     Bernard      first version
- */
-
-#ifndef __GIC_H__
-#define __GIC_H__
-
-int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
-int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
-
-void arm_gic_mask(rt_uint32_t index, int irq);
-void arm_gic_umask(rt_uint32_t index, int irq);
-void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
-void arm_gic_set_group(rt_uint32_t index, int vector, int group);
-
-int arm_gic_get_active_irq(rt_uint32_t index);
-void arm_gic_ack(rt_uint32_t index, int irq);
-
-void arm_gic_dump_type(rt_uint32_t index);
-void rt_hw_vector_init(void);
-
-#endif
-
diff --git a/bsp/qemu-vexpress-a9/cpu/interrupt.c b/bsp/qemu-vexpress-a9/cpu/interrupt.c
deleted file mode 100644
index d7e9ec08fa..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/interrupt.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-06     Bernard      first version
- * 2018-11-22     Jesven       add smp support
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include "realview.h"
-#include "gic.h"
-
-#define MAX_HANDLERS                NR_IRQS_PBA8
-
-/* exception and interrupt handler table */
-struct rt_irq_desc isr_table[MAX_HANDLERS];
-
-#ifndef RT_USING_SMP
-/* Those varibles will be accessed in ISR, so we need to share them. */
-rt_uint32_t rt_interrupt_from_thread        = 0;
-rt_uint32_t rt_interrupt_to_thread          = 0;
-rt_uint32_t rt_thread_switch_interrupt_flag = 0;
-#endif
-
-const unsigned int VECTOR_BASE = 0x00;
-extern void rt_cpu_vector_set_base(unsigned int addr);
-extern int system_vectors;
-
-void rt_hw_vector_init(void)
-{
-    rt_cpu_vector_set_base((unsigned int)&system_vectors);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    rt_uint32_t gic_cpu_base;
-    rt_uint32_t gic_dist_base;
-
-    /* initialize vector table */
-    rt_hw_vector_init();
-
-    /* initialize exceptions table */
-    rt_memset(isr_table, 0x00, sizeof(isr_table));
-
-    /* initialize ARM GIC */
-    gic_dist_base = REALVIEW_GIC_DIST_BASE;
-    gic_cpu_base = REALVIEW_GIC_CPU_BASE;
-
-    arm_gic_dist_init(0, gic_dist_base, 0);
-    arm_gic_cpu_init(0, gic_cpu_base);
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-    arm_gic_mask(0, vector);
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    arm_gic_umask(0, vector);
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector < MAX_HANDLERS)
-    {
-        old_handler = isr_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-            isr_table[vector].handler = handler;
-            isr_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
diff --git a/bsp/qemu-vexpress-a9/cpu/interrupt.h b/bsp/qemu-vexpress-a9/cpu/interrupt.h
deleted file mode 100644
index 045246b21d..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/interrupt.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-06     Bernard      first version
- */
-
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-#define INT_IRQ     0x00
-#define INT_FIQ     0x01
-
-void rt_hw_interrupt_control(int vector, int priority, int route);
-
-void rt_hw_interrupt_init(void);
-
-#endif
diff --git a/bsp/qemu-vexpress-a9/cpu/mmu.c b/bsp/qemu-vexpress-a9/cpu/mmu.c
deleted file mode 100644
index b2503e4260..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/mmu.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * File      : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2012-01-10     bernard      porting to AM1808
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <board.h>
-
-#include "cp15.h"
-
-#define DESC_SEC       (0x2)
-#define CB             (3<<2)  //cache_on, write_back
-#define CNB            (2<<2)  //cache_on, write_through
-#define NCB            (1<<2)  //cache_off,WR_BUF on
-#define NCNB           (0<<2)  //cache_off,WR_BUF off
-#define AP_RW          (3<<10) //supervisor=RW, user=RW
-#define AP_RO          (2<<10) //supervisor=RW, user=RO
-#define XN             (1<<4)  // eXecute Never
-
-#define DOMAIN_FAULT   (0x0)
-#define DOMAIN_CHK     (0x1)
-#define DOMAIN_NOTCHK  (0x3)
-#define DOMAIN0        (0x0<<5)
-#define DOMAIN1        (0x1<<5)
-
-#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
-
-/* Read/Write, cache, write back */
-#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
-/* Read/Write, cache, write through */
-#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
-/* Read/Write without cache and write buffer */
-#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
-/* Read/Write without cache and write buffer, no execute */
-#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
-/* Read/Write without cache and write buffer */
-#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
-
-/* dump 2nd level page table */
-void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    for (i = 0; i < 256; i++)
-    {
-        rt_uint32_t pte2 = ptb[i];
-        if ((pte2 & 0x3) == 0)
-        {
-            if (fcnt == 0)
-                rt_kprintf("    ");
-            rt_kprintf("%04x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("    %04x: %x: ", i, pte2);
-        if ((pte2 & 0x3) == 0x1)
-        {
-            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
-                       (pte2 >> 15) & 0x1,
-                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
-                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
-        }
-    }
-}
-
-void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    rt_kprintf("page table@%p\n", ptb);
-    for (i = 0; i < 1024*4; i++)
-    {
-        rt_uint32_t pte1 = ptb[i];
-        if ((pte1 & 0x3) == 0)
-        {
-            rt_kprintf("%03x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("%03x: %08x: ", i, pte1);
-        if ((pte1 & 0x3) == 0x3)
-        {
-            rt_kprintf("LPAE\n");
-        }
-        else if ((pte1 & 0x3) == 0x1)
-        {
-            rt_kprintf("pte,ns:%d,domain:%d\n",
-                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
-            /*
-             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
-             *                               - 0x80000000 + 0xC0000000));
-             */
-        }
-        else if (pte1 & (1 << 18))
-        {
-            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("section,ns:%d,ap:%x,"
-                       "xn:%d,texcb:%02x,domain:%d\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       (((pte1 & (0x7 << 12)) >> 10) |
-                        ((pte1 &        0x0c) >>  2)) & 0x1f,
-                       (pte1 >> 5) & 0xf);
-        }
-    }
-}
-
-/* level1 page table, each entry for 1MB memory. */
-volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
-void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
-                      rt_uint32_t vaddrEnd,
-                      rt_uint32_t paddrStart,
-                      rt_uint32_t attr)
-{
-    volatile rt_uint32_t *pTT;
-    volatile int i, nSec;
-    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
-    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
-    for(i = 0; i <= nSec; i++)
-    {
-        *pTT = attr | (((paddrStart >> 20) + i) << 20);
-        pTT++;
-    }
-}
-
-unsigned long rt_hw_set_domain_register(unsigned long domain_val)
-{
-    unsigned long old_domain;
-
-    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
-    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
-
-    return old_domain;
-}
-
-void rt_hw_mmu_init(void)
-{
-    rt_hw_cpu_dcache_disable();
-    rt_hw_cpu_icache_disable();
-    rt_cpu_mmu_disable();
-
-    /* set page table */
-    /* 4G 1:1 memory */
-    rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
-    /* IO memory region */
-    rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
-
-    /*rt_hw_cpu_dump_page_table(MMUTable);*/
-    rt_hw_set_domain_register(0x55555555);
-
-    rt_cpu_tlb_set(MMUTable);
-
-    rt_cpu_mmu_enable();
-
-    rt_hw_cpu_icache_enable();
-    rt_hw_cpu_dcache_enable();
-}
-
diff --git a/bsp/qemu-vexpress-a9/cpu/pmu.c b/bsp/qemu-vexpress-a9/cpu/pmu.c
deleted file mode 100644
index 07911a2db7..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/pmu.c
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <rtthread.h>
-#include "pmu.h"
-
-void rt_hw_pmu_dump_feature(void)
-{
-    unsigned long reg;
-
-    reg = rt_hw_pmu_get_control();
-    rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n",
-               reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f);
-    RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f));
-}
diff --git a/bsp/qemu-vexpress-a9/cpu/pmu.h b/bsp/qemu-vexpress-a9/cpu/pmu.h
deleted file mode 100644
index 05c1420dd8..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/pmu.h
+++ /dev/null
@@ -1,151 +0,0 @@
-#ifndef __PMU_H__
-#define __PMU_H__
-
-#include "board.h"
-
-/* Number of counters */
-#define ARM_PMU_CNTER_NR 4
-
-enum rt_hw_pmu_event_type {
-    ARM_PMU_EVENT_PMNC_SW_INCR      = 0x00,
-    ARM_PMU_EVENT_L1_ICACHE_REFILL  = 0x01,
-    ARM_PMU_EVENT_ITLB_REFILL       = 0x02,
-    ARM_PMU_EVENT_L1_DCACHE_REFILL  = 0x03,
-    ARM_PMU_EVENT_L1_DCACHE_ACCESS  = 0x04,
-    ARM_PMU_EVENT_DTLB_REFILL       = 0x05,
-    ARM_PMU_EVENT_MEM_READ          = 0x06,
-    ARM_PMU_EVENT_MEM_WRITE         = 0x07,
-    ARM_PMU_EVENT_INSTR_EXECUTED    = 0x08,
-    ARM_PMU_EVENT_EXC_TAKEN         = 0x09,
-    ARM_PMU_EVENT_EXC_EXECUTED      = 0x0A,
-    ARM_PMU_EVENT_CID_WRITE         = 0x0B,
-};
-
-/* Enable bit */
-#define ARM_PMU_PMCR_E   (0x01 << 0)
-/* Event counter reset */
-#define ARM_PMU_PMCR_P   (0x01 << 1)
-/* Cycle counter reset */
-#define ARM_PMU_PMCR_C   (0x01 << 2)
-/* Cycle counter divider */
-#define ARM_PMU_PMCR_D   (0x01 << 3)
-
-#ifdef __GNUC__
-rt_inline void rt_hw_pmu_enable_cnt(int divide64)
-{
-    unsigned long pmcr;
-    unsigned long pmcntenset;
-
-    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
-    pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C;
-    if (divide64)
-        pmcr |= ARM_PMU_PMCR_D;
-    else
-        pmcr &= ~ARM_PMU_PMCR_D;
-    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
-
-    /* enable all the counters */
-    pmcntenset = ~0;
-    asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset));
-    /* clear overflows(just in case) */
-    asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset));
-}
-
-rt_inline unsigned long rt_hw_pmu_get_control(void)
-{
-    unsigned long pmcr;
-    asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
-    return pmcr;
-}
-
-rt_inline unsigned long rt_hw_pmu_get_ceid(void)
-{
-    unsigned long reg;
-    /* only PMCEID0 is supported, PMCEID1 is RAZ. */
-    asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg));
-    return reg;
-}
-
-rt_inline unsigned long rt_hw_pmu_get_cnten(void)
-{
-    unsigned long pmcnt;
-    asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt));
-    return pmcnt;
-}
-
-rt_inline void rt_hw_pmu_reset_cycle(void)
-{
-    unsigned long pmcr;
-
-    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
-    pmcr |= ARM_PMU_PMCR_C;
-    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
-    asm volatile ("isb");
-}
-
-rt_inline void rt_hw_pmu_reset_event(void)
-{
-    unsigned long pmcr;
-
-    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
-    pmcr |= ARM_PMU_PMCR_P;
-    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
-    asm volatile ("isb");
-}
-
-rt_inline unsigned long rt_hw_pmu_get_cycle(void)
-{
-    unsigned long cyc;
-    asm volatile ("isb");
-    asm volatile ("mrc  p15, 0, %0, c9, c13, 0" : "=r"(cyc));
-    return cyc;
-}
-
-rt_inline void rt_hw_pmu_select_counter(int idx)
-{
-    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
-
-    asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx));
-    /* Linux add an isb here, don't know why here. */
-    asm volatile ("isb");
-}
-
-rt_inline void rt_hw_pmu_select_event(int idx,
-                                      enum rt_hw_pmu_event_type eve)
-{
-    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
-
-    rt_hw_pmu_select_counter(idx);
-    asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve));
-}
-
-rt_inline unsigned long rt_hw_pmu_read_counter(int idx)
-{
-    unsigned long reg;
-
-    rt_hw_pmu_select_counter(idx);
-    asm volatile ("isb");
-    asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg));
-    return reg;
-}
-
-rt_inline unsigned long rt_hw_pmu_get_ovsr(void)
-{
-    unsigned long reg;
-    asm volatile ("isb");
-    asm ("mrc  p15, 0, %0, c9, c12, 3" : "=r"(reg));
-    return reg;
-}
-
-rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg)
-{
-    asm ("mcr  p15, 0, %0, c9, c12, 3" : : "r"(reg));
-    asm volatile ("isb");
-}
-
-#endif
-
-void rt_hw_pmu_dump_feature(void);
-
-#endif /* end of include guard: __PMU_H__ */
-
diff --git a/bsp/qemu-vexpress-a9/cpu/stack.c b/bsp/qemu-vexpress-a9/cpu/stack.c
deleted file mode 100644
index dfb97557bc..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/stack.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-23     Bernard      the first version
- * 2011-10-05     Bernard      add thumb mode
- */
-#include <rtthread.h>
-#include <board.h>
-
-/**
- * @addtogroup AM33xx
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry 
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-        rt_uint8_t *stack_addr, void *texit)
-{
-    rt_uint32_t *stk;
-
-    stack_addr += sizeof(rt_uint32_t);
-    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
-    stk 	 = (rt_uint32_t*)stack_addr;
-    *(--stk) = (rt_uint32_t)tentry;			/* entry point */
-    *(--stk) = (rt_uint32_t)texit;			/* lr */
-    *(--stk) = 0;							/* r12 */
-    *(--stk) = 0;							/* r11 */
-    *(--stk) = 0;							/* r10 */
-    *(--stk) = 0;							/* r9 */
-    *(--stk) = 0;							/* r8 */
-    *(--stk) = 0;							/* r7 */
-    *(--stk) = 0;							/* r6 */
-    *(--stk) = 0;							/* r5 */
-    *(--stk) = 0;							/* r4 */
-    *(--stk) = 0;							/* r3 */
-    *(--stk) = 0;							/* r2 */
-    *(--stk) = 0;							/* r1 */
-    *(--stk) = (rt_uint32_t)parameter;		/* r0 : argument */
-    /* cpsr */
-    if ((rt_uint32_t)tentry & 0x01)
-        *(--stk) = SVCMODE | 0x20;			/* thumb mode */
-    else
-        *(--stk) = SVCMODE;					/* arm mode   */
-
-#ifdef RT_USING_LWP
-    *(--stk) = 0;		/* user lr */
-    *(--stk) = 0;		/* user sp*/
-#endif
-
-    /* return task's current stack address */
-    return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/bsp/qemu-vexpress-a9/cpu/start_gcc.S b/bsp/qemu-vexpress-a9/cpu/start_gcc.S
deleted file mode 100644
index b71d8a1568..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/start_gcc.S
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- * 2018-11-22     Jesven       in the interrupt context, use rt_scheduler_do_irq_switch checks
- *                             and switches to a new thread
- */
-
-#include "rtconfig.h"
-
-.equ Mode_USR,        0x10
-.equ Mode_FIQ,        0x11
-.equ Mode_IRQ,        0x12
-.equ Mode_SVC,        0x13
-.equ Mode_ABT,        0x17
-.equ Mode_UND,        0x1B
-.equ Mode_SYS,        0x1F
-
-.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
-.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
-
-.equ UND_Stack_Size,     0x00000000
-.equ SVC_Stack_Size,     0x00000400
-.equ ABT_Stack_Size,     0x00000000
-.equ RT_FIQ_STACK_PGSZ,  0x00000000
-.equ RT_IRQ_STACK_PGSZ,  0x00000800
-.equ USR_Stack_Size,     0x00000400
-
-#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
-                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
-
-.section .data.share.isr
-/* stack */
-.globl stack_start
-.globl stack_top
-
-stack_start:
-.rept ISR_Stack_Size
-.byte 0
-.endr
-stack_top:
-
-.text
-/* reset entry */
-.globl _reset
-_reset:
-    /* set the cpu to SVC32 mode and disable interrupt */
-    mrs     r0, cpsr
-    bic     r0, r0, #0x1f
-    orr     r0, r0, #0x13
-    msr     cpsr_c, r0
-
-    mrc p15, 0, r1, c1, c0, 1
-    mov r0, #(1<<6)
-    orr r1, r0
-    mcr p15, 0, r1, c1, c0, 1 //enable smp
-
-    ldr lr, =after_enable_mmu
-    ldr r0, =mtbl
-    b enable_mmu
-
-after_enable_mmu:
-
-    /* setup stack */
-    bl      stack_setup
-
-    /* clear .bss */
-    mov     r0,#0                   /* get a zero                       */
-    ldr     r1,=__bss_start         /* bss start                        */
-    ldr     r2,=__bss_end           /* bss end                          */
-
-bss_loop:
-    cmp     r1,r2                   /* check if data to clear           */
-    strlo   r0,[r1],#4              /* clear 4 bytes                    */
-    blo     bss_loop                /* loop until done                  */
-
-    /* call C++ constructors of global objects                          */
-    ldr     r0, =__ctors_start__
-    ldr     r1, =__ctors_end__
-
-ctor_loop:
-    cmp     r0, r1
-    beq     ctor_end
-    ldr     r2, [r0], #4
-    stmfd   sp!, {r0-r1}
-    mov     lr, pc
-    bx      r2
-    ldmfd   sp!, {r0-r1}
-    b       ctor_loop
-ctor_end:
-
-    /* start RT-Thread Kernel */
-    bl      flush_cache_all
-    ldr     pc, _rtthread_startup
-_rtthread_startup:
-    .word rtthread_startup
-
-stack_setup:
-    ldr     r0, =stack_top
-
-    @  Set the startup stack for svc
-    mov     sp, r0
-
-    @  Enter Undefined Instruction Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #UND_Stack_Size
-
-    @  Enter Abort Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #ABT_Stack_Size
-
-    @  Enter FIQ Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #RT_FIQ_STACK_PGSZ
-
-    @  Enter IRQ Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #RT_IRQ_STACK_PGSZ
-
-    /* come back to SVC mode */
-    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
-    bx      lr
-
-    .global enable_mmu
-enable_mmu:
-    orr r0, #0x18
-    mcr p15, 0, r0, c2, c0, 0 @ttbr0
-
-    mov r0, #(1 << 5)         @PD1=1
-    mcr p15, 0, r0, c2, c0, 2 @ttbcr
-
-    mov r0, #1
-    mcr p15, 0, r0, c3, c0, 0 @dacr
-
-    mov r0, #0
-    mcr p15, 0, r0, c8, c7, 0
-    mcr p15, 0, r0, c7, c5, 0 @iciallu
-    mcr p15, 0, r0, c7, c5, 6 @bpiall
-
-    mrc p15, 0, r0, c1, c0, 0
-    orr r0, #(1 | 4)
-    orr r0, #(1 << 12)
-    mcr p15, 0, r0, c1, c0, 0
-    dsb
-    isb
-    mov pc, lr
-
-.global flush_cache_all
-flush_cache_all:
-    stmfd   sp!, {r0-r12, lr}
-    bl  v7_flush_dcache_all
-    mov r0, #0
-    mcr p15, 0, r0, c7, c5, 0       @ I+BTB cache invalidate
-    dsb
-    isb
-    ldmfd   sp!, {r0-r12, lr}
-    mov pc, lr
-
-    v7_flush_dcache_all:
-    dmb                 @ ensure ordering with previous memory accesses
-    mrc p15, 1, r0, c0, c0, 1       @ read clidr
-    ands    r3, r0, #0x7000000      @ extract loc from clidr
-    mov r3, r3, lsr #23         @ left align loc bit field
-    beq finished            @ if loc is 0, then no need to clean
-    mov r10, #0             @ start clean at cache level 0
-loop1:
-    add r2, r10, r10, lsr #1        @ work out 3x current cache level
-    mov r1, r0, lsr r2          @ extract cache type bits from clidr
-    and r1, r1, #7          @ mask of the bits for current cache only
-    cmp r1, #2              @ see what cache we have at this level
-    blt skip                @ skip if no cache, or just i-cache
-    mcr p15, 2, r10, c0, c0, 0      @ select current cache level in cssr
-    isb                 @ isb to sych the new cssr&csidr
-    mrc p15, 1, r1, c0, c0, 0       @ read the new csidr
-    and r2, r1, #7          @ extract the length of the cache lines
-    add r2, r2, #4          @ add 4 (line length offset)
-    ldr r4, =0x3ff
-    ands    r4, r4, r1, lsr #3      @ find maximum number on the way size
-    clz r5, r4              @ find bit position of way size increment
-    ldr r7, =0x7fff
-    ands    r7, r7, r1, lsr #13     @ extract max number of the index size
-loop2:
-    mov r9, r4              @ create working copy of max way size
-loop3:
-    orr r11, r10, r9, lsl r5        @ factor way and cache number into r11
-    orr r11, r11, r7, lsl r2        @ factor index number into r11
-    mcr p15, 0, r11, c7, c14, 2     @ clean & invalidate by set/way
-    subs    r9, r9, #1          @ decrement the way
-    bge loop3
-    subs    r7, r7, #1          @ decrement the index
-    bge loop2
-skip:
-    add r10, r10, #2            @ increment cache number
-    cmp r3, r10
-    bgt loop1
-finished:
-    mov r10, #0             @ swith back to cache level 0
-    mcr p15, 2, r10, c0, c0, 0      @ select current cache level in cssr
-    dsb
-    isb
-    mov pc, lr
-
-/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
-.section .text.isr, "ax"
-    .align  5
-.globl vector_fiq
-vector_fiq:
-    stmfd   sp!,{r0-r7,lr}
-    bl      rt_hw_trap_fiq
-    ldmfd   sp!,{r0-r7,lr}
-    subs    pc, lr, #4
-
-.globl      rt_interrupt_enter
-.globl      rt_interrupt_leave
-.globl      rt_thread_switch_interrupt_flag
-.globl      rt_interrupt_from_thread
-.globl      rt_interrupt_to_thread
-
-    .align  5
-.globl vector_irq
-vector_irq:
-#ifdef RT_USING_SMP
-    clrex
-#endif
-    stmfd   sp!, {r0-r12,lr}
-
-    bl      rt_interrupt_enter
-    bl      rt_hw_trap_irq
-    bl      rt_interrupt_leave
-
-#ifdef RT_USING_SMP
-    mov     r0, sp
-    bl      rt_scheduler_do_irq_switch
-
-    ldmfd   sp!, {r0-r12,lr}
-    subs    pc,  lr, #4
-#else
-    @ if rt_thread_switch_interrupt_flag set, jump to
-    @ rt_hw_context_switch_interrupt_do and don't return
-    ldr     r0, =rt_thread_switch_interrupt_flag
-    ldr     r1, [r0]
-    cmp     r1, #1
-    beq     rt_hw_context_switch_interrupt_do
-
-    ldmfd   sp!, {r0-r12,lr}
-    subs    pc,  lr, #4
-
-rt_hw_context_switch_interrupt_do:
-    mov     r1,  #0         @ clear flag
-    str     r1,  [r0]
-
-    mov     r1, sp          @ r1 point to {r0-r3} in stack
-    add     sp, sp, #4*4
-    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
-    mrs     r0,  spsr       @ get cpsr of interrupt thread
-    sub     r2,  lr, #4     @ save old task's pc to r2
-
-    @ Switch to SVC mode with no interrupt. If the usr mode guest is
-    @ interrupted, this will just switch to the stack of kernel space.
-    @ save the registers in kernel space won't trigger data abort.
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
-    stmfd   sp!, {r2}       @ push old task's pc
-    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
-    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
-    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
-    stmfd   sp!, {r0}       @ push old task's cpsr
-
-#ifdef RT_USING_LWP
-    stmfd sp, {r13, r14}^  @push usr_sp, usr_lr
-    sub sp, #8
-#endif
-
-    ldr     r4,  =rt_interrupt_from_thread
-    ldr     r5,  [r4]
-    str     sp,  [r5]       @ store sp in preempted tasks's TCB
-
-    ldr     r6,  =rt_interrupt_to_thread
-    ldr     r6,  [r6]
-    ldr     sp,  [r6]       @ get new task's stack pointer
-
-#ifdef RT_USING_LWP
-    ldmfd sp, {r13, r14}^  @pop usr_sp, usr_lr
-    add sp, #8
-#endif
-
-    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
-    msr     spsr_cxsf, r4
-
-    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
-
-#endif
-
-.macro push_svc_reg
-    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
-    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
-    mov     r0, sp
-    mrs     r6, spsr                @/* Save CPSR                       */
-    str     lr, [r0, #15*4]         @/* Push PC                         */
-    str     r6, [r0, #16*4]         @/* Push CPSR                       */
-    cps     #Mode_SVC
-    str     sp, [r0, #13*4]         @/* Save calling SP                 */
-    str     lr, [r0, #14*4]         @/* Save calling PC                 */
-.endm
-
-    .align  5
-    .globl  vector_swi
-.weak SVC_Handler
-SVC_Handler:
-vector_swi:
-    push_svc_reg
-    bl      rt_hw_trap_swi
-    b       .
-
-    .align  5
-    .globl  vector_undef
-vector_undef:
-    push_svc_reg
-    bl      rt_hw_trap_undef
-    b       .
-
-    .align  5
-    .globl  vector_pabt
-vector_pabt:
-    push_svc_reg
-    bl      rt_hw_trap_pabt
-    b       .
-
-    .align  5
-    .globl  vector_dabt
-vector_dabt:
-    push_svc_reg
-    bl      rt_hw_trap_dabt
-    b       .
-
-    .align  5
-    .globl  vector_resv
-vector_resv:
-    push_svc_reg
-    bl      rt_hw_trap_resv
-    b       .
-
-#ifdef RT_USING_SMP
-.global set_secondary_cpu_boot_address
-set_secondary_cpu_boot_address:
-    ldr r0, =secondary_cpu_start
-
-    mvn r1, #0 //0xffffffff
-    ldr r2, =0x10000034
-    str r1, [r2]
-    str r0, [r2, #-4]
-    mov pc, lr
-
-.global secondary_cpu_start
-secondary_cpu_start:
-    mrc p15, 0, r1, c1, c0, 1
-    mov r0, #(1<<6)
-    orr r1, r0
-    mcr p15, 0, r1, c1, c0, 1 //enable smp
-
-    ldr r0, =mtbl
-    ldr lr, =1f
-
-    b enable_mmu
-1:
-    mrc p15, 0, r0, c1, c0, 0
-    bic r0, #(1<<13)
-    mcr p15, 0, r0, c1, c0, 0
-
-    cps #Mode_IRQ
-    ldr sp, =irq_stack_2_limit
-
-    cps #Mode_FIQ
-    ldr sp, =irq_stack_2_limit
-
-    cps #Mode_SVC
-    ldr sp, =svc_stack_2_limit
-
-    b secondary_cpu_c_start
-#endif
-
-.bss
-.align 2   //align to  2~2=4
-svc_stack_2:
-    .space (1 << 10)
-svc_stack_2_limit:
-
-irq_stack_2:
-    .space (1 << 10)
-irq_stack_2_limit:
-
-.data
-#define DEVICE_MEM  0x10c06
-#define NORMAL_MEM  0x11c0e
-.align 14
-mtbl:
-
-    //vaddr: 0x00000000
-    .rept 0x100
-    .word 0x0
-    .endr
-
-    //vaddr: 0x10000000
-    .equ mmu_tbl_map_paddr, 0x10000000
-    .rept 0x400
-    .word mmu_tbl_map_paddr | DEVICE_MEM
-    .equ mmu_tbl_map_paddr, mmu_tbl_map_paddr + 0x100000
-    .endr
-
-    //vaddr: 0x50000000
-    .rept 0x100
-    .word 0x0
-    .endr
-
-    //vaddr: 0x60000000
-    .equ mmu_tbl_map_paddr, 0x60000000
-    .rept 0x800
-    .word mmu_tbl_map_paddr | NORMAL_MEM
-    .equ mmu_tbl_map_paddr, mmu_tbl_map_paddr + 0x100000
-    .endr
-
-    //vaddr: 0xe0000000
-    .rept 0x200
-    .word 0x0
-    .endr
diff --git a/bsp/qemu-vexpress-a9/cpu/trap.c b/bsp/qemu-vexpress-a9/cpu/trap.c
deleted file mode 100644
index a1f00d0075..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/trap.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-20     Bernard      first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <board.h>
-
-#include "armv7.h"
-
-#include "gic.h"
-
-#ifdef RT_USING_FINSH
-extern long list_thread(void);
-#endif
-
-/**
- * this function will show registers of CPU
- *
- * @param regs the registers point
- */
-void rt_hw_show_register(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("Execption:\n");
-    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
-}
-
-/**
- * When comes across an instruction which it cannot handle,
- * it takes the undefined instruction trap.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("undefined instruction:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * The software interrupt instruction (SWI) is used for entering
- * Supervisor mode, usually to request a particular supervisor
- * function.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("software interrupt:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * An abort indicates that the current memory access cannot be completed,
- * which occurs during an instruction prefetch.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("prefetch abort:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * An abort indicates that the current memory access cannot be completed,
- * which occurs during a data access.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("data abort:");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * Normally, system will never reach here
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("reserved trap:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-#define GIC_ACK_INTID_MASK              0x000003ff
-
-void rt_hw_trap_irq(void)
-{
-    void *param;
-    unsigned long ir;
-    unsigned long fullir;
-    rt_isr_handler_t isr_func;
-    extern struct rt_irq_desc isr_table[];
-
-    fullir = arm_gic_get_active_irq(0);
-    ir = fullir & GIC_ACK_INTID_MASK;
-
-    if (ir == 1023)
-    {
-        /* Spurious interrupt */
-        return;
-    }
-
-    /* get interrupt service routine */
-    isr_func = isr_table[ir].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-    isr_table[ir].counter++;
-#endif
-    if (isr_func)
-    {
-        /* Interrupt for myself. */
-        param = isr_table[ir].param;
-        /* turn to interrupt service routine */
-        isr_func(ir, param);
-    }
-
-    /* end of interrupt */
-    arm_gic_ack(0, fullir);
-}
-
-void rt_hw_trap_fiq(void)
-{
-    void *param;
-    unsigned long ir;
-    unsigned long fullir;
-    rt_isr_handler_t isr_func;
-    extern struct rt_irq_desc isr_table[];
-
-    fullir = arm_gic_get_active_irq(0);
-    ir = fullir & GIC_ACK_INTID_MASK;
-
-    /* get interrupt service routine */
-    isr_func = isr_table[ir].handler;
-    param = isr_table[ir].param;
-
-    /* turn to interrupt service routine */
-    isr_func(ir, param);
-
-    /* end of interrupt */
-    arm_gic_ack(0, fullir);
-}
-
diff --git a/bsp/qemu-vexpress-a9/cpu/vector_gcc.S b/bsp/qemu-vexpress-a9/cpu/vector_gcc.S
deleted file mode 100644
index 2473e1f850..0000000000
--- a/bsp/qemu-vexpress-a9/cpu/vector_gcc.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * File      : vector_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.section .vectors, "ax"
-.code 32
-
-.globl system_vectors
-system_vectors:
-    ldr pc, _vector_reset
-    ldr pc, _vector_undef
-    ldr pc, _vector_swi
-    ldr pc, _vector_pabt
-    ldr pc, _vector_dabt
-    ldr pc, _vector_resv
-    ldr pc, _vector_irq
-    ldr pc, _vector_fiq
-
-.globl _reset
-.globl vector_undef
-.globl vector_swi
-.globl vector_pabt
-.globl vector_dabt
-.globl vector_resv
-.globl vector_irq
-.globl vector_fiq
-
-_vector_reset:
-    .word _reset
-_vector_undef:
-    .word vector_undef
-_vector_swi:
-    .word SVC_Handler
-_vector_pabt:
-    .word vector_pabt
-_vector_dabt:
-    .word vector_dabt
-_vector_resv:
-    .word vector_resv
-_vector_irq:
-    .word vector_irq
-_vector_fiq:
-    .word vector_fiq
-
-.balignl    16,0xdeadbeef
diff --git a/bsp/qemu-vexpress-a9/drivers/board.c b/bsp/qemu-vexpress-a9/drivers/board.c
index 6ffac7efd7..e236c68b80 100644
--- a/bsp/qemu-vexpress-a9/drivers/board.c
+++ b/bsp/qemu-vexpress-a9/drivers/board.c
@@ -17,6 +17,15 @@
 #include "board.h"
 #include "drv_timer.h"
 
+#include <mmu.h>
+
+struct mem_desc platform_mem_desc[] = {
+    {0x10000000, 0x50000000, 0x10000000, DEVICE_MEM},
+    {0x60000000, 0xe0000000, 0x60000000, NORMAL_MEM}
+};
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
+
 #define SYS_CTRL                        __REG32(REALVIEW_SCTL_BASE)
 
 extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
diff --git a/bsp/qemu-vexpress-a9/platform/SConscript b/bsp/qemu-vexpress-a9/platform/SConscript
new file mode 100644
index 0000000000..1b580929da
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/platform/SConscript
@@ -0,0 +1,13 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Split('''
+''')
+
+CPPPATH = [ cwd + '/cpu',
+cwd + '/include',
+]
+
+group = DefineGroup('Platform', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/qemu-vexpress-a9/platform/cpu/platform.h b/bsp/qemu-vexpress-a9/platform/cpu/platform.h
new file mode 100644
index 0000000000..2d5cc5f61b
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/platform/cpu/platform.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-22     quanzhao     first version
+ */
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+/* for 'rt_inline' */
+#include <rtdef.h>
+/* SOC-relative definitions */
+#include "realview.h"
+
+/* the maximum entries of the exception table */
+#define MAX_HANDLERS    NR_IRQS_PBA8
+
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    return REALVIEW_GIC_DIST_BASE;
+}
+
+rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
+{
+    return REALVIEW_GIC_CPU_BASE;
+}
+
+#define GIC_IRQ_START   0
+
+#define GIC_ACK_INTID_MASK  0x000003ff
+
+#endif  /* __PLATFORM_H__ */
diff --git a/bsp/qemu-vexpress-a9/rtconfig.h b/bsp/qemu-vexpress-a9/rtconfig.h
index b6c3399da3..831d54c52f 100644
--- a/bsp/qemu-vexpress-a9/rtconfig.h
+++ b/bsp/qemu-vexpress-a9/rtconfig.h
@@ -10,7 +10,9 @@
 #define RT_USING_SMP
 #define RT_CPUS_NR 2
 #define RT_ALIGN_SIZE 4
+/* RT_THREAD_PRIORITY_8 is not set */
 #define RT_THREAD_PRIORITY_32
+/* RT_THREAD_PRIORITY_256 is not set */
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
@@ -37,7 +39,10 @@
 
 #define RT_USING_MEMPOOL
 #define RT_USING_MEMHEAP
+/* RT_USING_NOHEAP is not set */
 #define RT_USING_SMALL_MEM
+/* RT_USING_SLAB is not set */
+/* RT_USING_MEMHEAP_AS_HEAP is not set */
 #define RT_USING_MEMTRACE
 #define RT_USING_HEAP
 
@@ -53,6 +58,7 @@
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_A
 #define ARCH_ARM_CORTEX_A9
+/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
 
 /* RT-Thread Components */
 
@@ -73,11 +79,14 @@
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
+/* FINSH_ECHO_DISABLE_DEFAULT is not set */
 #define FINSH_THREAD_PRIORITY 20
 #define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
+/* FINSH_USING_AUTH is not set */
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
+/* FINSH_USING_MSH_ONLY is not set */
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
@@ -87,21 +96,29 @@
 #define DFS_FILESYSTEMS_MAX 2
 #define DFS_FILESYSTEM_TYPES_MAX 8
 #define DFS_FD_MAX 16
+/* RT_USING_DFS_MNTTABLE is not set */
 #define RT_USING_DFS_ELMFAT
 
 /* elm-chan's FatFs, Generic FAT Filesystem Module */
 
 #define RT_DFS_ELM_CODE_PAGE 437
 #define RT_DFS_ELM_WORD_ACCESS
+/* RT_DFS_ELM_USE_LFN_0 is not set */
+/* RT_DFS_ELM_USE_LFN_1 is not set */
+/* RT_DFS_ELM_USE_LFN_2 is not set */
 #define RT_DFS_ELM_USE_LFN_3
 #define RT_DFS_ELM_USE_LFN 3
 #define RT_DFS_ELM_MAX_LFN 255
 #define RT_DFS_ELM_DRIVES 2
 #define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
+/* RT_DFS_ELM_USE_ERASE is not set */
 #define RT_DFS_ELM_REENTRANT
 #define RT_USING_DFS_DEVFS
 #define RT_USING_DFS_ROMFS
 #define RT_USING_DFS_RAMFS
+/* RT_USING_DFS_UFFS is not set */
+/* RT_USING_DFS_JFFS2 is not set */
+/* RT_USING_DFS_NFS is not set */
 
 /* Device Drivers */
 
@@ -110,12 +127,19 @@
 #define RT_USING_SERIAL
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
+/* RT_USING_CAN is not set */
+/* RT_USING_HWTIMER is not set */
+/* RT_USING_CPUTIME is not set */
 #define RT_USING_I2C
 #define RT_USING_I2C_BITOPS
 #define RT_USING_PIN
+/* RT_USING_ADC is not set */
+/* RT_USING_PWM is not set */
 #define RT_USING_MTD_NOR
 #define RT_USING_MTD_NAND
 #define RT_MTD_NAND_DEBUG
+/* RT_USING_MTD is not set */
+/* RT_USING_PM is not set */
 #define RT_USING_RTC
 #define RT_USING_SOFT_RTC
 #define RT_USING_SDIO
@@ -124,18 +148,31 @@
 #define RT_MMCSD_STACK_SIZE 1024
 #define RT_MMCSD_THREAD_PREORITY 22
 #define RT_MMCSD_MAX_PARTITION 16
+/* RT_SDIO_DEBUG is not set */
 #define RT_USING_SPI
+/* RT_USING_QSPI is not set */
 #define RT_USING_SPI_MSD
 #define RT_USING_SFUD
 #define RT_SFUD_USING_SFDP
 #define RT_SFUD_USING_FLASH_INFO_TABLE
+/* RT_SFUD_USING_QSPI is not set */
+/* RT_DEBUG_SFUD is not set */
+/* RT_USING_W25QXX is not set */
+/* RT_USING_GD is not set */
+/* RT_USING_ENC28J60 is not set */
+/* RT_USING_SPI_WIFI is not set */
 #define RT_USING_WDT
+/* RT_USING_AUDIO is not set */
+/* RT_USING_SENSOR is not set */
 
 /* Using WiFi */
 
+/* RT_USING_WIFI is not set */
 
 /* Using USB */
 
+/* RT_USING_USB_HOST is not set */
+/* RT_USING_USB_DEVICE is not set */
 
 /* POSIX layer and C standard library */
 
@@ -145,6 +182,7 @@
 #define RT_USING_POSIX_MMAP
 #define RT_USING_POSIX_TERMIOS
 #define RT_USING_POSIX_AIO
+/* RT_USING_MODULE is not set */
 
 /* Network */
 
@@ -161,9 +199,13 @@
 /* light weight TCP/IP stack */
 
 #define RT_USING_LWIP
+/* RT_USING_LWIP141 is not set */
 #define RT_USING_LWIP202
+/* RT_USING_LWIP210 is not set */
 #define RT_USING_LWIP_IPV6
+/* RT_LWIP_IGMP is not set */
 #define RT_LWIP_ICMP
+/* RT_LWIP_SNMP is not set */
 #define RT_LWIP_DNS
 #define RT_LWIP_DHCP
 #define IP_SOF_BROADCAST 1
@@ -176,6 +218,8 @@
 #define RT_LWIP_MSKADDR "255.255.255.0"
 #define RT_LWIP_UDP
 #define RT_LWIP_TCP
+/* RT_LWIP_RAW is not set */
+/* RT_LWIP_PPP is not set */
 #define RT_MEMP_NUM_NETCONN 8
 #define RT_LWIP_PBUF_NUM 16
 #define RT_LWIP_RAW_PCB_NUM 4
@@ -187,6 +231,8 @@
 #define RT_LWIP_TCPTHREAD_PRIORITY 10
 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
 #define RT_LWIP_TCPTHREAD_STACKSIZE 1024
+/* LWIP_NO_RX_THREAD is not set */
+/* LWIP_NO_TX_THREAD is not set */
 #define RT_LWIP_ETHTHREAD_PRIORITY 12
 #define RT_LWIP_ETHTHREAD_STACKSIZE 1024
 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
@@ -196,62 +242,164 @@
 #define LWIP_SO_RCVTIMEO 1
 #define LWIP_SO_SNDTIMEO 1
 #define LWIP_SO_RCVBUF 1
+/* RT_LWIP_NETIF_LOOPBACK is not set */
 #define LWIP_NETIF_LOOPBACK 0
+/* RT_LWIP_STATS is not set */
+/* RT_LWIP_DEBUG is not set */
 
 /* Modbus master and slave stack */
 
+/* RT_USING_MODBUS is not set */
 
 /* AT commands */
 
+/* RT_USING_AT is not set */
+/* LWIP_USING_DHCPD is not set */
 
 /* VBUS(Virtual Software BUS) */
 
+/* RT_USING_VBUS is not set */
 
 /* Utilities */
 
 #define RT_USING_LOGTRACE
 #define LOG_TRACE_MAX_SESSION 16
+/* LOG_TRACE_USING_LEVEL_NOTRACE is not set */
+/* LOG_TRACE_USING_LEVEL_ERROR is not set */
+/* LOG_TRACE_USING_LEVEL_WARNING is not set */
 #define LOG_TRACE_USING_LEVEL_INFO
+/* LOG_TRACE_USING_LEVEL_VERBOSE is not set */
+/* LOG_TRACE_USING_LEVEL_DEBUG is not set */
+/* LOG_TRACE_USING_MEMLOG is not set */
+/* RT_USING_RYM is not set */
+/* RT_USING_ULOG is not set */
+/* RT_USING_UTEST is not set */
 #define RT_USING_LWP
 
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
 
+/* PKG_USING_PAHOMQTT is not set */
+/* PKG_USING_WEBCLIENT is not set */
+/* PKG_USING_WEBNET is not set */
+/* PKG_USING_MONGOOSE is not set */
+/* PKG_USING_WEBTERMINAL is not set */
+/* PKG_USING_CJSON is not set */
+/* PKG_USING_JSMN is not set */
+/* PKG_USING_LIBMODBUS is not set */
+/* PKG_USING_LJSON is not set */
+/* PKG_USING_EZXML is not set */
+/* PKG_USING_NANOPB is not set */
 
 /* Wi-Fi */
 
 /* Marvell WiFi */
 
+/* PKG_USING_WLANMARVELL is not set */
 
 /* Wiced WiFi */
 
+/* PKG_USING_WLAN_WICED is not set */
+/* PKG_USING_RW007 is not set */
+/* PKG_USING_COAP is not set */
+/* PKG_USING_NOPOLL is not set */
+/* PKG_USING_NETUTILS is not set */
+/* PKG_USING_AT_DEVICE is not set */
+/* PKG_USING_WIZNET is not set */
 
 /* IoT Cloud */
 
+/* PKG_USING_ONENET is not set */
+/* PKG_USING_GAGENT_CLOUD is not set */
+/* PKG_USING_ALI_IOTKIT is not set */
+/* PKG_USING_AZURE is not set */
+/* PKG_USING_TENCENT_IOTKIT is not set */
+/* PKG_USING_NIMBLE is not set */
+/* PKG_USING_OTA_DOWNLOADER is not set */
 
 /* security packages */
 
+/* PKG_USING_MBEDTLS is not set */
+/* PKG_USING_libsodium is not set */
+/* PKG_USING_TINYCRYPT is not set */
 
 /* language packages */
 
+/* PKG_USING_LUA is not set */
+/* PKG_USING_JERRYSCRIPT is not set */
+/* PKG_USING_MICROPYTHON is not set */
 
 /* multimedia packages */
 
+/* PKG_USING_OPENMV is not set */
+/* PKG_USING_MUPDF is not set */
 
 /* tools packages */
 
+/* PKG_USING_CMBACKTRACE is not set */
+/* PKG_USING_EASYFLASH is not set */
+/* PKG_USING_EASYLOGGER is not set */
+/* PKG_USING_SYSTEMVIEW is not set */
+/* PKG_USING_RDB is not set */
+/* PKG_USING_QRCODE is not set */
+/* PKG_USING_ULOG_EASYFLASH is not set */
+/* PKG_USING_ADBD is not set */
 
 /* system packages */
 
+/* PKG_USING_GUIENGINE is not set */
+/* PKG_USING_PERSIMMON is not set */
+/* PKG_USING_CAIRO is not set */
+/* PKG_USING_PIXMAN is not set */
+/* PKG_USING_LWEXT4 is not set */
+/* PKG_USING_PARTITION is not set */
+/* PKG_USING_FAL is not set */
+/* PKG_USING_SQLITE is not set */
+/* PKG_USING_RTI is not set */
+/* PKG_USING_LITTLEVGL2RTT is not set */
+/* PKG_USING_CMSIS is not set */
+/* PKG_USING_DFS_YAFFS is not set */
+/* PKG_USING_LITTLEFS is not set */
 
 /* peripheral libraries and drivers */
 
 /* sensors drivers */
 
+/* PKG_USING_LSM6DSL is not set */
+/* PKG_USING_LPS22HB is not set */
+/* PKG_USING_HTS221 is not set */
+/* PKG_USING_LSM303AGR is not set */
+/* PKG_USING_BME280 is not set */
+/* PKG_USING_BMA400 is not set */
+/* PKG_USING_BMI160_BMX160 is not set */
+/* PKG_USING_SPL0601 is not set */
+/* PKG_USING_REALTEK_AMEBA is not set */
+/* PKG_USING_SHT2X is not set */
+/* PKG_USING_AHT10 is not set */
+/* PKG_USING_AP3216C is not set */
+/* PKG_USING_STM32_SDIO is not set */
+/* PKG_USING_ICM20608 is not set */
+/* PKG_USING_U8G2 is not set */
+/* PKG_USING_BUTTON is not set */
+/* PKG_USING_MPU6XXX is not set */
+/* PKG_USING_PCF8574 is not set */
+/* PKG_USING_SX12XX is not set */
+/* PKG_USING_KENDRYTE_SDK is not set */
 
 /* miscellaneous packages */
 
+/* PKG_USING_LIBCSV is not set */
+/* PKG_USING_OPTPARSE is not set */
+/* PKG_USING_FASTLZ is not set */
+/* PKG_USING_MINILZO is not set */
+/* PKG_USING_QUICKLZ is not set */
+/* PKG_USING_MULTIBUTTON is not set */
+/* PKG_USING_CANFESTIVAL is not set */
+/* PKG_USING_ZLIB is not set */
+/* PKG_USING_DSTR is not set */
+/* PKG_USING_TINYFRAME is not set */
+/* PKG_USING_KENDRYTE_DEMO is not set */
 
 /* samples: kernel and components samples */
 
@@ -259,5 +407,6 @@
 #define RT_USING_UART0
 #define RT_USING_UART1
 #define BSP_DRV_EMAC
+/* BSP_DRV_AUDIO is not set */
 
 #endif
diff --git a/bsp/qemu-vexpress-a9/rtconfig.py b/bsp/qemu-vexpress-a9/rtconfig.py
index 8ccd0227e4..d417673898 100644
--- a/bsp/qemu-vexpress-a9/rtconfig.py
+++ b/bsp/qemu-vexpress-a9/rtconfig.py
@@ -2,14 +2,15 @@ import os
 
 # toolchains options
 ARCH='arm'
-CPU='cortex-a9'
+CPU='cortex-a'
 CROSS_TOOL='gcc'
 
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
+# only support GNU GCC compiler.
 PLATFORM    = 'gcc'
-EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+EXEC_PATH   = '/usr/bin'
 
 if os.getenv('RTT_EXEC_PATH'):
     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
diff --git a/components/lwp/SConscript b/components/lwp/SConscript
index d3b799257b..f151f3b92e 100644
--- a/components/lwp/SConscript
+++ b/components/lwp/SConscript
@@ -5,7 +5,7 @@ cwd     = GetCurrentDir()
 src     = []
 CPPPATH = [cwd]
 
-support_arch  = {"arm": ["cortex-m3", "cortex-m4", "cortex-m7", "arm926", "cortex-a9"]}
+support_arch  = {"arm": ["cortex-m3", "cortex-m4", "cortex-m7", "arm926", "cortex-a"]}
 platform_file = {'armcc': 'rvds.S', 'gcc': 'gcc.S', 'iar': 'iar.S'}
 
 if rtconfig.PLATFORM in platform_file.keys():	# support platforms
diff --git a/components/lwp/arch/arm/cortex-a/lwp_gcc.S b/components/lwp/arch/arm/cortex-a/lwp_gcc.S
new file mode 100644
index 0000000000..6c89152b0c
--- /dev/null
+++ b/components/lwp/arch/arm/cortex-a/lwp_gcc.S
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     Jesven       first version
+ */
+
+#define  Mode_USR       0x10
+#define  Mode_FIQ       0x11
+#define  Mode_IRQ       0x12
+#define  Mode_SVC       0x13
+#define  Mode_MON       0x16
+#define  Mode_ABT       0x17
+#define  Mode_UDF       0x1B
+#define  Mode_SYS       0x1F
+
+#define A_Bit        0x100 
+#define I_Bit        0x80 @; when I bit is set, IRQ is disabled
+#define F_Bit        0x40 @; when F bit is set, FIQ is disabled
+#define T_Bit        0x20
+
+.cpu cortex-a9
+.syntax unified
+.text
+
+/*
+ * void lwp_user_entry(args, text, data);
+ */
+.global lwp_user_entry
+.type lwp_user_entry, % function
+lwp_user_entry:
+    mrs     r9, cpsr
+    bic     r9, #0x1f
+    orr     r9, #Mode_USR
+    cpsid i
+    msr     spsr, r9
+
+    /* set data address. */
+    mov     r9, r2
+    movs    pc, r1
+
+/*
+ * void SVC_Handler(void);
+ */
+.global SVC_Handler
+.type SVC_Handler, % function
+SVC_Handler:
+    push {lr}
+    mrs lr, spsr
+    push {r4, r5, lr}
+    cpsie i
+
+    push {r0 - r3, r12}
+    and r0, r7, #0xff
+    bl lwp_get_sys_api
+    cmp r0, #0           /* r0 = api */
+    mov lr, r0
+    pop {r0 - r3, r12}
+    beq svc_exit
+    blx lr
+
+svc_exit:
+    cpsid i
+    pop {r4, r5, lr}
+    msr spsr_cxsf, lr
+    pop {lr}
+    movs pc, lr
diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S
index 97b3dbc447..b009630fa8 100644
--- a/libcpu/arm/cortex-a/context_gcc.S
+++ b/libcpu/arm/cortex-a/context_gcc.S
@@ -8,7 +8,14 @@
  * 2013-07-05     Bernard      the first version
  */
 
+#include "rtconfig.h"
 .section .text, "ax"
+
+#ifdef RT_USING_SMP
+#define rt_hw_interrupt_disable rt_hw_local_irq_disable
+#define rt_hw_interrupt_enable  rt_hw_local_irq_enable
+#endif
+
 /*
  * rt_base_t rt_hw_interrupt_disable();
  */
@@ -34,6 +41,16 @@ rt_hw_interrupt_enable:
 rt_hw_context_switch_to:
     ldr sp, [r0]            @ get new task stack pointer
 
+#ifdef RT_USING_SMP
+    mov     r0, r1
+    bl      rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+
+#ifdef RT_USING_LWP
+    ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr
+    add sp, #8
+#endif
+
     ldmfd sp!, {r4}         @ pop new task spsr
     msr spsr_cxsf, r4
 
@@ -62,9 +79,24 @@ rt_hw_context_switch:
 
     stmfd sp!, {r4}         @ push cpsr
 
+#ifdef RT_USING_LWP
+    stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
+    sub sp, #8
+#endif
+
     str sp, [r0]            @ store sp in preempted tasks TCB
     ldr sp, [r1]            @ get new task stack pointer
 
+#ifdef RT_USING_SMP
+    mov     r0, r2
+    bl      rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+
+#ifdef RT_USING_LWP
+    ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr
+    add sp, #8
+#endif
+
     ldmfd sp!, {r4}         @ pop new task cpsr to spsr
     msr spsr_cxsf, r4
     ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
@@ -72,11 +104,70 @@ rt_hw_context_switch:
 /*
  * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
  */
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
 .globl rt_thread_switch_interrupt_flag
 .globl rt_interrupt_from_thread
 .globl rt_interrupt_to_thread
 .globl rt_hw_context_switch_interrupt
 rt_hw_context_switch_interrupt:
+#ifdef RT_USING_SMP
+    /* r0 :irq_mod context
+     * r1 :addr of from_thread's sp
+     * r2 :addr of to_thread's sp
+     * r3 :to_thread's tcb
+     */
+
+    @ r0 point to {r0-r3} in stack
+    push    {r1 - r3}
+    mov     r1, r0
+    add     r0, r0, #4*4
+    ldmfd   r0!, {r4-r12,lr}@ reload saved registers
+    mrs     r3,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r4-r7}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r4-r7}    @ push old task's r0-r3
+    stmfd   sp!, {r3}       @ push old task's cpsr
+
+#ifdef RT_USING_LWP
+    stmfd sp, {r13,r14}^    @push usr_sp usr_lr
+    sub sp, #8
+#endif
+
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ
+    pop     {r1 - r3}
+    mov     sp, r0
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+    str     sp, [r1]
+
+    ldr     sp, [r2]
+    mov     r0, r3
+    bl      rt_cpus_lock_status_restore
+
+#ifdef RT_USING_LWP
+    ldmfd sp, {r13,r14}^  @pop usr_sp usr_lr
+    add sp, #8
+#endif
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+#else /*RT_USING_SMP*/
     ldr r2, =rt_thread_switch_interrupt_flag
     ldr r3, [r2]
     cmp r3, #1
@@ -89,3 +180,4 @@ _reswitch:
     ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
     str r1, [r2]
     bx  lr
+#endif /*RT_USING_SMP*/
diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h
index 486f38200d..97c5b93ad2 100644
--- a/libcpu/arm/cortex-a/cp15.h
+++ b/libcpu/arm/cortex-a/cp15.h
@@ -5,6 +5,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
+ * 2018-03-25     quanzhao     the first version
  */
 #ifndef __CP15_H__
 #define __CP15_H__
@@ -15,6 +16,9 @@ void rt_cpu_mmu_disable(void);
 void rt_cpu_mmu_enable(void);
 void rt_cpu_tlb_set(volatile unsigned long*);
 
+void rt_cpu_dcache_clean_flush(void);
+void rt_cpu_icache_flush(void);
+
 void rt_cpu_vector_set_base(unsigned int addr);
 
 #endif
diff --git a/libcpu/arm/cortex-a/cp15_gcc.S b/libcpu/arm/cortex-a/cp15_gcc.S
index 0e3e60655c..dd2436ffee 100644
--- a/libcpu/arm/cortex-a/cp15_gcc.S
+++ b/libcpu/arm/cortex-a/cp15_gcc.S
@@ -15,6 +15,11 @@ rt_cpu_get_smp_id:
 
 .globl rt_cpu_vector_set_base
 rt_cpu_vector_set_base:
+    /* clear SCTRL.V to customize the vector address */
+    mrc     p15, #0, r1, c1, c0, #0
+    bic     r1, #(1 << 13)
+    mcr     p15, #0, r1, c1, c0, #0
+    /* set up the vector address */
     mcr     p15, #0, r0, c12, c0, #0
     dsb
     bx      lr
@@ -36,7 +41,7 @@ rt_hw_cpu_icache_enable:
 _FLD_MAX_WAY:
    .word  0x3ff
 _FLD_MAX_IDX:
-   .word  0x7ff
+   .word  0x7fff
 
 .globl rt_cpu_dcache_clean_flush
 rt_cpu_dcache_clean_flush:
@@ -84,6 +89,14 @@ finished:
     pop     {r4-r11}
     bx      lr
 
+.globl rt_cpu_icache_flush
+rt_cpu_icache_flush:
+    mov r0, #0
+    mcr p15, 0, r0, c7, c5, 0       @ I+BTB cache invalidate
+    dsb
+    isb
+    bx      lr
+
 .globl rt_hw_cpu_dcache_disable
 rt_hw_cpu_dcache_disable:
     push    {r4-r11, lr}
diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c
index 2d78715011..6b129f89ee 100644
--- a/libcpu/arm/cortex-a/cpu.c
+++ b/libcpu/arm/cortex-a/cpu.c
@@ -6,28 +6,78 @@
  * Change Logs:
  * Date           Author       Notes
  * 2011-09-15     Bernard      first version
+ * 2018-11-22     Jesven       add rt_hw_cpu_id()
  */
 
 #include <rthw.h>
 #include <rtthread.h>
 #include <board.h>
 
+#ifdef RT_USING_SMP
+int rt_hw_cpu_id(void)
+{
+    int cpu_id;
+    __asm__ volatile (
+            "mrc p15, 0, %0, c0, c0, 5"
+            :"=r"(cpu_id)
+            );
+    cpu_id &= 0xf;
+    return cpu_id;
+};
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    unsigned long tmp;
+    unsigned long newval;
+    rt_hw_spinlock_t lockval;
+
+    __asm__ __volatile__(
+            "pld [%0]"
+            ::"r"(&lock->slock)
+            );
+
+    __asm__ __volatile__(
+            "1: ldrex   %0, [%3]\n"
+            "   add %1, %0, %4\n"
+            "   strex   %2, %1, [%3]\n"
+            "   teq %2, #0\n"
+            "   bne 1b"
+            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+            : "r" (&lock->slock), "I" (1 << 16)
+            : "cc");
+
+    while (lockval.tickets.next != lockval.tickets.owner) {
+        __asm__ __volatile__("wfe":::"memory");
+        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
+    }
+
+    __asm__ volatile ("dmb":::"memory");
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    __asm__ volatile ("dmb":::"memory");
+    lock->tickets.owner++;
+    __asm__ volatile ("dsb ishst\nsev":::"memory");
+}
+#endif /*RT_USING_SMP*/
+
 /**
- * @addtogroup AM33xx
+ * @addtogroup ARM CPU
  */
 /*@{*/
 
 /** shutdown CPU */
 void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
-
-	level = rt_hw_interrupt_disable();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 /*@}*/
diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c
new file mode 100644
index 0000000000..2a46142b54
--- /dev/null
+++ b/libcpu/arm/cortex-a/gic.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2014-04-03     Grissiom     many enhancements
+ * 2018-11-22     Jesven       add rt_hw_ipi_send()
+ *                             add rt_hw_ipi_handler_install()
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "gic.h"
+#include "cp15.h"
+
+struct arm_gic
+{
+    rt_uint32_t offset;         /* the first interrupt index in the vector table */
+
+    rt_uint32_t dist_hw_base;   /* the base address of the gic distributor */
+    rt_uint32_t cpu_hw_base;    /* the base addrees of the gic cpu interface */
+};
+
+/* 'ARM_GIC_MAX_NR' is the number of cores */
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+static unsigned int _gic_max_irq;
+
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
+
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_pending(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_active(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+/* Set up the cpu mask for the specific interrupt */
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
+{
+    rt_uint32_t old_tgt;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+void arm_gic_umask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_dump_type(rt_uint32_t index)
+{
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
+}
+
+void arm_gic_dump(rt_uint32_t index)
+{
+    unsigned int i, k;
+
+    k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+    rt_kprintf("--- hw mask ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n--- hw pending ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
+                                        i * 32));
+    }
+    rt_kprintf("\n--- hw active ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n");
+}
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
+#endif
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
+{
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
+
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
+
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
+        _gic_max_irq = ARM_GIC_NR_IRQS;
+
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+    cpumask |= cpumask << 24;
+
+    GIC_DIST_CTRL(dist_base) = 0x0;
+
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
+
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
+
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
+
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
+
+#if 0
+    /* All interrupts defaults to IGROUP1(IRQ). */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
+#endif
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0;
+
+    /* Enable group0 and group1 interrupt forwarding. */
+    GIC_DIST_CTRL(dist_base) = 0x01;
+
+    return 0;
+}
+
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].cpu_hw_base = cpu_base;
+
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    GIC_CPU_BINPOINT(cpu_base) = 0x7;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
+
+    return 0;
+}
+
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
+{
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
+}
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+ {
+     /* note: ipi_vector maybe different with irq_vector */
+     GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector;
+}
+#endif
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
+{
+    /* note: ipi_vector maybe different with irq_vector */
+    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
+}
+#endif
diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h
new file mode 100644
index 0000000000..6d86dd31e0
--- /dev/null
+++ b/libcpu/arm/cortex-a/gic.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+#include <rthw.h>
+#include <platform.h>
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_clear_active(rt_uint32_t index, int irq);
+void arm_gic_clear_pending(rt_uint32_t index, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+void arm_gic_dump(rt_uint32_t index);
+
+#endif
+
diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c
index fb6e3ff3e0..b7a70719a9 100644
--- a/libcpu/arm/cortex-a/interrupt.c
+++ b/libcpu/arm/cortex-a/interrupt.c
@@ -6,68 +6,32 @@
  * Change Logs:
  * Date           Author       Notes
  * 2013-07-06     Bernard      first version
- * 2014-04-03     Grissiom     port to VMM
+ * 2018-11-22     Jesven       add smp support
  */
 
 #include <rthw.h>
 #include <rtthread.h>
+#include "interrupt.h"
+#include "gic.h"
 
-#include <irq_numbers.h>
-#include <interrupt.h>
-
-#include <gic.h>
-#include "cp15.h"
-
-#define MAX_HANDLERS                IMX_INTERRUPT_COUNT
-
-extern volatile rt_uint8_t rt_interrupt_nest;
 
 /* exception and interrupt handler table */
 struct rt_irq_desc isr_table[MAX_HANDLERS];
 
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
+#ifndef RT_USING_SMP
+/* Those varibles will be accessed in ISR, so we need to share them. */
+rt_uint32_t rt_interrupt_from_thread        = 0;
+rt_uint32_t rt_interrupt_to_thread          = 0;
+rt_uint32_t rt_thread_switch_interrupt_flag = 0;
+#endif
 
+const unsigned int VECTOR_BASE = 0x00;
 extern void rt_cpu_vector_set_base(unsigned int addr);
 extern int system_vectors;
 
-/* keep compatible with platform SDK */
-void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
-{
-    rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
-}
-
-void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
-{
-    gic_set_irq_priority(irq_id, priority);
-    gic_set_irq_security(irq_id, false);    // set IRQ as non-secure
-    gic_set_cpu_target(irq_id, cpu_id, true);
-    gic_enable_irq(irq_id, true);
-}
-
-void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
+void rt_hw_vector_init(void)
 {
-    gic_enable_irq(irq_id, false);
-    gic_set_cpu_target(irq_id, cpu_id, false);
-}
-
-static void rt_hw_vector_init(void)
-{
-    int sctrl;
-    unsigned int *src = (unsigned int *)&system_vectors;
-
-    /* C12-C0 is only active when SCTLR.V = 0 */
-    asm volatile ("mrc p15, #0, %0, c1, c0, #0"
-                  :"=r" (sctrl));
-    sctrl &= ~(1 << 13);
-    asm volatile ("mcr p15, #0, %0, c1, c0, #0"
-                  :
-                  :"r" (sctrl));
-
-    asm volatile ("mcr p15, #0, %0, c12, c0, #0"
-                  :
-                  :"r" (src));
+    rt_cpu_vector_set_base((unsigned int)&system_vectors);
 }
 
 /**
@@ -75,14 +39,24 @@ static void rt_hw_vector_init(void)
  */
 void rt_hw_interrupt_init(void)
 {
+    rt_uint32_t gic_cpu_base;
+    rt_uint32_t gic_dist_base;
+    rt_uint32_t gic_irq_start;
+
+    /* initialize vector table */
     rt_hw_vector_init();
-    gic_init();
 
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
+    /* initialize exceptions table */
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+
+    /* initialize ARM GIC */
+    gic_dist_base = platform_get_gic_dist_base();
+    gic_cpu_base = platform_get_gic_cpu_base();
+
+    gic_irq_start = GIC_IRQ_START;
+
+    arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
+    arm_gic_cpu_init(0, gic_cpu_base);
 }
 
 /**
@@ -91,7 +65,7 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int vector)
 {
-    disable_interrupt(vector, 0);
+    arm_gic_mask(0, vector);
 }
 
 /**
@@ -100,9 +74,26 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-    enable_interrupt(vector, 0, 0);
+    arm_gic_umask(0, vector);
 }
 
+/**
+ * This function returns the active interrupt number.
+ * @param none
+ */
+int rt_hw_interrupt_get_irq(void)
+{
+    return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK;
+}
+
+/**
+ * This function acknowledges the interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_ack(int vector)
+{
+    arm_gic_ack(0, vector);
+}
 /**
  * This function will install a interrupt service routine to a interrupt.
  * @param vector the interrupt number
@@ -126,23 +117,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
             isr_table[vector].handler = handler;
             isr_table[vector].param = param;
         }
-        // arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
     }
 
     return old_handler;
 }
-
-/**
- * Trigger a software IRQ
- *
- * Since we are running in single core, the target CPU are always CPU0.
- */
-void rt_hw_interrupt_trigger(int vector)
-{
-    // arm_gic_trigger(0, 1, vector);
-}
-
-void rt_hw_interrupt_clear(int vector)
-{
-    gic_write_end_of_irq(vector);
-}
diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h
new file mode 100644
index 0000000000..bff29d402d
--- /dev/null
+++ b/libcpu/arm/cortex-a/interrupt.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard      first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <platform.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_control(int vector, int priority, int route);
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_ack(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c
index 58acdd8145..1260f41fe5 100644
--- a/libcpu/arm/cortex-a/mmu.c
+++ b/libcpu/arm/cortex-a/mmu.c
@@ -13,35 +13,7 @@
 #include <board.h>
 
 #include "cp15.h"
-
-#define DESC_SEC       (0x2)
-#define CB             (3<<2)  //cache_on, write_back
-#define CNB            (2<<2)  //cache_on, write_through
-#define NCB            (1<<2)  //cache_off,WR_BUF on
-#define NCNB           (0<<2)  //cache_off,WR_BUF off
-#define AP_RW          (3<<10) //supervisor=RW, user=RW
-#define AP_RO          (2<<10) //supervisor=RW, user=RO
-#define XN             (1<<4)  // eXecute Never
-
-#define DOMAIN_FAULT   (0x0)
-#define DOMAIN_CHK     (0x1)
-#define DOMAIN_NOTCHK  (0x3)
-#define DOMAIN0        (0x0<<5)
-#define DOMAIN1        (0x1<<5)
-
-#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
-
-/* Read/Write, cache, write back */
-#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
-/* Read/Write, cache, write through */
-#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
-/* Read/Write without cache and write buffer */
-#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
-/* Read/Write without cache and write buffer, no execute */
-#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
-/* Read/Write without cache and write buffer */
-#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+#include "mmu.h"
 
 /* dump 2nd level page table */
 void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
@@ -178,18 +150,25 @@ unsigned long rt_hw_set_domain_register(unsigned long domain_val)
     return old_domain;
 }
 
+void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size)
+{
+    /* set page table */
+    for(; size > 0; size--)
+    {
+        rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
+                mdesc->paddr_start, mdesc->attr);
+        mdesc++;
+    }
+}
+
 void rt_hw_mmu_init(void)
 {
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
     rt_hw_cpu_dcache_disable();
     rt_hw_cpu_icache_disable();
     rt_cpu_mmu_disable();
 
-    /* set page table */
-    /* 4G 1:1 memory */
-    rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
-    /* IO memory region */
-    rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
-
     /*rt_hw_cpu_dump_page_table(MMUTable);*/
     rt_hw_set_domain_register(0x55555555);
 
diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h
new file mode 100644
index 0000000000..deec690c69
--- /dev/null
+++ b/libcpu/arm/cortex-a/mmu.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-25     quanzhao     the first version
+ */
+#ifndef __MMU_H_
+#define __MMU_H_
+
+#include <rtthread.h>
+
+#define DESC_SEC       (0x2)
+#define MEMWB          (3<<2)  /* write back, no write allocate */
+#define MEMWT          (2<<2)  /* write through, no write allocate */
+#define SHAREDEVICE    (1<<2)  /* shared device */
+#define STRONGORDER    (0<<2)  /* strong ordered */
+#define XN             (1<<4)  /* eXecute Never */
+#define AP_RW          (3<<10) /* supervisor=RW, user=RW */
+#define AP_RO          (2<<10) /* supervisor=RW, user=RO */
+#define SHARED         (1<<16) /* shareable */
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* device mapping type */
+#define DEVICE_MEM     (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN)
+/* normal memory mapping type */
+#define NORMAL_MEM     (SHARED|AP_RW|DOMAIN0|MEMWB|DESC_SEC)
+
+struct mem_desc
+{
+    rt_uint32_t vaddr_start;
+    rt_uint32_t vaddr_end;
+    rt_uint32_t paddr_start;
+    rt_uint32_t attr;
+};
+
+
+#endif
diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c
index 1d3ebcb9e6..d76b8a428a 100644
--- a/libcpu/arm/cortex-a/stack.c
+++ b/libcpu/arm/cortex-a/stack.c
@@ -50,13 +50,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     *(--stk) = 0xdeadbeef;                  /* r2 */
     *(--stk) = 0xdeadbeef;                  /* r1 */
     *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
-
     /* cpsr */
     if ((rt_uint32_t)tentry & 0x01)
         *(--stk) = SVCMODE | 0x20;          /* thumb mode */
     else
         *(--stk) = SVCMODE;                 /* arm mode   */
 
+#ifdef RT_USING_LWP
+    *(--stk) = 0;       /* user lr */
+    *(--stk) = 0;       /* user sp*/
+#endif
+
     /* return task's current stack address */
     return (rt_uint8_t *)stk;
 }
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 2f16d16807..0f4ff58364 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -6,8 +6,12 @@
  * Change Logs:
  * Date           Author       Notes
  * 2013-07-05     Bernard      the first version
+ * 2018-11-22     Jesven       in the interrupt context, use rt_scheduler_do_irq_switch checks
+ *                             and switches to a new thread
  */
 
+#include "rtconfig.h"
+
 .equ Mode_USR,        0x10
 .equ Mode_FIQ,        0x11
 .equ Mode_IRQ,        0x12
@@ -20,11 +24,11 @@
 .equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
 
 .equ UND_Stack_Size,     0x00000000
-.equ SVC_Stack_Size,     0x00000100
+.equ SVC_Stack_Size,     0x00000400
 .equ ABT_Stack_Size,     0x00000000
 .equ RT_FIQ_STACK_PGSZ,  0x00000000
-.equ RT_IRQ_STACK_PGSZ,  0x00000100
-.equ USR_Stack_Size,     0x00000100
+.equ RT_IRQ_STACK_PGSZ,  0x00000800
+.equ USR_Stack_Size,     0x00000400
 
 #define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                  RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
@@ -44,12 +48,8 @@ stack_top:
 /* reset entry */
 .globl _reset
 _reset:
-    bl      rt_cpu_mmu_disable
     /* set the cpu to SVC32 mode and disable interrupt */
-    mrs     r0, cpsr
-    bic     r0, r0, #0x1f
-    orr     r0, r0, #0x13
-    msr     cpsr_c, r0
+    cps #Mode_SVC
 
     /* setup stack */
     bl      stack_setup
@@ -64,6 +64,20 @@ bss_loop:
     strlo   r0,[r1],#4              /* clear 4 bytes                    */
     blo     bss_loop                /* loop until done                  */
 
+#ifdef RT_USING_SMP
+    mrc p15, 0, r1, c1, c0, 1
+    mov r0, #(1<<6)
+    orr r1, r0
+    mcr p15, 0, r1, c1, c0, 1 //enable smp
+#endif
+
+    /* initialize the mmu table and enable mmu */
+    ldr r0, =platform_mem_desc
+    ldr r1, =platform_mem_desc_size
+    ldr r1, [r1]
+    bl rt_hw_init_mmu_table
+    bl rt_hw_mmu_init
+
     /* call C++ constructors of global objects                          */
     ldr     r0, =__ctors_start__
     ldr     r1, =__ctors_end__
@@ -137,12 +151,22 @@ vector_fiq:
     .align  5
 .globl vector_irq
 vector_irq:
+#ifdef RT_USING_SMP
+    clrex
+#endif
     stmfd   sp!, {r0-r12,lr}
 
     bl      rt_interrupt_enter
     bl      rt_hw_trap_irq
     bl      rt_interrupt_leave
 
+#ifdef RT_USING_SMP
+    mov     r0, sp
+    bl      rt_scheduler_do_irq_switch
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
+#else
     @ if rt_thread_switch_interrupt_flag set, jump to
     @ rt_hw_context_switch_interrupt_do and don't return
     ldr     r0, =rt_thread_switch_interrupt_flag
@@ -174,6 +198,11 @@ rt_hw_context_switch_interrupt_do:
     stmfd   sp!, {r1-r4}    @ push old task's r0-r3
     stmfd   sp!, {r0}       @ push old task's cpsr
 
+#ifdef RT_USING_LWP
+    stmfd sp, {r13, r14}^  @push usr_sp, usr_lr
+    sub sp, #8
+#endif
+
     ldr     r4,  =rt_interrupt_from_thread
     ldr     r5,  [r4]
     str     sp,  [r5]       @ store sp in preempted tasks's TCB
@@ -182,11 +211,18 @@ rt_hw_context_switch_interrupt_do:
     ldr     r6,  [r6]
     ldr     sp,  [r6]       @ get new task's stack pointer
 
+#ifdef RT_USING_LWP
+    ldmfd sp, {r13, r14}^  @pop usr_sp, usr_lr
+    add sp, #8
+#endif
+
     ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
     msr     spsr_cxsf, r4
 
     ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
 
+#endif
+
 .macro push_svc_reg
     sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
     stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
@@ -200,36 +236,86 @@ rt_hw_context_switch_interrupt_do:
 .endm
 
     .align  5
-    .globl	vector_swi
+    .globl  vector_swi
+.weak SVC_Handler
+SVC_Handler:
 vector_swi:
     push_svc_reg
     bl      rt_hw_trap_swi
     b       .
 
     .align  5
-    .globl	vector_undef
+    .globl  vector_undef
 vector_undef:
     push_svc_reg
     bl      rt_hw_trap_undef
     b       .
 
     .align  5
-    .globl	vector_pabt
+    .globl  vector_pabt
 vector_pabt:
     push_svc_reg
     bl      rt_hw_trap_pabt
     b       .
 
     .align  5
-    .globl	vector_dabt
+    .globl  vector_dabt
 vector_dabt:
     push_svc_reg
     bl      rt_hw_trap_dabt
     b       .
 
     .align  5
-    .globl	vector_resv
+    .globl  vector_resv
 vector_resv:
     push_svc_reg
     bl      rt_hw_trap_resv
     b       .
+
+#ifdef RT_USING_SMP
+.global set_secondary_cpu_boot_address
+set_secondary_cpu_boot_address:
+    ldr r0, =secondary_cpu_start
+
+    mvn r1, #0 //0xffffffff
+    ldr r2, =0x10000034
+    str r1, [r2]
+    str r0, [r2, #-4]
+    mov pc, lr
+
+.global secondary_cpu_start
+secondary_cpu_start:
+    mrc p15, 0, r1, c1, c0, 1
+    mov r0, #(1<<6)
+    orr r1, r0
+    mcr p15, 0, r1, c1, c0, 1 //enable smp
+
+    mrc p15, 0, r0, c1, c0, 0
+    bic r0, #(1<<13)
+    mcr p15, 0, r0, c1, c0, 0
+
+    cps #Mode_IRQ
+    ldr sp, =irq_stack_2_limit
+
+    cps #Mode_FIQ
+    ldr sp, =irq_stack_2_limit
+
+    cps #Mode_SVC
+    ldr sp, =svc_stack_2_limit
+
+    /* initialize the mmu table and enable mmu */
+    bl rt_hw_mmu_init
+
+    b secondary_cpu_c_start
+#endif
+
+.bss
+.align 2   //align to  2~2=4
+svc_stack_2:
+    .space (1 << 10)
+svc_stack_2_limit:
+
+irq_stack_2:
+    .space (1 << 10)
+irq_stack_2_limit:
+
diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c
index f3b2c26e6d..54628933ff 100644
--- a/libcpu/arm/cortex-a/trap.c
+++ b/libcpu/arm/cortex-a/trap.c
@@ -10,13 +10,11 @@
 
 #include <rtthread.h>
 #include <rthw.h>
-#include <board.h>
+#include <platform.h>
 
 #include "armv7.h"
+#include "interrupt.h"
 
-#include "gic.h"
-
-extern struct rt_thread *rt_current_thread;
 #ifdef RT_USING_FINSH
 extern long list_thread(void);
 #endif
@@ -130,48 +128,52 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
 void rt_hw_trap_irq(void)
 {
     void *param;
+    int ir;
     rt_isr_handler_t isr_func;
     extern struct rt_irq_desc isr_table[];
 
-    // vectNum = RESERVED[31:13] | CPUID[12:10] | INTERRUPT_ID[9:0]
-    // send ack and get ID source
-    uint32_t vectNum = gic_read_irq_ack();
+    ir = rt_hw_interrupt_get_irq();
 
-    // Check that INT_ID isn't 1023 or 1022 (spurious interrupt)
-    if (vectNum & 0x0200)
+    if (ir == 1023)
     {
-        gic_write_end_of_irq(vectNum);  // send end of irq
+        /* Spurious interrupt */
+        return;
     }
-    else
-    {
-        // copy the local value to the global image of CPUID
-        unsigned cpu = (vectNum >> 10) & 0x7;
-        unsigned irq = vectNum & 0x1FF;
 
-        /* skip warning */
-        cpu = cpu;
-
-        // Call the service routine stored in the handlers array. If there isn't
-        // one for this IRQ, then call the default handler.
-        /* get interrupt service routine */
-        isr_func = isr_table[irq].handler;
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
 #ifdef RT_USING_INTERRUPT_INFO
-        isr_table[irq].counter++;
+    isr_table[ir].counter++;
 #endif
-        if (isr_func)
-        {
-            /* Interrupt for myself. */
-            param = isr_table[irq].param;
-            /* turn to interrupt service routine */
-            isr_func(irq, param);
-        }
-
-        // Signal the end of the irq.
-        gic_write_end_of_irq(vectNum);
+    if (isr_func)
+    {
+        /* Interrupt for myself. */
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
     }
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
 }
 
 void rt_hw_trap_fiq(void)
 {
-    /* TODO */
+    void *param;
+    int ir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    ir = rt_hw_interrupt_get_irq();
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+    param = isr_table[ir].param;
+
+    /* turn to interrupt service routine */
+    isr_func(ir, param);
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
 }
+
-- 
cgit v1.3.1


From bd8f0d04232b5725ed8965bf528946906775f8cf Mon Sep 17 00:00:00 2001
From: BernardXiong <bernard.xiong@gmail.com>
Date: Tue, 26 Mar 2019 13:36:01 +0000
Subject: [libcpu] Fix the build directory issue

---
 libcpu/SConscript           | 2 +-
 libcpu/arc/SConscript       | 4 ++--
 libcpu/arm/SConscript       | 8 +++-----
 libcpu/avr32/SConscript     | 2 +-
 libcpu/blackfin/SConscript  | 2 +-
 libcpu/c-sky/SConscript     | 4 ++--
 libcpu/m16c/SConscript      | 2 +-
 libcpu/mips/SConscript      | 4 ++--
 libcpu/nios/SConscript      | 2 +-
 libcpu/ppc/SConscript       | 4 ++--
 libcpu/risc-v/SConscript    | 4 ++--
 libcpu/sim/SConscript       | 2 +-
 libcpu/ti-dsp/SConscript    | 2 +-
 libcpu/unicore32/SConscript | 2 +-
 libcpu/v850/SConscript      | 2 +-
 libcpu/xilinx/SConscript    | 2 +-
 16 files changed, 23 insertions(+), 25 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/SConscript b/libcpu/SConscript
index 774e7f4043..6092707e6d 100644
--- a/libcpu/SConscript
+++ b/libcpu/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 if rtconfig.ARCH in list:
-    group = group + SConscript(os.path.join(cwd, rtconfig.ARCH, 'SConscript'))
+    group = group + SConscript(os.path.join(rtconfig.ARCH, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/arc/SConscript b/libcpu/arc/SConscript
index cbec0b5ec1..3c69b578fa 100644
--- a/libcpu/arc/SConscript
+++ b/libcpu/arc/SConscript
@@ -9,9 +9,9 @@ cwd   = GetCurrentDir()
 group = []
 
 # add common code files
-group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/arm/SConscript b/libcpu/arm/SConscript
index 36a214327b..f6ea13fb91 100644
--- a/libcpu/arm/SConscript
+++ b/libcpu/arm/SConscript
@@ -5,14 +5,12 @@ from building import *
 
 Import('rtconfig')
 
-cwd   = GetCurrentDir()
-group = []
-list  = os.listdir(cwd)
+cwd = GetCurrentDir()
 
 # add common code files
-group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+group = SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/avr32/SConscript b/libcpu/avr32/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/avr32/SConscript
+++ b/libcpu/avr32/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/blackfin/SConscript b/libcpu/blackfin/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/blackfin/SConscript
+++ b/libcpu/blackfin/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/c-sky/SConscript b/libcpu/c-sky/SConscript
index 36a214327b..640e46a4fb 100644
--- a/libcpu/c-sky/SConscript
+++ b/libcpu/c-sky/SConscript
@@ -10,9 +10,9 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/m16c/SConscript b/libcpu/m16c/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/m16c/SConscript
+++ b/libcpu/m16c/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/mips/SConscript b/libcpu/mips/SConscript
index 36a214327b..640e46a4fb 100644
--- a/libcpu/mips/SConscript
+++ b/libcpu/mips/SConscript
@@ -10,9 +10,9 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/nios/SConscript b/libcpu/nios/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/nios/SConscript
+++ b/libcpu/nios/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/ppc/SConscript b/libcpu/ppc/SConscript
index 36a214327b..640e46a4fb 100644
--- a/libcpu/ppc/SConscript
+++ b/libcpu/ppc/SConscript
@@ -10,9 +10,9 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 36a214327b..640e46a4fb 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -10,9 +10,9 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
+group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/sim/SConscript b/libcpu/sim/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/sim/SConscript
+++ b/libcpu/sim/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/ti-dsp/SConscript b/libcpu/ti-dsp/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/ti-dsp/SConscript
+++ b/libcpu/ti-dsp/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/unicore32/SConscript b/libcpu/unicore32/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/unicore32/SConscript
+++ b/libcpu/unicore32/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/v850/SConscript b/libcpu/v850/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/v850/SConscript
+++ b/libcpu/v850/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/xilinx/SConscript b/libcpu/xilinx/SConscript
index ebdd1357ee..4f1441895c 100644
--- a/libcpu/xilinx/SConscript
+++ b/libcpu/xilinx/SConscript
@@ -10,6 +10,6 @@ group = []
 list  = os.listdir(cwd)
 
 # cpu porting code files
-group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
-- 
cgit v1.3.1


From fcb88f70343f9e2dd8e3ba3ab7cba56497ad1415 Mon Sep 17 00:00:00 2001
From: ZYH <lymz@foxmail.com>
Date: Thu, 28 Mar 2019 16:49:43 +0800
Subject: [libcpu][k210]fix stack frame print

---
 libcpu/risc-v/k210/interrupt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c
index 45b437c099..b582599daf 100644
--- a/libcpu/risc-v/k210/interrupt.c
+++ b/libcpu/risc-v/k210/interrupt.c
@@ -270,7 +270,7 @@ struct exception_stack_frame
 
 void print_stack_frame(uintptr_t * sp)
 {
-    struct exception_stack_frame * esf = (struct exception_stack_frame *)sp;
+    struct exception_stack_frame * esf = (struct exception_stack_frame *)(sp+1);
 
     rt_kprintf("\n=================================================================\n");
     rt_kprintf("x1 (ra   : Return address                ) ==> 0x%08x%08x\n", esf->x1 >> 32  , esf->x1 & UINT32_MAX);
-- 
cgit v1.3.1


From fbd40fc5b8b94cf370fdea9a2433991f43e542f6 Mon Sep 17 00:00:00 2001
From: qz721 <295354721@qq.com>
Date: Fri, 29 Mar 2019 20:22:25 +0800
Subject: Add standard rt-thread cache interfaces for arm/cortex-a.

Add cache invalidate and clean interfaces.
Adjust the default cache type of memory to 'WriteBach with WriteAllocate'.
---
 libcpu/arm/cortex-a/cache.c | 94 +++++++++++++++++++++++++++++++++++++++++++++
 libcpu/arm/cortex-a/mmu.h   |  3 +-
 2 files changed, 96 insertions(+), 1 deletion(-)
 create mode 100644 libcpu/arm/cortex-a/cache.c

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c
new file mode 100644
index 0000000000..6d28d9e9f9
--- /dev/null
+++ b/libcpu/arm/cortex-a/cache.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-29 	  quanzhao 	   the first version
+ */
+#include <rthw.h>
+#include <rtdef.h>
+
+rt_inline rt_uint32_t rt_cpu_icache_line_size(void)
+{
+    rt_uint32_t ctr;
+    asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr));
+    return 4 << (ctr & 0xF);
+}
+
+rt_inline rt_uint32_t rt_cpu_dcache_line_size(void)
+{
+    rt_uint32_t ctr;
+    asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr));
+    return 4 << ((ctr >> 16) & 0xF);
+}
+
+void rt_hw_cpu_icache_invalidate(void *addr, int size)
+{
+    rt_uint32_t line_size = rt_cpu_icache_line_size();
+    rt_uint32_t start_addr = (rt_uint32_t)addr;
+    rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
+
+    start_addr &= ~(line_size-1);
+    end_addr &= ~(line_size-1);
+    while (start_addr < end_addr)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr));  /* icimvau */
+        start_addr += line_size;
+    }
+}
+
+void rt_hw_cpu_dcache_invalidate(void *addr, int size)
+{
+    rt_uint32_t line_size = rt_cpu_dcache_line_size();
+    rt_uint32_t start_addr = (rt_uint32_t)addr;
+    rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
+
+    start_addr &= ~(line_size-1);
+    end_addr &= ~(line_size-1);
+    while (start_addr < end_addr)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr));  /* dcimvac */
+        start_addr += line_size;
+    }
+}
+
+void rt_hw_cpu_dcache_clean(void *addr, int size)
+{
+    rt_uint32_t line_size = rt_cpu_dcache_line_size();
+    rt_uint32_t start_addr = (rt_uint32_t)addr;
+    rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
+
+    start_addr &= ~(line_size-1);
+    end_addr &= ~(line_size-1);
+    while (start_addr < end_addr)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */
+        start_addr += line_size;
+    }
+}
+
+void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_INVALIDATE)
+        rt_hw_cpu_icache_invalidate(addr, size);
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_FLUSH)
+        rt_hw_cpu_dcache_clean(addr, size);
+    else if (ops == RT_HW_CACHE_INVALIDATE)
+        rt_hw_cpu_dcache_invalidate(addr, size);
+}
+
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}
diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h
index deec690c69..fbce6df935 100644
--- a/libcpu/arm/cortex-a/mmu.h
+++ b/libcpu/arm/cortex-a/mmu.h
@@ -13,6 +13,7 @@
 #include <rtthread.h>
 
 #define DESC_SEC       (0x2)
+#define MEMWBWA        ((1<<12)|(3<<2))     /* write back, write allocate */
 #define MEMWB          (3<<2)  /* write back, no write allocate */
 #define MEMWT          (2<<2)  /* write through, no write allocate */
 #define SHAREDEVICE    (1<<2)  /* shared device */
@@ -34,7 +35,7 @@
 /* device mapping type */
 #define DEVICE_MEM     (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN)
 /* normal memory mapping type */
-#define NORMAL_MEM     (SHARED|AP_RW|DOMAIN0|MEMWB|DESC_SEC)
+#define NORMAL_MEM     (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)
 
 struct mem_desc
 {
-- 
cgit v1.3.1


From 5d166c389d6c81fbeea3e175100d4922453991ee Mon Sep 17 00:00:00 2001
From: xuzhuoyi <xzy476386434@vip.qq.com>
Date: Sun, 31 Mar 2019 15:44:24 +0800
Subject: [bsp][gd32e230k-start] Add GD32E230K-START BSP port

---
 bsp/gd32e230k-start/.config                        |  288 +++
 bsp/gd32e230k-start/Kconfig                        |   72 +
 .../Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h |  212 ++
 .../CMSIS/GD/GD32E230/Include/system_gd32e230.h    |   58 +
 .../GD/GD32E230/Source/ARM/startup_gd32e230.s      |  256 +++
 .../GD/GD32E230/Source/IAR/startup_gd32e230.s      |  303 +++
 .../CMSIS/GD/GD32E230/Source/system_gd32e230.c     |  371 ++++
 .../Include/gd32e230_adc.h                         |  351 ++++
 .../Include/gd32e230_cmp.h                         |  162 ++
 .../Include/gd32e230_crc.h                         |  120 ++
 .../Include/gd32e230_dbg.h                         |  123 ++
 .../Include/gd32e230_dma.h                         |  264 +++
 .../Include/gd32e230_exti.h                        |  278 +++
 .../Include/gd32e230_fmc.h                         |  272 +++
 .../Include/gd32e230_fwdgt.h                       |  119 ++
 .../Include/gd32e230_gpio.h                        |  388 ++++
 .../Include/gd32e230_i2c.h                         |  389 ++++
 .../Include/gd32e230_misc.h                        |   86 +
 .../Include/gd32e230_pmu.h                         |  146 ++
 .../Include/gd32e230_rcu.h                         |  672 +++++++
 .../Include/gd32e230_rtc.h                         |  561 ++++++
 .../Include/gd32e230_spi.h                         |  424 ++++
 .../Include/gd32e230_syscfg.h                      |  187 ++
 .../Include/gd32e230_timer.h                       |  760 ++++++++
 .../Include/gd32e230_usart.h                       |  614 ++++++
 .../Include/gd32e230_wwdgt.h                       |   88 +
 .../Source/gd32e230_adc.c                          |  844 ++++++++
 .../Source/gd32e230_cmp.c                          |  180 ++
 .../Source/gd32e230_crc.c                          |  206 ++
 .../Source/gd32e230_dbg.c                          |  140 ++
 .../Source/gd32e230_dma.c                          |  562 ++++++
 .../Source/gd32e230_exti.c                         |  254 +++
 .../Source/gd32e230_fmc.c                          |  814 ++++++++
 .../Source/gd32e230_fwdgt.c                        |  252 +++
 .../Source/gd32e230_gpio.c                         |  399 ++++
 .../Source/gd32e230_i2c.c                          |  797 ++++++++
 .../Source/gd32e230_misc.c                         |  142 ++
 .../Source/gd32e230_pmu.c                          |  301 +++
 .../Source/gd32e230_rcu.c                          | 1034 ++++++++++
 .../Source/gd32e230_rtc.c                          |  965 +++++++++
 .../Source/gd32e230_spi.c                          | 1003 ++++++++++
 .../Source/gd32e230_syscfg.c                       |  207 ++
 .../Source/gd32e230_timer.c                        | 2059 ++++++++++++++++++++
 .../Source/gd32e230_usart.c                        | 1318 +++++++++++++
 .../Source/gd32e230_wwdgt.c                        |  148 ++
 bsp/gd32e230k-start/Libraries/SConscript           |   33 +
 bsp/gd32e230k-start/SConscript                     |   14 +
 bsp/gd32e230k-start/SConstruct                     |   39 +
 bsp/gd32e230k-start/applications/SConscript        |   11 +
 bsp/gd32e230k-start/applications/main.c            |   27 +
 bsp/gd32e230k-start/drivers/SConscript             |   33 +
 bsp/gd32e230k-start/drivers/board.c                |   87 +
 bsp/gd32e230k-start/drivers/board.h                |   47 +
 bsp/gd32e230k-start/drivers/drv_gpio.c             |  539 +++++
 bsp/gd32e230k-start/drivers/drv_gpio.h             |   18 +
 bsp/gd32e230k-start/drivers/drv_i2c.c              |  381 ++++
 bsp/gd32e230k-start/drivers/drv_i2c.h              |   29 +
 bsp/gd32e230k-start/drivers/drv_spi.c              |  290 +++
 bsp/gd32e230k-start/drivers/drv_spi.h              |   19 +
 bsp/gd32e230k-start/drivers/drv_usart.c            |  381 ++++
 bsp/gd32e230k-start/drivers/drv_usart.h            |   19 +
 bsp/gd32e230k-start/drivers/gd32e230_libopt.h      |   60 +
 bsp/gd32e230k-start/gd32_rom.icf                   |   40 +
 bsp/gd32e230k-start/gd32_rom.ld                    |  142 ++
 bsp/gd32e230k-start/gd32_rom.sct                   |   15 +
 bsp/gd32e230k-start/project.uvoptx                 | 1301 +++++++++++++
 bsp/gd32e230k-start/project.uvprojx                |  952 +++++++++
 bsp/gd32e230k-start/rtconfig.h                     |  158 ++
 bsp/gd32e230k-start/rtconfig.py                    |  126 ++
 bsp/gd32e230k-start/template.uvoptx                |  185 ++
 bsp/gd32e230k-start/template.uvprojx               |  400 ++++
 libcpu/arm/cortex-m23/SConscript                   |   23 +
 libcpu/arm/cortex-m23/context_gcc.S                |  210 ++
 libcpu/arm/cortex-m23/context_iar.S                |  202 ++
 libcpu/arm/cortex-m23/context_rvds.S               |  207 ++
 libcpu/arm/cortex-m23/cpuport.c                    |  403 ++++
 76 files changed, 25580 insertions(+)
 create mode 100644 bsp/gd32e230k-start/.config
 create mode 100644 bsp/gd32e230k-start/Kconfig
 create mode 100644 bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h
 create mode 100644 bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/system_gd32e230.h
 create mode 100644 bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s
 create mode 100644 bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s
 create mode 100644 bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/system_gd32e230.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_adc.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_cmp.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_crc.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dbg.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dma.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_exti.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fmc.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fwdgt.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_gpio.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_i2c.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_misc.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_pmu.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rcu.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rtc.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_spi.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_syscfg.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_timer.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_usart.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_wwdgt.h
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_adc.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_cmp.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_crc.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dbg.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dma.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_exti.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fmc.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fwdgt.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_gpio.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_i2c.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_misc.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_pmu.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rcu.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rtc.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_spi.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_syscfg.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_timer.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_usart.c
 create mode 100644 bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_wwdgt.c
 create mode 100644 bsp/gd32e230k-start/Libraries/SConscript
 create mode 100644 bsp/gd32e230k-start/SConscript
 create mode 100644 bsp/gd32e230k-start/SConstruct
 create mode 100644 bsp/gd32e230k-start/applications/SConscript
 create mode 100644 bsp/gd32e230k-start/applications/main.c
 create mode 100644 bsp/gd32e230k-start/drivers/SConscript
 create mode 100644 bsp/gd32e230k-start/drivers/board.c
 create mode 100644 bsp/gd32e230k-start/drivers/board.h
 create mode 100644 bsp/gd32e230k-start/drivers/drv_gpio.c
 create mode 100644 bsp/gd32e230k-start/drivers/drv_gpio.h
 create mode 100644 bsp/gd32e230k-start/drivers/drv_i2c.c
 create mode 100644 bsp/gd32e230k-start/drivers/drv_i2c.h
 create mode 100644 bsp/gd32e230k-start/drivers/drv_spi.c
 create mode 100644 bsp/gd32e230k-start/drivers/drv_spi.h
 create mode 100644 bsp/gd32e230k-start/drivers/drv_usart.c
 create mode 100644 bsp/gd32e230k-start/drivers/drv_usart.h
 create mode 100644 bsp/gd32e230k-start/drivers/gd32e230_libopt.h
 create mode 100644 bsp/gd32e230k-start/gd32_rom.icf
 create mode 100644 bsp/gd32e230k-start/gd32_rom.ld
 create mode 100644 bsp/gd32e230k-start/gd32_rom.sct
 create mode 100644 bsp/gd32e230k-start/project.uvoptx
 create mode 100644 bsp/gd32e230k-start/project.uvprojx
 create mode 100644 bsp/gd32e230k-start/rtconfig.h
 create mode 100644 bsp/gd32e230k-start/rtconfig.py
 create mode 100644 bsp/gd32e230k-start/template.uvoptx
 create mode 100644 bsp/gd32e230k-start/template.uvprojx
 create mode 100644 libcpu/arm/cortex-m23/SConscript
 create mode 100644 libcpu/arm/cortex-m23/context_gcc.S
 create mode 100644 libcpu/arm/cortex-m23/context_iar.S
 create mode 100644 libcpu/arm/cortex-m23/context_rvds.S
 create mode 100644 libcpu/arm/cortex-m23/cpuport.c

(limited to 'libcpu')

diff --git a/bsp/gd32e230k-start/.config b/bsp/gd32e230k-start/.config
new file mode 100644
index 0000000000..40cac74cf7
--- /dev/null
+++ b/bsp/gd32e230k-start/.config
@@ -0,0 +1,288 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_DEBUG_INIT=0
+CONFIG_RT_DEBUG_THREAD=0
+CONFIG_RT_USING_HOOK=y
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=4
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+CONFIG_RT_DFS_ELM_USE_LFN_0=y
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
+CONFIG_RT_DFS_ELM_USE_LFN=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_NET is not set
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_USING_I2C_BITOPS is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI_MSD is not set
+CONFIG_RT_USING_SFUD=y
+# CONFIG_RT_SFUD_USING_SFDP is not set
+CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
+# CONFIG_RT_SFUD_DEBUG is not set
+# CONFIG_RT_USING_W25QXX is not set
+# CONFIG_RT_USING_GD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_POSIX is not set
+# CONFIG_HAVE_SYS_SIGNALS is not set
+
+#
+# Network stack
+#
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_LWIP141 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# system packages
+#
+
+#
+# RT-Thread GUI Engine
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_ONENET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_IPERF is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_SAMPLES is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_RT_USING_USART0=y
+CONFIG_RT_USING_USART1=y
+# CONFIG_RT_USING_USART2 is not set
+# CONFIG_RT_USING_UART3 is not set
+# CONFIG_RT_USING_UART4 is not set
+CONFIG_RT_USING_SPI0=y
+CONFIG_RT_USING_SPI1=y
+# CONFIG_RT_USING_SPI2 is not set
+CONFIG_RT_USING_I2C0=y
+# CONFIG_RT_USING_I2C1 is not set
diff --git a/bsp/gd32e230k-start/Kconfig b/bsp/gd32e230k-start/Kconfig
new file mode 100644
index 0000000000..e4706f4d4f
--- /dev/null
+++ b/bsp/gd32e230k-start/Kconfig
@@ -0,0 +1,72 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config RT_USING_USART0
+    bool "Using USART0"
+    select RT_USING_SERIAL
+    default y
+    
+config RT_USING_USART1
+    bool "Using USART1"
+    select RT_USING_SERIAL
+    default n
+
+config RT_USING_USART2
+    bool "Using USART2"
+    select RT_USING_SERIAL
+    default n
+
+config RT_USING_UART3
+    bool "Using UART3"
+    select RT_USING_SERIAL
+    default n
+    
+config RT_USING_UART4
+    bool "Using UART4"
+    select RT_USING_SERIAL
+    default n
+
+config RT_USING_SPI0
+    bool "Using SPI0"
+    select RT_USING_SPI
+    default y 
+
+config RT_USING_SPI1
+    bool "Using SPI1"
+    select RT_USING_SPI
+    default n  
+
+config RT_USING_SPI2
+    bool "Using SPI2"
+    select RT_USING_SPI
+    default n 
+
+config RT_USING_I2C0
+    bool "Using I2C0"
+    select RT_USING_I2C
+    default n 
+
+config RT_USING_I2C1
+    bool "Using I2C1"
+    select RT_USING_I2C
+    default n  
+
+
+
diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h
new file mode 100644
index 0000000000..60838636f7
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h
@@ -0,0 +1,212 @@
+/*!
+    \file    gd32e230.h
+    \brief   general definitions for GD32E230
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_H
+#define GD32E230_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* define GD32E230 */
+#if !defined (GD32E230)
+ #define GD32E230
+#endif /* define GD32E230 */
+#if !defined (GD32E230)
+ #error "Please select the target GD32E230 device used in your application (in gd32e230.h file)"
+#endif /* undefine GD32E230 tip */
+
+/* define value of high speed crystal oscillator (HXTAL) in Hz */
+#if !defined  (HXTAL_VALUE)
+#define HXTAL_VALUE    ((uint32_t)8000000)
+#endif /* high speed crystal oscillator value */
+
+/* define startup timeout value of high speed crystal oscillator (HXTAL) */
+#if !defined  (HXTAL_STARTUP_TIMEOUT)
+#define HXTAL_STARTUP_TIMEOUT   ((uint16_t)0x0800)
+#endif /* high speed crystal oscillator startup timeout */
+
+/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
+#if !defined  (IRC8M_VALUE) 
+#define IRC8M_VALUE  ((uint32_t)8000000)
+#endif /* internal 8MHz RC oscillator value */
+
+/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
+#if !defined  (IRC8M_STARTUP_TIMEOUT)
+#define IRC8M_STARTUP_TIMEOUT   ((uint16_t)0x0500)
+#endif /* internal 8MHz RC oscillator startup timeout */
+
+/* define value of internal RC oscillator for ADC in Hz */
+#if !defined  (IRC28M_VALUE) 
+#define IRC28M_VALUE ((uint32_t)28000000)
+#endif /* IRC28M_VALUE */
+
+#if !defined  (IRC48M_VALUE) 
+#define IRC48M_VALUE ((uint32_t)48000000)
+#endif /* IRC48M_VALUE */
+
+/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
+#if !defined  (IRC40K_VALUE) 
+#define IRC40K_VALUE  ((uint32_t)40000)
+#endif /* internal 40KHz RC oscillator value */
+
+/* define value of low speed crystal oscillator (LXTAL)in Hz */
+#if !defined  (LXTAL_VALUE) 
+#define LXTAL_VALUE  ((uint32_t)32768)
+#endif /* low speed crystal oscillator value */
+
+/* GD32E1x0 firmware library version number V1.0 */
+#define __GD32E230_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version     */
+#define __GD32E230_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version     */
+#define __GD32E230_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version     */
+#define __GD32E230_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __GD32E230_STDPERIPH_VERSION        ((__GD32E230_STDPERIPH_VERSION_MAIN << 24)\
+                                            |(__GD32E230_STDPERIPH_VERSION_SUB1 << 16)\
+                                            |(__GD32E230_STDPERIPH_VERSION_SUB2 << 8)\
+                                            |(__GD32E230_STDPERIPH_VERSION_RC))
+
+/* configuration of the Cortex-M23 processor and core peripherals                                        */
+#define __CM23_REV                0x0100U   /*!< Core revision r1p0                                      */
+#define __SAUREGION_PRESENT       0U        /*!< SAU regions are not present                             */
+#define __MPU_PRESENT             0U        /*!< MPU is present                                          */
+#define __VTOR_PRESENT            1U        /*!< VTOR is present                                         */
+#define __NVIC_PRIO_BITS          2U        /*!< Number of Bits used for Priority Levels                 */
+#define __Vendor_SysTickConfig    0U        /*!< Set to 1 if different SysTick Config is used            */
+
+/* define interrupt number */
+typedef enum IRQn
+{
+    /* Cortex-M23 processor exceptions numbers */
+    NonMaskableInt_IRQn          = -14,    /*!< non maskable interrupt                                   */
+    HardFault_IRQn               = -13,    /*!< hardfault interrupt                                      */
+
+    SVCall_IRQn                  = -5,     /*!< sv call interrupt                                        */
+
+    PendSV_IRQn                  = -2,     /*!< pend sv interrupt                                        */
+    SysTick_IRQn                 = -1,     /*!< system tick interrupt                                    */
+    /* interruput numbers */
+    WWDGT_IRQn                   = 0,      /*!< window watchdog timer interrupt                          */
+    LVD_IRQn                     = 1,      /*!< LVD through EXTI line detect interrupt                   */
+    RTC_IRQn                     = 2,      /*!< RTC through EXTI line interrupt                          */
+    FMC_IRQn                     = 3,      /*!< FMC interrupt                                            */
+    RCU_IRQn                     = 4,      /*!< RCU interrupt                                            */
+    EXTI0_1_IRQn                 = 5,      /*!< EXTI line 0 and 1 interrupts                             */
+    EXTI2_3_IRQn                 = 6,      /*!< EXTI line 2 and 3 interrupts                             */
+    EXTI4_15_IRQn                = 7,      /*!< EXTI line 4 to 15 interrupts                             */
+    DMA_Channel0_IRQn            = 9,      /*!< DMA channel 0 interrupt                                  */
+    DMA_Channel1_2_IRQn          = 10,     /*!< DMA channel 1 and channel 2 interrupts                   */
+    DMA_Channel3_4_IRQn          = 11,     /*!< DMA channel 3 and channel 4 interrupts                   */
+    ADC_CMP_IRQn                 = 12,     /*!< ADC, CMP interrupts                            */
+    TIMER0_BRK_UP_TRG_COM_IRQn   = 13,     /*!< TIMER0 break, update, trigger and commutation interrupts */
+    TIMER0_Channel_IRQn          = 14,     /*!< TIMER0 channel capture compare interrupts                */
+    TIMER2_IRQn                  = 16,     /*!< TIMER2 interrupt                                         */
+    TIMER5_IRQn                  = 17,     /*!< TIMER5 interrupt                                         */
+    TIMER13_IRQn                 = 19,     /*!< TIMER13 interrupt                                        */
+    TIMER14_IRQn                 = 20,     /*!< TIMER14 interrupt                                        */
+    TIMER15_IRQn                 = 21,     /*!< TIMER15 interrupt                                        */
+    TIMER16_IRQn                 = 22,     /*!< TIMER16 interrupt                                        */
+    I2C0_EV_IRQn                 = 23,     /*!< I2C0 event interrupt                                     */
+    I2C1_EV_IRQn                 = 24,     /*!< I2C1 event interrupt                                     */
+    SPI0_IRQn                    = 25,     /*!< SPI0 interrupt                                           */
+    SPI1_IRQn                    = 26,     /*!< SPI1 interrupt                                           */
+    USART0_IRQn                  = 27,     /*!< USART0 interrupt                                         */
+    USART1_IRQn                  = 28,     /*!< USART1 interrupt                                         */
+    I2C0_ER_IRQn                 = 32,     /*!< I2C0 error interrupt                                     */
+    I2C1_ER_IRQn                 = 34,     /*!< I2C1 error interrupt                                     */
+} IRQn_Type;
+
+/* includes */
+#include "core_cm23.h"
+#include "system_gd32e230.h"
+#include <stdint.h>
+
+/* enum definitions */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
+typedef enum {RESET = 0, SET = !RESET} FlagStatus;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
+
+/* bit operations */
+#define REG32(addr)                  (*(volatile uint32_t *)(uint32_t)(addr))
+#define REG16(addr)                  (*(volatile uint16_t *)(uint32_t)(addr))
+#define REG8(addr)                   (*(volatile uint8_t *)(uint32_t)(addr))
+#define BIT(x)                       ((uint32_t)((uint32_t)0x01U<<(x)))
+#define BITS(start, end)             ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 
+#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
+
+/* main flash and SRAM memory map */
+#define FLASH_BASE            ((uint32_t)0x08000000U)       /*!< main FLASH base address          */
+#define SRAM_BASE             ((uint32_t)0x20000000U)       /*!< SRAM base address                */
+/* SRAM and peripheral base bit-band region */
+#define SRAM_BB_BASE          ((uint32_t)0x22000000U)       /*!< SRAM bit-band base address       */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U)       /*!< peripheral bit-band base address */
+/* peripheral memory map */
+#define APB1_BUS_BASE         ((uint32_t)0x40000000U)       /*!< apb1 base address                */
+#define APB2_BUS_BASE         ((uint32_t)0x40010000U)       /*!< apb2 base address                */
+#define AHB1_BUS_BASE         ((uint32_t)0x40020000U)       /*!< ahb1 base address                */
+#define AHB2_BUS_BASE         ((uint32_t)0x48000000U)       /*!< ahb2 base address                */
+/* advanced peripheral bus 1 memory map */
+#define TIMER_BASE            (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address               */
+#define RTC_BASE              (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address                 */
+#define WWDGT_BASE            (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address               */
+#define FWDGT_BASE            (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address               */
+#define SPI_BASE              (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address                 */
+#define USART_BASE            (APB1_BUS_BASE + 0x00004400U) /*!< USART base address               */
+#define I2C_BASE              (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address                 */
+#define PMU_BASE              (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address                 */
+/* advanced peripheral bus 2 memory map */
+#define SYSCFG_BASE           (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address              */
+#define CMP_BASE              (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address                 */
+#define EXTI_BASE             (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address                */
+#define ADC_BASE              (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address                 */
+/* advanced high performance bus 1 memory map */
+#define DMA_BASE              (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address                 */
+#define DMA_CHANNEL_BASE      (DMA_BASE + 0x00000008U)      /*!< DMA channel base address         */
+#define RCU_BASE              (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address                 */
+#define FMC_BASE              (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address                 */
+#define CRC_BASE              (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address                 */
+/* advanced high performance bus 2 memory map */
+#define GPIO_BASE             (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address                */
+/* option byte and debug memory map */
+#define OB_BASE               ((uint32_t)0x1FFFF800U)       /*!< OB base address                  */
+#define DBG_BASE              ((uint32_t)0x40015800U)       /*!< DBG base address                 */
+
+#include "gd32e230_libopt.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GD32E230_H */
diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/system_gd32e230.h b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/system_gd32e230.h
new file mode 100644
index 0000000000..45441bd546
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/system_gd32e230.h
@@ -0,0 +1,58 @@
+/*!
+    \file  system_gd32e230.h
+    \brief CMSIS Cortex-M23 Device Peripheral Access Layer Header File for
+           GD32E230 Device Series
+*/
+
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#ifndef SYSTEM_GD32E230_H
+#define SYSTEM_GD32E230_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* system clock frequency (core clock) */
+extern uint32_t SystemCoreClock;
+
+/* function declarations */
+/* initialize the system and update the SystemCoreClock variable */
+extern void SystemInit (void);
+/* update the SystemCoreClock with current core clock retrieved from cpu registers */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_GD32E230_H */
diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s
new file mode 100644
index 0000000000..8b001a390f
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s
@@ -0,0 +1,256 @@
+;/*!
+;    \file    startup_gd32e230.s
+;    \brief   start up file
+;
+;    \version 2018-6-19, V1.0.0, firmware for GD32E230
+;*/
+;
+;/*
+;    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+;    All rights reserved.
+;
+;    Redistribution and use in source and binary forms, with or without modification, 
+;are permitted provided that the following conditions are met:
+;
+;    1. Redistributions of source code must retain the above copyright notice, this 
+;       list of conditions and the following disclaimer.
+;    2. Redistributions in binary form must reproduce the above copyright notice, 
+;       this list of conditions and the following disclaimer in the documentation 
+;       and/or other materials provided with the distribution.
+;    3. Neither the name of the copyright holder nor the names of its contributors 
+;       may be used to endorse or promote products derived from this software without 
+;       specific prior written permission.
+;
+;    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+;OF SUCH DAMAGE.
+;*/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+;               /* reset Vector Mapped to at Address 0 */
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+;               /* external interrupts handler */
+                DCD     WWDGT_IRQHandler                  ; 16:Window Watchdog Timer
+                DCD     LVD_IRQHandler                    ; 17:LVD through EXTI Line detect
+                DCD     RTC_IRQHandler                    ; 18:RTC through EXTI Line
+                DCD     FMC_IRQHandler                    ; 19:FMC
+                DCD     RCU_IRQHandler                    ; 20:RCU
+                DCD     EXTI0_1_IRQHandler                ; 21:EXTI Line 0 and EXTI Line 1
+                DCD     EXTI2_3_IRQHandler                ; 22:EXTI Line 2 and EXTI Line 3
+                DCD     EXTI4_15_IRQHandler               ; 23:EXTI Line 4 to EXTI Line 15
+                DCD     0                                 ; Reserved
+                DCD     DMA_Channel0_IRQHandler           ; 25:DMA Channel 0 
+                DCD     DMA_Channel1_2_IRQHandler         ; 26:DMA Channel 1 and DMA Channel 2
+                DCD     DMA_Channel3_4_IRQHandler         ; 27:DMA Channel 3 and DMA Channel 4
+                DCD     ADC_CMP_IRQHandler                ; 28:ADC and Comparator
+                DCD     TIMER0_BRK_UP_TRG_COM_IRQHandler  ; 29:TIMER0 Break,Update,Trigger and Commutation
+                DCD     TIMER0_Channel_IRQHandler         ; 30:TIMER0 Channel Capture Compare
+                DCD     0                                 ; Reserved
+                DCD     TIMER2_IRQHandler                 ; 32:TIMER2
+                DCD     TIMER5_IRQHandler                 ; 33:TIMER5
+                DCD     0                                 ; Reserved
+                DCD     TIMER13_IRQHandler                ; 35:TIMER13
+                DCD     TIMER14_IRQHandler                ; 36:TIMER14
+                DCD     TIMER15_IRQHandler                ; 37:TIMER15
+                DCD     TIMER16_IRQHandler                ; 38:TIMER16
+                DCD     I2C0_EV_IRQHandler                ; 39:I2C0 Event
+                DCD     I2C1_EV_IRQHandler                ; 40:I2C1 Event
+                DCD     SPI0_IRQHandler                   ; 41:SPI0
+                DCD     SPI1_IRQHandler                   ; 42:SPI1
+                DCD     USART0_IRQHandler                 ; 43:USART0
+                DCD     USART1_IRQHandler                 ; 44:USART1
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C0_ER_IRQHandler                ; 48:I2C0 Error
+                DCD     0                                 ; Reserved
+                DCD     I2C1_ER_IRQHandler                ; 50:I2C1 Error
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler   PROC
+                EXPORT  Reset_Handler                     [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler                       [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                 [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler                       [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+;               /* external interrupts handler */
+                EXPORT  WWDGT_IRQHandler                  [WEAK]
+                EXPORT  LVD_IRQHandler                    [WEAK]
+                EXPORT  RTC_IRQHandler                    [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  RCU_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_1_IRQHandler                [WEAK]
+                EXPORT  EXTI2_3_IRQHandler                [WEAK]
+                EXPORT  EXTI4_15_IRQHandler               [WEAK]
+                EXPORT  DMA_Channel0_IRQHandler           [WEAK]
+                EXPORT  DMA_Channel1_2_IRQHandler         [WEAK]
+                EXPORT  DMA_Channel3_4_IRQHandler         [WEAK]
+                EXPORT  ADC_CMP_IRQHandler                [WEAK]
+                EXPORT  TIMER0_BRK_UP_TRG_COM_IRQHandler  [WEAK]
+                EXPORT  TIMER0_Channel_IRQHandler         [WEAK]
+                EXPORT  TIMER2_IRQHandler                 [WEAK]
+                EXPORT  TIMER5_IRQHandler                 [WEAK]
+                EXPORT  TIMER13_IRQHandler                [WEAK]
+                EXPORT  TIMER14_IRQHandler                [WEAK]
+                EXPORT  TIMER15_IRQHandler                [WEAK]
+                EXPORT  TIMER16_IRQHandler                [WEAK]
+                EXPORT  I2C0_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  SPI0_IRQHandler                   [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  USART0_IRQHandler                 [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  I2C0_ER_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+RTC_IRQHandler
+FMC_IRQHandler
+RCU_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+DMA_Channel0_IRQHandler
+DMA_Channel1_2_IRQHandler
+DMA_Channel3_4_IRQHandler
+ADC_CMP_IRQHandler
+TIMER0_BRK_UP_TRG_COM_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER2_IRQHandler
+TIMER5_IRQHandler
+TIMER13_IRQHandler
+TIMER14_IRQHandler
+TIMER15_IRQHandler
+TIMER16_IRQHandler
+I2C0_EV_IRQHandler
+I2C1_EV_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_ER_IRQHandler
+
+                B       .
+                ENDP
+
+                ALIGN
+
+; user Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END
diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s
new file mode 100644
index 0000000000..a491356ce0
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s
@@ -0,0 +1,303 @@
+;/*!
+;    \file    startup_gd32e230.s
+;    \brief   start up file
+;
+;    \version 2018-06-19, V1.0.0, firmware for GD32E230
+;*/
+;
+;/*
+;    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+;    All rights reserved.
+;
+;    Redistribution and use in source and binary forms, with or without modification, 
+;are permitted provided that the following conditions are met:
+;
+;    1. Redistributions of source code must retain the above copyright notice, this 
+;       list of conditions and the following disclaimer.
+;    2. Redistributions in binary form must reproduce the above copyright notice, 
+;       this list of conditions and the following disclaimer in the documentation 
+;       and/or other materials provided with the distribution.
+;    3. Neither the name of the copyright holder nor the names of its contributors 
+;       may be used to endorse or promote products derived from this software without 
+;       specific prior written permission.
+;
+;    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+;OF SUCH DAMAGE.
+;*/
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)                         ; top of stack
+        DCD     Reset_Handler                       ; Vector Number 1,Reset Handler
+
+        DCD     NMI_Handler                         ; Vector Number 2,NMI Handler
+        DCD     HardFault_Handler                   ; Vector Number 3,Hard Fault Handler
+        DCD     MemManage_Handler                   ; Vector Number 4,MPU Fault Handler
+        DCD     BusFault_Handler                    ; Vector Number 5,Bus Fault Handler
+        DCD     UsageFault_Handler                  ; Vector Number 6,Usage Fault Handler
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     SVC_Handler                         ; Vector Number 11,SVCall Handler
+        DCD     DebugMon_Handler                    ; Vector Number 12,Debug Monitor Handler
+        DCD     0                                   ; Reserved
+        DCD     PendSV_Handler                      ; Vector Number 14,PendSV Handler
+        DCD     SysTick_Handler                     ; Vector Number 15,SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDGT_IRQHandler                    ; 16:Window Watchdog Timer
+        DCD     LVD_IRQHandler                      ; 17:LVD through EXTI Line detect
+        DCD     RTC_IRQHandler                      ; 18:RTC through EXTI Line
+        DCD     FMC_IRQHandler                      ; 19:FMC
+        DCD     RCU_IRQHandler                      ; 20:RCU
+        DCD     EXTI0_1_IRQHandler                  ; 21:EXTI Line 0 and EXTI Line 1
+        DCD     EXTI2_3_IRQHandler                  ; 22:EXTI Line 2 and EXTI Line 3
+        DCD     EXTI4_15_IRQHandler                 ; 23:EXTI Line 4 to EXTI Line 15
+        DCD     0                                   ; Reserved
+        DCD     DMA_Channel0_IRQHandler             ; 25:DMA Channel 0 
+        DCD     DMA_Channel1_2_IRQHandler           ; 26:DMA Channel 1 and DMA Channel 2
+        DCD     DMA_Channel3_4_IRQHandler           ; 27:DMA Channel 3 and DMA Channel 4
+        DCD     ADC_CMP_IRQHandler                  ; 28:ADC and Comparator
+        DCD     TIMER0_BRK_UP_TRG_COM_IRQHandler    ; 29:TIMER0 Break,Update,Trigger and Commutation
+        DCD     TIMER0_Channel_IRQHandler           ; 30:TIMER0 Channel Capture Compare
+        DCD     0                                   ; Reserved
+        DCD     TIMER2_IRQHandler                   ; 32:TIMER2
+        DCD     TIMER5_IRQHandler                   ; 33:TIMER5
+        DCD     0                                   ; Reserved
+        DCD     TIMER13_IRQHandler                  ; 35:TIMER13
+        DCD     TIMER14_IRQHandler                  ; 36:TIMER14
+        DCD     TIMER15_IRQHandler                  ; 37:TIMER15
+        DCD     TIMER16_IRQHandler                  ; 38:TIMER16
+        DCD     I2C0_EV_IRQHandler                  ; 39:I2C0 Event
+        DCD     I2C1_EV_IRQHandler                  ; 40:I2C1 Event
+        DCD     SPI0_IRQHandler                     ; 41:SPI0
+        DCD     SPI1_IRQHandler                     ; 42:SPI1
+        DCD     USART0_IRQHandler                   ; 43:USART0
+        DCD     USART1_IRQHandler                   ; 44:USART1
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     I2C0_ER_IRQHandler                  ; 48:I2C0 Error
+        DCD     0                                   ; Reserved
+        DCD     I2C1_ER_IRQHandler                  ; 50:I2C1 Error
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+       
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+       
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+       
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+        
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+        
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+        
+        PUBWEAK WWDGT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+        B WWDGT_IRQHandler
+        
+        PUBWEAK LVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+        B LVD_IRQHandler
+        
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+        
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+        
+        PUBWEAK RCU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_IRQHandler
+        B RCU_IRQHandler
+        
+        PUBWEAK EXTI0_1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_1_IRQHandler
+        B EXTI0_1_IRQHandler
+        
+        PUBWEAK EXTI2_3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_3_IRQHandler
+        B EXTI2_3_IRQHandler
+        
+        PUBWEAK EXTI4_15_IRQHandler                  
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_15_IRQHandler                  
+        B EXTI4_15_IRQHandler                  
+        
+        PUBWEAK DMA_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA_Channel0_IRQHandler
+        B DMA_Channel0_IRQHandler
+        
+        PUBWEAK DMA_Channel1_2_IRQHandler          
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA_Channel1_2_IRQHandler          
+        B DMA_Channel1_2_IRQHandler          
+        
+        PUBWEAK DMA_Channel3_4_IRQHandler          
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA_Channel3_4_IRQHandler          
+        B DMA_Channel3_4_IRQHandler                 
+        
+        PUBWEAK ADC_CMP_IRQHandler                    
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_CMP_IRQHandler                    
+        B ADC_CMP_IRQHandler                    
+        
+        PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler                
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_UP_TRG_COM_IRQHandler                
+        B TIMER0_BRK_UP_TRG_COM_IRQHandler                
+        
+        PUBWEAK TIMER0_Channel_IRQHandler               
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler               
+        B TIMER0_Channel_IRQHandler               
+        
+        PUBWEAK TIMER2_IRQHandler               
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler               
+        B TIMER2_IRQHandler               
+      
+        PUBWEAK TIMER5_IRQHandler               
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_IRQHandler               
+        B TIMER5_IRQHandler               
+        
+        PUBWEAK TIMER13_IRQHandler                
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER13_IRQHandler                
+        B TIMER13_IRQHandler                
+        
+        PUBWEAK TIMER14_IRQHandler    
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER14_IRQHandler    
+        B TIMER14_IRQHandler    
+        
+        PUBWEAK TIMER15_IRQHandler   
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER15_IRQHandler   
+        B TIMER15_IRQHandler   
+        
+        PUBWEAK TIMER16_IRQHandler 
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER16_IRQHandler 
+        B TIMER16_IRQHandler 
+        
+        PUBWEAK I2C0_EV_IRQHandler         
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler         
+        B I2C0_EV_IRQHandler         
+        
+        PUBWEAK I2C1_EV_IRQHandler                 
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler                 
+        B I2C1_EV_IRQHandler                 
+        
+        PUBWEAK SPI0_IRQHandler                 
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+        B SPI0_IRQHandler                 
+
+        PUBWEAK SPI1_IRQHandler                 
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler                 
+        B SPI1_IRQHandler
+
+        PUBWEAK USART0_IRQHandler                 
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler                 
+        B USART0_IRQHandler                 
+
+        PUBWEAK USART1_IRQHandler                 
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler                 
+        B USART1_IRQHandler                 
+        
+        PUBWEAK I2C0_ER_IRQHandler              
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler              
+        B I2C0_ER_IRQHandler              
+
+        PUBWEAK I2C1_ER_IRQHandler             
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler             
+        B I2C1_ER_IRQHandler                      
+        END
\ No newline at end of file
diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/system_gd32e230.c b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/system_gd32e230.c
new file mode 100644
index 0000000000..a4768d181f
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/system_gd32e230.c
@@ -0,0 +1,371 @@
+/*!
+    \file  system_gd32e230.c
+    \brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for
+           GD32E1x0 Device Series
+*/
+
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#include "gd32e230.h"
+
+/* system frequency define */
+#define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
+#define __HXTAL           (HXTAL_VALUE)            /* high speed crystal oscillator frequency */
+#define __SYS_OSC_CLK     (__IRC8M)                /* main oscillator frequency */
+
+#define VECT_TAB_OFFSET  (uint32_t)0x00            /* vector table base offset */
+
+/* select a system clock by uncommenting the following line */
+//#define __SYSTEM_CLOCK_8M_HXTAL              (__HXTAL)
+//#define __SYSTEM_CLOCK_8M_IRC8M              (__IRC8M)
+#define __SYSTEM_CLOCK_72M_PLL_HXTAL         (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2    (uint32_t)(72000000)
+
+#define SEL_IRC8M       0x00
+#define SEL_HXTAL       0x01
+#define SEL_PLL         0x02
+
+/* set the system clock frequency and declare the system clock configuration function */
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
+static void system_clock_8m_hxtal(void);
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
+static void system_clock_72m_hxtal(void);
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
+static void system_clock_72m_irc8m(void);
+
+#else
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
+static void system_clock_8m_irc8m(void);
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+
+/* configure the system clock */
+static void system_clock_config(void);
+
+/*!
+    \brief      setup the microcontroller system, initialize the system
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SystemInit (void)
+{
+    /* enable IRC8M */
+    RCU_CTL0 |= RCU_CTL0_IRC8MEN;
+    while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
+    }
+    /* reset RCU */
+    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
+                  RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+    RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
+    RCU_CFG1 &= ~(RCU_CFG1_PREDV);
+    RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
+    RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
+    RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
+    RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
+    RCU_INT = 0x00000000U;
+
+    /* configure system clock */
+    system_clock_config();
+    
+#ifdef VECT_TAB_SRAM
+    nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
+#else
+    nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
+#endif
+}
+
+/*!
+    \brief      configure the system clock
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_config(void)
+{
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+    system_clock_8m_hxtal();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+    system_clock_72m_hxtal();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+    system_clock_72m_irc8m();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
+    system_clock_72m_irc48m();
+#else
+    system_clock_8m_irc8m();
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+}
+
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+/*!
+    \brief      configure the system clock to 8M by HXTAL
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_8m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL0 |= RCU_CTL0_HXTALEN;
+    
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
+    }
+    while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));    
+    /* if fail */
+    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
+        while(1){
+        }
+    }
+    
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+    
+    /* select HXTAL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
+    
+    /* wait until HXTAL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects HXTAL as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL0 |= RCU_CTL0_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
+    }
+    while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+    /* if fail */
+    if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
+        while(1){
+        }
+    }
+    
+    FMC_WS &= ~FMC_WS_WSCNT;
+    FMC_WS |= WS_WSCNT_2;
+    
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+
+    /* PLL = HXTAL * 9 = 72 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
+
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_irc8m(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable IRC8M */
+    RCU_CTL0 |= RCU_CTL0_IRC8MEN;
+
+    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
+    }
+    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
+        while(1){
+        }
+    }
+
+    FMC_WS &= ~FMC_WS_WSCNT;
+    FMC_WS |= WS_WSCNT_2;
+    
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+    /* PLL = (IRC8M/2) * 18 = 72 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
+    RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
+    
+    /* enable PLL */
+    RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#else
+/*!
+    \brief      configure the system clock to 8M by IRC8M
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_8m_irc8m(void)
+{
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+    
+    /* select IRC8M as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
+    
+    /* wait until IRC8M is selected as system clock */
+    while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
+    }
+}
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+
+/*!
+    \brief      update the SystemCoreClock with current core clock retrieved from cpu registers
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SystemCoreClockUpdate (void)
+{
+    uint32_t sws = 0U;
+    uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
+    /* exponent of AHB clock divider */
+    const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+    sws = GET_BITS(RCU_CFG0, 2, 3);
+    switch(sws){
+    /* IRC8M is selected as CK_SYS */
+    case SEL_IRC8M:
+        SystemCoreClock = IRC8M_VALUE;
+        break;
+    /* HXTAL is selected as CK_SYS */
+    case SEL_HXTAL:
+        SystemCoreClock = HXTAL_VALUE;
+        break;
+    /* PLL is selected as CK_SYS */
+    case SEL_PLL:
+        /* get the value of PLLMF[3:0] */
+        pllmf = GET_BITS(RCU_CFG0, 18, 21);
+        pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
+        /* high 16 bits */
+        if(1U == pllmf4){
+            pllmf += 17U;
+        }else if(15U == pllmf){
+            pllmf = 16U;
+        }else{
+            pllmf += 2U;
+        }
+        
+        /* PLL clock source selection, HXTAL or IRC8M/2 */
+        pllsel = GET_BITS(RCU_CFG0, 16, 16);
+        if(0U != pllsel){
+            prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
+            SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
+        }else{
+            SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
+        }
+        break;
+    /* IRC8M is selected as CK_SYS */
+    default:
+        SystemCoreClock = IRC8M_VALUE;
+        break;
+    }
+    /* calculate AHB clock frequency */
+    idx = GET_BITS(RCU_CFG0, 4, 7);
+    clk_exp = ahb_exp[idx];
+    SystemCoreClock >>= clk_exp;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_adc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_adc.h
new file mode 100644
index 0000000000..2ffbec390e
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_adc.h
@@ -0,0 +1,351 @@
+/*!
+    \file  gd32e230_adc.h
+    \brief definitions for the ADC
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_ADC_H
+#define GD32E230_ADC_H
+
+#include "gd32e230.h"
+
+/* ADC definitions */
+#define ADC                              ADC_BASE
+
+/* registers definitions */
+#define ADC_STAT                         REG32(ADC + 0x00U)               /*!< ADC status register */
+#define ADC_CTL0                         REG32(ADC + 0x04U)               /*!< ADC control register 0 */
+#define ADC_CTL1                         REG32(ADC + 0x08U)               /*!< ADC control register 1 */
+#define ADC_SAMPT0                       REG32(ADC + 0x0CU)               /*!< ADC sampling time register 0 */
+#define ADC_SAMPT1                       REG32(ADC + 0x10U)               /*!< ADC sampling time register 1 */
+#define ADC_IOFF0                        REG32(ADC + 0x14U)               /*!< ADC inserted channel data offset register 0 */
+#define ADC_IOFF1                        REG32(ADC + 0x18U)               /*!< ADC inserted channel data offset register 1 */
+#define ADC_IOFF2                        REG32(ADC + 0x1CU)               /*!< ADC inserted channel data offset register 2 */
+#define ADC_IOFF3                        REG32(ADC + 0x20U)               /*!< ADC inserted channel data offset register 3 */
+#define ADC_WDHT                         REG32(ADC + 0x24U)               /*!< ADC watchdog high threshold register */
+#define ADC_WDLT                         REG32(ADC + 0x28U)               /*!< ADC watchdog low threshold register */
+#define ADC_RSQ0                         REG32(ADC + 0x2CU)               /*!< ADC regular sequence register 0 */
+#define ADC_RSQ1                         REG32(ADC + 0x30U)               /*!< ADC regular sequence register 1 */
+#define ADC_RSQ2                         REG32(ADC + 0x34U)               /*!< ADC regular sequence register 2 */
+#define ADC_ISQ                          REG32(ADC + 0x38U)               /*!< ADC inserted sequence register */
+#define ADC_IDATA0                       REG32(ADC + 0x3CU)               /*!< ADC inserted data register 0 */
+#define ADC_IDATA1                       REG32(ADC + 0x40U)               /*!< ADC inserted data register 1 */
+#define ADC_IDATA2                       REG32(ADC + 0x44U)               /*!< ADC inserted data register 2 */
+#define ADC_IDATA3                       REG32(ADC + 0x48U)               /*!< ADC inserted data register 3 */
+#define ADC_RDATA                        REG32(ADC + 0x4CU)               /*!< ADC regular data register */
+#define ADC_OVSAMPCTL                    REG32(ADC + 0x80U)               /*!< ADC oversampling control register */
+
+/* bits definitions */
+/* ADC_STAT */
+#define ADC_STAT_WDE                     BIT(0)                           /*!< analog watchdog event flag */
+#define ADC_STAT_EOC                     BIT(1)                           /*!< end of conversion flag */
+#define ADC_STAT_EOIC                    BIT(2)                           /*!< inserted channel end of conversion flag */
+#define ADC_STAT_STIC                    BIT(3)                           /*!< inserted channel start flag */
+#define ADC_STAT_STRC                    BIT(4)                           /*!< regular channel start flag */
+
+/* ADC_CTL0 */
+#define ADC_CTL0_WDCHSEL                 BITS(0,4)                        /*!< analog watchdog channel select bits */
+#define ADC_CTL0_EOCIE                   BIT(5)                           /*!< interrupt enable for EOC */
+#define ADC_CTL0_WDEIE                   BIT(6)                           /*!< analog watchdog interrupt enable */
+#define ADC_CTL0_EOICIE                  BIT(7)                           /*!< interrupt enable for inserted channels */
+#define ADC_CTL0_SM                      BIT(8)                           /*!< scan mode */
+#define ADC_CTL0_WDSC                    BIT(9)                           /*!< when in scan mode, analog watchdog is effective on a single channel */
+#define ADC_CTL0_ICA                     BIT(10)                          /*!< automatic inserted group conversion */
+#define ADC_CTL0_DISRC                   BIT(11)                          /*!< discontinuous mode on regular channels */
+#define ADC_CTL0_DISIC                   BIT(12)                          /*!< discontinuous mode on inserted channels */
+#define ADC_CTL0_DISNUM                  BITS(13,15)                      /*!< discontinuous mode channel count */
+#define ADC_CTL0_IWDEN                   BIT(22)                          /*!< analog watchdog enable on inserted channels */
+#define ADC_CTL0_RWDEN                   BIT(23)                          /*!< analog watchdog enable on regular channels */
+#define ADC_CTL0_DRES                    BITS(24,25)                      /*!< ADC data resolution */
+
+/* ADC_CTL1 */
+#define ADC_CTL1_ADCON                   BIT(0)                           /*!< ADC converter on */
+#define ADC_CTL1_CTN                     BIT(1)                           /*!< continuous conversion */
+#define ADC_CTL1_CLB                     BIT(2)                           /*!< ADC calibration */
+#define ADC_CTL1_RSTCLB                  BIT(3)                           /*!< reset calibration */
+#define ADC_CTL1_DMA                     BIT(8)                           /*!< direct memory access mode */
+#define ADC_CTL1_DAL                     BIT(11)                          /*!< data alignment */
+#define ADC_CTL1_ETSIC                   BITS(12,14)                      /*!< external trigger select for inserted channel */
+#define ADC_CTL1_ETEIC                   BIT(15)                          /*!< external trigger enable for inserted channel */
+#define ADC_CTL1_ETSRC                   BITS(17,19)                      /*!< external trigger select for regular channel */
+#define ADC_CTL1_ETERC                   BIT(20)                          /*!< external trigger enable for regular channel */
+#define ADC_CTL1_SWICST                  BIT(21)                          /*!< start on inserted channel */
+#define ADC_CTL1_SWRCST                  BIT(22)                          /*!< start on regular channel */
+#define ADC_CTL1_TSVREN                  BIT(23)                          /*!< enable channel 16 and 17 */
+
+/* ADC_SAMPTx x=0,1 */
+#define ADC_SAMPTX_SPTN                  BITS(0,2)                        /*!< channel n(n=0..9,16 and 17) sample time selection */
+
+/* ADC_IOFFx x=0..3 */
+#define ADC_IOFFX_IOFF                   BITS(0,11)                       /*!< data offset for inserted channel x */
+
+/* ADC_WDHT */
+#define ADC_WDHT_WDHT                    BITS(0,11)                       /*!< analog watchdog high threshold */
+
+/* ADC_WDLT */
+#define ADC_WDLT_WDLT                    BITS(0,11)                       /*!< analog watchdog low threshold */
+
+/* ADC_RSQx x=0..2 */
+#define ADC_RSQX_RSQN                    BITS(0,4)                        /*!< n conversion in regular sequence */
+#define ADC_RSQ0_RL                      BITS(20,23)                      /*!< regular channel sequence length */
+
+/* ADC_ISQ */
+#define ADC_ISQ_ISQN                     BITS(0,4)                        /*!< n conversion in regular sequence */
+#define ADC_ISQ_IL                       BITS(20,21)                      /*!< inserted sequence length */
+
+/* ADC_IDATAx x=0..3*/
+#define ADC_IDATAX_IDATAN                BITS(0,15)                       /*!< inserted channel x conversion data  */
+
+/* ADC_RDATA */
+#define ADC_RDATA_RDATA                  BITS(0,15)                       /*!< regular channel data */
+
+/* ADC_OVSAMPCTL */
+#define ADC_OVSAMPCTL_OVSEN              BIT(0)                           /*!< oversampling enable */
+#define ADC_OVSAMPCTL_OVSR               BITS(2,4)                        /*!< oversampling ratio */
+#define ADC_OVSAMPCTL_OVSS               BITS(5,8)                        /*!< oversampling shift */
+#define ADC_OVSAMPCTL_TOVS               BIT(9)                           /*!< triggered oversampling */
+
+/* constants definitions */
+/* ADC flag definitions */
+#define ADC_FLAG_WDE                     ADC_STAT_WDE                                /*!< analog watchdog event flag */
+#define ADC_FLAG_EOC                     ADC_STAT_EOC                                /*!< end of group conversion flag */
+#define ADC_FLAG_EOIC                    ADC_STAT_EOIC                               /*!< end of inserted channel group conversion flag */
+#define ADC_FLAG_STIC                    ADC_STAT_STIC                               /*!< start flag of inserted channel group */
+#define ADC_FLAG_STRC                    ADC_STAT_STRC                               /*!< start flag of regular channel group */
+
+/* adc_ctl0 register value */
+#define CTL0_DISNUM(regval)              (BITS(13,15) & ((uint32_t)(regval) << 13))  /*!< number of conversions in discontinuous mode */
+
+/* ADC special function */
+#define ADC_SCAN_MODE                    ADC_CTL0_SM                                 /*!< scan mode */
+#define ADC_INSERTED_CHANNEL_AUTO        ADC_CTL0_ICA                                /*!< inserted channel group convert automatically */
+#define ADC_CONTINUOUS_MODE              ADC_CTL1_CTN                                /*!< continuous mode */
+
+/* ADC data alignment */
+#define ADC_DATAALIGN_RIGHT              ((uint32_t)0x00000000U)                     /*!< right alignment */
+#define ADC_DATAALIGN_LEFT               ADC_CTL1_DAL                                /*!< left alignment */
+
+/* external trigger select for regular  channel */
+#define CTL1_ETSRC(regval)               (BITS(17,19) & ((uint32_t)(regval) << 17))  
+#define ADC_EXTTRIG_REGULAR_T0_CH0       CTL1_ETSRC(0)                               /*!< TIMER0 CH0 event select */
+#define ADC_EXTTRIG_REGULAR_T0_CH1       CTL1_ETSRC(1)                               /*!< TIMER0 CH1 event select */
+#define ADC_EXTTRIG_REGULAR_T0_CH2       CTL1_ETSRC(2)                               /*!< TIMER0 CH2 event select */
+#define ADC_EXTTRIG_REGULAR_T2_TRGO      CTL1_ETSRC(4)                               /*!< TIMER2 TRGO event select */
+#define ADC_EXTTRIG_REGULAR_T14_CH0      CTL1_ETSRC(5)                               /*!< TIMER14 CH0 event select */
+#define ADC_EXTTRIG_REGULAR_EXTI_11      CTL1_ETSRC(6)                               /*!< external interrupt line 11 */
+#define ADC_EXTTRIG_REGULAR_NONE         CTL1_ETSRC(7)                               /*!< software trigger */
+
+/* external trigger select for inserted channel */
+#define CTL1_ETSIC(regval)               (BITS(12,14) & ((uint32_t)(regval) << 12))  
+#define ADC_EXTTRIG_INSERTED_T0_TRGO     CTL1_ETSIC(0)                               /*!< TIMER0 TRGO event select */
+#define ADC_EXTTRIG_INSERTED_T0_CH3      CTL1_ETSIC(1)                               /*!< TIMER0 CH3 event select */
+#define ADC_EXTTRIG_INSERTED_T2_CH3      CTL1_ETSIC(4)                               /*!< TIMER2 CH3 event select */
+#define ADC_EXTTRIG_INSERTED_T14_TRGO    CTL1_ETSIC(5)                               /*!< TIMER14 TRGO event select */
+#define ADC_EXTTRIG_INSERTED_EXTI_15     CTL1_ETSIC(6)                               /*!< external interrupt line 15 */
+#define ADC_EXTTRIG_INSERTED_NONE        CTL1_ETSIC(7)                               /*!< software trigger */
+
+/* adc_samptx register value */
+#define SAMPTX_SPT(regval)               (BITS(0,2) & ((uint32_t)(regval) << 0))     
+#define ADC_SAMPLETIME_1POINT5           SAMPTX_SPT(0)                               /*!< 1.5 sampling cycles */
+#define ADC_SAMPLETIME_7POINT5           SAMPTX_SPT(1)                               /*!< 7.5 sampling cycles */
+#define ADC_SAMPLETIME_13POINT5          SAMPTX_SPT(2)                               /*!< 13.5 sampling cycles */
+#define ADC_SAMPLETIME_28POINT5          SAMPTX_SPT(3)                               /*!< 28.5 sampling cycles */
+#define ADC_SAMPLETIME_41POINT5          SAMPTX_SPT(4)                               /*!< 41.5 sampling cycles */
+#define ADC_SAMPLETIME_55POINT5          SAMPTX_SPT(5)                               /*!< 55.5 sampling cycles */
+#define ADC_SAMPLETIME_71POINT5          SAMPTX_SPT(6)                               /*!< 71.5 sampling cycles */
+#define ADC_SAMPLETIME_239POINT5         SAMPTX_SPT(7)                               /*!< 239.5 sampling cycles */
+
+/* ADC data offset for inserted channel x*/
+#define IOFFX_IOFF(regval)               (BITS(0,11) & ((uint32_t)(regval) << 0))    
+
+/* ADC analog watchdog high threshold  */
+#define WDHT_WDHT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))    
+
+/* ADC analog watchdog low  threshold */
+#define WDLT_WDLT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))    
+
+/* ADC regular channel group length */
+#define RSQ0_RL(regval)                  (BITS(20,23) & ((uint32_t)(regval) << 20))  
+
+/* ADC inserted channel group length */
+#define ISQ_IL(regval)                   (BITS(20,21) & ((uint32_t)(regval) << 20))  
+
+/* ADC resolution definitions */
+#define CTL0_DRES(regval)                (BITS(24,25) & ((regval) << 24))            /*!< ADC resolution */
+#define ADC_RESOLUTION_12B               CTL0_DRES(0)                                /*!< 12-bit ADC resolution */
+#define ADC_RESOLUTION_10B               CTL0_DRES(1)                                /*!< 10-bit ADC resolution */
+#define ADC_RESOLUTION_8B                CTL0_DRES(2)                                /*!< 8-bit ADC resolution */
+#define ADC_RESOLUTION_6B                CTL0_DRES(3)                                /*!< 6-bit ADC resolution */
+
+/* ADC oversampling shift */
+#define OVSAMPCTL_OVSS(regval)           (BITS(5,8) & ((uint32_t)(regval) << 5))     
+#define ADC_OVERSAMPLING_SHIFT_NONE      OVSAMPCTL_OVSS(0)                           /*!< no oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_1B        OVSAMPCTL_OVSS(1)                           /*!< 1-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_2B        OVSAMPCTL_OVSS(2)                           /*!< 2-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_3B        OVSAMPCTL_OVSS(3)                           /*!< 3-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_4B        OVSAMPCTL_OVSS(4)                           /*!< 4-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_5B        OVSAMPCTL_OVSS(5)                           /*!< 5-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_6B        OVSAMPCTL_OVSS(6)                           /*!< 6-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_7B        OVSAMPCTL_OVSS(7)                           /*!< 7-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_8B        OVSAMPCTL_OVSS(8)                           /*!< 8-bit oversampling shift */
+
+/* ADC oversampling ratio */
+#define OVSAMPCTL_OVSR(regval)           (BITS(2,4) & ((uint32_t)(regval) << 2))     
+#define ADC_OVERSAMPLING_RATIO_MUL2      OVSAMPCTL_OVSR(0)                           /*!< oversampling ratio multiple 2 */
+#define ADC_OVERSAMPLING_RATIO_MUL4      OVSAMPCTL_OVSR(1)                           /*!< oversampling ratio multiple 4 */
+#define ADC_OVERSAMPLING_RATIO_MUL8      OVSAMPCTL_OVSR(2)                           /*!< oversampling ratio multiple 8 */
+#define ADC_OVERSAMPLING_RATIO_MUL16     OVSAMPCTL_OVSR(3)                           /*!< oversampling ratio multiple 16 */
+#define ADC_OVERSAMPLING_RATIO_MUL32     OVSAMPCTL_OVSR(4)                           /*!< oversampling ratio multiple 32 */
+#define ADC_OVERSAMPLING_RATIO_MUL64     OVSAMPCTL_OVSR(5)                           /*!< oversampling ratio multiple 64 */
+#define ADC_OVERSAMPLING_RATIO_MUL128    OVSAMPCTL_OVSR(6)                           /*!< oversampling ratio multiple 128 */
+#define ADC_OVERSAMPLING_RATIO_MUL256    OVSAMPCTL_OVSR(7)                           /*!< oversampling ratio multiple 256 */
+
+/* ADC triggered oversampling */
+#define ADC_OVERSAMPLING_ALL_CONVERT     0U                                          /*!< all oversampled conversions for a channel are done consecutively after a trigger */
+#define ADC_OVERSAMPLING_ONE_CONVERT     1U                                          /*!< each oversampled conversion for a channel needs a trigger */
+
+/* ADC channel group definitions */
+#define ADC_REGULAR_CHANNEL              ((uint8_t)0x01U)                            /*!< ADC regular channel group */
+#define ADC_INSERTED_CHANNEL             ((uint8_t)0x02U)                            /*!< ADC inserted channel group */
+#define ADC_REGULAR_INSERTED_CHANNEL     ((uint8_t)0x03U)                            /*!< both regular and inserted channel group */
+#define ADC_CHANNEL_DISCON_DISABLE       ((uint8_t)0x04U)                            /*!< disable discontinuous mode of regular & inserted channel */
+
+/* ADC inserted channel definitions */
+#define ADC_INSERTED_CHANNEL_0           ((uint8_t)0x00U)                            /*!< ADC inserted channel 0 */
+#define ADC_INSERTED_CHANNEL_1           ((uint8_t)0x01U)                            /*!< ADC inserted channel 1 */
+#define ADC_INSERTED_CHANNEL_2           ((uint8_t)0x02U)                            /*!< ADC inserted channel 2 */
+#define ADC_INSERTED_CHANNEL_3           ((uint8_t)0x03U)                            /*!< ADC inserted channel 3 */
+
+/* ADC channel definitions */
+#define ADC_CHANNEL_0                    ((uint8_t)0x00U)                            /*!< ADC channel 0 */
+#define ADC_CHANNEL_1                    ((uint8_t)0x01U)                            /*!< ADC channel 1 */
+#define ADC_CHANNEL_2                    ((uint8_t)0x02U)                            /*!< ADC channel 2 */
+#define ADC_CHANNEL_3                    ((uint8_t)0x03U)                            /*!< ADC channel 3 */
+#define ADC_CHANNEL_4                    ((uint8_t)0x04U)                            /*!< ADC channel 4 */
+#define ADC_CHANNEL_5                    ((uint8_t)0x05U)                            /*!< ADC channel 5 */
+#define ADC_CHANNEL_6                    ((uint8_t)0x06U)                            /*!< ADC channel 6 */
+#define ADC_CHANNEL_7                    ((uint8_t)0x07U)                            /*!< ADC channel 7 */
+#define ADC_CHANNEL_8                    ((uint8_t)0x08U)                            /*!< ADC channel 8 */
+#define ADC_CHANNEL_9                    ((uint8_t)0x09U)                            /*!< ADC channel 9 */
+#define ADC_CHANNEL_16                   ((uint8_t)0x10U)                            /*!< ADC channel 16 */
+#define ADC_CHANNEL_17                   ((uint8_t)0x11U)                            /*!< ADC channel 17 */
+
+/* ADC interrupt definitions */
+#define ADC_INT_WDE                      ADC_STAT_WDE                                /*!< analog watchdog event interrupt */
+#define ADC_INT_EOC                      ADC_STAT_EOC                                /*!< end of group conversion interrupt */
+#define ADC_INT_EOIC                     ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt */
+
+/* ADC interrupt flag */
+#define ADC_INT_FLAG_WDE                 ADC_STAT_WDE                                /*!< analog watchdog event interrupt flag */
+#define ADC_INT_FLAG_EOC                 ADC_STAT_EOC                                /*!< end of group conversion interrupt flag */
+#define ADC_INT_FLAG_EOIC                ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt flag */
+
+/* function declarations */
+/* reset ADC */
+void adc_deinit(void);
+/* enable ADC interface */
+void adc_enable(void);
+/* disable ADC interface */
+void adc_disable(void);
+
+/* ADC calibration and reset calibration */
+void adc_calibration_enable(void);
+/* enable DMA request */
+void adc_dma_mode_enable(void);
+/* disable DMA request */
+void adc_dma_mode_disable(void);
+
+/* enable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_enable(void);
+/* disable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_disable(void);
+
+/* configure ADC discontinuous mode */
+void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
+/* configure ADC special function */
+void adc_special_function_config(uint32_t function, ControlStatus newvalue);
+
+/* configure ADC data alignment */
+void adc_data_alignment_config(uint32_t data_alignment);
+/* configure the length of regular channel group or inserted channel group */
+void adc_channel_length_config(uint8_t channel_group, uint32_t length);
+/* configure ADC regular channel */
+void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
+/* configure ADC inserted channel */
+void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
+/* configure ADC inserted channel offset */
+void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
+/* enable ADC external trigger */
+void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
+/* configure ADC external trigger source */
+void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
+/* enable ADC software trigger */
+void adc_software_trigger_enable(uint8_t channel_group);
+
+/* read ADC regular group data register */
+uint16_t adc_regular_data_read(void);
+/* read ADC inserted group data register */
+uint16_t adc_inserted_data_read(uint8_t inserted_channel);
+
+/* get the ADC flag bits */
+FlagStatus adc_flag_get(uint32_t flag);
+/* clear the ADC flag bits */
+void adc_flag_clear(uint32_t flag);
+/* get the ADC interrupt bits */
+FlagStatus adc_interrupt_flag_get(uint32_t flag);
+/* clear the ADC flag */
+void adc_interrupt_flag_clear(uint32_t flag);
+/* enable ADC interrupt */
+void adc_interrupt_enable(uint32_t interrupt);
+/* disable ADC interrupt */
+void adc_interrupt_disable(uint32_t interrupt);
+
+/* configure ADC analog watchdog single channel */
+void adc_watchdog_single_channel_enable(uint8_t channel);
+/* configure ADC analog watchdog group channel */
+void adc_watchdog_group_channel_enable(uint8_t channel_group);
+/* disable ADC analog watchdog */
+void adc_watchdog_disable(void);
+/* configure ADC analog watchdog threshold */
+void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
+
+/* configure ADC resolution */
+void adc_resolution_config(uint32_t resolution);
+/* configure ADC oversample mode */
+void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
+/* enable ADC oversample mode */
+void adc_oversample_mode_enable(void);
+/* disable ADC oversample mode */
+void adc_oversample_mode_disable(void);
+
+#endif /* GD32E230_ADC_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_cmp.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_cmp.h
new file mode 100644
index 0000000000..aa9d8a9b2c
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_cmp.h
@@ -0,0 +1,162 @@
+/*!
+    \file  gd32e230_cmp.h
+    \brief definitions for the CMP
+
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_CMP_H
+#define GD32E230_CMP_H
+
+#include "gd32e230.h"
+
+/* CMP definitions */
+#define CMP                                      CMP_BASE                       /*!< CMP base address */  
+
+/* registers definitions */
+#define CMP_CS                                   REG32((CMP) + 0x00U)           /*!< CMP control and status register */
+
+/* CMP_CS bits definitions */
+#define CMP_CS_CMPEN                             BIT(0)                         /*!< CMP enable  */
+#define CMP_CS_CMPSW                             BIT(1)                         /*!< CMP switch */
+#define CMP_CS_CMPM                              BITS(2,3)                      /*!< CMP mode */
+#define CMP_CS_CMPMSEL                           BITS(4,6)                      /*!< COMP_M input selection */
+#define CMP_CS_CMPOSEL                           BITS(8,10)                     /*!< CMP output selection */
+#define CMP_CS_CMPPL                             BIT(11)                        /*!< polarity of CMP output */
+#define CMP_CS_CMPHST                            BITS(12,13)                    /*!< CMP hysteresis */
+#define CMP_CS_CMPO                              BIT(14)                        /*!< CMP output */
+#define CMP_CS_CMPLK                             BIT(15)                        /*!< CMP lock */
+
+/* consts definitions */
+/* operating mode */
+typedef enum{
+    CMP_HIGHSPEED = 0,                                                          /*!< high speed mode */
+    CMP_MIDDLESPEED,                                                            /*!< medium speed mode */
+    CMP_LOWSPEED,                                                               /*!< low speed mode */
+    CMP_VERYLOWSPEED                                                            /*!< very-low speed mode */
+}operating_mode_enum;
+
+/* inverting input */
+typedef enum{
+    CMP_1_4VREFINT = 0,                                                         /*!< VREFINT /4 input */
+    CMP_1_2VREFINT,                                                             /*!< VREFINT /2 input */
+    CMP_3_4VREFINT,                                                             /*!< VREFINT *3/4 input */
+    CMP_VREFINT,                                                                /*!< VREFINT input */
+    CMP_PA4,                                                                    /*!< PA4 input */
+    CMP_PA5,                                                                    /*!< PA5 input */
+    CMP_PA0,                                                                    /*!< PA0 input */
+    CMP_PA2                                                                     /*!< PA2 input */
+}inverting_input_enum;
+
+/* hysteresis */
+typedef enum{
+    CMP_HYSTERESIS_NO = 0,                                                      /*!< output no hysteresis */
+    CMP_HYSTERESIS_LOW,                                                         /*!< output low hysteresis */
+    CMP_HYSTERESIS_MIDDLE,                                                      /*!< output middle hysteresis */
+    CMP_HYSTERESIS_HIGH                                                         /*!< output high hysteresis */
+}cmp_hysteresis_enum;
+
+/* output */  
+typedef enum{
+    CMP_OUTPUT_NONE = 0x0U,                                                     /*!< output no selection */
+    CMP_OUTPUT_TIMER0BKIN = 0x1U,                                               /*!< TIMER 0 break input */
+    CMP_OUTPUT_TIMER0IC0 = 0x2U,                                                /*!< TIMER 0 channel0 input capture */
+    CMP_OUTPUT_TIMER0OCPRECLR = 0x3U,                                           /*!< TIMER 0 OCPRE_CLR input */
+    CMP_OUTPUT_TIMER2IC0 = 0x06U,                                               /*!< TIMER 2 channel0 input capture */
+    CMP_OUTPUT_TIMER2OCPRECLR = 0x7U                                            /*!< TIMER 2 OCPRE_CLR input */
+}cmp_output_enum;
+
+/* CMP mode */
+#define CS_CMPM(regval)                         (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define CS_CMPM_HIGHSPEED                       CS_CMPM(0)                      /*!< CMP mode high speed */
+#define CS_CMPM_MIDDLESPEED                     CS_CMPM(1)                      /*!< CMP mode middle speed */
+#define CS_CMPM_LOWSPEED                        CS_CMPM(2)                      /*!< CMP mode low speed */
+#define CS_CMPM_VERYLOWSPEED                    CS_CMPM(3)                      /*!< CMP mode very low speed */
+
+/* comparator inverting input */
+#define CS_CMPMSEL(regval)                      (BITS(4,6) & ((uint32_t)(regval) << 4))
+#define CS_CMPMSEL_1_4VREFINT                   CS_CMPMSEL(0)                   /*!< CMP inverting input 1/4 Vrefint */
+#define CS_CMPMSEL_1_2VREFINT                   CS_CMPMSEL(1)                   /*!< CMP inverting input 1/2 Vrefint */
+#define CS_CMPMSEL_3_4VREFINT                   CS_CMPMSEL(2)                   /*!< CMP inverting input 3/4 Vrefint */
+#define CS_CMPMSEL_VREFINT                      CS_CMPMSEL(3)                   /*!< CMP inverting input Vrefint */
+#define CS_CMPMSEL_PA4                          CS_CMPMSEL(4)                   /*!< CMP inverting input PA4*/
+#define CS_CMPMSEL_PA5                          CS_CMPMSEL(5)                   /*!< CMP inverting input PA5*/
+#define CS_CMPMSEL_PA0                          CS_CMPMSEL(6)                   /*!< CMP inverting input PA0*/
+#define CS_CMPMSEL_PA2                          CS_CMPMSEL(7)                   /*!< CMP inverting input PA2*/
+
+/* CMP output */
+#define CS_CMPOSEL(regval)                      (BITS(8,10) & ((uint32_t)(regval) << 8))
+#define CS_CMPOSEL_OUTPUT_NONE                  CS_CMPOSEL(0)                   /*!< CMP output none  */
+#define CS_CMPOSEL_OUTPUT_TIMER0BKIN            CS_CMPOSEL(1)                   /*!< CMP output TIMER 0 break input */
+#define CS_CMPOSEL_OUTPUT_TIMER0IC0             CS_CMPOSEL(2)                   /*!< CMP output TIMER 0 channel 0 input capture */
+#define CS_CMPOSEL_OUTPUT_TIMER0OCPRECLR        CS_CMPOSEL(3)                   /*!< CMP output TIMER 0 ocpreclear input */ 
+#define CS_CMPOSEL_OUTPUT_TIMER2IC0             CS_CMPOSEL(6)                   /*!< CMP output TIMER 2 channle 0 input capture */
+#define CS_CMPOSEL_OUTPUT_TIMER2OCPRECLR        CS_CMPOSEL(7)                   /*!< CMP output TIMER 2 ocpreclear input */
+
+/* CMP hysteresis */
+#define CS_CMPHST(regval)                       (BITS(12,13) & ((uint32_t)(regval) << 12))
+#define CS_CMPHST_HYSTERESIS_NO                 CS_CMPHST(0)                    /*!< CMP output no hysteresis */
+#define CS_CMPHST_HYSTERESIS_LOW                CS_CMPHST(1)                    /*!< CMP output low hysteresis */
+#define CS_CMPHST_HYSTERESIS_MIDDLE             CS_CMPHST(2)                    /*!< CMP output middle hysteresis */
+#define CS_CMPHST_HYSTERESIS_HIGH               CS_CMPHST(3)                    /*!< CMP output high hysteresis */
+
+/* CMP output level */
+#define CMP_OUTPUTLEVEL_HIGH                     ((uint32_t)0x00000001)         /*!< comparator output high */
+#define CMP_OUTPUTLEVEL_LOW                      ((uint32_t)0x00000000)         /*!< comparator output low */
+
+/* output polarity of comparator */
+#define CMP_OUTPUT_POLARITY_INVERTED             ((uint32_t)0x00000001)         /*!< output is inverted */
+#define CMP_OUTPUT_POLARITY_NOINVERTED           ((uint32_t)0x00000000)         /*!< output is not inverted */
+
+/* function declarations */
+
+/* initialization functions */
+/* CMP deinit */
+void cmp_deinit(void);
+/* CMP mode init */
+void cmp_mode_init(operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis);
+/* CMP output init */
+void cmp_output_init(cmp_output_enum output_slection, uint32_t output_polarity);
+/* enable CMP */
+void cmp_enable(void);
+/* disable CMP */
+void cmp_disable(void);
+/* enable CMP switch */
+void cmp_switch_enable(void);
+/* disable CMP switch */
+void cmp_switch_disable(void);
+/* get output level */
+uint32_t cmp_output_level_get(void);
+/* lock the CMP */
+void cmp_lock_enable(void);
+
+#endif /* GD32E230_CMP_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_crc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_crc.h
new file mode 100644
index 0000000000..619ce47970
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_crc.h
@@ -0,0 +1,120 @@
+/*!
+    \file    gd32e230_crc.h
+    \brief   definitions for the CRC
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_CRC_H
+#define GD32E230_CRC_H
+
+#include "gd32e230.h"
+
+/* CRC definitions */
+#define CRC                            CRC_BASE
+
+/* registers definitions */
+#define CRC_DATA                       REG32((CRC) + 0x00U)            /*!< CRC data register */
+#define CRC_FDATA                      REG32((CRC) + 0x04U)            /*!< CRC free data register */
+#define CRC_CTL                        REG32((CRC) + 0x08U)            /*!< CRC control register */
+#define CRC_IDATA                      REG32((CRC) + 0x10U)            /*!< CRC initialization data register */
+#define CRC_POLY                       REG32((CRC) + 0x14U)            /*!< CRC polynomial register */
+
+/* bits definitions */
+/* CRC_DATA */
+#define CRC_DATA_DATA                  BITS(0,31)                      /*!< CRC data bits */
+
+/* CRC_FDATA */
+#define CRC_FDATA_FDATA                BITS(0,7)                       /*!< CRC free data bits */
+
+/* CRC_CTL */
+#define CRC_CTL_RST                    BIT(0)                          /*!< CRC reset bit */
+#define CRC_CTL_PS                     BITS(3,4)                       /*!< size of polynomial function bits */
+#define CRC_CTL_REV_I                  BITS(5,6)                       /*!< input data reverse function bits */
+#define CRC_CTL_REV_O                  BIT(7)                          /*!< output data reverse function bit */
+
+/* CRC_INIT */
+#define CRC_IDATA_IDATA                BITS(0,31)                      /*!< CRC initialization data bits */
+
+/* CRC_POLY */
+#define CRC_POLY_POLY                  BITS(0,31)                      /*!< CRC polynomial value bits */
+
+/* constants definitions */
+/* size of polynomial function */
+#define CTL_PS(regval)                 (BITS(3, 4) & ((regval) << 3))
+#define CRC_CTL_PS_32                  CTL_PS(0)                       /*!< 32-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_16                  CTL_PS(1)                       /*!< 16-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_8                   CTL_PS(2)                       /*!< 8-bit polynomial for CRC calculation */
+#define CRC_CTL_PS_7                   CTL_PS(3)                       /*!< 7-bit polynomial for CRC calculation */
+
+/* input data reverse function */
+#define CTL_REV_I(regval)              (BITS(5, 6) & ((regval) << 5))
+#define CRC_INPUT_DATA_NOT             CTL_REV_I(0)                    /*!< input data not reverse */
+#define CRC_INPUT_DATA_BYTE            CTL_REV_I(1)                    /*!< input data reversed by byte type */
+#define CRC_INPUT_DATA_HALFWORD        CTL_REV_I(2)                    /*!< input data reversed by half-word type */
+#define CRC_INPUT_DATA_WORD            CTL_REV_I(3)                    /*!< input data reversed by word type */
+
+/* function declarations */
+/* deinit CRC calculation unit */
+void crc_deinit(void);
+
+/* enable the reverse operation of output data */
+void crc_reverse_output_data_enable(void);
+/* disable the reverse operation of output data */
+void crc_reverse_output_data_disable(void);
+
+/* reset data register to the value of initializaiton data register */
+void crc_data_register_reset(void);
+/* read the data register  */
+uint32_t crc_data_register_read(void);
+
+/* read the free data register */
+uint8_t crc_free_data_register_read(void);
+/* write the free data register */
+void crc_free_data_register_write(uint8_t free_data);
+
+/* write the initial value register */
+void crc_init_data_register_write(uint32_t init_data);
+/* configure the CRC input data function */
+void crc_input_data_reverse_config(uint32_t data_reverse);
+
+/* configure the CRC size of polynomial function */
+void crc_polynomial_size_set(uint32_t poly_size);
+/* configure the CRC polynomial value function */
+void crc_polynomial_set(uint32_t poly);
+
+/* CRC calculate a 32-bit data */
+uint32_t crc_single_data_calculate(uint32_t sdata);
+/* CRC calculate a 32-bit data array */
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
+
+#endif /* GD32E230_CRC_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dbg.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dbg.h
new file mode 100644
index 0000000000..4a07da903e
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dbg.h
@@ -0,0 +1,123 @@
+/*!
+    \file    gd32e230_dbg.h
+    \brief   definitions for the DBG
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_DBG_H
+#define GD32E230_DBG_H
+
+#include "gd32e230.h"
+
+/* DBG definitions */
+#define DBG                      DBG_BASE
+
+/* registers definitions */
+#define DBG_ID                   REG32(DBG + 0x00U)      /*!< DBG_ID code register */
+#define DBG_CTL0                 REG32(DBG + 0x04U)      /*!< DBG control register 0 */
+#define DBG_CTL1                 REG32(DBG + 0x08U)      /*!< DBG control register 1 */
+
+/* bits definitions */
+/* DBG_ID */
+#define DBG_ID_ID_CODE           BITS(0,31)             /*!< DBG ID code values */
+
+/* DBG_CTL0 */
+#define DBG_CTL0_SLP_HOLD        BIT(0)                 /*!< keep debugger connection during sleep mode */
+#define DBG_CTL0_DSLP_HOLD       BIT(1)                 /*!< keep debugger connection during deepsleep mode */
+#define DBG_CTL0_STB_HOLD        BIT(2)                 /*!< keep debugger connection during standby mode */
+#define DBG_CTL0_FWDGT_HOLD      BIT(8)                 /*!< debug FWDGT kept when core is halted */
+#define DBG_CTL0_WWDGT_HOLD      BIT(9)                 /*!< debug WWDGT kept when core is halted */
+#define DBG_CTL0_TIMER0_HOLD     BIT(10)                /*!< TIMER0 counter kept when core is halted */
+#define DBG_CTL0_TIMER2_HOLD     BIT(12)                /*!< TIMER2 counter kept when core is halted */
+#define DBG_CTL0_I2C0_HOLD       BIT(15)                /*!< hold I2C0 smbus when core is halted */
+#define DBG_CTL0_I2C1_HOLD       BIT(16)                /*!< hold I2C1 smbus when core is halted */
+#define DBG_CTL0_TIMER5_HOLD     BIT(19)                /*!< hold TIMER5 counter when core is halted */
+#define DBG_CTL0_TIMER13_HOLD    BIT(27)                /*!< hold TIMER13 counter when core is halted */
+
+/* DBG_CTL1 */
+#define DBG_CTL1_RTC_HOLD        BIT(10)                /*!< hold RTC calendar and wakeup counter when core is halted */
+#define DBG_CTL1_TIMER14_HOLD    BIT(16)                /*!< hold TIMER14 counter when core is halted */
+#define DBG_CTL1_TIMER15_HOLD    BIT(17)                /*!< hold TIMER15 counter when core is halted */
+#define DBG_CTL1_TIMER16_HOLD    BIT(18)                /*!< hold TIMER16 counter when core is halted */
+
+/* constants definitions */
+#define DBG_LOW_POWER_SLEEP      DBG_CTL0_SLP_HOLD      /*!< keep debugger connection during sleep mode */
+#define DBG_LOW_POWER_DEEPSLEEP  DBG_CTL0_DSLP_HOLD     /*!< keep debugger connection during deepsleep mode */
+#define DBG_LOW_POWER_STANDBY    DBG_CTL0_STB_HOLD      /*!< keep debugger connection during standby mode */
+
+/* define the peripheral debug hold bit position and its register index offset */
+#define DBG_REGIDX_BIT(regidx, bitpos)      (((regidx) << 6) | (bitpos))
+#define DBG_REG_VAL(periph)                 (REG32(DBG + ((uint32_t)(periph) >> 6)))
+#define DBG_BIT_POS(val)                    ((uint32_t)(val) & 0x1FU)
+
+/* register index */
+enum dbg_reg_idx
+{
+    DBG_IDX_CTL0  = 0x04U, 
+    DBG_IDX_CTL1  = 0x08U, 
+};
+
+/* peripherals hold bit */
+typedef enum
+{
+    DBG_FWDGT_HOLD          = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U),              /*!< FWDGT hold bit */
+    DBG_WWDGT_HOLD          = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U),              /*!< WWDGT hold bit */
+    DBG_TIMER0_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U),             /*!< TIMER0 hold bit */
+    DBG_TIMER2_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U),             /*!< TIMER2 hold bit */
+    DBG_TIMER5_HOLD         = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U),             /*!< TIMER5 hold bit */
+    DBG_TIMER13_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U),             /*!< TIMER13 hold bit */
+    DBG_TIMER14_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U),             /*!< TIMER14 hold bit */
+    DBG_TIMER15_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U),             /*!< TIMER15 hold bit */
+    DBG_TIMER16_HOLD        = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U),             /*!< TIMER16 hold bit */
+    DBG_I2C0_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U),             /*!< I2C0 hold bit */
+    DBG_I2C1_HOLD           = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U),             /*!< I2C1 hold bit */
+    DBG_RTC_HOLD            = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U),             /*!< RTC hold bit */
+}dbg_periph_enum;
+
+/* function declarations */
+/* deinitialize the DBG */
+void dbg_deinit(void);
+/* read DBG_ID code register */
+uint32_t dbg_id_get(void);
+
+/* enable low power behavior when the MCU is in debug mode */
+void dbg_low_power_enable(uint32_t dbg_low_power);
+/* disable low power behavior when the MCU is in debug mode */
+void dbg_low_power_disable(uint32_t dbg_low_power);
+
+/* enable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_enable(dbg_periph_enum dbg_periph);
+/* disable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_disable(dbg_periph_enum dbg_periph);
+
+#endif /* GD32E230_DBG_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dma.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dma.h
new file mode 100644
index 0000000000..2205e1bdce
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dma.h
@@ -0,0 +1,264 @@
+/*!
+    \file  gd32e230_dma.h
+    \brief definitions for the DMA
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_DMA_H
+#define GD32E230_DMA_H
+
+#include "gd32e230.h"
+
+/* DMA definitions */
+#define DMA                               DMA_BASE              /*!< DMA base address */
+
+/* registers definitions */
+#define DMA_INTF                          REG32(DMA + 0x00U)    /*!< DMA interrupt flag register */
+#define DMA_INTC                          REG32(DMA + 0x04U)    /*!< DMA interrupt flag clear register */
+#define DMA_CH0CTL                        REG32(DMA + 0x08U)    /*!< DMA channel 0 control register */
+#define DMA_CH0CNT                        REG32(DMA + 0x0CU)    /*!< DMA channel 0 counter register */
+#define DMA_CH0PADDR                      REG32(DMA + 0x10U)    /*!< DMA channel 0 peripheral base address register */
+#define DMA_CH0MADDR                      REG32(DMA + 0x14U)    /*!< DMA channel 0 memory base address register */
+#define DMA_CH1CTL                        REG32(DMA + 0x1CU)    /*!< DMA channel 1 control register */
+#define DMA_CH1CNT                        REG32(DMA + 0x20U)    /*!< DMA channel 1 counter register */
+#define DMA_CH1PADDR                      REG32(DMA + 0x24U)    /*!< DMA channel 1 peripheral base address register */
+#define DMA_CH1MADDR                      REG32(DMA + 0x28U)    /*!< DMA channel 1 memory base address register */
+#define DMA_CH2CTL                        REG32(DMA + 0x30U)    /*!< DMA channel 2 control register */
+#define DMA_CH2CNT                        REG32(DMA + 0x34U)    /*!< DMA channel 2 counter register */
+#define DMA_CH2PADDR                      REG32(DMA + 0x38U)    /*!< DMA channel 2 peripheral base address register */
+#define DMA_CH2MADDR                      REG32(DMA + 0x3CU)    /*!< DMA channel 2 memory base address register */
+#define DMA_CH3CTL                        REG32(DMA + 0x44U)    /*!< DMA channel 3 control register */
+#define DMA_CH3CNT                        REG32(DMA + 0x48U)    /*!< DMA channel 3 counter register */
+#define DMA_CH3PADDR                      REG32(DMA + 0x4CU)    /*!< DMA channel 3 peripheral base address register */
+#define DMA_CH3MADDR                      REG32(DMA + 0x50U)    /*!< DMA channel 3 memory base address register */
+#define DMA_CH4CTL                        REG32(DMA + 0x58U)    /*!< DMA channel 4 control register */
+#define DMA_CH4CNT                        REG32(DMA + 0x5CU)    /*!< DMA channel 4 counter register */
+#define DMA_CH4PADDR                      REG32(DMA + 0x60U)    /*!< DMA channel 4 peripheral base address register */
+#define DMA_CH4MADDR                      REG32(DMA + 0x64U)    /*!< DMA channel 4 memory base address register */
+
+/* bits definitions */
+/* DMA_INTF */
+#define DMA_INTF_GIF                      BIT(0)                /*!< global interrupt flag of channel */
+#define DMA_INTF_FTFIF                    BIT(1)                /*!< full transfer finish flag of channel */
+#define DMA_INTF_HTFIF                    BIT(2)                /*!< half transfer finish flag of channel */
+#define DMA_INTF_ERRIF                    BIT(3)                /*!< error flag of channel */
+
+/* DMA_INTC */
+#define DMA_INTC_GIFC                     BIT(0)                /*!< clear global interrupt flag of channel */
+#define DMA_INTC_FTFIFC                   BIT(1)                /*!< clear transfer finish flag of channel */
+#define DMA_INTC_HTFIFC                   BIT(2)                /*!< clear half transfer finish flag of channel */
+#define DMA_INTC_ERRIFC                   BIT(3)                /*!< clear error flag of channel */
+
+/* DMA_CHxCTL,x=0..4 */
+#define DMA_CHXCTL_CHEN                   BIT(0)                /*!< channel x enable */
+#define DMA_CHXCTL_FTFIE                  BIT(1)                /*!< enable bit for channel x transfer complete interrupt */
+#define DMA_CHXCTL_HTFIE                  BIT(2)                /*!< enable bit for channel x transfer half complete interrupt */
+#define DMA_CHXCTL_ERRIE                  BIT(3)                /*!< enable bit for channel x error interrupt */
+#define DMA_CHXCTL_DIR                    BIT(4)                /*!< direction of the data transfer on the channel */
+#define DMA_CHXCTL_CMEN                   BIT(5)                /*!< circulation mode */
+#define DMA_CHXCTL_PNAGA                  BIT(6)                /*!< next address generation algorithm of peripheral */
+#define DMA_CHXCTL_MNAGA                  BIT(7)                /*!< next address generation algorithm of memory */
+#define DMA_CHXCTL_PWIDTH                 BITS(8,9)             /*!< transfer data size of peripheral */
+#define DMA_CHXCTL_MWIDTH                 BITS(10,11)           /*!< transfer data size of memory */
+#define DMA_CHXCTL_PRIO                   BITS(12,13)           /*!< priority level of channelx */
+#define DMA_CHXCTL_M2M                    BIT(14)               /*!< memory to memory mode */
+
+/* DMA_CHxCNT,x=0..4 */
+#define DMA_CHXCNT_CNT                    BITS(0,15)            /*!< transfer counter */
+
+/* DMA_CHxPADDR,x=0..4 */
+#define DMA_CHXPADDR_PADDR                BITS(0,31)            /*!< peripheral base address */
+
+/* DMA_CHxMADDR,x=0..4 */
+#define DMA_CHXMADDR_MADDR                BITS(0,31)            /*!< memory base address */
+
+/* constants definitions */
+/* DMA channel select */
+typedef enum 
+{
+    DMA_CH0 = 0,                          /*!< DMA Channel0 */
+    DMA_CH1,                              /*!< DMA Channel1 */ 
+    DMA_CH2,                              /*!< DMA Channel2 */ 
+    DMA_CH3,                              /*!< DMA Channel3 */ 
+    DMA_CH4,                              /*!< DMA Channel4 */ 
+} dma_channel_enum;
+
+/* DMA initialize struct */
+typedef struct
+{
+    uint32_t periph_addr;                 /*!< peripheral base address */
+    uint32_t periph_width;                /*!< transfer data size of peripheral */
+    uint32_t memory_addr;                 /*!< memory base address */
+    uint32_t memory_width;                /*!< transfer data size of memory */
+    uint32_t number;                      /*!< channel transfer number */
+    uint32_t priority;                    /*!< channel priority level */
+    uint8_t periph_inc;                   /*!< peripheral increasing mode */
+    uint8_t memory_inc;                   /*!< memory increasing mode */
+    uint8_t direction;                    /*!< channel data transfer direction */
+} dma_parameter_struct;
+
+/* DMA reset value */
+#define DMA_CHCTL_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCTL register */
+#define DMA_CHCNT_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCNT register */
+#define DMA_CHPADDR_RESET_VALUE           ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXPADDR register */
+#define DMA_CHMADDR_RESET_VALUE           ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXMADDR register */
+#define DMA_CHINTF_RESET_VALUE            (DMA_INTF_GIF | DMA_INTF_FTFIF | \
+                                           DMA_INTF_HTFIF | DMA_INTF_ERRIF)
+
+#define DMA_FLAG_ADD(flag,shift)          ((flag) << ((uint32_t)(shift) * 4U))            /*!< DMA channel flag shift */
+
+/* DMA_CHCTL base address */
+#define DMA_CHXCTL_BASE                   (DMA + 0x08U)                                   /*!< the base address of DMA channel CHXCTL register */
+#define DMA_CHXCNT_BASE                   (DMA + 0x0CU)                                   /*!< the base address of DMA channel CHXCNT register */
+#define DMA_CHXPADDR_BASE                 (DMA + 0x10U)                                   /*!< the base address of DMA channel CHXPADDR register */
+#define DMA_CHXMADDR_BASE                 (DMA + 0x14U)                                   /*!< the base address of DMA channel CHXMADDR register */
+
+/* DMA channel shift bit */
+#define DMA_CHCTL(channel)                REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel))         /*!< the address of DMA channel CHXCTL register */
+#define DMA_CHCNT(channel)                REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel))         /*!< the address of DMA channel CHXCNT register */
+#define DMA_CHPADDR(channel)              REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel))       /*!< the address of DMA channel CHXPADDR register */
+#define DMA_CHMADDR(channel)              REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel))       /*!< the address of DMA channel CHXMADDR register */
+
+/* DMA_INTF register */
+/* interrupt flag bits */
+#define DMA_INT_FLAG_G                    DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
+#define DMA_INT_FLAG_FTF                  DMA_INTF_FTFIF                                  /*!< full transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_HTF                  DMA_INTF_HTFIF                                  /*!< half transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_ERR                  DMA_INTF_ERRIF                                  /*!< error interrupt flag of channel */
+
+/* flag bits */
+#define DMA_FLAG_G                        DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
+#define DMA_FLAG_FTF                      DMA_INTF_FTFIF                                  /*!< full transfer finish flag of channel */
+#define DMA_FLAG_HTF                      DMA_INTF_HTFIF                                  /*!< half transfer finish flag of channel */
+#define DMA_FLAG_ERR                      DMA_INTF_ERRIF                                  /*!< error flag of channel */
+
+/* DMA_CHxCTL register */
+/* interrupt enable bits */
+#define DMA_INT_FTF                       DMA_CHXCTL_FTFIE                                /*!< enable bit for channel full transfer finish interrupt */
+#define DMA_INT_HTF                       DMA_CHXCTL_HTFIE                                /*!< enable bit for channel half transfer finish interrupt */
+#define DMA_INT_ERR                       DMA_CHXCTL_ERRIE                                /*!< enable bit for channel error interrupt */
+
+/* transfer direction */
+#define DMA_PERIPHERAL_TO_MEMORY          ((uint32_t)0x00000000U)                         /*!< read from peripheral and write to memory */
+#define DMA_MEMORY_TO_PERIPHERAL          ((uint32_t)0x00000001U)                         /*!< read from memory and write to peripheral */
+
+/* peripheral increasing mode */
+#define DMA_PERIPH_INCREASE_DISABLE       ((uint32_t)0x00000000U)                         /*!< next address of peripheral is fixed address mode */
+#define DMA_PERIPH_INCREASE_ENABLE        ((uint32_t)0x00000001U)                         /*!< next address of peripheral is increasing address mode */
+
+/* memory increasing mode */
+#define DMA_MEMORY_INCREASE_DISABLE       ((uint32_t)0x00000000U)                         /*!< next address of memory is fixed address mode */
+#define DMA_MEMORY_INCREASE_ENABLE        ((uint32_t)0x00000001U)                         /*!< next address of memory is increasing address mode */
+
+/* transfer data size of peripheral */
+#define CHCTL_PWIDTH(regval)              (BITS(8,9) & ((regval) << 8))                   /*!< transfer data size of peripheral */
+#define DMA_PERIPHERAL_WIDTH_8BIT         CHCTL_PWIDTH(0U)                                 /*!< transfer data size of peripheral is 8-bit */
+#define DMA_PERIPHERAL_WIDTH_16BIT        CHCTL_PWIDTH(1U)                                 /*!< transfer data size of peripheral is 16-bit */
+#define DMA_PERIPHERAL_WIDTH_32BIT        CHCTL_PWIDTH(2U)                                 /*!< transfer data size of peripheral is 32-bit */
+
+/* transfer data size of memory */
+#define CHCTL_MWIDTH(regval)              (BITS(10,11) & ((regval) << 10))                /*!< transfer data size of memory */
+#define DMA_MEMORY_WIDTH_8BIT             CHCTL_MWIDTH(0U)                                 /*!< transfer data size of memory is 8-bit */
+#define DMA_MEMORY_WIDTH_16BIT            CHCTL_MWIDTH(1U)                                 /*!< transfer data size of memory is 16-bit */
+#define DMA_MEMORY_WIDTH_32BIT            CHCTL_MWIDTH(2U)                                 /*!< transfer data size of memory is 32-bit */
+
+/* channel priority level */
+#define CHCTL_PRIO(regval)                (BITS(12,13) & ((regval) << 12))                /*!< DMA channel priority level */
+#define DMA_PRIORITY_LOW                  CHCTL_PRIO(0U)                                   /*!< low priority */
+#define DMA_PRIORITY_MEDIUM               CHCTL_PRIO(1U)                                   /*!< medium priority */
+#define DMA_PRIORITY_HIGH                 CHCTL_PRIO(2U)                                   /*!< high priority */
+#define DMA_PRIORITY_ULTRA_HIGH           CHCTL_PRIO(3U)                                   /*!< ultra high priority */
+
+/* DMA_CHxCNT register */
+/* transfer counter */
+#define DMA_CHANNEL_CNT_MASK              DMA_CHXCNT_CNT                    
+
+/* function declarations */
+/* deinitialize DMA a channel registers */
+void dma_deinit(dma_channel_enum channelx);
+/* initialize the parameters of DMA struct with the default values */
+void dma_struct_para_init(dma_parameter_struct* init_struct);
+/* initialize DMA channel */
+void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct);
+/* enable DMA circulation mode */
+void dma_circulation_enable(dma_channel_enum channelx);
+/* disable DMA circulation mode */
+void dma_circulation_disable(dma_channel_enum channelx);
+/* enable memory to memory mode */
+void dma_memory_to_memory_enable(dma_channel_enum channelx);
+/* disable memory to memory mode */
+void dma_memory_to_memory_disable(dma_channel_enum channelx);
+/* enable DMA channel */
+void dma_channel_enable(dma_channel_enum channelx);
+/* disable DMA channel */
+void dma_channel_disable(dma_channel_enum channelx);
+
+/* set DMA peripheral base address */
+void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
+/* set DMA memory base address */
+void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
+/* set the number of remaining data to be transferred by the DMA */
+void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
+/* get the number of remaining data to be transferred by the DMA */
+uint32_t dma_transfer_number_get(dma_channel_enum channelx);
+/* configure priority level of DMA channel */
+void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
+/* configure transfer data size of memory */
+void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
+/* configure transfer data size of peripheral */
+void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
+/* enable next address increasement algorithm of memory */
+void dma_memory_increase_enable(dma_channel_enum channelx);
+/* disable next address increasement algorithm of memory */
+void dma_memory_increase_disable(dma_channel_enum channelx);
+/* enable next address increasement algorithm of peripheral */
+void dma_periph_increase_enable(dma_channel_enum channelx);
+/* disable next address increasement algorithm of peripheral */
+void dma_periph_increase_disable(dma_channel_enum channelx);
+/* configure the direction of data transfer on the channel */
+void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction);
+
+/* check DMA flag is set or not */
+FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
+/* clear DMA a channel flag */
+void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
+/* check DMA flag and interrupt enable bit is set or not */
+FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
+/* clear DMA a channel flag */
+void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
+/* enable DMA interrupt */
+void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
+/* disable DMA interrupt */
+void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
+
+#endif /* GD32E230_DMA_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_exti.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_exti.h
new file mode 100644
index 0000000000..4d8b875c4a
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_exti.h
@@ -0,0 +1,278 @@
+/*!
+    \file  gd32e230_exti.h
+    \brief definitions for the EXTI
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_EXTI_H
+#define GD32E230_EXTI_H
+
+#include "gd32e230.h"
+
+/* EXTI definitions */
+#define EXTI                         EXTI_BASE
+
+/* registers definitions */
+#define EXTI_INTEN                   REG32(EXTI + 0x00U)      /*!< interrupt enable register */
+#define EXTI_EVEN                    REG32(EXTI + 0x04U)      /*!< event enable register */
+#define EXTI_RTEN                    REG32(EXTI + 0x08U)      /*!< rising edge trigger enable register */
+#define EXTI_FTEN                    REG32(EXTI + 0x0CU)      /*!< falling trigger enable register */
+#define EXTI_SWIEV                   REG32(EXTI + 0x10U)      /*!< software interrupt event register */
+#define EXTI_PD                      REG32(EXTI + 0x14U)      /*!< pending register */
+
+/* bits definitions */
+/* EXTI_INTEN */
+#define EXTI_INTEN_INTEN0            BIT(0)                   /*!< interrupt from line 0 */
+#define EXTI_INTEN_INTEN1            BIT(1)                   /*!< interrupt from line 1 */
+#define EXTI_INTEN_INTEN2            BIT(2)                   /*!< interrupt from line 2 */
+#define EXTI_INTEN_INTEN3            BIT(3)                   /*!< interrupt from line 3 */
+#define EXTI_INTEN_INTEN4            BIT(4)                   /*!< interrupt from line 4 */
+#define EXTI_INTEN_INTEN5            BIT(5)                   /*!< interrupt from line 5 */
+#define EXTI_INTEN_INTEN6            BIT(6)                   /*!< interrupt from line 6 */
+#define EXTI_INTEN_INTEN7            BIT(7)                   /*!< interrupt from line 7 */
+#define EXTI_INTEN_INTEN8            BIT(8)                   /*!< interrupt from line 8 */
+#define EXTI_INTEN_INTEN9            BIT(9)                   /*!< interrupt from line 9 */
+#define EXTI_INTEN_INTEN10           BIT(10)                  /*!< interrupt from line 10 */
+#define EXTI_INTEN_INTEN11           BIT(11)                  /*!< interrupt from line 11 */
+#define EXTI_INTEN_INTEN12           BIT(12)                  /*!< interrupt from line 12 */
+#define EXTI_INTEN_INTEN13           BIT(13)                  /*!< interrupt from line 13 */
+#define EXTI_INTEN_INTEN14           BIT(14)                  /*!< interrupt from line 14 */
+#define EXTI_INTEN_INTEN15           BIT(15)                  /*!< interrupt from line 15 */
+#define EXTI_INTEN_INTEN16           BIT(16)                  /*!< interrupt from line 16 */
+#define EXTI_INTEN_INTEN17           BIT(17)                  /*!< interrupt from line 17 */
+#define EXTI_INTEN_INTEN18           BIT(18)                  /*!< interrupt from line 18 */
+#define EXTI_INTEN_INTEN19           BIT(19)                  /*!< interrupt from line 19 */
+#define EXTI_INTEN_INTEN20           BIT(20)                  /*!< interrupt from line 20 */
+#define EXTI_INTEN_INTEN21           BIT(21)                  /*!< interrupt from line 21 */
+#define EXTI_INTEN_INTEN22           BIT(22)                  /*!< interrupt from line 22 */
+#define EXTI_INTEN_INTEN23           BIT(23)                  /*!< interrupt from line 23 */
+#define EXTI_INTEN_INTEN24           BIT(24)                  /*!< interrupt from line 24 */
+#define EXTI_INTEN_INTEN25           BIT(25)                  /*!< interrupt from line 25 */
+#define EXTI_INTEN_INTEN26           BIT(26)                  /*!< interrupt from line 26 */
+#define EXTI_INTEN_INTEN27           BIT(27)                  /*!< interrupt from line 27 */
+
+/* EXTI_EVEN */
+#define EXTI_EVEN_EVEN0              BIT(0)                   /*!< event from line 0 */
+#define EXTI_EVEN_EVEN1              BIT(1)                   /*!< event from line 1 */
+#define EXTI_EVEN_EVEN2              BIT(2)                   /*!< event from line 2 */
+#define EXTI_EVEN_EVEN3              BIT(3)                   /*!< event from line 3 */
+#define EXTI_EVEN_EVEN4              BIT(4)                   /*!< event from line 4 */
+#define EXTI_EVEN_EVEN5              BIT(5)                   /*!< event from line 5 */
+#define EXTI_EVEN_EVEN6              BIT(6)                   /*!< event from line 6 */
+#define EXTI_EVEN_EVEN7              BIT(7)                   /*!< event from line 7 */
+#define EXTI_EVEN_EVEN8              BIT(8)                   /*!< event from line 8 */
+#define EXTI_EVEN_EVEN9              BIT(9)                   /*!< event from line 9 */
+#define EXTI_EVEN_EVEN10             BIT(10)                  /*!< event from line 10 */
+#define EXTI_EVEN_EVEN11             BIT(11)                  /*!< event from line 11 */
+#define EXTI_EVEN_EVEN12             BIT(12)                  /*!< event from line 12 */
+#define EXTI_EVEN_EVEN13             BIT(13)                  /*!< event from line 13 */
+#define EXTI_EVEN_EVEN14             BIT(14)                  /*!< event from line 14 */
+#define EXTI_EVEN_EVEN15             BIT(15)                  /*!< event from line 15 */
+#define EXTI_EVEN_EVEN16             BIT(16)                  /*!< event from line 16 */
+#define EXTI_EVEN_EVEN17             BIT(17)                  /*!< event from line 17 */
+#define EXTI_EVEN_EVEN18             BIT(18)                  /*!< event from line 18 */
+#define EXTI_EVEN_EVEN19             BIT(19)                  /*!< event from line 19 */
+#define EXTI_EVEN_EVEN20             BIT(20)                  /*!< event from line 20 */
+#define EXTI_EVEN_EVEN21             BIT(21)                  /*!< event from line 21 */
+#define EXTI_EVEN_EVEN22             BIT(22)                  /*!< event from line 22 */
+#define EXTI_EVEN_EVEN23             BIT(23)                  /*!< event from line 23 */
+#define EXTI_EVEN_EVEN24             BIT(24)                  /*!< event from line 24 */
+#define EXTI_EVEN_EVEN25             BIT(25)                  /*!< event from line 25 */
+#define EXTI_EVEN_EVEN26             BIT(26)                  /*!< event from line 26 */
+#define EXTI_EVEN_EVEN27             BIT(27)                  /*!< event from line 27 */
+
+/* EXTI_RTEN */
+#define EXTI_RTEN_RTEN0              BIT(0)                   /*!< rising edge from line 0 */
+#define EXTI_RTEN_RTEN1              BIT(1)                   /*!< rising edge from line 1 */
+#define EXTI_RTEN_RTEN2              BIT(2)                   /*!< rising edge from line 2 */
+#define EXTI_RTEN_RTEN3              BIT(3)                   /*!< rising edge from line 3 */
+#define EXTI_RTEN_RTEN4              BIT(4)                   /*!< rising edge from line 4 */
+#define EXTI_RTEN_RTEN5              BIT(5)                   /*!< rising edge from line 5 */
+#define EXTI_RTEN_RTEN6              BIT(6)                   /*!< rising edge from line 6 */
+#define EXTI_RTEN_RTEN7              BIT(7)                   /*!< rising edge from line 7 */
+#define EXTI_RTEN_RTEN8              BIT(8)                   /*!< rising edge from line 8 */
+#define EXTI_RTEN_RTEN9              BIT(9)                   /*!< rising edge from line 9 */
+#define EXTI_RTEN_RTEN10             BIT(10)                  /*!< rising edge from line 10 */
+#define EXTI_RTEN_RTEN11             BIT(11)                  /*!< rising edge from line 11 */
+#define EXTI_RTEN_RTEN12             BIT(12)                  /*!< rising edge from line 12 */
+#define EXTI_RTEN_RTEN13             BIT(13)                  /*!< rising edge from line 13 */
+#define EXTI_RTEN_RTEN14             BIT(14)                  /*!< rising edge from line 14 */
+#define EXTI_RTEN_RTEN15             BIT(15)                  /*!< rising edge from line 15 */
+#define EXTI_RTEN_RTEN16             BIT(16)                  /*!< rising edge from line 16 */
+#define EXTI_RTEN_RTEN17             BIT(17)                  /*!< rising edge from line 17 */
+#define EXTI_RTEN_RTEN19             BIT(19)                  /*!< rising edge from line 19 */
+#define EXTI_RTEN_RTEN21             BIT(21)                  /*!< rising edge from line 21 */
+
+/* EXTI_FTEN */
+#define EXTI_FTEN_FTEN0              BIT(0)                   /*!< falling edge from line 0 */
+#define EXTI_FTEN_FTEN1              BIT(1)                   /*!< falling edge from line 1 */
+#define EXTI_FTEN_FTEN2              BIT(2)                   /*!< falling edge from line 2 */
+#define EXTI_FTEN_FTEN3              BIT(3)                   /*!< falling edge from line 3 */
+#define EXTI_FTEN_FTEN4              BIT(4)                   /*!< falling edge from line 4 */
+#define EXTI_FTEN_FTEN5              BIT(5)                   /*!< falling edge from line 5 */
+#define EXTI_FTEN_FTEN6              BIT(6)                   /*!< falling edge from line 6 */
+#define EXTI_FTEN_FTEN7              BIT(7)                   /*!< falling edge from line 7 */
+#define EXTI_FTEN_FTEN8              BIT(8)                   /*!< falling edge from line 8 */
+#define EXTI_FTEN_FTEN9              BIT(9)                   /*!< falling edge from line 9 */
+#define EXTI_FTEN_FTEN10             BIT(10)                  /*!< falling edge from line 10 */
+#define EXTI_FTEN_FTEN11             BIT(11)                  /*!< falling edge from line 11 */
+#define EXTI_FTEN_FTEN12             BIT(12)                  /*!< falling edge from line 12 */
+#define EXTI_FTEN_FTEN13             BIT(13)                  /*!< falling edge from line 13 */
+#define EXTI_FTEN_FTEN14             BIT(14)                  /*!< falling edge from line 14 */
+#define EXTI_FTEN_FTEN15             BIT(15)                  /*!< falling edge from line 15 */
+#define EXTI_FTEN_FTEN16             BIT(16)                  /*!< falling edge from line 16 */
+#define EXTI_FTEN_FTEN17             BIT(17)                  /*!< falling edge from line 17 */
+#define EXTI_FTEN_FTEN19             BIT(19)                  /*!< falling edge from line 19 */
+#define EXTI_FTEN_FTEN21             BIT(21)                  /*!< falling edge from line 21 */
+
+/* EXTI_SWIEV */
+#define EXTI_SWIEV_SWIEV0            BIT(0)                   /*!< software interrupt/event request from line 0 */
+#define EXTI_SWIEV_SWIEV1            BIT(1)                   /*!< software interrupt/event request from line 1 */
+#define EXTI_SWIEV_SWIEV2            BIT(2)                   /*!< software interrupt/event request from line 2 */
+#define EXTI_SWIEV_SWIEV3            BIT(3)                   /*!< software interrupt/event request from line 3 */
+#define EXTI_SWIEV_SWIEV4            BIT(4)                   /*!< software interrupt/event request from line 4 */
+#define EXTI_SWIEV_SWIEV5            BIT(5)                   /*!< software interrupt/event request from line 5 */
+#define EXTI_SWIEV_SWIEV6            BIT(6)                   /*!< software interrupt/event request from line 6 */
+#define EXTI_SWIEV_SWIEV7            BIT(7)                   /*!< software interrupt/event request from line 7 */
+#define EXTI_SWIEV_SWIEV8            BIT(8)                   /*!< software interrupt/event request from line 8 */
+#define EXTI_SWIEV_SWIEV9            BIT(9)                   /*!< software interrupt/event request from line 9 */
+#define EXTI_SWIEV_SWIEV10           BIT(10)                  /*!< software interrupt/event request from line 10 */
+#define EXTI_SWIEV_SWIEV11           BIT(11)                  /*!< software interrupt/event request from line 11 */
+#define EXTI_SWIEV_SWIEV12           BIT(12)                  /*!< software interrupt/event request from line 12 */
+#define EXTI_SWIEV_SWIEV13           BIT(13)                  /*!< software interrupt/event request from line 13 */
+#define EXTI_SWIEV_SWIEV14           BIT(14)                  /*!< software interrupt/event request from line 14 */
+#define EXTI_SWIEV_SWIEV15           BIT(15)                  /*!< software interrupt/event request from line 15 */
+#define EXTI_SWIEV_SWIEV16           BIT(16)                  /*!< software interrupt/event request from line 16 */
+#define EXTI_SWIEV_SWIEV17           BIT(17)                  /*!< software interrupt/event request from line 17 */
+#define EXTI_SWIEV_SWIEV19           BIT(19)                  /*!< software interrupt/event request from line 19 */
+#define EXTI_SWIEV_SWIEV21           BIT(21)                  /*!< software interrupt/event request from line 21 */
+
+/* EXTI_PD */
+#define EXTI_PD_PD0                  BIT(0)                   /*!< interrupt/event pending status from line 0 */
+#define EXTI_PD_PD1                  BIT(1)                   /*!< interrupt/event pending status from line 1 */
+#define EXTI_PD_PD2                  BIT(2)                   /*!< interrupt/event pending status from line 2 */
+#define EXTI_PD_PD3                  BIT(3)                   /*!< interrupt/event pending status from line 3 */
+#define EXTI_PD_PD4                  BIT(4)                   /*!< interrupt/event pending status from line 4 */
+#define EXTI_PD_PD5                  BIT(5)                   /*!< interrupt/event pending status from line 5 */
+#define EXTI_PD_PD6                  BIT(6)                   /*!< interrupt/event pending status from line 6 */
+#define EXTI_PD_PD7                  BIT(7)                   /*!< interrupt/event pending status from line 7 */
+#define EXTI_PD_PD8                  BIT(8)                   /*!< interrupt/event pending status from line 8 */
+#define EXTI_PD_PD9                  BIT(9)                   /*!< interrupt/event pending status from line 9 */
+#define EXTI_PD_PD10                 BIT(10)                  /*!< interrupt/event pending status from line 10 */
+#define EXTI_PD_PD11                 BIT(11)                  /*!< interrupt/event pending status from line 11 */
+#define EXTI_PD_PD12                 BIT(12)                  /*!< interrupt/event pending status from line 12 */
+#define EXTI_PD_PD13                 BIT(13)                  /*!< interrupt/event pending status from line 13 */
+#define EXTI_PD_PD14                 BIT(14)                  /*!< interrupt/event pending status from line 14 */
+#define EXTI_PD_PD15                 BIT(15)                  /*!< interrupt/event pending status from line 15 */
+#define EXTI_PD_PD16                 BIT(16)                  /*!< interrupt/event pending status from line 16 */
+#define EXTI_PD_PD17                 BIT(17)                  /*!< interrupt/event pending status from line 17 */
+#define EXTI_PD_PD19                 BIT(19)                  /*!< interrupt/event pending status from line 19 */
+#define EXTI_PD_PD21                 BIT(21)                  /*!< interrupt/event pending status from line 21 */
+
+/* constants definitions */
+/* EXTI line number */
+typedef enum
+{ 
+    EXTI_0      = BIT(0),                                     /*!< EXTI line 0 */
+    EXTI_1      = BIT(1),                                     /*!< EXTI line 1 */
+    EXTI_2      = BIT(2),                                     /*!< EXTI line 2 */
+    EXTI_3      = BIT(3),                                     /*!< EXTI line 3 */
+    EXTI_4      = BIT(4),                                     /*!< EXTI line 4 */
+    EXTI_5      = BIT(5),                                     /*!< EXTI line 5 */
+    EXTI_6      = BIT(6),                                     /*!< EXTI line 6 */
+    EXTI_7      = BIT(7),                                     /*!< EXTI line 7 */
+    EXTI_8      = BIT(8),                                     /*!< EXTI line 8 */
+    EXTI_9      = BIT(9),                                     /*!< EXTI line 9 */
+    EXTI_10     = BIT(10),                                    /*!< EXTI line 10 */
+    EXTI_11     = BIT(11),                                    /*!< EXTI line 11 */
+    EXTI_12     = BIT(12),                                    /*!< EXTI line 12 */
+    EXTI_13     = BIT(13),                                    /*!< EXTI line 13 */
+    EXTI_14     = BIT(14),                                    /*!< EXTI line 14 */
+    EXTI_15     = BIT(15),                                    /*!< EXTI line 15 */
+    EXTI_16     = BIT(16),                                    /*!< EXTI line 16 */
+    EXTI_17     = BIT(17),                                    /*!< EXTI line 17 */
+    EXTI_18     = BIT(18),                                    /*!< EXTI line 18 */
+    EXTI_19     = BIT(19),                                    /*!< EXTI line 19 */
+    EXTI_20     = BIT(20),                                    /*!< EXTI line 20 */    
+    EXTI_21     = BIT(21),                                    /*!< EXTI line 21 */
+    EXTI_22     = BIT(22),                                    /*!< EXTI line 22 */
+    EXTI_23     = BIT(23),                                    /*!< EXTI line 23 */
+    EXTI_24     = BIT(24),                                    /*!< EXTI line 24 */
+    EXTI_25     = BIT(25),                                    /*!< EXTI line 25 */
+    EXTI_26     = BIT(26),                                    /*!< EXTI line 26 */
+    EXTI_27     = BIT(27),                                    /*!< EXTI line 27 */
+}exti_line_enum;
+
+/* external interrupt and event */
+typedef enum
+{
+    EXTI_INTERRUPT   = 0,                                     /*!< EXTI interrupt mode */
+    EXTI_EVENT                                                /*!< EXTI event mode */
+}exti_mode_enum;
+
+/* interrupt trigger mode */
+typedef enum
+{ 
+    EXTI_TRIG_RISING = 0,                                     /*!< EXTI rising edge trigger */
+    EXTI_TRIG_FALLING,                                        /*!< EXTI falling edge trigger */
+    EXTI_TRIG_BOTH                                            /*!< EXTI rising and falling edge trigger */
+}exti_trig_type_enum;
+
+/* function declarations */
+/* deinitialize the EXTI */
+void exti_deinit(void);
+/* enable the configuration of EXTI initialize */
+void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
+/* enable the interrupts from EXTI line x */
+void exti_interrupt_enable(exti_line_enum linex);
+/* enable the events from EXTI line x */
+void exti_event_enable(exti_line_enum linex);
+/* disable the interrupts from EXTI line x */
+void exti_interrupt_disable(exti_line_enum linex);
+/* disable the events from EXTI line x */
+void exti_event_disable(exti_line_enum linex);
+
+/* get EXTI lines pending flag */
+FlagStatus exti_flag_get(exti_line_enum linex);
+/* clear EXTI lines pending flag */
+void exti_flag_clear(exti_line_enum linex);
+/* get EXTI lines flag when the interrupt flag is set */
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
+/* clear EXTI lines pending flag */
+void exti_interrupt_flag_clear(exti_line_enum linex);
+/* EXTI software interrupt event enable */
+void exti_software_interrupt_enable(exti_line_enum linex);
+/* EXTI software interrupt event disable */
+void exti_software_interrupt_disable(exti_line_enum linex);
+
+#endif /* GD32E230_EXTI_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fmc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fmc.h
new file mode 100644
index 0000000000..50f6d4b8bd
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fmc.h
@@ -0,0 +1,272 @@
+/*!
+    \file  gd32e230_fmc.h
+    \brief definitions for the FMC
+
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_FMC_H
+#define GD32E230_FMC_H
+
+#include "gd32e230.h"
+
+/* FMC and option byte definition */
+#define FMC                     FMC_BASE                    /*!< FMC register base address */
+#define OB                      OB_BASE                     /*!< option byte base address */
+
+/* registers definitions */
+#define FMC_WS                  REG32((FMC) + 0x00U)        /*!< FMC wait state register */
+#define FMC_KEY                 REG32((FMC) + 0x04U)        /*!< FMC unlock key register */
+#define FMC_OBKEY               REG32((FMC) + 0x08U)        /*!< FMC option bytes unlock key register */
+#define FMC_STAT                REG32((FMC) + 0x0CU)        /*!< FMC status register */
+#define FMC_CTL                 REG32((FMC) + 0x10U)        /*!< FMC control register */
+#define FMC_ADDR                REG32((FMC) + 0x14U)        /*!< FMC address register */
+#define FMC_OBSTAT              REG32((FMC) + 0x1CU)        /*!< FMC option bytes status register */
+#define FMC_WP                  REG32((FMC) + 0x20U)        /*!< FMC write protection register */
+#define FMC_PID                 REG32((FMC) + 0x100U)       /*!< FMC product ID register */
+
+#define OB_SPC_USER             REG32((OB) + 0x00U)         /*!< option byte security protection value and user value */
+#define OB_DATA                 REG32((OB) + 0x04U)         /*!< option byte data value*/
+#define OB_WP                   REG32((OB) + 0x08U)         /*!< option byte write protection */
+
+/* bits definitions */
+/* FMC_WS */
+#define FMC_WS_WSCNT            BITS(0,2)                   /*!< wait state counter */
+#define FMC_WS_PFEN             BIT(4)                      /*!< pre-fetch enable */
+#define FMC_WS_PGW              BIT(15)                     /*!< program width to flash memory */
+
+/* FMC_KEY */
+#define FMC_KEY_KEY             BITS(0,31)                  /*!< FMC main flash unlock key bits */
+
+/* FMC_OBKEY */
+#define FMC_OBKEY_OBKEY         BITS(0,31)                  /*!< option bytes unlock key bits */
+
+/* FMC_STAT */
+#define FMC_STAT_BUSY           BIT(0)                      /*!< flash busy flag bit */
+#define FMC_STAT_PGERR          BIT(2)                      /*!< flash program error flag bit */
+#define FMC_STAT_PGAERR         BIT(3)                      /*!< program alignment error flag bit */
+#define FMC_STAT_WPERR          BIT(4)                      /*!< flash write protection error flag bit */
+#define FMC_STAT_ENDF           BIT(5)                      /*!< end of operation flag bit */
+
+/* FMC_CTL */
+#define FMC_CTL_PG              BIT(0)                      /*!< main flash program command bit */
+#define FMC_CTL_PER             BIT(1)                      /*!< main flash page erase bit */
+#define FMC_CTL_MER             BIT(2)                      /*!< main flash mass erase bit */
+#define FMC_CTL_OBPG            BIT(4)                      /*!< option bytes program command bit */
+#define FMC_CTL_OBER            BIT(5)                      /*!< option bytes erase command bit */
+#define FMC_CTL_START           BIT(6)                      /*!< send erase command to FMC bit */
+#define FMC_CTL_LK              BIT(7)                      /*!< flash lock bit */
+#define FMC_CTL_OBWEN           BIT(9)                      /*!< option bytes erase/program enable bit */
+#define FMC_CTL_ERRIE           BIT(10)                     /*!< error interrupt enable bit */
+#define FMC_CTL_ENDIE           BIT(12)                     /*!< end of operation interrupt enable bit */
+#define FMC_CTL_OBRLD           BIT(13)                     /*!< option bytes reload bit */
+
+/* FMC_ADDR */
+#define FMC_ADDR_ADDR           BITS(0,31)                  /*!< flash command address bits */
+
+/* FMC_OBSTAT */
+#define FMC_OBSTAT_OBERR        BIT(0)                      /*!< option bytes read error bit */
+#define FMC_OBSTAT_PLEVEL_BIT0  BIT(1)                      /*!< protection level bit 0 */
+#define FMC_OBSTAT_PLEVEL_BIT1  BIT(2)                      /*!< protection level bit 1 */
+#define FMC_OBSTAT_USER         BITS(8,15)                  /*!< option bytes user bits */
+#define FMC_OBSTAT_DATA         BITS(16,31)                 /*!< option byte data bits */
+
+/* FMC_WP */
+#define FMC_WP_WP               BITS(0,15)                  /*!< store WP[15:0] of option byte block after system reset */
+
+/* FMC_PID */
+#define FMC_PID_PID             BITS(0,31)                  /*!< product ID bits */
+
+/* constants definitions */
+/* fmc state */
+typedef enum
+{
+    FMC_READY,                                              /*!< the operation has been completed */
+    FMC_BUSY,                                               /*!< the operation is in progress */
+    FMC_PGERR,                                              /*!< program error */
+    FMC_PGAERR,                                             /*!< program alignment error */
+    FMC_WPERR,                                              /*!< erase/program protection error */
+    FMC_TOERR,                                              /*!< timeout error */
+    FMC_OB_HSPC                                             /*!< option byte security protection code high */
+}fmc_state_enum;
+
+/* unlock key */
+#define UNLOCK_KEY0                ((uint32_t)0x45670123U)  /*!< unlock key 0 */
+#define UNLOCK_KEY1                ((uint32_t)0xCDEF89ABU)  /*!< unlock key 1 */
+
+/* wait state counter value */
+#define WS_WSCNT_0                 ((uint8_t)0x00U)         /*!< 0 wait state added */
+#define WS_WSCNT_1                 ((uint8_t)0x01U)         /*!< 1 wait state added */
+#define WS_WSCNT_2                 ((uint8_t)0x02U)         /*!< 2 wait state added */
+
+/* read protect configure */
+#define FMC_NSPC                   ((uint16_t)0x5AA5U)      /*!< no security protection */
+#define FMC_LSPC                   ((uint16_t)0x44BBU)      /*!< low security protection, any value except 0xA5 or 0xCC */
+#define FMC_HSPC                   ((uint16_t)0x33CCU)      /*!< high security protection */
+
+#define LOW_16BITS_MASK            ((uint32_t)0x0000FFFFU)  /*!< low 16 bits mask  */
+#define HIGH_16BITS_MASK           ((uint32_t)0xFFFF0000U)  /*!< high 16 bits mask  */
+
+/* option byte address */
+#define OB_SPC_USER_ADDRESS        ((uint32_t)0x1FFFF800U)  /*!< address of option byte security protection and user */
+#define OB_DATA_ADDRESS            ((uint32_t)0x1FFFF804U)  /*!< address of option byte data */
+#define OB_WP_ADDRESS              ((uint32_t)0x1FFFF808U)  /*!< address of option byte write protection */
+
+/* option byte write protection */
+#define OB_LWP                     ((uint32_t)0x000000FFU)  /*!< write protection low bits */
+#define OB_HWP                     ((uint32_t)0x0000FF00U)  /*!< write protection high bits */
+
+/* option byte software/hardware free watchdog timer */  
+#define OB_FWDGT_HW                ((uint8_t)(~BIT(0)))     /*!< hardware free watchdog timer */
+#define OB_FWDGT_SW                ((uint8_t)BIT(0))        /*!< software free watchdog timer */
+
+/* option byte reset or not entering deep sleep mode */
+#define OB_DEEPSLEEP_RST           ((uint8_t)(~BIT(1)))     /*!< generate a reset instead of entering deepsleep mode */
+#define OB_DEEPSLEEP_NRST          ((uint8_t)BIT(1))        /*!< no reset when entering deepsleep mode */
+
+/* option byte reset or not entering standby mode */
+#define OB_STDBY_RST               ((uint8_t)(~BIT(2)))     /*!< generate a reset instead of entering standby mode */
+#define OB_STDBY_NRST              ((uint8_t)BIT(2))        /*!< no reset when entering deepsleep mode */
+
+/* option byte OB_BOOT1_n set */
+#define OB_BOOT1_SET_1             ((uint8_t)(~BIT(4)))     /*!< BOOT1 bit is 1 */
+#define OB_BOOT1_SET_0             ((uint8_t)BIT(4))        /*!< BOOT1 bit is 0 */
+
+/* option byte VDDA monitor enable/disable */
+#define OB_VDDA_DISABLE            ((uint8_t)(~BIT(5)))     /*!< disable VDDA monitor */
+#define OB_VDDA_ENABLE             ((uint8_t)BIT(5))        /*!< enable VDDA monitor */
+
+/* option byte SRAM parity enable/disable */
+#define OB_SRAM_PARITY_ENABLE      ((uint8_t)(~BIT(6)))     /*!< enable SRAM parity check */
+#define OB_SRAM_PARITY_DISABLE     ((uint8_t)BIT(6))        /*!< disable SRAM parity check */
+
+/* option byte security protection level in FMC_OBSTAT register */
+#define OB_OBSTAT_PLEVEL_NO        ((uint8_t)0x00U)         /*!< no security protection */
+#define OB_OBSTAT_PLEVEL_LOW       ((uint8_t)0x01U)         /*!< low security protection */
+#define OB_OBSTAT_PLEVEL_HIGH      ((uint8_t)0x03U)         /*!< high security protection */
+
+/* option byte user mask */
+#define OB_USER_MASK               ((uint8_t)0x88U)         /*!< OB_USER reserved bit mask */
+
+/* option byte data address */
+#define OB_DATA_ADDR0              ((uint32_t)0x1FFFF804U)  /*!< option byte data address 0 */
+#define OB_DATA_ADDR1              ((uint32_t)0x1FFFF806U)  /*!< option byte data address 1 */
+
+/* FMC flags */
+#define FMC_FLAG_BUSY              FMC_STAT_BUSY            /*!< FMC busy flag */
+#define FMC_FLAG_PGERR             FMC_STAT_PGERR           /*!< FMC programming error flag */
+#define FMC_FLAG_PGAERR            FMC_STAT_PGAERR          /*!< FMC program alignment error flag */
+#define FMC_FLAG_WPERR             FMC_STAT_WPERR           /*!< FMC write protection error flag */
+#define FMC_FLAG_END               FMC_STAT_ENDF            /*!< FMC end of programming flag */
+
+/* FMC interrupt flags */
+#define FMC_INT_FLAG_PGERR         FMC_STAT_PGERR           /*!< FMC programming error flag */
+#define FMC_INT_FLAG_PGAERR        FMC_STAT_PGAERR          /*!< FMC program alignment error flag */
+#define FMC_INT_FLAG_WPERR         FMC_STAT_WPERR           /*!< FMC write protection error flag */
+#define FMC_INT_FLAG_END           FMC_STAT_ENDF            /*!< FMC end of programming flag */
+
+/* FMC interrupt enable */
+#define FMC_INTEN_END              FMC_CTL_ENDIE            /*!< enable FMC end of operation interrupt */
+#define FMC_INTEN_ERR              FMC_CTL_ERRIE            /*!< enable FMC error interrupt */
+
+/* FMC time out */
+#define FMC_TIMEOUT_COUNT          ((uint32_t)0x000F0000U)  /*!< count to judge of FMC timeout */
+
+/* function declarations */
+/* FMC main memory programming functions */
+/* unlock the main FMC operation */
+void fmc_unlock(void);
+/* lock the main FMC operation */
+void fmc_lock(void);
+/* set the wait state counter value */
+void fmc_wscnt_set(uint8_t wscnt);
+
+/* pre-fetch enable */
+void fmc_prefetch_enable(void);
+/* pre-fetch disable */
+void fmc_prefetch_disable(void);
+/* FMC erase page */
+fmc_state_enum fmc_page_erase(uint32_t page_address);
+/* FMC erase whole chip */
+fmc_state_enum fmc_mass_erase(void);
+/* FMC program a double word at the corresponding address */
+fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data);
+/* FMC program a word at the corresponding address */
+fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
+
+/* FMC option bytes programming functions */
+/* unlock the option byte operation */
+void ob_unlock(void);
+/* lock the option byte operation */
+void ob_lock(void);
+/* reload the option byte and generate a system reset */
+void ob_reset(void);
+/* get option byte value */
+uint32_t option_byte_value_get(uint32_t addr);
+/* erase option byte */
+fmc_state_enum ob_erase(void);
+/* enable option byte write protection (OB_WP) */
+fmc_state_enum ob_write_protection_enable(uint16_t ob_wp);
+/* configure read out protect */
+fmc_state_enum ob_security_protection_config(uint16_t ob_spc);
+/* write the FMC option byte user */
+fmc_state_enum ob_user_write(uint8_t ob_user);
+/* write the FMC option byte data */
+fmc_state_enum ob_data_program(uint16_t data);
+/* get the FMC option byte OB_USER */
+uint8_t ob_user_get(void);
+/* get the FMC option byte OB_DATA */
+uint16_t ob_data_get(void);
+/* get the FMC option byte write protection */
+uint16_t ob_write_protection_get(void);
+/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
+uint32_t ob_obstat_plevel_get(void);
+
+/* FMC interrupts and flags management functions */
+/* enable FMC interrupt */
+void fmc_interrupt_enable(uint32_t interrupt);
+/* disable FMC interrupt */
+void fmc_interrupt_disable(uint32_t interrupt);
+/* get flag set or reset */
+FlagStatus fmc_flag_get(uint32_t flag);
+/* clear the FMC pending flag */
+void fmc_flag_clear(uint32_t flag);
+/* get intrrupt flag set or reset */
+FlagStatus fmc_interrupt_flag_get(uint32_t int_flag);
+/* clear the FMC interrupt pending flag by writing 1 */
+void fmc_interrupt_flag_clear(uint32_t int_flag);
+/* return the FMC state */
+fmc_state_enum fmc_state_get(void);
+/* check FMC ready or not */
+fmc_state_enum fmc_ready_wait(uint32_t timeout);
+
+#endif /* GD32E230_FMC_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fwdgt.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fwdgt.h
new file mode 100644
index 0000000000..101f87a34a
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fwdgt.h
@@ -0,0 +1,119 @@
+/*!
+    \file  gd32e230_fwdgt.h
+    \brief definitions for the FWDGT 
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_FWDGT_H
+#define GD32E230_FWDGT_H
+
+#include "gd32e230.h"
+
+/* FWDGT definitions */
+#define FWDGT                       FWDGT_BASE
+
+/* registers definitions */
+#define FWDGT_CTL                   REG32((FWDGT) + 0x00000000U)                     /*!< FWDGT control register */
+#define FWDGT_PSC                   REG32((FWDGT) + 0x00000004U)                     /*!< FWDGT prescaler register */
+#define FWDGT_RLD                   REG32((FWDGT) + 0x00000008U)                     /*!< FWDGT reload register */
+#define FWDGT_STAT                  REG32((FWDGT) + 0x0000000CU)                     /*!< FWDGT status register */
+#define FWDGT_WND                   REG32((FWDGT) + 0x00000010U)                     /*!< FWDGT window register */
+
+/* bits definitions */
+/* FWDGT_CTL */
+#define FWDGT_CTL_CMD               BITS(0,15)                                 /*!< FWDGT command value */
+
+/* FWDGT_PSC */
+#define FWDGT_PSC_PSC               BITS(0,2)                                  /*!< FWDGT prescaler divider value */
+
+/* FWDGT_RLD */
+#define FWDGT_RLD_RLD               BITS(0,11)                                 /*!< FWDGT counter reload value */
+
+/* FWDGT_STAT */
+#define FWDGT_STAT_PUD              BIT(0)                                     /*!< FWDGT prescaler divider value update */
+#define FWDGT_STAT_RUD              BIT(1)                                     /*!< FWDGT counter reload value update */
+#define FWDGT_STAT_WUD              BIT(2)                                     /*!< FWDGT counter window value update */
+
+/* FWDGT_WND */
+#define FWDGT_WND_WND               BITS(0,11)                                 /*!< FWDGT counter window value */
+
+/* constants definitions */
+/* FWDGT_PSC register value */
+#define PSC_PSC(regval)             (BITS(0,2) & ((uint32_t)(regval) << 0U))
+#define FWDGT_PSC_DIV4              ((uint8_t)PSC_PSC(0))                      /*!< FWDGT prescaler set to 4 */
+#define FWDGT_PSC_DIV8              ((uint8_t)PSC_PSC(1))                      /*!< FWDGT prescaler set to 8 */
+#define FWDGT_PSC_DIV16             ((uint8_t)PSC_PSC(2))                      /*!< FWDGT prescaler set to 16 */
+#define FWDGT_PSC_DIV32             ((uint8_t)PSC_PSC(3))                      /*!< FWDGT prescaler set to 32 */
+#define FWDGT_PSC_DIV64             ((uint8_t)PSC_PSC(4))                      /*!< FWDGT prescaler set to 64 */
+#define FWDGT_PSC_DIV128            ((uint8_t)PSC_PSC(5))                      /*!< FWDGT prescaler set to 128 */
+#define FWDGT_PSC_DIV256            ((uint8_t)PSC_PSC(6))                      /*!< FWDGT prescaler set to 256 */
+
+/* control value */
+#define FWDGT_WRITEACCESS_ENABLE    ((uint16_t)0x00005555U)                    /*!< FWDGT_CTL bits write access enable value */
+#define FWDGT_WRITEACCESS_DISABLE   ((uint16_t)0x00000000U)                    /*!< FWDGT_CTL bits write access disable value */
+#define FWDGT_KEY_RELOAD            ((uint16_t)0x0000AAAAU)                    /*!< FWDGT_CTL bits fwdgt counter reload value */
+#define FWDGT_KEY_ENABLE            ((uint16_t)0x0000CCCCU)                    /*!< FWDGT_CTL bits fwdgt counter enable value */
+
+/* FWDGT timeout value */
+#define FWDGT_WND_TIMEOUT           ((uint32_t)0x000FFFFFU)                    /*!< FWDGT_WND register write operation state flag timeout */
+#define FWDGT_PSC_TIMEOUT           ((uint32_t)0x000FFFFFU)                    /*!< FWDGT_PSC register write operation state flag timeout */
+#define FWDGT_RLD_TIMEOUT           ((uint32_t)0x000FFFFFU)                    /*!< FWDGT_RLD register write operation state flag timeout */
+
+/* FWDGT flag definitions */
+#define FWDGT_FLAG_PUD              FWDGT_STAT_PUD                             /*!< a write operation to FWDGT_PSC register is on going */
+#define FWDGT_FLAG_RUD              FWDGT_STAT_RUD                             /*!< a write operation to FWDGT_RLD register is on going */
+#define FWDGT_FLAG_WUD              FWDGT_STAT_WUD                             /*!< a write operation to FWDGT_WND register is on going */
+
+/* function declarations */
+/* enable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_enable(void);
+/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
+void fwdgt_write_disable(void);
+/* start the free watchdog timer counter */
+void fwdgt_enable(void);
+
+/* configure the free watchdog timer counter prescaler value */
+ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
+/* configure the free watchdog timer counter reload value */
+ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
+/* configure the free watchdog timer counter window value */
+ErrStatus fwdgt_window_value_config(uint16_t window_value);
+/* reload the counter of FWDGT */
+void fwdgt_counter_reload(void);
+/* configure counter reload value, and prescaler divider value */
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
+
+/* get flag state of FWDGT */
+FlagStatus fwdgt_flag_get(uint16_t flag);
+
+#endif /* GD32E230_FWDGT_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_gpio.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_gpio.h
new file mode 100644
index 0000000000..252383983d
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_gpio.h
@@ -0,0 +1,388 @@
+/*!
+    \file    gd32e230_gpio.h
+    \brief   definitions for the GPIO
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_GPIO_H
+#define GD32E230_GPIO_H
+
+#include "gd32e230.h"
+
+/* GPIOx(x=A,B,C,F) definitions */
+#define GPIOA                      (GPIO_BASE + 0x00000000U)
+#define GPIOB                      (GPIO_BASE + 0x00000400U)
+#define GPIOC                      (GPIO_BASE + 0x00000800U)
+#define GPIOF                      (GPIO_BASE + 0x00001400U)
+
+/* registers definitions */
+#define GPIO_CTL(gpiox)            REG32((gpiox) + 0x00U)    /*!< GPIO port control register */
+#define GPIO_OMODE(gpiox)          REG32((gpiox) + 0x04U)    /*!< GPIO port output mode register */
+#define GPIO_OSPD(gpiox)           REG32((gpiox) + 0x08U)    /*!< GPIO port output speed register */
+#define GPIO_PUD(gpiox)            REG32((gpiox) + 0x0CU)    /*!< GPIO port pull-up/pull-down register */
+#define GPIO_ISTAT(gpiox)          REG32((gpiox) + 0x10U)    /*!< GPIO port input status register */
+#define GPIO_OCTL(gpiox)           REG32((gpiox) + 0x14U)    /*!< GPIO port output control register */
+#define GPIO_BOP(gpiox)            REG32((gpiox) + 0x18U)    /*!< GPIO port bit operation register */
+#define GPIO_LOCK(gpiox)           REG32((gpiox) + 0x1CU)    /*!< GPIO port configuration lock register */
+#define GPIO_AFSEL0(gpiox)         REG32((gpiox) + 0x20U)    /*!< GPIO alternate function selected register 0 */
+#define GPIO_AFSEL1(gpiox)         REG32((gpiox) + 0x24U)    /*!< GPIO alternate function selected register 1 */
+#define GPIO_BC(gpiox)             REG32((gpiox) + 0x28U)    /*!< GPIO bit clear register */
+#define GPIO_TG(gpiox)             REG32((gpiox) + 0x2CU)    /*!< GPIO port bit toggle register */
+
+/* bits definitions */
+/* GPIO_CTL */
+#define GPIO_CTL_CTL0              BITS(0,1)             /*!< pin 0 configuration bits */ 
+#define GPIO_CTL_CTL1              BITS(2,3)             /*!< pin 1 configuration bits */
+#define GPIO_CTL_CTL2              BITS(4,5)             /*!< pin 2 configuration bits */
+#define GPIO_CTL_CTL3              BITS(6,7)             /*!< pin 3 configuration bits */
+#define GPIO_CTL_CTL4              BITS(8,9)             /*!< pin 4 configuration bits */
+#define GPIO_CTL_CTL5              BITS(10,11)           /*!< pin 5 configuration bits */
+#define GPIO_CTL_CTL6              BITS(12,13)           /*!< pin 6 configuration bits */
+#define GPIO_CTL_CTL7              BITS(14,15)           /*!< pin 7 configuration bits */
+#define GPIO_CTL_CTL8              BITS(16,17)           /*!< pin 8 configuration bits */
+#define GPIO_CTL_CTL9              BITS(18,19)           /*!< pin 9 configuration bits */
+#define GPIO_CTL_CTL10             BITS(20,21)           /*!< pin 10 configuration bits */
+#define GPIO_CTL_CTL11             BITS(22,23)           /*!< pin 11 configuration bits */
+#define GPIO_CTL_CTL12             BITS(24,25)           /*!< pin 12 configuration bits */
+#define GPIO_CTL_CTL13             BITS(26,27)           /*!< pin 13 configuration bits */
+#define GPIO_CTL_CTL14             BITS(28,29)           /*!< pin 14 configuration bits */
+#define GPIO_CTL_CTL15             BITS(30,31)           /*!< pin 15 configuration bits */
+
+/* GPIO_OMODE */
+#define GPIO_OMODE_OM0             BIT(0)                /*!< pin 0 output mode bit */
+#define GPIO_OMODE_OM1             BIT(1)                /*!< pin 1 output mode bit */
+#define GPIO_OMODE_OM2             BIT(2)                /*!< pin 2 output mode bit */
+#define GPIO_OMODE_OM3             BIT(3)                /*!< pin 3 output mode bit */
+#define GPIO_OMODE_OM4             BIT(4)                /*!< pin 4 output mode bit */
+#define GPIO_OMODE_OM5             BIT(5)                /*!< pin 5 output mode bit */
+#define GPIO_OMODE_OM6             BIT(6)                /*!< pin 6 output mode bit */
+#define GPIO_OMODE_OM7             BIT(7)                /*!< pin 7 output mode bit */
+#define GPIO_OMODE_OM8             BIT(8)                /*!< pin 8 output mode bit */
+#define GPIO_OMODE_OM9             BIT(9)                /*!< pin 9 output mode bit */
+#define GPIO_OMODE_OM10            BIT(10)               /*!< pin 10 output mode bit */
+#define GPIO_OMODE_OM11            BIT(11)               /*!< pin 11 output mode bit */
+#define GPIO_OMODE_OM12            BIT(12)               /*!< pin 12 output mode bit */
+#define GPIO_OMODE_OM13            BIT(13)               /*!< pin 13 output mode bit */
+#define GPIO_OMODE_OM14            BIT(14)               /*!< pin 14 output mode bit */
+#define GPIO_OMODE_OM15            BIT(15)               /*!< pin 15 output mode bit */
+
+/* GPIO_OSPD */
+#define GPIO_OSPD_OSPD0           BITS(0,1)              /*!< pin 0 output max speed bits */
+#define GPIO_OSPD_OSPD1           BITS(2,3)              /*!< pin 1 output max speed bits */
+#define GPIO_OSPD_OSPD2           BITS(4,5)              /*!< pin 2 output max speed bits */
+#define GPIO_OSPD_OSPD3           BITS(6,7)              /*!< pin 3 output max speed bits */
+#define GPIO_OSPD_OSPD4           BITS(8,9)              /*!< pin 4 output max speed bits */
+#define GPIO_OSPD_OSPD5           BITS(10,11)            /*!< pin 5 output max speed bits */
+#define GPIO_OSPD_OSPD6           BITS(12,13)            /*!< pin 6 output max speed bits */
+#define GPIO_OSPD_OSPD7           BITS(14,15)            /*!< pin 7 output max speed bits */
+#define GPIO_OSPD_OSPD8           BITS(16,17)            /*!< pin 8 output max speed bits */
+#define GPIO_OSPD_OSPD9           BITS(18,19)            /*!< pin 9 output max speed bits */
+#define GPIO_OSPD_OSPD10          BITS(20,21)            /*!< pin 10 output max speed bits */
+#define GPIO_OSPD_OSPD11          BITS(22,23)            /*!< pin 11 output max speed bits */
+#define GPIO_OSPD_OSPD12          BITS(24,25)            /*!< pin 12 output max speed bits */
+#define GPIO_OSPD_OSPD13          BITS(26,27)            /*!< pin 13 output max speed bits */
+#define GPIO_OSPD_OSPD14          BITS(28,29)            /*!< pin 14 output max speed bits */
+#define GPIO_OSPD_OSPD15          BITS(30,31)            /*!< pin 15 output max speed bits */
+
+/* GPIO_PUD */
+#define GPIO_PUD_PUD0              BITS(0,1)             /*!< pin 0 pull-up or pull-down bits */
+#define GPIO_PUD_PUD1              BITS(2,3)             /*!< pin 1 pull-up or pull-down bits */
+#define GPIO_PUD_PUD2              BITS(4,5)             /*!< pin 2 pull-up or pull-down bits */
+#define GPIO_PUD_PUD3              BITS(6,7)             /*!< pin 3 pull-up or pull-down bits */
+#define GPIO_PUD_PUD4              BITS(8,9)             /*!< pin 4 pull-up or pull-down bits */
+#define GPIO_PUD_PUD5              BITS(10,11)           /*!< pin 5 pull-up or pull-down bits */
+#define GPIO_PUD_PUD6              BITS(12,13)           /*!< pin 6 pull-up or pull-down bits */
+#define GPIO_PUD_PUD7              BITS(14,15)           /*!< pin 7 pull-up or pull-down bits */
+#define GPIO_PUD_PUD8              BITS(16,17)           /*!< pin 8 pull-up or pull-down bits */
+#define GPIO_PUD_PUD9              BITS(18,19)           /*!< pin 9 pull-up or pull-down bits */
+#define GPIO_PUD_PUD10             BITS(20,21)           /*!< pin 10 pull-up or pull-down bits */
+#define GPIO_PUD_PUD11             BITS(22,23)           /*!< pin 11 pull-up or pull-down bits */
+#define GPIO_PUD_PUD12             BITS(24,25)           /*!< pin 12 pull-up or pull-down bits */
+#define GPIO_PUD_PUD13             BITS(26,27)           /*!< pin 13 pull-up or pull-down bits */
+#define GPIO_PUD_PUD14             BITS(28,29)           /*!< pin 14 pull-up or pull-down bits */
+#define GPIO_PUD_PUD15             BITS(30,31)           /*!< pin 15 pull-up or pull-down bits */
+
+/* GPIO_ISTAT */
+#define GPIO_ISTAT_ISTAT0          BIT(0)                /*!< pin 0 input status */
+#define GPIO_ISTAT_ISTAT1          BIT(1)                /*!< pin 1 input status */
+#define GPIO_ISTAT_ISTAT2          BIT(2)                /*!< pin 2 input status */
+#define GPIO_ISTAT_ISTAT3          BIT(3)                /*!< pin 3 input status */
+#define GPIO_ISTAT_ISTAT4          BIT(4)                /*!< pin 4 input status */
+#define GPIO_ISTAT_ISTAT5          BIT(5)                /*!< pin 5 input status */
+#define GPIO_ISTAT_ISTAT6          BIT(6)                /*!< pin 6 input status */
+#define GPIO_ISTAT_ISTAT7          BIT(7)                /*!< pin 7 input status */
+#define GPIO_ISTAT_ISTAT8          BIT(8)                /*!< pin 8 input status */
+#define GPIO_ISTAT_ISTAT9          BIT(9)                /*!< pin 9 input status */
+#define GPIO_ISTAT_ISTAT10         BIT(10)               /*!< pin 10 input status */
+#define GPIO_ISTAT_ISTAT11         BIT(11)               /*!< pin 11 input status */
+#define GPIO_ISTAT_ISTAT12         BIT(12)               /*!< pin 12 input status */
+#define GPIO_ISTAT_ISTAT13         BIT(13)               /*!< pin 13 input status */
+#define GPIO_ISTAT_ISTAT14         BIT(14)               /*!< pin 14 input status */
+#define GPIO_ISTAT_ISTAT15         BIT(15)               /*!< pin 15 input status */
+
+/* GPIO_OCTL */
+#define GPIO_OCTL_OCTL0            BIT(0)                /*!< pin 0 output bit */
+#define GPIO_OCTL_OCTL1            BIT(1)                /*!< pin 1 output bit */
+#define GPIO_OCTL_OCTL2            BIT(2)                /*!< pin 2 output bit */
+#define GPIO_OCTL_OCTL3            BIT(3)                /*!< pin 3 output bit */
+#define GPIO_OCTL_OCTL4            BIT(4)                /*!< pin 4 output bit */
+#define GPIO_OCTL_OCTL5            BIT(5)                /*!< pin 5 output bit */
+#define GPIO_OCTL_OCTL6            BIT(6)                /*!< pin 6 output bit */
+#define GPIO_OCTL_OCTL7            BIT(7)                /*!< pin 7 output bit */
+#define GPIO_OCTL_OCTL8            BIT(8)                /*!< pin 8 output bit */
+#define GPIO_OCTL_OCTL9            BIT(9)                /*!< pin 9 output bit */
+#define GPIO_OCTL_OCTL10           BIT(10)               /*!< pin 10 output bit */
+#define GPIO_OCTL_OCTL11           BIT(11)               /*!< pin 11 output bit */
+#define GPIO_OCTL_OCTL12           BIT(12)               /*!< pin 12 output bit */
+#define GPIO_OCTL_OCTL13           BIT(13)               /*!< pin 13 output bit */
+#define GPIO_OCTL_OCTL14           BIT(14)               /*!< pin 14 output bit */
+#define GPIO_OCTL_OCTL15           BIT(15)               /*!< pin 15 output bit */
+
+/* GPIO_BOP */
+#define GPIO_BOP_BOP0              BIT(0)                /*!< pin 0 set bit */
+#define GPIO_BOP_BOP1              BIT(1)                /*!< pin 1 set bit */
+#define GPIO_BOP_BOP2              BIT(2)                /*!< pin 2 set bit */
+#define GPIO_BOP_BOP3              BIT(3)                /*!< pin 3 set bit */
+#define GPIO_BOP_BOP4              BIT(4)                /*!< pin 4 set bit */
+#define GPIO_BOP_BOP5              BIT(5)                /*!< pin 5 set bit */
+#define GPIO_BOP_BOP6              BIT(6)                /*!< pin 6 set bit */
+#define GPIO_BOP_BOP7              BIT(7)                /*!< pin 7 set bit */
+#define GPIO_BOP_BOP8              BIT(8)                /*!< pin 8 set bit */
+#define GPIO_BOP_BOP9              BIT(9)                /*!< pin 9 set bit */
+#define GPIO_BOP_BOP10             BIT(10)               /*!< pin 10 set bit */
+#define GPIO_BOP_BOP11             BIT(11)               /*!< pin 11 set bit */
+#define GPIO_BOP_BOP12             BIT(12)               /*!< pin 12 set bit */
+#define GPIO_BOP_BOP13             BIT(13)               /*!< pin 13 set bit */
+#define GPIO_BOP_BOP14             BIT(14)               /*!< pin 14 set bit */
+#define GPIO_BOP_BOP15             BIT(15)               /*!< pin 15 set bit */
+#define GPIO_BOP_CR0               BIT(16)               /*!< pin 0 clear bit */
+#define GPIO_BOP_CR1               BIT(17)               /*!< pin 1 clear bit */
+#define GPIO_BOP_CR2               BIT(18)               /*!< pin 2 clear bit */
+#define GPIO_BOP_CR3               BIT(19)               /*!< pin 3 clear bit */
+#define GPIO_BOP_CR4               BIT(20)               /*!< pin 4 clear bit */
+#define GPIO_BOP_CR5               BIT(21)               /*!< pin 5 clear bit */
+#define GPIO_BOP_CR6               BIT(22)               /*!< pin 6 clear bit */
+#define GPIO_BOP_CR7               BIT(23)               /*!< pin 7 clear bit */
+#define GPIO_BOP_CR8               BIT(24)               /*!< pin 8 clear bit */
+#define GPIO_BOP_CR9               BIT(25)               /*!< pin 9 clear bit */
+#define GPIO_BOP_CR10              BIT(26)               /*!< pin 10 clear bit */
+#define GPIO_BOP_CR11              BIT(27)               /*!< pin 11 clear bit */
+#define GPIO_BOP_CR12              BIT(28)               /*!< pin 12 clear bit */
+#define GPIO_BOP_CR13              BIT(29)               /*!< pin 13 clear bit */
+#define GPIO_BOP_CR14              BIT(30)               /*!< pin 14 clear bit */
+#define GPIO_BOP_CR15              BIT(31)               /*!< pin 15 clear bit */
+
+/* GPIO_LOCK */
+#define GPIO_LOCK_LK0              BIT(0)                /*!< pin 0 lock bit */
+#define GPIO_LOCK_LK1              BIT(1)                /*!< pin 1 lock bit */
+#define GPIO_LOCK_LK2              BIT(2)                /*!< pin 2 lock bit */
+#define GPIO_LOCK_LK3              BIT(3)                /*!< pin 3 lock bit */
+#define GPIO_LOCK_LK4              BIT(4)                /*!< pin 4 lock bit */
+#define GPIO_LOCK_LK5              BIT(5)                /*!< pin 5 lock bit */
+#define GPIO_LOCK_LK6              BIT(6)                /*!< pin 6 lock bit */
+#define GPIO_LOCK_LK7              BIT(7)                /*!< pin 7 lock bit */
+#define GPIO_LOCK_LK8              BIT(8)                /*!< pin 8 lock bit */
+#define GPIO_LOCK_LK9              BIT(9)                /*!< pin 9 lock bit */
+#define GPIO_LOCK_LK10             BIT(10)               /*!< pin 10 lock bit */
+#define GPIO_LOCK_LK11             BIT(11)               /*!< pin 11 lock bit */
+#define GPIO_LOCK_LK12             BIT(12)               /*!< pin 12 lock bit */
+#define GPIO_LOCK_LK13             BIT(13)               /*!< pin 13 lock bit */
+#define GPIO_LOCK_LK14             BIT(14)               /*!< pin 14 lock bit */
+#define GPIO_LOCK_LK15             BIT(15)               /*!< pin 15 lock bit */
+#define GPIO_LOCK_LKK              BIT(16)               /*!< pin sequence lock key */
+
+/* GPIO_AFSEL0 */
+#define GPIO_AFSEL0_SEL0           BITS(0,3)             /*!< pin 0 alternate function selected */
+#define GPIO_AFSEL0_SEL1           BITS(4,7)             /*!< pin 1 alternate function selected */
+#define GPIO_AFSEL0_SEL2           BITS(8,11)            /*!< pin 2 alternate function selected */
+#define GPIO_AFSEL0_SEL3           BITS(12,15)           /*!< pin 3 alternate function selected */
+#define GPIO_AFSEL0_SEL4           BITS(16,19)           /*!< pin 4 alternate function selected */
+#define GPIO_AFSEL0_SEL5           BITS(20,23)           /*!< pin 5 alternate function selected */
+#define GPIO_AFSEL0_SEL6           BITS(24,27)           /*!< pin 6 alternate function selected */
+#define GPIO_AFSEL0_SEL7           BITS(28,31)           /*!< pin 7 alternate function selected */
+
+/* GPIO_AFSEL1 */
+#define GPIO_AFSEL1_SEL8           BITS(0,3)             /*!< pin 8 alternate function selected */
+#define GPIO_AFSEL1_SEL9           BITS(4,7)             /*!< pin 9 alternate function selected */
+#define GPIO_AFSEL1_SEL10          BITS(8,11)            /*!< pin 10 alternate function selected */
+#define GPIO_AFSEL1_SEL11          BITS(12,15)           /*!< pin 11 alternate function selected */
+#define GPIO_AFSEL1_SEL12          BITS(16,19)           /*!< pin 12 alternate function selected */
+#define GPIO_AFSEL1_SEL13          BITS(20,23)           /*!< pin 13 alternate function selected */
+#define GPIO_AFSEL1_SEL14          BITS(24,27)           /*!< pin 14 alternate function selected */
+#define GPIO_AFSEL1_SEL15          BITS(28,31)           /*!< pin 15 alternate function selected */
+
+/* GPIO_BC */
+#define GPIO_BC_CR0                BIT(0)                /*!< pin 0 clear bit */
+#define GPIO_BC_CR1                BIT(1)                /*!< pin 1 clear bit */
+#define GPIO_BC_CR2                BIT(2)                /*!< pin 2 clear bit */
+#define GPIO_BC_CR3                BIT(3)                /*!< pin 3 clear bit */
+#define GPIO_BC_CR4                BIT(4)                /*!< pin 4 clear bit */
+#define GPIO_BC_CR5                BIT(5)                /*!< pin 5 clear bit */
+#define GPIO_BC_CR6                BIT(6)                /*!< pin 6 clear bit */
+#define GPIO_BC_CR7                BIT(7)                /*!< pin 7 clear bit */
+#define GPIO_BC_CR8                BIT(8)                /*!< pin 8 clear bit */
+#define GPIO_BC_CR9                BIT(9)                /*!< pin 9 clear bit */
+#define GPIO_BC_CR10               BIT(10)               /*!< pin 10 clear bit */
+#define GPIO_BC_CR11               BIT(11)               /*!< pin 11 clear bit */
+#define GPIO_BC_CR12               BIT(12)               /*!< pin 12 clear bit */
+#define GPIO_BC_CR13               BIT(13)               /*!< pin 13 clear bit */
+#define GPIO_BC_CR14               BIT(14)               /*!< pin 14 clear bit */
+#define GPIO_BC_CR15               BIT(15)               /*!< pin 15 clear bit */
+
+/* GPIO_TG */
+#define GPIO_TG_TG0                BIT(0)                /*!< pin 0 toggle bit */
+#define GPIO_TG_TG1                BIT(1)                /*!< pin 1 toggle bit */
+#define GPIO_TG_TG2                BIT(2)                /*!< pin 2 toggle bit */
+#define GPIO_TG_TG3                BIT(3)                /*!< pin 3 toggle bit */
+#define GPIO_TG_TG4                BIT(4)                /*!< pin 4 toggle bit */
+#define GPIO_TG_TG5                BIT(5)                /*!< pin 5 toggle bit */
+#define GPIO_TG_TG6                BIT(6)                /*!< pin 6 toggle bit */
+#define GPIO_TG_TG7                BIT(7)                /*!< pin 7 toggle bit */
+#define GPIO_TG_TG8                BIT(8)                /*!< pin 8 toggle bit */
+#define GPIO_TG_TG9                BIT(9)                /*!< pin 9 toggle bit */
+#define GPIO_TG_TG10               BIT(10)               /*!< pin 10 toggle bit */
+#define GPIO_TG_TG11               BIT(11)               /*!< pin 11 toggle bit */
+#define GPIO_TG_TG12               BIT(12)               /*!< pin 12 toggle bit */
+#define GPIO_TG_TG13               BIT(13)               /*!< pin 13 toggle bit */
+#define GPIO_TG_TG14               BIT(14)               /*!< pin 14 toggle bit */
+#define GPIO_TG_TG15               BIT(15)               /*!< pin 15 toggle bit */
+
+/* constants definitions */
+typedef FlagStatus bit_status;
+
+/* output mode definitions */
+#define CTL_CLTR(regval)           (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define GPIO_MODE_INPUT            CTL_CLTR(0)           /*!< input mode */
+#define GPIO_MODE_OUTPUT           CTL_CLTR(1)           /*!< output mode */
+#define GPIO_MODE_AF               CTL_CLTR(2)           /*!< alternate function mode */
+#define GPIO_MODE_ANALOG           CTL_CLTR(3)           /*!< analog mode */
+
+/* pull-up/pull-down definitions */
+#define PUD_PUPD(regval)           (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define GPIO_PUPD_NONE             PUD_PUPD(0)           /*!< floating mode, no pull-up and pull-down resistors */
+#define GPIO_PUPD_PULLUP           PUD_PUPD(1)           /*!< with pull-up resistor */
+#define GPIO_PUPD_PULLDOWN         PUD_PUPD(2)           /*!< with pull-down resistor */
+
+/* GPIO pin definitions */
+#define GPIO_PIN_0                 BIT(0)                /*!< GPIO pin 0 */
+#define GPIO_PIN_1                 BIT(1)                /*!< GPIO pin 1 */
+#define GPIO_PIN_2                 BIT(2)                /*!< GPIO pin 2 */
+#define GPIO_PIN_3                 BIT(3)                /*!< GPIO pin 3 */
+#define GPIO_PIN_4                 BIT(4)                /*!< GPIO pin 4 */
+#define GPIO_PIN_5                 BIT(5)                /*!< GPIO pin 5 */
+#define GPIO_PIN_6                 BIT(6)                /*!< GPIO pin 6 */
+#define GPIO_PIN_7                 BIT(7)                /*!< GPIO pin 7 */
+#define GPIO_PIN_8                 BIT(8)                /*!< GPIO pin 8 */
+#define GPIO_PIN_9                 BIT(9)                /*!< GPIO pin 9 */
+#define GPIO_PIN_10                BIT(10)               /*!< GPIO pin 10 */
+#define GPIO_PIN_11                BIT(11)               /*!< GPIO pin 11 */
+#define GPIO_PIN_12                BIT(12)               /*!< GPIO pin 12 */
+#define GPIO_PIN_13                BIT(13)               /*!< GPIO pin 13 */
+#define GPIO_PIN_14                BIT(14)               /*!< GPIO pin 14 */
+#define GPIO_PIN_15                BIT(15)               /*!< GPIO pin 15 */
+#define GPIO_PIN_ALL               BITS(0,15)            /*!< GPIO pin all */
+
+/* GPIO mode configuration values */
+#define GPIO_MODE_SET(n, mode)     ((uint32_t)((uint32_t)(mode) << (2U * (n))))
+#define GPIO_MODE_MASK(n)          (0x3U << (2U * (n)))
+
+/* GPIO pull-up/pull-down values */
+#define GPIO_PUPD_SET(n, pupd)     ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
+#define GPIO_PUPD_MASK(n)          (0x3U << (2U * (n)))
+
+/* GPIO output speed values */
+#define GPIO_OSPEED_SET(n, speed)  ((uint32_t)((uint32_t)(speed) << (2U * (n))))
+#define GPIO_OSPEED_MASK(n)        (0x3U << (2U * (n)))
+
+/* GPIO output type */
+#define GPIO_OTYPE_PP              ((uint8_t)(0x00U))    /*!< push pull mode */
+#define GPIO_OTYPE_OD              ((uint8_t)(0x01U))    /*!< open drain mode */
+
+/* GPIO output max speed value */
+#define OSPD_OSPD0(regval)         (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define GPIO_OSPEED_2MHZ           OSPD_OSPD0(0)         /*!< output max speed 2MHz */
+#define GPIO_OSPEED_10MHZ          OSPD_OSPD0(1)         /*!< output max speed 10MHz */
+#define GPIO_OSPEED_50MHZ          OSPD_OSPD0(3)         /*!< output max speed 50MHz */
+
+/* GPIO alternate function values */
+#define GPIO_AFR_SET(n, af)        ((uint32_t)((uint32_t)(af) << (4U * (n))))
+#define GPIO_AFR_MASK(n)           (0xFU << (4U * (n)))
+ 
+/* GPIO alternate function */
+#define AF(regval)                 (BITS(0,3) & ((uint32_t)(regval) << 0)) 
+#define GPIO_AF_0                   AF(0)                /*!< alternate function 0 selected */
+#define GPIO_AF_1                   AF(1)                /*!< alternate function 1 selected */
+#define GPIO_AF_2                   AF(2)                /*!< alternate function 2 selected */
+#define GPIO_AF_3                   AF(3)                /*!< alternate function 3 selected */
+#define GPIO_AF_4                   AF(4)                /*!< alternate function 4 selected (port A,B only) */
+#define GPIO_AF_5                   AF(5)                /*!< alternate function 5 selected (port A,B only) */
+#define GPIO_AF_6                   AF(6)                /*!< alternate function 6 selected (port A,B only) */
+#define GPIO_AF_7                   AF(7)                /*!< alternate function 7 selected (port A,B only) */
+
+/* function declarations */
+/* reset GPIO port */
+void gpio_deinit(uint32_t gpio_periph);
+/* set GPIO mode */
+void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
+/* set GPIO output type and speed */
+void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
+
+/* set GPIO pin bit */
+void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
+/* reset GPIO pin bit */
+void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
+/* write data to the specified GPIO pin */
+void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
+/* write data to the specified GPIO port */
+void gpio_port_write(uint32_t gpio_periph, uint16_t data);
+
+/* get GPIO pin input status */
+FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
+/* get GPIO port input status */
+uint16_t gpio_input_port_get(uint32_t gpio_periph);
+/* get GPIO pin output status */
+FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
+/* get GPIO port output status */
+uint16_t gpio_output_port_get(uint32_t gpio_periph);
+
+/* set GPIO alternate function */
+void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin);
+/* lock GPIO pin bit */
+void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
+
+/* toggle GPIO pin status */
+void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
+/* toggle GPIO port status */
+void gpio_port_toggle(uint32_t gpio_periph);
+
+#endif /* GD32E230_GPIO_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_i2c.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_i2c.h
new file mode 100644
index 0000000000..ab07d46987
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_i2c.h
@@ -0,0 +1,389 @@
+/*!
+    \file  gd32e230_i2c.h
+    \brief definitions for the I2C
+
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_I2C_H
+#define GD32E230_I2C_H
+
+#include "gd32e230.h"
+
+/* I2Cx(x=0,1) definitions */
+#define I2C0                          I2C_BASE                   /*!< I2C0 base address */
+#define I2C1                          (I2C_BASE+0x400U)          /*!< I2C1 base address */
+
+/* registers definitions */
+#define I2C_CTL0(i2cx)                REG32((i2cx) + 0x00U)      /*!< I2C control register 0 */
+#define I2C_CTL1(i2cx)                REG32((i2cx) + 0x04U)      /*!< I2C control register 1 */
+#define I2C_SADDR0(i2cx)              REG32((i2cx) + 0x08U)      /*!< I2C slave address register 0*/
+#define I2C_SADDR1(i2cx)              REG32((i2cx) + 0x0CU)      /*!< I2C slave address register */
+#define I2C_DATA(i2cx)                REG32((i2cx) + 0x10U)      /*!< I2C transfer buffer register */
+#define I2C_STAT0(i2cx)               REG32((i2cx) + 0x14U)      /*!< I2C transfer status register 0 */
+#define I2C_STAT1(i2cx)               REG32((i2cx) + 0x18U)      /*!< I2C transfer status register */
+#define I2C_CKCFG(i2cx)               REG32((i2cx) + 0x1CU)      /*!< I2C clock configure register */
+#define I2C_RT(i2cx)                  REG32((i2cx) + 0x20U)      /*!< I2C rise time register */
+#define I2C_SAMCS(i2cx)               REG32((i2cx) + 0x80U)      /*!< I2C SAM control and status register */
+#define I2C_FMPCFG(i2cx)              REG32((i2cx) + 0x90U)      /*!< I2C fast-mode-plus configure register */
+
+/* bits definitions */
+/* I2Cx_CTL0 */
+#define I2C_CTL0_I2CEN                BIT(0)        /*!< peripheral enable */
+#define I2C_CTL0_SMBEN                BIT(1)        /*!< SMBus mode */
+#define I2C_CTL0_SMBSEL               BIT(3)        /*!< SMBus type */
+#define I2C_CTL0_ARPEN                BIT(4)        /*!< ARP enable */
+#define I2C_CTL0_PECEN                BIT(5)        /*!< PEC enable */
+#define I2C_CTL0_GCEN                 BIT(6)        /*!< general call enable */
+#define I2C_CTL0_SS                   BIT(7)        /*!< clock stretching disable (slave mode) */
+#define I2C_CTL0_START                BIT(8)        /*!< start generation */
+#define I2C_CTL0_STOP                 BIT(9)        /*!< stop generation */
+#define I2C_CTL0_ACKEN                BIT(10)       /*!< acknowledge enable */
+#define I2C_CTL0_POAP                 BIT(11)       /*!< acknowledge/PEC position (for data reception) */
+#define I2C_CTL0_PECTRANS             BIT(12)       /*!< packet error checking */
+#define I2C_CTL0_SALT                 BIT(13)       /*!< SMBus alert */
+#define I2C_CTL0_SRESET               BIT(15)       /*!< software reset */
+
+/* I2Cx_CTL1 */
+#define I2C_CTL1_I2CCLK               BITS(0,6)     /*!< I2CCLK[6:0] bits (peripheral clock frequency) */
+#define I2C_CTL1_ERRIE                BIT(8)        /*!< error interrupt inable */
+#define I2C_CTL1_EVIE                 BIT(9)        /*!< event interrupt enable */
+#define I2C_CTL1_BUFIE                BIT(10)       /*!< buffer interrupt enable */
+#define I2C_CTL1_DMAON                BIT(11)       /*!< DMA requests enable */
+#define I2C_CTL1_DMALST               BIT(12)       /*!< DMA last transfer */
+
+/* I2Cx_SADDR0 */
+#define I2C_SADDR0_ADDRESS0           BIT(0)        /*!< bit 0 of a 10-bit address */
+#define I2C_SADDR0_ADDRESS            BITS(1,7)     /*!< 7-bit address or bits 7:1 of a 10-bit address */
+#define I2C_SADDR0_ADDRESS_H          BITS(8,9)     /*!< highest two bits of a 10-bit address */
+#define I2C_SADDR0_ADDFORMAT          BIT(15)       /*!< address mode for the I2C slave */
+
+/* I2Cx_SADDR1 */
+#define I2C_SADDR1_DUADEN             BIT(0)        /*!< aual-address mode switch */
+#define I2C_SADDR1_ADDRESS2           BITS(1,7)     /*!< second I2C address for the slave in dual-address mode */
+
+/* I2Cx_DATA */
+#define I2C_DATA_TRB                  BITS(0,7)     /*!< 8-bit data register */
+
+/* I2Cx_STAT0 */
+#define I2C_STAT0_SBSEND              BIT(0)        /*!< start bit (master mode) */
+#define I2C_STAT0_ADDSEND             BIT(1)        /*!< address sent (master mode)/matched (slave mode) */
+#define I2C_STAT0_BTC                 BIT(2)        /*!< byte transfer finished */
+#define I2C_STAT0_ADD10SEND           BIT(3)        /*!< 10-bit header sent (master mode) */
+#define I2C_STAT0_STPDET              BIT(4)        /*!< stop detection (slave mode) */
+#define I2C_STAT0_RBNE                BIT(6)        /*!< data register not empty (receivers) */
+#define I2C_STAT0_TBE                 BIT(7)        /*!< data register empty (transmitters) */
+#define I2C_STAT0_BERR                BIT(8)        /*!< bus error */
+#define I2C_STAT0_LOSTARB             BIT(9)        /*!< arbitration lost (master mode) */
+#define I2C_STAT0_AERR                BIT(10)       /*!< acknowledge failure */
+#define I2C_STAT0_OUERR               BIT(11)       /*!< overrun/underrun */
+#define I2C_STAT0_PECERR              BIT(12)       /*!< PEC error in reception */
+#define I2C_STAT0_SMBTO               BIT(14)       /*!< timeout signal in SMBus mode */
+#define I2C_STAT0_SMBALT              BIT(15)       /*!< SMBus alert status */
+
+/* I2Cx_STAT1 */
+#define I2C_STAT1_MASTER              BIT(0)        /*!< master/slave */
+#define I2C_STAT1_I2CBSY              BIT(1)        /*!< bus busy */
+#define I2C_STAT1_TR                  BIT(2)        /*!< transmitter/receiver */
+#define I2C_STAT1_RXGC                BIT(4)        /*!< general call address (slave mode) */
+#define I2C_STAT1_DEFSMB              BIT(5)        /*!< SMBus device default address (slave mode) */
+#define I2C_STAT1_HSTSMB              BIT(6)        /*!< SMBus host header (slave mode) */
+#define I2C_STAT1_DUMODF              BIT(7)        /*!< dual flag (slave mode) */
+#define I2C_STAT1_PECV                BITS(8,15)    /*!< packet error checking value */
+
+/* I2Cx_CKCFG */
+#define I2C_CKCFG_CLKC                BITS(0,11)    /*!< clock control register in fast/standard mode or fast mode plus(master mode) */
+#define I2C_CKCFG_DTCY                BIT(14)       /*!< duty cycle of fast mode or fast mode plus */
+#define I2C_CKCFG_FAST                BIT(15)       /*!< I2C speed selection in master mode */
+
+/* I2Cx_RT */
+#define I2C_RT_RISETIME               BITS(0,6)     /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */
+
+/* I2Cx_SAMCS */
+#define I2C_SAMCS_SAMEN               BIT(0)        /*!< SAM_V interface enable */
+#define I2C_SAMCS_STOEN               BIT(1)        /*!< SAM_V interface timeout detect enable */
+#define I2C_SAMCS_TFFIE               BIT(4)        /*!< txframe fall interrupt enable */
+#define I2C_SAMCS_TFRIE               BIT(5)        /*!< txframe rise interrupt enable */
+#define I2C_SAMCS_RFFIE               BIT(6)        /*!< rxframe fall interrupt enable */
+#define I2C_SAMCS_RFRIE               BIT(7)        /*!< rxframe rise interrupt enable */
+#define I2C_SAMCS_TXF                 BIT(8)        /*!< level of txframe signal */
+#define I2C_SAMCS_RXF                 BIT(9)        /*!< level of rxframe signal */
+#define I2C_SAMCS_TFF                 BIT(12)       /*!< txframe fall flag */
+#define I2C_SAMCS_TFR                 BIT(13)       /*!< txframe rise flag */
+#define I2C_SAMCS_RFF                 BIT(14)       /*!< rxframe fall flag */
+#define I2C_SAMCS_RFR                 BIT(15)       /*!< rxframe rise flag */
+
+/* I2Cx_FMPCFG */
+#define I2C_FMPCFG_FMPEN              BIT(0)        /*!< fast mode plus enable bit */
+
+/* constants definitions */
+/* define the I2C bit position and its register index offset */
+#define I2C_REGIDX_BIT(regidx, bitpos)  (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define I2C_REG_VAL(i2cx, offset)       (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
+#define I2C_BIT_POS(val)                ((uint32_t)(val) & 0x1FU)
+#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)   (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
+                                                              | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
+#define I2C_REG_VAL2(i2cx, offset)      (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
+#define I2C_BIT_POS2(val)               (((uint32_t)(val) & 0x1F0000U) >> 16)
+
+/* register offset */
+#define I2C_CTL1_REG_OFFSET           0x04U         /*!< CTL1 register offset */
+#define I2C_STAT0_REG_OFFSET          0x14U         /*!< STAT0 register offset */
+#define I2C_STAT1_REG_OFFSET          0x18U         /*!< STAT1 register offset */
+#define I2C_SAMCS_REG_OFFSET          0x80U         /*!< SAMCS register offset */
+
+/* I2C flags */
+typedef enum
+{
+    /* flags in STAT0 register */
+    I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U),                /*!< start condition sent out in master mode */
+    I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U),               /*!< address is sent in master mode or received and matches in slave mode */
+    I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U),                   /*!< byte transmission finishes */
+    I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U),             /*!< header of 10-bit address is sent in master mode */
+    I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U),                /*!< stop condition detected in slave mode */
+    I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U),                  /*!< I2C_DATA is not Empty during receiving */
+    I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U),                   /*!< I2C_DATA is empty during transmitting */
+    I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U),                  /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
+    I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U),               /*!< arbitration lost in master mode */
+    I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U),                 /*!< acknowledge error */
+    I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U),                /*!< over-run or under-run situation occurs in slave mode */
+    I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U),               /*!< PEC error when receiving data */
+    I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U),                /*!< timeout signal in SMBus mode */
+    I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U),               /*!< SMBus alert status */
+    /* flags in STAT1 register */
+    I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U),                /*!< a flag indicating whether I2C block is in master or slave mode */
+    I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U),                /*!< busy flag */
+    I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U),                    /*!< whether the I2C is a transmitter or a receiver */
+    I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U),                  /*!< general call address (00h) received */
+    I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U),                /*!< default address of SMBus device */
+    I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U),                /*!< SMBus host header detected in slave mode */
+    I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U),                 /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
+    /* flags in SAMCS register */
+    I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U),                  /*!< txframe fall flag */
+    I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U),                  /*!< txframe rise flag */
+    I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U),                  /*!< rxframe fall flag */
+    I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U)                   /*!< rxframe rise flag */
+}i2c_flag_enum;
+
+/* I2C interrupt flags */
+typedef enum
+{
+    /* interrupt flags in CTL1 register */
+    I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U),        /*!< start condition sent out in master mode interrupt flag */
+    I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U),       /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
+    I2C_INT_FLAG_BTC =  I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U),          /*!< byte transmission finishes */
+    I2C_INT_FLAG_ADD10SEND =  I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U),    /*!< header of 10-bit address is sent in master mode interrupt flag */
+    I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U),        /*!< stop condition detected in slave mode interrupt flag */
+    I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U),          /*!< I2C_DATA is not Empty during receiving interrupt flag */
+    I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U),           /*!< I2C_DATA is empty during transmitting interrupt flag */    
+    I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U),          /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
+    I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U),       /*!< arbitration lost in master mode interrupt flag */
+    I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U),         /*!< acknowledge error interrupt flag */
+    I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U),        /*!< over-run or under-run situation occurs in slave mode interrupt flag */
+    I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U),       /*!< PEC error when receiving data interrupt flag */
+    I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U),        /*!< timeout signal in SMBus mode interrupt flag */
+    I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U),       /*!< SMBus Alert status interrupt flag */
+    /* interrupt flags in SAMCS register */
+    I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U),         /*!< txframe fall interrupt flag */ 
+    I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U),         /*!< txframe rise interrupt  flag */
+    I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U),         /*!< rxframe fall interrupt flag */
+    I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U)          /*!< rxframe rise interrupt flag */
+}i2c_interrupt_flag_enum;
+
+/* I2C interrupt enable or disable */
+typedef enum
+{
+    /* interrupt in CTL1 register */
+    I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U),                     /*!< error interrupt enable */
+    I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U),                      /*!< event interrupt enable */
+    I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U),                    /*!< buffer interrupt enable */
+    /* interrupt in SAMCS register */
+    I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U),                    /*!< txframe fall interrupt enable  */
+    I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U),                    /*!< txframe rise interrupt  enable */
+    I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U),                    /*!< rxframe fall interrupt enable */
+    I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U)                     /*!< rxframe rise interrupt enable */
+}i2c_interrupt_enum;
+
+/* SMBus/I2C mode switch and SMBus type selection */
+#define I2C_I2CMODE_ENABLE            ((uint32_t)0x00000000U)                  /*!< I2C mode */
+#define I2C_SMBUSMODE_ENABLE          I2C_CTL0_SMBEN                           /*!< SMBus mode */
+
+/* SMBus/I2C mode switch and SMBus type selection */
+#define I2C_SMBUS_DEVICE              ((uint32_t)0x00000000U)                  /*!< SMBus mode device type */
+#define I2C_SMBUS_HOST                I2C_CTL0_SMBSEL                          /*!< SMBus mode host type */
+
+/* I2C transfer direction */
+#define I2C_RECEIVER                  ((uint32_t)0x00000001U)                  /*!< receiver */
+#define I2C_TRANSMITTER               ((uint32_t)0xFFFFFFFEU)                  /*!< transmitter */
+
+/* whether or not to send an ACK */
+#define I2C_ACK_DISABLE               ((uint32_t)0x00000000U)                  /*!< ACK will be not sent */
+#define I2C_ACK_ENABLE                ((uint32_t)0x00000001U)                  /*!< ACK will be sent */
+
+/* I2C POAP position*/
+#define I2C_ACKPOS_NEXT               ((uint32_t)0x00000000U)                  /*!< ACKEN bit decides whether or not to send ACK for the next byte */
+#define I2C_ACKPOS_CURRENT            ((uint32_t)0x00000001U)                  /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
+
+/* whether or not to stretch SCL low */
+#define I2C_SCLSTRETCH_ENABLE         I2C_CTL0_SS                              /*!< SCL stretching is enabled */
+#define I2C_SCLSTRETCH_DISABLE        ((uint32_t)0x00000000U)                  /*!< SCL stretching is disabled */
+
+/* whether or not to response to a general call */
+#define I2C_GCEN_ENABLE               I2C_CTL0_GCEN                            /*!< slave will response to a general call */
+#define I2C_GCEN_DISABLE              ((uint32_t)0x00000000U)                  /*!< slave will not response to a general call */
+
+/* software reset I2C */
+#define I2C_SRESET_SET                I2C_CTL0_SRESET                          /*!< I2C is under reset */
+#define I2C_SRESET_RESET              ((uint32_t)0x00000000U)                  /*!< I2C is not under reset */
+
+/* I2C DMA mode configure */
+/* DMA mode switch */
+#define I2C_DMA_ON                    I2C_CTL1_DMAON                           /*!< DMA mode enabled */
+#define I2C_DMA_OFF                   ((uint32_t)0x00000000U)                  /*!< DMA mode disabled */
+
+/* flag indicating DMA last transfer */
+#define I2C_DMALST_ON                 I2C_CTL1_DMALST                          /*!< next DMA EOT is the last transfer */
+#define I2C_DMALST_OFF                ((uint32_t)0x00000000U)                  /*!< next DMA EOT is not the last transfer */
+
+/* I2C PEC configure */
+/* PEC enable */
+#define I2C_PEC_ENABLE                I2C_CTL0_PECEN                           /*!< PEC calculation on */
+#define I2C_PEC_DISABLE               ((uint32_t)0x00000000U)                  /*!< PEC calculation off */
+
+/* PEC transfer */
+#define I2C_PECTRANS_ENABLE           I2C_CTL0_PECTRANS                        /*!< transfer PEC */
+#define I2C_PECTRANS_DISABLE          ((uint32_t)0x00000000U)                  /*!< not transfer PEC value */
+
+/* I2C SMBus configure */
+/* issue or not alert through SMBA pin */
+#define I2C_SALTSEND_ENABLE           I2C_CTL0_SALT                            /*!< issue alert through SMBA pin */
+#define I2C_SALTSEND_DISABLE          ((uint32_t)0x00000000U)                  /*!< not issue alert through SMBA */
+
+/* ARP protocol in SMBus switch */
+#define I2C_ARP_ENABLE                I2C_CTL0_ARPEN                           /*!< ARP enable */
+#define I2C_ARP_DISABLE               ((uint32_t)0x00000000U)                  /*!< ARP disable */
+
+/* fast mode plus enable */
+#define I2C_FAST_MODE_PLUS_ENABLE     I2C_FMPCFG_FMPEN                         /*!< fast mode plus enable */
+#define I2C_FAST_MODE_PLUS_DISABLE    ((uint32_t)0x00000000U)                  /*!< fast mode plus disable */
+
+/* transmit I2C data */
+#define DATA_TRANS(regval)            (BITS(0,7) & ((uint32_t)(regval) << 0))
+
+/* receive I2C data */
+#define DATA_RECV(regval)             GET_BITS((uint32_t)(regval), 0, 7)
+
+/* I2C duty cycle in fast mode or fast mode plus */
+#define I2C_DTCY_2                    ((uint32_t)0x00000000U)                  /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */
+#define I2C_DTCY_16_9                 I2C_CKCFG_DTCY                           /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */
+
+/* address mode for the I2C slave */
+#define I2C_ADDFORMAT_7BITS           ((uint32_t)0x00000000U)                  /*!< address:7 bits */
+#define I2C_ADDFORMAT_10BITS          I2C_SADDR0_ADDFORMAT                     /*!< address:10 bits */
+
+/* function declarations */
+/* reset I2C */
+void i2c_deinit(uint32_t i2c_periph);
+/* configure I2C clock */
+void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
+/* configure I2C address */
+void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
+/* SMBus type selection */
+void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
+/* whether or not to send an ACK */
+void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
+/* configure I2C POAP position */
+void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
+/* master sends slave address */
+void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
+/* enable dual-address mode */
+void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
+/* disable dual-address mode */
+void i2c_dualaddr_disable(uint32_t i2c_periph);
+/* enable I2C */
+void i2c_enable(uint32_t i2c_periph);
+/* disable I2C */
+void i2c_disable(uint32_t i2c_periph);
+
+/* generate a START condition on I2C bus */
+void i2c_start_on_bus(uint32_t i2c_periph);
+/* generate a STOP condition on I2C bus */
+void i2c_stop_on_bus(uint32_t i2c_periph);
+/* I2C transmit data function */
+void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
+/* I2C receive data function */
+uint8_t i2c_data_receive(uint32_t i2c_periph);
+/* enable I2C DMA mode */
+void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
+/* configure whether next DMA EOT is DMA last transfer or not */
+void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
+/* whether to stretch SCL low when data is not ready in slave mode */
+void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
+/* whether or not to response to a general call */
+void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
+/* software reset I2C */
+void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
+
+/* I2C PEC calculation on or off */
+void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
+/* I2C whether to transfer PEC value */
+void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
+/* packet error checking value */
+uint8_t i2c_pec_value_get(uint32_t i2c_periph);
+/* I2C issue alert through SMBA pin */
+void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
+/* I2C ARP protocol in SMBus switch */
+void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
+
+/* enable SAM_V interface */
+void i2c_sam_enable(uint32_t i2c_periph);
+/* disable SAM_V interface */
+void i2c_sam_disable(uint32_t i2c_periph);
+/* enable SAM_V interface timeout detect */
+void i2c_sam_timeout_enable(uint32_t i2c_periph);
+/* disable SAM_V interface timeout detect */
+void i2c_sam_timeout_disable(uint32_t i2c_periph);
+
+/* check I2C flag is set or not */
+FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
+/* clear I2C flag */
+void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
+/* enable I2C interrupt */
+void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
+/* disable I2C interrupt */
+void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
+/* check I2C interrupt flag */
+FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
+/* clear I2C interrupt flag */
+void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
+
+#endif /* GD32E230_I2C_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_misc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_misc.h
new file mode 100644
index 0000000000..4bc91a9600
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_misc.h
@@ -0,0 +1,86 @@
+/*!
+    \file  gd32e230_misc.h
+    \brief definitions for the MISC
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_MISC_H
+#define GD32E230_MISC_H
+
+#include "gd32e230.h"
+
+/* constants definitions */
+/* set the RAM and FLASH base address */
+#define NVIC_VECTTAB_RAM            ((uint32_t)0x20000000)                      /*!< RAM base address */
+#define NVIC_VECTTAB_FLASH          ((uint32_t)0x08000000)                      /*!< Flash base address */
+
+/* set the NVIC vector table offset mask */
+#define NVIC_VECTTAB_OFFSET_MASK    ((uint32_t)0x1FFFFF80)                      /*!< NVIC vector table offset mask */
+
+/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
+#define NVIC_AIRCR_VECTKEY_MASK     ((uint32_t)0x05FA0000)                      /*!< NVIC VECTKEY mask */
+
+/* choose the method to enter or exit the lowpower mode */
+#define SCB_SCR_SLEEPONEXIT         ((uint8_t)0x02)                             /*!< choose the the system whether enter low power mode by exiting from ISR */
+#define SCB_SCR_SLEEPDEEP           ((uint8_t)0x04)                             /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
+#define SCB_SCR_SEVONPEND           ((uint8_t)0x10)                             /*!< choose the interrupt source that can wake up the lowpower mode */
+
+#define SCB_LPM_SLEEP_EXIT_ISR      SCB_SCR_SLEEPONEXIT                         /*!< low power mode by exiting from ISR */
+#define SCB_LPM_DEEPSLEEP           SCB_SCR_SLEEPDEEP                           /*!< DEEPSLEEP mode or SLEEP mode */
+#define SCB_LPM_WAKE_BY_ALL_INT     SCB_SCR_SEVONPEND                           /*!< wakeup by all interrupt */
+
+/* choose the systick clock source */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU)                     /*!< systick clock source is from HCLK/8 */
+#define SYSTICK_CLKSOURCE_HCLK      ((uint32_t)0x00000004U)                     /*!< systick clock source is from HCLK */
+
+/* function declarations */
+
+/* enable NVIC request */
+void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_priority);
+/* disable NVIC request */
+void nvic_irq_disable(uint8_t nvic_irq);
+/* initiates a system reset request to reset the MCU */
+void nvic_system_reset(void);
+
+/* set the NVIC vector table base address */
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
+
+/* set the state of the low power mode */
+void system_lowpower_set(uint8_t lowpower_mode);
+/* reset the state of the low power mode */
+void system_lowpower_reset(uint8_t lowpower_mode);
+
+/* set the systick clock source */
+void systick_clksource_set(uint32_t systick_clksource);
+
+#endif /* GD32E230_MISC_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_pmu.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_pmu.h
new file mode 100644
index 0000000000..1db5b1fb47
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_pmu.h
@@ -0,0 +1,146 @@
+/*!
+    \file  gd32e230_pmu.h
+    \brief definitions for the PMU
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_PMU_H
+#define GD32E230_PMU_H
+
+#include "gd32e230.h"
+
+/* PMU definitions */
+#define PMU                           PMU_BASE                 /*!< PMU base address */
+
+/* registers definitions */
+#define PMU_CTL                       REG32((PMU) + 0x00U)     /*!< PMU control register */
+#define PMU_CS                        REG32((PMU) + 0x04U)     /*!< PMU control and status register */
+
+/* bits definitions */
+/* PMU_CTL */
+#define PMU_CTL_LDOLP                 BIT(0)                   /*!< LDO low power mode */
+#define PMU_CTL_STBMOD                BIT(1)                   /*!< standby mode */
+#define PMU_CTL_WURST                 BIT(2)                   /*!< wakeup flag reset */
+#define PMU_CTL_STBRST                BIT(3)                   /*!< standby flag reset */
+#define PMU_CTL_LVDEN                 BIT(4)                   /*!< low voltage detector enable */
+#define PMU_CTL_LVDT                  BITS(5,7)                /*!< low voltage detector threshold */
+#define PMU_CTL_BKPWEN                BIT(8)                   /*!< backup domain write enable */
+#define PMU_CTL_LDOVS_0               BIT(14)                  /*!< LDO output voltage select */
+#define PMU_CTL_LDOVS_1               BIT(15)                  /*!< LDO output voltage select */
+#define PMU_CTL_LDOVS                 BITS(14,15)              /*!< LDO output voltage select */
+
+/* PMU_CS */
+#define PMU_CS_WUF                    BIT(0)                   /*!< wakeup flag */
+#define PMU_CS_STBF                   BIT(1)                   /*!< standby flag */
+#define PMU_CS_LVDF                   BIT(2)                   /*!< low voltage detector status flag */
+#define PMU_CS_WUPEN0                 BIT(8)                   /*!< wakeup pin enable */
+#define PMU_CS_WUPEN1                 BIT(9)                   /*!< wakeup pin enable */
+#define PMU_CS_WUPEN5                 BIT(13)                  /*!< wakeup pin enable */
+#define PMU_CS_WUPEN6                 BIT(14)                  /*!< wakeup pin enable */
+
+/* constants definitions */
+/* PMU low voltage detector threshold definitions */
+#define CTL_LVDT(regval)              (BITS(5,7)&((uint32_t)(regval)<<5))
+#define PMU_LVDT_0                    CTL_LVDT(0)              /*!< voltage threshold is 2.1V */
+#define PMU_LVDT_1                    CTL_LVDT(1)              /*!< voltage threshold is 2.3V */
+#define PMU_LVDT_2                    CTL_LVDT(2)              /*!< voltage threshold is 2.4V */
+#define PMU_LVDT_3                    CTL_LVDT(3)              /*!< voltage threshold is 2.6V */
+#define PMU_LVDT_4                    CTL_LVDT(4)              /*!< voltage threshold is 2.7V */
+#define PMU_LVDT_5                    CTL_LVDT(5)              /*!< voltage threshold is 2.9V */
+#define PMU_LVDT_6                    CTL_LVDT(6)              /*!< voltage threshold is 3.0V */
+#define PMU_LVDT_7                    CTL_LVDT(7)              /*!< voltage threshold is 3.1V */
+
+/* PMU LDO output voltage select definitions */
+#define CTL_LDOVS(regval)             (BITS(14,15)&((uint32_t)(regval)<<14))
+#define PMU_LDOVS_HIGH                CTL_LDOVS(1)             /*!< LDO output voltage high mode */
+#define PMU_LDOVS_LOW                 CTL_LDOVS(2)             /*!< LDO output voltage low mode */
+
+/* PMU ldo definitions */
+#define PMU_LDO_NORMAL                ((uint32_t)0x00000000U)  /*!< LDO operates normally when PMU enter deepsleep mode */
+#define PMU_LDO_LOWPOWER              PMU_CTL_LDOLP            /*!< LDO work at low power status when PMU enter deepsleep mode */
+
+/* PMU flag definitions */
+#define PMU_FLAG_WAKEUP               PMU_CS_WUF               /*!< wakeup flag status */
+#define PMU_FLAG_STANDBY              PMU_CS_STBF              /*!< standby flag status */
+#define PMU_FLAG_LVD                  PMU_CS_LVDF              /*!< LVD flag status */
+
+/* PMU WKUP pin definitions */
+#define PMU_WAKEUP_PIN0               PMU_CS_WUPEN0            /*!< WKUP Pin 0 (PA0) enable */
+#define PMU_WAKEUP_PIN1               PMU_CS_WUPEN1            /*!< WKUP Pin 1 (PC13) enable */
+#define PMU_WAKEUP_PIN5               PMU_CS_WUPEN5            /*!< WKUP Pin 5 (PB5) enable */
+#define PMU_WAKEUP_PIN6               PMU_CS_WUPEN6            /*!< WKUP Pin 6 (PB15) enable */
+
+/* PMU flag reset definitions */
+#define PMU_FLAG_RESET_WAKEUP         PMU_CTL_WURST            /*!< wakeup flag reset */
+#define PMU_FLAG_RESET_STANDBY        PMU_CTL_STBRST           /*!< standby flag reset */
+
+/* PMU command constants definitions */
+#define WFI_CMD                       ((uint8_t)0x00U)         /*!< use WFI command */
+#define WFE_CMD                       ((uint8_t)0x01U)         /*!< use WFE command */
+
+/* function declarations */
+/* reset PMU registers */
+void pmu_deinit(void);
+
+/* select low voltage detector threshold */
+void pmu_lvd_select(uint32_t lvdt_n);
+/* select LDO output voltage */
+void pmu_ldo_output_select(uint32_t ldo_output);
+/* disable PMU lvd */
+void pmu_lvd_disable(void);
+
+/* set PMU mode */
+/* PMU work in sleep mode */
+void pmu_to_sleepmode(uint8_t sleepmodecmd);
+/* PMU work in deepsleep mode */
+void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
+/* PMU work in standby mode */
+void pmu_to_standbymode(uint8_t standbymodecmd);
+/* enable PMU wakeup pin */
+void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
+/* disable PMU wakeup pin */
+void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
+
+/* backup related functions */
+/* enable backup domain write */
+void pmu_backup_write_enable(void);
+/* disable backup domain write */
+void pmu_backup_write_disable(void);
+
+/* flag functions */
+/* clear flag bit */
+void pmu_flag_clear(uint32_t flag_clear);
+/* get flag state */
+FlagStatus pmu_flag_get(uint32_t flag);
+
+#endif /* GD32E230_PMU_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rcu.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rcu.h
new file mode 100644
index 0000000000..53f2e34e34
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rcu.h
@@ -0,0 +1,672 @@
+/*!
+    \file  gd32e230_rcu.h
+    \brief definitions for the RCU
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_RCU_H
+#define GD32E230_RCU_H
+
+#include "gd32e230.h"
+
+/* RCU definitions */
+#define RCU                         RCU_BASE
+
+/* registers definitions */
+#define RCU_CTL0                    REG32(RCU + 0x00U)        /*!< control register 0 */
+#define RCU_CFG0                    REG32(RCU + 0x04U)        /*!< configuration register 0 */
+#define RCU_INT                     REG32(RCU + 0x08U)        /*!< interrupt register */
+#define RCU_APB2RST                 REG32(RCU + 0x0CU)        /*!< APB2 reset register */
+#define RCU_APB1RST                 REG32(RCU + 0x10U)        /*!< APB1 reset register */
+#define RCU_AHBEN                   REG32(RCU + 0x14U)        /*!< AHB enable register */
+#define RCU_APB2EN                  REG32(RCU + 0x18U)        /*!< APB2 enable register */
+#define RCU_APB1EN                  REG32(RCU + 0x1CU)        /*!< APB1 enable register  */
+#define RCU_BDCTL                   REG32(RCU + 0x20U)        /*!< backup domain control register */
+#define RCU_RSTSCK                  REG32(RCU + 0x24U)        /*!< reset source /clock register */
+#define RCU_AHBRST                  REG32(RCU + 0x28U)        /*!< AHB reset register */
+#define RCU_CFG1                    REG32(RCU + 0x2CU)        /*!< configuration register 1 */
+#define RCU_CFG2                    REG32(RCU + 0x30U)        /*!< configuration register 2 */
+#define RCU_CTL1                    REG32(RCU + 0x34U)        /*!< control register 1 */
+#define RCU_VKEY                    REG32(RCU + 0x100U)       /*!< voltage key register */
+#define RCU_DSV                     REG32(RCU + 0x134U)       /*!< deep-sleep mode voltage register */
+
+/* bits definitions */
+/* RCU_CTL0 */
+#define RCU_CTL0_IRC8MEN            BIT(0)                    /*!< internal high speed oscillator enable */
+#define RCU_CTL0_IRC8MSTB           BIT(1)                    /*!< IRC8M high speed internal oscillator stabilization flag */
+#define RCU_CTL0_IRC8MADJ           BITS(3,7)                 /*!< high speed internal oscillator clock trim adjust value */
+#define RCU_CTL0_IRC8MCALIB         BITS(8,15)                /*!< high speed internal oscillator calibration value register */
+#define RCU_CTL0_HXTALEN            BIT(16)                   /*!< external high speed oscillator enable */
+#define RCU_CTL0_HXTALSTB           BIT(17)                   /*!< external crystal oscillator clock stabilization flag */
+#define RCU_CTL0_HXTALBPS           BIT(18)                   /*!< external crystal oscillator clock bypass mode enable */
+#define RCU_CTL0_CKMEN              BIT(19)                   /*!< HXTAL clock monitor enable */
+#define RCU_CTL0_PLLEN              BIT(24)                   /*!< PLL enable */
+#define RCU_CTL0_PLLSTB             BIT(25)                   /*!< PLL clock stabilization flag */
+
+/* RCU_CFG0 */
+#define RCU_CFG0_SCS                BITS(0,1)                 /*!< system clock switch */
+#define RCU_CFG0_SCSS               BITS(2,3)                 /*!< system clock switch status */
+#define RCU_CFG0_AHBPSC             BITS(4,7)                 /*!< AHB prescaler selection */
+#define RCU_CFG0_APB1PSC            BITS(8,10)                /*!< APB1 prescaler selection */
+#define RCU_CFG0_APB2PSC            BITS(11,13)               /*!< APB2 prescaler selection */
+#define RCU_CFG0_ADCPSC             BITS(14,15)               /*!< ADC clock prescaler selection */
+#define RCU_CFG0_PLLSEL             BIT(16)                   /*!< PLL clock source selection */
+#define RCU_CFG0_PLLPREDV           BIT(17)                   /*!< divider for PLL source clock selection */
+#define RCU_CFG0_PLLMF              (BIT(27) | BITS(18,21))   /*!< PLL multiply factor */
+#define RCU_CFG0_CKOUTSEL           BITS(24,26)               /*!< CK_OUT clock source selection */
+#define RCU_CFG0_PLLMF4             BIT(27)                   /*!< bit 4 of PLLMF */
+#define RCU_CFG0_CKOUTDIV           BITS(28,30)               /*!< CK_OUT divider which the CK_OUT frequency can be reduced */
+#define RCU_CFG0_PLLDV              BIT(31)                   /*!< CK_PLL divide by 1 or 2 */
+
+/* RCU_INT */
+#define RCU_INT_IRC40KSTBIF         BIT(0)                    /*!< IRC40K stabilization interrupt flag */
+#define RCU_INT_LXTALSTBIF          BIT(1)                    /*!< LXTAL stabilization interrupt flag */
+#define RCU_INT_IRC8MSTBIF          BIT(2)                    /*!< IRC8M stabilization interrupt flag */
+#define RCU_INT_HXTALSTBIF          BIT(3)                    /*!< HXTAL stabilization interrupt flag */
+#define RCU_INT_PLLSTBIF            BIT(4)                    /*!< PLL stabilization interrupt flag */
+#define RCU_INT_IRC28MSTBIF         BIT(5)                    /*!< IRC28M stabilization interrupt flag */
+#define RCU_INT_CKMIF               BIT(7)                    /*!< HXTAL clock stuck interrupt flag */
+#define RCU_INT_IRC40KSTBIE         BIT(8)                    /*!< IRC40K stabilization interrupt enable */
+#define RCU_INT_LXTALSTBIE          BIT(9)                    /*!< LXTAL stabilization interrupt enable */
+#define RCU_INT_IRC8MSTBIE          BIT(10)                   /*!< IRC8M stabilization interrupt enable */
+#define RCU_INT_HXTALSTBIE          BIT(11)                   /*!< HXTAL stabilization interrupt enable */
+#define RCU_INT_PLLSTBIE            BIT(12)                   /*!< PLL stabilization interrupt enable */
+#define RCU_INT_IRC28MSTBIE         BIT(13)                   /*!< IRC28M stabilization interrupt enable */
+#define RCU_INT_IRC40KSTBIC         BIT(16)                   /*!< IRC40K stabilization interrupt clear */
+#define RCU_INT_LXTALSTBIC          BIT(17)                   /*!< LXTAL stabilization interrupt clear */
+#define RCU_INT_IRC8MSTBIC          BIT(18)                   /*!< IRC8M stabilization interrupt clear */
+#define RCU_INT_HXTALSTBIC          BIT(19)                   /*!< HXTAL stabilization interrupt clear */
+#define RCU_INT_PLLSTBIC            BIT(20)                   /*!< PLL stabilization interrupt clear */
+#define RCU_INT_IRC28MSTBIC         BIT(21)                   /*!< IRC28M stabilization interrupt clear */
+#define RCU_INT_CKMIC               BIT(23)                   /*!< HXTAL clock stuck interrupt clear */
+
+/* RCU_APB2RST */
+#define RCU_APB2RST_CFGRST          BIT(0)                    /*!< system configuration reset */
+#define RCU_APB2RST_ADCRST          BIT(9)                    /*!< ADC reset */
+#define RCU_APB2RST_TIMER0RST       BIT(11)                   /*!< TIMER0 reset */
+#define RCU_APB2RST_SPI0RST         BIT(12)                   /*!< SPI0 reset */
+#define RCU_APB2RST_USART0RST       BIT(14)                   /*!< USART0 reset */
+#define RCU_APB2RST_TIMER14RST      BIT(16)                   /*!< TIMER14 reset */
+#define RCU_APB2RST_TIMER15RST      BIT(17)                   /*!< TIMER15 reset */
+#define RCU_APB2RST_TIMER16RST      BIT(18)                   /*!< TIMER16 reset */
+
+/* RCU_APB1RST */
+#define RCU_APB1RST_TIMER2RST       BIT(1)                    /*!< TIMER2 timer reset */
+#define RCU_APB1RST_TIMER5RST       BIT(4)                    /*!< TIMER5 timer reset */
+#define RCU_APB1RST_TIMER13RST      BIT(8)                    /*!< TIMER13 timer reset */
+#define RCU_APB1RST_WWDGTRST        BIT(11)                   /*!< window watchdog timer reset */
+#define RCU_APB1RST_SPI1RST         BIT(14)                   /*!< SPI1 reset */
+#define RCU_APB1RST_USART1RST       BIT(17)                   /*!< USART1 reset */
+#define RCU_APB1RST_I2C0RST         BIT(21)                   /*!< I2C0 reset */
+#define RCU_APB1RST_I2C1RST         BIT(22)                   /*!< I2C1 reset */
+#define RCU_APB1RST_PMURST          BIT(28)                   /*!< power control reset */
+
+/* RCU_AHBEN */
+#define RCU_AHBEN_DMAEN             BIT(0)                    /*!< DMA clock enable */
+#define RCU_AHBEN_SRAMSPEN          BIT(2)                    /*!< SRAM interface clock enable */
+#define RCU_AHBEN_FMCSPEN           BIT(4)                    /*!< FMC clock enable */
+#define RCU_AHBEN_CRCEN             BIT(6)                    /*!< CRC clock enable */
+#define RCU_AHBEN_PAEN              BIT(17)                   /*!< GPIO port A clock enable */
+#define RCU_AHBEN_PBEN              BIT(18)                   /*!< GPIO port B clock enable */
+#define RCU_AHBEN_PCEN              BIT(19)                   /*!< GPIO port C clock enable */
+#define RCU_AHBEN_PFEN              BIT(22)                   /*!< GPIO port F clock enable */
+
+/* RCU_APB2EN */
+#define RCU_APB2EN_CFGCMPEN         BIT(0)                    /*!< system configuration and comparator clock enable */
+#define RCU_APB2EN_ADCEN            BIT(9)                    /*!< ADC interface clock enable */
+#define RCU_APB2EN_TIMER0EN         BIT(11)                   /*!< TIMER0 timer clock enable */
+#define RCU_APB2EN_SPI0EN           BIT(12)                   /*!< SPI0 clock enable */
+#define RCU_APB2EN_USART0EN         BIT(14)                   /*!< USART0 clock enable */
+#define RCU_APB2EN_TIMER14EN        BIT(16)                   /*!< TIMER14 timer clock enable */
+#define RCU_APB2EN_TIMER15EN        BIT(17)                   /*!< TIMER15 timer clock enable */
+#define RCU_APB2EN_TIMER16EN        BIT(18)                   /*!< TIMER16 timer clock enable */
+#define RCU_APB2EN_DBGMCUEN         BIT(22)                   /*!< DBGMCU clock enable */
+
+/* RCU_APB1EN */
+#define RCU_APB1EN_TIMER2EN         BIT(1)                    /*!< TIMER2 timer clock enable */
+#define RCU_APB1EN_TIMER5EN         BIT(4)                    /*!< TIMER5 timer clock enable */
+#define RCU_APB1EN_TIMER13EN        BIT(8)                    /*!< TIMER13 timer clock enable */
+#define RCU_APB1EN_WWDGTEN          BIT(11)                   /*!< window watchdog timer clock enable */
+#define RCU_APB1EN_SPI1EN           BIT(14)                   /*!< SPI1 clock enable */
+#define RCU_APB1EN_USART1EN         BIT(17)                   /*!< USART1 clock enable */
+#define RCU_APB1EN_I2C0EN           BIT(21)                   /*!< I2C0 clock enable */
+#define RCU_APB1EN_I2C1EN           BIT(22)                   /*!< I2C1 clock enable */
+#define RCU_APB1EN_PMUEN            BIT(28)                   /*!< power interface clock enable */
+
+/* RCU_BDCTL */
+#define RCU_BDCTL_LXTALEN           BIT(0)                    /*!< LXTAL enable */
+#define RCU_BDCTL_LXTALSTB          BIT(1)                    /*!< external low-speed oscillator stabilization */
+#define RCU_BDCTL_LXTALBPS          BIT(2)                    /*!< LXTAL bypass mode enable */
+#define RCU_BDCTL_LXTALDRI          BITS(3,4)                 /*!< LXTAL drive capability */
+#define RCU_BDCTL_RTCSRC            BITS(8,9)                 /*!< RTC clock entry selection */
+#define RCU_BDCTL_RTCEN             BIT(15)                   /*!< RTC clock enable */
+#define RCU_BDCTL_BKPRST            BIT(16)                   /*!< backup domain reset */
+
+/* RCU_RSTSCK */
+#define RCU_RSTSCK_IRC40KEN         BIT(0)                    /*!< IRC40K enable */
+#define RCU_RSTSCK_IRC40KSTB        BIT(1)                    /*!< IRC40K stabilization */
+#define RCU_RSTSCK_V12RSTF          BIT(23)                   /*!< V12 domain power reset flag */
+#define RCU_RSTSCK_RSTFC            BIT(24)                   /*!< reset flag clear */
+#define RCU_RSTSCK_OBLRSTF          BIT(25)                   /*!< option byte loader reset flag */
+#define RCU_RSTSCK_EPRSTF           BIT(26)                   /*!< external pin reset flag */
+#define RCU_RSTSCK_PORRSTF          BIT(27)                   /*!< power reset flag */
+#define RCU_RSTSCK_SWRSTF           BIT(28)                   /*!< software reset flag */
+#define RCU_RSTSCK_FWDGTRSTF        BIT(29)                   /*!< free watchdog timer reset flag */
+#define RCU_RSTSCK_WWDGTRSTF        BIT(30)                   /*!< window watchdog timer reset flag */
+#define RCU_RSTSCK_LPRSTF           BIT(31)                   /*!< low-power reset flag */
+
+/* RCU_AHBRST */
+#define RCU_AHBRST_PARST            BIT(17)                   /*!< GPIO port A reset */
+#define RCU_AHBRST_PBRST            BIT(18)                   /*!< GPIO port B reset */
+#define RCU_AHBRST_PCRST            BIT(19)                   /*!< GPIO port C reset */
+#define RCU_AHBRST_PFRST            BIT(22)                   /*!< GPIO port F reset */
+
+/* RCU_CFG1 */
+#define RCU_CFG1_PREDV              BITS(0,3)                 /*!< CK_HXTAL divider previous PLL */
+
+/* RCU_CFG2 */
+#define RCU_CFG2_USART0SEL          BITS(0,1)                 /*!< CK_USART0 clock source selection */
+#define RCU_CFG2_ADCSEL             BIT(8)                    /*!< CK_ADC clock source selection */
+#define RCU_CFG2_IRC28MDIV          BIT(16)                   /*!< CK_IRC28M divider 2 or not */
+#define RCU_CFG2_ADCPSC2            BIT(31)                   /*!< bit 2 of ADCPSC */
+
+/* RCU_CTL1 */
+#define RCU_CTL1_IRC28MEN           BIT(0)                    /*!< IRC28M internal 28M RC oscillator enable */
+#define RCU_CTL1_IRC28MSTB          BIT(1)                    /*!< IRC28M internal 28M RC oscillator stabilization flag */
+#define RCU_CTL1_IRC28MADJ          BITS(3,7)                 /*!< internal 28M RC oscillator clock trim adjust value */
+#define RCU_CTL1_IRC28MCALIB        BITS(8,15)                /*!< internal 28M RC oscillator calibration value register */
+
+/* RCU_VKEY */
+#define RCU_VKEY_KEY                BITS(0,31)                /*!< key of RCU_DSV register */
+
+/* RCU_DSV */
+#define RCU_DSV_DSLPVS              BITS(0,1)                 /*!< deep-sleep mode voltage select */
+
+/* constants definitions */
+/* define the peripheral clock enable bit position and its register index offset */
+#define RCU_REGIDX_BIT(regidx, bitpos)      (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos))
+#define RCU_REG_VAL(periph)                 (REG32(RCU + ((uint32_t)(periph)>>6)))
+#define RCU_BIT_POS(val)                    ((uint32_t)(val) & 0x1FU)
+/* define the voltage key unlock value */
+#define RCU_VKEY_UNLOCK                     ((uint32_t)0x1A2B3C4D)
+
+/* register index */
+typedef enum
+{
+    /* peripherals enable */
+    IDX_AHBEN      = 0x14U, 
+    IDX_APB2EN     = 0x18U, 
+    IDX_APB1EN     = 0x1CU, 
+    /* peripherals reset */
+    IDX_AHBRST     = 0x28U, 
+    IDX_APB2RST    = 0x0CU, 
+    IDX_APB1RST    = 0x10U, 
+    /* clock stabilization */
+    IDX_CTL0       = 0x00U,
+    IDX_BDCTL      = 0x20U,
+    IDX_CTL1       = 0x34U,
+    /* peripheral reset */
+    IDX_RSTSCK     = 0x24U,
+    /* clock stabilization and stuck interrupt */
+    IDX_INT        = 0x08U,
+    /* configuration register */
+    IDX_CFG0       = 0x04U,
+    IDX_CFG2       = 0x30U
+}reg_idx;
+
+/* peripheral clock enable */
+typedef enum
+{
+    /* AHB peripherals */
+    RCU_DMA     = RCU_REGIDX_BIT(IDX_AHBEN, 0U),                  /*!< DMA clock */
+    RCU_CRC     = RCU_REGIDX_BIT(IDX_AHBEN, 6U),                  /*!< CRC clock */
+    RCU_GPIOA   = RCU_REGIDX_BIT(IDX_AHBEN, 17U),                 /*!< GPIOA clock */
+    RCU_GPIOB   = RCU_REGIDX_BIT(IDX_AHBEN, 18U),                 /*!< GPIOB clock */
+    RCU_GPIOC   = RCU_REGIDX_BIT(IDX_AHBEN, 19U),                 /*!< GPIOC clock */
+    RCU_GPIOF   = RCU_REGIDX_BIT(IDX_AHBEN, 22U),                 /*!< GPIOF clock */
+    
+    /* APB2 peripherals */
+    RCU_CFGCMP  = RCU_REGIDX_BIT(IDX_APB2EN, 0U),                 /*!< CFGCMP clock */
+    RCU_ADC     = RCU_REGIDX_BIT(IDX_APB2EN, 9U),                 /*!< ADC clock */
+    RCU_TIMER0  = RCU_REGIDX_BIT(IDX_APB2EN, 11U),                /*!< TIMER0 clock */
+    RCU_SPI0    = RCU_REGIDX_BIT(IDX_APB2EN, 12U),                /*!< SPI0 clock */
+    RCU_USART0  = RCU_REGIDX_BIT(IDX_APB2EN, 14U),                /*!< USART0 clock */
+    RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U),                /*!< TIMER14 clock */
+    RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U),                /*!< TIMER15 clock */
+    RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U),                /*!< TIMER16 clock */
+    RCU_DBGMCU  = RCU_REGIDX_BIT(IDX_APB2EN, 22U),                /*!< DBGMCU clock */
+    
+    /* APB1 peripherals */
+    RCU_TIMER2  = RCU_REGIDX_BIT(IDX_APB1EN, 1U),                 /*!< TIMER2 clock */
+    RCU_TIMER5  = RCU_REGIDX_BIT(IDX_APB1EN, 4U),                 /*!< TIMER5 clock */
+    RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U),                 /*!< TIMER13 clock */
+    RCU_WWDGT   = RCU_REGIDX_BIT(IDX_APB1EN, 11U),                /*!< WWDGT clock */
+    RCU_SPI1    = RCU_REGIDX_BIT(IDX_APB1EN, 14U),                /*!< SPI1 clock */
+    RCU_USART1  = RCU_REGIDX_BIT(IDX_APB1EN, 17U),                /*!< USART1 clock */
+    RCU_I2C0    = RCU_REGIDX_BIT(IDX_APB1EN, 21U),                /*!< I2C0 clock */
+    RCU_I2C1    = RCU_REGIDX_BIT(IDX_APB1EN, 22U),                /*!< I2C1 clock */
+    RCU_PMU     = RCU_REGIDX_BIT(IDX_APB1EN, 28U),                /*!< PMU clock */
+    
+    /* Backup domain control(BDCTL) */
+    RCU_RTC     = RCU_REGIDX_BIT(IDX_BDCTL, 15U)                  /*!< RTC clock */
+}rcu_periph_enum;
+
+/* peripheral clock enable when sleep mode*/
+typedef enum
+{
+    /* AHB peripherals */
+    RCU_SRAM_SLP     = RCU_REGIDX_BIT(IDX_AHBEN, 2U),             /*!< SRAM clock */
+    RCU_FMC_SLP      = RCU_REGIDX_BIT(IDX_AHBEN, 4U),             /*!< FMC clock */
+}rcu_periph_sleep_enum;
+
+/* peripherals reset */
+typedef enum
+{
+    /* AHB peripherals reset */
+    RCU_GPIOARST   = RCU_REGIDX_BIT(IDX_AHBRST, 17U),             /*!< GPIOA reset */
+    RCU_GPIOBRST   = RCU_REGIDX_BIT(IDX_AHBRST, 18U),             /*!< GPIOB reset */
+    RCU_GPIOCRST   = RCU_REGIDX_BIT(IDX_AHBRST, 19U),             /*!< GPIOC reset */
+    RCU_GPIOFRST   = RCU_REGIDX_BIT(IDX_AHBRST, 22U),             /*!< GPIOF reset */
+    
+    /* APB2 peripherals reset */
+    RCU_CFGCMPRST  = RCU_REGIDX_BIT(IDX_APB2RST, 0U),             /*!< CFGCMP reset */
+    RCU_ADCRST     = RCU_REGIDX_BIT(IDX_APB2RST, 9U),             /*!< ADC reset */
+    RCU_TIMER0RST  = RCU_REGIDX_BIT(IDX_APB2RST, 11U),            /*!< TIMER0 reset */
+    RCU_SPI0RST    = RCU_REGIDX_BIT(IDX_APB2RST, 12U),            /*!< SPI0 reset */
+    RCU_USART0RST  = RCU_REGIDX_BIT(IDX_APB2RST, 14U),            /*!< USART0 reset */
+    RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U),            /*!< TIMER14 reset */
+    RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U),            /*!< TIMER15 reset */
+    RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U),            /*!< TIMER16 reset */
+    
+    /* APB1 peripherals reset */
+    RCU_TIMER2RST  = RCU_REGIDX_BIT(IDX_APB1RST, 1U),             /*!< TIMER2 reset */
+    RCU_TIMER5RST  = RCU_REGIDX_BIT(IDX_APB1RST, 4U),             /*!< TIMER5 reset */
+    RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U),             /*!< TIMER13 reset */
+    RCU_WWDGTRST   = RCU_REGIDX_BIT(IDX_APB1RST, 11U),            /*!< WWDGT reset */
+    RCU_SPI1RST    = RCU_REGIDX_BIT(IDX_APB1RST, 14U),            /*!< SPI1 reset */
+    RCU_USART1RST  = RCU_REGIDX_BIT(IDX_APB1RST, 17U),            /*!< USART1 reset */
+    RCU_I2C0RST    = RCU_REGIDX_BIT(IDX_APB1RST, 21U),            /*!< I2C0 reset */
+    RCU_I2C1RST    = RCU_REGIDX_BIT(IDX_APB1RST, 22U),            /*!< I2C1 reset */
+    RCU_PMURST     = RCU_REGIDX_BIT(IDX_APB1RST, 28U),            /*!< PMU reset */
+}rcu_periph_reset_enum;
+
+/* clock stabilization and peripheral reset flags */
+typedef enum
+{
+    RCU_FLAG_IRC40KSTB    = RCU_REGIDX_BIT(IDX_RSTSCK, 1U),       /*!< IRC40K stabilization flags */
+    RCU_FLAG_LXTALSTB     = RCU_REGIDX_BIT(IDX_BDCTL, 1U),        /*!< LXTAL stabilization flags */
+    RCU_FLAG_IRC8MSTB     = RCU_REGIDX_BIT(IDX_CTL0, 1U),         /*!< IRC8M stabilization flags */
+    RCU_FLAG_HXTALSTB     = RCU_REGIDX_BIT(IDX_CTL0, 17U),        /*!< HXTAL stabilization flags */
+    RCU_FLAG_PLLSTB       = RCU_REGIDX_BIT(IDX_CTL0, 25U),        /*!< PLL stabilization flags */
+    RCU_FLAG_IRC28MSTB    = RCU_REGIDX_BIT(IDX_CTL1, 1U),         /*!< IRC28M stabilization flags */
+
+    RCU_FLAG_V12RST       = RCU_REGIDX_BIT(IDX_RSTSCK, 23U),      /*!< V12 reset flags */
+    RCU_FLAG_OBLRST       = RCU_REGIDX_BIT(IDX_RSTSCK, 25U),      /*!< OBL reset flags */
+    RCU_FLAG_EPRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 26U),      /*!< EPR reset flags */
+    RCU_FLAG_PORRST       = RCU_REGIDX_BIT(IDX_RSTSCK, 27U),      /*!< power reset flags */
+    RCU_FLAG_SWRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 28U),      /*!< SW reset flags */
+    RCU_FLAG_FWDGTRST     = RCU_REGIDX_BIT(IDX_RSTSCK, 29U),      /*!< FWDGT reset flags */
+    RCU_FLAG_WWDGTRST     = RCU_REGIDX_BIT(IDX_RSTSCK, 30U),      /*!< WWDGT reset flags */
+    RCU_FLAG_LPRST        = RCU_REGIDX_BIT(IDX_RSTSCK, 31U)       /*!< LP reset flags */
+}rcu_flag_enum;
+
+/* clock stabilization and ckm interrupt flags */
+typedef enum
+{
+    RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U),         /*!< IRC40K stabilization interrupt flag */
+    RCU_INT_FLAG_LXTALSTB  = RCU_REGIDX_BIT(IDX_INT, 1U),         /*!< LXTAL stabilization interrupt flag */
+    RCU_INT_FLAG_IRC8MSTB  = RCU_REGIDX_BIT(IDX_INT, 2U),         /*!< IRC8M stabilization interrupt flag */
+    RCU_INT_FLAG_HXTALSTB  = RCU_REGIDX_BIT(IDX_INT, 3U),         /*!< HXTAL stabilization interrupt flag */
+    RCU_INT_FLAG_PLLSTB    = RCU_REGIDX_BIT(IDX_INT, 4U),         /*!< PLL stabilization interrupt flag */
+    RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U),         /*!< IRC28M stabilization interrupt flag */
+    RCU_INT_FLAG_CKM       = RCU_REGIDX_BIT(IDX_INT, 7U),         /*!< CKM interrupt flag */
+}rcu_int_flag_enum;
+
+/* clock stabilization and stuck interrupt flags clear */
+typedef enum
+{
+    RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U),    /*!< IRC40K stabilization interrupt flags clear */
+    RCU_INT_FLAG_LXTALSTB_CLR  = RCU_REGIDX_BIT(IDX_INT, 17U),    /*!< LXTAL stabilization interrupt flags clear */
+    RCU_INT_FLAG_IRC8MSTB_CLR  = RCU_REGIDX_BIT(IDX_INT, 18U),    /*!< IRC8M stabilization interrupt flags clear */
+    RCU_INT_FLAG_HXTALSTB_CLR  = RCU_REGIDX_BIT(IDX_INT, 19U),    /*!< HXTAL stabilization interrupt flags clear */
+    RCU_INT_FLAG_PLLSTB_CLR    = RCU_REGIDX_BIT(IDX_INT, 20U),    /*!< PLL stabilization interrupt flags clear */
+    RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U),    /*!< IRC28M stabilization interrupt flags clear */
+    RCU_INT_FLAG_CKM_CLR       = RCU_REGIDX_BIT(IDX_INT, 23U),    /*!< CKM interrupt flags clear */
+}rcu_int_flag_clear_enum;
+
+/* clock stabilization interrupt enable or disable */
+typedef enum
+{
+    RCU_INT_IRC40KSTB       = RCU_REGIDX_BIT(IDX_INT, 8U),        /*!< IRC40K stabilization interrupt */
+    RCU_INT_LXTALSTB        = RCU_REGIDX_BIT(IDX_INT, 9U),        /*!< LXTAL stabilization interrupt */
+    RCU_INT_IRC8MSTB        = RCU_REGIDX_BIT(IDX_INT, 10U),       /*!< IRC8M stabilization interrupt */
+    RCU_INT_HXTALSTB        = RCU_REGIDX_BIT(IDX_INT, 11U),       /*!< HXTAL stabilization interrupt */
+    RCU_INT_PLLSTB          = RCU_REGIDX_BIT(IDX_INT, 12U),       /*!< PLL stabilization interrupt */
+    RCU_INT_IRC28MSTB       = RCU_REGIDX_BIT(IDX_INT, 13U),       /*!< IRC28M stabilization interrupt */
+}rcu_int_enum;
+
+/* ADC clock source */
+typedef enum
+{
+    RCU_ADCCK_IRC28M_DIV2   = 0U,                                 /*!< ADC clock source select IRC28M/2 */
+    RCU_ADCCK_IRC28M,                                             /*!< ADC clock source select IRC28M */
+    RCU_ADCCK_APB2_DIV2,                                          /*!< ADC clock source select APB2/2 */
+    RCU_ADCCK_AHB_DIV3,                                           /*!< ADC clock source select AHB/3 */
+    RCU_ADCCK_APB2_DIV4,                                          /*!< ADC clock source select APB2/4 */
+    RCU_ADCCK_AHB_DIV5,                                           /*!< ADC clock source select AHB/5 */
+    RCU_ADCCK_APB2_DIV6,                                          /*!< ADC clock source select APB2/6 */
+    RCU_ADCCK_AHB_DIV7,                                           /*!< ADC clock source select AHB/7 */
+    RCU_ADCCK_APB2_DIV8,                                          /*!< ADC clock source select APB2/8 */
+    RCU_ADCCK_AHB_DIV9                                            /*!< ADC clock source select AHB/9 */
+}rcu_adc_clock_enum;
+
+/* oscillator types */
+typedef enum
+{
+    RCU_HXTAL   = RCU_REGIDX_BIT(IDX_CTL0, 16U),                  /*!< HXTAL */
+    RCU_LXTAL   = RCU_REGIDX_BIT(IDX_BDCTL, 0U),                  /*!< LXTAL */
+    RCU_IRC8M   = RCU_REGIDX_BIT(IDX_CTL0, 0U),                   /*!< IRC8M */
+    RCU_IRC28M  = RCU_REGIDX_BIT(IDX_CTL1, 0U),                   /*!< IRC28M */
+    RCU_IRC40K  = RCU_REGIDX_BIT(IDX_RSTSCK, 0U),                 /*!< IRC40K */
+    RCU_PLL_CK  = RCU_REGIDX_BIT(IDX_CTL0, 24U)                   /*!< PLL */
+}rcu_osci_type_enum;
+
+/* rcu clock frequency */
+typedef enum
+{
+    CK_SYS      = 0U,                                             /*!< system clock */
+    CK_AHB,                                                       /*!< AHB clock */
+    CK_APB1,                                                      /*!< APB1 clock */
+    CK_APB2,                                                      /*!< APB2 clock */
+    CK_ADC,                                                       /*!< ADC clock */
+    CK_USART                                                      /*!< USART clock */
+}rcu_clock_freq_enum;
+
+/* system clock source select */
+#define CFG0_SCS(regval)            (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_CKSYSSRC_IRC8M          CFG0_SCS(0)                   /*!< system clock source select IRC8M */
+#define RCU_CKSYSSRC_HXTAL          CFG0_SCS(1)                   /*!< system clock source select HXTAL */
+#define RCU_CKSYSSRC_PLL            CFG0_SCS(2)                   /*!< system clock source select PLL */
+
+/* system clock source select status */
+#define CFG0_SCSS(regval)           (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define RCU_SCSS_IRC8M              CFG0_SCSS(0)                  /*!< system clock source select IRC8M */
+#define RCU_SCSS_HXTAL              CFG0_SCSS(1)                  /*!< system clock source select HXTAL */
+#define RCU_SCSS_PLL                CFG0_SCSS(2)                  /*!< system clock source select PLL */
+
+/* AHB prescaler selection */
+#define CFG0_AHBPSC(regval)         (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define RCU_AHB_CKSYS_DIV1          CFG0_AHBPSC(0)                /*!< AHB prescaler select CK_SYS */
+#define RCU_AHB_CKSYS_DIV2          CFG0_AHBPSC(8)                /*!< AHB prescaler select CK_SYS/2 */
+#define RCU_AHB_CKSYS_DIV4          CFG0_AHBPSC(9)                /*!< AHB prescaler select CK_SYS/4 */
+#define RCU_AHB_CKSYS_DIV8          CFG0_AHBPSC(10)               /*!< AHB prescaler select CK_SYS/8 */
+#define RCU_AHB_CKSYS_DIV16         CFG0_AHBPSC(11)               /*!< AHB prescaler select CK_SYS/16 */
+#define RCU_AHB_CKSYS_DIV64         CFG0_AHBPSC(12)               /*!< AHB prescaler select CK_SYS/64 */
+#define RCU_AHB_CKSYS_DIV128        CFG0_AHBPSC(13)               /*!< AHB prescaler select CK_SYS/128 */
+#define RCU_AHB_CKSYS_DIV256        CFG0_AHBPSC(14)               /*!< AHB prescaler select CK_SYS/256 */
+#define RCU_AHB_CKSYS_DIV512        CFG0_AHBPSC(15)               /*!< AHB prescaler select CK_SYS/512 */
+
+/* APB1 prescaler selection */
+#define CFG0_APB1PSC(regval)        (BITS(8,10) & ((uint32_t)(regval) << 8))
+#define RCU_APB1_CKAHB_DIV1         CFG0_APB1PSC(0)               /*!< APB1 prescaler select CK_AHB */
+#define RCU_APB1_CKAHB_DIV2         CFG0_APB1PSC(4)               /*!< APB1 prescaler select CK_AHB/2 */
+#define RCU_APB1_CKAHB_DIV4         CFG0_APB1PSC(5)               /*!< APB1 prescaler select CK_AHB/4 */
+#define RCU_APB1_CKAHB_DIV8         CFG0_APB1PSC(6)               /*!< APB1 prescaler select CK_AHB/8 */
+#define RCU_APB1_CKAHB_DIV16        CFG0_APB1PSC(7)               /*!< APB1 prescaler select CK_AHB/16 */
+
+/* APB2 prescaler selection */
+#define CFG0_APB2PSC(regval)        (BITS(11,13) & ((uint32_t)(regval) << 11))
+#define RCU_APB2_CKAHB_DIV1         CFG0_APB2PSC(0)               /*!< APB2 prescaler select CK_AHB */
+#define RCU_APB2_CKAHB_DIV2         CFG0_APB2PSC(4)               /*!< APB2 prescaler select CK_AHB/2 */
+#define RCU_APB2_CKAHB_DIV4         CFG0_APB2PSC(5)               /*!< APB2 prescaler select CK_AHB/4 */
+#define RCU_APB2_CKAHB_DIV8         CFG0_APB2PSC(6)               /*!< APB2 prescaler select CK_AHB/8 */
+#define RCU_APB2_CKAHB_DIV16        CFG0_APB2PSC(7)               /*!< APB2 prescaler select CK_AHB/16 */
+
+/* ADC clock prescaler selection */
+#define CFG0_ADCPSC(regval)         (BITS(14,15) & ((uint32_t)(regval) << 14))
+#define RCU_ADC_CKAPB2_DIV2         CFG0_ADCPSC(0)                /*!< ADC clock prescaler select CK_APB2/2 */
+#define RCU_ADC_CKAPB2_DIV4         CFG0_ADCPSC(1)                /*!< ADC clock prescaler select CK_APB2/4 */
+#define RCU_ADC_CKAPB2_DIV6         CFG0_ADCPSC(2)                /*!< ADC clock prescaler select CK_APB2/6 */
+#define RCU_ADC_CKAPB2_DIV8         CFG0_ADCPSC(3)                /*!< ADC clock prescaler select CK_APB2/8 */
+
+/* PLL clock source selection */
+#define RCU_PLLSRC_IRC8M_DIV2       (uint32_t)0x00000000U         /*!< PLL clock source select IRC8M/2 */
+#define RCU_PLLSRC_HXTAL            RCU_CFG0_PLLSEL               /*!< PLL clock source select HXTAL */
+
+/* HXTAL divider for PLL source clock selection */
+#define RCU_PLLPREDV                (uint32_t)0x00000000U         /*!< HXTAL clock selected */
+#define RCU_PLLPREDV_DIV2           RCU_CFG0_PLLPREDV             /*!< HXTAL/2 clock selected */
+
+/* PLL multiply factor */
+#define CFG0_PLLMF(regval)          (BITS(18,21) & ((uint32_t)(regval) << 18))
+#define RCU_PLL_MUL2                CFG0_PLLMF(0)                       /*!< PLL source clock multiply by 2 */
+#define RCU_PLL_MUL3                CFG0_PLLMF(1)                       /*!< PLL source clock multiply by 3 */
+#define RCU_PLL_MUL4                CFG0_PLLMF(2)                       /*!< PLL source clock multiply by 4 */
+#define RCU_PLL_MUL5                CFG0_PLLMF(3)                       /*!< PLL source clock multiply by 5 */
+#define RCU_PLL_MUL6                CFG0_PLLMF(4)                       /*!< PLL source clock multiply by 6 */
+#define RCU_PLL_MUL7                CFG0_PLLMF(5)                       /*!< PLL source clock multiply by 7 */
+#define RCU_PLL_MUL8                CFG0_PLLMF(6)                       /*!< PLL source clock multiply by 8 */
+#define RCU_PLL_MUL9                CFG0_PLLMF(7)                       /*!< PLL source clock multiply by 9 */
+#define RCU_PLL_MUL10               CFG0_PLLMF(8)                       /*!< PLL source clock multiply by 10 */
+#define RCU_PLL_MUL11               CFG0_PLLMF(9)                       /*!< PLL source clock multiply by 11 */
+#define RCU_PLL_MUL12               CFG0_PLLMF(10)                      /*!< PLL source clock multiply by 12 */
+#define RCU_PLL_MUL13               CFG0_PLLMF(11)                      /*!< PLL source clock multiply by 13 */
+#define RCU_PLL_MUL14               CFG0_PLLMF(12)                      /*!< PLL source clock multiply by 14 */
+#define RCU_PLL_MUL15               CFG0_PLLMF(13)                      /*!< PLL source clock multiply by 15 */
+#define RCU_PLL_MUL16               CFG0_PLLMF(14)                      /*!< PLL source clock multiply by 16 */
+#define RCU_PLL_MUL17               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0))   /*!< PLL source clock multiply by 17 */
+#define RCU_PLL_MUL18               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1))   /*!< PLL source clock multiply by 18 */
+#define RCU_PLL_MUL19               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2))   /*!< PLL source clock multiply by 19 */
+#define RCU_PLL_MUL20               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3))   /*!< PLL source clock multiply by 20 */
+#define RCU_PLL_MUL21               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4))   /*!< PLL source clock multiply by 21 */
+#define RCU_PLL_MUL22               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5))   /*!< PLL source clock multiply by 22 */
+#define RCU_PLL_MUL23               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6))   /*!< PLL source clock multiply by 23 */
+#define RCU_PLL_MUL24               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7))   /*!< PLL source clock multiply by 24 */
+#define RCU_PLL_MUL25               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8))   /*!< PLL source clock multiply by 25 */
+#define RCU_PLL_MUL26               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9))   /*!< PLL source clock multiply by 26 */
+#define RCU_PLL_MUL27               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10))  /*!< PLL source clock multiply by 27 */
+#define RCU_PLL_MUL28               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11))  /*!< PLL source clock multiply by 28 */
+#define RCU_PLL_MUL29               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12))  /*!< PLL source clock multiply by 29 */
+#define RCU_PLL_MUL30               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13))  /*!< PLL source clock multiply by 30 */
+#define RCU_PLL_MUL31               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14))  /*!< PLL source clock multiply by 31 */
+#define RCU_PLL_MUL32               (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15))  /*!< PLL source clock multiply by 32 */
+
+/* CK_OUT clock source selection */
+#define CFG0_CKOUTSEL(regval)       (BITS(24,26) & ((uint32_t)(regval) << 24))
+#define RCU_CKOUTSRC_NONE           CFG0_CKOUTSEL(0)                    /*!< no clock selected */
+#define RCU_CKOUTSRC_IRC28M         CFG0_CKOUTSEL(1)                    /*!< CK_OUT clock source select IRC28M */
+#define RCU_CKOUTSRC_IRC40K         CFG0_CKOUTSEL(2)                    /*!< CK_OUT clock source select IRC40K */
+#define RCU_CKOUTSRC_LXTAL          CFG0_CKOUTSEL(3)                    /*!< CK_OUT clock source select LXTAL */
+#define RCU_CKOUTSRC_CKSYS          CFG0_CKOUTSEL(4)                    /*!< CK_OUT clock source select CKSYS */
+#define RCU_CKOUTSRC_IRC8M          CFG0_CKOUTSEL(5)                    /*!< CK_OUT clock source select IRC8M */
+#define RCU_CKOUTSRC_HXTAL          CFG0_CKOUTSEL(6)                    /*!< CK_OUT clock source select HXTAL */
+#define RCU_CKOUTSRC_CKPLL_DIV1     (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */
+#define RCU_CKOUTSRC_CKPLL_DIV2     CFG0_CKOUTSEL(7)                    /*!< CK_OUT clock source select CK_PLL/2 */
+
+/* CK_OUT divider */
+#define CFG0_CKOUTDIV(regval)       (BITS(28,30) & ((uint32_t)(regval) << 28))
+#define RCU_CKOUT_DIV1              CFG0_CKOUTDIV(0)                    /*!< CK_OUT is divided by 1 */
+#define RCU_CKOUT_DIV2              CFG0_CKOUTDIV(1)                    /*!< CK_OUT is divided by 2 */
+#define RCU_CKOUT_DIV4              CFG0_CKOUTDIV(2)                    /*!< CK_OUT is divided by 4 */
+#define RCU_CKOUT_DIV8              CFG0_CKOUTDIV(3)                    /*!< CK_OUT is divided by 8 */
+#define RCU_CKOUT_DIV16             CFG0_CKOUTDIV(4)                    /*!< CK_OUT is divided by 16 */
+#define RCU_CKOUT_DIV32             CFG0_CKOUTDIV(5)                    /*!< CK_OUT is divided by 32 */
+#define RCU_CKOUT_DIV64             CFG0_CKOUTDIV(6)                    /*!< CK_OUT is divided by 64 */
+#define RCU_CKOUT_DIV128            CFG0_CKOUTDIV(7)                    /*!< CK_OUT is divided by 128 */
+
+/* CK_PLL divide by 1 or 2 for CK_OUT */
+#define RCU_PLLDV_CKPLL_DIV2        (uint32_t)0x00000000U               /*!< CK_PLL divide by 2 for CK_OUT */
+#define RCU_PLLDV_CKPLL             RCU_CFG0_PLLDV                      /*!< CK_PLL divide by 1 for CK_OUT */
+
+/* LXTAL drive capability */
+#define BDCTL_LXTALDRI(regval)      (BITS(3,4) & ((uint32_t)(regval) << 3))
+#define RCU_LXTAL_LOWDRI            BDCTL_LXTALDRI(0)                   /*!< lower driving capability */
+#define RCU_LXTAL_MED_LOWDRI        BDCTL_LXTALDRI(1)                   /*!< medium low driving capability */
+#define RCU_LXTAL_MED_HIGHDRI       BDCTL_LXTALDRI(2)                   /*!< medium high driving capability */
+#define RCU_LXTAL_HIGHDRI           BDCTL_LXTALDRI(3)                   /*!< higher driving capability */
+
+/* RTC clock entry selection */
+#define BDCTL_RTCSRC(regval)        (BITS(8,9) & ((uint32_t)(regval) << 8))
+#define RCU_RTCSRC_NONE             BDCTL_RTCSRC(0)                     /*!< no clock selected */
+#define RCU_RTCSRC_LXTAL            BDCTL_RTCSRC(1)                     /*!< LXTAL selected as RTC source clock */
+#define RCU_RTCSRC_IRC40K           BDCTL_RTCSRC(2)                     /*!< IRC40K selected as RTC source clock */
+#define RCU_RTCSRC_HXTAL_DIV32      BDCTL_RTCSRC(3)                     /*!< HXTAL/32 selected as RTC source clock */
+
+/* CK_HXTAL divider previous PLL */
+#define CFG1_PREDV(regval)         (BITS(0,3) & ((uint32_t)(regval) << 0))
+#define RCU_PLL_PREDV1              CFG1_PREDV(0)                       /*!< PLL not divided */
+#define RCU_PLL_PREDV2              CFG1_PREDV(1)                       /*!< PLL divided by 2 */
+#define RCU_PLL_PREDV3              CFG1_PREDV(2)                       /*!< PLL divided by 3 */
+#define RCU_PLL_PREDV4              CFG1_PREDV(3)                       /*!< PLL divided by 4 */
+#define RCU_PLL_PREDV5              CFG1_PREDV(4)                       /*!< PLL divided by 5 */
+#define RCU_PLL_PREDV6              CFG1_PREDV(5)                       /*!< PLL divided by 6 */
+#define RCU_PLL_PREDV7              CFG1_PREDV(6)                       /*!< PLL divided by 7 */
+#define RCU_PLL_PREDV8              CFG1_PREDV(7)                       /*!< PLL divided by 8 */
+#define RCU_PLL_PREDV9              CFG1_PREDV(8)                       /*!< PLL divided by 9 */
+#define RCU_PLL_PREDV10             CFG1_PREDV(9)                       /*!< PLL divided by 10 */
+#define RCU_PLL_PREDV11             CFG1_PREDV(10)                      /*!< PLL divided by 11 */
+#define RCU_PLL_PREDV12             CFG1_PREDV(11)                      /*!< PLL divided by 12 */
+#define RCU_PLL_PREDV13             CFG1_PREDV(12)                      /*!< PLL divided by 13 */
+#define RCU_PLL_PREDV14             CFG1_PREDV(13)                      /*!< PLL divided by 14 */
+#define RCU_PLL_PREDV15             CFG1_PREDV(14)                      /*!< PLL divided by 15 */
+#define RCU_PLL_PREDV16             CFG1_PREDV(15)                      /*!< PLL divided by 16 */
+
+/* USART0 clock source selection */
+#define CFG2_USART0SEL(regval)      (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_USART0SRC_CKAPB2        CFG2_USART0SEL(0)                   /*!< CK_USART0 select CK_APB2 */
+#define RCU_USART0SRC_CKSYS         CFG2_USART0SEL(1)                   /*!< CK_USART0 select CK_SYS */
+#define RCU_USART0SRC_LXTAL         CFG2_USART0SEL(2)                   /*!< CK_USART0 select LXTAL */
+#define RCU_USART0SRC_IRC8M         CFG2_USART0SEL(3)                   /*!< CK_USART0 select IRC8M */
+
+/* ADC clock source selection */
+#define RCU_ADCSRC_IRC28M           (uint32_t)0x00000000U               /*!< ADC clock source select */
+#define RCU_ADCSRC_AHB_APB2DIV      RCU_CFG2_ADCSEL                     /*!< ADC clock source select */
+
+/* IRC28M clock divider for ADC */
+#define RCU_ADC_IRC28M_DIV2         (uint32_t)0x00000000U               /*!< IRC28M/2 select to ADC clock */
+#define RCU_ADC_IRC28M_DIV1         RCU_CFG2_IRC28MDIV                  /*!< IRC28M select to ADC clock */
+
+/* Deep-sleep mode voltage */
+#define DSV_DSLPVS(regval)          (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_DEEPSLEEP_V_1_0         DSV_DSLPVS(0)                       /*!< core voltage is 1.0V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_0_9         DSV_DSLPVS(1)                       /*!< core voltage is 0.9V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_0_8         DSV_DSLPVS(2)                       /*!< core voltage is 0.8V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_1_2         DSV_DSLPVS(3)                       /*!< core voltage is 1.2V in deep-sleep mode */
+
+/* function declarations */
+/* deinitialize the RCU */
+void rcu_deinit(void);
+/* enable the peripherals clock */
+void rcu_periph_clock_enable(rcu_periph_enum periph);
+/* disable the peripherals clock */
+void rcu_periph_clock_disable(rcu_periph_enum periph);
+/* enable the peripherals clock when sleep mode */
+void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
+/* disable the peripherals clock when sleep mode */
+void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
+/* reset the peripherals */
+void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
+/* disable reset the peripheral */
+void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
+/* reset the BKP */
+void rcu_bkp_reset_enable(void);
+/* disable the BKP reset */
+void rcu_bkp_reset_disable(void);
+
+/* configure the system clock source */
+void rcu_system_clock_source_config(uint32_t ck_sys);
+/* get the system clock source */
+uint32_t rcu_system_clock_source_get(void);
+/* configure the AHB prescaler selection */
+void rcu_ahb_clock_config(uint32_t ck_ahb);
+/* configure the APB1 prescaler selection */
+void rcu_apb1_clock_config(uint32_t ck_apb1);
+/* configure the APB2 prescaler selection */
+void rcu_apb2_clock_config(uint32_t ck_apb2);
+/* configure the ADC clock source and prescaler selection */
+void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc);
+/* configure the CK_OUT clock source and divider */
+void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div);
+
+/* configure the PLL clock source selection and PLL multiply factor */
+void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
+/* configure the USART clock source selection */
+void rcu_usart_clock_config(uint32_t ck_usart);
+/* configure the RTC clock source selection */
+void rcu_rtc_clock_config(uint32_t rtc_clock_source);
+/* configure the HXTAL divider used as input of PLL */
+void rcu_hxtal_prediv_config(uint32_t hxtal_prediv);
+/* configure the LXTAL drive capability */
+void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
+
+/* get the clock stabilization and periphral reset flags */
+FlagStatus rcu_flag_get(rcu_flag_enum flag);
+/* clear the reset flag */
+void rcu_all_reset_flag_clear(void);
+/* get the clock stabilization interrupt and ckm flags */
+FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
+/* clear the interrupt flags */
+void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
+/* enable the stabilization interrupt */
+void rcu_interrupt_enable(rcu_int_enum stab_int);
+/* disable the stabilization interrupt */
+void rcu_interrupt_disable(rcu_int_enum stab_int);
+
+/* wait until oscillator stabilization flags is SET */
+ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
+/* turn on the oscillator */
+void rcu_osci_on(rcu_osci_type_enum osci);
+/* turn off the oscillator */
+void rcu_osci_off(rcu_osci_type_enum osci);
+/* enable the oscillator bypass mode */
+void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
+/* disable the oscillator bypass mode */
+void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
+/* enable the HXTAL clock monitor */
+void rcu_hxtal_clock_monitor_enable(void);
+/* disable the HXTAL clock monitor */
+void rcu_hxtal_clock_monitor_disable(void);
+
+/* set the IRC8M adjust value */
+void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
+/* set the IRC28M adjust value */
+void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval);
+/* unlock the voltage key */
+void rcu_voltage_key_unlock(void);
+/* set the deep sleep mode voltage */
+void rcu_deepsleep_voltage_set(uint32_t dsvol);
+
+/* get the system clock, bus and peripheral clock frequency */
+uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
+
+#endif /* GD32E230_RCU_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rtc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rtc.h
new file mode 100644
index 0000000000..27756b1609
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rtc.h
@@ -0,0 +1,561 @@
+/*!
+    \file  gd32e230_rtc.h
+    \brief definitions for the RTC 
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_RTC_H
+#define GD32E230_RTC_H
+
+#include "gd32e230.h"
+
+/* RTC definitions */
+#define RTC                                RTC_BASE
+
+/* registers definitions */
+#define RTC_TIME                           REG32((RTC) + 0x00000000U)                  /*!< RTC time of day register */
+#define RTC_DATE                           REG32((RTC) + 0x00000004U)                  /*!< RTC date register */
+#define RTC_CTL                            REG32((RTC) + 0x00000008U)                  /*!< RTC control register */
+#define RTC_STAT                           REG32((RTC) + 0x0000000CU)                  /*!< RTC status register */
+#define RTC_PSC                            REG32((RTC) + 0x00000010U)                  /*!< RTC time prescaler register */
+#define RTC_ALRM0TD                        REG32((RTC) + 0x0000001CU)                  /*!< RTC alarm 0 time and date register */
+#define RTC_WPK                            REG32((RTC) + 0x00000024U)                  /*!< RTC write protection key register */
+#define RTC_SS                             REG32((RTC) + 0x00000028U)                  /*!< RTC sub second register */
+#define RTC_SHIFTCTL                       REG32((RTC) + 0x0000002CU)                  /*!< RTC shift function control register */
+#define RTC_TTS                            REG32((RTC) + 0x00000030U)                  /*!< RTC time of timestamp register */
+#define RTC_DTS                            REG32((RTC) + 0x00000034U)                  /*!< RTC date of timestamp register */
+#define RTC_SSTS                           REG32((RTC) + 0x00000038U)                  /*!< RTC sub second of timestamp register */
+#define RTC_HRFC                           REG32((RTC) + 0x0000003CU)                  /*!< RTC high resolution frequency compensation registor */
+#define RTC_TAMP                           REG32((RTC) + 0x00000040U)                  /*!< RTC tamper register */
+#define RTC_ALRM0SS                        REG32((RTC) + 0x00000044U)                  /*!< RTC alarm 0 sub second register */
+#define RTC_BKP0                           REG32((RTC) + 0x00000050U)                  /*!< RTC backup 0 register */
+#define RTC_BKP1                           REG32((RTC) + 0x00000054U)                  /*!< RTC backup 1 register */
+#define RTC_BKP2                           REG32((RTC) + 0x00000058U)                  /*!< RTC backup 2 register */
+#define RTC_BKP3                           REG32((RTC) + 0x0000005CU)                  /*!< RTC backup 3 register */
+#define RTC_BKP4                           REG32((RTC) + 0x00000060U)                  /*!< RTC backup 4 register */
+
+/* bits definitions */
+/* RTC_TIME */
+#define RTC_TIME_SCU                       BITS(0,3)                                   /*!< second units in BCD code */
+#define RTC_TIME_SCT                       BITS(4,6)                                   /*!< second tens in BCD code */
+#define RTC_TIME_MNU                       BITS(8,11)                                  /*!< minute units in BCD code */
+#define RTC_TIME_MNT                       BITS(12,14)                                 /*!< minute tens in BCD code */
+#define RTC_TIME_HRU                       BITS(16,19)                                 /*!< hour units in BCD code */
+#define RTC_TIME_HRT                       BITS(20,21)                                 /*!< hour tens in BCD code */
+#define RTC_TIME_PM                        BIT(22)                                     /*!< AM/PM notation */
+
+/* RTC_DATE */
+#define RTC_DATE_DAYU                      BITS(0,3)                                   /*!< date units in BCD code */
+#define RTC_DATE_DAYT                      BITS(4,5)                                   /*!< date tens in BCD code */
+#define RTC_DATE_MONU                      BITS(8,11)                                  /*!< month units in BCD code */
+#define RTC_DATE_MONT                      BIT(12)                                     /*!< month tens in BCD code */
+#define RTC_DATE_DOW                       BITS(13,15)                                 /*!< day of week units */
+#define RTC_DATE_YRU                       BITS(16,19)                                 /*!< year units in BCD code */
+#define RTC_DATE_YRT                       BITS(20,23)                                 /*!< year tens in BCD code */
+
+/* RTC_CTL */
+#define RTC_CTL_TSEG                       BIT(3)                                      /*!< valid event edge of time-stamp */
+#define RTC_CTL_REFEN                      BIT(4)                                      /*!< reference clock detection function enable */
+#define RTC_CTL_BPSHAD                     BIT(5)                                      /*!< shadow registers bypass control */
+#define RTC_CTL_CS                         BIT(6)                                      /*!< display format of clock system */
+#define RTC_CTL_ALRM0EN                    BIT(8)                                      /*!< alarm function enable */
+#define RTC_CTL_TSEN                       BIT(11)                                     /*!< time-stamp function enable */
+#define RTC_CTL_ALRM0IE                    BIT(12)                                     /*!< RTC alarm interrupt enable */
+#define RTC_CTL_TSIE                       BIT(15)                                     /*!< time-stamp interrupt enable */
+#define RTC_CTL_A1H                        BIT(16)                                     /*!< add 1 hour(summer time change) */
+#define RTC_CTL_S1H                        BIT(17)                                     /*!< subtract 1 hour(winter time change) */
+#define RTC_CTL_DSM                        BIT(18)                                     /*!< daylight saving mark */
+#define RTC_CTL_COS                        BIT(19)                                     /*!< calibration output selection */
+#define RTC_CTL_OPOL                       BIT(20)                                     /*!< output polarity */
+#define RTC_CTL_OS                         BITS(21,22)                                 /*!< output selection */
+#define RTC_CTL_COEN                       BIT(23)                                     /*!< calibration output enable */
+
+/* RTC_STAT */
+#define RTC_STAT_ALRM0WF                   BIT(0)                                      /*!< alarm configuration can be write flag */
+#define RTC_STAT_SOPF                      BIT(3)                                      /*!< shift function operation pending flag */
+#define RTC_STAT_YCM                       BIT(4)                                      /*!< year configuration mark status flag */
+#define RTC_STAT_RSYNF                     BIT(5)                                      /*!< register synchronization flag */
+#define RTC_STAT_INITF                     BIT(6)                                      /*!< initialization state flag */
+#define RTC_STAT_INITM                     BIT(7)                                      /*!< enter initialization mode */
+#define RTC_STAT_ALRM0F                    BIT(8)                                      /*!< alarm occurs flag */
+#define RTC_STAT_TSF                       BIT(11)                                     /*!< time-stamp flag */
+#define RTC_STAT_TSOVRF                    BIT(12)                                     /*!< time-stamp overflow flag */
+#define RTC_STAT_TP0F                      BIT(13)                                     /*!< RTC tamp 0 detected flag */
+#define RTC_STAT_TP1F                      BIT(14)                                     /*!< RTC tamp 1 detected flag */
+#define RTC_STAT_SCPF                      BIT(16)                                     /*!< recalibration pending flag */
+
+/* RTC_PSC */
+#define RTC_PSC_FACTOR_S                   BITS(0,14)                                  /*!< synchronous prescaler factor */
+#define RTC_PSC_FACTOR_A                   BITS(16,22)                                 /*!< asynchronous prescaler factor */
+
+/* RTC_ALRM0TD */
+#define RTC_ALRM0TD_SCU                    BITS(0,3)                                   /*!< second units in BCD code */
+#define RTC_ALRM0TD_SCT                    BITS(4,6)                                   /*!< second tens in BCD code */
+#define RTC_ALRM0TD_MSKS                   BIT(7)                                      /*!< alarm second mask bit */
+#define RTC_ALRM0TD_MNU                    BITS(8,11)                                  /*!< minutes units in BCD code */
+#define RTC_ALRM0TD_MNT                    BITS(12,14)                                 /*!< minutes tens in BCD code */
+#define RTC_ALRM0TD_MSKM                   BIT(15)                                     /*!< alarm minutes mask bit */
+#define RTC_ALRM0TD_HRU                    BITS(16,19)                                 /*!< hour units in BCD code */
+#define RTC_ALRM0TD_HRT                    BITS(20,21)                                 /*!< hour units in BCD code */
+#define RTC_ALRM0TD_PM                     BIT(22)                                     /*!< AM/PM flag */
+#define RTC_ALRM0TD_MSKH                   BIT(23)                                     /*!< alarm hour mask bit */
+#define RTC_ALRM0TD_DAYU                   BITS(24,27)                                 /*!< date units or week day in BCD code */
+#define RTC_ALRM0TD_DAYT                   BITS(28,29)                                 /*!< date tens in BCD code */
+#define RTC_ALRM0TD_DOWS                   BIT(30)                                     /*!< day of week  selection */
+#define RTC_ALRM0TD_MSKD                   BIT(31)                                     /*!< alarm date mask bit */
+
+/* RTC_WPK */
+#define RTC_WPK_WPK                        BITS(0,7)                                   /*!< key for write protection */
+
+/* RTC_SS */
+#define RTC_SS_SSC                         BITS(0,15)                                  /*!< sub second value */
+
+/* RTC_SHIFTCTL */
+#define RTC_SHIFTCTL_SFS                   BITS(0,14)                                  /*!< subtract a fraction of a second */
+#define RTC_SHIFTCTL_A1S                   BIT(31)                                     /*!< one second add */
+
+/* RTC_TTS */
+#define RTC_TTS_SCU                        BITS(0,3)                                   /*!< second units in BCD code */
+#define RTC_TTS_SCT                        BITS(4,6)                                   /*!< second units in BCD code */
+#define RTC_TTS_MNU                        BITS(8,11)                                  /*!< minute units in BCD code */
+#define RTC_TTS_MNT                        BITS(12,14)                                 /*!< minute tens in BCD code */
+#define RTC_TTS_HRU                        BITS(16,19)                                 /*!< hour units in BCD code */
+#define RTC_TTS_HRT                        BITS(20,21)                                 /*!< hour tens in BCD code */
+#define RTC_TTS_PM                         BIT(22)                                     /*!< AM/PM notation */
+
+/* RTC_DTS */
+#define RTC_DTS_DAYU                       BITS(0,3)                                   /*!< date units in BCD code */
+#define RTC_DTS_DAYT                       BITS(4,5)                                   /*!< date tens in BCD code */
+#define RTC_DTS_MONU                       BITS(8,11)                                  /*!< month units in BCD code */
+#define RTC_DTS_MONT                       BIT(12)                                     /*!< month tens in BCD code */
+#define RTC_DTS_DOW                        BITS(13,15)                                 /*!< day of week units */
+
+/* RTC_SSTS */
+#define RTC_SSTS_SSC                       BITS(0,15)                                  /*!< timestamp sub second units */
+
+/* RTC_HRFC */
+#define RTC_HRFC_CMSK                      BITS(0,8)                                   /*!< calibration mask number */
+#define RTC_HRFC_CWND16                    BIT(13)                                     /*!< calibration window select 16 seconds */
+#define RTC_HRFC_CWND8                     BIT(14)                                     /*!< calibration window select 16 seconds */
+#define RTC_HRFC_FREQI                     BIT(15)                                     /*!< increase RTC frequency by 488.5ppm */
+
+/* RTC_TAMP */
+#define RTC_TAMP_TP0EN                     BIT(0)                                      /*!< tamper 0 detection enable */
+#define RTC_TAMP_TP0EG                     BIT(1)                                      /*!< tamper 0 event trigger edge for RTC tamp 0 input */
+#define RTC_TAMP_TPIE                      BIT(2)                                      /*!< tamper detection interrupt enable */
+#define RTC_TAMP_TP1EN                     BIT(3)                                      /*!< tamper 1 detection enable */
+#define RTC_TAMP_TP1EG                     BIT(4)                                      /*!< tamper 1 event trigger edge for RTC tamp 1 input */
+#define RTC_TAMP_TPTS                      BIT(7)                                      /*!< make tamper function used for timestamp function */
+#define RTC_TAMP_FREQ                      BITS(8,10)                                  /*!< sample frequency of tamper event detection */
+#define RTC_TAMP_FLT                       BITS(11,12)                                 /*!< RTC tamp x filter count setting */
+#define RTC_TAMP_PRCH                      BITS(13,14)                                 /*!< precharge duration time of RTC tamp x */
+#define RTC_TAMP_DISPU                     BIT(15)                                     /*!< RTC tamp x pull up disable bit */
+#define RTC_TAMP_PC13VAL                   BIT(18)                                     /*!< alarm output type control/PC13 output value */
+#define RTC_TAMP_PC13MDE                   BIT(19)                                     /*!< PC13 mode */
+#define RTC_TAMP_PC14VAL                   BIT(20)                                     /*!< PC14 output value */
+#define RTC_TAMP_PC14MDE                   BIT(21)                                     /*!< PC14 mode */
+#define RTC_TAMP_PC15VAL                   BIT(22)                                     /*!< PC15 output value */
+#define RTC_TAMP_PC15MDE                   BIT(23)                                     /*!< PC15 mode */
+
+/* RTC_ALRM0SS */
+#define RTC_ALRM0SS_SSC                    BITS(0,14)                                  /*!< alarm sub second value */
+#define RTC_ALRM0SS_MASKSSC                BITS(24,27)                                 /*!< mask control bit of SS */
+
+/* RTC_BKP0 */
+#define RTC_BKP0_DATA                      BITS(0,31)                                  /*!< backup domain registers */
+
+/* RTC_BKP1 */
+#define RTC_BKP1_DATA                      BITS(0,31)                                  /*!< backup domain registers */
+
+/* RTC_BKP2 */
+#define RTC_BKP2_DATA                      BITS(0,31)                                  /*!< backup domain registers */
+
+/* RTC_BKP3 */
+#define RTC_BKP3_DATA                      BITS(0,31)                                  /*!< backup domain registers */
+
+/* RTC_BKP4 */
+#define RTC_BKP4_DATA                      BITS(0,31)                                  /*!< backup domain registers */
+
+/* constants definitions */
+/* structure for initialization of the RTC */
+typedef struct
+{
+    uint8_t rtc_year;                                                                  /*!< RTC year value: 0x0 - 0x99(BCD format) */
+    uint8_t rtc_month;                                                                 /*!< RTC month value */
+    uint8_t rtc_date;                                                                  /*!< RTC date value: 0x1 - 0x31(BCD format) */
+    uint8_t rtc_day_of_week;                                                           /*!< RTC weekday value */
+    uint8_t rtc_hour;                                                                  /*!< RTC hour value */
+    uint8_t rtc_minute;                                                                /*!< RTC minute value: 0x0 - 0x59(BCD format) */
+    uint8_t rtc_second;                                                                /*!< RTC second value: 0x0 - 0x59(BCD format) */
+    uint16_t rtc_factor_asyn;                                                          /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
+    uint16_t rtc_factor_syn;                                                           /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
+    uint32_t rtc_am_pm;                                                                /*!< RTC AM/PM value */
+    uint32_t rtc_display_format;                                                       /*!< RTC time notation */
+}rtc_parameter_struct;
+
+/* structure for RTC alarm configuration */
+typedef struct
+{
+    uint32_t rtc_alarm_mask;                                                           /*!< RTC alarm mask */
+    uint32_t rtc_weekday_or_date;                                                      /*!< specify RTC alarm is on date or weekday */
+    uint8_t rtc_alarm_day;                                                             /*!< RTC alarm date or weekday value*/
+    uint8_t rtc_alarm_hour;                                                            /*!< RTC alarm hour value */
+    uint8_t rtc_alarm_minute;                                                          /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
+    uint8_t rtc_alarm_second;                                                          /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
+    uint32_t rtc_am_pm;                                                                /*!< RTC alarm AM/PM value */
+}rtc_alarm_struct;
+
+/* structure for RTC time-stamp configuration */
+typedef struct
+{
+    uint8_t rtc_timestamp_month;                                                       /*!< RTC time-stamp month value */
+    uint8_t rtc_timestamp_date;                                                        /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
+    uint8_t rtc_timestamp_day;                                                         /*!< RTC time-stamp weekday value */
+    uint8_t rtc_timestamp_hour;                                                        /*!< RTC time-stamp hour value */
+    uint8_t rtc_timestamp_minute;                                                      /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
+    uint8_t rtc_timestamp_second;                                                      /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
+    uint32_t rtc_am_pm;                                                                /*!< RTC time-stamp AM/PM value */
+}rtc_timestamp_struct;
+
+/* structure for RTC tamper configuration */
+typedef struct
+{
+    uint32_t rtc_tamper_source;                                                        /*!< RTC tamper source */
+    uint32_t rtc_tamper_trigger;                                                       /*!< RTC tamper trigger */
+    uint32_t rtc_tamper_filter;                                                        /*!< RTC tamper consecutive samples needed during a voltage level detection */
+    uint32_t rtc_tamper_sample_frequency;                                              /*!< RTC tamper sampling frequency during a voltage level detection */
+    ControlStatus rtc_tamper_precharge_enable;                                         /*!< RTC tamper precharge feature during a voltage level detection */
+    uint32_t rtc_tamper_precharge_time;                                                /*!< RTC tamper precharge duration if precharge feature is enabled */
+    ControlStatus rtc_tamper_with_timestamp;                                           /*!< RTC tamper time-stamp feature */
+}rtc_tamper_struct; 
+
+/* time register value */
+#define TIME_SC(regval)                    (BITS(0,6) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_TIME_SC bit field */
+#define GET_TIME_SC(regval)                GET_BITS((regval),0,6)                      /*!< get value of RTC_TIME_SC bit field */
+
+#define TIME_MN(regval)                    (BITS(8,14) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_TIME_MN bit field */
+#define GET_TIME_MN(regval)                GET_BITS((regval),8,14)                     /*!< get value of RTC_TIME_MN bit field */
+
+#define TIME_HR(regval)                    (BITS(16,21) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_TIME_HR bit field */
+#define GET_TIME_HR(regval)                GET_BITS((regval),16,21)                    /*!< get value of RTC_TIME_HR bit field */
+
+#define RTC_AM                             ((uint32_t)0x00000000U)                      /*!< AM format */
+#define RTC_PM                             RTC_TIME_PM                                 /*!< PM format */
+
+/* date register value */
+#define DATE_DAY(regval)                   (BITS(0,5) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_DATE_DAY bit field */
+#define GET_DATE_DAY(regval)               GET_BITS((regval),0,5)                      /*!< get value of RTC_DATE_DAY bit field */
+
+#define DATE_MON(regval)                   (BITS(8,12) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_DATE_MON bit field */
+#define GET_DATE_MON(regval)               GET_BITS((regval),8,12)                     /*!< get value of RTC_DATE_MON bit field */
+#define RTC_JAN                            ((uint8_t)0x01U)                            /*!< Janurary */
+#define RTC_FEB                            ((uint8_t)0x02U)                            /*!< February */
+#define RTC_MAR                            ((uint8_t)0x03U)                            /*!< March */
+#define RTC_APR                            ((uint8_t)0x04U)                            /*!< April */
+#define RTC_MAY                            ((uint8_t)0x05U)                            /*!< May */
+#define RTC_JUN                            ((uint8_t)0x06U)                            /*!< June */
+#define RTC_JUL                            ((uint8_t)0x07U)                            /*!< July */
+#define RTC_AUG                            ((uint8_t)0x08U)                            /*!< August */
+#define RTC_SEP                            ((uint8_t)0x09U)                            /*!< September */
+#define RTC_OCT                            ((uint8_t)0x10U)                            /*!< October */
+#define RTC_NOV                            ((uint8_t)0x11U)                            /*!< November */
+#define RTC_DEC                            ((uint8_t)0x12U)                            /*!< December */
+
+#define DATE_DOW(regval)                   (BITS(13,15) & ((uint32_t)(regval) << 13U))  /*!< write value to RTC_DATE_DOW bit field */
+#define GET_DATE_DOW(regval)               GET_BITS((regval),13,15)                    /*!< get value of RTC_DATE_DOW bit field */
+#define RTC_MONDAY                         ((uint8_t)0x01U)                            /*!< Monday */
+#define RTC_TUESDAY                        ((uint8_t)0x02U)                            /*!< Tuesday */
+#define RTC_WEDSDAY                        ((uint8_t)0x03U)                            /*!< Wednesday */
+#define RTC_THURSDAY                       ((uint8_t)0x04U)                            /*!< Thursday */
+#define RTC_FRIDAY                         ((uint8_t)0x05U)                            /*!< Friday */
+#define RTC_SATURDAY                       ((uint8_t)0x06U)                            /*!< Saturday */
+#define RTC_SUNDAY                         ((uint8_t)0x07U)                            /*!< Sunday */
+
+#define DATE_YR(regval)                    (BITS(16,23) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_DATE_YR bit field */
+#define GET_DATE_YR(regval)                GET_BITS((regval),16,23)                    /*!< get value of RTC_DATE_YR bit field */
+
+/* ctl register value */
+#define CTL_OS(regval)                     (BITS(21,22) & ((uint32_t)(regval) << 21U))   /*!< write value to RTC_CTL_OS bit field */
+#define RTC_OS_DISABLE                     CTL_OS(0)                                   /*!< disable output RTC_ALARM */
+#define RTC_OS_ENABLE                      CTL_OS(1)                                   /*!< enable alarm flag output */
+
+#define RTC_CALIBRATION_512HZ              RTC_CTL_COEN                                /*!< calibration output of 512Hz is enable */
+#define RTC_CALIBRATION_1HZ                (RTC_CTL_COEN | RTC_CTL_COS)                /*!< calibration output of 1Hz is enable */
+#define RTC_ALARM_HIGH                     RTC_CTL_OS                                  /*!< enable alarm flag output with high level */
+#define RTC_ALARM_LOW                      (RTC_CTL_OS | RTC_CTL_OPOL)                 /*!< enable alarm flag output with low level*/
+
+#define RTC_24HOUR                         ((uint32_t)0x00000000U)                     /*!< 24-hour format */
+#define RTC_12HOUR                         RTC_CTL_CS                                  /*!< 12-hour format */
+
+#define RTC_TIMESTAMP_RISING_EDGE          ((uint32_t)0x00000000U)                     /*!< rising edge is valid event edge for time-stamp event */
+#define RTC_TIMESTAMP_FALLING_EDGE         RTC_CTL_TSEG                                /*!< falling edge is valid event edge for time-stamp event */
+ 
+/* psc register value */
+#define PSC_FACTOR_S(regval)               (BITS(0,14) & ((uint32_t)(regval) << 0U))    /*!< write value to RTC_PSC_FACTOR_S bit field */
+#define GET_PSC_FACTOR_S(regval)           GET_BITS((regval),0,14)                     /*!< get value of RTC_PSC_FACTOR_S bit field */
+
+#define PSC_FACTOR_A(regval)               (BITS(16,22) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_PSC_FACTOR_A bit field */
+#define GET_PSC_FACTOR_A(regval)           GET_BITS((regval),16,22)                    /*!< get value of RTC_PSC_FACTOR_A bit field */
+
+/* alrm0td register value */
+#define ALRM0TD_SC(regval)                 (BITS(0,6) & ((uint32_t)(regval)<< 0U))      /*!< write value to RTC_ALRM0TD_SC bit field */
+#define GET_ALRM0TD_SC(regval)             GET_BITS((regval),0,6)                      /*!< get value of RTC_ALRM0TD_SC bit field */
+
+#define ALRM0TD_MN(regval)                 (BITS(8,14) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_ALRM0TD_MN bit field */
+#define GET_ALRM0TD_MN(regval)             GET_BITS((regval),8,14)                     /*!< get value of RTC_ALRM0TD_MN bit field */
+
+#define ALRM0TD_HR(regval)                 (BITS(16,21) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_ALRM0TD_HR bit field */
+#define GET_ALRM0TD_HR(regval)             GET_BITS((regval),16,21)                    /*!< get value of RTC_ALRM0TD_HR bit field */
+
+#define ALRM0TD_DAY(regval)                (BITS(24,29) & ((uint32_t)(regval) << 24U))  /*!< write value to RTC_ALRM0TD_DAY bit field */
+#define GET_ALRM0TD_DAY(regval)            GET_BITS((regval),24,29)                    /*!< get value of RTC_ALRM0TD_DAY bit field */
+
+#define RTC_ALARM_NONE_MASK                ((uint32_t)0x00000000U)                     /*!< alarm none mask */
+#define RTC_ALARM_DATE_MASK                RTC_ALRM0TD_MSKD                            /*!< alarm date mask */
+#define RTC_ALARM_HOUR_MASK                RTC_ALRM0TD_MSKH                            /*!< alarm hour mask */
+#define RTC_ALARM_MINUTE_MASK              RTC_ALRM0TD_MSKM                            /*!< alarm minute mask */
+#define RTC_ALARM_SECOND_MASK              RTC_ALRM0TD_MSKS                            /*!< alarm second mask */
+#define RTC_ALARM_ALL_MASK                 (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS)    /*!< alarm all mask */
+
+#define RTC_ALARM_DATE_SELECTED            ((uint32_t)0x00000000U)                     /*!< alarm date format selected */
+#define RTC_ALARM_WEEKDAY_SELECTED         RTC_ALRM0TD_DOWS                            /*!< alarm weekday format selected */
+
+/* wpk register value */
+#define WPK_WPK(regval)                    (BITS(0,7) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_WPK_WPK bit field */
+
+/* ss register value */
+#define SS_SSC(regval)                     (BITS(0,15) & ((uint32_t)(regval) << 0U))    /*!< write value to RTC_SS_SSC bit field */
+
+/* shiftctl register value */
+#define SHIFTCTL_SFS(regval)               (BITS(0,14) & ((uint32_t)(regval) << 0U))    /*!< write value to RTC_SHIFTCTL_SFS bit field */
+
+#define RTC_SHIFT_ADD1S_RESET              ((uint32_t)0x00000000U)                     /*!< not add 1 second */
+#define RTC_SHIFT_ADD1S_SET                RTC_SHIFTCTL_A1S                            /*!< add one second to the clock */
+
+/* tts register value */
+#define TTS_SC(regval)                     (BITS(0,6) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_TTS_SC bit field */
+#define GET_TTS_SC(regval)                 GET_BITS((regval),0,6)                      /*!< get value of RTC_TTS_SC bit field */
+
+#define TTS_MN(regval)                     (BITS(8,14) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_TTS_MN bit field */
+#define GET_TTS_MN(regval)                 GET_BITS((regval),8,14)                     /*!< get value of RTC_TTS_MN bit field */
+
+#define TTS_HR(regval)                     (BITS(16,21) & ((uint32_t)(regval) << 16U))  /*!< write value to RTC_TTS_HR bit field */
+#define GET_TTS_HR(regval)                 GET_BITS((regval),16,21)                    /*!< get value of RTC_TTS_HR bit field */
+
+/* dts register value */
+#define DTS_DAY(regval)                    (BITS(0,5) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_DTS_DAY bit field */
+#define GET_DTS_DAY(regval)                GET_BITS((regval),0,5)                      /*!< get value of RTC_DTS_DAY bit field */
+
+#define DTS_MON(regval)                    (BITS(8,12) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_DTS_MON bit field */
+#define GET_DTS_MON(regval)                GET_BITS((regval),8,12)                     /*!< get value of RTC_DTS_MON bit field */
+
+#define DTS_DOW(regval)                    (BITS(13,15) & ((uint32_t)(regval) << 13U))  /*!< write value to RTC_DTS_DOW bit field */
+#define GET_DTS_DOW(regval)                GET_BITS((regval),13,15)                    /*!< get value of RTC_DTS_DOW bit field */
+
+/* ssts register value */
+#define SSTS_SSC(regval)                   (BITS(0,15) & ((uint32_t)(regval) << 0U))    /*!< write value to RTC_SSTS_SSC bit field */
+
+/* hrfc register value */
+#define HRFC_CMSK(regval)                  (BITS(0,8) & ((uint32_t)(regval) << 0U))     /*!< write value to RTC_HRFC_CMSK bit field */
+
+#define RTC_CALIBRATION_WINDOW_32S         ((uint32_t)0x00000000U)                     /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
+#define RTC_CALIBRATION_WINDOW_16S         RTC_HRFC_CWND16                             /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
+#define RTC_CALIBRATION_WINDOW_8S          RTC_HRFC_CWND8                              /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
+
+#define RTC_CALIBRATION_PLUS_SET           RTC_HRFC_FREQI                              /*!< increase RTC frequency by 488.5ppm */
+#define RTC_CALIBRATION_PLUS_RESET         ((uint32_t)0x00000000U)                     /*!< no effect */
+
+/* tamp register value */
+#define TAMP_FREQ(regval)                  (BITS(8,10) & ((uint32_t)(regval) << 8U))    /*!< write value to RTC_TAMP_FREQ bit field */
+#define RTC_FREQ_DIV32768                  TAMP_FREQ(0)                                /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV16384                  TAMP_FREQ(1)                                /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV8192                   TAMP_FREQ(2)                                /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV4096                   TAMP_FREQ(3)                                /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV2048                   TAMP_FREQ(4)                                /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV1024                   TAMP_FREQ(5)                                /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV512                    TAMP_FREQ(6)                                /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
+#define RTC_FREQ_DIV256                    TAMP_FREQ(7)                                /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
+
+#define TAMP_FLT(regval)                   (BITS(11,12) & ((uint32_t)(regval) << 11U))  /*!< write value to RTC_TAMP_FLT bit field */
+#define RTC_FLT_EDGE                       TAMP_FLT(0)                                 /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
+#define RTC_FLT_2S                         TAMP_FLT(1)                                 /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event  */
+#define RTC_FLT_4S                         TAMP_FLT(2)                                 /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
+#define RTC_FLT_8S                         TAMP_FLT(3)                                 /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event  */
+
+#define TAMP_PRCH(regval)                  (BITS(13,14) & ((uint32_t)(regval) << 13U))  /*!< write value to RTC_TAMP_PRCH bit field */
+#define RTC_PRCH_1C                        TAMP_PRCH(0)                                /*!< 1 RTC clock prechagre time before each sampling */
+#define RTC_PRCH_2C                        TAMP_PRCH(1)                                /*!< 2 RTC clock prechagre time before each sampling  */
+#define RTC_PRCH_4C                        TAMP_PRCH(2)                                /*!< 4 RTC clock prechagre time before each sampling */
+#define RTC_PRCH_8C                        TAMP_PRCH(3)                                /*!< 8 RTC clock prechagre time before each sampling */
+
+#define RTC_TAMPER0                        RTC_TAMP_TP0EN                              /*!< tamper 0 detection enable */
+#define RTC_TAMPER1                        RTC_TAMP_TP1EN                              /*!< tamper 1 detection enable */
+
+#define RTC_TAMPER_TRIGGER_EDGE_RISING     ((uint32_t)0x00000000U)                     /*!< tamper detection is in rising edge mode */
+#define RTC_TAMPER_TRIGGER_EDGE_FALLING    RTC_TAMP_TP0EG                              /*!< tamper detection is in falling edge mode */
+#define RTC_TAMPER_TRIGGER_LEVEL_LOW       ((uint32_t)0x00000000U)                     /*!< tamper detection is in low level mode */
+#define RTC_TAMPER_TRIGGER_LEVEL_HIGH      RTC_TAMP_TP0EG                              /*!< tamper detection is in high level mode */
+
+#define RTC_TAMPER_TRIGGER_POS             ((uint32_t)0x00000001U)                     /* shift position of trigger relative to source */
+
+#define RTC_ALARM_OUTPUT_OD                ((uint32_t)0x00000000U)                     /*!< RTC alarm output open-drain mode */
+#define RTC_ALARM_OUTPUT_PP                RTC_TAMP_PC13VAL                            /*!< RTC alarm output push-pull mode */
+
+/* alrm0ss register value */
+#define ALRM0SS_SSC(regval)                (BITS(0,14) & ((uint32_t)(regval)<< 0U))     /*!< write value to RTC_ALRM0SS_SSC bit field */
+
+#define ALRM0SS_MASKSSC(regval)            (BITS(24,27) & ((uint32_t)(regval) << 24U))  /*!< write value to RTC_ALRM0SS_MASKSSC bit field */
+#define RTC_MASKSSC_0_14                   ALRM0SS_MASKSSC(0)                          /*!< mask alarm subsecond configuration */
+#define RTC_MASKSSC_1_14                   ALRM0SS_MASKSSC(1)                          /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */
+#define RTC_MASKSSC_2_14                   ALRM0SS_MASKSSC(2)                          /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */
+#define RTC_MASKSSC_3_14                   ALRM0SS_MASKSSC(3)                          /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */
+#define RTC_MASKSSC_4_14                   ALRM0SS_MASKSSC(4)                          /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */
+#define RTC_MASKSSC_5_14                   ALRM0SS_MASKSSC(5)                          /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */
+#define RTC_MASKSSC_6_14                   ALRM0SS_MASKSSC(6)                          /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */
+#define RTC_MASKSSC_7_14                   ALRM0SS_MASKSSC(7)                          /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */
+#define RTC_MASKSSC_8_14                   ALRM0SS_MASKSSC(8)                          /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */
+#define RTC_MASKSSC_9_14                   ALRM0SS_MASKSSC(9)                          /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */
+#define RTC_MASKSSC_10_14                  ALRM0SS_MASKSSC(10)                         /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */
+#define RTC_MASKSSC_11_14                  ALRM0SS_MASKSSC(11)                         /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */
+#define RTC_MASKSSC_12_14                  ALRM0SS_MASKSSC(12)                         /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */
+#define RTC_MASKSSC_13_14                  ALRM0SS_MASKSSC(13)                         /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */
+#define RTC_MASKSSC_14                     ALRM0SS_MASKSSC(14)                         /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */
+#define RTC_MASKSSC_NONE                   ALRM0SS_MASKSSC(15)                         /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */
+
+/* RTC interrupt source */
+#define RTC_INT_TIMESTAMP                  RTC_CTL_TSIE                                /*!< time-stamp interrupt enable */
+#define RTC_INT_ALARM                      RTC_CTL_ALRM0IE                             /*!< RTC alarm interrupt enable */
+#define RTC_INT_TAMP                       RTC_TAMP_TPIE                               /*!< tamper detection interrupt enable */
+
+/* write protect key */
+#define RTC_UNLOCK_KEY1                    ((uint8_t)0xCAU)                            /*!< RTC unlock key1 */
+#define RTC_UNLOCK_KEY2                    ((uint8_t)0x53U)                            /*!< RTC unlock key2 */
+#define RTC_LOCK_KEY                       ((uint8_t)0xFFU)                            /*!< RTC lock key */
+
+/* registers reset value */
+#define RTC_REGISTER_RESET                 ((uint32_t)0x00000000U)                     /*!< RTC common register reset value */
+#define RTC_DATE_RESET                     ((uint32_t)0x00002101U)                     /*!< RTC_DATE register reset value */
+#define RTC_STAT_RESET                     ((uint32_t)0x00000007U)                     /*!< RTC_STAT register reset value */
+#define RTC_PSC_RESET                      ((uint32_t)0x007F00FFU)                     /*!< RTC_PSC register reset value */
+
+/* RTC timeout value */
+#define RTC_INITM_TIMEOUT                  ((uint32_t)0x00004000U)                     /*!< initialization state flag timeout */
+#define RTC_RSYNF_TIMEOUT                  ((uint32_t)0x00008000U)                     /*!< register synchronization flag timeout */
+#define RTC_HRFC_TIMEOUT                   ((uint32_t)0x00001000U)                     /*!< recalibration pending flag timeout */
+#define RTC_SHIFTCTL_TIMEOUT               ((uint32_t)0x00001000U)                     /*!< shift function operation pending flag timeout */
+#define RTC_ALRM0WF_TIMEOUT                ((uint32_t)0x00008000U)                     /*!< alarm configuration can be write flag timeout */
+
+/* RTC flag */
+#define RTC_FLAG_RECALIBRATION             RTC_STAT_SCPF                               /*!< recalibration pending flag */
+#define RTC_FLAG_TAMP1                     RTC_STAT_TP1F                               /*!< tamper 1 event flag */
+#define RTC_FLAG_TAMP0                     RTC_STAT_TP0F                               /*!< tamper 0 event flag */
+#define RTC_FLAG_TIMESTAMP_OVERFLOW        RTC_STAT_TSOVRF                             /*!< time-stamp overflow event flag */
+#define RTC_FLAG_TIMESTAMP                 RTC_STAT_TSF                                /*!< time-stamp event flag */
+#define RTC_FLAG_ALARM0                    RTC_STAT_ALRM0F                             /*!< alarm event flag */
+#define RTC_FLAG_INIT                      RTC_STAT_INITF                              /*!< init mode event flag */
+#define RTC_FLAG_RSYN                      RTC_STAT_RSYNF                              /*!< registers synchronized flag */
+#define RTC_FLAG_YCM                       RTC_STAT_YCM                                /*!< year parameter configured event flag */
+#define RTC_FLAG_SHIFT                     RTC_STAT_SOPF                               /*!< shift operation pending flag */
+#define RTC_FLAG_ALARM0_WRITTEN            RTC_STAT_ALRM0WF                            /*!< alarm written available flag */
+
+/* function declarations */
+/* reset most of the RTC registers */
+ErrStatus rtc_deinit(void);
+/* initialize RTC registers */
+ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct);
+/* enter RTC init mode */
+ErrStatus rtc_init_mode_enter(void);
+/* exit RTC init mode */
+void rtc_init_mode_exit(void);
+/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */
+ErrStatus rtc_register_sync_wait(void);
+
+/* get current time and date */
+void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct);
+/* get current subsecond value */
+uint32_t rtc_subsecond_get(void);
+
+/* configure RTC alarm */
+void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time);
+/* configure subsecond of RTC alarm */
+void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond);
+/* get RTC alarm */
+void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time);
+/* get RTC alarm subsecond */
+uint32_t rtc_alarm_subsecond_get(void);
+/* enable RTC alarm */
+void rtc_alarm_enable(void);
+/* disable RTC alarm */
+ErrStatus rtc_alarm_disable(void);
+
+/* enable RTC time-stamp */
+void rtc_timestamp_enable(uint32_t edge);
+/* disable RTC time-stamp */
+void rtc_timestamp_disable(void);
+/* get RTC timestamp time and date */
+void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp);
+/* get RTC time-stamp subsecond */
+uint32_t rtc_timestamp_subsecond_get(void);
+
+/* enable RTC tamper */
+void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper);
+/* disable RTC tamper */
+void rtc_tamper_disable(uint32_t source);
+
+/* enable specified RTC interrupt */
+void rtc_interrupt_enable(uint32_t interrupt);
+/* disble specified RTC interrupt */
+void rtc_interrupt_disable(uint32_t interrupt);
+/* check specified flag */
+FlagStatus rtc_flag_get(uint32_t flag);
+/* clear specified flag */
+void rtc_flag_clear(uint32_t flag);
+
+/* configure RTC alternate output source */
+void rtc_alter_output_config(uint32_t source, uint32_t mode);
+/* configure RTC calibration register */
+ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus);
+/* ajust the daylight saving time by adding or substracting one hour from the current time */
+void rtc_hour_adjust(uint32_t operation);
+/* ajust RTC second or subsecond value of current time */
+ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus);
+/* enable RTC bypass shadow registers function */
+void rtc_bypass_shadow_enable(void);
+/* disable RTC bypass shadow registers function */
+void rtc_bypass_shadow_disable(void);
+/* enable RTC reference clock detection function */
+ErrStatus rtc_refclock_detection_enable(void);
+/* disable RTC reference clock detection function */
+ErrStatus rtc_refclock_detection_disable(void);
+
+#endif /* GD32E230_RTC_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_spi.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_spi.h
new file mode 100644
index 0000000000..5be789ff11
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_spi.h
@@ -0,0 +1,424 @@
+/*!
+    \file  gd32e230_spi.h
+    \brief definitions for the SPI
+
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_SPI_H
+#define GD32E230_SPI_H
+
+#include "gd32e230.h"
+
+/* SPIx(x=0,1) definitions */
+#define SPI0                            (SPI_BASE + 0x0000F800U)
+#define SPI1                            SPI_BASE
+
+/* SPI registers definitions */
+#define SPI_CTL0(spix)                  REG32((spix) + 0x00U)                   /*!< SPI control register 0 */
+#define SPI_CTL1(spix)                  REG32((spix) + 0x04U)                   /*!< SPI control register 1*/
+#define SPI_STAT(spix)                  REG32((spix) + 0x08U)                   /*!< SPI status register */
+#define SPI_DATA(spix)                  REG32((spix) + 0x0CU)                   /*!< SPI data register */
+#define SPI_CRCPOLY(spix)               REG32((spix) + 0x10U)                   /*!< SPI CRC polynomial register */
+#define SPI_RCRC(spix)                  REG32((spix) + 0x14U)                   /*!< SPI receive CRC register */
+#define SPI_TCRC(spix)                  REG32((spix) + 0x18U)                   /*!< SPI transmit CRC register */
+#define SPI_I2SCTL(spix)                REG32((spix) + 0x1CU)                   /*!< SPI I2S control register */
+#define SPI_I2SPSC(spix)                REG32((spix) + 0x20U)                   /*!< SPI I2S clock prescaler register */
+#define SPI_QCTL(spix)                  REG32((spix) + 0x80U)                   /*!< SPI quad mode control register(only SPI1) */
+
+/* bits definitions */
+/* SPI_CTL0 */
+#define SPI_CTL0_CKPH                   BIT(0)                                  /*!< clock phase selection */
+#define SPI_CTL0_CKPL                   BIT(1)                                  /*!< clock polarity selection */
+#define SPI_CTL0_MSTMOD                 BIT(2)                                  /*!< master mode enable */
+#define SPI_CTL0_PSC                    BITS(3,5)                               /*!< master clock prescaler selection */
+#define SPI_CTL0_SPIEN                  BIT(6)                                  /*!< SPI enable*/
+#define SPI_CTL0_LF                     BIT(7)                                  /*!< LSB first mode */
+#define SPI_CTL0_SWNSS                  BIT(8)                                  /*!< NSS pin selection in NSS software mode */
+#define SPI_CTL0_SWNSSEN                BIT(9)                                  /*!< NSS software mode selection */
+#define SPI_CTL0_RO                     BIT(10)                                 /*!< receive only */
+/* only available in SPI0*/
+#define SPI_CTL0_FF16                   BIT(11)                                 /*!< data frame size */
+/* only available in SPI1*/
+#define SPI_CTL0_CRCL                   BIT(11)                                 /*!< CRC length */
+#define SPI_CTL0_CRCNT                  BIT(12)                                 /*!< CRC next transfer */
+#define SPI_CTL0_CRCEN                  BIT(13)                                 /*!< CRC calculation enable */
+#define SPI_CTL0_BDOEN                  BIT(14)                                 /*!< bidirectional transmit output enable*/
+#define SPI_CTL0_BDEN                   BIT(15)                                 /*!< bidirectional enable */
+
+/* SPI_CTL1 */
+#define SPI_CTL1_DMAREN                 BIT(0)                                  /*!< receive buffer dma enable */
+#define SPI_CTL1_DMATEN                 BIT(1)                                  /*!< transmit buffer dma enable */
+#define SPI_CTL1_NSSDRV                 BIT(2)                                  /*!< drive NSS output */
+#define SPI_CTL1_NSSP                   BIT(3)                                  /*!< SPI NSS pulse mode enable */
+#define SPI_CTL1_TMOD                   BIT(4)                                  /*!< SPI TI mode enable */
+#define SPI_CTL1_ERRIE                  BIT(5)                                  /*!< errors interrupt enable */
+#define SPI_CTL1_RBNEIE                 BIT(6)                                  /*!< receive buffer not empty interrupt enable */
+#define SPI_CTL1_TBEIE                  BIT(7)                                  /*!< transmit buffer empty interrupt enable */
+/* only available in SPI1 */
+#define SPI_CTL1_DZ                     BITS(8,11)                              /*!< data size */
+#define SPI_CTL1_BYTEN                  BIT(12)                                 /*!< byte access to FIFO enable */
+#define SPI_CTL1_RXDMA_ODD              BIT(13)                                 /*!< odd bytes in RX DMA channel */
+#define SPI_CTL1_TXDMA_ODD              BIT(14)                                 /*!< odd bytes in TX DMA channel */
+
+/* SPI_STAT */
+#define SPI_STAT_RBNE                   BIT(0)                                  /*!< receive buffer not empty */
+#define SPI_STAT_TBE                    BIT(1)                                  /*!< transmit buffer empty */
+#define SPI_STAT_I2SCH                  BIT(2)                                  /*!< I2S channel side */
+#define SPI_STAT_TXURERR                BIT(3)                                  /*!< I2S transmission underrun error bit */
+#define SPI_STAT_CRCERR                 BIT(4)                                  /*!< SPI CRC error bit */
+#define SPI_STAT_CONFERR                BIT(5)                                  /*!< SPI configuration error bit */
+#define SPI_STAT_RXORERR                BIT(6)                                  /*!< SPI reception overrun error bit */
+#define SPI_STAT_TRANS                  BIT(7)                                  /*!< transmitting on-going bit */
+#define SPI_STAT_FERR                   BIT(8)                                  /*!< format error bit */
+/* only available in SPI1 */
+#define SPI_STAT_RXLVL                  BITS(9,10)                              /*!< RXFIFO level */
+#define SPI_STAT_TXLVL                  BITS(11,12)                             /*!< TXFIFO level */
+
+/* SPI_DATA */
+#define SPI_DATA_DATA                   BITS(0,15)                              /*!< data transfer register */
+
+/* SPI_CRCPOLY */
+#define SPI_CRCPOLY_CRCPOLY             BITS(0,15)                              /*!< CRC polynomial value */
+
+/* SPI_RCRC */
+#define SPI_RCRC_RCRC                   BITS(0,15)                              /*!< RX CRC value */
+
+/* SPI_TCRC */
+#define SPI_TCRC_TCRC                   BITS(0,15)                              /*!< TX CRC value */
+
+/* SPI_I2SCTL */
+#define SPI_I2SCTL_CHLEN                BIT(0)                                  /*!< channel length */
+#define SPI_I2SCTL_DTLEN                BITS(1,2)                               /*!< data length */
+#define SPI_I2SCTL_CKPL                 BIT(3)                                  /*!< idle state clock polarity */
+#define SPI_I2SCTL_I2SSTD               BITS(4,5)                               /*!< I2S standard selection */
+#define SPI_I2SCTL_PCMSMOD              BIT(7)                                  /*!< PCM frame synchronization mode */
+#define SPI_I2SCTL_I2SOPMOD             BITS(8,9)                               /*!< I2S operation mode */
+#define SPI_I2SCTL_I2SEN                BIT(10)                                 /*!< I2S enable */
+#define SPI_I2SCTL_I2SSEL               BIT(11)                                 /*!< I2S mode selection */
+
+/* SPI_I2SPSC */
+#define SPI_I2SPSC_DIV                  BITS(0,7)                               /*!< dividing factor for the prescaler */
+#define SPI_I2SPSC_OF                   BIT(8)                                  /*!< odd factor for the prescaler */
+#define SPI_I2SPSC_MCKOEN               BIT(9)                                  /*!< I2S MCK output enable */
+
+/* SPIx_QCTL(x=1) */
+#define SPI_QCTL_QMOD                   BIT(0)                                  /*!< quad-SPI mode enable */
+#define SPI_QCTL_QRD                    BIT(1)                                  /*!< quad-SPI mode read select */
+#define SPI_QCTL_IO23_DRV               BIT(2)                                  /*!< drive SPI_IO2 and SPI_IO3 enable */
+
+/* constants definitions */
+/* SPIx and I2Sx parameter struct definitions */
+typedef struct
+{   
+    uint32_t device_mode;                                                       /*!< SPI master or slave */
+    uint32_t trans_mode;                                                        /*!< SPI transtype */
+    uint32_t frame_size;                                                        /*!< SPI frame size */
+    uint32_t nss;                                                               /*!< SPI NSS control by handware or software */
+    uint32_t endian;                                                            /*!< SPI big endian or little endian */
+    uint32_t clock_polarity_phase;                                              /*!< SPI clock phase and polarity */
+    uint32_t prescale;                                                          /*!< SPI prescale factor */
+}spi_parameter_struct;
+
+/* SPI mode definitions */
+#define SPI_MASTER                      (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)      /*!< SPI as master */
+#define SPI_SLAVE                       ((uint32_t)0x00000000U)                 /*!< SPI as slave */
+
+/* SPI bidirectional transfer direction */
+#define SPI_BIDIRECTIONAL_TRANSMIT      SPI_CTL0_BDOEN                          /*!< SPI work in transmit-only mode */
+#define SPI_BIDIRECTIONAL_RECEIVE       (~SPI_CTL0_BDOEN)                       /*!< SPI work in receive-only mode */
+
+/* SPI transmit type */
+#define SPI_TRANSMODE_FULLDUPLEX        ((uint32_t)0x00000000U)                 /*!< SPI receive and send data at fullduplex communication */
+#define SPI_TRANSMODE_RECEIVEONLY       SPI_CTL0_RO                             /*!< SPI only receive data */
+#define SPI_TRANSMODE_BDRECEIVE         SPI_CTL0_BDEN                           /*!< bidirectional receive data */
+#define SPI_TRANSMODE_BDTRANSMIT        (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)        /*!< bidirectional transmit data*/
+
+/* SPI NSS control mode */
+#define SPI_NSS_SOFT                    SPI_CTL0_SWNSSEN                        /*!< SPI NSS control by sofrware */
+#define SPI_NSS_HARD                    ((uint32_t)0x00000000U)                 /*!< SPI NSS control by hardware */
+
+/* SPI transmit way */
+#define SPI_ENDIAN_MSB                  ((uint32_t)0x00000000U)                 /*!< SPI transmit way is big endian: transmit MSB first */
+#define SPI_ENDIAN_LSB                  SPI_CTL0_LF                             /*!< SPI transmit way is little endian: transmit LSB first */
+
+/* SPI clock phase and polarity */
+#define SPI_CK_PL_LOW_PH_1EDGE          ((uint32_t)0x00000000U)                 /*!< SPI clock polarity is low level and phase is first edge */
+#define SPI_CK_PL_HIGH_PH_1EDGE         SPI_CTL0_CKPL                           /*!< SPI clock polarity is high level and phase is first edge */
+#define SPI_CK_PL_LOW_PH_2EDGE          SPI_CTL0_CKPH                           /*!< SPI clock polarity is low level and phase is second edge */
+#define SPI_CK_PL_HIGH_PH_2EDGE         (SPI_CTL0_CKPL | SPI_CTL0_CKPH)         /*!< SPI clock polarity is high level and phase is second edge */
+
+/* SPI clock prescale factor */
+#define CTL0_PSC(regval)                (BITS(3,5) & ((uint32_t)(regval) << 3))
+#define SPI_PSC_2                       CTL0_PSC(0)                             /*!< SPI clock prescale factor is 2 */
+#define SPI_PSC_4                       CTL0_PSC(1)                             /*!< SPI clock prescale factor is 4 */
+#define SPI_PSC_8                       CTL0_PSC(2)                             /*!< SPI clock prescale factor is 8 */
+#define SPI_PSC_16                      CTL0_PSC(3)                             /*!< SPI clock prescale factor is 16 */
+#define SPI_PSC_32                      CTL0_PSC(4)                             /*!< SPI clock prescale factor is 32 */
+#define SPI_PSC_64                      CTL0_PSC(5)                             /*!< SPI clock prescale factor is 64 */
+#define SPI_PSC_128                     CTL0_PSC(6)                             /*!< SPI clock prescale factor is 128 */
+#define SPI_PSC_256                     CTL0_PSC(7)                             /*!< SPI clock prescale factor is 256 */
+
+/* SPIx frame size */
+#define CTL1_FRAMESIZE(regval)           (BITS(8,11) & ((uint32_t)(regval) << 8))        
+#define SPI_FRAMESIZE_4BIT               CTL1_FRAMESIZE(3)                      /*!< SPI frame size is 4 bits */
+#define SPI_FRAMESIZE_5BIT               CTL1_FRAMESIZE(4)                      /*!< SPI frame size is 5 bits */
+#define SPI_FRAMESIZE_6BIT               CTL1_FRAMESIZE(5)                      /*!< SPI frame size is 6 bits */
+#define SPI_FRAMESIZE_7BIT               CTL1_FRAMESIZE(6)                      /*!< SPI frame size is 7 bits */
+#define SPI_FRAMESIZE_8BIT               CTL1_FRAMESIZE(7)                      /*!< SPI frame size is 8 bits */
+#define SPI_FRAMESIZE_9BIT               CTL1_FRAMESIZE(8)                      /*!< SPI frame size is 9 bits */
+#define SPI_FRAMESIZE_10BIT              CTL1_FRAMESIZE(9)                      /*!< SPI frame size is 10 bits */
+#define SPI_FRAMESIZE_11BIT              CTL1_FRAMESIZE(10)                     /*!< SPI frame size is 11 bits */
+#define SPI_FRAMESIZE_12BIT              CTL1_FRAMESIZE(11)                     /*!< SPI frame size is 12 bits */
+#define SPI_FRAMESIZE_13BIT              CTL1_FRAMESIZE(12)                     /*!< SPI frame size is 13 bits */
+#define SPI_FRAMESIZE_14BIT              CTL1_FRAMESIZE(13)                     /*!< SPI frame size is 14 bits */
+#define SPI_FRAMESIZE_15BIT              CTL1_FRAMESIZE(14)                     /*!< SPI frame size is 15 bits */
+#define SPI_FRAMESIZE_16BIT              CTL1_FRAMESIZE(15)                     /*!< SPI frame size is 16 bits */
+
+/* SPIx CRC length(x=1) */
+#define SPI_CRC_8BIT                    ((uint32_t)0x00000000U)                 /*!< SPI CRC length is 8 bits */
+#define SPI_CRC_16BIT                   SPI_CTL0_CRCL                           /*!< SPI CRC length is 16 bits */
+
+/* SPIx byte access enable(x=1) */
+#define SPI_HALFWORD_ACCESS             ((uint32_t)0x00000000U)                 /*!< SPI half-word access to FIFO */
+#define SPI_BYTE_ACCESS                 SPI_CTL1_BYTEN                          /*!< SPI byte access to FIFO */
+
+/* SPIx odd bytes in TX DMA channel(x=1) */
+#define SPI_TXDMA_EVEN                  ((uint32_t)0x00000000U)                 /*!< SPI number of byte in TX DMA channel is even */
+#define SPI_TXDMA_ODD                   SPI_CTL1_TXDMA_ODD                      /*!< SPI number of byte in TX DMA channel is odd */
+
+/* SPIx odd bytes in RX DMA channel(x=1) */
+#define SPI_RXDMA_EVEN                  ((uint32_t)0x00000000U)                 /*!< SPI number of byte in RX DMA channel is even */
+#define SPI_RXDMA_ODD                   SPI_CTL1_RXDMA_ODD                      /*!< SPI number of byte in RX DMA channel is odd */
+
+/* SPIx TXFIFO level(x=1) */
+#define CTL1_TXLVL(regval)              (BITS(11,12) & ((uint32_t)(regval) << 11))
+#define SPI_TXLVL_EMPTY                 CTL1_RXLVL(0)                           /*!< SPI TXFIFO is empty */
+#define SPI_TXLVL_QUARTER_FULL          CTL1_RXLVL(1)                           /*!< SPI TXFIFO is a quarter of full */
+#define SPI_TXLVL_HAlF_FULL             CTL1_RXLVL(2)                           /*!< SPI TXFIFO is a half of full */
+#define SPI_TXLVL_FULL                  CTL1_RXLVL(3)                           /*!< SPI TXFIFO is full */
+
+/* SPIx RXFIFO level(x=1) */
+#define CTL1_RXLVL(regval)              (BITS(9,10) & ((uint32_t)(regval) << 9))
+#define SPI_RXLVL_EMPTY                 CTL1_RXLVL(0)                           /*!< SPI RXFIFO is empty */
+#define SPI_RXLVL_QUARTER_FULL          CTL1_RXLVL(1)                           /*!< SPI RXFIFO is a quarter of full */
+#define SPI_RXLVL_HAlF_FULL             CTL1_RXLVL(2)                           /*!< SPI RXFIFO is a half of full */
+#define SPI_RXLVL_FULL                  CTL1_RXLVL(3)                           /*!< SPI RXFIFO is full */
+
+/* I2S audio sample rate */
+#define I2S_AUDIOSAMPLE_8K              ((uint32_t)8000U)                       /*!< I2S audio sample rate is 8KHz */
+#define I2S_AUDIOSAMPLE_11K             ((uint32_t)11025U)                      /*!< I2S audio sample rate is 11KHz */
+#define I2S_AUDIOSAMPLE_16K             ((uint32_t)16000U)                      /*!< I2S audio sample rate is 16KHz */
+#define I2S_AUDIOSAMPLE_22K             ((uint32_t)22050U)                      /*!< I2S audio sample rate is 22KHz */
+#define I2S_AUDIOSAMPLE_32K             ((uint32_t)32000U)                      /*!< I2S audio sample rate is 32KHz */
+#define I2S_AUDIOSAMPLE_44K             ((uint32_t)44100U)                      /*!< I2S audio sample rate is 44KHz */
+#define I2S_AUDIOSAMPLE_48K             ((uint32_t)48000U)                      /*!< I2S audio sample rate is 48KHz */
+#define I2S_AUDIOSAMPLE_96K             ((uint32_t)96000U)                      /*!< I2S audio sample rate is 96KHz */
+#define I2S_AUDIOSAMPLE_192K            ((uint32_t)192000U)                     /*!< I2S audio sample rate is 192KHz */
+
+/* I2S frame format */
+#define I2SCTL_DTLEN(regval)            (BITS(1,2) & ((uint32_t)(regval) << 1))
+#define I2S_FRAMEFORMAT_DT16B_CH16B     I2SCTL_DTLEN(0)                         /*!< I2S data length is 16 bit and channel length is 16 bit */
+#define I2S_FRAMEFORMAT_DT16B_CH32B     (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 16 bit and channel length is 32 bit */
+#define I2S_FRAMEFORMAT_DT24B_CH32B     (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 24 bit and channel length is 32 bit */
+#define I2S_FRAMEFORMAT_DT32B_CH32B     (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 32 bit and channel length is 32 bit */
+
+/* I2S master clock output */
+#define I2S_MCKOUT_DISABLE              ((uint32_t)0x00000000U)                 /*!< I2S master clock output disable */
+#define I2S_MCKOUT_ENABLE               SPI_I2SPSC_MCKOEN                       /*!< I2S master clock output enable */
+
+/* I2S operation mode */
+#define I2SCTL_I2SOPMOD(regval)         (BITS(8,9) & ((uint32_t)(regval) << 8))
+#define I2S_MODE_SLAVETX                I2SCTL_I2SOPMOD(0)                      /*!< I2S slave transmit mode */
+#define I2S_MODE_SLAVERX                I2SCTL_I2SOPMOD(1)                      /*!< I2S slave receive mode */
+#define I2S_MODE_MASTERTX               I2SCTL_I2SOPMOD(2)                      /*!< I2S master transmit mode */
+#define I2S_MODE_MASTERRX               I2SCTL_I2SOPMOD(3)                      /*!< I2S master receive mode */
+
+/* I2S standard */
+#define I2SCTL_I2SSTD(regval)           (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define I2S_STD_PHILLIPS                I2SCTL_I2SSTD(0)                        /*!< I2S phillips standard */
+#define I2S_STD_MSB                     I2SCTL_I2SSTD(1)                        /*!< I2S MSB standard */
+#define I2S_STD_LSB                     I2SCTL_I2SSTD(2)                        /*!< I2S LSB standard */
+#define I2S_STD_PCMSHORT                I2SCTL_I2SSTD(3)                        /*!< I2S PCM short standard */
+#define I2S_STD_PCMLONG                 (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
+
+/* I2S clock polarity */
+#define I2S_CKPL_LOW                    ((uint32_t)0x00000000U)                 /*!< I2S clock polarity low level */
+#define I2S_CKPL_HIGH                   SPI_I2SCTL_CKPL                         /*!< I2S clock polarity high level */
+
+/* SPI DMA constants definitions */                                    
+#define SPI_DMA_TRANSMIT                ((uint8_t)0x00U)                        /*!< SPI transmit data use DMA */
+#define SPI_DMA_RECEIVE                 ((uint8_t)0x01U)                        /*!< SPI receive data use DMA */
+
+/* SPI CRC constants definitions */
+#define SPI_CRC_TX                      ((uint8_t)0x00U)                        /*!< SPI transmit CRC value */
+#define SPI_CRC_RX                      ((uint8_t)0x01U)                        /*!< SPI receive CRC value */
+
+/* SPI/I2S interrupt enable/disable constants definitions */
+#define SPI_I2S_INT_TBE                 ((uint8_t)0x00U)                        /*!< transmit buffer empty interrupt */
+#define SPI_I2S_INT_RBNE                ((uint8_t)0x01U)                        /*!< receive buffer not empty interrupt */
+#define SPI_I2S_INT_ERR                 ((uint8_t)0x02U)                        /*!< error interrupt */
+
+/* SPI/I2S interrupt flag constants definitions */
+#define SPI_I2S_INT_FLAG_TBE            ((uint8_t)0x00U)                        /*!< transmit buffer empty interrupt flag */
+#define SPI_I2S_INT_FLAG_RBNE           ((uint8_t)0x01U)                        /*!< receive buffer not empty interrupt flag */
+#define SPI_I2S_INT_FLAG_RXORERR        ((uint8_t)0x02U)                        /*!< overrun interrupt flag */
+#define SPI_INT_FLAG_CONFERR            ((uint8_t)0x03U)                        /*!< config error interrupt flag */
+#define SPI_INT_FLAG_CRCERR             ((uint8_t)0x04U)                        /*!< CRC error interrupt flag */
+#define I2S_INT_FLAG_TXURERR            ((uint8_t)0x05U)                        /*!< underrun error interrupt flag */
+#define SPI_I2S_INT_FLAG_FERR           ((uint8_t)0x06U)                        /*!< format error interrupt flag */
+
+/* SPI/I2S flag definitions */                                                  
+#define SPI_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
+#define SPI_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
+#define SPI_FLAG_CRCERR                 SPI_STAT_CRCERR                         /*!< CRC error flag */
+#define SPI_FLAG_CONFERR                SPI_STAT_CONFERR                        /*!< mode config error flag */
+#define SPI_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< receive overrun error flag */
+#define SPI_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
+#define SPI_FLAG_FERR                   SPI_STAT_FERR                           /*!< format error interrupt flag */
+#define I2S_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
+#define I2S_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
+#define I2S_FLAG_CH                     SPI_STAT_I2SCH                          /*!< channel side flag */
+#define I2S_FLAG_TXURERR                SPI_STAT_TXURERR                        /*!< underrun error flag */
+#define I2S_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< overrun error flag */
+#define I2S_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
+#define I2S_FLAG_FERR                   SPI_STAT_FERR                           /*!< format error interrupt flag */
+
+/* function declarations */
+/* SPI/I2S deinitialization and initialization functions */
+/* reset SPI and I2S */
+void spi_i2s_deinit(uint32_t spi_periph);
+/* initialize the parameters of SPI struct with the default values */
+void spi_struct_para_init(spi_parameter_struct* spi_struct);
+/* initialize SPI parameter */
+ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
+/* enable SPI */
+void spi_enable(uint32_t spi_periph);
+/* disable SPI */
+void spi_disable(uint32_t spi_periph);
+
+/* initialize I2S parameter */
+void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
+/* configure I2S prescaler */
+void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
+/* enable I2S */
+void i2s_enable(uint32_t spi_periph);
+/* disable I2S */
+void i2s_disable(uint32_t spi_periph);
+
+/* NSS functions */
+/* enable SPI NSS output */
+void spi_nss_output_enable(uint32_t spi_periph);
+/* disable SPI NSS output */
+void spi_nss_output_disable(uint32_t spi_periph);
+/* SPI NSS pin high level in software mode */
+void spi_nss_internal_high(uint32_t spi_periph);
+/* SPI NSS pin low level in software mode */
+void spi_nss_internal_low(uint32_t spi_periph);
+
+/* enable SPI DMA */
+void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
+/* disable SPI DMA */
+void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
+
+/* configure SPI/I2S data frame format */
+ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
+/* SPI transmit data */
+void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
+/* SPI receive data */
+uint16_t spi_i2s_data_receive(uint32_t spi_periph); 
+/* configure SPI bidirectional transfer direction */
+void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
+
+/* SPI CRC functions */
+/* set SPI CRC polynomial */
+void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
+/* get SPI CRC polynomial */
+uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
+/* turn on SPI CRC function */
+void spi_crc_on(uint32_t spi_periph);
+/* turn off SPI CRC function */
+void spi_crc_off(uint32_t spi_periph);
+/* SPI next data is CRC value */
+void spi_crc_next(uint32_t spi_periph);
+/* get SPI CRC send value or receive value */
+uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
+
+/* SPI TI mode functions */
+/* enable SPI TI mode */
+void spi_ti_mode_enable(uint32_t spi_periph);
+/* disable SPI TI mode */
+void spi_ti_mode_disable(uint32_t spi_periph);
+
+/* SPI NSS pulse mode functions */
+/* enable SPI NSS pulse mode */
+void spi_nssp_mode_enable(uint32_t spi_periph);
+/* disable SPI NSS pulse mode */
+void spi_nssp_mode_disable(uint32_t spi_periph);
+
+/* quad wire SPI functions */
+/* enable quad wire SPI */
+void qspi_enable(uint32_t spi_periph);
+/* disable quad wire SPI */
+void qspi_disable(uint32_t spi_periph);
+/* enable quad wire SPI write */
+void qspi_write_enable(uint32_t spi_periph);
+/* enable quad wire SPI read */
+void qspi_read_enable(uint32_t spi_periph);
+/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
+void qspi_io23_output_enable(uint32_t spi_periph);
+/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
+void qspi_io23_output_disable(uint32_t spi_periph);
+
+/* flag and interrupt functions */
+/* enable SPI and I2S interrupt */
+void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
+/* disable SPI and I2S interrupt */
+void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
+/* get SPI and I2S interrupt status */
+FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
+/* get SPI and I2S flag status */
+FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
+/* clear SPI CRC error flag status */
+void spi_crc_error_clear(uint32_t spi_periph);
+
+/* only for SPI1 FIFO added */
+/* configure SPI access size to FIFO(8-bit or 16-bit) */
+void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size);
+/* configure SPI total number of data transmitting by DMA is odd or not */
+void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd);
+/* configure SPI total number of data receiving by DMA is odd or not */
+void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd);
+/* set CRC length */
+void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length);
+
+#endif /* GD32E230_SPI_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_syscfg.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_syscfg.h
new file mode 100644
index 0000000000..9109a89602
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_syscfg.h
@@ -0,0 +1,187 @@
+/*!
+    \file  GD32e230_syscfg.h
+    \brief definitions for the SYSCFG
+
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_SYSCFG_H
+#define GD32E230_SYSCFG_H
+
+#include "gd32e230.h"
+
+/* SYSCFG definitions */
+#define SYSCFG                              SYSCFG_BASE
+
+/* registers definitions */
+#define SYSCFG_CFG0                         REG32(SYSCFG + 0x00U)               /*!< system configuration register 0 */
+#define SYSCFG_EXTISS0                      REG32(SYSCFG + 0x08U)               /*!< EXTI sources selection register 0 */
+#define SYSCFG_EXTISS1                      REG32(SYSCFG + 0x0CU)               /*!< EXTI sources selection register 1 */
+#define SYSCFG_EXTISS2                      REG32(SYSCFG + 0x10U)               /*!< EXTI sources selection register 2 */
+#define SYSCFG_EXTISS3                      REG32(SYSCFG + 0x14U)               /*!< EXTI sources selection register 3 */
+#define SYSCFG_CFG2                         REG32(SYSCFG + 0x18U)               /*!< system configuration register 2 */
+#define SYSCFG_CPU_IRQ_LAT                  REG32(SYSCFG + 0x100U)              /*!< IRQ Latency register */
+
+/* SYSCFG_CFG0 bits definitions */
+#define SYSCFG_CFG0_BOOT_MODE               BITS(0,1)                           /*!< SYSCFG memory remap config */
+#define SYSCFG_CFG0_PA11_PA12_RMP           BIT(4)                              /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins) */
+#define SYSCFG_CFG0_ADC_DMA_RMP             BIT(8)                              /*!< ADC DMA remap config */
+#define SYSCFG_CFG0_USART0_TX_DMA_RMP       BIT(9)                              /*!< USART0 Tx DMA remap config */
+#define SYSCFG_CFG0_USART0_RX_DMA_RMP       BIT(10)                             /*!< USART0 Rx DMA remap config */
+#define SYSCFG_CFG0_TIMER15_DMA_RMP         BIT(11)                             /*!< TIMER 15 DMA remap config */
+#define SYSCFG_CFG0_TIMER16_DMA_RMP         BIT(12)                             /*!< TIMER 16 DMA remap config */
+#define SYSCFG_CFG0_PB9_HCCE                BIT(19)                             /*!< PB9 pin high current capability enable */
+
+/* SYSCFG_EXTISS0 bits definitions */
+#define SYSCFG_EXTISS0_EXTI0_SS             BITS(0,3)                           /*!< EXTI 0 configuration */
+#define SYSCFG_EXTISS0_EXTI1_SS             BITS(4,7)                           /*!< EXTI 1 configuration */
+#define SYSCFG_EXTISS0_EXTI2_SS             BITS(8,11)                          /*!< EXTI 2 configuration */
+#define SYSCFG_EXTISS0_EXTI3_SS             BITS(12,15)                         /*!< EXTI 3 configuration */
+
+/* SYSCFG_EXTISS1 bits definitions */
+#define SYSCFG_EXTISS1_EXTI4_SS             BITS(0,3)                           /*!< EXTI 4 configuration */
+#define SYSCFG_EXTISS1_EXTI5_SS             BITS(4,7)                           /*!< EXTI 5 configuration */
+#define SYSCFG_EXTISS1_EXTI6_SS             BITS(8,11)                          /*!< EXTI 6 configuration */
+#define SYSCFG_EXTISS1_EXTI7_SS             BITS(12,15)                         /*!< EXTI 7 configuration */
+
+/* SYSCFG_EXTISS2 bits definitions */
+#define SYSCFG_EXTISS2_EXTI8_SS             BITS(0,3)                           /*!< EXTI 8 configuration */
+#define SYSCFG_EXTISS2_EXTI9_SS             BITS(4,7)                           /*!< EXTI 9 configuration */
+#define SYSCFG_EXTISS2_EXTI10_SS            BITS(8,11)                          /*!< EXTI 10 configuration */
+#define SYSCFG_EXTISS2_EXTI11_SS            BITS(12,15)                         /*!< EXTI 11 configuration */
+
+/* SYSCFG_EXTISS3 bits definitions */
+#define SYSCFG_EXTISS3_EXTI12_SS            BITS(0,3)                           /*!< EXTI 12 configuration */
+#define SYSCFG_EXTISS3_EXTI13_SS            BITS(4,7)                           /*!< EXTI 13 configuration */
+#define SYSCFG_EXTISS3_EXTI14_SS            BITS(8,11)                          /*!< EXTI 14 configuration */
+#define SYSCFG_EXTISS3_EXTI15_SS            BITS(12,15)                         /*!< EXTI 15 configuration */
+
+/* SYSCFG_CFG2 bits definitions */
+#define SYSCFG_CFG2_LOCKUP_LOCK             BIT(0)                              /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M23 with break input of TIMER0/14/15/16 */
+#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK  BIT(1)                              /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */
+#define SYSCFG_CFG2_LVD_LOCK                BIT(2)                              /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */
+#define SYSCFG_CFG2_SRAM_PCEF               BIT(8)                              /*!< SRAM parity check error flag */
+
+/* SYSCFG_CPU_IRQ_LAT bits definitions */
+#define SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY      BITS(0,7)                           /*!< IRQ_LATENCY specifies the minimum number of cycles between an interrupt */
+
+/* constants definitions */
+/* DMA remap definitions */
+#define SYSCFG_PA11_REMAP_PA12              SYSCFG_CFG0_PA11_PA12_RMP           /*!< PA11 PA12 remap */
+#define SYSCFG_DMA_REMAP_ADC                SYSCFG_CFG0_ADC_DMA_RMP             /*!< ADC DMA remap */
+#define SYSCFG_DMA_REMAP_USART0TX           SYSCFG_CFG0_USART0_TX_DMA_RMP       /*!< USART0_TX DMA remap */
+#define SYSCFG_DMA_REMAP_USART0RX           SYSCFG_CFG0_USART0_RX_DMA_RMP       /*!< USART0_RX DMA remap */
+#define SYSCFG_DMA_REMAP_TIMER15            SYSCFG_CFG0_TIMER15_DMA_RMP         /*!< TIMER15 DMA remap */
+#define SYSCFG_DMA_REMAP_TIMER16            SYSCFG_CFG0_TIMER16_DMA_RMP         /*!< TIMER16 DMA remap */
+
+/* high current definitions */
+#define SYSCFG_HIGH_CURRENT_ENABLE          SYSCFG_CFG0_PB9_HCCE                /*!< high current enable */
+#define SYSCFG_HIGH_CURRENT_DISABLE         (~SYSCFG_CFG0_PB9_HCCE)             /*!< high current disable */
+
+/* EXTI source select definition */
+#define EXTISS0                             ((uint8_t)0x00U)                    /*!< EXTI source select register 0 */
+#define EXTISS1                             ((uint8_t)0x01U)                    /*!< EXTI source select register 1 */
+#define EXTISS2                             ((uint8_t)0x02U)                    /*!< EXTI source select register 2 */
+#define EXTISS3                             ((uint8_t)0x03U)                    /*!< EXTI source select register 3 */
+
+/* EXTI source select mask bits definition */
+#define EXTI_SS_MASK                        BITS(0,3)                           /*!< EXTI source select mask */
+
+/* EXTI source select jumping step definition */
+#define EXTI_SS_JSTEP                       ((uint8_t)(0x04U))                  /*!< EXTI source select jumping step */
+
+/* EXTI source select moving step definition */
+#define EXTI_SS_MSTEP(pin)                  (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP))   /*!< EXTI source select moving step */
+
+/* EXTI source port definitions */
+#define EXTI_SOURCE_GPIOA                   ((uint8_t)0x00U)                    /*!< EXTI GPIOA configuration */
+#define EXTI_SOURCE_GPIOB                   ((uint8_t)0x01U)                    /*!< EXTI GPIOB configuration */
+#define EXTI_SOURCE_GPIOC                   ((uint8_t)0x02U)                    /*!< EXTI GPIOC configuration */
+#define EXTI_SOURCE_GPIOF                   ((uint8_t)0x05U)                    /*!< EXTI GPIOF configuration */
+
+/* EXTI source pin definitions */
+#define EXTI_SOURCE_PIN0                    ((uint8_t)0x00U)                    /*!< EXTI GPIO pin0 configuration */
+#define EXTI_SOURCE_PIN1                    ((uint8_t)0x01U)                    /*!< EXTI GPIO pin1 configuration */
+#define EXTI_SOURCE_PIN2                    ((uint8_t)0x02U)                    /*!< EXTI GPIO pin2 configuration */
+#define EXTI_SOURCE_PIN3                    ((uint8_t)0x03U)                    /*!< EXTI GPIO pin3 configuration */
+#define EXTI_SOURCE_PIN4                    ((uint8_t)0x04U)                    /*!< EXTI GPIO pin4 configuration */
+#define EXTI_SOURCE_PIN5                    ((uint8_t)0x05U)                    /*!< EXTI GPIO pin5 configuration */
+#define EXTI_SOURCE_PIN6                    ((uint8_t)0x06U)                    /*!< EXTI GPIO pin6 configuration */
+#define EXTI_SOURCE_PIN7                    ((uint8_t)0x07U)                    /*!< EXTI GPIO pin7 configuration */
+#define EXTI_SOURCE_PIN8                    ((uint8_t)0x08U)                    /*!< EXTI GPIO pin8 configuration */
+#define EXTI_SOURCE_PIN9                    ((uint8_t)0x09U)                    /*!< EXTI GPIO pin9 configuration */
+#define EXTI_SOURCE_PIN10                   ((uint8_t)0x0AU)                    /*!< EXTI GPIO pin10 configuration */
+#define EXTI_SOURCE_PIN11                   ((uint8_t)0x0BU)                    /*!< EXTI GPIO pin11 configuration */
+#define EXTI_SOURCE_PIN12                   ((uint8_t)0x0CU)                    /*!< EXTI GPIO pin12 configuration */
+#define EXTI_SOURCE_PIN13                   ((uint8_t)0x0DU)                    /*!< EXTI GPIO pin13 configuration */
+#define EXTI_SOURCE_PIN14                   ((uint8_t)0x0EU)                    /*!< EXTI GPIO pin14 configuration */
+#define EXTI_SOURCE_PIN15                   ((uint8_t)0x0FU)                    /*!< EXTI GPIO pin15 configuration */
+
+/* lock definitions */
+#define SYSCFG_LOCK_LOCKUP                  SYSCFG_CFG2_LOCKUP_LOCK             /*!< LOCKUP output lock */
+#define SYSCFG_LOCK_SRAM_PARITY_ERROR       SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK  /*!< SRAM parity error lock */
+#define SYSCFG_LOCK_LVD                     SYSCFG_CFG2_LVD_LOCK                /*!< LVD lock */
+
+/* SRAM parity check error flag definitions */
+#define SYSCFG_SRAM_PCEF                    SYSCFG_CFG2_SRAM_PCEF               /*!< SRAM parity check error flag */
+
+/* SYSCFG_CPU_IRQ_LAT register IRQ_LATENCY value */
+#define IRQ_LATENCY(regval)                (BITS(0,7) & ((uint32_t)(regval) << 0U))     /*!< write value to IRQ_LATENCY bits field */
+
+/* function declarations */
+/* deinit syscfg module */
+void syscfg_deinit(void);
+
+/* enable the DMA channels remapping */
+void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap);
+/* disable the DMA channels remapping */
+void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap);
+
+/* enable PB9 high current capability */
+void syscfg_high_current_enable(void);
+/* disable PB9 high current capability */
+void syscfg_high_current_disable(void);
+
+/* configure the GPIO pin as EXTI Line */
+void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
+/* connect TIMER0/14/15/16 break input to the selected parameter */
+void syscfg_lock_config(uint32_t syscfg_lock);
+
+/* set the IRQ_LATENCY value */
+void irq_latency_set(uint8_t irq_latency);
+
+/* check if the specified flag in SYSCFG_CFG2 is set or not */
+FlagStatus syscfg_flag_get(uint32_t syscfg_flag);
+/* clear the flag in SYSCFG_CFG2 by writing 1 */
+void syscfg_flag_clear(uint32_t syscfg_flag);
+
+#endif /* GD32E230_SYSCFG_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_timer.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_timer.h
new file mode 100644
index 0000000000..c69aa8f895
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_timer.h
@@ -0,0 +1,760 @@
+/*!
+    \file    gd32e230_timer.h
+    \brief   definitions for the TIMER
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_TIMER_H
+#define GD32E230_TIMER_H
+
+#include "gd32e230.h"
+
+/* TIMERx(x=0,1,2,5,13..16) definitions */
+#define TIMER0                           (TIMER_BASE + 0x00012C00U)
+#define TIMER2                           (TIMER_BASE + 0x00000400U)
+#define TIMER5                           (TIMER_BASE + 0x00001000U)
+#define TIMER13                          (TIMER_BASE + 0x00002000U)
+#define TIMER14                          (TIMER_BASE + 0x00014000U)
+#define TIMER15                          (TIMER_BASE + 0x00014400U)
+#define TIMER16                          (TIMER_BASE + 0x00014800U)
+
+/* registers definitions */
+#define TIMER_CTL0(timerx)               REG32((timerx) + 0x00U)           /*!< TIMER control register 0 */
+#define TIMER_CTL1(timerx)               REG32((timerx) + 0x04U)           /*!< TIMER control register 1 */
+#define TIMER_SMCFG(timerx)              REG32((timerx) + 0x08U)           /*!< TIMER slave mode configuration register */
+#define TIMER_DMAINTEN(timerx)           REG32((timerx) + 0x0CU)           /*!< TIMER DMA and interrupt enable register */
+#define TIMER_INTF(timerx)               REG32((timerx) + 0x10U)           /*!< TIMER interrupt flag register */
+#define TIMER_SWEVG(timerx)              REG32((timerx) + 0x14U)           /*!< TIMER software event generation register */
+#define TIMER_CHCTL0(timerx)             REG32((timerx) + 0x18U)           /*!< TIMER channel control register 0 */
+#define TIMER_CHCTL1(timerx)             REG32((timerx) + 0x1CU)           /*!< TIMER channel control register 1 */
+#define TIMER_CHCTL2(timerx)             REG32((timerx) + 0x20U)           /*!< TIMER channel control register 2 */
+#define TIMER_CNT(timerx)                REG32((timerx) + 0x24U)           /*!< TIMER counter register */
+#define TIMER_PSC(timerx)                REG32((timerx) + 0x28U)           /*!< TIMER prescaler register */
+#define TIMER_CAR(timerx)                REG32((timerx) + 0x2CU)           /*!< TIMER counter auto reload register */
+#define TIMER_CREP(timerx)               REG32((timerx) + 0x30U)           /*!< TIMER counter repetition register */
+#define TIMER_CH0CV(timerx)              REG32((timerx) + 0x34U)           /*!< TIMER channel 0 capture/compare value register */
+#define TIMER_CH1CV(timerx)              REG32((timerx) + 0x38U)           /*!< TIMER channel 1 capture/compare value register */
+#define TIMER_CH2CV(timerx)              REG32((timerx) + 0x3CU)           /*!< TIMER channel 2 capture/compare value register */
+#define TIMER_CH3CV(timerx)              REG32((timerx) + 0x40U)           /*!< TIMER channel 3 capture/compare value register */
+#define TIMER_CCHP(timerx)               REG32((timerx) + 0x44U)           /*!< TIMER complementary channel protection register */
+#define TIMER_DMACFG(timerx)             REG32((timerx) + 0x48U)           /*!< TIMER DMA configuration register */
+#define TIMER_DMATB(timerx)              REG32((timerx) + 0x4CU)           /*!< TIMER DMA transfer buffer register */
+#define TIMER_IRMP(timerx)               REG32((timerx) + 0x50U)           /*!< TIMER channel input remap register */
+#define TIMER_CFG(timerx)                REG32((timerx) + 0xFCU)           /*!< TIMER configuration register */
+
+/* bits definitions */
+/* TIMER_CTL0 */
+#define TIMER_CTL0_CEN                   BIT(0)              /*!< TIMER counter enable */
+#define TIMER_CTL0_UPDIS                 BIT(1)              /*!< update disable */
+#define TIMER_CTL0_UPS                   BIT(2)              /*!< update source */
+#define TIMER_CTL0_SPM                   BIT(3)              /*!< single pulse mode */
+#define TIMER_CTL0_DIR                   BIT(4)              /*!< timer counter direction */
+#define TIMER_CTL0_CAM                   BITS(5,6)           /*!< center-aligned mode selection */
+#define TIMER_CTL0_ARSE                  BIT(7)              /*!< auto-reload shadow enable */
+#define TIMER_CTL0_CKDIV                 BITS(8,9)           /*!< clock division */
+
+/* TIMER_CTL1 */
+#define TIMER_CTL1_CCSE                  BIT(0)              /*!< commutation control shadow enable */
+#define TIMER_CTL1_CCUC                  BIT(2)              /*!< commutation control shadow register update control */
+#define TIMER_CTL1_DMAS                  BIT(3)              /*!< DMA request source selection */
+#define TIMER_CTL1_MMC                   BITS(4,6)           /*!< master mode control */
+#define TIMER_CTL1_TI0S                  BIT(7)              /*!< channel 0 trigger input selection(hall mode selection) */
+#define TIMER_CTL1_ISO0                  BIT(8)              /*!< idle state of channel 0 output */
+#define TIMER_CTL1_ISO0N                 BIT(9)              /*!< idle state of channel 0 complementary output */
+#define TIMER_CTL1_ISO1                  BIT(10)             /*!< idle state of channel 1 output */
+#define TIMER_CTL1_ISO1N                 BIT(11)             /*!< idle state of channel 1 complementary output */
+#define TIMER_CTL1_ISO2                  BIT(12)             /*!< idle state of channel 2 output */
+#define TIMER_CTL1_ISO2N                 BIT(13)             /*!< idle state of channel 2 complementary output */
+#define TIMER_CTL1_ISO3                  BIT(14)             /*!< idle state of channel 3 output */
+
+/* TIMER_SMCFG */
+#define TIMER_SMCFG_SMC                  BITS(0,2)           /*!< slave mode control */
+#define TIMER_SMCFG_OCRC                 BIT(3)              /*!< OCPRE clear source selection */
+#define TIMER_SMCFG_TRGS                 BITS(4,6)           /*!< trigger selection */
+#define TIMER_SMCFG_MSM                  BIT(7)              /*!< master-slave mode */
+#define TIMER_SMCFG_ETFC                 BITS(8,11)          /*!< external trigger filter control */
+#define TIMER_SMCFG_ETPSC                BITS(12,13)         /*!< external trigger prescaler */
+#define TIMER_SMCFG_SMC1                 BIT(14)             /*!< part of SMC for enable external clock mode 1 */
+#define TIMER_SMCFG_ETP                  BIT(15)             /*!< external trigger polarity */
+ 
+/* TIMER_DMAINTEN */
+#define TIMER_DMAINTEN_UPIE              BIT(0)              /*!< update interrupt enable */
+#define TIMER_DMAINTEN_CH0IE             BIT(1)              /*!< channel 0 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH1IE             BIT(2)              /*!< channel 1 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH2IE             BIT(3)              /*!< channel 2 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH3IE             BIT(4)              /*!< channel 3 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CMTIE             BIT(5)              /*!< commutation interrupt request enable */
+#define TIMER_DMAINTEN_TRGIE             BIT(6)              /*!< trigger interrupt enable */
+#define TIMER_DMAINTEN_BRKIE             BIT(7)              /*!< break interrupt enable */
+#define TIMER_DMAINTEN_UPDEN             BIT(8)              /*!< update DMA request enable */
+#define TIMER_DMAINTEN_CH0DEN            BIT(9)              /*!< channel 0 DMA request enable */
+#define TIMER_DMAINTEN_CH1DEN            BIT(10)             /*!< channel 1 DMA request enable */
+#define TIMER_DMAINTEN_CH2DEN            BIT(11)             /*!< channel 2 DMA request enable */
+#define TIMER_DMAINTEN_CH3DEN            BIT(12)             /*!< channel 3 DMA request enable */
+#define TIMER_DMAINTEN_CMTDEN            BIT(13)             /*!< commutation DMA request enable */
+#define TIMER_DMAINTEN_TRGDEN            BIT(14)             /*!< trigger DMA request enable */
+
+/* TIMER_INTF */
+#define TIMER_INTF_UPIF                  BIT(0)              /*!< update interrupt flag */
+#define TIMER_INTF_CH0IF                 BIT(1)              /*!< channel 0 capture/compare interrupt flag */
+#define TIMER_INTF_CH1IF                 BIT(2)              /*!< channel 1 capture/compare interrupt flag */
+#define TIMER_INTF_CH2IF                 BIT(3)              /*!< channel 2 capture/compare interrupt flag */
+#define TIMER_INTF_CH3IF                 BIT(4)              /*!< channel 3 capture/compare interrupt flag */
+#define TIMER_INTF_CMTIF                 BIT(5)              /*!< channel commutation interrupt flag */
+#define TIMER_INTF_TRGIF                 BIT(6)              /*!< trigger interrupt flag */
+#define TIMER_INTF_BRKIF                 BIT(7)              /*!< break interrupt flag */
+#define TIMER_INTF_CH0OF                 BIT(9)              /*!< channel 0 overcapture flag */
+#define TIMER_INTF_CH1OF                 BIT(10)             /*!< channel 1 overcapture flag */
+#define TIMER_INTF_CH2OF                 BIT(11)             /*!< channel 2 overcapture flag */
+#define TIMER_INTF_CH3OF                 BIT(12)             /*!< channel 3 overcapture flag */
+
+/* TIMER_SWEVG */
+#define TIMER_SWEVG_UPG                  BIT(0)              /*!< update event generate */
+#define TIMER_SWEVG_CH0G                 BIT(1)              /*!< channel 0 capture or compare event generation */
+#define TIMER_SWEVG_CH1G                 BIT(2)              /*!< channel 1 capture or compare event generation */
+#define TIMER_SWEVG_CH2G                 BIT(3)              /*!< channel 2 capture or compare event generation */
+#define TIMER_SWEVG_CH3G                 BIT(4)              /*!< channel 3 capture or compare event generation */
+#define TIMER_SWEVG_CMTG                 BIT(5)              /*!< channel commutation event generation */
+#define TIMER_SWEVG_TRGG                 BIT(6)              /*!< trigger event generation */
+#define TIMER_SWEVG_BRKG                 BIT(7)              /*!< break event generation */
+
+/* TIMER_CHCTL0 */
+/* output compare mode */
+#define TIMER_CHCTL0_CH0MS               BITS(0,1)           /*!< channel 0 mode selection */
+#define TIMER_CHCTL0_CH0COMFEN           BIT(2)              /*!< channel 0 output compare fast enable */
+#define TIMER_CHCTL0_CH0COMSEN           BIT(3)              /*!< channel 0 output compare shadow enable */
+#define TIMER_CHCTL0_CH0COMCTL           BITS(4,6)           /*!< channel 0 output compare mode */
+#define TIMER_CHCTL0_CH0COMCEN           BIT(7)              /*!< channel 0 output compare clear enable */
+#define TIMER_CHCTL0_CH1MS               BITS(8,9)           /*!< channel 1 mode selection */
+#define TIMER_CHCTL0_CH1COMFEN           BIT(10)             /*!< channel 1 output compare fast enable */
+#define TIMER_CHCTL0_CH1COMSEN           BIT(11)             /*!< channel 1 output compare shadow enable */
+#define TIMER_CHCTL0_CH1COMCTL           BITS(12,14)         /*!< channel 1 output compare mode */
+#define TIMER_CHCTL0_CH1COMCEN           BIT(15)             /*!< channel 1 output compare clear enable */
+/* input capture mode */
+#define TIMER_CHCTL0_CH0CAPPSC           BITS(2,3)           /*!< channel 0 input capture prescaler */
+#define TIMER_CHCTL0_CH0CAPFLT           BITS(4,7)           /*!< channel 0 input capture filter control */
+#define TIMER_CHCTL0_CH1CAPPSC           BITS(10,11)         /*!< channel 1 input capture prescaler */
+#define TIMER_CHCTL0_CH1CAPFLT           BITS(12,15)         /*!< channel 1 input capture filter control */
+
+/* TIMER_CHCTL1 */
+/* output compare mode */
+#define TIMER_CHCTL1_CH2MS               BITS(0,1)           /*!< channel 2 mode selection */
+#define TIMER_CHCTL1_CH2COMFEN           BIT(2)              /*!< channel 2 output compare fast enable */
+#define TIMER_CHCTL1_CH2COMSEN           BIT(3)              /*!< channel 2 output compare shadow enable */
+#define TIMER_CHCTL1_CH2COMCTL           BITS(4,6)           /*!< channel 2 output compare mode */
+#define TIMER_CHCTL1_CH2COMCEN           BIT(7)              /*!< channel 2 output compare clear enable */
+#define TIMER_CHCTL1_CH3MS               BITS(8,9)           /*!< channel 3 mode selection */
+#define TIMER_CHCTL1_CH3COMFEN           BIT(10)             /*!< channel 3 output compare fast enable */
+#define TIMER_CHCTL1_CH3COMSEN           BIT(11)             /*!< channel 3 output compare shadow enable */
+#define TIMER_CHCTL1_CH3COMCTL           BITS(12,14)         /*!< channel 3 output compare mode */
+#define TIMER_CHCTL1_CH3COMCEN           BIT(15)             /*!< channel 3 output compare clear enable */
+/* input capture mode */
+#define TIMER_CHCTL1_CH2CAPPSC           BITS(2,3)           /*!< channel 2 input capture prescaler */
+#define TIMER_CHCTL1_CH2CAPFLT           BITS(4,7)           /*!< channel 2 input capture filter control */
+#define TIMER_CHCTL1_CH3CAPPSC           BITS(10,11)         /*!< channel 3 input capture prescaler */
+#define TIMER_CHCTL1_CH3CAPFLT           BITS(12,15)         /*!< channel 3 input capture filter control */
+
+/* TIMER_CHCTL2 */
+#define TIMER_CHCTL2_CH0EN               BIT(0)              /*!< channel 0 capture/compare function enable */
+#define TIMER_CHCTL2_CH0P                BIT(1)              /*!< channel 0 capture/compare function polarity */
+#define TIMER_CHCTL2_CH0NEN              BIT(2)              /*!< channel 0 complementary output enable */
+#define TIMER_CHCTL2_CH0NP               BIT(3)              /*!< channel 0 complementary output polarity */
+#define TIMER_CHCTL2_CH1EN               BIT(4)              /*!< channel 1 capture/compare function enable  */
+#define TIMER_CHCTL2_CH1P                BIT(5)              /*!< channel 1 capture/compare function polarity */
+#define TIMER_CHCTL2_CH1NEN              BIT(6)              /*!< channel 1 complementary output enable */
+#define TIMER_CHCTL2_CH1NP               BIT(7)              /*!< channel 1 complementary output polarity */
+#define TIMER_CHCTL2_CH2EN               BIT(8)              /*!< channel 2 capture/compare function enable  */
+#define TIMER_CHCTL2_CH2P                BIT(9)              /*!< channel 2 capture/compare function polarity */
+#define TIMER_CHCTL2_CH2NEN              BIT(10)             /*!< channel 2 complementary output enable */
+#define TIMER_CHCTL2_CH2NP               BIT(11)             /*!< channel 2 complementary output polarity */
+#define TIMER_CHCTL2_CH3EN               BIT(12)             /*!< channel 3 capture/compare function enable  */
+#define TIMER_CHCTL2_CH3P                BIT(13)             /*!< channel 3 capture/compare function polarity */
+#define TIMER_CHCTL2_CH3NP               BIT(15)             /*!< channel 3 complementary output polarity */
+
+/* TIMER_CNT */
+#define TIMER_CNT_CNT16                  BITS(0,15)          /*!< 16 bit timer counter */
+
+/* TIMER_PSC */
+#define TIMER_PSC_PSC                    BITS(0,15)          /*!< prescaler value of the counter clock */
+
+/* TIMER_CAR */
+#define TIMER_CAR_CARL16                 BITS(0,15)          /*!< 16 bit counter auto reload value */
+
+/* TIMER_CREP */
+#define TIMER_CREP_CREP                  BITS(0,7)           /*!< counter repetition value */
+
+/* TIMER_CH0CV */
+#define TIMER_CH0CV_CH0VAL16             BITS(0,15)          /*!< 16 bit capture/compare value of channel 0 */
+
+/* TIMER_CH1CV */
+#define TIMER_CH1CV_CH1VAL16             BITS(0,15)          /*!< 16 bit capture/compare value of channel 1 */
+
+/* TIMER_CH2CV */
+#define TIMER_CH2CV_CH2VAL16             BITS(0,15)          /*!< 16 bit capture/compare value of channel 2 */
+
+/* TIMER_CH3CV */
+#define TIMER_CH3CV_CH3VAL16             BITS(0,15)          /*!< 16 bit capture/compare value of channel 3 */
+
+/* TIMER_CCHP */
+#define TIMER_CCHP_DTCFG                 BITS(0,7)           /*!< dead time configure */
+#define TIMER_CCHP_PROT                  BITS(8,9)           /*!< complementary register protect control */
+#define TIMER_CCHP_IOS                   BIT(10)             /*!< idle mode off-state configure */
+#define TIMER_CCHP_ROS                   BIT(11)             /*!< run mode off-state configure */
+#define TIMER_CCHP_BRKEN                 BIT(12)             /*!< break enable */
+#define TIMER_CCHP_BRKP                  BIT(13)             /*!< break polarity */
+#define TIMER_CCHP_OAEN                  BIT(14)             /*!< output automatic enable */
+#define TIMER_CCHP_POEN                  BIT(15)             /*!< primary output enable */
+
+/* TIMER_DMACFG */
+#define TIMER_DMACFG_DMATA               BITS(0,4)           /*!< DMA transfer access start address */
+#define TIMER_DMACFG_DMATC               BITS(8,12)          /*!< DMA transfer count */
+
+/* TIMER_DMATB */
+#define TIMER_DMATB_DMATB                BITS(0,15)          /*!< DMA transfer buffer address */
+
+/* TIMER_IRMP */
+#define TIMER13_IRMP_CI0_RMP             BITS(0,1)           /*!< TIMER13 channel 0 input remap */
+
+/* TIMER_CFG */
+#define TIMER_CFG_OUTSEL                 BIT(0)              /*!< the output value selection */
+#define TIMER_CFG_CHVSEL                 BIT(1)              /*!< write CHxVAL register selection */
+
+/* constants definitions */
+/* TIMER init parameter struct definitions*/
+typedef struct
+{ 
+    uint16_t prescaler;                         /*!< prescaler value */
+    uint16_t alignedmode;                       /*!< aligned mode */
+    uint16_t counterdirection;                  /*!< counter direction */
+    uint16_t clockdivision;                     /*!< clock division value */
+    uint32_t period;                            /*!< period value */
+    uint8_t  repetitioncounter;                 /*!< the counter repetition value */
+}timer_parameter_struct;
+
+/* break parameter struct definitions*/
+typedef struct
+{ 
+    uint16_t runoffstate;                       /*!< run mode off-state */
+    uint16_t ideloffstate;                      /*!< idle mode off-state */
+    uint16_t deadtime;                          /*!< dead time */
+    uint16_t breakpolarity;                     /*!< break polarity */
+    uint16_t outputautostate;                   /*!< output automatic enable */
+    uint16_t protectmode;                       /*!< complementary register protect control */
+    uint16_t breakstate;                        /*!< break enable */
+}timer_break_parameter_struct;
+
+/* channel output parameter struct definitions */
+typedef struct
+{ 
+    uint16_t outputstate;                       /*!< channel output state */
+    uint16_t outputnstate;                      /*!< channel complementary output state */
+    uint16_t ocpolarity;                        /*!< channel output polarity */
+    uint16_t ocnpolarity;                       /*!< channel complementary output polarity */
+    uint16_t ocidlestate;                       /*!< idle state of channel output */
+    uint16_t ocnidlestate;                      /*!< idle state of channel complementary output */
+}timer_oc_parameter_struct;
+
+/* channel input parameter struct definitions */
+typedef struct
+{ 
+    uint16_t icpolarity;                        /*!< channel input polarity */
+    uint16_t icselection;                       /*!< channel input mode selection */
+    uint16_t icprescaler;                       /*!< channel input capture prescaler */
+    uint16_t icfilter;                          /*!< channel input capture filter control */
+}timer_ic_parameter_struct;
+
+/* TIMER interrupt enable or disable */
+#define TIMER_INT_UP                        TIMER_DMAINTEN_UPIE                     /*!< update interrupt */
+#define TIMER_INT_CH0                       TIMER_DMAINTEN_CH0IE                    /*!< channel 0 interrupt */
+#define TIMER_INT_CH1                       TIMER_DMAINTEN_CH1IE                    /*!< channel 1 interrupt */
+#define TIMER_INT_CH2                       TIMER_DMAINTEN_CH2IE                    /*!< channel 2 interrupt */
+#define TIMER_INT_CH3                       TIMER_DMAINTEN_CH3IE                    /*!< channel 3 interrupt */
+#define TIMER_INT_CMT                       TIMER_DMAINTEN_CMTIE                    /*!< channel commutation interrupt flag */
+#define TIMER_INT_TRG                       TIMER_DMAINTEN_TRGIE                    /*!< trigger interrupt */
+#define TIMER_INT_BRK                       TIMER_DMAINTEN_BRKIE                    /*!< break interrupt */
+
+/* TIMER flag */
+#define TIMER_FLAG_UP                       TIMER_INTF_UPIF                         /*!< update flag */
+#define TIMER_FLAG_CH0                      TIMER_INTF_CH0IF                        /*!< channel 0 flag */
+#define TIMER_FLAG_CH1                      TIMER_INTF_CH1IF                        /*!< channel 1 flag */
+#define TIMER_FLAG_CH2                      TIMER_INTF_CH2IF                        /*!< channel 2 flag */
+#define TIMER_FLAG_CH3                      TIMER_INTF_CH3IF                        /*!< channel 3 flag */
+#define TIMER_FLAG_CMT                      TIMER_INTF_CMTIF                        /*!< channel commutation flag */
+#define TIMER_FLAG_TRG                      TIMER_INTF_TRGIF                        /*!< trigger flag */
+#define TIMER_FLAG_BRK                      TIMER_INTF_BRKIF                        /*!< break flag */
+#define TIMER_FLAG_CH0O                     TIMER_INTF_CH0OF                        /*!< channel 0 overcapture flag */
+#define TIMER_FLAG_CH1O                     TIMER_INTF_CH1OF                        /*!< channel 1 overcapture flag */
+#define TIMER_FLAG_CH2O                     TIMER_INTF_CH2OF                        /*!< channel 2 overcapture flag */
+#define TIMER_FLAG_CH3O                     TIMER_INTF_CH3OF                        /*!< channel 3 overcapture flag */
+
+/* TIMER interrupt flag */
+#define TIMER_INT_FLAG_UP                   TIMER_INTF_UPIF                         /*!< update interrupt flag */
+#define TIMER_INT_FLAG_CH0                  TIMER_INTF_CH0IF                        /*!< channel 0 interrupt flag */
+#define TIMER_INT_FLAG_CH1                  TIMER_INTF_CH1IF                        /*!< channel 1 interrupt flag */
+#define TIMER_INT_FLAG_CH2                  TIMER_INTF_CH2IF                        /*!< channel 2 interrupt flag */
+#define TIMER_INT_FLAG_CH3                  TIMER_INTF_CH3IF                        /*!< channel 3 interrupt flag */
+#define TIMER_INT_FLAG_CMT                  TIMER_INTF_CMTIF                        /*!< channel commutation interrupt flag */
+#define TIMER_INT_FLAG_TRG                  TIMER_INTF_TRGIF                        /*!< trigger interrupt flag */
+#define TIMER_INT_FLAG_BRK                  TIMER_INTF_BRKIF
+
+/* TIMER DMA source enable */
+#define TIMER_DMA_UPD                       ((uint16_t)TIMER_DMAINTEN_UPDEN)        /*!< update DMA enable */
+#define TIMER_DMA_CH0D                      ((uint16_t)TIMER_DMAINTEN_CH0DEN)       /*!< channel 0 DMA enable */
+#define TIMER_DMA_CH1D                      ((uint16_t)TIMER_DMAINTEN_CH1DEN)       /*!< channel 1 DMA enable */
+#define TIMER_DMA_CH2D                      ((uint16_t)TIMER_DMAINTEN_CH2DEN)       /*!< channel 2 DMA enable */
+#define TIMER_DMA_CH3D                      ((uint16_t)TIMER_DMAINTEN_CH3DEN)       /*!< channel 3 DMA enable */
+#define TIMER_DMA_CMTD                      ((uint16_t)TIMER_DMAINTEN_CMTDEN)       /*!< commutation DMA request enable */
+#define TIMER_DMA_TRGD                      ((uint16_t)TIMER_DMAINTEN_TRGDEN)       /*!< trigger DMA enable */
+
+/* channel DMA request source selection */ 
+#define TIMER_DMAREQUEST_UPDATEEVENT        TIMER_CTL1_DMAS                         /*!< DMA request of channel y is sent when update event occurs */
+#define TIMER_DMAREQUEST_CHANNELEVENT       ((uint32_t)0x00000000U)                 /*!< DMA request of channel y is sent when channel y event occurs */
+
+/* DMA access base address */
+#define DMACFG_DMATA(regval)                (BITS(0, 4) & ((uint32_t)(regval) << 0U))
+#define TIMER_DMACFG_DMATA_CTL0             DMACFG_DMATA(0)                         /*!< DMA transfer address is TIMER_CTL0 */
+#define TIMER_DMACFG_DMATA_CTL1             DMACFG_DMATA(1)                         /*!< DMA transfer address is TIMER_CTL1 */
+#define TIMER_DMACFG_DMATA_SMCFG            DMACFG_DMATA(2)                         /*!< DMA transfer address is TIMER_SMCFG */
+#define TIMER_DMACFG_DMATA_DMAINTEN         DMACFG_DMATA(3)                         /*!< DMA transfer address is TIMER_DMAINTEN */
+#define TIMER_DMACFG_DMATA_INTF             DMACFG_DMATA(4)                         /*!< DMA transfer address is TIMER_INTF */
+#define TIMER_DMACFG_DMATA_SWEVG            DMACFG_DMATA(5)                         /*!< DMA transfer address is TIMER_SWEVG */
+#define TIMER_DMACFG_DMATA_CHCTL0           DMACFG_DMATA(6)                         /*!< DMA transfer address is TIMER_CHCTL0 */
+#define TIMER_DMACFG_DMATA_CHCTL1           DMACFG_DMATA(7)                         /*!< DMA transfer address is TIMER_CHCTL1 */
+#define TIMER_DMACFG_DMATA_CHCTL2           DMACFG_DMATA(8)                         /*!< DMA transfer address is TIMER_CHCTL2 */
+#define TIMER_DMACFG_DMATA_CNT              DMACFG_DMATA(9)                         /*!< DMA transfer address is TIMER_CNT */
+#define TIMER_DMACFG_DMATA_PSC              DMACFG_DMATA(10)                        /*!< DMA transfer address is TIMER_PSC */
+#define TIMER_DMACFG_DMATA_CAR              DMACFG_DMATA(11)                        /*!< DMA transfer address is TIMER_CAR */
+#define TIMER_DMACFG_DMATA_CREP             DMACFG_DMATA(12)                        /*!< DMA transfer address is TIMER_CREP */
+#define TIMER_DMACFG_DMATA_CH0CV            DMACFG_DMATA(13)                        /*!< DMA transfer address is TIMER_CH0CV */
+#define TIMER_DMACFG_DMATA_CH1CV            DMACFG_DMATA(14)                        /*!< DMA transfer address is TIMER_CH1CV */
+#define TIMER_DMACFG_DMATA_CH2CV            DMACFG_DMATA(15)                        /*!< DMA transfer address is TIMER_CH2CV */
+#define TIMER_DMACFG_DMATA_CH3CV            DMACFG_DMATA(16)                        /*!< DMA transfer address is TIMER_CH3CV */
+#define TIMER_DMACFG_DMATA_CCHP             DMACFG_DMATA(17)                        /*!< DMA transfer address is TIMER_CCHP */
+#define TIMER_DMACFG_DMATA_DMACFG           DMACFG_DMATA(18)                        /*!< DMA transfer address is TIMER_DMACFG */
+
+/* DMA access burst length */
+#define DMACFG_DMATC(regval)                (BITS(8, 12) & ((uint32_t)(regval) << 8U))
+#define TIMER_DMACFG_DMATC_1TRANSFER        DMACFG_DMATC(0)                         /*!< DMA transfer 1 time */
+#define TIMER_DMACFG_DMATC_2TRANSFER        DMACFG_DMATC(1)                         /*!< DMA transfer 2 times */
+#define TIMER_DMACFG_DMATC_3TRANSFER        DMACFG_DMATC(2)                         /*!< DMA transfer 3 times */
+#define TIMER_DMACFG_DMATC_4TRANSFER        DMACFG_DMATC(3)                         /*!< DMA transfer 4 times */
+#define TIMER_DMACFG_DMATC_5TRANSFER        DMACFG_DMATC(4)                         /*!< DMA transfer 5 times */
+#define TIMER_DMACFG_DMATC_6TRANSFER        DMACFG_DMATC(5)                         /*!< DMA transfer 6 times */
+#define TIMER_DMACFG_DMATC_7TRANSFER        DMACFG_DMATC(6)                         /*!< DMA transfer 7 times */
+#define TIMER_DMACFG_DMATC_8TRANSFER        DMACFG_DMATC(7)                         /*!< DMA transfer 8 times */
+#define TIMER_DMACFG_DMATC_9TRANSFER        DMACFG_DMATC(8)                         /*!< DMA transfer 9 times */
+#define TIMER_DMACFG_DMATC_10TRANSFER       DMACFG_DMATC(9)                         /*!< DMA transfer 10 times */
+#define TIMER_DMACFG_DMATC_11TRANSFER       DMACFG_DMATC(10)                        /*!< DMA transfer 11 times */
+#define TIMER_DMACFG_DMATC_12TRANSFER       DMACFG_DMATC(11)                        /*!< DMA transfer 12 times */
+#define TIMER_DMACFG_DMATC_13TRANSFER       DMACFG_DMATC(12)                        /*!< DMA transfer 13 times */
+#define TIMER_DMACFG_DMATC_14TRANSFER       DMACFG_DMATC(13)                        /*!< DMA transfer 14 times */
+#define TIMER_DMACFG_DMATC_15TRANSFER       DMACFG_DMATC(14)                        /*!< DMA transfer 15 times */
+#define TIMER_DMACFG_DMATC_16TRANSFER       DMACFG_DMATC(15)                        /*!< DMA transfer 16 times */
+#define TIMER_DMACFG_DMATC_17TRANSFER       DMACFG_DMATC(16)                        /*!< DMA transfer 17 times */
+#define TIMER_DMACFG_DMATC_18TRANSFER       DMACFG_DMATC(17)                        /*!< DMA transfer 18 times */
+
+/* TIMER software event generation source */
+#define TIMER_EVENT_SRC_UPG                 ((uint16_t)0x0001U)                     /*!< update event generation */
+#define TIMER_EVENT_SRC_CH0G                ((uint16_t)0x0002U)                     /*!< channel 0 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH1G                ((uint16_t)0x0004U)                     /*!< channel 1 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH2G                ((uint16_t)0x0008U)                     /*!< channel 2 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH3G                ((uint16_t)0x0010U)                     /*!< channel 3 capture or compare event generation */
+#define TIMER_EVENT_SRC_CMTG                ((uint16_t)0x0020U)                     /*!< channel commutation event generation */
+#define TIMER_EVENT_SRC_TRGG                ((uint16_t)0x0040U)                     /*!< trigger event generation */
+#define TIMER_EVENT_SRC_BRKG                ((uint16_t)0x0080U)                     /*!< break event generation */
+
+/* center-aligned mode selection */
+#define CTL0_CAM(regval)                    ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
+#define TIMER_COUNTER_EDGE                  CTL0_CAM(0)                             /*!< edge-aligned mode */
+#define TIMER_COUNTER_CENTER_DOWN           CTL0_CAM(1)                             /*!< center-aligned and counting down assert mode */
+#define TIMER_COUNTER_CENTER_UP             CTL0_CAM(2)                             /*!< center-aligned and counting up assert mode */
+#define TIMER_COUNTER_CENTER_BOTH           CTL0_CAM(3)                             /*!< center-aligned and counting up/down assert mode */
+
+/* TIMER prescaler reload mode */
+#define TIMER_PSC_RELOAD_NOW                TIMER_SWEVG_UPG                         /*!< the prescaler is loaded right now */
+#define TIMER_PSC_RELOAD_UPDATE             ((uint32_t)0x00000000U)                 /*!< the prescaler is loaded at the next update event */
+
+/* count direction */
+#define TIMER_COUNTER_UP                    ((uint16_t)0x0000U)                     /*!< counter up direction */
+#define TIMER_COUNTER_DOWN                  ((uint16_t)TIMER_CTL0_DIR)              /*!< counter down direction */
+
+/* specify division ratio between TIMER clock and dead-time and sampling clock */
+#define CTL0_CKDIV(regval)                  ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
+#define TIMER_CKDIV_DIV1                    CTL0_CKDIV(0)                           /*!< clock division value is 1, fDTS=fTIMER_CK */
+#define TIMER_CKDIV_DIV2                    CTL0_CKDIV(1)                           /*!< clock division value is 2, fDTS= fTIMER_CK/2 */
+#define TIMER_CKDIV_DIV4                    CTL0_CKDIV(2)                           /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
+
+/* single pulse mode */
+#define TIMER_SP_MODE_SINGLE                TIMER_CTL0_SPM                          /*!< single pulse mode */
+#define TIMER_SP_MODE_REPETITIVE            ((uint32_t)0x00000000U)                 /*!< repetitive pulse mode */
+
+/* update source */
+#define TIMER_UPDATE_SRC_REGULAR            TIMER_CTL0_UPS                          /*!< update generate only by counter overflow/underflow */
+#define TIMER_UPDATE_SRC_GLOBAL            ((uint32_t)0x00000000U)                  /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
+
+/* run mode off-state configure */
+#define TIMER_ROS_STATE_ENABLE              ((uint16_t)TIMER_CCHP_ROS)              /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_ROS_STATE_DISABLE             ((uint16_t)0x0000U)                     /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */
+
+/* idle mode off-state configure */                                                 
+#define TIMER_IOS_STATE_ENABLE              ((uint16_t)TIMER_CCHP_IOS)              /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_IOS_STATE_DISABLE             ((uint16_t)0x0000U)                     /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */
+
+/* break input polarity */
+#define TIMER_BREAK_POLARITY_LOW            ((uint16_t)0x0000U)                     /*!< break input polarity is low */
+#define TIMER_BREAK_POLARITY_HIGH           ((uint16_t)TIMER_CCHP_BRKP)             /*!< break input polarity is high */
+
+/* output automatic enable */
+#define TIMER_OUTAUTO_ENABLE                ((uint16_t)TIMER_CCHP_OAEN)             /*!< output automatic enable */
+#define TIMER_OUTAUTO_DISABLE               ((uint16_t)0x0000U)                     /*!< output automatic disable */
+
+/* complementary register protect control */
+#define CCHP_PROT(regval)                   ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
+#define TIMER_CCHP_PROT_OFF                 CCHP_PROT(0)                            /*!< protect disable */
+#define TIMER_CCHP_PROT_0                   CCHP_PROT(1)                            /*!< PROT mode 0 */
+#define TIMER_CCHP_PROT_1                   CCHP_PROT(2)                            /*!< PROT mode 1 */
+#define TIMER_CCHP_PROT_2                   CCHP_PROT(3)                            /*!< PROT mode 2 */
+
+/* break input enable */
+#define TIMER_BREAK_ENABLE                  ((uint16_t)TIMER_CCHP_BRKEN)            /*!< break input enable */
+#define TIMER_BREAK_DISABLE                 ((uint16_t)0x0000U)                     /*!< break input disable */
+
+/* TIMER channel n(n=0,1,2,3) */
+#define TIMER_CH_0                          ((uint16_t)0x0000U)                     /*!< TIMER channel 0(TIMERx(x=0,2,13..16)) */
+#define TIMER_CH_1                          ((uint16_t)0x0001U)                     /*!< TIMER channel 1(TIMERx(x=0,2,14)) */
+#define TIMER_CH_2                          ((uint16_t)0x0002U)                     /*!< TIMER channel 2(TIMERx(x=0,2)) */
+#define TIMER_CH_3                          ((uint16_t)0x0003U)                     /*!< TIMER channel 3(TIMERx(x=0,2)) */
+#define TIMER_CH_0_1                        ((uint16_t)0x0004U)                     /*!< TIMER channel 0 and 1 for function parameter */
+
+/* channel enable state*/
+#define TIMER_CCX_ENABLE                    ((uint32_t)0x00000001U)                 /*!< channel enable */
+#define TIMER_CCX_DISABLE                   ((uint32_t)0x00000000U)                 /*!< channel disable */
+
+/* channel complementary output enable state*/
+#define TIMER_CCXN_ENABLE                   ((uint16_t)0x0004U)                     /*!< channel complementary enable */
+#define TIMER_CCXN_DISABLE                  ((uint16_t)0x0000U)                     /*!< channel complementary disable */
+
+/* channel output polarity */
+#define TIMER_OC_POLARITY_HIGH              ((uint16_t)0x0000U)                     /*!< channel output polarity is high */
+#define TIMER_OC_POLARITY_LOW               ((uint16_t)0x0002U)                     /*!< channel output polarity is low */
+
+/* channel complementary output polarity */
+#define TIMER_OCN_POLARITY_HIGH             ((uint16_t)0x0000U)                     /*!< channel complementary output polarity is high */
+#define TIMER_OCN_POLARITY_LOW              ((uint16_t)0x0008U)                     /*!< channel complementary output polarity is low */
+
+/* idle state of channel output */ 
+#define TIMER_OC_IDLE_STATE_HIGH            ((uint16_t)0x0100)                      /*!< idle state of channel output is high */
+#define TIMER_OC_IDLE_STATE_LOW             ((uint16_t)0x0000)                      /*!< idle state of channel output is low */
+
+/* idle state of channel complementary output */ 
+#define TIMER_OCN_IDLE_STATE_HIGH           ((uint16_t)0x0200U)                     /*!< idle state of channel complementary output is high */
+#define TIMER_OCN_IDLE_STATE_LOW            ((uint16_t)0x0000U)                     /*!< idle state of channel complementary output is low */
+
+/* channel output compare mode */
+#define TIMER_OC_MODE_TIMING                ((uint16_t)0x0000U)                     /*!< timing mode */
+#define TIMER_OC_MODE_ACTIVE                ((uint16_t)0x0010U)                     /*!< active mode */
+#define TIMER_OC_MODE_INACTIVE              ((uint16_t)0x0020U)                     /*!< inactive mode */
+#define TIMER_OC_MODE_TOGGLE                ((uint16_t)0x0030U)                     /*!< toggle mode */
+#define TIMER_OC_MODE_LOW                   ((uint16_t)0x0040U)                     /*!< force low mode */
+#define TIMER_OC_MODE_HIGH                  ((uint16_t)0x0050U)                     /*!< force high mode */
+#define TIMER_OC_MODE_PWM0                  ((uint16_t)0x0060U)                     /*!< PWM0 mode */
+#define TIMER_OC_MODE_PWM1                  ((uint16_t)0x0070U)                     /*!< PWM1 mode*/
+
+/* channel output compare shadow enable */
+#define TIMER_OC_SHADOW_ENABLE              ((uint16_t)0x0008U)                     /*!< channel output shadow state enable */
+#define TIMER_OC_SHADOW_DISABLE             ((uint16_t)0x0000U)                     /*!< channel output shadow state disable */
+
+/* channel output compare fast enable */
+#define TIMER_OC_FAST_ENABLE                ((uint16_t)0x0004)                      /*!< channel output fast function enable */
+#define TIMER_OC_FAST_DISABLE               ((uint16_t)0x0000)                      /*!< channel output fast function disable */
+
+/* channel output compare clear enable */
+#define TIMER_OC_CLEAR_ENABLE               ((uint16_t)0x0080U)                     /*!< channel output clear function enable */
+#define TIMER_OC_CLEAR_DISABLE              ((uint16_t)0x0000U)                     /*!< channel output clear function disable */
+
+/* channel control shadow register update control */ 
+#define TIMER_UPDATECTL_CCU                 ((uint32_t)0x00000000U)                 /*!< the shadow registers are updated when CMTG bit is set */
+#define TIMER_UPDATECTL_CCUTRI              TIMER_CTL1_CCUC                         /*!< the shadow registers are updated when CMTG bit is set or an rising edge of TRGI occurs */
+
+/* channel input capture polarity */
+#define TIMER_IC_POLARITY_RISING            ((uint16_t)0x0000U)                     /*!< input capture rising edge */
+#define TIMER_IC_POLARITY_FALLING           ((uint16_t)0x0002U)                     /*!< input capture falling edge */
+#define TIMER_IC_POLARITY_BOTH_EDGE         ((uint16_t)0x000AU)                     /*!< input capture both edge */
+
+/* TIMER input capture selection */
+#define TIMER_IC_SELECTION_DIRECTTI         ((uint16_t)0x0001U)                     /*!< channel y is configured as input and icy is mapped on CIy */
+#define TIMER_IC_SELECTION_INDIRECTTI       ((uint16_t)0x0002U)                     /*!< channel y is configured as input and icy is mapped on opposite input */
+#define TIMER_IC_SELECTION_ITS              ((uint16_t)0x0003U)                     /*!< channel y is configured as input and icy is mapped on ITS */
+
+/* channel input capture prescaler */
+#define TIMER_IC_PSC_DIV1                   ((uint16_t)0x0000U)                     /*!< no prescaler */
+#define TIMER_IC_PSC_DIV2                   ((uint16_t)0x0004U)                     /*!< divided by 2 */
+#define TIMER_IC_PSC_DIV4                   ((uint16_t)0x0008U)                     /*!< divided by 4*/
+#define TIMER_IC_PSC_DIV8                   ((uint16_t)0x000CU)                     /*!< divided by 8 */
+
+/* trigger selection */
+#define SMCFG_TRGSEL(regval)                (BITS(4, 6) & ((uint32_t)(regval) << 4U))
+#define TIMER_SMCFG_TRGSEL_ITI0              SMCFG_TRGSEL(0)                        /*!< internal trigger 0 */
+#define TIMER_SMCFG_TRGSEL_ITI1              SMCFG_TRGSEL(1)                        /*!< internal trigger 1 */
+#define TIMER_SMCFG_TRGSEL_ITI2              SMCFG_TRGSEL(2)                        /*!< internal trigger 2 */
+#define TIMER_SMCFG_TRGSEL_ITI3              SMCFG_TRGSEL(3)                        /*!< internal trigger 3 */
+#define TIMER_SMCFG_TRGSEL_CI0F_ED           SMCFG_TRGSEL(4)                        /*!< TI0 Edge Detector */
+#define TIMER_SMCFG_TRGSEL_CI0FE0            SMCFG_TRGSEL(5)                        /*!< filtered TIMER input 0 */
+#define TIMER_SMCFG_TRGSEL_CI1FE1            SMCFG_TRGSEL(6)                        /*!< filtered TIMER input 1 */
+#define TIMER_SMCFG_TRGSEL_ETIFP             SMCFG_TRGSEL(7)                        /*!< external trigger */
+
+/* master mode control */
+#define CTL1_MMC(regval)                    (BITS(4, 6) & ((uint32_t)(regval) << 4U))
+#define TIMER_TRI_OUT_SRC_RESET             CTL1_MMC(0)                             /*!< the UPG bit as trigger output */
+#define TIMER_TRI_OUT_SRC_ENABLE            CTL1_MMC(1)                             /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
+#define TIMER_TRI_OUT_SRC_UPDATE            CTL1_MMC(2)                             /*!< update event as trigger output */
+#define TIMER_TRI_OUT_SRC_CH0               CTL1_MMC(3)                             /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */
+#define TIMER_TRI_OUT_SRC_O0CPRE            CTL1_MMC(4)                             /*!< O0CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O1CPRE            CTL1_MMC(5)                             /*!< O1CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O2CPRE            CTL1_MMC(6)                             /*!< O2CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O3CPRE            CTL1_MMC(7)                             /*!< O3CPRE as trigger output */
+
+/* slave mode control */
+#define SMCFG_SMC(regval)                   (BITS(0, 2) & ((uint32_t)(regval) << 0U)) 
+#define TIMER_SLAVE_MODE_DISABLE            SMCFG_SMC(0)                            /*!< slave mode disable */
+#define TIMER_ENCODER_MODE0                 SMCFG_SMC(1)                            /*!< encoder mode 0 */
+#define TIMER_ENCODER_MODE1                 SMCFG_SMC(2)                            /*!< encoder mode 1 */
+#define TIMER_ENCODER_MODE2                 SMCFG_SMC(3)                            /*!< encoder mode 2 */
+#define TIMER_SLAVE_MODE_RESTART            SMCFG_SMC(4)                            /*!< restart mode */
+#define TIMER_SLAVE_MODE_PAUSE              SMCFG_SMC(5)                            /*!< pause mode */
+#define TIMER_SLAVE_MODE_EVENT              SMCFG_SMC(6)                            /*!< event mode */
+#define TIMER_SLAVE_MODE_EXTERNAL0          SMCFG_SMC(7)                            /*!< external clock mode 0 */
+
+/* OCPRE clear source selection */                                                  
+#define TIMER_OCPRE_CLEAR_SOURCE_CLR        ((uint8_t)0x00U)                        /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */
+#define TIMER_OCPRE_CLEAR_SOURCE_ETIF       ((uint8_t)0x01U)                        /*!< OCPRE_CLR_INT is connected to ETIF */
+#define TIMER_OCPRE_CLEAR_SOURCE_DISABLE    ((uint8_t)0x02U)                        /*!< OCRC=0, and disable ETI */
+
+/* master slave mode selection */ 
+#define TIMER_MASTER_SLAVE_MODE_ENABLE      TIMER_SMCFG_MSM                         /*!< master slave mode enable */
+#define TIMER_MASTER_SLAVE_MODE_DISABLE     ((uint32_t)0x00000000U)                 /*!< master slave mode disable */
+
+/* external trigger prescaler */
+#define SMCFG_ETPSC(regval)                 (BITS(12, 13) & ((uint32_t)(regval) << 12U))
+#define TIMER_EXT_TRI_PSC_OFF               SMCFG_ETPSC(0)                          /*!< no divided */
+#define TIMER_EXT_TRI_PSC_DIV2              SMCFG_ETPSC(1)                          /*!< divided by 2 */
+#define TIMER_EXT_TRI_PSC_DIV4              SMCFG_ETPSC(2)                          /*!< divided by 4 */
+#define TIMER_EXT_TRI_PSC_DIV8              SMCFG_ETPSC(3)                          /*!< divided by 8 */
+
+/* external trigger polarity */
+#define TIMER_ETP_FALLING                   TIMER_SMCFG_ETP                         /*!< active low or falling edge active */
+#define TIMER_ETP_RISING                    ((uint32_t)0x00000000U)                 /*!< active high or rising edge active */
+
+/* channel 0 trigger input selection */ 
+#define TIMER_HALLINTERFACE_ENABLE          TIMER_CTL1_TI0S                         /*!< TIMER hall sensor mode enable */
+#define TIMER_HALLINTERFACE_DISABLE         ((uint32_t)0x00000000U)                 /*!< TIMER hall sensor mode disable */
+
+/* TIMERx(x=0,2,13,14,15,16) write cc register selection */
+#define TIMER_CHVSEL_ENABLE                 ((uint16_t)TIMER_CFG_OUTSEL)            /*!< write CHxVAL register selection enable */
+#define TIMER_CHVSEL_DISABLE                ((uint16_t)0x0000U)                     /*!< write CC register selection enable */
+
+/* the output value selection */
+#define TIMER_OUTSEL_ENABLE                 ((uint16_t)TIMER_CFG_OUTSEL)            /*!< output value selection enable */
+#define TIMER_OUTSEL_DISABLE                ((uint16_t)0x0000U)                     /*!< output value selection enable */
+
+/* timer13 channel 0 input remap */
+#define TIMER13_IRMP(regval)                (BITS(0, 1) & ((uint32_t)(regval) << 0U))       
+#define TIMER13_CI0_RMP_GPIO                TIMER13_IRMP(0)                         /*!< timer13 channel 0 input is connected to GPIO(TIMER13_CH0) */
+#define TIMER13_CI0_RMP_RTCCLK              TIMER13_IRMP(1)                         /*!< timer13 channel 0 input is connected to the RTCCLK */
+#define TIMER13_CI0_RMP_HXTAL_DIV32         TIMER13_IRMP(2)                         /*!< timer13 channel 0 input is connected to HXTAL/32 clock */
+#define TIMER13_CI0_RMP_CKOUTSEL            TIMER13_IRMP(3)                         /*!< timer13 channel 0 input is connected to CKOUTSEL */
+
+/* function declarations */
+/* TIMER timebase*/
+/* deinit a TIMER */
+void timer_deinit(uint32_t timer_periph);
+/* initialize TIMER init parameter struct */
+void timer_struct_para_init(timer_parameter_struct* initpara);
+/* initialize TIMER counter */
+void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
+/* enable a TIMER */
+void timer_enable(uint32_t timer_periph);
+/* disable a TIMER */
+void timer_disable(uint32_t timer_periph);
+/* enable the auto reload shadow function */
+void timer_auto_reload_shadow_enable(uint32_t timer_periph);
+/* disable the auto reload shadow function */
+void timer_auto_reload_shadow_disable(uint32_t timer_periph);
+/* enable the update event */
+void timer_update_event_enable(uint32_t timer_periph);
+/* disable the update event */
+void timer_update_event_disable(uint32_t timer_periph);
+/* set TIMER counter alignment mode */
+void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
+/* set TIMER counter up direction */
+void timer_counter_up_direction(uint32_t timer_periph);
+/* set TIMER counter down direction */
+void timer_counter_down_direction(uint32_t timer_periph);
+/* configure TIMER prescaler */
+void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload);
+/* configure TIMER repetition register value */
+void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition);
+/* configure TIMER autoreload register value */
+void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload);
+/* configure TIMER counter register value */
+void timer_counter_value_config(uint32_t timer_periph , uint16_t counter);
+/* read TIMER counter value */
+uint32_t timer_counter_read(uint32_t timer_periph);
+/* read TIMER prescaler value */
+uint16_t timer_prescaler_read(uint32_t timer_periph);
+/* configure TIMER single pulse mode */
+void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
+/* configure TIMER update source */
+void timer_update_source_config(uint32_t timer_periph, uint32_t update);
+/* OCPRE clear source selection */
+void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear);
+
+/* TIMER interrupt and flag*/
+/* enable the TIMER interrupt */
+void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
+/* disable the TIMER interrupt */
+void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
+/* get timer interrupt flag */
+FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
+/* clear TIMER interrupt flag */
+void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
+/* get TIMER flags */
+FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
+/* clear TIMER flags */
+void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
+
+/* timer DMA and event*/
+/* enable the TIMER DMA */
+void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
+/* disable the TIMER DMA */
+void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
+/* channel DMA request source selection */
+void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request);
+/* configure the TIMER DMA transfer */
+void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth);
+/* software generate events */
+void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
+
+/* TIMER channel complementary protection */
+/* initialize TIMER break parameter struct */
+void timer_break_struct_para_init(timer_break_parameter_struct* breakpara);
+/* configure TIMER break function */
+void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
+/* enable TIMER break function */
+void timer_break_enable(uint32_t timer_periph);
+/* disable TIMER break function */
+void timer_break_disable(uint32_t timer_periph);
+/* enable TIMER output automatic function */
+void timer_automatic_output_enable(uint32_t timer_periph);
+/* disable TIMER output automatic function */
+void timer_automatic_output_disable(uint32_t timer_periph);
+/* enable or disable TIMER primary output function */
+void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
+/* enable or disable channel capture/compare control shadow register */
+void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
+/* configure TIMER channel control shadow register update control */
+void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl);
+
+/* TIMER channel output */
+/* initialize TIMER channel output parameter struct */
+void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara);
+/* configure TIMER channel output function */
+void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara);
+/* configure TIMER channel output compare mode */
+void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode);
+/* configure TIMER channel output pulse value */
+void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse);
+/* configure TIMER channel output shadow function */
+void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
+/* configure TIMER channel output fast function */
+void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
+/* configure TIMER channel output clear function */
+void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear);
+/* configure TIMER channel output polarity */
+void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
+/* configure TIMER channel complementary output polarity */
+void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
+/* configure TIMER channel enable state */
+void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
+/* configure TIMER channel complementary output enable state */
+void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
+
+/* TIMER channel input */
+/* initialize TIMER channel input parameter struct */
+void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara);
+/* configure TIMER input capture parameter */
+void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
+/* configure TIMER channel input capture prescaler value */
+void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
+/* read TIMER channel capture compare register value */
+uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
+/* configure TIMER input pwm capture function */
+void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
+/* configure TIMER hall sensor mode */
+void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode);
+
+/* TIMER master and slave */
+/* select TIMER input trigger source */
+void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
+/* select TIMER master mode output trigger source */
+void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
+/* select TIMER slave mode */
+void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode);
+/* configure TIMER master slave mode */
+void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave);
+/* configure TIMER external trigger input */
+void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
+/* configure TIMER quadrature decoder mode */
+void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
+/* configure TIMER internal clock mode */
+void timer_internal_clock_config(uint32_t timer_periph);
+/* configure TIMER the internal trigger as external clock input */
+void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
+/* configure TIMER the external trigger as external clock input */
+void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter);
+/* configure TIMER the external clock mode 0 */
+void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
+/* configure TIMER the external clock mode 1 */
+void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
+/* disable TIMER the external clock mode 1 */
+void timer_external_clock_mode1_disable(uint32_t timer_periph);
+/* configure TIMER channel remap function */
+void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap);
+
+/* TIMER configure */
+/* configure TIMER write CHxVAL register selection */
+void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel);
+/* configure TIMER output value selection */
+void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel);
+
+#endif /* GD32E230_TIMER_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_usart.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_usart.h
new file mode 100644
index 0000000000..6cb6f61056
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_usart.h
@@ -0,0 +1,614 @@
+/*!
+    \file  gd32e230_usart.h
+    \brief definitions for the USART
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_USART_H
+#define GD32E230_USART_H
+
+#include "gd32e230.h"
+
+/* USARTx(x=0,1) definitions */
+#define USART0                        (USART_BASE + 0x0000F400U)
+#define USART1                        USART_BASE
+
+/* registers definitions */
+#define USART_CTL0(usartx)            REG32((usartx) + 0x00000000U)        /*!< USART control register 0 */
+#define USART_CTL1(usartx)            REG32((usartx) + 0x00000004U)        /*!< USART control register 1 */
+#define USART_CTL2(usartx)            REG32((usartx) + 0x00000008U)        /*!< USART control register 2 */
+#define USART_BAUD(usartx)            REG32((usartx) + 0x0000000CU)        /*!< USART baud rate register */
+#define USART_GP(usartx)              REG32((usartx) + 0x00000010U)        /*!< USART guard time and prescaler register */
+#define USART_RT(usartx)              REG32((usartx) + 0x00000014U)        /*!< USART receiver timeout register */
+#define USART_CMD(usartx)             REG32((usartx) + 0x00000018U)        /*!< USART command register */
+#define USART_STAT(usartx)            REG32((usartx) + 0x0000001CU)        /*!< USART status register */
+#define USART_INTC(usartx)            REG32((usartx) + 0x00000020U)        /*!< USART status clear register */
+#define USART_RDATA(usartx)           REG32((usartx) + 0x00000024U)        /*!< USART receive data register */
+#define USART_TDATA(usartx)           REG32((usartx) + 0x00000028U)        /*!< USART transmit data register */
+#define USART_CHC(usartx)             REG32((usartx) + 0x000000C0U)        /*!< USART coherence control register */
+#define USART_RFCS(usartx)            REG32((usartx) + 0x000000D0U)        /*!< USART receive FIFO control and status register */
+
+/* bits definitions */
+/* USARTx_CTL0 */
+#define USART_CTL0_UEN                BIT(0)                         /*!< USART enable */
+#define USART_CTL0_UESM               BIT(1)                         /*!< USART enable in deep-sleep mode */
+#define USART_CTL0_REN                BIT(2)                         /*!< receiver enable */
+#define USART_CTL0_TEN                BIT(3)                         /*!< transmitter enable */
+#define USART_CTL0_IDLEIE             BIT(4)                         /*!< idle line detected interrupt enable */
+#define USART_CTL0_RBNEIE             BIT(5)                         /*!< read data buffer not empty interrupt and overrun error interrupt enable */
+#define USART_CTL0_TCIE               BIT(6)                         /*!< transmission complete interrupt enable */
+#define USART_CTL0_TBEIE              BIT(7)                         /*!< transmitter register empty interrupt enable */
+#define USART_CTL0_PERRIE             BIT(8)                         /*!< parity error interrupt enable */
+#define USART_CTL0_PM                 BIT(9)                         /*!< parity mode */
+#define USART_CTL0_PCEN               BIT(10)                        /*!< parity control enable */
+#define USART_CTL0_WM                 BIT(11)                        /*!< wakeup method in mute mode */
+#define USART_CTL0_WL                 BIT(12)                        /*!< word length */
+#define USART_CTL0_MEN                BIT(13)                        /*!< mute mode enable */
+#define USART_CTL0_AMIE               BIT(14)                        /*!< address match interrupt enable */
+#define USART_CTL0_OVSMOD             BIT(15)                        /*!< oversample mode */
+#define USART_CTL0_DED                BITS(16,20)                    /*!< driver enable deassertion time */
+#define USART_CTL0_DEA                BITS(21,25)                    /*!< driver enable assertion time */
+#define USART_CTL0_RTIE               BIT(26)                        /*!< receiver timeout interrupt enable */
+#define USART_CTL0_EBIE               BIT(27)                        /*!< end of block interrupt enable */
+
+/* USARTx_CTL1 */
+#define USART_CTL1_ADDM               BIT(4)                         /*!< address detection mode */
+#define USART_CTL1_LBLEN              BIT(5)                         /*!< LIN break frame length */
+#define USART_CTL1_LBDIE              BIT(6)                         /*!< LIN break detection interrupt enable */
+#define USART_CTL1_CLEN               BIT(8)                         /*!< last bit clock pulse */
+#define USART_CTL1_CPH                BIT(9)                         /*!< clock phase */
+#define USART_CTL1_CPL                BIT(10)                        /*!< clock polarity */
+#define USART_CTL1_CKEN               BIT(11)                        /*!< ck pin enable */
+#define USART_CTL1_STB                BITS(12,13)                    /*!< stop bits length */
+#define USART_CTL1_LMEN               BIT(14)                        /*!< LIN mode enable */
+#define USART_CTL1_STRP               BIT(15)                        /*!< swap TX/RX pins */
+#define USART_CTL1_RINV               BIT(16)                        /*!< RX pin level inversion */
+#define USART_CTL1_TINV               BIT(17)                        /*!< TX pin level inversion */
+#define USART_CTL1_DINV               BIT(18)                        /*!< data bit level inversion */
+#define USART_CTL1_MSBF               BIT(19)                        /*!< most significant bit first */
+#define USART_CTL1_ABDEN              BIT(20)                        /*!< auto baud rate enable */
+#define USART_CTL1_ABDM               BITS(21,22)                    /*!< auto baud rate mode */
+#define USART_CTL1_RTEN               BIT(23)                        /*!< receiver timeout enable */
+#define USART_CTL1_ADDR               BITS(24,31)                    /*!< address of the USART terminal */
+
+/* USARTx_CTL2 */
+#define USART_CTL2_ERRIE              BIT(0)                         /*!< error interrupt enable in multibuffer communication */
+#define USART_CTL2_IREN               BIT(1)                         /*!< IrDA mode enable */
+#define USART_CTL2_IRLP               BIT(2)                         /*!< IrDA low-power */
+#define USART_CTL2_HDEN               BIT(3)                         /*!< half-duplex enable */
+#define USART_CTL2_NKEN               BIT(4)                         /*!< NACK enable in smartcard mode */
+#define USART_CTL2_SCEN               BIT(5)                         /*!< smartcard mode enable */
+#define USART_CTL2_DENR               BIT(6)                         /*!< DMA enable for reception */
+#define USART_CTL2_DENT               BIT(7)                         /*!< DMA enable for transmission */
+#define USART_CTL2_RTSEN              BIT(8)                         /*!< RTS enable */
+#define USART_CTL2_CTSEN              BIT(9)                         /*!< CTS enable */
+#define USART_CTL2_CTSIE              BIT(10)                        /*!< CTS interrupt enable */
+#define USART_CTL2_OSB                BIT(11)                        /*!< one sample bit mode */
+#define USART_CTL2_OVRD               BIT(12)                        /*!< overrun disable */
+#define USART_CTL2_DDRE               BIT(13)                        /*!< disable DMA on reception error */
+#define USART_CTL2_DEM                BIT(14)                        /*!< driver enable mode */
+#define USART_CTL2_DEP                BIT(15)                        /*!< driver enable polarity mode */
+#define USART_CTL2_SCRTNUM            BITS(17,19)                    /*!< smartcard auto-retry number */
+#define USART_CTL2_WUM                BITS(20,21)                    /*!< wakeup mode from deep-sleep mode */
+#define USART_CTL2_WUIE               BIT(22)                        /*!< wakeup from deep-sleep mode interrupt enable */
+
+/* USARTx_BAUD */
+#define USART_BAUD_FRADIV             BITS(0,3)                      /*!< fraction of baud-rate divider */
+#define USART_BAUD_INTDIV             BITS(4,15)                     /*!< integer of baud-rate divider */
+
+/* USARTx_GP */
+#define USART_GP_PSC                  BITS(0,7)                      /*!< prescaler value for dividing the system clock */
+#define USART_GP_GUAT                 BITS(8,15)                     /*!< guard time value in smartcard mode */
+
+/* USARTx_RT */
+#define USART_RT_RT                   BITS(0,23)                     /*!< receiver timeout threshold */
+#define USART_RT_BL                   BITS(24,31)                    /*!< block length */
+
+/* USARTx_CMD */
+#define USART_CMD_ABDCMD              BIT(0)                         /*!< auto baudrate detection command */
+#define USART_CMD_SBKCMD              BIT(1)                         /*!< send break command */
+#define USART_CMD_MMCMD               BIT(2)                         /*!< mute mode command */
+#define USART_CMD_RXFCMD              BIT(3)                         /*!< receive data flush command */
+#define USART_CMD_TXFCMD              BIT(4)                         /*!< transmit data flush request */
+
+/* USARTx_STAT */
+#define USART_STAT_PERR               BIT(0)                         /*!< parity error flag */
+#define USART_STAT_FERR               BIT(1)                         /*!< frame error flag */
+#define USART_STAT_NERR               BIT(2)                         /*!< noise error flag */
+#define USART_STAT_ORERR              BIT(3)                         /*!< overrun error */
+#define USART_STAT_IDLEF              BIT(4)                         /*!< idle line detected flag */
+#define USART_STAT_RBNE               BIT(5)                         /*!< read data buffer not empty */
+#define USART_STAT_TC                 BIT(6)                         /*!< transmission completed */
+#define USART_STAT_TBE                BIT(7)                         /*!< transmit data register empty */
+#define USART_STAT_LBDF               BIT(8)                         /*!< LIN break detected flag */
+#define USART_STAT_CTSF               BIT(9)                         /*!< CTS change flag */
+#define USART_STAT_CTS                BIT(10)                        /*!< CTS level */
+#define USART_STAT_RTF                BIT(11)                        /*!< receiver timeout flag */
+#define USART_STAT_EBF                BIT(12)                        /*!< end of block flag */
+#define USART_STAT_ABDE               BIT(14)                        /*!< auto baudrate detection error */
+#define USART_STAT_ABDF               BIT(15)                        /*!< auto baudrate detection flag */
+#define USART_STAT_BSY                BIT(16)                        /*!< busy flag */
+#define USART_STAT_AMF                BIT(17)                        /*!< address match flag */
+#define USART_STAT_SBF                BIT(18)                        /*!< send break flag */
+#define USART_STAT_RWU                BIT(19)                        /*!< receiver wakeup from mute mode */
+#define USART_STAT_WUF                BIT(20)                        /*!< wakeup from deep-sleep mode flag */
+#define USART_STAT_TEA                BIT(21)                        /*!< transmit enable acknowledge flag */
+#define USART_STAT_REA                BIT(22)                        /*!< receive enable acknowledge flag */
+
+/* USARTx_INTC */
+#define USART_INTC_PEC                BIT(0)                         /*!< parity error clear */
+#define USART_INTC_FEC                BIT(1)                         /*!< frame error flag clear */
+#define USART_INTC_NEC                BIT(2)                         /*!< noise detected clear */
+#define USART_INTC_OREC               BIT(3)                         /*!< overrun error clear */
+#define USART_INTC_IDLEC              BIT(4)                         /*!< idle line detected clear */
+#define USART_INTC_TCC                BIT(6)                         /*!< transmission complete clear */
+#define USART_INTC_LBDC               BIT(8)                         /*!< LIN break detected clear */
+#define USART_INTC_CTSC               BIT(9)                         /*!< CTS change clear */
+#define USART_INTC_RTC                BIT(11)                        /*!< receiver timeout clear */
+#define USART_INTC_EBC                BIT(12)                        /*!< end of timeout clear */
+#define USART_INTC_AMC                BIT(17)                        /*!< address match clear */
+#define USART_INTC_WUC                BIT(20)                        /*!< wakeup from deep-sleep mode clear */
+
+/* USARTx_RDATA */
+#define USART_RDATA_RDATA             BITS(0,8)                      /*!< receive data value */
+
+/* USARTx_TDATA */
+#define USART_TDATA_TDATA             BITS(0,8)                      /*!< transmit data value */
+
+/* USARTx_CHC */
+#define USART_CHC_HCM                 BIT(0)                         /*!< hardware flow control coherence mode */
+#define USART_CHC_EPERR               BIT(8)                         /*!< early parity error flag */
+
+/* USARTx_RFCS */
+#define USART_RFCS_ELNACK             BIT(0)                         /*!< early NACK */
+#define USART_RFCS_RFEN               BIT(8)                         /*!< receive FIFO enable */
+#define USART_RFCS_RFFIE              BIT(9)                         /*!< receive FIFO full interrupt enable */
+#define USART_RFCS_RFE                BIT(10)                        /*!< receive FIFO empty flag */
+#define USART_RFCS_RFF                BIT(11)                        /*!< receive FIFO full flag */
+#define USART_RFCS_RFCNT              BITS(12,14)                    /*!< receive FIFO counter number */
+#define USART_RFCS_RFFINT             BIT(15)                        /*!< receive FIFO full interrupt flag */
+
+/* constants definitions */
+
+/* define the USART bit position and its register index offset */
+#define USART_REGIDX_BIT(regidx, bitpos)    (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define USART_REG_VAL(usartx, offset)       (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
+#define USART_BIT_POS(val)                  ((uint32_t)(val) & 0x0000001FU)
+#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)   (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
+                                                              | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
+#define USART_REG_VAL2(usartx, offset)       (REG32((usartx) + ((uint32_t)(offset) >> 22)))
+#define USART_BIT_POS2(val)                  (((uint32_t)(val) & 0x001F0000U) >> 16)
+
+/* register offset */
+#define USART_CTL0_REG_OFFSET              0x00000000U                           /*!< CTL0 register offset */
+#define USART_CTL1_REG_OFFSET              0x00000004U                           /*!< CTL1 register offset */
+#define USART_CTL2_REG_OFFSET              0x00000008U                           /*!< CTL2 register offset */
+#define USART_STAT_REG_OFFSET              0x0000001CU                           /*!< STAT register offset */
+#define USART_CHC_REG_OFFSET               0x000000C0U                           /*!< CHC register offset */
+#define USART_RFCS_REG_OFFSET              0x000000D0U                           /*!< RFCS register offset */
+
+/* USART flags */
+typedef enum{
+    /* flags in STAT register */
+    USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U),         /*!< receive enable acknowledge flag */
+    USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U),         /*!< transmit enable acknowledge flag */
+    USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U),          /*!< wakeup from Deep-sleep mode flag */
+    USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U),         /*!< receiver wakeup from mute mode */
+    USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U),          /*!< send break flag */
+    USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U),          /*!< ADDR match flag */
+    USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U),         /*!< busy flag */
+    USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U),         /*!< auto baudrate detection flag */
+    USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U),        /*!< auto baudrate detection error */
+    USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U),          /*!< end of block flag */
+    USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U),          /*!< receiver timeout flag */
+    USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U),         /*!< CTS level */
+    USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U),         /*!< CTS change flag */
+    USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U),          /*!< LIN break detected flag */
+    USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U),          /*!< transmit data buffer empty */
+    USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U),           /*!< transmission complete */
+    USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U),         /*!< read data buffer not empty */
+    USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U),         /*!< IDLE line detected flag */
+    USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U),        /*!< overrun error */
+    USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),         /*!< noise error flag */
+    USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U),         /*!< frame error flag */
+    USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U),         /*!< parity error flag */
+    /* flags in CHC register */
+    USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U),         /*!< early parity error flag */
+    /* flags in RFCS register */
+    USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U),      /*!< receive FIFO full interrupt flag */
+    USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U),         /*!< receive FIFO full flag */
+    USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U),         /*!< receive FIFO empty flag */
+}usart_flag_enum;
+
+/* USART interrupt flags */
+typedef enum
+{
+    /* interrupt flags in CTL0 register */
+    USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U),       /*!< end of block interrupt and flag */
+    USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U),       /*!< receiver timeout interrupt and flag */
+    USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U),       /*!< address match interrupt and flag */
+    USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),       /*!< parity error interrupt and flag */
+    USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U),        /*!< transmitter buffer empty interrupt and flag */
+    USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U),         /*!< transmission complete interrupt and flag */
+    USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),       /*!< read data buffer not empty interrupt and flag */
+    USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
+    USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U),       /*!< IDLE line detected interrupt and flag */
+    /* interrupt flags in CTL1 register */
+    USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U),        /*!< LIN break detected interrupt and flag */
+    /* interrupt flags in CTL2 register */
+    USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U),       /*!< wakeup from deep-sleep mode interrupt and flag */
+    USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),       /*!< CTS interrupt and flag */
+    USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U),   /*!< error interrupt and noise error flag */
+    USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U),  /*!< error interrupt and overrun error */
+    USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U),   /*!< error interrupt and frame error flag */
+    /* interrupt flags in RFCS register */
+    USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U),       /*!< receive FIFO full interrupt and flag */
+}usart_interrupt_flag_enum;
+
+/* USART interrupt enable or disable */
+typedef enum
+{
+    /* interrupt in CTL0 register */
+    USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U),         /*!< end of block interrupt */
+    USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U),         /*!< receiver timeout interrupt */
+    USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U),         /*!< address match interrupt */
+    USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),        /*!< parity error interrupt */
+    USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),         /*!< transmitter buffer empty interrupt */
+    USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),          /*!< transmission complete interrupt */
+    USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),        /*!< read data buffer not empty interrupt and overrun error interrupt */
+    USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),        /*!< IDLE line detected interrupt */
+    /* interrupt in CTL1 register */
+    USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),         /*!< LIN break detected interrupt */
+    /* interrupt in CTL2 register */
+    USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U),         /*!< wakeup from deep-sleep mode interrupt */
+    USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),        /*!< CTS interrupt */
+    USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),         /*!< error interrupt */
+    /* interrupt in RFCS register */
+    USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U),         /*!< receive FIFO full interrupt */
+}usart_interrupt_enum;
+
+/* USART invert configure */
+typedef enum {
+    /* data bit level inversion */
+    USART_DINV_ENABLE,                                               /*!< data bit level inversion */
+    USART_DINV_DISABLE,                                              /*!< data bit level not inversion */
+    /* TX pin level inversion */
+    USART_TXPIN_ENABLE,                                              /*!< TX pin level inversion */               
+    USART_TXPIN_DISABLE,                                             /*!< TX pin level not inversion */
+    /* RX pin level inversion */
+    USART_RXPIN_ENABLE,                                              /*!< RX pin level inversion */
+    USART_RXPIN_DISABLE,                                             /*!< RX pin level not inversion */
+    /* swap TX/RX pins */
+    USART_SWAP_ENABLE,                                               /*!< swap TX/RX pins */                
+    USART_SWAP_DISABLE,                                              /*!< not swap TX/RX pins */
+}usart_invert_enum;
+
+/* USART receiver configure */
+#define CTL0_REN(regval)              (BIT(2) & ((uint32_t)(regval) << 2))
+#define USART_RECEIVE_ENABLE          CTL0_REN(1)                    /*!< enable receiver */
+#define USART_RECEIVE_DISABLE         CTL0_REN(0)                    /*!< disable receiver */
+
+/* USART transmitter configure */
+#define CTL0_TEN(regval)              (BIT(3) & ((uint32_t)(regval) << 3))
+#define USART_TRANSMIT_ENABLE         CTL0_TEN(1)                    /*!< enable transmitter */
+#define USART_TRANSMIT_DISABLE        CTL0_TEN(0)                    /*!< disable transmitter */
+
+/* USART parity bits definitions */
+#define CTL0_PM(regval)               (BITS(9,10) & ((uint32_t)(regval) << 9))
+#define USART_PM_NONE                 CTL0_PM(0)                     /*!< no parity */
+#define USART_PM_EVEN                 CTL0_PM(2)                     /*!< even parity */
+#define USART_PM_ODD                  CTL0_PM(3)                     /*!< odd parity */
+
+/* USART wakeup method in mute mode */
+#define CTL0_WM(regval)               (BIT(11) & ((uint32_t)(regval) << 11))
+#define USART_WM_IDLE                 CTL0_WM(0)                     /*!< idle line */
+#define USART_WM_ADDR                 CTL0_WM(1)                     /*!< address match */
+
+/* USART word length definitions */
+#define CTL0_WL(regval)               (BIT(12) & ((uint32_t)(regval) << 12))
+#define USART_WL_8BIT                 CTL0_WL(0)                     /*!< 8 bits */
+#define USART_WL_9BIT                 CTL0_WL(1)                     /*!< 9 bits */
+
+/* USART oversample mode */
+#define CTL0_OVSMOD(regval)           (BIT(15) & ((uint32_t)(regval) << 15))
+#define USART_OVSMOD_8                CTL0_OVSMOD(1)                 /*!< oversampling by 8 */
+#define USART_OVSMOD_16               CTL0_OVSMOD(0)                 /*!< oversampling by 16 */
+
+/* USART address detection mode */
+#define CTL1_ADDM(regval)             (BIT(4) & ((uint32_t)(regval) << 4))
+#define USART_ADDM_4BIT               CTL1_ADDM(0)                   /*!< 4-bit address detection */
+#define USART_ADDM_FULLBIT            CTL1_ADDM(1)                   /*!< full-bit address detection */
+
+/* USART LIN break frame length */
+#define CTL1_LBLEN(regval)            (BIT(5) & ((uint32_t)(regval) << 5))
+#define USART_LBLEN_10B               CTL1_LBLEN(0)                  /*!< 10 bits break detection */
+#define USART_LBLEN_11B               CTL1_LBLEN(1)                  /*!< 11 bits break detection */
+
+/* USART last bit clock pulse */
+#define CTL1_CLEN(regval)             (BIT(8) & ((uint32_t)(regval) << 8))
+#define USART_CLEN_NONE               CTL1_CLEN(0)                   /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */
+#define USART_CLEN_EN                 CTL1_CLEN(1)                   /*!< clock pulse of the last data bit (MSB) is output to the CK pin */
+
+/* USART clock phase */
+#define CTL1_CPH(regval)              (BIT(9) & ((uint32_t)(regval) << 9))
+#define USART_CPH_1CK                 CTL1_CPH(0)                    /*!< first clock transition is the first data capture edge */
+#define USART_CPH_2CK                 CTL1_CPH(1)                    /*!< second clock transition is the first data capture edge */
+
+/* USART clock polarity */
+#define CTL1_CPL(regval)              (BIT(10) & ((uint32_t)(regval) << 10))
+#define USART_CPL_LOW                 CTL1_CPL(0)                    /*!< steady low value on CK pin */
+#define USART_CPL_HIGH                CTL1_CPL(1)                    /*!< steady high value on CK pin */
+
+/* USART stop bits definitions */
+#define CTL1_STB(regval)              (BITS(12,13) & ((uint32_t)(regval) << 12))
+#define USART_STB_1BIT                CTL1_STB(0)                    /*!< 1 bit */
+#define USART_STB_0_5BIT              CTL1_STB(1)                    /*!< 0.5 bit */
+#define USART_STB_2BIT                CTL1_STB(2)                    /*!< 2 bits */
+#define USART_STB_1_5BIT              CTL1_STB(3)                    /*!< 1.5 bits */
+
+/* USART data is transmitted/received with the LSB/MSB first */
+#define CTL1_MSBF(regval)             (BIT(19) & ((uint32_t)(regval) << 19))
+#define USART_MSBF_LSB                CTL1_MSBF(0)                   /*!< LSB first */
+#define USART_MSBF_MSB                CTL1_MSBF(1)                   /*!< MSB first */
+
+/* USART auto baud rate detection mode bits definitions */
+#define CTL1_ABDM(regval)             (BITS(21,22) & ((uint32_t)(regval) << 21))
+#define USART_ABDM_FTOR               CTL1_ABDM(0)                   /*!< falling edge to rising edge measurement */
+#define USART_ABDM_FTOF               CTL1_ABDM(1)                   /*!< falling edge to falling edge measurement */
+
+/* USART IrDA low-power enable */
+#define CTL2_IRLP(regval)             (BIT(2) & ((uint32_t)(regval) << 2))
+#define USART_IRLP_LOW                CTL2_IRLP(1)                   /*!< low-power */
+#define USART_IRLP_NORMAL             CTL2_IRLP(0)                   /*!< normal */
+
+/* DMA enable for reception */
+#define CTL2_DENR(regval)             (BIT(6) & ((uint32_t)(regval) << 6))
+#define USART_DENR_ENABLE             CTL2_DENR(1)                   /*!< enable for reception */
+#define USART_DENR_DISABLE            CTL2_DENR(0)                   /*!< disable for reception */
+
+/* DMA enable for transmission */
+#define CTL2_DENT(regval)             (BIT(7) & ((uint32_t)(regval) << 7))
+#define USART_DENT_ENABLE             CTL2_DENT(1)                   /*!< enable for transmission */
+#define USART_DENT_DISABLE            CTL2_DENT(0)                   /*!< disable for transmission */
+
+/* USART RTS hardware flow control configure */
+#define CTL2_RTSEN(regval)            (BIT(8) & ((uint32_t)(regval) << 8))
+#define USART_RTS_ENABLE              CTL2_RTSEN(1)                  /*!< RTS hardware flow control enabled */
+#define USART_RTS_DISABLE             CTL2_RTSEN(0)                  /*!< RTS hardware flow control disabled */
+
+/* USART CTS hardware flow control configure */
+#define CTL2_CTSEN(regval)            (BIT(9) & ((uint32_t)(regval) << 9))
+#define USART_CTS_ENABLE              CTL2_CTSEN(1)                  /*!< CTS hardware flow control enabled */
+#define USART_CTS_DISABLE             CTL2_CTSEN(0)                  /*!< CTS hardware flow control disabled */
+
+/* USART one sample bit method configure */
+#define CTL2_OSB(regval)              (BIT(11) & ((uint32_t)(regval) << 11))
+#define USART_OSB_1BIT                CTL2_OSB(1)                    /*!< 1 sample bit */
+#define USART_OSB_3BIT                CTL2_OSB(0)                    /*!< 3 sample bits */
+
+/* USART driver enable polarity mode */
+#define CTL2_DEP(regval)              (BIT(15) & ((uint32_t)(regval) << 15))
+#define USART_DEP_HIGH                CTL2_DEP(0)                    /*!< DE signal is active high */
+#define USART_DEP_LOW                 CTL2_DEP(1)                    /*!< DE signal is active low */
+
+/* USART wakeup mode from deep-sleep mode */
+#define CTL2_WUM(regval)              (BITS(20,21) & ((uint32_t)(regval) << 20))
+#define USART_WUM_ADDR                CTL2_WUM(0)                    /*!< WUF active on address match */
+#define USART_WUM_STARTB              CTL2_WUM(2)                    /*!< WUF active on start bit */
+#define USART_WUM_RBNE                CTL2_WUM(3)                    /*!< WUF active on RBNE */
+
+/* USART hardware flow control coherence mode */
+#define CHC_HCM(regval)               (BIT(0) & ((uint32_t)(regval) << 0))
+#define USART_HCM_NONE                CHC_HCM(0)                    /*!< nRTS signal equals to the rxne status register */
+#define USART_HCM_EN                  CHC_HCM(1)                    /*!< nRTS signal is set when the last data bit has been sampled */
+
+/* function declarations */
+/* initialization functions */
+/* reset USART */
+void usart_deinit(uint32_t usart_periph);
+/* configure USART baud rate value */
+void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
+/* configure USART parity function */
+void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
+/* configure USART word length */
+void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
+/* configure USART stop bit length */
+void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
+/* enable USART */
+void usart_enable(uint32_t usart_periph);
+/* disable USART */
+void usart_disable(uint32_t usart_periph);
+/* configure USART transmitter */
+void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
+/* configure USART receiver */
+void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
+
+/* USART normal mode communication */
+/* data is transmitted/received with the LSB/MSB first */
+void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
+/* configure USART inverted */
+void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
+/* enable the USART overrun function */
+void usart_overrun_enable(uint32_t usart_periph);
+/* disable the USART overrun function */
+void usart_overrun_disable(uint32_t usart_periph);
+/* configure the USART oversample mode */
+void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
+/* configure sample bit method */
+void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb);
+/* enable receiver timeout */
+void usart_receiver_timeout_enable(uint32_t usart_periph);
+/* disable receiver timeout */
+void usart_receiver_timeout_disable(uint32_t usart_periph);
+/* configure receiver timeout threshold */
+void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
+/* USART transmit data function */
+void usart_data_transmit(uint32_t usart_periph, uint32_t data);
+/* USART receive data function */
+uint16_t usart_data_receive(uint32_t usart_periph);
+
+/* auto baud rate detection */
+/* enable auto baud rate detection */
+void usart_autobaud_detection_enable(uint32_t usart_periph);
+/* disable auto baud rate detection */
+void usart_autobaud_detection_disable(uint32_t usart_periph);
+/* configure auto baud rate detection mode */
+void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod);
+
+/* multi-processor communication */
+/* configure address of the USART */
+void usart_address_config(uint32_t usart_periph, uint8_t addr);
+/* configure address detection mode */
+void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
+/* enable mute mode */
+void usart_mute_mode_enable(uint32_t usart_periph);
+/* disable mute mode */
+void usart_mute_mode_disable(uint32_t usart_periph);
+/* configure wakeup method in mute mode */
+void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
+
+/* LIN mode communication */
+/* enable LIN mode */
+void usart_lin_mode_enable(uint32_t usart_periph);
+/* disable LIN mode */
+void usart_lin_mode_disable(uint32_t usart_periph);
+/* LIN break detection length */
+void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
+
+/* half-duplex communication */
+/* enable half-duplex mode */
+void usart_halfduplex_enable(uint32_t usart_periph);
+/* disable half-duplex mode */
+void usart_halfduplex_disable(uint32_t usart_periph);
+
+/* synchronous communication */
+/* enable clock */
+void usart_clock_enable(uint32_t usart_periph);
+/* disable clock */
+void usart_clock_disable(uint32_t usart_periph);
+/* configure USART synchronous mode parameters */
+void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
+
+/* smartcard communication */
+/* configure guard time value in smartcard mode */
+void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
+/* enable smartcard mode */
+void usart_smartcard_mode_enable(uint32_t usart_periph);
+/* disable smartcard mode */
+void usart_smartcard_mode_disable(uint32_t usart_periph);
+/* enable NACK in smartcard mode */
+void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
+/* disable NACK in smartcard mode */
+void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
+/* enable early NACK in smartcard mode */
+void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph);
+/* disable early NACK in smartcard mode */
+void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph);
+/* configure smartcard auto-retry number */
+void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
+/* configure block length */
+void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
+
+/* IrDA communication */
+/* enable IrDA mode */
+void usart_irda_mode_enable(uint32_t usart_periph);
+/* disable IrDA mode */
+void usart_irda_mode_disable(uint32_t usart_periph);
+/* configure the peripheral clock prescaler */
+void usart_prescaler_config(uint32_t usart_periph, uint32_t psc);
+/* configure IrDA low-power */
+void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
+
+/* hardware flow communication */
+/* configure hardware flow control RTS */
+void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
+/* configure hardware flow control CTS */
+void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
+
+/* coherence control */
+/* configure hardware flow control coherence mode */
+void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm);
+
+/* enable RS485 driver */
+void usart_rs485_driver_enable(uint32_t usart_periph);
+/* disable RS485 driver */
+void usart_rs485_driver_disable(uint32_t usart_periph);
+/* configure driver enable assertion time */
+void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime);
+/* configure driver enable de-assertion time */
+void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime);
+/* configure driver enable polarity mode */
+void usart_depolarity_config(uint32_t usart_periph, uint32_t dep);
+
+/* USART DMA */
+/* configure USART DMA for reception */
+void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
+/* configure USART DMA for transmission */
+void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
+/* disable DMA on reception error */
+void usart_reception_error_dma_disable(uint32_t usart_periph);
+/* enable DMA on reception error */
+void usart_reception_error_dma_enable(uint32_t usart_periph);
+
+/* enable USART to wakeup the mcu from deep-sleep mode */
+void usart_wakeup_enable(uint32_t usart_periph);
+/* disable USART to wakeup the mcu from deep-sleep mode */
+void usart_wakeup_disable(uint32_t usart_periph);
+/* configure the USART wakeup mode from deep-sleep mode */
+void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum);
+
+/* USART receive FIFO */
+/* enable receive FIFO */
+void usart_receive_fifo_enable(uint32_t usart_periph);
+/* disable receive FIFO */
+void usart_receive_fifo_disable(uint32_t usart_periph);
+/* read receive FIFO counter number */
+uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph);
+
+/* flag & interrupt functions */
+/* get flag in STAT/RFCS register */
+FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
+/* clear USART status */
+void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
+/* enable USART interrupt */
+void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum inttype);
+/* disable USART interrupt */
+void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum inttype);
+/* enable USART command */
+void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype);
+/* get USART interrupt and flag status */
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
+/* clear USART interrupt flag */
+void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag);
+
+#endif /* GD32E230_USART_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_wwdgt.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_wwdgt.h
new file mode 100644
index 0000000000..38445b36de
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_wwdgt.h
@@ -0,0 +1,88 @@
+/*!
+    \file  gd32e230_wwdgt.h
+    \brief definitions for the WWDGT 
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_WWDGT_H
+#define GD32E230_WWDGT_H
+
+#include "gd32e230.h"
+
+/* WWDGT definitions */
+#define WWDGT                       WWDGT_BASE
+
+/* registers definitions */
+#define WWDGT_CTL                   REG32((WWDGT) + 0x00000000U)                     /*!< WWDGT control register */
+#define WWDGT_CFG                   REG32((WWDGT) + 0x00000004U)                     /*!< WWDGT configuration register */
+#define WWDGT_STAT                  REG32((WWDGT) + 0x00000008U)                     /*!< WWDGT status register */
+
+/* bits definitions */
+/* WWDGT_CTL */
+#define WWDGT_CTL_CNT               BITS(0,6)                                  /*!< WWDGT counter value */
+#define WWDGT_CTL_WDGTEN            BIT(7)                                     /*!< WWDGT counter enable */
+
+/* WWDGT_CFG */
+#define WWDGT_CFG_WIN               BITS(0,6)                                  /*!< WWDGT counter window value */
+#define WWDGT_CFG_PSC               BITS(7,8)                                  /*!< WWDGT prescaler divider value */
+#define WWDGT_CFG_EWIE              BIT(9)                                     /*!< WWDGT early wakeup interrupt enable */
+
+/* WWDGT_STAT */
+#define WWDGT_STAT_EWIF             BIT(0)                                     /*!< WWDGT early wakeup interrupt flag */
+
+/* constants definitions */
+#define CFG_PSC(regval)             (BITS(7,8) & ((uint32_t)(regval) << 7U))    /*!< write value to WWDGT_CFG_PSC bit field */
+#define WWDGT_CFG_PSC_DIV1          ((uint32_t)CFG_PSC(0))                     /*!< the time base of WWDGT = (PCLK1/4096)/1 */
+#define WWDGT_CFG_PSC_DIV2          ((uint32_t)CFG_PSC(1))                     /*!< the time base of WWDGT = (PCLK1/4096)/2 */
+#define WWDGT_CFG_PSC_DIV4          ((uint32_t)CFG_PSC(2))                     /*!< the time base of WWDGT = (PCLK1/4096)/4 */
+#define WWDGT_CFG_PSC_DIV8          ((uint32_t)CFG_PSC(3))                     /*!< the time base of WWDGT = (PCLK1/4096)/8 */
+
+/* function declarations */
+/* reset the window watchdog timer configuration */
+void wwdgt_deinit(void);
+/* start the window watchdog timer counter */
+void wwdgt_enable(void);
+
+/* configure the window watchdog timer counter value */
+void wwdgt_counter_update(uint16_t counter_value);
+/* configure counter value, window value, and prescaler divider value */
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
+
+/* enable early wakeup interrupt of WWDGT */
+void wwdgt_interrupt_enable(void);
+/* check early wakeup interrupt state of WWDGT */
+FlagStatus wwdgt_flag_get(void);
+/* clear early wakeup interrupt state of WWDGT */
+void wwdgt_flag_clear(void);
+
+#endif /* GD32E230_WWDGT_H */
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_adc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_adc.c
new file mode 100644
index 0000000000..d0f7065336
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_adc.c
@@ -0,0 +1,844 @@
+/*!
+    \file    gd32e230_adc.c
+    \brief   ADC driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_adc.h"
+
+/*!
+    \brief      reset ADC
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_deinit(void)
+{
+    rcu_periph_reset_enable(RCU_ADCRST);
+    rcu_periph_reset_disable(RCU_ADCRST);
+}
+
+/*!
+    \brief      enable ADC interface
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_enable(void)
+{
+    if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){
+        ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON;
+    }
+}
+
+/*!
+    \brief      disable ADC interface
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_disable(void)
+{
+    ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON);
+}
+
+/*!
+    \brief      ADC calibration and reset calibration
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_calibration_enable(void)
+{
+    /* reset the selected ADC calibration register */
+    ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB;
+    /* check the RSTCLB bit state */
+    while((ADC_CTL1 & ADC_CTL1_RSTCLB)){
+    }
+
+    /* enable ADC calibration process */
+    ADC_CTL1 |= ADC_CTL1_CLB;
+    /* check the CLB bit state */
+    while((ADC_CTL1 & ADC_CTL1_CLB)){
+    }
+}
+
+/*!
+    \brief      enable DMA request 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_dma_mode_enable(void)
+{
+    ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA);
+}
+
+/*!
+    \brief      disable DMA request 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_dma_mode_disable(void)
+{
+    ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA);
+}
+
+/*!
+    \brief      enable the temperature sensor and Vrefint channel
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_tempsensor_vrefint_enable(void)
+{
+    /* enable the temperature sensor and Vrefint channel */
+    ADC_CTL1 |= ADC_CTL1_TSVREN;
+}
+
+/*!
+    \brief      disable the temperature sensor and Vrefint channel
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_tempsensor_vrefint_disable(void)
+{
+    /* disable the temperature sensor and Vrefint channel */
+    ADC_CTL1 &= ~ADC_CTL1_TSVREN;
+}
+
+/*!
+    \brief      configure ADC discontinuous mode 
+    \param[in]  channel_group: select the channel group
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+      \arg        ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel
+    \param[in]  length: number of conversions in discontinuous mode, the number can be 1..8
+                        for regular channel, the number has no effect for inserted channel
+    \param[out] none
+    \retval     none
+*/
+void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length)
+{
+    ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
+    
+    switch(channel_group){
+    case ADC_REGULAR_CHANNEL:
+        /* configure the number of conversions in discontinuous mode */
+        ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM);
+        ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U));
+        ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC;
+        break;
+    case ADC_INSERTED_CHANNEL:
+        ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC;
+        break;
+    case ADC_CHANNEL_DISCON_DISABLE:
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure ADC special function
+    \param[in]  function: the function to configure
+                one or more parameters can be selected which is shown as below:
+      \arg        ADC_SCAN_MODE: scan mode select
+      \arg        ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
+      \arg        ADC_CONTINUOUS_MODE: continuous mode select
+    \param[in]  newvalue: ENABLE or DISABLE
+    \param[out] none
+    \retval     none
+*/
+void adc_special_function_config(uint32_t function, ControlStatus newvalue)
+{
+    if(newvalue){
+        /* enable ADC scan mode */
+        if(RESET != (function & ADC_SCAN_MODE)){
+            ADC_CTL0 |= ADC_SCAN_MODE;
+        }
+        /* enable ADC inserted channel group convert automatically */
+        if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
+            ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO;
+        }
+        /* enable ADC continuous mode */
+        if(RESET != (function & ADC_CONTINUOUS_MODE)){
+            ADC_CTL1 |= ADC_CONTINUOUS_MODE;
+        }
+    }else{
+        /* disable ADC scan mode */
+        if(RESET != (function & ADC_SCAN_MODE)){
+            ADC_CTL0 &= ~ADC_SCAN_MODE;
+        }
+        /* disable ADC inserted channel group convert automatically */
+        if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
+            ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO;
+        }
+        /* disable ADC continuous mode */
+        if(RESET != (function & ADC_CONTINUOUS_MODE)){
+            ADC_CTL1 &= ~ADC_CONTINUOUS_MODE;
+        }
+    }
+}
+
+/*!
+    \brief      configure ADC data alignment 
+    \param[in]  data_alignment: data alignment select
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_DATAALIGN_RIGHT: right alignment
+      \arg        ADC_DATAALIGN_LEFT: left alignment
+    \param[out] none
+    \retval     none
+*/
+void adc_data_alignment_config(uint32_t data_alignment)
+{
+    if(ADC_DATAALIGN_RIGHT != data_alignment){
+        ADC_CTL1 |= ADC_CTL1_DAL;
+    }else{
+        ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL);
+    }
+}
+
+/*!
+    \brief      configure the length of regular channel group or inserted channel group
+    \param[in]  channel_group: select the channel group
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+    \param[in]  length: the length of the channel
+                        regular channel 1-16
+                        inserted channel 1-4
+    \param[out] none
+    \retval     none
+*/
+void adc_channel_length_config(uint8_t channel_group, uint32_t length)
+{
+    switch(channel_group){
+    case ADC_REGULAR_CHANNEL:
+        /* configure the length of regular channel group */
+        ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL);
+        ADC_RSQ0 |= RSQ0_RL((uint32_t)(length-1U));
+        break;
+    case ADC_INSERTED_CHANNEL:
+        /* configure the length of inserted channel group */
+        ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL);
+        ADC_ISQ |= ISQ_IL((uint32_t)(length-1U));
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure ADC regular channel
+    \param[in]  rank: the regular group sequence rank, this parameter must be between 0 to 15
+    \param[in]  channel: the selected ADC channel
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx
+    \param[in]  sample_time: the sample time value
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_SAMPLETIME_1POINT5: 1.5 cycles
+      \arg        ADC_SAMPLETIME_7POINT5: 7.5 cycles
+      \arg        ADC_SAMPLETIME_13POINT5: 13.5 cycles
+      \arg        ADC_SAMPLETIME_28POINT5: 28.5 cycles
+      \arg        ADC_SAMPLETIME_41POINT5: 41.5 cycles
+      \arg        ADC_SAMPLETIME_55POINT5: 55.5 cycles
+      \arg        ADC_SAMPLETIME_71POINT5: 71.5 cycles
+      \arg        ADC_SAMPLETIME_239POINT5: 239.5 cycles
+    \param[out] none
+    \retval     none
+*/
+void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
+{
+    uint32_t rsq,sampt;
+    
+    /* configure ADC regular sequence */
+    if(rank < 6U){
+        rsq = ADC_RSQ2;
+        rsq &=  ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
+        rsq |= ((uint32_t)channel << (5U*rank));
+        ADC_RSQ2 = rsq;
+    }else if(rank < 12U){
+        rsq = ADC_RSQ1;
+        rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
+        rsq |= ((uint32_t)channel << (5U*(rank-6U)));
+        ADC_RSQ1 = rsq;
+    }else if(rank < 16U){
+        rsq = ADC_RSQ0;
+        rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
+        rsq |= ((uint32_t)channel << (5U*(rank-12U)));
+        ADC_RSQ0 = rsq;
+    }else{
+    }
+    
+    /* configure ADC sampling time */
+    if(channel < 10U){
+        sampt = ADC_SAMPT1;
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
+        sampt |= (uint32_t)(sample_time << (3U*channel));
+        ADC_SAMPT1 = sampt;
+    }else if(channel < 19U){
+        sampt = ADC_SAMPT0;
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
+        sampt |= (uint32_t)(sample_time << (3U*(channel-10U)));
+        ADC_SAMPT0 = sampt;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      configure ADC inserted channel 
+    \param[in]  rank: the inserted group sequencer rank,this parameter must be between 0 to 3
+    \param[in]  channel: the selected ADC channel
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx
+    \param[in]  sample_time: The sample time value
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_SAMPLETIME_1POINT5: 1.5 cycles
+      \arg        ADC_SAMPLETIME_7POINT5: 7.5 cycles
+      \arg        ADC_SAMPLETIME_13POINT5: 13.5 cycles
+      \arg        ADC_SAMPLETIME_28POINT5: 28.5 cycles
+      \arg        ADC_SAMPLETIME_41POINT5: 41.5 cycles
+      \arg        ADC_SAMPLETIME_55POINT5: 55.5 cycles
+      \arg        ADC_SAMPLETIME_71POINT5: 71.5 cycles
+      \arg        ADC_SAMPLETIME_239POINT5: 239.5 cycles
+    \param[out] none
+    \retval     none
+*/
+void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
+{
+    uint8_t inserted_length;
+    uint32_t isq,sampt;
+
+    inserted_length = (uint8_t)GET_BITS(ADC_ISQ , 20U , 21U);
+  
+    isq = ADC_ISQ;
+    isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U)));
+    isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U));
+    ADC_ISQ = isq;
+
+    /* configure ADC sampling time */
+    if(channel < 10U){
+        sampt = ADC_SAMPT1;
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
+        sampt |= (uint32_t) sample_time << (3U*channel);
+        ADC_SAMPT1 = sampt;
+    }else if(channel < 19U){
+        sampt = ADC_SAMPT0;
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel - 10U))));
+        sampt |= ((uint32_t)sample_time << (3U*(channel - 10U)));
+        ADC_SAMPT0 = sampt;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      configure ADC inserted channel offset
+    \param[in]  inserted_channel: insert channel select
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_INSERTED_CHANNEL_0: ADC inserted channel 0
+      \arg        ADC_INSERTED_CHANNEL_1: ADC inserted channel 1
+      \arg        ADC_INSERTED_CHANNEL_2: ADC inserted channel 2
+      \arg        ADC_INSERTED_CHANNEL_3: ADC inserted channel 3
+    \param[in]  offset: the offset data
+    \param[out] none
+    \retval     none
+*/
+void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset)
+{
+    uint8_t inserted_length;
+    uint32_t num = 0U;
+
+    inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U);
+    num = 3U - (inserted_length - inserted_channel);
+    
+    if(num <= 3U){
+        /* calculate the offset of the register */
+        num = num * 4U;
+        /* configure the offset of the selected channels */
+        REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
+    }
+}
+
+/*!
+    \brief      enable or disable ADC external trigger 
+    \param[in]  channel_group: select the channel group
+                one or more parameters can be selected which is shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+    \param[in]  newvalue: ENABLE or DISABLE
+    \param[out] none
+    \retval     none
+*/
+void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue)
+{
+    if(newvalue){
+        /* external trigger enable for regular channel */
+        if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
+            ADC_CTL1 |= ADC_CTL1_ETERC;
+        }
+        /* external trigger enable for inserted channel */
+        if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
+            ADC_CTL1 |= ADC_CTL1_ETEIC;
+        }
+    }else{
+        /* external trigger disable for regular channel */
+        if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
+            ADC_CTL1 &= ~ADC_CTL1_ETERC;
+        }
+        /* external trigger disable for inserted channel */
+        if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
+            ADC_CTL1 &= ~ADC_CTL1_ETEIC;
+        }
+    }
+}
+
+/*!
+    \brief      configure ADC external trigger source 
+    \param[in]  channel_group: select the channel group
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+    \param[in]  external_trigger_source: regular or inserted group trigger source
+                only one parameter can be selected which is shown as below:
+                for regular channel:
+      \arg        ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select 
+      \arg        ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select 
+      \arg        ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select  
+      \arg        ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select 
+      \arg        ADC_EXTTRIG_REGULAR_T14_CH0:  TIMER14 CH0 event select 
+      \arg        ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11
+      \arg        ADC_EXTTRIG_REGULAR_NONE: software trigger
+                for inserted channel:
+      \arg        ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
+      \arg        ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select 
+      \arg        ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select 
+      \arg        ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select 
+      \arg        ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 
+      \arg        ADC_EXTTRIG_INSERTED_NONE: software trigger
+    \param[out] none
+    \retval     none
+*/
+void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source)
+{   
+    switch(channel_group){
+    case ADC_REGULAR_CHANNEL:
+        /* external trigger select for regular channel */
+        ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC);
+        ADC_CTL1 |= (uint32_t)external_trigger_source;
+        break;
+    case ADC_INSERTED_CHANNEL:
+        /* external trigger select for inserted channel */
+        ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC);
+        ADC_CTL1 |= (uint32_t)external_trigger_source;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      enable ADC software trigger 
+    \param[in]  channel_group: select the channel group
+                one or more parameters can be selected which is shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+    \param[out] none
+    \retval     none
+*/
+void adc_software_trigger_enable(uint8_t channel_group)
+{
+    /* enable regular group channel software trigger */
+    if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
+        ADC_CTL1 |= ADC_CTL1_SWRCST;
+    }
+    /* enable inserted channel group software trigger */
+    if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
+        ADC_CTL1 |= ADC_CTL1_SWICST;
+    }
+}
+
+/*!
+    \brief      read ADC regular group data register 
+    \param[in]  none
+    \param[out] none
+    \retval     the conversion value
+*/
+uint16_t adc_regular_data_read(void)
+{
+    return ((uint16_t)ADC_RDATA);
+}
+
+/*!
+    \brief      read ADC inserted group data register 
+    \param[in]  inserted_channel: inserted channel select
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_INSERTED_CHANNEL_0: ADC inserted channel 0
+      \arg        ADC_INSERTED_CHANNEL_1: ADC inserted channel 1
+      \arg        ADC_INSERTED_CHANNEL_2: ADC inserted channel 2
+      \arg        ADC_INSERTED_CHANNEL_3: ADC inserted channel 3
+    \param[out] none
+    \retval     the conversion value
+*/
+uint16_t adc_inserted_data_read(uint8_t inserted_channel)
+{
+    uint32_t idata;
+    /* read the data of the selected channel */
+    switch(inserted_channel){
+    case ADC_INSERTED_CHANNEL_0:
+        idata = ADC_IDATA0;
+        break;
+    case ADC_INSERTED_CHANNEL_1:
+        idata = ADC_IDATA1;
+        break;
+    case ADC_INSERTED_CHANNEL_2:
+        idata = ADC_IDATA2;
+        break;
+    case ADC_INSERTED_CHANNEL_3:
+        idata = ADC_IDATA3;
+        break;
+    default:
+        idata = 0U;
+        break;
+    }
+    return (uint16_t)idata;
+}
+
+/*!
+    \brief      get the ADC flag bits
+    \param[in]  flag: the adc flag bits
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_FLAG_WDE: analog watchdog event flag
+      \arg        ADC_FLAG_EOC: end of group conversion flag
+      \arg        ADC_FLAG_EOIC: end of inserted group conversion flag
+      \arg        ADC_FLAG_STIC: start flag of inserted channel group
+      \arg        ADC_FLAG_STRC: start flag of regular channel group
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus adc_flag_get(uint32_t flag)
+{
+    FlagStatus reval = RESET;
+    
+    if(ADC_STAT & flag){
+        reval = SET;
+    }
+    return reval;
+}
+
+/*!
+    \brief      clear the ADC flag 
+    \param[in]  flag: the adc flag 
+                one or more parameters can be selected which is shown as below:
+      \arg        ADC_FLAG_WDE: analog watchdog event flag
+      \arg        ADC_FLAG_EOC: end of group conversion flag
+      \arg        ADC_FLAG_EOIC: end of inserted group conversion flag
+      \arg        ADC_FLAG_STIC: start flag of inserted channel group
+      \arg        ADC_FLAG_STRC: start flag of regular channel group
+    \param[out] none
+    \retval     none
+*/
+void adc_flag_clear(uint32_t flag)
+{
+    ADC_STAT &= ~((uint32_t)flag);
+}
+
+/*!
+    \brief      get the ADC interrupt flag
+    \param[in]  flag: the adc interrupt flag
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_INT_FLAG_WDE: analog watchdog interrupt flag
+      \arg        ADC_INT_FLAG_EOC: end of group conversion interrupt flag
+      \arg        ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus adc_interrupt_flag_get(uint32_t flag)
+{
+    FlagStatus interrupt_flag = RESET;
+    uint32_t state;
+
+    /* check the interrupt bits */
+    switch(flag){
+    case ADC_INT_FLAG_WDE:
+        state = ADC_STAT & ADC_STAT_WDE;
+        if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){
+          interrupt_flag = SET;
+        }
+        break;
+    case ADC_INT_FLAG_EOC:
+        state = ADC_STAT & ADC_STAT_EOC;
+        if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){
+            interrupt_flag = SET;
+          }
+        break;
+    case ADC_INT_FLAG_EOIC:
+        state = ADC_STAT & ADC_STAT_EOIC;
+        if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){
+            interrupt_flag = SET;
+        }
+        break;
+    default:
+        break;
+    }
+    return interrupt_flag;
+}
+
+/*!
+    \brief      clear ADC interrupt flag
+    \param[in]  flag: the adc interrupt flag
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_INT_FLAG_WDE: analog watchdog interrupt flag
+      \arg        ADC_INT_FLAG_EOC: end of group conversion interrupt flag
+      \arg        ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
+    \param[out] none
+    \retval     none
+*/
+void adc_interrupt_flag_clear(uint32_t flag)
+{
+    ADC_STAT &= ~((uint32_t)flag);
+}
+
+/*!
+    \brief      enable ADC interrupt 
+    \param[in]  interrupt: the adc interrupt
+                one or more parameters can be selected which is shown as below:
+      \arg        ADC_INT_WDE: analog watchdog interrupt 
+      \arg        ADC_INT_EOC: end of group conversion interrupt 
+      \arg        ADC_INT_EOIC: end of inserted group conversion interrupt 
+    \param[out] none
+    \retval     none
+*/
+void adc_interrupt_enable(uint32_t interrupt)
+{
+    /* enable analog watchdog interrupt */
+    if(RESET != (interrupt & ADC_INT_WDE)){
+        ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE;
+    }  
+
+    /* enable end of group conversion interrupt */
+    if(RESET != (interrupt & ADC_INT_EOC)){
+        ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE;
+    }  
+
+    /* enable end of inserted group conversion interrupt */
+    if(RESET != (interrupt & ADC_INT_EOIC)){
+        ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE;
+    }
+}
+
+/*!
+    \brief      disable ADC interrupt 
+    \param[in]  interrupt: the adc interrupt flag
+                one or more parameters can be selected which is shown as below:
+      \arg        ADC_INT_WDE: analog watchdog interrupt 
+      \arg        ADC_INT_EOC: end of group conversion interrupt 
+      \arg        ADC_INT_EOIC: end of inserted group conversion interrupt 
+    \param[out] none
+    \retval     none
+*/
+void adc_interrupt_disable(uint32_t interrupt)
+{  
+    /* disable analog watchdog interrupt */
+    if(RESET != (interrupt & ADC_INT_WDE)){
+        ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE;
+    }
+    
+    /* disable end of group conversion interrupt */
+    if(RESET != (interrupt & ADC_INT_EOC)){
+        ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE;
+    }
+    
+    /* disable end of inserted group conversion interrupt */
+    if(RESET != (interrupt & ADC_INT_EOIC)){
+        ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE;
+    }
+}
+
+/*!
+    \brief      configure ADC analog watchdog single channel 
+    \param[in]  channel: the selected ADC channel
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx
+    \param[out] none
+    \retval     none
+*/
+void adc_watchdog_single_channel_enable(uint8_t channel)
+{
+    ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
+
+    ADC_CTL0 |= (uint32_t)channel;
+    ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
+}
+
+/*!
+    \brief      configure ADC analog watchdog group channel 
+    \param[in]  channel_group: the channel group use analog watchdog
+                only one parameter can be selected which is shown as below: 
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+      \arg        ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
+    \param[out] none
+    \retval     none
+*/
+void adc_watchdog_group_channel_enable(uint8_t channel_group)
+{
+    ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
+
+    /* select the group */
+    switch(channel_group){
+    case ADC_REGULAR_CHANNEL:
+        ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN;
+        break;
+    case ADC_INSERTED_CHANNEL:
+        ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN;
+        break;
+    case ADC_REGULAR_INSERTED_CHANNEL:
+        ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      disable ADC analog watchdog 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_watchdog_disable(void)
+{
+    ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
+}
+
+/*!
+    \brief      configure ADC analog watchdog threshold 
+    \param[in]  low_threshold: analog watchdog low threshold,0..4095
+    \param[in]  high_threshold: analog watchdog high threshold,0..4095
+    \param[out] none
+    \retval     none
+*/
+void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold)
+{
+    ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold);
+    ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold);
+}
+
+
+/*!
+    \brief      configure ADC resolution 
+    \param[in]  resolution: ADC resolution
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_RESOLUTION_12B: 12-bit ADC resolution
+      \arg        ADC_RESOLUTION_10B: 10-bit ADC resolution
+      \arg        ADC_RESOLUTION_8B: 8-bit ADC resolution
+      \arg        ADC_RESOLUTION_6B: 6-bit ADC resolution
+    \param[out] none
+    \retval     none
+*/
+void adc_resolution_config(uint32_t resolution)
+{
+    ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES);
+    ADC_CTL0 |= (uint32_t)resolution;
+}
+
+/*!
+    \brief      configure ADC oversample mode 
+    \param[in]  mode: ADC oversampling mode
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger
+      \arg        ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger
+    \param[in]  shift: ADC oversampling shift
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
+    \param[in]  ratio: ADC oversampling ratio
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2
+      \arg        ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4
+      \arg        ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8
+      \arg        ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16
+      \arg        ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32
+      \arg        ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64
+      \arg        ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128
+      \arg        ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256
+    \param[out] none
+    \retval     none
+*/
+void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio)
+{
+    /* configure ADC oversampling mode */
+    if(ADC_OVERSAMPLING_ONE_CONVERT == mode){
+        ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS;
+    }else{
+        ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
+    }
+    
+    /* configure the shift and ratio */
+    ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
+    ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio);
+}
+
+/*!
+    \brief      enable ADC oversample mode 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_oversample_mode_enable(void)
+{
+    ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN;
+}
+
+/*!
+    \brief      disable ADC oversample mode 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_oversample_mode_disable(void)
+{
+    ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_cmp.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_cmp.c
new file mode 100644
index 0000000000..46ef66cbcf
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_cmp.c
@@ -0,0 +1,180 @@
+/*!
+    \file    gd32e230_cmp.c
+    \brief   CMP driver
+
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_cmp.h"
+
+/*!
+    \brief      deinitialize comparator 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_deinit(void)
+{
+    CMP_CS = ((uint32_t)0x00000000U);
+}
+
+/*!
+    \brief      initialize comparator mode 
+    \param[in]  operating_mode
+      \arg        CMP_HIGHSPEED: high speed mode
+      \arg        CMP_MIDDLESPEED: medium speed mode
+      \arg        CMP_LOWSPEED: low speed mode
+      \arg        CMP_VERYLOWSPEED: very-low speed mode
+    \param[in]  inverting_input 
+      \arg        CMP_1_4VREFINT: VREFINT *1/4 input
+      \arg        CMP_1_2VREFINT: VREFINT *1/2 input
+      \arg        CMP_3_4VREFINT: VREFINT *3/4 input
+      \arg        CMP_VREFINT: VREFINT input
+      \arg        CMP_PA4: PA4 input
+      \arg        CMP_PA5: PA5 input
+      \arg        CMP_PA0: PA0 input
+      \arg        CMP_PA2: PA2 input
+    \param[in]  hysteresis
+      \arg        CMP_HYSTERESIS_NO: output no hysteresis
+      \arg        CMP_HYSTERESIS_LOW: output low hysteresis
+      \arg        CMP_HYSTERESIS_MIDDLE: output middle hysteresis
+      \arg        CMP_HYSTERESIS_HIGH: output high hysteresis
+    \param[out] none
+    \retval     none
+*/
+void cmp_mode_init(operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis)
+{
+    /* initialize comparator mode */
+    CMP_CS |= CS_CMPM(operating_mode) | CS_CMPMSEL(inverting_input) | CS_CMPHST(output_hysteresis);
+  
+}
+
+/*!
+    \brief      initialize comparator output
+    \param[in]  output_slection 
+      \arg        CMP_OUTPUT_NONE: output no selection
+      \arg        CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input
+      \arg        CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture 
+      \arg        CMP_OUTPUT_TIMER0OCPRECLR: TIMER 0 OCPRE_CLR input
+      \arg        CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture
+      \arg        CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input
+    \param[in]  output_polarity 
+      \arg        CMP_OUTPUT_POLARITY_INVERTED: output is inverted
+      \arg        CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted
+    \param[out] none
+    \retval     none
+*/
+void cmp_output_init(cmp_output_enum output_slection, uint32_t output_polarity)
+{
+    /* initialize comparator output */
+
+    CMP_CS |= CS_CMPOSEL(output_slection);
+    /* output polarity */
+    if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
+         CMP_CS |= CMP_CS_CMPPL;
+    }else{ 
+         CMP_CS &= ~CMP_CS_CMPPL;
+    }
+
+}
+
+/*!
+    \brief      enable comparator 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_enable(void)
+{
+    CMP_CS |= CMP_CS_CMPEN;
+}
+
+/*!
+    \brief      disable comparator 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_disable(void)
+{
+    CMP_CS &= ~CMP_CS_CMPEN;
+}
+
+/*!
+    \brief      enable comparator switch
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_switch_enable(void)
+{
+    CMP_CS |= CMP_CS_CMPSW;
+}
+
+/*!
+    \brief      disable comparator switch
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_switch_disable(void)
+{
+    CMP_CS &= ~CMP_CS_CMPSW;
+}
+
+/*!
+    \brief      get output level
+    \param[in]  none
+    \param[out] none
+    \retval     the output level
+*/
+uint32_t cmp_output_level_get(void)
+{
+    if(CMP_CS & CMP_CS_CMPO){
+        return CMP_OUTPUTLEVEL_HIGH;
+    }else{
+        return CMP_OUTPUTLEVEL_LOW;
+    }
+    
+}
+
+/*!
+    \brief      lock the comparator
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_lock_enable(void)
+{
+    CMP_CS |= CMP_CS_CMPLK;
+}
+
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_crc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_crc.c
new file mode 100644
index 0000000000..59391d7d38
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_crc.c
@@ -0,0 +1,206 @@
+/*!
+    \file    gd32e230_crc.c
+    \brief   CRC driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_crc.h"
+
+/*!
+    \brief      deinit CRC calculation unit
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void crc_deinit(void)
+{
+    CRC_IDATA = (uint32_t)0xFFFFFFFFU;
+    CRC_DATA  = (uint32_t)0xFFFFFFFFU;
+    CRC_FDATA = (uint32_t)0x00000000U;
+    CRC_POLY  = (uint32_t)0x04C11DB7U;
+    CRC_CTL   = CRC_CTL_RST;   
+}
+
+/*!
+    \brief      enable the reverse operation of output data
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void crc_reverse_output_data_enable(void)
+{
+    CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
+    CRC_CTL |= (uint32_t)CRC_CTL_REV_O;
+}
+
+/*!
+    \brief      disable the reverse operation of output data
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void crc_reverse_output_data_disable(void)
+{
+    CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
+}
+
+/*!
+    \brief      reset data register to the value of initializaiton data register
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void crc_data_register_reset(void)
+{
+    CRC_CTL |= (uint32_t)CRC_CTL_RST;
+}
+
+/*!
+    \brief      read the data register 
+    \param[in]  none
+    \param[out] none
+    \retval     32-bit value of the data register
+*/
+uint32_t crc_data_register_read(void)
+{
+    uint32_t data;
+    data = CRC_DATA;
+    return (data);
+}
+
+/*!
+    \brief      read the free data register
+    \param[in]  none
+    \param[out] none
+    \retval     8-bit value of the free data register
+*/
+uint8_t crc_free_data_register_read(void)
+{
+    uint8_t fdata;
+    fdata = (uint8_t)CRC_FDATA;
+    return (fdata);
+}
+
+/*!
+    \brief      write the free data register
+    \param[in]  free_data: specify 8-bit data
+    \param[out] none
+    \retval     none
+*/
+void crc_free_data_register_write(uint8_t free_data)
+{
+    CRC_FDATA = (uint32_t)free_data;
+}
+
+/*!
+    \brief      write the initializaiton data register
+    \param[in]  init_data:specify 32-bit data
+    \param[out] none
+    \retval     none
+*/
+void crc_init_data_register_write(uint32_t init_data)
+{
+    CRC_IDATA = (uint32_t)init_data;
+}
+
+/*!
+    \brief      configure the CRC input data function
+    \param[in]  data_reverse: specify input data reverse function
+      \arg        CRC_INPUT_DATA_NOT: input data is not reversed
+      \arg        CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
+      \arg        CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
+      \arg        CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
+    \param[out] none
+    \retval     none
+*/
+void crc_input_data_reverse_config(uint32_t data_reverse)
+{
+    CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I);
+    CRC_CTL |= (uint32_t)data_reverse;
+}
+
+/*!
+    \brief      configure the CRC size of polynomial function
+    \param[in]  poly_size: size of polynomial
+      \arg        CRC_CTL_PS_32: 32-bit polynomial for CRC calculation
+      \arg        CRC_CTL_PS_16: 16-bit polynomial for CRC calculation
+      \arg        CRC_CTL_PS_8: 8-bit polynomial for CRC calculation
+      \arg        CRC_CTL_PS_7: 7-bit polynomial for CRC calculation
+    \param[out] none
+    \retval     none
+*/
+void crc_polynomial_size_set(uint32_t poly_size)
+{
+    CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
+    CRC_CTL |= (uint32_t)poly_size;
+}
+
+/*!
+    \brief      configure the CRC polynomial value function
+    \param[in]  poly: configurable polynomial value
+    \param[out] none
+    \retval     none
+*/
+void crc_polynomial_set(uint32_t poly)
+{
+    CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
+    CRC_POLY = poly;
+}
+
+/*!
+    \brief      CRC calculate a 32-bit data
+    \param[in]  sdata: specify 32-bit data
+    \param[out] none
+    \retval     32-bit CRC calculate value
+*/
+uint32_t crc_single_data_calculate(uint32_t sdata)
+{
+    CRC_DATA = sdata;
+    return(CRC_DATA);
+}
+
+/*!
+    \brief      CRC calculate a 32-bit data array
+    \param[in]  array: pointer to an array of 32 bit data words
+    \param[in]  size: size of the array
+    \param[out] none
+    \retval     32-bit CRC calculate value
+*/
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
+{  
+    uint32_t index;
+    for(index = 0U; index < size; index++){
+        CRC_DATA = array[index];
+    }
+    return (CRC_DATA);    
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dbg.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dbg.c
new file mode 100644
index 0000000000..614bd6016e
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dbg.c
@@ -0,0 +1,140 @@
+/*!
+    \file    gd32e230_dbg.c
+    \brief   DBG driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_dbg.h"
+
+#define DBG_RESET_VAL       0x00000000U
+
+/*!
+    \brief      deinitialize the DBG
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dbg_deinit(void)
+{
+    DBG_CTL0 = DBG_RESET_VAL;
+    DBG_CTL1 = DBG_RESET_VAL;
+}
+
+/*!
+    \brief      read DBG_ID code register
+    \param[in]  none
+    \param[out] none
+    \retval     DBG_ID code
+*/
+uint32_t dbg_id_get(void)
+{
+    return DBG_ID;
+}
+
+/*!
+    \brief      enable low power behavior when the mcu is in debug mode
+    \param[in]  dbg_low_power:
+                this parameter can be any combination of the following values:
+      \arg        DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
+      \arg        DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
+      \arg        DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
+    \param[out] none
+    \retval     none
+*/
+void dbg_low_power_enable(uint32_t dbg_low_power)
+{
+    DBG_CTL0 |= dbg_low_power;
+}
+
+/*!
+    \brief      disable low power behavior when the mcu is in debug mode
+    \param[in]  dbg_low_power:
+                this parameter can be any combination of the following values:
+      \arg        DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
+      \arg        DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
+      \arg        DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
+    \param[out] none
+    \retval     none
+*/
+void dbg_low_power_disable(uint32_t dbg_low_power)
+{
+    DBG_CTL0 &= ~dbg_low_power;
+}
+
+/*!
+    \brief      enable peripheral behavior when the mcu is in debug mode
+    \param[in]  dbg_periph: DBG peripheral 
+                only one parameter can be selected which is shown as below:
+      \arg        DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
+      \arg        DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
+      \arg        DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
+      \arg        DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
+      \arg        DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
+      \arg        DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
+      \arg        DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
+      \arg        DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
+      \arg        DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
+      \arg        DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
+      \arg        DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
+      \arg        DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
+    \param[out] none
+    \retval     none
+*/
+void dbg_periph_enable(dbg_periph_enum dbg_periph)
+{
+    DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
+}
+
+/*!
+    \brief      disable peripheral behavior when the mcu is in debug mode
+    \param[in]  dbg_periph: DBG peripheral 
+                only one parameter can be selected which is shown as below:
+      \arg        DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
+      \arg        DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
+      \arg        DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
+      \arg        DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
+      \arg        DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
+      \arg        DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
+      \arg        DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
+      \arg        DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
+      \arg        DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
+      \arg        DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
+      \arg        DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
+      \arg        DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
+    \param[out] none
+    \retval     none
+*/
+void dbg_periph_disable(dbg_periph_enum dbg_periph)
+{
+    DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dma.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dma.c
new file mode 100644
index 0000000000..5cdf462001
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dma.c
@@ -0,0 +1,562 @@
+/*!
+    \file    gd32e230_dma.c
+    \brief   DMA driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_dma.h"
+
+/*!
+    \brief      deinitialize DMA a channel registers 
+    \param[in]  channelx: specify which DMA channel is deinitialized
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_deinit(dma_channel_enum channelx)
+{
+    /* disable DMA a channel */
+    DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
+    /* reset DMA channel registers */
+    DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
+    DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
+    DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
+    DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
+    DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
+}
+
+/*!
+    \brief      initialize the parameters of DMA struct with the default values
+    \param[in]  init_struct: the initialization data needed to initialize DMA channel
+    \param[out] none
+    \retval     none
+*/
+void dma_struct_para_init(dma_parameter_struct* init_struct)
+{
+    /* set the DMA struct with the default values */
+    init_struct->periph_addr  = 0U;
+    init_struct->periph_width = 0U; 
+    init_struct->periph_inc   = (uint8_t)DMA_PERIPH_INCREASE_DISABLE;
+    init_struct->memory_addr  = 0U;
+    init_struct->memory_width = 0U;
+    init_struct->memory_inc   = (uint8_t)DMA_MEMORY_INCREASE_DISABLE;
+    init_struct->number       = 0U;
+    init_struct->direction    = (uint8_t)DMA_PERIPHERAL_TO_MEMORY;
+    init_struct->priority     = (uint32_t)DMA_PRIORITY_LOW;
+}
+
+/*!
+    \brief      initialize DMA channel 
+    \param[in]  channelx: specify which DMA channel is initialized
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  init_struct: the data needed to initialize DMA channel
+                  periph_addr: peripheral base address
+                  periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT
+                  periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE 
+                  memory_addr: memory base address
+                  memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT
+                  memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
+                  direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL
+                  number: the number of remaining data to be transferred by the DMA
+                  priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
+    \param[out] none
+    \retval     none
+*/
+void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct)
+{
+    uint32_t ctl;
+    
+    dma_channel_disable(channelx);
+    
+    /* configure peripheral base address */
+    DMA_CHPADDR(channelx) = init_struct->periph_addr;
+    
+    /* configure memory base address */
+    DMA_CHMADDR(channelx) = init_struct->memory_addr;
+    
+    /* configure the number of remaining data to be transferred */
+    DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
+    
+    /* configure peripheral transfer width,memory transfer width,channel priotity */
+    ctl = DMA_CHCTL(channelx);
+    ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
+    ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
+    DMA_CHCTL(channelx) = ctl;
+
+    /* configure peripheral increasing mode */
+    if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
+        DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
+    }else{
+        DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
+    }
+
+    /* configure memory increasing mode */
+    if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){
+        DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
+    }else{
+        DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
+    }
+    
+    /* configure the direction of  data transfer */
+    if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
+        DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
+    }else{
+        DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
+    } 
+}
+
+/*!
+    \brief      enable DMA circulation mode  
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none 
+*/
+void dma_circulation_enable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN;
+}
+
+/*!
+    \brief      disable DMA circulation mode  
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none 
+*/
+void dma_circulation_disable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN;
+}
+
+/*!
+    \brief      enable memory to memory mode
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_to_memory_enable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M;
+}
+
+/*!
+    \brief      disable memory to memory mode
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_to_memory_disable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M;
+}
+
+/*!
+    \brief      enable DMA channel 
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none 
+*/
+void dma_channel_enable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN;
+}
+
+/*!
+    \brief      disable DMA channel 
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none 
+*/
+void dma_channel_disable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
+}
+
+/*!
+    \brief      set DMA peripheral base address  
+    \param[in]  channelx: specify which DMA channel to set peripheral base address 
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  address: peripheral base address
+    \param[out] none
+    \retval     none 
+*/
+void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
+{
+    DMA_CHPADDR(channelx) = address;
+}
+
+/*!
+    \brief      set DMA memory base address  
+    \param[in]  channelx: specify which DMA channel to set memory base address 
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  address: memory base address
+    \param[out] none
+    \retval     none 
+*/
+void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
+{
+    DMA_CHMADDR(channelx) = address;
+}
+
+/*!
+    \brief      set the number of remaining data to be transferred by the DMA  
+    \param[in]  channelx: specify which DMA channel to set number 
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  number: the number of remaining data to be transferred by the DMA
+    \param[out] none
+    \retval     none 
+*/
+void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
+{
+    DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK);
+}
+
+/*!
+    \brief      get the number of remaining data to be transferred by the DMA  
+    \param[in]  channelx: specify which DMA channel to set number 
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     the number of remaining data to be transferred by the DMA 
+*/
+uint32_t dma_transfer_number_get(dma_channel_enum channelx)
+{
+    return (uint32_t)DMA_CHCNT(channelx);
+}
+
+/*!
+    \brief      configure priority level of DMA channel
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  priority: priority level of this channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_PRIORITY_LOW: low priority
+      \arg        DMA_PRIORITY_MEDIUM: medium priority
+      \arg        DMA_PRIORITY_HIGH: high priority
+      \arg        DMA_PRIORITY_ULTRA_HIGH: ultra high priority
+    \param[out] none
+    \retval     none 
+*/
+void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
+{
+    uint32_t ctl;
+    
+    /* acquire DMA_CHxCTL register */
+    ctl = DMA_CHCTL(channelx);
+    /* assign regiser */
+    ctl &= ~DMA_CHXCTL_PRIO;
+    ctl |= priority;
+    DMA_CHCTL(channelx) = ctl;
+}
+
+/*!
+    \brief      configure transfer data width of memory 
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  mwidth: transfer data width of memory
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
+      \arg        DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
+      \arg        DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth)
+{
+    uint32_t ctl;
+    
+    /* acquire DMA_CHxCTL register */
+    ctl = DMA_CHCTL(channelx);
+    /* assign regiser */
+    ctl &= ~DMA_CHXCTL_MWIDTH;
+    ctl |= mwidth;
+    DMA_CHCTL(channelx) = ctl;
+}
+
+/*!
+    \brief      configure transfer data width of peripheral 
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  pwidth: transfer data width of peripheral
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
+      \arg        DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
+      \arg        DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
+    \param[out] none
+    \retval     none
+*/
+void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth)
+{
+    uint32_t ctl;
+    
+    /* acquire DMA_CHxCTL register */
+    ctl = DMA_CHCTL(channelx);
+    /* assign regiser */
+    ctl &= ~DMA_CHXCTL_PWIDTH;
+    ctl |= pwidth;
+    DMA_CHCTL(channelx) = ctl;
+}
+
+/*!
+    \brief      enable next address increasement algorithm of memory  
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_increase_enable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
+}
+
+/*!
+    \brief      disable next address increasement algorithm of memory  
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_increase_disable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
+}
+
+/*!
+    \brief      enable next address increasement algorithm of peripheral
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_periph_increase_enable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
+}
+
+/*!
+    \brief      disable next address increasement algorithm of peripheral  
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_periph_increase_disable(dma_channel_enum channelx)
+{
+    DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
+}
+
+/*!
+    \brief      configure the direction of data transfer on the channel  
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  direction: specify the direction of  data transfer
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
+      \arg        DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
+    \param[out] none
+    \retval     none
+*/
+void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction)
+{
+    if(DMA_PERIPHERAL_TO_MEMORY == direction){
+        DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
+    } else {
+        DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
+    }
+}
+
+/*!
+    \brief      check DMA flag is set or not 
+    \param[in]  channelx: specify which DMA channel to get flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_FLAG_G: global interrupt flag of channel
+      \arg        DMA_FLAG_FTF: full transfer finish flag of channel
+      \arg        DMA_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_FLAG_ERR: error flag of channel
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
+{
+    FlagStatus reval;
+
+    if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
+        reval = SET;
+    }else{
+        reval = RESET;
+    }
+    
+    return reval;
+}
+
+/*!
+    \brief      clear DMA a channel flag
+    \param[in]  channelx: specify which DMA channel to clear flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_FLAG_G: global interrupt flag of channel
+      \arg        DMA_FLAG_FTF: full transfer finish flag of channel
+      \arg        DMA_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_FLAG_ERR: error flag of channel
+    \param[out] none
+    \retval     none
+*/
+void dma_flag_clear(dma_channel_enum channelx, uint32_t flag)
+{
+    DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
+}
+
+/*!
+    \brief      check DMA flag and interrupt enable bit is set or not  
+    \param[in]  channelx: specify which DMA channel to get flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_INT_FLAG_FTF: transfer finish flag of channel
+      \arg        DMA_INT_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_INT_FLAG_ERR: error flag of channel
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
+{
+    uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
+    
+    switch(flag){
+        case DMA_INT_FLAG_FTF:
+            interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
+            interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
+            break;
+        case DMA_INT_FLAG_HTF:
+            interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
+            interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
+            break;
+        case DMA_INT_FLAG_ERR:
+            interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
+            interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE;
+            break;
+        default:
+            break;
+        }
+    
+    if(interrupt_flag && interrupt_enable){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear DMA a channel interrupt flag
+    \param[in]  channelx: specify which DMA channel to clear flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_INT_FLAG_G: global interrupt flag of channel
+      \arg        DMA_INT_FLAG_FTF: transfer finish flag of channel
+      \arg        DMA_INT_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_INT_FLAG_ERR: error flag of channel
+    \param[out] none
+    \retval     none
+*/
+void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
+{
+    DMA_INTC |= DMA_FLAG_ADD(flag,channelx);
+}
+
+/*!
+    \brief      enable DMA interrupt
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  source: specify which interrupt to enable
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_INT_ERR: channel error interrupt
+      \arg        DMA_INT_HTF: channel half transfer finish interrupt
+      \arg        DMA_INT_FTF: channel full transfer finish interrupt
+    \param[out] none
+    \retval     none
+*/
+void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
+{
+    DMA_CHCTL(channelx) |= source;
+}
+
+/*!
+    \brief      disable DMA interrupt
+    \param[in]  channelx: specify which DMA channel to set
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..4)
+    \param[in]  source: specify which interrupt to disable
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_INT_ERR: channel error interrupt
+      \arg        DMA_INT_HTF: channel half transfer finish interrupt
+      \arg        DMA_INT_FTF: channel full transfer finish interrupt
+    \param[out] none
+    \retval     none
+*/
+void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
+{
+    DMA_CHCTL(channelx) &= ~source;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_exti.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_exti.c
new file mode 100644
index 0000000000..894a38c62f
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_exti.c
@@ -0,0 +1,254 @@
+/*!
+    \file    gd32e230_exti.c
+    \brief   EXTI driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_exti.h"
+
+/*!
+    \brief      deinitialize the EXTI
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void exti_deinit(void)
+{
+    /* reset the value of all the EXTI registers */
+    EXTI_INTEN = (uint32_t)0x0F940000U;
+    EXTI_EVEN  = (uint32_t)0x00000000U;
+    EXTI_RTEN  = (uint32_t)0x00000000U;
+    EXTI_FTEN  = (uint32_t)0x00000000U;
+    EXTI_SWIEV = (uint32_t)0x00000000U;
+}
+
+/*!
+    \brief      initialize the EXTI
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..17,19,21): EXTI line x
+    \param[in]  mode: interrupt or event mode, refer to exti_mode_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_INTERRUPT: interrupt mode
+      \arg        EXTI_EVENT: event mode
+    \param[in]  trig_type: interrupt trigger type, refer to exti_trig_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_TRIG_RISING: rising edge trigger
+      \arg        EXTI_TRIG_FALLING: falling trigger
+      \arg        EXTI_TRIG_BOTH: rising and falling trigger
+    \param[out] none
+    \retval     none
+*/
+void exti_init(exti_line_enum linex, \
+                exti_mode_enum mode, \
+                exti_trig_type_enum trig_type)
+{
+    /* reset the EXTI line x */
+    EXTI_INTEN &= ~(uint32_t)linex;
+    EXTI_EVEN &= ~(uint32_t)linex;
+    EXTI_RTEN &= ~(uint32_t)linex;
+    EXTI_FTEN &= ~(uint32_t)linex;
+    
+    /* set the EXTI mode and enable the interrupts or events from EXTI line x */
+    switch(mode){
+    case EXTI_INTERRUPT:
+        EXTI_INTEN |= (uint32_t)linex;
+        break;
+    case EXTI_EVENT:
+        EXTI_EVEN |= (uint32_t)linex;
+        break;
+    default:
+        break;
+    }
+    
+    /* set the EXTI trigger type */
+    switch(trig_type){
+    case EXTI_TRIG_RISING:
+        EXTI_RTEN |= (uint32_t)linex;
+        EXTI_FTEN &= ~(uint32_t)linex;
+        break;
+    case EXTI_TRIG_FALLING:
+        EXTI_RTEN &= ~(uint32_t)linex;
+        EXTI_FTEN |= (uint32_t)linex;
+        break;
+    case EXTI_TRIG_BOTH:
+        EXTI_RTEN |= (uint32_t)linex;
+        EXTI_FTEN |= (uint32_t)linex;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      enable the interrupts from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..27): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_interrupt_enable(exti_line_enum linex)
+{
+    EXTI_INTEN |= (uint32_t)linex;
+}
+
+/*!
+    \brief      enable the events from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..27): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_event_enable(exti_line_enum linex)
+{
+    EXTI_EVEN |= (uint32_t)linex;
+}
+
+/*!
+    \brief      disable the interrupt from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..27): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_interrupt_disable(exti_line_enum linex)
+{
+    EXTI_INTEN &= ~(uint32_t)linex;
+}
+
+/*!
+    \brief      disable the events from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..27): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_event_disable(exti_line_enum linex)
+{
+    EXTI_EVEN &= ~(uint32_t)linex;
+}
+
+/*!
+    \brief      get EXTI lines flag
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..17,19,21): EXTI line x
+    \param[out] none
+    \retval     FlagStatus: status of flag (RESET or SET)
+*/
+FlagStatus exti_flag_get(exti_line_enum linex)
+{
+    if(RESET != (EXTI_PD & (uint32_t)linex)){
+        return SET;
+    }else{
+        return RESET;
+    } 
+}
+
+/*!
+    \brief      clear EXTI lines pending flag
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..17,19,21): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_flag_clear(exti_line_enum linex)
+{
+    EXTI_PD = (uint32_t)linex;
+}
+
+/*!
+    \brief      get EXTI lines flag when the interrupt flag is set
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..17,19,21): EXTI line x
+    \param[out] none
+    \retval     FlagStatus: status of flag (RESET or SET)
+*/
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
+{
+    uint32_t flag_left, flag_right;
+    
+    flag_left = EXTI_PD & (uint32_t)linex;
+    flag_right = EXTI_INTEN & (uint32_t)linex;
+    
+    if((RESET != flag_left) && (RESET != flag_right)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear EXTI lines pending flag
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..17,19,21): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_interrupt_flag_clear(exti_line_enum linex)
+{
+    EXTI_PD = (uint32_t)linex;
+}
+
+/*!
+    \brief      enable EXTI software interrupt event
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..17,19,21): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_software_interrupt_enable(exti_line_enum linex)
+{
+    EXTI_SWIEV |= (uint32_t)linex;
+}
+
+/*!
+    \brief      disable EXTI software interrupt event
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..17,19,21): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_software_interrupt_disable(exti_line_enum linex)
+{
+    EXTI_SWIEV &= ~(uint32_t)linex;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fmc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fmc.c
new file mode 100644
index 0000000000..1489157807
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fmc.c
@@ -0,0 +1,814 @@
+/*!
+    \file    gd32e230_fmc.c
+    \brief   FMC driver
+
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_fmc.h"
+
+/* FMC register bit offset */
+#define OB_HIGH_WP_OFFSET                 ((uint32_t)8U)
+#define FMC_OBSTAT_USER_OFFSET            ((uint32_t)8U)
+#define FMC_OBSTAT_DATA_OFFSET            ((uint32_t)16U)
+
+/*!
+    \brief      unlock the main FMC operation
+                it is better to used in pairs with fmc_lock
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fmc_unlock(void)
+{
+    if((RESET != (FMC_CTL & FMC_CTL_LK))){
+        /* write the FMC key */
+        FMC_KEY = UNLOCK_KEY0;
+        FMC_KEY = UNLOCK_KEY1;
+    }
+}
+
+/*!
+    \brief      lock the main FMC operation
+                it is better to used in pairs with fmc_unlock after an operation
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fmc_lock(void)
+{
+    /* set the LK bit*/
+    FMC_CTL |= FMC_CTL_LK;
+}
+
+/*!
+    \brief      set the wait state counter value
+    \param[in]  wscnt: wait state counter value
+      \arg        WS_WSCNT_0: 0 wait state added
+      \arg        WS_WSCNT_1: 1 wait state added
+      \arg        WS_WSCNT_2: 2 wait state added
+    \param[out] none
+    \retval     none
+*/
+void fmc_wscnt_set(uint8_t wscnt)
+{
+    uint32_t reg;
+    
+    reg = FMC_WS;
+    /* set the wait state counter value */
+    reg &= ~FMC_WS_WSCNT;
+    FMC_WS = (reg | wscnt);
+}
+
+/*!
+    \brief      pre-fetch enable
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fmc_prefetch_enable(void)
+{
+    FMC_WS |= FMC_WS_PFEN;
+}
+
+/*!
+    \brief      pre-fetch disable
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fmc_prefetch_disable(void)
+{
+    FMC_WS &= ~FMC_WS_PFEN;
+}
+
+/*!
+    \brief      erase page
+    \param[in]  page_address: target page start address
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum fmc_page_erase(uint32_t page_address)
+{
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+  
+    if(FMC_READY == fmc_state){ 
+        /* start page erase */
+        FMC_CTL |= FMC_CTL_PER;
+        FMC_ADDR = page_address;
+        FMC_CTL |= FMC_CTL_START;
+
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+        /* reset the PER bit */
+        FMC_CTL &= ~FMC_CTL_PER;
+    }
+    
+    /* return the FMC state  */
+    return fmc_state;
+}
+
+/*!
+    \brief      erase whole chip
+    \param[in]  none
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum fmc_mass_erase(void)
+{
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+  
+    if(FMC_READY == fmc_state){ 
+        /* start chip erase */
+        FMC_CTL |= FMC_CTL_MER; 
+        FMC_CTL |= FMC_CTL_START;
+    
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+        /* reset the MER bit */
+        FMC_CTL &= ~FMC_CTL_MER;
+    }
+    
+    /* return the fmc state  */
+    return fmc_state;
+}
+
+/*!
+    \brief      program a double word at the corresponding address in main flash, this 
+                function also applies to OTP(address 0x1FFF_7000~0x1FFF_73FF) programming
+    \param[in]  address: address to program
+    \param[in]  data: double word to program
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data)
+{
+    uint32_t data0, data1;
+    
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    data0 = (uint32_t)(data & 0xFFFFFFFFU);
+    data1 = (uint32_t)((data>>32U) & 0xFFFFFFFFU);
+    
+    /* configure program width */
+    FMC_WS |= FMC_WS_PGW;
+    if(FMC_READY == fmc_state){ 
+        /* set the PG bit to start program */
+        FMC_CTL |= FMC_CTL_PG; 
+        REG32(address) = data0;
+        REG32(address+4U) = data1;
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+        /* reset the PG bit */
+        FMC_CTL &= ~FMC_CTL_PG; 
+    }
+    FMC_WS &= ~(FMC_WS_PGW);
+  
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      program a word at the corresponding address in main flash, this function 
+                also applies to OTP(address 0x1FFF_7000~0x1FFF_73FF) programming
+    \param[in]  address: address to program
+    \param[in]  data: word to program
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
+{
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+    if(FMC_READY == fmc_state){ 
+        /* set the PG bit to start program */
+        FMC_CTL |= FMC_CTL_PG; 
+  
+        REG32(address) = data;
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+        /* reset the PG bit */
+        FMC_CTL &= ~FMC_CTL_PG; 
+    } 
+  
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      unlock the option byte operation
+                it is better to used in pairs with ob_lock
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ob_unlock(void)
+{
+    if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){
+        /* write the FMC key */
+        FMC_OBKEY = UNLOCK_KEY0;
+        FMC_OBKEY = UNLOCK_KEY1;
+    }
+    /* wait until OBWEN bit is set by hardware */
+    while(RESET == (FMC_CTL & FMC_CTL_OBWEN)){
+    }
+}
+
+/*!
+    \brief      lock the option byte operation
+                it is better to used in pairs with ob_unlock after an operation
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ob_lock(void)
+{
+    /* reset the OBWE bit */
+    FMC_CTL &= ~FMC_CTL_OBWEN;
+}
+
+/*!
+    \brief      reload the option byte and generate a system reset
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ob_reset(void)
+{
+    /* set the OBRLD bit */
+    FMC_CTL |= FMC_CTL_OBRLD;
+}
+
+/*!
+    \brief      get option byte value
+    \param[in]  addr: address of option byte
+      \arg        OB_SPC_USER_ADDRESS: address of option byte security protection and user
+      \arg        OB_DATA_ADDRESS: address of option byte data
+      \arg        OB_WP_ADDRESS: address of option byte write protection
+    \param[out] option byte value
+*/
+uint32_t option_byte_value_get(uint32_t addr)
+{
+    return *(volatile uint32_t *)(addr);
+}
+
+/*!
+    \brief      erase the option byte
+                programmer must ensure FMC & option byte are both unlocked before calling this function
+    \param[in]  none
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum ob_erase(void)
+{
+    uint16_t fmc_spc;
+    uint32_t val;
+    uint32_t fmc_plevel = ob_obstat_plevel_get();
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+    /* get the original option byte security protection code */
+    if(OB_OBSTAT_PLEVEL_NO == fmc_plevel){
+        fmc_spc = FMC_NSPC;
+    }else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel){
+        fmc_spc = FMC_LSPC;
+    }else{
+        fmc_spc = FMC_HSPC;
+        fmc_state = FMC_OB_HSPC;
+    }
+    val = HIGH_16BITS_MASK | (uint32_t)fmc_spc;
+    
+    if(FMC_READY == fmc_state){
+        /* start erase the option byte */
+        FMC_CTL |= FMC_CTL_OBER;
+        FMC_CTL |= FMC_CTL_START;
+
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+        if(FMC_READY == fmc_state){
+            /* reset the OBER bit */
+            FMC_CTL &= ~FMC_CTL_OBER;
+       
+            /* set the OBPG bit */
+            FMC_CTL |= FMC_CTL_OBPG;
+            
+            /* restore the last get option byte security protection code */
+            OB_SPC_USER = val;
+
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+ 
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
+            }
+        }else{
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
+            }
+        }  
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      enable option byte write protection (OB_WP)
+    \param[in]  ob_wp: write protection configuration data. Notice that set the
+                bit to 1 if you want to protect the corresponding pages.
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum ob_write_protection_enable(uint16_t ob_wp)
+{
+    uint32_t ob_wrp_val = 0U;
+
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+    ob_wp = (uint16_t)(~ob_wp);
+    ob_wrp_val |= (uint32_t)ob_wp&0x00FFU;
+    ob_wrp_val |= (((uint32_t)ob_wp&0xFF00U)>>8U) << 16U;
+    
+    if(FMC_READY == fmc_state){
+        /* set the OBPG bit*/
+        FMC_CTL |= FMC_CTL_OBPG;
+
+        if(0xFFFFFFFFU != ob_wrp_val){
+            OB_WP = ob_wrp_val;
+    
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        }
+        if(FMC_TOERR != fmc_state){
+            /* reset the OBPG bit */
+            FMC_CTL &= ~FMC_CTL_OBPG;
+        }
+    } 
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      configure security protection
+    \param[in]  ob_spc: specify security protection code
+      \arg        FMC_NSPC: no security protection
+      \arg        FMC_LSPC: low security protection
+      \arg        FMC_HSPC: high security protection
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum ob_security_protection_config(uint16_t ob_spc)
+{
+    uint32_t val;
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    val = option_byte_value_get(OB_SPC_USER_ADDRESS);
+    /* the OB_SPC byte cannot be reprogrammed if protection level is high */
+    if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()){
+        fmc_state = FMC_OB_HSPC;
+    }
+    
+    val &= ~LOW_16BITS_MASK;
+    val |= (uint32_t)ob_spc;
+
+    if(FMC_READY == fmc_state){
+        /* start erase the option byte */
+        FMC_CTL |= FMC_CTL_OBER;
+        FMC_CTL |= FMC_CTL_START;
+    
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+        if(FMC_READY == fmc_state){
+        
+            /* reset the OBER bit */
+            FMC_CTL &= ~FMC_CTL_OBER;
+      
+            /* enable the option bytes programming */
+            FMC_CTL |= FMC_CTL_OBPG;
+       
+            OB_SPC_USER = val;
+
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); 
+    
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
+            }
+        }else{
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBER bit */
+                FMC_CTL &= ~FMC_CTL_OBER;
+            }
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      program the FMC user option byte
+                this function can only clear the corresponding bits to be 0 rather than 1.
+                the function ob_erase is used to set all the bits to be 1.
+    \param[in]  ob_user: user option byte
+                one or more parameters (bitwise AND) can be selected which are shown as below:
+      \arg        OB_FWDGT_HW: hardware free watchdog timer
+      \arg        OB_DEEPSLEEP_RST: no reset when entering deepsleep mode
+      \arg        OB_STDBY_RST: no reset when entering standby mode
+      \arg        OB_BOOT1_SET_1: BOOT1 bit is 1
+      \arg        OB_VDDA_DISABLE: disable VDDA monitor
+      \arg        OB_SRAM_PARITY_ENABLE: enable sram parity check
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum ob_user_write(uint8_t ob_user)
+{
+    uint32_t val_spc_user;
+    /* check whether FMC is ready or not */
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+    val_spc_user = option_byte_value_get(OB_SPC_USER_ADDRESS);
+    
+    val_spc_user &= ~HIGH_16BITS_MASK;
+    
+    val_spc_user |= ((uint32_t)ob_user<<16U);
+    
+    if(FMC_READY == fmc_state){
+        /* start erase the option byte */
+        FMC_CTL |= FMC_CTL_OBER;
+        FMC_CTL |= FMC_CTL_START;
+    
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+        if(FMC_READY == fmc_state){
+        
+            /* reset the OBER bit */
+            FMC_CTL &= ~FMC_CTL_OBER;
+      
+            /* enable the option bytes programming */
+            FMC_CTL |= FMC_CTL_OBPG;
+       
+            OB_SPC_USER = val_spc_user;
+            
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); 
+    
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL &= ~FMC_CTL_OBPG;
+            }
+        }else{
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBER bit */
+                FMC_CTL &= ~FMC_CTL_OBER;
+            }
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      program the FMC data option byte
+    \param[in]  data: the data to be programmed, OB_DATA[0:15]
+    \param[out] none
+    \retval     fmc_state: state of FMC
+      \arg        FMC_READY: the operation has been completed
+      \arg        FMC_BUSY: the operation is in progress
+      \arg        FMC_PGERR: program error
+      \arg        FMC_PGAERR: program alignment error
+      \arg        FMC_WPERR: erase/program protection error
+      \arg        FMC_TOERR: timeout error
+      \arg        FMC_OB_HSPC: option byte security protection code high
+*/
+fmc_state_enum ob_data_program(uint16_t data)
+{
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    uint32_t val = 0U;
+
+    val |= (uint32_t)data&0x00FFU;
+    val |= (((uint32_t)data&0xFF00U)>>8U) << 16U;
+    
+    if(FMC_READY == fmc_state){
+        /* set the OBPG bit */
+        FMC_CTL |= FMC_CTL_OBPG; 
+        OB_DATA = val;
+    
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    
+        if(FMC_TOERR != fmc_state){
+            /* reset the OBPG bit */
+            FMC_CTL &= ~FMC_CTL_OBPG;
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      get OB_USER in register FMC_OBSTAT
+    \param[in]  none
+    \param[out] none
+    \retval     ob_user
+*/
+uint8_t ob_user_get(void)
+{
+    return (uint8_t)(FMC_OBSTAT >> FMC_OBSTAT_USER_OFFSET);
+}
+
+/*!
+    \brief      get OB_DATA in register FMC_OBSTAT
+    \param[in]  none
+    \param[out] none
+    \retval     ob_data
+*/
+uint16_t ob_data_get(void)
+{
+    return (uint16_t)(FMC_OBSTAT >> FMC_OBSTAT_DATA_OFFSET);
+}
+
+/*!
+    \brief      get the FMC option byte write protection (OB_WP) in register FMC_WP
+    \param[in]  none
+    \param[out] none
+    \retval     OB_WP
+*/
+uint16_t ob_write_protection_get(void)
+{
+    return (uint16_t)(FMC_WP);
+}
+
+/*!
+    \brief      get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register
+    \param[in]  none
+    \param[out] none
+    \retval     the value of PLEVEL
+*/
+uint32_t ob_obstat_plevel_get(void)
+{
+    return (FMC_OBSTAT & (FMC_OBSTAT_PLEVEL_BIT0 | FMC_OBSTAT_PLEVEL_BIT1));
+}
+
+/* FMC interrupts and flags management functions */
+/*!
+    \brief      enable FMC interrupt
+    \param[in]  interrupt: the FMC interrupt source
+      \arg        FMC_INTEN_END: FMC end of operation interrupt
+      \arg        FMC_INTEN_ERR: FMC error interrupt
+    \param[out] none
+    \retval     none
+*/
+void fmc_interrupt_enable(uint32_t interrupt)
+{
+    FMC_CTL |= interrupt;
+}
+
+/*!
+    \brief      disable FMC interrupt
+    \param[in]  interrupt: the FMC interrupt source
+      \arg        FMC_INTEN_END: FMC end of operation interrupt
+      \arg        FMC_INTEN_ERR: FMC error interrupt
+    \param[out] none
+    \retval     none
+*/
+void fmc_interrupt_disable(uint32_t interrupt)
+{
+    FMC_CTL &= ~(uint32_t)interrupt;
+}
+
+/*!
+    \brief      get flag set or reset
+    \param[in]  flag: check FMC flag
+                only one parameter can be selected which is shown as below:
+      \arg        FMC_FLAG_BUSY: FMC busy flag
+      \arg        FMC_FLAG_PGERR: FMC programming error flag
+      \arg        FMC_FLAG_PGAERR: FMC program alignment error flag
+      \arg        FMC_FLAG_WPERR: FMC write protection error flag
+      \arg        FMC_FLAG_END: FMC end of programming flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus fmc_flag_get(uint32_t flag)
+{
+    FlagStatus status = RESET;
+
+    if(FMC_STAT & flag){
+        status = SET;
+    }
+    /* return the state of corresponding FMC flag */
+    return status; 
+}
+
+/*!
+    \brief      clear the FMC pending flag by writing 1
+    \param[in]  flag: clear FMC flag
+                one or more parameters can be selected which is shown as below:
+      \arg        FMC_FLAG_PGERR: FMC programming error flag
+      \arg        FMC_FLAG_PGAERR: FMC program alignment error flag
+      \arg        FMC_FLAG_WPERR: FMC write protection error flag
+      \arg        FMC_FLAG_END: FMC end of programming flag
+    \param[out] none
+    \retval     none
+*/
+void fmc_flag_clear(uint32_t flag)
+{
+    /* clear the flags */
+    FMC_STAT = flag;
+}
+
+/*!
+    \brief      get intrrupt flag set or reset
+    \param[in]  flag: check FMC flag
+                only one parameter can be selected which is shown as below:
+      \arg        FMC_INT_FLAG_PGERR: FMC programming error flag
+      \arg        FMC_INT_FLAG_PGAERR: FMC program alignment error flag
+      \arg        FMC_INT_FLAG_WPERR: FMC write protection error flag
+      \arg        FMC_INT_FLAG_END: FMC end of programming flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus fmc_interrupt_flag_get(uint32_t int_flag)
+{
+    uint32_t intenable = 0U, flagstatus = 0U;
+    
+    if(FMC_INT_FLAG_END == int_flag){
+        /* get the interrupt enable bit status */
+        intenable = FMC_CTL & FMC_INTEN_END;
+        /* get the corresponding flag bit status */
+        flagstatus = FMC_STAT & int_flag;
+        if(intenable && flagstatus){
+            return SET;
+        }else{
+            return RESET;
+        }
+    }else{
+        /* get the interrupt enable bit status */
+        intenable = FMC_CTL & FMC_INTEN_ERR;
+        /* get the corresponding flag bit status */
+        flagstatus = FMC_STAT & int_flag;
+        if(intenable && flagstatus){
+            return SET;
+        }else{
+            return RESET;
+        }
+    }
+}
+
+/*!
+    \brief      clear the FMC interrupt pending flag by writing 1
+    \param[in]  flag: clear FMC flag
+                one or more parameters can be selected which is shown as below:
+      \arg        FMC_INT_FLAG_PGERR: FMC programming error flag
+      \arg        FMC_INT_FLAG_PGAERR: FMC program alignment error flag
+      \arg        FMC_INT_FLAG_WPERR: FMC write protection error flag
+      \arg        FMC_INT_FLAG_END: FMC end of programming flag
+    \param[out] none
+    \retval     none
+*/
+void fmc_interrupt_flag_clear(uint32_t int_flag)
+{
+    /* clear the flags */
+    FMC_STAT = int_flag;
+}
+
+/*!
+    \brief      get the FMC state
+    \param[in]  none
+    \param[out] none
+    \retval     fmc_state
+*/
+fmc_state_enum fmc_state_get(void)
+{
+    fmc_state_enum fmc_state = FMC_READY;
+  
+    if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){
+        fmc_state = FMC_BUSY;
+    }else{
+        if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){
+            fmc_state = FMC_WPERR;
+        }else{
+            if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)){
+                fmc_state = FMC_PGERR; 
+            }
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      check whether FMC is ready or not
+    \param[in]  timeout: timeout count
+    \param[out] none
+    \retval     fmc_state
+*/
+fmc_state_enum fmc_ready_wait(uint32_t timeout)
+{
+    fmc_state_enum fmc_state = FMC_BUSY;
+  
+    /* wait for FMC ready */
+    do{
+        /* get FMC state */
+        fmc_state = fmc_state_get();
+        timeout--;
+    }while((FMC_BUSY == fmc_state) && (0U != timeout));
+  
+    if(FMC_BUSY == fmc_state){
+        fmc_state = FMC_TOERR;
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fwdgt.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fwdgt.c
new file mode 100644
index 0000000000..d3daa1fc32
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fwdgt.c
@@ -0,0 +1,252 @@
+/*!
+    \file    gd32e230_fwdgt.c
+    \brief   FWDGT driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_fwdgt.h"
+
+/* write value to FWDGT_CTL_CMD bit field */
+#define CTL_CMD(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0U))  /*!< write value to FWDGT_CTL_CMD bit field */
+/* write value to FWDGT_RLD_RLD bit field */
+#define RLD_RLD(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0U))  /*!< write value to FWDGT_RLD_RLD bit field */
+/* write value to FWDGT_WND_WND bit field */
+#define WND_WND(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0U))  /*!< write value to FWDGT_WND_WND bit field */
+
+/*!
+    \brief      enable write access to FWDGT_PSC and FWDGT_RLD
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_write_enable(void)
+{
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+}
+
+/*!
+    \brief      disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_write_disable(void)
+{
+    FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
+}
+
+/*!
+    \brief      start the free watchdog timer counter
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_enable(void)
+{
+    FWDGT_CTL = FWDGT_KEY_ENABLE;
+}
+
+/*!
+    \brief      configure the free watchdog timer counter prescaler value
+    \param[in]  prescaler_value: specify prescaler value
+                only one parameter can be selected which is shown as below:
+      \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
+      \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
+      \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
+      \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
+      \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
+      \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
+      \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
+{
+    uint32_t timeout = FWDGT_PSC_TIMEOUT;
+    uint32_t flag_status = RESET;
+  
+    /* enable write access to FWDGT_PSC */
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+  
+    /* wait until the PUD flag to be reset */
+    do{
+        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
+    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+    
+    if ((uint32_t)RESET != flag_status){
+        return ERROR;
+    }
+    
+    /* configure FWDGT */
+    FWDGT_PSC = (uint32_t)prescaler_value; 
+
+    return SUCCESS;
+}
+
+/*!
+    \brief      configure the free watchdog timer counter reload value
+    \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
+{
+    uint32_t timeout = FWDGT_RLD_TIMEOUT;
+    uint32_t flag_status = RESET;
+  
+    /* enable write access to FWDGT_RLD */
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+  
+    /* wait until the RUD flag to be reset */
+    do{
+        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
+    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+   
+    if ((uint32_t)RESET != flag_status){
+        return ERROR;
+    }
+    
+    FWDGT_RLD = RLD_RLD(reload_value);
+
+    return SUCCESS;
+}
+
+/*!
+    \brief      configure the free watchdog timer counter window value
+    \param[in]  window_value: specify window value(0x0000 - 0x0FFF)
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_window_value_config(uint16_t window_value)
+{
+    uint32_t time_index = FWDGT_WND_TIMEOUT;
+    uint32_t flag_status = RESET;
+
+    /* enable write access to FWDGT_WND */
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+
+    /* wait until the WUD flag to be reset */
+    do{
+        flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
+    }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
+
+    if ((uint32_t)RESET != flag_status){
+        return ERROR; 
+    }
+    
+    FWDGT_WND = WND_WND(window_value);
+
+    return SUCCESS;
+}
+
+/*!
+    \brief      reload the counter of FWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_counter_reload(void)
+{
+    FWDGT_CTL = FWDGT_KEY_RELOAD;
+}
+
+/*!
+    \brief      configure counter reload value, and prescaler divider value
+    \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
+    \param[in]  prescaler_div: FWDGT prescaler value
+                only one parameter can be selected which is shown as below:
+      \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
+      \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
+      \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
+      \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
+      \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
+      \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
+      \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
+{
+    uint32_t timeout = FWDGT_PSC_TIMEOUT;
+    uint32_t flag_status = RESET;
+  
+    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+  
+    /* wait until the PUD flag to be reset */
+    do{
+        flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
+    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+    
+    if ((uint32_t)RESET != flag_status){
+        return ERROR;
+    }
+    
+    /* configure FWDGT */
+    FWDGT_PSC = (uint32_t)prescaler_div;       
+
+    timeout = FWDGT_RLD_TIMEOUT;    
+    /* wait until the RUD flag to be reset */
+    do{
+        flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
+    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+   
+    if ((uint32_t)RESET != flag_status){
+        return ERROR;
+    }
+    
+    FWDGT_RLD = RLD_RLD(reload_value);
+    
+    /* reload the counter */
+    FWDGT_CTL = FWDGT_KEY_RELOAD;
+    
+    return SUCCESS;
+}
+
+/*!
+    \brief      get flag state of FWDGT
+    \param[in]  flag: flag to get 
+                only one parameter can be selected which is shown as below:
+      \arg        FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
+      \arg        FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
+      \arg        FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus fwdgt_flag_get(uint16_t flag)
+{
+    if(RESET != (FWDGT_STAT & flag)){
+        return SET;
+    }
+    return RESET;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_gpio.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_gpio.c
new file mode 100644
index 0000000000..7223c98b85
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_gpio.c
@@ -0,0 +1,399 @@
+/*!
+    \file    gd32e230_gpio.c
+    \brief   GPIO driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_gpio.h"
+
+/*!
+    \brief      reset GPIO port
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F)
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[out] none
+    \retval     none
+*/
+void gpio_deinit(uint32_t gpio_periph)
+{
+    switch(gpio_periph){
+    case GPIOA:
+        /* reset GPIOA */
+        rcu_periph_reset_enable(RCU_GPIOARST);
+        rcu_periph_reset_disable(RCU_GPIOARST);
+        break;
+    case GPIOB:
+        /* reset GPIOB */
+        rcu_periph_reset_enable(RCU_GPIOBRST);
+        rcu_periph_reset_disable(RCU_GPIOBRST);
+        break;
+    case GPIOC:
+        /* reset GPIOC */
+        rcu_periph_reset_enable(RCU_GPIOCRST);
+        rcu_periph_reset_disable(RCU_GPIOCRST);
+        break;
+    case GPIOF:
+        /* reset GPIOF */
+        rcu_periph_reset_enable(RCU_GPIOFRST);
+        rcu_periph_reset_disable(RCU_GPIOFRST);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      set GPIO mode
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  mode: gpio pin mode
+      \arg        GPIO_MODE_INPUT: input mode
+      \arg        GPIO_MODE_OUTPUT: output mode
+      \arg        GPIO_MODE_AF: alternate function mode
+      \arg        GPIO_MODE_ANALOG: analog mode
+    \param[in]  pull_up_down: gpio pin with pull-up or pull-down resistor
+      \arg        GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors
+      \arg        GPIO_PUPD_PULLUP: with pull-up resistor
+      \arg        GPIO_PUPD_PULLDOWN:with pull-down resistor
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
+{
+    uint16_t i;
+    uint32_t ctl, pupd;
+
+    ctl = GPIO_CTL(gpio_periph);
+    pupd = GPIO_PUD(gpio_periph);
+
+    for(i = 0U;i < 16U;i++){
+        if((1U << i) & pin){
+            /* clear the specified pin mode bits */
+            ctl &= ~GPIO_MODE_MASK(i);
+            /* set the specified pin mode bits */
+            ctl |= GPIO_MODE_SET(i, mode);
+
+            /* clear the specified pin pupd bits */
+            pupd &= ~GPIO_PUPD_MASK(i);
+            /* set the specified pin pupd bits */
+            pupd |= GPIO_PUPD_SET(i, pull_up_down);
+        }
+    }
+
+    GPIO_CTL(gpio_periph) = ctl;
+    GPIO_PUD(gpio_periph) = pupd;
+}
+
+/*!
+    \brief      set GPIO output type and speed
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  otype: gpio pin output mode
+      \arg        GPIO_OTYPE_PP: push pull mode
+      \arg        GPIO_OTYPE_OD: open drain mode
+    \param[in]  speed: gpio pin output max speed
+      \arg        GPIO_OSPEED_2MHZ: output max speed 2MHz 
+      \arg        GPIO_OSPEED_10MHZ: output max speed 10MHz 
+      \arg        GPIO_OSPEED_50MHZ: output max speed 50MHz
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
+{
+    uint16_t i;
+    uint32_t ospeed;
+
+    if(GPIO_OTYPE_OD == otype){
+        GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
+    }else{
+        GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
+    }
+
+    /* get the specified pin output speed bits value */
+    ospeed = GPIO_OSPD(gpio_periph);
+
+    for(i = 0U;i < 16U;i++){
+        if((1U << i) & pin){
+            /* clear the specified pin output speed bits */
+            ospeed &= ~GPIO_OSPEED_MASK(i);
+            /* set the specified pin output speed bits */
+            ospeed |= GPIO_OSPEED_SET(i,speed);
+        }
+    }
+    GPIO_OSPD(gpio_periph) = ospeed;
+}
+
+/*!
+    \brief      set GPIO pin bit
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
+{
+    GPIO_BOP(gpio_periph) = (uint32_t)pin;
+}
+
+/*!
+    \brief      reset GPIO pin bit
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
+{
+    GPIO_BC(gpio_periph) = (uint32_t)pin;
+}
+
+/*!
+    \brief      write data to the specified GPIO pin
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[in]  bit_value: SET or RESET
+      \arg        RESET: clear the port pin
+      \arg        SET: set the port pin
+    \param[out] none
+    \retval     none
+*/
+void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
+{
+    if(RESET != bit_value){
+        GPIO_BOP(gpio_periph) = (uint32_t)pin;
+    }else{
+        GPIO_BC(gpio_periph) = (uint32_t)pin;
+    }
+}
+
+/*!
+    \brief      write data to the specified GPIO port
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  data: specify the value to be written to the port output control register
+    \param[out] none
+    \retval     none
+*/
+void gpio_port_write(uint32_t gpio_periph, uint16_t data)
+{
+    GPIO_OCTL(gpio_periph) = (uint32_t)data;
+}
+
+/*!
+    \brief      get GPIO pin input status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     SET or RESET
+*/
+FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
+{
+    if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
+        return SET; 
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      get GPIO all pins input status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[out] none
+    \retval     state of GPIO all pins
+*/
+uint16_t gpio_input_port_get(uint32_t gpio_periph)
+{
+    return (uint16_t)GPIO_ISTAT(gpio_periph);
+}
+
+/*!
+    \brief      get GPIO pin output status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     SET or RESET
+*/
+FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
+{
+    if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      get GPIO all pins output status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[out] none
+    \retval     state of GPIO all pins
+*/
+uint16_t gpio_output_port_get(uint32_t gpio_periph)
+{
+    return (uint16_t)GPIO_OCTL(gpio_periph);
+}
+
+/*!
+    \brief      set GPIO alternate function
+    \param[in]  gpio_periph: GPIOx(x = A,B,C) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C) 
+    \param[in]  alt_func_num: GPIO pin af function, please refer to specific device datasheet
+      \arg        GPIO_AF_0: TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0,
+                              I2C0, I2C1, SWDIO, SWCLK
+      \arg        GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1
+      \arg        GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0
+      \arg        GPIO_AF_3: I2C0, TIMER14
+      \arg        GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13
+      \arg        GPIO_AF_5(port A,B only): TIMER15, TIMER16, I2S0
+      \arg        GPIO_AF_6(port A,B only): SPI1
+      \arg        GPIO_AF_7(port A,B only): CMP
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
+{
+    uint16_t i;
+    uint32_t afrl, afrh;
+
+    afrl = GPIO_AFSEL0(gpio_periph);
+    afrh = GPIO_AFSEL1(gpio_periph);
+
+    for(i = 0U;i < 8U;i++){
+        if((1U << i) & pin){
+            /* clear the specified pin alternate function bits */
+            afrl &= ~GPIO_AFR_MASK(i);
+            afrl |= GPIO_AFR_SET(i,alt_func_num);
+        }
+    }
+
+    for(i = 8U;i < 16U;i++){
+        if((1U << i) & pin){
+            /* clear the specified pin alternate function bits */
+            afrh &= ~GPIO_AFR_MASK(i - 8U);
+            afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);
+        }
+    }
+
+    GPIO_AFSEL0(gpio_periph) = afrl;
+    GPIO_AFSEL1(gpio_periph) = afrh;
+}
+
+/*!
+    \brief      lock GPIO pin bit
+    \param[in]  gpio_periph: GPIOx(x = A,B) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B) 
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
+{
+    uint32_t lock = 0x00010000U;
+    lock |= pin;
+
+    /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */
+    GPIO_LOCK(gpio_periph) = (uint32_t)lock;
+    GPIO_LOCK(gpio_periph) = (uint32_t)pin;
+    GPIO_LOCK(gpio_periph) = (uint32_t)lock;
+    lock = GPIO_LOCK(gpio_periph);
+    lock = GPIO_LOCK(gpio_periph);
+}
+
+/*!
+    \brief      toggle GPIO pin status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F) 
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin)
+{
+    GPIO_TG(gpio_periph) = (uint32_t)pin;
+}
+
+/*!
+    \brief      toggle GPIO port status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,F)
+                only one parameter can be selected which is shown as below:
+      \arg        GPIOx(x = A,B,C,F) 
+    \param[out] none
+    \retval     none
+*/
+void gpio_port_toggle(uint32_t gpio_periph)
+{
+    GPIO_TG(gpio_periph) = 0x0000FFFFU;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_i2c.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_i2c.c
new file mode 100644
index 0000000000..89fb7f52e9
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_i2c.c
@@ -0,0 +1,797 @@
+/*!
+    \file    gd32e230_i2c.c
+    \brief   I2C driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_i2c.h"
+
+/* I2C register bit mask */
+#define I2CCLK_MAX                    ((uint32_t)0x0000007FU)             /*!< i2cclk maximum value */
+#define I2CCLK_MIN                    ((uint32_t)0x00000002U)             /*!< i2cclk minimum value */
+#define I2C_FLAG_MASK                 ((uint32_t)0x0000FFFFU)             /*!< i2c flag mask */
+#define I2C_ADDRESS_MASK              ((uint32_t)0x000003FFU)             /*!< i2c address mask */
+#define I2C_ADDRESS2_MASK             ((uint32_t)0x000000FEU)             /*!< the second i2c address mask */
+
+/* I2C register bit offset */
+#define STAT1_PECV_OFFSET             ((uint32_t)8U)     /* bit offset of PECV in I2C_STAT1 */
+
+/*!
+    \brief      reset I2C
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void i2c_deinit(uint32_t i2c_periph)
+{
+    switch(i2c_periph){
+    case I2C0:
+        /* reset I2C0 */
+        rcu_periph_reset_enable(RCU_I2C0RST);
+        rcu_periph_reset_disable(RCU_I2C0RST);
+        break;
+    case I2C1:
+        /* reset I2C1 */
+        rcu_periph_reset_enable(RCU_I2C1RST);
+        rcu_periph_reset_disable(RCU_I2C1RST);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure I2C clock
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
+                          and fast mode plus (up to 1MHz)
+    \param[in]  dutycyc: duty cycle in fast mode or fast mode plus
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_DTCY_2: T_low/T_high=2 
+      \arg        I2C_DTCY_16_9: T_low/T_high=16/9
+    \param[out] none
+    \retval     none
+*/
+void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
+{
+    uint32_t pclk1, clkc, freq, risetime;
+    uint32_t temp;
+    
+    pclk1 = rcu_clock_freq_get(CK_APB1);
+    /* I2C peripheral clock frequency */
+    freq = (uint32_t)(pclk1/1000000U);
+    if(freq >= I2CCLK_MAX){
+        freq = I2CCLK_MAX;
+    }
+    temp = I2C_CTL1(i2c_periph);
+    temp &= ~I2C_CTL1_I2CCLK;
+    temp |= freq;
+    
+    I2C_CTL1(i2c_periph) = temp;
+    
+    if(100000U >= clkspeed){
+        /* the maximum SCL rise time is 1000ns in standard mode */
+        risetime = (uint32_t)((pclk1/1000000U)+1U);
+        if(risetime >= I2CCLK_MAX){
+            I2C_RT(i2c_periph) = I2CCLK_MAX;
+        }else if(risetime <= I2CCLK_MIN){
+            I2C_RT(i2c_periph) = I2CCLK_MIN;
+        }else{
+            I2C_RT(i2c_periph) = risetime;
+        }
+        clkc = (uint32_t)(pclk1/(clkspeed*2U)); 
+        if(clkc < 0x04U){
+            /* the CLKC in standard mode minmum value is 4 */
+            clkc = 0x04U;
+        }
+        I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
+
+    }else if(400000U >= clkspeed){
+        /* the maximum SCL rise time is 300ns in fast mode */
+        I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
+        if(I2C_DTCY_2 == dutycyc){
+            /* I2C duty cycle is 2 */
+            clkc = (uint32_t)(pclk1/(clkspeed*3U));
+            I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
+        }else{
+            /* I2C duty cycle is 16/9 */
+            clkc = (uint32_t)(pclk1/(clkspeed*25U));
+            I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
+        }
+        if(0U == (clkc & I2C_CKCFG_CLKC)){
+            /* the CLKC in fast mode minmum value is 1 */
+            clkc |= 0x0001U;  
+        }
+        I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
+        I2C_CKCFG(i2c_periph) |= clkc;
+    }else{
+        /* fast mode plus, the maximum SCL rise time is 120ns */
+        I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U);
+        if(I2C_DTCY_2 == dutycyc){
+            /* I2C duty cycle is 2 */
+            clkc = (uint32_t)(pclk1/(clkspeed*3U));
+            I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
+        }else{
+            /* I2C duty cycle is 16/9 */
+            clkc = (uint32_t)(pclk1/(clkspeed*25U));
+            I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
+        }
+        /* enable fast mode */
+        I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
+        I2C_CKCFG(i2c_periph) |= clkc;
+        /* enable I2C fast mode plus */
+        I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN;
+    }
+}
+
+/*!
+    \brief      configure I2C address 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  mode:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_I2CMODE_ENABLE: I2C mode
+      \arg        I2C_SMBUSMODE_ENABLE: SMBus mode
+    \param[in]  addformat: 7bits or 10bits
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_ADDFORMAT_7BITS: 7bits
+      \arg        I2C_ADDFORMAT_10BITS: 10bits
+    \param[in]  addr: I2C address
+    \param[out] none
+    \retval     none
+*/
+void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
+{
+    /* SMBus/I2C mode selected */
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_SMBEN); 
+    ctl |= mode;
+    I2C_CTL0(i2c_periph) = ctl;
+    /* configure address */
+    addr = addr & I2C_ADDRESS_MASK;
+    I2C_SADDR0(i2c_periph) = (addformat | addr);
+}
+
+/*!
+    \brief      SMBus type selection
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  type:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_SMBUS_DEVICE: device
+      \arg        I2C_SMBUS_HOST: host
+    \param[out] none
+    \retval     none
+*/
+void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
+{
+    if(I2C_SMBUS_HOST == type){
+        I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
+    }else{
+        I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
+    }
+}
+
+/*!
+    \brief      whether or not to send an ACK
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  ack:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_ACK_ENABLE: ACK will be sent
+      \arg        I2C_ACK_DISABLE: ACK will not be sent
+    \param[out] none
+    \retval     none
+*/
+void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
+{
+    if(I2C_ACK_ENABLE == ack){
+        I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
+    }else{
+        I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
+    }
+}
+
+/*!
+    \brief      configure I2C POAP position
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  pos:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
+      \arg        I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
+    \param[out] none
+    \retval     none
+*/
+void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
+{
+    /* configure I2C POAP position */
+    if(I2C_ACKPOS_NEXT == pos){
+        I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
+    }else{
+        I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
+    }
+}
+
+/*!
+    \brief      master sends slave address
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  addr: slave address  
+    \param[in]  trandirection: transmitter or receiver
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_TRANSMITTER: transmitter  
+      \arg        I2C_RECEIVER:    receiver  
+    \param[out] none
+    \retval     none
+*/
+void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
+{
+    /* master is a transmitter or a receiver */
+    if(I2C_TRANSMITTER == trandirection){
+        addr = addr & I2C_TRANSMITTER;
+    }else{
+        addr = addr | I2C_RECEIVER;
+    }
+    /* send slave address */
+    I2C_DATA(i2c_periph) = addr;
+}
+
+/*!
+    \brief      enable dual-address mode
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  addr: the second address in dual-address mode
+    \param[out] none
+    \retval     none
+*/
+void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr)
+{
+    /* configure address */
+    addr = addr & I2C_ADDRESS2_MASK;
+    I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr);
+}
+
+/*!
+    \brief      disable dual-address mode
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
+    \param[out] none
+    \retval     none
+*/
+void i2c_dualaddr_disable(uint32_t i2c_periph)
+{
+    I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
+}
+
+/*!
+    \brief      enable I2C
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
+    \param[out] none
+    \retval     none
+*/
+void i2c_enable(uint32_t i2c_periph)
+{
+    I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
+}
+
+/*!
+    \brief      disable I2C
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
+    \param[out] none
+    \retval     none
+*/
+void i2c_disable(uint32_t i2c_periph)
+{
+    I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
+}
+
+/*!
+    \brief      generate a START condition on I2C bus
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void i2c_start_on_bus(uint32_t i2c_periph)
+{
+    I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
+}
+
+/*!
+    \brief      generate a STOP condition on I2C bus
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void i2c_stop_on_bus(uint32_t i2c_periph)
+{
+    I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
+}
+
+/*!
+    \brief      I2C transmit data function
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  data: data of transmission 
+    \param[out] none
+    \retval     none
+*/
+void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
+{
+    I2C_DATA(i2c_periph) = DATA_TRANS(data);
+}
+
+/*!
+    \brief      I2C receive data function
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     data of received
+*/
+uint8_t i2c_data_receive(uint32_t i2c_periph)
+{
+    return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
+}
+
+/*!
+    \brief      enable I2C DMA mode 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  dmastate:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_DMA_ON: DMA mode enable
+      \arg        I2C_DMA_OFF: DMA mode disable
+    \param[out] none
+    \retval     none
+*/
+void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
+{
+    /* configure I2C DMA function */
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL1(i2c_periph);
+    ctl &= ~(I2C_CTL1_DMAON); 
+    ctl |= dmastate;
+    I2C_CTL1(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      configure whether next DMA EOT is DMA last transfer or not
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  dmalast:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_DMALST_ON: next DMA EOT is the last transfer
+      \arg        I2C_DMALST_OFF: next DMA EOT is not the last transfer
+    \param[out] none
+    \retval     none
+*/
+void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast)
+{
+    /* configure DMA last transfer */
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL1(i2c_periph);
+    ctl &= ~(I2C_CTL1_DMALST); 
+    ctl |= dmalast;
+    I2C_CTL1(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      whether to stretch SCL low when data is not ready in slave mode 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  stretchpara:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
+      \arg        I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
+    \param[out] none
+    \retval     none
+*/
+void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
+{
+    /* configure I2C SCL strerching enable or disable */
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_SS); 
+    ctl |= stretchpara;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      whether or not to response to a general call 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  gcallpara:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_GCEN_ENABLE: slave will response to a general call
+      \arg        I2C_GCEN_DISABLE: slave will not response to a general call
+    \param[out] none
+    \retval     none
+*/
+void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
+{
+    /* configure slave response to a general call enable or disable */
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_GCEN); 
+    ctl |= gcallpara;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      software reset I2C 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  sreset:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_SRESET_SET: I2C is under reset
+      \arg        I2C_SRESET_RESET: I2C is not under reset
+    \param[out] none
+    \retval     none
+*/
+void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
+{
+    /* modify CTL0 and configure software reset I2C state */
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_SRESET); 
+    ctl |= sreset;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      I2C PEC calculation on or off
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  pecpara:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_PEC_ENABLE: PEC calculation on 
+      \arg        I2C_PEC_DISABLE: PEC calculation off 
+    \param[out] none
+    \retval     none
+*/
+void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
+{
+    /* on/off PEC calculation */
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_PECEN);
+    ctl |= pecstate;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      I2C whether to transfer PEC value
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  pecpara:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_PECTRANS_ENABLE: transfer PEC 
+      \arg        I2C_PECTRANS_DISABLE: not transfer PEC 
+    \param[out] none
+    \retval     none
+*/
+void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
+{
+    /* whether to transfer PEC */
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_PECTRANS);
+    ctl |= pecpara;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      get packet error checking value 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     PEC value
+*/
+uint8_t i2c_pec_value_get(uint32_t i2c_periph)
+{
+    return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET);
+}
+
+/*!
+    \brief      I2C issue alert through SMBA pin 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  smbuspara:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_SALTSEND_ENABLE: issue alert through SMBA pin 
+      \arg        I2C_SALTSEND_DISABLE: not issue alert through SMBA pin 
+    \param[out] none
+    \retval     none
+*/
+void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
+{
+    /* issue alert through SMBA pin configure*/
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_SALT);
+    ctl |= smbuspara;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      enable or disable I2C ARP protocol in SMBus switch
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  smbuspara:
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_ARP_ENABLE: enable ARP
+      \arg        I2C_ARP_DISABLE: disable ARP
+    \param[out] none
+    \retval     none
+*/
+void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
+{
+    /* enable or disable I2C ARP protocol*/
+    uint32_t ctl = 0U;
+    
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_ARPEN);
+    ctl |= arpstate;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      enable SAM_V interface
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void i2c_sam_enable(uint32_t i2c_periph)
+{
+    I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN;
+}
+
+/*!
+    \brief      disable SAM_V interface
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void i2c_sam_disable(uint32_t i2c_periph)
+{
+    I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN);
+}
+
+/*!
+    \brief      enable SAM_V interface timeout detect
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void i2c_sam_timeout_enable(uint32_t i2c_periph)
+{
+    I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN;
+}
+
+/*!
+    \brief      disable SAM_V interface timeout detect
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void i2c_sam_timeout_disable(uint32_t i2c_periph)
+{
+    I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN);
+}
+
+/*!
+    \brief      check I2C flag is set or not
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  flag: I2C flags, refer to i2c_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_FLAG_SBSEND: start condition send out 
+      \arg        I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
+      \arg        I2C_FLAG_BTC: byte transmission finishes
+      \arg        I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
+      \arg        I2C_FLAG_STPDET: stop condition detected in slave mode
+      \arg        I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
+      \arg        I2C_FLAG_TBE: I2C_DATA is empty during transmitting
+      \arg        I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
+      \arg        I2C_FLAG_LOSTARB: arbitration lost in master mode
+      \arg        I2C_FLAG_AERR: acknowledge error
+      \arg        I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
+      \arg        I2C_FLAG_PECERR: PEC error when receiving data
+      \arg        I2C_FLAG_SMBTO: timeout signal in SMBus mode
+      \arg        I2C_FLAG_SMBALT: SMBus alert status
+      \arg        I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
+      \arg        I2C_FLAG_I2CBSY: busy flag
+      \arg        I2C_FLAG_TR: whether the I2C is a transmitter or a receiver
+      \arg        I2C_FLAG_RXGC: general call address (00h) received
+      \arg        I2C_FLAG_DEFSMB: default address of SMBus device
+      \arg        I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
+      \arg        I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode
+      \arg        I2C_FLAG_TFF: txframe fall flag
+      \arg        I2C_FLAG_TFR: txframe rise flag
+      \arg        I2C_FLAG_RFF: rxframe fall flag
+      \arg        I2C_FLAG_RFR: rxframe rise flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
+{
+    if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear I2C flag
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  flag: I2C flags, refer to i2c_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg       I2C_FLAG_SMBALT: SMBus Alert status
+      \arg       I2C_FLAG_SMBTO: timeout signal in SMBus mode
+      \arg       I2C_FLAG_PECERR: PEC error when receiving data
+      \arg       I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode    
+      \arg       I2C_FLAG_AERR: acknowledge error
+      \arg       I2C_FLAG_LOSTARB: arbitration lost in master mode   
+      \arg       I2C_FLAG_BERR: a bus error   
+      \arg       I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
+      \arg       I2C_FLAG_TFF: txframe fall flag
+      \arg       I2C_FLAG_TFR: txframe rise flag
+      \arg       I2C_FLAG_RFF: rxframe fall flag
+      \arg       I2C_FLAG_RFR: rxframe rise flag
+    \param[out] none
+    \retval     none
+*/
+void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag)
+{
+    if(I2C_FLAG_ADDSEND == flag){
+        /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
+        I2C_STAT0(i2c_periph);
+        I2C_STAT1(i2c_periph);
+    }else{
+        I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag));
+    }
+}
+
+/*!
+    \brief      enable I2C interrupt
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  interrupt: I2C interrupts, refer to i2c_interrupt_enum
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_INT_ERR: error interrupt enable 
+      \arg        I2C_INT_EV: event interrupt enable 
+      \arg        I2C_INT_BUF: buffer interrupt enable
+      \arg        I2C_INT_TFF: txframe fall interrupt enable
+      \arg        I2C_INT_TFR: txframe rise interrupt enable
+      \arg        I2C_INT_RFF: rxframe fall interrupt enable
+      \arg        I2C_INT_RFR: rxframe rise interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
+{
+    I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt));
+}
+
+/*!
+    \brief      disable I2C interrupt
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  interrupt: I2C interrupts, refer to i2c_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_INT_ERR: error interrupt enable 
+      \arg        I2C_INT_EV: event interrupt enable 
+      \arg        I2C_INT_BUF: buffer interrupt enable
+      \arg        I2C_INT_TFF: txframe fall interrupt enable
+      \arg        I2C_INT_TFR: txframe rise interrupt enable
+      \arg        I2C_INT_RFF: rxframe fall interrupt enable
+      \arg        I2C_INT_RFR: rxframe rise interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
+{
+    I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt));
+}
+
+/*!
+    \brief      check I2C interrupt flag
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
+      \arg        I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
+      \arg        I2C_INT_FLAG_BTC: byte transmission finishes
+      \arg        I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
+      \arg        I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
+      \arg        I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
+      \arg        I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
+      \arg        I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
+      \arg        I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
+      \arg        I2C_INT_FLAG_AERR: acknowledge error interrupt flag
+      \arg        I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
+      \arg        I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
+      \arg        I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
+      \arg        I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
+      \arg        I2C_INT_FLAG_TFF: txframe fall interrupt flag
+      \arg        I2C_INT_FLAG_TFR: txframe rise interrupt flag
+      \arg        I2C_INT_FLAG_RFF: rxframe fall interrupt flag
+      \arg        I2C_INT_FLAG_RFR: rxframe rise interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
+{
+    uint32_t intenable = 0U, flagstatus = 0U, bufie;
+    
+    /* check BUFIE */
+    bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
+    
+    /* get the interrupt enable bit status */
+    intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
+    /* get the corresponding flag bit status */
+    flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag)));
+
+    if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){
+        if(intenable && bufie){
+            intenable = 1U;
+        }else{
+            intenable = 0U;
+        }
+    }
+    if((0U != flagstatus) && (0U != intenable)){
+        return SET;
+    }else{
+        return RESET; 
+    }
+}
+
+/*!
+    \brief      clear I2C interrupt flag
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
+      \arg        I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
+      \arg        I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
+      \arg        I2C_INT_FLAG_AERR: acknowledge error interrupt flag
+      \arg        I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
+      \arg        I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
+      \arg        I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
+      \arg        I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
+      \arg        I2C_INT_FLAG_TFF: txframe fall interrupt flag
+      \arg        I2C_INT_FLAG_TFR: txframe rise interrupt flag
+      \arg        I2C_INT_FLAG_RFF: rxframe fall interrupt flag
+      \arg        I2C_INT_FLAG_RFR: rxframe rise interrupt flag
+    \param[out] none
+    \retval     none
+*/
+void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
+{
+    if(I2C_INT_FLAG_ADDSEND == int_flag){
+        /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
+        I2C_STAT0(i2c_periph);
+        I2C_STAT1(i2c_periph);
+    }else{
+        I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag));
+    }
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_misc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_misc.c
new file mode 100644
index 0000000000..eac0dc0958
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_misc.c
@@ -0,0 +1,142 @@
+/*!
+    \file    gd32e230_misc.c
+    \brief   MISC driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_misc.h"
+
+/*!
+    \brief      enable NVIC request
+    \param[in]  nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
+    \param[in]  nvic_irq_priority: the priority needed to set (0-3)
+    \param[out] none
+    \retval     none
+*/
+void nvic_irq_enable(uint8_t nvic_irq, 
+                     uint8_t nvic_irq_priority)
+{
+    /* set the priority and enable the selected IRQ */
+    NVIC_SetPriority((IRQn_Type)nvic_irq, (uint32_t)nvic_irq_priority);
+    NVIC_EnableIRQ((IRQn_Type)nvic_irq);
+}
+
+/*!
+    \brief      disable NVIC request
+    \param[in]  nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
+    \param[out] none
+    \retval     none
+*/
+void nvic_irq_disable(uint8_t nvic_irq)
+{
+    /* disable the selected IRQ.*/
+    NVIC_DisableIRQ((IRQn_Type)nvic_irq);
+}
+
+/*  */
+/*!
+    \brief      initiates a system reset request to reset the MCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_system_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+/*!
+    \brief      set the NVIC vector table base address
+    \param[in]  nvic_vict_tab: the RAM or FLASH base address
+      \arg        NVIC_VECTTAB_RAM: RAM base address
+      \arg        NVIC_VECTTAB_FLASH: Flash base address
+    \param[in]  offset: Vector Table offset
+    \param[out] none
+    \retval     none
+*/
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
+{
+    SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
+}
+
+/*!
+    \brief      set the state of the low power mode
+    \param[in]  lowpower_mode: the low power mode state
+      \arg        SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power 
+                    mode by exiting from ISR
+      \arg        SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
+      \arg        SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up 
+                    by all the enable and disable interrupts
+    \param[out] none
+    \retval     none
+*/
+void system_lowpower_set(uint8_t lowpower_mode)
+{
+    SCB->SCR |= (uint32_t)lowpower_mode;
+}
+
+/*!
+    \brief      reset the state of the low power mode
+    \param[in]  lowpower_mode: the low power mode state
+      \arg        SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power 
+                    mode by exiting from ISR
+      \arg        SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
+      \arg        SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be 
+                    woke up by the enable interrupts
+    \param[out] none
+    \retval     none
+*/
+void system_lowpower_reset(uint8_t lowpower_mode)
+{
+    SCB->SCR &= (~(uint32_t)lowpower_mode);
+}
+
+/*!
+    \brief      set the systick clock source
+    \param[in]  systick_clksource: the systick clock source needed to choose
+      \arg        SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
+      \arg        SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
+    \param[out] none
+    \retval     none
+*/
+
+void systick_clksource_set(uint32_t systick_clksource)
+{
+    if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
+        /* set the systick clock source from HCLK */
+        SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+    }else{
+        /* set the systick clock source from HCLK/8 */
+        SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
+    }
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_pmu.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_pmu.c
new file mode 100644
index 0000000000..53e8a2e521
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_pmu.c
@@ -0,0 +1,301 @@
+/*!
+    \file    gd32e230_pmu.c
+    \brief   PMU driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_pmu.h"
+
+/*!
+    \brief      reset PMU register
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_deinit(void)
+{
+    /* reset PMU */
+    rcu_periph_reset_enable(RCU_PMURST);
+    rcu_periph_reset_disable(RCU_PMURST);
+}
+
+/*!
+    \brief      select low voltage detector threshold
+    \param[in]  lvdt_n:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_LVDT_0: voltage threshold is 2.1V
+      \arg        PMU_LVDT_1: voltage threshold is 2.3V
+      \arg        PMU_LVDT_2: voltage threshold is 2.4V
+      \arg        PMU_LVDT_3: voltage threshold is 2.6V
+      \arg        PMU_LVDT_4: voltage threshold is 2.7V
+      \arg        PMU_LVDT_5: voltage threshold is 2.9V
+      \arg        PMU_LVDT_6: voltage threshold is 3.0V
+      \arg        PMU_LVDT_7: voltage threshold is 3.1V
+    \param[out] none
+    \retval     none
+*/
+void pmu_lvd_select(uint32_t lvdt_n)
+{
+    /* disable LVD */
+    PMU_CTL &= ~PMU_CTL_LVDEN;
+    /* clear LVDT bits */
+    PMU_CTL &= ~PMU_CTL_LVDT;
+    /* set LVDT bits according to lvdt_n */
+    PMU_CTL |= lvdt_n;
+    /* enable LVD */
+    PMU_CTL |= PMU_CTL_LVDEN;
+}
+
+/*!
+    \brief      select LDO output voltage
+                these bits set by software when the main PLL closed
+    \param[in]  ldo_output:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_LDOVS_LOW: LDO output voltage low mode
+      \arg        PMU_LDOVS_HIGH: LDO output voltage high mode
+    \param[out] none
+    \retval     none
+*/
+void pmu_ldo_output_select(uint32_t ldo_output)
+{
+    PMU_CTL &= ~PMU_CTL_LDOVS;
+    PMU_CTL |= ldo_output;
+}
+
+/*!
+    \brief      disable PMU lvd
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_lvd_disable(void)
+{
+    /* disable LVD */
+    PMU_CTL &= ~PMU_CTL_LVDEN;
+}
+
+/*!
+    \brief      PMU work at sleep mode
+    \param[in]  sleepmodecmd:
+                only one parameter can be selected which is shown as below:
+      \arg        WFI_CMD: use WFI command
+      \arg        WFE_CMD: use WFE command
+    \param[out] none
+    \retval     none
+*/
+void pmu_to_sleepmode(uint8_t sleepmodecmd)
+{
+    /* clear sleepdeep bit of Cortex-M23 system control register */
+    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+    
+    /* select WFI or WFE command to enter sleep mode */
+    if(WFI_CMD == sleepmodecmd){
+        __WFI();
+    }else{
+        __WFE();
+    }
+}
+
+/*!
+    \brief      PMU work at deepsleep mode
+    \param[in]  ldo:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode
+      \arg        PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
+    \param[in]  deepsleepmodecmd:
+                only one parameter can be selected which is shown as below:
+      \arg        WFI_CMD: use WFI command
+      \arg        WFE_CMD: use WFE command
+    \param[out] none
+    \retval     none
+*/
+void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
+{
+    static uint32_t reg_snap[ 3 ];  
+    /* clear stbmod and ldolp bits */
+    PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
+    
+    /* set ldolp bit according to pmu_ldo */
+    PMU_CTL |= ldo;
+    
+    /* set sleepdeep bit of Cortex-M23 system control register */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    reg_snap[ 0 ] = REG32( 0xE000E010U );
+    reg_snap[ 1 ] = REG32( 0xE000E100U );
+    reg_snap[ 2 ] = REG32( 0xE000E104U );
+    
+    REG32( 0xE000E010U ) &= 0x00010004U;
+    REG32( 0xE000E180U )  = 0XF7FFEF19U;
+    REG32( 0xE000E184U )  = 0XFFFFFFFFU;
+  
+    /* select WFI or WFE command to enter deepsleep mode */
+    if(WFI_CMD == deepsleepmodecmd){
+        __WFI();
+    }else{
+        __SEV();
+        __WFE();
+        __WFE();
+    }
+
+    REG32( 0xE000E010U ) = reg_snap[ 0 ] ; 
+    REG32( 0xE000E100U ) = reg_snap[ 1 ] ;
+    REG32( 0xE000E104U ) = reg_snap[ 2 ] ;
+    
+    /* reset sleepdeep bit of Cortex-M23 system control register */
+    SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/*!
+    \brief      pmu work at standby mode
+    \param[in]  standbymodecmd:
+                only one parameter can be selected which is shown as below:
+      \arg        WFI_CMD: use WFI command
+      \arg        WFE_CMD: use WFE command
+    \param[out] none
+    \retval     none
+*/
+void pmu_to_standbymode(uint8_t standbymodecmd)
+{
+    /* set sleepdeep bit of Cortex-M23 system control register */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* set stbmod bit */
+    PMU_CTL |= PMU_CTL_STBMOD;
+        
+    /* reset wakeup flag */
+    PMU_CTL |= PMU_CTL_WURST;
+    
+    /* select WFI or WFE command to enter standby mode */
+    if(WFI_CMD == standbymodecmd){
+        __WFI();
+    }else{
+        __WFE();
+    }
+}
+
+/*!
+    \brief      enable wakeup pin
+    \param[in]  wakeup_pin:
+                one or more parameters can be selected which are shown as below:
+      \arg        PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) 
+      \arg        PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) 
+      \arg        PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) 
+      \arg        PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) 
+    \param[out] none
+    \retval     none
+*/
+void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
+{
+    PMU_CS |= wakeup_pin;
+}
+
+/*!
+    \brief      disable wakeup pin
+    \param[in]  wakeup_pin:
+                one or more parameters can be selected which are shown as below:
+      \arg        PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) 
+      \arg        PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) 
+      \arg        PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) 
+      \arg        PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
+    \param[out] none
+    \retval     none
+*/
+void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
+{
+    PMU_CS &= ~(wakeup_pin);
+}
+
+/*!
+    \brief      enable backup domain write
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_backup_write_enable(void)
+{
+    PMU_CTL |= PMU_CTL_BKPWEN;
+}
+
+/*!
+    \brief      disable backup domain write
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_backup_write_disable(void)
+{
+    PMU_CTL &= ~PMU_CTL_BKPWEN;
+}
+
+/*!
+    \brief      clear flag bit
+    \param[in]  flag_clear:
+                one or more parameters can be selected which are shown as below:
+      \arg        PMU_FLAG_RESET_WAKEUP: reset wakeup flag
+      \arg        PMU_FLAG_RESET_STANDBY: reset standby flag
+    \param[out] none
+    \retval     none
+*/
+void pmu_flag_clear(uint32_t flag_clear)
+{
+    if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){
+        /* reset wakeup flag */
+        PMU_CTL |= PMU_CTL_WURST;
+    }
+    if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){
+        /* reset standby flag */
+        PMU_CTL |= PMU_CTL_STBRST;
+    }
+}
+
+/*!
+    \brief      get flag state
+    \param[in]  flag:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_FLAG_WAKEUP: wakeup flag
+      \arg        PMU_FLAG_STANDBY: standby flag
+      \arg        PMU_FLAG_LVD: lvd flag
+    \param[out] none
+    \retval     FlagStatus SET or RESET
+*/
+FlagStatus pmu_flag_get(uint32_t flag)
+{
+    FlagStatus ret_status = RESET;
+    
+    if(PMU_CS & flag){
+        ret_status = SET;
+    }
+    
+    return ret_status;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rcu.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rcu.c
new file mode 100644
index 0000000000..9483fa68f9
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rcu.c
@@ -0,0 +1,1034 @@
+/*!
+    \file    gd32e230_rcu.c
+    \brief   RCU driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_rcu.h"
+
+/* define clock source */
+#define SEL_IRC8M       0x00U
+#define SEL_HXTAL       0x01U
+#define SEL_PLL         0x02U
+
+/* define startup timeout count */
+#define OSC_STARTUP_TIMEOUT         ((uint32_t)0x000FFFFFU)
+#define LXTAL_STARTUP_TIMEOUT       ((uint32_t)0x03FFFFFFU)
+
+/*!
+    \brief      deinitialize the RCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_deinit(void)
+{
+    /* enable IRC8M */
+    RCU_CTL0 |= RCU_CTL0_IRC8MEN;
+    while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
+    }
+    /* reset RCU */
+    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
+                  RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
+    RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
+    RCU_CFG1 &= ~(RCU_CFG1_PREDV);
+    RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
+    RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
+    RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
+    RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
+    RCU_INT = 0x00000000U;
+}
+
+/*!
+    \brief      enable the peripherals clock
+    \param[in]  periph: RCU peripherals, refer to rcu_periph_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_GPIOx (x=A,B,C,F): GPIO ports clock
+      \arg        RCU_DMA: DMA clock
+      \arg        RCU_CRC: CRC clock
+      \arg        RCU_CFGCMP: CFGCMP clock
+      \arg        RCU_ADC: ADC clock
+      \arg        RCU_TIMERx (x=0,2,5,13,14,15,16): TIMER clock
+      \arg        RCU_SPIx (x=0,1): SPI clock
+      \arg        RCU_USARTx (x=0,1): USART clock
+      \arg        RCU_WWDGT: WWDGT clock
+      \arg        RCU_I2Cx (x=0,1): I2C clock
+      \arg        RCU_PMU: PMU clock
+      \arg        RCU_RTC: RTC clock
+      \arg        RCU_DBGMCU: DBGMCU clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_clock_enable(rcu_periph_enum periph)
+{
+    RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+    \brief      disable the peripherals clock
+    \param[in]  periph: RCU peripherals, refer to rcu_periph_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_GPIOx (x=A,B,C,F): GPIO ports clock
+      \arg        RCU_DMA: DMA clock
+      \arg        RCU_CRC: CRC clock
+      \arg        RCU_CFGCMP: CFGCMP clock
+      \arg        RCU_ADC: ADC clock
+      \arg        RCU_TIMERx (x=0,2,5,13,14,15,16): TIMER clock
+      \arg        RCU_SPIx (x=0,1): SPI clock
+      \arg        RCU_USARTx (x=0,1): USART clock
+      \arg        RCU_WWDGT: WWDGT clock
+      \arg        RCU_I2Cx (x=0,1): I2C clock
+      \arg        RCU_PMU: PMU clock
+      \arg        RCU_RTC: RTC clock
+      \arg        RCU_DBGMCU: DBGMCU clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_clock_disable(rcu_periph_enum periph)
+{
+    RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+    \brief      enable the peripherals clock when sleep mode
+    \param[in]  periph: RCU peripherals, refer to rcu_periph_sleep_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_FMC_SLP: FMC clock
+      \arg        RCU_SRAM_SLP: SRAM clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
+{
+    RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+    \brief      disable the peripherals clock when sleep mode
+    \param[in]  periph: RCU peripherals, refer to rcu_periph_sleep_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_FMC_SLP: FMC clock
+      \arg        RCU_SRAM_SLP: SRAM clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
+{
+    RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
+}
+/*!
+    \brief      reset the peripherals
+    \param[in]  periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_GPIOxRST (x=A,B,C,F): reset GPIO ports
+      \arg        RCU_CFGCMPRST: reset CFGCMP
+      \arg        RCU_ADCRST: reset ADC
+      \arg        RCU_TIMERxRST (x=0,2,5,13,14,15,16): reset TIMER
+      \arg        RCU_SPIxRST (x=0,1): reset SPI
+      \arg        RCU_USARTxRST (x=0,1): reset USART
+      \arg        RCU_WWDGTRST: reset WWDGT
+      \arg        RCU_I2CxRST (x=0,1): reset I2C
+      \arg        RCU_PMURST: reset PMU
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
+{
+    RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
+}
+
+/*!
+    \brief      disable reset the peripheral
+    \param[in]  periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_GPIOxRST (x=A,B,C,F): reset GPIO ports
+      \arg        RCU_CFGCMPRST: reset CFGCMP
+      \arg        RCU_ADCRST: reset ADC
+      \arg        RCU_TIMERxRST (x=0,2,5,13,14,15,16): reset TIMER
+      \arg        RCU_SPIxRST (x=0,1): reset SPI
+      \arg        RCU_USARTxRST (x=0,1): reset USART
+      \arg        RCU_WWDGTRST: reset WWDGT
+      \arg        RCU_I2CxRST (x=0,1): reset I2C
+      \arg        RCU_PMURST: reset PMU
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
+{
+    RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
+}
+
+/*!
+    \brief      reset the BKP
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_bkp_reset_enable(void)
+{
+    RCU_BDCTL |= RCU_BDCTL_BKPRST;
+}
+
+/*!
+    \brief      disable the BKP reset
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_bkp_reset_disable(void)
+{
+    RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
+}
+
+/*!
+    \brief      configure the system clock source
+    \param[in]  ck_sys: system clock source select
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
+      \arg        RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
+      \arg        RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
+    \param[out] none
+    \retval     none
+*/
+void rcu_system_clock_source_config(uint32_t ck_sys)
+{
+    uint32_t cksys_source = 0U;
+    cksys_source = RCU_CFG0;
+    /* reset the SCS bits and set according to ck_sys */
+    cksys_source &= ~RCU_CFG0_SCS;
+    RCU_CFG0 = (ck_sys | cksys_source);
+}
+
+/*!
+    \brief      get the system clock source
+    \param[in]  none
+    \param[out] none
+    \retval     which clock is selected as CK_SYS source
+      \arg        RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source
+      \arg        RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source
+      \arg        RCU_SCSS_PLL: select CK_PLL as the CK_SYS source
+*/
+uint32_t rcu_system_clock_source_get(void)
+{
+    return (RCU_CFG0 & RCU_CFG0_SCSS);
+}
+
+/*!
+    \brief      configure the AHB clock prescaler selection
+    \param[in]  ck_ahb: AHB clock prescaler selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
+    \param[out] none
+    \retval     none
+*/
+void rcu_ahb_clock_config(uint32_t ck_ahb)
+{
+    uint32_t ahbpsc = 0U;
+    ahbpsc = RCU_CFG0;
+    /* reset the AHBPSC bits and set according to ck_ahb */
+    ahbpsc &= ~RCU_CFG0_AHBPSC;
+    RCU_CFG0 = (ck_ahb | ahbpsc);
+}
+
+/*!
+    \brief      configure the APB1 clock prescaler selection
+    \param[in]  ck_apb1: APB1 clock prescaler selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
+      \arg        RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
+      \arg        RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
+      \arg        RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
+      \arg        RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
+    \param[out] none
+    \retval     none
+*/
+void rcu_apb1_clock_config(uint32_t ck_apb1)
+{
+    uint32_t apb1psc = 0U;
+    apb1psc = RCU_CFG0;
+    /* reset the APB1PSC and set according to ck_apb1 */
+    apb1psc &= ~RCU_CFG0_APB1PSC;
+    RCU_CFG0 = (ck_apb1 | apb1psc);
+}
+
+/*!
+    \brief      configure the APB2 clock prescaler selection
+    \param[in]  ck_apb2: APB2 clock prescaler selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
+      \arg        RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
+      \arg        RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
+      \arg        RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
+      \arg        RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
+    \param[out] none
+    \retval     none
+*/
+void rcu_apb2_clock_config(uint32_t ck_apb2)
+{
+    uint32_t apb2psc = 0U;
+    apb2psc = RCU_CFG0;
+    /* reset the APB2PSC and set according to ck_apb2 */
+    apb2psc &= ~RCU_CFG0_APB2PSC;
+    RCU_CFG0 = (ck_apb2 | apb2psc);
+}
+
+/*!
+    \brief      configure the ADC clock prescaler selection
+    \param[in]  ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC
+      \arg        RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC
+      \arg        RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC
+      \arg        RCU_ADCCK_AHB_DIV3: select CK_AHB/3 as CK_ADC
+      \arg        RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC
+      \arg        RCU_ADCCK_AHB_DIV5: select CK_AHB/5 as CK_ADC
+      \arg        RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC
+      \arg        RCU_ADCCK_AHB_DIV7: select CK_AHB/7 as CK_ADC
+      \arg        RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC
+      \arg        RCU_ADCCK_AHB_DIV9: select CK_AHB/9 as CK_ADC
+    \param[out] none
+    \retval     none
+*/
+void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc)
+{
+    /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */
+    RCU_CFG0 &= ~RCU_CFG0_ADCPSC;
+    RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2);
+
+    /* set the ADC clock according to ck_adc */
+    switch(ck_adc){
+    case RCU_ADCCK_IRC28M_DIV2:
+        RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
+        RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_IRC28M:
+        RCU_CFG2 |= RCU_CFG2_IRC28MDIV;
+        RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_APB2_DIV2:
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_AHB_DIV3:
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
+        RCU_CFG2 |= RCU_CFG2_ADCPSC2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_APB2_DIV4:
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_AHB_DIV5: 
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
+        RCU_CFG2 |= RCU_CFG2_ADCPSC2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_APB2_DIV6: 
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_AHB_DIV7: 
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
+        RCU_CFG2 |= RCU_CFG2_ADCPSC2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_APB2_DIV8: 
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
+    case RCU_ADCCK_AHB_DIV9: 
+        RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
+        RCU_CFG2 |= RCU_CFG2_ADCPSC2;
+        RCU_CFG2 |= RCU_CFG2_ADCSEL;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure the CK_OUT clock source and divider
+    \param[in]  ckout_src: CK_OUT clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_CKOUTSRC_NONE: no clock selected
+      \arg        RCU_CKOUTSRC_IRC28M: IRC28M selected
+      \arg        RCU_CKOUTSRC_IRC40K: IRC40K selected
+      \arg        RCU_CKOUTSRC_LXTAL: LXTAL selected
+      \arg        RCU_CKOUTSRC_CKSYS: CKSYS selected
+      \arg        RCU_CKOUTSRC_IRC8M: IRC8M selected
+      \arg        RCU_CKOUTSRC_HXTAL: HXTAL selected
+      \arg        RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected
+      \arg        RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected
+    \param[in]  ckout_div: CK_OUT divider 
+      \arg        RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x
+    \param[out] none
+    \retval     none
+*/
+void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div)
+{
+    uint32_t ckout = 0U;
+    ckout = RCU_CFG0;
+    /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */
+    ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
+    RCU_CFG0 = (ckout | ckout_src | ckout_div);
+}
+
+/*!
+    \brief      configure the PLL clock source selection and PLL multiply factor
+    \param[in]  pll_src: PLL clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock
+      \arg        RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock
+    \param[in]  pll_mul: PLL multiply factor
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PLL_MULx(x=2..32): PLL source clock * x
+    \param[out] none
+    \retval     none
+*/
+void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
+{
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
+    RCU_CFG0 |= (pll_src | pll_mul);
+}
+
+/*!
+    \brief      configure the USART clock source selection
+    \param[in]  ck_usart: USART clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2
+      \arg        RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS
+      \arg        RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL
+      \arg        RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M
+    \param[out] none
+    \retval     none
+*/
+void rcu_usart_clock_config(uint32_t ck_usart)
+{
+    /* reset the USART0SEL bits and set according to ck_usart */
+    RCU_CFG2 &= ~RCU_CFG2_USART0SEL;
+    RCU_CFG2 |= ck_usart;
+}
+
+/*!
+    \brief      configure the RTC clock source selection
+    \param[in]  rtc_clock_source: RTC clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_RTCSRC_NONE: no clock selected
+      \arg        RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
+      \arg        RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
+      \arg        RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_rtc_clock_config(uint32_t rtc_clock_source)
+{
+    /* reset the RTCSRC bits and set according to rtc_clock_source */
+    RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
+    RCU_BDCTL |= rtc_clock_source;
+}
+
+/*!
+    \brief      configure the HXTAL divider used as input of PLL
+    \param[in]  hxtal_prediv: HXTAL divider used as input of PLL
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PLL_PREDVx(x=1..16): HXTAL divided x used as input of PLL
+    \param[out] none
+    \retval     none
+*/
+void rcu_hxtal_prediv_config(uint32_t hxtal_prediv)
+{
+    uint32_t prediv = 0U;
+    prediv = RCU_CFG1;
+    /* reset the PREDV bits and set according to hxtal_prediv */
+    prediv &= ~RCU_CFG1_PREDV;
+    RCU_CFG1 = (prediv | hxtal_prediv);
+}
+
+/*!
+    \brief      configure the LXTAL drive capability
+    \param[in]  lxtal_dricap: drive capability of LXTAL
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_LXTAL_LOWDRI: lower driving capability
+      \arg        RCU_LXTAL_MED_LOWDRI: medium low driving capability
+      \arg        RCU_LXTAL_MED_HIGHDRI: medium high driving capability
+      \arg        RCU_LXTAL_HIGHDRI: higher driving capability
+    \param[out] none
+    \retval     none
+*/
+void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
+{
+    /* reset the LXTALDRI bits and set according to lxtal_dricap */
+    RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI;
+    RCU_BDCTL |= lxtal_dricap;
+}
+
+/*!
+    \brief      get the clock stabilization and periphral reset flags
+    \param[in]  flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
+      \arg        RCU_FLAG_LXTALSTB: LXTAL stabilization flag
+      \arg        RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
+      \arg        RCU_FLAG_HXTALSTB: HXTAL stabilization flag
+      \arg        RCU_FLAG_PLLSTB: PLL stabilization flag
+      \arg        RCU_FLAG_IRC28MSTB: IRC28M stabilization flag
+      \arg        RCU_FLAG_V12RST: V12 domain power reset flag
+      \arg        RCU_FLAG_OBLRST: option byte loader reset flag
+      \arg        RCU_FLAG_EPRST: external pin reset flag
+      \arg        RCU_FLAG_PORRST: power reset flag
+      \arg        RCU_FLAG_SWRST: software reset flag
+      \arg        RCU_FLAG_FWDGTRST: free watchdog timer reset flag
+      \arg        RCU_FLAG_WWDGTRST: window watchdog timer reset flag
+      \arg        RCU_FLAG_LPRST: low-power reset flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus rcu_flag_get(rcu_flag_enum flag)
+{
+    if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear the reset flag
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_all_reset_flag_clear(void)
+{
+    RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
+}
+
+/*!
+    \brief      get the clock stabilization interrupt and ckm flags
+    \param[in]  int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
+      \arg        RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
+      \arg        RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
+      \arg        RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
+      \arg        RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
+      \arg        RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag
+      \arg        RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
+{
+    if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear the interrupt flags
+    \param[in]  int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
+    \param[out] none
+    \retval     none
+*/
+void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
+{
+    RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
+}
+
+/*!
+    \brief      enable the stabilization interrupt
+    \param[in]  stab_int: clock stabilization interrupt, refer to rcu_int_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
+      \arg        RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
+      \arg        RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
+      \arg        RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
+      \arg        RCU_INT_PLLSTB: PLL stabilization interrupt enable
+      \arg        RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void rcu_interrupt_enable(rcu_int_enum stab_int)
+{
+    RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
+}
+
+
+/*!
+    \brief      disable the stabilization interrupt
+    \param[in]  stab_int: clock stabilization interrupt, refer to rcu_int_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable
+      \arg        RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable
+      \arg        RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable
+      \arg        RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable
+      \arg        RCU_INT_PLLSTB: PLL stabilization interrupt disable
+      \arg        RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable
+    \param[out] none
+    \retval     none
+*/
+void rcu_interrupt_disable(rcu_int_enum stab_int)
+{
+    RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
+}
+
+/*!
+    \brief      wait until oscillator stabilization flags is SET
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: HXTAL
+      \arg        RCU_LXTAL: LXTAL
+      \arg        RCU_IRC8M: IRC8M
+      \arg        RCU_IRC28M: IRC28M
+      \arg        RCU_IRC40K: IRC40K
+      \arg        RCU_PLL_CK: PLL
+    \param[out] none
+    \retval     ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
+{
+    uint32_t stb_cnt = 0U;
+    ErrStatus reval = ERROR;
+    FlagStatus osci_stat = RESET;
+    switch(osci){
+    case RCU_HXTAL:
+         /* wait until HXTAL is stabilization and osci_stat is not more than timeout */
+        while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
+            stb_cnt++;
+        }
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
+            reval = SUCCESS;
+        }
+        break;
+        
+    /* wait LXTAL stable */
+    case RCU_LXTAL:
+        while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
+            stb_cnt++;
+        }
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
+            reval = SUCCESS;
+        }
+        break;
+
+    /* wait IRC8M stable */
+    case RCU_IRC8M:
+        while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
+            stb_cnt++;
+        }
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
+            reval = SUCCESS;
+        }
+        break;
+
+    /* wait IRC28M stable */
+    case RCU_IRC28M:
+        while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB);
+            stb_cnt++;
+        }
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)){
+            reval = SUCCESS;
+        }
+        break;
+        
+    /* wait IRC40K stable */
+    case RCU_IRC40K:
+        while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
+            stb_cnt++;
+        }
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
+            reval = SUCCESS;
+        }
+        break;
+
+    /* wait PLL stable */
+    case RCU_PLL_CK:
+        while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
+            stb_cnt++;
+        }
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
+            reval = SUCCESS;
+        }
+        break;
+   
+    default:
+        break;
+    }
+    /* return value */
+    return reval;
+}
+
+/*!
+    \brief      turn on the oscillator
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: HXTAL
+      \arg        RCU_LXTAL: LXTAL
+      \arg        RCU_IRC8M: IRC8M
+      \arg        RCU_IRC28M: IRC28M
+      \arg        RCU_IRC40K: IRC40K
+      \arg        RCU_PLL_CK: PLL
+    \param[out] none
+    \retval     none
+*/
+void rcu_osci_on(rcu_osci_type_enum osci)
+{
+    RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
+}
+
+/*!
+    \brief      turn off the oscillator
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: HXTAL
+      \arg        RCU_LXTAL: LXTAL
+      \arg        RCU_IRC8M: IRC8M
+      \arg        RCU_IRC28M: IRC28M
+      \arg        RCU_IRC40K: IRC40K
+      \arg        RCU_PLL_CK: PLL
+    \param[out] none
+    \retval     none
+*/
+void rcu_osci_off(rcu_osci_type_enum osci)
+{
+    RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
+}
+
+/*!
+    \brief      enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: HXTAL
+      \arg        RCU_LXTAL: LXTAL
+    \param[out] none
+    \retval     none
+*/
+void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
+{
+    uint32_t reg;
+    switch(osci){
+    case RCU_HXTAL:
+        /* HXTALEN must be reset before enable the oscillator bypass mode */
+        reg = RCU_CTL0;
+        RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
+        RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS);
+        break;
+    case RCU_LXTAL:
+        /* LXTALEN must be reset before enable the oscillator bypass mode */
+        reg = RCU_BDCTL;
+        RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
+        RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
+        break;
+    case RCU_IRC8M:
+    case RCU_IRC28M:
+    case RCU_IRC40K:
+    case RCU_PLL_CK:
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: HXTAL
+      \arg        RCU_LXTAL: LXTAL
+    \param[out] none
+    \retval     none
+*/
+void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
+{
+    uint32_t reg;
+    switch(osci){
+    case RCU_HXTAL:
+        /* HXTALEN must be reset before disable the oscillator bypass mode */
+        reg = RCU_CTL0;
+        RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
+        RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS));
+        break;
+    case RCU_LXTAL:
+        /* LXTALEN must be reset before disable the oscillator bypass mode */
+        reg = RCU_BDCTL;
+        RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
+        RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS));
+        break;
+    case RCU_IRC8M:
+    case RCU_IRC28M:
+    case RCU_IRC40K:
+    case RCU_PLL_CK:
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      enable the HXTAL clock monitor
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_hxtal_clock_monitor_enable(void)
+{
+    RCU_CTL0 |= RCU_CTL0_CKMEN;
+}
+
+/*!
+    \brief      disable the HXTAL clock monitor
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_hxtal_clock_monitor_disable(void)
+{
+    RCU_CTL0 &= ~RCU_CTL0_CKMEN;
+}
+
+/*!
+    \brief      set the IRC8M adjust value
+    \param[in]  irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F
+    \param[out] none
+    \retval     none
+*/
+void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval)
+{
+    uint32_t adjust = 0U;
+    adjust = RCU_CTL0;
+    /* reset the IRC8MADJ bits and set according to irc8m_adjval */
+    adjust &= ~RCU_CTL0_IRC8MADJ;
+    RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval)<<3));
+}
+
+/*!
+    \brief      set the IRC28M adjust value
+    \param[in]  irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F
+    \param[out] none
+    \retval     none
+*/
+void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval)
+{
+    uint32_t adjust = 0U;
+    adjust = RCU_CTL1;
+    /* reset the IRC28MADJ bits and set according to irc28m_adjval */
+    adjust &= ~RCU_CTL1_IRC28MADJ;
+    RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval)<<3));
+}
+
+/*!
+    \brief      unlock the voltage key
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_voltage_key_unlock(void)
+{
+    /* reset the KEY bits and set 0x1A2B3C4D */
+    RCU_VKEY &= ~RCU_VKEY_KEY;
+    RCU_VKEY |= RCU_VKEY_UNLOCK;
+}
+
+/*!
+    \brief      set voltage in deep sleep mode
+    \param[in]  dsvol: deep sleep mode voltage
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
+      \arg        RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
+      \arg        RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V
+      \arg        RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V
+    \param[out] none
+    \retval     none
+*/
+void rcu_deepsleep_voltage_set(uint32_t dsvol)
+{
+    /* reset the DSLPVS bits and set according to dsvol */
+    RCU_DSV &= ~RCU_DSV_DSLPVS;
+    RCU_DSV |= dsvol;
+}
+
+/*!
+    \brief      get the system clock, bus and peripheral clock frequency
+    \param[in]  clock: the clock frequency which to get
+                only one parameter can be selected which is shown as below:
+      \arg        CK_SYS: system clock frequency
+      \arg        CK_AHB: AHB clock frequency
+      \arg        CK_APB1: APB1 clock frequency
+      \arg        CK_APB2: APB2 clock frequency
+      \arg        CK_ADC: ADC clock frequency
+      \arg        CK_USART: USART0 clock frequency
+    \param[out] none
+    \retval     clock frequency of system, AHB, APB1, APB2, ADC or USRAT0
+*/
+uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
+{
+    uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U;
+    uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U;
+    uint32_t adc_freq = 0U, usart_freq = 0U;
+    uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
+    /* exponent of AHB, APB1 and APB2 clock divider */
+    const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+    const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+    const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+    sws = GET_BITS(RCU_CFG0, 2, 3);
+    switch(sws){
+    /* IRC8M is selected as CK_SYS */
+    case SEL_IRC8M:
+        cksys_freq = IRC8M_VALUE;
+        break;
+    /* HXTAL is selected as CK_SYS */
+    case SEL_HXTAL:
+        cksys_freq = HXTAL_VALUE;
+        break;
+    /* PLL is selected as CK_SYS */
+    case SEL_PLL:
+        /* get the value of PLLMF[3:0] */
+        pllmf = GET_BITS(RCU_CFG0, 18, 21);
+        pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
+        /* high 16 bits */
+        if(1U == pllmf4){
+            pllmf += 17U;
+        }else if(15U == pllmf){
+            pllmf = 16U;
+        }else{
+            pllmf += 2U;
+        }
+            
+        /* PLL clock source selection, HXTAL or IRC8M/2 */
+        pllsel = GET_BITS(RCU_CFG0, 16, 16);
+        if(0U != pllsel){
+            prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
+            cksys_freq = (HXTAL_VALUE / prediv) * pllmf;
+        }else{
+            cksys_freq = (IRC8M_VALUE >> 1) * pllmf;
+        }
+        break;
+    /* IRC8M is selected as CK_SYS */
+    default:
+        cksys_freq = IRC8M_VALUE;
+        break;
+    }
+    /* calculate AHB clock frequency */
+    idx = GET_BITS(RCU_CFG0, 4, 7);
+    clk_exp = ahb_exp[idx];
+    ahb_freq = cksys_freq >> clk_exp;
+    
+    /* calculate APB1 clock frequency */
+    idx = GET_BITS(RCU_CFG0, 8, 10);
+    clk_exp = apb1_exp[idx];
+    apb1_freq = ahb_freq >> clk_exp;
+    
+    /* calculate APB2 clock frequency */
+    idx = GET_BITS(RCU_CFG0, 11, 13);
+    clk_exp = apb2_exp[idx];
+    apb2_freq = ahb_freq >> clk_exp;
+    
+    /* return the clocks frequency */
+    switch(clock){
+    case CK_SYS:
+        ck_freq = cksys_freq;
+        break;
+    case CK_AHB:
+        ck_freq = ahb_freq;
+        break;
+    case CK_APB1:
+        ck_freq = apb1_freq;
+        break;
+    case CK_APB2:
+        ck_freq = apb2_freq;
+        break;
+    case CK_ADC:
+        /* calculate ADC clock frequency */
+        if(RCU_ADCSRC_AHB_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){
+            if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){
+                adc_freq = IRC28M_VALUE >> 1;
+            }else{
+                adc_freq = IRC28M_VALUE;
+            }
+        }else{
+            /* ADC clock select CK_APB2 divided by 2/4/6/8 or CK_AHB divided by 3/5/7/9 */
+            adcps = GET_BITS(RCU_CFG0, 14, 15);
+            adcps2 = GET_BITS(RCU_CFG2, 31, 31);
+            if(0U != adcps2){
+                /* ADC clock select CK_AHB divided by 3/5/7/9 */
+                adc_freq = ahb_freq / (adcps + 1U);
+            }else{
+                /* ADC clock select CK_APB2 divided by 2/4/6/8 */
+                adc_freq = apb2_freq / adcps;
+            }
+        }
+        ck_freq = adc_freq;
+        break;
+    case CK_USART:
+        /* calculate USART0 clock frequency */
+        if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
+            usart_freq = apb2_freq;
+        }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
+            usart_freq = cksys_freq;
+        }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
+            usart_freq = LXTAL_VALUE;
+        }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
+            usart_freq = IRC8M_VALUE;
+        }else{
+        }
+        ck_freq = usart_freq;
+        break;
+    default:
+        break;
+    }
+    return ck_freq;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rtc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rtc.c
new file mode 100644
index 0000000000..546afa781e
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rtc.c
@@ -0,0 +1,965 @@
+/*!
+    \file    gd32e230_rtc.c
+    \brief   RTC driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_rtc.h"
+
+/*!
+    \brief      reset most of the RTC registers
+    \param[in]  none
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_deinit(void)
+{
+    ErrStatus error_status = ERROR;
+
+    /* RTC_TAMP register is not under write protection */
+    RTC_TAMP = RTC_REGISTER_RESET;
+
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    /* reset RTC_CTL register, this can be done without the init mode */
+    RTC_CTL &= RTC_REGISTER_RESET;
+
+    /* enter init mode */
+    error_status = rtc_init_mode_enter();
+
+    if(ERROR != error_status){
+        /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition.
+           in order to read calendar from shadow register, not the real registers being reset */
+        RTC_TIME = RTC_REGISTER_RESET;
+        RTC_DATE = RTC_DATE_RESET;
+
+        RTC_PSC = RTC_PSC_RESET;
+
+        /* reset RTC_STAT register, also exit init mode.
+           at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */
+        RTC_STAT = RTC_STAT_RESET;
+      
+        /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */
+        RTC_ALRM0TD = RTC_REGISTER_RESET;
+        RTC_ALRM0SS = RTC_REGISTER_RESET;
+
+        /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */
+        RTC_SHIFTCTL = RTC_REGISTER_RESET;
+        RTC_HRFC = RTC_REGISTER_RESET;
+
+        error_status = rtc_register_sync_wait();  
+    }
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
+
+/*!
+    \brief      initialize RTC registers
+    \param[in]  rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains 
+                parameters for initialization of the rtc peripheral
+                members of the structure and the member values are shown as below:
+                  rtc_year: 0x0 - 0x99(BCD format)
+                  rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN,
+                             RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC
+                  rtc_date: 0x1 - 0x31(BCD format)
+                  rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY
+                                   RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY
+                  rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose
+                  rtc_minute: 0x0 - 0x59(BCD format)
+                  rtc_second: 0x0 - 0x59(BCD format)
+                  rtc_factor_asyn: 0x0 - 0x7F
+                  rtc_factor_syn: 0x0 - 0x7FFF
+                  rtc_am_pm: RTC_AM, RTC_PM
+                  rtc_display_format: RTC_24HOUR, RTC_12HOUR
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct)
+{
+    ErrStatus error_status = ERROR;
+    uint32_t reg_time = 0x00U, reg_date = 0x00U;
+
+    reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \
+                DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \
+                DATE_MON(rtc_initpara_struct->rtc_month) | \
+                DATE_DAY(rtc_initpara_struct->rtc_date)); 
+    
+    reg_time = (rtc_initpara_struct->rtc_am_pm| \
+                TIME_HR(rtc_initpara_struct->rtc_hour) | \
+                TIME_MN(rtc_initpara_struct->rtc_minute) | \
+                TIME_SC(rtc_initpara_struct->rtc_second)); 
+              
+    /* 1st: disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    /* 2nd: enter init mode */
+    error_status = rtc_init_mode_enter();
+
+    if(ERROR != error_status){
+        RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn)| \
+                                  PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn));
+
+        RTC_TIME = (uint32_t)reg_time;
+        RTC_DATE = (uint32_t)reg_date;
+
+        RTC_CTL &= (uint32_t)(~RTC_CTL_CS);
+        RTC_CTL |=  rtc_initpara_struct->rtc_display_format;
+        
+        /* 3rd: exit init mode */
+        rtc_init_mode_exit();
+        
+        /* 4th: wait the RSYNF flag to set */
+        error_status = rtc_register_sync_wait();
+    }
+
+    /* 5th: enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
+
+/*!
+    \brief      enter RTC init mode
+    \param[in]  none
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_init_mode_enter(void)
+{
+    uint32_t time_index = RTC_INITM_TIMEOUT;
+    uint32_t flag_status = RESET;
+    ErrStatus error_status = ERROR;
+
+    /* check whether it has been in init mode */
+    if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){
+        RTC_STAT |= RTC_STAT_INITM;
+        
+        /* wait until the INITF flag to be set */
+        do{
+           flag_status = RTC_STAT & RTC_STAT_INITF;
+        }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
+
+        if((uint32_t)RESET != flag_status){
+            error_status = SUCCESS;
+        }
+    }else{
+        error_status = SUCCESS;
+    }
+    return error_status;
+}
+
+/*!
+    \brief      exit RTC init mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_init_mode_exit(void)
+{
+    RTC_STAT &= (uint32_t)(~RTC_STAT_INITM);
+}
+
+/*!
+    \brief      wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow 
+                registers are updated
+    \param[in]  none
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_register_sync_wait(void)
+{
+    volatile uint32_t time_index = RTC_RSYNF_TIMEOUT;
+    uint32_t flag_status = RESET;
+    ErrStatus error_status = ERROR;
+
+    if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){
+        /* disable the write protection */
+        RTC_WPK = RTC_UNLOCK_KEY1;
+        RTC_WPK = RTC_UNLOCK_KEY2;
+
+        /* firstly clear RSYNF flag */
+        RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF);
+
+        /* wait until RSYNF flag to be set */
+        do{
+            flag_status = RTC_STAT & RTC_STAT_RSYNF;
+        }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
+
+        if((uint32_t)RESET != flag_status){
+            error_status = SUCCESS;
+        }
+        
+        /* enable the write protection */
+        RTC_WPK = RTC_LOCK_KEY;
+    }else{ 
+        error_status = SUCCESS;
+    }
+
+    return error_status;
+}
+
+/*!
+    \brief      get current time and date
+    \param[in]  none
+    \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains 
+                parameters for initialization of the rtc peripheral
+                members of the structure and the member values are shown as below:
+                  rtc_year: 0x0 - 0x99(BCD format)
+                  rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN,
+                             RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC
+                  rtc_date: 0x1 - 0x31(BCD format)
+                  rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY
+                                   RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY
+                  rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose
+                  rtc_minute: 0x0 - 0x59(BCD format)
+                  rtc_second: 0x0 - 0x59(BCD format)
+                  rtc_factor_asyn: 0x0 - 0x7F
+                  rtc_factor_syn: 0x0 - 0x7FFF
+                  rtc_am_pm: RTC_AM, RTC_PM
+                  rtc_display_format: RTC_24HOUR, RTC_12HOUR
+    \retval     none
+*/
+void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct)
+{
+    uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U;
+
+    temp_tr = (uint32_t)RTC_TIME;   
+    temp_dr = (uint32_t)RTC_DATE;
+    temp_pscr = (uint32_t)RTC_PSC;
+    temp_ctlr = (uint32_t)RTC_CTL;
+  
+    /* get current time and construct rtc_parameter_struct structure */
+    rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr);
+    rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr);
+    rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr);
+    rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr);  
+    rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr);
+    rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr);
+    rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr);
+    rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr);
+    rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr);
+    rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); 
+    rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS);
+}
+
+/*!
+    \brief      get current subsecond value
+    \param[in]  none
+    \param[out] none
+    \retval     current subsecond value
+*/
+uint32_t rtc_subsecond_get(void)
+{
+    uint32_t reg = 0x00U;
+    /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */
+    reg = (uint32_t)RTC_SS;
+    /* read RTC_DATE to unlock the 3 shadow registers */
+    (void) (RTC_DATE);
+
+    return reg;
+}
+
+/*!
+    \brief      configure RTC alarm
+    \param[in]  rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains 
+                parameters for RTC alarm configuration
+                members of the structure and the member values are shown as below:
+                  rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK
+                                  RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK
+                  rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED
+                  rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set
+                                 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY,
+                                    RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set
+                  rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format
+                  rtc_alarm_minute: 0x0 - 0x59(BCD format)
+                  rtc_alarm_second: 0x0 - 0x59(BCD format)
+                  rtc_am_pm: RTC_AM, RTC_PM
+    \param[out] none
+    \retval     none
+*/
+void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time)
+{
+    uint32_t reg_alrm0td = 0x00U;
+
+    reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \
+                 rtc_alarm_time->rtc_weekday_or_date | \
+                 rtc_alarm_time->rtc_am_pm | \
+                 ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \
+                 ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \
+                 ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \
+                 ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second));
+
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    RTC_ALRM0TD = (uint32_t)reg_alrm0td;
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      configure subsecond of RTC alarm
+    \param[in]  mask_subsecond: alarm subsecond mask
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_MASKSSC_0_14: mask alarm subsecond configuration
+      \arg        RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared
+      \arg        RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared
+      \arg        RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared
+      \arg        RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared
+      \arg        RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared
+      \arg        RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared
+      \arg        RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared
+      \arg        RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared
+      \arg        RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared
+      \arg        RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared
+      \arg        RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared
+      \arg        RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared
+      \arg        RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared
+      \arg        RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared
+      \arg        RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared
+    \param[in]  subsecond: alarm subsecond value(0x000 - 0x7FFF)
+    \param[out] none
+    \retval     none
+*/
+void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond)
+{
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;  
+
+    RTC_ALRM0SS = mask_subsecond | subsecond;  
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      enable RTC alarm
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_alarm_enable(void)
+{
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    RTC_CTL |= RTC_CTL_ALRM0EN;
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      disable RTC alarm
+    \param[in]  none
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_alarm_disable(void)
+{
+    volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT;
+    ErrStatus error_status = ERROR;
+    uint32_t flag_status = RESET;
+
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+    
+    /* clear the state of alarm */
+    RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN);  
+    
+    /* wait until ALRM0WF flag to be set after the alarm is disabled */
+    do{
+        flag_status = RTC_STAT & RTC_STAT_ALRM0WF;
+    }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status));
+    
+    if((uint32_t)RESET != flag_status){     
+        error_status = SUCCESS;
+    }
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
+
+/*!
+    \brief      get RTC alarm
+    \param[in]  none
+    \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains 
+                parameters for RTC alarm configuration
+                members of the structure and the member values are shown as below:
+                  rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK
+                                  RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK
+                  rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED
+                  rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set
+                                 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY,
+                                    RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set
+                  rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format
+                  rtc_alarm_minute: 0x0 - 0x59(BCD format)
+                  rtc_alarm_second: 0x0 - 0x59(BCD format)
+                  rtc_am_pm: RTC_AM, RTC_PM
+    \retval     none
+*/
+void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time)
+{
+    uint32_t reg_alrm0td = 0x00U;
+
+    /* get the value of RTC_ALRM0TD register */
+    reg_alrm0td = RTC_ALRM0TD;
+
+    /* get alarm parameters and construct the rtc_alarm_struct structure */
+    rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; 
+    rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM);
+    rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS);
+    rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td);
+    rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td);
+    rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td);
+    rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td);  
+}
+
+/*!
+    \brief      get RTC alarm subsecond
+    \param[in]  none
+    \param[out] none
+    \retval     RTC alarm subsecond value
+*/
+uint32_t rtc_alarm_subsecond_get(void)
+{
+    return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
+}
+
+/*!
+    \brief      enable RTC time-stamp
+    \param[in]  edge: specify which edge to detect of time-stamp
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event
+      \arg        RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event
+    \param[out] none
+    \retval     none
+*/
+void rtc_timestamp_enable(uint32_t edge)
+{
+    uint32_t reg_ctl = 0x00U;
+
+    /* clear the bits to be configured in RTC_CTL */
+    reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN)));
+
+    /* new configuration */
+    reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN);
+   
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    RTC_CTL = (uint32_t)reg_ctl;
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      disable RTC time-stamp
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_timestamp_disable(void)
+{
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+    
+    /* clear the TSEN bit */
+    RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN);
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      get RTC timestamp time and date
+    \param[in]  none
+    \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains 
+                parameters for RTC time-stamp configuration
+                members of the structure and the member values are shown as below:
+                  rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN,
+                                       RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC
+                  rtc_timestamp_date: 0x1 - 0x31(BCD format)
+                  rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY,
+                                     RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set
+                  rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format
+                  rtc_timestamp_minute: 0x0 - 0x59(BCD format)
+                  rtc_timestamp_second: 0x0 - 0x59(BCD format)
+                  rtc_am_pm: RTC_AM, RTC_PM
+    \retval     none
+*/
+void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp)
+{
+    uint32_t temp_tts = 0x00U, temp_dts = 0x00U;
+
+    /* get the value of time_stamp registers */
+    temp_tts = (uint32_t)RTC_TTS;
+    temp_dts = (uint32_t)RTC_DTS;
+  
+    /* get timestamp time and construct the rtc_timestamp_struct structure */
+    rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM);
+    rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts);
+    rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts);
+    rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts);
+    rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts);
+    rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts);
+    rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts);
+}
+
+/*!
+    \brief      get RTC time-stamp subsecond
+    \param[in]  none
+    \param[out] none
+    \retval     RTC time-stamp subsecond value
+*/
+uint32_t rtc_timestamp_subsecond_get(void)
+{
+    return ((uint32_t)RTC_SSTS);
+}
+
+/*!
+    \brief      enable RTC tamper
+    \param[in]  rtc_tamper: pointer to a rtc_tamper_struct structure which contains 
+                parameters for RTC tamper configuration
+                members of the structure and the member values are shown as below:
+                  rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1
+                  rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING
+                                      RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH
+                  rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S
+                  rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192,
+                                               RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024,
+                                               RTC_FREQ_DIV512, RTC_FREQ_DIV256
+                  rtc_tamper_precharge_enable: DISABLE, ENABLE
+                  rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C
+                  rtc_tamper_with_timestamp: DISABLE, ENABLE
+    \param[out] none
+    \retval     none
+*/
+void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper)
+{
+    /* disable tamper */
+    RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source); 
+
+    /* tamper filter must be used when the tamper source is voltage level detection */
+    RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT;
+    
+    /* the tamper source is voltage level detection */
+    if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE ){ 
+        RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT);
+
+        /* check if the tamper pin need precharge, if need, then configure the precharge time */
+        if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable){
+            RTC_TAMP |=  (uint32_t)RTC_TAMP_DISPU;    
+        }else{
+            RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time);
+        }
+
+        RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency);
+        RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter);
+    }
+    
+    RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS;  
+    
+    if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp){           
+        /* the tamper event also cause a time-stamp event */
+        RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS;
+    } 
+    
+    /* configure the tamper trigger */
+    RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS));    
+    if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger){
+        RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source)<< RTC_TAMPER_TRIGGER_POS);  
+    }    
+    /* enable tamper */
+    RTC_TAMP |=  (uint32_t)(rtc_tamper->rtc_tamper_source); 
+}
+
+/*!
+    \brief      disable RTC tamper
+    \param[in]  source: specify which tamper source to be disabled
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_TAMPER0
+      \arg        RTC_TAMPER1
+    \param[out] none
+    \retval     none
+*/
+void rtc_tamper_disable(uint32_t source)
+{
+    /* disable tamper */
+    RTC_TAMP &= (uint32_t)~source; 
+
+}
+
+/*!
+    \brief      enable specified RTC interrupt
+    \param[in]  interrupt: specify which interrupt source to be enabled
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_INT_TIMESTAMP: timestamp interrupt
+      \arg        RTC_INT_ALARM: alarm interrupt
+      \arg        RTC_INT_TAMP: tamp interrupt
+    \param[out] none
+    \retval     none
+*/
+void rtc_interrupt_enable(uint32_t interrupt)
+{  
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+ 
+    /* enable the interrupts in RTC_CTL register */
+    RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE);
+    /* enable the interrupts in RTC_TAMP register */
+    RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE);
+    
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY; 
+}
+
+/*!
+    \brief      disble specified RTC interrupt
+    \param[in]  interrupt: specify which interrupt source to be disabled
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_INT_TIMESTAMP: timestamp interrupt
+      \arg        RTC_INT_ALARM: alarm interrupt
+      \arg        RTC_INT_TAMP: tamp interrupt
+    \param[out] none
+    \retval     none
+*/
+void rtc_interrupt_disable(uint32_t interrupt)
+{  
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+ 
+    /* disable the interrupts in RTC_CTL register */
+    RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE);
+    /* disable the interrupts in RTC_TAMP register */
+    RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE);
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      check specified flag
+    \param[in]  flag: specify which flag to check
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_FLAG_RECALIBRATION: recalibration pending flag
+      \arg        RTC_FLAG_TAMP1: tamper 1 event flag
+      \arg        RTC_FLAG_TAMP0: tamper 0 event flag
+      \arg        RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag
+      \arg        RTC_FLAG_TIMESTAMP: time-stamp event flag
+      \arg        RTC_FLAG_ALARM0: alarm event flag
+      \arg        RTC_FLAG_INIT: init mode event flag
+      \arg        RTC_FLAG_RSYN: time and date registers synchronized event flag
+      \arg        RTC_FLAG_YCM: year parameter configured event flag
+      \arg        RTC_FLAG_SHIFT: shift operation pending flag
+      \arg        RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus rtc_flag_get(uint32_t flag)
+{
+    FlagStatus flag_state = RESET;
+    
+    if((uint32_t)RESET != (RTC_STAT & flag)){   
+        flag_state = SET;
+    }
+    return flag_state;
+}
+
+/*!
+    \brief      clear specified flag
+    \param[in]  flag: specify which flag to clear
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_FLAG_TAMP1: tamper 1 event flag
+      \arg        RTC_FLAG_TAMP0: tamper 0 event flag
+      \arg        RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag
+      \arg        RTC_FLAG_TIMESTAMP: time-stamp event flag
+      \arg        RTC_FLAG_ALARM0: alarm event flag
+      \arg        RTC_FLAG_RSYN: time and date registers synchronized event flag
+    \param[out] none
+    \retval     none
+*/
+void rtc_flag_clear(uint32_t flag)
+{
+    RTC_STAT &= (uint32_t)(~flag);  
+}
+
+/*!
+    \brief      configure rtc alternate output source
+    \param[in]  source: specify signal to output
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC 
+                                         is the default value, output 512Hz signal
+      \arg        RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC 
+                                       is the default value, output 512Hz signal
+      \arg        RTC_ALARM_HIGH: when the  alarm flag is set, the output pin is high
+      \arg        RTC_ALARM_LOW: when the  Alarm flag is set, the output pin is low
+    \param[in]  mode: specify the output pin (PC13) mode when output alarm signal
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_ALARM_OUTPUT_OD: open drain mode
+      \arg        RTC_ALARM_OUTPUT_PP: push pull mode
+    \param[out] none
+    \retval     none
+*/
+void rtc_alter_output_config(uint32_t source, uint32_t mode)
+{
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS);
+
+    RTC_CTL |= (uint32_t)(source);
+    
+    /* alarm output */
+    if((uint32_t)RESET != (source & RTC_OS_ENABLE)){
+        RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL);
+        RTC_TAMP |= (uint32_t)(mode);  
+    }
+    
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      configure RTC calibration register
+    \param[in]  window: select calibration window
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz
+      \arg        RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz
+      \arg        RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz
+    \param[in]  plus: add RTC clock or not
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock
+      \arg        RTC_CALIBRATION_PLUS_RESET: no effect
+    \param[in]  minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF)
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus)
+{
+    uint32_t time_index = RTC_HRFC_TIMEOUT;
+    ErrStatus error_status = ERROR;
+    uint32_t flag_status = RESET;
+    
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;    
+    
+    /* check if a calibration operation is ongoing */        
+    do{
+        flag_status = RTC_STAT & RTC_STAT_SCPF;
+    }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status));
+    
+    if((uint32_t)RESET == flag_status){
+        RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
+        error_status = SUCCESS;
+    }
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
+
+/*!
+    \brief      adjust the daylight saving time by adding or substracting one hour from the current time
+    \param[in]  operation: hour ajustment operation
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_CTL_A1H: add one hour
+      \arg        RTC_CTL_S1H: substract one hour
+    \param[out] none
+    \retval     none
+*/
+void rtc_hour_adjust(uint32_t operation)
+{
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    RTC_CTL |= (uint32_t)(operation);
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      adjust RTC second or subsecond value of current time
+    \param[in]  add: add 1s to current time or not
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_SHIFT_ADD1S_RESET: no effect
+      \arg        RTC_SHIFT_ADD1S_SET: add 1s to current time
+    \param[in]  minus: number of subsecond to minus from current time(0x0 - 0x7FFF)
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus)
+{
+    uint32_t time_index = RTC_SHIFTCTL_TIMEOUT;
+    ErrStatus error_status = ERROR;
+    uint32_t flag_status = RESET;
+    uint32_t temp=0U;
+
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+    
+    /* check if a shift operation is ongoing */    
+    do{
+        flag_status = RTC_STAT & RTC_STAT_SOPF;
+    }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status));
+  
+    temp = RTC_CTL & RTC_CTL_REFEN;
+    /* check if the function of reference clock detection is disabled */
+    if(((uint32_t)RESET == flag_status) && (RESET == temp)){  
+        RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
+        error_status = rtc_register_sync_wait();        
+    }
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
+
+/*!
+    \brief      enable RTC bypass shadow registers function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_bypass_shadow_enable(void)
+{ 
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD;
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      disable RTC bypass shadow registers function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_bypass_shadow_disable(void)
+{ 
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD;
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+}
+
+/*!
+    \brief      enable RTC reference clock detection function
+    \param[in]  none
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_refclock_detection_enable(void)
+{
+    ErrStatus error_status = ERROR;
+    
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    /* enter init mode */
+    error_status = rtc_init_mode_enter();
+
+    if(ERROR != error_status){
+        RTC_CTL |= (uint32_t)RTC_CTL_REFEN;
+        /* exit init mode */
+        rtc_init_mode_exit();
+    }
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
+
+/*!
+    \brief      disable RTC reference clock detection function
+    \param[in]  none
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus rtc_refclock_detection_disable(void)
+{
+    ErrStatus error_status = ERROR;
+    
+    /* disable the write protection */
+    RTC_WPK = RTC_UNLOCK_KEY1;
+    RTC_WPK = RTC_UNLOCK_KEY2;
+
+    /* enter init mode */
+    error_status = rtc_init_mode_enter();
+
+    if(ERROR != error_status){ 
+        RTC_CTL &= (uint32_t)~RTC_CTL_REFEN;
+        /* exit init mode */
+        rtc_init_mode_exit();
+    }
+
+    /* enable the write protection */
+    RTC_WPK = RTC_LOCK_KEY;
+
+    return error_status;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_spi.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_spi.c
new file mode 100644
index 0000000000..a48f5c426a
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_spi.c
@@ -0,0 +1,1003 @@
+/*!
+    \file    gd32e230_spi.c
+    \brief   SPI driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_spi.h"
+
+/* SPI/I2S parameter initialization mask */
+#define SPI_INIT_MASK                        ((uint32_t)0x00003040U)  /*!< SPI0 parameter initialization mask */
+#define SPI_FIFO_INIT_MASK1                  ((uint32_t)0x00003840U)  /*!< SPI1 parameter initialization mask1 */
+#define SPI_FIFO_INIT_MASK2                  ((uint32_t)0x0000F0FFU)  /*!< SPI1 parameter initialization mask2*/
+#define I2S_INIT_MASK                        ((uint32_t)0x0000F047U)  /*!< I2S parameter initialization mask */
+
+#define SPI_FRAMESIZE_MASK                   ((uint32_t)0x00000800U)  /*!< SPI0 frame size mask */
+#define SPI_BYTEN_MASK                       ((uint32_t)0x00001000U)  /*!< SPI1 access to FIFO mask */
+#define SPI_TXLVL_EMPTY_MASK                 ((uint32_t)0x00001800U)  /*!< SPI1 TXFIFO empty mask */
+#define SPI_RXLVL_EMPTY_MASK                 ((uint32_t)0x00000600U)  /*!< SPI1 RXFIFO empty mask */
+
+/* I2S clock source selection, multiplication and division mask */
+#define SPI_I2SPSC_RESET                     ((uint32_t)0x00000002U)  /*!< I2S clock prescaler register reset value */
+
+/*!
+    \brief      reset SPI and I2S 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_deinit(uint32_t spi_periph)
+{
+    switch(spi_periph){
+    case SPI0:
+        /* reset SPI0 and I2S0 */
+        rcu_periph_reset_enable(RCU_SPI0RST);
+        rcu_periph_reset_disable(RCU_SPI0RST);
+        break;
+    case SPI1:
+        /* reset SPI1 */
+        rcu_periph_reset_enable(RCU_SPI1RST);
+        rcu_periph_reset_disable(RCU_SPI1RST);
+        break;
+    default :
+        break;
+    }
+}
+
+/*!
+    \brief      initialize the parameters of SPI struct with the default values
+    \param[in]  spi_struct: SPI parameter stuct
+    \param[out] none
+    \retval     none
+*/
+void spi_struct_para_init(spi_parameter_struct* spi_struct)
+{
+    /* set the SPI struct with the default values */
+    spi_struct->device_mode = SPI_SLAVE;
+    spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX;
+    spi_struct->frame_size = SPI_FRAMESIZE_8BIT;
+    spi_struct->nss = SPI_NSS_HARD;
+    spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
+    spi_struct->prescale = SPI_PSC_2;
+}
+
+/*!
+    \brief      initialize SPI parameter
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  spi_struct: SPI parameter initialization stuct members of the structure 
+                            and the member values are shown as below:
+                  device_mode: SPI_MASTER, SPI_SLAVE
+                  trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
+                              SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT
+                  frame_size: SPI_FRAMESIZE_4BIT, SPI_FRAMESIZE_5BIT
+                              SPI_FRAMESIZE_6BIT, SPI_FRAMESIZE_7BIT
+                              SPI_FRAMESIZE_8BIT, SPI_FRAMESIZE_9BIT
+                              SPI_FRAMESIZE_10BIT, SPI_FRAMESIZE_11BIT
+                              SPI_FRAMESIZE_12BIT, SPI_FRAMESIZE_13BIT
+                              SPI_FRAMESIZE_14BIT, SPI_FRAMESIZE_15BIT
+                              SPI_FRAMESIZE_16BIT
+                  nss: SPI_NSS_SOFT, SPI_NSS_HARD
+                  endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB
+                  clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE
+                                        SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE
+                  prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
+{   
+    uint32_t reg1, reg2, reg3 = 0U;
+    
+    reg1 = SPI_CTL0(spi_periph);
+    reg1 &= SPI_INIT_MASK;
+    
+    reg2 = SPI_CTL0(spi_periph);
+    reg2 &= SPI_FIFO_INIT_MASK1;
+
+    reg3 = SPI_CTL1(spi_periph);
+    reg3 &= SPI_FIFO_INIT_MASK2;
+
+    if( SPI0 == spi_periph){
+        /* select SPI as master or slave */
+        reg1 |= spi_struct->device_mode;
+        /* select SPI transfer mode */
+        reg1 |= spi_struct->trans_mode;
+        /* select SPI NSS use hardware or software */
+        reg1 |= spi_struct->nss;
+        /* select SPI LSB or MSB */
+        reg1 |= spi_struct->endian;
+        /* select SPI polarity and phase */
+        reg1 |= spi_struct->clock_polarity_phase;
+        /* select SPI prescale to adjust transmit speed */
+        reg1 |= spi_struct->prescale;
+        /* select SPI frame size */
+        /* check SPI0 frame size is 8bits/16bits or not*/
+        if((SPI_FRAMESIZE_8BIT != spi_struct->frame_size) && (SPI_FRAMESIZE_16BIT != spi_struct->frame_size))
+        {
+            return ERROR;
+        }else{
+            reg1 |= (spi_struct->frame_size & SPI_FRAMESIZE_MASK);
+        }
+        
+        /* write to SPI_CTL0 register */
+        SPI_CTL0(spi_periph) = (uint32_t)reg1;
+    
+    }else{
+        /* select SPI as master or slave */
+        reg2 |= spi_struct->device_mode;
+        /* select SPI transfer mode */
+        reg2 |= spi_struct->trans_mode;
+        /* select SPI NSS use hardware or software */
+        reg2 |= spi_struct->nss;
+        /* select SPI LSB or MSB */
+        reg2 |= spi_struct->endian;
+        /* select SPI polarity and phase */
+        reg2 |= spi_struct->clock_polarity_phase;
+        /* select SPI prescale to adjust transmit speed */
+        reg2 |= spi_struct->prescale;
+        /* write to SPI_CTL0 register */
+        SPI_CTL0(spi_periph) = (uint32_t)reg2;
+
+        /* select SPI data size */
+        reg3 |= spi_struct->frame_size;
+        /* write to SPI_CTL0 register */
+        SPI_CTL1(spi_periph) = (uint32_t)reg3;
+    }
+    
+    /* select SPI mode */
+    SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
+    
+    return SUCCESS;
+}
+
+/*!
+    \brief      enable SPI
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_enable(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
+}
+
+/*!
+    \brief      disable SPI 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_disable(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
+}
+
+/*!
+    \brief      initialize I2S parameter 
+    \param[in]  spi_periph: SPIx(x=0)
+    \param[in]  mode: I2S operation mode
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_MODE_SLAVETX: I2S slave transmit mode
+      \arg        I2S_MODE_SLAVERX: I2S slave receive mode
+      \arg        I2S_MODE_MASTERTX: I2S master transmit mode
+      \arg        I2S_MODE_MASTERRX: I2S master receive mode
+    \param[in]  standard: I2S standard
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_STD_PHILLIPS: I2S phillips standard
+      \arg        I2S_STD_MSB: I2S MSB standard
+      \arg        I2S_STD_LSB: I2S LSB standard
+      \arg        I2S_STD_PCMSHORT: I2S PCM short standard
+      \arg        I2S_STD_PCMLONG: I2S PCM long standard
+    \param[in]  ckpl: I2S idle state clock polarity
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_CKPL_LOW: I2S clock polarity low level
+      \arg        I2S_CKPL_HIGH: I2S clock polarity high level
+    \param[out] none
+    \retval     none
+*/
+void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
+{
+    uint32_t reg = 0U;
+    reg = SPI_I2SCTL(spi_periph);
+    reg &= I2S_INIT_MASK;
+
+    /* enable I2S mode */
+    reg |= (uint32_t)SPI_I2SCTL_I2SSEL; 
+    /* select I2S mode */
+    reg |= (uint32_t)mode;
+    /* select I2S standard */
+    reg |= (uint32_t)standard;
+    /* select I2S polarity */
+    reg |= (uint32_t)ckpl;
+
+    /* write to SPI_I2SCTL register */
+    SPI_I2SCTL(spi_periph) = (uint32_t)reg;
+}
+
+/*!
+    \brief      configure I2S prescaler 
+    \param[in]  spi_periph: SPIx(x=0)
+    \param[in]  audiosample: I2S audio sample rate
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
+      \arg        I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
+      \arg        I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
+      \arg        I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
+      \arg        I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
+      \arg        I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
+      \arg        I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
+      \arg        I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
+      \arg        I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
+    \param[in]  frameformat: I2S data length and channel length
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
+      \arg        I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
+      \arg        I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
+      \arg        I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
+    \param[in]  mckout: I2S master clock output
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_MCKOUT_ENABLE: I2S master clock output enable
+      \arg        I2S_MCKOUT_DISABLE: I2S master clock output disable
+    \param[out] none
+    \retval     none
+*/
+void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
+{
+    uint32_t i2sdiv = 2U, i2sof = 0U;
+    uint32_t clks = 0U;
+    uint32_t i2sclock = 0U;
+
+    /* deinit SPI_I2SPSC register */
+    SPI_I2SPSC(spi_periph) = SPI_I2SPSC_RESET;
+
+    /* get system clock */
+    i2sclock = rcu_clock_freq_get(CK_SYS);
+    
+    /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
+    if(I2S_MCKOUT_ENABLE == mckout){
+        clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
+    }else{
+        if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){
+            clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample);
+        }else{
+            clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
+        }
+    }
+    
+    /* remove the floating point */
+    clks = (clks + 5U) / 10U;
+    i2sof = (clks & 0x00000001U);
+    i2sdiv = ((clks - i2sof) / 2U);
+    i2sof  = (i2sof << 8U);
+
+    /* set the default values */
+    if((i2sdiv < 2U) || (i2sdiv > 255U)){
+        i2sdiv = 2U;
+        i2sof = 0U;
+    }
+
+    /* configure SPI_I2SPSC */
+    SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
+
+    /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
+    SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
+    /* configure data frame format */
+    SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
+}
+
+
+/*!
+    \brief      enable I2S 
+    \param[in]  spi_periph: SPIx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void i2s_enable(uint32_t spi_periph)
+{
+    SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
+}
+
+/*!
+    \brief      disable I2S 
+    \param[in]  spi_periph: SPIx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void i2s_disable(uint32_t spi_periph)
+{
+    SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
+}
+
+/*!
+    \brief      enable SPI NSS output 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_nss_output_enable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
+}
+
+/*!
+    \brief      disable SPI NSS output 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_nss_output_disable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
+}
+
+/*!
+    \brief      SPI NSS pin high level in software mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_nss_internal_high(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
+}
+
+/*!
+    \brief      SPI NSS pin low level in software mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_nss_internal_low(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
+}
+
+/*!
+    \brief      enable SPI DMA send or receive 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  dma: SPI DMA mode
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_DMA_TRANSMIT: SPI transmit data using DMA
+      \arg        SPI_DMA_RECEIVE: SPI receive data using DMA
+    \param[out] none
+    \retval     none
+*/
+void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
+{
+    if(SPI_DMA_TRANSMIT == dma){
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
+    }else{
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
+    }
+}
+
+/*!
+    \brief      disable SPI DMA send or receive 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  dma: SPI DMA mode
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_DMA_TRANSMIT: SPI transmit data using DMA
+      \arg        SPI_DMA_RECEIVE: SPI receive data using DMA
+    \param[out] none
+    \retval     none
+*/
+void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
+{
+    if(SPI_DMA_TRANSMIT == dma){
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
+    }else{
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
+    }
+}
+
+/*!
+    \brief      configure SPI/I2S data frame format
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  frame_format: SPI frame size
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_FRAMESIZE_4BIT: SPI frame size is 4 bits
+      \arg        SPI_FRAMESIZE_5BIT: SPI frame size is 5 bits
+      \arg        SPI_FRAMESIZE_6BIT: SPI frame size is 6 bits
+      \arg        SPI_FRAMESIZE_7BIT: SPI frame size is 7 bits
+      \arg        SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
+      \arg        SPI_FRAMESIZE_9BIT: SPI frame size is 9 bits
+      \arg        SPI_FRAMESIZE_10BIT: SPI frame size is 10 bits
+      \arg        SPI_FRAMESIZE_11BIT: SPI frame size is 11 bits
+      \arg        SPI_FRAMESIZE_12BIT: SPI frame size is 12 bits
+      \arg        SPI_FRAMESIZE_13BIT: SPI frame size is 13 bits
+      \arg        SPI_FRAMESIZE_14BIT: SPI frame size is 14 bits
+      \arg        SPI_FRAMESIZE_15BIT: SPI frame size is 15 bits
+      \arg        SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
+{
+    if(SPI0 == spi_periph)
+    {
+        /* check SPI0 frame size is 8bits/16bits or not*/
+        if((SPI_FRAMESIZE_8BIT != frame_format) && (SPI_FRAMESIZE_16BIT != frame_format))
+        {
+            return ERROR;
+        }else{
+            /* clear SPI_CTL0_FF16 bit */
+            SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
+            /* configure SPI_CTL0_FF16 bit */
+            SPI_CTL0(spi_periph) |= ((uint32_t)frame_format & SPI_FRAMESIZE_MASK);
+        }
+    }
+    else{
+        /* clear SPI_CTL1_DZ bits */
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DZ);
+        /* confige SPI_CTL1_DZ bits */
+        SPI_CTL1(spi_periph) |= (uint32_t)frame_format;
+    }
+    return SUCCESS;
+}
+
+/*!
+    \brief      SPI transmit data
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  data: 16-bit data
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
+{
+    uint32_t reg, byten;
+    if(SPI0 == spi_periph)
+    {
+        SPI_DATA(spi_periph) = (uint32_t)data;
+    }
+    else
+    {
+        /* get the access size to FIFO */
+        byten = SPI_CTL1(spi_periph) & SPI_BYTEN_MASK;
+        if(RESET != byten)
+        {
+            reg = spi_periph + 0x0CU;
+            *( uint8_t *)(reg) = (uint8_t)data;
+        }else
+        {
+            SPI_DATA(spi_periph) = (uint16_t)data;
+        }
+    }
+}
+
+/*!
+    \brief      SPI receive data
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     16-bit data
+*/
+uint16_t spi_i2s_data_receive(uint32_t spi_periph)
+{
+    uint32_t reg, byten;
+    if(SPI0 == spi_periph)
+    {
+        return ((uint16_t)SPI_DATA(spi_periph));
+    }
+    else
+    {
+        /* get the access size to FIFO */
+        byten = SPI_CTL1(spi_periph) & SPI_BYTEN_MASK;
+        if(RESET != byten)
+        {
+            reg = spi_periph + 0x0CU;
+            return (uint16_t)(*(uint8_t *)(reg));
+        }else
+        {
+            return ((uint16_t)SPI_DATA(spi_periph));
+        }
+    }
+}
+
+/*!
+    \brief      configure SPI bidirectional transfer direction
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  transfer_direction: SPI transfer direction
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
+      \arg        SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
+    \param[out] none
+    \retval     none
+*/
+void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
+{
+    if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
+        /* set the transmit-only mode */
+        SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
+    }else{
+        /* set the receive-only mode */
+        SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
+    }
+}
+
+/*!
+    \brief      set SPI CRC polynomial 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  crc_poly: CRC polynomial value
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
+{
+    /* enable SPI CRC */
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
+    /* set SPI CRC polynomial */
+    SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
+}
+
+/*!
+    \brief      get SPI CRC polynomial 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     16-bit CRC polynomial
+*/
+uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
+{
+    return ((uint16_t)SPI_CRCPOLY(spi_periph));
+}
+
+/*!
+    \brief      turn on CRC function 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_on(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
+}
+
+/*!
+    \brief      turn off CRC function 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_off(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
+}
+
+/*!
+    \brief      SPI next data is CRC value
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_next(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
+}
+
+/*!
+    \brief      get SPI CRC send value or receive value
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  crc: SPI crc value
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_CRC_TX: get transmit crc value
+      \arg        SPI_CRC_RX: get receive crc value
+    \param[out] none
+    \retval     16-bit CRC value
+*/
+uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
+{
+    if(SPI_CRC_TX == crc){
+        return ((uint16_t)(SPI_TCRC(spi_periph)));
+    }else{
+        return ((uint16_t)(SPI_RCRC(spi_periph)));
+    }
+}
+
+/*!
+    \brief      enable SPI TI mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_ti_mode_enable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
+}
+
+/*!
+    \brief      disable SPI TI mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_ti_mode_disable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
+}
+
+/*!
+    \brief      enable SPI NSS pulse mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_nssp_mode_enable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
+}
+
+/*!
+    \brief      disable SPI NSS pulse mode
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_nssp_mode_disable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
+}
+
+/*!
+    \brief      enable quad wire SPI
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[out] none
+    \retval     none
+*/
+void qspi_enable(uint32_t spi_periph)
+{
+    SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
+}
+
+/*!
+    \brief      disable quad wire SPI 
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[out] none
+    \retval     none
+*/
+void qspi_disable(uint32_t spi_periph)
+{
+    SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
+}
+
+/*!
+    \brief      enable quad wire SPI write 
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[out] none
+    \retval     none
+*/
+void qspi_write_enable(uint32_t spi_periph)
+{
+    SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
+}
+
+/*!
+    \brief      enable quad wire SPI read 
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[out] none
+    \retval     none
+*/
+void qspi_read_enable(uint32_t spi_periph)
+{
+    SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
+}
+
+/*!
+    \brief      enable SPI_IO2 and SPI_IO3 pin output 
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[out] none
+    \retval     none
+*/
+void qspi_io23_output_enable(uint32_t spi_periph)
+{
+    SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
+}
+
+ /*!
+    \brief      disable SPI_IO2 and SPI_IO3 pin output 
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[out] none
+    \retval     none
+*/
+ void qspi_io23_output_disable(uint32_t spi_periph)
+{
+    SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
+}
+
+/*!
+    \brief      enable SPI and I2S interrupt 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  interrupt: SPI/I2S interrupt
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
+      \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
+      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
+                                   transmission underrun error and format error interrupt
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
+{
+    switch(interrupt){
+    /* SPI/I2S transmit buffer empty interrupt */
+    case SPI_I2S_INT_TBE:
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
+        break;
+    /* SPI/I2S receive buffer not empty interrupt */
+    case SPI_I2S_INT_RBNE:
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
+        break;
+    /* SPI/I2S error */
+    case SPI_I2S_INT_ERR:
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      disable SPI and I2S interrupt 
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  interrupt: SPI/I2S interrupt
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
+      \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
+      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
+                                   transmission underrun error and format error interrupt
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
+{
+    switch(interrupt){
+    /* SPI/I2S transmit buffer empty interrupt */
+    case SPI_I2S_INT_TBE:
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
+        break;
+    /* SPI/I2S receive buffer not empty interrupt */
+    case SPI_I2S_INT_RBNE:
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
+        break;
+    /* SPI/I2S error */
+    case SPI_I2S_INT_ERR:
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
+        break;
+    default :
+        break;
+    }
+}
+
+/*!
+    \brief      get SPI and I2S interrupt flag status
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  interrupt: SPI/I2S interrupt flag status
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
+      \arg        SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
+      \arg        SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
+      \arg        SPI_INT_FLAG_CONFERR: config error interrupt flag
+      \arg        SPI_INT_FLAG_CRCERR: CRC error interrupt flag
+      \arg        I2S_INT_FLAG_TXURERR: underrun error interrupt flag
+      \arg        SPI_I2S_INT_FLAG_FERR: format error interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
+{
+    uint32_t reg1 = SPI_STAT(spi_periph);
+    uint32_t reg2 = SPI_CTL1(spi_periph);
+
+    switch(interrupt){
+    /* SPI/I2S transmit buffer empty interrupt */
+    case SPI_I2S_INT_FLAG_TBE:
+        reg1 = reg1 & SPI_STAT_TBE;
+        reg2 = reg2 & SPI_CTL1_TBEIE;
+        break;
+    /* SPI/I2S receive buffer not empty interrupt */
+    case SPI_I2S_INT_FLAG_RBNE:
+        reg1 = reg1 & SPI_STAT_RBNE;
+        reg2 = reg2 & SPI_CTL1_RBNEIE;
+        break;
+    /* SPI/I2S overrun interrupt */
+    case SPI_I2S_INT_FLAG_RXORERR:
+        reg1 = reg1 & SPI_STAT_RXORERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    /* SPI config error interrupt */
+    case SPI_INT_FLAG_CONFERR:
+        reg1 = reg1 & SPI_STAT_CONFERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    /* SPI CRC error interrupt */
+    case SPI_INT_FLAG_CRCERR:
+        reg1 = reg1 & SPI_STAT_CRCERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    /* I2S underrun error interrupt */
+    case I2S_INT_FLAG_TXURERR:
+        reg1 = reg1 & SPI_STAT_TXURERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    /* SPI/I2S format error interrupt */
+    case SPI_I2S_INT_FLAG_FERR:
+        reg1 = reg1 & SPI_STAT_FERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    default :
+        break;
+    }
+    /*get SPI/I2S interrupt flag status */
+    if((0U != reg1) && (0U != reg2)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      get SPI and I2S flag status
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[in]  flag: SPI/I2S flag status
+                one or more parameters can be selected which are shown as below:
+      \arg        SPI_FLAG_TBE: transmit buffer empty flag
+      \arg        SPI_FLAG_RBNE: receive buffer not empty flag
+      \arg        SPI_FLAG_TRANS: transmit on-going flag
+      \arg        SPI_FLAG_RXORERR: receive overrun error flag
+      \arg        SPI_FLAG_CONFERR: mode config error flag
+      \arg        SPI_FLAG_CRCERR: CRC error flag
+      \arg        SPI_FLAG_FERR: format error interrupt flag
+      \arg        I2S_FLAG_TBE: transmit buffer empty flag
+      \arg        I2S_FLAG_RBNE: receive buffer not empty flag
+      \arg        I2S_FLAG_TRANS: transmit on-going flag
+      \arg        I2S_FLAG_RXORERR: overrun error flag
+      \arg        I2S_FLAG_TXURERR: underrun error flag
+      \arg        I2S_FLAG_CH: channel side flag
+                only for SPI1:
+      \arg        SPI_TXLVL_EMPTY: SPI TXFIFO is empty
+      \arg        SPI_TXLVL_QUARTER_FULL: SPI TXFIFO is a quarter of full
+      \arg        SPI_TXLVL_HAlF_FULL: SPI TXFIFO is a half of full
+      \arg        SPI_TXLVL_FULL: SPI TXFIFO is full
+      \arg        SPI_RXLVL_EMPTY: SPI RXFIFO is empty
+      \arg        SPI_RXLVL_QUARTER_FULL: SPI RXFIFO is a quarter of full
+      \arg        SPI_RXLVL_HAlF_FULL: SPI RXFIFO is a half of full
+      \arg        SPI_RXLVL_FULL: SPI RXFIFO is full
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
+{
+    if(RESET != (SPI_STAT(spi_periph) & flag)){
+        return SET;
+    }else{
+        if(SPI1 == spi_periph){
+            /* check TXFIFO is empty or not */
+            if(SPI_TXLVL_EMPTY == flag){
+                if(RESET != (SPI_STAT(spi_periph) & SPI_TXLVL_EMPTY_MASK)){
+                    return RESET;
+                }else{
+                    return SET;
+                }
+            }
+            /* check RXFIFO is empty or not */
+            if(SPI_RXLVL_EMPTY == flag){
+                if(RESET != (SPI_STAT(spi_periph) & SPI_RXLVL_EMPTY_MASK)){
+                    return RESET;
+                }else{
+                    return SET;
+                }
+            }
+        }
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear SPI CRC error flag status
+    \param[in]  spi_periph: SPIx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_error_clear(uint32_t spi_periph)
+{
+    SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
+}
+
+/*!
+    \brief      configure SPI1 access size to FIFO(8bit or 16bit)
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[in]  fifo_access_size: byte access enable
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_HALFWORD_ACCESS: half-word access to FIFO
+      \arg        SPI_BYTE_ACCESS: byte access to FIFO
+    \param[out] none
+    \retval     none
+*/
+void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size)
+{
+    /* clear SPI_CTL1_BYTEN bit */
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_BYTEN);
+    /* confige SPI_CTL1_BYTEN bit */
+    SPI_CTL1(spi_periph) |= (uint32_t)fifo_access_size;
+}
+
+/*!
+    \brief      configure SPI1 total number of data to transmit by DMA is odd or not
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[in]  odd: odd bytes in TX DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_TXDMA_EVEN: number of byte in TX DMA channel is even
+      \arg        SPI_TXDMA_ODD: number of byte in TX DMA channel is odd
+    \param[out] none
+    \retval     none
+*/
+void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd)
+{
+    /* clear SPI_CTL1_TXDMA_ODD bit */
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TXDMA_ODD);
+    /* confige SPI_CTL1_TXDMA_ODD bit */
+    SPI_CTL1(spi_periph) |= (uint32_t)odd;
+}
+
+/*!
+    \brief      configure SPI1 total number of data to receive by DMA is odd or not
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[in]  odd: odd bytes in RX DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_RXDMA_EVEN: number of bytes in RX DMA channel is even
+      \arg        SPI_RXDMA_ODD: number of bytes in RX DMA channel is odd
+    \param[out] none
+    \retval     none
+*/
+void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd)
+{
+    /* clear SPI_CTL1_RXDMA_ODD bit */
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RXDMA_ODD);
+    /* confige SPI_CTL1_RXDMA_ODD bit */
+    SPI_CTL1(spi_periph) |= (uint32_t)odd;
+}
+
+/*!
+    \brief      set CRC length
+    \param[in]  spi_periph: SPIx(x=1)
+    \param[in]  crc_length: CRC length
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_CRC_8BIT: CRC length is 8 bits
+      \arg        SPI_CRC_16BIT: CRC length is 16 bits
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length)
+{
+    /* clear SPI_CTL0_CRCL bit */
+    SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCL);
+    /* confige SPI_CTL0_CRCL bit */
+    SPI_CTL0(spi_periph) |= (uint32_t)crc_length;
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_syscfg.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_syscfg.c
new file mode 100644
index 0000000000..a0e79e4176
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_syscfg.c
@@ -0,0 +1,207 @@
+ /*!
+    \file    gd32e230_syscfg.h
+    \brief   SYSCFG driver
+
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_syscfg.h"
+
+/*!
+    \brief      reset the SYSCFG registers
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void syscfg_deinit(void)
+{
+    rcu_periph_reset_enable(RCU_CFGCMPRST);
+    rcu_periph_reset_disable(RCU_CFGCMPRST);
+}
+
+/*!
+    \brief      enable the DMA channels remapping
+    \param[in]  syscfg_dma_remap: specify the DMA channels to remap
+      \arg        SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
+      \arg        SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
+      \arg        SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
+      \arg        SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
+      \arg        SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
+      \arg        SYSCFG_PA11_REMAP_PA12: remap PA11 PA12
+    \param[out] none
+    \retval     none
+*/
+void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
+{
+    SYSCFG_CFG0 |= syscfg_dma_remap;
+}
+
+/*!
+    \brief      disable the DMA channels remapping
+    \param[in]  syscfg_dma_remap: specify the DMA channels to remap
+      \arg        SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
+      \arg        SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
+      \arg        SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
+      \arg        SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
+      \arg        SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
+      \arg        SYSCFG_PA11_REMAP_PA12: remap PA11 PA12
+    \param[out] none
+    \retval     none
+*/
+void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap)
+{
+    SYSCFG_CFG0 &= ~syscfg_dma_remap;
+}
+
+/*!
+    \brief      enable PB9 high current capability
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void syscfg_high_current_enable(void)
+{
+    SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE;
+}
+
+/*!
+    \brief      disable PB9 high current capability
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void syscfg_high_current_disable(void)
+{
+    SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
+}
+
+/*!
+    \brief      configure the GPIO pin as EXTI Line
+    \param[in]  exti_port: specify the GPIO port used in EXTI
+      \arg        EXTI_SOURCE_GPIOx(x = A,B,C,F): EXTI GPIO port
+    \param[in]  exti_pin: specify the EXTI line
+      \arg        EXTI_SOURCE_PINx(GPIOA x = 0..15,GPIOB x = 0..15,GPIOC x = 13..15,GPIOF x = 0.1.6.7): EXTI GPIO pin
+    \param[out] none
+    \retval     none
+*/
+void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
+{
+    uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
+    uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
+
+    switch(exti_pin / EXTI_SS_JSTEP){
+    case EXTISS0:
+        /* clear EXTI source line(0..3) */
+        SYSCFG_EXTISS0 &= clear_exti_mask;
+        /* configure EXTI soure line(0..3) */
+        SYSCFG_EXTISS0 |= config_exti_mask;
+        break;
+    case EXTISS1:
+        /* clear EXTI soure line(4..7) */
+        SYSCFG_EXTISS1 &= clear_exti_mask;
+        /* configure EXTI soure line(4..7) */
+        SYSCFG_EXTISS1 |= config_exti_mask;
+        break;
+    case EXTISS2:
+        /* clear EXTI soure line(8..11) */
+        SYSCFG_EXTISS2 &= clear_exti_mask;
+        /* configure EXTI soure line(8..11) */
+        SYSCFG_EXTISS2 |= config_exti_mask;
+        break;
+    case EXTISS3:
+        /* clear EXTI soure line(12..15) */
+        SYSCFG_EXTISS3 &= clear_exti_mask;
+        /* configure EXTI soure line(12..15) */
+        SYSCFG_EXTISS3 |= config_exti_mask;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      connect TIMER0/14/15/16 break input to the selected parameter
+    \param[in]  syscfg_lock: Specify the parameter to be connected
+      \arg        SYSCFG_LOCK_LOCKUP: Cortex-M23 lockup output connected to the break input
+      \arg        SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input
+      \arg        SYSCFG_LOCK_LVD: LVD interrupt connected to the break input
+    \param[out] none
+    \retval     none
+*/
+void syscfg_lock_config(uint32_t syscfg_lock)
+{
+    SYSCFG_CFG2 |= syscfg_lock;
+}
+
+/*!
+    \brief      set the wait state counter value
+    \param[in]  irq_latency: IRQ_LATENCY value (0x00 - 0xFF)
+    \param[out] none
+    \retval     none
+*/
+void irq_latency_set(uint8_t irq_latency)
+{
+    uint32_t reg;
+    
+    reg = SYSCFG_CPU_IRQ_LAT &(~(uint32_t)SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY);
+    reg |= (uint32_t)(IRQ_LATENCY(irq_latency));
+    
+    SYSCFG_CPU_IRQ_LAT = (uint32_t)reg;
+}
+/*!
+    \brief      check if the specified flag in SYSCFG_CFG2 is set or not.
+    \param[in]  syscfg_flag: specify the flag in SYSCFG_CFG2 to check.
+      \arg        SYSCFG_SRAM_PCEF: SRAM parity check error flag.
+    \param[out] none
+    \retval     the syscfg_flag state returned (SET or RESET).
+  */
+FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
+{
+    if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear the flag in SYSCFG_CFG2 by writing 1.
+    \param[in]  syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear.
+      \arg        SYSCFG_SRAM_PCEF: SRAM parity check error flag.
+    \param[out] none
+    \retval     none
+*/
+void syscfg_flag_clear(uint32_t syscfg_flag)
+{
+    SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
+}
+
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_timer.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_timer.c
new file mode 100644
index 0000000000..3fce2c47f8
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_timer.c
@@ -0,0 +1,2059 @@
+/*!
+    \file    gd32e230_timer.c
+    \brief   TIMER driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_timer.h"
+
+/* TIMER init parameter mask */
+#define ALIGNEDMODE_MASK            ((uint32_t)0x00000060U)   /*!< TIMER init parameter aligne dmode mask */
+#define COUNTERDIRECTION_MASK       ((uint32_t)0x00000010U)   /*!< TIMER init parameter counter direction mask */
+#define CLOCKDIVISION_MASK          ((uint32_t)0x00000300U)   /*!< TIMER init parameter clock division value mask */
+
+/*!
+    \brief      deinit a TIMER
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_deinit(uint32_t timer_periph)
+{
+    switch(timer_periph){
+    case TIMER0:
+        /* reset TIMER0 */
+        rcu_periph_reset_enable(RCU_TIMER0RST);
+        rcu_periph_reset_disable(RCU_TIMER0RST);
+        break;
+    case TIMER2:
+        /* reset TIMER2 */
+        rcu_periph_reset_enable(RCU_TIMER2RST);
+        rcu_periph_reset_disable(RCU_TIMER2RST);
+        break;
+    case TIMER5:
+        /* reset TIMER5 */
+        rcu_periph_reset_enable(RCU_TIMER5RST);
+        rcu_periph_reset_disable(RCU_TIMER5RST);
+        break;
+    case TIMER13:
+        /* reset TIMER13 */
+        rcu_periph_reset_enable(RCU_TIMER13RST);
+        rcu_periph_reset_disable(RCU_TIMER13RST);
+        break;
+    case TIMER14:
+        /* reset TIMER14 */
+        rcu_periph_reset_enable(RCU_TIMER14RST);
+        rcu_periph_reset_disable(RCU_TIMER14RST);
+        break;
+    case TIMER15:
+        /* reset TIMER15 */
+        rcu_periph_reset_enable(RCU_TIMER15RST);
+        rcu_periph_reset_disable(RCU_TIMER15RST);
+        break;
+    case TIMER16:
+        /* reset TIMER16 */
+        rcu_periph_reset_enable(RCU_TIMER16RST);
+        rcu_periph_reset_disable(RCU_TIMER16RST);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      initialize TIMER init parameter struct with a default value
+    \param[in]  initpara: init parameter struct
+    \param[out] none
+    \retval     none
+*/
+void timer_struct_para_init(timer_parameter_struct* initpara)
+{
+    /* initialize the init parameter struct member with the default value */
+    initpara->prescaler         = 0U;
+    initpara->alignedmode       = TIMER_COUNTER_EDGE;
+    initpara->counterdirection  = TIMER_COUNTER_UP;
+    initpara->period            = 65535U;
+    initpara->clockdivision     = TIMER_CKDIV_DIV1;
+    initpara->repetitioncounter = 0U;
+}
+
+/*!
+    \brief      initialize TIMER counter
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[in]  initpara: init parameter struct
+                  prescaler: prescaler value of the counter clock, 0~65535
+                  alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH
+                  counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN
+                  period: counter auto reload value, 0~65535
+                  clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4
+                  repetitioncounter: counter repetition value, 0~255
+    \param[out] none
+    \retval     none
+*/
+void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
+{
+    /* configure the counter prescaler value */
+    TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
+
+    /* configure the counter direction and aligned mode */
+    if((TIMER0 == timer_periph) || (TIMER2 == timer_periph)){
+        TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM);
+        TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
+        TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
+    }
+
+    /* configure the autoreload value */
+    TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
+    
+    if((TIMER0 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph)
+        || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
+        /* reset the CKDIV bit */
+        TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
+        TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
+    }
+
+    if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
+        /* configure the repetition counter value */
+        TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
+    }
+
+    /* generate an update event */
+    TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
+}
+
+/*!
+    \brief      enable a TIMER
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_enable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
+}
+
+/*!
+    \brief      disable a TIMER
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_disable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
+}
+
+/*!
+    \brief      enable the auto reload shadow function
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_auto_reload_shadow_enable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
+}
+
+/*!
+    \brief      disable the auto reload shadow function
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_auto_reload_shadow_disable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
+}
+
+/*!
+    \brief      enable the update event
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_update_event_enable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
+}
+
+/*!
+    \brief      disable the update event
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_update_event_disable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
+}
+
+/*!
+    \brief      set TIMER counter alignment mode
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[in]  aligned:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_COUNTER_EDGE: edge-aligned mode
+      \arg        TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
+      \arg        TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
+      \arg        TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
+    \param[out] none
+    \retval     none
+*/
+void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
+    TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
+}
+
+/*!
+    \brief      set TIMER counter up direction
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[out] none
+    \retval     none
+*/
+void timer_counter_up_direction(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
+}
+
+/*!
+    \brief      set TIMER counter down direction
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[out] none
+    \retval     none
+*/
+void timer_counter_down_direction(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
+}
+
+/*!
+    \brief      configure TIMER prescaler
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[in]  prescaler: prescaler value,0~65535
+    \param[in]  pscreload: prescaler reload mode
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
+      \arg        TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
+    \param[out] none
+    \retval     none
+*/
+void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
+{
+    TIMER_PSC(timer_periph) = (uint32_t)prescaler;
+    
+    if(TIMER_PSC_RELOAD_NOW == pscreload){
+        TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
+    }
+}
+
+/*!
+    \brief      configure TIMER repetition register value
+    \param[in]  timer_periph: TIMERx(x=0,15,16)
+    \param[in]  repetition: the counter repetition value,0~255
+    \param[out] none
+    \retval     none
+*/
+void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
+{
+    TIMER_CREP(timer_periph) = (uint32_t)repetition;
+} 
+ 
+/*!
+    \brief      configure TIMER autoreload register value
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[in]  autoreload: the counter auto-reload value,0~65535
+    \param[out] none
+    \retval     none
+*/         
+void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
+{
+    TIMER_CAR(timer_periph) = (uint32_t)autoreload;
+}
+
+/*!
+    \brief      configure TIMER counter register value
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[in]  counter: the counter value,0~65535
+    \param[out] none
+    \retval     none
+*/         
+void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
+{
+    TIMER_CNT(timer_periph) = (uint32_t)counter;
+}
+
+/*!
+    \brief      read TIMER counter value
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     counter value
+*/         
+uint32_t timer_counter_read(uint32_t timer_periph)
+{
+    uint32_t count_value = 0U;
+    count_value = TIMER_CNT(timer_periph);
+    return (count_value);
+}
+
+/*!
+    \brief      read TIMER prescaler value
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[out] none
+    \retval     prescaler register value
+*/         
+uint16_t timer_prescaler_read(uint32_t timer_periph)
+{
+    uint16_t prescaler_value = 0U;
+    prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
+    return (prescaler_value);
+}
+
+/*!
+    \brief      configure TIMER single pulse mode
+    \param[in]  timer_periph: TIMERx(x=0,2,5,14..16)
+    \param[in]  spmode:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_SP_MODE_SINGLE: single pulse mode
+      \arg        TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
+    \param[out] none
+    \retval     none
+*/
+void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
+{
+    if(TIMER_SP_MODE_SINGLE == spmode){
+        TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
+    }else if(TIMER_SP_MODE_REPETITIVE == spmode){
+        TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      configure TIMER update source 
+    \param[in]  timer_periph: TIMERx(x=0,2,5,13..16)
+    \param[in]  update:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
+      \arg        TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
+    \param[out] none
+    \retval     none
+*/
+void timer_update_source_config(uint32_t timer_periph, uint32_t update)
+{
+    if(TIMER_UPDATE_SRC_REGULAR == update){
+        TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
+    }else if(TIMER_UPDATE_SRC_GLOBAL == update){
+        TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      configure TIMER OCPRE clear source selection
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[in]  ocpreclear:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input
+      \arg        TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF
+    \param[out] none
+    \retval     none
+*/
+void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear)
+{
+    if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){
+        TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC;
+    }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){
+        TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      enable the TIMER interrupt
+    \param[in]  timer_periph: please refer to the following parameters 
+    \param[in]  interrupt: timer interrupt enable source
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,5,13..16)
+      \arg        TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0,2,13..16)
+      \arg        TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0,2,14)
+      \arg        TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0,2)
+      \arg        TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0,2)
+      \arg        TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16)
+      \arg        TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0,2,14)
+      \arg        TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
+{
+    TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; 
+}
+
+/*!
+    \brief      disable the TIMER interrupt
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  interrupt: timer interrupt source disable
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,5,13..16)
+      \arg        TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0,2,13..16)
+      \arg        TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0,2,14)
+      \arg        TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0,2)
+      \arg        TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0,2)
+      \arg        TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16)
+      \arg        TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0,2,14)
+      \arg        TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
+{
+    TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); 
+}
+
+/*!
+    \brief      get timer interrupt flag
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  interrupt: the timer interrupt bits
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0,2,5,13..16)
+      \arg        TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0,2,13..16)
+      \arg        TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0,2,14)
+      \arg        TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0,2)
+      \arg        TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0,2)
+      \arg        TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16)
+      \arg        TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,2,14)
+      \arg        TIMER_INT_FLAG_BRK:  break interrupt flag,TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
+{
+    uint32_t val;
+    val = (TIMER_DMAINTEN(timer_periph) & interrupt);
+    if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear TIMER interrupt flag
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  interrupt: the timer interrupt bits
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0,2,5,13..16)
+      \arg        TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0,2,13..16)
+      \arg        TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0,2,14)
+      \arg        TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0,2)
+      \arg        TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0,2)
+      \arg        TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16)
+      \arg        TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,2,14)
+      \arg        TIMER_INT_FLAG_BRK:  break interrupt flag, TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
+{
+    TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt);
+}
+
+/*!
+    \brief      get TIMER flags
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  flag: the timer interrupt flags
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_FLAG_UP: update flag, TIMERx(x=0,2,5,13..16)
+      \arg        TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0,2,13..16)
+      \arg        TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0,2,14)
+      \arg        TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0,2)
+      \arg        TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0,2)
+      \arg        TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16)
+      \arg        TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,2,14)
+      \arg        TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16)
+      \arg        TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,2,13..16)
+      \arg        TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,2,14)
+      \arg        TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,2)
+      \arg        TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,2)
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
+{
+    if(RESET != (TIMER_INTF(timer_periph) & flag)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear TIMER flags
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  flag: the timer interrupt flags
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_FLAG_UP: update flag, TIMERx(x=0,2,5,13..16)
+      \arg        TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0,2,13..16)
+      \arg        TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0,2,14)
+      \arg        TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0,2)
+      \arg        TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0,2)
+      \arg        TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16)
+      \arg        TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,2,14)
+      \arg        TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16)
+      \arg        TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,2,13..16)
+      \arg        TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,2,14)
+      \arg        TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,2)
+      \arg        TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,2)
+    \param[out] none
+    \retval     none
+*/
+void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
+{
+    TIMER_INTF(timer_periph) &= (~(uint32_t)flag);
+}
+
+/*!
+    \brief      enable the TIMER DMA
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  dma: specify which DMA to enable
+                one or more parameters can be selected which is shown as below:
+      \arg        TIMER_DMA_UPD: update DMA, TIMERx(x=0,2,5,14..16)
+      \arg        TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0,2,14..16)
+      \arg        TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,2,14)
+      \arg        TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,2)
+      \arg        TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,2)
+      \arg        TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14)
+      \arg        TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0,2,14)
+    \param[out] none
+    \retval     none
+*/
+void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
+{
+    TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; 
+}
+
+/*!
+    \brief      disable the TIMER DMA
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  dma: specify which DMA to disable
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_DMA_UPD: update DMA, TIMERx(x=0,2,5,14..16)
+      \arg        TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0,2,14..16)
+      \arg        TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,2,14)
+      \arg        TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,2)
+      \arg        TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,2)
+      \arg        TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14)
+      \arg        TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0,2,14)
+    \param[out] none
+    \retval     none
+*/
+void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
+{
+    TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); 
+}
+
+/*!
+    \brief      channel DMA request source selection
+    \param[in]  timer_periph: TIMERx(x=0,2,14..16)
+    \param[in]  dma_request: channel DMA request source selection
+                only one parameter can be selected which is shown as below:
+       \arg        TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
+       \arg        TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs 
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
+{
+    if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
+        TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
+    }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
+        TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      configure the TIMER DMA transfer
+    \param[in]  timer_periph: TIMERx(x=0,2,14..16)
+    \param[in]  dma_baseaddr:
+                only one parameter can be selected which is shown as below:
+       \arg        TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0,2,14)
+       \arg        TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0,2)
+       \arg        TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16)
+       \arg        TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0,2,14..16)
+       \arg        TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0,2,14)
+       \arg        TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0,2)
+       \arg        TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0,2)
+       \arg        TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16)
+       \arg        TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0,2,14..16)
+    \param[in]  dma_lenth:
+                only one parameter can be selected which is shown as below:
+       \arg        TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
+    \param[out] none
+    \retval     none
+*/
+void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
+{
+    TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
+    TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
+}
+
+/*!
+    \brief      software generate events 
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  event: the timer software event generation sources
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0,2,5,13..16)
+      \arg        TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0,2,13..16) 
+      \arg        TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0,2,14)
+      \arg        TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0,2) 
+      \arg        TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0,2) 
+      \arg        TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16) 
+      \arg        TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0,2,14)
+      \arg        TIMER_EVENT_SRC_BRKG:  break event generation, TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
+{
+    TIMER_SWEVG(timer_periph) |= (uint32_t)event;
+}
+
+/*!
+    \brief      initialize TIMER break parameter struct with a default value
+    \param[in]  breakpara: TIMER break parameter struct
+    \param[out] none
+    \retval     none
+*/
+void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
+{
+    /* initialize the break parameter struct member with the default value */
+    breakpara->runoffstate     = TIMER_ROS_STATE_DISABLE;
+    breakpara->ideloffstate    = TIMER_IOS_STATE_DISABLE;
+    breakpara->deadtime        = 0U;
+    breakpara->breakpolarity   = TIMER_BREAK_POLARITY_LOW;
+    breakpara->outputautostate = TIMER_OUTAUTO_DISABLE;
+    breakpara->protectmode     = TIMER_CCHP_PROT_OFF;
+    breakpara->breakstate      = TIMER_BREAK_DISABLE;
+}
+
+/*!
+    \brief      configure TIMER break function 
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[in]  breakpara: TIMER break parameter struct
+                runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE
+                ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE
+                deadtime: 0~255
+                breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH
+                outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE
+                protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2
+                breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
+    \param[out] none
+    \retval     none
+*/
+void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
+{
+    TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))|
+                                          ((uint32_t)(breakpara->ideloffstate))|
+                                          ((uint32_t)(breakpara->deadtime))|
+                                          ((uint32_t)(breakpara->breakpolarity))|
+                                          ((uint32_t)(breakpara->outputautostate)) |
+                                          ((uint32_t)(breakpara->protectmode))|
+                                          ((uint32_t)(breakpara->breakstate))) ;
+}
+
+/*!
+    \brief      enable TIMER break function
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_break_enable(uint32_t timer_periph)
+{
+    TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
+}
+
+/*!
+    \brief      disable TIMER break function
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_break_disable(uint32_t timer_periph)
+{
+    TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
+}
+
+/*!
+    \brief      enable TIMER output automatic function
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_automatic_output_enable(uint32_t timer_periph)
+{
+    TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
+}
+
+/*!
+    \brief      disable TIMER output automatic function
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[out] none
+    \retval     none
+*/
+void timer_automatic_output_disable(uint32_t timer_periph)
+{
+    TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
+}
+
+/*!
+    \brief      configure TIMER primary output function
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[in]  newvalue: ENABLE or DISABLE
+    \param[out] none
+    \retval     none
+*/
+void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
+{
+    if(ENABLE == newvalue){
+        TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
+    }else{
+        TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
+    }
+}
+
+/*!
+    \brief      enable or disable channel capture/compare control shadow register
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[in]  newvalue: ENABLE or DISABLE 
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
+{
+     if(ENABLE == newvalue){
+        TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
+    }else{
+        TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
+    }
+}
+
+/*!
+    \brief      configure TIMER channel control shadow register update control
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[in]  ccuctl: channel control shadow register update control
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
+      \arg        TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs 
+    \param[out] none
+    \retval     none
+*/              
+void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
+{
+    if(TIMER_UPDATECTL_CCU == ccuctl){
+        TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
+    }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
+        TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      initialize TIMER channel output parameter struct with a default value
+    \param[in]  ocpara: TIMER channel n output parameter struct
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
+{
+    /* initialize the channel output parameter struct member with the default value */
+    ocpara->outputstate  = (uint16_t)TIMER_CCX_DISABLE;
+    ocpara->outputnstate = TIMER_CCXN_DISABLE;
+    ocpara->ocpolarity   = TIMER_OC_POLARITY_HIGH;
+    ocpara->ocnpolarity  = TIMER_OCN_POLARITY_HIGH;
+    ocpara->ocidlestate  = TIMER_OC_IDLE_STATE_LOW;
+    ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
+}
+
+/*!
+    \brief      configure TIMER channel output function
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0,2))
+    \param[in]  ocpara: TIMER channeln output parameter struct
+                outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE
+                outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE
+                ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW
+                ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW
+                ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH
+                ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
+        /* reset the CH0P bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
+        /* set the CH0P bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
+
+        if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
+            /* reset the CH0NEN bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
+            /* set the CH0NEN bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
+            /* reset the CH0NP bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
+            /* set the CH0NP bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
+            /* reset the ISO0 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
+            /* set the ISO0 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
+            /* reset the ISO0N bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
+            /* set the ISO0N bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
+        }
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U);
+        /* reset the CH1P bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
+        /* set the CH1P bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
+
+        if(TIMER0 == timer_periph){
+            /* reset the CH1NEN bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
+            /* set the CH1NEN bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
+            /* reset the CH1NP bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
+            /* set the CH1NP bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
+            /* reset the ISO1 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
+            /* set the ISO1 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
+            /* reset the ISO1N bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
+            /* set the ISO1N bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
+        }
+        
+        if(TIMER14 == timer_periph){
+            /* reset the ISO1 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
+            /* set the ISO1 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
+        }
+        
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        /* reset the CH2EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+        TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
+        /* set the CH2EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U);
+        /* reset the CH2P bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
+        /* set the CH2P bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
+
+        if(TIMER0 == timer_periph){
+            /* reset the CH2NEN bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
+            /* set the CH2NEN bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
+            /* reset the CH2NP bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
+            /* set the CH2NP bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
+            /* reset the ISO2 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
+            /* set the ISO2 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
+            /* reset the ISO2N bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
+            /* set the ISO2N bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
+        }
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        /* reset the CH3EN bit */
+        TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
+        TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
+        /* set the CH3EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U);
+        /* reset the CH3P bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
+        /* set the CH3P bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
+
+        if(TIMER0 == timer_periph){
+            /* reset the ISO3 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
+            /* set the ISO3 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output compare mode
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[in]  ocmode: channel output compare mode
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_MODE_TIMING: timing mode
+      \arg        TIMER_OC_MODE_ACTIVE: active mode
+      \arg        TIMER_OC_MODE_INACTIVE: inactive mode
+      \arg        TIMER_OC_MODE_TOGGLE: toggle mode
+      \arg        TIMER_OC_MODE_LOW: force low mode
+      \arg        TIMER_OC_MODE_HIGH: force high mode
+      \arg        TIMER_OC_MODE_PWM0: PWM0 mode
+      \arg        TIMER_OC_MODE_PWM1: PWM1 mode
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output pulse value
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[in]  pulse: channel output pulse value,0~65535
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+         TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output shadow function
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[in]  ocshadow: channel output shadow state
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
+      \arg        TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output fast function
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[in]  ocfast: channel output fast function
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_FAST_ENABLE: channel output fast function enable
+      \arg        TIMER_OC_FAST_DISABLE: channel output fast function disable
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output clear function
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[in]  occlear: channel output clear function
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_CLEAR_ENABLE: channel output clear function enable
+      \arg        TIMER_OC_CLEAR_DISABLE: channel output clear function disable
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output polarity 
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[in]  ocpolarity: channel output polarity 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_POLARITY_HIGH: channel output polarity is high
+      \arg        TIMER_OC_POLARITY_LOW: channel output polarity is low
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel complementary output polarity 
+    \param[in]  timer_periph: TIMERx(x=0,2,14)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel2(TIMERx(x=0,2))
+    \param[in]  ocnpolarity: channel complementary output polarity 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
+      \arg        TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel enable state
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[in]  state: TIMER channel enable state
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CCX_ENABLE: channel enable 
+      \arg        TIMER_CCX_DISABLE: channel disable 
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel complementary output enable state
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[in]  channel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0))
+    \param[in]  ocnstate: TIMER channel complementary output enable state
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CCXN_ENABLE: channel complementary enable 
+      \arg        TIMER_CCXN_DISABLE: channel complementary disable 
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      initialize TIMER channel input parameter struct with a default value
+    \param[in]  icpara: TIMER channel intput parameter struct
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
+{
+    /* initialize the channel input parameter struct member with the default value */
+    icpara->icpolarity  = TIMER_IC_POLARITY_RISING;
+    icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
+    icpara->icprescaler = TIMER_IC_PSC_DIV1;
+    icpara->icfilter    = 0U;
+}
+
+/*!
+    \brief      configure TIMER input capture parameter 
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+     \param[in]  icpara: TIMER channel intput parameter struct
+                 icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE
+                 icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS
+                 icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
+                 icfilter: 0~15
+    \param[out]  none
+    \retval      none
+*/
+void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+
+        /* reset the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
+        /* reset the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
+
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+        break;
+    
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+
+        /* reset the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
+        /* reset the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
+        /* reset the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
+
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        /* reset the CH2EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+
+        /* reset the CH2P and CH2NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
+
+        /* reset the CH2MS bit */
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
+
+        /* reset the CH2CAPFLT bit */
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
+
+        /* set the CH2EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        /* reset the CH3EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
+
+        /* reset the CH3P and CH3NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P|TIMER_CHCTL2_CH3NP));
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
+
+        /* reset the CH3MS bit */
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
+
+        /* reset the CH3CAPFLT bit */
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
+
+        /* set the CH3EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
+        break;
+    default:
+        break;
+    }
+    /* configure TIMER channel input capture prescaler value */
+    timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
+}
+
+/*!
+    \brief      configure TIMER channel input capture prescaler value
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[in]  prescaler: channel input capture prescaler value
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_IC_PSC_DIV1: no prescaler
+      \arg        TIMER_IC_PSC_DIV2: divided by 2
+      \arg        TIMER_IC_PSC_DIV4: divided by 4
+      \arg        TIMER_IC_PSC_DIV8: divided by 8
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
+        TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
+        TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      read TIMER channel capture compare register value
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16))
+      \arg        TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14))
+      \arg        TIMER_CH_2: TIMER channel2(TIMERx(x=0,2))
+      \arg        TIMER_CH_3: TIMER channel3(TIMERx(x=0,2))
+    \param[out] none
+    \retval     channel capture compare register value
+*/
+uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
+{
+    uint32_t count_value = 0U;
+
+    switch(channel){
+    /* read TIMER channel 0 capture compare register value */
+    case TIMER_CH_0:
+        count_value = TIMER_CH0CV(timer_periph);
+        break;
+    /* read TIMER channel 1 capture compare register value */
+    case TIMER_CH_1:
+        count_value = TIMER_CH1CV(timer_periph);
+        break;
+    /* read TIMER channel 2 capture compare register value */
+    case TIMER_CH_2:
+        count_value = TIMER_CH2CV(timer_periph);
+        break;
+    /* read TIMER channel 3 capture compare register value */
+    case TIMER_CH_3:
+        count_value = TIMER_CH3CV(timer_periph);
+        break;
+    default:
+        break;
+    }
+    return (count_value);
+}
+
+/*!
+    \brief      configure TIMER input pwm capture function 
+    \param[in]  timer_periph: TIMERx(x=0,2,14)
+    \param[in]  channel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel0
+      \arg        TIMER_CH_1: TIMER channel1
+     \param[in]  icpwm:TIMER channel intput pwm parameter struct
+                 icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING
+                 icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI
+                 icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
+                 icfilter: 0~15
+    \param[out] none
+    \retval     none
+*/
+void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
+{
+    uint16_t icpolarity  = 0x0U;
+    uint16_t icselection = 0x0U;
+
+    /* Set channel input polarity */
+    if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
+        icpolarity = TIMER_IC_POLARITY_FALLING;
+    }else{
+        icpolarity = TIMER_IC_POLARITY_RISING;
+    }
+
+    /* Set channel input mode selection */
+    if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
+        icselection = TIMER_IC_SELECTION_INDIRECTTI;
+    }else{
+        icselection = TIMER_IC_SELECTION_DIRECTTI;
+    }
+
+    if(TIMER_CH_0 == channel){
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        /* reset the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+        /* set the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
+        /* reset the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+        /* set the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+        /* set the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+        /* configure TIMER channel input capture prescaler value */
+        timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler));
+
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        /* reset the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+        /* set the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U);
+        /* reset the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+        /* set the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
+        /* reset the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+        /* set the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+        /* configure TIMER channel input capture prescaler value */
+        timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler));
+    }else{
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        /* reset the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+        /* set the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
+        /* reset the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+        /* set the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
+        /* reset the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+        /* set the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+        /* configure TIMER channel input capture prescaler value */
+        timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
+
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        /* reset the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+        /* set the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
+        /* reset the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+        /* set the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+        /* set the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+        /* configure TIMER channel input capture prescaler value */
+        timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
+    }
+}
+
+/*!
+    \brief      configure TIMER hall sensor mode
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[in]  hallmode: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
+      \arg        TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
+    \param[out] none
+    \retval     none
+*/
+void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
+{
+    if(TIMER_HALLINTERFACE_ENABLE == hallmode){
+        TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
+    }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
+        TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      select TIMER input trigger source 
+    \param[in]  timer_periph: TIMERx(x=0,2,14)
+    \param[in]  intrigger:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,2,14))
+      \arg        TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,2,14))
+      \arg        TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,2))
+      \arg        TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0,2,14))
+      \arg        TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0,2,14))
+      \arg        TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0,2,14))
+      \arg        TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0,2))
+    \param[out] none
+    \retval     none
+*/
+void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
+{
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
+    TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
+}
+
+/*!
+    \brief      select TIMER master mode output trigger source 
+    \param[in]  timer_periph: TIMERx(x=0,2,5,14)
+    \param[in]  outrigger:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0,2,5,14))
+      \arg        TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0,2,5,14))
+      \arg        TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0,2,5,14))
+      \arg        TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO
+      \arg        TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0,2,14))
+      \arg        TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0,2,14))
+      \arg        TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0,2,14))
+      \arg        TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0,2,14))
+    \param[out] none
+    \retval     none
+*/
+void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
+{
+    TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
+    TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
+}
+
+/*!
+    \brief      select TIMER slave mode 
+    \param[in]  timer_periph: TIMERx(x=0,2,14)
+    \param[in]  slavemode:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0,2,14))
+      \arg        TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0,2))
+      \arg        TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0,2))
+      \arg        TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0,2))
+      \arg        TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0,2,14))
+      \arg        TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0,2,14))
+      \arg        TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0,2,14))
+      \arg        TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0,2,14))
+    \param[out] none
+    \retval     none
+*/
+
+void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
+{
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+
+    TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
+}
+
+/*!
+    \brief      configure TIMER master slave mode 
+    \param[in]  timer_periph: TIMERx(x=0,2,14)
+    \param[in]  masterslave:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
+      \arg        TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
+    \param[out] none
+    \retval     none
+*/ 
+void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
+{
+    if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
+        TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
+    }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
+        TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      configure TIMER external trigger input
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[in]  extprescaler:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_EXT_TRI_PSC_OFF: no divided
+      \arg        TIMER_EXT_TRI_PSC_DIV2: divided by 2
+      \arg        TIMER_EXT_TRI_PSC_DIV4: divided by 4
+      \arg        TIMER_EXT_TRI_PSC_DIV8: divided by 8
+    \param[in]  extpolarity:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_ETP_FALLING: active low or falling edge active
+      \arg        TIMER_ETP_RISING: active high or rising edge active
+    \param[in]  extfilter: a value between 0 and 15
+    \param[out] none
+    \retval     none
+*/
+void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler,
+                                   uint32_t extpolarity, uint32_t extfilter)
+{
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
+    TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
+    TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
+}
+
+/*!
+    \brief      configure TIMER quadrature decoder mode
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[in]  decomode: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
+      \arg        TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
+      \arg        TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
+    \param[in]  ic0polarity: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_IC_POLARITY_RISING: capture rising edge
+      \arg        TIMER_IC_POLARITY_FALLING: capture falling edge
+    \param[in]  ic1polarity:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_IC_POLARITY_RISING: capture rising edge
+      \arg        TIMER_IC_POLARITY_FALLING: capture falling edge
+    \param[out] none
+    \retval     none
+*/
+void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode,
+                                   uint16_t ic0polarity, uint16_t ic1polarity)
+{
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+    TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
+
+    TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS)));
+    TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
+
+    TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+    TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+    TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U));
+}
+
+/*!
+    \brief      configure TIMER internal clock mode
+    \param[in]  timer_periph: TIMERx(x=0,2,14)
+    \param[out] none
+    \retval     none
+*/
+void timer_internal_clock_config(uint32_t timer_periph)
+{
+    TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
+}
+
+/*!
+    \brief      configure TIMER the internal trigger as external clock input
+    \param[in]  timer_periph: TIMERx(x=0,2,14)
+    \param[in]  intrigger: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,2,14))
+      \arg        TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,2,14))
+      \arg        TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,2))
+    \param[out] none
+    \retval     none
+*/
+void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
+{
+    timer_input_trigger_source_select(timer_periph, intrigger);
+    TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
+    TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+}
+
+/*!
+    \brief      configure TIMER the external trigger as external clock input
+    \param[in]  timer_periph: TIMERx(x=0,2,14)
+    \param[in]  extrigger: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
+      \arg        TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
+      \arg        TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
+    \param[in]  extpolarity: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_IC_POLARITY_RISING: active high or rising edge active
+      \arg        TIMER_IC_POLARITY_FALLING: active low or falling edge active
+      \arg        TIMER_IC_POLARITY_BOTH_EDGE: active both edge
+    \param[in]  extfilter: a value between 0 and 15
+    \param[out] none
+    \retval     none
+*/
+void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger,
+                                       uint16_t extpolarity, uint32_t extfilter)
+{
+    if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        /* reset the CH1NP bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+        /* set the CH1NP bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
+        /* reset the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+        /* set the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
+        /* reset the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+        /* set the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+    }else{
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        /* reset the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+        /* set the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
+        /* reset the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+        /* set the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+    }
+    /* select TIMER input trigger source */
+    timer_input_trigger_source_select(timer_periph,extrigger);
+    /* reset the SMC bit */
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+    /* set the SMC bit */
+    TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+}
+
+/*!
+    \brief      configure TIMER the external clock mode0
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[in]  extprescaler: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_EXT_TRI_PSC_OFF: no divided
+      \arg        TIMER_EXT_TRI_PSC_DIV2: divided by 2
+      \arg        TIMER_EXT_TRI_PSC_DIV4: divided by 4
+      \arg        TIMER_EXT_TRI_PSC_DIV8: divided by 8
+    \param[in]  extpolarity: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_ETP_FALLING: active low or falling edge active
+      \arg        TIMER_ETP_RISING: active high or rising edge active
+    \param[in]  extfilter: a value between 0 and 15
+    \param[out] none
+    \retval     none
+*/
+void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler,
+                                       uint32_t extpolarity, uint32_t extfilter)
+{
+    /* configure TIMER external trigger input */
+    timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
+
+    /* reset the SMC bit,TRGS bit */
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
+    /* set the SMC bit,TRGS bit */
+    TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
+}
+
+/*!
+    \brief      configure TIMER the external clock mode1
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[in]  extprescaler: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_EXT_TRI_PSC_OFF: no divided
+      \arg        TIMER_EXT_TRI_PSC_DIV2: divided by 2
+      \arg        TIMER_EXT_TRI_PSC_DIV4: divided by 4
+      \arg        TIMER_EXT_TRI_PSC_DIV8: divided by 8
+    \param[in]  extpolarity: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_ETP_FALLING: active low or falling edge active
+      \arg        TIMER_ETP_RISING: active high or rising edge active
+    \param[in]  extfilter: a value between 0 and 15
+    \param[out] none
+    \retval     none
+*/
+void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler,
+                                       uint32_t extpolarity, uint32_t extfilter)
+{
+    /* configure TIMER external trigger input */
+    timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
+
+    TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
+}
+
+/*!
+    \brief      disable TIMER the external clock mode1
+    \param[in]  timer_periph: TIMERx(x=0,2)
+    \param[out] none
+    \retval     none
+*/
+void timer_external_clock_mode1_disable(uint32_t timer_periph)
+{
+    TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
+}
+
+/*!
+    \brief      configure TIMER channel remap function
+    \param[in]  timer_periph: TIMERx(x=13)
+    \param[in]  remap: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0)
+      \arg        TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK
+      \arg        TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock
+      \arg        TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap)
+{
+    TIMER_IRMP(timer_periph) = (uint32_t)remap;
+}
+
+/*!
+    \brief      configure TIMER write CHxVAL register selection
+    \param[in]  timer_periph: TIMERx(x=0,2,13..16)
+    \param[in]  ccsel: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CHVSEL_DISABLE: no effect
+      \arg        TIMER_CHVSEL_ENABLE:  when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored
+    \param[out] none
+    \retval     none
+*/
+void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel)
+{
+    if(TIMER_CHVSEL_ENABLE == ccsel){
+        TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL;
+    }else if(TIMER_CHVSEL_DISABLE == ccsel){
+        TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      configure TIMER output value selection
+    \param[in]  timer_periph: TIMERx(x=0,14..16)
+    \param[in]  outsel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OUTSEL_DISABLE: no effect
+      \arg        TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled
+    \param[out] none
+    \retval     none
+*/
+void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
+{
+    if(TIMER_OUTSEL_ENABLE == outsel){
+        TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL;
+    }else if(TIMER_OUTSEL_DISABLE == outsel){
+        TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL;
+    }else{
+        /* illegal parameters */
+    }
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_usart.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_usart.c
new file mode 100644
index 0000000000..f73723e4be
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_usart.c
@@ -0,0 +1,1318 @@
+/*!
+    \file    gd32e230_usart.c
+    \brief   USART driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_usart.h"
+
+/*!
+    \brief      reset USART
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_deinit(uint32_t usart_periph)
+{
+    switch(usart_periph){
+    case USART0:
+        /* reset USART0 */
+        rcu_periph_reset_enable(RCU_USART0RST);
+        rcu_periph_reset_disable(RCU_USART0RST);
+        break;
+    case USART1:
+        /* reset USART1 */
+        rcu_periph_reset_enable(RCU_USART1RST);
+        rcu_periph_reset_disable(RCU_USART1RST);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure USART baud rate value
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  baudval: baud rate value
+    \param[out] none
+    \retval     none
+*/ 
+void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
+{
+    uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
+    switch(usart_periph){
+         /* get clock frequency */
+    case USART0:
+         /* get USART0 clock */
+         uclk = rcu_clock_freq_get(CK_USART);
+         break;
+    case USART1:
+         /* get USART1 clock */
+         uclk = rcu_clock_freq_get(CK_APB1);
+         break;
+    default:
+         break;
+    }
+    if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){
+        /* oversampling by 8, configure the value of USART_BAUD */
+        udiv = ((2U*uclk)+baudval/2U)/baudval;
+        intdiv = udiv & 0x0000fff0U;
+        fradiv = (udiv>>1U) & 0x00000007U;
+        USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
+    }else{
+        /* oversampling by 16, configure the value of USART_BAUD */
+        udiv = (uclk+baudval/2U)/baudval;
+        intdiv = udiv & 0x0000fff0U;
+        fradiv = udiv & 0x0000000fU;
+        USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
+    }
+}
+
+/*!
+    \brief      configure USART parity
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  paritycfg: USART parity configure
+                only one parameter can be selected which is shown as below:
+      \arg        USART_PM_NONE: no parity
+      \arg        USART_PM_ODD: odd parity
+      \arg        USART_PM_EVEN: even parity
+    \param[out] none
+    \retval     none
+*/
+void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* clear USART_CTL0 PM,PCEN bits */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); 
+    /* configure USART parity mode */
+    USART_CTL0(usart_periph) |= paritycfg;
+}
+
+/*!
+    \brief      configure USART word length
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  wlen: USART word length configure
+                only one parameter can be selected which is shown as below:
+      \arg        USART_WL_8BIT: 8 bits
+      \arg        USART_WL_9BIT: 9 bits
+    \param[out] none
+    \retval     none
+*/
+void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* clear USART_CTL0 WL bit */
+    USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
+    /* configure USART word length */
+    USART_CTL0(usart_periph) |= wlen;
+}
+
+/*!
+    \brief      configure USART stop bit length
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  stblen: USART stop bit configure
+                only one parameter can be selected which is shown as below:
+      \arg        USART_STB_1BIT: 1 bit
+      \arg        USART_STB_0_5BIT: 0.5bit
+      \arg        USART_STB_2BIT: 2 bits
+      \arg        USART_STB_1_5BIT: 1.5bit
+    \param[out] none
+    \retval     none
+*/
+void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* clear USART_CTL1 STB bits */
+    USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
+    USART_CTL1(usart_periph) |= stblen;
+}
+
+/*!
+    \brief      enable USART
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_enable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) |= USART_CTL0_UEN;
+}
+
+/*!
+    \brief      disable USART
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_disable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+}
+
+/*!
+    \brief      configure USART transmitter
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  txconfig: enable or disable USART transmitter
+                only one parameter can be selected which is shown as below:
+      \arg        USART_TRANSMIT_ENABLE: enable USART transmission
+      \arg        USART_TRANSMIT_DISABLE: enable USART transmission
+    \param[out] none
+    \retval     none
+*/
+void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
+{
+    USART_CTL0(usart_periph) &= ~USART_CTL0_TEN;
+    /* configure transfer mode */
+    USART_CTL0(usart_periph) |= txconfig;
+}
+
+/*!
+    \brief      configure USART receiver
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  rxconfig: enable or disable USART receiver
+                only one parameter can be selected which is shown as below:
+      \arg        USART_RECEIVE_ENABLE: enable USART reception
+      \arg        USART_RECEIVE_DISABLE: disable USART reception
+    \param[out] none
+    \retval     none
+*/
+void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
+{
+    USART_CTL0(usart_periph) &= ~USART_CTL0_REN;
+    /* configure receiver mode */
+    USART_CTL0(usart_periph) |= rxconfig;
+}
+
+/*!
+    \brief      data is transmitted/received with the LSB/MSB first
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  msbf: LSB/MSB
+                only one parameter can be selected which is shown as below:
+      \arg        USART_MSBF_LSB: LSB first
+      \arg        USART_MSBF_MSB: MSB first
+    \param[out] none
+    \retval     none
+*/
+void usart_data_first_config(uint32_t usart_periph, uint32_t msbf)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* configure LSB or MSB first */
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF);
+    USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf);
+}
+
+/*!
+    \brief      USART inverted configure
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  invertpara: refer to usart_invert_enum
+                only one parameter can be selected which is shown as below:
+      \arg        USART_DINV_ENABLE: data bit level inversion
+      \arg        USART_DINV_DISABLE: data bit level not inversion
+      \arg        USART_TXPIN_ENABLE: TX pin level inversion
+      \arg        USART_TXPIN_DISABLE: TX pin level not inversion
+      \arg        USART_RXPIN_ENABLE: RX pin level inversion
+      \arg        USART_RXPIN_DISABLE: RX pin level not inversion
+      \arg        USART_SWAP_ENABLE: swap TX/RX pins
+      \arg        USART_SWAP_DISABLE: not swap TX/RX pins
+    \param[out] none
+    \retval     none
+*/
+void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* inverted or not the specified signal */
+    switch(invertpara){
+    case USART_DINV_ENABLE:
+        USART_CTL1(usart_periph) |= USART_CTL1_DINV;
+        break;
+    case USART_DINV_DISABLE:
+        USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV);
+        break;
+    case USART_TXPIN_ENABLE:
+        USART_CTL1(usart_periph) |= USART_CTL1_TINV;
+        break;
+    case USART_TXPIN_DISABLE:
+        USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV);
+        break;
+    case USART_RXPIN_ENABLE:
+        USART_CTL1(usart_periph) |= USART_CTL1_RINV;
+        break;
+    case USART_RXPIN_DISABLE:
+        USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV);
+        break;
+    case USART_SWAP_ENABLE:
+        USART_CTL1(usart_periph) |= USART_CTL1_STRP;
+        break;
+    case USART_SWAP_DISABLE:
+        USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      enable the USART overrun function
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_overrun_enable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* enable overrun function */
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD);
+}
+
+/*!
+    \brief      disable the USART overrun function
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_overrun_disable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* disable overrun function */
+    USART_CTL2(usart_periph) |= USART_CTL2_OVRD;
+}
+
+/*!
+    \brief      configure the USART oversample mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  oversamp: oversample value
+                only one parameter can be selected which is shown as below:
+      \arg        USART_OVSMOD_8: oversampling by 8
+      \arg        USART_OVSMOD_16: oversampling by 16
+    \param[out] none
+    \retval     none
+*/
+void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* clear OVSMOD bit */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD);
+    USART_CTL0(usart_periph) |= oversamp;
+}
+
+/*!
+    \brief      configure the sample bit method
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  osb: sample bit
+                only one parameter can be selected which is shown as below:
+      \arg        USART_OSB_1BIT: 1 bit
+      \arg        USART_OSB_3BIT: 3 bits
+    \param[out] none
+    \retval     none
+*/
+void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB);
+    USART_CTL2(usart_periph) |= osb;
+}
+
+/*!
+    \brief      enable receiver timeout
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_receiver_timeout_enable(uint32_t usart_periph)
+{
+    USART_CTL1(usart_periph) |= USART_CTL1_RTEN;
+}
+
+/*!
+    \brief      disable receiver timeout
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_receiver_timeout_disable(uint32_t usart_periph)
+{
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN);
+}
+
+/*!
+    \brief      configure receiver timeout threshold
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  rtimeout: 0x00000000-0x00FFFFFF, receiver timeout value in terms of number of baud clocks
+    \param[out] none
+    \retval     none
+*/
+void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout)
+{
+    USART_RT(usart_periph) &= ~(USART_RT_RT);
+    USART_RT(usart_periph) |= rtimeout;
+}
+
+/*!
+    \brief      USART transmit data function
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  data: data of transmission
+    \param[out] none
+    \retval     none
+*/
+void usart_data_transmit(uint32_t usart_periph, uint32_t data)
+{
+    USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data);
+}
+
+/*!
+    \brief      USART receive data function
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     data of received
+*/
+uint16_t usart_data_receive(uint32_t usart_periph)
+{
+    return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U));
+}
+
+/*!
+    \brief      enable auto baud rate detection
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_autobaud_detection_enable(uint32_t usart_periph)
+{
+    USART_CTL1(usart_periph) |= USART_CTL1_ABDEN;
+}
+
+/*!
+    \brief      disable auto baud rate detection
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_autobaud_detection_disable(uint32_t usart_periph)
+{
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN);
+}
+
+/*!
+    \brief      configure auto baud rate detection mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  abdmod: auto baud rate detection mode
+                only one parameter can be selected which is shown as below:
+      \arg        USART_ABDM_FTOR: falling edge to rising edge measurement
+      \arg        USART_ABDM_FTOF: falling edge to falling edge measurement
+    \param[out] none
+    \retval     none
+*/
+void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod)
+{
+    /* reset ABDM bits */
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM);
+    USART_CTL1(usart_periph) |= abdmod;
+}
+
+/*!
+    \brief      address of the USART terminal
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  addr: 0x00-0xFF, address of USART terminal
+    \param[out] none
+    \retval     none
+*/
+void usart_address_config(uint32_t usart_periph, uint8_t addr)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
+    USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24));
+}
+
+/*!
+    \brief      configure address detection mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  addmod: address detection mode
+                only one parameter can be selected which is shown as below:
+      \arg        USART_ADDM_4BIT: 4 bits
+      \arg        USART_ADDM_FULLBIT: full bits
+    \param[out] none
+    \retval     none
+*/
+void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM);
+    USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod);
+}
+
+/*!
+    \brief      enable mute mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_mute_mode_enable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) |= USART_CTL0_MEN;
+}
+
+/*!
+    \brief      disable mute mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_mute_mode_disable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN);
+}
+
+/*!
+    \brief      configure wakeup method in mute mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  wmethod: two methods be used to enter or exit the mute mode
+                only one parameter can be selected which is shown as below:
+      \arg        USART_WM_IDLE: idle line
+      \arg        USART_WM_ADDR: address mark
+    \param[out] none
+    \retval     none
+*/
+void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
+    USART_CTL0(usart_periph) |= wmethod;
+}
+
+/*!
+    \brief      enable LIN mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_lin_mode_enable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
+}
+
+/*!
+    \brief      disable LIN mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_lin_mode_disable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
+}
+
+/*!
+    \brief      LIN break detection length
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  lblen: LIN break detection length
+                only one parameter can be selected which is shown as below:
+      \arg        USART_LBLEN_10B: 10 bits break detection
+      \arg        USART_LBLEN_11B: 11 bits break detection
+    \param[out] none
+    \retval     none
+*/
+void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN);
+    USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen);
+}
+
+/*!
+    \brief      enable half-duplex mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_halfduplex_enable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
+}
+
+/*!
+    \brief      disable half-duplex mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_halfduplex_disable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
+}
+
+/*!
+    \brief      enable clock
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_clock_enable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
+}
+
+/*!
+    \brief      disable clock
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_clock_disable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
+}
+
+/*!
+    \brief      configure USART synchronous mode parameters
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  clen: last bit clock pulse
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin
+      \arg        USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin
+    \param[in]  cph: clock phase
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CPH_1CK: first clock transition is the first data capture edge
+      \arg        USART_CPH_2CK: second clock transition is the first data capture edge
+    \param[in]  cpl: clock polarity
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CPL_LOW: steady low value on CK pin
+      \arg        USART_CPL_HIGH: steady high value on CK pin
+    \param[out] none
+    \retval     none
+*/
+void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* reset USART_CTL1 CLEN,CPH,CPL bits */
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
+
+    USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen);
+    USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph);
+    USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl);
+}
+
+/*!
+    \brief      configure guard time value in smartcard mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  guat: 0x00-0xFF
+    \param[out] none
+    \retval     none
+*/
+void usart_guard_time_config(uint32_t usart_periph, uint32_t guat)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_GP(usart_periph) &= ~(USART_GP_GUAT);
+    USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8));
+}
+
+/*!
+    \brief      enable smartcard mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_enable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
+}
+
+/*!
+    \brief      disable smartcard mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_disable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
+}
+
+/*!
+    \brief      enable NACK in smartcard mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
+}
+
+/*!
+    \brief      disable NACK in smartcard mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
+}
+
+/*!
+    \brief      enable early NACK in smartcard mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph)
+{
+    USART_RFCS(usart_periph) |= USART_RFCS_ELNACK;
+}
+
+/*!
+    \brief      disable early NACK in smartcard mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph)
+{
+    USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK;
+}
+
+/*!
+    \brief      configure smartcard auto-retry number
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  scrtnum: 0x00000000-0x00000007, smartcard auto-retry number
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM);
+    USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << 17));
+}
+
+/*!
+    \brief      configure block length
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  bl: 0x00000000-0x000000FF
+    \param[out] none
+    \retval     none
+*/
+void usart_block_length_config(uint32_t usart_periph, uint32_t bl)
+{
+    USART_RT(usart_periph) &= ~(USART_RT_BL);
+    USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24));
+}
+
+/*!
+    \brief      enable IrDA mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_irda_mode_enable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) |= USART_CTL2_IREN;
+}
+
+/*!
+    \brief      disable IrDA mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_irda_mode_disable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
+}
+
+/*!
+    \brief      configure the peripheral clock prescaler in USART IrDA low-power or SmartCard mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  psc: 0x00000000-0x000000FF
+    \param[out] none
+    \retval     none
+*/
+void usart_prescaler_config(uint32_t usart_periph, uint32_t psc)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    USART_GP(usart_periph) &= ~(USART_GP_PSC);
+    USART_GP(usart_periph) |= psc;
+}
+
+/*!
+    \brief      configure IrDA low-power
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  irlp: IrDA low-power or normal
+                only one parameter can be selected which is shown as below:
+      \arg        USART_IRLP_LOW:    low-power
+      \arg        USART_IRLP_NORMAL: normal
+    \param[out] none
+    \retval     none
+*/
+void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP);
+    USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
+}
+
+/*!
+    \brief      configure hardware flow control RTS
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  rtsconfig: enable or disable RTS
+                only one parameter can be selected which is shown as below:
+      \arg        USART_RTS_ENABLE:  enable RTS
+      \arg        USART_RTS_DISABLE: disable RTS
+    \param[out] none
+    \retval     none
+*/
+void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN);
+    USART_CTL2(usart_periph) |= rtsconfig;
+}
+
+/*!
+    \brief      configure hardware flow control CTS
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  ctsconfig:  enable or disable CTS
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CTS_ENABLE:  enable CTS
+      \arg        USART_CTS_DISABLE: disable CTS
+    \param[out] none
+    \retval     none
+*/
+void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN;
+    USART_CTL2(usart_periph) |= ctsconfig;
+}
+
+ /*!
+    \brief      configure hardware flow control coherence mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  hcm:
+                only one parameter can be selected which is shown as below:
+      \arg        USART_HCM_NONE: nRTS signal equals to the rxne status register
+      \arg        USART_HCM_EN:   nRTS signal is set when the last data bit has been sampled
+    \param[out] none
+    \retval     none
+*/
+void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm)
+{
+    USART_CHC(usart_periph) &= ~(USART_CHC_HCM);
+    USART_CHC(usart_periph) |= (USART_CHC_HCM & hcm);
+}
+
+/*!
+    \brief      enable RS485 driver
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_rs485_driver_enable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) |= USART_CTL2_DEM;
+}
+
+/*!
+    \brief      disable RS485 driver
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_rs485_driver_disable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM);
+}
+
+/*!
+    \brief      configure driver enable assertion time
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  deatime: 0x00000000-0x0000001F
+    \param[out] none
+    \retval     none
+*/
+void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA);
+    USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21));
+}
+
+/*!
+    \brief      configure driver enable de-assertion time
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  dedtime: 0x00000000-0x0000001F
+    \param[out] none
+    \retval     none
+*/
+void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_DED);
+    USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16));
+}
+
+/*!
+    \brief      configure driver enable polarity mode
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  dep: DE signal
+                only one parameter can be selected which is shown as below:
+      \arg        USART_DEP_HIGH: DE signal is active high
+      \arg        USART_DEP_LOW: DE signal is active low
+    \param[out] none
+    \retval     none
+*/
+void usart_depolarity_config(uint32_t usart_periph, uint32_t dep)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* reset DEP bit */
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP);
+    USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep);
+}
+
+/*!
+    \brief      configure USART DMA reception
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  dmacmd: enable or disable DMA for reception
+                only one parameter can be selected which is shown as below:
+      \arg        USART_DENR_ENABLE: DMA enable for reception
+      \arg        USART_DENR_DISABLE: DMA disable for reception
+    \param[out] none
+    \retval     none
+*/
+void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
+{
+    USART_CTL2(usart_periph) &= ~USART_CTL2_DENR;
+    /* configure DMA reception */
+    USART_CTL2(usart_periph) |= dmacmd;
+}
+
+/*!
+    \brief      configure USART DMA transmission
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  dmacmd: enable or disable DMA for transmission
+                only one parameter can be selected which is shown as below:
+      \arg        USART_DENT_ENABLE: DMA enable for transmission
+      \arg        USART_DENT_DISABLE: DMA disable for transmission
+    \param[out] none
+    \retval     none
+*/
+void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
+{
+    USART_CTL2(usart_periph) &= ~USART_CTL2_DENT;
+    /* configure DMA transmission */
+    USART_CTL2(usart_periph) |= dmacmd;
+}
+
+/*!
+    \brief      disable DMA on reception error
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_reception_error_dma_disable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) |= USART_CTL2_DDRE;
+}
+
+/*!
+    \brief      enable DMA on reception error 
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_reception_error_dma_enable(uint32_t usart_periph)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE);
+}
+
+/*!
+    \brief      enable USART to wakeup the mcu from deep-sleep mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_wakeup_enable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) |= USART_CTL0_UESM;
+}
+
+/*!
+    \brief      disable USART to wakeup the mcu from deep-sleep mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void usart_wakeup_disable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM);
+}
+
+/*!
+    \brief      configure the USART wakeup mode from deep-sleep mode
+    \param[in]  usart_periph: USARTx(x=0)
+    \param[in]  wum: wakeup mode
+                only one parameter can be selected which is shown as below:
+      \arg        USART_WUM_ADDR: WUF active on address match
+      \arg        USART_WUM_STARTB: WUF active on start bit
+      \arg        USART_WUM_RBNE: WUF active on RBNE
+    \param[out] none
+    \retval     none
+*/
+void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum)
+{
+    /* disable USART */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+    /* reset WUM bit */
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM);
+    USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum);
+}
+
+/*!
+    \brief      enable receive FIFO
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_receive_fifo_enable(uint32_t usart_periph)
+{
+    USART_RFCS(usart_periph) |= USART_RFCS_RFEN;
+}
+
+/*!
+    \brief      disable receive FIFO
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void usart_receive_fifo_disable(uint32_t usart_periph)
+{
+    USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN);
+}
+
+/*!
+    \brief      read receive FIFO counter number
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[out] none
+    \retval     receive FIFO counter number
+*/
+uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph)
+{
+    return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U));
+}
+
+/*!
+    \brief      get flag in STAT/CHC/RFCS register
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  flag: flag type
+                only one parameter can be selected which is shown as below:
+      \arg        USART_FLAG_PERR: parity error flag
+      \arg        USART_FLAG_FERR: frame error flag
+      \arg        USART_FLAG_NERR: noise error flag
+      \arg        USART_FLAG_ORERR: overrun error
+      \arg        USART_FLAG_IDLE: idle line detected flag
+      \arg        USART_FLAG_RBNE: read data buffer not empty
+      \arg        USART_FLAG_TC: transmission completed
+      \arg        USART_FLAG_TBE: transmit data register empty
+      \arg        USART_FLAG_LBD: LIN break detected flag
+      \arg        USART_FLAG_CTSF: CTS change flag
+      \arg        USART_FLAG_CTS: CTS level
+      \arg        USART_FLAG_RT: receiver timeout flag
+      \arg        USART_FLAG_EB: end of block flag
+      \arg        USART_FLAG_ABDE: auto baudrate detection error
+      \arg        USART_FLAG_ABD: auto baudrate detection flag
+      \arg        USART_FLAG_BSY: busy flag
+      \arg        USART_FLAG_AM: address match flag
+      \arg        USART_FLAG_SB: send break flag
+      \arg        USART_FLAG_RWU: receiver wakeup from mute mode.
+      \arg        USART_FLAG_WU: wakeup from deep-sleep mode flag
+      \arg        USART_FLAG_TEA: transmit enable acknowledge flag
+      \arg        USART_FLAG_REA: receive enable acknowledge flag 
+      \arg        USART_FLAG_EPERR: early parity error flag
+      \arg        USART_FLAG_RFE: receive FIFO empty flag
+      \arg        USART_FLAG_RFF: receive FIFO full flag
+      \arg        USART_FLAG_RFFINT: receive FIFO full interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
+{
+    if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear USART status
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  flag: flag type
+                only one parameter can be selected which is shown as below:
+      \arg        USART_FLAG_PERR: parity error flag
+      \arg        USART_FLAG_FERR: frame error flag
+      \arg        USART_FLAG_NERR: noise detected flag
+      \arg        USART_FLAG_ORERR: overrun error flag
+      \arg        USART_FLAG_IDLE: idle line detected flag
+      \arg        USART_FLAG_TC: transmission complete flag
+      \arg        USART_FLAG_LBD: LIN break detected flag
+      \arg        USART_FLAG_CTSF: CTS change flag
+      \arg        USART_FLAG_RT: receiver timeout flag
+      \arg        USART_FLAG_EB: end of block flag
+      \arg        USART_FLAG_AM: address match flag
+      \arg        USART_FLAG_WU: wakeup from deep-sleep mode flag
+      \arg        USART_FLAG_EPERR: early parity error flag
+    \param[out] none
+    \retval     none
+*/
+void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
+{
+    USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag));
+}
+
+/*!
+    \brief      enable USART interrupt
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  inttype: interrupt type
+                only one parameter can be selected which is shown as below:
+      \arg        USART_INT_IDLE: idle interrupt
+      \arg        USART_INT_RBNE: read data buffer not empty interrupt and
+                                  overrun error interrupt enable interrupt
+      \arg        USART_INT_TC: transmission complete interrupt
+      \arg        USART_INT_TBE: transmit data register empty interrupt
+      \arg        USART_INT_PERR: parity error interrupt
+      \arg        USART_INT_AM: address match interrupt
+      \arg        USART_INT_RT: receiver timeout interrupt
+      \arg        USART_INT_EB: end of block interrupt
+      \arg        USART_INT_LBD: LIN break detection interrupt
+      \arg        USART_INT_ERR: error interrupt enable in multibuffer communication
+      \arg        USART_INT_CTS: CTS interrupt
+      \arg        USART_INT_WU: wakeup from deep-sleep mode interrupt
+      \arg        USART_INT_RFF: receive FIFO full interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum inttype)
+{
+    USART_REG_VAL(usart_periph, inttype) |= BIT(USART_BIT_POS(inttype));
+}
+
+/*!
+    \brief      disable USART interrupt
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  inttype: interrupt type
+                only one parameter can be selected which is shown as below:
+      \arg        USART_INT_IDLE: idle interrupt
+      \arg        USART_INT_RBNE: read data buffer not empty interrupt and
+                                  overrun error interrupt
+      \arg        USART_INT_TC: transmission complete interrupt
+      \arg        USART_INT_TBE: transmit data register empty interrupt
+      \arg        USART_INT_PERR: parity error interrupt
+      \arg        USART_INT_AM: address match interrupt
+      \arg        USART_INT_RT: receiver timeout interrupt
+      \arg        USART_INT_EB: end of block interrupt
+      \arg        USART_INT_LBD: LIN break detection interrupt
+      \arg        USART_INT_ERR: error interrupt enable in multibuffer communication
+      \arg        USART_INT_CTS: CTS interrupt
+      \arg        USART_INT_WU: wakeup from deep-sleep mode interrupt
+      \arg        USART_INT_RFF: receive FIFO full interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum inttype)
+{
+    USART_REG_VAL(usart_periph, inttype) &= ~BIT(USART_BIT_POS(inttype));
+}
+
+/*!
+    \brief      enable USART command
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  cmdtype: command type
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CMD_ABDCMD: auto baudrate detection command
+      \arg        USART_CMD_SBKCMD: send break command
+      \arg        USART_CMD_MMCMD: mute mode command
+      \arg        USART_CMD_RXFCMD: receive data flush command
+      \arg        USART_CMD_TXFCMD: transmit data flush request
+    \param[out] none
+    \retval     none
+*/
+void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype)
+{
+    USART_CMD(usart_periph) |= (cmdtype);   
+}
+
+/*!
+    \brief      get USART interrupt and flag status
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        USART_INT_FLAG_EB: end of block interrupt and flag
+      \arg        USART_INT_FLAG_RT: receiver timeout interrupt and flag
+      \arg        USART_INT_FLAG_AM: address match interrupt and flag 
+      \arg        USART_INT_FLAG_PERR: parity error interrupt and flag 
+      \arg        USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag 
+      \arg        USART_INT_FLAG_TC: transmission complete interrupt and flag
+      \arg        USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
+      \arg        USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
+      \arg        USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
+      \arg        USART_INT_FLAG_LBD: LIN break detected interrupt and flag 
+      \arg        USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag
+      \arg        USART_INT_FLAG_CTS: CTS interrupt and flag
+      \arg        USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
+      \arg        USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
+      \arg        USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
+      \arg        USART_INT_FLAG_RFF: receive FIFO full interrupt and flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag)
+{
+    uint32_t intenable = 0U, flagstatus = 0U;
+    /* get the interrupt enable bit status */
+    intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
+    /* get the corresponding flag bit status */
+    flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
+
+    if(flagstatus && intenable){
+        return SET;
+    }else{
+        return RESET; 
+    }
+}
+
+/*!
+    \brief      clear USART interrupt flag
+    \param[in]  usart_periph: USARTx(x=0,1)
+    \param[in]  flag: USART interrupt flag
+                only one parameter can be selected which is shown as below:
+      \arg        USART_INT_FLAG_PERR: parity error flag
+      \arg        USART_INT_FLAG_ERR_FERR: frame error flag
+      \arg        USART_INT_FLAG_ERR_NERR: noise detected flag
+      \arg        USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
+      \arg        USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
+      \arg        USART_INT_FLAG_IDLE: idle line detected flag
+      \arg        USART_INT_FLAG_TC: transmission complete flag
+      \arg        USART_INT_FLAG_LBD: LIN break detected flag
+      \arg        USART_INT_FLAG_CTS: CTS change flag
+      \arg        USART_INT_FLAG_RT: receiver timeout flag
+      \arg        USART_INT_FLAG_EB: end of block flag
+      \arg        USART_INT_FLAG_AM: address match flag
+      \arg        USART_INT_FLAG_WU: wakeup from deep-sleep mode flag
+      \arg        USART_INT_FLAG_RFF: receive FIFO full interrupt and flag
+    \param[out] none
+    \retval     none
+*/
+void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag)
+{
+    if(USART_INT_FLAG_RFF == flag){
+        USART_RFCS(usart_periph) &= (uint32_t)(~USART_RFCS_RFFINT);
+    }else{
+        USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag));
+    }
+}
diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_wwdgt.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_wwdgt.c
new file mode 100644
index 0000000000..4d1ad0200c
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_wwdgt.c
@@ -0,0 +1,148 @@
+/*!
+    \file    gd32e230_wwdgt.c
+    \brief   WWDGT driver
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32e230_wwdgt.h"
+#include "gd32e230_rcu.h"
+
+/* WWDGT_CTL register value */
+#define CTL_CNT(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0U))    /*!< write value to WWDGT_CTL_CNT bit field */
+/* WWDGT_CFG register value */
+#define CFG_WIN(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0U))    /*!< write value to WWDGT_CFG_WIN bit field */
+
+/*!
+    \brief      reset the window watchdog timer configuration
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_deinit(void)
+{
+    rcu_periph_reset_enable(RCU_WWDGTRST);
+    rcu_periph_reset_disable(RCU_WWDGTRST);
+}
+
+/*!
+    \brief      start the window watchdog timer counter
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_enable(void)
+{
+    WWDGT_CTL |= WWDGT_CTL_WDGTEN;
+}
+
+/*!
+    \brief      configure the window watchdog timer counter value
+    \param[in]  counter_value: 0x00000000 - 0x0000007F
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_counter_update(uint16_t counter_value)
+{
+    uint32_t reg = 0x00000000U;
+    
+    reg = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
+    reg |= (uint32_t)(CTL_CNT(counter_value));
+    
+    WWDGT_CTL = (uint32_t)reg;
+}
+
+/*!
+    \brief      configure counter value, window value, and prescaler divider value  
+    \param[in]  counter: 0x00000000 - 0x0000007F
+    \param[in]  window: 0x00000000 - 0x0000007F
+    \param[in]  prescaler: wwdgt prescaler value
+                only one parameter can be selected which is shown as below:
+      \arg        WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
+      \arg        WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
+      \arg        WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
+      \arg        WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
+{
+    uint32_t reg_cfg = 0x00000000U, reg_ctl = 0x00000000U;
+
+    /* clear WIN and PSC bits, clear CNT bit */
+    reg_cfg = WWDGT_CFG &(~((uint32_t)WWDGT_CFG_WIN|(uint32_t)WWDGT_CFG_PSC));
+    reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
+  
+    /* configure WIN and PSC bits, configure CNT bit */
+    reg_cfg |= (uint32_t)(CFG_WIN(window));
+    reg_cfg |= (uint32_t)(prescaler);
+    reg_ctl |= (uint32_t)(CTL_CNT(counter));
+    
+    WWDGT_CFG = (uint32_t)reg_cfg;
+    WWDGT_CTL = (uint32_t)reg_ctl;
+}
+
+/*!
+    \brief      enable early wakeup interrupt of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_interrupt_enable(void)
+{
+    WWDGT_CFG |= WWDGT_CFG_EWIE;
+}
+
+/*!
+    \brief      check early wakeup interrupt state of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus wwdgt_flag_get(void)
+{
+  if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)){
+        return SET;
+  }
+    return RESET;
+}
+
+/*!
+    \brief      clear early wakeup interrupt state of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_flag_clear(void)
+{
+    WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF);
+}
diff --git a/bsp/gd32e230k-start/Libraries/SConscript b/bsp/gd32e230k-start/Libraries/SConscript
new file mode 100644
index 0000000000..eb4cfb77c7
--- /dev/null
+++ b/bsp/gd32e230k-start/Libraries/SConscript
@@ -0,0 +1,33 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('GD32F30x_standard_peripheral/Source/*.c')
+src += [cwd + '/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [cwd + '/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s']
+
+path = [
+    cwd + '/CMSIS/GD/GD32F30x/Include',
+    cwd + '/CMSIS',
+    cwd + '/GD32F30x_standard_peripheral/Include',]
+    
+if GetDepend(['RT_USING_BSP_USB']):
+    path += [cwd + '/GD32F30x_usb_driver/Include']
+    src  += [cwd + '/GD32F30x_usb_driver/Source']
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F30X_HD']
+
+group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/gd32e230k-start/SConscript b/bsp/gd32e230k-start/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/gd32e230k-start/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/gd32e230k-start/SConstruct b/bsp/gd32e230k-start/SConstruct
new file mode 100644
index 0000000000..1cdbaab4a8
--- /dev/null
+++ b/bsp/gd32e230k-start/SConstruct
@@ -0,0 +1,39 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread-gd32f30x.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/gd32e230k-start/applications/SConscript b/bsp/gd32e230k-start/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/gd32e230k-start/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32e230k-start/applications/main.c b/bsp/gd32e230k-start/applications/main.c
new file mode 100644
index 0000000000..6e190ae3cc
--- /dev/null
+++ b/bsp/gd32e230k-start/applications/main.c
@@ -0,0 +1,27 @@
+/*
+ * File      : main.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-07-29     Arda.Fu      first implementation
+ */
+#include <rtthread.h>
+#include <board.h>
+
+int main(void)
+{
+    /* user app entry */
+
+    return 0;
+}
+
+
+
+
+
diff --git a/bsp/gd32e230k-start/drivers/SConscript b/bsp/gd32e230k-start/drivers/SConscript
new file mode 100644
index 0000000000..ef03e2dcf0
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/SConscript
@@ -0,0 +1,33 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'drivers')
+
+# add the general drivers.
+src = Split("""
+board.c
+drv_usart.c
+""")
+
+CPPPATH = [cwd]
+
+# add spi drivers.
+if GetDepend('RT_USING_SPI'):
+    src += ['drv_spi.c']
+    
+# add i2c drivers.
+if GetDepend('RT_USING_I2C'):
+    src += ['drv_i2c.c']
+
+# add pin drivers.
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+# add spi flash drivers.
+if GetDepend('RT_USING_SFUD'):
+    src += ['drv_spi_flash.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32e230k-start/drivers/board.c b/bsp/gd32e230k-start/drivers/board.c
new file mode 100644
index 0000000000..9ca024ec48
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/board.c
@@ -0,0 +1,87 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ */
+#include <stdint.h>
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  None
+  * @retval None
+  */
+void Error_Handler(void)
+{
+    /* USER CODE BEGIN Error_Handler */
+    /* User can add his own implementation to report the HAL error return state */
+    while (1)
+    {
+    }
+    /* USER CODE END Error_Handler */
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    NVIC_SetPriority(SysTick_IRQn, 0);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial GD32 board.
+ */
+void rt_hw_board_init()
+{
+    /* NVIC Configuration */
+#define NVIC_VTOR_MASK              0x3FFFFF80
+#ifdef  VECT_TAB_RAM
+    /* Set the Vector Table base location at 0x10000000 */
+    SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
+#else  /* VECT_TAB_FLASH  */
+    /* Set the Vector Table base location at 0x08000000 */
+    SCB->VTOR  = (0x08000000 & NVIC_VTOR_MASK);
+#endif
+
+    SystemClock_Config();
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_HEAP   
+    rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/gd32e230k-start/drivers/board.h b/bsp/gd32e230k-start/drivers/board.h
new file mode 100644
index 0000000000..de344e8768
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/board.h
@@ -0,0 +1,47 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <gd32e230.h>
+
+// <o> Internal SRAM memory size[Kbytes] <8-64>
+//	<i>Default: 64
+#ifdef __ICCARM__
+// Use *.icf ram symbal, to avoid hardcode.
+extern char __ICFEDIT_region_RAM_end__;
+#define GD32_SRAM_END          &__ICFEDIT_region_RAM_end__
+#else
+#define GD32_SRAM_SIZE         64
+#define GD32_SRAM_END          (0x20000000 + GD32_SRAM_SIZE * 1024)
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN    (&__bss_end)
+#endif
+
+#define HEAP_END          GD32_SRAM_END
+
+#endif
+
+//*** <<< end of configuration section >>>    ***
diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.c b/bsp/gd32e230k-start/drivers/drv_gpio.c
new file mode 100644
index 0000000000..6b9ecf4e34
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/drv_gpio.c
@@ -0,0 +1,539 @@
+/*
+ * File      : drv_gpio.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2017-10-20     ZYH            the first version
+ * 2018-04-23     misonyo        port to gd32f30x
+ */
+
+#include "drv_gpio.h"
+#include <rtdevice.h>
+#include <rthw.h>
+#include "gd32e230.h"
+#include "gd32e230_exti.h"
+
+#ifdef RT_USING_PIN
+
+#define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \
+        GPIO_PIN_##pin, EXTI_SOURCE_GPIO##port, EXTI_SOURCE_PIN##pin}
+#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0}
+
+/* GD32 GPIO driver */
+struct pin_index
+{
+    rt_int16_t index;
+    rcu_periph_enum clk;
+    rt_uint32_t gpio_periph;
+    rt_uint32_t pin;
+	  rt_uint32_t port_src;
+	  rt_uint32_t pin_src;
+};
+
+static const struct pin_index pins[] =
+{
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(7, C, 13),
+    __GD32_PIN(8, C, 14),
+    __GD32_PIN(9, C, 15),
+    __GD32_PIN(10, F, 0),
+    __GD32_PIN(11, F, 1),
+    __GD32_PIN(12, F, 2),
+    __GD32_PIN(13, F, 3),
+    __GD32_PIN(14, F, 4),
+    __GD32_PIN(15, F, 5),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(18, F, 6),
+    __GD32_PIN(19, F, 7),
+    __GD32_PIN(20, F, 8),
+    __GD32_PIN(21, F, 9),
+    __GD32_PIN(22, F, 10),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(26, C, 0),
+    __GD32_PIN(27, C, 1),
+    __GD32_PIN(28, C, 2),
+    __GD32_PIN(29, C, 3),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(34, A, 0),
+    __GD32_PIN(35, A, 1),
+    __GD32_PIN(36, A, 2),
+    __GD32_PIN(37, A, 3),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(40, A, 4),
+    __GD32_PIN(41, A, 5),
+    __GD32_PIN(42, A, 6),
+    __GD32_PIN(43, A, 7),
+    __GD32_PIN(44, C, 4),
+    __GD32_PIN(45, C, 5),
+    __GD32_PIN(46, B, 0),
+    __GD32_PIN(47, B, 1),
+    __GD32_PIN(48, B, 2),
+    __GD32_PIN(49, F, 11),
+    __GD32_PIN(50, F, 12),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(53, F, 13),
+    __GD32_PIN(54, F, 14),
+    __GD32_PIN(55, F, 15),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(69, B, 10),
+    __GD32_PIN(70, B, 11),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(73, B, 12),
+    __GD32_PIN(74, B, 13),
+    __GD32_PIN(75, B, 14),
+    __GD32_PIN(76, B, 15),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(96, C, 6),
+    __GD32_PIN(97, C, 7),
+    __GD32_PIN(98, C, 8),
+    __GD32_PIN(99, C, 9),
+    __GD32_PIN(100, A, 8),
+    __GD32_PIN(101, A, 9),
+    __GD32_PIN(102, A, 10),
+    __GD32_PIN(103, A, 11),
+    __GD32_PIN(104, A, 12),
+    __GD32_PIN(105, A, 13),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(109, A, 14),
+    __GD32_PIN(110, A, 15),
+    __GD32_PIN(111, C, 10),
+    __GD32_PIN(112, C, 11),
+    __GD32_PIN(113, C, 12),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(133, B, 3),
+    __GD32_PIN(134, B, 4),
+    __GD32_PIN(135, B, 5),
+    __GD32_PIN(136, B, 6),
+    __GD32_PIN(137, B, 7),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(139, B, 8),
+    __GD32_PIN(140, B, 9),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN_DEFAULT,
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {GPIO_PIN_0, EXTI0_1_IRQn},
+    {GPIO_PIN_1, EXTI0_1_IRQn},
+    {GPIO_PIN_2, EXTI2_3_IRQn},
+    {GPIO_PIN_3, EXTI2_3_IRQn},
+    {GPIO_PIN_4, EXTI4_15_IRQn},
+    {GPIO_PIN_5, EXTI4_15_IRQn},
+    {GPIO_PIN_6, EXTI4_15_IRQn},
+    {GPIO_PIN_7, EXTI4_15_IRQn},
+    {GPIO_PIN_8, EXTI4_15_IRQn},
+    {GPIO_PIN_9, EXTI4_15_IRQn},
+    {GPIO_PIN_10, EXTI4_15_IRQn},
+    {GPIO_PIN_11, EXTI4_15_IRQn},
+    {GPIO_PIN_12, EXTI4_15_IRQn},
+    {GPIO_PIN_13, EXTI4_15_IRQn},
+    {GPIO_PIN_14, EXTI4_15_IRQn},
+    {GPIO_PIN_15, EXTI4_15_IRQn},
+};
+struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+const struct pin_index *get_pin(rt_uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+        index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    rt_uint32_t pin_mode;
+	  rt_uint32_t otype;
+	  rt_uint32_t pull_up_down;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* GPIO Periph clock enable */
+    rcu_periph_clock_enable(index->clk);
+    pin_mode = GPIO_MODE_OUTPUT;
+		otype = GPIO_OTYPE_PP;
+		pull_up_down = GPIO_PUPD_NONE;
+    
+   switch(mode)
+   {
+   case PIN_MODE_OUTPUT:
+        /* output setting */
+        break;
+   case PIN_MODE_OUTPUT_OD:
+        /* output setting: od. */
+		    otype = GPIO_OTYPE_OD;
+        break;
+   case PIN_MODE_INPUT:
+        /* input setting: not pull. */
+        pin_mode = GPIO_MODE_INPUT;
+        break;
+   case PIN_MODE_INPUT_PULLUP:
+        /* input setting: pull up. */
+        pin_mode = GPIO_MODE_INPUT;
+	      pull_up_down = GPIO_PUPD_PULLUP;
+        break;
+   case PIN_MODE_INPUT_PULLDOWN:
+        /* input setting: pull down. */
+	      pin_mode = GPIO_MODE_INPUT;
+	      pull_up_down = GPIO_PUPD_PULLDOWN;
+        break;
+   default:
+        break;
+   }
+
+	  gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
+    gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin);
+	 
+}
+
+void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
+}
+
+int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    value = gpio_input_bit_get(index->gpio_periph, index->pin);
+
+    return value;
+}
+
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+    rt_uint8_t i;
+    for (i = 0; i < 32; i++)
+    {
+        if ((0x01 << i) == bit)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
+{
+    rt_int32_t mapindex = bit2bitno(pinbit);
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t hdr_index = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_EINVAL;
+    }
+    hdr_index = bit2bitno(index->pin);
+    if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_EINVAL;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[hdr_index].pin == pin &&
+        pin_irq_hdr_tab[hdr_index].hdr == hdr &&
+        pin_irq_hdr_tab[hdr_index].mode == mode &&
+        pin_irq_hdr_tab[hdr_index].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[hdr_index].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EFULL;
+    }
+    pin_irq_hdr_tab[hdr_index].pin = pin;
+    pin_irq_hdr_tab[hdr_index].hdr = hdr;
+    pin_irq_hdr_tab[hdr_index].mode = mode;
+    pin_irq_hdr_tab[hdr_index].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t hdr_index = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_EINVAL;
+    }
+    hdr_index = bit2bitno(index->pin);
+    if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_EINVAL;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[hdr_index].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[hdr_index].pin = -1;
+    pin_irq_hdr_tab[hdr_index].hdr = RT_NULL;
+    pin_irq_hdr_tab[hdr_index].mode = 0;
+    pin_irq_hdr_tab[hdr_index].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t hdr_index = -1;
+    exti_trig_type_enum trigger_mode;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_EINVAL;
+    }
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        hdr_index = bit2bitno(index->pin);
+        if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_EINVAL;
+        }
+        level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[hdr_index].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EINVAL;
+        }
+        irqmap = &pin_irq_map[hdr_index];
+   
+        switch (pin_irq_hdr_tab[hdr_index].mode)
+        {
+            case PIN_IRQ_MODE_RISING:
+                trigger_mode = EXTI_TRIG_RISING;
+                break;
+            case PIN_IRQ_MODE_FALLING:
+                trigger_mode = EXTI_TRIG_FALLING;
+                break;
+            case PIN_IRQ_MODE_RISING_FALLING:
+                trigger_mode = EXTI_TRIG_BOTH;
+                break;
+            default:
+                rt_hw_interrupt_enable(level);
+                return RT_EINVAL;
+        }
+
+        //rcu_periph_clock_enable(RCU_AF);
+
+        /* enable and set interrupt priority */
+        nvic_irq_enable(irqmap->irqno, 5U);
+        
+        /* connect EXTI line to  GPIO pin */
+				syscfg_exti_line_config(index->port_src, index->pin_src);
+
+        /* configure EXTI line */
+        exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
+        exti_interrupt_flag_clear((exti_line_enum)(index->pin));
+        
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return RT_EINVAL;
+        }
+        nvic_irq_disable(irqmap->irqno);
+    }
+    else
+    {
+        return RT_EINVAL;
+    }
+
+    return RT_EOK;
+}
+const static struct rt_pin_ops _gd32_pin_ops =
+{
+    gd32_pin_mode,
+    gd32_pin_write,
+    gd32_pin_read,
+    gd32_pin_attach_irq,
+    gd32_pin_detach_irq,
+    gd32_pin_irq_enable,
+};
+
+int rt_hw_pin_init(void)
+{
+    int result;
+
+    result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
+    
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
+{
+    if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
+    {
+        pin_irq_hdr(exti_line);
+        exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
+    } 
+}
+void EXTI0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(0);
+    rt_interrupt_leave();
+}
+void EXTI1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(1);
+    rt_interrupt_leave();
+}
+void EXTI2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(2);
+    rt_interrupt_leave();
+}
+void EXTI3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(3);
+    rt_interrupt_leave();
+}
+void EXTI4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(4);
+    rt_interrupt_leave();
+}
+void EXTI5_9_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(5);
+    GD32_GPIO_EXTI_IRQHandler(6);
+    GD32_GPIO_EXTI_IRQHandler(7);
+    GD32_GPIO_EXTI_IRQHandler(8);
+    GD32_GPIO_EXTI_IRQHandler(9);
+    rt_interrupt_leave();
+}
+void EXTI10_15_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(10);
+    GD32_GPIO_EXTI_IRQHandler(11);
+    GD32_GPIO_EXTI_IRQHandler(12);
+    GD32_GPIO_EXTI_IRQHandler(13);
+    GD32_GPIO_EXTI_IRQHandler(14);
+    GD32_GPIO_EXTI_IRQHandler(15);
+    rt_interrupt_leave();
+}
+
+#endif
diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.h b/bsp/gd32e230k-start/drivers/drv_gpio.h
new file mode 100644
index 0000000000..bca532ff2d
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/drv_gpio.h
@@ -0,0 +1,18 @@
+/*
+ * File      : drv_gpio.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-01-05     Bernard      the first version
+ */
+#ifndef GPIO_H__
+#define GPIO_H__
+
+
+#endif
diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.c b/bsp/gd32e230k-start/drivers/drv_i2c.c
new file mode 100644
index 0000000000..c0fbd5f7e9
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/drv_i2c.c
@@ -0,0 +1,381 @@
+/*
+ * File      : drv_i2c.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-06-05     tanek        first implementation.
+ * 2018-04-19     misonyo      Porting for gd32f30x
+ */
+
+#include "drv_i2c.h"
+#include <rtthread.h>
+#include "gd32e230.h"
+
+#ifdef RT_USING_I2C
+
+#include <rtdevice.h>
+
+#ifdef RT_USING_I2C_BITOPS
+
+/*user can change this*/
+#define I2C_BUS_NAME  "i2c2"
+
+/*user should change this to adapt specific board*/
+#define I2C_SCL_PIN          GPIO_PIN_4
+#define I2C_SCL_PORT         GPIOE
+#define I2C_SCL_CLK          RCU_GPIOE
+#define I2C_SDA_PIN          GPIO_PIN_5
+#define I2C_SDA_PORT         GPIOE
+#define I2C_SDA_CLK          RCU_GPIOE
+
+struct gd32_i2c_bit_data
+{
+    struct
+    {
+        rcu_periph_enum clk;
+        rt_uint32_t port;
+        rt_uint32_t pin;
+    }scl, sda;
+};
+
+static void gpio_set_sda(void *data, rt_int32_t state)
+{
+    struct gd32_i2c_bit_data* bd = data;
+
+    if (state)
+    {
+        gpio_bit_set(bd->sda.port, bd->sda.pin);
+    }
+    else
+    {
+        gpio_bit_reset(bd->sda.port, bd->sda.pin);
+    }
+}
+
+static void gpio_set_scl(void *data, rt_int32_t state)
+{
+    struct gd32_i2c_bit_data* bd = data;
+    if (state)
+    {
+        gpio_bit_set(bd->scl.port, bd->scl.pin);
+    }
+    else
+    {
+        gpio_bit_reset(bd->scl.port, bd->scl.pin);
+    }
+}
+
+static rt_int32_t gpio_get_sda(void *data)
+{
+    struct gd32_i2c_bit_data* bd = data;
+
+    return gpio_input_bit_get(bd->sda.port, bd->sda.pin);
+}
+
+static rt_int32_t gpio_get_scl(void *data)
+{
+    struct gd32_i2c_bit_data* bd = data;
+
+    return gpio_input_bit_get(bd->scl.port, bd->scl.pin);
+}
+
+static void gpio_udelay(rt_uint32_t us)
+{
+    int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us);
+    while(i)
+    {
+        i--;
+    }
+}
+
+static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd)
+{
+    rcu_periph_clock_enable(bd->sda.clk);
+    rcu_periph_clock_enable(bd->scl.clk);
+    gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin);
+    gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin);
+
+    gpio_bit_set(bd->sda.port, bd->sda.pin);
+    gpio_bit_set(bd->scl.port, bd->scl.pin);
+}
+
+#else /* use hardware i2c */
+
+struct gd32_i2c_bus
+{
+    struct rt_i2c_bus_device parent;
+    rt_uint32_t i2c_periph;
+};
+
+static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte)
+{
+    /* wait until I2C bus is idle */
+    while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY));
+
+    /* send a start condition to I2C bus */
+    i2c_start_on_bus(i2c_periph);
+
+    /* wait until SBSEND bit is set */
+    while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND));
+
+    /* send slave address to I2C bus */
+    i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER);
+
+    /* wait until ADDSEND bit is set */
+    while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND));
+
+    /* clear the ADDSEND bit */
+    i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND);
+
+    if(1 == data_byte){
+        /* disable acknowledge */
+        i2c_ack_config(i2c_periph,I2C_ACK_DISABLE);
+        /* send a stop condition to I2C bus */
+        i2c_stop_on_bus(i2c_periph);
+    }
+
+    /* while there is data to be read */
+    while(data_byte)
+    {
+        /* wait until the RBNE bit is set and clear it */
+        if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE))
+        {
+            /* read a byte from the EEPROM */
+            *p_buffer = i2c_data_receive(i2c_periph);
+
+            /* point to the next location where the byte read will be saved */
+            p_buffer++; 
+
+            /* decrement the read bytes counter */
+            data_byte--;
+            if(1 == data_byte)
+            {
+                /* disable acknowledge */
+                i2c_ack_config(i2c_periph,I2C_ACK_DISABLE);
+                /* send a stop condition to I2C bus */
+                i2c_stop_on_bus(i2c_periph);
+            }
+        }
+    }
+
+    /* wait until the stop condition is finished */
+    while(I2C_CTL0(i2c_periph)&0x0200);
+
+    /* enable acknowledge */
+    i2c_ack_config(i2c_periph,I2C_ACK_ENABLE);
+
+    i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT);
+
+    return 0;
+}
+
+static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte)
+{
+    /* wait until I2C bus is idle */
+    while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY));
+
+    /* send a start condition to I2C bus */
+    i2c_start_on_bus(i2c_periph);
+
+    /* wait until SBSEND bit is set */
+    while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND));
+
+    /* send slave address to I2C bus */
+    i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER);
+
+    /* wait until ADDSEND bit is set */
+    while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND));
+
+    /* clear the ADDSEND bit */
+    i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND);
+
+    /* wait until the transmit data buffer is empty */
+    while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE));
+
+    /* while there is data to be read */
+    while(data_byte)
+    {
+        i2c_data_transmit(i2c_periph, *p_buffer);
+
+        /* point to the next byte to be written */
+        p_buffer++;
+
+        /* decrement the write bytes counter */
+        data_byte --;
+
+        /* wait until BTC bit is set */
+        while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC));
+    }
+
+        /* send a stop condition to I2C bus */
+    i2c_stop_on_bus(i2c_periph);
+
+    /* wait until the stop condition is finished */
+    while(I2C_CTL0(i2c_periph)&0x0200);
+
+    return 0;
+}
+
+static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
+{
+    struct rt_i2c_msg *msg;
+    rt_uint32_t i;
+    rt_err_t ret = RT_ERROR;
+
+    struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus;
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+
+        if (msg->flags & RT_I2C_ADDR_10BIT)
+        {
+            i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0);
+        }
+        else
+        {
+            i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0);
+        }
+        if (msg->flags & RT_I2C_RD)
+        {
+            if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0)
+            {
+                i2c_dbg("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+        else
+        {
+            if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0)
+            {
+                i2c_dbg("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+    }
+    
+    ret = i;
+
+out:
+    i2c_dbg("send stop condition\n");
+
+    return ret;
+}
+
+static const struct rt_i2c_bus_device_ops i2c_ops =
+{ 
+    gd32_i2c_xfer,
+    RT_NULL,
+    RT_NULL
+};
+
+#endif /* RT_USING_I2C_BITOPS */
+
+int rt_hw_i2c_init(void)
+{
+#ifdef RT_USING_I2C_BITOPS
+    {
+        static struct rt_i2c_bus_device i2c_device;
+        static const struct gd32_i2c_bit_data _i2c_bdata =
+        {
+            /* SCL */
+            {    I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN},
+            /* SDA */
+            {    I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN},
+        };
+
+        static const struct rt_i2c_bit_ops _i2c_bit_ops =
+        {
+            (void*)&_i2c_bdata,
+            gpio_set_sda,
+            gpio_set_scl,
+            gpio_get_sda,
+            gpio_get_scl,
+            gpio_udelay,
+            1,
+            100
+        };
+
+        drv_i2c_gpio_init(&_i2c_bdata);
+
+        i2c_device.priv = (void *)&_i2c_bit_ops;
+        rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME);
+    } 
+
+#else   /* register hardware I2C */
+
+#ifdef RT_USING_I2C0
+#define I2C0_SPEED  100000
+
+    static struct gd32_i2c_bus gd32_i2c0;
+    /* enable GPIOB clock */
+    rcu_periph_clock_enable(RCU_GPIOB);
+
+    /* connect PB6 to I2C0_SCL, PB7 to I2C0_SDA */
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_6 | GPIO_PIN_7);
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7);
+
+    /* enable I2C clock */
+    rcu_periph_clock_enable(RCU_I2C0);
+    /* configure I2C clock */
+    i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2);
+
+    i2c_enable(I2C0);
+    /* enable acknowledge */
+    i2c_ack_config(I2C0,I2C_ACK_ENABLE);
+
+    rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus));
+    gd32_i2c0.parent.ops = &i2c_ops;
+    gd32_i2c0.i2c_periph = I2C0;
+    rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0");
+#endif
+
+#ifdef RT_USING_I2C1
+#define I2C1_SPEED  100000
+
+    static struct gd32_i2c_bus gd32_i2c1;
+    /* enable GPIOB clock */
+    rcu_periph_clock_enable(RCU_GPIOB);
+
+    /* connect PB10 to I2C1_SCL, PB11 to I2C1_SDA */
+    gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11);
+
+    /* enable I2C clock */
+    rcu_periph_clock_enable(RCU_I2C1);
+    /* configure I2C clock */
+    i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2);
+
+    i2c_enable(I2C1);
+    /* enable acknowledge */
+    i2c_ack_config(I2C1,I2C_ACK_ENABLE);
+
+    rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus));
+    gd32_i2c1.parent.ops = &i2c_ops;
+    gd32_i2c1.i2c_periph = I2C1;
+    rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1");
+#endif
+
+#endif /* RT_USING_I2C_BITOPS */
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#endif
+/* end of i2c driver */
diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.h b/bsp/gd32e230k-start/drivers/drv_i2c.h
new file mode 100644
index 0000000000..2cc86ace3c
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/drv_i2c.h
@@ -0,0 +1,29 @@
+/*
+ * File      : drv_i2c.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-06-05     tanek        first implementation.
+ */
+
+#ifndef __DRV_I2C__
+#define __DRV_I2C__
+
+
+#endif
diff --git a/bsp/gd32e230k-start/drivers/drv_spi.c b/bsp/gd32e230k-start/drivers/drv_spi.c
new file mode 100644
index 0000000000..7c749d75e0
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/drv_spi.c
@@ -0,0 +1,290 @@
+/*
+ * File      : drv_spi.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-06-05     tanek        first implementation.
+ * 2018-04-19     misonyo      Porting for gd32f30x
+ */
+
+#include "drv_spi.h"
+#include "gd32e230.h"
+#include <rtthread.h>
+
+#if defined(RT_USING_SPI) && defined(RT_USING_PIN)
+#include <rtdevice.h>
+
+#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \
+    !defined(RT_USING_SPI2)
+#error "Please define at least one SPIx"
+#endif
+
+/* #define DEBUG */
+#ifdef DEBUG
+#define DEBUG_PRINTF(...)   rt_kprintf(__VA_ARGS__)
+#else
+#define DEBUG_PRINTF(...)
+#endif
+
+/* private rt-thread spi ops function */
+static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
+static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
+
+static struct rt_spi_ops gd32_spi_ops =
+{
+    configure,
+    xfer
+};
+
+static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
+{
+    spi_parameter_struct spi_init_struct;
+
+    rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    if(configuration->data_width <= 8)
+    {
+        spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
+    }
+    else if(configuration->data_width <= 16)
+    {
+        spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT;
+    }
+    else
+    {
+        return RT_EIO;
+    }
+
+    {
+        rcu_clock_freq_enum spi_src;
+        rt_uint32_t spi_apb_clock;
+        rt_uint32_t max_hz;
+
+        max_hz = configuration->max_hz;
+
+        DEBUG_PRINTF("sys   freq: %d\n", rcu_clock_freq_get(CK_SYS));
+        DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2));
+        DEBUG_PRINTF("max   freq: %d\n", max_hz);
+
+        if (spi_periph == SPI1)
+        {
+            spi_src = CK_APB1;
+        }
+        else
+        {
+            spi_src = CK_APB2;
+        }
+        spi_apb_clock = rcu_clock_freq_get(spi_src);
+
+        if(max_hz >= spi_apb_clock/2)
+        {
+            spi_init_struct.prescale = SPI_PSC_2;
+        }
+        else if (max_hz >= spi_apb_clock/4)
+        {
+            spi_init_struct.prescale = SPI_PSC_4;
+        }
+        else if (max_hz >= spi_apb_clock/8)
+        {
+            spi_init_struct.prescale = SPI_PSC_8;
+        }
+        else if (max_hz >= spi_apb_clock/16)
+        {
+            spi_init_struct.prescale = SPI_PSC_16;
+        }
+        else if (max_hz >= spi_apb_clock/32)
+        {
+            spi_init_struct.prescale = SPI_PSC_32;
+        }
+        else if (max_hz >= spi_apb_clock/64)
+        {
+            spi_init_struct.prescale = SPI_PSC_64;
+        }
+        else if (max_hz >= spi_apb_clock/128)
+        {
+            spi_init_struct.prescale = SPI_PSC_128;
+        }
+        else
+        {
+            /*  min prescaler 256 */
+            spi_init_struct.prescale = SPI_PSC_256;
+        }
+    } /* baudrate */
+    
+    switch(configuration->mode & RT_SPI_MODE_3)
+    {
+    case RT_SPI_MODE_0:
+        spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
+        break;
+    case RT_SPI_MODE_1:
+        spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
+        break;
+    case RT_SPI_MODE_2:
+        spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
+        break;
+    case RT_SPI_MODE_3:
+        spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
+        break;
+    }
+    
+    /* MSB or LSB */
+    if(configuration->mode & RT_SPI_MSB)
+    {
+        spi_init_struct.endian = SPI_ENDIAN_MSB;
+    }
+    else
+    {
+        spi_init_struct.endian = SPI_ENDIAN_LSB;
+    }
+    
+    spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
+    spi_init_struct.device_mode = SPI_MASTER;
+    spi_init_struct.nss = SPI_NSS_SOFT;
+
+    spi_init(spi_periph, &spi_init_struct);
+
+    spi_crc_off(spi_periph);
+
+    spi_enable(spi_periph);
+
+    return RT_EOK;
+};
+
+static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
+{
+    rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data;
+    rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
+    struct rt_spi_configuration * config = &device->config;
+
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+
+    /* take CS */
+    if(message->cs_take)
+    {
+        rt_pin_write(gd32_cs_pin, PIN_LOW);
+        DEBUG_PRINTF("spi take cs\n");
+    }
+
+    {
+        if(config->data_width <= 8)
+        {
+            const rt_uint8_t * send_ptr = message->send_buf;
+            rt_uint8_t * recv_ptr = message->recv_buf;
+            rt_uint32_t size = message->length;
+            
+            DEBUG_PRINTF("spi poll transfer start: %d\n", size);
+
+            while(size--)
+            {
+                rt_uint8_t data = 0xFF;
+
+                if(send_ptr != RT_NULL)
+                {
+                    data = *send_ptr++;
+                }
+                
+                // Todo: replace register read/write by gd32f3 lib
+                //Wait until the transmit buffer is empty
+                while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
+                // Send the byte
+                spi_i2s_data_transmit(spi_periph, data);
+
+                //Wait until a data is received
+                while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
+                // Get the received data
+                data = spi_i2s_data_receive(spi_periph);
+
+                if(recv_ptr != RT_NULL)
+                {
+                    *recv_ptr++ = data;
+                }
+            }
+            DEBUG_PRINTF("spi poll transfer finsh\n");
+        }
+        else if(config->data_width <= 16)
+        {
+            const rt_uint16_t * send_ptr = message->send_buf;
+            rt_uint16_t * recv_ptr = message->recv_buf;
+            rt_uint32_t size = message->length;
+
+            while(size--)
+            {
+                rt_uint16_t data = 0xFF;
+
+                if(send_ptr != RT_NULL)
+                {
+                    data = *send_ptr++;
+                }
+
+                //Wait until the transmit buffer is empty
+                while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
+                // Send the byte
+                spi_i2s_data_transmit(spi_periph, data);
+
+                //Wait until a data is received
+                while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
+                // Get the received data
+                data = spi_i2s_data_receive(spi_periph);
+
+                if(recv_ptr != RT_NULL)
+                {
+                    *recv_ptr++ = data;
+                }
+            }
+        }
+    }
+
+    /* release CS */
+    if(message->cs_release)
+    {
+        rt_pin_write(gd32_cs_pin, PIN_HIGH);
+        DEBUG_PRINTF("spi release cs\n");
+    }
+
+    return message->length;
+};
+
+int gd32_hw_spi_init(void)
+{
+    int result = 0;
+#ifdef RT_USING_SPI0
+    static struct rt_spi_bus spi_bus0;
+    spi_bus0.parent.user_data = (void *)SPI0;
+
+    result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops);
+
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_SPI0);
+    /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */
+	  gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5 | GPIO_PIN_7);
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7);
+    gpio_mode_set(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN_5 | GPIO_PIN_7);
+#endif
+#ifdef RT_USING_SPI1
+    static struct rt_spi_bus spi_bus1;
+    spi_bus1.parent.user_data = (void *)SPI1;
+
+    result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops);
+
+    rcu_periph_clock_enable(RCU_SPI1);
+    rcu_periph_clock_enable(RCU_GPIOB);
+
+    /* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */
+		gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13 | GPIO_PIN_15);
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15);
+		gpio_mode_set(GPIOB, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN_14);
+#endif
+    return result;
+}
+INIT_BOARD_EXPORT(gd32_hw_spi_init);
+#endif
diff --git a/bsp/gd32e230k-start/drivers/drv_spi.h b/bsp/gd32e230k-start/drivers/drv_spi.h
new file mode 100644
index 0000000000..69b07b70af
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/drv_spi.h
@@ -0,0 +1,19 @@
+/*
+ * File      : gd32f30x_spi.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-01    aozima       first implementation.
+ */
+
+#ifndef gd32F30X_SPI_H_INCLUDED
+#define gd32F30X_SPI_H_INCLUDED
+
+
+#endif // gd32F30X_SPI_H_INCLUDED
diff --git a/bsp/gd32e230k-start/drivers/drv_usart.c b/bsp/gd32e230k-start/drivers/drv_usart.c
new file mode 100644
index 0000000000..c34ca232cb
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/drv_usart.c
@@ -0,0 +1,381 @@
+/*
+ * File      : drv_usart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2018-04-19     misonyo      Porting for gd32f30x
+ */
+
+#include <rthw.h>
+#include <drv_usart.h>
+#include <rtthread.h>
+#include "gd32e230.h"
+
+#ifdef RT_USING_SERIAL
+
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) && \
+    !defined(RT_USING_USART2) && !defined(RT_USING_UART3)  && \
+    !defined(RT_USING_UART4)
+#error "Please define at least one UARTx"
+
+#endif
+
+#include <rtdevice.h>
+
+/* GD32 uart driver */
+// Todo: compress uart info
+struct gd32_uart
+{
+    uint32_t uart_periph;
+    IRQn_Type irqn;
+    rcu_periph_enum per_clk;
+    rcu_periph_enum tx_gpio_clk;
+    rcu_periph_enum rx_gpio_clk;
+    uint32_t tx_port;
+    uint16_t tx_pin;
+    uint32_t rx_port;
+    uint16_t rx_pin; 
+
+    struct rt_serial_device * serial;
+    char *device_name;
+};
+
+static void uart_isr(struct rt_serial_device *serial);
+
+#if defined(RT_USING_USART0)
+struct rt_serial_device serial0;
+
+void USART0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial0);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_USART0 */
+
+#if defined(RT_USING_USART1)
+struct rt_serial_device serial1;
+
+void USART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial1);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_UART1 */
+
+#if defined(RT_USING_USART2)
+struct rt_serial_device serial2;
+
+void USART2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial2);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_UART2 */
+
+#if defined(RT_USING_UART3)
+struct rt_serial_device serial3;
+
+void UART3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial3);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_UART3 */
+
+#if defined(RT_USING_UART4)
+struct rt_serial_device serial4;
+
+void UART4_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial4);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_USING_UART4 */
+
+static const struct gd32_uart uarts[] = {
+    #ifdef RT_USING_USART0
+    {
+        USART0,                                 // uart peripheral index
+        USART0_IRQn,                            // uart iqrn
+        RCU_USART0, RCU_GPIOA, RCU_GPIOA,       // periph clock, tx gpio clock, rt gpio clock
+        GPIOA, GPIO_PIN_9,                      // tx port, tx pin
+        GPIOA, GPIO_PIN_10,                     // rx port, rx pin
+        &serial0,
+        "uart0",
+    },
+    #endif
+    
+    #ifdef RT_USING_USART1
+    {
+        USART1,                                 // uart peripheral index
+        USART1_IRQn,                            // uart iqrn
+        RCU_USART1, RCU_GPIOA, RCU_GPIOA,       // periph clock, tx gpio clock, rt gpio clock
+        GPIOA, GPIO_PIN_2,                      // tx port, tx pin
+        GPIOA, GPIO_PIN_3,                      // rx port, rx pin
+        &serial1,
+        "uart1",
+    },
+    #endif
+    
+    #ifdef RT_USING_USART2
+    {
+        USART2,                                 // uart peripheral index
+        USART2_IRQn,                            // uart iqrn
+        RCU_USART2, RCU_GPIOB, RCU_GPIOB,       // periph clock, tx gpio clock, rt gpio clock
+        GPIOB, GPIO_PIN_10,                     // tx port, tx alternate, tx pin
+        GPIOB, GPIO_PIN_11,                     // rx port, rx alternate, rx pin
+        &serial2,
+        "uart2",
+    },
+    #endif
+    
+    #ifdef RT_USING_UART3
+    {
+        UART3,                                 // uart peripheral index
+        UART3_IRQn,                            // uart iqrn
+        RCU_UART3, RCU_GPIOC, RCU_GPIOC,       // periph clock, tx gpio clock, rt gpio clock
+        GPIOC, GPIO_PIN_10,                    // tx port, tx alternate, tx pin
+        GPIOC, GPIO_PIN_11,                    // rx port, rx alternate, rx pin
+        &serial3,
+        "uart3",
+    },
+    #endif
+    
+    #ifdef RT_USING_UART4
+    {
+        UART4,                                 // uart peripheral index
+        UART4_IRQn,                            // uart iqrn
+        RCU_UART4, RCU_GPIOC, RCU_GPIOD,       // periph clock, tx gpio clock, rt gpio clock
+        GPIOC, GPIO_PIN_12,                    // tx port, tx alternate, tx pin
+        GPIOD, GPIO_PIN_2,                     // rx port, rx alternate, rx pin
+        &serial4,
+        "uart4",
+    },
+    #endif
+};
+
+
+/**
+* @brief UART MSP Initialization
+*        This function configures the hardware resources used in this example:
+*           - Peripheral's clock enable
+*           - Peripheral's GPIO Configuration
+*           - NVIC configuration for UART interrupt request enable
+* @param uart: UART handle pointer
+* @retval None
+*/
+void gd32_uart_gpio_init(struct gd32_uart *uart)
+{
+    /* enable USART clock */
+    rcu_periph_clock_enable(uart->tx_gpio_clk);
+    rcu_periph_clock_enable(uart->rx_gpio_clk);
+    rcu_periph_clock_enable(uart->per_clk);
+
+    /* connect port to USARTx_Tx */
+    gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->tx_pin);
+    gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->tx_pin);
+	
+    /* connect port to USARTx_Rx */
+    gpio_mode_set(uart->rx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, uart->rx_pin);
+	
+    NVIC_SetPriority(uart->irqn, 0);
+    NVIC_EnableIRQ(uart->irqn);
+}
+
+static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct gd32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = (struct gd32_uart *)serial->parent.user_data;
+    
+    gd32_uart_gpio_init(uart);
+    
+    usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
+
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_9:
+        usart_word_length_set(uart->uart_periph, USART_WL_9BIT);
+        break;
+
+    default:
+        usart_word_length_set(uart->uart_periph, USART_WL_8BIT);
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_2:
+        usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT);
+        break;
+    default:
+        usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT);
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_ODD:
+        usart_parity_config(uart->uart_periph, USART_PM_ODD);
+        break;
+    case PARITY_EVEN:
+        usart_parity_config(uart->uart_periph, USART_PM_EVEN);
+        break;
+    default:
+        usart_parity_config(uart->uart_periph, USART_PM_NONE);
+        break;
+    }
+
+    usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE);
+    usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE);
+    usart_enable(uart->uart_periph);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct gd32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct gd32_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->irqn);
+        /* disable interrupt */
+        usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE);
+
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(uart->irqn);
+        /* enable interrupt */
+        usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int gd32_putc(struct rt_serial_device *serial, char ch)
+{
+    struct gd32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct gd32_uart *)serial->parent.user_data;
+
+    usart_data_transmit(uart->uart_periph, ch);
+    while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
+    
+    return 1;
+}
+
+static int gd32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct gd32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct gd32_uart *)serial->parent.user_data;
+
+    ch = -1;
+    if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)
+        ch = usart_data_receive(uart->uart_periph);
+    return ch;
+}
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+    struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    /* UART in mode Receiver */
+    if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) &&
+            (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET))
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        /* Clear RXNE interrupt flag */
+        usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE);
+    }
+}
+
+static const struct rt_uart_ops gd32_uart_ops =
+{
+    gd32_configure,
+    gd32_control,
+    gd32_putc,
+    gd32_getc
+};
+
+int gd32_hw_usart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    int i;
+
+    for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
+    {
+        uarts[i].serial->ops    = &gd32_uart_ops;
+        uarts[i].serial->config = config;
+
+        /* register UART device */
+        rt_hw_serial_register(uarts[i].serial,
+                              uarts[i].device_name,
+                              RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                              (void *)&uarts[i]);
+    }
+
+    return 0;
+}
+INIT_BOARD_EXPORT(gd32_hw_usart_init);
+#endif
diff --git a/bsp/gd32e230k-start/drivers/drv_usart.h b/bsp/gd32e230k-start/drivers/drv_usart.h
new file mode 100644
index 0000000000..2158016272
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/drv_usart.h
@@ -0,0 +1,19 @@
+/*
+ * File      : drv_usart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+#ifndef __USART_H__
+#define __USART_H__
+
+
+#endif
diff --git a/bsp/gd32e230k-start/drivers/gd32e230_libopt.h b/bsp/gd32e230k-start/drivers/gd32e230_libopt.h
new file mode 100644
index 0000000000..61010d794f
--- /dev/null
+++ b/bsp/gd32e230k-start/drivers/gd32e230_libopt.h
@@ -0,0 +1,60 @@
+/*!
+    \file    gd32e230_libopt.h
+    \brief   library optional for gd32e230
+    
+    \version 2018-06-19, V1.0.0, firmware for GD32E230
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32E230_LIBOPT_H
+#define GD32E230_LIBOPT_H
+
+#include "gd32e230_adc.h"
+#include "gd32e230_crc.h"
+#include "gd32e230_dbg.h"
+#include "gd32e230_dma.h"
+#include "gd32e230_exti.h"
+#include "gd32e230_fmc.h"
+#include "gd32e230_gpio.h"
+#include "gd32e230_syscfg.h"
+#include "gd32e230_i2c.h"
+#include "gd32e230_fwdgt.h"
+#include "gd32e230_pmu.h"
+#include "gd32e230_rcu.h"
+#include "gd32e230_rtc.h"
+#include "gd32e230_spi.h"
+#include "gd32e230_timer.h"
+#include "gd32e230_usart.h"
+#include "gd32e230_wwdgt.h"
+#include "gd32e230_misc.h"
+#include "gd32e230_cmp.h"
+
+#endif /* GD32E230_LIBOPT_H */
diff --git a/bsp/gd32e230k-start/gd32_rom.icf b/bsp/gd32e230k-start/gd32_rom.icf
new file mode 100644
index 0000000000..d6665c3649
--- /dev/null
+++ b/bsp/gd32e230k-start/gd32_rom.icf
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807ffff;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_heap__   = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+export symbol __ICFEDIT_region_RAM_end__;
+
+define symbol __region_RAM1_start__ = 0x10000000;
+define symbol __region_RAM1_end__   = 0x1000FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM1_region  = mem:[from __region_RAM1_start__   to __region_RAM1_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };                        
+place in RAM1_region  { section .sram };
\ No newline at end of file
diff --git a/bsp/gd32e230k-start/gd32_rom.ld b/bsp/gd32e230k-start/gd32_rom.ld
new file mode 100644
index 0000000000..a017d88f4d
--- /dev/null
+++ b/bsp/gd32e230k-start/gd32_rom.ld
@@ -0,0 +1,142 @@
+/*
+ * linker script for GD32F30x with GNU ld
+ * bernard.xiong 2009-10-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  64k /* 64KB sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/gd32e230k-start/gd32_rom.sct b/bsp/gd32e230k-start/gd32_rom.sct
new file mode 100644
index 0000000000..abc5462a3f
--- /dev/null
+++ b/bsp/gd32e230k-start/gd32_rom.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x000080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x000080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00010000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/gd32e230k-start/project.uvoptx b/bsp/gd32e230k-start/project.uvoptx
new file mode 100644
index 0000000000..c97d8a37d1
--- /dev/null
+++ b/bsp/gd32e230k-start/project.uvoptx
@@ -0,0 +1,1301 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread_gd32f30x</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>19</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2V8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\components\libc\compilers\armlibc\time.c</PathWithFileName>
+      <FilenameWithoutPath>time.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>
diff --git a/bsp/gd32e230k-start/project.uvprojx b/bsp/gd32e230k-start/project.uvprojx
new file mode 100644
index 0000000000..66d282d567
--- /dev/null
+++ b/bsp/gd32e230k-start/project.uvprojx
@@ -0,0 +1,952 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread_gd32f30x</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>6120000::V6.12::.\ARMCLANG</pArmCC>
+      <pCCUsed>6120000::V6.12::.\ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>GD32E230K8</Device>
+          <Vendor>GigaDevice</Vendor>
+          <PackID>GigaDevice.GD32E230_DFP.1.0.0</PackID>
+          <PackURL>http://gd32mcu.21ic.com/data/documents/yingyongruanjian</PackURL>
+          <Cpu>IRAM(0x20000000,0x0002000) IROM(0x08000000,0x0010000) CPUTYPE("Cortex-M23") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:GD32E230K8$Device\Include\gd32e230.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:GD32E230K8$SVD\GD32E230.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread-gd32f30x</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M23"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x2000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x10000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>7</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>GD32E230, RT_USING_ARM_LIBC</Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;.;drivers;Libraries\CMSIS;..\..\include;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;.\Libraries\GD32E230_standard_peripheral\Include;.\Libraries\CMSIS\GD\GD32E230\Include;..\..\libcpu\arm\cortex-m23</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_gpio.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>GD32_Lib</GroupName>
+          <Files>
+            <File>
+              <FileName>gd32e230_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_cmp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_cmp.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_dbg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_dbg.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_fmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_fmc.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_fwdgt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_fwdgt.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_pmu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_pmu.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_rcu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_rcu.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32e230_wwdgt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_wwdgt.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_gd32e230.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Libraries\CMSIS\GD\GD32E230\Source\system_gd32e230.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_gd32e230.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Libraries\CMSIS\GD\GD32E230\Source\ARM\startup_gd32e230.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>signal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\signal.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORTEX-M23</GroupName>
+          <Files>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m23\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m23\context_rvds.S</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Filesystem</GroupName>
+          <Files>
+            <File>
+              <FileName>dfs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\dfs\src\dfs.c</FilePath>
+            </File>
+            <File>
+              <FileName>dfs_file.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\dfs\src\dfs_file.c</FilePath>
+            </File>
+            <File>
+              <FileName>dfs_fs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\dfs\src\dfs_fs.c</FilePath>
+            </File>
+            <File>
+              <FileName>dfs_posix.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\dfs\src\dfs_posix.c</FilePath>
+            </File>
+            <File>
+              <FileName>devfs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\dfs\filesystems\devfs\devfs.c</FilePath>
+            </File>
+            <File>
+              <FileName>dfs_elm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\dfs\filesystems\elmfat\dfs_elm.c</FilePath>
+            </File>
+            <File>
+              <FileName>ff.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\dfs\filesystems\elmfat\ff.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>0</GenerateAssemblyFile>
+              <AssembleAssemblyFile>0</AssembleAssemblyFile>
+              <PublicsOnly>0</PublicsOnly>
+              <StopOnExitCode>3</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>0</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <uGnu>2</uGnu>
+                <useXO>2</useXO>
+                <v6Lang>0</v6Lang>
+                <v6LangP>0</v6LangP>
+                <vShortEn>2</vShortEn>
+                <vShortWch>2</vShortWch>
+                <v6Lto>2</v6Lto>
+                <v6WtE>2</v6WtE>
+                <v6Rtti>2</v6Rtti>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <uClangAs>2</uClangAs>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>i2c_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\i2c\i2c_core.c</FilePath>
+            </File>
+            <File>
+              <FileName>i2c_dev.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\i2c\i2c_dev.c</FilePath>
+            </File>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\spi\spi_core.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_dev.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\spi\spi_dev.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>waitqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\symbol.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh_cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_file.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh_file.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_token.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>libc</GroupName>
+          <Files>
+            <File>
+              <FileName>libc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath>
+            </File>
+            <File>
+              <FileName>libc_syms.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\libc_syms.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem_std.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\mem_std.c</FilePath>
+            </File>
+            <File>
+              <FileName>stdio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\stdio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stubs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\stubs.c</FilePath>
+            </File>
+            <File>
+              <FileName>time.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\time.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
+        <targetInfos>
+          <targetInfo name="rt-thread_gd32f30x"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+</Project>
diff --git a/bsp/gd32e230k-start/rtconfig.h b/bsp/gd32e230k-start/rtconfig.h
new file mode 100644
index 0000000000..77e9056395
--- /dev/null
+++ b/bsp/gd32e230k-start/rtconfig.h
@@ -0,0 +1,158 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+#define RT_USING_OVERFLOW_CHECK
+#define RT_DEBUG_INIT 0
+#define RT_DEBUG_THREAD 0
+#define RT_USING_HOOK
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 4
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_0
+#define RT_DFS_ELM_USE_LFN 0
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
+#define RT_DFS_ELM_REENTRANT
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_USING_I2C
+#define RT_USING_PIN
+#define RT_USING_SPI
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+
+/* Network stack */
+
+/* light weight TCP/IP stack */
+
+
+/* Modbus master and slave stack */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* system packages */
+
+/* RT-Thread GUI Engine */
+
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* miscellaneous packages */
+
+
+/* example package: hello */
+
+#define RT_USING_USART0
+#define RT_USING_USART1
+#define RT_USING_SPI0
+#define RT_USING_SPI1
+#define RT_USING_I2C0
+
+#endif
diff --git a/bsp/gd32e230k-start/rtconfig.py b/bsp/gd32e230k-start/rtconfig.py
new file mode 100644
index 0000000000..c631bc3e44
--- /dev/null
+++ b/bsp/gd32e230k-start/rtconfig.py
@@ -0,0 +1,126 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM 	= 'armcc'
+    EXEC_PATH 	= r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM 	= 'iar'
+    EXEC_PATH 	= r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # tool-chains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+	
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct'
+
+    LFLAGS += ' --keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)' 
+
+    EXEC_PATH += '/ARM/ARMCC/bin'
+    print(EXEC_PATH)
+
+    CFLAGS += ' --c99'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --debug'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M4'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' -Ol'
+    CFLAGS += ' --use_c++_inline'
+
+    AFLAGS = ''
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M4'
+    AFLAGS += ' --fpu None'
+
+    LFLAGS = ' --config gd32_rom.icf'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny'
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+    LFLAGS += ' --entry __iar_program_start'
+
+    EXEC_PATH += '/arm/bin/'
+    POST_ACTION = ''
+
diff --git a/bsp/gd32e230k-start/template.uvoptx b/bsp/gd32e230k-start/template.uvoptx
new file mode 100644
index 0000000000..8fc841b0e1
--- /dev/null
+++ b/bsp/gd32e230k-start/template.uvoptx
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread_gd32f30x</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>16000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL010000 -FP0($$Device:GD32F303ZE$Flash\GD32F30x_HD.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>
diff --git a/bsp/gd32e230k-start/template.uvprojx b/bsp/gd32e230k-start/template.uvprojx
new file mode 100644
index 0000000000..9b0a830d22
--- /dev/null
+++ b/bsp/gd32e230k-start/template.uvprojx
@@ -0,0 +1,400 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread_gd32f30x</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>GD32F303ZE</Device>
+          <Vendor>GigaDevice</Vendor>
+          <PackID>GigaDevice.GD32F30x_DFP.1.0.1</PackID>
+          <PackURL>http://gd32mcu.21ic.com/data/documents/yingyongruanjian</PackURL>
+          <Cpu>IRAM(0x20000000-0x2000FFFF)IROM(0x08000000-0x0807FFFF) CLOCK(16000000) CPUTYPE("Cortex-M4")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"Startup\GD\GD32F30x\startup_gd32f30x_hd.s" ("GD32F30x Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>gd32f30x.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\GD\GD32F30x\GD32F30x_HD.SFR</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>GD\GD32F30x\</RegisterFilePath>
+          <DBRegisterFilePath>GD\GD32F30x\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread-gd32f30x</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>4</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;.;drivers;Libraries\CMSIS\GD\GD32F30x\Include;Libraries\CMSIS;Libraries\GD32F30x_standard_peripheral\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--keep *.o(RTMSymTab)  --keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.1" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.1"/>
+        <targetInfos>
+          <targetInfo name="rt-thread_gd32f30x"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+</Project>
diff --git a/libcpu/arm/cortex-m23/SConscript b/libcpu/arm/cortex-m23/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/cortex-m23/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S
new file mode 100644
index 0000000000..d17a8aa12c
--- /dev/null
+++ b/libcpu/arm/cortex-m23/context_gcc.S
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date         Author    Notes
+ * 2009-10-11   Bernard   First version
+ * 2010-12-29   onelife   Modify for EFM32
+ * 2011-06-17   onelife   Merge all of the assembly source code into context_gcc.S
+ * 2011-07-12   onelife   Add interrupt context check function
+ * 2013-06-18   aozima    add restore MSP feature.
+ * 2013-07-09   aozima    enhancement hard fault exception handler.
+ */
+ 
+    .cpu    cortex-m3
+    .fpu    softvfp
+    .syntax unified
+    .thumb
+    .text
+
+    .equ    SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
+    .equ    ICSR, 0xE000ED04                /* interrupt control state register */
+    .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
+    
+    .equ    SHPR3, 0xE000ED20               /* system priority register (3) */
+    .equ    PENDSV_PRI_LOWEST, 0x00FF0000   /* PendSV priority value (lowest) */
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+    .global rt_hw_interrupt_disable
+    .type rt_hw_interrupt_disable, %function
+rt_hw_interrupt_disable:
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+    .global rt_hw_interrupt_enable
+    .type rt_hw_interrupt_enable, %function
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, R0
+    BX      LR
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * R0 --> from
+ * R1 --> to
+ */
+    .global rt_hw_context_switch_interrupt
+    .type rt_hw_context_switch_interrupt, %function
+    .global rt_hw_context_switch
+    .type rt_hw_context_switch, %function
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    /* set rt_thread_switch_interrupt_flag to 1 */
+    LDR     R2, =rt_thread_switch_interrupt_flag
+    LDR     R3, [R2]
+    CMP     R3, #1
+    BEQ     _reswitch
+    MOV     R3, #1
+    STR     R3, [R2]
+
+    LDR     R2, =rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
+    STR     R0, [R2]
+
+_reswitch:
+    LDR     R2, =rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
+    STR     R1, [R2]
+
+    LDR     R0, =ICSR           /* trigger the PendSV exception (causes context switch) */
+    LDR     R1, =PENDSVSET_BIT
+    STR     R1, [R0]
+    BX      LR
+
+/* R0 --> switch from thread stack
+ * R1 --> switch to thread stack
+ * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
+ */
+    .global PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    /* disable interrupt to protect context switch */
+    MRS     R2, PRIMASK
+    CPSID   I
+
+    /* get rt_thread_switch_interrupt_flag */
+    LDR     R0, =rt_thread_switch_interrupt_flag
+    LDR     R1, [R0]
+    CBZ     R1, pendsv_exit         /* pendsv aLReady handled */
+
+    /* clear rt_thread_switch_interrupt_flag to 0 */
+    MOV     R1, #0
+    STR     R1, [R0]
+
+    LDR     R0, =rt_interrupt_from_thread
+    LDR     R1, [R0]
+    CBZ     R1, switch_to_thread    /* skip register save at the first time */
+
+    MRS     R1, PSP                 /* get from thread stack pointer */
+    STMFD   R1!, {R4 - R11}         /* push R4 - R11 register */
+    LDR     R0, [R0]
+    STR     R1, [R0]                /* update from thread stack pointer */
+
+switch_to_thread:
+    LDR     R1, =rt_interrupt_to_thread
+    LDR     R1, [R1]
+    LDR     R1, [R1]                /* load thread stack pointer */
+
+    LDMFD   R1!, {R4 - R11}         /* pop R4 - R11 register */
+    MSR     PSP, R1                 /* update stack pointer */
+
+pendsv_exit:
+    /* restore interrupt */
+    MSR     PRIMASK, R2
+
+    ORR     LR, LR, #0x04
+    BX      LR
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * R0 --> to
+ */
+    .global rt_hw_context_switch_to
+    .type rt_hw_context_switch_to, %function
+rt_hw_context_switch_to:
+    LDR     R1, =rt_interrupt_to_thread
+    STR     R0, [R1]
+
+    /* set from thread to 0 */
+    LDR     R1, =rt_interrupt_from_thread
+    MOV     R0, #0
+    STR     R0, [R1]
+
+    /* set interrupt flag to 1 */
+    LDR     R1, =rt_thread_switch_interrupt_flag
+    MOV     R0, #1
+    STR     R0, [R1]
+
+    /* set the PendSV exception priority */
+    LDR     R0, =SHPR3
+    LDR     R1, =PENDSV_PRI_LOWEST
+    LDR.W   R2, [R0,#0]             /* read */
+    ORR     R1, R1, R2              /* modify */
+    STR     R1, [R0]                /* write-back */
+
+    LDR     R0, =ICSR               /* trigger the PendSV exception (causes context switch) */
+    LDR     R1, =PENDSVSET_BIT
+    STR     R1, [R0]
+
+    /* restore MSP */
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    /* enable interrupts at processor level */
+    CPSIE   F
+    CPSIE   I
+
+    /* never reach here! */
+
+/* compatible with old version */
+    .global rt_hw_interrupt_thread_switch
+    .type rt_hw_interrupt_thread_switch, %function
+rt_hw_interrupt_thread_switch:
+    BX      LR
+    NOP
+
+    .global HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    /* get current context */
+    MRS     r0, msp                 /* get fault context from handler. */
+    TST     lr, #0x04               /* if(!EXC_RETURN[2]) */
+    BEQ     _get_sp_done
+    MRS     r0, psp                 /* get fault context from thread. */
+_get_sp_done:
+
+    STMFD   r0!, {r4 - r11}         /* push r4 - r11 register */
+    STMFD   r0!, {lr}               /* push exec_return register */
+
+    TST     lr, #0x04               /* if(!EXC_RETURN[2]) */
+    BEQ     _update_msp
+    MSR     psp, r0                 /* update stack pointer to PSP. */
+    B       _update_done
+_update_msp:
+    MSR     msp, r0                 /* update stack pointer to MSP. */
+_update_done:
+
+    PUSH    {LR}
+    BL      rt_hw_hard_fault_exception
+    POP     {LR}
+
+    ORR     LR, LR, #0x04
+    BX      LR
+
+/*
+ * rt_uint32_t rt_hw_interrupt_check(void);
+ * R0 --> state
+ */
+    .global rt_hw_interrupt_check
+    .type rt_hw_interrupt_check, %function
+rt_hw_interrupt_check:
+    MRS     R0, IPSR
+    BX      LR
diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S
new file mode 100644
index 0000000000..91645c48b3
--- /dev/null
+++ b/libcpu/arm/cortex-m23/context_iar.S
@@ -0,0 +1,202 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version
+; * 2009-09-27     Bernard      add protect when contex switch occurs
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2013-07-09     aozima       enhancement hard fault exception handler.
+; */
+
+;/**
+; * @addtogroup cortex-m3
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+    EXPORT rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+    EXPORT  rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, r0
+    BX      LR
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+    EXPORT rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+    EXPORT PendSV_Handler
+PendSV_Handler:
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK
+    CPSID   I
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]
+    CBZ     r1, pendsv_exit         ; pendsv already handled
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOV     r1, #0x00
+    STR     r1, [r0]
+
+    LDR     r0, =rt_interrupt_from_thread
+    LDR     r1, [r0]
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
+
+    MRS     r1, psp                 ; get from thread stack pointer
+    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
+    LDR     r0, [r0]
+    STR     r1, [r0]                ; update from thread stack pointer
+
+switch_to_thread
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                ; load thread stack pointer
+
+    LDMFD   r1!, {r4 - r11}         ; pop r4 - r11 register
+    MSR     psp, r1                 ; update stack pointer
+
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
+    ORR     lr, lr, #0x04
+    BX      lr
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; */
+    EXPORT rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOV     r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    LDR     r0, =NVIC_INT_CTRL      ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   F
+    CPSIE   I
+
+    ; never reach here!
+
+; compatible with old version
+    EXPORT rt_hw_interrupt_thread_switch
+rt_hw_interrupt_thread_switch:
+    BX      lr
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler:
+
+    ; get current context
+    MRS     r0, msp                 ; get fault context from handler.
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    BEQ     _get_sp_done
+    MRS     r0, psp                 ; get fault context from thread.
+_get_sp_done
+
+    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
+    ;STMFD   r0!, {lr}               ; push exec_return register
+    SUB     r0, r0, #0x04
+    STR     lr, [r0]
+
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    BEQ     _update_msp
+    MSR     psp, r0                 ; update stack pointer to PSP.
+    B       _update_done
+_update_msp
+    MSR     msp, r0                 ; update stack pointer to MSP.
+_update_done
+
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+
+    END
diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S
new file mode 100644
index 0000000000..c0a2130703
--- /dev/null
+++ b/libcpu/arm/cortex-m23/context_rvds.S
@@ -0,0 +1,207 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2013-07-09     aozima       enhancement hard fault exception handler.
+; */
+
+;/**
+; * @addtogroup CORTEX-M23
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable    PROC
+    EXPORT  rt_hw_interrupt_disable
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable    PROC
+    EXPORT  rt_hw_interrupt_enable
+    MSR     PRIMASK, r0
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch_interrupt
+rt_hw_context_switch    PROC
+    EXPORT rt_hw_context_switch
+
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+    ENDP
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+PendSV_Handler   PROC
+    EXPORT PendSV_Handler
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK
+    CPSID   I
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]
+    CBZ     r1, pendsv_exit         ; pendsv already handled
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOV     r1, #0x00
+    STR     r1, [r0]
+
+    LDR     r0, =rt_interrupt_from_thread
+    LDR     r1, [r0]
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
+
+    MRS     r1, psp                 ; get from thread stack pointer
+    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
+    LDR     r0, [r0]
+    STR     r1, [r0]                ; update from thread stack pointer
+
+switch_to_thread
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                ; load thread stack pointer
+
+    LDMFD   r1!, {r4 - r11}         ; pop r4 - r11 register
+    MSR     psp, r1                 ; update stack pointer
+
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
+    ORR     lr, lr, #0x04
+    BX      lr
+    ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to    PROC
+    EXPORT rt_hw_context_switch_to
+    ; set to thread
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOV     r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    ; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   F
+    CPSIE   I
+
+    ; never reach here!
+    ENDP
+
+; compatible with old version
+rt_hw_interrupt_thread_switch PROC
+    EXPORT rt_hw_interrupt_thread_switch
+    BX      lr
+    ENDP
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler    PROC
+
+    ; get current context
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    ITE     EQ
+    MRSEQ   r0, msp                 ; [2]=0 ==> Z=1, get fault context from handler.
+    MRSNE   r0, psp                 ; [2]=1 ==> Z=0, get fault context from thread.
+
+    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
+    STMFD   r0!, {lr}               ; push exec_return register
+
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    ITE     EQ
+    MSREQ   msp, r0                 ; [2]=0 ==> Z=1, update stack pointer to MSP.
+    MSRNE   psp, r0                 ; [2]=1 ==> Z=0, update stack pointer to PSP.
+
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+    ENDP
+
+    ALIGN   4
+
+    END
diff --git a/libcpu/arm/cortex-m23/cpuport.c b/libcpu/arm/cortex-m23/cpuport.c
new file mode 100644
index 0000000000..a386747750
--- /dev/null
+++ b/libcpu/arm/cortex-m23/cpuport.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2009-01-05   Bernard     first version
+ * 2011-02-14   onelife     Modify for EFM32
+ * 2011-06-17   onelife     Merge all of the C source code into cpuport.c
+ * 2012-12-23   aozima      stack addr align to 8byte.
+ * 2012-12-29   Bernard     Add exception hook.
+ * 2013-07-09   aozima      enhancement hard fault exception handler.
+ */
+
+#include <rtthread.h>
+
+struct exception_stack_frame
+{
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r12;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t psr;
+};
+
+struct stack_frame
+{
+    /* r4 ~ r11 register */
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+
+    struct exception_stack_frame exception_stack_frame;
+};
+
+/* flag in interrupt handling */
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+/* exception hook */
+static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct stack_frame *stack_frame;
+    rt_uint8_t         *stk;
+    unsigned long       i;
+
+    stk  = stack_addr + sizeof(rt_uint32_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
+    stk -= sizeof(struct stack_frame);
+
+    stack_frame = (struct stack_frame *)stk;
+
+    /* init all register */
+    for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
+    {
+        ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
+    }
+
+    stack_frame->exception_stack_frame.r0  = (unsigned long)parameter; /* r0 : argument */
+    stack_frame->exception_stack_frame.r1  = 0;                        /* r1 */
+    stack_frame->exception_stack_frame.r2  = 0;                        /* r2 */
+    stack_frame->exception_stack_frame.r3  = 0;                        /* r3 */
+    stack_frame->exception_stack_frame.r12 = 0;                        /* r12 */
+    stack_frame->exception_stack_frame.lr  = (unsigned long)texit;     /* lr */
+    stack_frame->exception_stack_frame.pc  = (unsigned long)tentry;    /* entry point, pc */
+    stack_frame->exception_stack_frame.psr = 0x01000000L;              /* PSR */
+
+    /* return task's current stack address */
+    return stk;
+}
+
+/**
+ * This function set the hook, which is invoked on fault exception handling.
+ *
+ * @param exception_handle the exception handling hook function.
+ */
+void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context))
+{
+    rt_exception_hook = exception_handle;
+}
+
+#define SCB_CFSR        (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
+#define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
+#define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
+#define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED0C)  /* Reset control Address Register */
+#define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
+
+#define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
+#define SCB_CFSR_BFSR   (*(volatile const unsigned char*)0xE000ED29)  /* Bus Fault Status Register */
+#define SCB_CFSR_UFSR   (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
+
+#ifdef RT_USING_FINSH
+static void usage_fault_track(void)
+{
+    rt_kprintf("usage fault:\n");
+    rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
+
+    if(SCB_CFSR_UFSR & (1<<0))
+    {
+        /* [0]:UNDEFINSTR */
+        rt_kprintf("UNDEFINSTR ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<1))
+    {
+        /* [1]:INVSTATE */
+        rt_kprintf("INVSTATE ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<2))
+    {
+        /* [2]:INVPC */
+        rt_kprintf("INVPC ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<3))
+    {
+        /* [3]:NOCP */
+        rt_kprintf("NOCP ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<8))
+    {
+        /* [8]:UNALIGNED */
+        rt_kprintf("UNALIGNED ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<9))
+    {
+        /* [9]:DIVBYZERO */
+        rt_kprintf("DIVBYZERO ");
+    }
+
+    rt_kprintf("\n");
+}
+
+static void bus_fault_track(void)
+{
+    rt_kprintf("bus fault:\n");
+    rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
+
+    if(SCB_CFSR_BFSR & (1<<0))
+    {
+        /* [0]:IBUSERR */
+        rt_kprintf("IBUSERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<1))
+    {
+        /* [1]:PRECISERR */
+        rt_kprintf("PRECISERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<2))
+    {
+        /* [2]:IMPRECISERR */
+        rt_kprintf("IMPRECISERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<3))
+    {
+        /* [3]:UNSTKERR */
+        rt_kprintf("UNSTKERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<4))
+    {
+        /* [4]:STKERR */
+        rt_kprintf("STKERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<7))
+    {
+        rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR);
+    }
+    else
+    {
+        rt_kprintf("\n");
+    }
+}
+
+static void mem_manage_fault_track(void)
+{
+    rt_kprintf("mem manage fault:\n");
+    rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
+
+    if(SCB_CFSR_MFSR & (1<<0))
+    {
+        /* [0]:IACCVIOL */
+        rt_kprintf("IACCVIOL ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<1))
+    {
+        /* [1]:DACCVIOL */
+        rt_kprintf("DACCVIOL ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<3))
+    {
+        /* [3]:MUNSTKERR */
+        rt_kprintf("MUNSTKERR ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<4))
+    {
+        /* [4]:MSTKERR */
+        rt_kprintf("MSTKERR ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<7))
+    {
+        /* [7]:MMARVALID */
+        rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR);
+    }
+    else
+    {
+        rt_kprintf("\n");
+    }
+}
+
+static void hard_fault_track(void)
+{
+    if(SCB_HFSR & (1UL<<1))
+    {
+        /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */
+        rt_kprintf("failed vector fetch\n");
+    }
+
+    if(SCB_HFSR & (1UL<<30))
+    {
+        /* [30]:FORCED, Indicates hard fault is taken because of bus fault,
+                        memory management fault, or usage fault. */
+        if(SCB_CFSR_BFSR)
+        {
+            bus_fault_track();
+        }
+
+        if(SCB_CFSR_MFSR)
+        {
+            mem_manage_fault_track();
+        }
+
+        if(SCB_CFSR_UFSR)
+        {
+            usage_fault_track();
+        }
+    }
+
+    if(SCB_HFSR & (1UL<<31))
+    {
+        /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */
+        rt_kprintf("debug event\n");
+    }
+}
+#endif /* RT_USING_FINSH */
+
+struct exception_info
+{
+    rt_uint32_t exc_return;
+    struct stack_frame stack_frame;
+};
+
+/*
+ * fault exception handler
+ */
+void rt_hw_hard_fault_exception(struct exception_info * exception_info)
+{
+    extern long list_thread(void);
+    struct stack_frame* context = &exception_info->stack_frame;
+
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(exception_info);
+        if (result == RT_EOK)
+            return;
+    }
+
+    rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr);
+
+    rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0);
+    rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1);
+    rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2);
+    rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3);
+    rt_kprintf("r04: 0x%08x\n", context->r4);
+    rt_kprintf("r05: 0x%08x\n", context->r5);
+    rt_kprintf("r06: 0x%08x\n", context->r6);
+    rt_kprintf("r07: 0x%08x\n", context->r7);
+    rt_kprintf("r08: 0x%08x\n", context->r8);
+    rt_kprintf("r09: 0x%08x\n", context->r9);
+    rt_kprintf("r10: 0x%08x\n", context->r10);
+    rt_kprintf("r11: 0x%08x\n", context->r11);
+    rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12);
+    rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr);
+    rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc);
+
+    if(exception_info->exc_return & (1 << 2) )
+    {
+        rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name);
+
+#ifdef RT_USING_FINSH
+        list_thread();
+#endif /* RT_USING_FINSH */
+    }
+    else
+    {
+        rt_kprintf("hard fault on handler\r\n\r\n");
+    }
+
+#ifdef RT_USING_FINSH
+    hard_fault_track();
+#endif /* RT_USING_FINSH */
+
+    while (1);
+}
+
+/**
+ * shutdown CPU
+ */
+void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    RT_ASSERT(0);
+}
+
+/**
+ * reset CPU
+ */
+RT_WEAK void rt_hw_cpu_reset(void)
+{
+    SCB_AIRCR = SCB_RESET_VALUE;
+}
+
+#ifdef RT_USING_CPU_FFS
+/**
+ * This function finds the first bit set (beginning with the least significant bit)
+ * in value and return the index of that bit.
+ *
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
+ * zero from any of these functions means that the argument was zero.
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
+ * shall return 0.
+ */
+#if defined(__CC_ARM)
+__asm int __rt_ffs(int value)
+{
+    CMP     r0, #0x00
+    BEQ     exit
+
+    RBIT    r0, r0
+    CLZ     r0, r0
+    ADDS    r0, r0, #0x01
+
+exit
+    BX      lr
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+int __rt_ffs(int value)
+{
+    if (value == 0) return value;
+
+    asm("RBIT %0, %1" : "=r"(value) : "r"(value));
+    asm("CLZ  %0, %1" : "=r"(value) : "r"(value));
+    asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value));
+
+    return value;
+}
+#elif defined(__GNUC__)
+int __rt_ffs(int value)
+{
+    return __builtin_ffs(value);
+}
+#endif
+
+#endif
-- 
cgit v1.3.1


From 5a460aadcd1df4fcfb14aafeb248230a47e9cbeb Mon Sep 17 00:00:00 2001
From: xuzhuoyi <xzy476386434@vip.qq.com>
Date: Sun, 31 Mar 2019 21:17:55 +0800
Subject: [bsp][gd32e230k-start] Update Sconscript

---
 bsp/gd32e230k-start/Libraries/SConscript |  22 +-
 bsp/gd32e230k-start/SConstruct           |   2 +-
 bsp/gd32e230k-start/drivers/SConscript   |   4 -
 bsp/gd32e230k-start/drivers/board.h      |   2 +-
 bsp/gd32e230k-start/project.uvoptx       | 564 ++++++++++++-------------------
 bsp/gd32e230k-start/project.uvprojx      | 318 +++++++----------
 bsp/gd32e230k-start/rtconfig.h           |  61 ++--
 bsp/gd32e230k-start/rtconfig.py          |   4 +-
 bsp/gd32e230k-start/template.uvoptx      |  18 +-
 bsp/gd32e230k-start/template.uvprojx     |  62 ++--
 libcpu/arm/cortex-m23/context_gcc.S      | 122 +++----
 libcpu/arm/cortex-m23/context_iar.S      |  90 ++---
 libcpu/arm/cortex-m23/context_rvds.S     |  84 ++---
 libcpu/arm/cortex-m23/cpuport.c          | 328 ++----------------
 14 files changed, 618 insertions(+), 1063 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/gd32e230k-start/Libraries/SConscript b/bsp/gd32e230k-start/Libraries/SConscript
index eb4cfb77c7..e79dc34216 100644
--- a/bsp/gd32e230k-start/Libraries/SConscript
+++ b/bsp/gd32e230k-start/Libraries/SConscript
@@ -6,27 +6,21 @@ cwd = GetCurrentDir()
 
 # The set of source files associated with this SConscript file.
 
-src = Glob('GD32F30x_standard_peripheral/Source/*.c')
-src += [cwd + '/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c']
+src = Glob('GD32E230_standard_peripheral/Source/*.c')
+src += [cwd + '/CMSIS/GD/GD32E230/Source/system_gd32e230.c']
 
 #add for startup script
-if rtconfig.CROSS_TOOL == 'gcc':
-    src += [cwd + '/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.s']
-elif rtconfig.CROSS_TOOL == 'keil':
-    src += [cwd + '/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s']
+if rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s']
 elif rtconfig.CROSS_TOOL == 'iar':
-    src += [cwd + '/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s']
+    src += [cwd + '/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s']
 
 path = [
-    cwd + '/CMSIS/GD/GD32F30x/Include',
+    cwd + '/CMSIS/GD/GD32E230/Include',
     cwd + '/CMSIS',
-    cwd + '/GD32F30x_standard_peripheral/Include',]
-    
-if GetDepend(['RT_USING_BSP_USB']):
-    path += [cwd + '/GD32F30x_usb_driver/Include']
-    src  += [cwd + '/GD32F30x_usb_driver/Source']
+    cwd + '/GD32E230_standard_peripheral/Include',]
 
-CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F30X_HD']
+CPPDEFINES = ['GD32E230']
 
 group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
 
diff --git a/bsp/gd32e230k-start/SConstruct b/bsp/gd32e230k-start/SConstruct
index 1cdbaab4a8..57a8ac59fc 100644
--- a/bsp/gd32e230k-start/SConstruct
+++ b/bsp/gd32e230k-start/SConstruct
@@ -15,7 +15,7 @@ except:
     print(RTT_ROOT)
     exit(-1)
 
-TARGET = 'rtthread-gd32f30x.' + rtconfig.TARGET_EXT
+TARGET = 'rtthread-gd32f230.' + rtconfig.TARGET_EXT
 
 env = Environment(tools = ['mingw'],
     AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
diff --git a/bsp/gd32e230k-start/drivers/SConscript b/bsp/gd32e230k-start/drivers/SConscript
index ef03e2dcf0..45fd672f5f 100644
--- a/bsp/gd32e230k-start/drivers/SConscript
+++ b/bsp/gd32e230k-start/drivers/SConscript
@@ -24,10 +24,6 @@ if GetDepend('RT_USING_I2C'):
 if GetDepend('RT_USING_PIN'):
     src += ['drv_gpio.c']
 
-# add spi flash drivers.
-if GetDepend('RT_USING_SFUD'):
-    src += ['drv_spi_flash.c']
-
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/bsp/gd32e230k-start/drivers/board.h b/bsp/gd32e230k-start/drivers/board.h
index de344e8768..bff43464b4 100644
--- a/bsp/gd32e230k-start/drivers/board.h
+++ b/bsp/gd32e230k-start/drivers/board.h
@@ -29,7 +29,7 @@ extern char __ICFEDIT_region_RAM_end__;
 #define GD32_SRAM_END          (0x20000000 + GD32_SRAM_SIZE * 1024)
 #endif
 
-#ifdef __CC_ARM
+#ifdef __ARMCC_VERSION
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__
diff --git a/bsp/gd32e230k-start/project.uvoptx b/bsp/gd32e230k-start/project.uvoptx
index c97d8a37d1..aa084f2049 100644
--- a/bsp/gd32e230k-start/project.uvoptx
+++ b/bsp/gd32e230k-start/project.uvoptx
@@ -22,7 +22,7 @@
   </DaveTm>
 
   <Target>
-    <TargetName>rt-thread_gd32f30x</TargetName>
+    <TargetName>rt-thread_gd32e230</TargetName>
     <ToolsetNumber>0x4</ToolsetNumber>
     <ToolsetName>ARM-ADS</ToolsetName>
     <TargetOption>
@@ -103,7 +103,7 @@
         <bEvRecOn>1</bEvRecOn>
         <bSchkAxf>0</bSchkAxf>
         <bTchkAxf>0</bTchkAxf>
-        <nTsel>19</nTsel>
+        <nTsel>14</nTsel>
         <sDll></sDll>
         <sDllPa></sDllPa>
         <sDlgDll></sDlgDll>
@@ -175,8 +175,8 @@
   </Target>
 
   <Group>
-    <GroupName>Applications</GroupName>
-    <tvExp>1</tvExp>
+    <GroupName>Kernel</GroupName>
+    <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
@@ -187,207 +187,207 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>applications\main.c</PathWithFileName>
-      <FilenameWithoutPath>main.c</FilenameWithoutPath>
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+      <PathWithFileName>Libraries\GD32E230_standard_peripheral\Source\gd32e230_spi.c</PathWithFileName>
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-      <PathWithFileName>..\..\src\object.c</PathWithFileName>
-      <FilenameWithoutPath>object.c</FilenameWithoutPath>
+      <PathWithFileName>Libraries\GD32E230_standard_peripheral\Source\gd32e230_syscfg.c</PathWithFileName>
+      <FilenameWithoutPath>gd32e230_syscfg.c</FilenameWithoutPath>
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@@ -655,8 +655,8 @@
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-      <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
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@@ -667,8 +667,8 @@
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-      <FilenameWithoutPath>signal.c</FilenameWithoutPath>
+      <PathWithFileName>Libraries\GD32E230_standard_peripheral\Source\gd32e230_usart.c</PathWithFileName>
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@@ -691,22 +691,34 @@
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-      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
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-    <tvExp>1</tvExp>
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@@ -718,7 +730,7 @@
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@@ -730,7 +742,7 @@
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@@ -742,7 +754,7 @@
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@@ -767,23 +779,11 @@
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-      <FilenameWithoutPath>libc_syms.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>84</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\armlibc\mem_std.c</PathWithFileName>
-      <FilenameWithoutPath>mem_std.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>85</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\armlibc\stdio.c</PathWithFileName>
-      <FilenameWithoutPath>stdio.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>86</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\armlibc\stubs.c</PathWithFileName>
-      <FilenameWithoutPath>stubs.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>9</GroupNumber>
-      <FileNumber>87</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\armlibc\time.c</PathWithFileName>
-      <FilenameWithoutPath>time.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-  </Group>
-
   <Group>
     <GroupName>::CMSIS</GroupName>
     <tvExp>0</tvExp>
diff --git a/bsp/gd32e230k-start/project.uvprojx b/bsp/gd32e230k-start/project.uvprojx
index 66d282d567..4466ae7d45 100644
--- a/bsp/gd32e230k-start/project.uvprojx
+++ b/bsp/gd32e230k-start/project.uvprojx
@@ -7,11 +7,10 @@
 
   <Targets>
     <Target>
-      <TargetName>rt-thread_gd32f30x</TargetName>
+      <TargetName>rt-thread_gd32e230</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
-      <pArmCC>6120000::V6.12::.\ARMCLANG</pArmCC>
-      <pCCUsed>6120000::V6.12::.\ARMCLANG</pCCUsed>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
       <uAC6>1</uAC6>
       <TargetOption>
         <TargetCommonOption>
@@ -50,7 +49,7 @@
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
           <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>rtthread-gd32f30x</OutputName>
+          <OutputName>rtthread-gd32e230</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
@@ -313,7 +312,7 @@
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
-            <Optim>7</Optim>
+            <Optim>1</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
             <OneElfS>0</OneElfS>
@@ -322,14 +321,14 @@
             <PlainCh>0</PlainCh>
             <Ropi>0</Ropi>
             <Rwpi>0</Rwpi>
-            <wLevel>3</wLevel>
+            <wLevel>0</wLevel>
             <uThumb>0</uThumb>
             <uSurpInc>0</uSurpInc>
             <uC99>1</uC99>
             <uGnu>0</uGnu>
             <useXO>0</useXO>
-            <v6Lang>3</v6Lang>
-            <v6LangP>3</v6LangP>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
             <vShortEn>1</vShortEn>
             <vShortWch>1</vShortWch>
             <v6Lto>0</v6Lto>
@@ -337,9 +336,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>GD32E230, RT_USING_ARM_LIBC</Define>
+              <Define>GD32E230</Define>
               <Undefine></Undefine>
-              <IncludePath>applications;.;drivers;Libraries\CMSIS;..\..\include;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;.\Libraries\GD32E230_standard_peripheral\Include;.\Libraries\CMSIS\GD\GD32E230\Include;..\..\libcpu\arm\cortex-m23</IncludePath>
+              <IncludePath>.;..\..\include;applications;.;drivers;Libraries\CMSIS\GD\GD32E230\Include;Libraries\CMSIS;Libraries\GD32E230_standard_peripheral\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m23;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\finsh</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -373,13 +372,93 @@
             <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
-            <Misc>--keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc>
+            <Misc></Misc>
             <LinkerInputFile></LinkerInputFile>
             <DisabledWarnings></DisabledWarnings>
           </LDads>
         </TargetArmAds>
       </TargetOption>
       <Groups>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\cpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>signal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\signal.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
         <Group>
           <GroupName>Applications</GroupName>
           <Files>
@@ -426,187 +505,112 @@
             <File>
               <FileName>gd32e230_adc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_adc.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_adc.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_cmp.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_cmp.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_cmp.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_crc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_crc.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_crc.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_dbg.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_dbg.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_dbg.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_dma.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_dma.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_exti.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_exti.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_exti.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_fmc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_fmc.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_fmc.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_fwdgt.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_fwdgt.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_fwdgt.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_gpio.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_gpio.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_gpio.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_i2c.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_i2c.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_i2c.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_misc.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_misc.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_pmu.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_pmu.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_pmu.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_rcu.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_rcu.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_rcu.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_rtc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_rtc.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_rtc.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_spi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_spi.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_spi.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_syscfg.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_syscfg.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_syscfg.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_timer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_timer.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_timer.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_usart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_usart.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_usart.c</FilePath>
             </File>
             <File>
               <FileName>gd32e230_wwdgt.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\GD32E230_standard_peripheral\Source\gd32e230_wwdgt.c</FilePath>
+              <FilePath>Libraries\GD32E230_standard_peripheral\Source\gd32e230_wwdgt.c</FilePath>
             </File>
             <File>
               <FileName>system_gd32e230.c</FileName>
               <FileType>1</FileType>
-              <FilePath>.\Libraries\CMSIS\GD\GD32E230\Source\system_gd32e230.c</FilePath>
+              <FilePath>Libraries\CMSIS\GD\GD32E230\Source\system_gd32e230.c</FilePath>
             </File>
             <File>
               <FileName>startup_gd32e230.s</FileName>
               <FileType>2</FileType>
-              <FilePath>.\Libraries\CMSIS\GD\GD32E230\Source\ARM\startup_gd32e230.s</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Kernel</GroupName>
-          <Files>
-            <File>
-              <FileName>clock.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\clock.c</FilePath>
-            </File>
-            <File>
-              <FileName>components.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\components.c</FilePath>
-            </File>
-            <File>
-              <FileName>device.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\device.c</FilePath>
-            </File>
-            <File>
-              <FileName>idle.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\idle.c</FilePath>
-            </File>
-            <File>
-              <FileName>ipc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\ipc.c</FilePath>
-            </File>
-            <File>
-              <FileName>irq.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\irq.c</FilePath>
-            </File>
-            <File>
-              <FileName>kservice.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\kservice.c</FilePath>
-            </File>
-            <File>
-              <FileName>mem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\mem.c</FilePath>
-            </File>
-            <File>
-              <FileName>mempool.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\mempool.c</FilePath>
-            </File>
-            <File>
-              <FileName>object.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\object.c</FilePath>
-            </File>
-            <File>
-              <FileName>scheduler.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\scheduler.c</FilePath>
-            </File>
-            <File>
-              <FileName>signal.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\signal.c</FilePath>
-            </File>
-            <File>
-              <FileName>thread.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\thread.c</FilePath>
-            </File>
-            <File>
-              <FileName>timer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\timer.c</FilePath>
+              <FilePath>Libraries\CMSIS\GD\GD32E230\Source\ARM\startup_gd32e230.s</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
-          <GroupName>CORTEX-M23</GroupName>
+          <GroupName>cpu</GroupName>
           <Files>
             <File>
               <FileName>backtrace.c</FileName>
@@ -635,46 +639,6 @@
             </File>
           </Files>
         </Group>
-        <Group>
-          <GroupName>Filesystem</GroupName>
-          <Files>
-            <File>
-              <FileName>dfs.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\dfs.c</FilePath>
-            </File>
-            <File>
-              <FileName>dfs_file.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\dfs_file.c</FilePath>
-            </File>
-            <File>
-              <FileName>dfs_fs.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\dfs_fs.c</FilePath>
-            </File>
-            <File>
-              <FileName>dfs_posix.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\dfs_posix.c</FilePath>
-            </File>
-            <File>
-              <FileName>devfs.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\filesystems\devfs\devfs.c</FilePath>
-            </File>
-            <File>
-              <FileName>dfs_elm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\filesystems\elmfat\dfs_elm.c</FilePath>
-            </File>
-            <File>
-              <FileName>ff.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\filesystems\elmfat\ff.c</FilePath>
-            </File>
-          </Files>
-        </Group>
         <Group>
           <GroupName>DeviceDrivers</GroupName>
           <GroupOption>
@@ -720,9 +684,9 @@
                 <v6WtE>2</v6WtE>
                 <v6Rtti>2</v6Rtti>
                 <VariousControls>
-                  <MiscControls></MiscControls>
-                  <Define></Define>
-                  <Undefine></Undefine>
+                  <MiscControls> --c99</MiscControls>
+                  <Define> </Define>
+                  <Undefine> </Undefine>
                   <IncludePath></IncludePath>
                 </VariousControls>
               </Cads>
@@ -777,6 +741,16 @@
               <FileType>1</FileType>
               <FilePath>..\..\components\drivers\spi\spi_dev.c</FilePath>
             </File>
+            <File>
+              <FileName>spi_flash_sfud.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\spi\spi_flash_sfud.c</FilePath>
+            </File>
+            <File>
+              <FileName>sfud.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\spi\sfud\src\sfud.c</FilePath>
+            </File>
             <File>
               <FileName>completion.c</FileName>
               <FileType>1</FileType>
@@ -792,6 +766,11 @@
               <FileType>1</FileType>
               <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
             </File>
+            <File>
+              <FileName>ringblk_buf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
+            </File>
             <File>
               <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
@@ -894,41 +873,6 @@
             </File>
           </Files>
         </Group>
-        <Group>
-          <GroupName>libc</GroupName>
-          <Files>
-            <File>
-              <FileName>libc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath>
-            </File>
-            <File>
-              <FileName>libc_syms.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\libc\compilers\armlibc\libc_syms.c</FilePath>
-            </File>
-            <File>
-              <FileName>mem_std.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\libc\compilers\armlibc\mem_std.c</FilePath>
-            </File>
-            <File>
-              <FileName>stdio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\libc\compilers\armlibc\stdio.c</FilePath>
-            </File>
-            <File>
-              <FileName>stubs.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\libc\compilers\armlibc\stubs.c</FilePath>
-            </File>
-            <File>
-              <FileName>time.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\libc\compilers\armlibc\time.c</FilePath>
-            </File>
-          </Files>
-        </Group>
         <Group>
           <GroupName>::CMSIS</GroupName>
         </Group>
@@ -942,7 +886,7 @@
       <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
         <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
         <targetInfos>
-          <targetInfo name="rt-thread_gd32f30x"/>
+          <targetInfo name="rt-thread_gd32e230"/>
         </targetInfos>
       </component>
     </components>
diff --git a/bsp/gd32e230k-start/rtconfig.h b/bsp/gd32e230k-start/rtconfig.h
index 77e9056395..b490faaf8a 100644
--- a/bsp/gd32e230k-start/rtconfig.h
+++ b/bsp/gd32e230k-start/rtconfig.h
@@ -11,13 +11,13 @@
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 100
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
 #define RT_USING_OVERFLOW_CHECK
-#define RT_DEBUG_INIT 0
-#define RT_DEBUG_THREAD 0
 #define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDEL_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
 
 /* Inter-Thread communication */
 
@@ -39,12 +39,14 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x40001
 
 /* RT-Thread Components */
 
 #define RT_USING_COMPONENTS_INIT
 #define RT_USING_USER_MAIN
 #define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
 
 /* C++ features */
 
@@ -62,45 +64,37 @@
 #define FINSH_CMD_SIZE 80
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
 
-#define RT_USING_DFS
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
-#define DFS_FD_MAX 4
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 437
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_0
-#define RT_DFS_ELM_USE_LFN 0
-#define RT_DFS_ELM_MAX_LFN 255
-#define RT_DFS_ELM_DRIVES 2
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
-#define RT_DFS_ELM_REENTRANT
-#define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
 #define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_I2C
 #define RT_USING_PIN
 #define RT_USING_SPI
+#define RT_USING_SFUD
+#define RT_SFUD_USING_FLASH_INFO_TABLE
+
+/* Using WiFi */
+
 
 /* Using USB */
 
 
 /* POSIX layer and C standard library */
 
-#define RT_USING_LIBC
 
-/* Network stack */
+/* Network */
+
+/* Socket abstraction layer */
+
 
 /* light weight TCP/IP stack */
 
@@ -108,6 +102,9 @@
 /* Modbus master and slave stack */
 
 
+/* AT commands */
+
+
 /* VBUS(Virtual Software BUS) */
 
 
@@ -116,11 +113,6 @@
 
 /* RT-Thread online packages */
 
-/* system packages */
-
-/* RT-Thread GUI Engine */
-
-
 /* IoT - internet of things */
 
 
@@ -132,6 +124,9 @@
 /* Wiced WiFi */
 
 
+/* IoT Cloud */
+
+
 /* security packages */
 
 
@@ -144,10 +139,16 @@
 /* tools packages */
 
 
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
 /* miscellaneous packages */
 
 
-/* example package: hello */
+/* samples: kernel and components samples */
 
 #define RT_USING_USART0
 #define RT_USING_USART1
diff --git a/bsp/gd32e230k-start/rtconfig.py b/bsp/gd32e230k-start/rtconfig.py
index c631bc3e44..f953a5e67b 100644
--- a/bsp/gd32e230k-start/rtconfig.py
+++ b/bsp/gd32e230k-start/rtconfig.py
@@ -2,7 +2,7 @@ import os
 
 # toolchains options
 ARCH='arm'
-CPU='cortex-m4'
+CPU='cortex-m23'
 CROSS_TOOL='keil'
 
 if os.getenv('RTT_CC'):
@@ -71,8 +71,6 @@ elif PLATFORM == 'armcc':
     EXEC_PATH += '/ARM/ARMCC/bin'
     print(EXEC_PATH)
 
-    CFLAGS += ' --c99'
-
     if BUILD == 'debug':
         CFLAGS += ' -g -O0'
         AFLAGS += ' -g'
diff --git a/bsp/gd32e230k-start/template.uvoptx b/bsp/gd32e230k-start/template.uvoptx
index 8fc841b0e1..93d9c266ef 100644
--- a/bsp/gd32e230k-start/template.uvoptx
+++ b/bsp/gd32e230k-start/template.uvoptx
@@ -22,11 +22,11 @@
   </DaveTm>
 
   <Target>
-    <TargetName>rt-thread_gd32f30x</TargetName>
+    <TargetName>rt-thread_gd32e230</TargetName>
     <ToolsetNumber>0x4</ToolsetNumber>
     <ToolsetName>ARM-ADS</ToolsetName>
     <TargetOption>
-      <CLKADS>16000000</CLKADS>
+      <CLKADS>12000000</CLKADS>
       <OPTTT>
         <gFlags>1</gFlags>
         <BeepAtEnd>1</BeepAtEnd>
@@ -73,7 +73,7 @@
         <LExpSel>0</LExpSel>
       </OPTXL>
       <OPTFL>
-        <tvExp>0</tvExp>
+        <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
@@ -103,7 +103,7 @@
         <bEvRecOn>1</bEvRecOn>
         <bSchkAxf>0</bSchkAxf>
         <bTchkAxf>0</bTchkAxf>
-        <nTsel>4</nTsel>
+        <nTsel>14</nTsel>
         <sDll></sDll>
         <sDllPa></sDllPa>
         <sDlgDll></sDlgDll>
@@ -114,18 +114,18 @@
         <tDlgDll></tDlgDll>
         <tDlgPa></tDlgPa>
         <tIfile></tIfile>
-        <pMon>Segger\JL2CM3.dll</pMon>
+        <pMon>BIN\UL2V8M.DLL</pMon>
       </DebugOpt>
       <TargetDriverDllRegistry>
         <SetRegEntry>
           <Number>0</Number>
-          <Key>JL2CM3</Key>
-          <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000</Name>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM))</Name>
         </SetRegEntry>
         <SetRegEntry>
           <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL010000 -FP0($$Device:GD32F303ZE$Flash\GD32F30x_HD.FLM))</Name>
+          <Key>JL2CM3</Key>
+          <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000</Name>
         </SetRegEntry>
       </TargetDriverDllRegistry>
       <Breakpoint/>
diff --git a/bsp/gd32e230k-start/template.uvprojx b/bsp/gd32e230k-start/template.uvprojx
index 9b0a830d22..cf0ba886d1 100644
--- a/bsp/gd32e230k-start/template.uvprojx
+++ b/bsp/gd32e230k-start/template.uvprojx
@@ -7,23 +7,23 @@
 
   <Targets>
     <Target>
-      <TargetName>rt-thread_gd32f30x</TargetName>
+      <TargetName>rt-thread_gd32e230</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
-      <uAC6>0</uAC6>
+      <uAC6>1</uAC6>
       <TargetOption>
         <TargetCommonOption>
-          <Device>GD32F303ZE</Device>
+          <Device>GD32E230K8</Device>
           <Vendor>GigaDevice</Vendor>
-          <PackID>GigaDevice.GD32F30x_DFP.1.0.1</PackID>
+          <PackID>GigaDevice.GD32E230_DFP.1.0.0</PackID>
           <PackURL>http://gd32mcu.21ic.com/data/documents/yingyongruanjian</PackURL>
-          <Cpu>IRAM(0x20000000-0x2000FFFF)IROM(0x08000000-0x0807FFFF) CLOCK(16000000) CPUTYPE("Cortex-M4")</Cpu>
+          <Cpu>IRAM(0x20000000,0x0002000) IROM(0x08000000,0x0010000) CPUTYPE("Cortex-M23") CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile>"Startup\GD\GD32F30x\startup_gd32f30x_hd.s" ("GD32F30x Startup Code")</StartupFile>
-          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000)</FlashDriverDll>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
-          <RegisterFile>gd32f30x.h</RegisterFile>
+          <RegisterFile>$$Device:GD32E230K8$Device\Include\gd32e230.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -33,14 +33,14 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>SFD\GD\GD32F30x\GD32F30x_HD.SFR</SFDFile>
+          <SFDFile>$$Device:GD32E230K8$SVD\GD32E230.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
           <IncludePath></IncludePath>
           <LibPath></LibPath>
-          <RegisterFilePath>GD\GD32F30x\</RegisterFilePath>
-          <DBRegisterFilePath>GD\GD32F30x\</DBRegisterFilePath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -49,7 +49,7 @@
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
           <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>rtthread-gd32f30x</OutputName>
+          <OutputName>rtthread-gd32e230</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
@@ -109,14 +109,14 @@
           <ComprImg>1</ComprImg>
         </CommonProperty>
         <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments> -REMAP</SimDllArguments>
-          <SimDlgDll>DCM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments></TargetDllArguments>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
           <TargetDlgDll>TCM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+          <TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
         </DllOption>
         <DebugOption>
           <OPTHX>
@@ -137,8 +137,8 @@
             <DriverSelection>4096</DriverSelection>
           </Flash1>
           <bUseTDR>1</bUseTDR>
-          <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3></Flash3>
           <Flash4></Flash4>
           <pFcarmOut></pFcarmOut>
           <pFcarmGrp></pFcarmGrp>
@@ -174,7 +174,7 @@
             <AdsLsxf>1</AdsLsxf>
             <RvctClst>0</RvctClst>
             <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <AdsCpuType>"Cortex-M23"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
@@ -184,6 +184,7 @@
             <hadXRAM>0</hadXRAM>
             <uocXRam>0</uocXRam>
             <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
@@ -192,7 +193,7 @@
             <uLtcg>0</uLtcg>
             <nSecure>0</nSecure>
             <RoSelD>3</RoSelD>
-            <RwSelD>4</RwSelD>
+            <RwSelD>3</RwSelD>
             <CodeSel>0</CodeSel>
             <OptFeed>0</OptFeed>
             <NoZi1>0</NoZi1>
@@ -244,12 +245,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
+                <Size>0x2000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x80000</Size>
+                <Size>0x10000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -274,7 +275,7 @@
               <OCR_RVCT4>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x80000</Size>
+                <Size>0x10000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -299,7 +300,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
+                <Size>0x2000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -324,6 +325,7 @@
             <uThumb>0</uThumb>
             <uSurpInc>0</uSurpInc>
             <uC99>1</uC99>
+            <uGnu>0</uGnu>
             <useXO>0</useXO>
             <v6Lang>1</v6Lang>
             <v6LangP>1</v6LangP>
@@ -387,10 +389,10 @@
   <RTE>
     <apis/>
     <components>
-      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.1" condition="ARMv6_7_8-M Device">
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.1"/>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.5.1"/>
         <targetInfos>
-          <targetInfo name="rt-thread_gd32f30x"/>
+          <targetInfo name="rt-thread_gd32e230"/>
         </targetInfos>
       </component>
     </components>
diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S
index d17a8aa12c..d9993247e2 100644
--- a/libcpu/arm/cortex-m23/context_gcc.S
+++ b/libcpu/arm/cortex-m23/context_gcc.S
@@ -5,26 +5,25 @@
  *
  * Change Logs:
  * Date         Author    Notes
- * 2009-10-11   Bernard   First version
- * 2010-12-29   onelife   Modify for EFM32
- * 2011-06-17   onelife   Merge all of the assembly source code into context_gcc.S
- * 2011-07-12   onelife   Add interrupt context check function
- * 2013-06-18   aozima    add restore MSP feature.
- * 2013-07-09   aozima    enhancement hard fault exception handler.
+ * 2010-01-25   Bernard      first version
+ * 2012-06-01   aozima       set pendsv priority to 0xFF.
+ * 2012-08-17   aozima       fixed bug: store r8 - r11.
+ * 2013-02-20   aozima       port to gcc.
+ * 2013-06-18   aozima       add restore MSP feature.
+ * 2013-11-04   bright       fixed hardfault bug for gcc.
  */
  
-    .cpu    cortex-m3
+    .cpu    cortex-m0
     .fpu    softvfp
     .syntax unified
     .thumb
     .text
 
-    .equ    SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
-    .equ    ICSR, 0xE000ED04                /* interrupt control state register */
-    .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
-    
-    .equ    SHPR3, 0xE000ED20               /* system priority register (3) */
-    .equ    PENDSV_PRI_LOWEST, 0x00FF0000   /* PendSV priority value (lowest) */
+	.equ 	SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
+	.equ 	NVIC_INT_CTRL, 0xE000ED04       /* interrupt control state register */
+	.equ 	NVIC_SHPR3, 0xE000ED20          /* system priority register (3) */
+	.equ 	NVIC_PENDSV_PRI, 0x00FF0000     /* PendSV priority value (lowest) */
+	.equ 	NVIC_PENDSVSET, 0x10000000      /* value to trigger PendSV exception */
 
 /*
  * rt_base_t rt_hw_interrupt_disable();
@@ -61,7 +60,7 @@ rt_hw_context_switch:
     LDR     R3, [R2]
     CMP     R3, #1
     BEQ     _reswitch
-    MOV     R3, #1
+    MOVS    R3, #1
     STR     R3, [R2]
 
     LDR     R2, =rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
@@ -71,8 +70,8 @@ _reswitch:
     LDR     R2, =rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
     STR     R1, [R2]
 
-    LDR     R0, =ICSR           /* trigger the PendSV exception (causes context switch) */
-    LDR     R1, =PENDSVSET_BIT
+    LDR     R0, =NVIC_INT_CTRL           /* trigger the PendSV exception (causes context switch) */
+    LDR     R1, =NVIC_PENDSVSET
     STR     R1, [R0]
     BX      LR
 
@@ -90,36 +89,56 @@ PendSV_Handler:
     /* get rt_thread_switch_interrupt_flag */
     LDR     R0, =rt_thread_switch_interrupt_flag
     LDR     R1, [R0]
-    CBZ     R1, pendsv_exit         /* pendsv aLReady handled */
+    CMP     R1, #0x00
+    BEQ     pendsv_exit		/* pendsv aLReady handled */
 
     /* clear rt_thread_switch_interrupt_flag to 0 */
-    MOV     R1, #0
+    MOVS    R1, #0
     STR     R1, [R0]
 
     LDR     R0, =rt_interrupt_from_thread
     LDR     R1, [R0]
-    CBZ     R1, switch_to_thread    /* skip register save at the first time */
+    CMP     R1, #0x00
+    BEQ     switch_to_thread    /* skip register save at the first time */
 
-    MRS     R1, PSP                 /* get from thread stack pointer */
-    STMFD   R1!, {R4 - R11}         /* push R4 - R11 register */
+	MRS     R1, PSP                 /* get from thread stack pointer */
+
+    SUBS    R1, R1, #0x20           /* space for {R4 - R7} and {R8 - R11} */
     LDR     R0, [R0]
     STR     R1, [R0]                /* update from thread stack pointer */
 
+    STMIA   R1!, {R4 - R7}          /* push thread {R4 - R7} register to thread stack */
+
+    MOV     R4, R8                  /* mov thread {R8 - R11} to {R4 - R7} */
+    MOV     R5, R9
+    MOV     R6, R10
+    MOV     R7, R11
+    STMIA   R1!, {R4 - R7}          /* push thread {R8 - R11} high register to thread stack */
 switch_to_thread:
     LDR     R1, =rt_interrupt_to_thread
     LDR     R1, [R1]
     LDR     R1, [R1]                /* load thread stack pointer */
 
-    LDMFD   R1!, {R4 - R11}         /* pop R4 - R11 register */
+	LDMIA   R1!, {R4 - R7}          /* pop thread {R4 - R7} register from thread stack */
+    PUSH    {R4 - R7}               /* push {R4 - R7} to MSP for copy {R8 - R11} */
+
+    LDMIA   R1!, {R4 - R7}          /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */
+    MOV     R8,  R4                 /* mov {R4 - R7} to {R8 - R11} */
+    MOV     R9,  R5
+    MOV     R10, R6
+    MOV     R11, R7
+
+    POP     {R4 - R7}               /* pop {R4 - R7} from MSP */
+
     MSR     PSP, R1                 /* update stack pointer */
 
 pendsv_exit:
     /* restore interrupt */
     MSR     PRIMASK, R2
 
-    ORR     LR, LR, #0x04
-    BX      LR
-
+    MOVS    R0, #0x04
+    RSBS    R0, R0, #0x00
+    BX      R0
 /*
  * void rt_hw_context_switch_to(rt_uint32 to);
  * R0 --> to
@@ -132,34 +151,33 @@ rt_hw_context_switch_to:
 
     /* set from thread to 0 */
     LDR     R1, =rt_interrupt_from_thread
-    MOV     R0, #0
+    MOVS    R0, #0
     STR     R0, [R1]
 
     /* set interrupt flag to 1 */
     LDR     R1, =rt_thread_switch_interrupt_flag
-    MOV     R0, #1
+    MOVS    R0, #1
     STR     R0, [R1]
 
     /* set the PendSV exception priority */
-    LDR     R0, =SHPR3
-    LDR     R1, =PENDSV_PRI_LOWEST
-    LDR.W   R2, [R0,#0]             /* read */
-    ORR     R1, R1, R2              /* modify */
-    STR     R1, [R0]                /* write-back */
-
-    LDR     R0, =ICSR               /* trigger the PendSV exception (causes context switch) */
-    LDR     R1, =PENDSVSET_BIT
+    LDR     R0, =NVIC_SHPR3
+    LDR     R1, =NVIC_PENDSV_PRI
+    LDR     R2, [R0,#0x00]       /* read */
+    ORRS    R1, R1, R2             /* modify */
+    STR     R1, [R0]             /* write-back */
+
+    LDR     R0, =NVIC_INT_CTRL               /* trigger the PendSV exception (causes context switch) */
+    LDR     R1, =NVIC_PENDSVSET
     STR     R1, [R0]
-
+    NOP
     /* restore MSP */
-    LDR     r0, =SCB_VTOR
-    LDR     r0, [r0]
-    LDR     r0, [r0]
+    LDR     R0, =SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
     NOP
-    MSR     msp, r0
+    MSR     MSP, R0
 
     /* enable interrupts at processor level */
-    CPSIE   F
     CPSIE   I
 
     /* never reach here! */
@@ -175,29 +193,11 @@ rt_hw_interrupt_thread_switch:
     .type HardFault_Handler, %function
 HardFault_Handler:
     /* get current context */
-    MRS     r0, msp                 /* get fault context from handler. */
-    TST     lr, #0x04               /* if(!EXC_RETURN[2]) */
-    BEQ     _get_sp_done
-    MRS     r0, psp                 /* get fault context from thread. */
-_get_sp_done:
-
-    STMFD   r0!, {r4 - r11}         /* push r4 - r11 register */
-    STMFD   r0!, {lr}               /* push exec_return register */
-
-    TST     lr, #0x04               /* if(!EXC_RETURN[2]) */
-    BEQ     _update_msp
-    MSR     psp, r0                 /* update stack pointer to PSP. */
-    B       _update_done
-_update_msp:
-    MSR     msp, r0                 /* update stack pointer to MSP. */
-_update_done:
-
+    MRS     R0, PSP                 /* get fault thread stack pointer */
     PUSH    {LR}
     BL      rt_hw_hard_fault_exception
-    POP     {LR}
+    POP     {PC}
 
-    ORR     LR, LR, #0x04
-    BX      LR
 
 /*
  * rt_uint32_t rt_hw_interrupt_check(void);
diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S
index 91645c48b3..50d3781359 100644
--- a/libcpu/arm/cortex-m23/context_iar.S
+++ b/libcpu/arm/cortex-m23/context_iar.S
@@ -5,20 +5,20 @@
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
-; * 2009-01-17     Bernard      first version
-; * 2009-09-27     Bernard      add protect when contex switch occurs
+; * 2010-01-25     Bernard      first version
+; * 2012-06-01     aozima       set pendsv priority to 0xFF.
+; * 2012-08-17     aozima       fixed bug: store r8 - r11.
 ; * 2013-06-18     aozima       add restore MSP feature.
-; * 2013-07-09     aozima       enhancement hard fault exception handler.
 ; */
 
 ;/**
-; * @addtogroup cortex-m3
+; * @addtogroup CORTEX-M0
 ; */
 ;/*@{*/
 
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
-NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
 NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
@@ -62,7 +62,7 @@ rt_hw_context_switch:
     LDR     r3, [r2]
     CMP     r3, #1
     BEQ     _reswitch
-    MOV     r3, #1
+    MOVS    r3, #0x1
     STR     r3, [r2]
 
     LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
@@ -90,65 +90,91 @@ PendSV_Handler:
     ; get rt_thread_switch_interrupt_flag
     LDR     r0, =rt_thread_switch_interrupt_flag
     LDR     r1, [r0]
-    CBZ     r1, pendsv_exit         ; pendsv already handled
+    CMP     r1, #0x00
+    BEQ     pendsv_exit                ; pendsv already handled
 
     ; clear rt_thread_switch_interrupt_flag to 0
-    MOV     r1, #0x00
+    MOVS    r1, #0x00
     STR     r1, [r0]
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, switch_to_thread    ; skip register save at the first time
+    CMP     r1, #0x00
+    BEQ     switch_to_thread        ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
-    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
+
+    SUBS    r1, r1, #0x20           ; space for {r4 - r7} and {r8 - r11}
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
+    STMIA   r1!, {r4 - r7}          ; push thread {r4 - r7} register to thread stack
+
+    MOV     r4, r8                  ; mov thread {r8 - r11} to {r4 - r7}
+    MOV     r5, r9
+    MOV     r6, r10
+    MOV     r7, r11
+    STMIA   r1!, {r4 - r7}          ; push thread {r8 - r11} high register to thread stack
+
 switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
 
-    LDMFD   r1!, {r4 - r11}         ; pop r4 - r11 register
+    LDMIA   r1!, {r4 - r7}          ; pop thread {r4 - r7} register from thread stack
+    PUSH    {r4 - r7}               ; push {r4 - r7} to MSP for copy {r8 - r11}
+
+    LDMIA   r1!, {r4 - r7}          ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
+    MOV     r8,  r4                 ; mov {r4 - r7} to {r8 - r11}
+    MOV     r9,  r5
+    MOV     r10, r6
+    MOV     r11, r7
+
+    POP     {r4 - r7}               ; pop {r4 - r7} from MSP
+
     MSR     psp, r1                 ; update stack pointer
 
 pendsv_exit
     ; restore interrupt
     MSR     PRIMASK, r2
 
-    ORR     lr, lr, #0x04
-    BX      lr
+    MOVS    r0, #0x04
+    RSBS    r0, r0, #0x00
+    BX      r0
 
 ;/*
 ; * void rt_hw_context_switch_to(rt_uint32 to);
 ; * r0 --> to
+; * this fucntion is used to perform the first thread switch
 ; */
     EXPORT rt_hw_context_switch_to
 rt_hw_context_switch_to:
+    ; set to thread
     LDR     r1, =rt_interrupt_to_thread
     STR     r0, [r1]
 
     ; set from thread to 0
     LDR     r1, =rt_interrupt_from_thread
-    MOV     r0, #0x0
+    MOVS    r0, #0x0
     STR     r0, [r1]
 
     ; set interrupt flag to 1
     LDR     r1, =rt_thread_switch_interrupt_flag
-    MOV     r0, #1
+    MOVS    r0, #1
     STR     r0, [r1]
 
     ; set the PendSV exception priority
-    LDR     r0, =NVIC_SYSPRI2
+    LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
-    LDR.W   r2, [r0,#0x00]       ; read
-    ORR     r1,r1,r2             ; modify
+    LDR     r2, [r0,#0x00]       ; read
+    ORRS    r1,r1,r2             ; modify
     STR     r1, [r0]             ; write-back
 
-    LDR     r0, =NVIC_INT_CTRL      ; trigger the PendSV exception (causes context switch)
+    ; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
     LDR     r1, =NVIC_PENDSVSET
     STR     r1, [r0]
+    NOP
 
     ; restore MSP
     LDR     r0, =SCB_VTOR
@@ -158,7 +184,6 @@ rt_hw_context_switch_to:
     MSR     msp, r0
 
     ; enable interrupts at processor level
-    CPSIE   F
     CPSIE   I
 
     ; never reach here!
@@ -173,30 +198,9 @@ rt_hw_interrupt_thread_switch:
 HardFault_Handler:
 
     ; get current context
-    MRS     r0, msp                 ; get fault context from handler.
-    TST     lr, #0x04               ; if(!EXC_RETURN[2])
-    BEQ     _get_sp_done
-    MRS     r0, psp                 ; get fault context from thread.
-_get_sp_done
-
-    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
-    ;STMFD   r0!, {lr}               ; push exec_return register
-    SUB     r0, r0, #0x04
-    STR     lr, [r0]
-
-    TST     lr, #0x04               ; if(!EXC_RETURN[2])
-    BEQ     _update_msp
-    MSR     psp, r0                 ; update stack pointer to PSP.
-    B       _update_done
-_update_msp
-    MSR     msp, r0                 ; update stack pointer to MSP.
-_update_done
-
+    MRS     r0, psp                 ; get fault thread stack pointer
     PUSH    {lr}
     BL      rt_hw_hard_fault_exception
-    POP     {lr}
-
-    ORR     lr, lr, #0x04
-    BX      lr
+    POP     {pc}
 
     END
diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S
index c0a2130703..54145773d3 100644
--- a/libcpu/arm/cortex-m23/context_rvds.S
+++ b/libcpu/arm/cortex-m23/context_rvds.S
@@ -5,9 +5,10 @@
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
-; * 2009-01-17     Bernard      first version
+; * 2010-01-25     Bernard      first version
+; * 2012-06-01     aozima       set pendsv priority to 0xFF.
+; * 2012-08-17     aozima       fixed bug: store r8 - r11.
 ; * 2013-06-18     aozima       add restore MSP feature.
-; * 2013-07-09     aozima       enhancement hard fault exception handler.
 ; */
 
 ;/**
@@ -17,7 +18,7 @@
 
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
-NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
 NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
@@ -45,8 +46,8 @@ rt_hw_interrupt_disable    PROC
 ; */
 rt_hw_interrupt_enable    PROC
     EXPORT  rt_hw_interrupt_enable
-    MSR     PRIMASK, r0
-    BX      LR
+    MSR		PRIMASK, r0
+    BX		LR
     ENDP
 
 ;/*
@@ -64,7 +65,7 @@ rt_hw_context_switch    PROC
     LDR     r3, [r2]
     CMP     r3, #1
     BEQ     _reswitch
-    MOV     r3, #1
+    MOVS    r3, #0x01
     STR     r3, [r2]
 
     LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
@@ -83,7 +84,7 @@ _reswitch
 ; r0 --> switch from thread stack
 ; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
-PendSV_Handler   PROC
+PendSV_Handler    PROC
     EXPORT PendSV_Handler
 
     ; disable interrupt to protect context switch
@@ -93,35 +94,57 @@ PendSV_Handler   PROC
     ; get rt_thread_switch_interrupt_flag
     LDR     r0, =rt_thread_switch_interrupt_flag
     LDR     r1, [r0]
-    CBZ     r1, pendsv_exit         ; pendsv already handled
+    CMP     r1, #0x00
+    BEQ     pendsv_exit                ; pendsv already handled
 
     ; clear rt_thread_switch_interrupt_flag to 0
-    MOV     r1, #0x00
+    MOVS    r1, #0x00
     STR     r1, [r0]
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, switch_to_thread    ; skip register save at the first time
+    CMP     r1, #0x00
+    BEQ     switch_to_thread        ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
-    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
+
+    SUBS    r1, r1, #0x20           ; space for {r4 - r7} and {r8 - r11}
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
+    STMIA   r1!, {r4 - r7}          ; push thread {r4 - r7} register to thread stack
+
+    MOV     r4, r8                  ; mov thread {r8 - r11} to {r4 - r7}
+    MOV     r5, r9
+    MOV     r6, r10
+    MOV     r7, r11
+    STMIA   r1!, {r4 - r7}          ; push thread {r8 - r11} high register to thread stack
+
 switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
 
-    LDMFD   r1!, {r4 - r11}         ; pop r4 - r11 register
+    LDMIA   r1!, {r4 - r7}          ; pop thread {r4 - r7} register from thread stack
+    PUSH    {r4 - r7}               ; push {r4 - r7} to MSP for copy {r8 - r11}
+
+    LDMIA   r1!, {r4 - r7}          ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
+    MOV     r8,  r4                 ; mov {r4 - r7} to {r8 - r11}
+    MOV     r9,  r5
+    MOV     r10, r6
+    MOV     r11, r7
+
+    POP     {r4 - r7}               ; pop {r4 - r7} from MSP
+
     MSR     psp, r1                 ; update stack pointer
 
 pendsv_exit
     ; restore interrupt
     MSR     PRIMASK, r2
 
-    ORR     lr, lr, #0x04
-    BX      lr
+    MOVS    r0, #0x04
+    RSBS    r0, r0, #0x00
+    BX      r0
     ENDP
 
 ;/*
@@ -137,19 +160,19 @@ rt_hw_context_switch_to    PROC
 
     ; set from thread to 0
     LDR     r1, =rt_interrupt_from_thread
-    MOV     r0, #0x0
+    MOVS    r0, #0x0
     STR     r0, [r1]
 
     ; set interrupt flag to 1
     LDR     r1, =rt_thread_switch_interrupt_flag
-    MOV     r0, #1
+    MOVS    r0, #1
     STR     r0, [r1]
 
     ; set the PendSV exception priority
-    LDR     r0, =NVIC_SYSPRI2
+    LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
-    LDR.W   r2, [r0,#0x00]       ; read
-    ORR     r1,r1,r2             ; modify
+    LDR     r2, [r0,#0x00]       ; read
+    ORRS    r1,r1,r2             ; modify
     STR     r1, [r0]             ; write-back
 
     ; trigger the PendSV exception (causes context switch)
@@ -164,7 +187,6 @@ rt_hw_context_switch_to    PROC
     MSR     msp, r0
 
     ; enable interrupts at processor level
-    CPSIE   F
     CPSIE   I
 
     ; never reach here!
@@ -177,29 +199,15 @@ rt_hw_interrupt_thread_switch PROC
     ENDP
 
     IMPORT rt_hw_hard_fault_exception
-    EXPORT HardFault_Handler
+
 HardFault_Handler    PROC
+    EXPORT HardFault_Handler
 
     ; get current context
-    TST     lr, #0x04               ; if(!EXC_RETURN[2])
-    ITE     EQ
-    MRSEQ   r0, msp                 ; [2]=0 ==> Z=1, get fault context from handler.
-    MRSNE   r0, psp                 ; [2]=1 ==> Z=0, get fault context from thread.
-
-    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
-    STMFD   r0!, {lr}               ; push exec_return register
-
-    TST     lr, #0x04               ; if(!EXC_RETURN[2])
-    ITE     EQ
-    MSREQ   msp, r0                 ; [2]=0 ==> Z=1, update stack pointer to MSP.
-    MSRNE   psp, r0                 ; [2]=1 ==> Z=0, update stack pointer to PSP.
-
+    MRS     r0, psp                 ; get fault thread stack pointer
     PUSH    {lr}
     BL      rt_hw_hard_fault_exception
-    POP     {lr}
-
-    ORR     lr, lr, #0x04
-    BX      lr
+    POP     {pc}
     ENDP
 
     ALIGN   4
diff --git a/libcpu/arm/cortex-m23/cpuport.c b/libcpu/arm/cortex-m23/cpuport.c
index a386747750..5d36fa11fe 100644
--- a/libcpu/arm/cortex-m23/cpuport.c
+++ b/libcpu/arm/cortex-m23/cpuport.c
@@ -4,13 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date         Author      Notes
- * 2009-01-05   Bernard     first version
- * 2011-02-14   onelife     Modify for EFM32
- * 2011-06-17   onelife     Merge all of the C source code into cpuport.c
- * 2012-12-23   aozima      stack addr align to 8byte.
- * 2012-12-29   Bernard     Add exception hook.
- * 2013-07-09   aozima      enhancement hard fault exception handler.
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ * 2012-05-31     aozima       Merge all of the C source code into cpuport.c
+ * 2012-08-17     aozima       fixed bug: store r8 - r11.
+ * 2012-12-23     aozima       stack addr align to 8byte.
  */
 
 #include <rtthread.h>
@@ -29,11 +27,13 @@ struct exception_stack_frame
 
 struct stack_frame
 {
-    /* r4 ~ r11 register */
+    /* r4 ~ r7 low register */
     rt_uint32_t r4;
     rt_uint32_t r5;
     rt_uint32_t r6;
     rt_uint32_t r7;
+
+    /* r8 ~ r11 high register */
     rt_uint32_t r8;
     rt_uint32_t r9;
     rt_uint32_t r10;
@@ -45,8 +45,6 @@ struct stack_frame
 /* flag in interrupt handling */
 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
 rt_uint32_t rt_thread_switch_interrupt_flag;
-/* exception hook */
-static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
 
 /**
  * This function will initialize thread stack
@@ -92,312 +90,46 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
     return stk;
 }
 
+extern long list_thread(void);
+extern rt_thread_t rt_current_thread;
 /**
- * This function set the hook, which is invoked on fault exception handling.
- *
- * @param exception_handle the exception handling hook function.
+ * fault exception handling
  */
-void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context))
+void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
 {
-    rt_exception_hook = exception_handle;
+    rt_kprintf("psr: 0x%08x\n", contex->psr);
+    rt_kprintf(" pc: 0x%08x\n", contex->pc);
+    rt_kprintf(" lr: 0x%08x\n", contex->lr);
+    rt_kprintf("r12: 0x%08x\n", contex->r12);
+    rt_kprintf("r03: 0x%08x\n", contex->r3);
+    rt_kprintf("r02: 0x%08x\n", contex->r2);
+    rt_kprintf("r01: 0x%08x\n", contex->r1);
+    rt_kprintf("r00: 0x%08x\n", contex->r0);
+
+    rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
+
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+
+    while (1);
 }
 
 #define SCB_CFSR        (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
 #define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
 #define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
 #define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
-#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED0C)  /* Reset control Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED00)  /* Reset control Address Register */
 #define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
 
 #define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
 #define SCB_CFSR_BFSR   (*(volatile const unsigned char*)0xE000ED29)  /* Bus Fault Status Register */
 #define SCB_CFSR_UFSR   (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
 
-#ifdef RT_USING_FINSH
-static void usage_fault_track(void)
-{
-    rt_kprintf("usage fault:\n");
-    rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
-
-    if(SCB_CFSR_UFSR & (1<<0))
-    {
-        /* [0]:UNDEFINSTR */
-        rt_kprintf("UNDEFINSTR ");
-    }
-
-    if(SCB_CFSR_UFSR & (1<<1))
-    {
-        /* [1]:INVSTATE */
-        rt_kprintf("INVSTATE ");
-    }
-
-    if(SCB_CFSR_UFSR & (1<<2))
-    {
-        /* [2]:INVPC */
-        rt_kprintf("INVPC ");
-    }
-
-    if(SCB_CFSR_UFSR & (1<<3))
-    {
-        /* [3]:NOCP */
-        rt_kprintf("NOCP ");
-    }
-
-    if(SCB_CFSR_UFSR & (1<<8))
-    {
-        /* [8]:UNALIGNED */
-        rt_kprintf("UNALIGNED ");
-    }
-
-    if(SCB_CFSR_UFSR & (1<<9))
-    {
-        /* [9]:DIVBYZERO */
-        rt_kprintf("DIVBYZERO ");
-    }
-
-    rt_kprintf("\n");
-}
-
-static void bus_fault_track(void)
-{
-    rt_kprintf("bus fault:\n");
-    rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
-
-    if(SCB_CFSR_BFSR & (1<<0))
-    {
-        /* [0]:IBUSERR */
-        rt_kprintf("IBUSERR ");
-    }
-
-    if(SCB_CFSR_BFSR & (1<<1))
-    {
-        /* [1]:PRECISERR */
-        rt_kprintf("PRECISERR ");
-    }
-
-    if(SCB_CFSR_BFSR & (1<<2))
-    {
-        /* [2]:IMPRECISERR */
-        rt_kprintf("IMPRECISERR ");
-    }
-
-    if(SCB_CFSR_BFSR & (1<<3))
-    {
-        /* [3]:UNSTKERR */
-        rt_kprintf("UNSTKERR ");
-    }
-
-    if(SCB_CFSR_BFSR & (1<<4))
-    {
-        /* [4]:STKERR */
-        rt_kprintf("STKERR ");
-    }
-
-    if(SCB_CFSR_BFSR & (1<<7))
-    {
-        rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR);
-    }
-    else
-    {
-        rt_kprintf("\n");
-    }
-}
-
-static void mem_manage_fault_track(void)
-{
-    rt_kprintf("mem manage fault:\n");
-    rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
-
-    if(SCB_CFSR_MFSR & (1<<0))
-    {
-        /* [0]:IACCVIOL */
-        rt_kprintf("IACCVIOL ");
-    }
-
-    if(SCB_CFSR_MFSR & (1<<1))
-    {
-        /* [1]:DACCVIOL */
-        rt_kprintf("DACCVIOL ");
-    }
-
-    if(SCB_CFSR_MFSR & (1<<3))
-    {
-        /* [3]:MUNSTKERR */
-        rt_kprintf("MUNSTKERR ");
-    }
-
-    if(SCB_CFSR_MFSR & (1<<4))
-    {
-        /* [4]:MSTKERR */
-        rt_kprintf("MSTKERR ");
-    }
-
-    if(SCB_CFSR_MFSR & (1<<7))
-    {
-        /* [7]:MMARVALID */
-        rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR);
-    }
-    else
-    {
-        rt_kprintf("\n");
-    }
-}
-
-static void hard_fault_track(void)
-{
-    if(SCB_HFSR & (1UL<<1))
-    {
-        /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */
-        rt_kprintf("failed vector fetch\n");
-    }
-
-    if(SCB_HFSR & (1UL<<30))
-    {
-        /* [30]:FORCED, Indicates hard fault is taken because of bus fault,
-                        memory management fault, or usage fault. */
-        if(SCB_CFSR_BFSR)
-        {
-            bus_fault_track();
-        }
-
-        if(SCB_CFSR_MFSR)
-        {
-            mem_manage_fault_track();
-        }
-
-        if(SCB_CFSR_UFSR)
-        {
-            usage_fault_track();
-        }
-    }
-
-    if(SCB_HFSR & (1UL<<31))
-    {
-        /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */
-        rt_kprintf("debug event\n");
-    }
-}
-#endif /* RT_USING_FINSH */
-
-struct exception_info
-{
-    rt_uint32_t exc_return;
-    struct stack_frame stack_frame;
-};
-
-/*
- * fault exception handler
- */
-void rt_hw_hard_fault_exception(struct exception_info * exception_info)
-{
-    extern long list_thread(void);
-    struct stack_frame* context = &exception_info->stack_frame;
-
-    if (rt_exception_hook != RT_NULL)
-    {
-        rt_err_t result;
-
-        result = rt_exception_hook(exception_info);
-        if (result == RT_EOK)
-            return;
-    }
-
-    rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr);
-
-    rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0);
-    rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1);
-    rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2);
-    rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3);
-    rt_kprintf("r04: 0x%08x\n", context->r4);
-    rt_kprintf("r05: 0x%08x\n", context->r5);
-    rt_kprintf("r06: 0x%08x\n", context->r6);
-    rt_kprintf("r07: 0x%08x\n", context->r7);
-    rt_kprintf("r08: 0x%08x\n", context->r8);
-    rt_kprintf("r09: 0x%08x\n", context->r9);
-    rt_kprintf("r10: 0x%08x\n", context->r10);
-    rt_kprintf("r11: 0x%08x\n", context->r11);
-    rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12);
-    rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr);
-    rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc);
-
-    if(exception_info->exc_return & (1 << 2) )
-    {
-        rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name);
-
-#ifdef RT_USING_FINSH
-        list_thread();
-#endif /* RT_USING_FINSH */
-    }
-    else
-    {
-        rt_kprintf("hard fault on handler\r\n\r\n");
-    }
-
-#ifdef RT_USING_FINSH
-    hard_fault_track();
-#endif /* RT_USING_FINSH */
-
-    while (1);
-}
-
-/**
- * shutdown CPU
- */
-void rt_hw_cpu_shutdown(void)
-{
-    rt_kprintf("shutdown...\n");
-
-    RT_ASSERT(0);
-}
-
 /**
  * reset CPU
  */
 RT_WEAK void rt_hw_cpu_reset(void)
 {
-    SCB_AIRCR = SCB_RESET_VALUE;
-}
-
-#ifdef RT_USING_CPU_FFS
-/**
- * This function finds the first bit set (beginning with the least significant bit)
- * in value and return the index of that bit.
- *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of
- * zero from any of these functions means that the argument was zero.
- *
- * @return return the index of the first bit set. If value is 0, then this function
- * shall return 0.
- */
-#if defined(__CC_ARM)
-__asm int __rt_ffs(int value)
-{
-    CMP     r0, #0x00
-    BEQ     exit
-
-    RBIT    r0, r0
-    CLZ     r0, r0
-    ADDS    r0, r0, #0x01
-
-exit
-    BX      lr
+    SCB_AIRCR  = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk);
 }
-#elif defined(__IAR_SYSTEMS_ICC__)
-int __rt_ffs(int value)
-{
-    if (value == 0) return value;
-
-    asm("RBIT %0, %1" : "=r"(value) : "r"(value));
-    asm("CLZ  %0, %1" : "=r"(value) : "r"(value));
-    asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value));
-
-    return value;
-}
-#elif defined(__GNUC__)
-int __rt_ffs(int value)
-{
-    return __builtin_ffs(value);
-}
-#endif
-
-#endif
-- 
cgit v1.3.1


From fd8eb60a67588f53125f3175594e51d634fd3f79 Mon Sep 17 00:00:00 2001
From: xuzhuoyi <xzy476386434@vip.qq.com>
Date: Sun, 31 Mar 2019 23:26:35 +0800
Subject: [bsp][gd32e230k-start] Update Kconfig

---
 bsp/gd32e230k-start/.config             | 163 +++++++++++++++++++++-----------
 bsp/gd32e230k-start/Kconfig             |   5 -
 bsp/gd32e230k-start/drivers/drv_gpio.c  | 134 +++++++-------------------
 bsp/gd32e230k-start/drivers/drv_i2c.c   |   3 +-
 bsp/gd32e230k-start/drivers/drv_spi.c   |   6 +-
 bsp/gd32e230k-start/drivers/drv_usart.c |  88 +----------------
 bsp/gd32e230k-start/project.uvoptx      |   4 +-
 bsp/gd32e230k-start/project.uvprojx     |  12 +--
 bsp/gd32e230k-start/rtconfig.h          |   5 +
 bsp/gd32e230k-start/template.uvoptx     |   2 +-
 bsp/gd32e230k-start/template.uvprojx    |   4 +-
 libcpu/arm/cortex-m23/context_gcc.S     |   7 +-
 libcpu/arm/cortex-m23/context_iar.S     |   5 +-
 libcpu/arm/cortex-m23/context_rvds.S    |   3 +-
 libcpu/arm/cortex-m23/cpuport.c         |   3 +-
 15 files changed, 176 insertions(+), 268 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/gd32e230k-start/.config b/bsp/gd32e230k-start/.config
index 40cac74cf7..8f18d4257e 100644
--- a/bsp/gd32e230k-start/.config
+++ b/bsp/gd32e230k-start/.config
@@ -7,20 +7,32 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
 CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=100
-CONFIG_RT_DEBUG=y
-CONFIG_RT_DEBUG_COLOR=y
 CONFIG_RT_USING_OVERFLOW_CHECK=y
-CONFIG_RT_DEBUG_INIT=0
-CONFIG_RT_DEBUG_THREAD=0
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
 
 #
 # Inter-Thread communication
@@ -47,11 +59,13 @@ CONFIG_RT_USING_HEAP=y
 # Kernel Device Object
 #
 CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
-# CONFIG_RT_USING_MODULE is not set
+CONFIG_RT_VER_NUM=0x40001
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -59,6 +73,7 @@ CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
 CONFIG_RT_USING_COMPONENTS_INIT=y
 CONFIG_RT_USING_USER_MAIN=y
 CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
 
 #
 # C++ features
@@ -82,67 +97,58 @@ CONFIG_FINSH_CMD_SIZE=80
 CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_USING_MSH_DEFAULT=y
 # CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
 
 #
 # Device virtual file system
 #
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=4
-CONFIG_RT_USING_DFS_ELMFAT=y
-
-#
-# elm-chan's FatFs, Generic FAT Filesystem Module
-#
-CONFIG_RT_DFS_ELM_CODE_PAGE=437
-CONFIG_RT_DFS_ELM_WORD_ACCESS=y
-CONFIG_RT_DFS_ELM_USE_LFN_0=y
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
 # CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
 # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
 # CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
-CONFIG_RT_DFS_ELM_USE_LFN=0
-CONFIG_RT_DFS_ELM_MAX_LFN=255
-CONFIG_RT_DFS_ELM_DRIVES=2
-CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
-# CONFIG_RT_DFS_ELM_USE_ERASE is not set
-CONFIG_RT_DFS_ELM_REENTRANT=y
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_NET is not set
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
-# CONFIG_RT_USING_DFS_NFS is not set
 
 #
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 CONFIG_RT_USING_I2C=y
 # CONFIG_RT_USING_I2C_BITOPS is not set
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
 # CONFIG_RT_USING_SPI_MSD is not set
 CONFIG_RT_USING_SFUD=y
 # CONFIG_RT_SFUD_USING_SFDP is not set
 CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
-# CONFIG_RT_SFUD_DEBUG is not set
+# CONFIG_RT_SFUD_USING_QSPI is not set
+# CONFIG_RT_DEBUG_SFUD is not set
 # CONFIG_RT_USING_W25QXX is not set
 # CONFIG_RT_USING_GD is not set
 # CONFIG_RT_USING_ENC28J60 is not set
 # CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+
+#
+# Using WiFi
+#
 # CONFIG_RT_USING_WIFI is not set
 
 #
@@ -154,27 +160,33 @@ CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
 #
 # POSIX layer and C standard library
 #
-CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
-# CONFIG_RT_USING_POSIX is not set
-# CONFIG_HAVE_SYS_SIGNALS is not set
 
 #
-# Network stack
+# Network
 #
 
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
 #
 # light weight TCP/IP stack
 #
 # CONFIG_RT_USING_LWIP is not set
-# CONFIG_RT_USING_LWIP141 is not set
-# CONFIG_RT_USING_LWIP202 is not set
 
 #
 # Modbus master and slave stack
 #
 # CONFIG_RT_USING_MODBUS is not set
 
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
 #
 # VBUS(Virtual Software BUS)
 #
@@ -185,25 +197,13 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # RT-Thread online packages
 #
 
-#
-# system packages
-#
-
-#
-# RT-Thread GUI Engine
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-
 #
 # IoT - internet of things
 #
@@ -212,10 +212,10 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_LJSON is not set
 # CONFIG_PKG_USING_EZXML is not set
 # CONFIG_PKG_USING_NANOPB is not set
-# CONFIG_PKG_USING_GAGENT_CLOUD is not set
 
 #
 # Wi-Fi
@@ -233,7 +233,16 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
 # CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
 
 #
 # security packages
@@ -245,6 +254,7 @@ CONFIG_RT_USING_LIBC=y
 #
 # language packages
 #
+# CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
 
@@ -252,6 +262,7 @@ CONFIG_RT_USING_LIBC=y
 # multimedia packages
 #
 # CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
 
 #
 # tools packages
@@ -260,17 +271,58 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
-# CONFIG_PKG_USING_IPERF is not set
+# CONFIG_PKG_USING_RDB is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
 
 #
 # miscellaneous packages
 #
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
-# CONFIG_PKG_USING_SAMPLES is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 
 #
 # example package: hello
@@ -283,6 +335,5 @@ CONFIG_RT_USING_USART1=y
 # CONFIG_RT_USING_UART4 is not set
 CONFIG_RT_USING_SPI0=y
 CONFIG_RT_USING_SPI1=y
-# CONFIG_RT_USING_SPI2 is not set
 CONFIG_RT_USING_I2C0=y
 # CONFIG_RT_USING_I2C1 is not set
diff --git a/bsp/gd32e230k-start/Kconfig b/bsp/gd32e230k-start/Kconfig
index e4706f4d4f..36b2d0eeb1 100644
--- a/bsp/gd32e230k-start/Kconfig
+++ b/bsp/gd32e230k-start/Kconfig
@@ -53,11 +53,6 @@ config RT_USING_SPI1
     select RT_USING_SPI
     default n  
 
-config RT_USING_SPI2
-    bool "Using SPI2"
-    select RT_USING_SPI
-    default n 
-
 config RT_USING_I2C0
     bool "Using I2C0"
     select RT_USING_I2C
diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.c b/bsp/gd32e230k-start/drivers/drv_gpio.c
index 6b9ecf4e34..288ba6c832 100644
--- a/bsp/gd32e230k-start/drivers/drv_gpio.c
+++ b/bsp/gd32e230k-start/drivers/drv_gpio.c
@@ -1,16 +1,17 @@
 /*
  * File      : drv_gpio.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
+ * COPYRIGHT (C) 2019, RT-Thread Development Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
  * http://www.rt-thread.org/license/LICENSE
  *
  * Change Logs:
- * Date           Author            Notes
+ * Date           Author         Notes
  * 2017-10-20     ZYH            the first version
  * 2018-04-23     misonyo        port to gd32f30x
+ * 2019-03-31     xuzhuoyi       Porting for gd32e230
  */
 
 #include "drv_gpio.h"
@@ -23,7 +24,7 @@
 
 #define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \
         GPIO_PIN_##pin, EXTI_SOURCE_GPIO##port, EXTI_SOURCE_PIN##pin}
-#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0}
+#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0}
 
 /* GD32 GPIO driver */
 struct pin_index
@@ -39,102 +40,37 @@ struct pin_index
 static const struct pin_index pins[] =
 {
     __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(7, C, 13),
-    __GD32_PIN(8, C, 14),
-    __GD32_PIN(9, C, 15),
-    __GD32_PIN(10, F, 0),
-    __GD32_PIN(11, F, 1),
-    __GD32_PIN(12, F, 2),
-    __GD32_PIN(13, F, 3),
-    __GD32_PIN(14, F, 4),
-    __GD32_PIN(15, F, 5),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(18, F, 6),
-    __GD32_PIN(19, F, 7),
-    __GD32_PIN(20, F, 8),
-    __GD32_PIN(21, F, 9),
-    __GD32_PIN(22, F, 10),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(26, C, 0),
-    __GD32_PIN(27, C, 1),
-    __GD32_PIN(28, C, 2),
-    __GD32_PIN(29, C, 3),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(34, A, 0),
-    __GD32_PIN(35, A, 1),
-    __GD32_PIN(36, A, 2),
-    __GD32_PIN(37, A, 3),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(40, A, 4),
-    __GD32_PIN(41, A, 5),
-    __GD32_PIN(42, A, 6),
-    __GD32_PIN(43, A, 7),
-    __GD32_PIN(44, C, 4),
-    __GD32_PIN(45, C, 5),
-    __GD32_PIN(46, B, 0),
-    __GD32_PIN(47, B, 1),
-    __GD32_PIN(48, B, 2),
-    __GD32_PIN(49, F, 11),
-    __GD32_PIN(50, F, 12),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(53, F, 13),
-    __GD32_PIN(54, F, 14),
-    __GD32_PIN(55, F, 15),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(69, B, 10),
-    __GD32_PIN(70, B, 11),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(73, B, 12),
-    __GD32_PIN(74, B, 13),
-    __GD32_PIN(75, B, 14),
-    __GD32_PIN(76, B, 15),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(96, C, 6),
-    __GD32_PIN(97, C, 7),
-    __GD32_PIN(98, C, 8),
-    __GD32_PIN(99, C, 9),
-    __GD32_PIN(100, A, 8),
-    __GD32_PIN(101, A, 9),
-    __GD32_PIN(102, A, 10),
-    __GD32_PIN(103, A, 11),
-    __GD32_PIN(104, A, 12),
-    __GD32_PIN(105, A, 13),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(109, A, 14),
-    __GD32_PIN(110, A, 15),
-    __GD32_PIN(111, C, 10),
-    __GD32_PIN(112, C, 11),
-    __GD32_PIN(113, C, 12),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(133, B, 3),
-    __GD32_PIN(134, B, 4),
-    __GD32_PIN(135, B, 5),
-    __GD32_PIN(136, B, 6),
-    __GD32_PIN(137, B, 7),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN(139, B, 8),
-    __GD32_PIN(140, B, 9),
-    __GD32_PIN_DEFAULT,
-    __GD32_PIN_DEFAULT,
+    __GD32_PIN(2, F, 0),
+    __GD32_PIN(3, F, 1),
+	  __GD32_PIN_DEFAULT,
+		__GD32_PIN_DEFAULT,
+    __GD32_PIN(6, A, 0),
+    __GD32_PIN(7, A, 1),
+    __GD32_PIN(8, A, 2),
+    __GD32_PIN(9, A, 3),
+    __GD32_PIN(10, A, 4),
+    __GD32_PIN(11, A, 5),
+    __GD32_PIN(12, A, 6),
+    __GD32_PIN(13, A, 7),
+    __GD32_PIN(14, B, 0),
+    __GD32_PIN(15, B, 1),
+    __GD32_PIN(16, B, 2),
+		__GD32_PIN_DEFAULT,
+    __GD32_PIN(18, A, 8),
+    __GD32_PIN(19, A, 9),
+    __GD32_PIN(20, A, 10),
+    __GD32_PIN(21, A, 11),
+    __GD32_PIN(22, A, 12),
+    __GD32_PIN(23, A, 13),
+    __GD32_PIN(24, A, 14),
+    __GD32_PIN(25, A, 15),
+    __GD32_PIN(26, B, 3),
+    __GD32_PIN(27, B, 4),
+    __GD32_PIN(28, B, 5),
+    __GD32_PIN(29, B, 6),
+    __GD32_PIN(30, B, 7),
+    __GD32_PIN_DEFAULT,
+    __GD32_PIN(32, B, 8),
 };
 
 struct pin_irq_map
diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.c b/bsp/gd32e230k-start/drivers/drv_i2c.c
index c0fbd5f7e9..78ddd99bdd 100644
--- a/bsp/gd32e230k-start/drivers/drv_i2c.c
+++ b/bsp/gd32e230k-start/drivers/drv_i2c.c
@@ -1,7 +1,7 @@
 /*
  * File      : drv_i2c.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ * COPYRIGHT (C) 2006 - 2019, RT-Thread Development Team
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
  * Date           Author       Notes
  * 2017-06-05     tanek        first implementation.
  * 2018-04-19     misonyo      Porting for gd32f30x
+ * 2019-03-31     xuzhuoyi     Porting for gd32e230
  */
 
 #include "drv_i2c.h"
diff --git a/bsp/gd32e230k-start/drivers/drv_spi.c b/bsp/gd32e230k-start/drivers/drv_spi.c
index 7c749d75e0..1611b1d338 100644
--- a/bsp/gd32e230k-start/drivers/drv_spi.c
+++ b/bsp/gd32e230k-start/drivers/drv_spi.c
@@ -1,7 +1,7 @@
 /*
  * File      : drv_spi.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017 RT-Thread Develop Team
+ * COPYRIGHT (C) 2019 RT-Thread Develop Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -11,6 +11,7 @@
  * Date           Author       Notes
  * 2017-06-05     tanek        first implementation.
  * 2018-04-19     misonyo      Porting for gd32f30x
+ * 2019-03-31     xuzhuoyi     Porting for gd32e230
  */
 
 #include "drv_spi.h"
@@ -20,8 +21,7 @@
 #if defined(RT_USING_SPI) && defined(RT_USING_PIN)
 #include <rtdevice.h>
 
-#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \
-    !defined(RT_USING_SPI2)
+#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1)
 #error "Please define at least one SPIx"
 #endif
 
diff --git a/bsp/gd32e230k-start/drivers/drv_usart.c b/bsp/gd32e230k-start/drivers/drv_usart.c
index c34ca232cb..eef2f741b8 100644
--- a/bsp/gd32e230k-start/drivers/drv_usart.c
+++ b/bsp/gd32e230k-start/drivers/drv_usart.c
@@ -11,6 +11,7 @@
  * Date           Author       Notes
  * 2009-01-05     Bernard      the first version
  * 2018-04-19     misonyo      Porting for gd32f30x
+ * 2019-03-31     xuzhuoyi     Porting for gd32e230
  */
 
 #include <rthw.h>
@@ -23,9 +24,7 @@
 #define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
 #define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
 
-#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) && \
-    !defined(RT_USING_USART2) && !defined(RT_USING_UART3)  && \
-    !defined(RT_USING_UART4)
+#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1)
 #error "Please define at least one UARTx"
 
 #endif
@@ -84,53 +83,6 @@ void USART1_IRQHandler(void)
 
 #endif /* RT_USING_UART1 */
 
-#if defined(RT_USING_USART2)
-struct rt_serial_device serial2;
-
-void USART2_IRQHandler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    uart_isr(&serial2);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-#endif /* RT_USING_UART2 */
-
-#if defined(RT_USING_UART3)
-struct rt_serial_device serial3;
-
-void UART3_IRQHandler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    uart_isr(&serial3);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-#endif /* RT_USING_UART3 */
-
-#if defined(RT_USING_UART4)
-struct rt_serial_device serial4;
-
-void UART4_IRQHandler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    uart_isr(&serial4);
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif /* RT_USING_UART4 */
-
 static const struct gd32_uart uarts[] = {
     #ifdef RT_USING_USART0
     {
@@ -155,42 +107,6 @@ static const struct gd32_uart uarts[] = {
         "uart1",
     },
     #endif
-    
-    #ifdef RT_USING_USART2
-    {
-        USART2,                                 // uart peripheral index
-        USART2_IRQn,                            // uart iqrn
-        RCU_USART2, RCU_GPIOB, RCU_GPIOB,       // periph clock, tx gpio clock, rt gpio clock
-        GPIOB, GPIO_PIN_10,                     // tx port, tx alternate, tx pin
-        GPIOB, GPIO_PIN_11,                     // rx port, rx alternate, rx pin
-        &serial2,
-        "uart2",
-    },
-    #endif
-    
-    #ifdef RT_USING_UART3
-    {
-        UART3,                                 // uart peripheral index
-        UART3_IRQn,                            // uart iqrn
-        RCU_UART3, RCU_GPIOC, RCU_GPIOC,       // periph clock, tx gpio clock, rt gpio clock
-        GPIOC, GPIO_PIN_10,                    // tx port, tx alternate, tx pin
-        GPIOC, GPIO_PIN_11,                    // rx port, rx alternate, rx pin
-        &serial3,
-        "uart3",
-    },
-    #endif
-    
-    #ifdef RT_USING_UART4
-    {
-        UART4,                                 // uart peripheral index
-        UART4_IRQn,                            // uart iqrn
-        RCU_UART4, RCU_GPIOC, RCU_GPIOD,       // periph clock, tx gpio clock, rt gpio clock
-        GPIOC, GPIO_PIN_12,                    // tx port, tx alternate, tx pin
-        GPIOD, GPIO_PIN_2,                     // rx port, rx alternate, rx pin
-        &serial4,
-        "uart4",
-    },
-    #endif
 };
 
 
diff --git a/bsp/gd32e230k-start/project.uvoptx b/bsp/gd32e230k-start/project.uvoptx
index aa084f2049..5da1234dd3 100644
--- a/bsp/gd32e230k-start/project.uvoptx
+++ b/bsp/gd32e230k-start/project.uvoptx
@@ -103,7 +103,7 @@
         <bEvRecOn>1</bEvRecOn>
         <bSchkAxf>0</bSchkAxf>
         <bTchkAxf>0</bTchkAxf>
-        <nTsel>14</nTsel>
+        <nTsel>19</nTsel>
         <sDll></sDll>
         <sDllPa></sDllPa>
         <sDlgDll></sDlgDll>
@@ -384,7 +384,7 @@
 
   <Group>
     <GroupName>Drivers</GroupName>
-    <tvExp>0</tvExp>
+    <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
diff --git a/bsp/gd32e230k-start/project.uvprojx b/bsp/gd32e230k-start/project.uvprojx
index 4466ae7d45..115df957ba 100644
--- a/bsp/gd32e230k-start/project.uvprojx
+++ b/bsp/gd32e230k-start/project.uvprojx
@@ -10,7 +10,7 @@
       <TargetName>rt-thread_gd32e230</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
-      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <pCCUsed>6120000::V6.12::.\ARMCLANG</pCCUsed>
       <uAC6>1</uAC6>
       <TargetOption>
         <TargetCommonOption>
@@ -312,10 +312,10 @@
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
-            <Optim>1</Optim>
+            <Optim>7</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
-            <OneElfS>0</OneElfS>
+            <OneElfS>1</OneElfS>
             <Strict>0</Strict>
             <EnumInt>0</EnumInt>
             <PlainCh>0</PlainCh>
@@ -684,9 +684,9 @@
                 <v6WtE>2</v6WtE>
                 <v6Rtti>2</v6Rtti>
                 <VariousControls>
-                  <MiscControls> --c99</MiscControls>
-                  <Define> </Define>
-                  <Undefine> </Undefine>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
                   <IncludePath></IncludePath>
                 </VariousControls>
               </Cads>
diff --git a/bsp/gd32e230k-start/rtconfig.h b/bsp/gd32e230k-start/rtconfig.h
index b490faaf8a..ef5a6509f7 100644
--- a/bsp/gd32e230k-start/rtconfig.h
+++ b/bsp/gd32e230k-start/rtconfig.h
@@ -148,8 +148,13 @@
 /* miscellaneous packages */
 
 
+/* sample package */
+
 /* samples: kernel and components samples */
 
+
+/* example package: hello */
+
 #define RT_USING_USART0
 #define RT_USING_USART1
 #define RT_USING_SPI0
diff --git a/bsp/gd32e230k-start/template.uvoptx b/bsp/gd32e230k-start/template.uvoptx
index 93d9c266ef..090bdb9227 100644
--- a/bsp/gd32e230k-start/template.uvoptx
+++ b/bsp/gd32e230k-start/template.uvoptx
@@ -103,7 +103,7 @@
         <bEvRecOn>1</bEvRecOn>
         <bSchkAxf>0</bSchkAxf>
         <bTchkAxf>0</bTchkAxf>
-        <nTsel>14</nTsel>
+        <nTsel>19</nTsel>
         <sDll></sDll>
         <sDllPa></sDllPa>
         <sDlgDll></sDlgDll>
diff --git a/bsp/gd32e230k-start/template.uvprojx b/bsp/gd32e230k-start/template.uvprojx
index cf0ba886d1..43c9f16629 100644
--- a/bsp/gd32e230k-start/template.uvprojx
+++ b/bsp/gd32e230k-start/template.uvprojx
@@ -312,10 +312,10 @@
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
-            <Optim>1</Optim>
+            <Optim>7</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
-            <OneElfS>0</OneElfS>
+            <OneElfS>1</OneElfS>
             <Strict>0</Strict>
             <EnumInt>0</EnumInt>
             <PlainCh>0</PlainCh>
diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S
index d9993247e2..4fc5a3adbd 100644
--- a/libcpu/arm/cortex-m23/context_gcc.S
+++ b/libcpu/arm/cortex-m23/context_gcc.S
@@ -1,19 +1,20 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date         Author    Notes
+ * Date         Author       Notes
  * 2010-01-25   Bernard      first version
  * 2012-06-01   aozima       set pendsv priority to 0xFF.
  * 2012-08-17   aozima       fixed bug: store r8 - r11.
  * 2013-02-20   aozima       port to gcc.
  * 2013-06-18   aozima       add restore MSP feature.
  * 2013-11-04   bright       fixed hardfault bug for gcc.
+ * 2019-03-31   xuzhuoyi     port to Cortex-M23.
  */
  
-    .cpu    cortex-m0
+    .cpu    cortex-m23
     .fpu    softvfp
     .syntax unified
     .thumb
diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S
index 50d3781359..4f30c0bc0c 100644
--- a/libcpu/arm/cortex-m23/context_iar.S
+++ b/libcpu/arm/cortex-m23/context_iar.S
@@ -1,5 +1,5 @@
 ;/*
-; * Copyright (c) 2006-2018, RT-Thread Development Team
+; * Copyright (c) 2006-2019, RT-Thread Development Team
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -9,10 +9,11 @@
 ; * 2012-06-01     aozima       set pendsv priority to 0xFF.
 ; * 2012-08-17     aozima       fixed bug: store r8 - r11.
 ; * 2013-06-18     aozima       add restore MSP feature.
+; * 2019-03-31     xuzhuoyi     port to Cortex-M23.
 ; */
 
 ;/**
-; * @addtogroup CORTEX-M0
+; * @addtogroup CORTEX-M23
 ; */
 ;/*@{*/
 
diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S
index 54145773d3..f243097cc6 100644
--- a/libcpu/arm/cortex-m23/context_rvds.S
+++ b/libcpu/arm/cortex-m23/context_rvds.S
@@ -1,5 +1,5 @@
 ;/*
-; * Copyright (c) 2006-2018, RT-Thread Development Team
+; * Copyright (c) 2006-2019, RT-Thread Development Team
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -9,6 +9,7 @@
 ; * 2012-06-01     aozima       set pendsv priority to 0xFF.
 ; * 2012-08-17     aozima       fixed bug: store r8 - r11.
 ; * 2013-06-18     aozima       add restore MSP feature.
+; * 2019-03-31     xuzhuoyi     port to Cortex-M23.
 ; */
 
 ;/**
diff --git a/libcpu/arm/cortex-m23/cpuport.c b/libcpu/arm/cortex-m23/cpuport.c
index 5d36fa11fe..842802c866 100644
--- a/libcpu/arm/cortex-m23/cpuport.c
+++ b/libcpu/arm/cortex-m23/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,6 +9,7 @@
  * 2012-05-31     aozima       Merge all of the C source code into cpuport.c
  * 2012-08-17     aozima       fixed bug: store r8 - r11.
  * 2012-12-23     aozima       stack addr align to 8byte.
+ * 2019-03-31     xuzhuoyi     port to Cortex-M23.
  */
 
 #include <rtthread.h>
-- 
cgit v1.3.1


From b10039f396cb1f32cb0a4b7ee3692bf96332fc1e Mon Sep 17 00:00:00 2001
From: qz721 <295354721@qq.com>
Date: Mon, 1 Apr 2019 14:21:59 +0800
Subject: Disable the data alignment check.

---
 libcpu/arm/cortex-a/start_gcc.S | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 0f4ff58364..7464ba6161 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -51,6 +51,11 @@ _reset:
     /* set the cpu to SVC32 mode and disable interrupt */
     cps #Mode_SVC
 
+    /* disable the data alignment check */
+    mrc p15, 0, r1, c1, c0, 0
+    bic r1, #(1<<1)
+    mcr p15, 0, r1, c1, c0, 0
+
     /* setup stack */
     bl      stack_setup
 
-- 
cgit v1.3.1


From 4acd8db61eb366878b849716db25558abaa5325b Mon Sep 17 00:00:00 2001
From: xuzhuoyi <xzy476386434@vip.qq.com>
Date: Wed, 10 Apr 2019 22:33:25 +0800
Subject: [bsp][tms320f28379d] Add finsh init in rt_init_thread

---
 bsp/tms320f28379d/applications/application.c |  9 ++++---
 bsp/tms320f28379d/drivers/board.c            | 11 +++++++-
 bsp/tms320f28379d/drivers/drv_sci.c          |  4 +--
 libcpu/ti-dsp/c28x/context.s                 | 40 ++++++++++++++++++++++++----
 libcpu/ti-dsp/c28x/cpuport.c                 |  4 +++
 5 files changed, 56 insertions(+), 12 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/tms320f28379d/applications/application.c b/bsp/tms320f28379d/applications/application.c
index 4ceb5eef75..5c7b769a4d 100644
--- a/bsp/tms320f28379d/applications/application.c
+++ b/bsp/tms320f28379d/applications/application.c
@@ -12,12 +12,15 @@
 #include <board.h>
 #include <rtthread.h>
 
+#ifdef RT_USING_FINSH
+#include "shell.h"
+#endif
+
 void rt_init_thread_entry(void* parameter)
 {
-    /* initialization RT-Thread Components */
-    rt_components_init();
+#ifdef RT_USING_FINSH
     finsh_system_init();
-	
+#endif
 }
 
 int rt_application_init()
diff --git a/bsp/tms320f28379d/drivers/board.c b/bsp/tms320f28379d/drivers/board.c
index ee1c9f06af..b83cb7a966 100644
--- a/bsp/tms320f28379d/drivers/board.c
+++ b/bsp/tms320f28379d/drivers/board.c
@@ -13,8 +13,16 @@
 #include "drv_sci.h"
 #include "F28x_Project.h"
 
+extern rt_uint32_t rt_thread_switch_interrupt_flag;
+
 extern interrupt void RTOSINT_Handler();
 
+void trap_rtosint()
+{
+    if(rt_thread_switch_interrupt_flag)
+        asm(" trap #16");
+}
+
 /**
  * This is the timer interrupt service routine.
  *
@@ -31,7 +39,7 @@ interrupt void cpu_timer2_isr(void)
 }
 
 /**
- * This function will initial STM32 board.
+ * This function will initial TMS320F28379D board.
  */
 void rt_hw_board_init()
 {
@@ -68,4 +76,5 @@ void rt_hw_board_init()
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
+    rt_interrupt_leave_sethook((void (*)(void))trap_rtosint);
 }
diff --git a/bsp/tms320f28379d/drivers/drv_sci.c b/bsp/tms320f28379d/drivers/drv_sci.c
index e345097f06..0920d382f5 100644
--- a/bsp/tms320f28379d/drivers/drv_sci.c
+++ b/bsp/tms320f28379d/drivers/drv_sci.c
@@ -214,7 +214,6 @@ int rt_hw_sci_init(void)
     CpuSysRegs.PCLKCR7.bit.SCI_C = 1;
 
     PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr;
-    //PieVectTable.SCIA_TX_INT = &sciaTxFifoIsr;
 
     EDIS;
 
@@ -223,8 +222,7 @@ int rt_hw_sci_init(void)
     //
     PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
     PieCtrlRegs.PIEIER9.bit.INTx1 = 1;   // PIE Group 9, INT1
-    //PieCtrlRegs.PIEIER9.bit.INTx2 = 1;   // PIE Group 9, INT2
-    IER = 0x100;                         // Enable CPU INT
+    IER |= 0x100;                        // Enable CPU INT
     EINT;
 
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
diff --git a/libcpu/ti-dsp/c28x/context.s b/libcpu/ti-dsp/c28x/context.s
index 019b5def13..fc1734f5ca 100644
--- a/libcpu/ti-dsp/c28x/context.s
+++ b/libcpu/ti-dsp/c28x/context.s
@@ -94,11 +94,10 @@ _rt_hw_interrupt_enable:
  
     .asmfunc
 _rt_hw_context_switch_interrupt:
-_rt_hw_context_switch:
     MOVL    XAR0, #0
     MOV     AR0, AL
     MOVL    XAR4, *-SP[4]
-    ; set rt_thread_switch_interrupt_flag to 1 
+    ; set rt_thread_switch_interrupt_flag to 1
     MOVL    XAR5, #_rt_thread_switch_interrupt_flag
     MOVL    XAR6, *XAR5
     MOVL    ACC, XAR6
@@ -114,6 +113,37 @@ _reswitch:
     MOVL    XAR5, #_rt_interrupt_to_thread     ; set rt_interrupt_to_thread
     MOVL    *XAR5, XAR4
 
+    ;TRAP    #16
+    LRETR
+    .endasmfunc
+
+;
+; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; r0 --> from
+; r4 --> to
+
+
+    .asmfunc
+_rt_hw_context_switch:
+    MOVL    XAR0, #0
+    MOV     AR0, AL
+    MOVL    XAR4, *-SP[4]
+    ; set rt_thread_switch_interrupt_flag to 1 
+    MOVL    XAR5, #_rt_thread_switch_interrupt_flag
+    MOVL    XAR6, *XAR5
+    MOVL    ACC, XAR6
+    CMPB    AL, #1
+    B       _reswitch2, EQ
+    MOVL     XAR6, #1
+    MOVL    *XAR5, XAR6
+
+    MOVL    XAR5, #_rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    MOVL    *XAR5, XAR0
+
+_reswitch2:
+    MOVL    XAR5, #_rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    MOVL    *XAR5, XAR4
+
     TRAP    #16
     LRETR
     .endasmfunc
@@ -159,9 +189,9 @@ _RTOSINT_Handler:
 ;#endif
 
     MOV     AL, *AR0
-    MOV     AR1, AL
+    MOV     AR0, AL
     MOVZ    AR1, @SP                 ; get from thread stack pointer
-    MOV     *AR0, AR1                ; update from thread stack pointer 
+    MOV     *AR0, AR1                ; update from thread stack pointer
 
 switch_to_thread:
     MOV     AR1, #_rt_interrupt_to_thread
@@ -175,7 +205,7 @@ switch_to_thread:
 ;#endif
 
     MOV     @SP, AR1
-    INC     SP
+    ;INC     SP
     RT_CTX_RESTORE     ; pop r4 - r11 register
 
 rtosint_exit:
diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c
index 8885f647a9..2d42884bed 100644
--- a/libcpu/ti-dsp/c28x/cpuport.c
+++ b/libcpu/ti-dsp/c28x/cpuport.c
@@ -17,6 +17,9 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 /* exception hook */
 static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
 
+extern rt_uint16_t rt_hw_get_st0(void);
+extern rt_uint16_t rt_hw_get_st1(void);
+
 struct exception_stack_frame
 {
     rt_uint32_t t_st0;
@@ -59,6 +62,7 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
     stk  = stack_addr;
     stk  = (rt_uint8_t *)RT_ALIGN((rt_uint32_t)stk, 8);
     //stk -= sizeof(struct stack_frame);
+    stk += 1;
 
     stack_frame = (struct stack_frame *)stk;
 
-- 
cgit v1.3.1


From 752152b63e5b8f3a82de7b39255712f41e7efac2 Mon Sep 17 00:00:00 2001
From: xuzhuoyi <xzy476386434@vip.qq.com>
Date: Sun, 14 Apr 2019 12:26:25 +0800
Subject: [bsp][tms320f28379d] Fix FPU config problem

---
 bsp/tms320f28379d/.cproject  | 2 +-
 libcpu/ti-dsp/c28x/context.s | 5 +----
 2 files changed, 2 insertions(+), 5 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/tms320f28379d/.cproject b/bsp/tms320f28379d/.cproject
index 15acd78f25..3641f26b27 100644
--- a/bsp/tms320f28379d/.cproject
+++ b/bsp/tms320f28379d/.cproject
@@ -32,7 +32,7 @@
 								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.LARGE_MEMORY_MODEL.2001892821" name="Option deprecated, set by default (--large_memory_model, -ml)" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.LARGE_MEMORY_MODEL" value="true" valueType="boolean"/>
 								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.UNIFIED_MEMORY.1224119119" name="Unified memory (--unified_memory, -mt)" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.UNIFIED_MEMORY" value="true" valueType="boolean"/>
 								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.SILICON_VERSION.1107602335" name="Processor version (--silicon_version, -v)" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.SILICON_VERSION.28" valueType="enumerated"/>
-								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.FLOAT_SUPPORT.1330432923" name="Specify floating point support (--float_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.FLOAT_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.FLOAT_SUPPORT.fpu32" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.FLOAT_SUPPORT.1330432923" name="Specify floating point support (--float_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.FLOAT_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.FLOAT_SUPPORT.softlib" valueType="enumerated"/>
 								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.CLA_SUPPORT.1090597518" name="Specify CLA support (--cla_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.CLA_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.CLA_SUPPORT.cla1" valueType="enumerated"/>
 								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.VCU_SUPPORT.1640791193" name="Specify VCU support (--vcu_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.VCU_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.VCU_SUPPORT.vcu2" valueType="enumerated"/>
 								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.TMU_SUPPORT.1184307973" name="Specify TMU support (--tmu_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.TMU_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_18.1.compilerID.TMU_SUPPORT.tmu0" valueType="enumerated"/>
diff --git a/libcpu/ti-dsp/c28x/context.s b/libcpu/ti-dsp/c28x/context.s
index fc1734f5ca..2b853a0075 100644
--- a/libcpu/ti-dsp/c28x/context.s
+++ b/libcpu/ti-dsp/c28x/context.s
@@ -113,7 +113,6 @@ _reswitch:
     MOVL    XAR5, #_rt_interrupt_to_thread     ; set rt_interrupt_to_thread
     MOVL    *XAR5, XAR4
 
-    ;TRAP    #16
     LRETR
     .endasmfunc
 
@@ -169,8 +168,6 @@ _RTOSINT_Handler:
     MOV     AR1, AL
     CMP     AR1, #0
     B       switch_to_thread, EQ    ; skip register save at the first time 
-
-    ;MOVZ    AR1, @SP                 ; get from thread stack pointer 
     
 ;#if defined (__VFP_FP__) && !defined(__SOFTFP__)
 ;    TST     lr, #0x10           ; if(!EXC_RETURN[4]) 
@@ -205,7 +202,7 @@ switch_to_thread:
 ;#endif
 
     MOV     @SP, AR1
-    ;INC     SP
+
     RT_CTX_RESTORE     ; pop r4 - r11 register
 
 rtosint_exit:
-- 
cgit v1.3.1


From 61f2a71511121bf48949a6f3df9cd4089410b003 Mon Sep 17 00:00:00 2001
From: qz721 <295354721@qq.com>
Date: Fri, 26 Apr 2019 10:50:48 +0800
Subject: Rename 'platform.h' in 'imx6ul' and 'qemu-vexpress-a9' BSPs.

This filename conflicts with the 'mbedtls' package. They are renamed
in the name of the corresponding chips and included in 'board.h'.
Files that rely on this file should include 'board.h' instead.
---
 bsp/imx6ul/drivers/board.h                   |  1 +
 bsp/imx6ul/drivers/imx6ul.h                  | 96 ++++++++++++++++++++++++++++
 bsp/imx6ul/platform/cpu/platform.h           | 96 ----------------------------
 bsp/qemu-vexpress-a9/drivers/board.h         |  1 +
 bsp/qemu-vexpress-a9/drivers/vexpress_a9.h   | 37 +++++++++++
 bsp/qemu-vexpress-a9/platform/SConscript     | 13 ----
 bsp/qemu-vexpress-a9/platform/cpu/platform.h | 37 -----------
 libcpu/arm/cortex-a/gic.h                    |  2 +-
 libcpu/arm/cortex-a/interrupt.h              |  2 +-
 libcpu/arm/cortex-a/trap.c                   |  2 +-
 10 files changed, 138 insertions(+), 149 deletions(-)
 create mode 100644 bsp/imx6ul/drivers/imx6ul.h
 delete mode 100644 bsp/imx6ul/platform/cpu/platform.h
 create mode 100644 bsp/qemu-vexpress-a9/drivers/vexpress_a9.h
 delete mode 100644 bsp/qemu-vexpress-a9/platform/SConscript
 delete mode 100644 bsp/qemu-vexpress-a9/platform/cpu/platform.h

(limited to 'libcpu')

diff --git a/bsp/imx6ul/drivers/board.h b/bsp/imx6ul/drivers/board.h
index 3e98e302c2..76593e2f08 100644
--- a/bsp/imx6ul/drivers/board.h
+++ b/bsp/imx6ul/drivers/board.h
@@ -13,6 +13,7 @@
 
 #include <registers.h>
 #include <irq_numbers.h>
+#include "imx6ul.h"
 
 #define CONFIG_MX6
 #define CONFIG_MX6UL
diff --git a/bsp/imx6ul/drivers/imx6ul.h b/bsp/imx6ul/drivers/imx6ul.h
new file mode 100644
index 0000000000..7f0db1354f
--- /dev/null
+++ b/bsp/imx6ul/drivers/imx6ul.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-22     quanzhao     first version
+ */
+#ifndef __IMX6UL_H__
+#define __IMX6UL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+/* SOC-relative definitions */
+//#include "realview.h"
+#include "gic_registers.h"
+#include "irq_numbers.h"
+
+/* the maximum number of gic */
+# define ARM_GIC_MAX_NR 1
+
+/* the maximum number of interrupts */
+#define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT
+
+/* the maximum entries of the interrupt table */
+#define MAX_HANDLERS IMX_INTERRUPT_COUNT
+
+/* the basic constants needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    rt_uint32_t gic_base;
+    asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
+    return gic_base + kGICDBaseOffset;
+}
+
+rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
+{
+    rt_uint32_t gic_base;
+    asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
+    return gic_base + kGICCBaseOffset;
+}
+
+#define GIC_IRQ_START   0
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+/* the definition needed by gic.c */
+#define __REG32(x)  (*((volatile unsigned int *)(x)))
+
+/* keep compatible with platform SDK */
+typedef enum {
+    CPU_0,
+    CPU_1,
+    CPU_2,
+    CPU_3,
+} cpuid_e;
+
+enum _gicd_sgi_filter
+{
+    //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
+    kGicSgiFilter_UseTargetList = 0,
+
+    //! Forward the interrupt to all CPU interfaces except that of the processor that requested
+    //! the interrupt.
+    kGicSgiFilter_AllOtherCPUs = 1,
+
+    //! Forward the interrupt only to the CPU interface of the processor that requested the
+    //! interrupt.
+    kGicSgiFilter_OnlyThisCPU = 2
+};
+
+typedef void (*irq_hdlr_t) (void);
+
+extern void rt_hw_interrupt_mask(int vector);
+extern void rt_hw_interrupt_umask(int vector);
+extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+    void *param, const char *name);
+
+rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
+{
+    rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
+}
+
+rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
+{
+    rt_hw_interrupt_umask(irq_id);
+}
+
+rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
+{
+    rt_hw_interrupt_mask(irq_id);
+}
+
+#endif  /* __IMX6UL_H__ */
diff --git a/bsp/imx6ul/platform/cpu/platform.h b/bsp/imx6ul/platform/cpu/platform.h
deleted file mode 100644
index f6a3995bc5..0000000000
--- a/bsp/imx6ul/platform/cpu/platform.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-03-22     quanzhao     first version
- */
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-/* SOC-relative definitions */
-//#include "realview.h"
-#include "gic_registers.h"
-#include "irq_numbers.h"
-
-/* the maximum number of gic */
-# define ARM_GIC_MAX_NR 1
-
-/* the maximum number of interrupts */
-#define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT
-
-/* the maximum entries of the interrupt table */
-#define MAX_HANDLERS IMX_INTERRUPT_COUNT
-
-/* the basic constants needed by gic */
-rt_inline rt_uint32_t platform_get_gic_dist_base(void)
-{
-    rt_uint32_t gic_base;
-    asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
-    return gic_base + kGICDBaseOffset;
-}
-
-rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
-{
-    rt_uint32_t gic_base;
-    asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
-    return gic_base + kGICCBaseOffset;
-}
-
-#define GIC_IRQ_START   0
-
-#define GIC_ACK_INTID_MASK              0x000003ff
-
-/* the definition needed by gic.c */
-#define __REG32(x)  (*((volatile unsigned int *)(x)))
-
-/* keep compatible with platform SDK */
-typedef enum {
-    CPU_0,
-    CPU_1,
-    CPU_2,
-    CPU_3,
-} cpuid_e;
-
-enum _gicd_sgi_filter
-{
-    //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
-    kGicSgiFilter_UseTargetList = 0,
-
-    //! Forward the interrupt to all CPU interfaces except that of the processor that requested
-    //! the interrupt.
-    kGicSgiFilter_AllOtherCPUs = 1,
-
-    //! Forward the interrupt only to the CPU interface of the processor that requested the
-    //! interrupt.
-    kGicSgiFilter_OnlyThisCPU = 2
-};
-
-typedef void (*irq_hdlr_t) (void);
-
-extern void rt_hw_interrupt_mask(int vector);
-extern void rt_hw_interrupt_umask(int vector);
-extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-    void *param, const char *name);
-
-rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
-{
-    rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
-}
-
-rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
-{
-    rt_hw_interrupt_umask(irq_id);
-}
-
-rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
-{
-    rt_hw_interrupt_mask(irq_id);
-}
-
-#endif  /* __PLATFORM_H__ */
diff --git a/bsp/qemu-vexpress-a9/drivers/board.h b/bsp/qemu-vexpress-a9/drivers/board.h
index 2d3d87fdbb..ccbe0f8c9e 100644
--- a/bsp/qemu-vexpress-a9/drivers/board.h
+++ b/bsp/qemu-vexpress-a9/drivers/board.h
@@ -16,6 +16,7 @@
 #define __BOARD_H__
 
 #include <realview.h>
+#include "vexpress_a9.h"
 
 #if defined(__CC_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
diff --git a/bsp/qemu-vexpress-a9/drivers/vexpress_a9.h b/bsp/qemu-vexpress-a9/drivers/vexpress_a9.h
new file mode 100644
index 0000000000..a6467973c5
--- /dev/null
+++ b/bsp/qemu-vexpress-a9/drivers/vexpress_a9.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-22     quanzhao     first version
+ */
+
+#ifndef __VEXPRESS_A9_H__
+#define __VEXPRESS_A9_H__
+
+/* for 'rt_inline' */
+#include <rtdef.h>
+/* SOC-relative definitions */
+#include "realview.h"
+
+/* the maximum entries of the exception table */
+#define MAX_HANDLERS    NR_IRQS_PBA8
+
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    return REALVIEW_GIC_DIST_BASE;
+}
+
+rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
+{
+    return REALVIEW_GIC_CPU_BASE;
+}
+
+#define GIC_IRQ_START   0
+
+#define GIC_ACK_INTID_MASK  0x000003ff
+
+#endif  /* __VEXPRESS_A9_H__ */
diff --git a/bsp/qemu-vexpress-a9/platform/SConscript b/bsp/qemu-vexpress-a9/platform/SConscript
deleted file mode 100644
index 1b580929da..0000000000
--- a/bsp/qemu-vexpress-a9/platform/SConscript
+++ /dev/null
@@ -1,13 +0,0 @@
-from building import *
-
-cwd = GetCurrentDir()
-src = Split('''
-''')
-
-CPPPATH = [ cwd + '/cpu',
-cwd + '/include',
-]
-
-group = DefineGroup('Platform', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/qemu-vexpress-a9/platform/cpu/platform.h b/bsp/qemu-vexpress-a9/platform/cpu/platform.h
deleted file mode 100644
index 2d5cc5f61b..0000000000
--- a/bsp/qemu-vexpress-a9/platform/cpu/platform.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-03-22     quanzhao     first version
- */
-
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
-
-/* for 'rt_inline' */
-#include <rtdef.h>
-/* SOC-relative definitions */
-#include "realview.h"
-
-/* the maximum entries of the exception table */
-#define MAX_HANDLERS    NR_IRQS_PBA8
-
-/* the basic constants and interfaces needed by gic */
-rt_inline rt_uint32_t platform_get_gic_dist_base(void)
-{
-    return REALVIEW_GIC_DIST_BASE;
-}
-
-rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
-{
-    return REALVIEW_GIC_CPU_BASE;
-}
-
-#define GIC_IRQ_START   0
-
-#define GIC_ACK_INTID_MASK  0x000003ff
-
-#endif  /* __PLATFORM_H__ */
diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h
index 6d86dd31e0..a16d0467fb 100644
--- a/libcpu/arm/cortex-a/gic.h
+++ b/libcpu/arm/cortex-a/gic.h
@@ -12,7 +12,7 @@
 #define __GIC_H__
 
 #include <rthw.h>
-#include <platform.h>
+#include <board.h>
 
 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
 int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h
index bff29d402d..31f79cc66e 100644
--- a/libcpu/arm/cortex-a/interrupt.h
+++ b/libcpu/arm/cortex-a/interrupt.h
@@ -12,7 +12,7 @@
 #define __INTERRUPT_H__
 
 #include <rthw.h>
-#include <platform.h>
+#include <board.h>
 
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c
index 54628933ff..a25f6ac862 100644
--- a/libcpu/arm/cortex-a/trap.c
+++ b/libcpu/arm/cortex-a/trap.c
@@ -10,7 +10,7 @@
 
 #include <rtthread.h>
 #include <rthw.h>
-#include <platform.h>
+#include <board.h>
 
 #include "armv7.h"
 #include "interrupt.h"
-- 
cgit v1.3.1


From 1e7bd3d8a1082060f6cf71631849da903787d045 Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Sat, 27 Apr 2019 13:54:51 +0800
Subject: 修改lwp支持中arm cortex-a的swi入口函数处理
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 components/lwp/arch/arm/cortex-a/lwp_gcc.S  | 6 +++---
 components/lwp/arch/arm/cortex-a9/lwp_gcc.S | 8 ++++----
 libcpu/arm/cortex-a/start_gcc.S             | 4 +---
 3 files changed, 8 insertions(+), 10 deletions(-)

(limited to 'libcpu')

diff --git a/components/lwp/arch/arm/cortex-a/lwp_gcc.S b/components/lwp/arch/arm/cortex-a/lwp_gcc.S
index 6c89152b0c..395974a2b7 100644
--- a/components/lwp/arch/arm/cortex-a/lwp_gcc.S
+++ b/components/lwp/arch/arm/cortex-a/lwp_gcc.S
@@ -45,9 +45,9 @@ lwp_user_entry:
 /*
  * void SVC_Handler(void);
  */
-.global SVC_Handler
-.type SVC_Handler, % function
-SVC_Handler:
+.global vector_swi
+.type vector_swi, % function
+vector_swi:
     push {lr}
     mrs lr, spsr
     push {r4, r5, lr}
diff --git a/components/lwp/arch/arm/cortex-a9/lwp_gcc.S b/components/lwp/arch/arm/cortex-a9/lwp_gcc.S
index 6c89152b0c..93e88f7c97 100644
--- a/components/lwp/arch/arm/cortex-a9/lwp_gcc.S
+++ b/components/lwp/arch/arm/cortex-a9/lwp_gcc.S
@@ -43,11 +43,11 @@ lwp_user_entry:
     movs    pc, r1
 
 /*
- * void SVC_Handler(void);
+ * void vector_swi(void);
  */
-.global SVC_Handler
-.type SVC_Handler, % function
-SVC_Handler:
+.global vector_swi
+.type vector_swi, % function
+vector_swi:
     push {lr}
     mrs lr, spsr
     push {r4, r5, lr}
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 7464ba6161..51026b7ed5 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -241,9 +241,7 @@ rt_hw_context_switch_interrupt_do:
 .endm
 
     .align  5
-    .globl  vector_swi
-.weak SVC_Handler
-SVC_Handler:
+.weak vector_swi
 vector_swi:
     push_svc_reg
     bl      rt_hw_trap_swi
-- 
cgit v1.3.1


From 0f33da3f0e222461e505a933f4d66b328f10479a Mon Sep 17 00:00:00 2001
From: misonyo <misonyo@foxmail.com>
Date: Sat, 27 Apr 2019 17:35:46 +0800
Subject: [libcpu/cortex-m7]add cache driver

---
 bsp/imxrt/Libraries/imxrt1021/drivers/SConscript  |  1 -
 bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c | 71 ------------------
 bsp/imxrt/Libraries/imxrt1050/drivers/SConscript  |  1 -
 bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c | 71 ------------------
 libcpu/arm/cortex-m7/cpu_cache.c                  | 89 +++++++++++++++++++++++
 5 files changed, 89 insertions(+), 144 deletions(-)
 delete mode 100644 bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c
 delete mode 100644 bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c
 create mode 100644 libcpu/arm/cortex-m7/cpu_cache.c

(limited to 'libcpu')

diff --git a/bsp/imxrt/Libraries/imxrt1021/drivers/SConscript b/bsp/imxrt/Libraries/imxrt1021/drivers/SConscript
index db25271739..b8cd9401cd 100644
--- a/bsp/imxrt/Libraries/imxrt1021/drivers/SConscript
+++ b/bsp/imxrt/Libraries/imxrt1021/drivers/SConscript
@@ -5,7 +5,6 @@ cwd = GetCurrentDir()
 # add the general drivers.
 src = Split("""
 drv_uart.c
-drv_cache.c
 """)
 
 CPPPATH = [cwd]
diff --git a/bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c b/bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c
deleted file mode 100644
index 4f88e769c4..0000000000
--- a/bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-04-02     tanek        first implementation
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <fsl_cache.h>
-
-void rt_hw_cpu_icache_enable(void)
-{
-    SCB_EnableICache();
-}
-
-void rt_hw_cpu_icache_disable(void)
-{
-    SCB_DisableICache();
-}
-
-rt_base_t rt_hw_cpu_icache_status(void)
-{
-    return 0;
-}
-
-void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
-{
-    if (ops & RT_HW_CACHE_INVALIDATE)
-    {
-        ICACHE_InvalidateByRange((uint32_t)addr, size);
-    }
-}
-
-void rt_hw_cpu_dcache_enable(void)
-{
-    SCB_EnableDCache();
-}
-
-void rt_hw_cpu_dcache_disable(void)
-{
-    SCB_DisableDCache();
-}
-
-rt_base_t rt_hw_cpu_dcache_status(void)
-{
-    return 0;
-}
-
-void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
-{
-    if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
-    {
-        DCACHE_CleanInvalidateByRange((uint32_t)addr, size);
-    }
-    else if (ops & RT_HW_CACHE_FLUSH)
-    {
-        DCACHE_CleanByRange((uint32_t)addr, size);
-    }
-    else if (ops & RT_HW_CACHE_INVALIDATE)
-    {
-        DCACHE_InvalidateByRange((uint32_t)addr, size);
-    }
-    else
-    {
-        RT_ASSERT(0);
-    }
-}
diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
index d22ab2b10a..8a322f88f3 100644
--- a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
@@ -5,7 +5,6 @@ cwd = GetCurrentDir()
 # add the general drivers.
 src = Split("""
 drv_uart.c
-drv_cache.c
 """)
 
 CPPPATH = [cwd]
diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c
deleted file mode 100644
index 4f88e769c4..0000000000
--- a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-04-02     tanek        first implementation
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <fsl_cache.h>
-
-void rt_hw_cpu_icache_enable(void)
-{
-    SCB_EnableICache();
-}
-
-void rt_hw_cpu_icache_disable(void)
-{
-    SCB_DisableICache();
-}
-
-rt_base_t rt_hw_cpu_icache_status(void)
-{
-    return 0;
-}
-
-void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
-{
-    if (ops & RT_HW_CACHE_INVALIDATE)
-    {
-        ICACHE_InvalidateByRange((uint32_t)addr, size);
-    }
-}
-
-void rt_hw_cpu_dcache_enable(void)
-{
-    SCB_EnableDCache();
-}
-
-void rt_hw_cpu_dcache_disable(void)
-{
-    SCB_DisableDCache();
-}
-
-rt_base_t rt_hw_cpu_dcache_status(void)
-{
-    return 0;
-}
-
-void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
-{
-    if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
-    {
-        DCACHE_CleanInvalidateByRange((uint32_t)addr, size);
-    }
-    else if (ops & RT_HW_CACHE_FLUSH)
-    {
-        DCACHE_CleanByRange((uint32_t)addr, size);
-    }
-    else if (ops & RT_HW_CACHE_INVALIDATE)
-    {
-        DCACHE_InvalidateByRange((uint32_t)addr, size);
-    }
-    else
-    {
-        RT_ASSERT(0);
-    }
-}
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c
new file mode 100644
index 0000000000..4a1a9c2201
--- /dev/null
+++ b/libcpu/arm/cortex-m7/cpu_cache.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-02     tanek        first implementation
+ * 2019-04-27     misonyo      update to cortex-m7 series
+ */
+
+#include <rthw.h>
+#include <rtdef.h>
+#include <board.h>
+
+/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
+#define L1CACHE_LINESIZE_BYTE       (32)
+
+void rt_hw_cpu_icache_enable(void)
+{
+    SCB_EnableICache();
+}
+
+void rt_hw_cpu_icache_disable(void)
+{
+    SCB_DisableICache();
+}
+
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
+{
+    rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1);
+    rt_int32_t size_byte = size + address - (rt_uint32_t)addr;
+    rt_uint32_t linesize = 32U;
+    if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        __DSB();
+        while (size_byte > 0)
+        {
+            SCB->ICIMVAU = address;
+            address += linesize;
+            size_byte -= linesize;
+        }
+        __DSB();
+        __ISB();
+    }
+}
+
+void rt_hw_cpu_dcache_enable(void)
+{
+    SCB_EnableDCache();
+}
+
+void rt_hw_cpu_dcache_disable(void)
+{
+    SCB_DisableDCache();
+}
+
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
+{
+    rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1);
+    rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr;
+
+    if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
+    {
+        SCB_CleanInvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+    }
+    else if (ops & RT_HW_CACHE_FLUSH)
+    {
+        SCB_CleanDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+    }
+    else if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        SCB_InvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+    }
+    else
+    {
+        RT_ASSERT(0);
+    }
+}
-- 
cgit v1.3.1


From d729448f5e84b96eaede631cab5201c21bfe24e1 Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Thu, 9 May 2019 08:39:08 +0800
Subject: [libcpu][arm/cortex-a] Add correct comments.

---
 libcpu/arm/cortex-a/context_gcc.S | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S
index b009630fa8..af5c516e4d 100644
--- a/libcpu/arm/cortex-a/context_gcc.S
+++ b/libcpu/arm/cortex-a/context_gcc.S
@@ -34,8 +34,9 @@ rt_hw_interrupt_enable:
     bx  lr
 
 /*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
+ * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread);
+ * r0 --> to (thread stack)
+ * r1 --> to_thread
  */
 .globl rt_hw_context_switch_to
 rt_hw_context_switch_to:
@@ -64,9 +65,10 @@ _guest_switch_lvl:
 
 .section .text.isr, "ax"
 /*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r0 --> from
- * r1 --> to
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread);
+ * r0 --> from (from_thread stack)
+ * r1 --> to (to_thread stack)
+ * r2 --> to_thread
  */
 .globl rt_hw_context_switch
 rt_hw_context_switch:
@@ -158,7 +160,7 @@ rt_hw_context_switch_interrupt:
     bl      rt_cpus_lock_status_restore
 
 #ifdef RT_USING_LWP
-    ldmfd sp, {r13,r14}^  @pop usr_sp usr_lr
+    ldmfd sp, {r13,r14}^    @pop usr_sp usr_lr
     add sp, #8
 #endif
 
-- 
cgit v1.3.1


From 6cdfb2ac92d8422136f926024b2c2f969fce6b9e Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Thu, 9 May 2019 19:28:52 +0800
Subject: fix signal code

---
 include/rtdef.h                   |   3 +
 libcpu/arm/cortex-a/context_gcc.S |  81 ++++++------------
 libcpu/arm/cortex-a/start_gcc.S   |  39 +++++++--
 src/scheduler.c                   |  84 +++++++++++++-----
 src/signal.c                      | 176 ++++++++++++++++++++++++++++++--------
 src/thread.c                      |   2 +
 6 files changed, 267 insertions(+), 118 deletions(-)

(limited to 'libcpu')

diff --git a/include/rtdef.h b/include/rtdef.h
index 743b91d959..253333253a 100644
--- a/include/rtdef.h
+++ b/include/rtdef.h
@@ -495,6 +495,7 @@ typedef siginfo_t rt_siginfo_t;
 #define RT_THREAD_STAT_SIGNAL           0x10
 #define RT_THREAD_STAT_SIGNAL_READY     (RT_THREAD_STAT_SIGNAL | RT_THREAD_READY)
 #define RT_THREAD_STAT_SIGNAL_WAIT      0x20
+#define RT_THREAD_STAT_SIGNAL_PENDING   0x40
 #define RT_THREAD_STAT_SIGNAL_MASK      0xf0
 
 /**
@@ -596,7 +597,9 @@ struct rt_thread
     rt_sigset_t     sig_pending;                        /**< the pending signals */
     rt_sigset_t     sig_mask;                           /**< the mask bits of signal */
 
+#ifndef RT_USING_SMP
     void            *sig_ret;                           /**< the return stack pointer from signal */
+#endif
     rt_sighandler_t *sig_vectors;                       /**< vectors of signal handler */
     void            *si_list;                           /**< the signal infor list */
 #endif
diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S
index af5c516e4d..dff7a1de68 100644
--- a/libcpu/arm/cortex-a/context_gcc.S
+++ b/libcpu/arm/cortex-a/context_gcc.S
@@ -46,16 +46,7 @@ rt_hw_context_switch_to:
     mov     r0, r1
     bl      rt_cpus_lock_status_restore
 #endif /*RT_USING_SMP*/
-
-#ifdef RT_USING_LWP
-    ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr
-    add sp, #8
-#endif
-
-    ldmfd sp!, {r4}         @ pop new task spsr
-    msr spsr_cxsf, r4
-
-    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+    b       rt_hw_context_switch_exit
 
 .section .bss.share.isr
 _guest_switch_lvl:
@@ -93,15 +84,7 @@ rt_hw_context_switch:
     mov     r0, r2
     bl      rt_cpus_lock_status_restore
 #endif /*RT_USING_SMP*/
-
-#ifdef RT_USING_LWP
-    ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr
-    add sp, #8
-#endif
-
-    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
-    msr spsr_cxsf, r4
-    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+    b       rt_hw_context_switch_exit
 
 /*
  * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
@@ -123,51 +106,19 @@ rt_hw_context_switch:
 .globl rt_hw_context_switch_interrupt
 rt_hw_context_switch_interrupt:
 #ifdef RT_USING_SMP
-    /* r0 :irq_mod context
+    /* r0 :svc_mod context
      * r1 :addr of from_thread's sp
      * r2 :addr of to_thread's sp
      * r3 :to_thread's tcb
      */
 
-    @ r0 point to {r0-r3} in stack
-    push    {r1 - r3}
-    mov     r1, r0
-    add     r0, r0, #4*4
-    ldmfd   r0!, {r4-r12,lr}@ reload saved registers
-    mrs     r3,  spsr       @ get cpsr of interrupt thread
-    sub     r2,  lr, #4     @ save old task's pc to r2
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
-    stmfd   sp!, {r2}       @ push old task's pc
-    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
-    ldmfd   r1,  {r4-r7}    @ restore r0-r3 of the interrupt thread
-    stmfd   sp!, {r4-r7}    @ push old task's r0-r3
-    stmfd   sp!, {r3}       @ push old task's cpsr
-
-#ifdef RT_USING_LWP
-    stmfd sp, {r13,r14}^    @push usr_sp usr_lr
-    sub sp, #8
-#endif
-
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ
-    pop     {r1 - r3}
-    mov     sp, r0
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
-    str     sp, [r1]
+    str     r0, [r1]
 
     ldr     sp, [r2]
     mov     r0, r3
     bl      rt_cpus_lock_status_restore
 
-#ifdef RT_USING_LWP
-    ldmfd sp, {r13,r14}^    @pop usr_sp usr_lr
-    add sp, #8
-#endif
-
-    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
-    msr     spsr_cxsf, r4
-
-    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+    b       rt_hw_context_switch_exit
 
 #else /*RT_USING_SMP*/
     ldr r2, =rt_thread_switch_interrupt_flag
@@ -183,3 +134,25 @@ _reswitch:
     str r1, [r2]
     bx  lr
 #endif /*RT_USING_SMP*/
+
+.global rt_hw_context_switch_exit
+rt_hw_context_switch_exit:
+
+#ifdef RT_USING_SMP
+#ifdef RT_USING_SIGNALS
+    mov     r0, sp
+    cps #Mode_IRQ
+    bl      rt_signal_check
+    cps #Mode_SVC
+    mov     sp, r0
+#endif
+#endif
+
+#ifdef RT_USING_LWP
+    ldmfd   sp, {r13, r14}^ /* usr_sp, usr_lr */
+    add     sp, #8
+#endif
+    ldmfd   sp!, {r1}
+    msr     spsr_cxsf, r1        /* original mode */
+    ldmfd   sp!, {r0-r12,lr,pc}^ /* irq return */
+
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 51026b7ed5..014846f3aa 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -11,7 +11,6 @@
  */
 
 #include "rtconfig.h"
-
 .equ Mode_USR,        0x10
 .equ Mode_FIQ,        0x11
 .equ Mode_IRQ,        0x12
@@ -158,20 +157,48 @@ vector_fiq:
 vector_irq:
 #ifdef RT_USING_SMP
     clrex
+
+    stmfd   sp!, {r0, r1}
+    cps     #Mode_SVC
+    mov     r0, sp          /* svc_sp */
+    mov     r1, lr          /* svc_lr */
+
+    cps     #Mode_IRQ
+    sub     lr, #4
+    stmfd   r0!, {r1, lr}       /* svc_lr, svc_pc */
+    stmfd   r0!, {r2 - r12}
+    ldmfd   sp!, {r1, r2}     /* original r0, r1 */
+    stmfd   r0!, {r1 - r2}
+    mrs     r1,  spsr         /* original mode */
+    stmfd   r0!, {r1}
+
+#ifdef RT_USING_LWP
+    stmfd   r0, {r13, r14}^ /* usr_sp, usr_lr */
+    sub   r0, #8
 #endif
-    stmfd   sp!, {r0-r12,lr}
+    /* now irq stack is clean */
+    /* r0 is task svc_sp */
+    /* backup r0 -> r8 */
+    mov r8, r0
 
     bl      rt_interrupt_enter
     bl      rt_hw_trap_irq
     bl      rt_interrupt_leave
 
-#ifdef RT_USING_SMP
-    mov     r0, sp
+    cps     #Mode_SVC
+    mov     sp, r8
+    mov     r0, r8
     bl      rt_scheduler_do_irq_switch
 
-    ldmfd   sp!, {r0-r12,lr}
-    subs    pc,  lr, #4
+    b       rt_hw_context_switch_exit
+
 #else
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
     @ if rt_thread_switch_interrupt_flag set, jump to
     @ rt_hw_context_switch_interrupt_do and don't return
     ldr     r0, =rt_thread_switch_interrupt_flag
diff --git a/src/scheduler.c b/src/scheduler.c
index be29d9a7e0..3da723687c 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -322,8 +322,23 @@ void rt_schedule(void)
     if (pcpu->irq_nest)
     {
         pcpu->irq_switch_flag = 1;
+        rt_hw_interrupt_enable(level);
+        goto __exit;
     }
-    else if (current_thread->scheduler_lock_nest == 1) /* whether lock scheduler */
+
+#ifdef RT_USING_SIGNALS
+    if ((current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND)
+    {
+        /* if current_thread signal is in pending */
+
+        if ((current_thread->stat & RT_THREAD_STAT_SIGNAL_MASK) & RT_THREAD_STAT_SIGNAL_PENDING)
+        {
+            rt_thread_resume(current_thread);
+        }
+    }
+#endif
+
+    if (current_thread->scheduler_lock_nest == 1) /* whether lock scheduler */
     {
         rt_ubase_t highest_ready_priority;
 
@@ -366,27 +381,32 @@ void rt_schedule(void)
                 _rt_scheduler_stack_check(to_thread);
 #endif
 
-                {
-                    extern void rt_thread_handle_sig(rt_bool_t clean_state);
-
-                    rt_hw_context_switch((rt_ubase_t)&current_thread->sp,
-                                         (rt_ubase_t)&to_thread->sp, to_thread);
-
-                    /* enable interrupt */
-                    rt_hw_interrupt_enable(level);
-
-#ifdef RT_USING_SIGNALS
-                    /* check signal status */
-                    rt_thread_handle_sig(RT_TRUE);
-#endif
-                    goto __exit;
-                }
+                rt_hw_context_switch((rt_ubase_t)&current_thread->sp,
+                        (rt_ubase_t)&to_thread->sp, to_thread);
             }
         }
     }
 
+#ifdef RT_USING_SIGNALS
+    if (current_thread->stat & RT_THREAD_STAT_SIGNAL_PENDING)
+    {
+        extern void rt_thread_handle_sig(rt_bool_t clean_state);
+
+        current_thread->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING;
+
+        rt_hw_interrupt_enable(level);
+
+        /* check signal status */
+        rt_thread_handle_sig(RT_TRUE);
+    }
+    else
+    {
+        rt_hw_interrupt_enable(level);
+    }
+#else
     /* enable interrupt */
     rt_hw_interrupt_enable(level);
+#endif
 
 __exit:
     return ;
@@ -465,13 +485,25 @@ void rt_schedule(void)
 
                     rt_hw_context_switch((rt_ubase_t)&from_thread->sp,
                             (rt_ubase_t)&to_thread->sp);
+#ifdef RT_USING_SIGNALS
+                    if (rt_current_thread->stat & RT_THREAD_STAT_SIGNAL_PENDING)
+                    {
+                        extern void rt_thread_handle_sig(rt_bool_t clean_state);
+
+                        rt_current_thread->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING;
 
+                        rt_hw_interrupt_enable(level);
+
+                        /* check signal status */
+                        rt_thread_handle_sig(RT_TRUE);
+                    }
+                    else
+                    {
+                        rt_hw_interrupt_enable(level);
+                    }
+#else
                     /* enable interrupt */
                     rt_hw_interrupt_enable(level);
-
-#ifdef RT_USING_SIGNALS
-                    /* check signal status */
-                    rt_thread_handle_sig(RT_TRUE);
 #endif
                     goto __exit;
                 }
@@ -519,6 +551,18 @@ void rt_scheduler_do_irq_switch(void *context)
     pcpu   = rt_cpu_index(cpu_id);
     current_thread = pcpu->current_thread;
 
+#ifdef RT_USING_SIGNALS
+    if ((current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND)
+    {
+        /* if current_thread signal is in pending */
+
+        if ((current_thread->stat & RT_THREAD_STAT_SIGNAL_MASK) & RT_THREAD_STAT_SIGNAL_PENDING)
+        {
+            rt_thread_resume(current_thread);
+        }
+    }
+#endif
+
     if (pcpu->irq_switch_flag == 0)
     {
         rt_hw_interrupt_enable(level);
diff --git a/src/signal.c b/src/signal.c
index 06c2055d26..0cab6215af 100644
--- a/src/signal.c
+++ b/src/signal.c
@@ -52,17 +52,27 @@ static void _signal_entry(void *parameter)
     /* handle signal */
     rt_thread_handle_sig(RT_FALSE);
 
-    /* never come back... */
-    rt_hw_interrupt_disable();
+#ifdef RT_USING_SMP
+    {
+        struct rt_cpu* pcpu = rt_cpu_self();
+
+        if (--pcpu->current_thread->cpus_lock_nest == 0)
+        {
+            pcpu->current_thread->scheduler_lock_nest--;
+        }
+
+    }
+#else
     /* return to thread */
     tid->sp = tid->sig_ret;
     tid->sig_ret = RT_NULL;
+#endif
 
     LOG_D("switch back to: 0x%08x\n", tid->sp);
     tid->stat &= ~RT_THREAD_STAT_SIGNAL;
 
 #ifdef RT_USING_SMP
-    rt_hw_context_switch_to((rt_ubase_t)&(tid->sp), tid);
+    rt_hw_context_switch_to((rt_base_t)&parameter, tid);
 #else
     rt_hw_context_switch_to((rt_ubase_t)&(tid->sp));
 #endif /*RT_USING_SMP*/
@@ -82,16 +92,21 @@ static void _signal_deliver(rt_thread_t tid)
 {
     rt_ubase_t level;
 
+    level = rt_hw_interrupt_disable();
+
     /* thread is not interested in pended signals */
-    if (!(tid->sig_pending & tid->sig_mask)) return;
+    if (!(tid->sig_pending & tid->sig_mask))
+    {
+        rt_hw_interrupt_enable(level);
+        return;
+    }
 
-    level = rt_hw_interrupt_disable();
     if ((tid->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND)
     {
         /* resume thread to handle signal */
         rt_thread_resume(tid);
         /* add signal state */
-        tid->stat |= RT_THREAD_STAT_SIGNAL;
+        tid->stat |= (RT_THREAD_STAT_SIGNAL | RT_THREAD_STAT_SIGNAL_PENDING);
 
         rt_hw_interrupt_enable(level);
 
@@ -108,17 +123,36 @@ static void _signal_deliver(rt_thread_t tid)
             rt_hw_interrupt_enable(level);
 
             /* do signal action in self thread context */
-            rt_thread_handle_sig(RT_TRUE);
+            if (rt_interrupt_get_nest() == 0)
+            {
+                rt_thread_handle_sig(RT_TRUE);
+            }
         }
         else if (!((tid->stat & RT_THREAD_STAT_SIGNAL_MASK) & RT_THREAD_STAT_SIGNAL))
         {
             /* add signal state */
-            tid->stat |= RT_THREAD_STAT_SIGNAL;
+            tid->stat |= (RT_THREAD_STAT_SIGNAL | RT_THREAD_STAT_SIGNAL_PENDING);
 
+#ifdef RT_USING_SMP
+            {
+                int cpu_id;
+
+                cpu_id = tid->oncpu;
+                if ((cpu_id != RT_CPU_DETACHED) && (cpu_id != rt_hw_cpu_id()))
+                {
+                    rt_uint32_t cpu_mask;
+
+                    cpu_mask = RT_CPU_MASK ^ (1 << cpu_id);
+                    rt_hw_ipi_send(RT_SCHEDULE_IPI, cpu_mask);
+                }
+            }
+#else
             /* point to the signal handle entry */
+            tid->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING;
             tid->sig_ret = tid->sp;
             tid->sp = rt_hw_stack_init((void *)_signal_entry, RT_NULL,
                                        (void *)((char *)tid->sig_ret - 32), RT_NULL);
+#endif
 
             rt_hw_interrupt_enable(level);
             LOG_D("signal stack pointer @ 0x%08x", tid->sp);
@@ -133,14 +167,53 @@ static void _signal_deliver(rt_thread_t tid)
     }
 }
 
+#ifdef RT_USING_SMP
+void *rt_signal_check(void* context)
+{
+    rt_base_t level;
+    int cpu_id;
+    struct rt_cpu* pcpu;
+    struct rt_thread *current_thread;
+
+    level = rt_hw_interrupt_disable();
+    cpu_id = rt_hw_cpu_id();
+    pcpu   = rt_cpu_index(cpu_id);
+    current_thread = pcpu->current_thread;
+
+    if (pcpu->irq_nest)
+    {
+        rt_hw_interrupt_enable(level);
+        return context;
+    }
+
+    if (current_thread->cpus_lock_nest == 1)
+    {
+        if (current_thread->stat & RT_THREAD_STAT_SIGNAL_PENDING)
+        {
+            void *sig_context;
+
+            current_thread->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING;
+
+            rt_hw_interrupt_enable(level);
+            sig_context = rt_hw_stack_init((void *)_signal_entry, context,
+                    (void *)(context - 32), RT_NULL);
+            return sig_context;
+        }
+    }
+    rt_hw_interrupt_enable(level);
+    return context;
+}
+#endif
+
 rt_sighandler_t rt_signal_install(int signo, rt_sighandler_t handler)
 {
+    rt_base_t level;
     rt_sighandler_t old = RT_NULL;
     rt_thread_t tid = rt_thread_self();
 
     if (!sig_valid(signo)) return SIG_ERR;
 
-    rt_enter_critical();
+    level = rt_hw_interrupt_disable();
     if (tid->sig_vectors == RT_NULL)
     {
         rt_thread_alloc_sig(tid);
@@ -154,7 +227,7 @@ rt_sighandler_t rt_signal_install(int signo, rt_sighandler_t handler)
         else if (handler == SIG_DFL) tid->sig_vectors[signo] = _signal_default_handler;
         else tid->sig_vectors[signo] = handler;
     }
-    rt_exit_critical();
+    rt_hw_interrupt_enable(level);
 
     return old;
 }
@@ -272,7 +345,20 @@ __done:
 
             LOG_D("sigwait: %d sig raised!", signo);
             if (si_prev) si_prev->list.next = si_node->list.next;
-            else tid->si_list = si_node->list.next;
+            else
+            {
+                struct siginfo_node *node_next;
+
+                if (si_node->list.next)
+                {
+                    node_next = (void *)rt_slist_entry(si_node->list.next, struct siginfo_node, list);
+                    tid->si_list = node_next;
+                }
+                else
+                {
+                    tid->si_list = RT_NULL;
+                }
+            }
 
             /* clear pending */
             tid->sig_pending &= ~sig_mask(signo);
@@ -281,7 +367,14 @@ __done:
         }
 
         si_prev = si_node;
-        si_node = (void *)rt_slist_entry(si_node->list.next, struct siginfo_node, list);
+        if (si_node->list.next)
+        {
+            si_node = (void *)rt_slist_entry(si_node->list.next, struct siginfo_node, list);
+        }
+        else
+        {
+            si_node = RT_NULL;
+        }
      }
 
 __done_int:
@@ -320,13 +413,13 @@ void rt_thread_handle_sig(rt_bool_t clean_state)
 
                 signo   = si_node->si.si_signo;
                 handler = tid->sig_vectors[signo];
+                tid->sig_pending &= ~sig_mask(signo);
                 rt_hw_interrupt_enable(level);
 
                 LOG_D("handle signal: %d, handler 0x%08x", signo, handler);
                 if (handler) handler(signo);
 
                 level = rt_hw_interrupt_disable();
-                tid->sig_pending &= ~sig_mask(signo);
                 error = -RT_EINTR;
 
                 rt_mp_free(si_node); /* release this siginfo node */
@@ -335,10 +428,16 @@ void rt_thread_handle_sig(rt_bool_t clean_state)
             }
 
             /* whether clean signal status */
-            if (clean_state == RT_TRUE) tid->stat &= ~RT_THREAD_STAT_SIGNAL;
+            if (clean_state == RT_TRUE)
+            {
+                tid->stat &= ~RT_THREAD_STAT_SIGNAL;
+            }
+            else
+            {
+                return;
+            }
         }
     }
-
     rt_hw_interrupt_enable(level);
 }
 
@@ -364,30 +463,30 @@ void rt_thread_alloc_sig(rt_thread_t tid)
 void rt_thread_free_sig(rt_thread_t tid)
 {
     rt_base_t level;
-    struct siginfo_node *si_list;
+    struct siginfo_node *si_node;
     rt_sighandler_t *sig_vectors;
 
     level = rt_hw_interrupt_disable();
-    si_list = (struct siginfo_node *)tid->si_list;
+    si_node = (struct siginfo_node *)tid->si_list;
     tid->si_list = RT_NULL;
 
     sig_vectors = tid->sig_vectors;
     tid->sig_vectors = RT_NULL;
     rt_hw_interrupt_enable(level);
 
-    if (si_list)
+    if (si_node)
     {
         struct rt_slist_node *node;
-        struct siginfo_node  *si_node;
+        struct rt_slist_node *node_to_free;
 
         LOG_D("free signal info list");
-        node = &(si_list->list);
+        node = &(si_node->list);
         do
         {
-            si_node = rt_slist_entry(node, struct siginfo_node, list);
-            rt_mp_free(si_node);
-
+            node_to_free = node;
             node = node->next;
+            si_node = rt_slist_entry(node_to_free, struct siginfo_node, list);
+            rt_mp_free(si_node);
         } while (node);
     }
 
@@ -418,30 +517,23 @@ int rt_thread_kill(rt_thread_t tid, int sig)
         struct rt_slist_node *node;
         struct siginfo_node  *entry;
 
-        node = (struct rt_slist_node *)tid->si_list;
-        rt_hw_interrupt_enable(level);
+        si_node = (struct siginfo_node *)tid->si_list;
+        if (si_node)
+            node = (struct rt_slist_node *)&si_node->list;
+        else
+            node = RT_NULL;
 
         /* update sig info */
-        rt_enter_critical();
         for (; (node) != RT_NULL; node = node->next)
         {
             entry = rt_slist_entry(node, struct siginfo_node, list);
             if (entry->si.si_signo == sig)
             {
                 memcpy(&(entry->si), &si, sizeof(siginfo_t));
-                rt_exit_critical();
+                rt_hw_interrupt_enable(level);
                 return 0;
             }
         }
-        rt_exit_critical();
-
-        /* disable interrupt to protect tcb */
-        level = rt_hw_interrupt_disable();
-    }
-    else
-    {
-        /* a new signal */
-        tid->sig_pending |= sig_mask(sig);
     }
     rt_hw_interrupt_enable(level);
 
@@ -452,14 +544,22 @@ int rt_thread_kill(rt_thread_t tid, int sig)
         memcpy(&(si_node->si), &si, sizeof(siginfo_t));
 
         level = rt_hw_interrupt_disable();
-        if (!tid->si_list) tid->si_list = si_node;
-        else
+
+        if (tid->si_list)
         {
             struct siginfo_node *si_list;
 
             si_list = (struct siginfo_node *)tid->si_list;
             rt_slist_append(&(si_list->list), &(si_node->list));
         }
+        else
+        {
+            tid->si_list = si_node;
+        }
+
+        /* a new signal */
+        tid->sig_pending |= sig_mask(sig);
+
         rt_hw_interrupt_enable(level);
     }
     else
diff --git a/src/thread.c b/src/thread.c
index 0f2e1dc3d0..276bba9938 100644
--- a/src/thread.c
+++ b/src/thread.c
@@ -191,7 +191,9 @@ static rt_err_t _rt_thread_init(struct rt_thread *thread,
     thread->sig_mask    = 0x00;
     thread->sig_pending = 0x00;
 
+#ifndef RT_USING_SMP
     thread->sig_ret     = RT_NULL;
+#endif
     thread->sig_vectors = RT_NULL;
     thread->si_list     = RT_NULL;
 #endif
-- 
cgit v1.3.1


From bcb7fac0d0dd5b06d1fbc0b046883068b70f0e23 Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Sat, 11 May 2019 09:00:15 +0800
Subject: fix signals for k210

---
 bsp/k210/rtconfig.py               |   2 +-
 libcpu/risc-v/common/context_gcc.S | 126 +++++++++----------------------------
 libcpu/risc-v/k210/interrupt_gcc.S |  57 +++--------------
 3 files changed, 42 insertions(+), 143 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/k210/rtconfig.py b/bsp/k210/rtconfig.py
index 47ee1cc932..b9258cd374 100755
--- a/bsp/k210/rtconfig.py
+++ b/bsp/k210/rtconfig.py
@@ -15,7 +15,7 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM    = 'gcc'
-    EXEC_PATH   = r'/opt/riscv64-unknown-elf/bin'
+    EXEC_PATH   = r'/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin'
 else:
     print('Please make sure your toolchains is GNU GCC!')
     exit(0)
diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S
index 62e64d8104..f28b15319b 100644
--- a/libcpu/risc-v/common/context_gcc.S
+++ b/libcpu/risc-v/common/context_gcc.S
@@ -49,45 +49,9 @@ rt_hw_context_switch_to:
     mv   a0,   a1
     jal  rt_cpus_lock_status_restore
 #endif
-
-    /* load epc from stack */
-    LOAD a0,   0 * REGBYTES(sp)
-    csrw mepc, a0
-    LOAD x1,   1 * REGBYTES(sp)
-    /* load mstatus from stack */
     LOAD a0,   2 * REGBYTES(sp)
     csrw mstatus, a0
-    LOAD x4,   4 * REGBYTES(sp)
-    LOAD x5,   5 * REGBYTES(sp)
-    LOAD x6,   6 * REGBYTES(sp)
-    LOAD x7,   7 * REGBYTES(sp)
-    LOAD x8,   8 * REGBYTES(sp)
-    LOAD x9,   9 * REGBYTES(sp)
-    LOAD x10, 10 * REGBYTES(sp)
-    LOAD x11, 11 * REGBYTES(sp)
-    LOAD x12, 12 * REGBYTES(sp)
-    LOAD x13, 13 * REGBYTES(sp)
-    LOAD x14, 14 * REGBYTES(sp)
-    LOAD x15, 15 * REGBYTES(sp)
-    LOAD x16, 16 * REGBYTES(sp)
-    LOAD x17, 17 * REGBYTES(sp)
-    LOAD x18, 18 * REGBYTES(sp)
-    LOAD x19, 19 * REGBYTES(sp)
-    LOAD x20, 20 * REGBYTES(sp)
-    LOAD x21, 21 * REGBYTES(sp)
-    LOAD x22, 22 * REGBYTES(sp)
-    LOAD x23, 23 * REGBYTES(sp)
-    LOAD x24, 24 * REGBYTES(sp)
-    LOAD x25, 25 * REGBYTES(sp)
-    LOAD x26, 26 * REGBYTES(sp)
-    LOAD x27, 27 * REGBYTES(sp)
-    LOAD x28, 28 * REGBYTES(sp)
-    LOAD x29, 29 * REGBYTES(sp)
-    LOAD x30, 30 * REGBYTES(sp)
-    LOAD x31, 31 * REGBYTES(sp)
-
-    addi sp,  sp, 32 * REGBYTES
-    mret
+    j    rt_hw_context_switch_exit
 
 /*
  * #ifdef RT_USING_SMP
@@ -102,7 +66,6 @@ rt_hw_context_switch_to:
  */
     .globl rt_hw_context_switch
 rt_hw_context_switch:
-
     /* saved from thread context
      *     x1/ra       -> sp(0)
      *     x1/ra       -> sp(1)
@@ -163,48 +126,7 @@ save_mpie:
     jal  rt_cpus_lock_status_restore
 #endif /*RT_USING_SMP*/
 
-    /* resw ra to mepc */
-    LOAD a1,   0 * REGBYTES(sp)
-    csrw mepc, a1
-    LOAD x1,   1 * REGBYTES(sp)
-
-    /* force to machin mode(MPP=11) */
-    li a1, 0x00001800;
-    csrs mstatus, a1
-    LOAD a1,   2 * REGBYTES(sp)
-    csrs mstatus, a1
-
-    LOAD x4,   4 * REGBYTES(sp)
-    LOAD x5,   5 * REGBYTES(sp)
-    LOAD x6,   6 * REGBYTES(sp)
-    LOAD x7,   7 * REGBYTES(sp)
-    LOAD x8,   8 * REGBYTES(sp)
-    LOAD x9,   9 * REGBYTES(sp)
-    LOAD x10, 10 * REGBYTES(sp)
-    LOAD x11, 11 * REGBYTES(sp)
-    LOAD x12, 12 * REGBYTES(sp)
-    LOAD x13, 13 * REGBYTES(sp)
-    LOAD x14, 14 * REGBYTES(sp)
-    LOAD x15, 15 * REGBYTES(sp)
-    LOAD x16, 16 * REGBYTES(sp)
-    LOAD x17, 17 * REGBYTES(sp)
-    LOAD x18, 18 * REGBYTES(sp)
-    LOAD x19, 19 * REGBYTES(sp)
-    LOAD x20, 20 * REGBYTES(sp)
-    LOAD x21, 21 * REGBYTES(sp)
-    LOAD x22, 22 * REGBYTES(sp)
-    LOAD x23, 23 * REGBYTES(sp)
-    LOAD x24, 24 * REGBYTES(sp)
-    LOAD x25, 25 * REGBYTES(sp)
-    LOAD x26, 26 * REGBYTES(sp)
-    LOAD x27, 27 * REGBYTES(sp)
-    LOAD x28, 28 * REGBYTES(sp)
-    LOAD x29, 29 * REGBYTES(sp)
-    LOAD x30, 30 * REGBYTES(sp)
-    LOAD x31, 31 * REGBYTES(sp)
-
-    addi sp,  sp, 32 * REGBYTES
-    mret
+    j rt_hw_context_switch_exit
 
 #ifdef RT_USING_SMP
 /*
@@ -220,26 +142,42 @@ rt_hw_context_switch_interrupt:
 
     STORE a0, 0(a1)
 
-    csrr  a1, mepc
-    STORE a1, 0 * REGBYTES(a0)
-
-    csrr  a1, mstatus
-    STORE a1, 2 * REGBYTES(a0)
-
     LOAD  sp, 0(a2)
     move  a0, a3
     call rt_cpus_lock_status_restore
 
+    j rt_hw_context_switch_exit
+
+#endif
+
+.global rt_hw_context_switch_exit
+rt_hw_context_switch_exit:
+#ifdef RT_USING_SMP
+#ifdef RT_USING_SIGNALS
+    mv a0, sp
+
+    csrr  t0, mhartid
+    /* switch interrupt stack of current cpu */
+    la    sp, __stack_start__
+    addi  t1, t0, 1
+    li    t2, __STACKSIZE__
+    mul   t1, t1, t2
+    add   sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
+
+    call rt_signal_check
+    mv sp, a0
+#endif
+#endif
     /* resw ra to mepc */
-    LOAD a1,   0 * REGBYTES(sp)
-    csrw mepc, a1
+    LOAD a0,   0 * REGBYTES(sp)
+    csrw mepc, a0
+
     LOAD x1,   1 * REGBYTES(sp)
 
-    /* force to machin mode(MPP=11) */
-    li a1, 0x00001800;
-    csrs mstatus, a1
-    LOAD a1,   2 * REGBYTES(sp)
-    csrs mstatus, a1
+    li    t0, 0x00001800
+    csrs  mstatus, t0
+    LOAD a0,   2 * REGBYTES(sp)
+    csrs mstatus, a0
 
     LOAD x4,   4 * REGBYTES(sp)
     LOAD x5,   5 * REGBYTES(sp)
@@ -272,5 +210,3 @@ rt_hw_context_switch_interrupt:
 
     addi sp,  sp, 32 * REGBYTES
     mret
-
-#endif
diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S
index aeda72ab31..0393ea51f8 100644
--- a/libcpu/risc-v/k210/interrupt_gcc.S
+++ b/libcpu/risc-v/k210/interrupt_gcc.S
@@ -20,8 +20,12 @@ trap_entry:
     addi sp, sp, -32 * REGBYTES
 
     STORE x1,   1 * REGBYTES(sp)
-    li    t0,   0x80
-    STORE t0,   2 * REGBYTES(sp)
+
+    csrr  x1, mstatus
+    STORE x1,   2 * REGBYTES(sp)
+
+    csrr  x1, mepc
+    STORE x1, 0 * REGBYTES(sp)
 
     STORE x4,   4 * REGBYTES(sp)
     STORE x5,   5 * REGBYTES(sp)
@@ -75,9 +79,11 @@ trap_entry:
 
 #ifdef RT_USING_SMP
     /* s0 --> sp */
+    mv  sp, s0
     mv  a0, s0
     call rt_scheduler_do_irq_switch
-    mv  sp, s0
+    j   rt_hw_context_switch_exit
+
 #else
 
     /* switch to from_thread stack */
@@ -89,9 +95,6 @@ trap_entry:
     beqz  s2, spurious_interrupt
     sw    zero, 0(s0)
 
-    csrr  a0, mepc
-    STORE a0, 0 * REGBYTES(sp)
-
     la    s0, rt_interrupt_from_thread
     LOAD  s1, 0(s0)
     STORE sp, 0(s1)
@@ -100,47 +103,7 @@ trap_entry:
     LOAD  s1, 0(s0)
     LOAD  sp, 0(s1)
 
-    LOAD  a0,  0 * REGBYTES(sp)
-    csrw  mepc, a0
 #endif
 
 spurious_interrupt:
-    LOAD  x1,   1 * REGBYTES(sp)
-
-    /* Remain in M-mode after mret */
-    li    t0, 0x00001800
-    csrs  mstatus, t0
-    LOAD  t0,   2 * REGBYTES(sp)
-    csrs  mstatus, t0 
-
-    LOAD  x4,   4 * REGBYTES(sp)
-    LOAD  x5,   5 * REGBYTES(sp)
-    LOAD  x6,   6 * REGBYTES(sp)
-    LOAD  x7,   7 * REGBYTES(sp)
-    LOAD  x8,   8 * REGBYTES(sp)
-    LOAD  x9,   9 * REGBYTES(sp)
-    LOAD  x10, 10 * REGBYTES(sp)
-    LOAD  x11, 11 * REGBYTES(sp)
-    LOAD  x12, 12 * REGBYTES(sp)
-    LOAD  x13, 13 * REGBYTES(sp)
-    LOAD  x14, 14 * REGBYTES(sp)
-    LOAD  x15, 15 * REGBYTES(sp)
-    LOAD  x16, 16 * REGBYTES(sp)
-    LOAD  x17, 17 * REGBYTES(sp)
-    LOAD  x18, 18 * REGBYTES(sp)
-    LOAD  x19, 19 * REGBYTES(sp)
-    LOAD  x20, 20 * REGBYTES(sp)
-    LOAD  x21, 21 * REGBYTES(sp)
-    LOAD  x22, 22 * REGBYTES(sp)
-    LOAD  x23, 23 * REGBYTES(sp)
-    LOAD  x24, 24 * REGBYTES(sp)
-    LOAD  x25, 25 * REGBYTES(sp)
-    LOAD  x26, 26 * REGBYTES(sp)
-    LOAD  x27, 27 * REGBYTES(sp)
-    LOAD  x28, 28 * REGBYTES(sp)
-    LOAD  x29, 29 * REGBYTES(sp)
-    LOAD  x30, 30 * REGBYTES(sp)
-    LOAD  x31, 31 * REGBYTES(sp)
-
-    addi  sp, sp, 32 * REGBYTES
-    mret
+    j rt_hw_context_switch_exit
-- 
cgit v1.3.1


From ec6cb9f2602c11a676b059c8f23401422690227c Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Sun, 12 May 2019 15:07:26 +0800
Subject: [BSP][qemu-vexpress-a9] code cleaup for compiling warning.

---
 bsp/qemu-vexpress-a9/drivers/drv_sdio.c      | 5 +----
 bsp/qemu-vexpress-a9/drivers/secondary_cpu.c | 2 ++
 components/drivers/sdio/sd.c                 | 2 +-
 libcpu/arm/cortex-a/interrupt.h              | 2 ++
 4 files changed, 6 insertions(+), 5 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/qemu-vexpress-a9/drivers/drv_sdio.c b/bsp/qemu-vexpress-a9/drivers/drv_sdio.c
index 1ecd147289..2628222627 100644
--- a/bsp/qemu-vexpress-a9/drivers/drv_sdio.c
+++ b/bsp/qemu-vexpress-a9/drivers/drv_sdio.c
@@ -440,14 +440,11 @@ int pl180_init(void)
     sdhci->priv = pdat;
     write32(pdat->virt + PL180_POWER, 0xbf);
 
-    // rt_kprintf("power:0x%08x\n", read32(pdat->virt + PL180_POWER));
-
     host->ops = &ops;
     host->freq_min = 400000;
     host->freq_max = 50000000;
     host->valid_ocr = VDD_32_33 | VDD_33_34;
-    // host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
-    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
+    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
     host->max_seg_size = 2048;
     host->max_dma_segs = 10;
     host->max_blk_size = 512;
diff --git a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c
index 29bb9ec895..9221ecee87 100644
--- a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c
+++ b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c
@@ -17,6 +17,8 @@
 #include "drv_timer.h"
 
 #ifdef RT_USING_SMP
+#include <interrupt.h>
+
 static void rt_hw_timer2_isr(int vector, void *param)
 {
     rt_tick_increase();
diff --git a/components/drivers/sdio/sd.c b/components/drivers/sdio/sd.c
index 3e7ad1cd16..183eba169d 100644
--- a/components/drivers/sdio/sd.c
+++ b/components/drivers/sdio/sd.c
@@ -264,7 +264,7 @@ static rt_int32_t mmcsd_switch(struct rt_mmcsd_card *card)
 
     if ((buf[16] & 0xF) != 1) 
     {
-        LOG_E("switching card to high speed failed!");
+        LOG_I("switching card to high speed failed!");
         goto err;
     }
 
diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h
index 31f79cc66e..442187edee 100644
--- a/libcpu/arm/cortex-a/interrupt.h
+++ b/libcpu/arm/cortex-a/interrupt.h
@@ -17,6 +17,8 @@
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
+void rt_hw_vector_init(void);
+
 void rt_hw_interrupt_control(int vector, int priority, int route);
 
 void rt_hw_interrupt_init(void);
-- 
cgit v1.3.1


From 257d21c0bdc78d87ed7a30f9b3577ceaf247fdff Mon Sep 17 00:00:00 2001
From: neal <pin001@163.com>
Date: Sun, 12 May 2019 23:17:27 -0700
Subject: [bsp][at91sam9g45]Fix build bugs which caused by the change of
 libcpu/arm/arm926/start_gcc.S

---
 bsp/allwinner_tina/libcpu/interrupt.c           |  3 ++-
 bsp/at91sam9g45/drivers/board.c                 |  4 ++--
 bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld |  8 ++++----
 bsp/at91sam9g45/platform/interrupt.c            | 25 ++++++++++++++++++++++++-
 bsp/at91sam9g45/rtconfig.py                     |  2 +-
 libcpu/arm/arm926/trap.c                        |  6 +++---
 6 files changed, 36 insertions(+), 12 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/allwinner_tina/libcpu/interrupt.c b/bsp/allwinner_tina/libcpu/interrupt.c
index b32a331c60..14f53b6881 100644
--- a/bsp/allwinner_tina/libcpu/interrupt.c
+++ b/bsp/allwinner_tina/libcpu/interrupt.c
@@ -102,6 +102,7 @@ void rt_hw_interrupt_mask(int vector)
 }
 
 /**
+
  * This function will un-mask a interrupt.
  * @param vector the interrupt number
  */
@@ -167,7 +168,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
     return old_handler;
 }
 
-void rt_interrupt_dispatch(void)
+void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
 {
     void *param;
     int vector;
diff --git a/bsp/at91sam9g45/drivers/board.c b/bsp/at91sam9g45/drivers/board.c
index c14055f310..59ac3f1ba4 100644
--- a/bsp/at91sam9g45/drivers/board.c
+++ b/bsp/at91sam9g45/drivers/board.c
@@ -36,8 +36,8 @@
 extern int Image$$ER_ZI$$ZI$$Limit;
 #define HEAP_BEGIN  (&Image$$ER_ZI$$ZI$$Limit)
 #elif (defined (__GNUC__))
-extern unsigned char __bss_end__;
-#define HEAP_BEGIN  (&__bss_end__)
+extern unsigned char __bss_end;
+#define HEAP_BEGIN  (&__bss_end)
 #elif (defined (__ICCARM__))
 #pragma section=".noinit"
 #define HEAP_BEGIN  (__section_end(".noinit"))
diff --git a/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld
index a0dd88e868..ca159b7cd4 100644
--- a/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld
+++ b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld
@@ -1,6 +1,6 @@
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
-ENTRY(start)
+ENTRY(system_vectors)
 SECTIONS
 {
     . = 0x70000000;
@@ -8,7 +8,7 @@ SECTIONS
     . = ALIGN(4);
     .text : 
     {
-        *(.init)
+        *(.vectors)
         *(.text)
         *(.gnu.linkonce.t*)
         
@@ -76,9 +76,9 @@ SECTIONS
     .nobss : { *(.nobss) }
     
     . = ALIGN(4);
-    __bss_start__ = .;
+    __bss_start = .;
     .bss : { *(.bss)}
-    __bss_end__ = .;
+    __bss_end = .;
 
     /* stabs debugging sections. */
     .stab 0 : { *(.stab) }
diff --git a/bsp/at91sam9g45/platform/interrupt.c b/bsp/at91sam9g45/platform/interrupt.c
index b19bcb3bde..9f7cabf3f8 100644
--- a/bsp/at91sam9g45/platform/interrupt.c
+++ b/bsp/at91sam9g45/platform/interrupt.c
@@ -332,7 +332,7 @@ void rt_hw_interrupt_umask(int irq)
  * @return old handler
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                    void *param, char *name)
+                                    void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 
@@ -419,6 +419,29 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
     AT91C_BASE_AIC->AIC_EOICR = 0x0;
 }
 
+void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
+{
+    rt_isr_handler_t isr_func;
+    rt_uint32_t irq;
+    void *param;
+
+    /* get irq number */
+    irq = rt_hw_interrupt_get_active(fiq_irq);
+
+    /* get interrupt service routine */
+    isr_func = irq_desc[irq].handler;
+    param = irq_desc[irq].param;
+
+    /* turn to interrupt service routine */
+    isr_func(irq, param);
+
+    rt_hw_interrupt_ack(fiq_irq, irq);
+#ifdef RT_USING_INTERRUPT_INFO
+    irq_desc[irq].counter ++;
+#endif
+}
+
+
 #ifdef RT_USING_FINSH
 #ifdef RT_USING_INTERRUPT_INFO
 void list_irq(void)
diff --git a/bsp/at91sam9g45/rtconfig.py b/bsp/at91sam9g45/rtconfig.py
index 3684b54578..bd29b56f4f 100644
--- a/bsp/at91sam9g45/rtconfig.py
+++ b/bsp/at91sam9g45/rtconfig.py
@@ -10,7 +10,7 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
 	PLATFORM 	= 'gcc'
-	EXEC_PATH = r'D:\arm-2013.11\bin'
+	EXEC_PATH = '/usr/bin'
 elif CROSS_TOOL == 'keil':
 	PLATFORM 	= 'armcc'
 	EXEC_PATH 	= 'C:/Keil_v5'
diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c
index de04c3f8cb..9e7ba48037 100644
--- a/libcpu/arm/arm926/trap.c
+++ b/libcpu/arm/arm926/trap.c
@@ -197,14 +197,14 @@ void rt_hw_trap_resv(struct rt_hw_register *regs)
     rt_hw_cpu_shutdown();
 }
 
-extern void rt_interrupt_dispatch(void);
+extern void rt_interrupt_dispatch(rt_uint32_t fiq_irq);
 
 void rt_hw_trap_irq(void)
 {
-    rt_interrupt_dispatch();
+    rt_interrupt_dispatch(INT_IRQ);
 }
 
 void rt_hw_trap_fiq(void)
 {
-    rt_interrupt_dispatch();
+    rt_interrupt_dispatch(INT_FIQ);
 }
-- 
cgit v1.3.1


From 36ffdc058b3aeb447d74dd916c26e1dd80b80def Mon Sep 17 00:00:00 2001
From: HubretXie <xiexianbin@gmail.com>
Date: Tue, 28 May 2019 21:30:45 +0800
Subject: 对CM3,CM4,CM7  自动开启RT_USING_CPU_FFS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'libcpu')

diff --git a/libcpu/Kconfig b/libcpu/Kconfig
index 239fa58346..3c8c73636d 100644
--- a/libcpu/Kconfig
+++ b/libcpu/Kconfig
@@ -4,6 +4,10 @@ config ARCH_CPU_64BIT
 config ARCH_ARM
     bool
 
+config RT_USING_CPU_FFS
+    bool
+    default n
+
 config ARCH_ARM_CORTEX_M
     bool
     select ARCH_ARM
@@ -18,6 +22,7 @@ config ARCH_ARM_CORTEX_M0
 config ARCH_ARM_CORTEX_M3
     bool
     select ARCH_ARM_CORTEX_M
+    select RT_USING_CPU_FFS
 
 config ARCH_ARM_MPU
     bool
@@ -26,10 +31,12 @@ config ARCH_ARM_MPU
 config ARCH_ARM_CORTEX_M4
     bool
     select ARCH_ARM_CORTEX_M
+    select RT_USING_CPU_FFS
 
 config ARCH_ARM_CORTEX_M7
     bool
     select ARCH_ARM_CORTEX_M
+    select RT_USING_CPU_FFS
 
 config ARCH_ARM_CORTEX_R
     bool
-- 
cgit v1.3.1


From 043611b98aca955e9cb511c51baf7240389fba75 Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Wed, 29 May 2019 08:26:08 +0800
Subject: add cortex-a fpu support

---
 libcpu/arm/cortex-a/context_gcc.S | 24 ++++++++++++++
 libcpu/arm/cortex-a/stack.c       |  3 ++
 libcpu/arm/cortex-a/start_gcc.S   | 70 +++++++++++++++++++++++++++++++++++++++
 libcpu/arm/cortex-a/trap.c        | 33 ++++++++++++++++++
 4 files changed, 130 insertions(+)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S
index dff7a1de68..768c5138e9 100644
--- a/libcpu/arm/cortex-a/context_gcc.S
+++ b/libcpu/arm/cortex-a/context_gcc.S
@@ -76,6 +76,18 @@ rt_hw_context_switch:
     stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
     sub sp, #8
 #endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
 
     str sp, [r0]            @ store sp in preempted tasks TCB
     ldr sp, [r1]            @ get new task stack pointer
@@ -147,6 +159,18 @@ rt_hw_context_switch_exit:
     mov     sp, r0
 #endif
 #endif
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+1:
+#endif
 
 #ifdef RT_USING_LWP
     ldmfd   sp, {r13, r14}^ /* usr_sp, usr_lr */
diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c
index d76b8a428a..07d795ab5b 100644
--- a/libcpu/arm/cortex-a/stack.c
+++ b/libcpu/arm/cortex-a/stack.c
@@ -60,6 +60,9 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     *(--stk) = 0;       /* user lr */
     *(--stk) = 0;       /* user sp*/
 #endif
+#ifdef RT_USING_FPU
+    *(--stk) = 0;       /* not use fpu*/
+#endif
 
     /* return task's current stack address */
     return (rt_uint8_t *)stk;
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 014846f3aa..91faa0e3ff 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -22,7 +22,11 @@
 .equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
 .equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
 
+#ifdef RT_USING_FPU
+.equ UND_Stack_Size,     0x00000400
+#else
 .equ UND_Stack_Size,     0x00000000
+#endif
 .equ SVC_Stack_Size,     0x00000400
 .equ ABT_Stack_Size,     0x00000000
 .equ RT_FIQ_STACK_PGSZ,  0x00000000
@@ -50,6 +54,11 @@ _reset:
     /* set the cpu to SVC32 mode and disable interrupt */
     cps #Mode_SVC
 
+#ifdef RT_USING_FPU
+    mov r4, #0xfffffff
+    mcr p15, 0, r4, c1, c0, 2
+#endif
+
     /* disable the data alignment check */
     mrc p15, 0, r1, c1, c0, 0
     bic r1, #(1<<1)
@@ -176,6 +185,19 @@ vector_irq:
     stmfd   r0, {r13, r14}^ /* usr_sp, usr_lr */
     sub   r0, #8
 #endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb r0!, {d0-d15}
+    vstmdb r0!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd r0!, {r5}
+1:
+    stmfd r0!, {r6}
+#endif
+
     /* now irq stack is clean */
     /* r0 is task svc_sp */
     /* backup r0 -> r8 */
@@ -234,6 +256,18 @@ rt_hw_context_switch_interrupt_do:
     stmfd sp, {r13, r14}^  @push usr_sp, usr_lr
     sub sp, #8
 #endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
 
     ldr     r4,  =rt_interrupt_from_thread
     ldr     r5,  [r4]
@@ -243,6 +277,19 @@ rt_hw_context_switch_interrupt_do:
     ldr     r6,  [r6]
     ldr     sp,  [r6]       @ get new task's stack pointer
 
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+1:
+#endif
+
 #ifdef RT_USING_LWP
     ldmfd sp, {r13, r14}^  @pop usr_sp, usr_lr
     add sp, #8
@@ -278,7 +325,14 @@ vector_swi:
     .globl  vector_undef
 vector_undef:
     push_svc_reg
+    cps #Mode_UND
     bl      rt_hw_trap_undef
+#ifdef RT_USING_FPU
+    ldr     lr, [sp, #15*4]
+    ldmia   sp, {r0 - r12}
+    add     sp, sp, #17 * 4
+    movs    pc, lr
+#endif
     b       .
 
     .align  5
@@ -315,6 +369,12 @@ set_secondary_cpu_boot_address:
 
 .global secondary_cpu_start
 secondary_cpu_start:
+
+#ifdef RT_USING_FPU
+    mov r4, #0xfffffff
+    mcr p15, 0, r4, c1, c0, 2
+#endif
+
     mrc p15, 0, r1, c1, c0, 1
     mov r0, #(1<<6)
     orr r1, r0
@@ -324,6 +384,11 @@ secondary_cpu_start:
     bic r0, #(1<<13)
     mcr p15, 0, r0, c1, c0, 0
 
+#ifdef RT_USING_FPU
+    cps #Mode_UND
+    ldr sp, =und_stack_2_limit
+#endif
+
     cps #Mode_IRQ
     ldr sp, =irq_stack_2_limit
 
@@ -349,3 +414,8 @@ irq_stack_2:
     .space (1 << 10)
 irq_stack_2_limit:
 
+#ifdef RT_USING_FPU
+und_stack_2:
+    .space (1 << 10)
+und_stack_2_limit:
+#endif
diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c
index a25f6ac862..dc232a46ee 100644
--- a/libcpu/arm/cortex-a/trap.c
+++ b/libcpu/arm/cortex-a/trap.c
@@ -45,6 +45,39 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
  */
 void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
 {
+#ifdef RT_USING_FPU
+    {
+        uint32_t ins;
+        uint32_t addr;
+
+        if (regs->cpsr & (1 << 5))
+        {
+            /* thumb mode */
+            addr = regs->pc - 2;
+            ins = (uint32_t)*(uint16_t*)addr;
+            if ((ins & (3 << 11)) != 0)
+            {
+                /* 32 bit ins */
+                ins <<= 16;
+                ins += *(uint16_t*)(addr + 2);
+            }
+        }
+        else
+        {
+            addr = regs->pc - 4;
+            ins = *(uint32_t*)addr;
+        }
+        if ((ins & 0xe00) == 0xa00)
+        {
+            /* float ins */
+            uint32_t val = (1U << 30);
+
+            asm volatile ("vmsr fpexc, %0"::"r"(val):"memory");
+            regs->pc = addr;
+            return;
+        }
+    }
+#endif
     rt_kprintf("undefined instruction:\n");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-- 
cgit v1.3.1


From 21d32cdb3abe15f495b88cfaa18e1441357137ed Mon Sep 17 00:00:00 2001
From: 明德无敌赵晓薇 <1755923166@qq.com>
Date: Tue, 18 Jun 2019 20:59:00 +0800
Subject: [libcpu][C28x] Fix bugs of old c28x interrupt api which can not save
 and restore int status

In C28x DSP, interrupt status are stored in ST1 register. Both INTM and DBGM is used for masking interrupt, while the latter one is used in real-time debug mode. The origin function rudely enable and disable the interrupt without considering the recent interrupt status, which not only may cause  problem in some situation but also is not in conformity with rt-thread design specifications. The new api will fix this bug.
---
 libcpu/ti-dsp/c28x/context.s | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/ti-dsp/c28x/context.s b/libcpu/ti-dsp/c28x/context.s
index 2b853a0075..f0555d6d35 100644
--- a/libcpu/ti-dsp/c28x/context.s
+++ b/libcpu/ti-dsp/c28x/context.s
@@ -73,7 +73,9 @@ RT_CTX_RESTORE  .macro
 ;
     .asmfunc
 _rt_hw_interrupt_disable:
-    DINT
+    PUSH  ST1
+    SETC  INTM,DBGM
+    MOV   AL, *--SP
     LRETR
     .endasmfunc
 
@@ -82,7 +84,8 @@ _rt_hw_interrupt_disable:
 ;
     .asmfunc
 _rt_hw_interrupt_enable:
-    EINT
+    MOV   *SP++, AL
+    POP   ST1
     LRETR
     .endasmfunc
     
-- 
cgit v1.3.1


From fc155f88107ca347fb2d306793476786e544f993 Mon Sep 17 00:00:00 2001
From: ZYH <lymz@foxmail.com>
Date: Wed, 19 Jun 2019 10:29:56 +0800
Subject: fix cortex-a cahce

---
 libcpu/arm/cortex-a/cache.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c
index 6d28d9e9f9..30af86baa1 100644
--- a/libcpu/arm/cortex-a/cache.c
+++ b/libcpu/arm/cortex-a/cache.c
@@ -30,6 +30,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size)
     rt_uint32_t start_addr = (rt_uint32_t)addr;
     rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
 
+    asm volatile ("dmb":::"memory");
     start_addr &= ~(line_size-1);
     end_addr &= ~(line_size-1);
     while (start_addr < end_addr)
@@ -37,6 +38,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size)
         asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr));  /* icimvau */
         start_addr += line_size;
     }
+    asm volatile ("dsb\n\tisb":::"memory");
 }
 
 void rt_hw_cpu_dcache_invalidate(void *addr, int size)
@@ -45,6 +47,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
     rt_uint32_t start_addr = (rt_uint32_t)addr;
     rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
 
+    asm volatile ("dmb":::"memory");
     start_addr &= ~(line_size-1);
     end_addr &= ~(line_size-1);
     while (start_addr < end_addr)
@@ -52,6 +55,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
         asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr));  /* dcimvac */
         start_addr += line_size;
     }
+    asm volatile ("dsb":::"memory");
 }
 
 void rt_hw_cpu_dcache_clean(void *addr, int size)
@@ -60,6 +64,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
     rt_uint32_t start_addr = (rt_uint32_t)addr;
     rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
 
+    asm volatile ("dmb":::"memory");
     start_addr &= ~(line_size-1);
     end_addr &= ~(line_size-1);
     while (start_addr < end_addr)
@@ -67,6 +72,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
         asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */
         start_addr += line_size;
     }
+    asm volatile ("dsb":::"memory");
 }
 
 void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
-- 
cgit v1.3.1


From 31ffc4582c04b4ff5e59404b06d1e52d4b5cff63 Mon Sep 17 00:00:00 2001
From: yangjie <yangjiexaut@126.com>
Date: Wed, 3 Jul 2019 18:47:11 +0800
Subject: [libcpu/arm]add __rt_ffs() for armclang in CORTEX M3/4/7

---
 libcpu/arm/cortex-m3/cpuport.c | 20 ++++++++++++++++++++
 libcpu/arm/cortex-m4/cpuport.c | 22 +++++++++++++++++++++-
 libcpu/arm/cortex-m7/cpuport.c | 22 +++++++++++++++++++++-
 3 files changed, 62 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c
index a386747750..0a948c528b 100644
--- a/libcpu/arm/cortex-m3/cpuport.c
+++ b/libcpu/arm/cortex-m3/cpuport.c
@@ -11,6 +11,7 @@
  * 2012-12-23   aozima      stack addr align to 8byte.
  * 2012-12-29   Bernard     Add exception hook.
  * 2013-07-09   aozima      enhancement hard fault exception handler.
+ * 2019-07-03   yangjie     add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -382,6 +383,25 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     exit                 \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "exit:                        \n"
+        "BX      lr                   \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c
index 18f027895b..71a7fb16f9 100644
--- a/libcpu/arm/cortex-m4/cpuport.c
+++ b/libcpu/arm/cortex-m4/cpuport.c
@@ -14,6 +14,7 @@
  * 2012-12-29     Bernard      Add exception hook.
  * 2013-06-23     aozima       support lazy stack optimized.
  * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -453,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
  * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
-#if defined(__CC_ARM) || defined(__CLANG_ARM)
+#if defined(__CC_ARM) 
 __asm int __rt_ffs(int value)
 {
     CMP     r0, #0x00
@@ -466,6 +467,25 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     exit                 \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "exit:                        \n"
+        "BX      lr                   \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c
index 18f027895b..85960baede 100644
--- a/libcpu/arm/cortex-m7/cpuport.c
+++ b/libcpu/arm/cortex-m7/cpuport.c
@@ -14,6 +14,7 @@
  * 2012-12-29     Bernard      Add exception hook.
  * 2013-06-23     aozima       support lazy stack optimized.
  * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -453,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
  * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
-#if defined(__CC_ARM) || defined(__CLANG_ARM)
+#if defined(__CC_ARM)
 __asm int __rt_ffs(int value)
 {
     CMP     r0, #0x00
@@ -466,6 +467,25 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     exit                 \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "exit:                        \n"
+        "BX      lr                   \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
-- 
cgit v1.3.1


From d68220d8667462339640cfda2f3d80484bd1f8db Mon Sep 17 00:00:00 2001
From: 明德无敌赵晓薇 <1755923166@qq.com>
Date: Wed, 3 Jul 2019 19:31:54 +0800
Subject: [libcpu][c28x]Add __rt_ffs support

Use a native instruction "Count Sign Bits" to support fast ffs function, then add __rt_ffs support in C28x.
---
 libcpu/ti-dsp/c28x/context.s | 22 ++++++++++++++++++++++
 libcpu/ti-dsp/c28x/cpuport.c | 15 +++++++++++++++
 2 files changed, 37 insertions(+)

(limited to 'libcpu')

diff --git a/libcpu/ti-dsp/c28x/context.s b/libcpu/ti-dsp/c28x/context.s
index f0555d6d35..f21e0ddb6e 100644
--- a/libcpu/ti-dsp/c28x/context.s
+++ b/libcpu/ti-dsp/c28x/context.s
@@ -6,6 +6,8 @@
 ; Change Logs:
 ; Date           Author       Notes
 ; 2018-09-01     xuzhuoyi     the first version.
+; 2019-06-17     zhaoxiaowei  fix bugs of old c28x interrupt api.
+; 2019-07-03     zhaoxiaowei  add _rt_hw_calc_csb function to support __rt_ffs.
 ;
 
     .ref   _rt_interrupt_to_thread
@@ -15,6 +17,7 @@
     .def   _RTOSINT_Handler
     .def   _rt_hw_get_st0
     .def   _rt_hw_get_st1
+    .def   _rt_hw_calc_csb
     .def   _rt_hw_context_switch_interrupt
     .def   _rt_hw_context_switch
     .def   _rt_hw_context_switch_to
@@ -229,6 +232,25 @@ _rt_hw_get_st1:
     LRETR
     .endasmfunc
 
+; C28x do not have a build-in "__ffs" func in its C compiler.
+; We can use the "Count Sign Bits" (CSB) instruction to make one.
+; CSB will return the number of 0's minus 1 above the highest set bit.
+; The count is placed in T. For example:
+;    ACC        T     maxbit
+; 0x00000001    30      0
+; 0x00000010    26      4
+; 0x000001FF    22      8
+; 0x000001F0    22      8
+    .asmfunc
+_rt_hw_calc_csb:
+    MOV     AH, #0
+    CSB     ACC                   ; T = no. of sign bits - 1
+    MOVU    ACC, T                ; ACC = no. of sign bits - 1
+    SUBB    ACC, #30              ; ACC = ACC - 30
+    ABS     ACC                   ; ACC = |ACC|
+    lretr
+    .endasmfunc
+
 ;
 ; * void rt_hw_context_switch_to(rt_uint32 to);
 ; * r0 --> to
diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c
index 2d42884bed..e34556c524 100644
--- a/libcpu/ti-dsp/c28x/cpuport.c
+++ b/libcpu/ti-dsp/c28x/cpuport.c
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-09-01     xuzhuoyi     the first version.
+ * 2019-07-03     zhaoxiaowei  add support for __rt_ffs.
  */
 
 #include <rtthread.h>
@@ -19,6 +20,7 @@ static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
 
 extern rt_uint16_t rt_hw_get_st0(void);
 extern rt_uint16_t rt_hw_get_st1(void);
+extern int rt_hw_calc_csb(int value);
 
 struct exception_stack_frame
 {
@@ -102,6 +104,19 @@ struct exception_info
     struct stack_frame stack_frame;
 };
 
+#ifdef RT_USING_CPU_FFS
+/*
+ * This function called rt_hw_calc_csb to finds the first bit set in value.
+ * rt_hw_calc_csb is a native assembly program that use "CSB" instruction in C28x.
+ * When you use this function, remember that "int" is only 16-bit in C28x's C compiler.
+ * If value is a number bigger that 0xFFFF, trouble may be caused.
+ * Maybe change "int __rt_ffs(int value)" to "rt_int32_t __rt_ffs(rt_int32_t value)" will be better.
+ */
+int __rt_ffs(int value)
+{
+    return rt_hw_calc_csb(value);
+}
+#endif
 
 /**
  * shutdown CPU
-- 
cgit v1.3.1


From d6b2f56f150b014d8c9595ce68bbd98e45c0ed1c Mon Sep 17 00:00:00 2001
From: Zhou Yanjie <zhouyanjie@zoho.com>
Date: Fri, 19 Jul 2019 20:46:06 +0800
Subject: libcpu: MIPS: 清理代码/Clean up code.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

清理内容重复的头文件。

Clean up duplicate header files.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 bsp/pic32ethernet/project.cbp         | 2 +-
 libcpu/mips/loongson_1b/cache_gcc.S   | 7 ++++++-
 libcpu/mips/loongson_1b/context_gcc.S | 6 +++++-
 libcpu/mips/loongson_1b/start_gcc.S   | 6 +++++-
 libcpu/mips/loongson_1c/cache_gcc.S   | 7 ++++++-
 libcpu/mips/loongson_1c/context_gcc.S | 6 +++++-
 libcpu/mips/loongson_1c/start_gcc.S   | 6 +++++-
 libcpu/mips/pic32/context_gcc.S       | 6 +++++-
 libcpu/mips/x1000/mips_cache_gcc.S    | 2 +-
 libcpu/mips/x1000/mips_context_gcc.S  | 2 +-
 libcpu/mips/x1000/mips_excpt_gcc.S    | 2 +-
 libcpu/mips/x1000/mips_fp_gcc.S       | 2 +-
 libcpu/mips/x1000/startup_gcc.S       | 2 +-
 libcpu/mips/xburst/cache_gcc.S        | 7 ++++++-
 libcpu/mips/xburst/context_gcc.S      | 7 ++++++-
 libcpu/mips/xburst/start_gcc.S        | 6 +++++-
 16 files changed, 60 insertions(+), 16 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/pic32ethernet/project.cbp b/bsp/pic32ethernet/project.cbp
index ad51307464..b03c35100d 100644
--- a/bsp/pic32ethernet/project.cbp
+++ b/bsp/pic32ethernet/project.cbp
@@ -376,7 +376,7 @@
 		</Unit>
 		<Unit filename="..\..\libcpu\mips\common\cache.h" />
 		<Unit filename="..\..\libcpu\mips\common\exception.h" />
-		<Unit filename="..\..\libcpu\mips\common\mips.inc" />
+		<Unit filename="..\..\libcpu\mips\common\mips_def.h" />
 		<Unit filename="..\..\libcpu\mips\common\mipscfg.h" />
 		<Unit filename="..\..\libcpu\mips\common\mipsregs.h" />
 		<Unit filename="..\..\libcpu\mips\common\stackframe.h" />
diff --git a/libcpu/mips/loongson_1b/cache_gcc.S b/libcpu/mips/loongson_1b/cache_gcc.S
index bb6f46de4c..bd4759f2b9 100644
--- a/libcpu/mips/loongson_1b/cache_gcc.S
+++ b/libcpu/mips/loongson_1b/cache_gcc.S
@@ -13,8 +13,13 @@
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
  */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
 #include "../common/mipsregs.h"
-#include "../common/mips.inc"
+#include "../common/mips_def.h"
 #include "../common/asm.h"
 #include "cache.h"
 
diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S
index ce004dc716..be06538bd5 100644
--- a/libcpu/mips/loongson_1b/context_gcc.S
+++ b/libcpu/mips/loongson_1b/context_gcc.S
@@ -14,7 +14,11 @@
  * 2011-08-08     lgnq         port to Loongson LS1B
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 
     .section ".text", "ax"
diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S
index fd98335671..4b2aad1e2e 100644
--- a/libcpu/mips/loongson_1b/start_gcc.S
+++ b/libcpu/mips/loongson_1b/start_gcc.S
@@ -13,7 +13,11 @@
  * 2010-09-04     bernard      porting to Jz47xx
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 
 	.section ".start", "ax"
diff --git a/libcpu/mips/loongson_1c/cache_gcc.S b/libcpu/mips/loongson_1c/cache_gcc.S
index af25c31ded..c8f570e529 100644
--- a/libcpu/mips/loongson_1c/cache_gcc.S
+++ b/libcpu/mips/loongson_1c/cache_gcc.S
@@ -14,8 +14,13 @@
  * 2011-08-08     lgnq         port to Loongson LS1B
  * 2015-07-08     chinesebear  port to Loongson LS1C
  */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
 #include "../common/mipsregs.h"
-#include "../common/mips.inc"
+#include "../common/mips_def.h"
 #include "../common/asm.h"
 #include "cache.h"
 
diff --git a/libcpu/mips/loongson_1c/context_gcc.S b/libcpu/mips/loongson_1c/context_gcc.S
index fbffd34866..934d5f44a9 100644
--- a/libcpu/mips/loongson_1c/context_gcc.S
+++ b/libcpu/mips/loongson_1c/context_gcc.S
@@ -14,7 +14,11 @@
  * 2011-08-08     lgnq         port to Loongson LS1B
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 #include "stackframe_fpu.h"
 
diff --git a/libcpu/mips/loongson_1c/start_gcc.S b/libcpu/mips/loongson_1c/start_gcc.S
index 4e71bc0524..a0a8f9ec72 100644
--- a/libcpu/mips/loongson_1c/start_gcc.S
+++ b/libcpu/mips/loongson_1c/start_gcc.S
@@ -13,7 +13,11 @@
  * 2010-09-04     bernard      porting to Jz47xx
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 #include "sdram_cfg.h"
 #include "cache.h"
diff --git a/libcpu/mips/pic32/context_gcc.S b/libcpu/mips/pic32/context_gcc.S
index 3e820fb9d8..283c86f1cd 100644
--- a/libcpu/mips/pic32/context_gcc.S
+++ b/libcpu/mips/pic32/context_gcc.S
@@ -1,5 +1,9 @@
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
 #include <p32xxxx.h>
-#include "../common/mips.inc"
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 
     .section ".text", "ax"
diff --git a/libcpu/mips/x1000/mips_cache_gcc.S b/libcpu/mips/x1000/mips_cache_gcc.S
index 671f193af0..50f2245638 100644
--- a/libcpu/mips/x1000/mips_cache_gcc.S
+++ b/libcpu/mips/x1000/mips_cache_gcc.S
@@ -23,7 +23,7 @@
  */
 
 #ifndef __ASSEMBLY__
-#	define	__ASSEMBLY__
+#define	__ASSEMBLY__
 #endif
 
 #include "../common/mips.h"
diff --git a/libcpu/mips/x1000/mips_context_gcc.S b/libcpu/mips/x1000/mips_context_gcc.S
index d4c314ab65..10ddc30c5c 100644
--- a/libcpu/mips/x1000/mips_context_gcc.S
+++ b/libcpu/mips/x1000/mips_context_gcc.S
@@ -23,7 +23,7 @@
  */
 
 #ifndef __ASSEMBLY__
-#	define __ASSEMBLY__
+#define __ASSEMBLY__
 #endif
 
 #include "../common/mips.h"
diff --git a/libcpu/mips/x1000/mips_excpt_gcc.S b/libcpu/mips/x1000/mips_excpt_gcc.S
index c403adf93b..ae9344b40f 100644
--- a/libcpu/mips/x1000/mips_excpt_gcc.S
+++ b/libcpu/mips/x1000/mips_excpt_gcc.S
@@ -23,7 +23,7 @@
  */
 
 #ifndef __ASSEMBLY__
-#	define __ASSEMBLY__
+#define __ASSEMBLY__
 #endif
 
 #include "../common/mips.h"
diff --git a/libcpu/mips/x1000/mips_fp_gcc.S b/libcpu/mips/x1000/mips_fp_gcc.S
index b219084065..3210c1b545 100644
--- a/libcpu/mips/x1000/mips_fp_gcc.S
+++ b/libcpu/mips/x1000/mips_fp_gcc.S
@@ -23,7 +23,7 @@
  */
 
 #ifndef __ASSEMBLY__
-#	define __ASSEMBLY__
+#define __ASSEMBLY__
 #endif
 
 #ifdef __mips_hard_float
diff --git a/libcpu/mips/x1000/startup_gcc.S b/libcpu/mips/x1000/startup_gcc.S
index 1376cb7dd4..05b782364b 100644
--- a/libcpu/mips/x1000/startup_gcc.S
+++ b/libcpu/mips/x1000/startup_gcc.S
@@ -23,7 +23,7 @@
  */
 
 #ifndef __ASSEMBLY__
-#	define __ASSEMBLY__
+#define __ASSEMBLY__
 #endif
 
 #include "../common/mips.h"
diff --git a/libcpu/mips/xburst/cache_gcc.S b/libcpu/mips/xburst/cache_gcc.S
index 76552698d0..c55dff20cd 100644
--- a/libcpu/mips/xburst/cache_gcc.S
+++ b/libcpu/mips/xburst/cache_gcc.S
@@ -4,7 +4,12 @@
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  */
-#include "../common/mips.inc"
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/mipsregs.h"
 #include "../common/stackframe.h"
 
diff --git a/libcpu/mips/xburst/context_gcc.S b/libcpu/mips/xburst/context_gcc.S
index d018de3da8..270501d387 100644
--- a/libcpu/mips/xburst/context_gcc.S
+++ b/libcpu/mips/xburst/context_gcc.S
@@ -5,7 +5,12 @@
  * 2010-05-17     swkyer       first version
  * 2010-09-11     bernard      port to Jz4755
  */
-#include "../common/mips.inc"
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 #include "stack.h"
 
diff --git a/libcpu/mips/xburst/start_gcc.S b/libcpu/mips/xburst/start_gcc.S
index 322c2beae8..52aa4a6cca 100644
--- a/libcpu/mips/xburst/start_gcc.S
+++ b/libcpu/mips/xburst/start_gcc.S
@@ -6,7 +6,11 @@
  * 2010-09-04     bernard      porting to Jz47xx
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 #include "stack.h"
 
-- 
cgit v1.3.1


From d45efced1c934ace5540fc80fd9951aea556b15a Mon Sep 17 00:00:00 2001
From: Zhou Yanjie <zhouyanjie@zoho.com>
Date: Fri, 19 Jul 2019 20:54:36 +0800
Subject: libcpu: MIPS: 更新版权信息/Update copyright information.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

更新版权信息。

Update copyright information.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 libcpu/mips/common/mips.h             | 20 +++-----------------
 libcpu/mips/common/mips_def.h         | 20 +++-----------------
 libcpu/mips/loongson_1b/cache_gcc.S   |  9 +++------
 libcpu/mips/loongson_1b/context_gcc.S |  9 +++------
 libcpu/mips/loongson_1b/start_gcc.S   |  9 +++------
 libcpu/mips/loongson_1c/cache_gcc.S   |  9 +++------
 libcpu/mips/loongson_1c/context_gcc.S |  9 +++------
 libcpu/mips/loongson_1c/start_gcc.S   | 11 ++++-------
 libcpu/mips/pic32/context_gcc.S       | 11 +++++++++++
 libcpu/mips/x1000/mips_cache_gcc.S    | 20 +++-----------------
 libcpu/mips/x1000/mips_context_gcc.S  | 20 +++-----------------
 libcpu/mips/x1000/mips_excpt_gcc.S    | 20 +++-----------------
 libcpu/mips/x1000/mips_fp_gcc.S       | 20 +++-----------------
 libcpu/mips/x1000/startup_gcc.S       | 20 +++-----------------
 libcpu/mips/xburst/cache_gcc.S        |  6 +++++-
 libcpu/mips/xburst/context_gcc.S      |  8 ++++++--
 libcpu/mips/xburst/start_gcc.S        |  8 ++++++--
 17 files changed, 68 insertions(+), 161 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h
index 6a9811ae7e..a4bc74a050 100644
--- a/libcpu/mips/common/mips.h
+++ b/libcpu/mips/common/mips.h
@@ -1,25 +1,11 @@
 /*
- * File      : mips.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef _COMMON_MIPS_H_
diff --git a/libcpu/mips/common/mips_def.h b/libcpu/mips/common/mips_def.h
index 70da2deccf..1727684f50 100644
--- a/libcpu/mips/common/mips_def.h
+++ b/libcpu/mips/common/mips_def.h
@@ -1,25 +1,11 @@
 /*
- * File      : mips_def.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef _COMMON_MIPS_DEF_H_
diff --git a/libcpu/mips/loongson_1b/cache_gcc.S b/libcpu/mips/loongson_1b/cache_gcc.S
index bd4759f2b9..1e718c9883 100644
--- a/libcpu/mips/loongson_1b/cache_gcc.S
+++ b/libcpu/mips/loongson_1b/cache_gcc.S
@@ -1,17 +1,14 @@
 /*
- * File      : cache_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S
index be06538bd5..bed2c13252 100644
--- a/libcpu/mips/loongson_1b/context_gcc.S
+++ b/libcpu/mips/loongson_1b/context_gcc.S
@@ -1,17 +1,14 @@
 /*
- * File      : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S
index 4b2aad1e2e..f54fbb9a1d 100644
--- a/libcpu/mips/loongson_1b/start_gcc.S
+++ b/libcpu/mips/loongson_1b/start_gcc.S
@@ -1,16 +1,13 @@
 /*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-04     bernard      porting to Jz47xx
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/loongson_1c/cache_gcc.S b/libcpu/mips/loongson_1c/cache_gcc.S
index c8f570e529..649a88b67b 100644
--- a/libcpu/mips/loongson_1c/cache_gcc.S
+++ b/libcpu/mips/loongson_1c/cache_gcc.S
@@ -1,11 +1,7 @@
 /*
- * File      : cache_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -13,6 +9,7 @@
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
  * 2015-07-08     chinesebear  port to Loongson LS1C
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/loongson_1c/context_gcc.S b/libcpu/mips/loongson_1c/context_gcc.S
index 934d5f44a9..53bce723e7 100644
--- a/libcpu/mips/loongson_1c/context_gcc.S
+++ b/libcpu/mips/loongson_1c/context_gcc.S
@@ -1,17 +1,14 @@
 /*
- * File      : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/loongson_1c/start_gcc.S b/libcpu/mips/loongson_1c/start_gcc.S
index a0a8f9ec72..1d13ef7f0f 100644
--- a/libcpu/mips/loongson_1c/start_gcc.S
+++ b/libcpu/mips/loongson_1c/start_gcc.S
@@ -1,16 +1,13 @@
 /*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
+ * 2010-09-04     bernard      porting to JZ47xx
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/pic32/context_gcc.S b/libcpu/mips/pic32/context_gcc.S
index 283c86f1cd..bd46dffdc7 100644
--- a/libcpu/mips/pic32/context_gcc.S
+++ b/libcpu/mips/pic32/context_gcc.S
@@ -1,3 +1,14 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-24     aozima       first version
+ * 2019-07-19     Zhou Yanjie  clean up code
+ */
+
 #ifndef __ASSEMBLY__
 #define __ASSEMBLY__
 #endif
diff --git a/libcpu/mips/x1000/mips_cache_gcc.S b/libcpu/mips/x1000/mips_cache_gcc.S
index 50f2245638..cc69cba1a6 100644
--- a/libcpu/mips/x1000/mips_cache_gcc.S
+++ b/libcpu/mips/x1000/mips_cache_gcc.S
@@ -1,25 +1,11 @@
 /*
- * File      : mips_cache_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��19��     Urey         the first version
+ * 2016-09-19     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/x1000/mips_context_gcc.S b/libcpu/mips/x1000/mips_context_gcc.S
index 10ddc30c5c..5cb473a72a 100644
--- a/libcpu/mips/x1000/mips_context_gcc.S
+++ b/libcpu/mips/x1000/mips_context_gcc.S
@@ -1,25 +1,11 @@
 /*
- * File      : mips_context_asm.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/x1000/mips_excpt_gcc.S b/libcpu/mips/x1000/mips_excpt_gcc.S
index ae9344b40f..bca6fd1956 100644
--- a/libcpu/mips/x1000/mips_excpt_gcc.S
+++ b/libcpu/mips/x1000/mips_excpt_gcc.S
@@ -1,25 +1,11 @@
 /*
- * File      : mips_excpt_asm.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/x1000/mips_fp_gcc.S b/libcpu/mips/x1000/mips_fp_gcc.S
index 3210c1b545..303519afe4 100644
--- a/libcpu/mips/x1000/mips_fp_gcc.S
+++ b/libcpu/mips/x1000/mips_fp_gcc.S
@@ -1,25 +1,11 @@
 /*
- * File      : mips_vfp32_asm.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��9��     Urey         the first version
+ * 2016-09-09     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/x1000/startup_gcc.S b/libcpu/mips/x1000/startup_gcc.S
index 05b782364b..c5112614fc 100644
--- a/libcpu/mips/x1000/startup_gcc.S
+++ b/libcpu/mips/x1000/startup_gcc.S
@@ -1,25 +1,11 @@
 /*
- * File      : startup.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/xburst/cache_gcc.S b/libcpu/mips/xburst/cache_gcc.S
index c55dff20cd..a8d215764c 100644
--- a/libcpu/mips/xburst/cache_gcc.S
+++ b/libcpu/mips/xburst/cache_gcc.S
@@ -1,8 +1,12 @@
 /*
- * File      : cache_init.S
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/xburst/context_gcc.S b/libcpu/mips/xburst/context_gcc.S
index 270501d387..a44d3bdcc7 100644
--- a/libcpu/mips/xburst/context_gcc.S
+++ b/libcpu/mips/xburst/context_gcc.S
@@ -1,9 +1,13 @@
 /*
- * File      : context_gcc.S
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Jz4755
+ * 2010-09-11     bernard      port to JZ4755
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
diff --git a/libcpu/mips/xburst/start_gcc.S b/libcpu/mips/xburst/start_gcc.S
index 52aa4a6cca..da8bfa9251 100644
--- a/libcpu/mips/xburst/start_gcc.S
+++ b/libcpu/mips/xburst/start_gcc.S
@@ -1,9 +1,13 @@
 /*
- * File      : start_gcc.S
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
+ * 2010-09-04     bernard      porting to JZ47xx
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
 #ifndef __ASSEMBLY__
-- 
cgit v1.3.1


From 49e9d19c82a345633a7b0a95b4997c448d3e6609 Mon Sep 17 00:00:00 2001
From: tyustli <1225613647@qq.com>
Date: Wed, 24 Jul 2019 17:03:26 +0800
Subject: first version

---
 bsp/gd32vf103v-eval/.cproject                      |  205 ++
 bsp/gd32vf103v-eval/.gitignore                     |    1 +
 bsp/gd32vf103v-eval/.project                       |   88 +
 .../ilg.gnumcueclipse.debug.gdbjtag.openocd.prefs  |    2 +
 .../ilg.gnumcueclipse.managedbuild.cross.prefs     |    2 +
 ...lg.gnumcueclipse.managedbuild.cross.riscv.prefs |    2 +
 .../.settings/language.settings.xml                |   14 +
 bsp/gd32vf103v-eval/Kconfig                        |   20 +
 bsp/gd32vf103v-eval/README.md                      |  185 ++
 bsp/gd32vf103v-eval/SConscript                     |   18 +
 bsp/gd32vf103v-eval/SConstruct                     |   30 +
 bsp/gd32vf103v-eval/applications/SConscript        |   11 +
 bsp/gd32vf103v-eval/applications/main.c            |   19 +
 bsp/gd32vf103v-eval/board/Kconfig                  |   34 +
 bsp/gd32vf103v-eval/board/SConscript               |   11 +
 bsp/gd32vf103v-eval/board/board.c                  |   68 +
 bsp/gd32vf103v-eval/board/board.h                  |   25 +
 bsp/gd32vf103v-eval/board/gd32vf103_libopt.h       |   64 +
 bsp/gd32vf103v-eval/drivers/SConscript             |   19 +
 bsp/gd32vf103v-eval/drivers/drv_usart.c            |  243 +++
 bsp/gd32vf103v-eval/drivers/drv_usart.h            |   12 +
 .../Include/gd32vf103_adc.h                        |  396 ++++
 .../Include/gd32vf103_bkp.h                        |  227 +++
 .../Include/gd32vf103_can.h                        |  717 +++++++
 .../Include/gd32vf103_crc.h                        |   78 +
 .../Include/gd32vf103_dac.h                        |  242 +++
 .../Include/gd32vf103_dbg.h                        |  109 ++
 .../Include/gd32vf103_dma.h                        |  282 +++
 .../Include/gd32vf103_eclic.h                      |   62 +
 .../Include/gd32vf103_exmc.h                       |  126 ++
 .../Include/gd32vf103_exti.h                       |  244 +++
 .../Include/gd32vf103_fmc.h                        |  311 ++++
 .../Include/gd32vf103_fwdgt.h                      |  104 ++
 .../Include/gd32vf103_gpio.h                       |  423 +++++
 .../Include/gd32vf103_i2c.h                        |  342 ++++
 .../Include/gd32vf103_pmu.h                        |  125 ++
 .../Include/gd32vf103_rcu.h                        |  720 +++++++
 .../Include/gd32vf103_rtc.h                        |  148 ++
 .../Include/gd32vf103_spi.h                        |  341 ++++
 .../Include/gd32vf103_timer.h                      |  722 +++++++
 .../Include/gd32vf103_usart.h                      |  374 ++++
 .../Include/gd32vf103_wwdgt.h                      |   86 +
 .../Source/gd32vf103_adc.c                         |  992 ++++++++++
 .../Source/gd32vf103_bkp.c                         |  292 +++
 .../Source/gd32vf103_can.c                         |  989 ++++++++++
 .../Source/gd32vf103_crc.c                         |  127 ++
 .../Source/gd32vf103_dac.c                         |  537 ++++++
 .../Source/gd32vf103_dbg.c                         |  110 ++
 .../Source/gd32vf103_dma.c                         |  731 ++++++++
 .../Source/gd32vf103_eclic.c                       |   99 +
 .../Source/gd32vf103_exmc.c                        |  164 ++
 .../Source/gd32vf103_exti.c                        |  252 +++
 .../Source/gd32vf103_fmc.c                         |  649 +++++++
 .../Source/gd32vf103_fwdgt.c                       |  151 ++
 .../Source/gd32vf103_gpio.c                        |  503 +++++
 .../Source/gd32vf103_i2c.c                         |  726 ++++++++
 .../Source/gd32vf103_pmu.c                         |  270 +++
 .../Source/gd32vf103_rcu.c                         | 1111 +++++++++++
 .../Source/gd32vf103_rtc.c                         |  273 +++
 .../Source/gd32vf103_spi.c                         |  766 ++++++++
 .../Source/gd32vf103_timer.c                       | 1965 ++++++++++++++++++++
 .../Source/gd32vf103_usart.c                       |  764 ++++++++
 .../Source/gd32vf103_wwdgt.c                       |  146 ++
 .../GD32VF103_standard_peripheral/gd32vf103.h      |  230 +++
 .../system_gd32vf103.c                             |  998 ++++++++++
 .../system_gd32vf103.h                             |   60 +
 .../libraries/n22/drivers/core_v5.h                |  127 ++
 .../libraries/n22/drivers/n22_eclic.h              |   47 +
 .../libraries/n22/drivers/n22_func.c               |  279 +++
 .../libraries/n22/drivers/n22_func.h               |   82 +
 .../libraries/n22/drivers/n22_tmr.h                |   17 +
 .../libraries/n22/drivers/riscv_bits.h             |   36 +
 .../libraries/n22/drivers/riscv_const.h            |   18 +
 .../libraries/n22/drivers/riscv_encoding.h         | 1342 +++++++++++++
 .../libraries/n22/drivers/sections.h               |   17 +
 .../libraries/n22/env_Eclipse/GD32VF103x4.lds      |  175 ++
 .../libraries/n22/env_Eclipse/GD32VF103x6.lds      |  175 ++
 .../libraries/n22/env_Eclipse/GD32VF103x8.lds      |  175 ++
 .../libraries/n22/env_Eclipse/GD32VF103xB.lds      |  199 ++
 .../libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds  |  182 ++
 .../libraries/n22/env_Eclipse/entry.S              |  204 ++
 .../libraries/n22/env_Eclipse/handlers.c           |   24 +
 .../libraries/n22/env_Eclipse/init.c               |   28 +
 .../libraries/n22/env_Eclipse/start.S              |  247 +++
 bsp/gd32vf103v-eval/libraries/n22/stubs/_exit.c    |   17 +
 bsp/gd32vf103v-eval/libraries/n22/stubs/close.c    |    8 +
 bsp/gd32vf103v-eval/libraries/n22/stubs/fstat.c    |   16 +
 bsp/gd32vf103v-eval/libraries/n22/stubs/isatty.c   |   10 +
 bsp/gd32vf103v-eval/libraries/n22/stubs/lseek.c    |   13 +
 bsp/gd32vf103v-eval/libraries/n22/stubs/read.c     |   31 +
 bsp/gd32vf103v-eval/libraries/n22/stubs/sbrk.c     |   19 +
 bsp/gd32vf103v-eval/libraries/n22/stubs/stub.h     |   15 +
 bsp/gd32vf103v-eval/libraries/n22/stubs/write.c    |   45 +
 .../libraries/n22/stubs/write_hex.c                |   17 +
 .../libraries/n22/tools/openocd_upload.sh          |    5 +
 bsp/gd32vf103v-eval/rtconfig.h                     |  171 ++
 bsp/gd32vf103v-eval/rtconfig.py                    |   63 +
 libcpu/risc-v/bumblebee/SConscript                 |   14 +
 libcpu/risc-v/bumblebee/interrupt_gcc.S            |  129 ++
 99 files changed, 24104 insertions(+)
 create mode 100644 bsp/gd32vf103v-eval/.cproject
 create mode 100644 bsp/gd32vf103v-eval/.gitignore
 create mode 100644 bsp/gd32vf103v-eval/.project
 create mode 100644 bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.debug.gdbjtag.openocd.prefs
 create mode 100644 bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.managedbuild.cross.prefs
 create mode 100644 bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs
 create mode 100644 bsp/gd32vf103v-eval/.settings/language.settings.xml
 create mode 100644 bsp/gd32vf103v-eval/Kconfig
 create mode 100644 bsp/gd32vf103v-eval/README.md
 create mode 100644 bsp/gd32vf103v-eval/SConscript
 create mode 100644 bsp/gd32vf103v-eval/SConstruct
 create mode 100644 bsp/gd32vf103v-eval/applications/SConscript
 create mode 100644 bsp/gd32vf103v-eval/applications/main.c
 create mode 100644 bsp/gd32vf103v-eval/board/Kconfig
 create mode 100644 bsp/gd32vf103v-eval/board/SConscript
 create mode 100644 bsp/gd32vf103v-eval/board/board.c
 create mode 100644 bsp/gd32vf103v-eval/board/board.h
 create mode 100644 bsp/gd32vf103v-eval/board/gd32vf103_libopt.h
 create mode 100644 bsp/gd32vf103v-eval/drivers/SConscript
 create mode 100644 bsp/gd32vf103v-eval/drivers/drv_usart.c
 create mode 100644 bsp/gd32vf103v-eval/drivers/drv_usart.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_can.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_can.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/gd32vf103.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/core_v5.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/n22_eclic.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/n22_tmr.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_bits.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_const.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_encoding.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/drivers/sections.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/entry.S
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/handlers.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/init.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/start.S
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/_exit.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/close.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/fstat.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/isatty.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/lseek.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/read.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/sbrk.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/stub.h
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/write.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/stubs/write_hex.c
 create mode 100644 bsp/gd32vf103v-eval/libraries/n22/tools/openocd_upload.sh
 create mode 100644 bsp/gd32vf103v-eval/rtconfig.h
 create mode 100644 bsp/gd32vf103v-eval/rtconfig.py
 create mode 100644 libcpu/risc-v/bumblebee/SConscript
 create mode 100644 libcpu/risc-v/bumblebee/interrupt_gcc.S

(limited to 'libcpu')

diff --git a/bsp/gd32vf103v-eval/.cproject b/bsp/gd32vf103v-eval/.cproject
new file mode 100644
index 0000000000..aea4ab4f37
--- /dev/null
+++ b/bsp/gd32vf103v-eval/.cproject
@@ -0,0 +1,205 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326" moduleId="org.eclipse.cdt.core.settings" name="GD32VF103xB">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326" name="GD32VF103xB" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
+					<folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326." name="/" resourcePath="">
+						<toolChain errorParsers="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.debug.2046554316" name="RISC-V Cross GCC" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.debug">
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+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.652943790" name="GNU RISC-V Cross C++ Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.177215711"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.152259553" name="GNU RISC-V Cross C Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.607423220"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.1329800486" name="GNU RISC-V Cross C++ Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.1762099292"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1318851383" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.228826367"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.406723166" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1681627356"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.85513256" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1458513031"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.514060807" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.1188837593"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="GD32V103V_EVAL.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.756742950" name="Executable" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1542802236;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1542802236.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1471375400;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1349005409">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.488215038;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.888297046">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="GD32VF103xB">
+			<resource resourceType="PROJECT" workspacePath="/GD32V103V_EVAL"/>
+		</configuration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>
diff --git a/bsp/gd32vf103v-eval/.gitignore b/bsp/gd32vf103v-eval/.gitignore
new file mode 100644
index 0000000000..69c708b7c7
--- /dev/null
+++ b/bsp/gd32vf103v-eval/.gitignore
@@ -0,0 +1 @@
+/GD32VF103xB/
diff --git a/bsp/gd32vf103v-eval/.project b/bsp/gd32vf103v-eval/.project
new file mode 100644
index 0000000000..ee79a7f74b
--- /dev/null
+++ b/bsp/gd32vf103v-eval/.project
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>GD32V103V_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>rt-thread</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/components</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/include</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/include</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/lipcpu</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/src</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/src</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/components/drivers</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/components/finsh</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/finsh</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/components/src</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/drivers/src</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/lipcpu/bumblebee</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/libcpu/risc-v/bumblebee</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/lipcpu/common</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/libcpu/risc-v/common</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/components/drivers/include</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/drivers/include</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/components/drivers/serial</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components/drivers/serial</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.debug.gdbjtag.openocd.prefs b/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.debug.gdbjtag.openocd.prefs
new file mode 100644
index 0000000000..4405a95acf
--- /dev/null
+++ b/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.debug.gdbjtag.openocd.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+install.folder=E\:\\GD32\\GD32VF103\\GD32VF103SDK\\GDM32501_SDK\\IDE\\eclipse_toolchain\\openocd\\0.10.0-12-20190618-0815\\bin
diff --git a/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.managedbuild.cross.prefs b/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.managedbuild.cross.prefs
new file mode 100644
index 0000000000..ad2ccabb4b
--- /dev/null
+++ b/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.managedbuild.cross.prefs
@@ -0,0 +1,2 @@
+buildTools.path=E\:\\GD32\\GD32VF103\\GD32VF103SDK\\GDM32501_SDK\\IDE\\eclipse_toolchain\\BuildTools\\2.10-20180103-1919\\bin
+eclipse.preferences.version=1
diff --git a/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs b/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs
new file mode 100644
index 0000000000..85f8498577
--- /dev/null
+++ b/bsp/gd32vf103v-eval/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.512258282=E\:\\GD32\\GD32VF103\\GD32VF103SDK\\GDM32501_SDK\\IDE\\eclipse_toolchain\\RISC-VEmbeddedGCC\\riscv64-unknown-elf-gcc-8.2.0-2019.02.0-x86_64-w64-mingw32\\bin
diff --git a/bsp/gd32vf103v-eval/.settings/language.settings.xml b/bsp/gd32vf103v-eval/.settings/language.settings.xml
new file mode 100644
index 0000000000..931634b7b0
--- /dev/null
+++ b/bsp/gd32vf103v-eval/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1573373326" name="GD32VF103xB">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1826576228655354303" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/bsp/gd32vf103v-eval/Kconfig b/bsp/gd32vf103v-eval/Kconfig
new file mode 100644
index 0000000000..223a0f5bec
--- /dev/null
+++ b/bsp/gd32vf103v-eval/Kconfig
@@ -0,0 +1,20 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+ 
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/gd32vf103v-eval/README.md b/bsp/gd32vf103v-eval/README.md
new file mode 100644
index 0000000000..7c65c15b78
--- /dev/null
+++ b/bsp/gd32vf103v-eval/README.md
@@ -0,0 +1,185 @@
+# HIFIVE1 #
+
+## 简介
+
+[HIFIVE1](https://www.sifive.com/products/hifive1/) 是由 SiFive 公司推出的全球首款基于开源指令集 RISC-V 架构的商用 SoC Freedom E310 的开发板。
+
+![1538284005769](figures/board.png)
+
+
+
+### 板载资源：
+
+| 硬件 | 描述 |
+| -- | -- |
+|Soc| SiFive Freedom E310 (FE310) |
+| 内核    | SiFive E31 RISC-V Core                                      |
+| 架构       |  32-bit RV32IMAC                                         |
+| 主频       | 320+ MHz                                              |
+| 性能 | 1.61 DMIPs/MHz, 2.73 Coremark/MHz            |
+|SRAM| 16KB |
+|Flash| 16MB QSPI + 16KB 指令Cache |
+
+## 编译说明
+
+### 下载 Freedom Studio
+
+Freedom Studio 是 SiFive 公司推出的一个集成开发环境，用来编写和调试基于 SiFive 处理器的软件。内嵌了编译好的 RISC-V GCC 工具链、OpenOCD、以及一些示例和文档。
+
+下载地址：[官网下载](https://www.sifive.com/products/tools/)
+
+![1538295358180](figures/dowmload.png)
+
+下载成功之后，解压到和 rt-thread 源码同一目录下
+
+![1538295750998](figures/untar.png)
+
+### 配置工具链
+
+工具链就在解压开的 IDE  `F:\FreedomStudio\SiFive\riscv64-unknown-elf-gcc-20171231-x86_64-w64-mingw32\bin` 目录下。
+
+在源码  `rt-thread/bsp/hifive1/` 目录下，运行 env 工具，输入下面的命令设置 gcc 工具链路径
+
+```
+set RTT_EXEC_PATH=F:\FreedomStudio\SiFive\riscv64-unknown-elf-gcc-20171231-x86_64-w64-mingw32\bin
+```
+
+### 添加环境变量
+
+将 **工具链**和**编译工具**的路径 添加到环境变量里，输入命令如下
+
+```
+set path=%path%;工具链的路径;编译工具的路径;
+```
+
+例如：
+
+```
+set path=%path%;F:\FreedomStudio\SiFive\riscv64-unknown-elf-gcc-20171231-x86_64-w64-mingw32\bin;F:\FreedomStudio\build-tools\bin
+```
+
+![1538296570129](figures/env.png)
+
+### 从 env 工具打开 IDE
+
+利用 cd 命令，切换到解压开的 IDE 目录
+
+![1538296766437](figures/cd.png)
+
+输入 Freedom Studio 按 Tab 键 自动补全，然后按回车运行 IDE。
+
+![1538296878924](figures/open_ide.png)
+
+在弹出的窗口输入 workspace 创建工作空间，然后点击启动打开 IDE。
+
+![1538296978929](figures/ide.png)
+
+### 导入工程
+
+在菜单栏点击 `File->Import` 
+
+![1538297215062](figures/import.png)
+
+按照下面的图片导入工程
+
+![1538297303505](figures/import2.png)
+
+![1538297553367](figures/import3.png)
+
+
+
+### 编译
+
+![1538297679868](figures/build.png)
+
+然后等待编译完成
+
+![1538297922206](figures/builded.png)
+
+
+
+
+## 烧写及执行
+
+### 安装驱动
+
+1. 使用 Micro USB 线连接电脑和开发板。
+
+2. 然后双击安装 IDE 目录 `F:\FreedomStudio\SiFive\Drivers` 下的驱动文件
+
+### 添加字符串定义
+
+点击菜单栏 `Window->preferences`  按下图的步骤将 字符串 `cross_prefix` 定义为 `riscv64-unknown-elf-`
+
+![1538298633528](figures/string.png)
+
+### 配置 Debug 参数
+
+选中生成的 `rtthread.elf` 文件,右键配置 Debug 参数，如下图所示
+
+![1538298914673](figures/debug.png)
+
+按下图新建一个 Debug 选项
+
+![1538299063801](figures/debug1.png)
+
+打开 `Debugger` 选项卡 添加如下参数
+
+```
+-f openocd.cfg
+
+set mem inaccessible-by-default off
+set arch riscv:rv32
+set remotetimeout 250
+```
+
+如下图所示：
+
+![1538299273874](figures/debug2.png)
+
+打开 `startup` 选项卡，去掉**主机模式**和**复位命令**
+
+![1538299521246](figures/debug3.png)
+
+然后待程序停止在 main 函数处，然后点击继续运行程序就运行起来了。
+
+![1538299736730](figures/run.png)
+
+### 运行结果
+
+下载程序之后，连接串口(115200-N-8-1)，可以看到RT-Thread的输出信息：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     3.0.4 build May 30 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0_RX/TX：GPIO 16/17 |
+
+
+### 4.1 IO在板级支持包中的映射情况
+
+| IO号 | 板级包中的定义 |
+| -- | -- |
+| GPIO19 | LED_GREEN |
+| GPIO21 | LED_BLUE |
+| GPIO22 | LED_RED |
+
+## 5. 联系人信息
+
+维护人：
+- [tanek](https://github.com/TanekLiang)
+
+## 6. 参考
+
+* [HIFIVE1 Info](https://www.sifive.com/products/hifive1/)
+* [HIFIVE1 Software Development Tools](https://www.sifive.com/products/tools/)
+* [hifive1-getting-started-guide](https://www.sifive.com/documentation/boards/hifive1/hifive1-getting-started-guide/)
+* [hifive1-schematics](https://www.sifive.com/documentation/boards/hifive1/hifive1-schematics/)
diff --git a/bsp/gd32vf103v-eval/SConscript b/bsp/gd32vf103v-eval/SConscript
new file mode 100644
index 0000000000..534ec8eb5a
--- /dev/null
+++ b/bsp/gd32vf103v-eval/SConscript
@@ -0,0 +1,18 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = str(Dir('#'))
+src = Glob('*.c')
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+group = DefineGroup('', src, depend = [''], CPPPATH = [])
+#objs += group
+Return('objs')
diff --git a/bsp/gd32vf103v-eval/SConstruct b/bsp/gd32vf103v-eval/SConstruct
new file mode 100644
index 0000000000..3caac2f35d
--- /dev/null
+++ b/bsp/gd32vf103v-eval/SConstruct
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/gd32vf103v-eval/applications/SConscript b/bsp/gd32vf103v-eval/applications/SConscript
new file mode 100644
index 0000000000..ef1c39fd83
--- /dev/null
+++ b/bsp/gd32vf103v-eval/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd, ]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32vf103v-eval/applications/main.c b/bsp/gd32vf103v-eval/applications/main.c
new file mode 100644
index 0000000000..c411937c18
--- /dev/null
+++ b/bsp/gd32vf103v-eval/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-23     tyustli      first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+int main(int argc, char *argv[]) {
+    return RT_EOK;
+}
+
+/******************** end of file *******************/
+
diff --git a/bsp/gd32vf103v-eval/board/Kconfig b/bsp/gd32vf103v-eval/board/Kconfig
new file mode 100644
index 0000000000..402b48b4aa
--- /dev/null
+++ b/bsp/gd32vf103v-eval/board/Kconfig
@@ -0,0 +1,34 @@
+menu "Hardware Drivers Config"
+
+config SOC_STM32F429IG
+    bool
+    select SOC_SERIES_STM32F4
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_USART
+        bool "Enable USART (usart0)"
+        select BSP_USING_UART
+        select BSP_USING_UART0
+        default y
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default y
+        endif
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/gd32vf103v-eval/board/SConscript b/bsp/gd32vf103v-eval/board/SConscript
new file mode 100644
index 0000000000..afdaecc642
--- /dev/null
+++ b/bsp/gd32vf103v-eval/board/SConscript
@@ -0,0 +1,11 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32vf103v-eval/board/board.c b/bsp/gd32vf103v-eval/board/board.c
new file mode 100644
index 0000000000..6e666c281c
--- /dev/null
+++ b/bsp/gd32vf103v-eval/board/board.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-23     tyustli      first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+
+#ifdef RT_USING_SERIAL
+#include <drv_usart.h>
+#endif
+
+/*  System Tick Configuration */
+static void systick_config(rt_uint32_t ticks) {
+    /* set value */
+    *(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIMECMP) = ticks;
+    /* enable interrupt */
+    eclic_irq_enable(CLIC_INT_TMR, 0, 0);
+    /* clear value */
+    *(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIME) = 0;
+}
+
+/* This is the timer interrupt service routine. */
+void eclic_mtip_handler(void) {
+    /* clear value */
+    *(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIME) = 0;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* tick increase */
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void rt_hw_board_init(void) {
+    systick_config(TMR_FREQ / RT_TICK_PER_SECOND);
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
+#endif
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+    /* Set the shell console output device */
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/******************** end of file *******************/
+
diff --git a/bsp/gd32vf103v-eval/board/board.h b/bsp/gd32vf103v-eval/board/board.h
new file mode 100644
index 0000000000..422634fc38
--- /dev/null
+++ b/bsp/gd32vf103v-eval/board/board.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-23     tyustli      first version
+ *
+ */
+
+#ifndef __BOARD__
+#define __BOARD__
+#include "gd32vf103.h"
+
+extern void *_end;
+extern void *_heap_end;
+#define HEAP_BEGIN  &_end
+#define HEAP_END    &_heap_end
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD__ */
+
+/******************** end of file *******************/
diff --git a/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h b/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h
new file mode 100644
index 0000000000..ca292d2659
--- /dev/null
+++ b/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h
@@ -0,0 +1,64 @@
+/*!
+ \file  gd32vf103_libopt.h
+ \brief library optional for gd32vf103
+
+ \version 2019-6-5, V1.0.0, demo for GD32VF103
+ */
+
+/*
+ Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification, 
+ are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this 
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice, 
+ this list of conditions and the following disclaimer in the documentation 
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors 
+ may be used to endorse or promote products derived from this software without 
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+ IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ OF SUCH DAMAGE.
+ */
+
+#ifndef GD32VF103_LIBOPT_H
+#define GD32VF103_LIBOPT_H
+
+#include "gd32vf103_adc.h"
+#include "gd32vf103_bkp.h"
+#include "gd32vf103_can.h"
+#include "gd32vf103_crc.h"
+#include "gd32vf103_dac.h"
+#include "gd32vf103_dma.h"
+#include "gd32vf103_eclic.h"
+#include "gd32vf103_exmc.h"
+#include "gd32vf103_exti.h"
+#include "gd32vf103_fmc.h"
+#include "gd32vf103_gpio.h"
+#include "gd32vf103_i2c.h"
+#include "gd32vf103_fwdgt.h"
+#include "gd32vf103_dbg.h"
+#include "gd32vf103_pmu.h"
+#include "gd32vf103_rcu.h"
+#include "gd32vf103_rtc.h"
+#include "gd32vf103_spi.h"
+#include "gd32vf103_timer.h"
+#include "gd32vf103_usart.h"
+#include "gd32vf103_wwdgt.h"
+#include "n22_func.h"
+
+#endif /* GD32VF103_LIBOPT_H */
+
+/******************** end of file *******************/
+
diff --git a/bsp/gd32vf103v-eval/drivers/SConscript b/bsp/gd32vf103v-eval/drivers/SConscript
new file mode 100644
index 0000000000..975bcd5d5d
--- /dev/null
+++ b/bsp/gd32vf103v-eval/drivers/SConscript
@@ -0,0 +1,19 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split('''
+drv_uart.c
+''')
+CPPPATH = [cwd]
+
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+if GetDepend('RT_USING_I2C'):
+    src += ['drv_i2c.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/gd32vf103v-eval/drivers/drv_usart.c b/bsp/gd32vf103v-eval/drivers/drv_usart.c
new file mode 100644
index 0000000000..b093ebe5aa
--- /dev/null
+++ b/bsp/gd32vf103v-eval/drivers/drv_usart.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-23     tyustli      first version
+ */
+
+#include <drv_usart.h>
+
+#ifdef RT_USING_SERIAL
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
+    && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
+    #error "Please define at least one BSP_USING_UARTx"
+    /* this driver can be disabled at menuconfig �� RT-Thread Components �� Device Drivers */
+#endif
+
+struct gd32_usart {
+    char *name;
+    rt_uint32_t usart_base;
+    rt_uint32_t usart_clk;
+    rt_uint32_t gpio_clk;
+    rt_uint32_t gpio_port;
+    rt_uint32_t tx_pin;
+    rt_uint32_t rx_pin;
+    IRQn_Type irqn;
+    struct rt_serial_device serial;
+};
+
+enum {
+#ifdef BSP_USING_UART0
+    GDUSART0_INDEX,
+#endif
+};
+
+static struct gd32_usart usart_config[] = {
+#ifdef BSP_USING_UART0
+        { "uart0",
+        USART0, RCU_USART0, RCU_GPIOA,
+        GPIOA,
+        GPIO_PIN_9,
+        GPIO_PIN_10, USART0_IRQn, },
+#endif
+        };
+
+static rt_err_t gd32_configure(struct rt_serial_device *serial,
+        struct serial_configure *cfg) {
+    struct gd32_usart *usart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    usart = (struct gd32_usart *) serial->parent.user_data;
+    RT_ASSERT(usart != RT_NULL);
+
+    /* enable GPIO clock */
+    rcu_periph_clock_enable(usart->gpio_clk);
+    /* enable USART clock */
+    rcu_periph_clock_enable(usart->usart_clk);
+    /* connect port to USARTx_Tx */
+    gpio_init(usart->gpio_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ,
+            usart->tx_pin);
+    /* connect port to USARTx_Rx */
+    gpio_init(usart->gpio_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ,
+            usart->rx_pin);
+
+    usart_deinit(usart->usart_base);
+    usart_baudrate_set(usart->usart_base, cfg->baud_rate);
+
+    switch (cfg->data_bits) {
+    case DATA_BITS_8:
+        usart_word_length_set(usart->usart_base, USART_WL_8BIT);
+        break;
+
+    case DATA_BITS_9:
+        usart_word_length_set(usart->usart_base, USART_WL_9BIT);
+        break;
+    default:
+        usart_word_length_set(usart->usart_base, USART_WL_8BIT);
+        break;
+    }
+
+    switch (cfg->stop_bits) {
+    case STOP_BITS_1:
+        usart_stop_bit_set(usart->usart_base, USART_STB_1BIT);
+        break;
+    case STOP_BITS_2:
+        usart_stop_bit_set(usart->usart_base, USART_STB_2BIT);
+        break;
+    default:
+        usart_stop_bit_set(usart->usart_base, USART_STB_1BIT);
+        break;
+    }
+
+    switch (cfg->parity) {
+    case PARITY_NONE:
+        usart_parity_config(usart->usart_base, USART_PM_NONE);
+        break;
+    case PARITY_ODD:
+        usart_parity_config(usart->usart_base, USART_PM_ODD);
+        break;
+    case PARITY_EVEN:
+        usart_parity_config(usart->usart_base, USART_PM_EVEN);
+        break;
+    default:
+        usart_parity_config(usart->usart_base, USART_PM_NONE);
+        break;
+    }
+    usart_hardware_flow_rts_config(usart->usart_base, USART_RTS_DISABLE);
+    usart_hardware_flow_cts_config(usart->usart_base, USART_RTS_DISABLE);
+    usart_receive_config(usart->usart_base, USART_RECEIVE_ENABLE);
+    usart_transmit_config(usart->usart_base, USART_TRANSMIT_ENABLE);
+    usart_enable(usart->usart_base);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd,
+        void *arg) {
+    struct gd32_usart *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart = (struct gd32_usart *) serial->parent.user_data;
+    RT_ASSERT(usart != RT_NULL);
+
+    switch (cmd) {
+    case RT_DEVICE_CTRL_CLR_INT:
+        eclic_irq_disable(usart->usart_base);
+        usart_interrupt_disable(usart->usart_base, USART_INT_RBNE);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1);
+        eclic_irq_enable(usart->irqn, 1, 0);
+        /* enable USART0 receive interrupt */
+        usart_interrupt_enable(usart->usart_base, USART_INT_RBNE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int gd32_putc(struct rt_serial_device *serial, char ch) {
+    struct gd32_usart *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart = (struct gd32_usart *) serial->parent.user_data;
+    RT_ASSERT(usart != RT_NULL);
+
+    usart_data_transmit(usart->usart_base, (uint8_t) ch);
+    while (usart_flag_get(usart->usart_base, USART_FLAG_TBE) == RESET)
+        ;
+
+    return 1;
+}
+
+static int gd32_getc(struct rt_serial_device *serial) {
+    int ch;
+    struct gd32_usart *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart = (struct gd32_usart *) serial->parent.user_data;
+    RT_ASSERT(usart != RT_NULL);
+
+    ch = -1;
+    if (RESET != usart_flag_get(usart->usart_base, USART_FLAG_RBNE)) {
+        ch = usart_data_receive(usart->usart_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops gd32_usart_ops = { gd32_configure, gd32_control,
+        gd32_putc, gd32_getc,
+        RT_NULL };
+
+static void usart_isr(struct rt_serial_device *serial) {
+    struct gd32_usart *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    usart = (struct gd32_usart *) serial->parent.user_data;
+    RT_ASSERT(usart != RT_NULL);
+
+    if ((usart_interrupt_flag_get(usart->usart_base, USART_INT_FLAG_RBNE)
+            != RESET)
+            && (RESET != usart_flag_get(usart->usart_base, USART_FLAG_RBNE))) {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        usart_interrupt_flag_clear(usart->usart_base, USART_INT_FLAG_RBNE);
+        usart_flag_clear(usart->usart_base, USART_FLAG_RBNE);
+    } else {
+        if (usart_flag_get(usart->usart_base, USART_FLAG_CTSF) != RESET) {
+            usart_flag_clear(usart->usart_base, USART_FLAG_CTSF);
+        }
+
+        if (usart_flag_get(usart->usart_base, USART_FLAG_LBDF) != RESET) {
+            usart_flag_clear(usart->usart_base, USART_FLAG_LBDF);
+        }
+
+        if (usart_flag_get(usart->usart_base, USART_FLAG_TC) != RESET) {
+            usart_flag_clear(usart->usart_base, USART_FLAG_TC);
+        }
+    }
+}
+#ifdef BSP_USING_UART0
+
+void USART0_IRQHandler(void) {
+    rt_interrupt_enter();
+
+    usart_isr(&usart_config[GDUSART0_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+int rt_hw_usart_init(void) {
+    rt_size_t obj_num;
+    int index;
+
+    obj_num = sizeof(usart_config) / sizeof(struct gd32_usart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (index = 0; index < obj_num; index++) {
+        usart_config[index].serial.ops = &gd32_usart_ops;
+        usart_config[index].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&usart_config[index].serial,
+                usart_config[index].name,
+                RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
+                        | RT_DEVICE_FLAG_INT_TX, &usart_config[index]);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+
+#endif /* RT_USING_SERIAL */
+
+/******************** end of file *******************/
diff --git a/bsp/gd32vf103v-eval/drivers/drv_usart.h b/bsp/gd32vf103v-eval/drivers/drv_usart.h
new file mode 100644
index 0000000000..d4883262ed
--- /dev/null
+++ b/bsp/gd32vf103v-eval/drivers/drv_usart.h
@@ -0,0 +1,12 @@
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+
+int rt_hw_usart_init(void);
+
+#endif /* __DRV_USART_H__ */
+
+/******************* end of file *******************/
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h
new file mode 100644
index 0000000000..316c021a3f
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h
@@ -0,0 +1,396 @@
+/*!
+    \file  gd32vf103_adc.h
+    \brief definitions for the ADC
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_ADC_H
+#define GD32VF103_ADC_H
+
+#include "gd32vf103.h"
+
+/* ADC definitions */
+#define ADC0                            ADC_BASE
+#define ADC1                            (ADC_BASE + 0x400U)
+
+/* registers definitions */
+#define ADC_STAT(adcx)                  REG32((adcx) + 0x00U)            /*!< ADC status register */
+#define ADC_CTL0(adcx)                  REG32((adcx) + 0x04U)            /*!< ADC control register 0 */
+#define ADC_CTL1(adcx)                  REG32((adcx) + 0x08U)            /*!< ADC control register 1 */
+#define ADC_SAMPT0(adcx)                REG32((adcx) + 0x0CU)            /*!< ADC sampling time register 0 */
+#define ADC_SAMPT1(adcx)                REG32((adcx) + 0x10U)            /*!< ADC sampling time register 1 */
+#define ADC_IOFF0(adcx)                 REG32((adcx) + 0x14U)            /*!< ADC inserted channel data offset register 0 */
+#define ADC_IOFF1(adcx)                 REG32((adcx) + 0x18U)            /*!< ADC inserted channel data offset register 1 */
+#define ADC_IOFF2(adcx)                 REG32((adcx) + 0x1CU)            /*!< ADC inserted channel data offset register 2 */
+#define ADC_IOFF3(adcx)                 REG32((adcx) + 0x20U)            /*!< ADC inserted channel data offset register 3 */
+#define ADC_WDHT(adcx)                  REG32((adcx) + 0x24U)            /*!< ADC watchdog high threshold register */
+#define ADC_WDLT(adcx)                  REG32((adcx) + 0x28U)            /*!< ADC watchdog low threshold register */
+#define ADC_RSQ0(adcx)                  REG32((adcx) + 0x2CU)            /*!< ADC regular sequence register 0 */
+#define ADC_RSQ1(adcx)                  REG32((adcx) + 0x30U)            /*!< ADC regular sequence register 1 */
+#define ADC_RSQ2(adcx)                  REG32((adcx) + 0x34U)            /*!< ADC regular sequence register 2 */
+#define ADC_ISQ(adcx)                   REG32((adcx) + 0x38U)            /*!< ADC inserted sequence register */
+#define ADC_IDATA0(adcx)                REG32((adcx) + 0x3CU)            /*!< ADC inserted data register 0 */
+#define ADC_IDATA1(adcx)                REG32((adcx) + 0x40U)            /*!< ADC inserted data register 1 */
+#define ADC_IDATA2(adcx)                REG32((adcx) + 0x44U)            /*!< ADC inserted data register 2 */
+#define ADC_IDATA3(adcx)                REG32((adcx) + 0x48U)            /*!< ADC inserted data register 3 */
+#define ADC_RDATA(adcx)                 REG32((adcx) + 0x4CU)            /*!< ADC regular data register */
+#define ADC_OVSCR(adcx)                 REG32((adcx) + 0x80U)            /*!< ADC oversample control register */
+
+/* bits definitions */
+/* ADC_STAT */
+#define ADC_STAT_WDE                    BIT(0)                           /*!< analog watchdog event flag */
+#define ADC_STAT_EOC                    BIT(1)                           /*!< end of conversion */
+#define ADC_STAT_EOIC                   BIT(2)                           /*!< inserted channel end of conversion */
+#define ADC_STAT_STIC                   BIT(3)                           /*!< inserted channel start flag */
+#define ADC_STAT_STRC                   BIT(4)                           /*!< regular channel start flag */
+
+/* ADC_CTL0 */
+#define ADC_CTL0_WDCHSEL                BITS(0,4)                        /*!< analog watchdog channel select bits */
+#define ADC_CTL0_EOCIE                  BIT(5)                           /*!< interrupt enable for EOC */
+#define ADC_CTL0_WDEIE                  BIT(6)                           /*!< analog watchdog interrupt enable */
+#define ADC_CTL0_EOICIE                 BIT(7)                           /*!< interrupt enable for inserted channels */
+#define ADC_CTL0_SM                     BIT(8)                           /*!< scan mode */
+#define ADC_CTL0_WDSC                   BIT(9)                           /*!< when in scan mode, analog watchdog is effective on a single channel */
+#define ADC_CTL0_ICA                    BIT(10)                          /*!< automatic inserted group conversion */
+#define ADC_CTL0_DISRC                  BIT(11)                          /*!< discontinuous mode on regular channels */
+#define ADC_CTL0_DISIC                  BIT(12)                          /*!< discontinuous mode on inserted channels */
+#define ADC_CTL0_DISNUM                 BITS(13,15)                      /*!< discontinuous mode channel count */
+#define ADC_CTL0_SYNCM                  BITS(16,19)                      /*!< sync mode selection */
+#define ADC_CTL0_IWDEN                  BIT(22)                          /*!< analog watchdog enable on inserted channels */
+#define ADC_CTL0_RWDEN                  BIT(23)                          /*!< analog watchdog enable on regular channels */
+
+/* ADC_CTL1 */
+#define ADC_CTL1_ADCON                  BIT(0)                           /*!< ADC converter on */
+#define ADC_CTL1_CTN                    BIT(1)                           /*!< continuous conversion */
+#define ADC_CTL1_CLB                    BIT(2)                           /*!< ADC calibration */
+#define ADC_CTL1_RSTCLB                 BIT(3)                           /*!< reset calibration */
+#define ADC_CTL1_DMA                    BIT(8)                           /*!< direct memory access mode */
+#define ADC_CTL1_DAL                    BIT(11)                          /*!< data alignment */
+#define ADC_CTL1_ETSIC                  BITS(12,14)                      /*!< external trigger select for inserted channel */
+#define ADC_CTL1_ETEIC                  BIT(15)                          /*!< external trigger enable for inserted channel */
+#define ADC_CTL1_ETSRC                  BITS(17,19)                      /*!< external trigger select for regular channel */
+#define ADC_CTL1_ETERC                  BIT(20)                          /*!< external trigger conversion mode for inserted channels */
+#define ADC_CTL1_SWICST                 BIT(21)                          /*!< start on inserted channel */
+#define ADC_CTL1_SWRCST                 BIT(22)                          /*!< start on regular channel */
+#define ADC_CTL1_TSVREN                 BIT(23)                          /*!< channel 16 and 17 enable of ADC0 */
+
+/* ADC_SAMPTx x=0..1 */
+#define ADC_SAMPTX_SPTN                 BITS(0,2)                        /*!< channel n sample time selection */
+
+/* ADC_IOFFx x=0..3 */
+#define ADC_IOFFX_IOFF                  BITS(0,11)                       /*!< data offset for inserted channel x */
+
+/* ADC_WDHT */
+#define ADC_WDHT_WDHT                   BITS(0,11)                       /*!< analog watchdog high threshold */
+
+/* ADC_WDLT */
+#define ADC_WDLT_WDLT                   BITS(0,11)                       /*!< analog watchdog low threshold */
+
+/* ADC_RSQx x=0..2 */
+#define ADC_RSQX_RSQN                   BITS(0,4)                        /*!< nth conversion in regular sequence */
+#define ADC_RSQ0_RL                     BITS(20,23)                      /*!< regular channel sequence length */
+
+/* ADC_ISQ */
+#define ADC_ISQ_ISQN                    BITS(0,4)                        /*!< nth conversion in inserted sequence */
+#define ADC_ISQ_IL                      BITS(20,21)                      /*!< inserted sequence length */
+
+/* ADC_IDATAx x=0..3*/
+#define ADC_IDATAX_IDATAN               BITS(0,15)                       /*!< inserted data n */
+
+/* ADC_RDATA */
+#define ADC_RDATA_RDATA                 BITS(0,15)                       /*!< regular data */
+#define ADC_RDATA_ADC1RDTR              BITS(16,31)                      /*!< ADC1 regular channel data */
+
+/* ADC_OVSCR */
+#define ADC_OVSCR_OVSEN                 BIT(0)                           /*!< oversampling enable */
+#define ADC_OVSCR_OVSR                  BITS(2,4)                        /*!< oversampling ratio */
+#define ADC_OVSCR_OVSS                  BITS(5,8)                        /*!< oversampling shift */
+#define ADC_OVSCR_TOVS                  BIT(9)                           /*!< triggered oversampling */
+#define ADC_OVSCR_DRES                  BITS(12,13)                      /*!< ADC data resolution */
+
+/* constants definitions */
+/* adc_stat register value */
+#define ADC_FLAG_WDE                    ADC_STAT_WDE                                 /*!< analog watchdog event flag */
+#define ADC_FLAG_EOC                    ADC_STAT_EOC                                 /*!< end of conversion */
+#define ADC_FLAG_EOIC                   ADC_STAT_EOIC                                /*!< inserted channel end of conversion */
+#define ADC_FLAG_STIC                   ADC_STAT_STIC                                /*!< inserted channel start flag */
+#define ADC_FLAG_STRC                   ADC_STAT_STRC                                /*!< regular channel start flag */
+
+/* adc_ctl0 register value */
+#define CTL0_DISNUM(regval)             (BITS(13,15) & ((uint32_t)(regval) << 13))   /*!< write value to ADC_CTL0_DISNUM bit field */
+
+/* scan mode */
+#define ADC_SCAN_MODE                   ADC_CTL0_SM                                  /*!< scan mode */
+
+/* inserted channel group convert automatically */
+#define ADC_INSERTED_CHANNEL_AUTO       ADC_CTL0_ICA                                 /*!< inserted channel group convert automatically */
+
+/* ADC sync mode */
+#define CTL0_SYNCM(regval)              (BITS(16,19) & ((uint32_t)(regval) << 16))   /*!< write value to ADC_CTL0_SYNCM bit field */
+#define ADC_MODE_FREE                                        CTL0_SYNCM(0)           /*!< all the ADCs work independently */
+#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL          CTL0_SYNCM(1)           /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
+#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION          CTL0_SYNCM(2)           /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
+#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST     CTL0_SYNCM(3)           /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
+#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW     CTL0_SYNCM(4)           /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
+#define ADC_DAUL_INSERTED_PARALLEL                           CTL0_SYNCM(5)           /*!< ADC0 and ADC1 work in inserted parallel mode only */
+#define ADC_DAUL_REGULAL_PARALLEL                            CTL0_SYNCM(6)           /*!< ADC0 and ADC1 work in regular parallel mode only */
+#define ADC_DAUL_REGULAL_FOLLOWUP_FAST                       CTL0_SYNCM(7)           /*!< ADC0 and ADC1 work in follow-up fast mode only */
+#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW                       CTL0_SYNCM(8)           /*!< ADC0 and ADC1 work in follow-up slow mode only */
+#define ADC_DAUL_INSERTED_TRIGGER_ROTATION                   CTL0_SYNCM(9)           /*!< ADC0 and ADC1 work in trigger rotation mode only */
+
+/* adc_ctl1 register value */
+#define ADC_DATAALIGN_RIGHT              ((uint32_t)0x00000000U)                     /*!< LSB alignment */
+#define ADC_DATAALIGN_LEFT               ADC_CTL1_DAL                                /*!< MSB alignment */
+
+/* continuous mode */
+#define ADC_CONTINUOUS_MODE              ADC_CTL1_CTN                                /*!< continuous mode */
+
+/* external trigger select for regular channel */
+#define CTL1_ETSRC(regval)               (BITS(17,19) & ((uint32_t)(regval) << 17))  /*!< write value to ADC_CTL1_ETSRC bit field */
+/* for ADC0 and ADC1 regular channel */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH0    CTL1_ETSRC(0)                               /*!< TIMER0 CH0 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH1    CTL1_ETSRC(1)                               /*!< TIMER0 CH1 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH2    CTL1_ETSRC(2)                               /*!< TIMER0 CH2 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T1_CH1    CTL1_ETSRC(3)                               /*!< TIMER1 CH1 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO   CTL1_ETSRC(4)                               /*!< TIMER2 TRGO event select */
+#define ADC0_1_EXTTRIG_REGULAR_T3_CH3    CTL1_ETSRC(5)                               /*!< TIMER3 CH3 event select */
+#define ADC0_1_EXTTRIG_REGULAR_EXTI_11   CTL1_ETSRC(6)                               /*!< external interrupt line 11 */
+#define ADC0_1_EXTTRIG_REGULAR_NONE      CTL1_ETSRC(7)                               /*!< software trigger */
+
+/* external trigger mode for inserted channel */
+#define CTL1_ETSIC(regval)               (BITS(12,14) & ((uint32_t)(regval) << 12))  /*!< write value to ADC_CTL1_ETSIC bit field */
+/* for ADC0 and ADC1 inserted channel */
+#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO  CTL1_ETSIC(0)                               /*!< TIMER0 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_T0_CH3   CTL1_ETSIC(1)                               /*!< TIMER0 CH3 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO  CTL1_ETSIC(2)                               /*!< TIMER1 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_T1_CH0   CTL1_ETSIC(3)                               /*!< TIMER1 CH0 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T2_CH3   CTL1_ETSIC(4)                               /*!< TIMER2 CH3 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO  CTL1_ETSIC(5)                               /*!< TIMER3 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_EXTI_15  CTL1_ETSIC(6)                               /*!< external interrupt line 15 */
+#define ADC0_1_EXTTRIG_INSERTED_NONE     CTL1_ETSIC(7)                               /*!< software trigger */
+
+/* adc_samptx register value */
+#define SAMPTX_SPT(regval)               (BITS(0,2) & ((uint32_t)(regval) << 0))     /*!< write value to ADC_SAMPTX_SPT bit field */
+#define ADC_SAMPLETIME_1POINT5           SAMPTX_SPT(0)                               /*!< 1.5 sampling cycles */
+#define ADC_SAMPLETIME_7POINT5           SAMPTX_SPT(1)                               /*!< 7.5 sampling cycles */
+#define ADC_SAMPLETIME_13POINT5          SAMPTX_SPT(2)                               /*!< 13.5 sampling cycles */
+#define ADC_SAMPLETIME_28POINT5          SAMPTX_SPT(3)                               /*!< 28.5 sampling cycles */
+#define ADC_SAMPLETIME_41POINT5          SAMPTX_SPT(4)                               /*!< 41.5 sampling cycles */
+#define ADC_SAMPLETIME_55POINT5          SAMPTX_SPT(5)                               /*!< 55.5 sampling cycles */
+#define ADC_SAMPLETIME_71POINT5          SAMPTX_SPT(6)                               /*!< 71.5 sampling cycles */
+#define ADC_SAMPLETIME_239POINT5         SAMPTX_SPT(7)                               /*!< 239.5 sampling cycles */
+
+/* adc_ioffx register value */
+#define IOFFX_IOFF(regval)               (BITS(0,11) & ((uint32_t)(regval) << 0))    /*!< write value to ADC_IOFFX_IOFF bit field */
+
+/* adc_wdht register value */
+#define WDHT_WDHT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))    /*!< write value to ADC_WDHT_WDHT bit field */
+
+/* adc_wdlt register value */
+#define WDLT_WDLT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))    /*!< write value to ADC_WDLT_WDLT bit field */
+
+/* adc_rsqx register value */
+#define RSQ0_RL(regval)                  (BITS(20,23) & ((uint32_t)(regval) << 20))  /*!< write value to ADC_RSQ0_RL bit field */
+
+/* adc_isq register value */
+#define ISQ_IL(regval)                   (BITS(20,21) & ((uint32_t)(regval) << 20))  /*!< write value to ADC_ISQ_IL bit field */
+
+/* ADC channel group definitions */
+#define ADC_REGULAR_CHANNEL              ((uint8_t)0x01U)                            /*!< adc regular channel group */
+#define ADC_INSERTED_CHANNEL             ((uint8_t)0x02U)                            /*!< adc inserted channel group */
+#define ADC_REGULAR_INSERTED_CHANNEL     ((uint8_t)0x03U)                            /*!< both regular and inserted channel group */
+
+#define ADC_CHANNEL_DISCON_DISABLE       ((uint8_t)0x04U)                            /*!< disable discontinuous mode of regular & inserted channel */
+
+/* ADC inserted channel definitions */
+#define ADC_INSERTED_CHANNEL_0           ((uint8_t)0x00U)                            /*!< adc inserted channel 0 */
+#define ADC_INSERTED_CHANNEL_1           ((uint8_t)0x01U)                            /*!< adc inserted channel 1 */
+#define ADC_INSERTED_CHANNEL_2           ((uint8_t)0x02U)                            /*!< adc inserted channel 2 */
+#define ADC_INSERTED_CHANNEL_3           ((uint8_t)0x03U)                            /*!< adc inserted channel 3 */
+
+/* ADC channel definitions */
+#define ADC_CHANNEL_0                    ((uint8_t)0x00U)                            /*!< ADC channel 0 */
+#define ADC_CHANNEL_1                    ((uint8_t)0x01U)                            /*!< ADC channel 1 */
+#define ADC_CHANNEL_2                    ((uint8_t)0x02U)                            /*!< ADC channel 2 */
+#define ADC_CHANNEL_3                    ((uint8_t)0x03U)                            /*!< ADC channel 3 */
+#define ADC_CHANNEL_4                    ((uint8_t)0x04U)                            /*!< ADC channel 4 */
+#define ADC_CHANNEL_5                    ((uint8_t)0x05U)                            /*!< ADC channel 5 */
+#define ADC_CHANNEL_6                    ((uint8_t)0x06U)                            /*!< ADC channel 6 */
+#define ADC_CHANNEL_7                    ((uint8_t)0x07U)                            /*!< ADC channel 7 */
+#define ADC_CHANNEL_8                    ((uint8_t)0x08U)                            /*!< ADC channel 8 */
+#define ADC_CHANNEL_9                    ((uint8_t)0x09U)                            /*!< ADC channel 9 */
+#define ADC_CHANNEL_10                   ((uint8_t)0x0AU)                            /*!< ADC channel 10 */
+#define ADC_CHANNEL_11                   ((uint8_t)0x0BU)                            /*!< ADC channel 11 */
+#define ADC_CHANNEL_12                   ((uint8_t)0x0CU)                            /*!< ADC channel 12 */
+#define ADC_CHANNEL_13                   ((uint8_t)0x0DU)                            /*!< ADC channel 13 */
+#define ADC_CHANNEL_14                   ((uint8_t)0x0EU)                            /*!< ADC channel 14 */
+#define ADC_CHANNEL_15                   ((uint8_t)0x0FU)                            /*!< ADC channel 15 */
+#define ADC_CHANNEL_16                   ((uint8_t)0x10U)                            /*!< ADC channel 16 */
+#define ADC_CHANNEL_17                   ((uint8_t)0x11U)                            /*!< ADC channel 17 */
+
+/* ADC interrupt */
+#define ADC_INT_WDE                      ADC_STAT_WDE                                /*!< analog watchdog event interrupt */
+#define ADC_INT_EOC                      ADC_STAT_EOC                                /*!< end of group conversion interrupt */
+#define ADC_INT_EOIC                     ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt */
+
+/* ADC interrupt flag */
+#define ADC_INT_FLAG_WDE                 ADC_STAT_WDE                                /*!< analog watchdog event interrupt flag */
+#define ADC_INT_FLAG_EOC                 ADC_STAT_EOC                                /*!< end of group conversion interrupt flag */
+#define ADC_INT_FLAG_EOIC                ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt flag */
+
+/* ADC resolution definitions */
+#define OVSCR_DRES(regval)               (BITS(12,13) & ((uint32_t)(regval) << 12))
+#define ADC_RESOLUTION_12B               OVSCR_DRES(0)                               /*!< 12-bit ADC resolution */
+#define ADC_RESOLUTION_10B               OVSCR_DRES(1)                               /*!< 10-bit ADC resolution */
+#define ADC_RESOLUTION_8B                OVSCR_DRES(2)                               /*!< 8-bit ADC resolution */
+#define ADC_RESOLUTION_6B                OVSCR_DRES(3)                               /*!< 6-bit ADC resolution */
+
+/* ADC oversampling mode */
+#define ADC_OVERSAMPLING_ALL_CONVERT     0                                           /*!< all oversampled conversions for a channel are done consecutively after a trigger */
+#define ADC_OVERSAMPLING_ONE_CONVERT     1                                           /*!< each oversampled conversion for a channel needs a trigger */
+
+/* ADC oversampling shift */
+#define OVSCR_OVSS(regval)               (BITS(5,8) & ((uint32_t)(regval) << 5))
+#define ADC_OVERSAMPLING_SHIFT_NONE      OVSCR_OVSS(0)                               /*!< no oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_1B        OVSCR_OVSS(1)                               /*!< 1-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_2B        OVSCR_OVSS(2)                               /*!< 2-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_3B        OVSCR_OVSS(3)                               /*!< 3-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_4B        OVSCR_OVSS(4)                               /*!< 4-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_5B        OVSCR_OVSS(5)                               /*!< 5-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_6B        OVSCR_OVSS(6)                               /*!< 6-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_7B        OVSCR_OVSS(7)                               /*!< 7-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_8B        OVSCR_OVSS(8)                               /*!< 8-bit oversampling shift */
+
+/* ADC oversampling ratio */
+#define OVSCR_OVSR(regval)               (BITS(2,4) & ((uint32_t)(regval) << 2))
+#define ADC_OVERSAMPLING_RATIO_MUL2      OVSCR_OVSR(0)                               /*!< oversampling ratio X2 */
+#define ADC_OVERSAMPLING_RATIO_MUL4      OVSCR_OVSR(1)                               /*!< oversampling ratio X4 */
+#define ADC_OVERSAMPLING_RATIO_MUL8      OVSCR_OVSR(2)                               /*!< oversampling ratio X8 */
+#define ADC_OVERSAMPLING_RATIO_MUL16     OVSCR_OVSR(3)                               /*!< oversampling ratio X16 */
+#define ADC_OVERSAMPLING_RATIO_MUL32     OVSCR_OVSR(4)                               /*!< oversampling ratio X32 */
+#define ADC_OVERSAMPLING_RATIO_MUL64     OVSCR_OVSR(5)                               /*!< oversampling ratio X64 */
+#define ADC_OVERSAMPLING_RATIO_MUL128    OVSCR_OVSR(6)                               /*!< oversampling ratio X128 */
+#define ADC_OVERSAMPLING_RATIO_MUL256    OVSCR_OVSR(7)                               /*!< oversampling ratio X256 */
+
+/* function declarations */
+/* initialization config */
+/* reset ADC */
+void adc_deinit(uint32_t adc_periph);
+/* configure the ADC sync mode */
+void adc_mode_config(uint32_t mode);
+/* enable or disable ADC special function */
+void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
+/* configure ADC data alignment */
+void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
+/* enable ADC interface */
+void adc_enable(uint32_t adc_periph);
+/* disable ADC interface */
+void adc_disable(uint32_t adc_periph);
+/* ADC calibration and reset calibration */
+void adc_calibration_enable(uint32_t adc_periph);
+/* enable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_enable(void);
+/* disable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_disable(void);
+
+/* DMA config */
+/* enable DMA request */
+void adc_dma_mode_enable(uint32_t adc_periph);
+/* disable DMA request */
+void adc_dma_mode_disable(uint32_t adc_periph);
+
+/* regular group and inserted group config */
+/* configure ADC discontinuous mode */
+void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
+
+/* configure the length of regular channel group or inserted channel group */
+void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
+/* configure ADC regular channel */
+void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
+/* configure ADC inserted channel */
+void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
+/* configure ADC inserted channel offset */
+void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
+
+/* configure ADC external trigger source */
+void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
+/* configure ADC external trigger */
+void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
+/* enable ADC software trigger */
+void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
+
+/* get channel data */
+/* read ADC regular group data register */
+uint16_t adc_regular_data_read(uint32_t adc_periph);
+/* read ADC inserted group data register */
+uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
+/* read the last ADC0 and ADC1 conversion result data in sync mode */
+uint32_t adc_sync_mode_convert_value_read(void);
+
+/* watchdog config */
+/* configure ADC analog watchdog single channel */
+void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
+/* configure ADC analog watchdog group channel */
+void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
+/* disable ADC analog watchdog */
+void adc_watchdog_disable(uint32_t adc_periph);
+/* configure ADC analog watchdog threshold */
+void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
+
+/* interrupt & flag functions */
+/* get the ADC flag bits */
+FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
+/* clear the ADC flag bits */
+void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
+/* get the bit state of ADCx software start conversion */
+FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
+/* get the bit state of ADCx software inserted channel start conversion */
+FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
+/* get the ADC interrupt bits */
+FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
+/* clear the ADC flag */
+void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
+/* enable ADC interrupt */
+void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
+/* disable ADC interrupt */
+void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
+
+/* ADC resolution & oversample */
+/* ADC resolution config */
+void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
+/* ADC oversample mode config */
+void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio);
+/* enable ADC oversample mode */
+void adc_oversample_mode_enable(uint32_t adc_periph);
+/* disable ADC oversample mode */
+void adc_oversample_mode_disable(uint32_t adc_periph);
+
+#endif /* GD32VF103_ADC_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h
new file mode 100644
index 0000000000..a6e1a3fd9e
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h
@@ -0,0 +1,227 @@
+/*!
+    \file    gd32vf103_bkp.h
+    \brief   definitions for the BKP
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_BKP_H
+#define GD32VF103_BKP_H
+
+#include "gd32vf103.h"
+
+/* BKP definitions */
+#define BKP                             BKP_BASE                 /*!< BKP base address */
+
+/* registers definitions */
+#define BKP_DATA0                       REG16((BKP) + 0x04U)     /*!< BKP data register 0 */
+#define BKP_DATA1                       REG16((BKP) + 0x08U)     /*!< BKP data register 1 */
+#define BKP_DATA2                       REG16((BKP) + 0x0CU)     /*!< BKP data register 2 */
+#define BKP_DATA3                       REG16((BKP) + 0x10U)     /*!< BKP data register 3 */
+#define BKP_DATA4                       REG16((BKP) + 0x14U)     /*!< BKP data register 4 */
+#define BKP_DATA5                       REG16((BKP) + 0x18U)     /*!< BKP data register 5 */
+#define BKP_DATA6                       REG16((BKP) + 0x1CU)     /*!< BKP data register 6 */
+#define BKP_DATA7                       REG16((BKP) + 0x20U)     /*!< BKP data register 7 */
+#define BKP_DATA8                       REG16((BKP) + 0x24U)     /*!< BKP data register 8 */
+#define BKP_DATA9                       REG16((BKP) + 0x28U)     /*!< BKP data register 9 */
+#define BKP_DATA10                      REG16((BKP) + 0x40U)     /*!< BKP data register 10 */
+#define BKP_DATA11                      REG16((BKP) + 0x44U)     /*!< BKP data register 11 */
+#define BKP_DATA12                      REG16((BKP) + 0x48U)     /*!< BKP data register 12 */
+#define BKP_DATA13                      REG16((BKP) + 0x4CU)     /*!< BKP data register 13 */
+#define BKP_DATA14                      REG16((BKP) + 0x50U)     /*!< BKP data register 14 */
+#define BKP_DATA15                      REG16((BKP) + 0x54U)     /*!< BKP data register 15 */
+#define BKP_DATA16                      REG16((BKP) + 0x58U)     /*!< BKP data register 16 */
+#define BKP_DATA17                      REG16((BKP) + 0x5CU)     /*!< BKP data register 17 */
+#define BKP_DATA18                      REG16((BKP) + 0x60U)     /*!< BKP data register 18 */
+#define BKP_DATA19                      REG16((BKP) + 0x64U)     /*!< BKP data register 19 */
+#define BKP_DATA20                      REG16((BKP) + 0x68U)     /*!< BKP data register 20 */
+#define BKP_DATA21                      REG16((BKP) + 0x6CU)     /*!< BKP data register 21 */
+#define BKP_DATA22                      REG16((BKP) + 0x70U)     /*!< BKP data register 22 */
+#define BKP_DATA23                      REG16((BKP) + 0x74U)     /*!< BKP data register 23 */
+#define BKP_DATA24                      REG16((BKP) + 0x78U)     /*!< BKP data register 24 */
+#define BKP_DATA25                      REG16((BKP) + 0x7CU)     /*!< BKP data register 25 */
+#define BKP_DATA26                      REG16((BKP) + 0x80U)     /*!< BKP data register 26 */
+#define BKP_DATA27                      REG16((BKP) + 0x84U)     /*!< BKP data register 27 */
+#define BKP_DATA28                      REG16((BKP) + 0x88U)     /*!< BKP data register 28 */
+#define BKP_DATA29                      REG16((BKP) + 0x8CU)     /*!< BKP data register 29 */
+#define BKP_DATA30                      REG16((BKP) + 0x90U)     /*!< BKP data register 30 */
+#define BKP_DATA31                      REG16((BKP) + 0x94U)     /*!< BKP data register 31 */
+#define BKP_DATA32                      REG16((BKP) + 0x98U)     /*!< BKP data register 32 */
+#define BKP_DATA33                      REG16((BKP) + 0x9CU)     /*!< BKP data register 33 */
+#define BKP_DATA34                      REG16((BKP) + 0xA0U)     /*!< BKP data register 34 */
+#define BKP_DATA35                      REG16((BKP) + 0xA4U)     /*!< BKP data register 35 */
+#define BKP_DATA36                      REG16((BKP) + 0xA8U)     /*!< BKP data register 36 */
+#define BKP_DATA37                      REG16((BKP) + 0xACU)     /*!< BKP data register 37 */
+#define BKP_DATA38                      REG16((BKP) + 0xB0U)     /*!< BKP data register 38 */
+#define BKP_DATA39                      REG16((BKP) + 0xB4U)     /*!< BKP data register 39 */
+#define BKP_DATA40                      REG16((BKP) + 0xB8U)     /*!< BKP data register 40 */
+#define BKP_DATA41                      REG16((BKP) + 0xBCU)     /*!< BKP data register 41 */
+#define BKP_OCTL                        REG16((BKP) + 0x2CU)     /*!< RTC signal output control register */
+#define BKP_TPCTL                       REG16((BKP) + 0x30U)     /*!< tamper pin control register */
+#define BKP_TPCS                        REG16((BKP) + 0x34U)     /*!< tamper control and status register */
+
+/* bits definitions */
+/* BKP_DATA */
+#define BKP_DATA                        BITS(0,15)               /*!< backup data */
+
+/* BKP_OCTL */
+#define BKP_OCTL_RCCV                   BITS(0,6)                /*!< RTC clock calibration value */
+#define BKP_OCTL_COEN                   BIT(7)                   /*!< RTC clock calibration output enable */
+#define BKP_OCTL_ASOEN                  BIT(8)                   /*!< RTC alarm or second signal output enable */
+#define BKP_OCTL_ROSEL                  BIT(9)                   /*!< RTC output selection */
+
+/* BKP_TPCTL */
+#define BKP_TPCTL_TPEN                  BIT(0)                   /*!< tamper detection enable */
+#define BKP_TPCTL_TPAL                  BIT(1)                   /*!< tamper pin active level */
+
+/* BKP_TPCS */
+#define BKP_TPCS_TER                    BIT(0)                   /*!< tamper event reset */
+#define BKP_TPCS_TIR                    BIT(1)                   /*!< tamper interrupt reset */
+#define BKP_TPCS_TPIE                   BIT(2)                   /*!< tamper interrupt enable */
+#define BKP_TPCS_TEF                    BIT(8)                   /*!< tamper event flag */
+#define BKP_TPCS_TIF                    BIT(9)                   /*!< tamper interrupt flag */
+
+/* constants definitions */
+/* BKP data register number */
+typedef enum 
+{
+    BKP_DATA_0 = 1,                                              /*!< BKP data register 0 */
+    BKP_DATA_1,                                                  /*!< BKP data register 1 */
+    BKP_DATA_2,                                                  /*!< BKP data register 2 */
+    BKP_DATA_3,                                                  /*!< BKP data register 3 */
+    BKP_DATA_4,                                                  /*!< BKP data register 4 */
+    BKP_DATA_5,                                                  /*!< BKP data register 5 */
+    BKP_DATA_6,                                                  /*!< BKP data register 6 */
+    BKP_DATA_7,                                                  /*!< BKP data register 7 */
+    BKP_DATA_8,                                                  /*!< BKP data register 8 */
+    BKP_DATA_9,                                                  /*!< BKP data register 9 */
+    BKP_DATA_10,                                                 /*!< BKP data register 10 */
+    BKP_DATA_11,                                                 /*!< BKP data register 11 */
+    BKP_DATA_12,                                                 /*!< BKP data register 12 */
+    BKP_DATA_13,                                                 /*!< BKP data register 13 */
+    BKP_DATA_14,                                                 /*!< BKP data register 14 */
+    BKP_DATA_15,                                                 /*!< BKP data register 15 */
+    BKP_DATA_16,                                                 /*!< BKP data register 16 */
+    BKP_DATA_17,                                                 /*!< BKP data register 17 */
+    BKP_DATA_18,                                                 /*!< BKP data register 18 */
+    BKP_DATA_19,                                                 /*!< BKP data register 19 */
+    BKP_DATA_20,                                                 /*!< BKP data register 20 */
+    BKP_DATA_21,                                                 /*!< BKP data register 21 */
+    BKP_DATA_22,                                                 /*!< BKP data register 22 */
+    BKP_DATA_23,                                                 /*!< BKP data register 23 */
+    BKP_DATA_24,                                                 /*!< BKP data register 24 */
+    BKP_DATA_25,                                                 /*!< BKP data register 25 */
+    BKP_DATA_26,                                                 /*!< BKP data register 26 */
+    BKP_DATA_27,                                                 /*!< BKP data register 27 */
+    BKP_DATA_28,                                                 /*!< BKP data register 28 */
+    BKP_DATA_29,                                                 /*!< BKP data register 29 */
+    BKP_DATA_30,                                                 /*!< BKP data register 30 */
+    BKP_DATA_31,                                                 /*!< BKP data register 31 */
+    BKP_DATA_32,                                                 /*!< BKP data register 32 */
+    BKP_DATA_33,                                                 /*!< BKP data register 33 */
+    BKP_DATA_34,                                                 /*!< BKP data register 34 */
+    BKP_DATA_35,                                                 /*!< BKP data register 35 */
+    BKP_DATA_36,                                                 /*!< BKP data register 36 */
+    BKP_DATA_37,                                                 /*!< BKP data register 37 */
+    BKP_DATA_38,                                                 /*!< BKP data register 38 */
+    BKP_DATA_39,                                                 /*!< BKP data register 39 */
+    BKP_DATA_40,                                                 /*!< BKP data register 40 */
+    BKP_DATA_41,                                                 /*!< BKP data register 41 */
+}bkp_data_register_enum;
+
+/* BKP register */
+#define BKP_DATA0_9(number)             REG16((BKP) + 0x04U + (number) * 0x04U)
+#define BKP_DATA10_41(number)           REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
+
+/* get data of BKP data register */
+#define BKP_DATA_GET(regval)            GET_BITS((uint32_t)(regval), 0, 15)
+
+/* RTC clock calibration value */
+#define OCTL_RCCV(regval)               (BITS(0,6) & ((uint32_t)(regval) << 0))
+
+/* RTC output selection */
+#define RTC_OUTPUT_ALARM_PULSE          ((uint16_t)0x0000U)      /*!< RTC alarm pulse is selected as the RTC output */
+#define RTC_OUTPUT_SECOND_PULSE         ((uint16_t)0x0200U)      /*!< RTC second pulse is selected as the RTC output */
+
+/* tamper pin active level */
+#define TAMPER_PIN_ACTIVE_HIGH          ((uint16_t)0x0000U)      /*!< the tamper pin is active high */
+#define TAMPER_PIN_ACTIVE_LOW           ((uint16_t)0x0002U)      /*!< the tamper pin is active low */
+
+/* tamper flag */
+#define BKP_FLAG_TAMPER                 BKP_TPCS_TEF             /*!< tamper event flag */
+
+/* tamper interrupt flag */
+#define BKP_INT_FLAG_TAMPER             BKP_TPCS_TIF             /*!< tamper interrupt flag */
+
+/* function declarations */
+/* reset BKP registers */
+void bkp_deinit(void);
+/* write BKP data register */
+void bkp_data_write(bkp_data_register_enum register_number, uint16_t data);
+/* read BKP data register */
+uint16_t bkp_data_read(bkp_data_register_enum register_number);
+
+/* RTC related functions */
+/* enable RTC clock calibration output */
+void bkp_rtc_calibration_output_enable(void);
+/* disable RTC clock calibration output */
+void bkp_rtc_calibration_output_disable(void);
+/* enable RTC alarm or second signal output */
+void bkp_rtc_signal_output_enable(void);
+/* disable RTC alarm or second signal output */
+void bkp_rtc_signal_output_disable(void);
+/* select RTC output */
+void bkp_rtc_output_select(uint16_t outputsel);
+/* set RTC clock calibration value */
+void bkp_rtc_calibration_value_set(uint8_t value);
+
+/* tamper pin related functions */
+/* enable tamper pin detection */
+void bkp_tamper_detection_enable(void);
+/* disable tamper pin detection */
+void bkp_tamper_detection_disable(void);
+/* set tamper pin active level */
+void bkp_tamper_active_level_set(uint16_t level);
+
+/* interrupt & flag functions */
+/* enable tamper interrupt */
+void bkp_interrupt_enable(void);
+/* disable tamper interrupt */
+void bkp_interrupt_disable(void);
+/* get tamper flag state */
+FlagStatus bkp_flag_get(void);
+/* clear tamper flag state */
+void bkp_flag_clear(void);
+/* get tamper interrupt flag state */
+FlagStatus bkp_interrupt_flag_get(void);
+/* clear tamper interrupt flag state */
+void bkp_interrupt_flag_clear(void);
+
+#endif /* GD32VF103_BKP_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_can.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_can.h
new file mode 100644
index 0000000000..db12a5f982
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_can.h
@@ -0,0 +1,717 @@
+/*!
+    \file  gd32vf103_can.h
+    \brief definitions for the CAN
+ 
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_CAN_H
+#define GD32VF103_CAN_H
+
+#include "gd32vf103.h"
+
+/* CAN definitions */
+#define CAN0                               CAN_BASE                      /*!< CAN0 base address */
+#define CAN1                               (CAN0 + 0x00000400U)          /*!< CAN1 base address */
+
+/* registers definitions */
+#define CAN_CTL(canx)                      REG32((canx) + 0x00U)         /*!< CAN control register */
+#define CAN_STAT(canx)                     REG32((canx) + 0x04U)         /*!< CAN status register */
+#define CAN_TSTAT(canx)                    REG32((canx) + 0x08U)         /*!< CAN transmit status register*/
+#define CAN_RFIFO0(canx)                   REG32((canx) + 0x0CU)         /*!< CAN receive FIFO0 register */
+#define CAN_RFIFO1(canx)                   REG32((canx) + 0x10U)         /*!< CAN receive FIFO1 register */
+#define CAN_INTEN(canx)                    REG32((canx) + 0x14U)         /*!< CAN interrupt enable register */
+#define CAN_ERR(canx)                      REG32((canx) + 0x18U)         /*!< CAN error register */
+#define CAN_BT(canx)                       REG32((canx) + 0x1CU)         /*!< CAN bit timing register */
+#define CAN_TMI0(canx)                     REG32((canx) + 0x180U)        /*!< CAN transmit mailbox0 identifier register */
+#define CAN_TMP0(canx)                     REG32((canx) + 0x184U)        /*!< CAN transmit mailbox0 property register */
+#define CAN_TMDATA00(canx)                 REG32((canx) + 0x188U)        /*!< CAN transmit mailbox0 data0 register */
+#define CAN_TMDATA10(canx)                 REG32((canx) + 0x18CU)        /*!< CAN transmit mailbox0 data1 register */
+#define CAN_TMI1(canx)                     REG32((canx) + 0x190U)        /*!< CAN transmit mailbox1 identifier register */
+#define CAN_TMP1(canx)                     REG32((canx) + 0x194U)        /*!< CAN transmit mailbox1 property register */
+#define CAN_TMDATA01(canx)                 REG32((canx) + 0x198U)        /*!< CAN transmit mailbox1 data0 register */
+#define CAN_TMDATA11(canx)                 REG32((canx) + 0x19CU)        /*!< CAN transmit mailbox1 data1 register */
+#define CAN_TMI2(canx)                     REG32((canx) + 0x1A0U)        /*!< CAN transmit mailbox2 identifier register */
+#define CAN_TMP2(canx)                     REG32((canx) + 0x1A4U)        /*!< CAN transmit mailbox2 property register */
+#define CAN_TMDATA02(canx)                 REG32((canx) + 0x1A8U)        /*!< CAN transmit mailbox2 data0 register */
+#define CAN_TMDATA12(canx)                 REG32((canx) + 0x1ACU)        /*!< CAN transmit mailbox2 data1 register */
+#define CAN_RFIFOMI0(canx)                 REG32((canx) + 0x1B0U)        /*!< CAN receive FIFO0 mailbox identifier register */
+#define CAN_RFIFOMP0(canx)                 REG32((canx) + 0x1B4U)        /*!< CAN receive FIFO0 mailbox property register */
+#define CAN_RFIFOMDATA00(canx)             REG32((canx) + 0x1B8U)        /*!< CAN receive FIFO0 mailbox data0 register */
+#define CAN_RFIFOMDATA10(canx)             REG32((canx) + 0x1BCU)        /*!< CAN receive FIFO0 mailbox data1 register */
+#define CAN_RFIFOMI1(canx)                 REG32((canx) + 0x1C0U)        /*!< CAN receive FIFO1 mailbox identifier register */
+#define CAN_RFIFOMP1(canx)                 REG32((canx) + 0x1C4U)        /*!< CAN receive FIFO1 mailbox property register */
+#define CAN_RFIFOMDATA01(canx)             REG32((canx) + 0x1C8U)        /*!< CAN receive FIFO1 mailbox data0 register */
+#define CAN_RFIFOMDATA11(canx)             REG32((canx) + 0x1CCU)        /*!< CAN receive FIFO1 mailbox data1 register */
+#define CAN_FCTL(canx)                     REG32((canx) + 0x200U)        /*!< CAN filter control register */
+#define CAN_FMCFG(canx)                    REG32((canx) + 0x204U)        /*!< CAN filter mode register */
+#define CAN_FSCFG(canx)                    REG32((canx) + 0x20CU)        /*!< CAN filter scale register */
+#define CAN_FAFIFO(canx)                   REG32((canx) + 0x214U)        /*!< CAN filter associated FIFO register */
+#define CAN_FW(canx)                       REG32((canx) + 0x21CU)        /*!< CAN filter working register */
+#define CAN_F0DATA0(canx)                  REG32((canx) + 0x240U)        /*!< CAN filter 0 data 0 register */
+#define CAN_F1DATA0(canx)                  REG32((canx) + 0x248U)        /*!< CAN filter 1 data 0 register */
+#define CAN_F2DATA0(canx)                  REG32((canx) + 0x250U)        /*!< CAN filter 2 data 0 register */
+#define CAN_F3DATA0(canx)                  REG32((canx) + 0x258U)        /*!< CAN filter 3 data 0 register */
+#define CAN_F4DATA0(canx)                  REG32((canx) + 0x260U)        /*!< CAN filter 4 data 0 register */
+#define CAN_F5DATA0(canx)                  REG32((canx) + 0x268U)        /*!< CAN filter 5 data 0 register */
+#define CAN_F6DATA0(canx)                  REG32((canx) + 0x270U)        /*!< CAN filter 6 data 0 register */
+#define CAN_F7DATA0(canx)                  REG32((canx) + 0x278U)        /*!< CAN filter 7 data 0 register */
+#define CAN_F8DATA0(canx)                  REG32((canx) + 0x280U)        /*!< CAN filter 8 data 0 register */
+#define CAN_F9DATA0(canx)                  REG32((canx) + 0x288U)        /*!< CAN filter 9 data 0 register */
+#define CAN_F10DATA0(canx)                 REG32((canx) + 0x290U)        /*!< CAN filter 10 data 0 register */
+#define CAN_F11DATA0(canx)                 REG32((canx) + 0x298U)        /*!< CAN filter 11 data 0 register */
+#define CAN_F12DATA0(canx)                 REG32((canx) + 0x2A0U)        /*!< CAN filter 12 data 0 register */
+#define CAN_F13DATA0(canx)                 REG32((canx) + 0x2A8U)        /*!< CAN filter 13 data 0 register */
+#define CAN_F14DATA0(canx)                 REG32((canx) + 0x2B0U)        /*!< CAN filter 14 data 0 register */
+#define CAN_F15DATA0(canx)                 REG32((canx) + 0x2B8U)        /*!< CAN filter 15 data 0 register */
+#define CAN_F16DATA0(canx)                 REG32((canx) + 0x2C0U)        /*!< CAN filter 16 data 0 register */
+#define CAN_F17DATA0(canx)                 REG32((canx) + 0x2C8U)        /*!< CAN filter 17 data 0 register */
+#define CAN_F18DATA0(canx)                 REG32((canx) + 0x2D0U)        /*!< CAN filter 18 data 0 register */
+#define CAN_F19DATA0(canx)                 REG32((canx) + 0x2D8U)        /*!< CAN filter 19 data 0 register */
+#define CAN_F20DATA0(canx)                 REG32((canx) + 0x2E0U)        /*!< CAN filter 20 data 0 register */
+#define CAN_F21DATA0(canx)                 REG32((canx) + 0x2E8U)        /*!< CAN filter 21 data 0 register */
+#define CAN_F22DATA0(canx)                 REG32((canx) + 0x2F0U)        /*!< CAN filter 22 data 0 register */
+#define CAN_F23DATA0(canx)                 REG32((canx) + 0x3F8U)        /*!< CAN filter 23 data 0 register */
+#define CAN_F24DATA0(canx)                 REG32((canx) + 0x300U)        /*!< CAN filter 24 data 0 register */
+#define CAN_F25DATA0(canx)                 REG32((canx) + 0x308U)        /*!< CAN filter 25 data 0 register */
+#define CAN_F26DATA0(canx)                 REG32((canx) + 0x310U)        /*!< CAN filter 26 data 0 register */
+#define CAN_F27DATA0(canx)                 REG32((canx) + 0x318U)        /*!< CAN filter 27 data 0 register */
+#define CAN_F0DATA1(canx)                  REG32((canx) + 0x244U)        /*!< CAN filter 0 data 1 register */
+#define CAN_F1DATA1(canx)                  REG32((canx) + 0x24CU)        /*!< CAN filter 1 data 1 register */
+#define CAN_F2DATA1(canx)                  REG32((canx) + 0x254U)        /*!< CAN filter 2 data 1 register */
+#define CAN_F3DATA1(canx)                  REG32((canx) + 0x25CU)        /*!< CAN filter 3 data 1 register */
+#define CAN_F4DATA1(canx)                  REG32((canx) + 0x264U)        /*!< CAN filter 4 data 1 register */
+#define CAN_F5DATA1(canx)                  REG32((canx) + 0x26CU)        /*!< CAN filter 5 data 1 register */
+#define CAN_F6DATA1(canx)                  REG32((canx) + 0x274U)        /*!< CAN filter 6 data 1 register */
+#define CAN_F7DATA1(canx)                  REG32((canx) + 0x27CU)        /*!< CAN filter 7 data 1 register */
+#define CAN_F8DATA1(canx)                  REG32((canx) + 0x284U)        /*!< CAN filter 8 data 1 register */
+#define CAN_F9DATA1(canx)                  REG32((canx) + 0x28CU)        /*!< CAN filter 9 data 1 register */
+#define CAN_F10DATA1(canx)                 REG32((canx) + 0x294U)        /*!< CAN filter 10 data 1 register */
+#define CAN_F11DATA1(canx)                 REG32((canx) + 0x29CU)        /*!< CAN filter 11 data 1 register */
+#define CAN_F12DATA1(canx)                 REG32((canx) + 0x2A4U)        /*!< CAN filter 12 data 1 register */
+#define CAN_F13DATA1(canx)                 REG32((canx) + 0x2ACU)        /*!< CAN filter 13 data 1 register */
+#define CAN_F14DATA1(canx)                 REG32((canx) + 0x2B4U)        /*!< CAN filter 14 data 1 register */
+#define CAN_F15DATA1(canx)                 REG32((canx) + 0x2BCU)        /*!< CAN filter 15 data 1 register */
+#define CAN_F16DATA1(canx)                 REG32((canx) + 0x2C4U)        /*!< CAN filter 16 data 1 register */
+#define CAN_F17DATA1(canx)                 REG32((canx) + 0x24CU)        /*!< CAN filter 17 data 1 register */
+#define CAN_F18DATA1(canx)                 REG32((canx) + 0x2D4U)        /*!< CAN filter 18 data 1 register */
+#define CAN_F19DATA1(canx)                 REG32((canx) + 0x2DCU)        /*!< CAN filter 19 data 1 register */
+#define CAN_F20DATA1(canx)                 REG32((canx) + 0x2E4U)        /*!< CAN filter 20 data 1 register */
+#define CAN_F21DATA1(canx)                 REG32((canx) + 0x2ECU)        /*!< CAN filter 21 data 1 register */
+#define CAN_F22DATA1(canx)                 REG32((canx) + 0x2F4U)        /*!< CAN filter 22 data 1 register */
+#define CAN_F23DATA1(canx)                 REG32((canx) + 0x2FCU)        /*!< CAN filter 23 data 1 register */
+#define CAN_F24DATA1(canx)                 REG32((canx) + 0x304U)        /*!< CAN filter 24 data 1 register */
+#define CAN_F25DATA1(canx)                 REG32((canx) + 0x30CU)        /*!< CAN filter 25 data 1 register */
+#define CAN_F26DATA1(canx)                 REG32((canx) + 0x314U)        /*!< CAN filter 26 data 1 register */
+#define CAN_F27DATA1(canx)                 REG32((canx) + 0x31CU)        /*!< CAN filter 27 data 1 register */
+
+/* CAN transmit mailbox bank */
+#define CAN_TMI(canx, bank)                REG32((canx) + 0x180U + ((bank) * 0x10U))        /*!< CAN transmit mailbox identifier register */
+#define CAN_TMP(canx, bank)                REG32((canx) + 0x184U + ((bank) * 0x10U))        /*!< CAN transmit mailbox property register */
+#define CAN_TMDATA0(canx, bank)            REG32((canx) + 0x188U + ((bank) * 0x10U))        /*!< CAN transmit mailbox data0 register */
+#define CAN_TMDATA1(canx, bank)            REG32((canx) + 0x18CU + ((bank) * 0x10U))        /*!< CAN transmit mailbox data1 register */
+
+/* CAN filter bank */
+#define CAN_FDATA0(canx, bank)             REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U)  /*!< CAN filter data 0 register */
+#define CAN_FDATA1(canx, bank)             REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U)  /*!< CAN filter data 1 register */
+
+/* CAN receive fifo mailbox bank */
+#define CAN_RFIFOMI(canx, bank)            REG32((canx) + 0x1B0U + ((bank) * 0x10U))        /*!< CAN receive FIFO mailbox identifier register */
+#define CAN_RFIFOMP(canx, bank)            REG32((canx) + 0x1B4U + ((bank) * 0x10U))        /*!< CAN receive FIFO mailbox property register */
+#define CAN_RFIFOMDATA0(canx, bank)        REG32((canx) + 0x1B8U + ((bank) * 0x10U))        /*!< CAN receive FIFO mailbox data0 register */
+#define CAN_RFIFOMDATA1(canx, bank)        REG32((canx) + 0x1BCU + ((bank) * 0x10U))        /*!< CAN receive FIFO mailbox data1 register */
+
+/* bits definitions */
+/* CAN_CTL */
+#define CAN_CTL_IWMOD                      BIT(0)                       /*!< initial working mode */
+#define CAN_CTL_SLPWMOD                    BIT(1)                       /*!< sleep working mode */
+#define CAN_CTL_TFO                        BIT(2)                       /*!< transmit FIFO order */
+#define CAN_CTL_RFOD                       BIT(3)                       /*!< receive FIFO overwrite disable */
+#define CAN_CTL_ARD                        BIT(4)                       /*!< automatic retransmission disable */
+#define CAN_CTL_AWU                        BIT(5)                       /*!< automatic wakeup */
+#define CAN_CTL_ABOR                       BIT(6)                       /*!< automatic bus-off recovery */
+#define CAN_CTL_TTC                        BIT(7)                       /*!< time triggered communication */
+#define CAN_CTL_SWRST                      BIT(15)                      /*!< CAN software reset */
+#define CAN_CTL_DFZ                        BIT(16)                      /*!< CAN debug freeze */
+
+/* CAN_STAT */
+#define CAN_STAT_IWS                       BIT(0)                       /*!< initial working state */
+#define CAN_STAT_SLPWS                     BIT(1)                       /*!< sleep working state */
+#define CAN_STAT_ERRIF                     BIT(2)                       /*!< error interrupt flag*/
+#define CAN_STAT_WUIF                      BIT(3)                       /*!< status change interrupt flag of wakeup from sleep working mode */
+#define CAN_STAT_SLPIF                     BIT(4)                       /*!< status change interrupt flag of sleep working mode entering */
+#define CAN_STAT_TS                        BIT(8)                       /*!< transmitting state */
+#define CAN_STAT_RS                        BIT(9)                       /*!< receiving state */
+#define CAN_STAT_LASTRX                    BIT(10)                      /*!< last sample value of rx pin */
+#define CAN_STAT_RXL                       BIT(11)                      /*!< CAN rx signal */
+
+/* CAN_TSTAT */
+#define CAN_TSTAT_MTF0                     BIT(0)                       /*!< mailbox0 transmit finished */
+#define CAN_TSTAT_MTFNERR0                 BIT(1)                       /*!< mailbox0 transmit finished and no error */
+#define CAN_TSTAT_MAL0                     BIT(2)                       /*!< mailbox0 arbitration lost */
+#define CAN_TSTAT_MTE0                     BIT(3)                       /*!< mailbox0 transmit error */
+#define CAN_TSTAT_MST0                     BIT(7)                       /*!< mailbox0 stop transmitting */
+#define CAN_TSTAT_MTF1                     BIT(8)                       /*!< mailbox1 transmit finished */
+#define CAN_TSTAT_MTFNERR1                 BIT(9)                       /*!< mailbox1 transmit finished and no error */
+#define CAN_TSTAT_MAL1                     BIT(10)                      /*!< mailbox1 arbitration lost */
+#define CAN_TSTAT_MTE1                     BIT(11)                      /*!< mailbox1 transmit error */
+#define CAN_TSTAT_MST1                     BIT(15)                      /*!< mailbox1 stop transmitting */
+#define CAN_TSTAT_MTF2                     BIT(16)                      /*!< mailbox2 transmit finished */
+#define CAN_TSTAT_MTFNERR2                 BIT(17)                      /*!< mailbox2 transmit finished and no error */
+#define CAN_TSTAT_MAL2                     BIT(18)                      /*!< mailbox2 arbitration lost */
+#define CAN_TSTAT_MTE2                     BIT(19)                      /*!< mailbox2 transmit error */
+#define CAN_TSTAT_MST2                     BIT(23)                      /*!< mailbox2 stop transmitting */
+#define CAN_TSTAT_NUM                      BITS(24,25)                  /*!< mailbox number */
+#define CAN_TSTAT_TME0                     BIT(26)                      /*!< transmit mailbox0 empty */
+#define CAN_TSTAT_TME1                     BIT(27)                      /*!< transmit mailbox1 empty */
+#define CAN_TSTAT_TME2                     BIT(28)                      /*!< transmit mailbox2 empty */
+#define CAN_TSTAT_TMLS0                    BIT(29)                      /*!< last sending priority flag for mailbox0 */
+#define CAN_TSTAT_TMLS1                    BIT(30)                      /*!< last sending priority flag for mailbox1 */
+#define CAN_TSTAT_TMLS2                    BIT(31)                      /*!< last sending priority flag for mailbox2 */
+
+/* CAN_RFIFO0 */
+#define CAN_RFIFO0_RFL0                    BITS(0,1)                    /*!< receive FIFO0 length */
+#define CAN_RFIFO0_RFF0                    BIT(3)                       /*!< receive FIFO0 full */
+#define CAN_RFIFO0_RFO0                    BIT(4)                       /*!< receive FIFO0 overfull */
+#define CAN_RFIFO0_RFD0                    BIT(5)                       /*!< receive FIFO0 dequeue */
+
+/* CAN_RFIFO1 */
+#define CAN_RFIFO1_RFL1                    BITS(0,1)                    /*!< receive FIFO1 length */
+#define CAN_RFIFO1_RFF1                    BIT(3)                       /*!< receive FIFO1 full */
+#define CAN_RFIFO1_RFO1                    BIT(4)                       /*!< receive FIFO1 overfull */
+#define CAN_RFIFO1_RFD1                    BIT(5)                       /*!< receive FIFO1 dequeue */
+
+/* CAN_INTEN */
+#define CAN_INTEN_TMEIE                    BIT(0)                       /*!< transmit mailbox empty interrupt enable */
+#define CAN_INTEN_RFNEIE0                  BIT(1)                       /*!< receive FIFO0 not empty interrupt enable */
+#define CAN_INTEN_RFFIE0                   BIT(2)                       /*!< receive FIFO0 full interrupt enable */
+#define CAN_INTEN_RFOIE0                   BIT(3)                       /*!< receive FIFO0 overfull interrupt enable */
+#define CAN_INTEN_RFNEIE1                  BIT(4)                       /*!< receive FIFO1 not empty interrupt enable */
+#define CAN_INTEN_RFFIE1                   BIT(5)                       /*!< receive FIFO1 full interrupt enable */
+#define CAN_INTEN_RFOIE1                   BIT(6)                       /*!< receive FIFO1 overfull interrupt enable */
+#define CAN_INTEN_WERRIE                   BIT(8)                       /*!< warning error interrupt enable */
+#define CAN_INTEN_PERRIE                   BIT(9)                       /*!< passive error interrupt enable */
+#define CAN_INTEN_BOIE                     BIT(10)                      /*!< bus-off interrupt enable */
+#define CAN_INTEN_ERRNIE                   BIT(11)                      /*!< error number interrupt enable */
+#define CAN_INTEN_ERRIE                    BIT(15)                      /*!< error interrupt enable */
+#define CAN_INTEN_WIE                      BIT(16)                      /*!< wakeup interrupt enable */
+#define CAN_INTEN_SLPWIE                   BIT(17)                      /*!< sleep working interrupt enable */
+
+/* CAN_ERR */
+#define CAN_ERR_WERR                       BIT(0)                       /*!< warning error */
+#define CAN_ERR_PERR                       BIT(1)                       /*!< passive error */
+#define CAN_ERR_BOERR                      BIT(2)                       /*!< bus-off error */
+#define CAN_ERR_ERRN                       BITS(4,6)                    /*!< error number */
+#define CAN_ERR_TECNT                      BITS(16,23)                  /*!< transmit error count */
+#define CAN_ERR_RECNT                      BITS(24,31)                  /*!< receive error count */
+
+/* CAN_BT */
+#define CAN_BT_BAUDPSC                     BITS(0,9)                    /*!< baudrate prescaler */
+#define CAN_BT_BS1                         BITS(16,19)                  /*!< bit segment 1 */
+#define CAN_BT_BS2                         BITS(20,22)                  /*!< bit segment 2 */
+#define CAN_BT_SJW                         BITS(24,25)                  /*!< resynchronization jump width */
+#define CAN_BT_LCMOD                       BIT(30)                      /*!< loopback communication mode */
+#define CAN_BT_SCMOD                       BIT(31)                      /*!< silent communication mode */
+
+/* CAN_TMIx */
+#define CAN_TMI_TEN                        BIT(0)                       /*!< transmit enable */
+#define CAN_TMI_FT                         BIT(1)                       /*!< frame type */
+#define CAN_TMI_FF                         BIT(2)                       /*!< frame format */
+#define CAN_TMI_EFID                       BITS(3,31)                   /*!< the frame identifier */
+#define CAN_TMI_SFID                       BITS(21,31)                  /*!< the frame identifier */
+
+/* CAN_TMPx */
+#define CAN_TMP_DLENC                      BITS(0,3)                    /*!< data length code */
+#define CAN_TMP_TSEN                       BIT(8)                       /*!< time stamp enable */
+#define CAN_TMP_TS                         BITS(16,31)                  /*!< time stamp */
+
+/* CAN_TMDATA0x */
+#define CAN_TMDATA0_DB0                    BITS(0,7)                    /*!< transmit data byte 0 */
+#define CAN_TMDATA0_DB1                    BITS(8,15)                   /*!< transmit data byte 1 */
+#define CAN_TMDATA0_DB2                    BITS(16,23)                  /*!< transmit data byte 2 */
+#define CAN_TMDATA0_DB3                    BITS(24,31)                  /*!< transmit data byte 3 */
+
+/* CAN_TMDATA1x */
+#define CAN_TMDATA1_DB4                    BITS(0,7)                    /*!< transmit data byte 4 */
+#define CAN_TMDATA1_DB5                    BITS(8,15)                   /*!< transmit data byte 5 */
+#define CAN_TMDATA1_DB6                    BITS(16,23)                  /*!< transmit data byte 6 */
+#define CAN_TMDATA1_DB7                    BITS(24,31)                  /*!< transmit data byte 7 */
+
+/* CAN_RFIFOMIx */
+#define CAN_RFIFOMI_FT                     BIT(1)                       /*!< frame type */
+#define CAN_RFIFOMI_FF                     BIT(2)                       /*!< frame format */
+#define CAN_RFIFOMI_EFID                   BITS(3,31)                   /*!< the frame identifier */
+#define CAN_RFIFOMI_SFID                   BITS(21,31)                  /*!< the frame identifier */
+
+/* CAN_RFIFOMPx */
+#define CAN_RFIFOMP_DLENC                  BITS(0,3)                    /*!< receive data length code */
+#define CAN_RFIFOMP_FI                     BITS(8,15)                   /*!< filter index */
+#define CAN_RFIFOMP_TS                     BITS(16,31)                  /*!< time stamp */
+
+/* CAN_RFIFOMDATA0x */
+#define CAN_RFIFOMDATA0_DB0                BITS(0,7)                    /*!< receive data byte 0 */
+#define CAN_RFIFOMDATA0_DB1                BITS(8,15)                   /*!< receive data byte 1 */
+#define CAN_RFIFOMDATA0_DB2                BITS(16,23)                  /*!< receive data byte 2 */
+#define CAN_RFIFOMDATA0_DB3                BITS(24,31)                  /*!< receive data byte 3 */
+
+/* CAN_RFIFOMDATA1x */
+#define CAN_RFIFOMDATA1_DB4                BITS(0,7)                    /*!< receive data byte 4 */
+#define CAN_RFIFOMDATA1_DB5                BITS(8,15)                   /*!< receive data byte 5 */
+#define CAN_RFIFOMDATA1_DB6                BITS(16,23)                  /*!< receive data byte 6 */
+#define CAN_RFIFOMDATA1_DB7                BITS(24,31)                  /*!< receive data byte 7 */
+
+/* CAN_FCTL */
+#define CAN_FCTL_FLD                       BIT(0)                       /*!< filter lock disable */
+#define CAN_FCTL_HBC1F                     BITS(8,13)                   /*!< header bank of CAN1 filter */
+
+/* CAN_FMCFG */
+#define CAN_FMCFG_FMOD(regval)             BIT(regval)                  /*!< filter mode, list or mask*/
+
+/* CAN_FSCFG */
+#define CAN_FSCFG_FS(regval)               BIT(regval)                  /*!< filter scale, 32 bits or 16 bits*/
+
+/* CAN_FAFIFO */
+#define CAN_FAFIFOR_FAF(regval)            BIT(regval)                  /*!< filter associated with FIFO */
+
+/* CAN_FW */
+#define CAN_FW_FW(regval)                  BIT(regval)                  /*!< filter working */
+
+/* CAN_FxDATAy */
+#define CAN_FDATA_FD(regval)               BIT(regval)                  /*!< filter data */
+
+/* consts definitions */
+/* define the CAN bit position and its register index offset */
+#define CAN_REGIDX_BIT(regidx, bitpos)              (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define CAN_REG_VAL(canx, offset)                   (REG32((canx) + ((uint32_t)(offset) >> 6)))
+#define CAN_BIT_POS(val)                            ((uint32_t)(val) & 0x1FU)
+
+#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1)   (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
+#define CAN_REG_VALS(canx, offset)                  (REG32((canx) + ((uint32_t)(offset) >> 12)))
+#define CAN_BIT_POS0(val)                           (((uint32_t)(val) >> 6) & 0x1FU)
+#define CAN_BIT_POS1(val)                           ((uint32_t)(val) & 0x1FU)
+
+/* register offset */
+#define STAT_REG_OFFSET                    ((uint8_t)0x04U)             /*!< STAT register offset */
+#define TSTAT_REG_OFFSET                   ((uint8_t)0x08U)             /*!< TSTAT register offset */
+#define RFIFO0_REG_OFFSET                  ((uint8_t)0x0CU)             /*!< RFIFO0 register offset */
+#define RFIFO1_REG_OFFSET                  ((uint8_t)0x10U)             /*!< RFIFO1 register offset */
+#define ERR_REG_OFFSET                     ((uint8_t)0x18U)             /*!< ERR register offset */
+
+/* CAN flags */
+typedef enum {
+	/* flags in TSTAT register */
+	CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
+	CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
+	CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
+	CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
+	CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
+	CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
+	/* flags in RFIFO0 register */
+	CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
+	CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
+	/* flags in RFIFO1 register */
+	CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
+	CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
+	/* flags in ERR register */
+	CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
+	CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
+	CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
+} can_flag_enum;
+
+/* CAN interrupt flags */
+typedef enum {
+	/* interrupt flags in STAT register */
+	CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
+	CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
+	CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */
+	/* interrupt flags in TSTAT register */
+	CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */
+	CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */
+	CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */
+	/* interrupt flags in RFIFO0 register */
+	CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */
+	CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */
+	/* interrupt flags in RFIFO0 register */
+	CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
+	CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
+} can_interrupt_flag_enum;
+
+/* CAN initiliaze parameters struct */
+typedef struct {
+	uint8_t working_mode; /*!< CAN working mode */
+	uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
+	uint8_t time_segment_1; /*!< time segment 1 */
+	uint8_t time_segment_2; /*!< time segment 2 */
+	ControlStatus time_triggered; /*!< time triggered communication mode */
+	ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
+	ControlStatus auto_wake_up; /*!< automatic wake-up mode */
+	ControlStatus auto_retrans; /*!< automatic retransmission mode disable */
+	ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
+	ControlStatus trans_fifo_order; /*!< transmit FIFO order */
+	uint16_t prescaler; /*!< baudrate prescaler */
+} can_parameter_struct;
+
+/* CAN transmit message struct */
+typedef struct {
+	uint32_t tx_sfid; /*!< standard format frame identifier */
+	uint32_t tx_efid; /*!< extended format frame identifier */
+	uint8_t tx_ff; /*!< format of frame, standard or extended format */
+	uint8_t tx_ft; /*!< type of frame, data or remote */
+	uint8_t tx_dlen; /*!< data length */
+	uint8_t tx_data[8]; /*!< transmit data */
+} can_trasnmit_message_struct;
+
+/* CAN receive message struct */
+typedef struct {
+	uint32_t rx_sfid; /*!< standard format frame identifier */
+	uint32_t rx_efid; /*!< extended format frame identifier */
+	uint8_t rx_ff; /*!< format of frame, standard or extended format */
+	uint8_t rx_ft; /*!< type of frame, data or remote */
+	uint8_t rx_dlen; /*!< data length */
+	uint8_t rx_data[8]; /*!< receive data */
+	uint8_t rx_fi; /*!< filtering index */
+} can_receive_message_struct;
+
+/* CAN filter parameters struct */
+typedef struct {
+	uint16_t filter_list_high; /*!< filter list number high bits*/
+	uint16_t filter_list_low; /*!< filter list number low bits */
+	uint16_t filter_mask_high; /*!< filter mask number high bits */
+	uint16_t filter_mask_low; /*!< filter mask number low bits */
+	uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
+	uint16_t filter_number; /*!< filter number */
+	uint16_t filter_mode; /*!< filter mode, list or mask */
+	uint16_t filter_bits; /*!< filter scale */
+	ControlStatus filter_enable; /*!< filter work or not */
+} can_filter_parameter_struct;
+
+/* CAN errors */
+typedef enum {
+	CAN_ERROR_NONE = 0, /*!< no error */
+	CAN_ERROR_FILL, /*!< fill error */
+	CAN_ERROR_FORMATE, /*!< format error */
+	CAN_ERROR_ACK, /*!< ACK error */
+	CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
+	CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
+	CAN_ERROR_CRC, /*!< CRC error */
+	CAN_ERROR_SOFTWARECFG, /*!< software configure */
+} can_error_enum;
+
+/* transmit states */
+typedef enum {
+	CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */
+	CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */
+	CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */
+	CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */
+} can_transmit_state_enum;
+
+typedef enum {
+	CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */
+	CAN_FILTER_STRUCT, /* CAN filter parameters struct */
+	CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
+	CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */
+} can_struct_type_enum;
+
+/* CAN baudrate prescaler*/
+#define BT_BAUDPSC(regval)                 (BITS(0,9) & ((uint32_t)(regval) << 0))
+
+/* CAN bit segment 1*/
+#define BT_BS1(regval)                     (BITS(16,19) & ((uint32_t)(regval) << 16))
+
+/* CAN bit segment 2*/
+#define BT_BS2(regval)                     (BITS(20,22) & ((uint32_t)(regval) << 20))
+
+/* CAN resynchronization jump width*/
+#define BT_SJW(regval)                     (BITS(24,25) & ((uint32_t)(regval) << 24))
+
+/* CAN communication mode*/
+#define BT_MODE(regval)                    (BITS(30,31) & ((uint32_t)(regval) << 30))
+
+/* CAN FDATA high 16 bits */
+#define FDATA_MASK_HIGH(regval)            (BITS(16,31) & ((uint32_t)(regval) << 16))
+
+/* CAN FDATA low 16 bits */
+#define FDATA_MASK_LOW(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0))
+
+/* CAN1 filter start bank_number*/
+#define FCTL_HBC1F(regval)                 (BITS(8,13) & ((uint32_t)(regval) << 8))
+
+/* CAN transmit mailbox extended identifier*/
+#define TMI_EFID(regval)                   (BITS(3,31) & ((uint32_t)(regval) << 3))
+
+/* CAN transmit mailbox standard identifier*/
+#define TMI_SFID(regval)                   (BITS(21,31) & ((uint32_t)(regval) << 21))
+
+/* transmit data byte 0 */
+#define TMDATA0_DB0(regval)                (BITS(0,7) & ((uint32_t)(regval) << 0))
+
+/* transmit data byte 1 */
+#define TMDATA0_DB1(regval)                (BITS(8,15) & ((uint32_t)(regval) << 8))
+
+/* transmit data byte 2 */
+#define TMDATA0_DB2(regval)                (BITS(16,23) & ((uint32_t)(regval) << 16))
+
+/* transmit data byte 3 */
+#define TMDATA0_DB3(regval)                (BITS(24,31) & ((uint32_t)(regval) << 24))
+
+/* transmit data byte 4 */
+#define TMDATA1_DB4(regval)                (BITS(0,7) & ((uint32_t)(regval) << 0))
+
+/* transmit data byte 5 */
+#define TMDATA1_DB5(regval)                (BITS(8,15) & ((uint32_t)(regval) << 8))
+
+/* transmit data byte 6 */
+#define TMDATA1_DB6(regval)                (BITS(16,23) & ((uint32_t)(regval) << 16))
+
+/* transmit data byte 7 */
+#define TMDATA1_DB7(regval)                (BITS(24,31) & ((uint32_t)(regval) << 24))
+
+/* receive mailbox extended identifier*/
+#define GET_RFIFOMI_EFID(regval)           GET_BITS((uint32_t)(regval), 3, 31)
+
+/* receive mailbox standrad identifier*/
+#define GET_RFIFOMI_SFID(regval)           GET_BITS((uint32_t)(regval), 21, 31)
+
+/* receive data length */
+#define GET_RFIFOMP_DLENC(regval)          GET_BITS((uint32_t)(regval), 0, 3)
+
+/* the index of the filter by which the frame is passed */
+#define GET_RFIFOMP_FI(regval)             GET_BITS((uint32_t)(regval), 8, 15)
+
+/* receive data byte 0 */
+#define GET_RFIFOMDATA0_DB0(regval)        GET_BITS((uint32_t)(regval), 0, 7)
+
+/* receive data byte 1 */
+#define GET_RFIFOMDATA0_DB1(regval)        GET_BITS((uint32_t)(regval), 8, 15)
+
+/* receive data byte 2 */
+#define GET_RFIFOMDATA0_DB2(regval)        GET_BITS((uint32_t)(regval), 16, 23)
+
+/* receive data byte 3 */
+#define GET_RFIFOMDATA0_DB3(regval)        GET_BITS((uint32_t)(regval), 24, 31)
+
+/* receive data byte 4 */
+#define GET_RFIFOMDATA1_DB4(regval)        GET_BITS((uint32_t)(regval), 0, 7)
+
+/* receive data byte 5 */
+#define GET_RFIFOMDATA1_DB5(regval)        GET_BITS((uint32_t)(regval), 8, 15)
+
+/* receive data byte 6 */
+#define GET_RFIFOMDATA1_DB6(regval)        GET_BITS((uint32_t)(regval), 16, 23)
+
+/* receive data byte 7 */
+#define GET_RFIFOMDATA1_DB7(regval)        GET_BITS((uint32_t)(regval), 24, 31)
+
+/* error number */
+#define GET_ERR_ERRN(regval)               GET_BITS((uint32_t)(regval), 4, 6)
+
+/* transmit error count */
+#define GET_ERR_TECNT(regval)              GET_BITS((uint32_t)(regval), 16, 23)
+
+/* receive  error count */
+#define GET_ERR_RECNT(regval)              GET_BITS((uint32_t)(regval), 24, 31)
+
+/* CAN errors */
+#define ERR_ERRN(regval)                   (BITS(4,6) & ((uint32_t)(regval) << 4))
+#define CAN_ERRN_0                         ERR_ERRN(0)                  /* no error */
+#define CAN_ERRN_1                         ERR_ERRN(1)                  /*!< fill error */
+#define CAN_ERRN_2                         ERR_ERRN(2)                  /*!< format error */
+#define CAN_ERRN_3                         ERR_ERRN(3)                  /*!< ACK error */
+#define CAN_ERRN_4                         ERR_ERRN(4)                  /*!< bit recessive error */
+#define CAN_ERRN_5                         ERR_ERRN(5)                  /*!< bit dominant error */
+#define CAN_ERRN_6                         ERR_ERRN(6)                  /*!< CRC error */
+#define CAN_ERRN_7                         ERR_ERRN(7)                  /*!< software error */
+
+#define CAN_STATE_PENDING                  ((uint32_t)0x00000000U)      /*!< CAN pending */
+
+/* CAN communication mode */
+#define CAN_NORMAL_MODE                    ((uint8_t)0x00U)             /*!< normal communication mode */
+#define CAN_LOOPBACK_MODE                  ((uint8_t)0x01U)             /*!< loopback communication mode */
+#define CAN_SILENT_MODE                    ((uint8_t)0x02U)             /*!< silent communication mode */
+#define CAN_SILENT_LOOPBACK_MODE           ((uint8_t)0x03U)             /*!< loopback and silent communication mode */
+
+/* CAN resynchronisation jump width */
+#define CAN_BT_SJW_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
+#define CAN_BT_SJW_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
+#define CAN_BT_SJW_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
+#define CAN_BT_SJW_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
+
+/* CAN time segment 1 */
+#define CAN_BT_BS1_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
+#define CAN_BT_BS1_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
+#define CAN_BT_BS1_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
+#define CAN_BT_BS1_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
+#define CAN_BT_BS1_5TQ                     ((uint8_t)0x04U)             /*!< 5 time quanta */
+#define CAN_BT_BS1_6TQ                     ((uint8_t)0x05U)             /*!< 6 time quanta */
+#define CAN_BT_BS1_7TQ                     ((uint8_t)0x06U)             /*!< 7 time quanta */
+#define CAN_BT_BS1_8TQ                     ((uint8_t)0x07U)             /*!< 8 time quanta */
+#define CAN_BT_BS1_9TQ                     ((uint8_t)0x08U)             /*!< 9 time quanta */
+#define CAN_BT_BS1_10TQ                    ((uint8_t)0x09U)             /*!< 10 time quanta */
+#define CAN_BT_BS1_11TQ                    ((uint8_t)0x0AU)             /*!< 11 time quanta */
+#define CAN_BT_BS1_12TQ                    ((uint8_t)0x0BU)             /*!< 12 time quanta */
+#define CAN_BT_BS1_13TQ                    ((uint8_t)0x0CU)             /*!< 13 time quanta */
+#define CAN_BT_BS1_14TQ                    ((uint8_t)0x0DU)             /*!< 14 time quanta */
+#define CAN_BT_BS1_15TQ                    ((uint8_t)0x0EU)             /*!< 15 time quanta */
+#define CAN_BT_BS1_16TQ                    ((uint8_t)0x0FU)             /*!< 16 time quanta */
+
+/* CAN time segment 2 */
+#define CAN_BT_BS2_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
+#define CAN_BT_BS2_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
+#define CAN_BT_BS2_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
+#define CAN_BT_BS2_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
+#define CAN_BT_BS2_5TQ                     ((uint8_t)0x04U)             /*!< 5 time quanta */
+#define CAN_BT_BS2_6TQ                     ((uint8_t)0x05U)             /*!< 6 time quanta */
+#define CAN_BT_BS2_7TQ                     ((uint8_t)0x06U)             /*!< 7 time quanta */
+#define CAN_BT_BS2_8TQ                     ((uint8_t)0x07U)             /*!< 8 time quanta */
+
+/* CAN mailbox number */
+#define CAN_MAILBOX0                       ((uint8_t)0x00U)             /*!< mailbox0 */
+#define CAN_MAILBOX1                       ((uint8_t)0x01U)             /*!< mailbox1 */
+#define CAN_MAILBOX2                       ((uint8_t)0x02U)             /*!< mailbox2 */
+#define CAN_NOMAILBOX                      ((uint8_t)0x03U)             /*!< no mailbox empty */
+
+/* CAN frame format */
+#define CAN_FF_STANDARD                    ((uint32_t)0x00000000U)      /*!< standard frame */
+#define CAN_FF_EXTENDED                    ((uint32_t)0x00000004U)      /*!< extended frame */
+
+/* CAN receive fifo */
+#define CAN_FIFO0                          ((uint8_t)0x00U)             /*!< receive FIFO0 */
+#define CAN_FIFO1                          ((uint8_t)0x01U)             /*!< receive FIFO1 */
+
+/* frame number of receive fifo */
+#define CAN_RFIF_RFL_MASK                  ((uint32_t)0x00000003U)      /*!< mask for frame number in receive FIFOx */
+
+#define CAN_SFID_MASK                      ((uint32_t)0x000007FFU)      /*!< mask of standard identifier */
+#define CAN_EFID_MASK                      ((uint32_t)0x1FFFFFFFU)      /*!< mask of extended identifier */
+
+/* CAN working mode */
+#define CAN_MODE_INITIALIZE                ((uint8_t)0x01U)             /*!< CAN initialize mode */
+#define CAN_MODE_NORMAL                    ((uint8_t)0x02U)             /*!< CAN normal mode */
+#define CAN_MODE_SLEEP                     ((uint8_t)0x04U)             /*!< CAN sleep mode */
+
+/* filter bits */
+#define CAN_FILTERBITS_16BIT               ((uint8_t)0x00U)             /*!< CAN filter 16 bits */
+#define CAN_FILTERBITS_32BIT               ((uint8_t)0x01U)             /*!< CAN filter 32 bits */
+
+/* filter mode */
+#define CAN_FILTERMODE_MASK                ((uint8_t)0x00U)             /*!< mask mode */
+#define CAN_FILTERMODE_LIST                ((uint8_t)0x01U)             /*!< list mode */
+
+/* filter 16 bits mask */
+#define CAN_FILTER_MASK_16BITS             ((uint32_t)0x0000FFFFU)      /*!< can filter 16 bits mask */
+
+/* frame type */
+#define CAN_FT_DATA                        ((uint32_t)0x00000000U)      /*!< data frame */
+#define CAN_FT_REMOTE                      ((uint32_t)0x00000002U)      /*!< remote frame */
+
+/* CAN timeout */
+#define CAN_TIMEOUT                        ((uint32_t)0x0000FFFFU)      /*!< timeout value */
+
+/* interrupt enable bits */
+#define CAN_INT_TME                        CAN_INTEN_TMEIE              /*!< transmit mailbox empty interrupt enable */
+#define CAN_INT_RFNE0                      CAN_INTEN_RFNEIE0            /*!< receive FIFO0 not empty interrupt enable */
+#define CAN_INT_RFF0                       CAN_INTEN_RFFIE0             /*!< receive FIFO0 full interrupt enable */
+#define CAN_INT_RFO0                       CAN_INTEN_RFOIE0             /*!< receive FIFO0 overfull interrupt enable */
+#define CAN_INT_RFNE1                      CAN_INTEN_RFNEIE1            /*!< receive FIFO1 not empty interrupt enable */
+#define CAN_INT_RFF1                       CAN_INTEN_RFFIE1             /*!< receive FIFO1 full interrupt enable */
+#define CAN_INT_RFO1                       CAN_INTEN_RFOIE1             /*!< receive FIFO1 overfull interrupt enable */
+#define CAN_INT_WERR                       CAN_INTEN_WERRIE             /*!< warning error interrupt enable */
+#define CAN_INT_PERR                       CAN_INTEN_PERRIE             /*!< passive error interrupt enable */
+#define CAN_INT_BO                         CAN_INTEN_BOIE               /*!< bus-off interrupt enable */
+#define CAN_INT_ERRN                       CAN_INTEN_ERRNIE             /*!< error number interrupt enable */
+#define CAN_INT_ERR                        CAN_INTEN_ERRIE              /*!< error interrupt enable */
+#define CAN_INT_WAKEUP                     CAN_INTEN_WIE                /*!< wakeup interrupt enable */
+#define CAN_INT_SLPW                       CAN_INTEN_SLPWIE             /*!< sleep working interrupt enable */
+
+/* function declarations */
+/* deinitialize CAN */
+void can_deinit(uint32_t can_periph);
+/* initialize CAN struct */
+void can_struct_para_init(can_struct_type_enum type, void* p_struct);
+/* initialize CAN */
+ErrStatus can_init(uint32_t can_periph,
+		can_parameter_struct* can_parameter_init);
+/* CAN filter init */
+void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
+/* set can1 fliter start bank number */
+void can1_filter_start_bank(uint8_t start_bank);
+/* enable functions */
+/* CAN debug freeze enable */
+void can_debug_freeze_enable(uint32_t can_periph);
+/* CAN debug freeze disable */
+void can_debug_freeze_disable(uint32_t can_periph);
+/* CAN time trigger mode enable */
+void can_time_trigger_mode_enable(uint32_t can_periph);
+/* CAN time trigger mode disable */
+void can_time_trigger_mode_disable(uint32_t can_periph);
+
+/* transmit functions */
+/* transmit CAN message */
+uint8_t can_message_transmit(uint32_t can_periph,
+		can_trasnmit_message_struct* transmit_message);
+/* get CAN transmit state */
+can_transmit_state_enum can_transmit_states(uint32_t can_periph,
+		uint8_t mailbox_number);
+/* stop CAN transmission */
+void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
+/* CAN receive message */
+void can_message_receive(uint32_t can_periph, uint8_t fifo_number,
+		can_receive_message_struct* receive_message);
+/* CAN release fifo */
+void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
+/* CAN receive message length */
+uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
+/* CAN working mode */
+ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
+/* CAN wakeup from sleep mode */
+ErrStatus can_wakeup(uint32_t can_periph);
+
+/* CAN get error */
+can_error_enum can_error_get(uint32_t can_periph);
+/* get CAN receive error number */
+uint8_t can_receive_error_number_get(uint32_t can_periph);
+/* get CAN transmit error number */
+uint8_t can_transmit_error_number_get(uint32_t can_periph);
+
+/* CAN interrupt enable */
+void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
+/* CAN interrupt disable */
+void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
+/* CAN get flag state */
+FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
+/* CAN clear flag state */
+void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
+/* CAN get interrupt flag state */
+FlagStatus can_interrupt_flag_get(uint32_t can_periph,
+		can_interrupt_flag_enum flag);
+/* CAN clear interrupt flag state */
+void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
+
+#endif /* GD32VF103_CAN_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h
new file mode 100644
index 0000000000..c86fe995b3
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h
@@ -0,0 +1,78 @@
+/*!
+    \file  gd32vf103_crc.h
+    \brief definitions for the CRC
+
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_CRC_H
+#define GD32VF103_CRC_H
+
+#include "gd32vf103.h"
+
+/* CRC definitions */
+#define CRC                            CRC_BASE
+
+/* registers definitions */
+#define CRC_DATA                       REG32(CRC + 0x00U)              /*!< CRC data register */
+#define CRC_FDATA                      REG32(CRC + 0x04U)              /*!< CRC free data register */
+#define CRC_CTL                        REG32(CRC + 0x08U)              /*!< CRC control register */
+
+/* bits definitions */
+/* CRC_DATA */
+#define CRC_DATA_DATA                  BITS(0, 31)                     /*!< CRC calculation result bits */
+
+/* CRC_FDATA */
+#define CRC_FDATA_FDATA                BITS(0, 7)                      /*!< CRC free data bits */
+
+/* CRC_CTL */
+#define CRC_CTL_RST                    BIT(0)                          /*!< CRC reset CRC_DATA register bit */
+
+/* function declarations */
+/* deinit CRC calculation unit */
+void crc_deinit(void);
+
+/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
+void crc_data_register_reset(void);
+/* read the value of the data register */
+uint32_t crc_data_register_read(void);
+
+/* read the value of the free data register */
+uint8_t crc_free_data_register_read(void);
+/* write data to the free data register */
+void crc_free_data_register_write(uint8_t free_data);
+
+/* calculate the CRC value of a 32-bit data */
+uint32_t crc_single_data_calculate(uint32_t sdata);
+/* calculate the CRC value of an array of 32-bit values */
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
+
+#endif /* GD32VF103_CRC_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h
new file mode 100644
index 0000000000..165899f226
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h
@@ -0,0 +1,242 @@
+/*!
+    \file    gd32vf103_dac.h
+    \brief   definitions for the DAC
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_DAC_H
+#define GD32VF103_DAC_H
+
+#include "gd32vf103.h"
+
+/* DACx(x=0,1) definitions */
+#define DAC                     DAC_BASE
+#define DAC0                    (0U)
+#define DAC1                    (1U)
+
+/* registers definitions */
+#define DAC_CTL                 REG32(DAC + 0x00U)   /*!< DAC control register */
+#define DAC_SWT                 REG32(DAC + 0x04U)   /*!< DAC software trigger register */
+#define DAC0_R12DH              REG32(DAC + 0x08U)   /*!< DAC0 12-bit right-aligned data holding register */
+#define DAC0_L12DH              REG32(DAC + 0x0CU)   /*!< DAC0 12-bit left-aligned data holding register */
+#define DAC0_R8DH               REG32(DAC + 0x10U)   /*!< DAC0 8-bit right-aligned data holding register */
+#define DAC1_R12DH              REG32(DAC + 0x14U)   /*!< DAC1 12-bit right-aligned data holding register */
+#define DAC1_L12DH              REG32(DAC + 0x18U)   /*!< DAC1 12-bit left-aligned data holding register */
+#define DAC1_R8DH               REG32(DAC + 0x1CU)   /*!< DAC1 8-bit right-aligned data holding register */
+#define DACC_R12DH              REG32(DAC + 0x20U)   /*!< DAC concurrent mode 12-bit right-aligned data holding register */
+#define DACC_L12DH              REG32(DAC + 0x24U)   /*!< DAC concurrent mode 12-bit left-aligned data holding register */
+#define DACC_R8DH               REG32(DAC + 0x28U)   /*!< DAC concurrent mode 8-bit right-aligned data holding register */
+#define DAC0_DO                 REG32(DAC + 0x2CU)   /*!< DAC0 data output register */
+#define DAC1_DO                 REG32(DAC + 0x30U)   /*!< DAC1 data output register */
+
+/* bits definitions */
+/* DAC_CTL */
+#define DAC_CTL_DEN0            BIT(0)               /*!< DAC0 enable/disable bit */
+#define DAC_CTL_DBOFF0          BIT(1)               /*!< DAC0 output buffer turn on/turn off bit */
+#define DAC_CTL_DTEN0           BIT(2)               /*!< DAC0 trigger enable/disable bit */
+#define DAC_CTL_DTSEL0          BITS(3,5)            /*!< DAC0 trigger source selection enable/disable bits */
+#define DAC_CTL_DWM0            BITS(6,7)            /*!< DAC0 noise wave mode */
+#define DAC_CTL_DWBW0           BITS(8,11)           /*!< DAC0 noise wave bit width */
+#define DAC_CTL_DDMAEN0         BIT(12)              /*!< DAC0 DMA enable/disable bit */
+#define DAC_CTL_DEN1            BIT(16)              /*!< DAC1 enable/disable bit */ 
+#define DAC_CTL_DBOFF1          BIT(17)              /*!< DAC1 output buffer turn on/turn off bit */
+#define DAC_CTL_DTEN1           BIT(18)              /*!< DAC1 trigger enable/disable bit */
+#define DAC_CTL_DTSEL1          BITS(19,21)          /*!< DAC1 trigger source selection enable/disable bits */
+#define DAC_CTL_DWM1            BITS(22,23)          /*!< DAC1 noise wave mode */
+#define DAC_CTL_DWBW1           BITS(24,27)          /*!< DAC1 noise wave bit width */
+#define DAC_CTL_DDMAEN1         BIT(28)              /*!< DAC1 DMA enable/disable bit */
+
+/* DAC_SWT */
+#define DAC_SWT_SWTR0           BIT(0)               /*!< DAC0 software trigger bit, cleared by hardware */
+#define DAC_SWT_SWTR1           BIT(1)               /*!< DAC1 software trigger bit, cleared by hardware */
+
+/* DAC0_R12DH */
+#define DAC0_R12DH_DAC0_DH      BITS(0,11)           /*!< DAC0 12-bit right-aligned data bits */
+
+/* DAC0_L12DH */
+#define DAC0_L12DH_DAC0_DH      BITS(4,15)           /*!< DAC0 12-bit left-aligned data bits */
+
+/* DAC0_R8DH */
+#define DAC0_R8DH_DAC0_DH       BITS(0,7)            /*!< DAC0 8-bit right-aligned data bits */
+
+/* DAC1_R12DH */
+#define DAC1_R12DH_DAC1_DH      BITS(0,11)           /*!< DAC1 12-bit right-aligned data bits */
+
+/* DAC1_L12DH */
+#define DAC1_L12DH_DAC1_DH      BITS(4,15)           /*!< DAC1 12-bit left-aligned data bits */
+
+/* DAC1_R8DH */
+#define DAC1_R8DH_DAC1_DH       BITS(0,7)            /*!< DAC1 8-bit right-aligned data bits */
+
+/* DACC_R12DH */
+#define DACC_R12DH_DAC0_DH      BITS(0,11)           /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
+#define DACC_R12DH_DAC1_DH      BITS(16,27)          /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
+
+/* DACC_L12DH */
+#define DACC_L12DH_DAC0_DH      BITS(4,15)           /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
+#define DACC_L12DH_DAC1_DH      BITS(20,31)          /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
+
+/* DACC_R8DH */
+#define DACC_R8DH_DAC0_DH       BITS(0,7)            /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
+#define DACC_R8DH_DAC1_DH       BITS(8,15)           /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
+
+/* DAC0_DO */
+#define DAC0_DO_DAC0_DO         BITS(0,11)           /*!< DAC0 12-bit output data bits */
+
+/* DAC1_DO */
+#define DAC1_DO_DAC1_DO         BITS(0,11)           /*!< DAC1 12-bit output data bits */
+
+/* constants definitions */
+/* DAC trigger source */
+#define CTL_DTSEL(regval)       (BITS(3,5) & ((uint32_t)(regval) << 3))
+#define DAC_TRIGGER_T5_TRGO     CTL_DTSEL(0)         /*!< TIMER5 TRGO */
+#define DAC_TRIGGER_T2_TRGO     CTL_DTSEL(1)         /*!< TIMER2 TRGO */
+#define DAC_TRIGGER_T6_TRGO     CTL_DTSEL(2)         /*!< TIMER6 TRGO */
+#define DAC_TRIGGER_T4_TRGO     CTL_DTSEL(3)         /*!< TIMER4 TRGO */
+#define DAC_TRIGGER_T1_TRGO     CTL_DTSEL(4)         /*!< TIMER1 TRGO */
+#define DAC_TRIGGER_T3_TRGO     CTL_DTSEL(5)         /*!< TIMER3 TRGO */
+#define DAC_TRIGGER_EXTI_9      CTL_DTSEL(6)         /*!< EXTI interrupt line9 event */
+#define DAC_TRIGGER_SOFTWARE    CTL_DTSEL(7)         /*!< software trigger */
+
+/* DAC noise wave mode */
+#define CTL_DWM(regval)         (BITS(6,7) & ((uint32_t)(regval) << 6))
+#define DAC_WAVE_DISABLE        CTL_DWM(0)           /*!< wave disable */
+#define DAC_WAVE_MODE_LFSR      CTL_DWM(1)           /*!< LFSR noise mode */
+#define DAC_WAVE_MODE_TRIANGLE  CTL_DWM(2)           /*!< triangle noise mode */
+
+/* DAC noise wave bit width */
+#define DWBW(regval)            (BITS(8,11) & ((uint32_t)(regval) << 8))
+#define DAC_WAVE_BIT_WIDTH_1    DWBW(0)              /*!< bit width of the wave signal is 1 */
+#define DAC_WAVE_BIT_WIDTH_2    DWBW(1)              /*!< bit width of the wave signal is 2 */
+#define DAC_WAVE_BIT_WIDTH_3    DWBW(2)              /*!< bit width of the wave signal is 3 */
+#define DAC_WAVE_BIT_WIDTH_4    DWBW(3)              /*!< bit width of the wave signal is 4 */
+#define DAC_WAVE_BIT_WIDTH_5    DWBW(4)              /*!< bit width of the wave signal is 5 */
+#define DAC_WAVE_BIT_WIDTH_6    DWBW(5)              /*!< bit width of the wave signal is 6 */
+#define DAC_WAVE_BIT_WIDTH_7    DWBW(6)              /*!< bit width of the wave signal is 7 */
+#define DAC_WAVE_BIT_WIDTH_8    DWBW(7)              /*!< bit width of the wave signal is 8 */
+#define DAC_WAVE_BIT_WIDTH_9    DWBW(8)              /*!< bit width of the wave signal is 9 */
+#define DAC_WAVE_BIT_WIDTH_10   DWBW(9)              /*!< bit width of the wave signal is 10 */
+#define DAC_WAVE_BIT_WIDTH_11   DWBW(10)             /*!< bit width of the wave signal is 11 */
+#define DAC_WAVE_BIT_WIDTH_12   DWBW(11)             /*!< bit width of the wave signal is 12 */
+
+/* unmask LFSR bits in DAC LFSR noise mode */
+#define DAC_LFSR_BIT0           DAC_WAVE_BIT_WIDTH_1  /*!< unmask the LFSR bit0 */
+#define DAC_LFSR_BITS1_0        DAC_WAVE_BIT_WIDTH_2  /*!< unmask the LFSR bits[1:0] */
+#define DAC_LFSR_BITS2_0        DAC_WAVE_BIT_WIDTH_3  /*!< unmask the LFSR bits[2:0] */
+#define DAC_LFSR_BITS3_0        DAC_WAVE_BIT_WIDTH_4  /*!< unmask the LFSR bits[3:0] */
+#define DAC_LFSR_BITS4_0        DAC_WAVE_BIT_WIDTH_5  /*!< unmask the LFSR bits[4:0] */
+#define DAC_LFSR_BITS5_0        DAC_WAVE_BIT_WIDTH_6  /*!< unmask the LFSR bits[5:0] */
+#define DAC_LFSR_BITS6_0        DAC_WAVE_BIT_WIDTH_7  /*!< unmask the LFSR bits[6:0] */
+#define DAC_LFSR_BITS7_0        DAC_WAVE_BIT_WIDTH_8  /*!< unmask the LFSR bits[7:0] */
+#define DAC_LFSR_BITS8_0        DAC_WAVE_BIT_WIDTH_9  /*!< unmask the LFSR bits[8:0] */
+#define DAC_LFSR_BITS9_0        DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
+#define DAC_LFSR_BITS10_0       DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
+#define DAC_LFSR_BITS11_0       DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
+
+/* DAC data alignment */
+#define DATA_ALIGN(regval)      (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define DAC_ALIGN_12B_R         DATA_ALIGN(0)        /*!< data right 12b alignment */
+#define DAC_ALIGN_12B_L         DATA_ALIGN(1)        /*!< data left  12b alignment */
+#define DAC_ALIGN_8B_R          DATA_ALIGN(2)        /*!< data right  8b alignment */
+/* triangle amplitude in DAC triangle noise mode */
+#define DAC_TRIANGLE_AMPLITUDE_1    DAC_WAVE_BIT_WIDTH_1  /*!< triangle amplitude is 1 */
+#define DAC_TRIANGLE_AMPLITUDE_3    DAC_WAVE_BIT_WIDTH_2  /*!< triangle amplitude is 3 */
+#define DAC_TRIANGLE_AMPLITUDE_7    DAC_WAVE_BIT_WIDTH_3  /*!< triangle amplitude is 7 */
+#define DAC_TRIANGLE_AMPLITUDE_15   DAC_WAVE_BIT_WIDTH_4  /*!< triangle amplitude is 15 */
+#define DAC_TRIANGLE_AMPLITUDE_31   DAC_WAVE_BIT_WIDTH_5  /*!< triangle amplitude is 31 */
+#define DAC_TRIANGLE_AMPLITUDE_63   DAC_WAVE_BIT_WIDTH_6  /*!< triangle amplitude is 63 */
+#define DAC_TRIANGLE_AMPLITUDE_127  DAC_WAVE_BIT_WIDTH_7  /*!< triangle amplitude is 127 */
+#define DAC_TRIANGLE_AMPLITUDE_255  DAC_WAVE_BIT_WIDTH_8  /*!< triangle amplitude is 255 */
+#define DAC_TRIANGLE_AMPLITUDE_511  DAC_WAVE_BIT_WIDTH_9  /*!< triangle amplitude is 511 */
+#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
+#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
+#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
+
+/* function declarations */
+/* initialization functions */
+/* deinitialize DAC */
+void dac_deinit(void);
+/* enable DAC */
+void dac_enable(uint32_t dac_periph);
+/* disable DAC */
+void dac_disable(uint32_t dac_periph);
+/* enable DAC DMA */
+void dac_dma_enable(uint32_t dac_periph);
+/* disable DAC DMA */
+void dac_dma_disable(uint32_t dac_periph); 
+/* enable DAC output buffer */
+void dac_output_buffer_enable(uint32_t dac_periph);
+/* disable DAC output buffer */
+void dac_output_buffer_disable(uint32_t dac_periph);
+/* get the last data output value */
+uint16_t dac_output_value_get(uint32_t dac_periph);
+/* set DAC data holding register value */
+void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
+
+/* DAC trigger configuration */
+/* enable DAC trigger */
+void dac_trigger_enable(uint32_t dac_periph);
+/* disable DAC trigger */
+void dac_trigger_disable(uint32_t dac_periph);
+/* configure DAC trigger source */
+void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
+/* enable DAC software trigger */
+void dac_software_trigger_enable(uint32_t dac_periph);
+/* disable DAC software trigger */
+void dac_software_trigger_disable(uint32_t dac_periph);
+
+/* DAC wave mode configuration */
+/* configure DAC wave mode */
+void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
+/* configure DAC wave bit width */
+void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
+/* configure DAC LFSR noise mode */
+void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
+/* configure DAC triangle noise mode */
+void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
+
+/* DAC concurrent mode configuration */
+/* enable DAC concurrent mode */
+void dac_concurrent_enable(void);
+/* disable DAC concurrent mode */
+void dac_concurrent_disable(void);
+/* enable DAC concurrent software trigger */
+void dac_concurrent_software_trigger_enable(void);
+/* disable DAC concurrent software trigger */
+void dac_concurrent_software_trigger_disable(void);
+/* enable DAC concurrent buffer function */
+void dac_concurrent_output_buffer_enable(void);
+/* disable DAC concurrent buffer function */
+void dac_concurrent_output_buffer_disable(void);
+/* set DAC concurrent mode data holding register value */
+void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); 
+
+#endif /* GD32VF103_DAC_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h
new file mode 100644
index 0000000000..244ca291b3
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h
@@ -0,0 +1,109 @@
+/*!
+    \file  gd32vf103_dbg.h
+    \brief definitions for the DBG
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_DBG_H
+#define GD32VF103_DBG_H
+
+#include "gd32vf103.h"
+
+/* DBG definitions */
+#define DBG                      DBG_BASE
+
+/* registers definitions */
+#define DBG_ID                   REG32(DBG + 0x00U)         /*!< DBG_ID code register */
+#define DBG_CTL                  REG32(DBG + 0x04U)         /*!< DBG control register */
+
+/* bits definitions */
+/* DBG_ID */
+#define DBG_ID_ID_CODE           BITS(0,31)                 /*!< DBG ID code values */
+
+/* DBG_CTL */
+#define DBG_CTL_SLP_HOLD         BIT(0)                     /*!< keep debugger connection during sleep mode */
+#define DBG_CTL_DSLP_HOLD        BIT(1)                     /*!< keep debugger connection during deepsleep mode */
+#define DBG_CTL_STB_HOLD         BIT(2)                     /*!< keep debugger connection during standby mode */
+#define DBG_CTL_FWDGT_HOLD       BIT(8)                     /*!< debug FWDGT kept when core is halted */
+#define DBG_CTL_WWDGT_HOLD       BIT(9)                     /*!< debug WWDGT kept when core is halted */
+#define DBG_CTL_TIMER0_HOLD      BIT(10)                    /*!< hold TIMER0 counter when core is halted */
+#define DBG_CTL_TIMER1_HOLD      BIT(11)                    /*!< hold TIMER1 counter when core is halted */
+#define DBG_CTL_TIMER2_HOLD      BIT(12)                    /*!< hold TIMER2 counter when core is halted */
+#define DBG_CTL_TIMER3_HOLD      BIT(13)                    /*!< hold TIMER3 counter when core is halted */
+#define DBG_CTL_CAN0_HOLD        BIT(14)                    /*!< debug CAN0 kept when core is halted */
+#define DBG_CTL_I2C0_HOLD        BIT(15)                    /*!< hold I2C0 smbus when core is halted */
+#define DBG_CTL_I2C1_HOLD        BIT(16)                    /*!< hold I2C1 smbus when core is halted */
+#define DBG_CTL_TIMER4_HOLD      BIT(18)                    /*!< hold TIMER4 counter when core is halted */
+#define DBG_CTL_TIMER5_HOLD      BIT(19)                    /*!< hold TIMER5 counter when core is halted */
+#define DBG_CTL_TIMER6_HOLD      BIT(20)                    /*!< hold TIMER6 counter when core is halted */
+#define DBG_CTL_CAN1_HOLD        BIT(21)                    /*!< debug CAN1 kept when core is halted */
+
+/* constants definitions */
+/* debug hold when core is halted */
+typedef enum
+{
+    DBG_FWDGT_HOLD             = BIT(8),                    /*!< debug FWDGT kept when core is halted */
+    DBG_WWDGT_HOLD             = BIT(9),                    /*!< debug WWDGT kept when core is halted */
+    DBG_TIMER0_HOLD            = BIT(10),                   /*!< hold TIMER0 counter when core is halted */
+    DBG_TIMER1_HOLD            = BIT(11),                   /*!< hold TIMER1 counter when core is halted */
+    DBG_TIMER2_HOLD            = BIT(12),                   /*!< hold TIMER2 counter when core is halted */
+    DBG_TIMER3_HOLD            = BIT(13),                   /*!< hold TIMER3 counter when core is halted */
+    DBG_CAN0_HOLD              = BIT(14),                   /*!< debug CAN0 kept when core is halted */
+    DBG_I2C0_HOLD              = BIT(15),                   /*!< hold I2C0 smbus when core is halted */
+    DBG_I2C1_HOLD              = BIT(16),                   /*!< hold I2C1 smbus when core is halted */
+    DBG_TIMER4_HOLD            = BIT(17),                   /*!< hold TIMER4 counter when core is halted */
+    DBG_TIMER5_HOLD            = BIT(18),                   /*!< hold TIMER5 counter when core is halted */
+    DBG_TIMER6_HOLD            = BIT(19),                   /*!< hold TIMER6 counter when core is halted */
+    DBG_CAN1_HOLD              = BIT(21),                   /*!< debug CAN1 kept when core is halted */
+}dbg_periph_enum;
+
+/* DBG low power mode configurations */
+#define DBG_LOW_POWER_SLEEP      DBG_CTL_SLP_HOLD           /*!< keep debugger connection during sleep mode */
+#define DBG_LOW_POWER_DEEPSLEEP  DBG_CTL_DSLP_HOLD          /*!< keep debugger connection during deepsleep mode */
+#define DBG_LOW_POWER_STANDBY    DBG_CTL_STB_HOLD           /*!< keep debugger connection during standby mode */
+
+/* function declarations */
+/* read DBG_ID code register */
+uint32_t dbg_id_get(void);
+
+/* low power behavior configuration */
+/* enable low power behavior when the MCU is in debug mode */
+void dbg_low_power_enable(uint32_t dbg_low_power);
+/* disable low power behavior when the MCU is in debug mode */
+void dbg_low_power_disable(uint32_t dbg_low_power);
+
+/* peripheral behavior configuration */
+/* enable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_enable(dbg_periph_enum dbg_periph);
+/* disable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_disable(dbg_periph_enum dbg_periph);
+
+#endif /* GD32VF103_DBG_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h
new file mode 100644
index 0000000000..ceeefe0dc8
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h
@@ -0,0 +1,282 @@
+/*!
+    \file    gd32vf103_dma.h
+    \brief   definitions for the DMA
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_DMA_H
+#define GD32VF103_DMA_H
+
+#include "gd32vf103.h"
+
+/* DMA definitions */
+#define DMA0                            (DMA_BASE)               /*!< DMA0 base address */
+#define DMA1                            (DMA_BASE + 0x0400U)     /*!< DMA1 base address */
+
+/* registers definitions */
+#define DMA_INTF(dmax)                  REG32((dmax) + 0x00U)    /*!< DMA interrupt flag register */
+#define DMA_INTC(dmax)                  REG32((dmax) + 0x04U)    /*!< DMA interrupt flag clear register */
+
+#define DMA_CH0CTL(dmax)                REG32((dmax) + 0x08U)    /*!< DMA channel 0 control register */
+#define DMA_CH0CNT(dmax)                REG32((dmax) + 0x0CU)    /*!< DMA channel 0 counter register */
+#define DMA_CH0PADDR(dmax)              REG32((dmax) + 0x10U)    /*!< DMA channel 0 peripheral base address register */
+#define DMA_CH0MADDR(dmax)              REG32((dmax) + 0x14U)    /*!< DMA channel 0 memory base address register */
+
+#define DMA_CH1CTL(dmax)                REG32((dmax) + 0x1CU)    /*!< DMA channel 1 control register */
+#define DMA_CH1CNT(dmax)                REG32((dmax) + 0x20U)    /*!< DMA channel 1 counter register */
+#define DMA_CH1PADDR(dmax)              REG32((dmax) + 0x24U)    /*!< DMA channel 1 peripheral base address register */
+#define DMA_CH1MADDR(dmax)              REG32((dmax) + 0x28U)    /*!< DMA channel 1 memory base address register */
+
+#define DMA_CH2CTL(dmax)                REG32((dmax) + 0x30U)    /*!< DMA channel 2 control register */
+#define DMA_CH2CNT(dmax)                REG32((dmax) + 0x34U)    /*!< DMA channel 2 counter register */
+#define DMA_CH2PADDR(dmax)              REG32((dmax) + 0x38U)    /*!< DMA channel 2 peripheral base address register */
+#define DMA_CH2MADDR(dmax)              REG32((dmax) + 0x3CU)    /*!< DMA channel 2 memory base address register */
+
+#define DMA_CH3CTL(dmax)                REG32((dmax) + 0x44U)    /*!< DMA channel 3 control register */
+#define DMA_CH3CNT(dmax)                REG32((dmax) + 0x48U)    /*!< DMA channel 3 counter register */
+#define DMA_CH3PADDR(dmax)              REG32((dmax) + 0x4CU)    /*!< DMA channel 3 peripheral base address register */
+#define DMA_CH3MADDR(dmax)              REG32((dmax) + 0x50U)    /*!< DMA channel 3 memory base address register */
+
+#define DMA_CH4CTL(dmax)                REG32((dmax) + 0x58U)    /*!< DMA channel 4 control register */
+#define DMA_CH4CNT(dmax)                REG32((dmax) + 0x5CU)    /*!< DMA channel 4 counter register */
+#define DMA_CH4PADDR(dmax)              REG32((dmax) + 0x60U)    /*!< DMA channel 4 peripheral base address register */
+#define DMA_CH4MADDR(dmax)              REG32((dmax) + 0x64U)    /*!< DMA channel 4 memory base address register */
+
+#define DMA_CH5CTL(dmax)                REG32((dmax) + 0x6CU)    /*!< DMA channel 5 control register */
+#define DMA_CH5CNT(dmax)                REG32((dmax) + 0x70U)    /*!< DMA channel 5 counter register */
+#define DMA_CH5PADDR(dmax)              REG32((dmax) + 0x74U)    /*!< DMA channel 5 peripheral base address register */
+#define DMA_CH5MADDR(dmax)              REG32((dmax) + 0x78U)    /*!< DMA channel 5 memory base address register */
+
+#define DMA_CH6CTL(dmax)                REG32((dmax) + 0x80U)    /*!< DMA channel 6 control register */
+#define DMA_CH6CNT(dmax)                REG32((dmax) + 0x84U)    /*!< DMA channel 6 counter register */
+#define DMA_CH6PADDR(dmax)              REG32((dmax) + 0x88U)    /*!< DMA channel 6 peripheral base address register */
+#define DMA_CH6MADDR(dmax)              REG32((dmax) + 0x8CU)    /*!< DMA channel 6 memory base address register */
+
+/* bits definitions */
+/* DMA_INTF */
+#define DMA_INTF_GIF                    BIT(0)                  /*!< global interrupt flag of channel */
+#define DMA_INTF_FTFIF                  BIT(1)                  /*!< full transfer finish flag of channel */
+#define DMA_INTF_HTFIF                  BIT(2)                  /*!< half transfer finish flag of channel */
+#define DMA_INTF_ERRIF                  BIT(3)                  /*!< error flag of channel */
+
+/* DMA_INTC */
+#define DMA_INTC_GIFC                   BIT(0)                  /*!< clear global interrupt flag of channel */
+#define DMA_INTC_FTFIFC                 BIT(1)                  /*!< clear transfer finish flag of channel */
+#define DMA_INTC_HTFIFC                 BIT(2)                  /*!< clear half transfer finish flag of channel */
+#define DMA_INTC_ERRIFC                 BIT(3)                  /*!< clear error flag of channel */
+
+/* DMA_CHxCTL, x=0..6 */
+#define DMA_CHXCTL_CHEN                 BIT(0)                  /*!< channel enable */
+#define DMA_CHXCTL_FTFIE                BIT(1)                  /*!< enable bit for channel full transfer finish interrupt */
+#define DMA_CHXCTL_HTFIE                BIT(2)                  /*!< enable bit for channel half transfer finish interrupt */
+#define DMA_CHXCTL_ERRIE                BIT(3)                  /*!< enable bit for channel error interrupt */
+#define DMA_CHXCTL_DIR                  BIT(4)                  /*!< transfer direction */
+#define DMA_CHXCTL_CMEN                 BIT(5)                  /*!< circular mode enable */
+#define DMA_CHXCTL_PNAGA                BIT(6)                  /*!< next address generation algorithm of peripheral */
+#define DMA_CHXCTL_MNAGA                BIT(7)                  /*!< next address generation algorithm of memory */
+#define DMA_CHXCTL_PWIDTH               BITS(8,9)               /*!< transfer data width of peripheral */
+#define DMA_CHXCTL_MWIDTH               BITS(10,11)             /*!< transfer data width of memory */
+#define DMA_CHXCTL_PRIO                 BITS(12,13)             /*!< priority level */
+#define DMA_CHXCTL_M2M                  BIT(14)                 /*!< memory to memory mode */
+
+/* DMA_CHxCNT, x=0..6 */
+#define DMA_CHXCNT_CNT                  BITS(0,15)              /*!< transfer counter */
+
+/* DMA_CHxPADDR, x=0..6 */
+#define DMA_CHXPADDR_PADDR              BITS(0,31)              /*!< peripheral base address */
+
+/* DMA_CHxMADDR, x=0..6 */
+#define DMA_CHXMADDR_MADDR              BITS(0,31)              /*!< memory base address */
+
+/* constants definitions */
+/* DMA channel select */
+typedef enum
+{
+    DMA_CH0 = 0,                /*!< DMA Channel0 */
+    DMA_CH1,                    /*!< DMA Channel1 */
+    DMA_CH2,                    /*!< DMA Channel2 */
+    DMA_CH3,                    /*!< DMA Channel3 */
+    DMA_CH4,                    /*!< DMA Channel4 */
+    DMA_CH5,                    /*!< DMA Channel5 */
+    DMA_CH6                     /*!< DMA Channel6 */
+} dma_channel_enum;
+
+/* DMA initialize struct */
+typedef struct
+{
+    uint32_t periph_addr;       /*!< peripheral base address */
+    uint32_t periph_width;      /*!< transfer data size of peripheral */
+    uint32_t memory_addr;       /*!< memory base address */
+    uint32_t memory_width;      /*!< transfer data size of memory */
+    uint32_t number;            /*!< channel transfer number */
+    uint32_t priority;          /*!< channel priority level */
+    uint8_t periph_inc;         /*!< peripheral increasing mode */
+    uint8_t memory_inc;         /*!< memory increasing mode */
+    uint8_t direction;          /*!< channel data transfer direction */
+
+} dma_parameter_struct;
+
+#define DMA_FLAG_ADD(flag, shift)           ((flag) << ((shift) * 4U))                      /*!< DMA channel flag shift */
+
+/* DMA_register address */
+#define DMA_CHCTL(dma, channel)             REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel))      /*!< the address of DMA channel CHXCTL register */
+#define DMA_CHCNT(dma, channel)             REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel))      /*!< the address of DMA channel CHXCNT register */
+#define DMA_CHPADDR(dma, channel)           REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel))      /*!< the address of DMA channel CHXPADDR register */
+#define DMA_CHMADDR(dma, channel)           REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel))      /*!< the address of DMA channel CHXMADDR register */
+
+/* DMA reset value */
+#define DMA_CHCTL_RESET_VALUE               ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCTL register */
+#define DMA_CHCNT_RESET_VALUE               ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCNT register */
+#define DMA_CHPADDR_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXPADDR register */
+#define DMA_CHMADDR_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXMADDR register */
+#define DMA_CHINTF_RESET_VALUE              (DMA_INTF_GIF | DMA_INTF_FTFIF | \
+                                             DMA_INTF_HTFIF | DMA_INTF_ERRIF)               /*!< clear DMA channel DMA_INTF register */
+
+/* DMA_INTF register */
+/* interrupt flag bits */
+#define DMA_INT_FLAG_G                      DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
+#define DMA_INT_FLAG_FTF                    DMA_INTF_FTFIF                                  /*!< full transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_HTF                    DMA_INTF_HTFIF                                  /*!< half transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_ERR                    DMA_INTF_ERRIF                                  /*!< error interrupt flag of channel */
+
+/* flag bits */
+#define DMA_FLAG_G                          DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
+#define DMA_FLAG_FTF                        DMA_INTF_FTFIF                                  /*!< full transfer finish flag of channel */
+#define DMA_FLAG_HTF                        DMA_INTF_HTFIF                                  /*!< half transfer finish flag of channel */
+#define DMA_FLAG_ERR                        DMA_INTF_ERRIF                                  /*!< error flag of channel */
+
+/* DMA_CHxCTL register */
+/* interrupt enable bits */
+#define DMA_INT_FTF                         DMA_CHXCTL_FTFIE                                /*!< enable bit for channel full transfer finish interrupt */
+#define DMA_INT_HTF                         DMA_CHXCTL_HTFIE                                /*!< enable bit for channel half transfer finish interrupt */
+#define DMA_INT_ERR                         DMA_CHXCTL_ERRIE                                /*!< enable bit for channel error interrupt */
+
+/* transfer direction */
+#define DMA_PERIPHERAL_TO_MEMORY            ((uint8_t)0x0000U)                         		/*!< read from peripheral and write to memory */
+#define DMA_MEMORY_TO_PERIPHERAL            ((uint8_t)0x0001U)                         		/*!< read from memory and write to peripheral */
+
+/* peripheral increasing mode */
+#define DMA_PERIPH_INCREASE_DISABLE         ((uint8_t)0x0000U)                              /*!< next address of peripheral is fixed address mode */
+#define DMA_PERIPH_INCREASE_ENABLE          ((uint8_t)0x0001U)                              /*!< next address of peripheral is increasing address mode */
+
+/* memory increasing mode */
+#define DMA_MEMORY_INCREASE_DISABLE         ((uint8_t)0x0000U)                              /*!< next address of memory is fixed address mode */
+#define DMA_MEMORY_INCREASE_ENABLE          ((uint8_t)0x0001U)                              /*!< next address of memory is increasing address mode */
+
+/* transfer data size of peripheral */
+#define CHCTL_PWIDTH(regval)                (BITS(8,9) & ((uint32_t)(regval) << 8))          /*!< transfer data size of peripheral */
+#define DMA_PERIPHERAL_WIDTH_8BIT           CHCTL_PWIDTH(0U)                                 /*!< transfer data size of peripheral is 8-bit */
+#define DMA_PERIPHERAL_WIDTH_16BIT          CHCTL_PWIDTH(1U)                                 /*!< transfer data size of peripheral is 16-bit */
+#define DMA_PERIPHERAL_WIDTH_32BIT          CHCTL_PWIDTH(2U)                                 /*!< transfer data size of peripheral is 32-bit */
+
+/* transfer data size of memory */
+#define CHCTL_MWIDTH(regval)                (BITS(10,11) & ((uint32_t)(regval) << 10))       /*!< transfer data size of memory */
+#define DMA_MEMORY_WIDTH_8BIT               CHCTL_MWIDTH(0U)                                 /*!< transfer data size of memory is 8-bit */
+#define DMA_MEMORY_WIDTH_16BIT              CHCTL_MWIDTH(1U)                                 /*!< transfer data size of memory is 16-bit */
+#define DMA_MEMORY_WIDTH_32BIT              CHCTL_MWIDTH(2U)                                 /*!< transfer data size of memory is 32-bit */
+
+/* channel priority level */
+#define CHCTL_PRIO(regval)                  (BITS(12,13) & ((uint32_t)(regval) << 12))       /*!< DMA channel priority level */
+#define DMA_PRIORITY_LOW                    CHCTL_PRIO(0U)                                   /*!< low priority */
+#define DMA_PRIORITY_MEDIUM                 CHCTL_PRIO(1U)                                   /*!< medium priority */
+#define DMA_PRIORITY_HIGH                   CHCTL_PRIO(2U)                                   /*!< high priority */
+#define DMA_PRIORITY_ULTRA_HIGH             CHCTL_PRIO(3U)                                   /*!< ultra high priority */
+
+/* memory to memory mode */
+#define DMA_MEMORY_TO_MEMORY_DISABLE        ((uint32_t)0x00000000U)                         /*!< disable memory to memory mode */
+#define DMA_MEMORY_TO_MEMORY_ENABLE         ((uint32_t)0x00000001U)                         /*!< enable memory to memory mode */
+
+/* DMA_CHxCNT register */
+/* transfer counter */
+#define DMA_CHANNEL_CNT_MASK                DMA_CHXCNT_CNT                                  /*!< transfer counter mask */
+
+/* function declarations */
+/* DMA deinitialization and initialization functions */
+/* deinitialize DMA a channel registers */
+void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
+/* initialize the parameters of DMA struct with the default values */
+void dma_struct_para_init(dma_parameter_struct* init_struct);
+/* initialize DMA channel */
+void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
+/* enable DMA circulation mode */
+void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable DMA circulation mode */
+void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable memory to memory mode */
+void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable memory to memory mode */
+void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable DMA channel */
+void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable DMA channel */
+void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
+
+/* DMA configuration functions */
+/* set DMA peripheral base address */
+void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
+/* set DMA memory base address */
+void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
+/* set the number of remaining data to be transferred by the DMA */
+void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
+/* get the number of remaining data to be transferred by the DMA */
+uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
+/* configure priority level of DMA channel */
+void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
+/* configure transfer data size of memory */
+void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
+/* configure transfer data size of peripheral */
+void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
+/* enable next address increasement algorithm of memory */
+void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable next address increasement algorithm of memory */
+void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable next address increasement algorithm of peripheral */
+void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable next address increasement algorithm of peripheral */
+void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* configure the direction of data transfer on the channel */
+void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
+
+/* flag and interrupt functions */
+/* check DMA flag is set or not */
+FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* clear the flag of a DMA channel */
+void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* check DMA flag and interrupt enable bit is set or not */
+FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* clear the interrupt flag of a DMA channel */
+void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* enable DMA interrupt */
+void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
+/* disable DMA interrupt */
+void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
+
+#endif /* GD32VF103_DMA_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h
new file mode 100644
index 0000000000..843ab4c254
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h
@@ -0,0 +1,62 @@
+/*!
+    \file  gd32vf103_eclic.h
+    \brief definitions for the ECLIC(Enhancement Core-Local Interrupt Controller)
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_ECLIC_H
+#define GD32VF103_ECLIC_H
+
+#include "gd32vf103.h"
+
+/* constants definitions */
+#define ECLIC_PRIGROUP_LEVEL0_PRIO4        0    /*!< 0 bits for level 4 bits for priority */
+#define ECLIC_PRIGROUP_LEVEL1_PRIO3        1    /*!< 1 bits for level 3 bits for priority */
+#define ECLIC_PRIGROUP_LEVEL2_PRIO2        2    /*!< 2 bits for level 2 bits for priority */
+#define ECLIC_PRIGROUP_LEVEL3_PRIO1        3    /*!< 3 bits for level 1 bits for priority */
+#define ECLIC_PRIGROUP_LEVEL4_PRIO0        4    /*!< 4 bits for level 0 bits for priority */
+
+#define __SEV           eclic_send_event
+
+/* function declarations */
+/* set the priority group */
+void eclic_priority_group_set(uint32_t prigroup);
+/* enable the interrupt request */
+void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority);
+/* disable the interrupt request */
+void eclic_irq_disable(uint32_t source);
+
+/* reset system */
+void eclic_system_reset(void);
+/* send event(SEV) */
+void eclic_send_event(void);
+
+#endif /* GD32VF103_ECLIC_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h
new file mode 100644
index 0000000000..1c72014b49
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h
@@ -0,0 +1,126 @@
+/*!
+    \file  gd32vf103_exmc.h
+    \brief definitions for the EXMC
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_EXMC_H
+#define GD32VF103_EXMC_H
+
+#include "gd32vf103.h"
+
+/* EXMC definitions */
+#define EXMC                              (EXMC_BASE)                   /*!< EXMC register base address */
+
+/* registers definitions */
+/* NOR/PSRAM */
+#define EXMC_SNCTL0                       REG32(EXMC + 0x00U)           /*!< EXMC SRAM/NOR flash control register 0 */
+#define EXMC_SNTCFG0                      REG32(EXMC + 0x04U)           /*!< EXMC SRAM/NOR flash timing configuration register 0 */
+#define EXMC_SNWTCFG0                     REG32(EXMC + 0x104U)          /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
+
+/* bits definitions */
+/* NOR/PSRAM */
+/* EXMC_SNCTLx, x=0 */
+#define EXMC_SNCTL_NRBKEN                 BIT(0)                        /*!< NOR bank enable */
+#define EXMC_SNCTL_NRMUX                  BIT(1)                        /*!< NOR bank memory address/data multiplexing */
+#define EXMC_SNCTL_NRTP                   BITS(2,3)                     /*!< NOR bank memory type */
+#define EXMC_SNCTL_NRW                    BITS(4,5)                     /*!< NOR bank memory data bus width */
+#define EXMC_SNCTL_NREN                   BIT(6)                        /*!< NOR flash access enable */
+#define EXMC_SNCTL_NRWTPOL                BIT(9)                        /*!< NWAIT signal polarity */
+#define EXMC_SNCTL_WREN                   BIT(12)                       /*!< write enable */
+#define EXMC_SNCTL_NRWTEN                 BIT(13)                       /*!< NWAIT signal enable */
+#define EXMC_SNCTL_ASYNCWAIT              BIT(15)                       /*!< asynchronous wait */
+
+/* EXMC_SNTCFGx, x=0 */
+#define EXMC_SNTCFG_ASET                  BITS(0,3)                     /*!< address setup time */
+#define EXMC_SNTCFG_AHLD                  BITS(4,7)                     /*!< address hold time */
+#define EXMC_SNTCFG_DSET                  BITS(8,15)                    /*!< data setup time */
+#define EXMC_SNTCFG_BUSLAT                BITS(16,19)                   /*!< bus latency */
+
+/* constants definitions */
+/* EXMC NOR/SRAM timing initialize struct */
+typedef struct
+{
+    uint32_t bus_latency;                                               /*!< configure the bus latency */
+    uint32_t asyn_data_setuptime;                                       /*!< configure the data setup time,asynchronous access mode valid */
+    uint32_t asyn_address_holdtime;                                     /*!< configure the address hold time,asynchronous access mode valid */
+    uint32_t asyn_address_setuptime;                                    /*!< configure the data setup time,asynchronous access mode valid */
+}exmc_norsram_timing_parameter_struct;
+
+/* EXMC NOR/SRAM initialize struct */
+typedef struct
+{
+    uint32_t norsram_region;                                            /*!< select the region of EXMC NOR/SRAM bank */
+    uint32_t asyn_wait;                                                 /*!< enable or disable the asynchronous wait function */
+    uint32_t nwait_signal;                                              /*!< enable or disable the NWAIT signal */
+    uint32_t memory_write;                                              /*!< enable or disable the write operation */
+    uint32_t nwait_polarity;                                            /*!< specifies the polarity of NWAIT signal from memory */
+    uint32_t databus_width;                                             /*!< specifies the databus width of external memory */
+    uint32_t memory_type;                                               /*!< specifies the type of external memory */
+    uint32_t address_data_mux;                                          /*!< specifies whether the data bus and address bus are multiplexed */
+    exmc_norsram_timing_parameter_struct* read_write_timing;            /*!< timing parameters for read and write */
+}exmc_norsram_parameter_struct;
+
+/* EXMC register address */
+#define EXMC_SNCTL(region)                REG32(EXMC + 0x08U * (region))                  /*!< EXMC SRAM/NOR flash control register */
+#define EXMC_SNTCFG(region)               REG32(EXMC + 0x04U + 0x08U * (region))          /*!< EXMC SRAM/NOR flash timing configuration register */
+
+/* NOR bank memory data bus width */
+#define SNCTL_NRW(regval)                 (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define EXMC_NOR_DATABUS_WIDTH_8B         SNCTL_NRW(0)                  /*!< NOR data width 8 bits */
+#define EXMC_NOR_DATABUS_WIDTH_16B        SNCTL_NRW(1)                  /*!< NOR data width 16 bits */
+
+/* NOR bank memory type */
+#define SNCTL_NRTP(regval)                (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define EXMC_MEMORY_TYPE_SRAM             SNCTL_NRTP(0)                 /*!< SRAM,ROM */
+#define EXMC_MEMORY_TYPE_PSRAM            SNCTL_NRTP(1)                 /*!< PSRAM,CRAM */
+#define EXMC_MEMORY_TYPE_NOR              SNCTL_NRTP(2)                 /*!< NOR flash */
+
+/* EXMC NOR/SRAM bank region definition */
+#define EXMC_BANK0_NORSRAM_REGION0        ((uint32_t)0x00000000U)       /*!< bank0 NOR/SRAM region0 */
+
+/* EXMC NWAIT signal polarity configuration */
+#define EXMC_NWAIT_POLARITY_LOW           ((uint32_t)0x00000000U)       /*!< low level is active of NWAIT */
+#define EXMC_NWAIT_POLARITY_HIGH          ((uint32_t)0x00000200U)       /*!< high level is active of NWAIT */
+
+/* function declarations */
+/* deinitialize EXMC NOR/SRAM region */
+void exmc_norsram_deinit(uint32_t norsram_region);
+/* exmc_norsram_parameter_struct parameter initialize */
+void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
+/* initialize EXMC NOR/SRAM region */
+void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
+/* EXMC NOR/SRAM bank enable */
+void exmc_norsram_enable(uint32_t norsram_region);
+/* EXMC NOR/SRAM bank disable */
+void exmc_norsram_disable(uint32_t norsram_region);
+
+#endif /* GD32VF103_EXMC_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h
new file mode 100644
index 0000000000..3a0d90901c
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h
@@ -0,0 +1,244 @@
+/*!
+    \file    gd32vf103_exti.h
+    \brief   definitions for the EXTI
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_EXTI_H
+#define GD32VF103_EXTI_H
+
+#include "gd32vf103.h"
+
+/* EXTI definitions */
+#define EXTI                         EXTI_BASE
+
+/* registers definitions */
+#define EXTI_INTEN                   REG32(EXTI + 0x00U)      /*!< interrupt enable register */
+#define EXTI_EVEN                    REG32(EXTI + 0x04U)      /*!< event enable register */
+#define EXTI_RTEN                    REG32(EXTI + 0x08U)      /*!< rising edge trigger enable register */
+#define EXTI_FTEN                    REG32(EXTI + 0x0CU)      /*!< falling trigger enable register */
+#define EXTI_SWIEV                   REG32(EXTI + 0x10U)      /*!< software interrupt event register */
+#define EXTI_PD                      REG32(EXTI + 0x14U)      /*!< pending register */
+
+/* bits definitions */
+/* EXTI_INTEN */
+#define EXTI_INTEN_INTEN0            BIT(0)                   /*!< interrupt from line 0 */
+#define EXTI_INTEN_INTEN1            BIT(1)                   /*!< interrupt from line 1 */
+#define EXTI_INTEN_INTEN2            BIT(2)                   /*!< interrupt from line 2 */
+#define EXTI_INTEN_INTEN3            BIT(3)                   /*!< interrupt from line 3 */
+#define EXTI_INTEN_INTEN4            BIT(4)                   /*!< interrupt from line 4 */
+#define EXTI_INTEN_INTEN5            BIT(5)                   /*!< interrupt from line 5 */
+#define EXTI_INTEN_INTEN6            BIT(6)                   /*!< interrupt from line 6 */
+#define EXTI_INTEN_INTEN7            BIT(7)                   /*!< interrupt from line 7 */
+#define EXTI_INTEN_INTEN8            BIT(8)                   /*!< interrupt from line 8 */
+#define EXTI_INTEN_INTEN9            BIT(9)                   /*!< interrupt from line 9 */
+#define EXTI_INTEN_INTEN10           BIT(10)                  /*!< interrupt from line 10 */
+#define EXTI_INTEN_INTEN11           BIT(11)                  /*!< interrupt from line 11 */
+#define EXTI_INTEN_INTEN12           BIT(12)                  /*!< interrupt from line 12 */
+#define EXTI_INTEN_INTEN13           BIT(13)                  /*!< interrupt from line 13 */
+#define EXTI_INTEN_INTEN14           BIT(14)                  /*!< interrupt from line 14 */
+#define EXTI_INTEN_INTEN15           BIT(15)                  /*!< interrupt from line 15 */
+#define EXTI_INTEN_INTEN16           BIT(16)                  /*!< interrupt from line 16 */
+#define EXTI_INTEN_INTEN17           BIT(17)                  /*!< interrupt from line 17 */
+#define EXTI_INTEN_INTEN18           BIT(18)                  /*!< interrupt from line 18 */
+
+/* EXTI_EVEN */
+#define EXTI_EVEN_EVEN0              BIT(0)                   /*!< event from line 0 */
+#define EXTI_EVEN_EVEN1              BIT(1)                   /*!< event from line 1 */
+#define EXTI_EVEN_EVEN2              BIT(2)                   /*!< event from line 2 */
+#define EXTI_EVEN_EVEN3              BIT(3)                   /*!< event from line 3 */
+#define EXTI_EVEN_EVEN4              BIT(4)                   /*!< event from line 4 */
+#define EXTI_EVEN_EVEN5              BIT(5)                   /*!< event from line 5 */
+#define EXTI_EVEN_EVEN6              BIT(6)                   /*!< event from line 6 */
+#define EXTI_EVEN_EVEN7              BIT(7)                   /*!< event from line 7 */
+#define EXTI_EVEN_EVEN8              BIT(8)                   /*!< event from line 8 */
+#define EXTI_EVEN_EVEN9              BIT(9)                   /*!< event from line 9 */
+#define EXTI_EVEN_EVEN10             BIT(10)                  /*!< event from line 10 */
+#define EXTI_EVEN_EVEN11             BIT(11)                  /*!< event from line 11 */
+#define EXTI_EVEN_EVEN12             BIT(12)                  /*!< event from line 12 */
+#define EXTI_EVEN_EVEN13             BIT(13)                  /*!< event from line 13 */
+#define EXTI_EVEN_EVEN14             BIT(14)                  /*!< event from line 14 */
+#define EXTI_EVEN_EVEN15             BIT(15)                  /*!< event from line 15 */
+#define EXTI_EVEN_EVEN16             BIT(16)                  /*!< event from line 16 */
+#define EXTI_EVEN_EVEN17             BIT(17)                  /*!< event from line 17 */
+#define EXTI_EVEN_EVEN18             BIT(18)                  /*!< event from line 18 */
+
+/* EXTI_RTEN */
+#define EXTI_RTEN_RTEN0              BIT(0)                   /*!< rising edge from line 0 */
+#define EXTI_RTEN_RTEN1              BIT(1)                   /*!< rising edge from line 1 */
+#define EXTI_RTEN_RTEN2              BIT(2)                   /*!< rising edge from line 2 */
+#define EXTI_RTEN_RTEN3              BIT(3)                   /*!< rising edge from line 3 */
+#define EXTI_RTEN_RTEN4              BIT(4)                   /*!< rising edge from line 4 */
+#define EXTI_RTEN_RTEN5              BIT(5)                   /*!< rising edge from line 5 */
+#define EXTI_RTEN_RTEN6              BIT(6)                   /*!< rising edge from line 6 */
+#define EXTI_RTEN_RTEN7              BIT(7)                   /*!< rising edge from line 7 */
+#define EXTI_RTEN_RTEN8              BIT(8)                   /*!< rising edge from line 8 */
+#define EXTI_RTEN_RTEN9              BIT(9)                   /*!< rising edge from line 9 */
+#define EXTI_RTEN_RTEN10             BIT(10)                  /*!< rising edge from line 10 */
+#define EXTI_RTEN_RTEN11             BIT(11)                  /*!< rising edge from line 11 */
+#define EXTI_RTEN_RTEN12             BIT(12)                  /*!< rising edge from line 12 */
+#define EXTI_RTEN_RTEN13             BIT(13)                  /*!< rising edge from line 13 */
+#define EXTI_RTEN_RTEN14             BIT(14)                  /*!< rising edge from line 14 */
+#define EXTI_RTEN_RTEN15             BIT(15)                  /*!< rising edge from line 15 */
+#define EXTI_RTEN_RTEN16             BIT(16)                  /*!< rising edge from line 16 */
+#define EXTI_RTEN_RTEN17             BIT(17)                  /*!< rising edge from line 17 */
+#define EXTI_RTEN_RTEN18             BIT(18)                  /*!< rising edge from line 18 */
+
+/* EXTI_FTEN */
+#define EXTI_FTEN_FTEN0              BIT(0)                   /*!< falling edge from line 0 */
+#define EXTI_FTEN_FTEN1              BIT(1)                   /*!< falling edge from line 1 */
+#define EXTI_FTEN_FTEN2              BIT(2)                   /*!< falling edge from line 2 */
+#define EXTI_FTEN_FTEN3              BIT(3)                   /*!< falling edge from line 3 */
+#define EXTI_FTEN_FTEN4              BIT(4)                   /*!< falling edge from line 4 */
+#define EXTI_FTEN_FTEN5              BIT(5)                   /*!< falling edge from line 5 */
+#define EXTI_FTEN_FTEN6              BIT(6)                   /*!< falling edge from line 6 */
+#define EXTI_FTEN_FTEN7              BIT(7)                   /*!< falling edge from line 7 */
+#define EXTI_FTEN_FTEN8              BIT(8)                   /*!< falling edge from line 8 */
+#define EXTI_FTEN_FTEN9              BIT(9)                   /*!< falling edge from line 9 */
+#define EXTI_FTEN_FTEN10             BIT(10)                  /*!< falling edge from line 10 */
+#define EXTI_FTEN_FTEN11             BIT(11)                  /*!< falling edge from line 11 */
+#define EXTI_FTEN_FTEN12             BIT(12)                  /*!< falling edge from line 12 */
+#define EXTI_FTEN_FTEN13             BIT(13)                  /*!< falling edge from line 13 */
+#define EXTI_FTEN_FTEN14             BIT(14)                  /*!< falling edge from line 14 */
+#define EXTI_FTEN_FTEN15             BIT(15)                  /*!< falling edge from line 15 */
+#define EXTI_FTEN_FTEN16             BIT(16)                  /*!< falling edge from line 16 */
+#define EXTI_FTEN_FTEN17             BIT(17)                  /*!< falling edge from line 17 */
+#define EXTI_FTEN_FTEN18             BIT(18)                  /*!< falling edge from line 18 */
+
+/* EXTI_SWIEV */
+#define EXTI_SWIEV_SWIEV0            BIT(0)                   /*!< software interrupt/event request from line 0 */
+#define EXTI_SWIEV_SWIEV1            BIT(1)                   /*!< software interrupt/event request from line 1 */
+#define EXTI_SWIEV_SWIEV2            BIT(2)                   /*!< software interrupt/event request from line 2 */
+#define EXTI_SWIEV_SWIEV3            BIT(3)                   /*!< software interrupt/event request from line 3 */
+#define EXTI_SWIEV_SWIEV4            BIT(4)                   /*!< software interrupt/event request from line 4 */
+#define EXTI_SWIEV_SWIEV5            BIT(5)                   /*!< software interrupt/event request from line 5 */
+#define EXTI_SWIEV_SWIEV6            BIT(6)                   /*!< software interrupt/event request from line 6 */
+#define EXTI_SWIEV_SWIEV7            BIT(7)                   /*!< software interrupt/event request from line 7 */
+#define EXTI_SWIEV_SWIEV8            BIT(8)                   /*!< software interrupt/event request from line 8 */
+#define EXTI_SWIEV_SWIEV9            BIT(9)                   /*!< software interrupt/event request from line 9 */
+#define EXTI_SWIEV_SWIEV10           BIT(10)                  /*!< software interrupt/event request from line 10 */
+#define EXTI_SWIEV_SWIEV11           BIT(11)                  /*!< software interrupt/event request from line 11 */
+#define EXTI_SWIEV_SWIEV12           BIT(12)                  /*!< software interrupt/event request from line 12 */
+#define EXTI_SWIEV_SWIEV13           BIT(13)                  /*!< software interrupt/event request from line 13 */
+#define EXTI_SWIEV_SWIEV14           BIT(14)                  /*!< software interrupt/event request from line 14 */
+#define EXTI_SWIEV_SWIEV15           BIT(15)                  /*!< software interrupt/event request from line 15 */
+#define EXTI_SWIEV_SWIEV16           BIT(16)                  /*!< software interrupt/event request from line 16 */
+#define EXTI_SWIEV_SWIEV17           BIT(17)                  /*!< software interrupt/event request from line 17 */
+#define EXTI_SWIEV_SWIEV18           BIT(18)                  /*!< software interrupt/event request from line 18 */
+
+/* EXTI_PD */
+#define EXTI_PD_PD0                  BIT(0)                   /*!< interrupt/event pending status from line 0 */
+#define EXTI_PD_PD1                  BIT(1)                   /*!< interrupt/event pending status from line 1 */
+#define EXTI_PD_PD2                  BIT(2)                   /*!< interrupt/event pending status from line 2 */
+#define EXTI_PD_PD3                  BIT(3)                   /*!< interrupt/event pending status from line 3 */
+#define EXTI_PD_PD4                  BIT(4)                   /*!< interrupt/event pending status from line 4 */
+#define EXTI_PD_PD5                  BIT(5)                   /*!< interrupt/event pending status from line 5 */
+#define EXTI_PD_PD6                  BIT(6)                   /*!< interrupt/event pending status from line 6 */
+#define EXTI_PD_PD7                  BIT(7)                   /*!< interrupt/event pending status from line 7 */
+#define EXTI_PD_PD8                  BIT(8)                   /*!< interrupt/event pending status from line 8 */
+#define EXTI_PD_PD9                  BIT(9)                   /*!< interrupt/event pending status from line 9 */
+#define EXTI_PD_PD10                 BIT(10)                  /*!< interrupt/event pending status from line 10 */
+#define EXTI_PD_PD11                 BIT(11)                  /*!< interrupt/event pending status from line 11 */
+#define EXTI_PD_PD12                 BIT(12)                  /*!< interrupt/event pending status from line 12 */
+#define EXTI_PD_PD13                 BIT(13)                  /*!< interrupt/event pending status from line 13 */
+#define EXTI_PD_PD14                 BIT(14)                  /*!< interrupt/event pending status from line 14 */
+#define EXTI_PD_PD15                 BIT(15)                  /*!< interrupt/event pending status from line 15 */
+#define EXTI_PD_PD16                 BIT(16)                  /*!< interrupt/event pending status from line 16 */
+#define EXTI_PD_PD17                 BIT(17)                  /*!< interrupt/event pending status from line 17 */
+#define EXTI_PD_PD18                 BIT(18)                  /*!< interrupt/event pending status from line 18 */
+
+/* constants definitions */
+/* EXTI line number */
+typedef enum {
+    EXTI_0 = BIT(0),                                          /*!< EXTI line 0 */
+    EXTI_1 = BIT(1),                                          /*!< EXTI line 1 */
+    EXTI_2 = BIT(2),                                          /*!< EXTI line 2 */
+    EXTI_3 = BIT(3),                                          /*!< EXTI line 3 */
+    EXTI_4 = BIT(4),                                          /*!< EXTI line 4 */
+    EXTI_5 = BIT(5),                                          /*!< EXTI line 5 */
+    EXTI_6 = BIT(6),                                          /*!< EXTI line 6 */
+    EXTI_7 = BIT(7),                                          /*!< EXTI line 7 */
+    EXTI_8 = BIT(8),                                          /*!< EXTI line 8 */
+    EXTI_9 = BIT(9),                                          /*!< EXTI line 9 */
+    EXTI_10 = BIT(10),                                        /*!< EXTI line 10 */
+    EXTI_11 = BIT(11),                                        /*!< EXTI line 11 */
+    EXTI_12 = BIT(12),                                        /*!< EXTI line 12 */
+    EXTI_13 = BIT(13),                                        /*!< EXTI line 13 */
+    EXTI_14 = BIT(14),                                        /*!< EXTI line 14 */
+    EXTI_15 = BIT(15),                                        /*!< EXTI line 15 */
+    EXTI_16 = BIT(16),                                        /*!< EXTI line 16 */
+    EXTI_17 = BIT(17),                                        /*!< EXTI line 17 */
+    EXTI_18 = BIT(18),                                        /*!< EXTI line 18 */
+} exti_line_enum;
+
+/* external interrupt and event  */
+typedef enum {
+    EXTI_INTERRUPT = 0,                                       /*!< EXTI interrupt mode */
+    EXTI_EVENT                                                /*!< EXTI event mode */
+} exti_mode_enum;
+
+/* interrupt trigger mode */
+typedef enum {
+    EXTI_TRIG_RISING = 0,                                     /*!< EXTI rising edge trigger */
+    EXTI_TRIG_FALLING,                                        /*!< EXTI falling edge trigger */
+    EXTI_TRIG_BOTH                                            /*!< EXTI rising edge and falling edge trigger */
+} exti_trig_type_enum;
+
+/* function declarations */
+/* initialization, EXTI lines configuration functions */
+/* deinitialize the EXTI */
+void exti_deinit(void);
+/* enable the configuration of EXTI initialize */
+void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
+/* enable the interrupts from EXTI line x */
+void exti_interrupt_enable(exti_line_enum linex);
+/* enable the events from EXTI line x */
+void exti_event_enable(exti_line_enum linex);
+/* disable the interrupts from EXTI line x */
+void exti_interrupt_disable(exti_line_enum linex);
+/* disable the events from EXTI line x */
+void exti_event_disable(exti_line_enum linex);
+
+/* interrupt & flag functions */
+/* get EXTI lines pending flag */
+FlagStatus exti_flag_get(exti_line_enum linex);
+/* clear EXTI lines pending flag */
+void exti_flag_clear(exti_line_enum linex);
+/* get EXTI lines flag when the interrupt flag is set */
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
+/* clear EXTI lines pending flag */
+void exti_interrupt_flag_clear(exti_line_enum linex);
+/* enable the EXTI software interrupt event  */
+void exti_software_interrupt_enable(exti_line_enum linex);
+/* disable the EXTI software interrupt event  */
+void exti_software_interrupt_disable(exti_line_enum linex);
+
+#endif /* GD32VF103_EXTI_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h
new file mode 100644
index 0000000000..2e6693ab76
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h
@@ -0,0 +1,311 @@
+/*!
+    \file  gd32vf103_fmc.h
+    \brief definitions for the FMC
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_FMC_H
+#define GD32VF103_FMC_H
+
+#include "gd32vf103.h"
+
+/* FMC and option byte definition */
+#define FMC                        FMC_BASE                        /*!< FMC register base address */
+#define OB                         OB_BASE                         /*!< option bytes base address */
+
+/* registers definitions */
+#define FMC_WS                     REG32((FMC) + 0x00U)            /*!< FMC wait state register */
+#define FMC_KEY0                   REG32((FMC) + 0x04U)            /*!< FMC unlock key register 0 */
+#define FMC_OBKEY                  REG32((FMC) + 0x08U)            /*!< FMC option bytes unlock key register */
+#define FMC_STAT0                  REG32((FMC) + 0x0CU)            /*!< FMC status register 0 */
+#define FMC_CTL0                   REG32((FMC) + 0x10U)            /*!< FMC control register 0 */
+#define FMC_ADDR0                  REG32((FMC) + 0x14U)            /*!< FMC address register 0 */
+#define FMC_OBSTAT                 REG32((FMC) + 0x1CU)            /*!< FMC option bytes status register */
+#define FMC_WP                     REG32((FMC) + 0x20U)            /*!< FMC erase/program protection register */
+#define FMC_PID                    REG32((FMC) + 0x100U)           /*!< FMC product ID register */
+
+#define OB_SPC                     REG16((OB) + 0x00U)             /*!< option byte security protection value */
+#define OB_USER                    REG16((OB) + 0x02U)             /*!< option byte user value*/
+#define OB_WP0                     REG16((OB) + 0x08U)             /*!< option byte write protection 0 */
+#define OB_WP1                     REG16((OB) + 0x0AU)             /*!< option byte write protection 1 */
+#define OB_WP2                     REG16((OB) + 0x0CU)             /*!< option byte write protection 2 */
+#define OB_WP3                     REG16((OB) + 0x0EU)             /*!< option byte write protection 3 */
+
+/* bits definitions */
+/* FMC_WS */
+#define FMC_WS_WSCNT               BITS(0,2)                       /*!< wait state counter */
+
+/* FMC_KEY0 */
+#define FMC_KEY0_KEY               BITS(0,31)                      /*!< FMC_CTL0 unlock key bits */
+
+/* FMC_OBKEY */
+#define FMC_OBKEY_OBKEY            BITS(0,31)                      /*!< option bytes unlock key bits */
+
+/* FMC_STAT0 */
+#define FMC_STAT0_BUSY             BIT(0)                          /*!< flash busy flag bit */
+#define FMC_STAT0_PGERR            BIT(2)                          /*!< flash program error flag bit */
+#define FMC_STAT0_WPERR            BIT(4)                          /*!< erase/program protection error flag bit */
+#define FMC_STAT0_ENDF             BIT(5)                          /*!< end of operation flag bit */
+
+/* FMC_CTL0 */
+#define FMC_CTL0_PG                BIT(0)                          /*!< main flash program for bank0 command bit */
+#define FMC_CTL0_PER               BIT(1)                          /*!< main flash page erase for bank0 command bit */
+#define FMC_CTL0_MER               BIT(2)                          /*!< main flash mass erase for bank0 command bit */
+#define FMC_CTL0_OBPG              BIT(4)                          /*!< option bytes program command bit */
+#define FMC_CTL0_OBER              BIT(5)                          /*!< option bytes erase command bit */
+#define FMC_CTL0_START             BIT(6)                          /*!< send erase command to FMC bit */
+#define FMC_CTL0_LK                BIT(7)                          /*!< FMC_CTL0 lock bit */
+#define FMC_CTL0_OBWEN             BIT(9)                          /*!< option bytes erase/program enable bit */
+#define FMC_CTL0_ERRIE             BIT(10)                         /*!< error interrupt enable bit */
+#define FMC_CTL0_ENDIE             BIT(12)                         /*!< end of operation interrupt enable bit */
+
+/* FMC_ADDR0 */
+#define FMC_ADDR0_ADDR             BITS(0,31)                      /*!< Flash erase/program command address bits */
+
+/* FMC_OBSTAT */
+#define FMC_OBSTAT_OBERR           BIT(0)                          /*!< option bytes read error bit. */
+#define FMC_OBSTAT_SPC             BIT(1)                          /*!< option bytes security protection code */
+#define FMC_OBSTAT_USER            BITS(2,9)                       /*!< store USER of option bytes block after system reset */
+#define FMC_OBSTAT_DATA            BITS(10,25)                     /*!< store DATA of option bytes block after system reset. */
+
+/* FMC_WP */
+#define FMC_WP_WP                  BITS(0,31)                      /*!< store WP of option bytes block after system reset */
+
+/* FMC_WSEN */
+#define FMC_WSEN_WSEN              BIT(0)                          /*!< FMC wait state enable bit */
+
+/* FMC_PID */
+#define FMC_PID_PID                BITS(0,31)                      /*!< product ID bits */
+
+/* constants definitions */
+/* define the FMC bit position and its register index offset */
+#define FMC_REGIDX_BIT(regidx, bitpos)              (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define FMC_REG_VAL(offset)                         (REG32(FMC + ((uint32_t)(offset) >> 6)))
+#define FMC_BIT_POS(val)                            ((uint32_t)(val) & 0x1FU)
+#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1)   (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
+#define FMC_REG_VALS(offset)                        (REG32(FMC + ((uint32_t)(offset) >> 12)))
+#define FMC_BIT_POS0(val)                           (((uint32_t)(val) >> 6) & 0x1FU)
+#define FMC_BIT_POS1(val)                           ((uint32_t)(val) & 0x1FU)
+#define FMC_REG_OFFSET_GET(flag)                    ((uint32_t)(flag) >> 12)
+
+/* configuration register */
+#define FMC_STAT0_REG_OFFSET       0x0CU                          /*!< status register 0 offset */
+#define FMC_CTL0_REG_OFFSET        0x10U                          /*!< control register 0 offset */
+#define FMC_OBSTAT_REG_OFFSET      0x1CU                          /*!< option byte status register offset */
+
+/* fmc state */
+typedef enum
+{
+    FMC_READY,                                                    /*!< the operation has been completed */
+    FMC_BUSY,                                                     /*!< the operation is in progress */
+    FMC_PGERR,                                                    /*!< program error */
+    FMC_WPERR,                                                    /*!< erase/program protection error */
+    FMC_TOERR,                                                    /*!< timeout error */
+}fmc_state_enum;
+
+/* FMC interrupt enable */
+typedef enum
+{
+    FMC_INT_END     = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U),            /*!< enable FMC end of program interrupt */
+    FMC_INT_ERR     = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U),            /*!< enable FMC error interrupt */
+}fmc_int_enum;
+
+/* FMC flags */
+typedef enum
+{
+    FMC_FLAG_BUSY   = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U),                  /*!< FMC busy flag */
+    FMC_FLAG_PGERR  = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U),                  /*!< FMC operation error flag bit */
+    FMC_FLAG_WPERR  = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U),                  /*!< FMC erase/program protection error flag bit */
+    FMC_FLAG_END    = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U),                  /*!< FMC end of operation flag bit */
+    FMC_FLAG_OBERR  = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U),                 /*!< FMC option bytes read error flag */
+}fmc_flag_enum;
+
+/* FMC interrupt flags */
+typedef enum
+{
+    FMC_INT_FLAG_PGERR  = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U),  /*!< FMC operation error interrupt flag bit */
+    FMC_INT_FLAG_WPERR  = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U),  /*!< FMC erase/program protection error interrupt flag bit */
+    FMC_INT_FLAG_END    = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U),  /*!< FMC end of operation interrupt flag bit */
+}fmc_interrupt_flag_enum;
+
+/* unlock key */
+#define UNLOCK_KEY0                ((uint32_t)0x45670123U)        /*!< unlock key 0 */
+#define UNLOCK_KEY1                ((uint32_t)0xCDEF89ABU)        /*!< unlock key 1 */
+
+/* FMC wait state counter */
+#define WS_WSCNT(regval)           (BITS(0,2) & ((uint32_t)(regval)))
+#define WS_WSCNT_0                 WS_WSCNT(0)                    /*!< FMC 0 wait */
+#define WS_WSCNT_1                 WS_WSCNT(1)                    /*!< FMC 1 wait */
+#define WS_WSCNT_2                 WS_WSCNT(2)                    /*!< FMC 2 wait */
+
+/* option bytes software/hardware free watch dog timer */  
+#define OB_FWDGT_SW                ((uint8_t)0x01U)               /*!< software free watchdog */
+#define OB_FWDGT_HW                ((uint8_t)0x00U)               /*!< hardware free watchdog */
+
+/* option bytes reset or not entering deep sleep mode */
+#define OB_DEEPSLEEP_NRST          ((uint8_t)0x02U)               /*!< no reset when entering deepsleep mode */
+#define OB_DEEPSLEEP_RST           ((uint8_t)0x00U)               /*!< generate a reset instead of entering deepsleep mode */
+
+/* option bytes reset or not entering standby mode */
+#define OB_STDBY_NRST              ((uint8_t)0x04U)               /*!< no reset when entering deepsleep mode */
+#define OB_STDBY_RST               ((uint8_t)0x00U)               /*!< generate a reset instead of entering standby mode */
+
+/* option bytes boot bank value */
+#define OB_BOOT_B0                 ((uint8_t)0x08U)               /*!< boot from bank0 */
+
+#define OB_USER_MASK               ((uint8_t)0xF0U)               /*!< MASK value */
+
+/* read protect configure */
+#define FMC_NSPC                   ((uint8_t)0xA5U)               /*!< no security protection */
+#define FMC_USPC                   ((uint8_t)0xBBU)               /*!< under security protection */
+
+/* OB_SPC */
+#define OB_SPC_SPC                 ((uint32_t)0x000000FFU)        /*!< option byte security protection value */
+#define OB_SPC_SPC_N               ((uint32_t)0x0000FF00U)        /*!< option byte security protection complement value */
+
+/* OB_USER */
+#define OB_USER_USER               ((uint32_t)0x00FF0000U)        /*!< user option value */
+#define OB_USER_USER_N             ((uint32_t)0xFF000000U)        /*!< user option complement value */
+
+/* OB_WP0 */
+#define OB_WP0_WP0                 ((uint32_t)0x000000FFU)        /*!< FMC write protection option value */
+
+/* OB_WP1 */
+#define OB_WP1_WP1                 ((uint32_t)0x0000FF00U)        /*!< FMC write protection option complement value */
+
+/* OB_WP2 */
+#define OB_WP2_WP2                 ((uint32_t)0x00FF0000U)        /*!< FMC write protection option value */
+
+/* OB_WP3 */
+#define OB_WP3_WP3                 ((uint32_t)0xFF000000U)        /*!< FMC write protection option complement value */
+
+/* option bytes write protection */
+#define OB_WP_0                    ((uint32_t)0x00000001U)        /*!< erase/program protection of sector 0  */
+#define OB_WP_1                    ((uint32_t)0x00000002U)        /*!< erase/program protection of sector 1  */
+#define OB_WP_2                    ((uint32_t)0x00000004U)        /*!< erase/program protection of sector 2  */
+#define OB_WP_3                    ((uint32_t)0x00000008U)        /*!< erase/program protection of sector 3  */
+#define OB_WP_4                    ((uint32_t)0x00000010U)        /*!< erase/program protection of sector 4  */
+#define OB_WP_5                    ((uint32_t)0x00000020U)        /*!< erase/program protection of sector 5  */
+#define OB_WP_6                    ((uint32_t)0x00000040U)        /*!< erase/program protection of sector 6  */
+#define OB_WP_7                    ((uint32_t)0x00000080U)        /*!< erase/program protection of sector 7  */
+#define OB_WP_8                    ((uint32_t)0x00000100U)        /*!< erase/program protection of sector 8  */
+#define OB_WP_9                    ((uint32_t)0x00000200U)        /*!< erase/program protection of sector 9  */
+#define OB_WP_10                   ((uint32_t)0x00000400U)        /*!< erase/program protection of sector 10 */
+#define OB_WP_11                   ((uint32_t)0x00000800U)        /*!< erase/program protection of sector 11 */
+#define OB_WP_12                   ((uint32_t)0x00001000U)        /*!< erase/program protection of sector 12 */
+#define OB_WP_13                   ((uint32_t)0x00002000U)        /*!< erase/program protection of sector 13 */
+#define OB_WP_14                   ((uint32_t)0x00004000U)        /*!< erase/program protection of sector 14 */
+#define OB_WP_15                   ((uint32_t)0x00008000U)        /*!< erase/program protection of sector 15 */
+#define OB_WP_16                   ((uint32_t)0x00010000U)        /*!< erase/program protection of sector 16 */
+#define OB_WP_17                   ((uint32_t)0x00020000U)        /*!< erase/program protection of sector 17 */
+#define OB_WP_18                   ((uint32_t)0x00040000U)        /*!< erase/program protection of sector 18 */
+#define OB_WP_19                   ((uint32_t)0x00080000U)        /*!< erase/program protection of sector 19 */
+#define OB_WP_20                   ((uint32_t)0x00100000U)        /*!< erase/program protection of sector 20 */
+#define OB_WP_21                   ((uint32_t)0x00200000U)        /*!< erase/program protection of sector 21 */
+#define OB_WP_22                   ((uint32_t)0x00400000U)        /*!< erase/program protection of sector 22 */
+#define OB_WP_23                   ((uint32_t)0x00800000U)        /*!< erase/program protection of sector 23 */
+#define OB_WP_24                   ((uint32_t)0x01000000U)        /*!< erase/program protection of sector 24 */
+#define OB_WP_25                   ((uint32_t)0x02000000U)        /*!< erase/program protection of sector 25 */
+#define OB_WP_26                   ((uint32_t)0x04000000U)        /*!< erase/program protection of sector 26 */
+#define OB_WP_27                   ((uint32_t)0x08000000U)        /*!< erase/program protection of sector 27 */
+#define OB_WP_28                   ((uint32_t)0x10000000U)        /*!< erase/program protection of sector 28 */
+#define OB_WP_29                   ((uint32_t)0x20000000U)        /*!< erase/program protection of sector 29 */
+#define OB_WP_30                   ((uint32_t)0x40000000U)        /*!< erase/program protection of sector 30 */
+#define OB_WP_31                   ((uint32_t)0x80000000U)        /*!< erase/program protection of sector 31 */
+#define OB_WP_ALL                  ((uint32_t)0xFFFFFFFFU)        /*!< erase/program protection of all sectors */
+
+/* FMC timeout */
+#define FMC_TIMEOUT_COUNT          ((uint32_t)0x000F0000U)        /*!< FMC timeout count value */
+
+/* FMC BANK address */
+#define FMC_SIZE                   (*(uint16_t *)0x1FFFF7E0U)     /*!< FMC size */
+#define SRAM_SIZE                  (*(uint16_t *)0x1FFFF7E2U)     /*!< SRAM size*/
+
+/* function declarations */
+/* FMC main memory programming functions */
+/* set the FMC wait state counter */
+void fmc_wscnt_set(uint32_t wscnt);
+/* unlock the main FMC operation */
+void fmc_unlock(void);
+/* lock the main FMC operation */
+void fmc_lock(void);
+/* FMC erase page */
+fmc_state_enum fmc_page_erase(uint32_t page_address);
+/* FMC erase whole chip */
+fmc_state_enum fmc_mass_erase(void);
+/* FMC program a word at the corresponding address */
+fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
+/* FMC program a half word at the corresponding address */
+fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
+
+/* FMC option bytes programming functions */
+/* unlock the option byte operation */
+void ob_unlock(void);
+/* lock the option byte operation */
+void ob_lock(void);
+/* erase the FMC option byte */
+fmc_state_enum ob_erase(void);
+/* enable write protect */
+fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
+/* configure the option byte security protection */
+fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
+/* write the FMC option byte */
+fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
+/* program option bytes data */
+fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
+/* get the FMC option byte user */
+uint8_t ob_user_get(void);
+/* get OB_DATA in register FMC_OBSTAT */
+uint16_t ob_data_get(void);
+/* get the FMC option byte write protection */
+uint32_t ob_write_protection_get(void);
+/* get FMC option byte security protection code value */
+FlagStatus ob_spc_get(void);
+
+/* FMC interrupts and flags management functions */
+/* enable FMC interrupt */
+void fmc_interrupt_enable(uint32_t interrupt);
+/* disable FMC interrupt */
+void fmc_interrupt_disable(uint32_t interrupt);
+/* check flag is set or not */
+FlagStatus fmc_flag_get(uint32_t flag);
+/* clear the FMC flag */
+void fmc_flag_clear(uint32_t flag);
+/* get FMC interrupt flag state */
+FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
+/* clear FMC interrupt flag state */
+void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
+/* return the FMC  state */
+fmc_state_enum fmc_state_get(void);
+/* check FMC ready or not */
+fmc_state_enum fmc_ready_wait(uint32_t timeout);
+
+#endif /* GD32VF103_FMC_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h
new file mode 100644
index 0000000000..cedfa0fbda
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h
@@ -0,0 +1,104 @@
+/*!
+    \file  gd32vf103_fwdgt.h
+    \brief definitions for the FWDGT
+    
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_FWDGT_H
+#define GD32VF103_FWDGT_H
+
+#include "gd32vf103.h"
+
+/* FWDGT definitions */
+#define FWDGT                       FWDGT_BASE                                /*!< FWDGT base address */
+
+/* registers definitions */
+#define FWDGT_CTL                   REG32((FWDGT) + 0x00000000U)              /*!< FWDGT control register */
+#define FWDGT_PSC                   REG32((FWDGT) + 0x00000004U)              /*!< FWDGT prescaler register */
+#define FWDGT_RLD                   REG32((FWDGT) + 0x00000008U)              /*!< FWDGT reload register */
+#define FWDGT_STAT                  REG32((FWDGT) + 0x0000000CU)              /*!< FWDGT status register */
+
+/* bits definitions */
+/* FWDGT_CTL */
+#define FWDGT_CTL_CMD               BITS(0,15)                                /*!< FWDGT command value */
+
+/* FWDGT_PSC */
+#define FWDGT_PSC_PSC               BITS(0,2)                                 /*!< FWDGT prescaler divider value */
+
+/* FWDGT_RLD */
+#define FWDGT_RLD_RLD               BITS(0,11)                                /*!< FWDGT counter reload value */
+
+/* FWDGT_STAT */
+#define FWDGT_STAT_PUD              BIT(0)                                    /*!< FWDGT prescaler divider value update */
+#define FWDGT_STAT_RUD              BIT(1)                                    /*!< FWDGT counter reload value update */
+
+/* constants definitions */
+/* psc register value */
+#define PSC_PSC(regval)             (BITS(0,2) & ((uint32_t)(regval) << 0))
+#define FWDGT_PSC_DIV4              ((uint8_t)PSC_PSC(0))                     /*!< FWDGT prescaler set to 4 */
+#define FWDGT_PSC_DIV8              ((uint8_t)PSC_PSC(1))                     /*!< FWDGT prescaler set to 8 */
+#define FWDGT_PSC_DIV16             ((uint8_t)PSC_PSC(2))                     /*!< FWDGT prescaler set to 16 */
+#define FWDGT_PSC_DIV32             ((uint8_t)PSC_PSC(3))                     /*!< FWDGT prescaler set to 32 */
+#define FWDGT_PSC_DIV64             ((uint8_t)PSC_PSC(4))                     /*!< FWDGT prescaler set to 64 */
+#define FWDGT_PSC_DIV128            ((uint8_t)PSC_PSC(5))                     /*!< FWDGT prescaler set to 128 */
+#define FWDGT_PSC_DIV256            ((uint8_t)PSC_PSC(6))                     /*!< FWDGT prescaler set to 256 */
+
+/* control value */
+#define FWDGT_WRITEACCESS_ENABLE    ((uint16_t)0x5555U)                       /*!< FWDGT_CTL bits write access enable value */
+#define FWDGT_WRITEACCESS_DISABLE   ((uint16_t)0x0000U)                       /*!< FWDGT_CTL bits write access disable value */
+#define FWDGT_KEY_RELOAD            ((uint16_t)0xAAAAU)                       /*!< FWDGT_CTL bits fwdgt counter reload value */
+#define FWDGT_KEY_ENABLE            ((uint16_t)0xCCCCU)                       /*!< FWDGT_CTL bits fwdgt counter enable value */
+
+/* FWDGT timeout value */
+#define FWDGT_PSC_TIMEOUT           ((uint32_t)0x000FFFFFU)                   /*!< FWDGT_PSC register write operation state flag timeout */
+#define FWDGT_RLD_TIMEOUT           ((uint32_t)0x000FFFFFU)                   /*!< FWDGT_RLD register write operation state flag timeout */
+
+/* FWDGT flag definitions */
+#define FWDGT_FLAG_PUD              FWDGT_STAT_PUD                            /*!< FWDGT prescaler divider value update flag */
+#define FWDGT_FLAG_RUD              FWDGT_STAT_RUD                            /*!< FWDGT counter reload value update flag */
+
+/* function declarations */
+/* enable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_enable(void);
+/* disable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_disable(void);
+/* start the free watchdog timer counter */
+void fwdgt_enable(void);
+
+/* reload the counter of FWDGT */
+void fwdgt_counter_reload(void);
+/* configure counter reload value, and prescaler divider value */
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
+
+/* get flag state of FWDGT */
+FlagStatus fwdgt_flag_get(uint16_t flag);
+
+#endif /* GD32VF103_FWDGT_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h
new file mode 100644
index 0000000000..2583646faa
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h
@@ -0,0 +1,423 @@
+/*!
+    \file  gd32vf103_gpio.h
+    \brief definitions for the GPIO
+    
+    \version 2019-06-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_GPIO_H
+#define GD32VF103_GPIO_H
+
+#include "gd32vf103.h"
+
+/* GPIOx(x=A,B,C,D,E) definitions */
+#define GPIOA                      (GPIO_BASE + 0x00000000U)
+#define GPIOB                      (GPIO_BASE + 0x00000400U)
+#define GPIOC                      (GPIO_BASE + 0x00000800U)
+#define GPIOD                      (GPIO_BASE + 0x00000C00U)
+#define GPIOE                      (GPIO_BASE + 0x00001000U)
+
+/* AFIO definitions */
+#define AFIO                       AFIO_BASE
+
+/* registers definitions */
+
+/* GPIO registers definitions */
+#define GPIO_CTL0(gpiox)           REG32((gpiox) + 0x00U)    /*!< GPIO port control register 0 */
+#define GPIO_CTL1(gpiox)           REG32((gpiox) + 0x04U)    /*!< GPIO port control register 1 */
+#define GPIO_ISTAT(gpiox)          REG32((gpiox) + 0x08U)    /*!< GPIO port input status register */
+#define GPIO_OCTL(gpiox)           REG32((gpiox) + 0x0CU)    /*!< GPIO port output control register */
+#define GPIO_BOP(gpiox)            REG32((gpiox) + 0x10U)    /*!< GPIO port bit operation register */
+#define GPIO_BC(gpiox)             REG32((gpiox) + 0x14U)    /*!< GPIO bit clear register */
+#define GPIO_LOCK(gpiox)           REG32((gpiox) + 0x18U)    /*!< GPIO port configuration lock register */
+
+/* AFIO registers definitions */
+#define AFIO_EC                    REG32(AFIO + 0x00U)       /*!< AFIO event control register */
+#define AFIO_PCF0                  REG32(AFIO + 0x04U)       /*!< AFIO port configuration register 0 */
+#define AFIO_EXTISS0               REG32(AFIO + 0x08U)       /*!< AFIO port EXTI sources selection register 0 */
+#define AFIO_EXTISS1               REG32(AFIO + 0x0CU)       /*!< AFIO port EXTI sources selection register 1 */
+#define AFIO_EXTISS2               REG32(AFIO + 0x10U)       /*!< AFIO port EXTI sources selection register 2 */
+#define AFIO_EXTISS3               REG32(AFIO + 0x14U)       /*!< AFIO port EXTI sources selection register 3 */
+#define AFIO_PCF1                  REG32(AFIO + 0x1CU)       /*!< AFIO port configuration register 1 */
+
+/* bits definitions */
+/* GPIO_CTL0 */
+#define GPIO_CTL0_MD0              BITS(0, 1)                /*!< port 0 mode bits */
+#define GPIO_CTL0_CTL0             BITS(2, 3)                /*!< pin 0 configuration bits */
+#define GPIO_CTL0_MD1              BITS(4, 5)                /*!< port 1 mode bits */
+#define GPIO_CTL0_CTL1             BITS(6, 7)                /*!< pin 1 configuration bits */
+#define GPIO_CTL0_MD2              BITS(8, 9)                /*!< port 2 mode bits */
+#define GPIO_CTL0_CTL2             BITS(10, 11)              /*!< pin 2 configuration bits */
+#define GPIO_CTL0_MD3              BITS(12, 13)              /*!< port 3 mode bits */
+#define GPIO_CTL0_CTL3             BITS(14, 15)              /*!< pin 3 configuration bits */
+#define GPIO_CTL0_MD4              BITS(16, 17)              /*!< port 4 mode bits */
+#define GPIO_CTL0_CTL4             BITS(18, 19)              /*!< pin 4 configuration bits */
+#define GPIO_CTL0_MD5              BITS(20, 21)              /*!< port 5 mode bits */
+#define GPIO_CTL0_CTL5             BITS(22, 23)              /*!< pin 5 configuration bits */
+#define GPIO_CTL0_MD6              BITS(24, 25)              /*!< port 6 mode bits */
+#define GPIO_CTL0_CTL6             BITS(26, 27)              /*!< pin 6 configuration bits */
+#define GPIO_CTL0_MD7              BITS(28, 29)              /*!< port 7 mode bits */
+#define GPIO_CTL0_CTL7             BITS(30, 31)              /*!< pin 7 configuration bits */
+
+/* GPIO_CTL1 */
+#define GPIO_CTL1_MD8              BITS(0, 1)                /*!< port 8 mode bits */
+#define GPIO_CTL1_CTL8             BITS(2, 3)                /*!< pin 8 configuration bits */
+#define GPIO_CTL1_MD9              BITS(4, 5)                /*!< port 9 mode bits */
+#define GPIO_CTL1_CTL9             BITS(6, 7)                /*!< pin 9 configuration bits */
+#define GPIO_CTL1_MD10             BITS(8, 9)                /*!< port 10 mode bits */
+#define GPIO_CTL1_CTL10            BITS(10, 11)              /*!< pin 10 configuration bits */
+#define GPIO_CTL1_MD11             BITS(12, 13)              /*!< port 11 mode bits */
+#define GPIO_CTL1_CTL11            BITS(14, 15)              /*!< pin 11 configuration bits */
+#define GPIO_CTL1_MD12             BITS(16, 17)              /*!< port 12 mode bits */
+#define GPIO_CTL1_CTL12            BITS(18, 19)              /*!< pin 12 configuration bits */
+#define GPIO_CTL1_MD13             BITS(20, 21)              /*!< port 13 mode bits */
+#define GPIO_CTL1_CTL13            BITS(22, 23)              /*!< pin 13 configuration bits */
+#define GPIO_CTL1_MD14             BITS(24, 25)              /*!< port 14 mode bits */
+#define GPIO_CTL1_CTL14            BITS(26, 27)              /*!< pin 14 configuration bits */
+#define GPIO_CTL1_MD15             BITS(28, 29)              /*!< port 15 mode bits */
+#define GPIO_CTL1_CTL15            BITS(30, 31)              /*!< pin 15 configuration bits */
+
+/* GPIO_ISTAT */
+#define GPIO_ISTAT_ISTAT0          BIT(0)                    /*!< pin 0 input status */
+#define GPIO_ISTAT_ISTAT1          BIT(1)                    /*!< pin 1 input status */
+#define GPIO_ISTAT_ISTAT2          BIT(2)                    /*!< pin 2 input status */
+#define GPIO_ISTAT_ISTAT3          BIT(3)                    /*!< pin 3 input status */
+#define GPIO_ISTAT_ISTAT4          BIT(4)                    /*!< pin 4 input status */
+#define GPIO_ISTAT_ISTAT5          BIT(5)                    /*!< pin 5 input status */
+#define GPIO_ISTAT_ISTAT6          BIT(6)                    /*!< pin 6 input status */
+#define GPIO_ISTAT_ISTAT7          BIT(7)                    /*!< pin 7 input status */
+#define GPIO_ISTAT_ISTAT8          BIT(8)                    /*!< pin 8 input status */
+#define GPIO_ISTAT_ISTAT9          BIT(9)                    /*!< pin 9 input status */
+#define GPIO_ISTAT_ISTAT10         BIT(10)                   /*!< pin 10 input status */
+#define GPIO_ISTAT_ISTAT11         BIT(11)                   /*!< pin 11 input status */
+#define GPIO_ISTAT_ISTAT12         BIT(12)                   /*!< pin 12 input status */
+#define GPIO_ISTAT_ISTAT13         BIT(13)                   /*!< pin 13 input status */
+#define GPIO_ISTAT_ISTAT14         BIT(14)                   /*!< pin 14 input status */
+#define GPIO_ISTAT_ISTAT15         BIT(15)                   /*!< pin 15 input status */
+
+/* GPIO_OCTL */
+#define GPIO_OCTL_OCTL0            BIT(0)                    /*!< pin 0 output bit */
+#define GPIO_OCTL_OCTL1            BIT(1)                    /*!< pin 1 output bit */
+#define GPIO_OCTL_OCTL2            BIT(2)                    /*!< pin 2 output bit */
+#define GPIO_OCTL_OCTL3            BIT(3)                    /*!< pin 3 output bit */
+#define GPIO_OCTL_OCTL4            BIT(4)                    /*!< pin 4 output bit */
+#define GPIO_OCTL_OCTL5            BIT(5)                    /*!< pin 5 output bit */
+#define GPIO_OCTL_OCTL6            BIT(6)                    /*!< pin 6 output bit */
+#define GPIO_OCTL_OCTL7            BIT(7)                    /*!< pin 7 output bit */
+#define GPIO_OCTL_OCTL8            BIT(8)                    /*!< pin 8 output bit */
+#define GPIO_OCTL_OCTL9            BIT(9)                    /*!< pin 9 output bit */
+#define GPIO_OCTL_OCTL10           BIT(10)                   /*!< pin 10 output bit */
+#define GPIO_OCTL_OCTL11           BIT(11)                   /*!< pin 11 output bit */
+#define GPIO_OCTL_OCTL12           BIT(12)                   /*!< pin 12 output bit */
+#define GPIO_OCTL_OCTL13           BIT(13)                   /*!< pin 13 output bit */
+#define GPIO_OCTL_OCTL14           BIT(14)                   /*!< pin 14 output bit */
+#define GPIO_OCTL_OCTL15           BIT(15)                   /*!< pin 15 output bit */
+
+/* GPIO_BOP */
+#define GPIO_BOP_BOP0              BIT(0)                    /*!< pin 0 set bit */
+#define GPIO_BOP_BOP1              BIT(1)                    /*!< pin 1 set bit */
+#define GPIO_BOP_BOP2              BIT(2)                    /*!< pin 2 set bit */
+#define GPIO_BOP_BOP3              BIT(3)                    /*!< pin 3 set bit */
+#define GPIO_BOP_BOP4              BIT(4)                    /*!< pin 4 set bit */
+#define GPIO_BOP_BOP5              BIT(5)                    /*!< pin 5 set bit */
+#define GPIO_BOP_BOP6              BIT(6)                    /*!< pin 6 set bit */
+#define GPIO_BOP_BOP7              BIT(7)                    /*!< pin 7 set bit */
+#define GPIO_BOP_BOP8              BIT(8)                    /*!< pin 8 set bit */
+#define GPIO_BOP_BOP9              BIT(9)                    /*!< pin 9 set bit */
+#define GPIO_BOP_BOP10             BIT(10)                   /*!< pin 10 set bit */
+#define GPIO_BOP_BOP11             BIT(11)                   /*!< pin 11 set bit */
+#define GPIO_BOP_BOP12             BIT(12)                   /*!< pin 12 set bit */
+#define GPIO_BOP_BOP13             BIT(13)                   /*!< pin 13 set bit */
+#define GPIO_BOP_BOP14             BIT(14)                   /*!< pin 14 set bit */
+#define GPIO_BOP_BOP15             BIT(15)                   /*!< pin 15 set bit */
+#define GPIO_BOP_CR0               BIT(16)                   /*!< pin 0 clear bit */
+#define GPIO_BOP_CR1               BIT(17)                   /*!< pin 1 clear bit */
+#define GPIO_BOP_CR2               BIT(18)                   /*!< pin 2 clear bit */
+#define GPIO_BOP_CR3               BIT(19)                   /*!< pin 3 clear bit */
+#define GPIO_BOP_CR4               BIT(20)                   /*!< pin 4 clear bit */
+#define GPIO_BOP_CR5               BIT(21)                   /*!< pin 5 clear bit */
+#define GPIO_BOP_CR6               BIT(22)                   /*!< pin 6 clear bit */
+#define GPIO_BOP_CR7               BIT(23)                   /*!< pin 7 clear bit */
+#define GPIO_BOP_CR8               BIT(24)                   /*!< pin 8 clear bit */
+#define GPIO_BOP_CR9               BIT(25)                   /*!< pin 9 clear bit */
+#define GPIO_BOP_CR10              BIT(26)                   /*!< pin 10 clear bit */
+#define GPIO_BOP_CR11              BIT(27)                   /*!< pin 11 clear bit */
+#define GPIO_BOP_CR12              BIT(28)                   /*!< pin 12 clear bit */
+#define GPIO_BOP_CR13              BIT(29)                   /*!< pin 13 clear bit */
+#define GPIO_BOP_CR14              BIT(30)                   /*!< pin 14 clear bit */
+#define GPIO_BOP_CR15              BIT(31)                   /*!< pin 15 clear bit */
+
+/* GPIO_BC */
+#define GPIO_BC_CR0                BIT(0)                    /*!< pin 0 clear bit */
+#define GPIO_BC_CR1                BIT(1)                    /*!< pin 1 clear bit */
+#define GPIO_BC_CR2                BIT(2)                    /*!< pin 2 clear bit */
+#define GPIO_BC_CR3                BIT(3)                    /*!< pin 3 clear bit */
+#define GPIO_BC_CR4                BIT(4)                    /*!< pin 4 clear bit */
+#define GPIO_BC_CR5                BIT(5)                    /*!< pin 5 clear bit */
+#define GPIO_BC_CR6                BIT(6)                    /*!< pin 6 clear bit */
+#define GPIO_BC_CR7                BIT(7)                    /*!< pin 7 clear bit */
+#define GPIO_BC_CR8                BIT(8)                    /*!< pin 8 clear bit */
+#define GPIO_BC_CR9                BIT(9)                    /*!< pin 9 clear bit */
+#define GPIO_BC_CR10               BIT(10)                   /*!< pin 10 clear bit */
+#define GPIO_BC_CR11               BIT(11)                   /*!< pin 11 clear bit */
+#define GPIO_BC_CR12               BIT(12)                   /*!< pin 12 clear bit */
+#define GPIO_BC_CR13               BIT(13)                   /*!< pin 13 clear bit */
+#define GPIO_BC_CR14               BIT(14)                   /*!< pin 14 clear bit */
+#define GPIO_BC_CR15               BIT(15)                   /*!< pin 15 clear bit */
+
+/* GPIO_LOCK */
+#define GPIO_LOCK_LK0              BIT(0)                    /*!< pin 0 lock bit */
+#define GPIO_LOCK_LK1              BIT(1)                    /*!< pin 1 lock bit */
+#define GPIO_LOCK_LK2              BIT(2)                    /*!< pin 2 lock bit */
+#define GPIO_LOCK_LK3              BIT(3)                    /*!< pin 3 lock bit */
+#define GPIO_LOCK_LK4              BIT(4)                    /*!< pin 4 lock bit */
+#define GPIO_LOCK_LK5              BIT(5)                    /*!< pin 5 lock bit */
+#define GPIO_LOCK_LK6              BIT(6)                    /*!< pin 6 lock bit */
+#define GPIO_LOCK_LK7              BIT(7)                    /*!< pin 7 lock bit */
+#define GPIO_LOCK_LK8              BIT(8)                    /*!< pin 8 lock bit */
+#define GPIO_LOCK_LK9              BIT(9)                    /*!< pin 9 lock bit */
+#define GPIO_LOCK_LK10             BIT(10)                   /*!< pin 10 lock bit */
+#define GPIO_LOCK_LK11             BIT(11)                   /*!< pin 11 lock bit */
+#define GPIO_LOCK_LK12             BIT(12)                   /*!< pin 12 lock bit */
+#define GPIO_LOCK_LK13             BIT(13)                   /*!< pin 13 lock bit */
+#define GPIO_LOCK_LK14             BIT(14)                   /*!< pin 14 lock bit */
+#define GPIO_LOCK_LK15             BIT(15)                   /*!< pin 15 lock bit */
+#define GPIO_LOCK_LKK              BIT(16)                   /*!< pin sequence lock key */
+
+/* AFIO_EC */
+#define AFIO_EC_PIN                BITS(0, 3)                /*!< event output pin selection */
+#define AFIO_EC_PORT               BITS(4, 6)                /*!< event output port selection */
+#define AFIO_EC_EOE                BIT(7)                    /*!< event output enable */
+
+/* AFIO_PCF0 */
+/* memory map and bit definitions for GD32F10X_CL devices */
+#define AFIO_PCF0_SPI0_REMAP             BIT(0)              /*!< SPI0 remapping */
+#define AFIO_PCF0_I2C0_REMAP             BIT(1)              /*!< I2C0 remapping */
+#define AFIO_PCF0_USART0_REMAP           BIT(2)              /*!< USART0 remapping */
+#define AFIO_PCF0_USART1_REMAP           BIT(3)              /*!< USART1 remapping */
+#define AFIO_PCF0_USART2_REMAP           BITS(4, 5)          /*!< USART2 remapping */
+#define AFIO_PCF0_TIMER0_REMAP           BITS(6, 7)          /*!< TIMER0 remapping */
+#define AFIO_PCF0_TIMER1_REMAP           BITS(8, 9)          /*!< TIMER1 remapping */
+#define AFIO_PCF0_TIMER2_REMAP           BITS(10, 11)        /*!< TIMER2 remapping */
+#define AFIO_PCF0_TIMER3_REMAP           BIT(12)             /*!< TIMER3 remapping */
+#define AFIO_PCF0_CAN_REMAP              BITS(13, 14)        /*!< CAN remapping */
+#define AFIO_PCF0_PD01_REMAP             BIT(15)             /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_PCF0_TIMER4CH3_IREMAP       BIT(16)             /*!< TIMER3 channel3 internal remapping */
+#define AFIO_PCF0_SWJ_CFG                BITS(24, 26)        /*!< serial wire JTAG configuration */
+#define AFIO_PCF0_SPI2_REMAP             BIT(28)             /*!< SPI2/I2S2 remapping */
+#define AFIO_PCF0_TIMER1_ITI1_REMAP      BIT(29)             /*!< TIMER1 internal trigger 1 remapping */
+
+/* AFIO_EXTISS0 */
+#define AFIO_EXTI0_SS                    BITS(0, 3)          /*!< EXTI 0 sources selection */
+#define AFIO_EXTI1_SS                    BITS(4, 7)          /*!< EXTI 1 sources selection */
+#define AFIO_EXTI2_SS                    BITS(8, 11)         /*!< EXTI 2 sources selection */
+#define AFIO_EXTI3_SS                    BITS(12, 15)        /*!< EXTI 3 sources selection */
+
+/* AFIO_EXTISS1 */
+#define AFIO_EXTI4_SS                    BITS(0, 3)          /*!< EXTI 4 sources selection */
+#define AFIO_EXTI5_SS                    BITS(4, 7)          /*!< EXTI 5 sources selection */
+#define AFIO_EXTI6_SS                    BITS(8, 11)         /*!< EXTI 6 sources selection */
+#define AFIO_EXTI7_SS                    BITS(12, 15)        /*!< EXTI 7 sources selection */
+
+/* AFIO_EXTISS2 */
+#define AFIO_EXTI8_SS                    BITS(0, 3)          /*!< EXTI 8 sources selection */
+#define AFIO_EXTI9_SS                    BITS(4, 7)          /*!< EXTI 9 sources selection */
+#define AFIO_EXTI10_SS                   BITS(8, 11)         /*!< EXTI 10 sources selection */
+#define AFIO_EXTI11_SS                   BITS(12, 15)        /*!< EXTI 11 sources selection */
+
+/* AFIO_EXTISS3 */
+#define AFIO_EXTI12_SS                   BITS(0, 3)          /*!< EXTI 12 sources selection */
+#define AFIO_EXTI13_SS                   BITS(4, 7)          /*!< EXTI 13 sources selection */
+#define AFIO_EXTI14_SS                   BITS(8, 11)         /*!< EXTI 14 sources selection */
+#define AFIO_EXTI15_SS                   BITS(12, 15)        /*!< EXTI 15 sources selection */
+
+/* AFIO_PCF1 */
+#define AFIO_PCF1_EXMC_NADV              BIT(10)             /*!< EXMC_NADV connect/disconnect */
+
+/* constants definitions */
+typedef FlagStatus bit_status;
+
+/* GPIO mode values set */
+#define GPIO_MODE_SET(n, mode)           ((uint32_t)((uint32_t)(mode) << (4U * (n))))
+#define GPIO_MODE_MASK(n)                (0xFU << (4U * (n)))
+
+/* GPIO mode definitions */
+#define GPIO_MODE_AIN                    ((uint8_t)0x00U)          /*!< analog input mode */
+#define GPIO_MODE_IN_FLOATING            ((uint8_t)0x04U)          /*!< floating input mode */
+#define GPIO_MODE_IPD                    ((uint8_t)0x28U)          /*!< pull-down input mode */
+#define GPIO_MODE_IPU                    ((uint8_t)0x48U)          /*!< pull-up input mode */
+#define GPIO_MODE_OUT_OD                 ((uint8_t)0x14U)          /*!< GPIO output with open-drain */
+#define GPIO_MODE_OUT_PP                 ((uint8_t)0x10U)          /*!< GPIO output with push-pull */
+#define GPIO_MODE_AF_OD                  ((uint8_t)0x1CU)          /*!< AFIO output with open-drain */
+#define GPIO_MODE_AF_PP                  ((uint8_t)0x18U)          /*!< AFIO output with push-pull */
+
+/* GPIO output max speed value */
+#define GPIO_OSPEED_10MHZ                ((uint8_t)0x01U)          /*!< output max speed 10MHz */
+#define GPIO_OSPEED_2MHZ                 ((uint8_t)0x02U)          /*!< output max speed 2MHz */
+#define GPIO_OSPEED_50MHZ                ((uint8_t)0x03U)          /*!< output max speed 50MHz */
+
+/* GPIO event output port definitions */
+#define GPIO_EVENT_PORT_GPIOA            ((uint8_t)0x00U)          /*!< event output port A */
+#define GPIO_EVENT_PORT_GPIOB            ((uint8_t)0x01U)          /*!< event output port B */
+#define GPIO_EVENT_PORT_GPIOC            ((uint8_t)0x02U)          /*!< event output port C */
+#define GPIO_EVENT_PORT_GPIOD            ((uint8_t)0x03U)          /*!< event output port D */
+#define GPIO_EVENT_PORT_GPIOE            ((uint8_t)0x04U)          /*!< event output port E */
+
+/* GPIO output port source definitions */
+#define GPIO_PORT_SOURCE_GPIOA           ((uint8_t)0x00U)          /*!< output port source A */
+#define GPIO_PORT_SOURCE_GPIOB           ((uint8_t)0x01U)          /*!< output port source B */
+#define GPIO_PORT_SOURCE_GPIOC           ((uint8_t)0x02U)          /*!< output port source C */
+#define GPIO_PORT_SOURCE_GPIOD           ((uint8_t)0x03U)          /*!< output port source D */
+#define GPIO_PORT_SOURCE_GPIOE           ((uint8_t)0x04U)          /*!< output port source E */
+
+/* GPIO event output pin definitions */
+#define GPIO_EVENT_PIN_0                 ((uint8_t)0x00U)          /*!< GPIO event pin 0 */
+#define GPIO_EVENT_PIN_1                 ((uint8_t)0x01U)          /*!< GPIO event pin 1 */
+#define GPIO_EVENT_PIN_2                 ((uint8_t)0x02U)          /*!< GPIO event pin 2 */
+#define GPIO_EVENT_PIN_3                 ((uint8_t)0x03U)          /*!< GPIO event pin 3 */
+#define GPIO_EVENT_PIN_4                 ((uint8_t)0x04U)          /*!< GPIO event pin 4 */
+#define GPIO_EVENT_PIN_5                 ((uint8_t)0x05U)          /*!< GPIO event pin 5 */
+#define GPIO_EVENT_PIN_6                 ((uint8_t)0x06U)          /*!< GPIO event pin 6 */
+#define GPIO_EVENT_PIN_7                 ((uint8_t)0x07U)          /*!< GPIO event pin 7 */
+#define GPIO_EVENT_PIN_8                 ((uint8_t)0x08U)          /*!< GPIO event pin 8 */
+#define GPIO_EVENT_PIN_9                 ((uint8_t)0x09U)          /*!< GPIO event pin 9 */
+#define GPIO_EVENT_PIN_10                ((uint8_t)0x0AU)          /*!< GPIO event pin 10 */
+#define GPIO_EVENT_PIN_11                ((uint8_t)0x0BU)          /*!< GPIO event pin 11 */
+#define GPIO_EVENT_PIN_12                ((uint8_t)0x0CU)          /*!< GPIO event pin 12 */
+#define GPIO_EVENT_PIN_13                ((uint8_t)0x0DU)          /*!< GPIO event pin 13 */
+#define GPIO_EVENT_PIN_14                ((uint8_t)0x0EU)          /*!< GPIO event pin 14 */
+#define GPIO_EVENT_PIN_15                ((uint8_t)0x0FU)          /*!< GPIO event pin 15 */
+
+/* GPIO output pin source definitions */
+#define GPIO_PIN_SOURCE_0                ((uint8_t)0x00U)          /*!< GPIO pin source 0 */
+#define GPIO_PIN_SOURCE_1                ((uint8_t)0x01U)          /*!< GPIO pin source 1 */
+#define GPIO_PIN_SOURCE_2                ((uint8_t)0x02U)          /*!< GPIO pin source 2 */
+#define GPIO_PIN_SOURCE_3                ((uint8_t)0x03U)          /*!< GPIO pin source 3 */
+#define GPIO_PIN_SOURCE_4                ((uint8_t)0x04U)          /*!< GPIO pin source 4 */
+#define GPIO_PIN_SOURCE_5                ((uint8_t)0x05U)          /*!< GPIO pin source 5 */
+#define GPIO_PIN_SOURCE_6                ((uint8_t)0x06U)          /*!< GPIO pin source 6 */
+#define GPIO_PIN_SOURCE_7                ((uint8_t)0x07U)          /*!< GPIO pin source 7 */
+#define GPIO_PIN_SOURCE_8                ((uint8_t)0x08U)          /*!< GPIO pin source 8 */
+#define GPIO_PIN_SOURCE_9                ((uint8_t)0x09U)          /*!< GPIO pin source 9 */
+#define GPIO_PIN_SOURCE_10               ((uint8_t)0x0AU)          /*!< GPIO pin source 10 */
+#define GPIO_PIN_SOURCE_11               ((uint8_t)0x0BU)          /*!< GPIO pin source 11 */
+#define GPIO_PIN_SOURCE_12               ((uint8_t)0x0CU)          /*!< GPIO pin source 12 */
+#define GPIO_PIN_SOURCE_13               ((uint8_t)0x0DU)          /*!< GPIO pin source 13 */
+#define GPIO_PIN_SOURCE_14               ((uint8_t)0x0EU)          /*!< GPIO pin source 14 */
+#define GPIO_PIN_SOURCE_15               ((uint8_t)0x0FU)          /*!< GPIO pin source 15 */
+
+/* GPIO pin definitions */
+#define GPIO_PIN_0                       BIT(0)                    /*!< GPIO pin 0 */
+#define GPIO_PIN_1                       BIT(1)                    /*!< GPIO pin 1 */
+#define GPIO_PIN_2                       BIT(2)                    /*!< GPIO pin 2 */
+#define GPIO_PIN_3                       BIT(3)                    /*!< GPIO pin 3 */
+#define GPIO_PIN_4                       BIT(4)                    /*!< GPIO pin 4 */
+#define GPIO_PIN_5                       BIT(5)                    /*!< GPIO pin 5 */
+#define GPIO_PIN_6                       BIT(6)                    /*!< GPIO pin 6 */
+#define GPIO_PIN_7                       BIT(7)                    /*!< GPIO pin 7 */
+#define GPIO_PIN_8                       BIT(8)                    /*!< GPIO pin 8 */
+#define GPIO_PIN_9                       BIT(9)                    /*!< GPIO pin 9 */
+#define GPIO_PIN_10                      BIT(10)                   /*!< GPIO pin 10 */
+#define GPIO_PIN_11                      BIT(11)                   /*!< GPIO pin 11 */
+#define GPIO_PIN_12                      BIT(12)                   /*!< GPIO pin 12 */
+#define GPIO_PIN_13                      BIT(13)                   /*!< GPIO pin 13 */
+#define GPIO_PIN_14                      BIT(14)                   /*!< GPIO pin 14 */
+#define GPIO_PIN_15                      BIT(15)                   /*!< GPIO pin 15 */
+#define GPIO_PIN_ALL                     BITS(0, 15)               /*!< GPIO pin all */
+
+/* GPIO remap definitions */
+#define GPIO_SPI0_REMAP                  ((uint32_t)0x00000001U)   /*!< SPI0 remapping */
+#define GPIO_I2C0_REMAP                  ((uint32_t)0x00000002U)   /*!< I2C0 remapping */
+#define GPIO_USART0_REMAP                ((uint32_t)0x00000004U)   /*!< USART0 remapping */
+#define GPIO_USART1_REMAP                ((uint32_t)0x00000008U)   /*!< USART1 remapping */
+#define GPIO_USART2_PARTIAL_REMAP        ((uint32_t)0x00140010U)   /*!< USART2 partial remapping */
+#define GPIO_USART2_FULL_REMAP           ((uint32_t)0x00140030U)   /*!< USART2 full remapping */
+#define GPIO_TIMER0_PARTIAL_REMAP        ((uint32_t)0x00160040U)   /*!< TIMER0 partial remapping */
+#define GPIO_TIMER0_FULL_REMAP           ((uint32_t)0x001600C0U)   /*!< TIMER0 full remapping */
+#define GPIO_TIMER1_PARTIAL_REMAP0       ((uint32_t)0x00180100U)   /*!< TIMER1 partial remapping */
+#define GPIO_TIMER1_PARTIAL_REMAP1       ((uint32_t)0x00180200U)   /*!< TIMER1 partial remapping */
+#define GPIO_TIMER1_FULL_REMAP           ((uint32_t)0x00180300U)   /*!< TIMER1 full remapping */
+#define GPIO_TIMER2_PARTIAL_REMAP        ((uint32_t)0x001A0800U)   /*!< TIMER2 partial remapping */
+#define GPIO_TIMER2_FULL_REMAP           ((uint32_t)0x001A0C00U)   /*!< TIMER2 full remapping */
+#define GPIO_TIMER3_REMAP                ((uint32_t)0x00001000U)   /*!< TIMER3 remapping */
+#define GPIO_CAN0_PARTIAL_REMAP          ((uint32_t)0x001D4000U)   /*!< CAN0 partial remapping */
+#define GPIO_CAN0_FULL_REMAP             ((uint32_t)0x001D6000U)   /*!< CAN0 full remapping */
+#define GPIO_PD01_REMAP                  ((uint32_t)0x00008000U)   /*!< PD01 remapping */
+#define GPIO_TIMER4CH3_IREMAP            ((uint32_t)0x00200001U)   /*!< TIMER4 channel3 internal remapping */
+#define GPIO_CAN1_REMAP                  ((uint32_t)0x00200040U)   /*!< CAN1 remapping */
+#define GPIO_SWJ_NONJTRST_REMAP          ((uint32_t)0x00300100U)   /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */
+#define GPIO_SWJ_SWDPENABLE_REMAP        ((uint32_t)0x00300200U)   /*!< JTAG-DP disabled */
+#define GPIO_SWJ_DISABLE_REMAP           ((uint32_t)0x00300400U)   /*!< JTAG-DP disabled */
+#define GPIO_SPI2_REMAP                  ((uint32_t)0x00201100U)   /*!< SPI2 remapping */
+#define GPIO_TIMER1ITI1_REMAP            ((uint32_t)0x00202000U)   /*!< TIMER1 internal trigger 1 remapping */
+#define GPIO_EXMC_NADV_REMAP             ((uint32_t)0x80000400U)   /*!< EXMC_NADV connect/disconnect */
+
+/* function declarations */
+/* reset GPIO port */
+void gpio_deinit(uint32_t gpio_periph);
+/* reset alternate function I/O(AFIO) */
+void gpio_afio_deinit(void);
+/* GPIO parameter initialization */
+void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin);
+
+/* set GPIO pin bit */
+void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
+/* reset GPIO pin bit */
+void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
+/* write data to the specified GPIO pin */
+void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
+/* write data to the specified GPIO port */
+void gpio_port_write(uint32_t gpio_periph, uint16_t data);
+
+/* get GPIO pin input status */
+FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
+/* get GPIO port input status */
+uint16_t gpio_input_port_get(uint32_t gpio_periph);
+/* get GPIO pin output status */
+FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
+/* get GPIO port output status */
+uint16_t gpio_output_port_get(uint32_t gpio_periph);
+
+/* configure GPIO pin remap */
+void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue);
+
+/* select GPIO pin exti sources */
+void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin);
+/* configure GPIO pin event output */
+void gpio_event_output_config(uint8_t output_port, uint8_t output_pin);
+/* enable GPIO pin event output */
+void gpio_event_output_enable(void);
+/* disable GPIO pin event output */
+void gpio_event_output_disable(void);
+
+/* lock GPIO pin bit */
+void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
+
+#endif /* GD32VF103_GPIO_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h
new file mode 100644
index 0000000000..caba0015b0
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h
@@ -0,0 +1,342 @@
+/*!
+    \file  gd32vf103_i2c.h
+    \brief definitions for the I2C
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_I2C_H
+#define GD32VF103_I2C_H
+
+#include "gd32vf103.h"
+
+/* I2Cx(x=0,1) definitions */
+#define I2C0                          I2C_BASE                   /*!< I2C0 base address */
+#define I2C1                          (I2C_BASE + 0x00000400U)   /*!< I2C1 base address */
+
+/* registers definitions */
+#define I2C_CTL0(i2cx)                REG32((i2cx) + 0x00U)      /*!< I2C control register 0 */
+#define I2C_CTL1(i2cx)                REG32((i2cx) + 0x04U)      /*!< I2C control register 1 */
+#define I2C_SADDR0(i2cx)              REG32((i2cx) + 0x08U)      /*!< I2C slave address register 0*/
+#define I2C_SADDR1(i2cx)              REG32((i2cx) + 0x0CU)      /*!< I2C slave address register */
+#define I2C_DATA(i2cx)                REG32((i2cx) + 0x10U)      /*!< I2C transfer buffer register */
+#define I2C_STAT0(i2cx)               REG32((i2cx) + 0x14U)      /*!< I2C transfer status register 0 */
+#define I2C_STAT1(i2cx)               REG32((i2cx) + 0x18U)      /*!< I2C transfer status register */
+#define I2C_CKCFG(i2cx)               REG32((i2cx) + 0x1CU)      /*!< I2C clock configure register */
+#define I2C_RT(i2cx)                  REG32((i2cx) + 0x20U)      /*!< I2C rise time register */
+
+/* bits definitions */
+/* I2Cx_CTL0 */
+#define I2C_CTL0_I2CEN                BIT(0)        /*!< peripheral enable */
+#define I2C_CTL0_SMBEN                BIT(1)        /*!< SMBus mode */
+#define I2C_CTL0_SMBSEL               BIT(3)        /*!< SMBus type */
+#define I2C_CTL0_ARPEN                BIT(4)        /*!< ARP enable */
+#define I2C_CTL0_PECEN                BIT(5)        /*!< PEC enable */
+#define I2C_CTL0_GCEN                 BIT(6)        /*!< general call enable */
+#define I2C_CTL0_SS                   BIT(7)        /*!< clock stretching disable (slave mode) */
+#define I2C_CTL0_START                BIT(8)        /*!< start generation */
+#define I2C_CTL0_STOP                 BIT(9)        /*!< stop generation */
+#define I2C_CTL0_ACKEN                BIT(10)       /*!< acknowledge enable */
+#define I2C_CTL0_POAP                 BIT(11)       /*!< acknowledge/PEC position (for data reception) */
+#define I2C_CTL0_PECTRANS             BIT(12)       /*!< packet error checking */
+#define I2C_CTL0_SALT                 BIT(13)       /*!< SMBus alert */
+#define I2C_CTL0_SRESET               BIT(15)       /*!< software reset */
+
+/* I2Cx_CTL1 */
+#define I2C_CTL1_I2CCLK               BITS(0,5)     /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
+#define I2C_CTL1_ERRIE                BIT(8)        /*!< error interrupt enable */
+#define I2C_CTL1_EVIE                 BIT(9)        /*!< event interrupt enable */
+#define I2C_CTL1_BUFIE                BIT(10)       /*!< buffer interrupt enable */
+#define I2C_CTL1_DMAON                BIT(11)       /*!< DMA requests enable */
+#define I2C_CTL1_DMALST               BIT(12)       /*!< DMA last transfer */
+
+/* I2Cx_SADDR0 */
+#define I2C_SADDR0_ADDRESS0           BIT(0)        /*!< bit 0 of a 10-bit address */
+#define I2C_SADDR0_ADDRESS            BITS(1,7)     /*!< 7-bit address or bits 7:1 of a 10-bit address */
+#define I2C_SADDR0_ADDRESS_H          BITS(8,9)     /*!< highest two bits of a 10-bit address */
+#define I2C_SADDR0_ADDFORMAT          BIT(15)       /*!< address mode for the I2C slave */
+
+/* I2Cx_SADDR1 */
+#define I2C_SADDR1_DUADEN             BIT(0)        /*!< aual-address mode switch */
+#define I2C_SADDR1_ADDRESS2           BITS(1,7)     /*!< second I2C address for the slave in dual-address mode */
+
+/* I2Cx_DATA */
+#define I2C_DATA_TRB                  BITS(0,7)     /*!< 8-bit data register */
+
+/* I2Cx_STAT0 */
+#define I2C_STAT0_SBSEND              BIT(0)        /*!< start bit (master mode) */
+#define I2C_STAT0_ADDSEND             BIT(1)        /*!< address sent (master mode)/matched (slave mode) */
+#define I2C_STAT0_BTC                 BIT(2)        /*!< byte transfer finished */
+#define I2C_STAT0_ADD10SEND           BIT(3)        /*!< 10-bit header sent (master mode) */
+#define I2C_STAT0_STPDET              BIT(4)        /*!< stop detection (slave mode) */
+#define I2C_STAT0_RBNE                BIT(6)        /*!< data register not empty (receivers) */
+#define I2C_STAT0_TBE                 BIT(7)        /*!< data register empty (transmitters) */
+#define I2C_STAT0_BERR                BIT(8)        /*!< bus error */
+#define I2C_STAT0_LOSTARB             BIT(9)        /*!< arbitration lost (master mode) */
+#define I2C_STAT0_AERR                BIT(10)       /*!< acknowledge failure */
+#define I2C_STAT0_OUERR               BIT(11)       /*!< overrun/underrun */
+#define I2C_STAT0_PECERR              BIT(12)       /*!< PEC error in reception */
+#define I2C_STAT0_SMBTO               BIT(14)       /*!< timeout signal in SMBus mode */
+#define I2C_STAT0_SMBALT              BIT(15)       /*!< SMBus alert status */
+
+/* I2Cx_STAT1 */
+#define I2C_STAT1_MASTER              BIT(0)        /*!< master/slave */
+#define I2C_STAT1_I2CBSY              BIT(1)        /*!< bus busy */
+#define I2C_STAT1_TR                  BIT(2)        /*!< transmitter/receiver */
+#define I2C_STAT1_RXGC                BIT(4)        /*!< general call address (slave mode) */
+#define I2C_STAT1_DEFSMB              BIT(5)        /*!< SMBus device default address (slave mode) */
+#define I2C_STAT1_HSTSMB              BIT(6)        /*!< SMBus host header (slave mode) */
+#define I2C_STAT1_DUMODF              BIT(7)        /*!< dual flag (slave mode) */
+#define I2C_STAT1_PECV                BITS(8,15)    /*!< packet error checking value */
+
+/* I2Cx_CKCFG */
+#define I2C_CKCFG_CLKC                BITS(0,11)    /*!< clock control register in fast/standard mode (master mode) */
+#define I2C_CKCFG_DTCY                BIT(14)       /*!< fast mode duty cycle */
+#define I2C_CKCFG_FAST                BIT(15)       /*!< I2C speed selection in master mode */
+
+/* I2Cx_RT */
+#define I2C_RT_RISETIME               BITS(0,5)     /*!< maximum rise time in fast/standard mode (Master mode) */
+
+/* constants definitions */
+/* define the I2C bit position and its register index offset */
+#define I2C_REGIDX_BIT(regidx, bitpos)  (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define I2C_REG_VAL(i2cx, offset)       (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
+#define I2C_BIT_POS(val)                ((uint32_t)(val) & 0x1FU)
+#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)   (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
+                                                              | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
+#define I2C_REG_VAL2(i2cx, offset)      (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
+#define I2C_BIT_POS2(val)               (((uint32_t)(val) & 0x1F0000U) >> 16)
+
+/* register offset */
+#define I2C_CTL1_REG_OFFSET           0x04U         /*!< CTL1 register offset */
+#define I2C_STAT0_REG_OFFSET          0x14U         /*!< STAT0 register offset */
+#define I2C_STAT1_REG_OFFSET          0x18U         /*!< STAT1 register offset */
+
+/* I2C flags */
+typedef enum {
+    /* flags in STAT0 register */
+    I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
+    I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
+    I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
+    I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
+    I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
+    I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
+    I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
+    I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
+    I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
+    I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
+    I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
+    I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
+    I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
+    I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
+    /* flags in STAT1 register */
+    I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
+    I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
+    I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
+    I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
+    I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
+    I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
+    I2C_FLAG_DUMODF = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
+} i2c_flag_enum;
+
+/* I2C interrupt flags */
+typedef enum {
+    /* interrupt flags in CTL1 register */
+    I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
+    I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
+    I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
+    I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
+    I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
+    I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
+    I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
+    I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
+    I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
+    I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
+    I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
+    I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
+    I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
+    I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
+} i2c_interrupt_flag_enum;
+
+/* I2C interrupt enable or disable */
+typedef enum {
+    /* interrupt in CTL1 register */
+    I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
+    I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
+    I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
+} i2c_interrupt_enum;
+
+/* SMBus/I2C mode switch and SMBus type selection */
+#define I2C_I2CMODE_ENABLE            ((uint32_t)0x00000000U)                  /*!< I2C mode */
+#define I2C_SMBUSMODE_ENABLE          I2C_CTL0_SMBEN                           /*!< SMBus mode */
+
+/* SMBus/I2C mode switch and SMBus type selection */
+#define I2C_SMBUS_DEVICE              ((uint32_t)0x00000000U)                  /*!< SMBus mode device type */
+#define I2C_SMBUS_HOST                I2C_CTL0_SMBSEL                          /*!< SMBus mode host type */
+
+/* I2C transfer direction */
+#define I2C_RECEIVER                  ((uint32_t)0x00000001U)                  /*!< receiver */
+#define I2C_TRANSMITTER               ((uint32_t)0xFFFFFFFEU)                  /*!< transmitter */
+
+/* whether or not to send an ACK */
+#define I2C_ACK_DISABLE               ((uint32_t)0x00000000U)                  /*!< ACK will be not sent */
+#define I2C_ACK_ENABLE                ((uint32_t)0x00000001U)                  /*!< ACK will be sent */
+
+/* I2C POAP position*/
+#define I2C_ACKPOS_NEXT               ((uint32_t)0x00000000U)                  /*!< ACKEN bit decides whether or not to send ACK for the next byte */
+#define I2C_ACKPOS_CURRENT            ((uint32_t)0x00000001U)                  /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
+
+/* I2C dual-address mode switch */
+#define I2C_DUADEN_DISABLE            ((uint32_t)0x00000000U)                  /*!< dual-address mode disabled */
+#define I2C_DUADEN_ENABLE             ((uint32_t)0x00000001U)                  /*!< dual-address mode enabled */
+
+/* whether or not to stretch SCL low */
+#define I2C_SCLSTRETCH_ENABLE         ((uint32_t)0x00000000U)                  /*!< SCL stretching is enabled */
+#define I2C_SCLSTRETCH_DISABLE        I2C_CTL0_SS                              /*!< SCL stretching is disabled */
+
+/* whether or not to response to a general call */
+#define I2C_GCEN_ENABLE               I2C_CTL0_GCEN                            /*!< slave will response to a general call */
+#define I2C_GCEN_DISABLE              ((uint32_t)0x00000000U)                  /*!< slave will not response to a general call */
+
+/* software reset I2C */
+#define I2C_SRESET_SET                I2C_CTL0_SRESET                          /*!< I2C is under reset */
+#define I2C_SRESET_RESET              ((uint32_t)0x00000000U)                  /*!< I2C is not under reset */
+
+/* I2C DMA mode configure */
+/* DMA mode switch */
+#define I2C_DMA_ON                    I2C_CTL1_DMAON                           /*!< DMA mode enabled */
+#define I2C_DMA_OFF                   ((uint32_t)0x00000000U)                  /*!< DMA mode disabled */
+
+/* flag indicating DMA last transfer */
+#define I2C_DMALST_ON                 I2C_CTL1_DMALST                          /*!< next DMA EOT is the last transfer */
+#define I2C_DMALST_OFF                ((uint32_t)0x00000000U)                  /*!< next DMA EOT is not the last transfer */
+
+/* I2C PEC configure */
+/* PEC enable */
+#define I2C_PEC_ENABLE                I2C_CTL0_PECEN                           /*!< PEC calculation on */
+#define I2C_PEC_DISABLE               ((uint32_t)0x00000000U)                   /*!< PEC calculation off */
+
+/* PEC transfer */
+#define I2C_PECTRANS_ENABLE           I2C_CTL0_PECTRANS                        /*!< transfer PEC */
+#define I2C_PECTRANS_DISABLE          ((uint32_t)0x00000000U)                  /*!< not transfer PEC value */
+
+/* I2C SMBus configure */
+/* issue or not alert through SMBA pin */
+#define I2C_SALTSEND_ENABLE           I2C_CTL0_SALT                            /*!< issue alert through SMBA pin */
+#define I2C_SALTSEND_DISABLE          ((uint32_t)0x00000000U)                  /*!< not issue alert through SMBA */
+
+/* ARP protocol in SMBus switch */
+#define I2C_ARP_ENABLE                I2C_CTL0_ARPEN                           /*!< ARP enable */
+#define I2C_ARP_DISABLE               ((uint32_t)0x00000000U)                  /*!< ARP disable */
+
+/* transmit I2C data */
+#define DATA_TRANS(regval)            (BITS(0,7) & ((uint32_t)(regval) << 0))
+
+/* receive I2C data */
+#define DATA_RECV(regval)             GET_BITS((uint32_t)(regval), 0, 7)
+
+/* I2C duty cycle in fast mode */
+#define I2C_DTCY_2                    ((uint32_t)0x00000000U)                  /*!< I2C fast mode Tlow/Thigh = 2 */
+#define I2C_DTCY_16_9                 I2C_CKCFG_DTCY                           /*!< I2C fast mode Tlow/Thigh = 16/9 */
+
+/* address mode for the I2C slave */
+#define I2C_ADDFORMAT_7BITS           ((uint32_t)0x00000000U)                  /*!< address:7 bits */
+#define I2C_ADDFORMAT_10BITS          I2C_SADDR0_ADDFORMAT                     /*!< address:10 bits */
+
+/* function declarations */
+/* reset I2C */
+void i2c_deinit(uint32_t i2c_periph);
+/* configure I2C clock */
+void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
+/* configure I2C address */
+void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr);
+/* SMBus type selection */
+void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
+/* whether or not to send an ACK */
+void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
+/* configure I2C POAP position */
+void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
+/* master sends slave address */
+void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection);
+/* configure I2C saddress1 */
+void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr);
+/* enable dual-address mode */
+void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
+/* disable dual-address mode */
+void i2c_dualaddr_disable(uint32_t i2c_periph);
+/* enable I2C */
+void i2c_enable(uint32_t i2c_periph);
+/* disable I2C */
+void i2c_disable(uint32_t i2c_periph);
+
+/* generate a START condition on I2C bus */
+void i2c_start_on_bus(uint32_t i2c_periph);
+/* generate a STOP condition on I2C bus */
+void i2c_stop_on_bus(uint32_t i2c_periph);
+/* I2C transmit data function */
+void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
+/* I2C receive data function */
+uint8_t i2c_data_receive(uint32_t i2c_periph);
+/* enable I2C DMA mode */
+void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
+/* configure whether next DMA EOT is DMA last transfer or not */
+void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
+/* whether to stretch SCL low when data is not ready in slave mode */
+void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
+/* whether or not to response to a general call */
+void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
+/* software reset I2C */
+void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
+
+/* I2C PEC calculation on or off */
+void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
+/* I2C whether to transfer PEC value */
+void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
+/* packet error checking value */
+uint8_t i2c_pec_value_get(uint32_t i2c_periph);
+/* I2C issue alert through SMBA pin */
+void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
+/* I2C ARP protocol in SMBus switch */
+void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
+
+/* check I2C flag is set or not */
+FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
+/* clear I2C flag */
+void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
+/* enable I2C interrupt */
+void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
+/* disable I2C interrupt */
+void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
+/* check I2C interrupt flag */
+FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag);
+/* clear I2C interrupt flag */
+void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag);
+
+#endif /* GD32VF103_I2C_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h
new file mode 100644
index 0000000000..244038127f
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h
@@ -0,0 +1,125 @@
+/*!
+    \file    gd32vf103_pmu.h
+    \brief   definitions for the PMU
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_PMU_H
+#define GD32VF103_PMU_H
+
+#include "gd32vf103.h"
+
+/* PMU definitions */
+#define PMU                           PMU_BASE                 /*!< PMU base address */
+
+/* registers definitions */
+#define PMU_CTL                       REG32((PMU) + 0x00U)     /*!< PMU control register */
+#define PMU_CS                        REG32((PMU) + 0x04U)     /*!< PMU control and status register */
+
+/* bits definitions */
+/* PMU_CTL */
+#define PMU_CTL_LDOLP                 BIT(0)                   /*!< LDO low power mode */
+#define PMU_CTL_STBMOD                BIT(1)                   /*!< standby mode */
+#define PMU_CTL_WURST                 BIT(2)                   /*!< wakeup flag reset */
+#define PMU_CTL_STBRST                BIT(3)                   /*!< standby flag reset */
+#define PMU_CTL_LVDEN                 BIT(4)                   /*!< low voltage detector enable */
+#define PMU_CTL_LVDT                  BITS(5,7)                /*!< low voltage detector threshold */
+#define PMU_CTL_BKPWEN                BIT(8)                   /*!< backup domain write enable */
+
+/* PMU_CS */
+#define PMU_CS_WUF                    BIT(0)                   /*!< wakeup flag */
+#define PMU_CS_STBF                   BIT(1)                   /*!< standby flag */
+#define PMU_CS_LVDF                   BIT(2)                   /*!< low voltage detector status flag */
+#define PMU_CS_WUPEN                  BIT(8)                   /*!< wakeup pin enable */
+
+/* constants definitions */
+/* PMU low voltage detector threshold definitions */
+#define CTL_LVDT(regval)              (BITS(5,7)&((uint32_t)(regval) << 5))
+#define PMU_LVDT_0                    CTL_LVDT(0)              /*!< voltage threshold is 2.2V */
+#define PMU_LVDT_1                    CTL_LVDT(1)              /*!< voltage threshold is 2.3V */
+#define PMU_LVDT_2                    CTL_LVDT(2)              /*!< voltage threshold is 2.4V */
+#define PMU_LVDT_3                    CTL_LVDT(3)              /*!< voltage threshold is 2.5V */
+#define PMU_LVDT_4                    CTL_LVDT(4)              /*!< voltage threshold is 2.6V */
+#define PMU_LVDT_5                    CTL_LVDT(5)              /*!< voltage threshold is 2.7V */
+#define PMU_LVDT_6                    CTL_LVDT(6)              /*!< voltage threshold is 2.8V */
+#define PMU_LVDT_7                    CTL_LVDT(7)              /*!< voltage threshold is 2.9V */
+
+/* PMU flag definitions */
+#define PMU_FLAG_WAKEUP               PMU_CS_WUF               /*!< wakeup flag status */
+#define PMU_FLAG_STANDBY              PMU_CS_STBF              /*!< standby flag status */
+#define PMU_FLAG_LVD                  PMU_CS_LVDF              /*!< lvd flag status */
+
+/* PMU ldo definitions */
+#define PMU_LDO_NORMAL                ((uint32_t)0x00000000U)  /*!< LDO normal work when PMU enter deepsleep mode */
+#define PMU_LDO_LOWPOWER              PMU_CTL_LDOLP            /*!< LDO work at low power status when PMU enter deepsleep mode */
+
+/* PMU flag reset definitions */
+#define PMU_FLAG_RESET_WAKEUP         ((uint8_t)0x00U)         /*!< wakeup flag reset */
+#define PMU_FLAG_RESET_STANDBY        ((uint8_t)0x01U)         /*!< standby flag reset */
+
+/* PMU command constants definitions */
+#define WFI_CMD                       ((uint8_t)0x00U)         /*!< use WFI command */
+#define WFE_CMD                       ((uint8_t)0x01U)         /*!< use WFE command */
+
+/* function declarations */
+/* reset PMU registers */
+void pmu_deinit(void);
+
+/* select low voltage detector threshold */
+void pmu_lvd_select(uint32_t lvdt_n);
+/* disable PMU lvd */
+void pmu_lvd_disable(void);
+
+/* set PMU mode */
+/* PMU work at sleep mode */
+void pmu_to_sleepmode(uint8_t sleepmodecmd);
+/* PMU work at deepsleep mode */
+void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
+/* PMU work at standby mode */
+void pmu_to_standbymode(uint8_t standbymodecmd);
+/* enable PMU wakeup pin */
+void pmu_wakeup_pin_enable(void);
+/* disable PMU wakeup pin */
+void pmu_wakeup_pin_disable(void);
+
+/* backup related functions */
+/* enable write access to the registers in backup domain */
+void pmu_backup_write_enable(void);
+/* disable write access to the registers in backup domain */
+void pmu_backup_write_disable(void);
+
+/* flag functions */
+/* get flag state */
+FlagStatus pmu_flag_get(uint32_t flag);
+/* clear flag bit */
+void pmu_flag_clear(uint32_t flag_reset);
+
+#endif /* GD32VF103_PMU_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h
new file mode 100644
index 0000000000..56afb42ac7
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h
@@ -0,0 +1,720 @@
+/*!
+    \file    gd32vf103_rcu.h
+    \brief   definitions for the RCU
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_RCU_H
+#define GD32VF103_RCU_H
+
+#include "gd32vf103.h"
+
+/* RCU definitions */
+#define RCU                             RCU_BASE
+
+/* registers definitions */
+
+#define RCU_CTL                         REG32(RCU + 0x00U)        /*!< control register */
+#define RCU_CFG0                        REG32(RCU + 0x04U)        /*!< clock configuration register 0 */
+#define RCU_INT                         REG32(RCU + 0x08U)        /*!< clock interrupt register */
+#define RCU_APB2RST                     REG32(RCU + 0x0CU)        /*!< APB2 reset register */
+#define RCU_APB1RST                     REG32(RCU + 0x10U)        /*!< APB1 reset register */
+#define RCU_AHBEN                       REG32(RCU + 0x14U)        /*!< AHB1 enable register */
+#define RCU_APB2EN                      REG32(RCU + 0x18U)        /*!< APB2 enable register */
+#define RCU_APB1EN                      REG32(RCU + 0x1CU)        /*!< APB1 enable register */
+#define RCU_BDCTL                       REG32(RCU + 0x20U)        /*!< backup domain control register */
+#define RCU_RSTSCK                      REG32(RCU + 0x24U)        /*!< reset source / clock register */
+#define RCU_AHBRST                      REG32(RCU + 0x28U)        /*!< AHB reset register */
+#define RCU_CFG1                        REG32(RCU + 0x2CU)        /*!< clock configuration register 1 */
+#define RCU_DSV                         REG32(RCU + 0x34U)        /*!< deep-sleep mode voltage register */
+
+
+/* bits definitions */
+/* RCU_CTL */
+#define RCU_CTL_IRC8MEN                 BIT(0)                    /*!< internal high speed oscillator enable */
+#define RCU_CTL_IRC8MSTB                BIT(1)                    /*!< IRC8M high speed internal oscillator stabilization flag */
+#define RCU_CTL_IRC8MADJ                BITS(3,7)                 /*!< high speed internal oscillator clock trim adjust value */
+#define RCU_CTL_IRC8MCALIB              BITS(8,15)                /*!< high speed internal oscillator calibration value register */
+#define RCU_CTL_HXTALEN                 BIT(16)                   /*!< external high speed oscillator enable */
+#define RCU_CTL_HXTALSTB                BIT(17)                   /*!< external crystal oscillator clock stabilization flag */
+#define RCU_CTL_HXTALBPS                BIT(18)                   /*!< external crystal oscillator clock bypass mode enable */
+#define RCU_CTL_CKMEN                   BIT(19)                   /*!< HXTAL clock monitor enable */
+#define RCU_CTL_PLLEN                   BIT(24)                   /*!< PLL enable */
+#define RCU_CTL_PLLSTB                  BIT(25)                   /*!< PLL clock stabilization flag */
+#define RCU_CTL_PLL1EN                  BIT(26)                   /*!< PLL1 enable */
+#define RCU_CTL_PLL1STB                 BIT(27)                   /*!< PLL1 clock stabilization flag */
+#define RCU_CTL_PLL2EN                  BIT(28)                   /*!< PLL2 enable */
+#define RCU_CTL_PLL2STB                 BIT(29)                   /*!< PLL2 clock stabilization flag */
+
+
+#define RCU_CFG0_SCS                    BITS(0,1)                 /*!< system clock switch */
+#define RCU_CFG0_SCSS                   BITS(2,3)                 /*!< system clock switch status */
+#define RCU_CFG0_AHBPSC                 BITS(4,7)                 /*!< AHB prescaler selection */
+#define RCU_CFG0_APB1PSC                BITS(8,10)                /*!< APB1 prescaler selection */
+#define RCU_CFG0_APB2PSC                BITS(11,13)               /*!< APB2 prescaler selection */
+#define RCU_CFG0_ADCPSC                 BITS(14,15)               /*!< ADC prescaler selection */
+#define RCU_CFG0_PLLSEL                 BIT(16)                   /*!< PLL clock source selection */
+#define RCU_CFG0_PREDV0_LSB             BIT(17)                   /*!< the LSB of PREDV0 division factor */
+#define RCU_CFG0_PLLMF                  BITS(18,21)               /*!< PLL clock multiplication factor */
+#define RCU_CFG0_USBFSPSC               BITS(22,23)               /*!< USBFS clock prescaler selection */
+#define RCU_CFG0_CKOUT0SEL              BITS(24,27)               /*!< CKOUT0 clock source selection */
+#define RCU_CFG0_ADCPSC_2               BIT(28)                   /*!< bit 2 of ADCPSC */
+#define RCU_CFG0_PLLMF_4                BIT(29)                   /*!< bit 4 of PLLMF */
+
+/* RCU_INT */
+#define RCU_INT_IRC40KSTBIF             BIT(0)                    /*!< IRC40K stabilization interrupt flag */
+#define RCU_INT_LXTALSTBIF              BIT(1)                    /*!< LXTAL stabilization interrupt flag */
+#define RCU_INT_IRC8MSTBIF              BIT(2)                    /*!< IRC8M stabilization interrupt flag */
+#define RCU_INT_HXTALSTBIF              BIT(3)                    /*!< HXTAL stabilization interrupt flag */
+#define RCU_INT_PLLSTBIF                BIT(4)                    /*!< PLL stabilization interrupt flag */
+#define RCU_INT_PLL1STBIF               BIT(5)                    /*!< PLL1 stabilization interrupt flag */
+#define RCU_INT_PLL2STBIF               BIT(6)                    /*!< PLL2 stabilization interrupt flag */
+#define RCU_INT_CKMIF                   BIT(7)                    /*!< HXTAL clock stuck interrupt flag */
+#define RCU_INT_IRC40KSTBIE             BIT(8)                    /*!< IRC40K stabilization interrupt enable */
+#define RCU_INT_LXTALSTBIE              BIT(9)                    /*!< LXTAL stabilization interrupt enable */
+#define RCU_INT_IRC8MSTBIE              BIT(10)                   /*!< IRC8M stabilization interrupt enable */
+#define RCU_INT_HXTALSTBIE              BIT(11)                   /*!< HXTAL stabilization interrupt enable */
+#define RCU_INT_PLLSTBIE                BIT(12)                   /*!< PLL stabilization interrupt enable */
+#define RCU_INT_PLL1STBIE               BIT(13)                   /*!< PLL1 stabilization interrupt enable */
+#define RCU_INT_PLL2STBIE               BIT(14)                   /*!< PLL2 stabilization interrupt enable */
+#define RCU_INT_IRC40KSTBIC             BIT(16)                   /*!< IRC40K stabilization interrupt clear */
+#define RCU_INT_LXTALSTBIC              BIT(17)                   /*!< LXTAL stabilization interrupt clear */
+#define RCU_INT_IRC8MSTBIC              BIT(18)                   /*!< IRC8M stabilization interrupt clear */
+#define RCU_INT_HXTALSTBIC              BIT(19)                   /*!< HXTAL stabilization interrupt clear */
+#define RCU_INT_PLLSTBIC                BIT(20)                   /*!< PLL stabilization interrupt clear */
+#define RCU_INT_PLL1STBIC               BIT(21)                   /*!< PLL1 stabilization interrupt clear */
+#define RCU_INT_PLL2STBIC               BIT(22)                   /*!< PLL2 stabilization interrupt clear */
+#define RCU_INT_CKMIC                   BIT(23)                   /*!< HXTAL clock stuck interrupt clear */
+
+/* RCU_APB2RST */
+#define RCU_APB2RST_AFRST               BIT(0)                    /*!< alternate function I/O reset */
+#define RCU_APB2RST_PARST               BIT(2)                    /*!< GPIO port A reset */
+#define RCU_APB2RST_PBRST               BIT(3)                    /*!< GPIO port B reset */
+#define RCU_APB2RST_PCRST               BIT(4)                    /*!< GPIO port C reset */
+#define RCU_APB2RST_PDRST               BIT(5)                    /*!< GPIO port D reset */
+#define RCU_APB2RST_PERST               BIT(6)                    /*!< GPIO port E reset */
+#define RCU_APB2RST_ADC0RST             BIT(9)                    /*!< ADC0 reset */
+#define RCU_APB2RST_ADC1RST             BIT(10)                   /*!< ADC1 reset */
+#define RCU_APB2RST_TIMER0RST           BIT(11)                   /*!< TIMER0 reset */
+#define RCU_APB2RST_SPI0RST             BIT(12)                   /*!< SPI0 reset */
+#define RCU_APB2RST_USART0RST           BIT(14)                   /*!< USART0 reset */
+
+/* RCU_APB1RST */
+#define RCU_APB1RST_TIMER1RST           BIT(0)                    /*!< TIMER1 reset */
+#define RCU_APB1RST_TIMER2RST           BIT(1)                    /*!< TIMER2 reset */
+#define RCU_APB1RST_TIMER3RST           BIT(2)                    /*!< TIMER3 reset */
+#define RCU_APB1RST_TIMER4RST           BIT(3)                    /*!< TIMER4 reset */
+#define RCU_APB1RST_TIMER5RST           BIT(4)                    /*!< TIMER5 reset */
+#define RCU_APB1RST_TIMER6RST           BIT(5)                    /*!< TIMER6 reset */
+
+#define RCU_APB1RST_WWDGTRST            BIT(11)                   /*!< WWDGT reset */
+#define RCU_APB1RST_SPI1RST             BIT(14)                   /*!< SPI1 reset */
+#define RCU_APB1RST_SPI2RST             BIT(15)                   /*!< SPI2 reset */
+#define RCU_APB1RST_USART1RST           BIT(17)                   /*!< USART1 reset */
+#define RCU_APB1RST_USART2RST           BIT(18)                   /*!< USART2 reset */
+#define RCU_APB1RST_UART3RST            BIT(19)                   /*!< UART3 reset */
+#define RCU_APB1RST_UART4RST            BIT(20)                   /*!< UART4 reset */
+#define RCU_APB1RST_I2C0RST             BIT(21)                   /*!< I2C0 reset */
+#define RCU_APB1RST_I2C1RST             BIT(22)                   /*!< I2C1 reset */
+#define RCU_APB1RST_CAN0RST             BIT(25)                   /*!< CAN0 reset */
+#define RCU_APB1RST_CAN1RST             BIT(26)                   /*!< CAN1 reset */
+#define RCU_APB1RST_BKPIRST             BIT(27)                   /*!< backup interface reset */
+#define RCU_APB1RST_PMURST              BIT(28)                   /*!< PMU reset */
+#define RCU_APB1RST_DACRST              BIT(29)                   /*!< DAC reset */
+
+/* RCU_AHBEN */
+#define RCU_AHBEN_DMA0EN                BIT(0)                    /*!< DMA0 clock enable */
+#define RCU_AHBEN_DMA1EN                BIT(1)                    /*!< DMA1 clock enable */
+#define RCU_AHBEN_SRAMSPEN              BIT(2)                    /*!< SRAM clock enable when sleep mode */
+#define RCU_AHBEN_FMCSPEN               BIT(4)                    /*!< FMC clock enable when sleep mode */
+#define RCU_AHBEN_CRCEN                 BIT(6)                    /*!< CRC clock enable */
+#define RCU_AHBEN_EXMCEN                BIT(8)                    /*!< EXMC clock enable */
+#define RCU_AHBEN_USBFSEN               BIT(12)                   /*!< USBFS clock enable */
+
+/* RCU_APB2EN */
+#define RCU_APB2EN_AFEN                 BIT(0)                    /*!< alternate function IO clock enable */
+#define RCU_APB2EN_PAEN                 BIT(2)                    /*!< GPIO port A clock enable */
+#define RCU_APB2EN_PBEN                 BIT(3)                    /*!< GPIO port B clock enable */
+#define RCU_APB2EN_PCEN                 BIT(4)                    /*!< GPIO port C clock enable */
+#define RCU_APB2EN_PDEN                 BIT(5)                    /*!< GPIO port D clock enable */
+#define RCU_APB2EN_PEEN                 BIT(6)                    /*!< GPIO port E clock enable */
+#define RCU_APB2EN_ADC0EN               BIT(9)                    /*!< ADC0 clock enable */
+#define RCU_APB2EN_ADC1EN               BIT(10)                   /*!< ADC1 clock enable */
+#define RCU_APB2EN_TIMER0EN             BIT(11)                   /*!< TIMER0 clock enable */
+#define RCU_APB2EN_SPI0EN               BIT(12)                   /*!< SPI0 clock enable */
+#define RCU_APB2EN_USART0EN             BIT(14)                   /*!< USART0 clock enable */
+
+/* RCU_APB1EN */
+#define RCU_APB1EN_TIMER1EN             BIT(0)                    /*!< TIMER1 clock enable */
+#define RCU_APB1EN_TIMER2EN             BIT(1)                    /*!< TIMER2 clock enable */
+#define RCU_APB1EN_TIMER3EN             BIT(2)                    /*!< TIMER3 clock enable */
+#define RCU_APB1EN_TIMER4EN             BIT(3)                    /*!< TIMER4 clock enable */
+#define RCU_APB1EN_TIMER5EN             BIT(4)                    /*!< TIMER5 clock enable */
+#define RCU_APB1EN_TIMER6EN             BIT(5)                    /*!< TIMER6 clock enable */
+#define RCU_APB1EN_WWDGTEN              BIT(11)                   /*!< WWDGT clock enable */
+#define RCU_APB1EN_SPI1EN               BIT(14)                   /*!< SPI1 clock enable */
+#define RCU_APB1EN_SPI2EN               BIT(15)                   /*!< SPI2 clock enable */
+#define RCU_APB1EN_USART1EN             BIT(17)                   /*!< USART1 clock enable */
+#define RCU_APB1EN_USART2EN             BIT(18)                   /*!< USART2 clock enable */
+#define RCU_APB1EN_UART3EN              BIT(19)                   /*!< UART3 clock enable */
+#define RCU_APB1EN_UART4EN              BIT(20)                   /*!< UART4 clock enable */
+#define RCU_APB1EN_I2C0EN               BIT(21)                   /*!< I2C0 clock enable */
+#define RCU_APB1EN_I2C1EN               BIT(22)                   /*!< I2C1 clock enable */
+#define RCU_APB1EN_CAN0EN               BIT(25)                   /*!< CAN0 clock enable */
+#define RCU_APB1EN_CAN1EN               BIT(26)                   /*!< CAN1 clock enable */
+#define RCU_APB1EN_BKPIEN               BIT(27)                   /*!< backup interface clock enable */
+#define RCU_APB1EN_PMUEN                BIT(28)                   /*!< PMU clock enable */
+#define RCU_APB1EN_DACEN                BIT(29)                   /*!< DAC clock enable */
+
+/* RCU_BDCTL */
+#define RCU_BDCTL_LXTALEN               BIT(0)                    /*!< LXTAL enable */
+#define RCU_BDCTL_LXTALSTB              BIT(1)                    /*!< low speed crystal oscillator stabilization flag */
+#define RCU_BDCTL_LXTALBPS              BIT(2)                    /*!< LXTAL bypass mode enable */
+#define RCU_BDCTL_RTCSRC                BITS(8,9)                 /*!< RTC clock entry selection */
+#define RCU_BDCTL_RTCEN                 BIT(15)                   /*!< RTC clock enable */
+#define RCU_BDCTL_BKPRST                BIT(16)                   /*!< backup domain reset */
+
+/* RCU_RSTSCK */
+#define RCU_RSTSCK_IRC40KEN             BIT(0)                    /*!< IRC40K enable */
+#define RCU_RSTSCK_IRC40KSTB            BIT(1)                    /*!< IRC40K stabilization flag */
+#define RCU_RSTSCK_RSTFC                BIT(24)                   /*!< reset flag clear */
+#define RCU_RSTSCK_EPRSTF               BIT(26)                   /*!< external pin reset flag */
+#define RCU_RSTSCK_PORRSTF              BIT(27)                   /*!< power reset flag */
+#define RCU_RSTSCK_SWRSTF               BIT(28)                   /*!< software reset flag */
+#define RCU_RSTSCK_FWDGTRSTF            BIT(29)                   /*!< free watchdog timer reset flag */
+#define RCU_RSTSCK_WWDGTRSTF            BIT(30)                   /*!< window watchdog timer reset flag */
+#define RCU_RSTSCK_LPRSTF               BIT(31)                   /*!< low-power reset flag */
+
+/* RCU_AHBRST */
+#define RCU_AHBRST_USBFSRST             BIT(12)                   /*!< USBFS reset */
+
+/* RCU_CFG1 */
+#define RCU_CFG1_PREDV0                 BITS(0,3)                 /*!< PREDV0 division factor */
+#define RCU_CFG1_PREDV1                 BITS(4,7)                 /*!< PREDV1 division factor */
+#define RCU_CFG1_PLL1MF                 BITS(8,11)                /*!< PLL1 clock multiplication factor */
+#define RCU_CFG1_PLL2MF                 BITS(12,15)               /*!< PLL2 clock multiplication factor */
+#define RCU_CFG1_PREDV0SEL              BIT(16)                   /*!< PREDV0 input clock source selection */
+#define RCU_CFG1_I2S1SEL                BIT(17)                   /*!< I2S1 clock source selection */
+#define RCU_CFG1_I2S2SEL                BIT(18)                   /*!< I2S2 clock source selection  */
+
+/* RCU_DSV */
+#define RCU_DSV_DSLPVS                  BITS(0,1)                 /*!< deep-sleep mode voltage select */
+
+/* constants definitions */
+/* define the peripheral clock enable bit position and its register index offset */
+#define RCU_REGIDX_BIT(regidx, bitpos)      (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define RCU_REG_VAL(periph)                 (REG32(RCU + ((uint32_t)(periph) >> 6)))
+#define RCU_BIT_POS(val)                    ((uint32_t)(val) & 0x1FU)
+
+/* register offset */
+/* peripherals enable */
+#define AHBEN_REG_OFFSET                0x14U                     /*!< AHB enable register offset */
+#define APB1EN_REG_OFFSET               0x1CU                     /*!< APB1 enable register offset */
+#define APB2EN_REG_OFFSET               0x18U                     /*!< APB2 enable register offset */
+
+/* peripherals reset */
+#define AHBRST_REG_OFFSET               0x28U                     /*!< AHB reset register offset */
+#define APB1RST_REG_OFFSET              0x10U                     /*!< APB1 reset register offset */
+#define APB2RST_REG_OFFSET              0x0CU                     /*!< APB2 reset register offset */
+#define RSTSCK_REG_OFFSET               0x24U                     /*!< reset source/clock register offset */
+
+/* clock control */
+#define CTL_REG_OFFSET                  0x00U                     /*!< control register offset */
+#define BDCTL_REG_OFFSET                0x20U                     /*!< backup domain control register offset */
+
+/* clock stabilization and stuck interrupt */
+#define INT_REG_OFFSET                  0x08U                     /*!< clock interrupt register offset */
+
+/* configuration register */
+#define CFG0_REG_OFFSET                 0x04U                     /*!< clock configuration register 0 offset */
+#define CFG1_REG_OFFSET                 0x2CU                     /*!< clock configuration register 1 offset */
+
+/* peripheral clock enable */
+typedef enum {
+	/* AHB peripherals */
+	RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U),              /*!< DMA0 clock */
+	RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U),              /*!< DMA1 clock */
+	RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U),               /*!< CRC clock */
+	RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U),              /*!< EXMC clock */
+	RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U),            /*!< USBFS clock */
+	/* APB1 peripherals */
+	RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U),           /*!< TIMER1 clock */
+	RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U),           /*!< TIMER2 clock */
+	RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U),           /*!< TIMER3 clock */
+	RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U),           /*!< TIMER4 clock */
+	RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U),           /*!< TIMER5 clock */
+	RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U),           /*!< TIMER6 clock */
+	RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U),           /*!< WWDGT clock */
+	RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U),            /*!< SPI1 clock */
+	RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U),            /*!< SPI2 clock */
+	RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U),          /*!< USART1 clock */
+	RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U),          /*!< USART2 clock */
+	RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U),           /*!< UART3 clock */
+	RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U),           /*!< UART4 clock */
+	RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U),            /*!< I2C0 clock */
+	RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U),            /*!< I2C1 clock */
+	RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U),            /*!< CAN0 clock */
+	RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U),            /*!< CAN1 clock */
+	RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U),            /*!< BKPI clock */
+	RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U),             /*!< PMU clock */
+	RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U),             /*!< DAC clock */
+	RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U),              /*!< RTC clock */
+	/* APB2 peripherals */
+	RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U),               /*!< alternate function clock */
+	RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U),            /*!< GPIOA clock */
+	RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U),            /*!< GPIOB clock */
+	RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U),            /*!< GPIOC clock */
+	RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U),            /*!< GPIOD clock */
+	RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U),            /*!< GPIOE clock */
+	RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U),             /*!< ADC0 clock */
+	RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U),            /*!< ADC1 clock */
+	RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U),          /*!< TIMER0 clock */
+	RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U),            /*!< SPI0 clock */
+	RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U),          /*!< USART0 clock */
+} rcu_periph_enum;
+
+/* peripheral clock enable when sleep mode*/
+typedef enum {
+/* AHB peripherals */
+	RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U),          /*!< SRAM clock */
+	RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U),           /*!< FMC clock */
+} rcu_periph_sleep_enum;
+
+/* peripherals reset */
+typedef enum {
+	/* AHB peripherals */
+	RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U),        /*!< USBFS clock reset */
+	/* APB1 peripherals */
+	RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U),       /*!< TIMER1 clock reset */
+	RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U),       /*!< TIMER2 clock reset */
+	RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U),       /*!< TIMER3 clock reset */
+	RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U),       /*!< TIMER4 clock reset */
+	RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U),       /*!< TIMER5 clock reset */
+	RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U),       /*!< TIMER6 clock reset */
+	RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U),       /*!< WWDGT clock reset */
+	RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U),        /*!< SPI1 clock reset */
+	RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U),        /*!< SPI2 clock reset */
+	RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U),      /*!< USART1 clock reset */
+	RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U),      /*!< USART2 clock reset */
+	RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U),       /*!< UART3 clock reset */
+	RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U),       /*!< UART4 clock reset */
+	RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U),        /*!< I2C0 clock reset */
+	RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U),        /*!< I2C1 clock reset */
+	RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U),        /*!< CAN0 clock reset */
+	RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U),        /*!< CAN1 clock reset */
+	RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U),        /*!< BKPI clock reset */
+	RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U),         /*!< PMU clock reset */
+	RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U),         /*!< DAC clock reset */
+	/* APB2 peripherals */
+	RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U),           /*!< alternate function clock reset */
+	RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U),        /*!< GPIOA clock reset */
+	RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U),        /*!< GPIOB clock reset */
+	RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U),        /*!< GPIOC clock reset */
+	RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U),        /*!< GPIOD clock reset */
+	RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U),        /*!< GPIOE clock reset */
+	RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U),         /*!< ADC0 clock reset */
+	RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U),        /*!< ADC1 clock reset */
+	RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U),      /*!< TIMER0 clock reset */
+	RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U),        /*!< SPI0 clock reset */
+	RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U),      /*!< USART0 clock reset */
+} rcu_periph_reset_enum;
+
+/* clock stabilization and peripheral reset flags */
+typedef enum {
+	/* clock stabilization flags */
+	RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U),       /*!< IRC8M stabilization flags */
+	RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U),      /*!< HXTAL stabilization flags */
+	RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U),        /*!< PLL stabilization flags */
+	RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U),       /*!< PLL1 stabilization flags */
+	RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U),       /*!< PLL2 stabilization flags */
+	RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U),     /*!< LXTAL stabilization flags */
+	RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U),   /*!< IRC40K stabilization flags */
+	/* reset source flags */
+	RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U),      /*!< external PIN reset flags */
+	RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U),     /*!< power reset flags */
+	RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U),      /*!< software reset flags */
+	RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U),   /*!< FWDGT reset flags */
+	RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U),   /*!< WWDGT reset flags */
+	RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U),      /*!< low-power reset flags */
+} rcu_flag_enum;
+
+/* clock stabilization and ckm interrupt flags */
+typedef enum {
+	RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U),  /*!< IRC40K stabilization interrupt flag */
+	RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U),   /*!< LXTAL stabilization interrupt flag */
+	RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U),   /*!< IRC8M stabilization interrupt flag */
+	RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U),   /*!< HXTAL stabilization interrupt flag */
+	RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U),     /*!< PLL stabilization interrupt flag */
+	RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U),    /*!< PLL1 stabilization interrupt flag */
+	RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U),    /*!< PLL2 stabilization interrupt flag */
+	RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U),        /*!< HXTAL clock stuck interrupt flag */
+} rcu_int_flag_enum;
+
+/* clock stabilization and stuck interrupt flags clear */
+typedef enum {
+	RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */
+	RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U),  /*!< LXTAL stabilization interrupt flags clear */
+	RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U),  /*!< IRC8M stabilization interrupt flags clear */
+	RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U),  /*!< HXTAL stabilization interrupt flags clear */
+	RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U),    /*!< PLL stabilization interrupt flags clear */
+	RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U),   /*!< PLL1 stabilization interrupt flags clear */
+	RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U),   /*!< PLL2 stabilization interrupt flags clear */
+	RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U),       /*!< CKM interrupt flags clear */
+} rcu_int_flag_clear_enum;
+
+/* clock stabilization interrupt enable or disable */
+typedef enum {
+	RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U),  /*!< IRC40K stabilization interrupt */
+	RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U),   /*!< LXTAL stabilization interrupt */
+	RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U),  /*!< IRC8M stabilization interrupt */
+	RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U),  /*!< HXTAL stabilization interrupt */
+	RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U),    /*!< PLL stabilization interrupt */
+	RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U),   /*!< PLL1 stabilization interrupt */
+	RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U),   /*!< PLL2 stabilization interrupt */
+} rcu_int_enum;
+
+/* oscillator types */
+typedef enum {
+    RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U),         /*!< HXTAL */
+    RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U),        /*!< LXTAL */
+    RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U),          /*!< IRC8M */
+    RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U),      /*!< IRC40K */
+    RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U),        /*!< PLL */
+    RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U),       /*!< PLL1 */
+    RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U),       /*!< PLL2 */
+} rcu_osci_type_enum;
+
+/* rcu clock frequency */
+typedef enum {
+    CK_SYS = 0, /*!< system clock */
+    CK_AHB, /*!< AHB clock */
+    CK_APB1, /*!< APB1 clock */
+    CK_APB2, /*!< APB2 clock */
+} rcu_clock_freq_enum;
+
+/* RCU_CFG0 register bit define */
+/* system clock source select */
+#define CFG0_SCS(regval)                (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_CKSYSSRC_IRC8M              CFG0_SCS(0)                         /*!< system clock source select IRC8M */
+#define RCU_CKSYSSRC_HXTAL              CFG0_SCS(1)                         /*!< system clock source select HXTAL */
+#define RCU_CKSYSSRC_PLL                CFG0_SCS(2)                         /*!< system clock source select PLL */
+
+/* system clock source select status */
+#define CFG0_SCSS(regval)               (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define RCU_SCSS_IRC8M                  CFG0_SCSS(0)                        /*!< system clock source select IRC8M */
+#define RCU_SCSS_HXTAL                  CFG0_SCSS(1)                        /*!< system clock source select HXTAL */
+#define RCU_SCSS_PLL                    CFG0_SCSS(2)                        /*!< system clock source select PLLP */
+
+/* AHB prescaler selection */
+#define CFG0_AHBPSC(regval)             (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define RCU_AHB_CKSYS_DIV1              CFG0_AHBPSC(0)                      /*!< AHB prescaler select CK_SYS */
+#define RCU_AHB_CKSYS_DIV2              CFG0_AHBPSC(8)                      /*!< AHB prescaler select CK_SYS/2 */
+#define RCU_AHB_CKSYS_DIV4              CFG0_AHBPSC(9)                      /*!< AHB prescaler select CK_SYS/4 */
+#define RCU_AHB_CKSYS_DIV8              CFG0_AHBPSC(10)                     /*!< AHB prescaler select CK_SYS/8 */
+#define RCU_AHB_CKSYS_DIV16             CFG0_AHBPSC(11)                     /*!< AHB prescaler select CK_SYS/16 */
+#define RCU_AHB_CKSYS_DIV64             CFG0_AHBPSC(12)                     /*!< AHB prescaler select CK_SYS/64 */
+#define RCU_AHB_CKSYS_DIV128            CFG0_AHBPSC(13)                     /*!< AHB prescaler select CK_SYS/128 */
+#define RCU_AHB_CKSYS_DIV256            CFG0_AHBPSC(14)                     /*!< AHB prescaler select CK_SYS/256 */
+#define RCU_AHB_CKSYS_DIV512            CFG0_AHBPSC(15)                     /*!< AHB prescaler select CK_SYS/512 */
+
+/* APB1 prescaler selection */
+#define CFG0_APB1PSC(regval)            (BITS(8,10) & ((uint32_t)(regval) << 8))
+#define RCU_APB1_CKAHB_DIV1             CFG0_APB1PSC(0)                     /*!< APB1 prescaler select CK_AHB */
+#define RCU_APB1_CKAHB_DIV2             CFG0_APB1PSC(4)                     /*!< APB1 prescaler select CK_AHB/2 */
+#define RCU_APB1_CKAHB_DIV4             CFG0_APB1PSC(5)                     /*!< APB1 prescaler select CK_AHB/4 */
+#define RCU_APB1_CKAHB_DIV8             CFG0_APB1PSC(6)                     /*!< APB1 prescaler select CK_AHB/8 */
+#define RCU_APB1_CKAHB_DIV16            CFG0_APB1PSC(7)                     /*!< APB1 prescaler select CK_AHB/16 */
+
+/* APB2 prescaler selection */
+#define CFG0_APB2PSC(regval)            (BITS(11,13) & ((uint32_t)(regval) << 11))
+#define RCU_APB2_CKAHB_DIV1             CFG0_APB2PSC(0)                     /*!< APB2 prescaler select CK_AHB */
+#define RCU_APB2_CKAHB_DIV2             CFG0_APB2PSC(4)                     /*!< APB2 prescaler select CK_AHB/2 */
+#define RCU_APB2_CKAHB_DIV4             CFG0_APB2PSC(5)                     /*!< APB2 prescaler select CK_AHB/4 */
+#define RCU_APB2_CKAHB_DIV8             CFG0_APB2PSC(6)                     /*!< APB2 prescaler select CK_AHB/8 */
+#define RCU_APB2_CKAHB_DIV16            CFG0_APB2PSC(7)                     /*!< APB2 prescaler select CK_AHB/16 */
+
+/* ADC prescaler select */
+#define RCU_CKADC_CKAPB2_DIV2           ((uint32_t)0x00000000U)             /*!< ADC prescaler select CK_APB2/2 */
+#define RCU_CKADC_CKAPB2_DIV4           ((uint32_t)0x00000001U)             /*!< ADC prescaler select CK_APB2/4 */
+#define RCU_CKADC_CKAPB2_DIV6           ((uint32_t)0x00000002U)             /*!< ADC prescaler select CK_APB2/6 */
+#define RCU_CKADC_CKAPB2_DIV8           ((uint32_t)0x00000003U)             /*!< ADC prescaler select CK_APB2/8 */
+#define RCU_CKADC_CKAPB2_DIV12          ((uint32_t)0x00000005U)             /*!< ADC prescaler select CK_APB2/12 */
+#define RCU_CKADC_CKAPB2_DIV16          ((uint32_t)0x00000007U)             /*!< ADC prescaler select CK_APB2/16 */
+
+/* PLL clock source selection */
+#define RCU_PLLSRC_IRC8M_DIV2           ((uint32_t)0x00000000U)             /*!< IRC8M/2 clock selected as source clock of PLL */
+#define RCU_PLLSRC_HXTAL                RCU_CFG0_PLLSEL                     /*!< HXTAL clock selected as source clock of PLL */
+
+/* PLL clock multiplication factor */
+#define PLLMF_4                         RCU_CFG0_PLLMF_4                    /* bit 4 of PLLMF */
+
+#define CFG0_PLLMF(regval)              (BITS(18,21) & ((uint32_t)(regval) << 18))
+#define RCU_PLL_MUL2                    CFG0_PLLMF(0)                       /*!< PLL source clock multiply by 2 */
+#define RCU_PLL_MUL3                    CFG0_PLLMF(1)                       /*!< PLL source clock multiply by 3 */
+#define RCU_PLL_MUL4                    CFG0_PLLMF(2)                       /*!< PLL source clock multiply by 4 */
+#define RCU_PLL_MUL5                    CFG0_PLLMF(3)                       /*!< PLL source clock multiply by 5 */
+#define RCU_PLL_MUL6                    CFG0_PLLMF(4)                       /*!< PLL source clock multiply by 6 */
+#define RCU_PLL_MUL7                    CFG0_PLLMF(5)                       /*!< PLL source clock multiply by 7 */
+#define RCU_PLL_MUL8                    CFG0_PLLMF(6)                       /*!< PLL source clock multiply by 8 */
+#define RCU_PLL_MUL9                    CFG0_PLLMF(7)                       /*!< PLL source clock multiply by 9 */
+#define RCU_PLL_MUL10                   CFG0_PLLMF(8)                       /*!< PLL source clock multiply by 10 */
+#define RCU_PLL_MUL11                   CFG0_PLLMF(9)                       /*!< PLL source clock multiply by 11 */
+#define RCU_PLL_MUL12                   CFG0_PLLMF(10)                      /*!< PLL source clock multiply by 12 */
+#define RCU_PLL_MUL13                   CFG0_PLLMF(11)                      /*!< PLL source clock multiply by 13 */
+#define RCU_PLL_MUL14                   CFG0_PLLMF(12)                      /*!< PLL source clock multiply by 14 */
+#define RCU_PLL_MUL6_5                  CFG0_PLLMF(13)                      /*!< PLL source clock multiply by 6.5 */
+#define RCU_PLL_MUL16                   CFG0_PLLMF(14)                      /*!< PLL source clock multiply by 16 */
+#define RCU_PLL_MUL17                   (PLLMF_4 | CFG0_PLLMF(0))           /*!< PLL source clock multiply by 17 */
+#define RCU_PLL_MUL18                   (PLLMF_4 | CFG0_PLLMF(1))           /*!< PLL source clock multiply by 18 */
+#define RCU_PLL_MUL19                   (PLLMF_4 | CFG0_PLLMF(2))           /*!< PLL source clock multiply by 19 */
+#define RCU_PLL_MUL20                   (PLLMF_4 | CFG0_PLLMF(3))           /*!< PLL source clock multiply by 20 */
+#define RCU_PLL_MUL21                   (PLLMF_4 | CFG0_PLLMF(4))           /*!< PLL source clock multiply by 21 */
+#define RCU_PLL_MUL22                   (PLLMF_4 | CFG0_PLLMF(5))           /*!< PLL source clock multiply by 22 */
+#define RCU_PLL_MUL23                   (PLLMF_4 | CFG0_PLLMF(6))           /*!< PLL source clock multiply by 23 */
+#define RCU_PLL_MUL24                   (PLLMF_4 | CFG0_PLLMF(7))           /*!< PLL source clock multiply by 24 */
+#define RCU_PLL_MUL25                   (PLLMF_4 | CFG0_PLLMF(8))           /*!< PLL source clock multiply by 25 */
+#define RCU_PLL_MUL26                   (PLLMF_4 | CFG0_PLLMF(9))           /*!< PLL source clock multiply by 26 */
+#define RCU_PLL_MUL27                   (PLLMF_4 | CFG0_PLLMF(10))          /*!< PLL source clock multiply by 27 */
+#define RCU_PLL_MUL28                   (PLLMF_4 | CFG0_PLLMF(11))          /*!< PLL source clock multiply by 28 */
+#define RCU_PLL_MUL29                   (PLLMF_4 | CFG0_PLLMF(12))          /*!< PLL source clock multiply by 29 */
+#define RCU_PLL_MUL30                   (PLLMF_4 | CFG0_PLLMF(13))          /*!< PLL source clock multiply by 30 */
+#define RCU_PLL_MUL31                   (PLLMF_4 | CFG0_PLLMF(14))          /*!< PLL source clock multiply by 31 */
+#define RCU_PLL_MUL32                   (PLLMF_4 | CFG0_PLLMF(15))          /*!< PLL source clock multiply by 32 */
+
+/* USBFS prescaler select */
+#define CFG0_USBPSC(regval)             (BITS(22,23) & ((uint32_t)(regval) << 22))
+#define RCU_CKUSB_CKPLL_DIV1_5          CFG0_USBPSC(0)                      /*!< USBFS prescaler select CK_PLL/1.5 */
+#define RCU_CKUSB_CKPLL_DIV1            CFG0_USBPSC(1)                      /*!< USBFS prescaler select CK_PLL/1 */
+#define RCU_CKUSB_CKPLL_DIV2_5          CFG0_USBPSC(2)                      /*!< USBFS prescaler select CK_PLL/2.5 */
+#define RCU_CKUSB_CKPLL_DIV2            CFG0_USBPSC(3)                      /*!< USBFS prescaler select CK_PLL/2 */
+
+/* CKOUT0 clock source selection */
+#define CFG0_CKOUT0SEL(regval)          (BITS(24,27) & ((uint32_t)(regval) << 24))
+#define RCU_CKOUT0SRC_NONE              CFG0_CKOUT0SEL(0)                   /*!< no clock selected */
+#define RCU_CKOUT0SRC_CKSYS             CFG0_CKOUT0SEL(4)                   /*!< system clock selected */
+#define RCU_CKOUT0SRC_IRC8M             CFG0_CKOUT0SEL(5)                   /*!< internal 8M RC oscillator clock selected */
+#define RCU_CKOUT0SRC_HXTAL             CFG0_CKOUT0SEL(6)                   /*!< high speed crystal oscillator clock (HXTAL) selected */
+#define RCU_CKOUT0SRC_CKPLL_DIV2        CFG0_CKOUT0SEL(7)                   /*!< CK_PLL/2 clock selected */
+#define RCU_CKOUT0SRC_CKPLL1            CFG0_CKOUT0SEL(8)                   /*!< CK_PLL1 clock selected */
+#define RCU_CKOUT0SRC_CKPLL2_DIV2       CFG0_CKOUT0SEL(9)                   /*!< CK_PLL2/2 clock selected */
+#define RCU_CKOUT0SRC_EXT1              CFG0_CKOUT0SEL(10)                  /*!< EXT1 selected */
+#define RCU_CKOUT0SRC_CKPLL2            CFG0_CKOUT0SEL(11)                  /*!< CK_PLL2 clock selected */
+
+/* RTC clock entry selection */
+#define BDCTL_RTCSRC(regval)            (BITS(8,9) & ((uint32_t)(regval) << 8))
+#define RCU_RTCSRC_NONE                 BDCTL_RTCSRC(0)                     /*!< no clock selected */
+#define RCU_RTCSRC_LXTAL                BDCTL_RTCSRC(1)                     /*!< RTC source clock select LXTAL  */
+#define RCU_RTCSRC_IRC40K               BDCTL_RTCSRC(2)                     /*!< RTC source clock select IRC40K */
+#define RCU_RTCSRC_HXTAL_DIV_128        BDCTL_RTCSRC(3)                     /*!< RTC source clock select HXTAL/128 */
+
+/* PREDV0 division factor */
+#define CFG1_PREDV0(regval)             (BITS(0,3) & ((uint32_t)(regval) << 0))
+#define RCU_PREDV0_DIV1                CFG1_PREDV0(0)                       /*!< PREDV0 input source clock not divided */
+#define RCU_PREDV0_DIV2                CFG1_PREDV0(1)                       /*!< PREDV0 input source clock divided by 2 */
+#define RCU_PREDV0_DIV3                CFG1_PREDV0(2)                       /*!< PREDV0 input source clock divided by 3 */
+#define RCU_PREDV0_DIV4                CFG1_PREDV0(3)                       /*!< PREDV0 input source clock divided by 4 */
+#define RCU_PREDV0_DIV5                CFG1_PREDV0(4)                       /*!< PREDV0 input source clock divided by 5 */
+#define RCU_PREDV0_DIV6                CFG1_PREDV0(5)                       /*!< PREDV0 input source clock divided by 6 */
+#define RCU_PREDV0_DIV7                CFG1_PREDV0(6)                       /*!< PREDV0 input source clock divided by 7 */
+#define RCU_PREDV0_DIV8                CFG1_PREDV0(7)                       /*!< PREDV0 input source clock divided by 8 */
+#define RCU_PREDV0_DIV9                CFG1_PREDV0(8)                       /*!< PREDV0 input source clock divided by 9 */
+#define RCU_PREDV0_DIV10               CFG1_PREDV0(9)                       /*!< PREDV0 input source clock divided by 10 */
+#define RCU_PREDV0_DIV11               CFG1_PREDV0(10)                      /*!< PREDV0 input source clock divided by 11 */
+#define RCU_PREDV0_DIV12               CFG1_PREDV0(11)                      /*!< PREDV0 input source clock divided by 12 */
+#define RCU_PREDV0_DIV13               CFG1_PREDV0(12)                      /*!< PREDV0 input source clock divided by 13 */
+#define RCU_PREDV0_DIV14               CFG1_PREDV0(13)                      /*!< PREDV0 input source clock divided by 14 */
+#define RCU_PREDV0_DIV15               CFG1_PREDV0(14)                      /*!< PREDV0 input source clock divided by 15 */
+#define RCU_PREDV0_DIV16               CFG1_PREDV0(15)                      /*!< PREDV0 input source clock divided by 16 */
+
+/* PREDV1 division factor */
+#define CFG1_PREDV1(regval)             (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define RCU_PREDV1_DIV1                CFG1_PREDV1(0)                       /*!< PREDV1 input source clock not divided */
+#define RCU_PREDV1_DIV2                CFG1_PREDV1(1)                       /*!< PREDV1 input source clock divided by 2 */
+#define RCU_PREDV1_DIV3                CFG1_PREDV1(2)                       /*!< PREDV1 input source clock divided by 3 */
+#define RCU_PREDV1_DIV4                CFG1_PREDV1(3)                       /*!< PREDV1 input source clock divided by 4 */
+#define RCU_PREDV1_DIV5                CFG1_PREDV1(4)                       /*!< PREDV1 input source clock divided by 5 */
+#define RCU_PREDV1_DIV6                CFG1_PREDV1(5)                       /*!< PREDV1 input source clock divided by 6 */
+#define RCU_PREDV1_DIV7                CFG1_PREDV1(6)                       /*!< PREDV1 input source clock divided by 7 */
+#define RCU_PREDV1_DIV8                CFG1_PREDV1(7)                       /*!< PREDV1 input source clock divided by 8 */
+#define RCU_PREDV1_DIV9                CFG1_PREDV1(8)                       /*!< PREDV1 input source clock divided by 9 */
+#define RCU_PREDV1_DIV10               CFG1_PREDV1(9)                       /*!< PREDV1 input source clock divided by 10 */
+#define RCU_PREDV1_DIV11               CFG1_PREDV1(10)                      /*!< PREDV1 input source clock divided by 11 */
+#define RCU_PREDV1_DIV12               CFG1_PREDV1(11)                      /*!< PREDV1 input source clock divided by 12 */
+#define RCU_PREDV1_DIV13               CFG1_PREDV1(12)                      /*!< PREDV1 input source clock divided by 13 */
+#define RCU_PREDV1_DIV14               CFG1_PREDV1(13)                      /*!< PREDV1 input source clock divided by 14 */
+#define RCU_PREDV1_DIV15               CFG1_PREDV1(14)                      /*!< PREDV1 input source clock divided by 15 */
+#define RCU_PREDV1_DIV16               CFG1_PREDV1(15)                      /*!< PREDV1 input source clock divided by 16 */
+
+/* PLL1 clock multiplication factor */
+#define CFG1_PLL1MF(regval)             (BITS(8,11) & ((uint32_t)(regval) << 8))
+#define RCU_PLL1_MUL8                   CFG1_PLL1MF(6)                      /*!< PLL1 source clock multiply by 8 */
+#define RCU_PLL1_MUL9                   CFG1_PLL1MF(7)                      /*!< PLL1 source clock multiply by 9 */
+#define RCU_PLL1_MUL10                  CFG1_PLL1MF(8)                      /*!< PLL1 source clock multiply by 10 */
+#define RCU_PLL1_MUL11                  CFG1_PLL1MF(9)                      /*!< PLL1 source clock multiply by 11 */
+#define RCU_PLL1_MUL12                  CFG1_PLL1MF(10)                     /*!< PLL1 source clock multiply by 12 */
+#define RCU_PLL1_MUL13                  CFG1_PLL1MF(11)                     /*!< PLL1 source clock multiply by 13 */
+#define RCU_PLL1_MUL14                  CFG1_PLL1MF(12)                     /*!< PLL1 source clock multiply by 14 */
+#define RCU_PLL1_MUL15                  CFG1_PLL1MF(13)                     /*!< PLL1 source clock multiply by 15 */
+#define RCU_PLL1_MUL16                  CFG1_PLL1MF(14)                     /*!< PLL1 source clock multiply by 16 */
+#define RCU_PLL1_MUL20                  CFG1_PLL1MF(15)                     /*!< PLL1 source clock multiply by 20 */
+
+/* PLL2 clock multiplication factor */
+#define CFG1_PLL2MF(regval)             (BITS(12,15) & ((uint32_t)(regval) << 12))
+#define RCU_PLL2_MUL8                   CFG1_PLL2MF(6)                      /*!< PLL2 source clock multiply by 8 */
+#define RCU_PLL2_MUL9                   CFG1_PLL2MF(7)                      /*!< PLL2 source clock multiply by 9 */
+#define RCU_PLL2_MUL10                  CFG1_PLL2MF(8)                      /*!< PLL2 source clock multiply by 10 */
+#define RCU_PLL2_MUL11                  CFG1_PLL2MF(9)                      /*!< PLL2 source clock multiply by 11 */
+#define RCU_PLL2_MUL12                  CFG1_PLL2MF(10)                     /*!< PLL2 source clock multiply by 12 */
+#define RCU_PLL2_MUL13                  CFG1_PLL2MF(11)                     /*!< PLL2 source clock multiply by 13 */
+#define RCU_PLL2_MUL14                  CFG1_PLL2MF(12)                     /*!< PLL2 source clock multiply by 14 */
+#define RCU_PLL2_MUL15                  CFG1_PLL2MF(13)                     /*!< PLL2 source clock multiply by 15 */
+#define RCU_PLL2_MUL16                  CFG1_PLL2MF(14)                     /*!< PLL2 source clock multiply by 16 */
+#define RCU_PLL2_MUL20                  CFG1_PLL2MF(15)                     /*!< PLL2 source clock multiply by 20 */
+
+
+/* PREDV0 input clock source selection */
+#define RCU_PREDV0SRC_HXTAL             ((uint32_t)0x00000000U)             /*!< HXTAL selected as PREDV0 input source clock */
+#define RCU_PREDV0SRC_CKPLL1            RCU_CFG1_PREDV0SEL                  /*!< CK_PLL1 selected as PREDV0 input source clock */
+
+/* I2S1 clock source selection */
+#define RCU_I2S1SRC_CKSYS               ((uint32_t)0x00000000U)             /*!< system clock selected as I2S1 source clock */
+#define RCU_I2S1SRC_CKPLL2_MUL2         RCU_CFG1_I2S1SEL                    /*!< (CK_PLL2 x 2) selected as I2S1 source clock */
+
+/* I2S2 clock source selection */
+#define RCU_I2S2SRC_CKSYS               ((uint32_t)0x00000000U)             /*!< system clock selected as I2S2 source clock */
+#define RCU_I2S2SRC_CKPLL2_MUL2         RCU_CFG1_I2S2SEL                    /*!< (CK_PLL2 x 2) selected as I2S2 source clock */
+
+
+/* deep-sleep mode voltage */
+#define DSV_DSLPVS(regval)              (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define RCU_DEEPSLEEP_V_1_2             DSV_DSLPVS(0)                       /*!< core voltage is 1.2V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_1_1             DSV_DSLPVS(1)                       /*!< core voltage is 1.1V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_1_0             DSV_DSLPVS(2)                       /*!< core voltage is 1.0V in deep-sleep mode */
+#define RCU_DEEPSLEEP_V_0_9             DSV_DSLPVS(3)                       /*!< core voltage is 0.9V in deep-sleep mode */
+
+/* function declarations */
+/* initialization, peripheral clock enable/disable functions */
+/* deinitialize the RCU */
+void rcu_deinit(void);
+/* enable the peripherals clock */
+void rcu_periph_clock_enable(rcu_periph_enum periph);
+/* disable the peripherals clock */
+void rcu_periph_clock_disable(rcu_periph_enum periph);
+/* enable the peripherals clock when sleep mode */
+void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
+/* disable the peripherals clock when sleep mode */
+void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
+/* reset the peripherals */
+void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
+/* disable reset the peripheral */
+void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
+/* reset the BKP domain */
+void rcu_bkp_reset_enable(void);
+/* disable the BKP domain reset */
+void rcu_bkp_reset_disable(void);
+
+/* clock configuration functions */
+/* configure the system clock source */
+void rcu_system_clock_source_config(uint32_t ck_sys);
+/* get the system clock source */
+uint32_t rcu_system_clock_source_get(void);
+/* configure the AHB prescaler selection */
+void rcu_ahb_clock_config(uint32_t ck_ahb);
+/* configure the APB1 prescaler selection */
+void rcu_apb1_clock_config(uint32_t ck_apb1);
+/* configure the APB2 prescaler selection */
+void rcu_apb2_clock_config(uint32_t ck_apb2);
+/* configure the CK_OUT0 clock source and divider */
+void rcu_ckout0_config(uint32_t ckout0_src);
+/* configure the PLL clock source selection and PLL multiply factor */
+void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
+
+/* configure the PREDV0 division factor and clock source */
+void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div);
+/* configure the PREDV1 division factor */
+void rcu_predv1_config(uint32_t predv1_div);
+/* configure the PLL1 clock */
+void rcu_pll1_config(uint32_t pll_mul);
+/* configure the PLL2 clock */
+void rcu_pll2_config(uint32_t pll_mul);
+
+/* peripheral clock configuration functions */
+/* configure the ADC division factor */
+void rcu_adc_clock_config(uint32_t adc_psc);
+/* configure the USBD/USBFS prescaler factor */
+void rcu_usb_clock_config(uint32_t usb_psc);
+/* configure the RTC clock source selection */
+void rcu_rtc_clock_config(uint32_t rtc_clock_source);
+
+/* configure the I2S1 clock source selection */
+void rcu_i2s1_clock_config(uint32_t i2s_clock_source);
+/* configure the I2S2 clock source selection */
+void rcu_i2s2_clock_config(uint32_t i2s_clock_source);
+
+/* interrupt & flag functions */
+/* get the clock stabilization and periphral reset flags */
+FlagStatus rcu_flag_get(rcu_flag_enum flag);
+/* clear the reset flag */
+void rcu_all_reset_flag_clear(void);
+/* get the clock stabilization interrupt and ckm flags */
+FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
+/* clear the interrupt flags */
+void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
+/* enable the stabilization interrupt */
+void rcu_interrupt_enable(rcu_int_enum stab_int);
+/* disable the stabilization interrupt */
+void rcu_interrupt_disable(rcu_int_enum stab_int);
+
+/* oscillator configuration functions */
+/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */
+ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
+/* turn on the oscillator */
+void rcu_osci_on(rcu_osci_type_enum osci);
+/* turn off the oscillator */
+void rcu_osci_off(rcu_osci_type_enum osci);
+/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
+void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
+/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
+void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
+/* enable the HXTAL clock monitor */
+void rcu_hxtal_clock_monitor_enable(void);
+/* disable the HXTAL clock monitor */
+void rcu_hxtal_clock_monitor_disable(void);
+
+/* set the IRC8M adjust value */
+void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval);
+/* set the deep sleep mode voltage */
+void rcu_deepsleep_voltage_set(uint32_t dsvol);
+
+/* get the system clock, bus and peripheral clock frequency */
+uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
+
+#endif /* GD32VF103_RCU_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h
new file mode 100644
index 0000000000..e17cdaa62d
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h
@@ -0,0 +1,148 @@
+/*!
+    \file  gd32vf103_rtc.h
+    \brief definitions for the RTC
+    
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_RTC_H
+#define GD32VF103_RTC_H
+
+#include "gd32vf103.h"
+
+/* RTC definitions */
+#define RTC                          RTC_BASE
+
+/* registers definitions */
+#define RTC_INTEN                    REG32(RTC + 0x00U)      /*!< interrupt enable register */
+#define RTC_CTL                      REG32(RTC + 0x04U)      /*!< control register */
+#define RTC_PSCH                     REG32(RTC + 0x08U)      /*!< prescaler high register */
+#define RTC_PSCL                     REG32(RTC + 0x0CU)      /*!< prescaler low register */
+#define RTC_DIVH                     REG32(RTC + 0x10U)      /*!< divider high register */
+#define RTC_DIVL                     REG32(RTC + 0x14U)      /*!< divider low register */
+#define RTC_CNTH                     REG32(RTC + 0x18U)      /*!< counter high register */
+#define RTC_CNTL                     REG32(RTC + 0x1CU)      /*!< counter low register */
+#define RTC_ALRMH                    REG32(RTC + 0x20U)      /*!< alarm high register */
+#define RTC_ALRML                    REG32(RTC + 0x24U)      /*!< alarm low register */
+
+/* bits definitions */
+/* RTC_INTEN */
+#define RTC_INTEN_SCIE               BIT(0)                   /*!< second interrupt enable */
+#define RTC_INTEN_ALRMIE             BIT(1)                   /*!< alarm interrupt enable */
+#define RTC_INTEN_OVIE               BIT(2)                   /*!< overflow interrupt enable */
+
+/* RTC_CTL */
+#define RTC_CTL_SCIF                 BIT(0)                   /*!< second interrupt flag */
+#define RTC_CTL_ALRMIF               BIT(1)                   /*!< alarm interrupt flag */
+#define RTC_CTL_OVIF                 BIT(2)                   /*!< overflow interrupt flag */
+#define RTC_CTL_RSYNF                BIT(3)                   /*!< registers synchronized flag */
+#define RTC_CTL_CMF                  BIT(4)                   /*!< configuration mode flag */
+#define RTC_CTL_LWOFF                BIT(5)                   /*!< last write operation finished flag */
+
+/* RTC_PSCH */
+#define RTC_PSCH_PSC                 BITS(0,3)                /*!< prescaler high value */
+
+/* RTC_PSCL */
+#define RTC_PSCL_PSC                 BITS(0,15)               /*!< prescaler low value */
+
+/* RTC_DIVH */
+#define RTC_DIVH_DIV                 BITS(0,3)                /*!< divider high value */
+
+/* RTC_DIVL */
+#define RTC_DIVL_DIV                 BITS(0,15)               /*!< divider low value */
+
+/* RTC_CNTH */
+#define RTC_CNTH_CNT                 BITS(0,15)               /*!< counter high value */
+
+/* RTC_CNTL */
+#define RTC_CNTL_CNT                 BITS(0,15)               /*!< counter low value */
+
+/* RTC_ALRMH */
+#define RTC_ALRMH_ALRM               BITS(0,15)               /*!< alarm high value */
+
+/* RTC_ALRML */
+#define RTC_ALRML_ALRM               BITS(0,15)               /*!< alarm low value */
+
+/* constants definitions */
+/* RTC interrupt enable or disable definitions */
+#define RTC_INT_SECOND               RTC_INTEN_SCIE           /*!< second interrupt enable */
+#define RTC_INT_ALARM                RTC_INTEN_ALRMIE         /*!< alarm interrupt enable */
+#define RTC_INT_OVERFLOW             RTC_INTEN_OVIE           /*!< overflow interrupt enable */
+
+/* RTC interrupt flag definitions */
+#define RTC_INT_FLAG_SECOND          RTC_CTL_SCIF             /*!< second interrupt flag */
+#define RTC_INT_FLAG_ALARM           RTC_CTL_ALRMIF           /*!< alarm interrupt flag */
+#define RTC_INT_FLAG_OVERFLOW        RTC_CTL_OVIF             /*!< overflow interrupt flag */
+
+/* RTC flag definitions */
+#define RTC_FLAG_SECOND              RTC_CTL_SCIF             /*!< second interrupt flag */
+#define RTC_FLAG_ALARM               RTC_CTL_ALRMIF           /*!< alarm interrupt flag */
+#define RTC_FLAG_OVERFLOW            RTC_CTL_OVIF             /*!< overflow interrupt flag */
+#define RTC_FLAG_RSYN                RTC_CTL_RSYNF            /*!< registers synchronized flag */
+#define RTC_FLAG_LWOF                RTC_CTL_LWOFF            /*!< last write operation finished flag */
+
+/* function declarations */
+/* initialization functions */
+/* enter RTC configuration mode */
+void rtc_configuration_mode_enter(void);
+/* exit RTC configuration mode */
+void rtc_configuration_mode_exit(void);
+/* set RTC counter value */
+void rtc_counter_set(uint32_t cnt);
+/* set RTC prescaler value */
+void rtc_prescaler_set(uint32_t psc);
+
+/* operation functions */
+/* wait RTC last write operation finished flag set */
+void rtc_lwoff_wait(void);
+/* wait RTC registers synchronized flag set */
+void rtc_register_sync_wait(void);
+/* set RTC alarm value */
+void rtc_alarm_config(uint32_t alarm);
+/* get RTC counter value */
+uint32_t rtc_counter_get(void);
+/* get RTC divider value */
+uint32_t rtc_divider_get(void);
+
+/* flag & interrupt functions */
+/* get RTC flag status */
+FlagStatus rtc_flag_get(uint32_t flag);
+/* clear RTC flag status */
+void rtc_flag_clear(uint32_t flag);
+/* get RTC interrupt flag status */
+FlagStatus rtc_interrupt_flag_get(uint32_t flag);
+/* clear RTC interrupt flag status */
+void rtc_interrupt_flag_clear(uint32_t flag);
+/* enable RTC interrupt */
+void rtc_interrupt_enable(uint32_t interrupt);
+/* disable RTC interrupt */
+void rtc_interrupt_disable(uint32_t interrupt);
+
+#endif /* GD32VF103_RTC_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h
new file mode 100644
index 0000000000..29c8180883
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h
@@ -0,0 +1,341 @@
+/*!
+    \file  gd32vf103_spi.h
+    \brief definitions for the SPI
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF10X_SPI_H
+#define GD32VF10X_SPI_H
+
+#include "gd32vf103.h"
+
+/* SPIx(x=0,1,2) definitions */
+#define SPI0                            (SPI_BASE + 0x0000F800U)
+#define SPI1                            SPI_BASE
+#define SPI2                            (SPI_BASE + 0x00000400U)
+
+/* SPI registers definitions */
+#define SPI_CTL0(spix)                  REG32((spix) + 0x00U)                   /*!< SPI control register 0 */
+#define SPI_CTL1(spix)                  REG32((spix) + 0x04U)                   /*!< SPI control register 1*/
+#define SPI_STAT(spix)                  REG32((spix) + 0x08U)                   /*!< SPI status register */
+#define SPI_DATA(spix)                  REG32((spix) + 0x0CU)                   /*!< SPI data register */
+#define SPI_CRCPOLY(spix)               REG32((spix) + 0x10U)                   /*!< SPI CRC polynomial register */
+#define SPI_RCRC(spix)                  REG32((spix) + 0x14U)                   /*!< SPI receive CRC register */
+#define SPI_TCRC(spix)                  REG32((spix) + 0x18U)                   /*!< SPI transmit CRC register */
+#define SPI_I2SCTL(spix)                REG32((spix) + 0x1CU)                   /*!< SPI I2S control register */
+#define SPI_I2SPSC(spix)                REG32((spix) + 0x20U)                   /*!< SPI I2S clock prescaler register */
+
+/* bits definitions */
+/* SPI_CTL0 */
+#define SPI_CTL0_CKPH                   BIT(0)                                  /*!< clock phase selection*/
+#define SPI_CTL0_CKPL                   BIT(1)                                  /*!< clock polarity selection */
+#define SPI_CTL0_MSTMOD                 BIT(2)                                  /*!< master mode enable */
+#define SPI_CTL0_PSC                    BITS(3,5)                               /*!< master clock prescaler selection */
+#define SPI_CTL0_SPIEN                  BIT(6)                                  /*!< SPI enable*/
+#define SPI_CTL0_LF                     BIT(7)                                  /*!< LSB first mode */
+#define SPI_CTL0_SWNSS                  BIT(8)                                  /*!< NSS pin selection in NSS software mode */
+#define SPI_CTL0_SWNSSEN                BIT(9)                                  /*!< NSS software mode selection */
+#define SPI_CTL0_RO                     BIT(10)                                 /*!< receive only */
+#define SPI_CTL0_FF16                   BIT(11)                                 /*!< data frame size */
+#define SPI_CTL0_CRCNT                  BIT(12)                                 /*!< CRC next transfer */
+#define SPI_CTL0_CRCEN                  BIT(13)                                 /*!< CRC calculation enable */
+#define SPI_CTL0_BDOEN                  BIT(14)                                 /*!< bidirectional transmit output enable*/
+#define SPI_CTL0_BDEN                   BIT(15)                                 /*!< bidirectional enable */
+
+/* SPI_CTL1 */
+#define SPI_CTL1_DMAREN                 BIT(0)                                  /*!< receive buffer dma enable */
+#define SPI_CTL1_DMATEN                 BIT(1)                                  /*!< transmit buffer dma enable */
+#define SPI_CTL1_NSSDRV                 BIT(2)                                  /*!< drive NSS output */
+#define SPI_CTL1_NSSP                   BIT(3)                                  /*!< SPI NSS pulse mode enable */
+#define SPI_CTL1_TMOD                   BIT(4)                                  /*!< SPI TI mode enable */
+#define SPI_CTL1_ERRIE                  BIT(5)                                  /*!< errors interrupt enable */
+#define SPI_CTL1_RBNEIE                 BIT(6)                                  /*!< receive buffer not empty interrupt enable */
+#define SPI_CTL1_TBEIE                  BIT(7)                                  /*!< transmit buffer empty interrupt enable */
+
+/* SPI_STAT */
+#define SPI_STAT_RBNE                   BIT(0)                                  /*!< receive buffer not empty */
+#define SPI_STAT_TBE                    BIT(1)                                  /*!< transmit buffer empty */
+#define SPI_STAT_I2SCH                  BIT(2)                                  /*!< I2S channel side */
+#define SPI_STAT_TXURERR                BIT(3)                                  /*!< I2S transmission underrun error bit */
+#define SPI_STAT_CRCERR                 BIT(4)                                  /*!< SPI CRC error bit */
+#define SPI_STAT_CONFERR                BIT(5)                                  /*!< SPI configuration error bit */
+#define SPI_STAT_RXORERR                BIT(6)                                  /*!< SPI reception overrun error bit */
+#define SPI_STAT_TRANS                  BIT(7)                                  /*!< transmitting on-going bit */
+#define SPI_STAT_FERR                   BIT(8)                                  /*!< format error bit */
+
+/* SPI_DATA */
+#define SPI_DATA_DATA                   BITS(0,15)                              /*!< data transfer register */
+
+/* SPI_CRCPOLY */
+#define SPI_CRCPOLY_CRCPOLY             BITS(0,15)                              /*!< CRC polynomial value */
+
+/* SPI_RCRC */
+#define SPI_RCRC_RCRC                   BITS(0,15)                              /*!< RX CRC value */
+
+/* SPI_TCRC */
+#define SPI_TCRC_TCRC                   BITS(0,15)                              /*!< TX CRC value */
+
+/* SPI_I2SCTL */
+#define SPI_I2SCTL_CHLEN                BIT(0)                                  /*!< channel length */
+#define SPI_I2SCTL_DTLEN                BITS(1,2)                               /*!< data length */
+#define SPI_I2SCTL_CKPL                 BIT(3)                                  /*!< idle state clock polarity */
+#define SPI_I2SCTL_I2SSTD               BITS(4,5)                               /*!< I2S standard selection */
+#define SPI_I2SCTL_PCMSMOD              BIT(7)                                  /*!< PCM frame synchronization mode */
+#define SPI_I2SCTL_I2SOPMOD             BITS(8,9)                               /*!< I2S operation mode */
+#define SPI_I2SCTL_I2SEN                BIT(10)                                 /*!< I2S enable */
+#define SPI_I2SCTL_I2SSEL               BIT(11)                                 /*!< I2S mode selection */
+
+/* SPI_I2SPSC */
+#define SPI_I2SPSC_DIV                  BITS(0,7)                               /*!< dividing factor for the prescaler */
+#define SPI_I2SPSC_OF                   BIT(8)                                  /*!< odd factor for the prescaler */
+#define SPI_I2SPSC_MCKOEN               BIT(9)                                  /*!< I2S MCK output enable */
+
+/* constants definitions */
+/* SPI and I2S parameter struct definitions */
+typedef struct
+{   
+    uint32_t device_mode;                                                       /*!< SPI master or slave */
+    uint32_t trans_mode;                                                        /*!< SPI transtype */
+    uint32_t frame_size;                                                        /*!< SPI frame size */
+    uint32_t nss;                                                               /*!< SPI NSS control by handware or software */
+    uint32_t endian;                                                            /*!< SPI big endian or little endian */
+    uint32_t clock_polarity_phase;                                              /*!< SPI clock phase and polarity */
+    uint32_t prescale;                                                          /*!< SPI prescale factor */
+}spi_parameter_struct;
+
+/* SPI mode definitions */
+#define SPI_MASTER                      (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)      /*!< SPI as master */
+#define SPI_SLAVE                       ((uint32_t)0x00000000U)                 /*!< SPI as slave */
+
+/* SPI bidirectional transfer direction */
+#define SPI_BIDIRECTIONAL_TRANSMIT      SPI_CTL0_BDOEN                          /*!< SPI work in transmit-only mode */
+#define SPI_BIDIRECTIONAL_RECEIVE       (~SPI_CTL0_BDOEN)                       /*!< SPI work in receive-only mode */
+
+/* SPI transmit type */
+#define SPI_TRANSMODE_FULLDUPLEX        ((uint32_t)0x00000000U)                 /*!< SPI receive and send data at fullduplex communication */
+#define SPI_TRANSMODE_RECEIVEONLY       SPI_CTL0_RO                             /*!< SPI only receive data */
+#define SPI_TRANSMODE_BDRECEIVE         SPI_CTL0_BDEN                           /*!< bidirectional receive data */
+#define SPI_TRANSMODE_BDTRANSMIT        (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)        /*!< bidirectional transmit data*/
+
+/* SPI frame size */
+#define SPI_FRAMESIZE_16BIT             SPI_CTL0_FF16                           /*!< SPI frame size is 16 bits */
+#define SPI_FRAMESIZE_8BIT              ((uint32_t)0x00000000U)                 /*!< SPI frame size is 8 bits */
+
+/* SPI NSS control mode */
+#define SPI_NSS_SOFT                    SPI_CTL0_SWNSSEN                        /*!< SPI NSS control by software */
+#define SPI_NSS_HARD                    ((uint32_t)0x00000000U)                 /*!< SPI NSS control by hardware */
+
+/* SPI transmit way */
+#define SPI_ENDIAN_MSB                  ((uint32_t)0x00000000U)                 /*!< SPI transmit way is big endian: transmit MSB first */
+#define SPI_ENDIAN_LSB                  SPI_CTL0_LF                             /*!< SPI transmit way is little endian: transmit LSB first */
+
+/* SPI clock phase and polarity */
+#define SPI_CK_PL_LOW_PH_1EDGE          ((uint32_t)0x00000000U)                 /*!< SPI clock polarity is low level and phase is first edge */
+#define SPI_CK_PL_HIGH_PH_1EDGE         SPI_CTL0_CKPL                           /*!< SPI clock polarity is high level and phase is first edge */
+#define SPI_CK_PL_LOW_PH_2EDGE          SPI_CTL0_CKPH                           /*!< SPI clock polarity is low level and phase is second edge */
+#define SPI_CK_PL_HIGH_PH_2EDGE         (SPI_CTL0_CKPL | SPI_CTL0_CKPH)         /*!< SPI clock polarity is high level and phase is second edge */
+
+/* SPI clock prescale factor */
+#define CTL0_PSC(regval)                (BITS(3,5) & ((uint32_t)(regval) << 3))
+#define SPI_PSC_2                       CTL0_PSC(0)                             /*!< SPI clock prescale factor is 2 */
+#define SPI_PSC_4                       CTL0_PSC(1)                             /*!< SPI clock prescale factor is 4 */
+#define SPI_PSC_8                       CTL0_PSC(2)                             /*!< SPI clock prescale factor is 8 */
+#define SPI_PSC_16                      CTL0_PSC(3)                             /*!< SPI clock prescale factor is 16 */
+#define SPI_PSC_32                      CTL0_PSC(4)                             /*!< SPI clock prescale factor is 32 */
+#define SPI_PSC_64                      CTL0_PSC(5)                             /*!< SPI clock prescale factor is 64 */
+#define SPI_PSC_128                     CTL0_PSC(6)                             /*!< SPI clock prescale factor is 128 */
+#define SPI_PSC_256                     CTL0_PSC(7)                             /*!< SPI clock prescale factor is 256 */
+
+/* I2S audio sample rate */
+#define I2S_AUDIOSAMPLE_8K              ((uint32_t)8000U)                       /*!< I2S audio sample rate is 8KHz */
+#define I2S_AUDIOSAMPLE_11K             ((uint32_t)11025U)                      /*!< I2S audio sample rate is 11KHz */
+#define I2S_AUDIOSAMPLE_16K             ((uint32_t)16000U)                      /*!< I2S audio sample rate is 16KHz */
+#define I2S_AUDIOSAMPLE_22K             ((uint32_t)22050U)                      /*!< I2S audio sample rate is 22KHz */
+#define I2S_AUDIOSAMPLE_32K             ((uint32_t)32000U)                      /*!< I2S audio sample rate is 32KHz */
+#define I2S_AUDIOSAMPLE_44K             ((uint32_t)44100U)                      /*!< I2S audio sample rate is 44KHz */
+#define I2S_AUDIOSAMPLE_48K             ((uint32_t)48000U)                      /*!< I2S audio sample rate is 48KHz */
+#define I2S_AUDIOSAMPLE_96K             ((uint32_t)96000U)                      /*!< I2S audio sample rate is 96KHz */
+#define I2S_AUDIOSAMPLE_192K            ((uint32_t)192000U)                     /*!< I2S audio sample rate is 192KHz */
+
+/* I2S frame format */
+#define I2SCTL_DTLEN(regval)            (BITS(1,2) & ((uint32_t)(regval) << 1))
+#define I2S_FRAMEFORMAT_DT16B_CH16B     I2SCTL_DTLEN(0)                         /*!< I2S data length is 16 bit and channel length is 16 bit */
+#define I2S_FRAMEFORMAT_DT16B_CH32B     (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 16 bit and channel length is 32 bit */
+#define I2S_FRAMEFORMAT_DT24B_CH32B     (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 24 bit and channel length is 32 bit */
+#define I2S_FRAMEFORMAT_DT32B_CH32B     (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 32 bit and channel length is 32 bit */
+
+/* I2S master clock output */
+#define I2S_MCKOUT_DISABLE              ((uint32_t)0x00000000U)                 /*!< I2S master clock output disable */
+#define I2S_MCKOUT_ENABLE               SPI_I2SPSC_MCKOEN                       /*!< I2S master clock output enable */
+
+/* I2S operation mode */
+#define I2SCTL_I2SOPMOD(regval)         (BITS(8,9) & ((uint32_t)(regval) << 8))
+#define I2S_MODE_SLAVETX                I2SCTL_I2SOPMOD(0)                      /*!< I2S slave transmit mode */
+#define I2S_MODE_SLAVERX                I2SCTL_I2SOPMOD(1)                      /*!< I2S slave receive mode */
+#define I2S_MODE_MASTERTX               I2SCTL_I2SOPMOD(2)                      /*!< I2S master transmit mode */
+#define I2S_MODE_MASTERRX               I2SCTL_I2SOPMOD(3)                      /*!< I2S master receive mode */
+
+/* I2S standard */
+#define I2SCTL_I2SSTD(regval)           (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define I2S_STD_PHILLIPS                I2SCTL_I2SSTD(0)                        /*!< I2S phillips standard */
+#define I2S_STD_MSB                     I2SCTL_I2SSTD(1)                        /*!< I2S MSB standard */
+#define I2S_STD_LSB                     I2SCTL_I2SSTD(2)                        /*!< I2S LSB standard */
+#define I2S_STD_PCMSHORT                I2SCTL_I2SSTD(3)                        /*!< I2S PCM short standard */
+#define I2S_STD_PCMLONG                 (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
+
+/* I2S clock polarity */
+#define I2S_CKPL_LOW                    ((uint32_t)0x00000000U)                 /*!< I2S clock polarity low level */
+#define I2S_CKPL_HIGH                   SPI_I2SCTL_CKPL                         /*!< I2S clock polarity high level */
+
+/* SPI DMA constants definitions */                                    
+#define SPI_DMA_TRANSMIT                ((uint8_t)0x00U)                        /*!< SPI transmit data use DMA */
+#define SPI_DMA_RECEIVE                 ((uint8_t)0x01U)                        /*!< SPI receive data use DMA */
+
+/* SPI CRC constants definitions */
+#define SPI_CRC_TX                      ((uint8_t)0x00U)                        /*!< SPI transmit CRC value */
+#define SPI_CRC_RX                      ((uint8_t)0x01U)                        /*!< SPI receive CRC value */
+
+/* SPI/I2S interrupt enable/disable constants definitions */
+#define SPI_I2S_INT_TBE                 ((uint8_t)0x00U)                        /*!< transmit buffer empty interrupt */
+#define SPI_I2S_INT_RBNE                ((uint8_t)0x01U)                        /*!< receive buffer not empty interrupt */
+#define SPI_I2S_INT_ERR                 ((uint8_t)0x02U)                        /*!< error interrupt */
+
+/* SPI/I2S interrupt flag constants definitions */
+#define SPI_I2S_INT_FLAG_TBE            ((uint8_t)0x00U)                        /*!< transmit buffer empty interrupt flag */
+#define SPI_I2S_INT_FLAG_RBNE           ((uint8_t)0x01U)                        /*!< receive buffer not empty interrupt flag */
+#define SPI_I2S_INT_FLAG_RXORERR        ((uint8_t)0x02U)                        /*!< overrun interrupt flag */
+#define SPI_INT_FLAG_CONFERR            ((uint8_t)0x03U)                        /*!< config error interrupt flag */
+#define SPI_INT_FLAG_CRCERR             ((uint8_t)0x04U)                        /*!< CRC error interrupt flag */
+#define I2S_INT_FLAG_TXURERR            ((uint8_t)0x05U)                        /*!< underrun error interrupt flag */
+#define SPI_I2S_INT_FLAG_FERR           ((uint8_t)0x06U)                        /*!< format error interrupt flag */
+
+/* SPI/I2S flag definitions */                                                  
+#define SPI_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
+#define SPI_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
+#define SPI_FLAG_CRCERR                 SPI_STAT_CRCERR                         /*!< CRC error flag */
+#define SPI_FLAG_CONFERR                SPI_STAT_CONFERR                        /*!< mode config error flag */
+#define SPI_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< receive overrun error flag */
+#define SPI_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
+#define SPI_FLAG_FERR                   SPI_STAT_FERR                           /*!< format error interrupt flag */
+#define I2S_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
+#define I2S_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
+#define I2S_FLAG_CH                     SPI_STAT_I2SCH                          /*!< channel side flag */
+#define I2S_FLAG_TXURERR                SPI_STAT_TXURERR                        /*!< underrun error flag */
+#define I2S_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< overrun error flag */
+#define I2S_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
+#define I2S_FLAG_FERR                   SPI_STAT_FERR                           /*!< format error interrupt flag */
+
+/* function declarations */
+/* SPI/I2S deinitialization and initialization functions */
+/* reset SPI and I2S */
+void spi_i2s_deinit(uint32_t spi_periph);
+/* initialize the parameters of SPI struct with the default values */
+void spi_struct_para_init(spi_parameter_struct* spi_struct);
+/* initialize SPI parameter */
+void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
+/* enable SPI */
+void spi_enable(uint32_t spi_periph);
+/* disable SPI */
+void spi_disable(uint32_t spi_periph);
+
+/* initialize I2S parameter */
+void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
+/* configure I2S prescaler */
+void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
+/* enable I2S */
+void i2s_enable(uint32_t spi_periph);
+/* disable I2S */
+void i2s_disable(uint32_t spi_periph);
+
+/* NSS functions */
+/* enable SPI NSS output */
+void spi_nss_output_enable(uint32_t spi_periph);
+/* disable SPI NSS output */
+void spi_nss_output_disable(uint32_t spi_periph);
+/* SPI NSS pin high level in software mode */
+void spi_nss_internal_high(uint32_t spi_periph);
+/* SPI NSS pin low level in software mode */
+void spi_nss_internal_low(uint32_t spi_periph);
+
+/* DMA communication */
+/* enable SPI DMA */
+void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
+/* disable SPI DMA */
+void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
+
+/* normal mode communication */
+/* configure SPI/I2S data frame format */
+void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
+/* SPI transmit data */
+void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
+/* SPI receive data */
+uint16_t spi_i2s_data_receive(uint32_t spi_periph);
+/* configure SPI bidirectional transfer direction */
+void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
+
+/* SPI CRC functions */
+/* set SPI CRC polynomial */
+void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
+/* get SPI CRC polynomial */
+uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
+/* turn on SPI CRC function */
+void spi_crc_on(uint32_t spi_periph);
+/* turn off SPI CRC function */
+void spi_crc_off(uint32_t spi_periph);
+/* SPI next data is CRC value */
+void spi_crc_next(uint32_t spi_periph);
+/* get SPI CRC send value or receive value */
+uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
+
+/* SPI TI mode functions */
+/* enable SPI TI mode */
+void spi_ti_mode_enable(uint32_t spi_periph);
+/* disable SPI TI mode */
+void spi_ti_mode_disable(uint32_t spi_periph);
+
+/* SPI NSS pulse mode functions */
+/* enable SPI NSS pulse mode */
+void spi_nssp_mode_enable(uint32_t spi_periph);
+/* disable SPI NSS pulse mode */
+void spi_nssp_mode_disable(uint32_t spi_periph);
+/* flag and interrupt functions */
+/* enable SPI and I2S interrupt */
+void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
+/* disable SPI and I2S interrupt */
+void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
+/* get SPI and I2S interrupt status */
+FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
+/* get SPI and I2S flag status */
+FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
+/* clear SPI CRC error flag status */
+void spi_crc_error_clear(uint32_t spi_periph);
+
+#endif /* GD32VF103_SPI_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h
new file mode 100644
index 0000000000..e9b475c37c
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h
@@ -0,0 +1,722 @@
+/*!
+    \file    gd32vf103_timer.h
+    \brief   definitions for the TIMER
+    
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_TIMER_H
+#define GD32VF103_TIMER_H
+
+#include "gd32vf103.h"
+
+/* TIMERx(x=0..13) definitions */
+#define TIMER0                           (TIMER_BASE + 0x00012C00U)
+#define TIMER1                           (TIMER_BASE + 0x00000000U)
+#define TIMER2                           (TIMER_BASE + 0x00000400U)
+#define TIMER3                           (TIMER_BASE + 0x00000800U)
+#define TIMER4                           (TIMER_BASE + 0x00000C00U)
+#define TIMER5                           (TIMER_BASE + 0x00001000U)
+#define TIMER6                           (TIMER_BASE + 0x00001400U)
+
+/* registers definitions */
+#define TIMER_CTL0(timerx)               REG32((timerx) + 0x00U)           /*!< TIMER control register 0 */
+#define TIMER_CTL1(timerx)               REG32((timerx) + 0x04U)           /*!< TIMER control register 1 */
+#define TIMER_SMCFG(timerx)              REG32((timerx) + 0x08U)           /*!< TIMER slave mode configuration register */
+#define TIMER_DMAINTEN(timerx)           REG32((timerx) + 0x0CU)           /*!< TIMER DMA and interrupt enable register */
+#define TIMER_INTF(timerx)               REG32((timerx) + 0x10U)           /*!< TIMER interrupt flag register */
+#define TIMER_SWEVG(timerx)              REG32((timerx) + 0x14U)           /*!< TIMER software event generation register */
+#define TIMER_CHCTL0(timerx)             REG32((timerx) + 0x18U)           /*!< TIMER channel control register 0 */
+#define TIMER_CHCTL1(timerx)             REG32((timerx) + 0x1CU)           /*!< TIMER channel control register 1 */
+#define TIMER_CHCTL2(timerx)             REG32((timerx) + 0x20U)           /*!< TIMER channel control register 2 */
+#define TIMER_CNT(timerx)                REG32((timerx) + 0x24U)           /*!< TIMER counter register */
+#define TIMER_PSC(timerx)                REG32((timerx) + 0x28U)           /*!< TIMER prescaler register */
+#define TIMER_CAR(timerx)                REG32((timerx) + 0x2CU)           /*!< TIMER counter auto reload register */
+#define TIMER_CREP(timerx)               REG32((timerx) + 0x30U)           /*!< TIMER counter repetition register */
+#define TIMER_CH0CV(timerx)              REG32((timerx) + 0x34U)           /*!< TIMER channel 0 capture/compare value register */
+#define TIMER_CH1CV(timerx)              REG32((timerx) + 0x38U)           /*!< TIMER channel 1 capture/compare value register */
+#define TIMER_CH2CV(timerx)              REG32((timerx) + 0x3CU)           /*!< TIMER channel 2 capture/compare value register */
+#define TIMER_CH3CV(timerx)              REG32((timerx) + 0x40U)           /*!< TIMER channel 3 capture/compare value register */
+#define TIMER_CCHP(timerx)               REG32((timerx) + 0x44U)           /*!< TIMER channel complementary protection register */
+#define TIMER_DMACFG(timerx)             REG32((timerx) + 0x48U)           /*!< TIMER DMA configuration register */
+#define TIMER_DMATB(timerx)              REG32((timerx) + 0x4CU)           /*!< TIMER DMA transfer buffer register */
+
+/* bits definitions */
+/* TIMER_CTL0 */
+#define TIMER_CTL0_CEN                   BIT(0)              /*!< TIMER counter enable */
+#define TIMER_CTL0_UPDIS                 BIT(1)              /*!< update disable */
+#define TIMER_CTL0_UPS                   BIT(2)              /*!< update source */
+#define TIMER_CTL0_SPM                   BIT(3)              /*!< single pulse mode */
+#define TIMER_CTL0_DIR                   BIT(4)              /*!< timer counter direction */
+#define TIMER_CTL0_CAM                   BITS(5,6)           /*!< center-aligned mode selection */
+#define TIMER_CTL0_ARSE                  BIT(7)              /*!< auto-reload shadow enable */
+#define TIMER_CTL0_CKDIV                 BITS(8,9)           /*!< clock division */
+
+/* TIMER_CTL1 */
+#define TIMER_CTL1_CCSE                  BIT(0)              /*!< commutation control shadow enable */
+#define TIMER_CTL1_CCUC                  BIT(2)              /*!< commutation control shadow register update control */
+#define TIMER_CTL1_DMAS                  BIT(3)              /*!< DMA request source selection */
+#define TIMER_CTL1_MMC                   BITS(4,6)           /*!< master mode control */
+#define TIMER_CTL1_TI0S                  BIT(7)              /*!< channel 0 trigger input selection(hall mode selection) */
+#define TIMER_CTL1_ISO0                  BIT(8)              /*!< idle state of channel 0 output */
+#define TIMER_CTL1_ISO0N                 BIT(9)              /*!< idle state of channel 0 complementary output */
+#define TIMER_CTL1_ISO1                  BIT(10)             /*!< idle state of channel 1 output */
+#define TIMER_CTL1_ISO1N                 BIT(11)             /*!< idle state of channel 1 complementary output */
+#define TIMER_CTL1_ISO2                  BIT(12)             /*!< idle state of channel 2 output */
+#define TIMER_CTL1_ISO2N                 BIT(13)             /*!< idle state of channel 2 complementary output */
+#define TIMER_CTL1_ISO3                  BIT(14)             /*!< idle state of channel 3 output */
+
+/* TIMER_SMCFG */
+#define TIMER_SMCFG_SMC                  BITS(0,2)           /*!< slave mode control */
+#define TIMER_SMCFG_TRGS                 BITS(4,6)           /*!< trigger selection */
+#define TIMER_SMCFG_MSM                  BIT(7)              /*!< master-slave mode */
+#define TIMER_SMCFG_ETFC                 BITS(8,11)          /*!< external trigger filter control */
+#define TIMER_SMCFG_ETPSC                BITS(12,13)         /*!< external trigger prescaler */
+#define TIMER_SMCFG_SMC1                 BIT(14)             /*!< part of SMC for enable external clock mode 1 */
+#define TIMER_SMCFG_ETP                  BIT(15)             /*!< external trigger polarity */
+
+/* TIMER_DMAINTEN */
+#define TIMER_DMAINTEN_UPIE              BIT(0)              /*!< update interrupt enable */
+#define TIMER_DMAINTEN_CH0IE             BIT(1)              /*!< channel 0 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH1IE             BIT(2)              /*!< channel 1 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH2IE             BIT(3)              /*!< channel 2 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH3IE             BIT(4)              /*!< channel 3 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CMTIE             BIT(5)              /*!< commutation interrupt request enable */
+#define TIMER_DMAINTEN_TRGIE             BIT(6)              /*!< trigger interrupt enable */
+#define TIMER_DMAINTEN_BRKIE             BIT(7)              /*!< break interrupt enable */
+#define TIMER_DMAINTEN_UPDEN             BIT(8)              /*!< update DMA request enable */
+#define TIMER_DMAINTEN_CH0DEN            BIT(9)              /*!< channel 0 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH1DEN            BIT(10)             /*!< channel 1 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH2DEN            BIT(11)             /*!< channel 2 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH3DEN            BIT(12)             /*!< channel 3 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CMTDEN            BIT(13)             /*!< commutation DMA request enable */
+#define TIMER_DMAINTEN_TRGDEN            BIT(14)             /*!< trigger DMA request enable */
+
+/* TIMER_INTF */
+#define TIMER_INTF_UPIF                  BIT(0)              /*!< update interrupt flag */
+#define TIMER_INTF_CH0IF                 BIT(1)              /*!< channel 0 capture/compare interrupt flag */
+#define TIMER_INTF_CH1IF                 BIT(2)              /*!< channel 1 capture/compare interrupt flag */
+#define TIMER_INTF_CH2IF                 BIT(3)              /*!< channel 2 capture/compare interrupt flag */
+#define TIMER_INTF_CH3IF                 BIT(4)              /*!< channel 3 capture/compare interrupt flag */
+#define TIMER_INTF_CMTIF                 BIT(5)              /*!< channel commutation interrupt flag */
+#define TIMER_INTF_TRGIF                 BIT(6)              /*!< trigger interrupt flag */
+#define TIMER_INTF_BRKIF                 BIT(7)              /*!< break interrupt flag */
+#define TIMER_INTF_CH0OF                 BIT(9)              /*!< channel 0 over capture flag */
+#define TIMER_INTF_CH1OF                 BIT(10)             /*!< channel 1 over capture flag */
+#define TIMER_INTF_CH2OF                 BIT(11)             /*!< channel 2 over capture flag */
+#define TIMER_INTF_CH3OF                 BIT(12)             /*!< channel 3 over capture flag */
+
+/* TIMER_SWEVG */
+#define TIMER_SWEVG_UPG                  BIT(0)              /*!< update event generate */
+#define TIMER_SWEVG_CH0G                 BIT(1)              /*!< channel 0 capture or compare event generation */
+#define TIMER_SWEVG_CH1G                 BIT(2)              /*!< channel 1 capture or compare event generation */
+#define TIMER_SWEVG_CH2G                 BIT(3)              /*!< channel 2 capture or compare event generation */
+#define TIMER_SWEVG_CH3G                 BIT(4)              /*!< channel 3 capture or compare event generation */
+#define TIMER_SWEVG_CMTG                 BIT(5)              /*!< channel commutation event generation */
+#define TIMER_SWEVG_TRGG                 BIT(6)              /*!< trigger event generation */
+#define TIMER_SWEVG_BRKG                 BIT(7)              /*!< break event generation */
+
+/* TIMER_CHCTL0 */
+/* output compare mode */
+#define TIMER_CHCTL0_CH0MS               BITS(0,1)           /*!< channel 0 mode selection */
+#define TIMER_CHCTL0_CH0COMFEN           BIT(2)              /*!< channel 0 output compare fast enable */
+#define TIMER_CHCTL0_CH0COMSEN           BIT(3)              /*!< channel 0 output compare shadow enable */
+#define TIMER_CHCTL0_CH0COMCTL           BITS(4,6)           /*!< channel 0 output compare control  */
+#define TIMER_CHCTL0_CH0COMCEN           BIT(7)              /*!< channel 0 output compare clear enable */
+#define TIMER_CHCTL0_CH1MS               BITS(8,9)           /*!< channel 1 mode selection */
+#define TIMER_CHCTL0_CH1COMFEN           BIT(10)             /*!< channel 1 output compare fast enable */
+#define TIMER_CHCTL0_CH1COMSEN           BIT(11)             /*!< channel 1 output compare shadow enable */
+#define TIMER_CHCTL0_CH1COMCTL           BITS(12,14)         /*!< channel 1 output compare control  */
+#define TIMER_CHCTL0_CH1COMCEN           BIT(15)             /*!< channel 1 output compare clear enable */
+/* input capture mode */
+#define TIMER_CHCTL0_CH0CAPPSC           BITS(2,3)           /*!< channel 0 input capture prescaler */
+#define TIMER_CHCTL0_CH0CAPFLT           BITS(4,7)           /*!< channel 0 input capture filter control */
+#define TIMER_CHCTL0_CH1CAPPSC           BITS(10,11)         /*!< channel 1 input capture prescaler */
+#define TIMER_CHCTL0_CH1CAPFLT           BITS(12,15)         /*!< channel 1 input capture filter control */
+
+/* TIMER_CHCTL1 */
+/* output compare mode */
+#define TIMER_CHCTL1_CH2MS               BITS(0,1)           /*!< channel 2 mode selection */
+#define TIMER_CHCTL1_CH2COMFEN           BIT(2)              /*!< channel 2 output compare fast enable */
+#define TIMER_CHCTL1_CH2COMSEN           BIT(3)              /*!< channel 2 output compare shadow enable */
+#define TIMER_CHCTL1_CH2COMCTL           BITS(4,6)           /*!< channel 2 output compare control */
+#define TIMER_CHCTL1_CH2COMCEN           BIT(7)              /*!< channel 2 output compare clear enable */
+#define TIMER_CHCTL1_CH3MS               BITS(8,9)           /*!< channel 3 mode selection */
+#define TIMER_CHCTL1_CH3COMFEN           BIT(10)             /*!< channel 3 output compare fast enable */
+#define TIMER_CHCTL1_CH3COMSEN           BIT(11)             /*!< channel 3 output compare shadow enable */
+#define TIMER_CHCTL1_CH3COMCTL           BITS(12,14)         /*!< channel 3 output compare control */
+#define TIMER_CHCTL1_CH3COMCEN           BIT(15)             /*!< channel 3 output compare clear enable */
+/* input capture mode */
+#define TIMER_CHCTL1_CH2CAPPSC           BITS(2,3)           /*!< channel 2 input capture prescaler */
+#define TIMER_CHCTL1_CH2CAPFLT           BITS(4,7)           /*!< channel 2 input capture filter control */
+#define TIMER_CHCTL1_CH3CAPPSC           BITS(10,11)         /*!< channel 3 input capture prescaler */
+#define TIMER_CHCTL1_CH3CAPFLT           BITS(12,15)         /*!< channel 3 input capture filter control */
+
+/* TIMER_CHCTL2 */
+#define TIMER_CHCTL2_CH0EN               BIT(0)              /*!< channel 0 capture/compare function enable */
+#define TIMER_CHCTL2_CH0P                BIT(1)              /*!< channel 0 capture/compare function polarity */
+#define TIMER_CHCTL2_CH0NEN              BIT(2)              /*!< channel 0 complementary output enable */
+#define TIMER_CHCTL2_CH0NP               BIT(3)              /*!< channel 0 complementary output polarity */
+#define TIMER_CHCTL2_CH1EN               BIT(4)              /*!< channel 1 capture/compare function enable  */
+#define TIMER_CHCTL2_CH1P                BIT(5)              /*!< channel 1 capture/compare function polarity */
+#define TIMER_CHCTL2_CH1NEN              BIT(6)              /*!< channel 1 complementary output enable */
+#define TIMER_CHCTL2_CH1NP               BIT(7)              /*!< channel 1 complementary output polarity */
+#define TIMER_CHCTL2_CH2EN               BIT(8)              /*!< channel 2 capture/compare function enable  */
+#define TIMER_CHCTL2_CH2P                BIT(9)              /*!< channel 2 capture/compare function polarity */
+#define TIMER_CHCTL2_CH2NEN              BIT(10)             /*!< channel 2 complementary output enable */
+#define TIMER_CHCTL2_CH2NP               BIT(11)             /*!< channel 2 complementary output polarity */
+#define TIMER_CHCTL2_CH3EN               BIT(12)             /*!< channel 3 capture/compare function enable  */
+#define TIMER_CHCTL2_CH3P                BIT(13)             /*!< channel 3 capture/compare function polarity */
+
+/* TIMER_CNT */
+#define TIMER_CNT_CNT                    BITS(0,15)          /*!< 16 bit timer counter */
+
+/* TIMER_PSC */
+#define TIMER_PSC_PSC                    BITS(0,15)          /*!< prescaler value of the counter clock */
+
+/* TIMER_CAR */
+#define TIMER_CAR_CARL                   BITS(0,15)          /*!< 16 bit counter auto reload value */
+
+/* TIMER_CREP */
+#define TIMER_CREP_CREP                  BITS(0,7)           /*!< counter repetition value */
+
+/* TIMER_CH0CV */
+#define TIMER_CH0CV_CH0VAL               BITS(0,15)          /*!< 16 bit capture/compare value of channel 0 */
+
+/* TIMER_CH1CV */
+#define TIMER_CH1CV_CH1VAL               BITS(0,15)          /*!< 16 bit capture/compare value of channel 1 */
+
+/* TIMER_CH2CV */
+#define TIMER_CH2CV_CH2VAL               BITS(0,15)          /*!< 16 bit capture/compare value of channel 2 */
+
+/* TIMER_CH3CV */
+#define TIMER_CH3CV_CH3VAL               BITS(0,15)          /*!< 16 bit capture/compare value of channel 3 */
+
+/* TIMER_CCHP */
+#define TIMER_CCHP_DTCFG                 BITS(0,7)           /*!< dead time configure */
+#define TIMER_CCHP_PROT                  BITS(8,9)           /*!< complementary register protect control */
+#define TIMER_CCHP_IOS                   BIT(10)             /*!< idle mode off-state configure */
+#define TIMER_CCHP_ROS                   BIT(11)             /*!< run mode off-state configure */
+#define TIMER_CCHP_BRKEN                 BIT(12)             /*!< break enable */
+#define TIMER_CCHP_BRKP                  BIT(13)             /*!< break polarity */
+#define TIMER_CCHP_OAEN                  BIT(14)             /*!< output automatic enable */
+#define TIMER_CCHP_POEN                  BIT(15)             /*!< primary output enable */
+
+/* TIMER_DMACFG */
+#define TIMER_DMACFG_DMATA               BITS(0,4)           /*!< DMA transfer access start address */
+#define TIMER_DMACFG_DMATC               BITS(8,12)          /*!< DMA transfer count */
+
+/* TIMER_DMATB */
+#define TIMER_DMATB_DMATB                BITS(0,15)          /*!< DMA transfer buffer address */
+
+/* constants definitions */
+/* TIMER init parameter struct definitions */
+typedef struct
+{ 
+    uint16_t prescaler;                                      /*!< prescaler value */
+    uint16_t alignedmode;                                    /*!< aligned mode */
+    uint16_t counterdirection;                               /*!< counter direction */
+    uint32_t period;                                         /*!< period value */
+    uint16_t clockdivision;                                  /*!< clock division value */
+    uint8_t  repetitioncounter;                              /*!< the counter repetition value */
+}timer_parameter_struct;
+
+/* break parameter struct definitions */
+typedef struct
+{ 
+    uint16_t runoffstate;                                    /*!< run mode off-state */
+    uint16_t ideloffstate;                                   /*!< idle mode off-state */
+    uint16_t deadtime;                                       /*!< dead time */
+    uint16_t breakpolarity;                                  /*!< break polarity */
+    uint16_t outputautostate;                                /*!< output automatic enable */
+    uint16_t protectmode;                                    /*!< complementary register protect control */
+    uint16_t breakstate;                                     /*!< break enable */
+}timer_break_parameter_struct;
+
+/* channel output parameter struct definitions */
+typedef struct
+{ 
+    uint16_t outputstate;                                    /*!< channel output state */
+    uint16_t outputnstate;                                   /*!< channel complementary output state */
+    uint16_t ocpolarity;                                     /*!< channel output polarity */
+    uint16_t ocnpolarity;                                    /*!< channel complementary output polarity */
+    uint16_t ocidlestate;                                    /*!< idle state of channel output */
+    uint16_t ocnidlestate;                                   /*!< idle state of channel complementary output */
+}timer_oc_parameter_struct;
+
+/* channel input parameter struct definitions */
+typedef struct
+{ 
+    uint16_t icpolarity;                                     /*!< channel input polarity */
+    uint16_t icselection;                                    /*!< channel input mode selection */
+    uint16_t icprescaler;                                    /*!< channel input capture prescaler */
+    uint16_t icfilter;                                       /*!< channel input capture filter control */
+}timer_ic_parameter_struct;
+
+/* TIMER interrupt enable or disable */
+#define TIMER_INT_UP                        TIMER_DMAINTEN_UPIE                     /*!< update interrupt */
+#define TIMER_INT_CH0                       TIMER_DMAINTEN_CH0IE                    /*!< channel 0 interrupt */
+#define TIMER_INT_CH1                       TIMER_DMAINTEN_CH1IE                    /*!< channel 1 interrupt */
+#define TIMER_INT_CH2                       TIMER_DMAINTEN_CH2IE                    /*!< channel 2 interrupt */
+#define TIMER_INT_CH3                       TIMER_DMAINTEN_CH3IE                    /*!< channel 3 interrupt */
+#define TIMER_INT_CMT                       TIMER_DMAINTEN_CMTIE                    /*!< channel commutation interrupt flag */
+#define TIMER_INT_TRG                       TIMER_DMAINTEN_TRGIE                    /*!< trigger interrupt */
+#define TIMER_INT_BRK                       TIMER_DMAINTEN_BRKIE                    /*!< break interrupt */
+
+/* TIMER interrupt flag */
+#define TIMER_INT_FLAG_UP                   TIMER_INT_UP                            /*!< update interrupt */
+#define TIMER_INT_FLAG_CH0                  TIMER_INT_CH0                           /*!< channel 0 interrupt */
+#define TIMER_INT_FLAG_CH1                  TIMER_INT_CH1                           /*!< channel 1 interrupt */
+#define TIMER_INT_FLAG_CH2                  TIMER_INT_CH2                           /*!< channel 2 interrupt */
+#define TIMER_INT_FLAG_CH3                  TIMER_INT_CH3                           /*!< channel 3 interrupt */
+#define TIMER_INT_FLAG_CMT                  TIMER_INT_CMT                           /*!< channel commutation interrupt flag */
+#define TIMER_INT_FLAG_TRG                  TIMER_INT_TRG                           /*!< trigger interrupt */
+#define TIMER_INT_FLAG_BRK                  TIMER_INT_BRK  
+
+/* TIMER flag */
+#define TIMER_FLAG_UP                       TIMER_INTF_UPIF                         /*!< update flag */
+#define TIMER_FLAG_CH0                      TIMER_INTF_CH0IF                        /*!< channel 0 flag */
+#define TIMER_FLAG_CH1                      TIMER_INTF_CH1IF                        /*!< channel 1 flag */
+#define TIMER_FLAG_CH2                      TIMER_INTF_CH2IF                        /*!< channel 2 flag */
+#define TIMER_FLAG_CH3                      TIMER_INTF_CH3IF                        /*!< channel 3 flag */
+#define TIMER_FLAG_CMT                      TIMER_INTF_CMTIF                        /*!< channel control update flag */
+#define TIMER_FLAG_TRG                      TIMER_INTF_TRGIF                        /*!< trigger flag */
+#define TIMER_FLAG_BRK                      TIMER_INTF_BRKIF                        /*!< break flag */
+#define TIMER_FLAG_CH0O                     TIMER_INTF_CH0OF                        /*!< channel 0 overcapture flag */
+#define TIMER_FLAG_CH1O                     TIMER_INTF_CH1OF                        /*!< channel 1 overcapture flag */
+#define TIMER_FLAG_CH2O                     TIMER_INTF_CH2OF                        /*!< channel 2 overcapture flag */
+#define TIMER_FLAG_CH3O                     TIMER_INTF_CH3OF                        /*!< channel 3 overcapture flag */
+
+/* TIMER DMA source enable */
+#define TIMER_DMA_UPD                       ((uint16_t)TIMER_DMAINTEN_UPDEN)        /*!< update DMA enable */
+#define TIMER_DMA_CH0D                      ((uint16_t)TIMER_DMAINTEN_CH0DEN)       /*!< channel 0 DMA enable */
+#define TIMER_DMA_CH1D                      ((uint16_t)TIMER_DMAINTEN_CH1DEN)       /*!< channel 1 DMA enable */
+#define TIMER_DMA_CH2D                      ((uint16_t)TIMER_DMAINTEN_CH2DEN)       /*!< channel 2 DMA enable */
+#define TIMER_DMA_CH3D                      ((uint16_t)TIMER_DMAINTEN_CH3DEN)       /*!< channel 3 DMA enable */
+#define TIMER_DMA_CMTD                      ((uint16_t)TIMER_DMAINTEN_CMTDEN)       /*!< commutation DMA request enable */
+#define TIMER_DMA_TRGD                      ((uint16_t)TIMER_DMAINTEN_TRGDEN)       /*!< trigger DMA enable */
+
+/* channel DMA request source selection */ 
+#define TIMER_DMAREQUEST_UPDATEEVENT        TIMER_CTL1_DMAS                         /*!< DMA request of channel n is sent when update event occurs */
+#define TIMER_DMAREQUEST_CHANNELEVENT       ((uint32_t)0x00000000U)                 /*!< DMA request of channel n is sent when channel n event occurs */
+
+/* DMA access base address */
+#define DMACFG_DMATA(regval)                (BITS(0, 4) & ((uint32_t)(regval) << 0U))
+#define TIMER_DMACFG_DMATA_CTL0             DMACFG_DMATA(0)                         /*!< DMA transfer address is TIMER_CTL0 */
+#define TIMER_DMACFG_DMATA_CTL1             DMACFG_DMATA(1)                         /*!< DMA transfer address is TIMER_CTL1 */
+#define TIMER_DMACFG_DMATA_SMCFG            DMACFG_DMATA(2)                         /*!< DMA transfer address is TIMER_SMCFG */
+#define TIMER_DMACFG_DMATA_DMAINTEN         DMACFG_DMATA(3)                         /*!< DMA transfer address is TIMER_DMAINTEN */
+#define TIMER_DMACFG_DMATA_INTF             DMACFG_DMATA(4)                         /*!< DMA transfer address is TIMER_INTF */
+#define TIMER_DMACFG_DMATA_SWEVG            DMACFG_DMATA(5)                         /*!< DMA transfer address is TIMER_SWEVG */
+#define TIMER_DMACFG_DMATA_CHCTL0           DMACFG_DMATA(6)                         /*!< DMA transfer address is TIMER_CHCTL0 */
+#define TIMER_DMACFG_DMATA_CHCTL1           DMACFG_DMATA(7)                         /*!< DMA transfer address is TIMER_CHCTL1 */
+#define TIMER_DMACFG_DMATA_CHCTL2           DMACFG_DMATA(8)                         /*!< DMA transfer address is TIMER_CHCTL2 */
+#define TIMER_DMACFG_DMATA_CNT              DMACFG_DMATA(9)                         /*!< DMA transfer address is TIMER_CNT */
+#define TIMER_DMACFG_DMATA_PSC              DMACFG_DMATA(10)                        /*!< DMA transfer address is TIMER_PSC */
+#define TIMER_DMACFG_DMATA_CAR              DMACFG_DMATA(11)                        /*!< DMA transfer address is TIMER_CAR */
+#define TIMER_DMACFG_DMATA_CREP             DMACFG_DMATA(12)                        /*!< DMA transfer address is TIMER_CREP */
+#define TIMER_DMACFG_DMATA_CH0CV            DMACFG_DMATA(13)                        /*!< DMA transfer address is TIMER_CH0CV */
+#define TIMER_DMACFG_DMATA_CH1CV            DMACFG_DMATA(14)                        /*!< DMA transfer address is TIMER_CH1CV */
+#define TIMER_DMACFG_DMATA_CH2CV            DMACFG_DMATA(15)                        /*!< DMA transfer address is TIMER_CH2CV */
+#define TIMER_DMACFG_DMATA_CH3CV            DMACFG_DMATA(16)                        /*!< DMA transfer address is TIMER_CH3CV */
+#define TIMER_DMACFG_DMATA_CCHP             DMACFG_DMATA(17)                        /*!< DMA transfer address is TIMER_CCHP */
+#define TIMER_DMACFG_DMATA_DMACFG           DMACFG_DMATA(18)                        /*!< DMA transfer address is TIMER_DMACFG */
+
+/* DMA access burst length */
+#define DMACFG_DMATC(regval)                (BITS(8, 12) & ((uint32_t)(regval) << 8U))
+#define TIMER_DMACFG_DMATC_1TRANSFER        DMACFG_DMATC(0)                         /*!< DMA transfer 1 time */
+#define TIMER_DMACFG_DMATC_2TRANSFER        DMACFG_DMATC(1)                         /*!< DMA transfer 2 times */
+#define TIMER_DMACFG_DMATC_3TRANSFER        DMACFG_DMATC(2)                         /*!< DMA transfer 3 times */
+#define TIMER_DMACFG_DMATC_4TRANSFER        DMACFG_DMATC(3)                         /*!< DMA transfer 4 times */
+#define TIMER_DMACFG_DMATC_5TRANSFER        DMACFG_DMATC(4)                         /*!< DMA transfer 5 times */
+#define TIMER_DMACFG_DMATC_6TRANSFER        DMACFG_DMATC(5)                         /*!< DMA transfer 6 times */
+#define TIMER_DMACFG_DMATC_7TRANSFER        DMACFG_DMATC(6)                         /*!< DMA transfer 7 times */
+#define TIMER_DMACFG_DMATC_8TRANSFER        DMACFG_DMATC(7)                         /*!< DMA transfer 8 times */
+#define TIMER_DMACFG_DMATC_9TRANSFER        DMACFG_DMATC(8)                         /*!< DMA transfer 9 times */
+#define TIMER_DMACFG_DMATC_10TRANSFER       DMACFG_DMATC(9)                         /*!< DMA transfer 10 times */
+#define TIMER_DMACFG_DMATC_11TRANSFER       DMACFG_DMATC(10)                        /*!< DMA transfer 11 times */
+#define TIMER_DMACFG_DMATC_12TRANSFER       DMACFG_DMATC(11)                        /*!< DMA transfer 12 times */
+#define TIMER_DMACFG_DMATC_13TRANSFER       DMACFG_DMATC(12)                        /*!< DMA transfer 13 times */
+#define TIMER_DMACFG_DMATC_14TRANSFER       DMACFG_DMATC(13)                        /*!< DMA transfer 14 times */
+#define TIMER_DMACFG_DMATC_15TRANSFER       DMACFG_DMATC(14)                        /*!< DMA transfer 15 times */
+#define TIMER_DMACFG_DMATC_16TRANSFER       DMACFG_DMATC(15)                        /*!< DMA transfer 16 times */
+#define TIMER_DMACFG_DMATC_17TRANSFER       DMACFG_DMATC(16)                        /*!< DMA transfer 17 times */
+#define TIMER_DMACFG_DMATC_18TRANSFER       DMACFG_DMATC(17)                        /*!< DMA transfer 18 times */
+
+/* TIMER software event generation source */
+#define TIMER_EVENT_SRC_UPG                 ((uint16_t)0x0001U)                     /*!< update event generation */
+#define TIMER_EVENT_SRC_CH0G                ((uint16_t)0x0002U)                     /*!< channel 0 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH1G                ((uint16_t)0x0004U)                     /*!< channel 1 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH2G                ((uint16_t)0x0008U)                     /*!< channel 2 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH3G                ((uint16_t)0x0010U)                     /*!< channel 3 capture or compare event generation */
+#define TIMER_EVENT_SRC_CMTG                ((uint16_t)0x0020U)                     /*!< channel commutation event generation */
+#define TIMER_EVENT_SRC_TRGG                ((uint16_t)0x0040U)                     /*!< trigger event generation */
+#define TIMER_EVENT_SRC_BRKG                ((uint16_t)0x0080U)                     /*!< break event generation */
+
+/* center-aligned mode selection */
+#define CTL0_CAM(regval)                    ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
+#define TIMER_COUNTER_EDGE                  CTL0_CAM(0)                             /*!< edge-aligned mode */
+#define TIMER_COUNTER_CENTER_DOWN           CTL0_CAM(1)                             /*!< center-aligned and counting down assert mode */
+#define TIMER_COUNTER_CENTER_UP             CTL0_CAM(2)                             /*!< center-aligned and counting up assert mode */
+#define TIMER_COUNTER_CENTER_BOTH           CTL0_CAM(3)                             /*!< center-aligned and counting up/down assert mode */
+
+/* TIMER prescaler reload mode */
+#define TIMER_PSC_RELOAD_NOW                TIMER_SWEVG_UPG                         /*!< the prescaler is loaded right now */
+#define TIMER_PSC_RELOAD_UPDATE             ((uint32_t)0x00000000U)                 /*!< the prescaler is loaded at the next update event */
+
+/* count direction */
+#define TIMER_COUNTER_UP                    ((uint16_t)0x0000U)                     /*!< counter up direction */
+#define TIMER_COUNTER_DOWN                  ((uint16_t)TIMER_CTL0_DIR)              /*!< counter down direction */
+
+/* specify division ratio between TIMER clock and dead-time and sampling clock */
+#define CTL0_CKDIV(regval)                  ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
+#define TIMER_CKDIV_DIV1                    CTL0_CKDIV(0)                           /*!< clock division value is 1,fDTS=fTIMER_CK */
+#define TIMER_CKDIV_DIV2                    CTL0_CKDIV(1)                           /*!< clock division value is 2,fDTS= fTIMER_CK/2 */
+#define TIMER_CKDIV_DIV4                    CTL0_CKDIV(2)                           /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
+
+/* single pulse mode */
+#define TIMER_SP_MODE_SINGLE                TIMER_CTL0_SPM                          /*!< single pulse mode */
+#define TIMER_SP_MODE_REPETITIVE            ((uint32_t)0x00000000U)                 /*!< repetitive pulse mode */
+
+/* update source */
+#define TIMER_UPDATE_SRC_REGULAR            TIMER_CTL0_UPS                          /*!< update generate only by counter overflow/underflow */
+#define TIMER_UPDATE_SRC_GLOBAL             ((uint32_t)0x00000000U)                 /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
+
+/* run mode off-state configure */
+#define TIMER_ROS_STATE_ENABLE              ((uint16_t)TIMER_CCHP_ROS)              /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_ROS_STATE_DISABLE             ((uint16_t)0x0000U)                     /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */
+
+
+/* idle mode off-state configure */                                                 
+#define TIMER_IOS_STATE_ENABLE              ((uint16_t)TIMER_CCHP_IOS)              /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_IOS_STATE_DISABLE             ((uint16_t)0x0000U)                     /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */
+
+/* break input polarity */
+#define TIMER_BREAK_POLARITY_LOW            ((uint16_t)0x0000U)                     /*!< break input polarity is low */
+#define TIMER_BREAK_POLARITY_HIGH           ((uint16_t)TIMER_CCHP_BRKP)             /*!< break input polarity is high */
+
+/* output automatic enable */
+#define TIMER_OUTAUTO_ENABLE                ((uint16_t)TIMER_CCHP_OAEN)             /*!< output automatic enable */
+#define TIMER_OUTAUTO_DISABLE               ((uint16_t)0x0000U)                     /*!< output automatic disable */
+
+/* complementary register protect control */
+#define CCHP_PROT(regval)                   ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
+#define TIMER_CCHP_PROT_OFF                 CCHP_PROT(0)                            /*!< protect disable */
+#define TIMER_CCHP_PROT_0                   CCHP_PROT(1)                            /*!< PROT mode 0 */
+#define TIMER_CCHP_PROT_1                   CCHP_PROT(2)                            /*!< PROT mode 1 */
+#define TIMER_CCHP_PROT_2                   CCHP_PROT(3)                            /*!< PROT mode 2 */
+
+/* break input enable */
+#define TIMER_BREAK_ENABLE                  ((uint16_t)TIMER_CCHP_BRKEN)            /*!< break input enable */
+#define TIMER_BREAK_DISABLE                 ((uint16_t)0x0000U)                     /*!< break input disable */
+
+/* TIMER channel n(n=0,1,2,3) */
+#define TIMER_CH_0                          ((uint16_t)0x0000U)                     /*!< TIMER channel 0(TIMERx(x=0..4)) */
+#define TIMER_CH_1                          ((uint16_t)0x0001U)                     /*!< TIMER channel 1(TIMERx(x=0..4)) */
+#define TIMER_CH_2                          ((uint16_t)0x0002U)                     /*!< TIMER channel 2(TIMERx(x=0..4)) */
+#define TIMER_CH_3                          ((uint16_t)0x0003U)                     /*!< TIMER channel 3(TIMERx(x=0..4)) */
+
+/* channel enable state */
+#define TIMER_CCX_ENABLE                    ((uint16_t)0x0001U)                     /*!< channel enable */
+#define TIMER_CCX_DISABLE                   ((uint16_t)0x0000U)                     /*!< channel disable */
+
+/* channel complementary output enable state */
+#define TIMER_CCXN_ENABLE                   ((uint16_t)0x0004U)                     /*!< channel complementary enable */
+#define TIMER_CCXN_DISABLE                  ((uint16_t)0x0000U)                     /*!< channel complementary disable */
+
+/* channel output polarity */
+#define TIMER_OC_POLARITY_HIGH              ((uint16_t)0x0000U)                     /*!< channel output polarity is high */
+#define TIMER_OC_POLARITY_LOW               ((uint16_t)0x0002U)                     /*!< channel output polarity is low */
+
+/* channel complementary output polarity */
+#define TIMER_OCN_POLARITY_HIGH             ((uint16_t)0x0000U)                     /*!< channel complementary output polarity is high */
+#define TIMER_OCN_POLARITY_LOW              ((uint16_t)0x0008U)                     /*!< channel complementary output polarity is low */
+
+/* idle state of channel output */ 
+#define TIMER_OC_IDLE_STATE_HIGH            ((uint16_t)0x0100)                      /*!< idle state of channel output is high */
+#define TIMER_OC_IDLE_STATE_LOW             ((uint16_t)0x0000)                      /*!< idle state of channel output is low */
+
+/* idle state of channel complementary output */ 
+#define TIMER_OCN_IDLE_STATE_HIGH           ((uint16_t)0x0200U)                     /*!< idle state of channel complementary output is high */
+#define TIMER_OCN_IDLE_STATE_LOW            ((uint16_t)0x0000U)                     /*!< idle state of channel complementary output is low */
+
+/* channel output compare mode */
+#define TIMER_OC_MODE_TIMING                ((uint16_t)0x0000U)                     /*!< timing mode */
+#define TIMER_OC_MODE_ACTIVE                ((uint16_t)0x0010U)                     /*!< active mode */
+#define TIMER_OC_MODE_INACTIVE              ((uint16_t)0x0020U)                     /*!< inactive mode */
+#define TIMER_OC_MODE_TOGGLE                ((uint16_t)0x0030U)                     /*!< toggle mode */
+#define TIMER_OC_MODE_LOW                   ((uint16_t)0x0040U)                     /*!< force low mode */
+#define TIMER_OC_MODE_HIGH                  ((uint16_t)0x0050U)                     /*!< force high mode */
+#define TIMER_OC_MODE_PWM0                  ((uint16_t)0x0060U)                     /*!< PWM0 mode */
+#define TIMER_OC_MODE_PWM1                  ((uint16_t)0x0070U)                     /*!< PWM1 mode */
+
+/* channel output compare shadow enable */
+#define TIMER_OC_SHADOW_ENABLE              ((uint16_t)0x0008U)                     /*!< channel output shadow state enable */
+#define TIMER_OC_SHADOW_DISABLE             ((uint16_t)0x0000U)                     /*!< channel output shadow state disable */
+
+/* channel output compare fast enable */
+#define TIMER_OC_FAST_ENABLE                ((uint16_t)0x0004)                      /*!< channel output fast function enable */
+#define TIMER_OC_FAST_DISABLE               ((uint16_t)0x0000)                      /*!< channel output fast function disable */
+
+/* channel output compare clear enable */
+#define TIMER_OC_CLEAR_ENABLE               ((uint16_t)0x0080U)                     /*!< channel output clear function enable */
+#define TIMER_OC_CLEAR_DISABLE              ((uint16_t)0x0000U)                     /*!< channel output clear function disable */
+
+/* channel control shadow register update control */ 
+#define TIMER_UPDATECTL_CCU                 ((uint32_t)0x00000000U)                 /*!< the shadow registers update by when CMTG bit is set */
+#define TIMER_UPDATECTL_CCUTRI              TIMER_CTL1_CCUC                         /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */
+
+/* channel input capture polarity */
+#define TIMER_IC_POLARITY_RISING            ((uint16_t)0x0000U)                     /*!< input capture rising edge */
+#define TIMER_IC_POLARITY_FALLING           ((uint16_t)0x0002U)                     /*!< input capture falling edge */
+#define TIMER_IC_POLARITY_BOTH_EDGE         ((uint16_t)0x000AU)                     /*!< input capture both edge */
+
+/* TIMER input capture selection */
+#define TIMER_IC_SELECTION_DIRECTTI         ((uint16_t)0x0001U)                     /*!< channel n is configured as input and icy is mapped on CIy */
+#define TIMER_IC_SELECTION_INDIRECTTI       ((uint16_t)0x0002U)                     /*!< channel n is configured as input and icy is mapped on opposite input */
+#define TIMER_IC_SELECTION_ITS              ((uint16_t)0x0003U)                     /*!< channel n is configured as input and icy is mapped on ITS */
+
+/* channel input capture prescaler */
+#define TIMER_IC_PSC_DIV1                   ((uint16_t)0x0000U)                     /*!< no prescaler */
+#define TIMER_IC_PSC_DIV2                   ((uint16_t)0x0004U)                     /*!< divided by 2 */
+#define TIMER_IC_PSC_DIV4                   ((uint16_t)0x0008U)                     /*!< divided by 4 */
+#define TIMER_IC_PSC_DIV8                   ((uint16_t)0x000CU)                     /*!< divided by 8 */
+
+/* trigger selection */
+#define SMCFG_TRGSEL(regval)                (BITS(4, 6) & ((uint32_t)(regval) << 4U))
+#define TIMER_SMCFG_TRGSEL_ITI0             SMCFG_TRGSEL(0)                         /*!< internal trigger 0 */
+#define TIMER_SMCFG_TRGSEL_ITI1             SMCFG_TRGSEL(1)                         /*!< internal trigger 1 */
+#define TIMER_SMCFG_TRGSEL_ITI2             SMCFG_TRGSEL(2)                         /*!< internal trigger 2 */
+#define TIMER_SMCFG_TRGSEL_ITI3             SMCFG_TRGSEL(3)                         /*!< internal trigger 3 */
+#define TIMER_SMCFG_TRGSEL_CI0F_ED          SMCFG_TRGSEL(4)                         /*!< TI0 Edge Detector */
+#define TIMER_SMCFG_TRGSEL_CI0FE0           SMCFG_TRGSEL(5)                         /*!< filtered TIMER input 0 */
+#define TIMER_SMCFG_TRGSEL_CI1FE1           SMCFG_TRGSEL(6)                         /*!< filtered TIMER input 1 */
+#define TIMER_SMCFG_TRGSEL_ETIFP            SMCFG_TRGSEL(7)                         /*!< filtered external trigger input */
+
+/* master mode control */
+#define CTL1_MMC(regval)                    (BITS(4, 6) & ((uint32_t)(regval) << 4U))
+#define TIMER_TRI_OUT_SRC_RESET             CTL1_MMC(0)                             /*!< the UPG bit as trigger output */
+#define TIMER_TRI_OUT_SRC_ENABLE            CTL1_MMC(1)                             /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
+#define TIMER_TRI_OUT_SRC_UPDATE            CTL1_MMC(2)                             /*!< update event as trigger output */
+#define TIMER_TRI_OUT_SRC_CH0               CTL1_MMC(3)                             /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */
+#define TIMER_TRI_OUT_SRC_O0CPRE            CTL1_MMC(4)                             /*!< O0CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O1CPRE            CTL1_MMC(5)                             /*!< O1CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O2CPRE            CTL1_MMC(6)                             /*!< O2CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O3CPRE            CTL1_MMC(7)                             /*!< O3CPRE as trigger output */
+
+/* slave mode control */
+#define SMCFG_SMC(regval)                   (BITS(0, 2) & ((uint32_t)(regval) << 0U)) 
+#define TIMER_SLAVE_MODE_DISABLE            SMCFG_SMC(0)                            /*!< slave mode disable */
+#define TIMER_ENCODER_MODE0                 SMCFG_SMC(1)                            /*!< encoder mode 0 */
+#define TIMER_ENCODER_MODE1                 SMCFG_SMC(2)                            /*!< encoder mode 1 */
+#define TIMER_ENCODER_MODE2                 SMCFG_SMC(3)                            /*!< encoder mode 2 */
+#define TIMER_SLAVE_MODE_RESTART            SMCFG_SMC(4)                            /*!< restart mode */
+#define TIMER_SLAVE_MODE_PAUSE              SMCFG_SMC(5)                            /*!< pause mode */
+#define TIMER_SLAVE_MODE_EVENT              SMCFG_SMC(6)                            /*!< event mode */
+#define TIMER_SLAVE_MODE_EXTERNAL0          SMCFG_SMC(7)                            /*!< external clock mode 0 */
+
+/* master slave mode selection */ 
+#define TIMER_MASTER_SLAVE_MODE_ENABLE      TIMER_SMCFG_MSM                         /*!< master slave mode enable */
+#define TIMER_MASTER_SLAVE_MODE_DISABLE     ((uint32_t)0x00000000U)                 /*!< master slave mode disable */
+
+/* external trigger prescaler */
+#define SMCFG_ETPSC(regval)                 (BITS(12, 13) & ((uint32_t)(regval) << 12U))
+#define TIMER_EXT_TRI_PSC_OFF               SMCFG_ETPSC(0)                          /*!< no divided */
+#define TIMER_EXT_TRI_PSC_DIV2              SMCFG_ETPSC(1)                          /*!< divided by 2 */
+#define TIMER_EXT_TRI_PSC_DIV4              SMCFG_ETPSC(2)                          /*!< divided by 4 */
+#define TIMER_EXT_TRI_PSC_DIV8              SMCFG_ETPSC(3)                          /*!< divided by 8 */
+
+/* external trigger polarity */
+#define TIMER_ETP_FALLING                   TIMER_SMCFG_ETP                         /*!< active low or falling edge active */
+#define TIMER_ETP_RISING                    ((uint32_t)0x00000000U)                 /*!< active high or rising edge active */
+
+/* channel 0 trigger input selection */ 
+#define TIMER_HALLINTERFACE_ENABLE          TIMER_CTL1_TI0S                         /*!< TIMER hall sensor mode enable */
+#define TIMER_HALLINTERFACE_DISABLE         ((uint32_t)0x00000000U)                 /*!< TIMER hall sensor mode disable */
+
+/* TIMERx(x=0..4) write CHxVAL register selection */
+#define TIMER_CHVSEL_ENABLE                 ((uint16_t)TIMER_CFG_OUTSEL)            /*!< write CHxVAL register selection enable */
+#define TIMER_CHVSEL_DISABLE                ((uint16_t)0x0000U)                     /*!< write CHxVAL register selection disable */
+
+/* function declarations */
+/* TIMER timebase */
+/* deinit a timer */
+void timer_deinit(uint32_t timer_periph);
+/* initialize TIMER init parameter struct */
+void timer_struct_para_init(timer_parameter_struct* initpara);
+/* initialize TIMER counter */
+void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
+/* enable a timer */
+void timer_enable(uint32_t timer_periph);
+/* disable a timer */
+void timer_disable(uint32_t timer_periph);
+/* enable the auto reload shadow function */
+void timer_auto_reload_shadow_enable(uint32_t timer_periph);
+/* disable the auto reload shadow function */
+void timer_auto_reload_shadow_disable(uint32_t timer_periph);
+/* enable the update event */
+void timer_update_event_enable(uint32_t timer_periph);
+/* disable the update event */
+void timer_update_event_disable(uint32_t timer_periph);
+/* set TIMER counter alignment mode */
+void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
+/* set TIMER counter up direction */
+void timer_counter_up_direction(uint32_t timer_periph);
+/* set TIMER counter down direction */
+void timer_counter_down_direction(uint32_t timer_periph);
+
+/* configure TIMER prescaler */
+void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload);
+/* configure TIMER repetition register value */
+void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition);
+/* configure TIMER autoreload register value */
+void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload);
+/* configure TIMER counter register value */
+void timer_counter_value_config(uint32_t timer_periph, uint16_t counter);
+/* read TIMER counter value */
+uint32_t timer_counter_read(uint32_t timer_periph);
+/* read TIMER prescaler value */
+uint16_t timer_prescaler_read(uint32_t timer_periph);
+/* configure TIMER single pulse mode */
+void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
+/* configure TIMER update source */
+void timer_update_source_config(uint32_t timer_periph, uint32_t update);
+
+/* TIMER DMA and event */
+/* enable the TIMER DMA */
+void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
+/* disable the TIMER DMA */
+void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
+/* channel DMA request source selection */
+void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request);
+/* configure the TIMER DMA transfer */
+void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth);
+/* software generate events */
+void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
+
+/* TIMER channel complementary protection */
+/* initialize TIMER break parameter struct */
+void timer_break_struct_para_init(timer_break_parameter_struct* breakpara);
+/* configure TIMER break function */
+void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
+/* enable TIMER break function */
+void timer_break_enable(uint32_t timer_periph);
+/* disable TIMER break function */
+void timer_break_disable(uint32_t timer_periph);
+/* enable TIMER output automatic function */
+void timer_automatic_output_enable(uint32_t timer_periph);
+/* disable TIMER output automatic function */
+void timer_automatic_output_disable(uint32_t timer_periph);
+/* enable or disable TIMER primary output function */
+void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
+/* enable or disable channel capture/compare control shadow register */
+void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
+/* configure TIMER channel control shadow register update control */
+void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl);
+
+/* TIMER channel output */
+/* initialize TIMER channel output parameter struct */
+void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara);
+/* configure TIMER channel output function */
+void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara);
+/* configure TIMER channel output compare mode */
+void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode);
+/* configure TIMER channel output pulse value */
+void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse);
+/* configure TIMER channel output shadow function */
+void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
+/* configure TIMER channel output fast function */
+void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
+/* configure TIMER channel output clear function */
+void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear);
+/* configure TIMER channel output polarity */
+void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
+/* configure TIMER channel complementary output polarity */
+void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
+/* configure TIMER channel enable state */
+void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
+/* configure TIMER channel complementary output enable state */
+void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
+
+/* TIMER channel input */
+/* initialize TIMER channel input parameter struct */
+void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara);
+/* configure TIMER input capture parameter */
+void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
+/* configure TIMER channel input capture prescaler value */
+void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
+/* read TIMER channel capture compare register value */
+uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
+/* configure TIMER input pwm capture function */
+void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
+/* configure TIMER hall sensor mode */
+void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode);
+
+/* TIMER master and slave mode */
+/* select TIMER input trigger source */
+void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
+/* select TIMER master mode output trigger source */
+void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
+/* select TIMER slave mode */
+void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode);
+/* configure TIMER master slave mode */
+void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave);
+/* configure TIMER external trigger input */
+void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
+/* configure TIMER quadrature decoder mode */
+void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
+/* configure TIMER internal clock mode */
+void timer_internal_clock_config(uint32_t timer_periph);
+/* configure TIMER the internal trigger as external clock input */
+void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
+/* configure TIMER the external trigger as external clock input */
+void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter);
+/* configure TIMER the external clock mode 0 */
+void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
+/* configure TIMER the external clock mode 1 */
+void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
+/* disable TIMER the external clock mode 1 */
+void timer_external_clock_mode1_disable(uint32_t timer_periph);
+
+/* TIMER interrupt and flag */
+/* enable the TIMER interrupt */
+void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
+/* disable the TIMER interrupt */
+void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
+/* get TIMER interrupt flag */
+FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
+/* clear TIMER interrupt flag */
+void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
+/* get TIMER flag */
+FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
+/* clear TIMER flag */
+void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
+
+#endif /* GD32VF103_TIMER_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h
new file mode 100644
index 0000000000..5caf7d81f5
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h
@@ -0,0 +1,374 @@
+/*!
+    \file    gd32vf103_usart.h
+    \brief   definitions for the USART
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_USART_H
+#define GD32VF103_USART_H
+
+#include "gd32vf103.h"
+
+/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */
+#define USART1                        USART_BASE                        /*!< USART1 base address */
+#define USART2                        (USART_BASE+(0x00000400U))        /*!< USART2 base address */
+#define UART3                         (USART_BASE+(0x00000800U))        /*!< UART3 base address */
+#define UART4                         (USART_BASE+(0x00000C00U))        /*!< UART4 base address */
+#define USART0                        (USART_BASE+(0x0000F400U))        /*!< USART0 base address */
+
+/* registers definitions */
+#define USART_STAT(usartx)            REG32((usartx) + (0x00000000U))   /*!< USART status register */
+#define USART_DATA(usartx)            REG32((usartx) + (0x00000004U))   /*!< USART data register */
+#define USART_BAUD(usartx)            REG32((usartx) + (0x00000008U))   /*!< USART baud rate register */
+#define USART_CTL0(usartx)            REG32((usartx) + (0x0000000CU))   /*!< USART control register 0 */
+#define USART_CTL1(usartx)            REG32((usartx) + (0x00000010U))   /*!< USART control register 1 */
+#define USART_CTL2(usartx)            REG32((usartx) + (0x00000014U))   /*!< USART control register 2 */
+#define USART_GP(usartx)              REG32((usartx) + (0x00000018U))   /*!< USART guard time and prescaler register */
+
+/* bits definitions */
+/* USARTx_STAT */
+#define USART_STAT_PERR               BIT(0)                            /*!< parity error flag */
+#define USART_STAT_FERR               BIT(1)                            /*!< frame error flag */
+#define USART_STAT_NERR               BIT(2)                            /*!< noise error flag */
+#define USART_STAT_ORERR              BIT(3)                            /*!< overrun error */
+#define USART_STAT_IDLEF              BIT(4)                            /*!< IDLE frame detected flag */
+#define USART_STAT_RBNE               BIT(5)                            /*!< read data buffer not empty */
+#define USART_STAT_TC                 BIT(6)                            /*!< transmission complete */
+#define USART_STAT_TBE                BIT(7)                            /*!< transmit data buffer empty */
+#define USART_STAT_LBDF               BIT(8)                            /*!< LIN break detected flag */
+#define USART_STAT_CTSF               BIT(9)                            /*!< CTS change flag */
+
+/* USARTx_DATA */
+#define USART_DATA_DATA               BITS(0,8)                         /*!< transmit or read data value */
+
+/* USARTx_BAUD */
+#define USART_BAUD_FRADIV             BITS(0,3)                         /*!< fraction part of baud-rate divider */
+#define USART_BAUD_INTDIV             BITS(4,15)                        /*!< integer part of baud-rate divider */
+
+/* USARTx_CTL0 */
+#define USART_CTL0_SBKCMD             BIT(0)                            /*!< send break command */
+#define USART_CTL0_RWU                BIT(1)                            /*!< receiver wakeup from mute mode */
+#define USART_CTL0_REN                BIT(2)                            /*!< receiver enable */
+#define USART_CTL0_TEN                BIT(3)                            /*!< transmitter enable */
+#define USART_CTL0_IDLEIE             BIT(4)                            /*!< idle line detected interrupt enable */
+#define USART_CTL0_RBNEIE             BIT(5)                            /*!< read data buffer not empty interrupt and overrun error interrupt enable */
+#define USART_CTL0_TCIE               BIT(6)                            /*!< transmission complete interrupt enable */
+#define USART_CTL0_TBEIE              BIT(7)                            /*!< transmitter buffer empty interrupt enable */
+#define USART_CTL0_PERRIE             BIT(8)                            /*!< parity error interrupt enable */
+#define USART_CTL0_PM                 BIT(9)                            /*!< parity mode */
+#define USART_CTL0_PCEN               BIT(10)                           /*!< parity check function enable */
+#define USART_CTL0_WM                 BIT(11)                           /*!< wakeup method in mute mode */
+#define USART_CTL0_WL                 BIT(12)                           /*!< word length */
+#define USART_CTL0_UEN                BIT(13)                           /*!< USART enable */
+
+/* USARTx_CTL1 */
+#define USART_CTL1_ADDR               BITS(0,3)                         /*!< address of USART */
+#define USART_CTL1_LBLEN              BIT(5)                            /*!< LIN break frame length */
+#define USART_CTL1_LBDIE              BIT(6)                            /*!< LIN break detected interrupt eanble */
+#define USART_CTL1_CLEN               BIT(8)                            /*!< CK length */
+#define USART_CTL1_CPH                BIT(9)                            /*!< CK phase */
+#define USART_CTL1_CPL                BIT(10)                           /*!< CK polarity */
+#define USART_CTL1_CKEN               BIT(11)                           /*!< CK pin enable */
+#define USART_CTL1_STB                BITS(12,13)                       /*!< STOP bits length */
+#define USART_CTL1_LMEN               BIT(14)                           /*!< LIN mode enable */
+
+/* USARTx_CTL2 */
+#define USART_CTL2_ERRIE              BIT(0)                            /*!< error interrupt enable */
+#define USART_CTL2_IREN               BIT(1)                            /*!< IrDA mode enable */
+#define USART_CTL2_IRLP               BIT(2)                            /*!< IrDA low-power */
+#define USART_CTL2_HDEN               BIT(3)                            /*!< half-duplex enable */
+#define USART_CTL2_NKEN               BIT(4)                            /*!< NACK enable in smartcard mode */
+#define USART_CTL2_SCEN               BIT(5)                            /*!< smartcard mode enable */
+#define USART_CTL2_DENR               BIT(6)                            /*!< DMA request enable for reception */
+#define USART_CTL2_DENT               BIT(7)                            /*!< DMA request enable for transmission */
+#define USART_CTL2_RTSEN              BIT(8)                            /*!< RTS enable */
+#define USART_CTL2_CTSEN              BIT(9)                            /*!< CTS enable */
+#define USART_CTL2_CTSIE              BIT(10)                           /*!< CTS interrupt enable */
+
+/* USARTx_GP */
+#define USART_GP_PSC                  BITS(0,7)                         /*!< prescaler value for dividing the system clock */
+#define USART_GP_GUAT                 BITS(8,15)                        /*!< guard time value in smartcard mode */
+
+/* constants definitions */
+/* define the USART bit position and its register index offset */
+#define USART_REGIDX_BIT(regidx, bitpos)     (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define USART_REG_VAL(usartx, offset)        (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6)))
+#define USART_BIT_POS(val)                   ((uint32_t)(val) & (0x0000001FU))
+#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)   (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
+                                                              | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
+#define USART_REG_VAL2(usartx, offset)       (REG32((usartx) + ((uint32_t)(offset) >> 22)))
+#define USART_BIT_POS2(val)                  (((uint32_t)(val) & (0x001F0000U)) >> 16)
+
+/* register offset */
+#define USART_STAT_REG_OFFSET                     (0x00000000U)        	/*!< STAT register offset */
+#define USART_CTL0_REG_OFFSET                     (0x0000000CU)        	/*!< CTL0 register offset */
+#define USART_CTL1_REG_OFFSET                     (0x00000010U)        	/*!< CTL1 register offset */
+#define USART_CTL2_REG_OFFSET                     (0x00000014U)        	/*!< CTL2 register offset */
+
+/* USART flags */
+typedef enum
+{
+    /* flags in STAT register */
+    USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U),      /*!< CTS change flag */
+    USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U),      /*!< LIN break detected flag */
+    USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U),       /*!< transmit data buffer empty */
+    USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U),        /*!< transmission complete */
+    USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U),      /*!< read data buffer not empty */
+    USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U),     /*!< IDLE frame detected flag */
+    USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U),     /*!< overrun error */
+    USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U),      /*!< noise error flag */
+    USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U),      /*!< frame error flag */
+    USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U),      /*!< parity error flag */
+}usart_flag_enum;
+
+/* USART interrupt flags */
+typedef enum
+{
+    /* interrupt flags in CTL0 register */
+    USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U),       /*!< parity error interrupt and flag */
+    USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U),        /*!< transmitter buffer empty interrupt and flag */
+    USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U),         /*!< transmission complete interrupt and flag */
+    USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U),       /*!< read data buffer not empty interrupt and flag */
+    USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
+    USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U),       /*!< IDLE line detected interrupt and flag */
+    /* interrupt flags in CTL1 register */
+    USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U),        /*!< LIN break detected interrupt and flag */
+    /* interrupt flags in CTL2 register */
+    USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U),       /*!< CTS interrupt and flag */
+    USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U),  /*!< error interrupt and overrun error */
+    USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U),   /*!< error interrupt and noise error flag */
+    USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U),   /*!< error interrupt and frame error flag */
+}usart_interrupt_flag_enum;
+
+/* USART interrupt enable or disable */
+typedef enum
+{
+    /* interrupt in CTL0 register */
+    USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),       /*!< parity error interrupt */
+    USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),        /*!< transmitter buffer empty interrupt */
+    USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),         /*!< transmission complete interrupt */
+    USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),       /*!< read data buffer not empty interrupt and overrun error interrupt */
+    USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),       /*!< IDLE line detected interrupt */
+    /* interrupt in CTL1 register */
+    USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),        /*!< LIN break detected interrupt */
+    /* interrupt in CTL2 register */
+    USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),       /*!< CTS interrupt */
+    USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),        /*!< error interrupt */
+}usart_interrupt_enum;
+
+/* USART receiver configure */
+#define CTL0_REN(regval)              (BIT(2) & ((uint32_t)(regval) << 2))
+#define USART_RECEIVE_ENABLE          CTL0_REN(1)                       /*!< enable receiver */
+#define USART_RECEIVE_DISABLE         CTL0_REN(0)                       /*!< disable receiver */
+
+/* USART transmitter configure */
+#define CTL0_TEN(regval)              (BIT(3) & ((uint32_t)(regval) << 3))
+#define USART_TRANSMIT_ENABLE         CTL0_TEN(1)                       /*!< enable transmitter */
+#define USART_TRANSMIT_DISABLE        CTL0_TEN(0)                       /*!< disable transmitter */
+
+/* USART parity bits definitions */
+#define CTL0_PM(regval)               (BITS(9,10) & ((uint32_t)(regval) << 9))
+#define USART_PM_NONE                 CTL0_PM(0)                        /*!< no parity */
+#define USART_PM_EVEN                 CTL0_PM(2)                        /*!< even parity */
+#define USART_PM_ODD                  CTL0_PM(3)                        /*!< odd parity */
+
+/* USART wakeup method in mute mode */
+#define CTL0_WM(regval)               (BIT(11) & ((uint32_t)(regval) << 11))
+#define USART_WM_IDLE                 CTL0_WM(0)                        /*!< idle line */
+#define USART_WM_ADDR                 CTL0_WM(1)                        /*!< address match */
+
+/* USART word length definitions */
+#define CTL0_WL(regval)               (BIT(12) & ((uint32_t)(regval) << 12))
+#define USART_WL_8BIT                 CTL0_WL(0)                        /*!< 8 bits */
+#define USART_WL_9BIT                 CTL0_WL(1)                        /*!< 9 bits */
+
+/* USART stop bits definitions */
+#define CTL1_STB(regval)              (BITS(12,13) & ((uint32_t)(regval) << 12))
+#define USART_STB_1BIT                CTL1_STB(0)                       /*!< 1 bit */
+#define USART_STB_0_5BIT              CTL1_STB(1)                       /*!< 0.5 bit */
+#define USART_STB_2BIT                CTL1_STB(2)                       /*!< 2 bits */
+#define USART_STB_1_5BIT              CTL1_STB(3)                       /*!< 1.5 bits */
+
+/* USART LIN break frame length */
+#define CTL1_LBLEN(regval)            (BIT(5) & ((uint32_t)(regval) << 5))
+#define USART_LBLEN_10B               CTL1_LBLEN(0)                     /*!< 10 bits */
+#define USART_LBLEN_11B               CTL1_LBLEN(1)                     /*!< 11 bits */
+
+/* USART CK length */
+#define CTL1_CLEN(regval)             (BIT(8) & ((uint32_t)(regval) << 8))
+#define USART_CLEN_NONE               CTL1_CLEN(0)                      /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */
+#define USART_CLEN_EN                 CTL1_CLEN(1)                      /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */
+
+/* USART clock phase */
+#define CTL1_CPH(regval)              (BIT(9) & ((uint32_t)(regval) << 9))
+#define USART_CPH_1CK                 CTL1_CPH(0)                       /*!< first clock transition is the first data capture edge */
+#define USART_CPH_2CK                 CTL1_CPH(1)                       /*!< second clock transition is the first data capture edge */
+
+/* USART clock polarity */
+#define CTL1_CPL(regval)              (BIT(10) & ((uint32_t)(regval) << 10))
+#define USART_CPL_LOW                 CTL1_CPL(0)                       /*!< steady low value on CK pin */
+#define USART_CPL_HIGH                CTL1_CPL(1)                       /*!< steady high value on CK pin */
+
+/* USART DMA request for receive configure */
+#define CLT2_DENR(regval)             (BIT(6) & ((uint32_t)(regval) << 6))
+#define USART_DENR_ENABLE             CLT2_DENR(1)                      /*!< DMA request enable for reception */
+#define USART_DENR_DISABLE            CLT2_DENR(0)                      /*!< DMA request disable for reception */
+
+/* USART DMA request for transmission configure */
+#define CLT2_DENT(regval)             (BIT(7) & ((uint32_t)(regval) << 7))
+#define USART_DENT_ENABLE             CLT2_DENT(1)                      /*!< DMA request enable for transmission */
+#define USART_DENT_DISABLE            CLT2_DENT(0)                      /*!< DMA request disable for transmission */
+
+/* USART RTS configure */
+#define CLT2_RTSEN(regval)            (BIT(8) & ((uint32_t)(regval) << 8))
+#define USART_RTS_ENABLE              CLT2_RTSEN(1)                     /*!< RTS enable */
+#define USART_RTS_DISABLE             CLT2_RTSEN(0)                     /*!< RTS disable */
+
+/* USART CTS configure */
+#define CLT2_CTSEN(regval)            (BIT(9) & ((uint32_t)(regval) << 9))
+#define USART_CTS_ENABLE              CLT2_CTSEN(1)                     /*!< CTS enable */
+#define USART_CTS_DISABLE             CLT2_CTSEN(0)                     /*!< CTS disable */
+
+/* USART IrDA low-power enable */
+#define CTL2_IRLP(regval)             (BIT(2) & ((uint32_t)(regval) << 2))
+#define USART_IRLP_LOW                CTL2_IRLP(1)                      /*!< low-power */
+#define USART_IRLP_NORMAL             CTL2_IRLP(0)                      /*!< normal */
+
+/* function declarations */
+/* initialization functions */
+/* reset USART */
+void usart_deinit(uint32_t usart_periph);
+/* configure USART baud rate value */
+void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
+/* configure USART parity function */
+void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
+/* configure USART word length */
+void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
+/* configure USART stop bit length */
+void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
+
+/* USART normal mode communication */
+/* enable USART */
+void usart_enable(uint32_t usart_periph);
+/* disable USART */
+void usart_disable(uint32_t usart_periph);
+/* configure USART transmitter */
+void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
+/* configure USART receiver */
+void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
+/* USART transmit data function */
+void usart_data_transmit(uint32_t usart_periph, uint32_t data);
+/* USART receive data function */
+uint16_t usart_data_receive(uint32_t usart_periph);
+
+/* multi-processor communication */
+/* configure address of the USART */
+void usart_address_config(uint32_t usart_periph, uint8_t addr);
+/* enable mute mode */
+void usart_mute_mode_enable(uint32_t usart_periph);
+/* disable mute mode */
+void usart_mute_mode_disable(uint32_t usart_periph);
+/* configure wakeup method in mute mode */
+void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
+
+/* LIN mode communication */
+/* LIN mode enable */
+void usart_lin_mode_enable(uint32_t usart_periph);
+/* LIN mode disable */
+void usart_lin_mode_disable(uint32_t usart_periph);
+/* LIN break detection length */
+void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
+/* send break frame */
+void usart_send_break(uint32_t usart_periph);
+
+/* half-duplex communication */
+/* half-duplex enable */
+void usart_halfduplex_enable(uint32_t usart_periph);
+/* half-duplex disable */
+void usart_halfduplex_disable(uint32_t usart_periph);
+
+/* synchronous communication */
+/* clock enable */
+void usart_synchronous_clock_enable(uint32_t usart_periph);
+/* clock disable */
+void usart_synchronous_clock_disable(uint32_t usart_periph);
+/* configure usart synchronous mode parameters */
+void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
+
+/* smartcard communication */
+/* guard time value configure in smartcard mode */
+void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut);
+/* smartcard mode enable */
+void usart_smartcard_mode_enable(uint32_t usart_periph);
+/* smartcard mode disable */
+void usart_smartcard_mode_disable(uint32_t usart_periph);
+/* NACK enable in smartcard mode */
+void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
+/* NACK disable in smartcard mode */
+void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
+
+/* IrDA communication */
+/* enable IrDA mode */
+void usart_irda_mode_enable(uint32_t usart_periph);
+/* disable IrDA mode */
+void usart_irda_mode_disable(uint32_t usart_periph);
+/* configure the peripheral clock prescaler */
+void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
+/* configure IrDA low-power */
+void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
+
+/* hardware flow communication */
+/* configure hardware flow control RTS */
+void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
+/* configure hardware flow control CTS */
+void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
+
+/* configure USART DMA for reception */
+void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
+/* configure USART DMA for transmission */
+void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
+
+/* flag functions */
+/* get flag in STAT register */
+FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
+/* clear flag in STAT register */
+void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
+
+/* interrupt functions */
+/* enable USART interrupt */
+void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag);
+/* disable USART interrupt */
+void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag);
+/* get USART interrupt and flag status */
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
+/* clear interrupt flag in STAT register */
+void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag);
+#endif /* GD32VF103_USART_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h
new file mode 100644
index 0000000000..b972bba458
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h
@@ -0,0 +1,86 @@
+/*!
+    \file  gd32vf103_wwdgt.h
+    \brief definitions for the WWDGT
+    
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_WWDGT_H
+#define GD32VF103_WWDGT_H
+
+#include "gd32vf103.h"
+
+/* WWDGT definitions */
+#define WWDGT                       WWDGT_BASE                                /*!< WWDGT base address */
+
+/* registers definitions */
+#define WWDGT_CTL                   REG32((WWDGT) + 0x00000000U)              /*!< WWDGT control register */
+#define WWDGT_CFG                   REG32((WWDGT) + 0x00000004U)              /*!< WWDGT configuration register */
+#define WWDGT_STAT                  REG32((WWDGT) + 0x00000008U)              /*!< WWDGT status register */
+
+/* bits definitions */
+/* WWDGT_CTL */
+#define WWDGT_CTL_CNT               BITS(0,6)                                 /*!< WWDGT counter value */
+#define WWDGT_CTL_WDGTEN            BIT(7)                                    /*!< WWDGT counter enable */
+
+/* WWDGT_CFG */
+#define WWDGT_CFG_WIN               BITS(0,6)                                 /*!< WWDGT counter window value */
+#define WWDGT_CFG_PSC               BITS(7,8)                                 /*!< WWDGT prescaler divider value */
+#define WWDGT_CFG_EWIE              BIT(9)                                    /*!< early wakeup interrupt enable */
+
+/* WWDGT_STAT */
+#define WWDGT_STAT_EWIF             BIT(0)                                    /*!< early wakeup interrupt flag */
+
+/* constants definitions */
+#define CFG_PSC(regval)             (BITS(7,8) & ((uint32_t)(regval) << 7))   /*!< write value to WWDGT_CFG_PSC bit field */
+#define WWDGT_CFG_PSC_DIV1          CFG_PSC(0)                                /*!< the time base of WWDGT = (PCLK1/4096)/1 */
+#define WWDGT_CFG_PSC_DIV2          CFG_PSC(1)                                /*!< the time base of WWDGT = (PCLK1/4096)/2 */
+#define WWDGT_CFG_PSC_DIV4          CFG_PSC(2)                                /*!< the time base of WWDGT = (PCLK1/4096)/4 */
+#define WWDGT_CFG_PSC_DIV8          CFG_PSC(3)                                /*!< the time base of WWDGT = (PCLK1/4096)/8 */
+
+/* function declarations */
+/* reset the window watchdog timer configuration */
+void wwdgt_deinit(void);
+/* start the window watchdog timer counter */
+void wwdgt_enable(void);
+
+/* configure the window watchdog timer counter value */
+void wwdgt_counter_update(uint16_t counter_value);
+/* configure counter value, window value, and prescaler divider value */
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
+
+/* enable early wakeup interrupt of WWDGT */
+void wwdgt_interrupt_enable(void);
+/* check early wakeup interrupt state of WWDGT */
+FlagStatus wwdgt_flag_get(void);
+/* clear early wakeup interrupt state of WWDGT */
+void wwdgt_flag_clear(void);
+
+#endif /* GD32VF103_WWDGT_H */
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c
new file mode 100644
index 0000000000..8a48676bc4
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c
@@ -0,0 +1,992 @@
+/*!
+    \file  gd32vf103_adc.c
+    \brief ADC driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_adc.h"
+
+/* discontinuous mode macro*/
+#define  ADC_CHANNEL_LENGTH_SUBTRACT_ONE            ((uint8_t)1U)
+
+/* ADC regular channel macro */
+#define  ADC_REGULAR_CHANNEL_RANK_SIX               ((uint8_t)6U)
+#define  ADC_REGULAR_CHANNEL_RANK_TWELVE            ((uint8_t)12U)
+#define  ADC_REGULAR_CHANNEL_RANK_SIXTEEN           ((uint8_t)16U)
+#define  ADC_REGULAR_CHANNEL_RANK_LENGTH            ((uint8_t)5U)
+
+/* ADC sampling time macro */
+#define  ADC_CHANNEL_SAMPLE_TEN                     ((uint8_t)10U)
+#define  ADC_CHANNEL_SAMPLE_EIGHTEEN                ((uint8_t)18U)
+#define  ADC_CHANNEL_SAMPLE_LENGTH                  ((uint8_t)3U)
+
+/* ADC inserted channel macro */
+#define  ADC_INSERTED_CHANNEL_RANK_LENGTH           ((uint8_t)5U)
+#define  ADC_INSERTED_CHANNEL_SHIFT_LENGTH          ((uint8_t)15U)
+
+/* ADC inserted channel offset macro */
+#define  ADC_OFFSET_LENGTH                          ((uint8_t)3U)
+#define  ADC_OFFSET_SHIFT_LENGTH                    ((uint8_t)4U)
+
+/*!
+    \brief      reset ADC 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_deinit(uint32_t adc_periph)
+{
+    switch(adc_periph){
+    case ADC0:
+        /* reset ADC0 */
+        rcu_periph_reset_enable(RCU_ADC0RST);
+        rcu_periph_reset_disable(RCU_ADC0RST);
+        break;
+    case ADC1:
+        /* reset ADC1 */
+        rcu_periph_reset_enable(RCU_ADC1RST);
+        rcu_periph_reset_disable(RCU_ADC1RST);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure the ADC sync mode
+    \param[in]  mode: ADC mode
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_MODE_FREE: all the ADCs work independently
+      \arg        ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
+      \arg        ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
+      \arg        ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
+      \arg        ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
+      \arg        ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
+      \arg        ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
+      \arg        ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
+      \arg        ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
+      \arg        ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
+    \param[out] none
+    \retval     none
+*/
+void adc_mode_config(uint32_t mode)
+{
+    ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
+    ADC_CTL0(ADC0) |= mode;
+}
+
+/*!
+    \brief      enable or disable ADC special function
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  function: the function to config
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_SCAN_MODE: scan mode select
+      \arg        ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
+      \arg        ADC_CONTINUOUS_MODE: continuous mode select
+    \param[in]  newvalue: ENABLE or DISABLE
+    \param[out] none
+    \retval     none
+*/
+void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
+{
+    if(newvalue){
+        if(0U != (function & ADC_SCAN_MODE)){
+            /* enable scan mode */
+            ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
+        }
+        if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
+            /* enable inserted channel group convert automatically */
+            ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
+        } 
+        if(0U != (function & ADC_CONTINUOUS_MODE)){
+            /* enable continuous mode */
+            ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
+        }        
+    }else{
+        if(0U != (function & ADC_SCAN_MODE)){
+            /* disable scan mode */
+            ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
+        }
+        if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
+            /* disable inserted channel group convert automatically */
+            ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
+        } 
+        if(0U != (function & ADC_CONTINUOUS_MODE)){
+            /* disable continuous mode */
+            ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
+        }       
+    }
+}
+
+/*!
+    \brief      configure ADC data alignment 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  data_alignment: data alignment select
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_DATAALIGN_RIGHT: LSB alignment
+      \arg        ADC_DATAALIGN_LEFT: MSB alignment
+    \param[out] none
+    \retval     none
+*/
+void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
+{
+    if(ADC_DATAALIGN_RIGHT != data_alignment){
+        /* MSB alignment */
+        ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
+    }else{
+        /* LSB alignment */
+        ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
+    }
+}
+
+/*!
+    \brief      enable ADC interface
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_enable(uint32_t adc_periph)
+{
+    if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
+        /* enable ADC */
+        ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
+    }       
+}
+
+/*!
+    \brief      disable ADC interface
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_disable(uint32_t adc_periph)
+{
+    /* disable ADC */
+    ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
+}
+
+/*!
+    \brief      ADC calibration and reset calibration
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_calibration_enable(uint32_t adc_periph)
+{
+    /* reset the selected ADC1 calibration registers */
+    ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
+    /* check the RSTCLB bit state */
+    while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
+    }
+    /* enable ADC calibration process */
+    ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
+    /* check the CLB bit state */
+    while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
+    }
+}
+
+/*!
+    \brief      enable the temperature sensor and Vrefint channel
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_tempsensor_vrefint_enable(void)
+{
+    /* enable the temperature sensor and Vrefint channel */
+    ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
+}
+
+/*!
+    \brief      disable the temperature sensor and Vrefint channel
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_tempsensor_vrefint_disable(void)
+{
+    /* disable the temperature sensor and Vrefint channel */
+    ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
+}
+
+/*!
+    \brief      enable DMA request 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_dma_mode_enable(uint32_t adc_periph)
+{
+    /* enable DMA request */
+    ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
+}
+
+/*!
+    \brief      disable DMA request 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_dma_mode_disable(uint32_t adc_periph)
+{
+    /* disable DMA request */
+    ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
+}
+
+/*!
+    \brief      configure ADC discontinuous mode 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_channel_group: select the channel group
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+      \arg        ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
+    \param[in]  length: number of conversions in discontinuous mode,the number can be 1..8
+                        for regular channel, the number has no effect for inserted channel
+    \param[out] none
+    \retval     none
+*/
+void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
+{
+    /* disable discontinuous mode of regular & inserted channel */
+    ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
+    switch(adc_channel_group){
+    case ADC_REGULAR_CHANNEL:
+        /* config the number of conversions in discontinuous mode */
+        ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
+        ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
+        /* enable regular channel group discontinuous mode */
+        ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
+        break;
+    case ADC_INSERTED_CHANNEL:
+        /* enable inserted channel group discontinuous mode */
+        ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
+        break;
+    case ADC_CHANNEL_DISCON_DISABLE:
+        /* disable discontinuous mode of regular & inserted channel */
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure the length of regular channel group or inserted channel group
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_channel_group: select the channel group
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+    \param[in]  length: the length of the channel
+                        regular channel 1-16
+                        inserted channel 1-4
+    \param[out] none
+    \retval     none
+*/
+void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
+{
+    switch(adc_channel_group){
+    case ADC_REGULAR_CHANNEL:
+        /* configure the length of regular channel group */
+        ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
+        ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
+        break;
+    case ADC_INSERTED_CHANNEL:
+        /* configure the length of inserted channel group */
+        ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
+        ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure ADC regular channel 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  rank: the regular group sequence rank,this parameter must be between 0 to 15
+    \param[in]  adc_channel: the selected ADC channel
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx 
+    \param[in]  sample_time: the sample time value
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_SAMPLETIME_1POINT5: 1.5 cycles
+      \arg        ADC_SAMPLETIME_7POINT5: 7.5 cycles
+      \arg        ADC_SAMPLETIME_13POINT5: 13.5 cycles
+      \arg        ADC_SAMPLETIME_28POINT5: 28.5 cycles
+      \arg        ADC_SAMPLETIME_41POINT5: 41.5 cycles
+      \arg        ADC_SAMPLETIME_55POINT5: 55.5 cycles
+      \arg        ADC_SAMPLETIME_71POINT5: 71.5 cycles
+      \arg        ADC_SAMPLETIME_239POINT5: 239.5 cycles
+    \param[out] none
+    \retval     none
+*/
+void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
+{
+    uint32_t rsq,sampt;
+    
+    /* ADC regular sequence config */
+    if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){
+        /* the regular group sequence rank is smaller than six */
+        rsq = ADC_RSQ2(adc_periph);
+        rsq &=  ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)));
+        /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
+        rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank));
+        ADC_RSQ2(adc_periph) = rsq;
+    }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){
+        /* the regular group sequence rank is smaller than twelve */
+        rsq = ADC_RSQ1(adc_periph);
+        rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))));
+        /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
+        rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)));
+        ADC_RSQ1(adc_periph) = rsq;
+    }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){
+        /* the regular group sequence rank is smaller than sixteen */
+        rsq = ADC_RSQ0(adc_periph);
+        rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))));
+        /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
+        rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)));
+        ADC_RSQ0(adc_periph) = rsq;
+    }else{
+    }
+    
+    /* ADC sampling time config */
+    if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
+        /* the regular group sequence rank is smaller than ten */
+        sampt = ADC_SAMPT1(adc_periph);
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
+        /* channel sample time set*/
+        sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel));
+        ADC_SAMPT1(adc_periph) = sampt;
+    }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
+        /* the regular group sequence rank is smaller than eighteen */
+        sampt = ADC_SAMPT0(adc_periph);
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
+        /* channel sample time set*/
+        sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
+        ADC_SAMPT0(adc_periph) = sampt;
+    }else{
+    }
+}
+
+/*!
+    \brief      configure ADC inserted channel 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  rank: the inserted group sequencer rank,this parameter must be between 0 to 3
+    \param[in]  adc_channel: the selected ADC channel
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
+    \param[in]  sample_time: The sample time value
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_SAMPLETIME_1POINT5: 1.5 cycles
+      \arg        ADC_SAMPLETIME_7POINT5: 7.5 cycles
+      \arg        ADC_SAMPLETIME_13POINT5: 13.5 cycles
+      \arg        ADC_SAMPLETIME_28POINT5: 28.5 cycles
+      \arg        ADC_SAMPLETIME_41POINT5: 41.5 cycles
+      \arg        ADC_SAMPLETIME_55POINT5: 55.5 cycles
+      \arg        ADC_SAMPLETIME_71POINT5: 71.5 cycles
+      \arg        ADC_SAMPLETIME_239POINT5: 239.5 cycles
+    \param[out] none
+    \retval     none
+*/
+void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
+{
+    uint8_t inserted_length;
+    uint32_t isq,sampt;
+    /* get inserted channel group length */
+    inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
+    /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
+    isq = ADC_ISQ(adc_periph);
+    isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)));
+    isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH));
+    ADC_ISQ(adc_periph) = isq;
+
+    /* ADC sampling time config */  
+    if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
+        /* the inserted group sequence rank is smaller than ten */
+        sampt = ADC_SAMPT1(adc_periph);
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
+        /* channel sample time set*/
+        sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel);
+        ADC_SAMPT1(adc_periph) = sampt;
+    }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
+        /* the inserted group sequence rank is smaller than eighteen */
+        sampt = ADC_SAMPT0(adc_periph);
+        sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
+        /* channel sample time set*/
+        sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
+        ADC_SAMPT0(adc_periph) = sampt;
+    }else{
+    }
+}
+
+/*!
+    \brief      configure ADC inserted channel offset 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  inserted_channel: insert channel select
+                only one parameter can be selected
+      \arg        ADC_INSERTED_CHANNEL_0: inserted channel0
+      \arg        ADC_INSERTED_CHANNEL_1: inserted channel1
+      \arg        ADC_INSERTED_CHANNEL_2: inserted channel2
+      \arg        ADC_INSERTED_CHANNEL_3: inserted channel3
+    \param[in]  offset: the offset data
+    \param[out] none
+    \retval     none
+*/
+void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
+{
+    uint8_t inserted_length;
+    uint32_t num = 0U;
+
+    inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
+    num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
+    
+    if(num <= ADC_OFFSET_LENGTH){
+        /* calculate the offset of the register */
+        num = num * ADC_OFFSET_SHIFT_LENGTH;
+        /* config the offset of the selected channels */
+        REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
+    }  
+}
+
+/*!
+    \brief      configure ADC external trigger source 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_channel_group: select the channel group
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+    \param[in]  external_trigger_source: regular or inserted group trigger source
+                only one parameter can be selected
+                for regular channel:
+      \arg        ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select 
+      \arg        ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select 
+      \arg        ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select 
+      \arg        ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select 
+      \arg        ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select 
+      \arg        ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select 
+      \arg        ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 
+      \arg        ADC0_1_EXTTRIG_REGULAR_NONE: software trigger
+                for inserted channel:
+      \arg        ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select 
+      \arg        ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select 
+      \arg        ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select 
+      \arg        ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select 
+      \arg        ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select 
+      \arg        ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select 
+      \arg        ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 
+      \arg        ADC0_1_EXTTRIG_INSERTED_NONE: software trigger
+    \param[out] none
+    \retval     none
+*/
+void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
+{   
+    switch(adc_channel_group){
+    case ADC_REGULAR_CHANNEL:
+        /* configure ADC regular group external trigger source */
+        ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
+        ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
+        break;
+    case ADC_INSERTED_CHANNEL:
+        /* configure ADC inserted group external trigger source */
+        ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
+        ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure ADC external trigger 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_channel_group: select the channel group
+                one or more parameters can be selected which are shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+    \param[in]  newvalue: ENABLE or DISABLE
+    \param[out] none
+    \retval     none
+*/
+void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
+{
+    if(newvalue){
+        if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
+            /* enable ADC regular channel group external trigger */
+            ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
+        }
+        if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
+            /* enable ADC inserted channel group external trigger */
+            ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
+        }        
+    }else{
+        if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
+            /* disable ADC regular channel group external trigger */
+            ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
+        }
+        if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
+            /* disable ADC regular channel group external trigger */
+            ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
+        }      
+    }
+}
+
+/*!
+    \brief      enable ADC software trigger 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_channel_group: select the channel group
+                one or more parameters can be selected which are shown as below:
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+    \param[out] none
+    \retval     none
+*/
+void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
+{
+    if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
+        /* enable ADC regular channel group software trigger */
+        ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
+    }
+    if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
+        /* enable ADC inserted channel group software trigger */
+        ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
+    }
+}
+
+/*!
+    \brief      read ADC regular group data register 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  none
+    \param[out] none
+    \retval     the conversion value
+*/
+uint16_t adc_regular_data_read(uint32_t adc_periph)
+{
+    return (uint16_t)(ADC_RDATA(adc_periph));
+}
+
+/*!
+    \brief      read ADC inserted group data register 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  inserted_channel: insert channel select
+                only one parameter can be selected
+      \arg        ADC_INSERTED_CHANNEL_0: inserted Channel0
+      \arg        ADC_INSERTED_CHANNEL_1: inserted channel1
+      \arg        ADC_INSERTED_CHANNEL_2: inserted Channel2
+      \arg        ADC_INSERTED_CHANNEL_3: inserted Channel3
+    \param[out] none
+    \retval     the conversion value
+*/
+uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
+{
+    uint32_t idata;
+    /* read the data of the selected channel */
+    switch(inserted_channel){
+    case ADC_INSERTED_CHANNEL_0:
+        /* read the data of channel 0 */
+        idata = ADC_IDATA0(adc_periph);
+        break;
+    case ADC_INSERTED_CHANNEL_1:
+        /* read the data of channel 1 */
+        idata = ADC_IDATA1(adc_periph);
+        break;
+    case ADC_INSERTED_CHANNEL_2:
+        /* read the data of channel 2 */
+        idata = ADC_IDATA2(adc_periph);
+        break;
+    case ADC_INSERTED_CHANNEL_3:
+        /* read the data of channel 3 */
+        idata = ADC_IDATA3(adc_periph);
+        break;
+    default:
+        idata = 0U;
+        break;
+    }
+    return (uint16_t)idata;
+}
+
+/*!
+    \brief      read the last ADC0 and ADC1 conversion result data in sync mode
+    \param[in]  none
+    \param[out] none
+    \retval     the conversion value
+*/
+uint32_t adc_sync_mode_convert_value_read(void)
+{
+    /* return conversion value */
+    return ADC_RDATA(ADC0);
+}
+
+
+/*!
+    \brief      configure ADC analog watchdog single channel 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_channel: the selected ADC channel
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
+    \param[out] none
+    \retval     none
+*/
+void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
+{
+    ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
+    /* analog watchdog channel select */
+    ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
+    ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
+}
+
+/*!
+    \brief      configure ADC analog watchdog group channel 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_channel_group: the channel group use analog watchdog
+                only one parameter can be selected which is shown as below: 
+      \arg        ADC_REGULAR_CHANNEL: regular channel group
+      \arg        ADC_INSERTED_CHANNEL: inserted channel group
+      \arg        ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
+    \param[out] none
+    \retval     none
+*/
+void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
+{
+    ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
+    /* select the group */
+    switch(adc_channel_group){
+    case ADC_REGULAR_CHANNEL:
+        /* regular channel analog watchdog enable */
+        ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
+        break;
+    case ADC_INSERTED_CHANNEL:
+        /* inserted channel analog watchdog enable */
+        ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
+        break;
+    case ADC_REGULAR_INSERTED_CHANNEL:
+        /* regular and inserted channel analog watchdog enable */
+        ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      disable ADC analog watchdog 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_watchdog_disable(uint32_t adc_periph)
+{
+    ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
+}
+
+/*!
+    \brief      configure ADC analog watchdog threshold 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  low_threshold: analog watchdog low threshold, 0..4095
+    \param[in]  high_threshold: analog watchdog high threshold, 0..4095
+    \param[out] none
+    \retval     none
+*/
+void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
+{
+    ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
+    ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
+}
+
+/*!
+    \brief      get the ADC flag bits
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_flag: the adc flag bits
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_FLAG_WDE: analog watchdog event flag
+      \arg        ADC_FLAG_EOC: end of group conversion flag
+      \arg        ADC_FLAG_EOIC: end of inserted group conversion flag
+      \arg        ADC_FLAG_STIC: start flag of inserted channel group
+      \arg        ADC_FLAG_STRC: start flag of regular channel group
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
+{
+    FlagStatus reval = RESET;
+    if(ADC_STAT(adc_periph) & adc_flag){
+        reval = SET;
+    }
+    return reval;
+}
+
+/*!
+    \brief      clear the ADC flag bits
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_flag: the adc flag bits
+                one or more parameters can be selected which are shown as below:
+      \arg        ADC_FLAG_WDE: analog watchdog event flag
+      \arg        ADC_FLAG_EOC: end of group conversion flag
+      \arg        ADC_FLAG_EOIC: end of inserted group conversion flag
+      \arg        ADC_FLAG_STIC: start flag of inserted channel group
+      \arg        ADC_FLAG_STRC: start flag of regular channel group
+    \param[out] none
+    \retval     none
+*/
+void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
+{
+    ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
+}
+
+/*!
+    \brief      get the bit state of ADCx software start conversion
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
+{
+    FlagStatus reval = RESET;
+    if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
+        reval = SET;
+    }
+    return reval;
+}
+
+/*!
+    \brief      get the bit state of ADCx software inserted channel start conversion
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
+{
+    FlagStatus reval = RESET;
+    if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
+        reval = SET;
+    }
+    return reval;
+}
+
+/*!
+    \brief      get the ADC interrupt bits
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_interrupt: the adc interrupt bits
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_INT_FLAG_WDE: analog watchdog interrupt
+      \arg        ADC_INT_FLAG_EOC: end of group conversion interrupt
+      \arg        ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
+{
+    FlagStatus interrupt_flag = RESET;
+    uint32_t state;
+    /* check the interrupt bits */
+    switch(adc_interrupt){
+    case ADC_INT_FLAG_WDE:
+        /* get the ADC analog watchdog interrupt bits */
+        state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
+        if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
+          interrupt_flag = SET;
+        }
+        break;
+    case ADC_INT_FLAG_EOC:
+        /* get the ADC end of group conversion interrupt bits */
+        state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
+          if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
+            interrupt_flag = SET;
+          }
+        break;
+    case ADC_INT_FLAG_EOIC:
+        /* get the ADC end of inserted group conversion interrupt bits */
+        state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
+        if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
+            interrupt_flag = SET;
+        }
+        break;
+    default:
+        break;
+    }
+    return interrupt_flag;
+}
+
+/*!
+    \brief      clear the ADC flag
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_interrupt: the adc status flag
+                one or more parameters can be selected which are shown as below:
+      \arg        ADC_INT_FLAG_WDE: analog watchdog interrupt
+      \arg        ADC_INT_FLAG_EOC: end of group conversion interrupt
+      \arg        ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
+    \param[out] none
+    \retval     none
+*/
+void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
+{
+    ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
+}
+
+/*!
+    \brief      enable ADC interrupt 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_interrupt: the adc interrupt
+                one or more parameters can be selected which are shown as below:
+      \arg        ADC_INT_WDE: analog watchdog interrupt flag
+      \arg        ADC_INT_EOC: end of group conversion interrupt flag
+      \arg        ADC_INT_EOIC: end of inserted group conversion interrupt flag
+    \param[out] none
+    \retval     none
+*/
+void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
+{
+    /* enable ADC analog watchdog interrupt */
+    if(0U != (adc_interrupt & ADC_INT_WDE)){
+        ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
+    }  
+    /* enable ADC end of group conversion interrupt */
+    if(0U != (adc_interrupt & ADC_INT_EOC)){      
+        ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
+    }  
+    /* enable ADC end of inserted group conversion interrupt */
+    if(0U != (adc_interrupt & ADC_INT_EOIC)){      
+        ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
+    }
+}
+
+/*!
+    \brief      disable ADC interrupt 
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  adc_interrupt: the adc interrupt flag
+                one or more parameters can be selected which are shown as below:
+      \arg        ADC_INT_WDE: analog watchdog interrupt flag
+      \arg        ADC_INT_EOC: end of group conversion interrupt flag
+      \arg        ADC_INT_EOIC: end of inserted group conversion interrupt flag
+    \param[out] none
+    \retval     none
+*/
+void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
+{  
+    /* disable ADC analog watchdog interrupt */
+    if(0U != (adc_interrupt & ADC_INT_WDE)){  
+        ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
+    }  
+    /* disable ADC end of group conversion interrupt */
+    if(0U != (adc_interrupt & ADC_INT_EOC)){      
+        ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
+    }  
+    /* disable ADC end of inserted group conversion interrupt */
+    if(0U != (adc_interrupt & ADC_INT_EOIC)){      
+        ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
+    }
+}
+
+/*!
+    \brief      adc resolution config
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  resolution: ADC resolution
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_RESOLUTION_12B: 12-bit ADC resolution
+      \arg        ADC_RESOLUTION_10B: 10-bit ADC resolution
+      \arg        ADC_RESOLUTION_8B: 8-bit ADC resolution
+      \arg        ADC_RESOLUTION_6B: 6-bit ADC resolution
+    \param[out] none
+    \retval     none
+*/
+void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
+{
+    ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_DRES);
+    ADC_OVSCR(adc_periph) |= (uint32_t)resolution;
+}
+
+/*!
+    \brief      adc oversample mode config
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[in]  mode: ADC oversampling mode
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel
+                are done consecutively after a trigger
+      \arg        ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel
+                needs a trigger
+    \param[in]  shift: ADC oversampling shift
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
+      \arg        ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
+    \param[in]  ratio: ADC oversampling ratio
+                only one parameter can be selected which is shown as below:
+      \arg        ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio X2
+      \arg        ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio X4
+      \arg        ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio X8
+      \arg        ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio X16
+      \arg        ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio X32
+      \arg        ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio X64
+      \arg        ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio X128
+      \arg        ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio X256
+    \param[out] none
+    \retval     none
+*/
+void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift,uint8_t ratio)
+{
+    if(mode){
+        ADC_OVSCR(adc_periph) |= (uint32_t)ADC_OVSCR_TOVS;
+    }else{
+        ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_TOVS);
+    }
+    /* config the shift and ratio */
+    ADC_OVSCR(adc_periph) &= ~((uint32_t)(ADC_OVSCR_OVSR | ADC_OVSCR_OVSS));
+    ADC_OVSCR(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio);
+}
+
+/*!
+    \brief      enable ADC oversample mode
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_oversample_mode_enable(uint32_t adc_periph)
+{
+    ADC_OVSCR(adc_periph) |= ADC_OVSCR_OVSEN;
+}
+
+/*!
+    \brief      disable ADC oversample mode
+    \param[in]  adc_periph: ADCx, x=0,1
+    \param[out] none
+    \retval     none
+*/
+void adc_oversample_mode_disable(uint32_t adc_periph)
+{
+    ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_OVSEN);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c
new file mode 100644
index 0000000000..e3b01e4c66
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c
@@ -0,0 +1,292 @@
+/*!
+    \file    gd32vf103_bkp.c
+    \brief   BKP driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_bkp.h"
+
+/* BKP register bits offset */
+#define BKP_TAMPER_BITS_OFFSET          ((uint32_t)8U)
+
+/*!
+    \brief      reset BKP registers
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_deinit(void)
+{
+    /* reset BKP domain register*/
+    rcu_bkp_reset_enable();
+    rcu_bkp_reset_disable();
+}
+
+/*!
+    \brief      write BKP data register
+    \param[in]  register_number: refer to bkp_data_register_enum
+                only one parameter can be selected which is shown as below:
+      \arg        BKP_DATA_x(x = 0..41): bkp data register number x
+    \param[in]  data: the data to be write in BKP data register
+    \param[out] none
+    \retval     none
+*/
+void bkp_data_write(bkp_data_register_enum register_number, uint16_t data)
+{
+    if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
+        BKP_DATA10_41(register_number - 1U) = data;
+    }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
+        BKP_DATA0_9(register_number - 1U) = data;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      read BKP data register
+    \param[in]  register_number: refer to bkp_data_register_enum
+                only one parameter can be selected which is shown as below:
+      \arg        BKP_DATA_x(x = 0..41): bkp data register number x
+    \param[out] none
+    \retval     data of BKP data register
+*/
+uint16_t bkp_data_read(bkp_data_register_enum register_number)
+{
+    uint16_t data = 0U;
+    
+    /* get the data from the BKP data register */
+    if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
+        data = BKP_DATA10_41(register_number - 1U);
+    }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
+        data = BKP_DATA0_9(register_number - 1U);
+    }else{
+        /* illegal parameters */
+    }
+    return data;
+}
+
+/*!
+    \brief      enable RTC clock calibration output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_calibration_output_enable(void)
+{
+    BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
+}
+
+/*!
+    \brief      disable RTC clock calibration output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_calibration_output_disable(void)
+{
+    BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
+}
+
+/*!
+    \brief      enable RTC alarm or second signal output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_signal_output_enable(void)
+{
+    BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
+}
+
+/*!
+    \brief      disable RTC alarm or second signal output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_signal_output_disable(void)
+{
+    BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
+}
+
+/*!
+    \brief      select RTC output
+    \param[in]  outputsel: RTC output selection
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output
+      \arg        RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_output_select(uint16_t outputsel)
+{
+    uint16_t ctl = 0U;
+    
+    /* configure BKP_OCTL_ROSEL with outputsel */
+    ctl = BKP_OCTL;
+    ctl &= (uint16_t)~BKP_OCTL_ROSEL;
+    ctl |= outputsel;
+    BKP_OCTL = ctl;
+}
+
+/*!
+    \brief      set RTC clock calibration value 
+    \param[in]  value: RTC clock calibration value
+      \arg        0x00 - 0x7F
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_calibration_value_set(uint8_t value)
+{
+    uint16_t ctl;
+    
+    /* configure BKP_OCTL_RCCV with value */
+    ctl = BKP_OCTL;
+    ctl &= (uint16_t)~BKP_OCTL_RCCV;
+    ctl |= (uint16_t)OCTL_RCCV(value);
+    BKP_OCTL = ctl;
+}
+
+/*!
+    \brief      enable tamper detection
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_tamper_detection_enable(void)
+{
+    BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
+}
+
+/*!
+    \brief      disable tamper detection
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_tamper_detection_disable(void)
+{
+    BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
+}
+
+/*!
+    \brief      set tamper pin active level
+    \param[in]  level: tamper active level
+                only one parameter can be selected which is shown as below:
+      \arg        TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high
+      \arg        TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low
+    \param[out] none
+    \retval     none
+*/
+void bkp_tamper_active_level_set(uint16_t level)
+{
+    uint16_t ctl = 0U;
+    
+    /* configure BKP_TPCTL_TPAL with level */
+    ctl = BKP_TPCTL;
+    ctl &= (uint16_t)~BKP_TPCTL_TPAL;
+    ctl |= level;
+    BKP_TPCTL = ctl;
+}
+
+/*!
+    \brief      enable tamper interrupt
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_interrupt_enable(void)
+{
+    BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
+}
+
+/*!
+    \brief      disable tamper interrupt
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_interrupt_disable(void)
+{
+    BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
+}
+
+/*!
+    \brief      get tamper flag state
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus bkp_flag_get(void)
+{
+    if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear tamper flag state
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_flag_clear(void)
+{
+    BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
+}
+
+/*!
+    \brief      get tamper interrupt flag state
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus bkp_interrupt_flag_get(void)
+{
+    if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear tamper interrupt flag state
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_interrupt_flag_clear(void)
+{
+    BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_can.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_can.c
new file mode 100644
index 0000000000..b90131ab60
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_can.c
@@ -0,0 +1,989 @@
+/*!
+    \file  gd32vf103_can.c
+    \brief CAN driver
+    
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_can.h"
+
+#define CAN_ERROR_HANDLE(s)     do{}while(1)
+
+/*!
+    \brief      deinitialize CAN 
+    \param[in]  can_periph
+    \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void can_deinit(uint32_t can_periph)
+{
+    if(CAN0 == can_periph){
+        rcu_periph_reset_enable(RCU_CAN0RST);
+        rcu_periph_reset_disable(RCU_CAN0RST);
+    }else{
+        rcu_periph_reset_enable(RCU_CAN1RST);
+        rcu_periph_reset_disable(RCU_CAN1RST);
+    }
+}
+
+/*!
+    \brief      initialize CAN parameter struct with a default value
+    \param[in]  type: the type of CAN parameter struct  
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_INIT_STRUCT: the CAN initial struct
+      \arg        CAN_FILTER_STRUCT: the CAN filter struct
+      \arg        CAN_TX_MESSAGE_STRUCT: the CAN TX message struct
+      \arg        CAN_RX_MESSAGE_STRUCT: the CAN RX message struct
+    \param[in]  p_struct: the pointer of the specific struct 
+    \param[out] none
+    \retval     none
+*/
+void can_struct_para_init(can_struct_type_enum type, void* p_struct)
+{
+    uint8_t i;
+    
+    /* get type of the struct */
+    switch(type){
+        /* used for can_init() */
+        case CAN_INIT_STRUCT:
+            ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE;
+            ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE;
+            ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE;
+            ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; 
+            ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; 
+            ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ;
+            ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ;
+            ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ;
+            ((can_parameter_struct*)p_struct)->time_triggered = DISABLE;
+            ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE;
+            ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE;
+            
+            break;
+        /* used for can_filter_init() */
+        case CAN_FILTER_STRUCT:
+            ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT;
+            ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE;
+            ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0;
+            ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U;
+            ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U;
+            ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U;
+            ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U;
+            ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK;
+            ((can_filter_parameter_struct*)p_struct)->filter_number = 0U;
+
+            break;
+        /* used for can_message_transmit() */
+        case CAN_TX_MESSAGE_STRUCT:
+            for(i = 0U; i < 8U; i++){
+                ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U;
+            }
+            
+            ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u;
+            ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U;
+            ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD;
+            ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA;
+            ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U;
+            
+            break;
+        /* used for can_message_receive() */
+        case CAN_RX_MESSAGE_STRUCT:
+            for(i = 0U; i < 8U; i++){
+                ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U;
+            }
+            
+            ((can_receive_message_struct*)p_struct)->rx_dlen = 0U;
+            ((can_receive_message_struct*)p_struct)->rx_efid = 0U;
+            ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD;
+            ((can_receive_message_struct*)p_struct)->rx_fi = 0U;
+            ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA;
+            ((can_receive_message_struct*)p_struct)->rx_sfid = 0U;
+            
+            break;
+
+        default:
+            CAN_ERROR_HANDLE("parameter is invalid \r\n");
+    }
+}
+
+/*!
+    \brief      initialize CAN
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  can_parameter_init: parameters for CAN initializtion
+      \arg        working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE
+      \arg        resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4)
+      \arg        time_segment_1: CAN_BT_BS1_xTQ(1..16)
+      \arg        time_segment_2: CAN_BT_BS2_xTQ(1..8)
+      \arg        time_triggered: ENABLE or DISABLE
+      \arg        auto_bus_off_recovery: ENABLE or DISABLE
+      \arg        auto_wake_up: ENABLE or DISABLE
+      \arg        auto_retrans: ENABLE or DISABLE
+      \arg        rec_fifo_overwrite: ENABLE or DISABLE
+      \arg        trans_fifo_order: ENABLE or DISABLE
+      \arg        prescaler: 0x0000 - 0x03FF
+    \param[out] none
+    \retval     ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init)
+{
+    uint32_t timeout = CAN_TIMEOUT;
+    ErrStatus flag = ERROR;
+    
+    /* disable sleep mode */
+    CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
+    /* enable initialize mode */
+    CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
+    /* wait ACK */
+    while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
+        timeout--;
+    }
+    /* check initialize working success */
+    if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
+        flag = ERROR;
+    }else{
+        /* set the bit timing register */
+        CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
+                              BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
+                              BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
+                              BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
+                              BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
+
+        /* time trigger communication mode */
+        if(ENABLE == can_parameter_init->time_triggered){
+            CAN_CTL(can_periph) |= CAN_CTL_TTC;
+        }else{
+            CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
+        }
+        /* automatic bus-off managment */
+        if(ENABLE == can_parameter_init->auto_bus_off_recovery){
+            CAN_CTL(can_periph) |= CAN_CTL_ABOR;
+        }else{
+            CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
+        }
+        /* automatic wakeup mode */
+        if(ENABLE == can_parameter_init->auto_wake_up){
+            CAN_CTL(can_periph) |= CAN_CTL_AWU;
+        }else{
+            CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
+        }
+        /* automatic retransmission mode disable*/
+        if(ENABLE == can_parameter_init->auto_retrans){
+            CAN_CTL(can_periph) |= CAN_CTL_ARD;
+        }else{
+            CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
+        }
+        /* receive fifo overwrite mode */        
+        if(ENABLE == can_parameter_init->rec_fifo_overwrite){
+            CAN_CTL(can_periph) |= CAN_CTL_RFOD;
+        }else{
+            CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
+        } 
+        /* transmit fifo order */
+        if(ENABLE == can_parameter_init->trans_fifo_order){
+            CAN_CTL(can_periph) |= CAN_CTL_TFO;
+        }else{
+            CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
+        }  
+        /* disable initialize mode */
+        CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
+        timeout = CAN_TIMEOUT;
+        /* wait the ACK */
+        while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
+            timeout--;
+        }
+        /* check exit initialize mode */
+        if(0U != timeout){
+            flag = SUCCESS;
+        }
+    }
+    CAN_TMI0(can_periph) = 0x0;
+    CAN_TMI1(can_periph) = 0x0;
+    CAN_TMI2(can_periph) = 0x0;
+    CAN_TMP0(can_periph) = 0x0;
+    CAN_TMP1(can_periph) = 0x0;
+    CAN_TMP2(can_periph) = 0x0;
+    CAN_TMDATA00(can_periph) = 0x0;
+    CAN_TMDATA01(can_periph) = 0x0;
+    CAN_TMDATA02(can_periph) = 0x0;
+    CAN_TMDATA10(can_periph) = 0x0;
+    CAN_TMDATA11(can_periph) = 0x0;
+    CAN_TMDATA12(can_periph) = 0x0;
+
+    return flag;
+}
+
+/*!
+    \brief      initialize CAN filter 
+    \param[in]  can_filter_parameter_init: struct for CAN filter initialization
+      \arg        filter_list_high: 0x0000 - 0xFFFF
+      \arg        filter_list_low: 0x0000 - 0xFFFF
+      \arg        filter_mask_high: 0x0000 - 0xFFFF
+      \arg        filter_mask_low: 0x0000 - 0xFFFF
+      \arg        filter_fifo_number: CAN_FIFO0, CAN_FIFO1 
+      \arg        filter_number: 0 - 27
+      \arg        filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST
+      \arg        filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT 
+      \arg        filter_enable: ENABLE or DISABLE
+    \param[out] none
+    \retval     none
+*/
+void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
+{
+    uint32_t val = 0U;
+    
+    val = ((uint32_t)1) << (can_filter_parameter_init->filter_number);
+    /* filter lock disable */
+    CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
+    /* disable filter */
+    CAN_FW(CAN0) &= ~(uint32_t)val;
+    
+    /* filter 16 bits */
+    if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){
+        /* set filter 16 bits */
+        CAN_FSCFG(CAN0) &= ~(uint32_t)val;
+        /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */
+        CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
+                                FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \
+                                FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
+        /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */
+        CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
+                                FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \
+                                FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
+    }
+    /* filter 32 bits */
+    if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){
+        /* set filter 32 bits */
+        CAN_FSCFG(CAN0) |= (uint32_t)val;
+        /* 32 bits list or first 32 bits list */
+        CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
+                                FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) |
+                                FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
+        /* 32 bits mask or second 32 bits list */
+        CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
+                                FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) |
+                                FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
+    }
+    
+    /* filter mode */
+    if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){
+        /* mask mode */
+        CAN_FMCFG(CAN0) &= ~(uint32_t)val;
+    }else{
+        /* list mode */
+        CAN_FMCFG(CAN0) |= (uint32_t)val;
+    }
+    
+    /* filter FIFO */
+    if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){
+        /* FIFO0 */
+        CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
+    }else{
+        /* FIFO1 */
+        CAN_FAFIFO(CAN0) |= (uint32_t)val;
+    }
+    
+    /* filter working */
+    if(ENABLE == can_filter_parameter_init->filter_enable){
+        
+        CAN_FW(CAN0) |= (uint32_t)val;
+    }
+    
+    /* filter lock enable */
+    CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
+}
+
+/*!
+    \brief      set CAN1 fliter start bank number
+    \param[in]  start_bank: CAN1 start bank number
+                only one parameter can be selected which is shown as below:
+      \arg        (1..27)
+    \param[out] none
+    \retval     none
+*/
+void can1_filter_start_bank(uint8_t start_bank)
+{
+    /* filter lock disable */
+    CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
+    /* set CAN1 filter start number */
+    CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F;
+    CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank);
+    /* filter lock enaable */
+    CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
+}
+
+/*!
+    \brief      enable CAN debug freeze
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void can_debug_freeze_enable(uint32_t can_periph)
+{
+    /* set DFZ bit */
+    CAN_CTL(can_periph) |= CAN_CTL_DFZ;
+    if(CAN0 == can_periph){
+        dbg_periph_enable(DBG_CAN0_HOLD);
+    }else{
+        dbg_periph_enable(DBG_CAN1_HOLD);
+    }
+}
+
+/*!
+    \brief      disable CAN debug freeze
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void can_debug_freeze_disable(uint32_t can_periph)
+{
+    /* set DFZ bit */
+    CAN_CTL(can_periph) &= ~CAN_CTL_DFZ;
+    if(CAN0 == can_periph){
+        dbg_periph_disable(DBG_CAN0_HOLD);
+    }else{
+        dbg_periph_disable(DBG_CAN1_HOLD);
+    }
+}
+
+/*!
+    \brief      enable CAN time trigger mode
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void can_time_trigger_mode_enable(uint32_t can_periph)
+{
+    uint8_t mailbox_number;
+    
+    /* enable the tcc mode */
+    CAN_CTL(can_periph) |= CAN_CTL_TTC;
+    /* enable time stamp */
+    for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){
+        CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN;
+    }
+}
+
+/*!
+    \brief      disable CAN time trigger mode
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void can_time_trigger_mode_disable(uint32_t can_periph)
+{
+    uint8_t mailbox_number; 
+    
+    /* disable the TCC mode */
+    CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
+    /* reset TSEN bits */
+    for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){
+        CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN;
+    }
+}
+
+/*!
+    \brief       transmit CAN message
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  transmit_message: struct for CAN transmit message
+      \arg        tx_sfid: 0x00000000 - 0x000007FF
+      \arg        tx_efid: 0x00000000 - 0x1FFFFFFF
+      \arg        tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
+      \arg        tx_ft: CAN_FT_DATA, CAN_FT_REMOTE
+      \arg        tx_dlenc: 1 - 7
+      \arg        tx_data[]: 0x00 - 0xFF
+    \param[out] none
+    \retval     mailbox_number
+*/
+uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message)
+{
+    uint8_t mailbox_number = CAN_MAILBOX0;
+
+    /* select one empty mailbox */
+    if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){
+        mailbox_number = CAN_MAILBOX0;
+    }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){
+        mailbox_number = CAN_MAILBOX1;
+    }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){
+        mailbox_number = CAN_MAILBOX2;
+    }else{
+        mailbox_number = CAN_NOMAILBOX;
+    }
+    /* return no mailbox empty */
+    if(CAN_NOMAILBOX == mailbox_number){
+        return CAN_NOMAILBOX;
+    }
+    
+    CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN;
+    if(CAN_FF_STANDARD == transmit_message->tx_ff){
+        /* set transmit mailbox standard identifier */
+        CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \
+                                                transmit_message->tx_ft);
+    }else{
+        /* set transmit mailbox extended identifier */
+        CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \
+                                                transmit_message->tx_ff | \
+                                                transmit_message->tx_ft);
+    }
+    /* set the data length */
+    CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC;
+    CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
+    /* set the data */
+    CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
+                                              TMDATA0_DB2(transmit_message->tx_data[2]) | \
+                                              TMDATA0_DB1(transmit_message->tx_data[1]) | \
+                                              TMDATA0_DB0(transmit_message->tx_data[0]);
+    CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \
+                                              TMDATA1_DB6(transmit_message->tx_data[6]) | \
+                                              TMDATA1_DB5(transmit_message->tx_data[5]) | \
+                                              TMDATA1_DB4(transmit_message->tx_data[4]);
+    /* enable transmission */
+    CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN;
+
+    return mailbox_number;
+}
+
+/*!
+    \brief      get CAN transmit state 
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  mailbox_number
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_MAILBOX(x=0,1,2)
+    \param[out] none
+    \retval     can_transmit_state_enum
+*/
+can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number)
+{
+    can_transmit_state_enum state = CAN_TRANSMIT_FAILED;
+    uint32_t val = 0U;
+    
+    /* check selected mailbox state */    
+    switch(mailbox_number){
+    /* mailbox0 */
+    case CAN_MAILBOX0:
+        val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0);
+        break;
+    /* mailbox1 */
+    case CAN_MAILBOX1:
+        val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1);
+        break;
+    /* mailbox2 */
+    case CAN_MAILBOX2:
+        val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2);
+        break;
+    default:
+        val = CAN_TRANSMIT_FAILED;
+        break;
+    }
+    
+    switch(val){
+        /* transmit pending */
+    case (CAN_STATE_PENDING): 
+        state = CAN_TRANSMIT_PENDING;
+        break;
+        /* mailbox0 transmit succeeded */
+    case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
+        state = CAN_TRANSMIT_OK;
+        break;
+        /* mailbox1 transmit succeeded */
+    case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1):
+        state = CAN_TRANSMIT_OK;
+        break;
+        /* mailbox2 transmit succeeded */
+    case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2):
+        state = CAN_TRANSMIT_OK;
+        break;
+        /* transmit failed */
+    default: 
+        state = CAN_TRANSMIT_FAILED;
+        break;
+    }
+    return state;
+}
+
+/*!
+    \brief      stop CAN transmission
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  mailbox_number
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_MAILBOXx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
+{
+    if(CAN_MAILBOX0 == mailbox_number){
+        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
+        while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){
+        }
+    }else if(CAN_MAILBOX1 == mailbox_number){
+        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
+        while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){
+        }
+    }else if(CAN_MAILBOX2 == mailbox_number){
+        CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
+        while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){
+        }
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      CAN receive message
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  fifo_number
+      \arg        CAN_FIFOx(x=0,1)
+    \param[out] receive_message: struct for CAN receive message
+      \arg        rx_sfid: 0x00000000 - 0x000007FF
+      \arg        rx_efid: 0x00000000 - 0x1FFFFFFF
+      \arg        rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED
+      \arg        rx_ft: CAN_FT_DATA, CAN_FT_REMOTE
+      \arg        rx_dlenc: 1 - 7
+      \arg        rx_data[]: 0x00 - 0xFF
+      \arg        rx_fi: 0 - 27
+    \retval     none
+*/
+void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message)
+{
+    /* get the frame format */
+    receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number));
+    if(CAN_FF_STANDARD == receive_message->rx_ff){
+        /* get standard identifier */
+        receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number)));
+    }else{
+        /* get extended identifier */
+        receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number)));
+    }
+    
+    /* get frame type */
+    receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number));        
+    /* filtering index */
+    receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));
+    /* get recevie data length */
+    receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
+    
+    /* receive data */
+    receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number)));
+    receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number)));
+    receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number)));
+    receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number)));
+    receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number)));
+    receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number)));
+    receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number)));
+    receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
+    
+    /* release FIFO */
+    if(CAN_FIFO0 == fifo_number){
+        CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
+    }else{
+        CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
+    }
+}
+
+/*!
+    \brief      release FIFO0
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  fifo_number
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_FIFOx(x=0,1)
+    \param[out] none
+    \retval     none
+*/
+void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
+{
+    if(CAN_FIFO0 == fifo_number){
+        CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
+    }else if(CAN_FIFO1 == fifo_number){
+        CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
+    }else{
+        /* illegal parameters */
+        CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n");
+    }
+}
+
+/*!
+    \brief      CAN receive message length
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  fifo_number
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_FIFOx(x=0,1) 
+    \param[out] none
+    \retval     message length
+*/
+uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
+{
+    uint8_t val = 0U;
+    
+    if(CAN_FIFO0 == fifo_number){
+        /* FIFO0 */
+        val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK);
+    }else if(CAN_FIFO1 == fifo_number){
+        /* FIFO1 */
+        val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK);
+    }else{
+        /* illegal parameters */
+    }
+    return val;
+}
+
+/*!
+    \brief      set CAN working mode
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  can_working_mode
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_MODE_INITIALIZE
+      \arg        CAN_MODE_NORMAL
+      \arg        CAN_MODE_SLEEP
+    \param[out] none
+    \retval     ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
+{
+    ErrStatus flag = ERROR;
+    /* timeout for IWS or also for SLPWS bits */
+    uint32_t timeout = CAN_TIMEOUT; 
+    
+    if(CAN_MODE_INITIALIZE == working_mode){
+        /* disable sleep mode */
+        CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
+        /* set initialize mode */
+        CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD;
+        /* wait the acknowledge */
+        while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
+            timeout--;
+        }
+        if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
+            flag = ERROR;
+        }else{
+            flag = SUCCESS;
+        }
+    }else if(CAN_MODE_NORMAL == working_mode){
+        /* enter normal mode */
+        CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
+        /* wait the acknowledge */
+        while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){
+            timeout--;
+        }
+        if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){
+            flag = ERROR;
+        }else{
+            flag = SUCCESS;
+        }
+    }else if(CAN_MODE_SLEEP == working_mode){
+        /* disable initialize mode */
+        CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
+        /* set sleep mode */
+        CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD;
+        /* wait the acknowledge */
+        while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){
+            timeout--;
+        }
+        if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
+            flag = ERROR;
+        }else{
+            flag = SUCCESS;
+        }
+    }else{
+        flag = ERROR;
+    }
+    return flag;
+}
+
+/*!
+    \brief      wake up CAN
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus can_wakeup(uint32_t can_periph)
+{
+    ErrStatus flag = ERROR;
+    uint32_t timeout = CAN_TIMEOUT;
+    
+    /* wakeup */
+    CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
+    
+    while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){
+        timeout--;
+    }
+    /* check state */
+    if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
+        flag = ERROR;
+    }else{
+        flag = SUCCESS;
+    }
+    return flag;
+}
+
+/*!
+    \brief      get CAN error type
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     can_error_enum
+      \arg        CAN_ERROR_NONE: no error
+      \arg        CAN_ERROR_FILL: fill error
+      \arg        CAN_ERROR_FORMATE: format error
+      \arg        CAN_ERROR_ACK: ACK error
+      \arg        CAN_ERROR_BITRECESSIVE: bit recessive
+      \arg        CAN_ERROR_BITDOMINANTER: bit dominant error
+      \arg        CAN_ERROR_CRC: CRC error
+      \arg        CAN_ERROR_SOFTWARECFG: software configure
+*/
+can_error_enum can_error_get(uint32_t can_periph)
+{
+    can_error_enum error;
+    error = CAN_ERROR_NONE;
+    
+    /* get error type */
+    error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph)));
+    return error;
+}
+
+/*!
+    \brief      get CAN receive error number
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     error number
+*/
+uint8_t can_receive_error_number_get(uint32_t can_periph)
+{
+    uint8_t val;
+    
+    /* get error count */
+    val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph)));
+    return val;
+}
+
+/*!
+    \brief      get CAN transmit error number
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[out] none
+    \retval     error number
+*/
+uint8_t can_transmit_error_number_get(uint32_t can_periph)
+{
+    uint8_t val;
+    
+    val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph)));
+    return val;
+}
+
+/*!
+    \brief      enable CAN interrupt 
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  interrupt 
+                one or more parameters can be selected which are shown as below:
+      \arg        CAN_INT_TME: transmit mailbox empty interrupt enable
+      \arg        CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
+      \arg        CAN_INT_RFF0: receive FIFO0 full interrupt enable
+      \arg        CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
+      \arg        CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
+      \arg        CAN_INT_RFF1: receive FIFO1 full interrupt enable
+      \arg        CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
+      \arg        CAN_INT_WERR: warning error interrupt enable
+      \arg        CAN_INT_PERR: passive error interrupt enable
+      \arg        CAN_INT_BO: bus-off interrupt enable
+      \arg        CAN_INT_ERRN: error number interrupt enable
+      \arg        CAN_INT_ERR: error interrupt enable
+      \arg        CAN_INT_WU: wakeup interrupt enable
+      \arg        CAN_INT_SLPW: sleep working interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
+{
+    CAN_INTEN(can_periph) |= interrupt;
+}
+
+/*!
+    \brief      disable CAN interrupt 
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  interrupt
+                one or more parameters can be selected which are shown as below:
+      \arg        CAN_INT_TME: transmit mailbox empty interrupt enable
+      \arg        CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
+      \arg        CAN_INT_RFF0: receive FIFO0 full interrupt enable
+      \arg        CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
+      \arg        CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
+      \arg        CAN_INT_RFF1: receive FIFO1 full interrupt enable
+      \arg        CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
+      \arg        CAN_INT_WERR: warning error interrupt enable
+      \arg        CAN_INT_PERR: passive error interrupt enable
+      \arg        CAN_INT_BO: bus-off interrupt enable
+      \arg        CAN_INT_ERRN: error number interrupt enable
+      \arg        CAN_INT_ERR: error interrupt enable
+      \arg        CAN_INT_WU: wakeup interrupt enable
+      \arg        CAN_INT_SLPW: sleep working interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
+{
+    CAN_INTEN(can_periph) &= ~interrupt;
+}
+
+/*!
+    \brief      get CAN flag state
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  flag: CAN flags, refer to can_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_FLAG_MTE2: mailbox 2 transmit error
+      \arg        CAN_FLAG_MTE1: mailbox 1 transmit error
+      \arg        CAN_FLAG_MTE0: mailbox 0 transmit error
+      \arg        CAN_FLAG_MTF2: mailbox 2 transmit finished
+      \arg        CAN_FLAG_MTF1: mailbox 1 transmit finished
+      \arg        CAN_FLAG_MTF0: mailbox 0 transmit finished
+      \arg        CAN_FLAG_RFO0: receive FIFO0 overfull
+      \arg        CAN_FLAG_RFF0: receive FIFO0 full
+      \arg        CAN_FLAG_RFO1: receive FIFO1 overfull
+      \arg        CAN_FLAG_RFF1: receive FIFO1 full
+      \arg        CAN_FLAG_BOERR: bus-off error
+      \arg        CAN_FLAG_PERR: passive error
+      \arg        CAN_FLAG_WERR: warning error
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
+{  
+    /* get flag and interrupt enable state */
+    if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear CAN flag state
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  flag: CAN flags, refer to can_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_FLAG_MTE2: mailbox 2 transmit error
+      \arg        CAN_FLAG_MTE1: mailbox 1 transmit error
+      \arg        CAN_FLAG_MTE0: mailbox 0 transmit error
+      \arg        CAN_FLAG_MTF2: mailbox 2 transmit finished
+      \arg        CAN_FLAG_MTF1: mailbox 1 transmit finished
+      \arg        CAN_FLAG_MTF0: mailbox 0 transmit finished
+      \arg        CAN_FLAG_RFO0: receive FIFO0 overfull
+      \arg        CAN_FLAG_RFF0: receive FIFO0 full
+      \arg        CAN_FLAG_RFO1: receive FIFO1 overfull
+      \arg        CAN_FLAG_RFF1: receive FIFO1 full
+      \arg		  CAN_FLAG_BOERR: bus-off error
+	  \arg		  CAN_FLAG_PERR: passive error
+	  \arg		  CAN_FLAG_WERR: warning error
+    \param[out] none
+    \retval     none
+*/
+void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
+{
+    CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag));
+}
+
+/*!
+    \brief      get CAN interrupt flag state
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  flag: CAN interrupt flags, refer to can_interrupt_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
+      \arg        CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
+      \arg        CAN_INT_FLAG_ERRIF: error interrupt flag
+      \arg        CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
+      \arg        CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
+      \arg        CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
+      \arg        CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
+      \arg        CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
+      \arg        CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
+      \arg        CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag)
+{  
+	uint32_t ret1 = RESET;
+	uint32_t ret2 = RESET;
+    
+    /* get the staus of interrupt flag */
+    ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag));
+    /* get the staus of interrupt enale bit */
+    ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag));
+    if(ret1 && ret2){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear CAN interrupt flag state
+    \param[in]  can_periph
+      \arg        CANx(x=0,1)
+    \param[in]  flag: CAN interrupt flags, refer to can_interrupt_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering
+      \arg        CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode
+      \arg        CAN_INT_FLAG_ERRIF: error interrupt flag
+      \arg        CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag
+      \arg        CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag
+      \arg        CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag
+      \arg        CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag
+      \arg        CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag
+      \arg        CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag
+      \arg        CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag
+	  \arg		  CAN_FLAG_BOERR: bus-off error
+	  \arg		  CAN_FLAG_PERR: passive error
+	  \arg		  CAN_FLAG_WERR: warning error
+    \param[out] none
+    \retval     none
+*/
+void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag)
+{
+    CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag));
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c
new file mode 100644
index 0000000000..5753485a58
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c
@@ -0,0 +1,127 @@
+/*!
+    \file  gd32vf103_crc.c
+    \brief CRC driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_crc.h"
+
+#define CRC_DATA_RESET_VALUE      ((uint32_t)0xFFFFFFFFU)
+#define CRC_FDATA_RESET_VALUE     ((uint32_t)0x00000000U)
+
+/*!
+    \brief      deinit CRC calculation unit
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void crc_deinit(void)
+{
+    CRC_DATA = CRC_DATA_RESET_VALUE;
+    CRC_FDATA = CRC_FDATA_RESET_VALUE;
+    CRC_CTL = (uint32_t)CRC_CTL_RST;
+}
+
+/*!
+    \brief      reset data register(CRC_DATA) to the value of 0xFFFFFFFF
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void crc_data_register_reset(void)
+{
+    CRC_CTL |= (uint32_t)CRC_CTL_RST;
+}
+
+/*!
+    \brief      read the value of the data register
+    \param[in]  none
+    \param[out] none
+    \retval     32-bit value of the data register
+*/
+uint32_t crc_data_register_read(void)
+{
+    uint32_t data;
+    data = CRC_DATA;
+    return (data);
+}
+
+/*!
+    \brief      read the value of the free data register
+    \param[in]  none
+    \param[out] none
+    \retval     8-bit value of the free data register
+*/
+uint8_t crc_free_data_register_read(void)
+{
+    uint8_t fdata;
+    fdata = (uint8_t)CRC_FDATA;
+    return (fdata);
+}
+
+/*!
+    \brief      write data to the free data register
+    \param[in]  free_data: specified 8-bit data
+    \param[out] none
+    \retval     none
+*/
+void crc_free_data_register_write(uint8_t free_data)
+{
+    CRC_FDATA = (uint32_t)free_data;
+}
+
+/*!
+    \brief      calculate the CRC value of a 32-bit data
+    \param[in]  sdata: specified 32-bit data
+    \param[out] none
+    \retval     32-bit value calculated by CRC
+*/
+uint32_t crc_single_data_calculate(uint32_t sdata)
+{
+    CRC_DATA = sdata;
+    return (CRC_DATA);
+}
+
+/*!
+    \brief      calculate the CRC value of an array of 32-bit values
+    \param[in]  array: pointer to an array of 32-bit values
+    \param[in]  size: size of the array
+    \param[out] none
+    \retval     32-bit value calculated by CRC
+*/
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
+{
+    uint32_t index;
+    for(index = 0U; index < size; index++){
+        CRC_DATA = array[index];
+    }
+    return (CRC_DATA);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c
new file mode 100644
index 0000000000..4ec51bf960
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c
@@ -0,0 +1,537 @@
+/*!
+    \file    gd32vf103_dac.c
+    \brief   DAC driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_dac.h"
+
+/* DAC register bit offset */
+#define DAC1_REG_OFFSET           ((uint32_t)16U)
+#define DH_12BIT_OFFSET           ((uint32_t)16U)
+#define DH_8BIT_OFFSET            ((uint32_t)8U)
+
+/*!
+    \brief      deinitialize DAC
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_deinit(void)
+{
+    rcu_periph_reset_enable(RCU_DACRST);
+    rcu_periph_reset_disable(RCU_DACRST);
+}
+
+/*!
+    \brief      enable DAC
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_enable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_CTL |= DAC_CTL_DEN0;
+    }else{
+        DAC_CTL |= DAC_CTL_DEN1;
+    }
+} 
+
+/*!
+    \brief      disable DAC
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_disable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_CTL &= ~DAC_CTL_DEN0;
+    }else{
+        DAC_CTL &= ~DAC_CTL_DEN1;
+    }
+}
+
+/*!
+    \brief      enable DAC DMA function
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_dma_enable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_CTL |= DAC_CTL_DDMAEN0;
+    }else{
+        DAC_CTL |= DAC_CTL_DDMAEN1;
+    }
+}
+
+/*!
+    \brief      disable DAC DMA function
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_dma_disable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_CTL &= ~DAC_CTL_DDMAEN0;
+    }else{
+        DAC_CTL &= ~DAC_CTL_DDMAEN1;
+    }
+}
+
+/*!
+    \brief      enable DAC output buffer
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_output_buffer_enable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_CTL &= ~DAC_CTL_DBOFF0;
+    }else{
+        DAC_CTL &= ~DAC_CTL_DBOFF1;
+    }
+}
+
+/*!
+    \brief      disable DAC output buffer
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_output_buffer_disable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_CTL |= DAC_CTL_DBOFF0;
+    }else{
+        DAC_CTL |= DAC_CTL_DBOFF1;
+    }
+}
+
+/*!
+    \brief      get DAC output value
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     DAC output data
+*/
+uint16_t dac_output_value_get(uint32_t dac_periph)
+{
+    uint16_t data = 0U;
+    if(DAC0 == dac_periph){
+        /* store the DAC0 output value */
+        data = (uint16_t)DAC0_DO;
+    }else{
+        /* store the DAC1 output value */
+        data = (uint16_t)DAC1_DO;
+    }
+    return data;
+}
+
+/*!
+    \brief      set the DAC specified data holding register value
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[in]  dac_align: data alignment
+                only one parameter can be selected which is shown as below:
+      \arg        DAC_ALIGN_8B_R: data right 8 bit alignment
+      \arg        DAC_ALIGN_12B_R: data right 12 bit alignment
+      \arg        DAC_ALIGN_12B_L: data left 12 bit alignment
+    \param[in]  data: data to be loaded
+    \param[out] none
+    \retval     none
+*/
+void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
+{
+    if(DAC0 == dac_periph){
+        switch(dac_align){
+        /* data right 12 bit alignment */
+        case DAC_ALIGN_12B_R:
+            DAC0_R12DH = data;
+            break;
+        /* data left 12 bit alignment */
+        case DAC_ALIGN_12B_L:
+            DAC0_L12DH = data;
+            break;
+        /* data right 8 bit alignment */
+        case DAC_ALIGN_8B_R:
+            DAC0_R8DH = data;
+            break;
+        default:
+            break;
+        }
+    }else{
+        switch(dac_align){
+        /* data right 12 bit alignment */
+        case DAC_ALIGN_12B_R:
+            DAC1_R12DH = data;
+            break;
+        /* data left 12 bit alignment */
+        case DAC_ALIGN_12B_L:
+            DAC1_L12DH = data;
+            break;
+        /* data right 8 bit alignment */
+        case DAC_ALIGN_8B_R:
+            DAC1_R8DH = data;
+            break;
+        default:
+            break;
+        }
+    }
+}
+
+/*!
+    \brief      enable DAC trigger
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_trigger_enable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_CTL |= DAC_CTL_DTEN0;
+    }else{
+        DAC_CTL |= DAC_CTL_DTEN1;
+    }
+}
+
+/*!
+    \brief      disable DAC trigger
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_trigger_disable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_CTL &= ~DAC_CTL_DTEN0;
+    }else{
+        DAC_CTL &= ~DAC_CTL_DTEN1;
+    }
+}
+
+/*!
+    \brief      set DAC trigger source
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[in]  triggersource: external triggers of DAC
+                only one parameter can be selected which is shown as below:
+      \arg        DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
+      \arg        DAC_TRIGGER_T2_TRGO: TIMER2 TRGO
+      \arg        DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
+      \arg        DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
+      \arg        DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
+      \arg        DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
+      \arg        DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
+      \arg        DAC_TRIGGER_SOFTWARE: software trigger
+    \param[out] none
+    \retval     none
+*/
+void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)
+{
+    if(DAC0 == dac_periph){
+        /* configure DAC0 trigger source */
+        DAC_CTL &= ~DAC_CTL_DTSEL0;
+        DAC_CTL |= triggersource;
+    }else{
+        /* configure DAC1 trigger source */
+        DAC_CTL &= ~DAC_CTL_DTSEL1;
+        DAC_CTL |= (triggersource << DAC1_REG_OFFSET);
+    }
+}
+
+/*!
+    \brief      enable DAC software trigger
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \retval     none
+*/
+void dac_software_trigger_enable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_SWT |= DAC_SWT_SWTR0;
+    }else{
+        DAC_SWT |= DAC_SWT_SWTR1;
+    }
+}
+
+/*!
+    \brief      disable DAC software trigger
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[out] none
+    \retval     none
+*/
+void dac_software_trigger_disable(uint32_t dac_periph)
+{
+    if(DAC0 == dac_periph){
+        DAC_SWT &= ~DAC_SWT_SWTR0;
+    }else{
+        DAC_SWT &= ~DAC_SWT_SWTR1;
+    }
+}
+
+/*!
+    \brief      configure DAC wave mode
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[in]  wave_mode: noise wave mode
+                only one parameter can be selected which is shown as below:
+      \arg        DAC_WAVE_DISABLE: wave disable
+      \arg        DAC_WAVE_MODE_LFSR: LFSR noise mode
+      \arg        DAC_WAVE_MODE_TRIANGLE: triangle noise mode
+    \param[out] none
+    \retval     none
+*/
+void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
+{
+    if(DAC0 == dac_periph){
+        /* configure DAC0 wave mode */
+        DAC_CTL &= ~DAC_CTL_DWM0;
+        DAC_CTL |= wave_mode;
+    }else{
+        /* configure DAC1 wave mode */
+        DAC_CTL &= ~DAC_CTL_DWM1;
+        DAC_CTL |= (wave_mode << DAC1_REG_OFFSET);
+    }
+}
+
+/*!
+    \brief      configure DAC wave bit width
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[in]  bit_width: noise wave bit width
+                only one parameter can be selected which is shown as below:
+      \arg        DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
+      \arg        DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
+      \arg        DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
+      \arg        DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
+      \arg        DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
+      \arg        DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
+      \arg        DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
+      \arg        DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
+      \arg        DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
+      \arg        DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
+      \arg        DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
+      \arg        DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
+    \param[out] none
+    \retval     none
+*/
+void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
+{
+    if(DAC0 == dac_periph){
+        /* configure DAC0 wave bit width */
+        DAC_CTL &= ~DAC_CTL_DWBW0;
+        DAC_CTL |= bit_width;
+    }else{
+        /* configure DAC1 wave bit width */
+        DAC_CTL &= ~DAC_CTL_DWBW1;
+        DAC_CTL |= (bit_width << DAC1_REG_OFFSET);
+    }
+}
+
+/*!
+    \brief      configure DAC LFSR noise mode
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[in]  unmask_bits: unmask LFSR bits in DAC LFSR noise mode
+                only one parameter can be selected which is shown as below:
+      \arg        DAC_LFSR_BIT0: unmask the LFSR bit0
+      \arg        DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
+      \arg        DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
+      \arg        DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
+      \arg        DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
+      \arg        DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
+      \arg        DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
+      \arg        DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
+      \arg        DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
+      \arg        DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
+      \arg        DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
+      \arg        DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
+    \param[out] none
+    \retval     none
+*/
+void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
+{
+    if(DAC0 == dac_periph){
+        /* configure DAC0 LFSR noise mode */
+        DAC_CTL &= ~DAC_CTL_DWBW0;
+        DAC_CTL |= unmask_bits;
+    }else{
+        /* configure DAC1 LFSR noise mode */
+        DAC_CTL &= ~DAC_CTL_DWBW1;
+        DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET);
+    }
+}
+
+/*!
+    \brief      configure DAC triangle noise mode
+    \param[in]  dac_periph: DACx(x = 0,1)
+    \param[in]  amplitude: triangle amplitude in DAC triangle noise mode
+                only one parameter can be selected which is shown as below:
+      \arg        DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
+      \arg        DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
+      \arg        DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
+      \arg        DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
+      \arg        DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
+      \arg        DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
+      \arg        DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
+      \arg        DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
+      \arg        DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
+      \arg        DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
+      \arg        DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
+      \arg        DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
+    \param[out] none
+    \retval     none
+*/
+void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
+{
+    if(DAC0 == dac_periph){
+        /* configure DAC0 triangle noise mode */
+        DAC_CTL &= ~DAC_CTL_DWBW0;
+        DAC_CTL |= amplitude;
+    }else{
+        /* configure DAC1 triangle noise mode */
+        DAC_CTL &= ~DAC_CTL_DWBW1;
+        DAC_CTL |= (amplitude << DAC1_REG_OFFSET);
+    }
+}
+
+/*!
+    \brief      enable DAC concurrent mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_concurrent_enable(void)
+{
+    uint32_t ctl = 0U;
+    ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
+    DAC_CTL |= (ctl);
+}
+
+/*!
+    \brief      disable DAC concurrent mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_concurrent_disable(void)
+{
+    uint32_t ctl = 0U;
+    ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
+    DAC_CTL &= (~ctl);
+}
+
+/*!
+    \brief      enable DAC concurrent software trigger function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_concurrent_software_trigger_enable(void)
+{
+    uint32_t swt = 0U;
+    swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
+    DAC_SWT |= (swt); 
+}
+
+/*!
+    \brief      disable DAC concurrent software trigger function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_concurrent_software_trigger_disable(void)
+{
+    uint32_t swt = 0U;
+    swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
+    DAC_SWT &= (~swt);
+}
+
+/*!
+    \brief      enable DAC concurrent buffer function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_concurrent_output_buffer_enable(void)
+{
+    uint32_t ctl = 0U;
+    ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
+    DAC_CTL &= (~ctl);
+}
+
+/*!
+    \brief      disable DAC concurrent buffer function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_concurrent_output_buffer_disable(void)
+{
+    uint32_t ctl = 0U;
+    ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
+    DAC_CTL |= (ctl);
+}
+
+/*!
+    \brief      set DAC concurrent mode data holding register value
+    \param[in]  dac_align: data alignment
+                only one parameter can be selected which is shown as below:
+      \arg        DAC_ALIGN_8B_R: data right 8b alignment
+      \arg        DAC_ALIGN_12B_R: data right 12b alignment
+      \arg        DAC_ALIGN_12B_L: data left 12b alignment
+    \param[in]  data0: data to be loaded
+    \param[in]  data1: data to be loaded
+    \param[out] none
+    \retval     none
+*/
+void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
+{
+    uint32_t data = 0U;
+    switch(dac_align){
+    /* data right 12b alignment */
+    case DAC_ALIGN_12B_R:
+        data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0;
+        DACC_R12DH = data;
+        break;
+    /* data left 12b alignment */
+    case DAC_ALIGN_12B_L:
+        data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0;
+        DACC_L12DH = data;
+        break;
+    /* data right 8b alignment */
+    case DAC_ALIGN_8B_R:
+        data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0;
+        DACC_R8DH = data;
+        break;
+    default:
+        break;
+    }
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c
new file mode 100644
index 0000000000..2e0dfe5277
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c
@@ -0,0 +1,110 @@
+/*!
+    \file  gd32vf103_dbg.c
+    \brief DBG driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_dbg.h"
+
+/*!
+    \brief      read DBG_ID code register
+    \param[in]  none
+    \param[out] none
+    \retval     DBG_ID code
+*/
+uint32_t dbg_id_get(void)
+{
+    return DBG_ID;
+}
+
+/*!
+    \brief      enable low power behavior when the mcu is in debug mode
+    \param[in]  dbg_low_power:
+                one or more parameters can be selected which are shown as below:
+      \arg        DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
+      \arg        DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
+      \arg        DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
+    \param[out] none
+    \retval     none
+*/
+void dbg_low_power_enable(uint32_t dbg_low_power)
+{
+    DBG_CTL |= dbg_low_power;
+}
+
+/*!
+    \brief      disable low power behavior when the mcu is in debug mode
+    \param[in]  dbg_low_power:
+                one or more parameters can be selected which are shown as below:
+      \arg        DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
+      \arg        DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
+      \arg        DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
+    \param[out] none
+    \retval     none
+*/
+void dbg_low_power_disable(uint32_t dbg_low_power)
+{
+    DBG_CTL &= ~dbg_low_power;
+}
+
+/*!
+    \brief      enable peripheral behavior when the mcu is in debug mode
+    \param[in]  dbg_periph: refer to dbg_periph_enum
+                one or more parameters can be selected which are shown as below:
+      \arg        DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
+      \arg        DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
+      \arg        DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted
+      \arg        DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
+      \arg        DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted
+    \param[out] none
+    \retval     none
+*/
+void dbg_periph_enable(dbg_periph_enum dbg_periph)
+{
+    DBG_CTL |= (uint32_t)dbg_periph;
+}
+
+/*!
+    \brief      disable peripheral behavior when the mcu is in debug mode
+    \param[in]  dbg_periph: refer to dbg_periph_enum
+                one or more parameters can be selected which are shown as below:
+      \arg        DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
+      \arg        DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
+      \arg        DBG_CANx_HOLD (x=0,1): hold CAN0 counter when core is halted
+      \arg        DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
+      \arg        DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted
+    \param[out] none
+    \retval     none
+*/
+void dbg_periph_disable(dbg_periph_enum dbg_periph)
+{
+    DBG_CTL &= ~(uint32_t)dbg_periph;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c
new file mode 100644
index 0000000000..0d2c12c8fb
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c
@@ -0,0 +1,731 @@
+/*!
+    \file    gd32vf103_dma.c
+    \brief   DMA driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_dma.h"
+
+#define DMA_WRONG_HANDLE        while(1){}
+
+/* check whether peripheral matches channels or not */
+static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);
+
+/*!
+    \brief      deinitialize DMA a channel registers
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel is deinitialized
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
+{
+	if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+		DMA_WRONG_HANDLE
+	}
+
+	/* disable DMA a channel */
+	DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
+	/* reset DMA channel registers */
+	DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
+	DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
+	DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
+	DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
+	DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
+}
+
+/*!
+    \brief      initialize the parameters of DMA struct with the default values
+    \param[in]  init_struct: the initialization data needed to initialize DMA channel
+    \param[out] none
+    \retval     none
+*/
+void dma_struct_para_init(dma_parameter_struct* init_struct)
+{
+    /* set the DMA struct with the default values */
+    init_struct->periph_addr  = 0U;
+    init_struct->periph_width = 0U;
+    init_struct->periph_inc   = DMA_PERIPH_INCREASE_DISABLE;
+    init_struct->memory_addr  = 0U;
+    init_struct->memory_width = 0U;
+    init_struct->memory_inc   = DMA_MEMORY_INCREASE_DISABLE;
+    init_struct->number       = 0U;
+    init_struct->direction    = DMA_PERIPHERAL_TO_MEMORY;
+    init_struct->priority     = DMA_PRIORITY_LOW;
+}
+
+/*!
+    \brief      initialize DMA channel
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel is initialized
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  init_struct: the data needed to initialize DMA channel
+                  periph_addr: peripheral base address
+                  periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
+                  periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
+                  memory_addr: memory base address
+                  memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
+                  memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
+                  direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
+                  number: the number of remaining data to be transferred by the DMA
+                  priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
+    \param[out] none
+    \retval     none
+*/
+void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct)
+{
+    uint32_t ctl;
+
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    /* configure peripheral base address */
+    DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr;
+
+    /* configure memory base address */
+    DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr;
+
+    /* configure the number of remaining data to be transferred */
+    DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
+
+    /* configure peripheral transfer width,memory transfer width and priority */
+    ctl = DMA_CHCTL(dma_periph, channelx);
+    ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
+    ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
+    DMA_CHCTL(dma_periph, channelx) = ctl;
+
+    /* configure peripheral increasing mode */
+    if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
+        DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
+    }else{
+        DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
+    }
+
+    /* configure memory increasing mode */
+    if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){
+        DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
+    }else{
+        DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
+    }
+
+    /* configure the direction of data transfer */
+    if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
+        DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
+    }else{
+        DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
+    }
+}
+
+/*!
+    \brief      enable DMA circulation mode
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
+}
+
+/*!
+    \brief      disable DMA circulation mode
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
+}
+
+/*!
+    \brief      enable memory to memory mode
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
+}
+
+/*!
+    \brief      disable memory to memory mode
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
+}
+
+/*!
+    \brief      enable DMA channel
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
+}
+
+/*!
+    \brief      disable DMA channel
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
+}
+
+/*!
+    \brief      set DMA peripheral base address
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel to set peripheral base address
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  address: peripheral base address
+    \param[out] none
+    \retval     none
+*/
+void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHPADDR(dma_periph, channelx) = address;
+}
+
+/*!
+    \brief      set DMA memory base address
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel to set memory base address
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  address: memory base address
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHMADDR(dma_periph, channelx) = address;
+}
+
+/*!
+    \brief      set the number of remaining data to be transferred by the DMA
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel to set number
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  number: the number of remaining data to be transferred by the DMA
+    \param[out] none
+    \retval     none
+*/
+void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
+}
+
+/*!
+    \brief      get the number of remaining data to be transferred by the DMA
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel to set number
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     uint32_t: the number of remaining data to be transferred by the DMA
+*/
+uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    return (uint32_t)DMA_CHCNT(dma_periph, channelx);
+}
+
+/*!
+    \brief      configure priority level of DMA channel
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  priority: priority Level of this channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_PRIORITY_LOW: low priority
+      \arg        DMA_PRIORITY_MEDIUM: medium priority
+      \arg        DMA_PRIORITY_HIGH: high priority
+      \arg        DMA_PRIORITY_ULTRA_HIGH: ultra high priority
+    \param[out] none
+    \retval     none
+*/
+void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
+{
+    uint32_t ctl;
+
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    /* acquire DMA_CHxCTL register */
+    ctl = DMA_CHCTL(dma_periph, channelx);
+    /* assign regiser */
+    ctl &= ~DMA_CHXCTL_PRIO;
+    ctl |= priority;
+    DMA_CHCTL(dma_periph, channelx) = ctl;
+}
+
+/*!
+    \brief      configure transfer data size of memory
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  mwidth: transfer data width of memory
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
+      \arg        DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
+      \arg        DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
+{
+    uint32_t ctl;
+
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    /* acquire DMA_CHxCTL register */
+    ctl = DMA_CHCTL(dma_periph, channelx);
+    /* assign regiser */
+    ctl &= ~DMA_CHXCTL_MWIDTH;
+    ctl |= mwidth;
+    DMA_CHCTL(dma_periph, channelx) = ctl;
+}
+
+/*!
+    \brief      configure transfer data size of peripheral
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  pwidth: transfer data width of peripheral
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
+      \arg        DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
+      \arg        DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
+    \param[out] none
+    \retval     none
+*/
+void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
+{
+    uint32_t ctl;
+
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    /* acquire DMA_CHxCTL register */
+    ctl = DMA_CHCTL(dma_periph, channelx);
+    /* assign regiser */
+    ctl &= ~DMA_CHXCTL_PWIDTH;
+    ctl |= pwidth;
+    DMA_CHCTL(dma_periph, channelx) = ctl;
+}
+
+/*!
+    \brief      enable next address increasement algorithm of memory
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
+}
+
+/*!
+    \brief      disable next address increasement algorithm of memory
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
+}
+
+/*!
+    \brief      enable next address increasement algorithm of peripheral
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
+}
+
+/*!
+    \brief      disable next address increasement algorithm of peripheral
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
+}
+
+/*!
+    \brief      configure the direction of data transfer on the channel
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  direction: specify the direction of data transfer
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
+      \arg        DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
+    \param[out] none
+    \retval     none
+*/
+void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    if(DMA_PERIPHERAL_TO_MEMORY == direction){
+        DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
+    } else {
+        DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
+    }
+}
+
+/*!
+    \brief      check DMA flag is set or not
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel to get flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_FLAG_G: global interrupt flag of channel
+      \arg        DMA_FLAG_FTF: full transfer finish flag of channel
+      \arg        DMA_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_FLAG_ERR: error flag of channel
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
+{
+    FlagStatus reval;
+
+    if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
+        reval = SET;
+    }else{
+        reval = RESET;
+    }
+
+    return reval;
+}
+
+/*!
+    \brief      clear DMA a channel flag
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel to clear flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_FLAG_G: global interrupt flag of channel
+      \arg        DMA_FLAG_FTF: full transfer finish flag of channel
+      \arg        DMA_FLAG_HTF: half transfer finish flag of channel
+      \arg        DMA_FLAG_ERR: error flag of channel
+    \param[out] none
+    \retval     none
+*/
+void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
+{
+    DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
+}
+
+/*!
+    \brief      check DMA flag and interrupt enable bit is set or not
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel to get flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
+      \arg        DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
+      \arg        DMA_INT_FLAG_ERR: error interrupt flag of channel
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
+{
+	uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
+
+	switch(flag){
+		case DMA_INT_FLAG_FTF:
+			/* check whether the full transfer finish interrupt flag is set and enabled */
+			interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
+			interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
+			break;
+		case DMA_INT_FLAG_HTF:
+			/* check whether the half transfer finish interrupt flag is set and enabled */
+			interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
+			interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
+			break;
+		case DMA_INT_FLAG_ERR:
+			/* check whether the error interrupt flag is set and enabled */
+			interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
+			interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
+			break;
+		default:
+			DMA_WRONG_HANDLE
+	}
+
+	/* when the interrupt flag is set and enabled, return SET */
+	if(interrupt_flag && interrupt_enable){
+		return SET;
+	}else{
+		return RESET;
+	}
+}
+
+/*!
+    \brief      clear DMA a channel flag
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel to clear flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  flag: specify get which flag
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_INT_FLAG_G: global interrupt flag of channel
+      \arg        DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
+      \arg        DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
+      \arg        DMA_INT_FLAG_ERR: error interrupt flag of channel
+    \param[out] none
+    \retval     none
+*/
+void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
+{
+    DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
+}
+
+/*!
+    \brief      enable DMA interrupt
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  source: specify which interrupt to enbale
+                one or more parameters can be selected which are shown as below
+      \arg        DMA_INT_FTF: channel full transfer finish interrupt
+      \arg        DMA_INT_HTF: channel half transfer finish interrupt
+      \arg        DMA_INT_ERR: channel error interrupt
+    \param[out] none
+    \retval     none
+*/
+void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) |= source;
+}
+
+/*!
+    \brief      disable DMA interrupt
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
+    \param[in]  source: specify which interrupt to disbale
+                one or more parameters can be selected which are shown as below
+      \arg        DMA_INT_FTF: channel full transfer finish interrupt
+      \arg        DMA_INT_HTF: channel half transfer finish interrupt
+      \arg        DMA_INT_ERR: channel error interrupt
+    \param[out] none
+    \retval     none
+*/
+void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
+{
+    if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
+        DMA_WRONG_HANDLE
+    }
+
+    DMA_CHCTL(dma_periph, channelx) &= ~source;
+}
+
+/*!
+    \brief      check whether peripheral and channels match
+    \param[in]  dma_periph: DMAx(x=0,1)
+      \arg        DMAx(x=0,1)
+    \param[in]  channelx: specify which DMA channel
+                only one parameter can be selected which is shown as below:
+      \arg        DMA_CHx(x=0..6)
+    \param[out] none
+    \retval     none
+*/
+static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx)
+{
+    ErrStatus val = SUCCESS;
+
+    if(DMA1 == dma_periph){
+        /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */
+        if(channelx > DMA_CH4){
+            val = ERROR;
+        }
+    }
+
+    return val;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c
new file mode 100644
index 0000000000..d4385d6363
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c
@@ -0,0 +1,99 @@
+/*!
+    \file  gd32vf103_eclic.c
+    \brief ECLIC(Enhancement Core-Local Interrupt Controller) driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_eclic.h"
+#include "riscv_encoding.h"
+
+#define REG_DBGMCU2       ((uint32_t)0xE0042008)
+#define REG_DBGMCU2EN     ((uint32_t)0xE004200C)
+
+/*!
+    \brief      set the priority group
+    \param[in]  prigroup: specify the priority group
+      \arg        ECLIC_PRIGROUP_LEVEL0_PRIO4
+      \arg        ECLIC_PRIGROUP_LEVEL1_PRIO3
+      \arg        ECLIC_PRIGROUP_LEVEL2_PRIO2
+      \arg        ECLIC_PRIGROUP_LEVEL3_PRIO1
+      \arg        ECLIC_PRIGROUP_LEVEL4_PRIO0
+    \param[out] none
+    \retval     none
+*/
+void eclic_priority_group_set(uint32_t prigroup) {
+    eclic_set_nlbits(prigroup);
+}
+
+/*!
+    \brief      enable the interrupt request
+    \param[in]  source: interrupt request, detailed in IRQn_Type
+    \param[in]  level: the level needed to set (maximum is 16)
+    \param[in]  priority: the priority needed to set (maximum is 16)
+    \param[out] none
+    \retval     none
+*/
+void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority) {
+    eclic_enable_interrupt(source);
+    eclic_set_int_level(source, level);
+    eclic_set_int_priority(source, priority);
+}
+
+/*!
+    \brief      disable the interrupt request
+    \param[in]  source: interrupt request, detailed in IRQn_Type
+    \param[out] none
+    \retval     none
+*/
+void eclic_irq_disable(uint32_t source) {
+    eclic_disable_interrupt(source);
+}
+
+/*!
+    \brief      reset system
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void eclic_system_reset(void) {
+    REG32(REG_DBGMCU2EN) = 0x4b5a6978;
+    REG32(REG_DBGMCU2) = 0x1;
+}
+
+/*!
+    \brief      send event(SEV)
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void eclic_send_event(void) {
+    set_csr(0x812, 0x1);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c
new file mode 100644
index 0000000000..d414e078e0
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c
@@ -0,0 +1,164 @@
+/*!
+    \file    gd32vf103_exmc.c
+    \brief   EXMC driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_exmc.h"
+
+/* EXMC bank0 register reset value */
+#define BANK0_SNCTL0_REGION_RESET         ((uint32_t)0x000030DAU)
+#define BANK0_SNTCFG_RESET                ((uint32_t)0x0FFFFFFFU)
+
+/* EXMC register bit offset */
+#define SNCTL_NRMUX_OFFSET                ((uint32_t)1U)
+#define SNCTL_WREN_OFFSET                 ((uint32_t)12U)
+#define SNCTL_NRWTEN_OFFSET               ((uint32_t)13U)
+#define SNCTL_ASYNCWAIT_OFFSET            ((uint32_t)15U)
+
+#define SNTCFG_AHLD_OFFSET                ((uint32_t)4U)
+#define SNTCFG_DSET_OFFSET                ((uint32_t)8U)
+#define SNTCFG_BUSLAT_OFFSET              ((uint32_t)16U)
+
+/*!
+    \brief      deinitialize EXMC NOR/SRAM region
+    \param[in]  norsram_region: select the region of bank0
+      \arg        EXMC_BANK0_NORSRAM_REGIONx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void exmc_norsram_deinit(uint32_t norsram_region)
+{
+    /* reset the registers */
+    if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
+        EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
+    }
+
+    EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
+}
+
+/*!
+    \brief      initialize the structure exmc_norsram_parameter_struct
+    \param[in]  none
+    \param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer
+    \retval     none
+*/
+void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
+{
+    /* configure the structure with default value */
+    exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
+    exmc_norsram_init_struct->address_data_mux = ENABLE;
+    exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
+    exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B;
+    exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
+    exmc_norsram_init_struct->memory_write = ENABLE;
+    exmc_norsram_init_struct->nwait_signal = ENABLE;
+    exmc_norsram_init_struct->asyn_wait = DISABLE;
+
+    /* read/write timing configure */
+    exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
+    exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
+    exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
+    exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
+}
+
+/*!
+    \brief      initialize EXMC NOR/SRAM region
+    \param[in]  exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter
+                  norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0
+                  asyn_wait: ENABLE or DISABLE
+                  nwait_signal: ENABLE or DISABLE
+                  memory_write: ENABLE or DISABLE
+                  nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH
+                  databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B
+                  memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR
+                  address_data_mux: ENABLE
+                  read_write_timing: structure exmc_norsram_timing_parameter_struct set the time
+    \param[out] none
+    \retval     none
+*/
+void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
+{
+    uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U;
+
+    /* get the register value */
+    snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
+
+    /* clear relative bits */
+    snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL | 
+                          EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
+
+    snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
+                        exmc_norsram_init_struct->memory_type |
+                        exmc_norsram_init_struct->databus_width |
+                        exmc_norsram_init_struct->nwait_polarity |
+                       (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
+                       (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
+                       (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
+
+    sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
+                       (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
+                       (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
+                       (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT );
+
+    /* nor flash access enable */
+    if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
+        snctl |= (uint32_t)EXMC_SNCTL_NREN;
+    }
+
+    /* configure the registers */
+    EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
+    EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
+}
+
+/*!
+    \brief      enable EXMC NOR/PSRAM bank region
+    \param[in]  norsram_region: specify the region of NOR/PSRAM bank
+      \arg        EXMC_BANK0_NORSRAM_REGIONx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void exmc_norsram_enable(uint32_t norsram_region)
+{
+    EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
+}
+
+/*!
+    \brief      disable EXMC NOR/PSRAM bank region
+    \param[in]  norsram_region: specify the region of NOR/PSRAM bank
+      \arg        EXMC_BANK0_NORSRAM_REGIONx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void exmc_norsram_disable(uint32_t norsram_region)
+{
+    EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c
new file mode 100644
index 0000000000..4833b213bd
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c
@@ -0,0 +1,252 @@
+/*!
+    \file    gd32vf103_exti.c
+    \brief   EXTI driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_exti.h"
+
+#define EXTI_REG_RESET_VALUE            ((uint32_t)0x00000000U)
+
+/*!
+ \brief      deinitialize the EXTI
+ \param[in]  none
+ \param[out] none
+ \retval     none
+ */
+void exti_deinit(void)
+{
+    /* reset the value of all the EXTI registers */
+    EXTI_INTEN = EXTI_REG_RESET_VALUE;
+    EXTI_EVEN  = EXTI_REG_RESET_VALUE;
+    EXTI_RTEN  = EXTI_REG_RESET_VALUE;
+    EXTI_FTEN  = EXTI_REG_RESET_VALUE;
+    EXTI_SWIEV = EXTI_REG_RESET_VALUE;
+}
+
+/*!
+    \brief      initialize the EXTI
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[in]  mode: interrupt or event mode, refer to exti_mode_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_INTERRUPT: interrupt mode
+      \arg        EXTI_EVENT: event mode
+    \param[in]  trig_type: trigger type, refer to exti_trig_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_TRIG_RISING: rising edge trigger
+      \arg        EXTI_TRIG_FALLING: falling edge trigger
+      \arg        EXTI_TRIG_BOTH: rising edge and falling edge trigger
+    \param[out] none
+    \retval     none
+ */
+void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
+{
+    /* reset the EXTI line x */
+    EXTI_INTEN &= ~(uint32_t) linex;
+    EXTI_EVEN &= ~(uint32_t) linex;
+    EXTI_RTEN &= ~(uint32_t) linex;
+    EXTI_FTEN &= ~(uint32_t) linex;
+
+    /* set the EXTI mode and enable the interrupts or events from EXTI line x */
+    switch (mode) {
+    case EXTI_INTERRUPT:
+        EXTI_INTEN |= (uint32_t) linex;
+        break;
+    case EXTI_EVENT:
+        EXTI_EVEN |= (uint32_t) linex;
+        break;
+    default:
+        break;
+    }
+
+    /* set the EXTI trigger type */
+    switch (trig_type) {
+    case EXTI_TRIG_RISING:
+        EXTI_RTEN |= (uint32_t) linex;
+        EXTI_FTEN &= ~(uint32_t) linex;
+        break;
+    case EXTI_TRIG_FALLING:
+        EXTI_RTEN &= ~(uint32_t) linex;
+        EXTI_FTEN |= (uint32_t) linex;
+        break;
+    case EXTI_TRIG_BOTH:
+        EXTI_RTEN |= (uint32_t) linex;
+        EXTI_FTEN |= (uint32_t) linex;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      enable the interrupts from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_interrupt_enable(exti_line_enum linex)
+{
+    EXTI_INTEN |= (uint32_t) linex;
+}
+
+/*!
+    \brief      enable the events from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_event_enable(exti_line_enum linex)
+{
+    EXTI_EVEN |= (uint32_t) linex;
+}
+
+/*!
+    \brief      disable the interrupt from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_interrupt_disable(exti_line_enum linex)
+{
+    EXTI_INTEN &= ~(uint32_t) linex;
+}
+
+/*!
+    \brief      disable the events from EXTI line x
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_event_disable(exti_line_enum linex)
+{
+    EXTI_EVEN &= ~(uint32_t) linex;
+}
+
+/*!
+    \brief      get EXTI lines flag
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     FlagStatus: status of flag (RESET or SET)
+*/
+FlagStatus exti_flag_get(exti_line_enum linex)
+{
+    if (RESET != (EXTI_PD & (uint32_t) linex)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear EXTI lines pending flag
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_flag_clear(exti_line_enum linex)
+{
+    EXTI_PD = (uint32_t) linex;
+}
+
+/*!
+    \brief      get EXTI lines flag when the interrupt flag is set
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     FlagStatus: status of flag (RESET or SET)
+*/
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
+{
+    uint32_t flag_left, flag_right;
+
+    flag_left = EXTI_PD & (uint32_t) linex;
+    flag_right = EXTI_INTEN & (uint32_t) linex;
+
+    if ((RESET != flag_left) && (RESET != flag_right)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear EXTI lines pending flag
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_interrupt_flag_clear(exti_line_enum linex)
+{
+    EXTI_PD = (uint32_t) linex;
+}
+
+/*!
+    \brief      enable EXTI software interrupt event
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_software_interrupt_enable(exti_line_enum linex)
+{
+    EXTI_SWIEV |= (uint32_t) linex;
+}
+
+/*!
+    \brief      disable EXTI software interrupt event
+    \param[in]  linex: EXTI line number, refer to exti_line_enum
+                only one parameter can be selected which is shown as below:
+      \arg        EXTI_x (x=0..18): EXTI line x
+    \param[out] none
+    \retval     none
+*/
+void exti_software_interrupt_disable(exti_line_enum linex)
+{
+    EXTI_SWIEV &= ~(uint32_t) linex;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c
new file mode 100644
index 0000000000..c219a79617
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c
@@ -0,0 +1,649 @@
+/*!
+    \file  gd32vf103_fmc.c
+    \brief FMC driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_fmc.h"
+
+/*!
+    \brief      set the wait state counter value
+    \param[in]  wscnt��wait state counter value
+      \arg        WS_WSCNT_0: FMC 0 wait state
+      \arg        WS_WSCNT_1: FMC 1 wait state
+      \arg        WS_WSCNT_2: FMC 2 wait state
+    \param[out] none
+    \retval     none
+ */
+void fmc_wscnt_set(uint32_t wscnt)
+{
+    uint32_t reg;
+
+    reg = FMC_WS;
+    /* set the wait state counter value */
+    reg &= ~FMC_WS_WSCNT;
+    FMC_WS = (reg | wscnt);
+}
+
+/*!
+    \brief      unlock the main FMC operation
+    \param[in]  none
+    \param[out] none
+    \retval     none
+ */
+void fmc_unlock(void)
+{
+    if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
+        /* write the FMC unlock key */
+        FMC_KEY0 = UNLOCK_KEY0;
+        FMC_KEY0 = UNLOCK_KEY1;
+    }
+}
+
+/*!
+    \brief      lock the main FMC operation
+    \param[in]  none
+    \param[out] none
+    \retval     none
+ */
+void fmc_lock(void)
+{
+    /* set the LK bit */
+    FMC_CTL0 |= FMC_CTL0_LK;
+}
+
+
+/*!
+    \brief      FMC erase page
+    \param[in]  page_address: the page address to be erased.
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum fmc_page_erase(uint32_t page_address)
+{
+    fmc_state_enum fmc_state;
+    fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+    /* if the last operation is completed, start page erase */
+    if (FMC_READY == fmc_state) {
+        FMC_CTL0 |= FMC_CTL0_PER;
+        FMC_ADDR0 = page_address;
+        FMC_CTL0 |= FMC_CTL0_START;
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        /* reset the PER bit */
+        FMC_CTL0 &= ~FMC_CTL0_PER;
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      FMC erase whole chip
+    \param[in]  none
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum fmc_mass_erase(void)
+{
+    fmc_state_enum fmc_state;
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+        if(FMC_READY == fmc_state){
+            /* start whole chip erase */
+            FMC_CTL0 |= FMC_CTL0_MER;
+            FMC_CTL0 |= FMC_CTL0_START;
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+            /* reset the MER bit */
+            FMC_CTL0 &= ~FMC_CTL0_MER;
+        }
+    /* return the FMC state  */
+    return fmc_state;
+}
+
+/*!
+    \brief      FMC program a word at the corresponding address
+    \param[in]  address: address to program
+    \param[in]  data: word to program
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
+{
+    fmc_state_enum fmc_state = FMC_READY;
+    fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    if(FMC_READY == fmc_state){
+        /* set the PG bit to start program */
+        FMC_CTL0 |= FMC_CTL0_PG;
+        REG32(address) = data;
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        /* reset the PG bit */
+        FMC_CTL0 &= ~FMC_CTL0_PG;
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+/*
+    \brief      FMC program a half word at the corresponding address
+    \param[in]  address: address to program
+    \param[in]  data: halfword to program
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+*/
+fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
+{
+    fmc_state_enum fmc_state = FMC_READY;
+    fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    if(FMC_READY == fmc_state){
+        /* set the PG bit to start program */
+        FMC_CTL0 |= FMC_CTL0_PG;
+        REG16(address) = data;
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        /* reset the PG bit */
+        FMC_CTL0 &= ~FMC_CTL0_PG;
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      unlock the option byte operation
+    \param[in]  none
+    \param[out] none
+    \retval     none
+ */
+void ob_unlock(void)
+{
+    if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
+        /* write the FMC key */
+        FMC_OBKEY = UNLOCK_KEY0;
+        FMC_OBKEY = UNLOCK_KEY1;
+    }
+
+    /* wait until OBWEN bit is set by hardware */
+    while (RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) {
+    }
+}
+
+/*!
+    \brief      lock the option byte operation
+    \param[in]  none
+    \param[out] none
+    \retval     none
+ */
+void ob_lock(void)
+{
+    /* reset the OBWEN bit */
+    FMC_CTL0 &= ~FMC_CTL0_OBWEN;
+}
+
+/*!
+    \brief      erase the FMC option byte
+    unlock the FMC_CTL0 and option byte before calling this function
+    \param[in]  none
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum ob_erase(void)
+{
+    uint16_t temp_spc = FMC_NSPC;
+
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    /* check the option byte security protection value */
+    if(RESET != ob_spc_get()){
+        temp_spc = FMC_USPC;
+    }
+
+    if(FMC_READY == fmc_state){
+
+        /* start erase the option byte */
+        FMC_CTL0 |= FMC_CTL0_OBER;
+        FMC_CTL0 |= FMC_CTL0_START;
+
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+        if(FMC_READY == fmc_state){
+            /* reset the OBER bit */
+            FMC_CTL0 &= ~FMC_CTL0_OBER;
+            /* set the OBPG bit */
+            FMC_CTL0 |= FMC_CTL0_OBPG;
+            /* no security protection */
+            OB_SPC = (uint16_t) temp_spc;
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+            if (FMC_TOERR != fmc_state) {
+                /* reset the OBPG bit */
+                FMC_CTL0 &= ~FMC_CTL0_OBPG;
+            }
+        }else{
+            if(FMC_TOERR != fmc_state){
+                /* reset the OBPG bit */
+                FMC_CTL0 &= ~FMC_CTL0_OBPG;
+            }
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      enable write protection
+    \param[in]  ob_wp: specify sector to be write protected, set the bit to 1 if
+    you want to protect the corresponding pages. meanwhile, sector
+    macro could used to set specific sector write protected.
+    one or more parameters can be selected which are shown as below:
+      \arg        OB_WPx(x = 0..31): write protect specify sector
+      \arg        OB_WP_ALL: write protect all sector
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
+{
+    uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3;
+
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    ob_wp = (uint32_t) (~ob_wp);
+    temp_wp0 = (uint16_t) (ob_wp & OB_WP0_WP0);
+    temp_wp1 = (uint16_t) ((ob_wp & OB_WP1_WP1) >> 8U);
+    temp_wp2 = (uint16_t) ((ob_wp & OB_WP2_WP2) >> 16U);
+    temp_wp3 = (uint16_t) ((ob_wp & OB_WP3_WP3) >> 24U);
+
+    if(FMC_READY == fmc_state){
+
+        /* set the OBPG bit*/
+        FMC_CTL0 |= FMC_CTL0_OBPG;
+
+        if(0xFFU != temp_wp0){
+            OB_WP0 = temp_wp0;
+
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        }
+        if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){
+            OB_WP1 = temp_wp1;
+
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        }
+        if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){
+            OB_WP2 = temp_wp2;
+
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        }
+        if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){
+            OB_WP3 = temp_wp3;
+
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+        }
+        if(FMC_TOERR != fmc_state){
+            /* reset the OBPG bit */
+            FMC_CTL0 &= ~FMC_CTL0_OBPG;
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      configure security protection
+    \param[in]  ob_spc: specify security protection
+    only one parameter can be selected which is shown as below:
+      \arg        FMC_NSPC: no security protection
+      \arg        FMC_USPC: under security protection
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
+{
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    if(FMC_READY == fmc_state){
+        FMC_CTL0 |= FMC_CTL0_OBER;
+        FMC_CTL0 |= FMC_CTL0_START;
+
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+        if(FMC_READY == fmc_state){
+            /* reset the OBER bit */
+            FMC_CTL0 &= ~FMC_CTL0_OBER;
+
+            /* start the option byte program */
+            FMC_CTL0 |= FMC_CTL0_OBPG;
+
+            OB_SPC = (uint16_t) ob_spc;
+
+            /* wait for the FMC ready */
+            fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+            if (FMC_TOERR != fmc_state) {
+                /* reset the OBPG bit */
+                FMC_CTL0 &= ~FMC_CTL0_OBPG;
+            }
+        }else{
+            if (FMC_TOERR != fmc_state) {
+                /* reset the OBER bit */
+                FMC_CTL0 &= ~FMC_CTL0_OBER;
+            }
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      program the FMC user option byte
+    \param[in]  ob_fwdgt: option byte watchdog value
+      \arg        OB_FWDGT_SW: software free watchdog
+     \arg        OB_FWDGT_HW: hardware free watchdog
+    \param[in]  ob_deepsleep: option byte deepsleep reset value
+      \arg        OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode
+      \arg        OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode
+    \param[in]  ob_stdby:option byte standby reset value
+       \arg        OB_STDBY_NRST: no reset when entering standby mode
+      \arg        OB_STDBY_RST: generate a reset instead of entering standby mode
+    \param[in]  ob_boot: specifies the option byte boot bank value
+      \arg        OB_BOOT_B0: boot from bank0
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
+{
+    fmc_state_enum fmc_state = FMC_READY;
+    uint8_t temp;
+
+    /* wait for the FMC ready */
+    fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    if(FMC_READY == fmc_state){
+        /* set the OBPG bit*/
+        FMC_CTL0 |= FMC_CTL0_OBPG;
+
+        temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK);
+        OB_USER = (uint16_t) temp;
+
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+        if(FMC_TOERR != fmc_state){
+            /* reset the OBPG bit */
+            FMC_CTL0 &= ~FMC_CTL0_OBPG;
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      program option bytes data
+    \param[in]  address: the option bytes address to be programmed
+    \param[in]  data: the byte to be programmed
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum ob_data_program(uint32_t address, uint8_t data) {
+    fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+    if(FMC_READY == fmc_state){
+        /* set the OBPG bit */
+        FMC_CTL0 |= FMC_CTL0_OBPG;
+        REG16(address) = data;
+
+        /* wait for the FMC ready */
+        fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
+
+        if(FMC_TOERR != fmc_state){
+            /* reset the OBPG bit */
+            FMC_CTL0 &= ~FMC_CTL0_OBPG;
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      get the FMC user option byte
+    \param[in]  none
+    \param[out] none
+    \retval     the FMC user option byte values
+ */
+uint8_t ob_user_get(void)
+{
+    /* return the FMC user option byte value */
+    return (uint8_t) (FMC_OBSTAT >> 2U);
+}
+
+/*!
+    \brief      get OB_DATA in register FMC_OBSTAT
+    \param[in]  none
+    \param[out] none
+    \retval     ob_data
+ */
+uint16_t ob_data_get(void)
+{
+    return (uint16_t) (FMC_OBSTAT >> 10U);
+}
+
+/*!
+    \brief      get the FMC option byte write protection
+    \param[in]  none
+    \param[out] none
+    \retval     the FMC write protection option byte value
+ */
+uint32_t ob_write_protection_get(void)
+{
+    /* return the FMC write protection option byte value */
+    return FMC_WP;
+}
+
+/*!
+    \brief      get the FMC option byte security protection
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+ */
+FlagStatus ob_spc_get(void)
+{
+    FlagStatus spc_state = RESET;
+
+    if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){
+        spc_state = SET;
+    }else{
+        spc_state = RESET;
+    }
+    return spc_state;
+}
+
+/*!
+    \brief      enable FMC interrupt
+    \param[in]  interrupt: the FMC interrupt source
+    only one parameter can be selected which is shown as below:
+      \arg        FMC_INT_END: enable FMC end of program interrupt
+      \arg        FMC_INT_ERR: enable FMC error interrupt
+    \param[out] none
+    \retval     none
+ */
+void fmc_interrupt_enable(uint32_t interrupt)
+{
+    FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt));
+}
+
+/*!
+    \brief      disable FMC interrupt
+    \param[in]  interrupt: the FMC interrupt source
+    only one parameter can be selected which is shown as below:
+      \arg        FMC_INT_END: enable FMC end of program interrupt
+      \arg        FMC_INT_ERR: enable FMC error interrupt
+    \param[out] none
+    \retval     none
+ */
+void fmc_interrupt_disable(uint32_t interrupt)
+{
+    FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt));
+}
+
+/*!
+    \brief      check flag is set or not
+    \param[in]  flag: check FMC flag
+    only one parameter can be selected which is shown as below:
+      \arg        FMC_FLAG_BUSY: FMC busy flag bit
+      \arg        FMC_FLAG_PGERR: FMC operation error flag bit
+      \arg        FMC_FLAG_WPERR: FMC erase/program protection error flag bit
+      \arg        FMC_FLAG_END: FMC end of operation flag bit
+      \arg        FMC_FLAG_OBERR: FMC option bytes read error flag bit
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+ */
+FlagStatus fmc_flag_get(uint32_t flag)
+{
+    if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/*!
+ \brief      clear the FMC flag
+ \param[in]  flag: clear FMC flag
+ only one parameter can be selected which is shown as below:
+ \arg        FMC_FLAG_PGERR: FMC operation error flag bit
+ \arg        FMC_FLAG_WPERR: FMC erase/program protection error flag bit
+ \arg        FMC_FLAG_END: FMC end of operation flag bit
+ \param[out] none
+ \retval     none
+ */
+void fmc_flag_clear(uint32_t flag)
+{
+    FMC_REG_VAL(flag) = (!FMC_REG_VAL(flag)) | BIT(FMC_BIT_POS(flag));
+}
+
+/*!
+    \brief      get FMC interrupt flag state
+    \param[in]  flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum
+    only one parameter can be selected which is shown as below:
+      \arg        FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit
+      \arg        FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit
+      \arg        FMC_INT_FLAG_END: FMC end of operation interrupt flag bit
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+ */
+FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
+{
+    FlagStatus ret1 = RESET;
+    FlagStatus ret2 = RESET;
+
+    if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
+        /* get the staus of interrupt flag */
+        ret1 = (FlagStatus) (FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
+        /* get the staus of interrupt enale bit */
+        ret2 = (FlagStatus) (FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
+    }
+
+    if(ret1 && ret2){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear FMC interrupt flag state
+    \param[in]  flag: FMC interrupt flags, refer to can_interrupt_flag_enum
+    only one parameter can be selected which is shown as below:
+      \arg        FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit
+      \arg        FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit
+      \arg        FMC_INT_FLAG_END: FMC end of operation interrupt flag bit
+     \param[out] none
+     \retval     none
+ */
+void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag)
+{
+    FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag));
+}
+
+/*!
+    \brief      get the FMC state
+    \param[in]  none
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum fmc_state_get(void)
+{
+    fmc_state_enum fmc_state = FMC_READY;
+
+    if((uint32_t) 0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){
+        fmc_state = FMC_BUSY;
+    }else{
+        if((uint32_t) 0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){
+            fmc_state = FMC_WPERR;
+        }else{
+            if((uint32_t) 0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){
+                fmc_state = FMC_PGERR;
+            }
+        }
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
+
+/*!
+    \brief      check whether FMC is ready or not
+    \param[in]  timeout: count of loop
+    \param[out] none
+    \retval     state of FMC, refer to fmc_state_enum
+ */
+fmc_state_enum fmc_ready_wait(uint32_t timeout)
+{
+    fmc_state_enum fmc_state = FMC_BUSY;
+
+    /* wait for FMC ready */
+    do{
+        /* get FMC state */
+        fmc_state = fmc_state_get();
+        timeout--;
+    }while((FMC_BUSY == fmc_state) && (0x00U != timeout));
+
+    if(FMC_BUSY == fmc_state){
+        fmc_state = FMC_TOERR;
+    }
+    /* return the FMC state */
+    return fmc_state;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c
new file mode 100644
index 0000000000..c0f2a38e83
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c
@@ -0,0 +1,151 @@
+/*!
+    \file  gd32vf103_fwdgt.c
+    \brief FWDGT driver
+       
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_fwdgt.h"
+
+/* write value to FWDGT_CTL_CMD bit field */
+#define CTL_CMD(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0))
+/* write value to FWDGT_RLD_RLD bit field */
+#define RLD_RLD(regval)             (BITS(0,11) & ((uint32_t)(regval) << 0))
+
+/*!
+    \brief      enable write access to FWDGT_PSC and FWDGT_RLD
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_write_enable(void)
+{
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+}
+
+/*!
+    \brief      disable write access to FWDGT_PSC and FWDGT_RLD
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_write_disable(void)
+{
+    FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
+}
+
+/*!
+    \brief      start the free watchdog timer counter
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_enable(void)
+{
+    FWDGT_CTL = FWDGT_KEY_ENABLE;
+}
+
+/*!
+    \brief      reload the counter of FWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void fwdgt_counter_reload(void)
+{
+    FWDGT_CTL = FWDGT_KEY_RELOAD;
+}
+
+/*!
+    \brief      configure counter reload value, and prescaler divider value
+    \param[in]  reload_value: specify reload value(0x0000 - 0x0FFF)
+    \param[in]  prescaler_div: FWDGT prescaler value
+                only one parameter can be selected which is shown as below:
+      \arg        FWDGT_PSC_DIV4: FWDGT prescaler set to 4
+      \arg        FWDGT_PSC_DIV8: FWDGT prescaler set to 8
+      \arg        FWDGT_PSC_DIV16: FWDGT prescaler set to 16
+      \arg        FWDGT_PSC_DIV32: FWDGT prescaler set to 32
+      \arg        FWDGT_PSC_DIV64: FWDGT prescaler set to 64
+      \arg        FWDGT_PSC_DIV128: FWDGT prescaler set to 128
+      \arg        FWDGT_PSC_DIV256: FWDGT prescaler set to 256
+    \param[out] none
+    \retval     ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
+{
+    uint32_t timeout = FWDGT_PSC_TIMEOUT;
+    uint32_t flag_status = RESET;
+  
+    /* enable write access to FWDGT_PSC,and FWDGT_RLD */
+    FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+    /* wait until the PUD flag to be reset */
+    do{
+       flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
+    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+    
+    if((uint32_t)RESET != flag_status){
+        return ERROR;
+    }
+    /* configure FWDGT */
+    FWDGT_PSC = (uint32_t)prescaler_div;
+
+    timeout = FWDGT_RLD_TIMEOUT;
+    /* wait until the RUD flag to be reset */
+    do{
+       flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
+    }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+   
+    if((uint32_t)RESET != flag_status){
+        return ERROR;
+    }
+    FWDGT_RLD = RLD_RLD(reload_value);
+    /* reload the counter */
+    FWDGT_CTL = FWDGT_KEY_RELOAD;
+
+    return SUCCESS;
+}
+
+/*!
+    \brief      get flag state of FWDGT
+    \param[in]  flag: flag to get 
+                only one parameter can be selected which is shown as below:
+      \arg        FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
+      \arg        FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus fwdgt_flag_get(uint16_t flag)
+{
+    if(FWDGT_STAT & flag){
+        return SET;
+    }
+    
+    return RESET;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c
new file mode 100644
index 0000000000..cc0fd3f644
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c
@@ -0,0 +1,503 @@
+/*!
+    \file  gd32vf103_gpio.c
+    \brief GPIO driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_gpio.h"
+
+#define AFIO_EXTI_SOURCE_MASK              ((uint8_t)0x03U)         /*!< AFIO exti source selection mask*/  
+#define AFIO_EXTI_SOURCE_FIELDS            ((uint8_t)0x04U)         /*!< select AFIO exti source registers */
+#define LSB_16BIT_MASK                     ((uint16_t)0xFFFFU)      /*!< LSB 16-bit mask */
+#define PCF_POSITION_MASK                  ((uint32_t)0x000F0000U)  /*!< AFIO_PCF register position mask */
+#define PCF_SWJCFG_MASK                    ((uint32_t)0xF0FFFFFFU)  /*!< AFIO_PCF register SWJCFG mask */
+#define PCF_LOCATION1_MASK                 ((uint32_t)0x00200000U)  /*!< AFIO_PCF register location1 mask */
+#define PCF_LOCATION2_MASK                 ((uint32_t)0x00100000U)  /*!< AFIO_PCF register location2 mask */
+#define AFIO_PCF1_FIELDS                   ((uint32_t)0x80000000U)  /*!< select AFIO_PCF1 register */
+#define GPIO_OUTPUT_PORT_OFFSET            ((uint32_t)4U)           /*!< GPIO event output port offset*/
+
+/*!
+    \brief      reset GPIO port
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[out] none
+    \retval     none
+*/
+void gpio_deinit(uint32_t gpio_periph)
+{
+    switch (gpio_periph) {
+    case GPIOA:
+        /* reset GPIOA */
+        rcu_periph_reset_enable(RCU_GPIOARST);
+        rcu_periph_reset_disable(RCU_GPIOARST);
+        break;
+    case GPIOB:
+        /* reset GPIOB */
+        rcu_periph_reset_enable(RCU_GPIOBRST);
+        rcu_periph_reset_disable(RCU_GPIOBRST);
+        break;
+    case GPIOC:
+        /* reset GPIOC */
+        rcu_periph_reset_enable(RCU_GPIOCRST);
+        rcu_periph_reset_disable(RCU_GPIOCRST);
+        break;
+    case GPIOD:
+        /* reset GPIOD */
+        rcu_periph_reset_enable(RCU_GPIODRST);
+        rcu_periph_reset_disable(RCU_GPIODRST);
+        break;
+    case GPIOE:
+        /* reset GPIOE */
+        rcu_periph_reset_enable(RCU_GPIOERST);
+        rcu_periph_reset_disable(RCU_GPIOERST);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      reset alternate function I/O(AFIO)
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_afio_deinit(void)
+{
+    rcu_periph_reset_enable(RCU_AFRST);
+    rcu_periph_reset_disable(RCU_AFRST);
+}
+
+/*!
+    \brief      GPIO parameter initialization
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[in]  mode: gpio pin mode
+                only one parameter can be selected which is shown as below:
+      \arg        GPIO_MODE_AIN: analog input mode
+      \arg        GPIO_MODE_IN_FLOATING: floating input mode
+      \arg        GPIO_MODE_IPD: pull-down input mode
+      \arg        GPIO_MODE_IPU: pull-up input mode
+      \arg        GPIO_MODE_OUT_OD: GPIO output with open-drain
+      \arg        GPIO_MODE_OUT_PP: GPIO output with push-pull
+      \arg        GPIO_MODE_AF_OD: AFIO output with open-drain
+      \arg        GPIO_MODE_AF_PP: AFIO output with push-pull
+    \param[in]  speed: gpio output max speed value
+                only one parameter can be selected which is shown as below:
+      \arg        GPIO_OSPEED_10MHZ: output max speed 10MHz
+      \arg        GPIO_OSPEED_2MHZ: output max speed 2MHz
+      \arg        GPIO_OSPEED_50MHZ: output max speed 50MHz
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+
+    \param[out] none
+    \retval     none
+*/
+void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed,
+        uint32_t pin)
+{
+    uint16_t i;
+    uint32_t temp_mode = 0U;
+    uint32_t reg = 0U;
+
+    /* GPIO mode configuration */
+    temp_mode = (uint32_t) (mode & ((uint32_t) 0x0FU));
+
+    /* GPIO speed configuration */
+    if (((uint32_t) 0x00U) != ((uint32_t) mode & ((uint32_t) 0x10U))) {
+        /* output mode max speed:10MHz,2MHz,50MHz */
+        temp_mode |= (uint32_t) speed;
+    }
+
+    /* configure the eight low port pins with GPIO_CTL0 */
+    for (i = 0U; i < 8U; i++) {
+        if ((1U << i) & pin) {
+            reg = GPIO_CTL0(gpio_periph);
+
+            /* clear the specified pin mode bits */
+            reg &= ~GPIO_MODE_MASK(i);
+            /* set the specified pin mode bits */
+            reg |= GPIO_MODE_SET(i, temp_mode);
+
+            /* set IPD or IPU */
+            if (GPIO_MODE_IPD == mode) {
+                /* reset the corresponding OCTL bit */
+                GPIO_BC(gpio_periph) = (uint32_t) ((1U << i) & pin);
+            } else {
+                /* set the corresponding OCTL bit */
+                if (GPIO_MODE_IPU == mode) {
+                    GPIO_BOP(gpio_periph) = (uint32_t) ((1U << i) & pin);
+                }
+            }
+            /* set GPIO_CTL0 register */
+            GPIO_CTL0(gpio_periph) = reg;
+        }
+    }
+    /* configure the eight high port pins with GPIO_CTL1 */
+    for (i = 8U; i < 16U; i++) {
+        if ((1U << i) & pin) {
+            reg = GPIO_CTL1(gpio_periph);
+
+            /* clear the specified pin mode bits */
+            reg &= ~GPIO_MODE_MASK(i - 8U);
+            /* set the specified pin mode bits */
+            reg |= GPIO_MODE_SET(i - 8U, temp_mode);
+
+            /* set IPD or IPU */
+            if (GPIO_MODE_IPD == mode) {
+                /* reset the corresponding OCTL bit */
+                GPIO_BC(gpio_periph) = (uint32_t) ((1U << i) & pin);
+            } else {
+                /* set the corresponding OCTL bit */
+                if (GPIO_MODE_IPU == mode) {
+                    GPIO_BOP(gpio_periph) = (uint32_t) ((1U << i) & pin);
+                }
+            }
+            /* set GPIO_CTL1 register */
+            GPIO_CTL1(gpio_periph) = reg;
+        }
+    }
+}
+
+/*!
+    \brief      set GPIO pin
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
+{
+    GPIO_BOP(gpio_periph) = (uint32_t) pin;
+}
+
+/*!
+    \brief      reset GPIO pin
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
+{
+    GPIO_BC(gpio_periph) = (uint32_t) pin;
+}
+
+/*!
+    \brief      write data to the specified GPIO pin
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[in]  bit_value: SET or RESET
+                only one parameter can be selected which is shown as below:
+      \arg        RESET: clear the port pin
+      \arg        SET: set the port pin
+    \param[out] none
+    \retval     none
+*/
+void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
+{
+    if (RESET != bit_value) {
+        GPIO_BOP(gpio_periph) = (uint32_t) pin;
+    } else {
+        GPIO_BC(gpio_periph) = (uint32_t) pin;
+    }
+}
+
+/*!
+    \brief      write data to the specified GPIO port
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[in]  data: specify the value to be written to the port output data register
+    \param[out] none
+    \retval     none
+*/
+void gpio_port_write(uint32_t gpio_periph, uint16_t data)
+{
+    GPIO_OCTL(gpio_periph) = (uint32_t) data;
+}
+
+/*!
+    \brief      get GPIO pin input status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[in]  pin: GPIO pin
+                only one parameter can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     input status of gpio pin: SET or RESET
+*/
+FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
+{
+    if ((uint32_t) RESET != (GPIO_ISTAT(gpio_periph) & (pin))) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/*!
+    \brief      get GPIO port input status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[out] none
+    \retval     input status of gpio all pins
+*/
+uint16_t gpio_input_port_get(uint32_t gpio_periph)
+{
+    return (uint16_t) (GPIO_ISTAT(gpio_periph));
+}
+
+/*!
+    \brief      get GPIO pin output status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[in]  pin: GPIO pin
+                only one parameter can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     output status of gpio pin: SET or RESET
+*/
+FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
+{
+    if ((uint32_t) RESET != (GPIO_OCTL(gpio_periph) & (pin))) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/*!
+    \brief      get GPIO port output status
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[out] none
+    \retval     output status of gpio all pins
+*/
+uint16_t gpio_output_port_get(uint32_t gpio_periph)
+{
+    return ((uint16_t) GPIO_OCTL(gpio_periph));
+}
+
+/*!
+    \brief      configure GPIO pin remap
+    \param[in]  gpio_remap: select the pin to remap
+                only one parameter can be selected which are shown as below:
+      \arg        GPIO_SPI0_REMAP: SPI0 remapping
+      \arg        GPIO_I2C0_REMAP: I2C0 remapping
+      \arg        GPIO_USART0_REMAP: USART0 remapping
+      \arg        GPIO_USART1_REMAP: USART1 remapping
+      \arg        GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping
+      \arg        GPIO_USART2_FULL_REMAP: USART2 full remapping
+      \arg        GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping
+      \arg        GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping
+      \arg        GPIO_TIMER1_PARTIAL_REMAP0: TIMER1 partial remapping
+      \arg        GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping
+      \arg        GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping
+      \arg        GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping
+      \arg        GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping
+      \arg        GPIO_TIMER3_REMAP: TIMER3 remapping
+      \arg        GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping
+      \arg        GPIO_CAN0_FULL_REMAP: CAN0 full remapping
+      \arg        GPIO_PD01_REMAP: PD01 remapping
+      \arg        GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping
+      \arg        GPIO_CAN1_REMAP: CAN1 remapping
+      \arg        GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP),but without NJTRST
+      \arg        GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled
+      \arg        GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled
+      \arg        GPIO_SPI2_REMAP: SPI2 remapping
+      \arg        GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping
+      \arg        GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect
+    \param[in]  newvalue: ENABLE or DISABLE
+    \param[out] none
+    \retval     none
+*/
+void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue)
+{
+    uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
+
+    if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) {
+        /* get AFIO_PCF1 regiter value */
+        temp_reg = AFIO_PCF1;
+    } else {
+        /* get AFIO_PCF0 regiter value */
+        temp_reg = AFIO_PCF0;
+    }
+
+    temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U;
+    remap1 = remap & LSB_16BIT_MASK;
+
+    /* judge pin remap type */
+    if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK)
+            == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) {
+        temp_reg &= PCF_SWJCFG_MASK;
+        AFIO_PCF0 &= PCF_SWJCFG_MASK;
+    } else if (PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)) {
+        remap2 = ((uint32_t) 0x03U) << temp_mask;
+        temp_reg &= ~remap2;
+        temp_reg |= ~PCF_SWJCFG_MASK;
+    }  else {
+        temp_reg &= ~(remap1 << ((remap >> 0x15U) * 0x10U));
+        temp_reg |= ~PCF_SWJCFG_MASK;
+    }
+
+    /* set pin remap value */
+    if (DISABLE != newvalue) {
+        temp_reg |= (remap1 << ((remap >> 0x15U) * 0x10U));
+    }
+
+    if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) {
+        /* set AFIO_PCF1 regiter value */
+        AFIO_PCF1 = temp_reg;
+    } else {
+        /* set AFIO_PCF0 regiter value */
+        AFIO_PCF0 = temp_reg;
+    }
+}
+
+/*!
+    \brief      select GPIO pin exti sources
+    \param[in]  gpio_outputport: gpio event output port
+                only one parameter can be selected which are shown as below:
+      \arg        GPIO_PORT_SOURCE_GPIOA: output port source A
+      \arg        GPIO_PORT_SOURCE_GPIOB: output port source B
+      \arg        GPIO_PORT_SOURCE_GPIOC: output port source C
+      \arg        GPIO_PORT_SOURCE_GPIOD: output port source D
+      \arg        GPIO_PORT_SOURCE_GPIOE: output port source E
+    \param[in]  gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15)
+    \param[out] none
+    \retval     none
+*/
+void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin)
+{
+    uint32_t source = 0U;
+    source = ((uint32_t) 0x0FU)
+            << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK));
+
+    /* select EXTI sources */
+    if (GPIO_PIN_SOURCE_4 > output_pin) {
+        /* select EXTI0/EXTI1/EXTI2/EXTI3 */
+        AFIO_EXTISS0 &= ~source;
+        AFIO_EXTISS0 |= (((uint32_t) output_port)
+                << (AFIO_EXTI_SOURCE_FIELDS
+                        * (output_pin & AFIO_EXTI_SOURCE_MASK)));
+    } else if (GPIO_PIN_SOURCE_8 > output_pin) {
+        /* select EXTI4/EXTI5/EXTI6/EXTI7 */
+        AFIO_EXTISS1 &= ~source;
+        AFIO_EXTISS1 |= (((uint32_t) output_port)
+                << (AFIO_EXTI_SOURCE_FIELDS
+                        * (output_pin & AFIO_EXTI_SOURCE_MASK)));
+    } else if (GPIO_PIN_SOURCE_12 > output_pin) {
+        /* select EXTI8/EXTI9/EXTI10/EXTI11 */
+        AFIO_EXTISS2 &= ~source;
+        AFIO_EXTISS2 |= (((uint32_t) output_port)
+                << (AFIO_EXTI_SOURCE_FIELDS
+                        * (output_pin & AFIO_EXTI_SOURCE_MASK)));
+    } else {
+        /* select EXTI12/EXTI13/EXTI14/EXTI15 */
+        AFIO_EXTISS3 &= ~source;
+        AFIO_EXTISS3 |= (((uint32_t) output_port)
+                << (AFIO_EXTI_SOURCE_FIELDS
+                        * (output_pin & AFIO_EXTI_SOURCE_MASK)));
+    }
+}
+
+/*!
+    \brief      configure GPIO pin event output
+    \param[in]  output_port: gpio event output port
+                only one parameter can be selected which are shown as below:
+      \arg        GPIO_EVENT_PORT_GPIOA: event output port A
+      \arg        GPIO_EVENT_PORT_GPIOB: event output port B
+      \arg        GPIO_EVENT_PORT_GPIOC: event output port C
+      \arg        GPIO_EVENT_PORT_GPIOD: event output port D
+      \arg        GPIO_EVENT_PORT_GPIOE: event output port E
+    \param[in]  output_pin:
+                only one parameter can be selected which are shown as below:
+      \arg        GPIO_EVENT_PIN_x(x=0..15)
+    \param[out] none
+    \retval     none
+*/
+void gpio_event_output_config(uint8_t output_port, uint8_t output_pin)
+{
+    uint32_t reg = 0U;
+    reg = AFIO_EC;
+
+    /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */
+    reg &= (uint32_t) (~(AFIO_EC_PORT | AFIO_EC_PIN));
+
+    reg |= (uint32_t) ((uint32_t) output_port << GPIO_OUTPUT_PORT_OFFSET);
+    reg |= (uint32_t) output_pin;
+
+    AFIO_EC = reg;
+}
+
+/*!
+    \brief      enable GPIO pin event output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_event_output_enable(void)
+{
+    AFIO_EC |= AFIO_EC_EOE;
+}
+
+/*!
+    \brief      disable GPIO pin event output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_event_output_disable(void)
+{
+    AFIO_EC &= (uint32_t) (~AFIO_EC_EOE);
+}
+
+/*!
+    \brief      lock GPIO pin
+    \param[in]  gpio_periph: GPIOx(x = A,B,C,D,E)
+    \param[in]  pin: GPIO pin
+                one or more parameters can be selected which are shown as below:
+      \arg        GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+    \param[out] none
+    \retval     none
+*/
+void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
+{
+    uint32_t lock = 0x00010000U;
+    lock |= pin;
+
+    /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */
+    GPIO_LOCK(gpio_periph) = (uint32_t) lock;
+    GPIO_LOCK(gpio_periph) = (uint32_t) pin;
+    GPIO_LOCK(gpio_periph) = (uint32_t) lock;
+    lock = GPIO_LOCK(gpio_periph);
+    lock = GPIO_LOCK(gpio_periph);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c
new file mode 100644
index 0000000000..1e6ab305c6
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c
@@ -0,0 +1,726 @@
+/*!
+    \file  gd32vf103_i2c.c
+    \brief I2C driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_i2c.h"
+
+/* I2C register bit mask */
+#define I2CCLK_MAX                    ((uint32_t)0x00000048U)             /*!< i2cclk maximum value */
+#define I2CCLK_MIN                    ((uint32_t)0x00000002U)             /*!< i2cclk minimum value */
+#define I2C_FLAG_MASK                 ((uint32_t)0x0000FFFFU)             /*!< i2c flag mask */
+#define I2C_ADDRESS_MASK              ((uint32_t)0x000003FFU)             /*!< i2c address mask */
+#define I2C_ADDRESS2_MASK             ((uint32_t)0x000000FEU)             /*!< the second i2c address mask */
+
+/* I2C register bit offset */
+#define STAT1_PECV_OFFSET             ((uint32_t)8U)     /* bit offset of PECV in I2C_STAT1 */
+
+/*!
+    \brief      reset I2C
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+ */
+void i2c_deinit(uint32_t i2c_periph) 
+{
+    switch (i2c_periph) {
+    case I2C0:
+        /* reset I2C0 */
+        rcu_periph_reset_enable(RCU_I2C0RST);
+        rcu_periph_reset_disable(RCU_I2C0RST);
+        break;
+    case I2C1:
+        /* reset I2C1 */
+        rcu_periph_reset_enable(RCU_I2C1RST);
+        rcu_periph_reset_disable(RCU_I2C1RST);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure I2C clock
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
+    \param[in]  dutycyc: duty cycle in fast mode
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_DTCY_2: T_low/T_high=2 
+    \arg        I2C_DTCY_16_9: T_low/T_high=16/9
+    \param[out] none
+    \retval     none
+ */
+void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) 
+{
+    uint32_t pclk1, clkc, freq, risetime;
+    uint32_t temp;
+
+    pclk1 = rcu_clock_freq_get(CK_APB1);
+    /* I2C peripheral clock frequency */
+    freq = (uint32_t) (pclk1 / 1000000U);
+    if (freq >= I2CCLK_MAX) {
+        freq = I2CCLK_MAX;
+    }
+    temp = I2C_CTL1(i2c_periph);
+    temp &= ~I2C_CTL1_I2CCLK;
+    temp |= freq;
+
+    I2C_CTL1(i2c_periph) = temp;
+
+    if (100000U >= clkspeed) {
+        /* the maximum SCL rise time is 1000ns in standard mode */
+        risetime = (uint32_t) ((pclk1 / 1000000U) + 1U);
+        if (risetime >= I2CCLK_MAX) {
+            I2C_RT(i2c_periph) = I2CCLK_MAX;
+        } else if (risetime <= I2CCLK_MIN) {
+            I2C_RT(i2c_periph) = I2CCLK_MIN;
+        } else {
+            I2C_RT(i2c_periph) = risetime;
+        }
+        clkc = (uint32_t) (pclk1 / (clkspeed * 2U));
+        if (clkc < 0x04U) {
+            /* the CLKC in standard mode minmum value is 4 */
+            clkc = 0x04U;
+        }
+        I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
+
+    } else if (400000U >= clkspeed) {
+        /* the maximum SCL rise time is 300ns in fast mode */
+        I2C_RT(i2c_periph) = (uint32_t) (((freq * (uint32_t) 300U)
+                / (uint32_t) 1000U) + (uint32_t) 1U);
+        if (I2C_DTCY_2 == dutycyc) {
+            /* I2C duty cycle is 2 */
+            clkc = (uint32_t) (pclk1 / (clkspeed * 3U));
+            I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
+        } else {
+            /* I2C duty cycle is 16/9 */
+            clkc = (uint32_t) (pclk1 / (clkspeed * 25U));
+            I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
+        }
+        if (0U == (clkc & I2C_CKCFG_CLKC)) {
+            /* the CLKC in fast mode minmum value is 1 */
+            clkc |= 0x0001U;
+        }
+        I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
+        I2C_CKCFG(i2c_periph) |= clkc;
+    } else {
+    }
+}
+
+/*!
+    \brief      configure I2C address 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  mode:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_I2CMODE_ENABLE: I2C mode
+    \arg        I2C_SMBUSMODE_ENABLE: SMBus mode
+    \param[in]  addformat: 7bits or 10bits
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_ADDFORMAT_7BITS: 7bits
+    \arg        I2C_ADDFORMAT_10BITS: 10bits
+    \param[in]  addr: I2C address
+    \param[out] none
+    \retval     none
+ */
+void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr) 
+{
+    /* SMBus/I2C mode selected */
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_SMBEN);
+    ctl |= mode;
+    I2C_CTL0(i2c_periph) = ctl;
+    /* configure address */
+    addr = addr & I2C_ADDRESS_MASK;
+    I2C_SADDR0(i2c_periph) = (addformat | addr);
+}
+
+/*!
+    \brief      SMBus type selection
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  type:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_SMBUS_DEVICE: device
+    \arg        I2C_SMBUS_HOST: host
+    \param[out] none
+    \retval     none
+ */
+void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
+{
+    if (I2C_SMBUS_HOST == type) {
+        I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
+    } else {
+        I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
+    }
+}
+
+/*!
+    \brief      whether or not to send an ACK
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  ack:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_ACK_ENABLE: ACK will be sent
+    \arg        I2C_ACK_DISABLE: ACK will not be sent
+    \param[out] none
+    \retval     none
+ */
+void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) 
+{
+    if (I2C_ACK_ENABLE == ack) {
+        I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
+    } else {
+        I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
+    }
+}
+
+/*!
+    \brief      configure I2C POAP position
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  pos:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
+    \arg        I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
+    \param[out] none
+    \retval     none
+ */
+void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) 
+{
+    /* configure I2C POAP position */
+    if (I2C_ACKPOS_NEXT == pos) {
+        I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
+    } else {
+        I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
+    }
+}
+
+/*!
+    \brief      master sends slave address
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  addr: slave address  
+    \param[in]  trandirection: transmitter or receiver
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_TRANSMITTER: transmitter  
+    \arg        I2C_RECEIVER:    receiver  
+    \param[out] none
+    \retval     none
+ */
+void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection) 
+{
+    /* master is a transmitter or a receiver */
+    if (I2C_TRANSMITTER == trandirection) {
+        addr = addr & I2C_TRANSMITTER;
+    } else {
+        addr = addr | I2C_RECEIVER;
+    }
+    /* send slave address */
+    I2C_DATA(i2c_periph) = addr;
+}
+
+/*!
+    \brief      configure I2C saddress1
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  addr: I2C address
+    \param[out] none
+    \retval     none
+*/
+void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr) 
+{
+    /* configure saddress1 */
+    I2C_SADDR1(i2c_periph) = (0xFE & addr);
+}
+
+/*!
+    \brief      enable dual-address mode
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  addr: the second address in dual-address mode
+    \param[out] none
+    \retval     none
+*/
+void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) 
+{
+    /* configure address */
+    addr = addr & I2C_ADDRESS2_MASK;
+    I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr);
+}
+
+/*!
+    \brief      disable dual-address mode
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
+    \param[out] none
+    \retval     none
+*/
+void i2c_dualaddr_disable(uint32_t i2c_periph)
+{
+    I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
+}
+
+/*!
+    \brief      enable I2C
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
+    \param[out] none
+    \retval     none
+ */
+void i2c_enable(uint32_t i2c_periph) 
+{
+    I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
+}
+
+/*!
+    \brief      disable I2C
+    \param[in]  i2c_periph: I2Cx(x=0,1) 
+    \param[out] none
+    \retval     none
+ */
+void i2c_disable(uint32_t i2c_periph) 
+{
+    I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
+}
+
+/*!
+    \brief      generate a START condition on I2C bus
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+ */
+void i2c_start_on_bus(uint32_t i2c_periph) 
+{
+    I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
+}
+
+/*!
+    \brief      generate a STOP condition on I2C bus
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     none
+ */
+void i2c_stop_on_bus(uint32_t i2c_periph)
+{
+    I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
+}
+
+/*!
+    \brief      I2C transmit data function
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  data: data of transmission 
+    \param[out] none
+    \retval     none
+ */
+void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) 
+{
+    I2C_DATA(i2c_periph) = DATA_TRANS(data);
+}
+
+/*!
+    \brief      I2C receive data function
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     data of received
+ */
+uint8_t i2c_data_receive(uint32_t i2c_periph) 
+{
+    return (uint8_t) DATA_RECV(I2C_DATA(i2c_periph));
+}
+
+/*!
+    \brief      enable I2C DMA mode 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  dmastate:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_DMA_ON: DMA mode enable
+    \arg        I2C_DMA_OFF: DMA mode disable
+    \param[out] none
+    \retval     none
+ */
+void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) 
+{
+    /* configure I2C DMA function */
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL1(i2c_periph);
+    ctl &= ~(I2C_CTL1_DMAON);
+    ctl |= dmastate;
+    I2C_CTL1(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      configure whether next DMA EOT is DMA last transfer or not
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  dmalast:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_DMALST_ON: next DMA EOT is the last transfer
+    \arg        I2C_DMALST_OFF: next DMA EOT is not the last transfer
+    \param[out] none
+    \retval     none
+ */
+void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) 
+{
+    /* configure DMA last transfer */
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL1(i2c_periph);
+    ctl &= ~(I2C_CTL1_DMALST);
+    ctl |= dmalast;
+    I2C_CTL1(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      whether to stretch SCL low when data is not ready in slave mode 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  stretchpara:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
+    \arg        I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
+    \param[out] none
+    \retval     none
+ */
+void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) 
+{
+    /* configure I2C SCL strerching enable or disable */
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_SS);
+    ctl |= stretchpara;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      whether or not to response to a general call 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  gcallpara:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_GCEN_ENABLE: slave will response to a general call
+    \arg        I2C_GCEN_DISABLE: slave will not response to a general call
+    \param[out] none
+    \retval     none
+ */
+void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
+{
+    /* configure slave response to a general call enable or disable */
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_GCEN);
+    ctl |= gcallpara;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      software reset I2C 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  sreset:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_SRESET_SET: I2C is under reset
+    \arg        I2C_SRESET_RESET: I2C is not under reset
+    \param[out] none
+    \retval     none
+ */
+void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
+{
+    /* modify CTL0 and configure software reset I2C state */
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_SRESET);
+    ctl |= sreset;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      I2C PEC calculation on or off
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  pecpara:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_PEC_ENABLE: PEC calculation on 
+    \arg        I2C_PEC_DISABLE: PEC calculation off 
+    \param[out] none
+    \retval     none
+ */
+void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) 
+{
+    /* on/off PEC calculation */
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_PECEN);
+    ctl |= pecstate;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      I2C whether to transfer PEC value
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  pecpara:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_PECTRANS_ENABLE: transfer PEC 
+    \arg        I2C_PECTRANS_DISABLE: not transfer PEC 
+    \param[out] none
+    \retval     none
+ */
+void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) 
+{
+    /* whether to transfer PEC */
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_PECTRANS);
+    ctl |= pecpara;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      get packet error checking value 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[out] none
+    \retval     PEC value
+ */
+uint8_t i2c_pec_value_get(uint32_t i2c_periph) 
+{
+    return (uint8_t) ((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>> STAT1_PECV_OFFSET);
+}
+
+/*!
+    \brief      I2C issue alert through SMBA pin 
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  smbuspara:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_SALTSEND_ENABLE: issue alert through SMBA pin 
+    \arg        I2C_SALTSEND_DISABLE: not issue alert through SMBA pin 
+    \param[out] none
+    \retval     none
+ */
+void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) 
+{
+    /* issue alert through SMBA pin configure*/
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_SALT);
+    ctl |= smbuspara;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      enable or disable I2C ARP protocol in SMBus switch
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  arpstate:
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_ARP_ENABLE: enable ARP
+    \arg        I2C_ARP_DISABLE: disable ARP
+    \param[out] none
+    \retval     none
+ */
+void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
+{
+    /* enable or disable I2C ARP protocol*/
+    uint32_t ctl = 0U;
+
+    ctl = I2C_CTL0(i2c_periph);
+    ctl &= ~(I2C_CTL0_ARPEN);
+    ctl |= arpstate;
+    I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+    \brief      check I2C flag is set or not
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  flag: I2C flags, refer to i2c_flag_enum
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_FLAG_SBSEND: start condition send out 
+    \arg        I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
+    \arg        I2C_FLAG_BTC: byte transmission finishes
+    \arg        I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
+    \arg        I2C_FLAG_STPDET: stop condition detected in slave mode
+    \arg        I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
+    \arg        I2C_FLAG_TBE: I2C_DATA is empty during transmitting
+    \arg        I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
+    \arg        I2C_FLAG_LOSTARB: arbitration lost in master mode
+    \arg        I2C_FLAG_AERR: acknowledge error
+    \arg        I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
+    \arg        I2C_FLAG_PECERR: PEC error when receiving data
+    \arg        I2C_FLAG_SMBTO: timeout signal in SMBus mode
+    \arg        I2C_FLAG_SMBALT: SMBus alert status
+    \arg        I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
+    \arg        I2C_FLAG_I2CBSY: busy flag
+    \arg        I2C_FLAG_TR: whether the I2C is a transmitter or a receiver
+    \arg        I2C_FLAG_RXGC: general call address (00h) received
+    \arg        I2C_FLAG_DEFSMB: default address of SMBus device
+    \arg        I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
+    \arg        I2C_FLAG_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+ */
+FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) 
+{
+    if (RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear I2C flag
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  flag: I2C flags, refer to i2c_flag_enum
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_FLAG_SMBALT: SMBus Alert status
+    \arg        I2C_FLAG_SMBTO: timeout signal in SMBus mode
+    \arg        I2C_FLAG_PECERR: PEC error when receiving data
+    \arg        I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode    
+    \arg        I2C_FLAG_AERR: acknowledge error
+    \arg        I2C_FLAG_LOSTARB: arbitration lost in master mode   
+    \arg        I2C_FLAG_BERR: a bus error   
+    \arg        I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
+    \param[out] none
+    \retval     none
+ */
+void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) 
+{
+    uint32_t temp;
+    if (I2C_FLAG_ADDSEND == flag) {
+        /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
+        temp = I2C_STAT0(i2c_periph);
+        temp = I2C_STAT1(i2c_periph);
+    } else {
+        I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag));
+    }
+}
+
+/*!
+    \brief      enable I2C interrupt
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  interrupt: I2C interrupts, refer to i2c_interrupt_enum
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_INT_ERR: error interrupt enable 
+    \arg        I2C_INT_EV: event interrupt enable 
+    \arg        I2C_INT_BUF: buffer interrupt enable
+    \param[out] none
+    \retval     none
+ */
+void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) 
+{
+    I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt));
+}
+
+/*!
+    \brief      disable I2C interrupt
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  interrupt: I2C interrupts, refer to i2c_flag_enum
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_INT_ERR: error interrupt enable 
+    \arg        I2C_INT_EV: event interrupt enable 
+    \arg        I2C_INT_BUF: buffer interrupt enable
+    \param[out] none
+    \retval     none
+ */
+void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) 
+{
+    I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt));
+}
+
+/*!
+    \brief      check I2C interrupt flag
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
+    \arg        I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
+    \arg        I2C_INT_FLAG_BTC: byte transmission finishes
+    \arg        I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
+    \arg        I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
+    \arg        I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
+    \arg        I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
+    \arg        I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
+    \arg        I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
+    \arg        I2C_INT_FLAG_AERR: acknowledge error interrupt flag
+    \arg        I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
+    \arg        I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
+    \arg        I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
+    \arg        I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+ */
+FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag) 
+{
+    uint32_t intenable = 0U, flagstatus = 0U, bufie;
+
+    /* check BUFIE */
+    bufie = I2C_CTL1(i2c_periph) & I2C_CTL1_BUFIE;
+
+    /* get the interrupt enable bit status */
+    intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
+    /* get the corresponding flag bit status */
+    flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag)& BIT(I2C_BIT_POS2(int_flag)));
+
+    if ((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) {
+        if (intenable && bufie) {
+            intenable = 1U;
+        } else {
+            intenable = 0U;
+        }
+    }
+    if ((0U != flagstatus) && (0U != intenable)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear I2C interrupt flag
+    \param[in]  i2c_periph: I2Cx(x=0,1)
+    \param[in]  int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
+                only one parameter can be selected which is shown as below:
+    \arg        I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
+    \arg        I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
+    \arg        I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
+    \arg        I2C_INT_FLAG_AERR: acknowledge error interrupt flag
+    \arg        I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
+    \arg        I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
+    \arg        I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
+    \arg        I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
+    \param[out] none
+    \retval     none
+ */
+void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag) 
+{
+    uint32_t temp;
+    if (I2C_INT_FLAG_ADDSEND == int_flag) {
+        /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
+        temp = I2C_STAT0(i2c_periph);
+        temp = I2C_STAT1(i2c_periph);
+    } else {
+        I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag));
+    }
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c
new file mode 100644
index 0000000000..905cec75c3
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c
@@ -0,0 +1,270 @@
+/*!
+    \file    gd32vf103_pmu.c
+    \brief   PMU driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_pmu.h"
+#include "riscv_encoding.h"
+
+/*!
+    \brief      reset PMU register
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_deinit(void)
+{
+	/* reset PMU */
+	rcu_periph_reset_enable(RCU_PMURST);
+	rcu_periph_reset_disable(RCU_PMURST);
+}
+
+/*!
+    \brief      select low voltage detector threshold
+    \param[in]  lvdt_n:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_LVDT_0: voltage threshold is 2.2V
+      \arg        PMU_LVDT_1: voltage threshold is 2.3V
+      \arg        PMU_LVDT_2: voltage threshold is 2.4V
+      \arg        PMU_LVDT_3: voltage threshold is 2.5V
+      \arg        PMU_LVDT_4: voltage threshold is 2.6V
+      \arg        PMU_LVDT_5: voltage threshold is 2.7V
+      \arg        PMU_LVDT_6: voltage threshold is 2.8V
+      \arg        PMU_LVDT_7: voltage threshold is 2.9V
+    \param[out] none
+    \retval     none
+*/
+void pmu_lvd_select(uint32_t lvdt_n)
+{
+	/* disable LVD */
+	PMU_CTL &= ~PMU_CTL_LVDEN;
+	/* clear LVDT bits */
+	PMU_CTL &= ~PMU_CTL_LVDT;
+	/* set LVDT bits according to lvdt_n */
+	PMU_CTL |= lvdt_n;
+	/* enable LVD */
+	PMU_CTL |= PMU_CTL_LVDEN;
+}
+
+/*!
+    \brief      disable PMU lvd
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_lvd_disable(void)
+{
+	/* disable LVD */
+	PMU_CTL &= ~PMU_CTL_LVDEN;
+}
+
+/*!
+    \brief      PMU work at sleep mode
+    \param[in]  sleepmodecmd:
+                only one parameter can be selected which is shown as below:
+      \arg        WFI_CMD: use WFI command
+      \arg        WFE_CMD: use WFE command
+    \param[out] none
+    \retval     none
+*/
+void pmu_to_sleepmode(uint8_t sleepmodecmd)
+{
+    /* clear sleepdeep bit of Cortex-M3 system control register */
+	clear_csr(0x811, 0x1);
+
+    /* select WFI or WFE command to enter sleep mode */
+    if(WFI_CMD == sleepmodecmd){
+        __WFI();
+    }else{
+    	clear_csr(mstatus, MSTATUS_MIE);
+    	set_csr(0x810, 0x1);
+    	__WFI();
+    	clear_csr(0x810, 0x1);
+    	set_csr(mstatus, MSTATUS_MIE);
+    }
+}
+
+/*!
+    \brief      PMU work at deepsleep mode
+    \param[in]  ldo:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode
+      \arg        PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
+    \param[in]  deepsleepmodecmd:
+                only one parameter can be selected which is shown as below:
+      \arg        WFI_CMD: use WFI command
+      \arg        WFE_CMD: use WFE command
+    \param[out] none
+    \retval     none
+*/
+void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
+{
+	/* clear stbmod and ldolp bits */
+    PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
+    /* set ldolp bit according to pmu_ldo */
+    PMU_CTL |= ldo;
+    /* set CSR_SLEEPVALUE bit of RISC-V system control register */
+    set_csr(0x811, 0x1);
+    /* select WFI or WFE command to enter deepsleep mode */
+    if(WFI_CMD == deepsleepmodecmd){
+        __WFI();
+    }else{
+    	clear_csr(mstatus, MSTATUS_MIE);
+    	set_csr(0x810, 0x1);
+    	__WFI();
+    	clear_csr(0x810, 0x1);
+    	set_csr(mstatus, MSTATUS_MIE);
+    }
+    /* reset sleepdeep bit of RISC-V system control register */
+    clear_csr(0x811, 0x1);
+}
+
+/*!
+    \brief      pmu work at standby mode
+    \param[in]  standbymodecmd:
+                only one parameter can be selected which is shown as below:
+      \arg        WFI_CMD: use WFI command
+      \arg        WFE_CMD: use WFE command
+    \param[out] none
+    \retval     none
+*/
+void pmu_to_standbymode(uint8_t standbymodecmd)
+{
+    /* set CSR_SLEEPVALUE bit of RISC-V system control register */
+	set_csr(0x811, 0x1);
+
+    /* set stbmod bit */
+    PMU_CTL |= PMU_CTL_STBMOD;
+
+    /* reset wakeup flag */
+    PMU_CTL |= PMU_CTL_WURST;
+
+    /* select WFI or WFE command to enter standby mode */
+    if(WFI_CMD == standbymodecmd){
+        __WFI();
+    }else{
+    	clear_csr(mstatus, MSTATUS_MIE);
+    	set_csr(0x810, 0x1);
+    	__WFI();
+    	clear_csr(0x810, 0x1);
+    	set_csr(mstatus, MSTATUS_MIE);
+    }
+    clear_csr(0x811, 0x1);
+}
+
+/*!
+    \brief      enable wakeup pin
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_wakeup_pin_enable(void)
+{
+	PMU_CS |= PMU_CS_WUPEN;
+}
+
+/*!
+    \brief      disable wakeup pin
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_wakeup_pin_disable(void)
+{
+	PMU_CS &= ~PMU_CS_WUPEN;
+}
+
+/*!
+    \brief      enable write access to the registers in backup domain
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_backup_write_enable(void)
+{
+    PMU_CTL |= PMU_CTL_BKPWEN;
+}
+
+/*!
+    \brief      disable write access to the registers in backup domain
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void pmu_backup_write_disable(void)
+{
+    PMU_CTL &= ~PMU_CTL_BKPWEN;
+}
+
+/*!
+    \brief      get flag state
+    \param[in]  flag:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_FLAG_WAKEUP: wakeup flag
+      \arg        PMU_FLAG_STANDBY: standby flag
+      \arg        PMU_FLAG_LVD: lvd flag
+    \param[out] none
+    \retval     FlagStatus SET or RESET
+*/
+FlagStatus pmu_flag_get(uint32_t flag)
+{
+    if(PMU_CS & flag){
+        return  SET;
+    }else{
+        return  RESET;
+    }
+}
+
+/*!
+    \brief      clear flag bit
+    \param[in]  flag_reset:
+                only one parameter can be selected which is shown as below:
+      \arg        PMU_FLAG_RESET_WAKEUP: reset wakeup flag
+      \arg        PMU_FLAG_RESET_STANDBY: reset standby flag
+    \param[out] none
+    \retval     none
+*/
+void pmu_flag_clear(uint32_t flag_reset)
+{
+    switch(flag_reset){
+    case PMU_FLAG_RESET_WAKEUP:
+        /* reset wakeup flag */
+        PMU_CTL |= PMU_CTL_WURST;
+        break;
+    case PMU_FLAG_RESET_STANDBY:
+        /* reset standby flag */
+        PMU_CTL |= PMU_CTL_STBRST;
+        break;
+    default :
+        break;
+    }
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c
new file mode 100644
index 0000000000..b2c0d83052
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c
@@ -0,0 +1,1111 @@
+/*!
+    \file    gd32vf103_rcu.c
+    \brief   RCU driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_rcu.h"
+
+/* define clock source */
+#define SEL_IRC8M                   ((uint16_t)0U)
+#define SEL_HXTAL                   ((uint16_t)1U)
+#define SEL_PLL                     ((uint16_t)2U)
+
+/* define startup timeout count */
+#define OSC_STARTUP_TIMEOUT         ((uint32_t)0xFFFFFU)
+#define LXTAL_STARTUP_TIMEOUT       ((uint32_t)0x3FFFFFFU)
+
+/*!
+    \brief      deinitialize the RCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_deinit(void)
+{
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+    rcu_osci_stab_wait(RCU_IRC8M);
+
+    /* reset CFG0 register */
+    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
+                  RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
+                  RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
+    /* reset CTL register */
+    RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
+    RCU_CTL &= ~RCU_CTL_HXTALBPS;
+    RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN);
+    /* reset INT and CFG1 register */
+    RCU_INT = 0x00ff0000U;
+    RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF |
+                  RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL);
+}
+
+/*!
+    \brief      enable the peripherals clock
+    \param[in]  periph: RCU peripherals, refer to rcu_periph_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock
+      \arg        RCU_AF : alternate function clock
+      \arg        RCU_CRC: CRC clock
+      \arg        RCU_DMAx (x=0,1): DMA clock
+      \arg        RCU_USBFS: USBFS clock
+      \arg        RCU_EXMC: EXMC clock
+      \arg        RCU_TIMERx (x=0,1,2,3,4,5,6): TIMER clock
+      \arg        RCU_WWDGT: WWDGT clock
+      \arg        RCU_SPIx (x=0,1,2): SPI clock
+      \arg        RCU_USARTx (x=0,1,2): USART clock
+      \arg        RCU_UARTx (x=3,4): UART clock
+      \arg        RCU_I2Cx (x=0,1): I2C clock
+      \arg        RCU_CANx (x=0,1): CAN clock
+      \arg        RCU_PMU: PMU clock
+      \arg        RCU_DAC: DAC clock
+      \arg        RCU_RTC: RTC clock
+      \arg        RCU_ADCx (x=0,1): ADC clock
+      \arg        RCU_BKPI: BKP interface clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_clock_enable(rcu_periph_enum periph)
+{
+    RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+    \brief      disable the peripherals clock
+    \param[in]  periph: RCU peripherals, refer to rcu_periph_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock
+      \arg        RCU_AF: alternate function clock
+      \arg        RCU_CRC: CRC clock
+      \arg        RCU_DMAx (x=0,1): DMA clock
+      \arg        RCU_USBFS: USBFS clock
+      \arg        RCU_EXMC: EXMC clock
+      \arg        RCU_TIMERx (x=0,1,2,3,4,5,6): TIMER clock
+      \arg        RCU_WWDGT: WWDGT clock
+      \arg        RCU_SPIx (x=0,1,2): SPI clock
+      \arg        RCU_USARTx (x=0,1,2): USART clock
+      \arg        RCU_UARTx (x=3,4): UART clock
+      \arg        RCU_I2Cx (x=0,1): I2C clock
+      \arg        RCU_CANx (x=0,1): CAN clock
+      \arg        RCU_PMU: PMU clock
+      \arg        RCU_DAC: DAC clock
+      \arg        RCU_RTC: RTC clock
+      \arg        RCU_ADCx (x=0,1): ADC clock
+      \arg        RCU_BKPI: BKP interface clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_clock_disable(rcu_periph_enum periph)
+{
+    RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+    \brief      enable the peripherals clock when sleep mode
+    \param[in]  periph: RCU peripherals, refer to rcu_periph_sleep_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_FMC_SLP: FMC clock
+      \arg        RCU_SRAM_SLP: SRAM clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
+{
+    RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+    \brief      disable the peripherals clock when sleep mode
+    \param[in]  periph: RCU peripherals, refer to rcu_periph_sleep_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_FMC_SLP: FMC clock
+      \arg        RCU_SRAM_SLP: SRAM clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
+{
+    RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+    \brief      reset the peripherals
+    \param[in]  periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports
+      \arg        RCU_AFRST : reset alternate function clock
+      \arg        RCU_USBFSRST: reset USBFS
+      \arg        RCU_TIMERxRST (x=0,1,2,3,4,5,6): reset TIMER
+      \arg        RCU_WWDGTRST: reset WWDGT
+      \arg        RCU_SPIxRST (x=0,1,2): reset SPI
+      \arg        RCU_USARTxRST (x=0,1,2): reset USART
+      \arg        RCU_UARTxRST (x=3,4): reset UART
+      \arg        RCU_I2CxRST (x=0,1): reset I2C
+      \arg        RCU_CANxRST (x=0,1): reset CAN
+      \arg        RCU_PMURST: reset PMU
+      \arg        RCU_DACRST: reset DAC
+      \arg        RCU_ADCxRST (x=0,1): reset ADC
+      \arg        RCU_BKPIRST: reset BKPI
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
+{
+    RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
+}
+
+/*!
+    \brief      disable reset the peripheral
+    \param[in]  periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports
+      \arg        RCU_AFRST : reset alternate function clock
+      \arg        RCU_USBFSRST: reset USBFS
+      \arg        RCU_TIMERxRST (x=0,1,2,3,4,5,6): reset TIMER
+      \arg        RCU_WWDGTRST: reset WWDGT
+      \arg        RCU_SPIxRST (x=0,1,2): reset SPI
+      \arg        RCU_USARTxRST (x=0,1,2): reset USART
+      \arg        RCU_UARTxRST (x=3,4): reset UART
+      \arg        RCU_I2CxRST (x=0,1): reset I2C
+      \arg        RCU_CANxRST (x=0,1): reset CAN
+      \arg        RCU_PMURST: reset PMU
+      \arg        RCU_DACRST: reset DAC
+      \arg        RCU_ADCxRST (x=0,1): reset ADC
+      \arg        RCU_BKPIRST: reset BKPI
+    \param[out] none
+    \retval     none
+*/
+void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
+{
+    RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
+}
+
+/*!
+    \brief      reset the BKP domain
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_bkp_reset_enable(void)
+{
+    RCU_BDCTL |= RCU_BDCTL_BKPRST;
+}
+
+/*!
+    \brief      disable the BKP domain reset
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_bkp_reset_disable(void)
+{
+    RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
+}
+
+/*!
+    \brief      configure the system clock source
+    \param[in]  ck_sys: system clock source select
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
+      \arg        RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
+      \arg        RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
+    \param[out] none
+    \retval     none
+*/
+void rcu_system_clock_source_config(uint32_t ck_sys)
+{
+    uint32_t reg;
+    
+    reg = RCU_CFG0;
+    /* reset the SCS bits and set according to ck_sys */
+    reg &= ~RCU_CFG0_SCS;
+    RCU_CFG0 = (reg | ck_sys);
+}
+
+/*!
+    \brief      get the system clock source
+    \param[in]  none
+    \param[out] none
+    \retval     which clock is selected as CK_SYS source
+      \arg        RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source
+      \arg        RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source
+      \arg        RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source
+*/
+uint32_t rcu_system_clock_source_get(void)
+{
+    return (RCU_CFG0 & RCU_CFG0_SCSS);
+}
+
+/*!
+    \brief      configure the AHB clock prescaler selection
+    \param[in]  ck_ahb: AHB clock prescaler selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
+    \param[out] none
+    \retval     none
+*/
+void rcu_ahb_clock_config(uint32_t ck_ahb)
+{
+    uint32_t reg;
+    
+    reg = RCU_CFG0;
+
+    /* reset the AHBPSC bits and set according to ck_ahb */
+    reg &= ~RCU_CFG0_AHBPSC;
+    RCU_CFG0 = (reg | ck_ahb);
+}
+
+/*!
+    \brief      configure the APB1 clock prescaler selection
+    \param[in]  ck_apb1: APB1 clock prescaler selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
+      \arg        RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
+      \arg        RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
+      \arg        RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
+      \arg        RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
+    \param[out] none
+    \retval     none
+*/
+void rcu_apb1_clock_config(uint32_t ck_apb1)
+{
+    uint32_t reg;
+    
+    reg = RCU_CFG0;
+
+    /* reset the APB1PSC and set according to ck_apb1 */
+    reg &= ~RCU_CFG0_APB1PSC;
+    RCU_CFG0 = (reg | ck_apb1);
+}
+
+/*!
+    \brief      configure the APB2 clock prescaler selection
+    \param[in]  ck_apb2: APB2 clock prescaler selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
+      \arg        RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
+      \arg        RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
+      \arg        RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
+      \arg        RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
+    \param[out] none
+    \retval     none
+*/
+void rcu_apb2_clock_config(uint32_t ck_apb2)
+{
+    uint32_t reg;
+    
+    reg = RCU_CFG0;
+
+    /* reset the APB2PSC and set according to ck_apb2 */
+    reg &= ~RCU_CFG0_APB2PSC;
+    RCU_CFG0 = (reg | ck_apb2);
+}
+
+/*!
+    \brief      configure the CK_OUT0 clock source
+    \param[in]  ckout0_src: CK_OUT0 clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_CKOUT0SRC_NONE: no clock selected
+      \arg        RCU_CKOUT0SRC_CKSYS: system clock selected
+      \arg        RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected
+      \arg        RCU_CKOUT0SRC_HXTAL: HXTAL selected
+      \arg        RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected
+      \arg        RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected
+      \arg        RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected
+      \arg        RCU_CKOUT0SRC_EXT1: EXT1 selected
+      \arg        RCU_CKOUT0SRC_CKPLL2: PLL2 selected
+    \param[out] none
+    \retval     none
+*/
+void rcu_ckout0_config(uint32_t ckout0_src)
+{
+    uint32_t reg;
+    
+    reg = RCU_CFG0;
+
+    /* reset the CKOUT0SRC, set according to ckout0_src */
+    reg &= ~RCU_CFG0_CKOUT0SEL;
+    RCU_CFG0 = (reg | ckout0_src);
+}
+
+/*!
+    \brief      configure the main PLL clock 
+    \param[in]  pll_src: PLL clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL
+      \arg        RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL
+    \param[in]  pll_mul: PLL clock multiplication factor
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PLL_MULx (x = 2..14, 6.5, 16..32)
+    \param[out] none
+    \retval     none
+*/
+void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
+{
+    uint32_t reg = 0U;
+
+    reg = RCU_CFG0;
+
+    /* PLL clock source and multiplication factor configuration */
+    reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    reg |= (pll_src | pll_mul);
+
+    RCU_CFG0 = reg;
+}
+
+/*!
+    \brief      configure the PREDV0 division factor and clock source
+    \param[in]  predv0_source: PREDV0 input clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock
+      \arg        RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock
+    \param[in]  predv0_div: PREDV0 division factor
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PREDV0_DIVx, x = 1..16
+    \param[out] none
+    \retval     none
+*/
+void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div)
+{
+    uint32_t reg = 0U;
+    
+    reg = RCU_CFG1;
+    /* reset PREDV0SEL and PREDV0 bits */
+    reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0);
+    /* set the PREDV0SEL and PREDV0 division factor */
+    reg |= (predv0_source | predv0_div);
+
+    RCU_CFG1 = reg;
+}
+
+/*!
+    \brief      configure the PREDV1 division factor
+    \param[in]  predv1_div: PREDV1 division factor
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PREDV1_DIVx, x = 1..16
+    \param[out] none
+    \retval     none
+*/
+void rcu_predv1_config(uint32_t predv1_div)
+{
+    uint32_t reg = 0U;
+    
+    reg = RCU_CFG1;
+    /* reset the PREDV1 bits */
+    reg &= ~RCU_CFG1_PREDV1;
+    /* set the PREDV1 division factor */
+    reg |= predv1_div;
+
+    RCU_CFG1 = reg;
+}
+
+/*!
+    \brief      configure the PLL1 clock 
+    \param[in]  pll_mul: PLL clock multiplication factor
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PLL1_MULx (x = 8..16, 20)
+    \param[out] none
+    \retval     none
+*/
+void rcu_pll1_config(uint32_t pll_mul)
+{
+    RCU_CFG1 &= ~RCU_CFG1_PLL1MF;
+    RCU_CFG1 |= pll_mul;
+}
+
+/*!
+    \brief      configure the PLL2 clock 
+    \param[in]  pll_mul: PLL clock multiplication factor
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_PLL2_MULx (x = 8..16, 20)
+    \param[out] none
+    \retval     none
+*/
+void rcu_pll2_config(uint32_t pll_mul)
+{
+    RCU_CFG1 &= ~RCU_CFG1_PLL2MF;
+    RCU_CFG1 |= pll_mul; 
+}
+
+/*!
+    \brief      configure the ADC prescaler factor
+    \param[in]  adc_psc: ADC prescaler factor
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2
+      \arg        RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4
+      \arg        RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6
+      \arg        RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8
+      \arg        RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12
+      \arg        RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16
+    \param[out] none
+    \retval     none
+*/
+void rcu_adc_clock_config(uint32_t adc_psc)
+{
+    uint32_t reg0;
+
+    /* reset the ADCPSC bits */
+    reg0 = RCU_CFG0;
+    reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC);
+
+    /* set the ADC prescaler factor */
+    switch(adc_psc){
+        case RCU_CKADC_CKAPB2_DIV2:
+        case RCU_CKADC_CKAPB2_DIV4:
+        case RCU_CKADC_CKAPB2_DIV6:
+        case RCU_CKADC_CKAPB2_DIV8:
+            reg0 |= (adc_psc << 14);
+            break;
+
+        case RCU_CKADC_CKAPB2_DIV12:
+        case RCU_CKADC_CKAPB2_DIV16:
+            adc_psc &= ~BIT(2);
+            reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2);
+            break;
+
+        default:
+            break;
+    }
+
+    /* set the register */
+    RCU_CFG0 = reg0;
+}
+
+/*!
+    \brief      configure the USBFS prescaler factor
+    \param[in]  usb_psc: USB prescaler factor
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_CKUSB_CKPLL_DIV1_5: USBFS prescaler select CK_PLL/1.5
+      \arg        RCU_CKUSB_CKPLL_DIV1: USBFS prescaler select CK_PLL/1
+      \arg        RCU_CKUSB_CKPLL_DIV2_5: USBFS prescaler select CK_PLL/2.5
+      \arg        RCU_CKUSB_CKPLL_DIV2: USBFS prescaler select CK_PLL/2
+    \param[out] none
+    \retval     none
+*/
+void rcu_usb_clock_config(uint32_t usb_psc)
+{
+    uint32_t reg;
+    
+    reg = RCU_CFG0;
+
+    /* configure the USBFS prescaler factor */
+    reg &= ~RCU_CFG0_USBFSPSC;
+    RCU_CFG0 = (reg | usb_psc);
+}
+
+/*!
+    \brief      configure the RTC clock source selection
+    \param[in]  rtc_clock_source: RTC clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_RTCSRC_NONE: no clock selected
+      \arg        RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
+      \arg        RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
+      \arg        RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_rtc_clock_config(uint32_t rtc_clock_source)
+{
+    uint32_t reg;
+    
+    reg = RCU_BDCTL; 
+    /* reset the RTCSRC bits and set according to rtc_clock_source */
+    reg &= ~RCU_BDCTL_RTCSRC;
+    RCU_BDCTL = (reg | rtc_clock_source);
+}
+
+/*!
+    \brief      configure the I2S1 clock source selection
+    \param[in]  i2s_clock_source: I2S1 clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock
+      \arg        RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_i2s1_clock_config(uint32_t i2s_clock_source)
+{
+    uint32_t reg;
+    
+    reg = RCU_CFG1; 
+    /* reset the I2S1SEL bit and set according to i2s_clock_source */
+    reg &= ~RCU_CFG1_I2S1SEL;
+    RCU_CFG1 = (reg | i2s_clock_source);
+}
+
+/*!
+    \brief      configure the I2S2 clock source selection
+    \param[in]  i2s_clock_source: I2S2 clock source selection
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock
+      \arg        RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock
+    \param[out] none
+    \retval     none
+*/
+void rcu_i2s2_clock_config(uint32_t i2s_clock_source)
+{
+    uint32_t reg;
+    
+    reg = RCU_CFG1; 
+    /* reset the I2S2SEL bit and set according to i2s_clock_source */
+    reg &= ~RCU_CFG1_I2S2SEL;
+    RCU_CFG1 = (reg | i2s_clock_source);
+}
+
+/*!
+    \brief      get the clock stabilization and periphral reset flags
+    \param[in]  flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
+      \arg        RCU_FLAG_HXTALSTB: HXTAL stabilization flag
+      \arg        RCU_FLAG_PLLSTB: PLL stabilization flag
+      \arg        RCU_FLAG_PLL1STB: PLL1 stabilization flag
+      \arg        RCU_FLAG_PLL2STB: PLL2 stabilization flag
+      \arg        RCU_FLAG_LXTALSTB: LXTAL stabilization flag
+      \arg        RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
+      \arg        RCU_FLAG_EPRST: external PIN reset flag
+      \arg        RCU_FLAG_PORRST: power reset flag
+      \arg        RCU_FLAG_SWRST: software reset flag
+      \arg        RCU_FLAG_FWDGTRST: free watchdog timer reset flag
+      \arg        RCU_FLAG_WWDGTRST: window watchdog timer reset flag
+      \arg        RCU_FLAG_LPRST: low-power reset flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus rcu_flag_get(rcu_flag_enum flag)
+{
+    /* get the rcu flag */
+    if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear all the reset flag
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_all_reset_flag_clear(void)
+{
+    RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
+}
+
+/*!
+    \brief      get the clock stabilization interrupt and ckm flags
+    \param[in]  int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
+      \arg        RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
+      \arg        RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
+      \arg        RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
+      \arg        RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
+      \arg        RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag
+      \arg        RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag
+      \arg        RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
+{
+    /* get the rcu interrupt flag */
+    if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear the interrupt flags
+    \param[in]  int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear
+      \arg        RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
+    \param[out] none
+    \retval     none
+*/
+void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
+{
+    RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
+}
+
+/*!
+    \brief      enable the stabilization interrupt
+    \param[in]  stab_int: clock stabilization interrupt, refer to rcu_int_enum
+                Only one parameter can be selected which is shown as below:
+      \arg        RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
+      \arg        RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
+      \arg        RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
+      \arg        RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
+      \arg        RCU_INT_PLLSTB: PLL stabilization interrupt enable
+      \arg        RCU_INT_PLL1STB: PLL1 stabilization interrupt enable
+      \arg        RCU_INT_PLL2STB: PLL2 stabilization interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void rcu_interrupt_enable(rcu_int_enum stab_int)
+{
+    RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
+}
+
+/*!
+    \brief      disable the stabilization interrupt
+    \param[in]  stab_int: clock stabilization interrupt, refer to rcu_int_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
+      \arg        RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
+      \arg        RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
+      \arg        RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
+      \arg        RCU_INT_PLLSTB: PLL stabilization interrupt enable
+      \arg        RCU_INT_PLL1STB: PLL1 stabilization interrupt enable
+      \arg        RCU_INT_PLL2STB: PLL2 stabilization interrupt enable
+    \param[out] none
+    \retval     none
+*/
+void rcu_interrupt_disable(rcu_int_enum stab_int)
+{
+    RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
+}
+
+/*!
+    \brief      wait for oscillator stabilization flags is SET or oscillator startup is timeout
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: high speed crystal oscillator(HXTAL)
+      \arg        RCU_LXTAL: low speed crystal oscillator(LXTAL)
+      \arg        RCU_IRC8M: internal 8M RC oscillators(IRC8M)
+      \arg        RCU_IRC40K: internal 40K RC oscillator(IRC40K)
+      \arg        RCU_PLL_CK: phase locked loop(PLL)
+      \arg        RCU_PLL1_CK: phase locked loop 1
+      \arg        RCU_PLL2_CK: phase locked loop 2
+    \param[out] none
+    \retval     ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
+{
+    uint32_t stb_cnt = 0U;
+    ErrStatus reval = ERROR;
+    FlagStatus osci_stat = RESET;
+    
+    switch(osci){
+    /* wait HXTAL stable */
+    case RCU_HXTAL:
+        while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
+            stb_cnt++;
+        }
+
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
+            reval = SUCCESS;
+        }
+        break;
+
+    /* wait LXTAL stable */
+    case RCU_LXTAL:
+        while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
+            stb_cnt++;
+        }
+
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
+            reval = SUCCESS;
+        }
+        break;
+
+    /* wait IRC8M stable */
+    case RCU_IRC8M:
+        while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
+            stb_cnt++;
+        }
+
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
+            reval = SUCCESS;
+        }
+        break;
+
+    /* wait IRC40K stable */
+    case RCU_IRC40K:
+        while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
+            stb_cnt++;
+        }
+
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
+            reval = SUCCESS;
+        }
+        break;
+
+    /* wait PLL stable */
+    case RCU_PLL_CK:
+        while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
+            stb_cnt++;
+        }
+
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
+            reval = SUCCESS;
+        }
+        break;
+    /* wait PLL1 stable */
+    case RCU_PLL1_CK:
+        while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
+            stb_cnt++;
+        }
+
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){
+            reval = SUCCESS;
+        }
+        break;
+    /* wait PLL2 stable */
+    case RCU_PLL2_CK:
+        while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+            osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
+            stb_cnt++;
+        }
+
+        /* check whether flag is set or not */
+        if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){
+            reval = SUCCESS;
+        }
+        break;
+
+    default:
+        break;
+    }
+
+    /* return value */
+    return reval;
+}
+
+/*!
+    \brief      turn on the oscillator
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: high speed crystal oscillator(HXTAL)
+      \arg        RCU_LXTAL: low speed crystal oscillator(LXTAL)
+      \arg        RCU_IRC8M: internal 8M RC oscillators(IRC8M)
+      \arg        RCU_IRC40K: internal 40K RC oscillator(IRC40K)
+      \arg        RCU_PLL_CK: phase locked loop(PLL)
+      \arg        RCU_PLL1_CK: phase locked loop 1
+      \arg        RCU_PLL2_CK: phase locked loop 2
+    \param[out] none
+    \retval     none
+*/
+void rcu_osci_on(rcu_osci_type_enum osci)
+{
+    RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
+}
+
+/*!
+    \brief      turn off the oscillator
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: high speed crystal oscillator(HXTAL)
+      \arg        RCU_LXTAL: low speed crystal oscillator(LXTAL)
+      \arg        RCU_IRC8M: internal 8M RC oscillators(IRC8M)
+      \arg        RCU_IRC40K: internal 40K RC oscillator(IRC40K)
+      \arg        RCU_PLL_CK: phase locked loop(PLL)
+      \arg        RCU_PLL1_CK: phase locked loop 1
+      \arg        RCU_PLL2_CK: phase locked loop 2
+    \param[out] none
+    \retval     none
+*/
+void rcu_osci_off(rcu_osci_type_enum osci)
+{
+    RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
+}
+
+/*!
+    \brief      enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: high speed crystal oscillator(HXTAL)
+      \arg        RCU_LXTAL: low speed crystal oscillator(LXTAL)
+    \param[out] none
+    \retval     none
+*/
+void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
+{
+    uint32_t reg;
+
+    switch(osci){
+    /* enable HXTAL to bypass mode */
+    case RCU_HXTAL:
+        reg = RCU_CTL;
+        RCU_CTL &= ~RCU_CTL_HXTALEN;
+        RCU_CTL = (reg | RCU_CTL_HXTALBPS);
+        break;
+    /* enable LXTAL to bypass mode */
+    case RCU_LXTAL:
+        reg = RCU_BDCTL;
+        RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
+        RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
+        break;
+    case RCU_IRC8M:
+    case RCU_IRC40K:
+    case RCU_PLL_CK:
+    case RCU_PLL1_CK:
+    case RCU_PLL2_CK:
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
+    \param[in]  osci: oscillator types, refer to rcu_osci_type_enum
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_HXTAL: high speed crystal oscillator(HXTAL)
+      \arg        RCU_LXTAL: low speed crystal oscillator(LXTAL)
+    \param[out] none
+    \retval     none
+*/
+void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
+{
+    uint32_t reg;
+    
+    switch(osci){
+    /* disable HXTAL to bypass mode */
+    case RCU_HXTAL:
+        reg = RCU_CTL;
+        RCU_CTL &= ~RCU_CTL_HXTALEN;
+        RCU_CTL = (reg & ~RCU_CTL_HXTALBPS);
+        break;
+    /* disable LXTAL to bypass mode */
+    case RCU_LXTAL:
+        reg = RCU_BDCTL;
+        RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
+        RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS);
+        break;
+    case RCU_IRC8M:
+    case RCU_IRC40K:
+    case RCU_PLL_CK:
+    case RCU_PLL1_CK:
+    case RCU_PLL2_CK:
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      enable the HXTAL clock monitor
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+
+void rcu_hxtal_clock_monitor_enable(void)
+{
+    RCU_CTL |= RCU_CTL_CKMEN;
+}
+
+/*!
+    \brief      disable the HXTAL clock monitor
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_hxtal_clock_monitor_disable(void)
+{
+    RCU_CTL &= ~RCU_CTL_CKMEN;
+}
+
+/*!
+    \brief      set the IRC8M adjust value
+    \param[in]  irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F
+    \param[out] none
+    \retval     none
+*/
+void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
+{
+    uint32_t reg;
+    
+    reg = RCU_CTL;
+    /* reset the IRC8MADJ bits and set according to irc8m_adjval */
+    reg &= ~RCU_CTL_IRC8MADJ;
+    RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3));
+}
+
+/*!
+    \brief      deep-sleep mode voltage select
+    \param[in]  dsvol: deep sleep mode voltage
+                only one parameter can be selected which is shown as below:
+      \arg        RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V
+      \arg        RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V
+      \arg        RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
+      \arg        RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
+    \param[out] none
+    \retval     none
+*/
+void rcu_deepsleep_voltage_set(uint32_t dsvol)
+{    
+    dsvol &= RCU_DSV_DSLPVS;
+    RCU_DSV = dsvol;
+}
+
+/*!
+    \brief      get the system clock, bus and peripheral clock frequency
+    \param[in]  clock: the clock frequency which to get
+                only one parameter can be selected which is shown as below:
+      \arg        CK_SYS: system clock frequency
+      \arg        CK_AHB: AHB clock frequency
+      \arg        CK_APB1: APB1 clock frequency
+      \arg        CK_APB2: APB2 clock frequency
+    \param[out] none
+    \retval     clock frequency of system, AHB, APB1, APB2
+*/
+uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
+{
+    uint32_t sws, ck_freq = 0U;
+    uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
+    uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp;
+    uint32_t predv0, predv1, pll1mf;
+
+    /* exponent of AHB, APB1 and APB2 clock divider */
+    uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+    uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+    uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+    sws = GET_BITS(RCU_CFG0, 2, 3);
+    switch(sws){
+    /* IRC8M is selected as CK_SYS */
+    case SEL_IRC8M:
+        cksys_freq = IRC8M_VALUE;
+        break;
+    /* HXTAL is selected as CK_SYS */
+    case SEL_HXTAL:
+        cksys_freq = HXTAL_VALUE;
+        break;
+    /* PLL is selected as CK_SYS */
+    case SEL_PLL:
+        /* PLL clock source selection, HXTAL or IRC8M/2 */
+        pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
+
+        if(RCU_PLLSRC_HXTAL == pllsel) {
+            /* PLL clock source is HXTAL */
+            ck_src = HXTAL_VALUE;
+
+            predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
+            /* source clock use PLL1 */
+            if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
+                predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
+                pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
+                if(17U == pll1mf){
+                    pll1mf = 20U;
+                }
+                ck_src = (ck_src / predv1) * pll1mf;
+            }
+            predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
+            ck_src /= predv0;
+        }else{
+            /* PLL clock source is IRC8M/2 */
+            ck_src = IRC8M_VALUE/2U;
+        }
+
+        /* PLL multiplication factor */
+        pllmf = GET_BITS(RCU_CFG0, 18, 21);
+        if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
+            pllmf |= 0x10U;
+        }
+        if(pllmf < 15U){
+            pllmf += 2U;
+        }else{
+            pllmf += 1U;
+        }
+
+        cksys_freq = ck_src * pllmf;
+
+        if(15U == pllmf){
+            /* PLL source clock multiply by 6.5 */
+            cksys_freq = ck_src * 6U + ck_src / 2U;
+        }
+
+        break;
+    /* IRC8M is selected as CK_SYS */
+    default:
+        cksys_freq = IRC8M_VALUE;
+        break;
+    }
+
+    /* calculate AHB clock frequency */
+    idx = GET_BITS(RCU_CFG0, 4, 7);
+    clk_exp = ahb_exp[idx];
+    ahb_freq = cksys_freq >> clk_exp;
+    
+    /* calculate APB1 clock frequency */
+    idx = GET_BITS(RCU_CFG0, 8, 10);
+    clk_exp = apb1_exp[idx];
+    apb1_freq = ahb_freq >> clk_exp;
+    
+    /* calculate APB2 clock frequency */
+    idx = GET_BITS(RCU_CFG0, 11, 13);
+    clk_exp = apb2_exp[idx];
+    apb2_freq = ahb_freq >> clk_exp;
+    
+    /* return the clocks frequency */
+    switch(clock){
+    case CK_SYS:
+        ck_freq = cksys_freq;
+        break;
+    case CK_AHB:
+        ck_freq = ahb_freq;
+        break;
+    case CK_APB1:
+        ck_freq = apb1_freq;
+        break;
+    case CK_APB2:
+        ck_freq = apb2_freq;
+        break;
+    default:
+        break;
+    }
+    return ck_freq;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c
new file mode 100644
index 0000000000..e397d3a2cf
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c
@@ -0,0 +1,273 @@
+/*!
+    \file  gd32vf103_rtc.c
+    \brief RTC driver
+    
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_rtc.h"
+
+/* RTC register high / low bits mask */
+#define RTC_HIGH_BITS_MASK         ((uint32_t)0x000F0000U)  /* RTC high bits mask */
+#define RTC_LOW_BITS_MASK          ((uint32_t)0x0000FFFFU)  /* RTC low bits mask */
+
+/* RTC register high bits offset */
+#define RTC_HIGH_BITS_OFFSET       ((uint32_t)16U)
+
+/*!
+    \brief      enter RTC configuration mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_configuration_mode_enter(void)
+{
+    RTC_CTL |= RTC_CTL_CMF;
+}
+
+/*!
+    \brief      exit RTC configuration mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_configuration_mode_exit(void)
+{
+    RTC_CTL &= ~RTC_CTL_CMF;
+}
+
+/*!
+    \brief      set RTC counter value
+    \param[in]  cnt: RTC counter value
+    \param[out] none
+    \retval     none
+*/
+void rtc_counter_set(uint32_t cnt)
+{
+    rtc_configuration_mode_enter();
+    /* set the RTC counter high bits */
+    RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET);
+    /* set the RTC counter low bits */
+    RTC_CNTL = (cnt & RTC_LOW_BITS_MASK);
+    rtc_configuration_mode_exit();
+}
+
+/*!
+    \brief      set RTC prescaler value
+    \param[in]  psc: RTC prescaler value
+    \param[out] none
+    \retval     none
+*/
+void rtc_prescaler_set(uint32_t psc)
+{
+    rtc_configuration_mode_enter();
+    /* set the RTC prescaler high bits */
+    RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET);
+    /* set the RTC prescaler low bits */
+    RTC_PSCL = (psc & RTC_LOW_BITS_MASK);
+    rtc_configuration_mode_exit();
+}
+
+/*!
+    \brief      wait RTC last write operation finished flag set
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_lwoff_wait(void)
+{
+    /* loop until LWOFF flag is set */
+    while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
+    }
+}
+
+/*!
+    \brief      wait RTC registers synchronized flag set
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rtc_register_sync_wait(void)
+{
+    /* clear RSYNF flag */
+    RTC_CTL &= ~RTC_CTL_RSYNF;
+    /* loop until RSYNF flag is set */
+    while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
+    }
+}
+
+/*!
+    \brief      set RTC alarm value
+    \param[in]  alarm: RTC alarm value
+    \param[out] none
+    \retval     none
+*/
+void rtc_alarm_config(uint32_t alarm)
+{
+    rtc_configuration_mode_enter();
+    /* set the alarm high bits */
+    RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET);
+    /* set the alarm low bits */
+    RTC_ALRML = (alarm & RTC_LOW_BITS_MASK);
+    rtc_configuration_mode_exit();
+}
+
+/*!
+    \brief      get RTC counter value
+    \param[in]  none
+    \param[out] none
+    \retval     RTC counter value
+*/
+uint32_t rtc_counter_get(void)
+{
+    uint32_t temp = 0x0U;
+    
+    temp = RTC_CNTL;
+    temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET);
+    return temp;
+}
+
+/*!
+    \brief      get RTC divider value
+    \param[in]  none
+    \param[out] none
+    \retval     RTC divider value
+*/
+uint32_t rtc_divider_get(void)
+{
+    uint32_t temp = 0x00U;
+    
+    temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET);
+    temp |= RTC_DIVL;
+    return temp;
+}
+
+/*!
+    \brief      get RTC flag status 
+    \param[in]  flag: specify which flag status to get
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_FLAG_SECOND: second interrupt flag
+      \arg        RTC_FLAG_ALARM: alarm interrupt flag
+      \arg        RTC_FLAG_OVERFLOW: overflow interrupt flag
+      \arg        RTC_FLAG_RSYN: registers synchronized flag
+      \arg        RTC_FLAG_LWOF: last write operation finished flag
+    \param[out] none
+    \retval     SET or RESET
+*/
+FlagStatus rtc_flag_get(uint32_t flag)
+{
+    if(RESET != (RTC_CTL & flag)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear RTC flag status
+    \param[in]  flag: specify which flag status to clear
+                one or more parameters can be selected which are shown as below:
+      \arg        RTC_FLAG_SECOND: second interrupt flag
+      \arg        RTC_FLAG_ALARM: alarm interrupt flag
+      \arg        RTC_FLAG_OVERFLOW: overflow interrupt flag
+      \arg        RTC_FLAG_RSYN: registers synchronized flag
+    \param[out] none
+    \retval     none
+*/
+void rtc_flag_clear(uint32_t flag)
+{
+    /* clear RTC flag */
+    RTC_CTL &= ~flag;
+}
+
+/*!
+    \brief      get RTC interrupt flag status 
+    \param[in]  flag: specify which flag status to get
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_INT_FLAG_SECOND: second interrupt flag
+      \arg        RTC_INT_FLAG_ALARM: alarm interrupt flag
+      \arg        RTC_INT_FLAG_OVERFLOW: overflow interrupt flag
+    \param[out] none
+    \retval     SET or RESET
+*/
+FlagStatus rtc_interrupt_flag_get(uint32_t flag)
+{
+    if(RESET != (RTC_CTL & flag)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear RTC interrupt flag status
+    \param[in]  flag: specify which flag status to clear
+                one or more parameters can be selected which are shown as below:
+      \arg        RTC_INT_FLAG_SECOND: second interrupt flag
+      \arg        RTC_INT_FLAG_ALARM: alarm interrupt flag
+      \arg        RTC_INT_FLAG_OVERFLOW: overflow interrupt flag
+    \param[out] none
+    \retval     none
+*/
+void rtc_interrupt_flag_clear(uint32_t flag)
+{
+    /* clear RTC interrupt flag */
+    RTC_CTL &= ~flag;
+}
+
+/*!
+    \brief      enable RTC interrupt
+    \param[in]  interrupt: specify which interrupt to enbale
+                one or more parameters can be selected which are shown as below:
+      \arg        RTC_INT_SECOND: second interrupt
+      \arg        RTC_INT_ALARM: alarm interrupt
+      \arg        RTC_INT_OVERFLOW: overflow interrupt
+    \param[out] none
+    \retval     none
+*/
+void rtc_interrupt_enable(uint32_t interrupt)
+{
+    RTC_INTEN |= interrupt;
+}
+
+/*!
+    \brief      disable RTC interrupt
+    \param[in]  interrupt: specify which interrupt to disbale
+                one or more parameters can be selected which are shown as below:
+      \arg        RTC_INT_SECOND: second interrupt
+      \arg        RTC_INT_ALARM: alarm interrupt
+      \arg        RTC_INT_OVERFLOW: overflow interrupt
+    \param[out] none
+    \retval     none
+*/
+void rtc_interrupt_disable(uint32_t interrupt)
+{
+    RTC_INTEN &= ~interrupt;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c
new file mode 100644
index 0000000000..2e1b3a16bb
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c
@@ -0,0 +1,766 @@
+/*!
+    \file  gd32vf103_spi.c
+    \brief SPI driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_spi.h"
+
+/* SPI/I2S parameter initialization mask */
+#define SPI_INIT_MASK                   ((uint32_t)0x00003040U)  /*!< SPI parameter initialization mask */
+#define I2S_INIT_MASK                   ((uint32_t)0x0000F047U)  /*!< I2S parameter initialization mask */
+
+/* I2S clock source selection, multiplication and division mask */
+#define I2S1_CLOCK_SEL                  ((uint32_t)0x00020000U)  /* I2S1 clock source selection */
+#define I2S2_CLOCK_SEL                  ((uint32_t)0x00040000U)  /* I2S2 clock source selection */
+#define I2S_CLOCK_MUL_MASK              ((uint32_t)0x0000F000U)  /* I2S clock multiplication mask */
+#define I2S_CLOCK_DIV_MASK              ((uint32_t)0x000000F0U)  /* I2S clock division mask */
+
+/* default value and offset */
+#define SPI_I2SPSC_DEFAULT_VALUE        ((uint32_t)0x00000002U)  /* default value of SPI_I2SPSC register */
+#define RCU_CFG1_PREDV1_OFFSET          4U                       /* PREDV1 offset in RCU_CFG1 */
+#define RCU_CFG1_PLL2MF_OFFSET          12U                      /* PLL2MF offset in RCU_CFG1 */
+
+/*!
+    \brief      reset SPI and I2S 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_deinit(uint32_t spi_periph)
+{
+    switch(spi_periph){
+    case SPI0:
+        /* reset SPI0 */
+        rcu_periph_reset_enable(RCU_SPI0RST);
+        rcu_periph_reset_disable(RCU_SPI0RST);
+        break;
+    case SPI1:
+        /* reset SPI1 and I2S1 */
+        rcu_periph_reset_enable(RCU_SPI1RST);
+        rcu_periph_reset_disable(RCU_SPI1RST);
+        break;
+    case SPI2:
+        /* reset SPI2 and I2S2 */
+        rcu_periph_reset_enable(RCU_SPI2RST);
+        rcu_periph_reset_disable(RCU_SPI2RST);
+        break;
+    default :
+        break;
+    }
+}
+
+/*!
+    \brief      initialize the parameters of SPI struct with the default values
+    \param[in]  spi_struct: SPI parameter stuct
+    \param[out] none
+    \retval     none
+*/
+void spi_struct_para_init(spi_parameter_struct* spi_struct)
+{
+    /* set the SPI struct with the default values */
+    spi_struct->device_mode = SPI_SLAVE;
+    spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX;
+    spi_struct->frame_size = SPI_FRAMESIZE_8BIT;
+    spi_struct->nss = SPI_NSS_HARD;
+    spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
+    spi_struct->prescale = SPI_PSC_2;
+}
+
+/*!
+    \brief      initialize SPI parameter
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  spi_struct: SPI parameter initialization stuct members of the structure 
+                            and the member values are shown as below:
+                  device_mode: SPI_MASTER, SPI_SLAVE
+                  trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
+                              SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT
+                  frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT
+                  nss: SPI_NSS_SOFT, SPI_NSS_HARD
+                  endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB
+                  clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE
+                                        SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE
+                  prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
+    \param[out] none
+    \retval     none
+*/
+void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
+{   
+    uint32_t reg = 0U;
+    reg = SPI_CTL0(spi_periph);
+    reg &= SPI_INIT_MASK;
+
+    /* select SPI as master or slave */
+    reg |= spi_struct->device_mode;
+    /* select SPI transfer mode */
+    reg |= spi_struct->trans_mode;
+    /* select SPI frame size */
+    reg |= spi_struct->frame_size;
+    /* select SPI NSS use hardware or software */
+    reg |= spi_struct->nss;
+    /* select SPI LSB or MSB */
+    reg |= spi_struct->endian;
+    /* select SPI polarity and phase */
+    reg |= spi_struct->clock_polarity_phase;
+    /* select SPI prescale to adjust transmit speed */
+    reg |= spi_struct->prescale;
+
+    /* write to SPI_CTL0 register */
+    SPI_CTL0(spi_periph) = (uint32_t)reg;
+
+    SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
+}
+
+/*!
+    \brief      enable SPI
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_enable(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
+}
+
+/*!
+    \brief      disable SPI 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_disable(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
+}
+
+/*!
+    \brief      initialize I2S parameter 
+    \param[in]  spi_periph: SPIx(x=1,2)
+    \param[in]  mode: I2S operation mode
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_MODE_SLAVETX: I2S slave transmit mode
+      \arg        I2S_MODE_SLAVERX: I2S slave receive mode
+      \arg        I2S_MODE_MASTERTX: I2S master transmit mode
+      \arg        I2S_MODE_MASTERRX: I2S master receive mode
+    \param[in]  standard: I2S standard
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_STD_PHILLIPS: I2S phillips standard
+      \arg        I2S_STD_MSB: I2S MSB standard
+      \arg        I2S_STD_LSB: I2S LSB standard
+      \arg        I2S_STD_PCMSHORT: I2S PCM short standard
+      \arg        I2S_STD_PCMLONG: I2S PCM long standard
+    \param[in]  ckpl: I2S idle state clock polarity
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_CKPL_LOW: I2S clock polarity low level
+      \arg        I2S_CKPL_HIGH: I2S clock polarity high level
+    \param[out] none
+    \retval     none
+*/
+void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
+{
+    uint32_t reg = 0U;
+    reg = SPI_I2SCTL(spi_periph);
+    reg &= I2S_INIT_MASK;
+
+    /* enable I2S mode */
+    reg |= (uint32_t)SPI_I2SCTL_I2SSEL; 
+    /* select I2S mode */
+    reg |= (uint32_t)mode;
+    /* select I2S standard */
+    reg |= (uint32_t)standard;
+    /* select I2S polarity */
+    reg |= (uint32_t)ckpl;
+
+    /* write to SPI_I2SCTL register */
+    SPI_I2SCTL(spi_periph) = (uint32_t)reg;
+}
+
+/*!
+    \brief      configure I2S prescaler 
+    \param[in]  spi_periph: SPIx(x=1,2)
+    \param[in]  audiosample: I2S audio sample rate
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
+      \arg        I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
+      \arg        I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
+      \arg        I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
+      \arg        I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
+      \arg        I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
+      \arg        I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
+      \arg        I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
+      \arg        I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
+    \param[in]  frameformat: I2S data length and channel length
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
+      \arg        I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
+      \arg        I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
+      \arg        I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
+    \param[in]  mckout: I2S master clock output
+                only one parameter can be selected which is shown as below:
+      \arg        I2S_MCKOUT_ENABLE: I2S master clock output enable
+      \arg        I2S_MCKOUT_DISABLE: I2S master clock output disable
+    \param[out] none
+    \retval     none
+*/
+void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
+{
+    uint32_t i2sdiv = 2U, i2sof = 0U;
+    uint32_t clks = 0U;
+    uint32_t i2sclock = 0U;
+
+    /* deinit SPI_I2SPSC register */
+    SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE;
+
+    /* get the I2S clock source */
+    if(SPI1 == ((uint32_t)spi_periph)){
+        /* I2S1 clock source selection */
+        clks = I2S1_CLOCK_SEL;
+    }else{
+        /* I2S2 clock source selection */
+        clks = I2S2_CLOCK_SEL;
+    }
+    
+    if(0U != (RCU_CFG1 & clks)){
+        /* get RCU PLL2 clock multiplication factor */
+        clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET);
+        
+        if((clks > 5U) && (clks < 15U)){
+            /* multiplier is between 8 and 16 */
+            clks += 2U;
+        }else{
+            if(15U == clks){
+                /* multiplier is 20 */
+                clks = 20U;
+            }
+        }
+
+        /* get the PREDV1 value */
+        i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >>  RCU_CFG1_PREDV1_OFFSET) + 1U);
+        /* calculate I2S clock based on PLL2 and PREDV1 */
+        i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
+    }else{
+        /* get system clock */
+        i2sclock = rcu_clock_freq_get(CK_SYS);
+    }
+    
+    /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
+    if(I2S_MCKOUT_ENABLE == mckout){
+        clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
+    }else{
+        if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){
+            clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample);
+        }else{
+            clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
+        }
+    }
+    
+    /* remove the floating point */
+    clks = (clks + 5U) / 10U;
+    i2sof  = (clks & 0x00000001U);
+    i2sdiv = ((clks - i2sof) / 2U);
+    i2sof  = (i2sof << 8U);
+
+    /* set the default values */
+    if((i2sdiv < 2U) || (i2sdiv > 255U)){
+        i2sdiv = 2U;
+        i2sof = 0U;
+    }
+    /* configure SPI_I2SPSC */
+    SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
+
+    /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
+    SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
+    /* configure data frame format */
+    SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
+}
+
+/*!
+    \brief      enable I2S 
+    \param[in]  spi_periph: SPIx(x=1,2)
+    \param[out] none
+    \retval     none
+*/
+void i2s_enable(uint32_t spi_periph)
+{
+    SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
+}
+
+/*!
+    \brief      disable I2S 
+    \param[in]  spi_periph: SPIx(x=1,2)
+    \param[out] none
+    \retval     none
+*/
+void i2s_disable(uint32_t spi_periph)
+{
+    SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
+}
+
+/*!
+    \brief      enable SPI NSS output 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_nss_output_enable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
+}
+
+/*!
+    \brief      disable SPI NSS output 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_nss_output_disable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
+}
+
+/*!
+    \brief      SPI NSS pin high level in software mode
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_nss_internal_high(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
+}
+
+/*!
+    \brief      SPI NSS pin low level in software mode
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_nss_internal_low(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
+}
+
+/*!
+    \brief      enable SPI DMA send or receive 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  dma: SPI DMA mode
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_DMA_TRANSMIT: SPI transmit data using DMA
+      \arg        SPI_DMA_RECEIVE: SPI receive data using DMA
+    \param[out] none
+    \retval     none
+*/
+void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
+{
+    if(SPI_DMA_TRANSMIT == dma){
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
+    }else{
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
+    }
+}
+
+/*!
+    \brief      disable SPI DMA send or receive 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  dma: SPI DMA mode
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_DMA_TRANSMIT: SPI transmit data using DMA
+      \arg        SPI_DMA_RECEIVE: SPI receive data using DMA
+    \param[out] none
+    \retval     none
+*/
+void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
+{
+    if(SPI_DMA_TRANSMIT == dma){
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
+    }else{
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
+    }
+}
+
+/*!
+    \brief      configure SPI/I2S data frame format
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  frame_format: SPI frame size
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
+      \arg        SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
+{
+    /* clear SPI_CTL0_FF16 bit */
+    SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
+    /* configure SPI_CTL0_FF16 bit */
+    SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
+}
+
+/*!
+    \brief      SPI transmit data
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  data: 16-bit data
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
+{
+    SPI_DATA(spi_periph) = (uint32_t)data;
+}
+
+/*!
+    \brief      SPI receive data
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     16-bit data
+*/
+uint16_t spi_i2s_data_receive(uint32_t spi_periph)
+{
+    return ((uint16_t)SPI_DATA(spi_periph));
+}
+
+/*!
+    \brief      configure SPI bidirectional transfer direction
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  transfer_direction: SPI transfer direction
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
+      \arg        SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
+    \param[out] none
+    \retval     none
+*/
+void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
+{
+    if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
+        /* set the transmit-only mode */
+        SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
+    }else{
+        /* set the receive-only mode */
+        SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
+    }
+}
+
+/*!
+    \brief      set SPI CRC polynomial 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  crc_poly: CRC polynomial value
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly)
+{
+    /* enable SPI CRC */
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
+
+    /* set SPI CRC polynomial */
+    SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
+}
+
+/*!
+    \brief      get SPI CRC polynomial 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     16-bit CRC polynomial
+*/
+uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
+{
+    return ((uint16_t)SPI_CRCPOLY(spi_periph));
+}
+
+/*!
+    \brief      turn on CRC function 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_on(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
+}
+
+/*!
+    \brief      turn off CRC function 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_off(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
+}
+
+/*!
+    \brief      SPI next data is CRC value
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_next(uint32_t spi_periph)
+{
+    SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
+}
+
+/*!
+    \brief      get SPI CRC send value or receive value
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  crc: SPI crc value
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_CRC_TX: get transmit crc value
+      \arg        SPI_CRC_RX: get receive crc value
+    \param[out] none
+    \retval     16-bit CRC value
+*/
+uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc)
+{
+    if(SPI_CRC_TX == crc){
+        return ((uint16_t)(SPI_TCRC(spi_periph)));
+    }else{
+        return ((uint16_t)(SPI_RCRC(spi_periph)));
+    }
+}
+
+/*!
+    \brief      enable SPI TI mode
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_ti_mode_enable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
+}
+
+/*!
+    \brief      disable SPI TI mode
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_ti_mode_disable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
+}
+
+/*!
+    \brief      enable SPI NSS pulse mode
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_nssp_mode_enable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
+}
+
+/*!
+    \brief      disable SPI NSS pulse mode
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_nssp_mode_disable(uint32_t spi_periph)
+{
+    SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
+}
+
+
+/*!
+    \brief      enable SPI and I2S interrupt 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  interrupt: SPI/I2S interrupt
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
+      \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
+      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
+                                   transmission underrun error and format error interrupt
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
+{
+    switch(interrupt){
+    /* SPI/I2S transmit buffer empty interrupt */
+    case SPI_I2S_INT_TBE:
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
+        break;
+    /* SPI/I2S receive buffer not empty interrupt */
+    case SPI_I2S_INT_RBNE:
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
+        break;
+    /* SPI/I2S error */
+    case SPI_I2S_INT_ERR:
+        SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      disable SPI and I2S interrupt 
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  interrupt: SPI/I2S interrupt
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_I2S_INT_TBE: transmit buffer empty interrupt
+      \arg        SPI_I2S_INT_RBNE: receive buffer not empty interrupt
+      \arg        SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
+                                   transmission underrun error and format error interrupt
+    \param[out] none
+    \retval     none
+*/
+void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
+{
+    switch(interrupt){
+    /* SPI/I2S transmit buffer empty interrupt */
+    case SPI_I2S_INT_TBE:
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
+        break;
+    /* SPI/I2S receive buffer not empty interrupt */
+    case SPI_I2S_INT_RBNE:
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
+        break;
+    /* SPI/I2S error */
+    case SPI_I2S_INT_ERR:
+        SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      get SPI and I2S interrupt flag status
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  interrupt: SPI/I2S interrupt flag status
+                only one parameter can be selected which is shown as below:
+      \arg        SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
+      \arg        SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
+      \arg        SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
+      \arg        SPI_INT_FLAG_CONFERR: config error interrupt flag
+      \arg        SPI_INT_FLAG_CRCERR: CRC error interrupt flag
+      \arg        I2S_INT_FLAG_TXURERR: underrun error interrupt flag
+      \arg        SPI_I2S_INT_FLAG_FERR: format error interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
+{
+    uint32_t reg1 = SPI_STAT(spi_periph);
+    uint32_t reg2 = SPI_CTL1(spi_periph);
+
+    switch(interrupt){
+    /* SPI/I2S transmit buffer empty interrupt */
+    case SPI_I2S_INT_FLAG_TBE:
+        reg1 = reg1 & SPI_STAT_TBE;
+        reg2 = reg2 & SPI_CTL1_TBEIE;
+        break;
+    /* SPI/I2S receive buffer not empty interrupt */
+    case SPI_I2S_INT_FLAG_RBNE:
+        reg1 = reg1 & SPI_STAT_RBNE;
+        reg2 = reg2 & SPI_CTL1_RBNEIE;
+        break;
+    /* SPI/I2S overrun interrupt */
+    case SPI_I2S_INT_FLAG_RXORERR:
+        reg1 = reg1 & SPI_STAT_RXORERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    /* SPI config error interrupt */
+    case SPI_INT_FLAG_CONFERR:
+        reg1 = reg1 & SPI_STAT_CONFERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    /* SPI CRC error interrupt */
+    case SPI_INT_FLAG_CRCERR:
+        reg1 = reg1 & SPI_STAT_CRCERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    /* I2S underrun error interrupt */
+    case I2S_INT_FLAG_TXURERR:
+        reg1 = reg1 & SPI_STAT_TXURERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    /* SPI/I2S format error interrupt */
+    case SPI_I2S_INT_FLAG_FERR:
+        reg1 = reg1 & SPI_STAT_FERR;
+        reg2 = reg2 & SPI_CTL1_ERRIE;
+        break;
+    default:
+        break;
+    }
+    /* get SPI/I2S interrupt flag status */
+    if((0U != reg1) && (0U != reg2)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      get SPI and I2S flag status
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[in]  flag: SPI/I2S flag status
+                one or more parameters can be selected which are shown as below:
+      \arg        SPI_FLAG_TBE: transmit buffer empty flag
+      \arg        SPI_FLAG_RBNE: receive buffer not empty flag
+      \arg        SPI_FLAG_TRANS: transmit on-going flag
+      \arg        SPI_FLAG_RXORERR: receive overrun error flag
+      \arg        SPI_FLAG_CONFERR: mode config error flag
+      \arg        SPI_FLAG_CRCERR: CRC error flag
+      \arg        SPI_FLAG_FERR: format error interrupt flag
+      \arg        I2S_FLAG_TBE: transmit buffer empty flag
+      \arg        I2S_FLAG_RBNE: receive buffer not empty flag
+      \arg        I2S_FLAG_TRANS: transmit on-going flag
+      \arg        I2S_FLAG_RXORERR: overrun error flag
+      \arg        I2S_FLAG_TXURERR: underrun error flag
+      \arg        I2S_FLAG_CH: channel side flag
+      \arg        I2S_FLAG_FERR: format error interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
+{
+    if(RESET != (SPI_STAT(spi_periph) & flag)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear SPI CRC error flag status
+    \param[in]  spi_periph: SPIx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void spi_crc_error_clear(uint32_t spi_periph)
+{
+    SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c
new file mode 100644
index 0000000000..e13e1cd29b
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c
@@ -0,0 +1,1965 @@
+/*!
+    \file  gd32vf103_timer.c
+    \brief TIMER driver
+    
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+#include "gd32vf103_timer.h"
+
+/* TIMER init parameter mask */
+#define ALIGNEDMODE_MASK            ((uint32_t)0x00000060U)   /*!< TIMER init parameter aligne dmode mask */
+#define COUNTERDIRECTION_MASK       ((uint32_t)0x00000010U)   /*!< TIMER init parameter counter direction mask */
+#define CLOCKDIVISION_MASK          ((uint32_t)0x00000300U)   /*!< TIMER init parameter clock division value mask */
+
+/*!
+    \brief      deinit a timer
+    \param[in]  timer_periph: TIMERx(x=0..13)
+    \param[out] none
+    \retval     none
+*/
+void timer_deinit(uint32_t timer_periph)
+{
+    switch(timer_periph){
+    case TIMER0:
+        /* reset TIMER0 */
+        rcu_periph_reset_enable(RCU_TIMER0RST);
+        rcu_periph_reset_disable(RCU_TIMER0RST);
+        break;
+    case TIMER1:
+        /* reset TIMER1 */
+        rcu_periph_reset_enable(RCU_TIMER1RST);
+        rcu_periph_reset_disable(RCU_TIMER1RST);
+        break;
+    case TIMER2:
+        /* reset TIMER2 */
+        rcu_periph_reset_enable(RCU_TIMER2RST);
+        rcu_periph_reset_disable(RCU_TIMER2RST);
+        break;
+    case TIMER3:
+        /* reset TIMER3 */
+        rcu_periph_reset_enable(RCU_TIMER3RST);
+        rcu_periph_reset_disable(RCU_TIMER3RST);
+        break;
+    case TIMER4:
+        /* reset TIMER4 */
+        rcu_periph_reset_enable(RCU_TIMER4RST);
+        rcu_periph_reset_disable(RCU_TIMER4RST);
+        break;
+    case TIMER5:
+        /* reset TIMER5 */
+        rcu_periph_reset_enable(RCU_TIMER5RST);
+        rcu_periph_reset_disable(RCU_TIMER5RST);
+        break;
+    case TIMER6:
+        /* reset TIMER6 */
+        rcu_periph_reset_enable(RCU_TIMER6RST);
+        rcu_periph_reset_disable(RCU_TIMER6RST);
+        break;
+
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      initialize TIMER init parameter struct with a default value
+    \param[in]  initpara: init parameter struct
+    \param[out] none
+    \retval     none
+*/
+void timer_struct_para_init(timer_parameter_struct* initpara)
+{
+    /* initialize the init parameter struct member with the default value */
+    initpara->prescaler         = 0U;
+    initpara->alignedmode       = TIMER_COUNTER_EDGE;
+    initpara->counterdirection  = TIMER_COUNTER_UP;
+    initpara->period            = 65535U;
+    initpara->clockdivision     = TIMER_CKDIV_DIV1;
+    initpara->repetitioncounter = 0U;
+}
+
+/*!
+    \brief      initialize TIMER counter
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  initpara: init parameter struct
+                  prescaler: prescaler value of the counter clock, 0~65535
+                  alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP,
+                               TIMER_COUNTER_CENTER_BOTH
+                  counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN
+                  period: counter auto reload value, 0~65535
+                  clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4
+                  repetitioncounter: counter repetition value, 0~255
+    \param[out] none
+    \retval     none
+*/
+void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
+{
+    /* configure the counter prescaler value */
+    TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
+
+    /* configure the counter direction and aligned mode */
+    if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)
+        || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) ){
+        TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM));
+        TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK);
+        TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);            
+    }else{
+        TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
+        TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); 
+    }
+    
+    /* configure the autoreload value */
+    TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
+
+    if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
+        /* reset the CKDIV bit */
+        TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV);
+        TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK);
+    }
+
+    if (TIMER0 == timer_periph) {
+        /* configure the repetition counter value */
+        TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
+    }
+
+    /* generate an update event */
+    TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
+}
+
+/*!
+    \brief      enable a timer
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[out] none
+    \retval     none
+*/
+void timer_enable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
+}
+
+/*!
+    \brief      disable a timer
+    \param[in]  timer_periph: TIMERx(x=0..13)
+    \param[out] none
+    \retval     none
+*/
+void timer_disable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
+}
+
+/*!
+    \brief      enable the auto reload shadow function
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[out] none
+    \retval     none
+*/
+void timer_auto_reload_shadow_enable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
+}
+
+/*!
+    \brief      disable the auto reload shadow function
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[out] none
+    \retval     none
+*/
+void timer_auto_reload_shadow_disable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
+}
+
+/*!
+    \brief      enable the update event
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[out] none
+    \retval     none
+*/
+void timer_update_event_enable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
+}
+
+/*!
+    \brief      disable the update event
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[out] none
+    \retval     none
+*/
+void timer_update_event_disable(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
+}
+
+/*!
+    \brief      set TIMER counter alignment mode
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  aligned: 
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_COUNTER_EDGE: edge-aligned mode
+      \arg        TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
+      \arg        TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
+      \arg        TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
+    \param[out] none
+    \retval     none
+*/
+void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
+{
+    TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM);
+    TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
+}
+
+/*!
+    \brief      set TIMER counter up direction
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void timer_counter_up_direction(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
+}
+
+/*!
+    \brief      set TIMER counter down direction
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void timer_counter_down_direction(uint32_t timer_periph)
+{
+    TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
+}
+
+/*!
+    \brief      configure TIMER prescaler
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  prescaler: prescaler value
+    \param[in]  pscreload: prescaler reload mode
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
+      \arg        TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
+    \param[out] none
+    \retval     none
+*/
+void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload)
+{
+    TIMER_PSC(timer_periph) = (uint32_t)prescaler;
+    
+    if(TIMER_PSC_RELOAD_NOW == pscreload){
+        TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
+    }
+}
+
+/*!
+    \brief      configure TIMER repetition register value
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[in]  repetition: the counter repetition value, 0~255
+    \param[out] none
+    \retval     none
+*/
+void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
+{
+    TIMER_CREP(timer_periph) = (uint32_t)repetition;
+} 
+ 
+/*!
+    \brief      configure TIMER autoreload register value
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  autoreload: the counter auto-reload value
+    \param[out] none
+    \retval     none
+*/         
+void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
+{
+    TIMER_CAR(timer_periph) = (uint32_t)autoreload;
+}
+
+/*!
+    \brief      configure TIMER counter register value
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  counter: the counter value
+    \param[out] none
+    \retval     none
+*/         
+void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
+{
+    TIMER_CNT(timer_periph) = (uint32_t)counter;
+}
+
+/*!
+    \brief      read TIMER counter value
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[out] none
+    \retval     counter value
+*/         
+uint32_t timer_counter_read(uint32_t timer_periph)
+{
+    uint32_t count_value = 0U;
+    count_value = TIMER_CNT(timer_periph);
+    return (count_value);
+}
+
+/*!
+    \brief      read TIMER prescaler value
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[out] none
+    \retval     prescaler register value
+*/         
+uint16_t timer_prescaler_read(uint32_t timer_periph)
+{
+    uint16_t prescaler_value = 0U;
+    prescaler_value = (uint16_t) (TIMER_PSC(timer_periph));
+    return (prescaler_value);
+}
+
+/*!
+    \brief      configure TIMER single pulse mode
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  spmode:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_SP_MODE_SINGLE: single pulse mode
+      \arg        TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
+    \param[out] none
+    \retval     none
+*/
+void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
+{
+    if(TIMER_SP_MODE_SINGLE == spmode){
+        TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
+    }else if(TIMER_SP_MODE_REPETITIVE == spmode){
+        TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
+    }else{
+        /* illegal parameters */        
+    }
+}
+
+/*!
+    \brief      configure TIMER update source 
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  update:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, 
+                                           or the slave mode controller trigger
+      \arg        TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
+    \param[out] none
+    \retval     none
+*/
+void timer_update_source_config(uint32_t timer_periph, uint32_t update)
+{
+    if(TIMER_UPDATE_SRC_REGULAR == update){
+        TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
+    }else if(TIMER_UPDATE_SRC_GLOBAL == update){
+        TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
+    }else{
+        /* illegal parameters */        
+    }
+}
+
+/*!
+    \brief      enable the TIMER DMA
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  dma: specify which DMA to enable
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_DMA_UPD:  update DMA enable, TIMERx(x=0..6)
+      \arg        TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4)
+      \arg        TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4)
+      \arg        TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4)
+      \arg        TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4)
+      \arg        TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0)
+      \arg        TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
+{
+    TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; 
+}
+
+/*!
+    \brief      disable the TIMER DMA
+    \param[in]  timer_periph: TIMERxTIMERx(x=0..6)
+    \param[in]  dma: specify which DMA to disbale
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_DMA_UPD:  update DMA enable, TIMERx(x=0..6)
+      \arg        TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4)
+      \arg        TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4)
+      \arg        TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4)
+      \arg        TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4)
+      \arg        TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0)
+      \arg        TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4,7)
+    \param[out] none
+    \retval     none
+*/
+void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
+{
+    TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); 
+}
+
+/*!
+    \brief      channel DMA request source selection
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  dma_request: channel DMA request source selection
+                only one parameter can be selected which is shown as below:
+       \arg        TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs
+       \arg        TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs 
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request)
+{
+    if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
+        TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
+    }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
+        TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
+    }else{
+        /* illegal parameters */        
+    }
+}
+
+/*!
+    \brief      configure the TIMER DMA transfer
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  dma_baseaddr:
+                only one parameter can be selected which is shown as below:
+       \arg        TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0)
+       \arg        TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..4)
+       \arg        TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0)
+       \arg        TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..4)
+    \param[in]  dma_lenth:
+                only one parameter can be selected which is shown as below:
+       \arg        TIMER_DMACFG_DMATC_xTRANSFER(x=1..6): DMA transfer x time
+    \param[out] none
+    \retval     none
+*/
+void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
+{
+    TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
+    TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
+}
+
+/*!
+    \brief      software generate events 
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  event: the timer software event generation sources
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..6)
+      \arg        TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4) 
+      \arg        TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4)
+      \arg        TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4) 
+      \arg        TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4) 
+      \arg        TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0) 
+      \arg        TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4)
+      \arg        TIMER_EVENT_SRC_BRKG:  break event generation, TIMERx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
+{
+    TIMER_SWEVG(timer_periph) |= (uint32_t)event;
+}
+
+/*!
+    \brief      initialize TIMER break parameter struct with a default value
+    \param[in]  breakpara: TIMER break parameter struct
+    \param[out] none
+    \retval     none
+*/
+void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
+{
+    /* initialize the break parameter struct member with the default value */
+    breakpara->runoffstate     = TIMER_ROS_STATE_DISABLE;
+    breakpara->ideloffstate    = TIMER_IOS_STATE_DISABLE;
+    breakpara->deadtime        = 0U;
+    breakpara->breakpolarity   = TIMER_BREAK_POLARITY_LOW;
+    breakpara->outputautostate = TIMER_OUTAUTO_DISABLE;
+    breakpara->protectmode     = TIMER_CCHP_PROT_OFF;
+    breakpara->breakstate      = TIMER_BREAK_DISABLE;
+}
+
+/*!
+    \brief      configure TIMER break function 
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[in]  breakpara: TIMER break parameter struct
+                  runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE
+                  ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE
+                  deadtime: 0~255
+                  breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH
+                  outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE
+                  protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2
+                  breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE
+    \param[out] none
+    \retval     none
+*/
+void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
+{
+    TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
+                                          ((uint32_t)(breakpara->ideloffstate))|
+                                          ((uint32_t)(breakpara->deadtime)) |
+                                          ((uint32_t)(breakpara->breakpolarity)) |
+                                          ((uint32_t)(breakpara->outputautostate)) |
+                                          ((uint32_t)(breakpara->protectmode)) |
+                                          ((uint32_t)(breakpara->breakstate)));
+}
+
+/*!
+    \brief      enable TIMER break function
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void timer_break_enable(uint32_t timer_periph)
+{
+    TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
+}
+
+/*!
+    \brief      disable TIMER break function
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void timer_break_disable(uint32_t timer_periph)
+{
+    TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
+}
+
+/*!
+    \brief      enable TIMER output automatic function
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void timer_automatic_output_enable(uint32_t timer_periph)
+{
+    TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
+}
+
+/*!
+    \brief      disable TIMER output automatic function
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void timer_automatic_output_disable(uint32_t timer_periph)
+{
+    TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
+}
+
+/*!
+    \brief      enable or disable TIMER primary output function
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[in]  newvalue: ENABLE or DISABLE
+    \param[out] none
+    \retval     none
+*/
+void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
+{
+    if(ENABLE == newvalue){
+        TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
+    }else{
+        TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
+    }
+}
+
+/*!
+    \brief      enable or disable channel capture/compare control shadow register 
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[in]  newvalue: ENABLE or DISABLE 
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
+{
+     if(ENABLE == newvalue){
+        TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
+    }else{
+        TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
+    }
+}
+
+/*!
+    \brief      configure TIMER channel control shadow register update control
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[in]  ccuctl: channel control shadow register update control
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
+      \arg        TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs 
+    \param[out] none
+    \retval     none
+*/              
+void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl)
+{
+    if(TIMER_UPDATECTL_CCU == ccuctl){
+        TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
+    }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
+        TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
+    }else{
+        /* illegal parameters */        
+    }
+}
+
+/*!
+    \brief      initialize TIMER channel output parameter struct with a default value
+    \param[in]  ocpara: TIMER channel n output parameter struct
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
+{
+    /* initialize the channel output parameter struct member with the default value */
+    ocpara->outputstate  = TIMER_CCX_DISABLE;
+    ocpara->outputnstate = TIMER_CCXN_DISABLE;
+    ocpara->ocpolarity   = TIMER_OC_POLARITY_HIGH;
+    ocpara->ocnpolarity  = TIMER_OCN_POLARITY_HIGH;
+    ocpara->ocidlestate  = TIMER_OC_IDLE_STATE_LOW;
+    ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
+}
+
+/*!
+    \brief      configure TIMER channel output function
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  ocpara: TIMER channeln output parameter struct
+                  outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE
+                  outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE
+                  ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW
+                  ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW
+                  ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH
+                  ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
+        /* reset the CH0P bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
+        /* set the CH0P bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
+
+        if (TIMER0 == timer_periph) {
+            /* reset the CH0NEN bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
+            /* set the CH0NEN bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
+            /* reset the CH0NP bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
+            /* set the CH0NP bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
+            /* reset the ISO0 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
+            /* set the ISO0 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
+            /* reset the ISO0N bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
+            /* set the ISO0N bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
+        }
+        TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U);
+        /* reset the CH1P bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
+        /* set the CH1P bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
+
+        if (TIMER0 == timer_periph) {
+            /* reset the CH1NEN bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
+            /* set the CH1NEN bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
+            /* reset the CH1NP bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
+            /* set the CH1NP bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
+            /* reset the ISO1 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
+            /* set the ISO1 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
+            /* reset the ISO1N bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
+            /* set the ISO1N bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
+        }
+        TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        /* reset the CH2EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+        /* set the CH2EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U);
+        /* reset the CH2P bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
+        /* set the CH2P bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
+
+        if (TIMER0 == timer_periph) {
+            /* reset the CH2NEN bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
+            /* set the CH2NEN bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
+            /* reset the CH2NP bit */
+            TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
+            /* set the CH2NP bit */
+            TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
+            /* reset the ISO2 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
+            /* set the ISO2 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
+            /* reset the ISO2N bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
+            /* set the ISO2N bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
+        }
+        TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        /* reset the CH3EN bit */
+        TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
+        /* set the CH3EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U);
+        /* reset the CH3P bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
+        /* set the CH3P bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
+
+        if (TIMER0 == timer_periph) {
+            /* reset the ISO3 bit */
+            TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
+            /* set the ISO3 bit */
+            TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
+        }
+        TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output compare mode
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  ocmode: channel output compare mode
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_MODE_TIMING: timing mode
+      \arg        TIMER_OC_MODE_ACTIVE: active mode
+      \arg        TIMER_OC_MODE_INACTIVE: inactive mode
+      \arg        TIMER_OC_MODE_TOGGLE: toggle mode
+      \arg        TIMER_OC_MODE_LOW: force low mode
+      \arg        TIMER_OC_MODE_HIGH: force high mode
+      \arg        TIMER_OC_MODE_PWM0: PWM mode 0
+      \arg        TIMER_OC_MODE_PWM1: PWM mode 1
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output pulse value
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  pulse: channel output pulse value
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+         TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output shadow function
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  ocshadow: channel output shadow state
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
+      \arg        TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output fast function
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  ocfast: channel output fast function
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_FAST_ENABLE: channel output fast function enable
+      \arg        TIMER_OC_FAST_DISABLE: channel output fast function disable
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output clear function
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..41))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  occlear: channel output clear function
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_CLEAR_ENABLE: channel output clear function enable
+      \arg        TIMER_OC_CLEAR_DISABLE: channel output clear function disable
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel output polarity 
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  ocpolarity: channel output polarity
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OC_POLARITY_HIGH: channel output polarity is high
+      \arg        TIMER_OC_POLARITY_LOW: channel output polarity is low
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel complementary output polarity 
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0))
+    \param[in]  ocnpolarity: channel complementary output polarity
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
+      \arg        TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel enable state
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  state: TIMER channel enable state
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CCX_ENABLE: channel enable 
+      \arg        TIMER_CCX_DISABLE: channel disable 
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure TIMER channel complementary output enable state
+    \param[in]  timer_periph: TIMERx(x=0)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_CH_0: TIMER channel 0
+      \arg        TIMER_CH_1: TIMER channel 1
+      \arg        TIMER_CH_2: TIMER channel 2
+    \param[in]  ocnstate: TIMER channel complementary output enable state
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_CCXN_ENABLE: channel complementary enable 
+      \arg        TIMER_CCXN_DISABLE: channel complementary disable 
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      initialize TIMER channel input parameter struct with a default value
+    \param[in]  icpara: TIMER channel intput parameter struct
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
+{
+    /* initialize the channel input parameter struct member with the default value */
+    icpara->icpolarity  = TIMER_IC_POLARITY_RISING;
+    icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
+    icpara->icprescaler = TIMER_IC_PSC_DIV1;
+    icpara->icfilter    = 0U;
+}
+
+/*!
+    \brief      configure TIMER input capture parameter 
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  icpara: TIMER channel intput parameter struct
+                  icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING,
+                              TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8)
+                  icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI,
+                               TIMER_IC_SELECTION_ITS
+                  icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4,
+                               TIMER_IC_PSC_DIV8
+                  icfilter: 0~15
+    \param[out]  none
+    \retval      none
+*/
+void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+
+        /* reset the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
+        /* reset the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
+
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+        break;
+    
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+
+        /* reset the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
+        /* reset the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
+        /* reset the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
+
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        /* reset the CH2EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
+
+        /* reset the CH2P and CH2NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP));
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
+
+        /* reset the CH2MS bit */
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
+
+        /* reset the CH2CAPFLT bit */
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
+
+        /* set the CH2EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        /* reset the CH3EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
+
+        /* reset the CH3P bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
+
+        /* reset the CH3MS bit */
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
+
+        /* reset the CH3CAPFLT bit */
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
+
+        /* set the CH3EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
+        break;
+    default:
+        break;
+    }
+    /* configure TIMER channel input capture prescaler value */
+    timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
+}
+
+/*!
+    \brief      configure TIMER channel input capture prescaler value
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[in]  prescaler: channel input capture prescaler value
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_IC_PSC_DIV1: no prescaler
+      \arg        TIMER_IC_PSC_DIV2: divided by 2
+      \arg        TIMER_IC_PSC_DIV4: divided by 4
+      \arg        TIMER_IC_PSC_DIV8: divided by 8
+    \param[out] none
+    \retval     none
+*/
+void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
+{
+    switch(channel){
+    /* configure TIMER_CH_0 */
+    case TIMER_CH_0:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
+        break;
+    /* configure TIMER_CH_1 */
+    case TIMER_CH_1:
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
+        TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
+        break;
+    /* configure TIMER_CH_2 */
+    case TIMER_CH_2:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
+        TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
+        break;
+    /* configure TIMER_CH_3 */
+    case TIMER_CH_3:
+        TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
+        TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      read TIMER channel capture compare register value
+    \param[in]  timer_periph: please refer to the following parameters
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
+      \arg        TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
+      \arg        TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
+      \arg        TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
+    \param[out] none
+    \retval     channel capture compare register value
+*/
+uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
+{
+    uint32_t count_value = 0U;
+
+    switch(channel){
+    case TIMER_CH_0:
+        /* read TIMER channel 0 capture compare register value */
+        count_value = TIMER_CH0CV(timer_periph);
+        break;
+    case TIMER_CH_1:
+        /* read TIMER channel 1 capture compare register value */
+        count_value = TIMER_CH1CV(timer_periph);
+        break;
+    case TIMER_CH_2:
+        /* read TIMER channel 2 capture compare register value */
+        count_value = TIMER_CH2CV(timer_periph);
+        break;
+    case TIMER_CH_3:
+        /* read TIMER channel 3 capture compare register value */
+        count_value = TIMER_CH3CV(timer_periph);
+        break;
+    default:
+        break;
+    }
+    return (count_value);
+}
+
+/*!
+    \brief      configure TIMER input pwm capture function 
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  channel:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_CH_0: TIMER channel 0
+      \arg        TIMER_CH_1: TIMER channel 1
+     \param[in] icpwm: TIMER channel intput pwm parameter struct
+                  icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING
+                  icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI
+                  icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, 
+                               TIMER_IC_PSC_DIV8
+                  icfilter: 0~15
+    \param[out] none
+    \retval     none
+*/
+void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
+{
+    uint16_t icpolarity  = 0x0U;
+    uint16_t icselection = 0x0U;
+
+    /* Set channel input polarity */
+    if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
+        icpolarity = TIMER_IC_POLARITY_FALLING;
+    }else{
+        icpolarity = TIMER_IC_POLARITY_RISING;
+    }
+    /* Set channel input mode selection */
+    if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
+        icselection = TIMER_IC_SELECTION_INDIRECTTI;
+    }else{
+        icselection = TIMER_IC_SELECTION_DIRECTTI;
+    }
+
+    if(TIMER_CH_0 == channel){
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        /* reset the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+        /* set the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
+        /* reset the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+        /* set the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+        /* set the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+        /* configure TIMER channel input capture prescaler value */
+        timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
+
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        /* reset the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
+        /* set the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
+        /* reset the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+        /* set the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
+        /* reset the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+        /* set the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+        /* configure TIMER channel input capture prescaler value */
+        timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
+    }else{
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        /* reset the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
+        /* set the CH1P and CH1NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
+        /* reset the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+        /* set the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
+        /* reset the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+        /* set the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+        /* configure TIMER channel input capture prescaler value */
+        timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
+
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        /* reset the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+        /* set the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
+        /* reset the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+        /* set the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+        /* set the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+        /* configure TIMER channel input capture prescaler value */
+        timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
+    }
+}
+
+/*!
+    \brief      configure TIMER hall sensor mode
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  hallmode:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
+      \arg        TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
+    \param[out] none
+    \retval     none
+*/
+void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)    
+{
+    if(TIMER_HALLINTERFACE_ENABLE == hallmode){
+        TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
+    }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
+        TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
+    }else{
+        /* illegal parameters */        
+    }
+}
+
+/*!
+    \brief      select TIMER input trigger source 
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  intrigger:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4))
+      \arg        TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4))
+      \arg        TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4))
+      \arg        TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4))
+      \arg        TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4))
+      \arg        TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4))
+      \arg        TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4))
+      \arg        TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0..4))
+    \param[out] none
+    \retval     none
+*/
+void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
+{
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
+    TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
+}
+
+/*!
+    \brief      select TIMER master mode output trigger source 
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  outrigger:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..6))
+      \arg        TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..6))
+      \arg        TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..6))
+      \arg        TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4))
+      \arg        TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4))
+      \arg        TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4))
+      \arg        TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4))
+      \arg        TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4))
+    \param[out] none
+    \retval     none
+*/
+void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
+{
+    TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
+    TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
+}
+
+/*!
+    \brief      select TIMER slave mode 
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  slavemode:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_SLAVE_MODE_DISABLE: slave mode disable
+      \arg        TIMER_ENCODER_MODE0: encoder mode 0
+      \arg        TIMER_ENCODER_MODE1: encoder mode 1
+      \arg        TIMER_ENCODER_MODE2: encoder mode 2
+      \arg        TIMER_SLAVE_MODE_RESTART: restart mode
+      \arg        TIMER_SLAVE_MODE_PAUSE: pause mode
+      \arg        TIMER_SLAVE_MODE_EVENT: event mode
+      \arg        TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0
+    \param[out] none
+    \retval     none
+*/
+
+void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
+{
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+    TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
+}
+
+/*!
+    \brief      configure TIMER master slave mode 
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  masterslave:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
+      \arg        TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
+    \param[out] none
+    \retval     none
+*/ 
+void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
+{
+    if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
+        TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
+    }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
+        TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
+    }else{
+        /* illegal parameters */        
+    }
+}
+
+/*!
+    \brief      configure TIMER external trigger input
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  extprescaler:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_EXT_TRI_PSC_OFF: no divided
+      \arg        TIMER_EXT_TRI_PSC_DIV2: divided by 2
+      \arg        TIMER_EXT_TRI_PSC_DIV4: divided by 4
+      \arg        TIMER_EXT_TRI_PSC_DIV8: divided by 8
+    \param[in]  extpolarity:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_ETP_FALLING: active low or falling edge active
+      \arg        TIMER_ETP_RISING: active high or rising edge active
+    \param[in]  extfilter: a value between 0 and 15
+    \param[out] none
+    \retval     none
+*/
+void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
+{
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
+    TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
+    TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
+}
+
+/*!
+    \brief      configure TIMER quadrature decoder mode
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  decomode:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
+      \arg        TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
+      \arg        TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
+    \param[in]  ic0polarity:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_IC_POLARITY_RISING: capture rising edge
+      \arg        TIMER_IC_POLARITY_FALLING: capture falling edge
+    \param[in]  ic1polarity:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_IC_POLARITY_RISING: capture rising edge
+      \arg        TIMER_IC_POLARITY_FALLING: capture falling edge
+    \param[out] none
+    \retval     none
+*/
+void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
+{
+    /* configure the quadrature decoder mode */
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+    TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
+    /* configure input capture selection */
+    TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS)));
+    TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
+    /* configure channel input capture polarity */
+    TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+    TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
+    TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U));
+}
+
+/*!
+    \brief      configure TIMER internal clock mode
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void timer_internal_clock_config(uint32_t timer_periph)
+{
+    TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
+}
+
+/*!
+    \brief      configure TIMER the internal trigger as external clock input
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  intrigger:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
+      \arg        TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
+      \arg        TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
+      \arg        TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
+    \param[out] none
+    \retval     none
+*/
+void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
+{
+    timer_input_trigger_source_select(timer_periph, intrigger);
+    TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
+    TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+}
+
+/*!
+    \brief      configure TIMER the external trigger as external clock input
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  extrigger:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
+      \arg        TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
+      \arg        TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
+    \param[in]  extpolarity:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_IC_POLARITY_RISING: active low or falling edge active
+      \arg        TIMER_IC_POLARITY_FALLING: active high or rising edge active
+    \param[in]  extfilter: a value between 0 and 15
+    \param[out] none
+    \retval     none
+*/
+void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter)
+{
+    if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
+        /* reset the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
+        /* reset the CH1NP bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
+        /* set the CH1NP bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
+        /* reset the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
+        /* set the CH1MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
+        /* reset the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
+        /* set the CH1CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
+        /* set the CH1EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+    }else{
+        /* reset the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
+        /* reset the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
+        /* set the CH0P and CH0NP bits */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
+        /* reset the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
+        /* set the CH0MS bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
+        /* reset the CH0CAPFLT bit */
+        TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U);
+        /* set the CH0EN bit */
+        TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+    }
+    /* select TIMER input trigger source */
+    timer_input_trigger_source_select(timer_periph, extrigger);
+    /* reset the SMC bit */
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
+    /* set the SMC bit */
+    TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+}
+
+/*!
+    \brief      configure TIMER the external clock mode0
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  extprescaler:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_EXT_TRI_PSC_OFF: no divided
+      \arg        TIMER_EXT_TRI_PSC_DIV2: divided by 2
+      \arg        TIMER_EXT_TRI_PSC_DIV4: divided by 4
+      \arg        TIMER_EXT_TRI_PSC_DIV8: divided by 8
+    \param[in]  extpolarity:
+                only one parameter can be selected which is shown as below: 
+      \arg        TIMER_ETP_FALLING: active low or falling edge active
+      \arg        TIMER_ETP_RISING: active high or rising edge active
+    \param[in]  extfilter: a value between 0 and 15
+    \param[out] none
+    \retval     none
+*/
+void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
+{
+    /* configure TIMER external trigger input */
+    timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
+    /* reset the SMC bit,TRGS bit */
+    TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
+    /* set the SMC bit,TRGS bit */
+    TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
+}
+
+/*!
+    \brief      configure TIMER the external clock mode1
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[in]  extprescaler:
+                only one parameter can be selected which is shown as below:  
+      \arg        TIMER_EXT_TRI_PSC_OFF: no divided
+      \arg        TIMER_EXT_TRI_PSC_DIV2: divided by 2
+      \arg        TIMER_EXT_TRI_PSC_DIV4: divided by 4
+      \arg        TIMER_EXT_TRI_PSC_DIV8: divided by 8
+    \param[in]  extpolarity:
+                only one parameter can be selected which is shown as below:  
+      \arg        TIMER_ETP_FALLING: active low or falling edge active
+      \arg        TIMER_ETP_RISING: active high or rising edge active
+    \param[in]  extfilter: a value between 0 and 15
+    \param[out] none
+    \retval     none
+*/
+void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
+{
+    /* configure TIMER external trigger input */
+    timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
+    TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
+}
+
+/*!
+    \brief      disable TIMER the external clock mode1
+    \param[in]  timer_periph: TIMERx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void timer_external_clock_mode1_disable(uint32_t timer_periph)
+{
+    TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
+}
+
+/*!
+    \brief      enable the TIMER interrupt
+    \param[in]  timer_periph: please refer to the following parameters 
+    \param[in]  interrupt: specify which interrupt to enable
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6)
+      \arg        TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_CH3: channel 3 interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0)
+      \arg        TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_BRK: break interrupt enable, TIMERx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
+{
+    TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; 
+}
+
+/*!
+    \brief      disable the TIMER interrupt
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  interrupt: specify which interrupt to disbale
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6)
+      \arg        TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4)
+      \arg        TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0)
+      \arg        TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4)
+      \arg        TIMER_INT_BRK: break interrupt enable, TIMERx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
+{
+    TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); 
+}
+
+/*!
+    \brief      get timer interrupt flag
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  interrupt: the timer interrupt bits
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6)
+      \arg        TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4)
+      \arg        TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4)
+      \arg        TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4)
+      \arg        TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4)
+      \arg        TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0) 
+      \arg        TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0)
+      \arg        TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0)
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
+{
+    uint32_t val;
+    val = (TIMER_DMAINTEN(timer_periph) & interrupt);
+    if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear TIMER interrupt flag
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  interrupt: the timer interrupt bits
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6)
+      \arg        TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4)
+      \arg        TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4)
+      \arg        TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4)
+      \arg        TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4)
+      \arg        TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0) 
+      \arg        TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0)
+      \arg        TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0)
+    \param[out] none
+    \retval     none
+*/
+void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
+{
+    TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
+}
+
+/*!
+    \brief      get TIMER flags
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  flag: the timer interrupt flags
+                only one parameter can be selected which is shown as below:
+      \arg        TIMER_FLAG_UP: update flag, TIMERx(x=0..6)
+      \arg        TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0)
+      \arg        TIMER_FLAG_TRG: trigger flag, TIMERx(x=0) 
+      \arg        TIMER_FLAG_BRK: break flag, TIMERx(x=0)
+      \arg        TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4)
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
+{
+    if(RESET != (TIMER_INTF(timer_periph) & flag)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear TIMER flags
+    \param[in]  timer_periph: TIMERx(x=0..6)
+    \param[in]  flag: the timer interrupt flags
+                one or more parameters can be selected which are shown as below:
+      \arg        TIMER_FLAG_UP: update flag, TIMERx(x=0..6)
+      \arg        TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0) 
+      \arg        TIMER_FLAG_TRG: trigger flag, TIMERx(x=0) 
+      \arg        TIMER_FLAG_BRK: break flag, TIMERx(x=0)
+      \arg        TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4)
+      \arg        TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4)
+    \param[out] none
+    \retval     none
+*/
+void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
+{
+    TIMER_INTF(timer_periph) = (~(uint32_t)flag);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c
new file mode 100644
index 0000000000..77c9a5159b
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c
@@ -0,0 +1,764 @@
+/*!
+    \file    gd32vf103_usart.c
+    \brief   USART driver
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_usart.h"
+
+/*!
+    \brief      reset USART/UART 
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_deinit(uint32_t usart_periph)
+{
+    switch(usart_periph){
+    case USART0:
+        /* reset USART0 */
+        rcu_periph_reset_enable(RCU_USART0RST);
+        rcu_periph_reset_disable(RCU_USART0RST);
+        break;
+    case USART1:
+        /* reset USART1 */
+        rcu_periph_reset_enable(RCU_USART1RST);
+        rcu_periph_reset_disable(RCU_USART1RST);
+        break;
+    case USART2:
+        /* reset USART2 */
+        rcu_periph_reset_enable(RCU_USART2RST);
+        rcu_periph_reset_disable(RCU_USART2RST);
+        break;
+    case UART3:
+        /* reset UART3 */
+        rcu_periph_reset_enable(RCU_UART3RST);
+        rcu_periph_reset_disable(RCU_UART3RST);
+        break;
+    case UART4:
+        /* reset UART4 */
+        rcu_periph_reset_enable(RCU_UART4RST);
+        rcu_periph_reset_disable(RCU_UART4RST);
+        break;
+    default:
+        break;
+    }
+}
+
+/*!
+    \brief      configure USART baud rate value
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  baudval: baud rate value
+    \param[out] none
+    \retval     none
+*/ 
+void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
+{
+    uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U;
+    switch(usart_periph){
+         /* get clock frequency */
+    case USART0:
+         /* get USART0 clock */
+         uclk=rcu_clock_freq_get(CK_APB2);
+         break;
+    case USART1:
+         /* get USART1 clock */
+         uclk=rcu_clock_freq_get(CK_APB1);
+         break;
+    case USART2:
+         /* get USART2 clock */
+         uclk=rcu_clock_freq_get(CK_APB1);
+         break;
+    case UART3:
+         /* get UART3 clock */
+         uclk=rcu_clock_freq_get(CK_APB1);
+         break;
+    case UART4:
+         /* get UART4 clock */
+         uclk=rcu_clock_freq_get(CK_APB1);
+         break;  
+    default:
+         break;
+    }
+    /* oversampling by 16, configure the value of USART_BAUD */
+    udiv = (uclk+baudval/2U)/baudval;
+    intdiv = udiv & (0x0000fff0U);
+    fradiv = udiv & (0x0000000fU);
+    USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
+}
+
+/*!
+    \brief     configure USART parity
+    \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in] paritycfg: configure USART parity
+               only one parameter can be selected which is shown as below:
+      \arg       USART_PM_NONE: no parity
+      \arg       USART_PM_ODD:  odd parity
+      \arg       USART_PM_EVEN: even parity 
+    \param[out] none
+    \retval     none
+*/
+void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
+{
+    /* clear USART_CTL0 PM,PCEN bits */
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
+    /* configure USART parity mode */
+    USART_CTL0(usart_periph) |= paritycfg ;
+}
+
+/*!
+    \brief     configure USART word length
+    \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in] wlen: USART word length configure
+               only one parameter can be selected which is shown as below:
+      \arg       USART_WL_8BIT: 8 bits
+      \arg       USART_WL_9BIT: 9 bits
+    \param[out] none
+    \retval     none
+*/
+void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
+{
+    /* clear USART_CTL0 WL bit */
+    USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
+    /* configure USART word length */
+    USART_CTL0(usart_periph) |= wlen;
+}
+
+/*!
+    \brief     configure USART stop bit length
+    \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in] stblen: USART stop bit configure
+               only one parameter can be selected which is shown as below:
+      \arg       USART_STB_1BIT:   1 bit
+      \arg       USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4)
+      \arg       USART_STB_2BIT:   2 bits
+      \arg       USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
+{
+    /* clear USART_CTL1 STB bits */
+    USART_CTL1(usart_periph) &= ~USART_CTL1_STB; 
+    /* configure USART stop bits */
+    USART_CTL1(usart_periph) |= stblen;
+}
+
+/*!
+    \brief      enable USART
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_enable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) |= USART_CTL0_UEN;
+}
+
+/*!
+    \brief     disable USART
+    \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_disable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+}
+
+/*!
+    \brief      configure USART transmitter
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  txconfig: enable or disable USART transmitter
+                only one parameter can be selected which is shown as below:
+      \arg        USART_TRANSMIT_ENABLE: enable USART transmission
+      \arg        USART_TRANSMIT_DISABLE: disable USART transmission
+    \param[out] none
+    \retval     none
+*/
+void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
+{
+    uint32_t ctl = 0U;
+    
+    ctl = USART_CTL0(usart_periph);
+    ctl &= ~USART_CTL0_TEN;
+    ctl |= txconfig;
+    /* configure transfer mode */
+    USART_CTL0(usart_periph) = ctl;
+}
+
+/*!
+    \brief      configure USART receiver
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  rxconfig: enable or disable USART receiver
+                only one parameter can be selected which is shown as below:
+      \arg        USART_RECEIVE_ENABLE: enable USART reception
+      \arg        USART_RECEIVE_DISABLE: disable USART reception
+    \param[out] none
+    \retval     none
+*/
+void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
+{
+    uint32_t ctl = 0U;
+    
+    ctl = USART_CTL0(usart_periph);
+    ctl &= ~USART_CTL0_REN;
+    ctl |= rxconfig;
+    /* configure receiver mode */
+    USART_CTL0(usart_periph) = ctl;
+}
+
+/*!
+    \brief      USART transmit data function
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  data: data of transmission 
+    \param[out] none
+    \retval     none
+*/
+void usart_data_transmit(uint32_t usart_periph, uint32_t data)
+{
+    USART_DATA(usart_periph) = USART_DATA_DATA & data;
+}
+
+/*!
+    \brief      USART receive data function
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     data of received
+*/
+uint16_t usart_data_receive(uint32_t usart_periph)
+{
+    return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U));
+}
+
+/*!
+    \brief      configure the address of the USART in wake up by address match mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  addr: address of USART/UART
+    \param[out] none
+    \retval     none
+*/
+void usart_address_config(uint32_t usart_periph, uint8_t addr)
+{
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
+    USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr);
+}
+
+/*!
+    \brief      receiver in mute mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_mute_mode_enable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) |= USART_CTL0_RWU;
+}
+
+/*!
+    \brief      receiver in active mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_mute_mode_disable(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU);
+}
+
+/*!
+    \brief      configure wakeup method in mute mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  wmethod: two methods be used to enter or exit the mute mode
+                only one parameter can be selected which is shown as below:
+      \arg        USART_WM_IDLE: idle line
+      \arg        USART_WM_ADDR: address mask
+    \param[out] none
+    \retval     none
+*/
+void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
+{
+    USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
+    USART_CTL0(usart_periph) |= wmethod;
+}
+
+/*!
+    \brief      enable LIN mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_lin_mode_enable(uint32_t usart_periph)
+{   
+    USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
+}
+
+/*!
+    \brief      disable LIN mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_lin_mode_disable(uint32_t usart_periph)
+{   
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
+}
+
+/*!
+    \brief      configure lin break frame length
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  lblen: lin break frame length
+                only one parameter can be selected which is shown as below:
+      \arg        USART_LBLEN_10B: 10 bits
+      \arg        USART_LBLEN_11B: 11 bits
+    \param[out] none
+    \retval     none
+*/
+void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen)
+{
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN);
+    USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen);
+}
+
+/*!
+    \brief      send break frame
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_send_break(uint32_t usart_periph)
+{
+    USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD;
+}
+
+/*!
+    \brief      enable half duplex mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_halfduplex_enable(uint32_t usart_periph)
+{   
+    USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
+}
+
+/*!
+    \brief      disable half duplex mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_halfduplex_disable(uint32_t usart_periph)
+{  
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
+}
+
+/*!
+    \brief      enable CK pin in synchronous mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void usart_synchronous_clock_enable(uint32_t usart_periph)
+{
+    USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
+}
+
+/*!
+    \brief      disable CK pin in synchronous mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void usart_synchronous_clock_disable(uint32_t usart_periph)
+{
+    USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
+}
+
+/*!
+    \brief      configure USART synchronous mode parameters
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[in]  clen: CK length
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame 
+      \arg        USART_CLEN_EN:   there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame
+    \param[in]  cph: clock phase
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CPH_1CK: first clock transition is the first data capture edge 
+      \arg        USART_CPH_2CK: second clock transition is the first data capture edge
+    \param[in]  cpl: clock polarity
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CPL_LOW:  steady low value on CK pin 
+      \Rag        USART_CPL_HIGH: steady high value on CK pin
+    \param[out] none
+    \retval     none
+*/
+void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
+{
+    uint32_t ctl = 0U;
+    
+    /* read USART_CTL1 register */
+    ctl = USART_CTL1(usart_periph);
+    ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
+    /* set CK length, CK phase, CK polarity */
+    ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl);
+
+    USART_CTL1(usart_periph) = ctl;
+}
+
+/*!
+    \brief      configure guard time value in smartcard mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[in]  gaut: guard time value
+    \param[out] none
+    \retval     none
+*/
+void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut)
+{
+    USART_GP(usart_periph) &= ~(USART_GP_GUAT);
+    USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8));
+}
+
+/*!
+    \brief      enable smartcard mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_enable(uint32_t usart_periph)
+{
+    USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
+}
+
+/*!
+    \brief      disable smartcard mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_disable(uint32_t usart_periph)
+{
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
+}
+
+/*!
+    \brief      enable NACK in smartcard mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
+{
+    USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
+}
+
+/*!
+    \brief      disable NACK in smartcard mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
+{
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
+}
+
+/*!
+    \brief      enable IrDA mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_irda_mode_enable(uint32_t usart_periph)
+{
+    USART_CTL2(usart_periph) |= USART_CTL2_IREN;
+}
+
+/*!
+    \brief      disable IrDA mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[out] none
+    \retval     none
+*/
+void usart_irda_mode_disable(uint32_t usart_periph)
+{
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
+}
+
+/*!
+    \brief      configure the peripheral clock prescaler in USART IrDA low-power mode
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  psc: 0x00-0xFF
+    \param[out] none
+    \retval     none
+*/
+void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
+{
+    USART_GP(usart_periph) &= ~(USART_GP_PSC);
+    USART_GP(usart_periph) |= psc;
+}
+
+/*!
+    \brief      configure IrDA low-power
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  irlp: IrDA low-power or normal
+                only one parameter can be selected which is shown as below:
+      \arg        USART_IRLP_LOW: low-power
+      \arg        USART_IRLP_NORMAL: normal
+    \param[out] none
+    \retval     none
+*/
+void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
+{
+    USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP);
+    USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
+}
+
+/*!
+    \brief      configure hardware flow control RTS
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[in]  rtsconfig: enable or disable RTS
+                only one parameter can be selected which is shown as below:
+      \arg        USART_RTS_ENABLE:  enable RTS
+      \arg        USART_RTS_DISABLE: disable RTS
+    \param[out] none
+    \retval     none
+*/
+void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
+{
+    uint32_t ctl = 0U;
+    
+    ctl = USART_CTL2(usart_periph);
+    ctl &= ~USART_CTL2_RTSEN;
+    ctl |= rtsconfig;
+    /* configure RTS */
+    USART_CTL2(usart_periph) = ctl;
+}
+
+/*!
+    \brief      configure hardware flow control CTS
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[in]  ctsconfig: enable or disable CTS
+                only one parameter can be selected which is shown as below:
+      \arg        USART_CTS_ENABLE:  enable CTS
+      \arg        USART_CTS_DISABLE: disable CTS
+    \param[out] none
+    \retval     none
+*/
+void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
+{
+    uint32_t ctl = 0U;
+    
+    ctl = USART_CTL2(usart_periph);
+    ctl &= ~USART_CTL2_CTSEN;
+    ctl |= ctsconfig;
+    /* configure CTS */
+    USART_CTL2(usart_periph) = ctl;
+}
+
+/*!
+    \brief      configure USART DMA reception
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3)
+    \param[in]  dmacmd: enable or disable DMA for reception
+                only one parameter can be selected which is shown as below:
+      \arg        USART_DENR_ENABLE:  DMA enable for reception
+      \arg        USART_DENR_DISABLE: DMA disable for reception
+    \param[out] none
+    \retval     none
+*/
+void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
+{
+    uint32_t ctl = 0U;
+    
+    ctl = USART_CTL2(usart_periph);
+    ctl &= ~USART_CTL2_DENR;
+    ctl |= dmacmd;
+    /* configure DMA reception */
+    USART_CTL2(usart_periph) = ctl;
+}
+
+/*!
+    \brief      configure USART DMA transmission
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3)
+    \param[in]  dmacmd: enable or disable DMA for transmission
+                only one parameter can be selected which is shown as below:
+      \arg        USART_DENT_ENABLE:  DMA enable for transmission
+      \arg        USART_DENT_DISABLE: DMA disable for transmission
+    \param[out] none
+    \retval     none
+*/
+void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
+{
+    uint32_t ctl = 0U;
+    
+    ctl = USART_CTL2(usart_periph);
+    ctl &= ~USART_CTL2_DENT;
+    ctl |= dmacmd;
+    /* configure DMA transmission */
+    USART_CTL2(usart_periph) = ctl;
+}
+
+/*!
+    \brief      get flag in STAT register
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  flag: USART flags, refer to usart_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        USART_FLAG_CTSF: CTS change flag
+      \arg        USART_FLAG_LBDF: LIN break detected flag 
+      \arg        USART_FLAG_TBE: transmit data buffer empty 
+      \arg        USART_FLAG_TC: transmission complete 
+      \arg        USART_FLAG_RBNE: read data buffer not empty 
+      \arg        USART_FLAG_IDLEF: IDLE frame detected flag 
+      \arg        USART_FLAG_ORERR: overrun error 
+      \arg        USART_FLAG_NERR: noise error flag 
+      \arg        USART_FLAG_FERR: frame error flag 
+      \arg        USART_FLAG_PERR: parity error flag 
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
+{
+    if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear flag in STAT register
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  flag: USART flags, refer to usart_flag_enum
+                only one parameter can be selected which is shown as below:
+      \arg        USART_FLAG_CTSF: CTS change flag
+      \arg        USART_FLAG_LBDF: LIN break detected flag
+      \arg        USART_FLAG_TC: transmission complete
+      \arg        USART_FLAG_RBNE: read data buffer not empty
+    \param[out] none
+    \retval     none
+*/
+void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
+{
+    USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag));
+}
+
+/*!
+    \brief      enable USART interrupt
+     \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  int_flag
+                only one parameter can be selected which is shown as below:
+      \arg        USART_INT_PERR: parity error interrupt
+      \arg        USART_INT_TBE: transmitter buffer empty interrupt
+      \arg        USART_INT_TC: transmission complete interrupt
+      \arg        USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
+      \arg        USART_INT_IDLE: IDLE line detected interrupt
+      \arg        USART_INT_LBD: LIN break detected interrupt
+      \arg        USART_INT_ERR: error interrupt
+      \arg        USART_INT_CTS: CTS interrupt
+    \param[out] none
+    \retval     none
+*/
+void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
+{
+    USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag));
+}
+
+/*!
+    \brief      disable USART interrupt
+     \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  int_flag
+                only one parameter can be selected which is shown as below:
+      \arg        USART_INT_PERR: parity error interrupt
+      \arg        USART_INT_TBE: transmitter buffer empty interrupt
+      \arg        USART_INT_TC: transmission complete interrupt
+      \arg        USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt
+      \arg        USART_INT_IDLE: IDLE line detected interrupt
+      \arg        USART_INT_LBD: LIN break detected interrupt
+      \arg        USART_INT_ERR: error interrupt
+      \arg        USART_INT_CTS: CTS interrupt
+    \param[out] none
+    \retval     none
+*/
+void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag)
+{
+    USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag));
+}
+
+/*!
+    \brief      get USART interrupt and flag status
+     \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  int_flag
+                only one parameter can be selected which is shown as below:
+      \arg        USART_INT_FLAG_PERR: parity error interrupt and flag
+      \arg        USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
+      \arg        USART_INT_FLAG_TC: transmission complete interrupt and flag
+      \arg        USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
+      \arg        USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
+      \arg        USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
+      \arg        USART_INT_FLAG_LBD: LIN break detected interrupt and flag
+      \arg        USART_INT_FLAG_CTS: CTS interrupt and flag
+      \arg        USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
+      \arg        USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
+      \arg        USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
+{
+    uint32_t intenable = 0U, flagstatus = 0U;
+    /* get the interrupt enable bit status */
+    intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
+    /* get the corresponding flag bit status */
+    flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
+
+    if(flagstatus && intenable){
+        return SET;
+    }else{
+        return RESET; 
+    }
+}
+
+/*!
+    \brief      clear USART interrupt flag in STAT register
+    \param[in]  usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
+    \param[in]  flag: USART interrupt flag
+                only one parameter can be selected which is shown as below:
+      \arg        USART_INT_FLAG_CTS: CTS change flag
+      \arg        USART_INT_FLAG_LBD: LIN break detected flag
+      \arg        USART_INT_FLAG_TC: transmission complete
+      \arg        USART_INT_FLAG_RBNE: read data buffer not empty
+    \param[out] none
+    \retval     none
+*/
+void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
+{
+    USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag));
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c
new file mode 100644
index 0000000000..e441348602
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c
@@ -0,0 +1,146 @@
+/*!
+    \file  gd32vf103_wwdgt.c
+    \brief WWDGT driver
+    
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32vf103_wwdgt.h"
+
+/* write value to WWDGT_CTL_CNT bit field */
+#define CTL_CNT(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0))
+/* write value to WWDGT_CFG_WIN bit field */
+#define CFG_WIN(regval)             (BITS(0,6) & ((uint32_t)(regval) << 0))
+
+/*!
+    \brief      reset the window watchdog timer configuration
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_deinit(void)
+{
+    rcu_periph_reset_enable(RCU_WWDGTRST);
+    rcu_periph_reset_disable(RCU_WWDGTRST);
+}
+
+/*!
+    \brief      start the window watchdog timer counter
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_enable(void)
+{
+    WWDGT_CTL |= WWDGT_CTL_WDGTEN;
+}
+
+/*!
+    \brief      configure the window watchdog timer counter value
+    \param[in]  counter_value: 0x00 - 0x7F
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_counter_update(uint16_t counter_value)
+{
+    uint32_t reg = 0U;
+    
+    reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
+    reg |= CTL_CNT(counter_value);
+    
+    WWDGT_CTL = reg;
+}
+
+/*!
+    \brief      configure counter value, window value, and prescaler divider value  
+    \param[in]  counter: 0x00 - 0x7F   
+    \param[in]  window: 0x00 - 0x7F
+    \param[in]  prescaler: wwdgt prescaler value
+                only one parameter can be selected which is shown as below:
+      \arg        WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
+      \arg        WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
+      \arg        WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
+      \arg        WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
+{
+    uint32_t reg_cfg = 0U, reg_ctl = 0U;
+
+    /* clear WIN and PSC bits, clear CNT bit */
+    reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
+    reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
+  
+    /* configure WIN and PSC bits, configure CNT bit */
+    reg_cfg |= CFG_WIN(window);
+    reg_cfg |= prescaler;
+    reg_ctl |= CTL_CNT(counter);
+    
+    WWDGT_CTL = reg_ctl;
+    WWDGT_CFG = reg_cfg;
+}
+
+/*!
+    \brief      enable early wakeup interrupt of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_interrupt_enable(void)
+{
+    WWDGT_CFG |= WWDGT_CFG_EWIE;
+}
+
+/*!
+    \brief      check early wakeup interrupt state of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus wwdgt_flag_get(void)
+{
+    if(WWDGT_STAT & WWDGT_STAT_EWIF){
+        return SET;
+    }
+
+    return RESET;
+}
+
+/*!
+    \brief      clear early wakeup interrupt state of WWDGT
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void wwdgt_flag_clear(void)
+{
+    WWDGT_STAT &= (~WWDGT_STAT_EWIF);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/gd32vf103.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/gd32vf103.h
new file mode 100644
index 0000000000..5bc3d94aec
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/gd32vf103.h
@@ -0,0 +1,230 @@
+/*!
+    \file    gd32vf103.h
+    \brief   general definitions for GD32VF103
+
+    \version 2019-6-5, V1.0.0, firmware for GD32VF103
+*/
+
+/*
+    Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32VF103_H
+#define GD32VF103_H
+
+#ifdef cplusplus
+ extern "C" {
+#endif 
+
+ /* IO definitions (access restrictions to peripheral registers) */
+ /**
+
+     <strong>IO Type Qualifiers</strong> are used
+     \li to specify the access to peripheral variables.
+     \li for automatic generation of peripheral register debug information.
+ */
+ #ifdef __cplusplus
+   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+ #else
+   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+ #endif
+ #define     __O     volatile             /*!< Defines 'write only' permissions                */
+ #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+
+#define HXTAL_VALUE    ((uint32_t)8000000) /*!< value of the external oscillator in Hz */
+
+/* define startup timeout value of high speed crystal oscillator (HXTAL) */
+#if !defined  (HXTAL_STARTUP_TIMEOUT)
+#define HXTAL_STARTUP_TIMEOUT   ((uint16_t)0xFFFF)
+#endif /* high speed crystal oscillator startup timeout */
+
+/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
+#if !defined  (IRC8M_VALUE) 
+#define IRC8M_VALUE  ((uint32_t)8000000)
+#endif /* internal 8MHz RC oscillator value */
+
+/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
+#if !defined  (IRC8M_STARTUP_TIMEOUT)
+#define IRC8M_STARTUP_TIMEOUT   ((uint16_t)0x0500)
+#endif /* internal 8MHz RC oscillator startup timeout */
+
+/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
+#if !defined  (IRC40K_VALUE) 
+#define IRC40K_VALUE  ((uint32_t)40000)
+#endif /* internal 40KHz RC oscillator value */
+
+/* define value of low speed crystal oscillator (LXTAL)in Hz */
+#if !defined  (LXTAL_VALUE) 
+#define LXTAL_VALUE  ((uint32_t)32768)
+#endif /* low speed crystal oscillator value */
+
+/* define interrupt number */
+typedef enum IRQn
+{
+	CLIC_INT_RESERVED        	 = 0,      			/*!< RISC-V reserved		*/
+	CLIC_INT_SFT         		 = 3,				/*!< Software interrupt		*/
+	CLIC_INT_TMR         		 = 7,				/*!< CPU Timer interrupt	*/
+	CLIC_INT_BWEI        		 = 17,				/*!< Bus Error interrupt	*/
+	CLIC_INT_PMOVI       		 = 18,				/*!< Performance Monitor	*/
+
+    /* interruput numbers */
+    WWDGT_IRQn                   = 19,      /*!< window watchDog timer interrupt                          */
+    LVD_IRQn                     = 20,      /*!< LVD through EXTI line detect interrupt                   */
+    TAMPER_IRQn                  = 21,      /*!< tamper through EXTI line detect                          */
+    RTC_IRQn                     = 22,      /*!< RTC alarm interrupt                                      */
+    FMC_IRQn                     = 23,      /*!< FMC interrupt                                            */
+    RCU_CTC_IRQn                 = 24,      /*!< RCU and CTC interrupt                                    */
+    EXTI0_IRQn                   = 25,      /*!< EXTI line 0 interrupts                                   */
+    EXTI1_IRQn                   = 26,      /*!< EXTI line 1 interrupts                                   */
+    EXTI2_IRQn                   = 27,      /*!< EXTI line 2 interrupts                                   */
+    EXTI3_IRQn                   = 28,      /*!< EXTI line 3 interrupts                                   */
+    EXTI4_IRQn                   = 29,     /*!< EXTI line 4 interrupts                                   */
+    DMA0_Channel0_IRQn           = 30,     /*!< DMA0 channel0 interrupt                                  */
+    DMA0_Channel1_IRQn           = 31,     /*!< DMA0 channel1 interrupt                                  */
+    DMA0_Channel2_IRQn           = 32,     /*!< DMA0 channel2 interrupt                                  */
+    DMA0_Channel3_IRQn           = 33,     /*!< DMA0 channel3 interrupt                                  */
+    DMA0_Channel4_IRQn           = 34,     /*!< DMA0 channel4 interrupt                                  */
+    DMA0_Channel5_IRQn           = 35,     /*!< DMA0 channel5 interrupt                                  */
+    DMA0_Channel6_IRQn           = 36,     /*!< DMA0 channel6 interrupt                                  */
+    ADC0_1_IRQn                  = 37,     /*!< ADC0 and ADC1 interrupt                                  */
+    CAN0_TX_IRQn                 = 38,     /*!< CAN0 TX interrupts                                       */
+    CAN0_RX0_IRQn                = 39,     /*!< CAN0 RX0 interrupts                                      */
+    CAN0_RX1_IRQn                = 40,     /*!< CAN0 RX1 interrupts                                      */
+    CAN0_EWMC_IRQn               = 41,     /*!< CAN0 EWMC interrupts                                     */
+    EXTI5_9_IRQn                 = 42,     /*!< EXTI[9:5] interrupts                                     */
+    TIMER0_BRK_IRQn              = 43,     /*!< TIMER0 break interrupts                                  */
+    TIMER0_UP_IRQn               = 44,     /*!< TIMER0 update interrupts                                 */
+    TIMER0_TRG_CMT_IRQn          = 45,     /*!< TIMER0 trigger and commutation interrupts                */
+    TIMER0_Channel_IRQn          = 46,     /*!< TIMER0 channel capture compare interrupts                */
+    TIMER1_IRQn                  = 47,     /*!< TIMER1 interrupt                                         */
+    TIMER2_IRQn                  = 48,     /*!< TIMER2 interrupt                                         */
+    TIMER3_IRQn                  = 49,     /*!< TIMER3 interrupts                                        */
+    I2C0_EV_IRQn                 = 50,     /*!< I2C0 event interrupt                                     */
+    I2C0_ER_IRQn                 = 51,     /*!< I2C0 error interrupt                                     */
+    I2C1_EV_IRQn                 = 52,     /*!< I2C1 event interrupt                                     */
+    I2C1_ER_IRQn                 = 53,     /*!< I2C1 error interrupt                                     */
+    SPI0_IRQn                    = 54,     /*!< SPI0 interrupt                                           */
+    SPI1_IRQn                    = 55,     /*!< SPI1 interrupt                                           */
+    USART0_IRQn                  = 56,     /*!< USART0 interrupt                                         */
+    USART1_IRQn                  = 57,     /*!< USART1 interrupt                                         */
+    USART2_IRQn                  = 58,     /*!< USART2 interrupt                                         */
+    EXTI10_15_IRQn               = 59,     /*!< EXTI[15:10] interrupts                                   */
+    RTC_ALARM_IRQn               = 60,     /*!< RTC alarm interrupt EXTI                                 */
+    USBFS_WKUP_IRQn              = 61,     /*!< USBFS wakeup interrupt                                   */
+
+    EXMC_IRQn                    = 67,     /*!< EXMC global interrupt                                    */
+
+    TIMER4_IRQn                  = 69,     /*!< TIMER4 global interrupt                                  */
+    SPI2_IRQn                    = 70,     /*!< SPI2 global interrupt                                    */
+    UART3_IRQn                   = 71,     /*!< UART3 global interrupt                                   */
+    UART4_IRQn                   = 72,     /*!< UART4 global interrupt                                   */
+    TIMER5_IRQn                  = 73,     /*!< TIMER5 global interrupt                                  */
+    TIMER6_IRQn                  = 74,     /*!< TIMER6 global interrupt                                  */
+    DMA1_Channel0_IRQn           = 75,     /*!< DMA1 channel0 global interrupt                           */
+    DMA1_Channel1_IRQn           = 76,     /*!< DMA1 channel1 global interrupt                           */
+    DMA1_Channel2_IRQn           = 77,     /*!< DMA1 channel2 global interrupt                           */
+    DMA1_Channel3_IRQn           = 78,     /*!< DMA1 channel3 global interrupt                           */
+    DMA1_Channel4_IRQn           = 79,     /*!< DMA1 channel3 global interrupt                           */
+
+    CAN1_TX_IRQn                 = 82,     /*!< CAN1 TX interrupt                                        */
+    CAN1_RX0_IRQn                = 83,     /*!< CAN1 RX0 interrupt                                       */
+    CAN1_RX1_IRQn                = 84,     /*!< CAN1 RX1 interrupt                                       */
+    CAN1_EWMC_IRQn               = 85,     /*!< CAN1 EWMC interrupt                                      */
+    USBFS_IRQn                   = 86,     /*!< USBFS global interrupt                                   */
+
+	ECLIC_NUM_INTERRUPTS
+} IRQn_Type;
+
+/* includes */
+#include "system_gd32vf103.h"
+#include <stdint.h>
+
+/* enum definitions */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+typedef enum {RESET = 0, SET = 1,MAX = 0X7FFFFFFF} FlagStatus;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
+
+/* bit operations */
+#define REG32(addr)                  (*(volatile uint32_t *)(uint32_t)(addr))
+#define REG16(addr)                  (*(volatile uint16_t *)(uint32_t)(addr))
+#define REG8(addr)                   (*(volatile uint8_t *)(uint32_t)(addr))
+#define BIT(x)                       ((uint32_t)((uint32_t)0x01U<<(x)))
+#define BITS(start, end)             ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 
+#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
+
+/* main flash and SRAM memory map */
+#define FLASH_BASE            ((uint32_t)0x08000000U)        /*!< main FLASH base address          */
+#define SRAM_BASE             ((uint32_t)0x20000000U)        /*!< SRAM0 base address               */
+#define OB_BASE               ((uint32_t)0x1FFFF800U)        /*!< OB base address                  */
+#define DBG_BASE              ((uint32_t)0xE0042000U)        /*!< DBG base address                 */
+#define EXMC_BASE             ((uint32_t)0xA0000000U)        /*!< EXMC register base address       */
+
+/* peripheral memory map */
+#define APB1_BUS_BASE         ((uint32_t)0x40000000U)        /*!< apb1 base address                */
+#define APB2_BUS_BASE         ((uint32_t)0x40010000U)        /*!< apb2 base address                */
+#define AHB1_BUS_BASE         ((uint32_t)0x40018000U)        /*!< ahb1 base address                */
+#define AHB3_BUS_BASE         ((uint32_t)0x60000000U)        /*!< ahb3 base address                */
+
+/* advanced peripheral bus 1 memory map */
+#define TIMER_BASE            (APB1_BUS_BASE + 0x00000000U)  /*!< TIMER base address               */
+#define RTC_BASE              (APB1_BUS_BASE + 0x00002800U)  /*!< RTC base address                 */
+#define WWDGT_BASE            (APB1_BUS_BASE + 0x00002C00U)  /*!< WWDGT base address               */
+#define FWDGT_BASE            (APB1_BUS_BASE + 0x00003000U)  /*!< FWDGT base address               */
+#define SPI_BASE              (APB1_BUS_BASE + 0x00003800U)  /*!< SPI base address                 */
+#define USART_BASE            (APB1_BUS_BASE + 0x00004400U)  /*!< USART base address               */
+#define I2C_BASE              (APB1_BUS_BASE + 0x00005400U)  /*!< I2C base address                 */
+#define CAN_BASE              (APB1_BUS_BASE + 0x00006400U)  /*!< CAN base address                 */
+#define BKP_BASE              (APB1_BUS_BASE + 0x00006C00U)  /*!< BKP base address                 */
+#define PMU_BASE              (APB1_BUS_BASE + 0x00007000U)  /*!< PMU base address                 */
+#define DAC_BASE              (APB1_BUS_BASE + 0x00007400U)  /*!< DAC base address                 */
+
+/* advanced peripheral bus 2 memory map */
+#define AFIO_BASE             (APB2_BUS_BASE + 0x00000000U)  /*!< AFIO base address                */
+#define EXTI_BASE             (APB2_BUS_BASE + 0x00000400U)  /*!< EXTI base address                */
+#define GPIO_BASE             (APB2_BUS_BASE + 0x00000800U)  /*!< GPIO base address                */
+#define ADC_BASE              (APB2_BUS_BASE + 0x00002400U)  /*!< ADC base address                 */
+
+/* advanced high performance bus 1 memory map */
+#define DMA_BASE              (AHB1_BUS_BASE + 0x00008000U)  /*!< DMA base address                 */
+#define RCU_BASE              (AHB1_BUS_BASE + 0x00009000U)  /*!< RCU base address                 */
+#define FMC_BASE              (AHB1_BUS_BASE + 0x0000A000U)  /*!< FMC base address                 */
+#define CRC_BASE              (AHB1_BUS_BASE + 0x0000B000U)  /*!< CRC base address                 */
+#define USBFS_BASE            (AHB1_BUS_BASE + 0x0FFE8000U)  /*!< USBFS base address               */
+
+/* define marco USE_STDPERIPH_DRIVER */
+#if !defined  USE_STDPERIPH_DRIVER
+#define USE_STDPERIPH_DRIVER
+#endif 
+#ifdef USE_STDPERIPH_DRIVER
+#include "gd32vf103_libopt.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+#ifdef cplusplus
+}
+#endif
+#endif 
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.c
new file mode 100644
index 0000000000..613ef2fa75
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.c
@@ -0,0 +1,998 @@
+/*!
+ \file    system_gd32vf103.c
+ \brief   RISC-V Device Peripheral Access Layer Source File for
+ GD32VF103 Device Series
+
+ \version 2019-6-5, V1.0.0, firmware for GD32VF103
+ */
+
+/*
+ Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+ are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ OF SUCH DAMAGE.
+ */
+
+/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */
+
+#include "gd32vf103.h"
+
+/* system frequency define */
+#define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
+#define __HXTAL           (HXTAL_VALUE)            /* high speed crystal oscillator frequency */
+#define __SYS_OSC_CLK     (__IRC8M)                /* main oscillator frequency */
+
+/* select a system clock by uncommenting the following line */
+/* use IRC8M */
+//#define __SYSTEM_CLOCK_48M_PLL_IRC8M            (uint32_t)(48000000)
+//#define __SYSTEM_CLOCK_72M_PLL_IRC8M            (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_108M_PLL_IRC8M           (uint32_t)(108000000)
+/********************************************************************/
+//#define __SYSTEM_CLOCK_HXTAL                    (HXTAL_VALUE)
+//#define __SYSTEM_CLOCK_24M_PLL_HXTAL            (uint32_t)(24000000)
+/********************************************************************/
+
+//#define __SYSTEM_CLOCK_36M_PLL_HXTAL            (uint32_t)(36000000)
+//#define __SYSTEM_CLOCK_48M_PLL_HXTAL            (uint32_t)(48000000)
+//#define __SYSTEM_CLOCK_56M_PLL_HXTAL            (uint32_t)(56000000)
+//#define __SYSTEM_CLOCK_72M_PLL_HXTAL            (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_96M_PLL_HXTAL            (uint32_t)(96000000)
+#define __SYSTEM_CLOCK_108M_PLL_HXTAL           (uint32_t)(108000000)
+
+#define SEL_IRC8M       0x00U
+#define SEL_HXTAL       0x01U
+#define SEL_PLL         0x02U
+
+/* set the system clock frequency and declare the system clock configuration function */
+#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M;
+static void system_clock_48m_irc8m(void);
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M;
+static void system_clock_72m_irc8m(void);
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M;
+static void system_clock_108m_irc8m(void);
+
+#elif defined (__SYSTEM_CLOCK_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
+static void system_clock_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL;
+static void system_clock_24m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL;
+static void system_clock_36m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
+static void system_clock_48m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL;
+static void system_clock_56m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
+static void system_clock_72m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
+static void system_clock_96m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
+static void system_clock_108m_hxtal(void);
+#else
+uint32_t SystemCoreClock = IRC8M_VALUE;
+#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */
+
+/* configure the system clock */
+static void system_clock_config(void);
+
+/*!
+ \brief      configure the system clock
+ \param[in]  none
+ \param[out] none
+ \retval     none
+ */
+static void system_clock_config(void) {
+#ifdef __SYSTEM_CLOCK_HXTAL
+    system_clock_hxtal();
+#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
+    system_clock_24m_hxtal();
+#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
+    system_clock_36m_hxtal();
+#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
+    system_clock_48m_hxtal();
+#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
+    system_clock_56m_hxtal();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+    system_clock_72m_hxtal();
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+    system_clock_96m_hxtal();
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+    system_clock_108m_hxtal();
+
+#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
+    system_clock_48m_irc8m();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
+    system_clock_72m_irc8m();
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
+    system_clock_108m_irc8m();
+#endif /* __SYSTEM_CLOCK_HXTAL */
+}
+
+/*!
+ \brief      setup the microcontroller system, initialize the system
+ \param[in]  none
+ \param[out] none
+ \retval     none
+ */
+void SystemInit(void) {
+    /* reset the RCC clock configuration to the default reset state */
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+
+    /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */
+    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC
+            | RCU_CFG0_APB2PSC |
+            RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
+
+    /* reset HXTALEN, CKMEN, PLLEN bits */
+    RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
+
+    /* Reset HXTALBPS bit */
+    RCU_CTL &= ~(RCU_CTL_HXTALBPS);
+
+    /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */
+
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
+    RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
+    RCU_CFG1 = 0x00000000U;
+
+    /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
+    RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN
+            | RCU_CTL_HXTALEN);
+    /* disable all interrupts */
+    RCU_INT = 0x00FF0000U;
+
+    /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
+    system_clock_config();
+}
+
+/*!
+ \brief      update the SystemCoreClock with current core clock retrieved from cpu registers
+ \param[in]  none
+ \param[out] none
+ \retval     none
+ */
+void SystemCoreClockUpdate(void) {
+    uint32_t scss;
+    uint32_t pllsel, predv0sel, pllmf, ck_src;
+    uint32_t predv0, predv1, pll1mf;
+
+    scss = GET_BITS(RCU_CFG0, 2, 3);
+
+    switch (scss) {
+    /* IRC8M is selected as CK_SYS */
+    case SEL_IRC8M:
+        SystemCoreClock = IRC8M_VALUE;
+        break;
+
+        /* HXTAL is selected as CK_SYS */
+    case SEL_HXTAL:
+        SystemCoreClock = HXTAL_VALUE;
+        break;
+
+        /* PLL is selected as CK_SYS */
+    case SEL_PLL:
+        /* PLL clock source selection, HXTAL or IRC8M/2 */
+        pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
+
+        if (RCU_PLLSRC_IRC8M_DIV2 == pllsel) {
+            /* PLL clock source is IRC8M/2 */
+            ck_src = IRC8M_VALUE / 2U;
+        } else {
+            /* PLL clock source is HXTAL */
+            ck_src = HXTAL_VALUE;
+
+            predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
+
+            /* source clock use PLL1 */
+            if (RCU_PREDV0SRC_CKPLL1 == predv0sel) {
+                predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
+                pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
+                if (17U == pll1mf) {
+                    pll1mf = 20U;
+                }
+                ck_src = (ck_src / predv1) * pll1mf;
+            }
+            predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
+            ck_src /= predv0;
+        }
+
+        /* PLL multiplication factor */
+        pllmf = GET_BITS(RCU_CFG0, 18, 21);
+
+        if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) {
+            pllmf |= 0x10U;
+        }
+
+        if (pllmf >= 15U) {
+            pllmf += 1U;
+        } else {
+            pllmf += 2U;
+        }
+
+        SystemCoreClock = ck_src * pllmf;
+
+        if (15U == pllmf) {
+            /* PLL source clock multiply by 6.5 */
+            SystemCoreClock = ck_src * 6U + ck_src / 2U;
+        }
+
+        break;
+
+        /* IRC8M is selected as CK_SYS */
+    default:
+        SystemCoreClock = IRC8M_VALUE;
+        break;
+    }
+}
+
+#ifdef __SYSTEM_CLOCK_HXTAL
+/*!
+    \brief      configure the system clock to HXTAL
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+    
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+    
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+    
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    
+    /* select HXTAL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
+    
+    /* wait until HXTAL is selected as system clock */
+    while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_24m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6);
+
+    if(HXTAL_VALUE==25000000){
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+		RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+		RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_36m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
+
+    if(HXTAL_VALUE==25000000){
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+		RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+		RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_48m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12);
+
+    if(HXTAL_VALUE==25000000){
+
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+		RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+		RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_56m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14);
+
+    if(HXTAL_VALUE==25000000){
+
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+		RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+		RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ 
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18);
+
+
+    if(HXTAL_VALUE==25000000){
+
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+		RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+		RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_96m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    if(HXTAL_VALUE==25000000){
+
+        /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */
+        RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+        RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24);
+
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+        /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */
+        RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+        RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24);
+
+		RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+		RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+/*!
+ \brief      configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+ \param[in]  none
+ \param[out] none
+ \retval     none
+ */
+
+static void system_clock_108m_hxtal(void) {
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do {
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
+        while (1) {
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27);
+
+    if (HXTAL_VALUE == 25000000) {
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF
+                | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8
+                | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {
+        }
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL2EN;
+        /* wait till PLL1 is ready */
+        while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {
+        }
+    } else if (HXTAL_VALUE == 8000000) {
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF
+                | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2
+                | RCU_PLL1_MUL20 | RCU_PLL2_MUL20);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {
+        }
+
+        /* enable PLL2 */
+        RCU_CTL |= RCU_CTL_PLL2EN;
+        /* wait till PLL1 is ready */
+        while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {
+        }
+
+    }
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
+/*!
+    \brief      configure the system clock to 48M by PLL which selects IRC8M as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_48m_irc8m(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+
+    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
+    }
+    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
+      while(1){
+      }
+    }
+
+    /* IRC8M is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= RCU_PLL_MUL12;
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects IRC8M as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_irc8m(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+
+    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
+    }
+    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
+      while(1){
+      }
+    }
+
+    /* IRC8M is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= RCU_PLL_MUL18;
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
+/*!
+    \brief      configure the system clock to 108M by PLL which selects IRC8M as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_108m_irc8m(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+
+    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
+    }
+    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
+      while(1){
+      }
+    }
+
+    /* IRC8M is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= RCU_PLL_MUL27;
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#endif
diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.h
new file mode 100644
index 0000000000..a31319bd75
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.h
@@ -0,0 +1,60 @@
+/*!
+ \file    system_gd32vf103.h
+ \brief   RISC-V Device Peripheral Access Layer Header File for
+ GD32VF103 Device Series
+
+ \version 2019-6-5, V1.0.0, firmware for GD32VF103
+ */
+
+/*
+ Copyright (c) 2019, GigaDevice Semiconductor Inc.
+
+ Redistribution and use in source and binary forms, with or without modification,
+ are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ OF SUCH DAMAGE.
+ */
+
+/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */
+
+#ifndef SYSTEM_GD32VF103_H
+#define SYSTEM_GD32VF103_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* system clock frequency (core clock) */
+extern uint32_t SystemCoreClock;
+
+/* function declarations */
+/* initialize the system and update the SystemCoreClock variable */
+extern void SystemInit(void);
+/* update the SystemCoreClock with current core clock retrieved from cpu registers */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_GD32VF103_H */
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/core_v5.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/core_v5.h
new file mode 100644
index 0000000000..3ce586e90e
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/core_v5.h
@@ -0,0 +1,127 @@
+#ifndef __CORE_V5_H__
+#define __CORE_V5_H__
+
+#define MSTATUS_UIE         	0x00000001
+#define MSTATUS_SIE         	0x00000002
+#define MSTATUS_HIE         	0x00000004
+#define MSTATUS_MIE         	0x00000008
+#define MSTATUS_UPIE        	0x00000010
+#define MSTATUS_SPIE        	0x00000020
+#define MSTATUS_HPIE        	0x00000040
+#define MSTATUS_MPIE        	0x00000080
+#define MSTATUS_SPP         	0x00000100
+#define MSTATUS_HPP         	0x00000600
+#define MSTATUS_MPP         	0x00001800
+#define MSTATUS_FS          	0x00006000
+#define MSTATUS_XS          	0x00018000
+#define MSTATUS_MPRV        	0x00020000
+#define MSTATUS_PUM         	0x00040000
+#define MSTATUS_MXR				0x00080000
+#define MSTATUS_VM          	0x1F000000
+#define MSTATUS32_SD        	0x80000000
+#define MSTATUS64_SD        	0x8000000000000000
+
+#if __riscv_xlen == 64
+#define MCAUSE_INT          	0x8000000000000000UL
+#define MCAUSE_CAUSE        	0x7FFFFFFFFFFFFFFFUL
+#else
+#define MCAUSE_INT          	0x80000000UL
+#define MCAUSE_CAUSE        	0x7FFFFFFFUL
+#endif
+
+#define IRQ_S_SOFT          	1
+#define IRQ_H_SOFT          	2
+#define IRQ_M_SOFT          	3
+#define IRQ_S_TIMER         	5
+#define IRQ_H_TIMER         	6
+#define IRQ_M_TIMER         	7
+#define IRQ_S_EXT           	9
+#define IRQ_H_EXT           	10
+#define IRQ_M_EXT           	11
+#define IRQ_COP             	12
+#define IRQ_HOST            	13
+
+/* Machine mode MCAUSE */
+#define TRAP_M_I_ACC_FAULT    	1   /* Instruction access fault */
+#define TRAP_M_L_ACC_FAULT   	5   /* Data load access fault */
+#define TRAP_M_S_ACC_FAULT   	7   /* Data store access fault */
+#define TRAP_U_ECALL        	8
+#define TRAP_S_ECALL        	9
+#define TRAP_H_ECALL        	10
+#define TRAP_M_ECALL        	11
+#define TRAP_M_I_PAGE_FAULT	12  /* Instruction page fault */
+#define TRAP_M_L_PAGE_FAULT	13  /* Data load page fault */
+#define TRAP_M_S_PAGE_FAULT	15  /* Data store page fault */
+#define TRAP_M_STACKOVF     	32
+#define TRAP_M_STACKUDF     	33
+
+/* Supervisor mode SCAUSE */
+#define TRAP_S_I_ACC_FAULT    	1   /* Instruction access fault */
+#define TRAP_S_L_ACC_FAULT   	5   /* Data load access fault */
+#define TRAP_S_S_ACC_FAULT   	7   /* Data store access fault */
+#define TRAP_S_I_PAGE_FAULT	12  /* Instruction page fault */
+#define TRAP_S_L_PAGE_FAULT	13  /* Data load page fault */
+#define TRAP_S_S_PAGE_FAULT	15  /* Data store page fault */
+
+#define MIP_SSIP            	(1 << IRQ_S_SOFT)
+#define MIP_HSIP            	(1 << IRQ_H_SOFT)
+#define MIP_MSIP            	(1 << IRQ_M_SOFT)
+#define MIP_STIP            	(1 << IRQ_S_TIMER)
+#define MIP_HTIP            	(1 << IRQ_H_TIMER)
+#define MIP_MTIP            	(1 << IRQ_M_TIMER)
+#define MIP_SEIP            	(1 << IRQ_S_EXT)
+#define MIP_HEIP            	(1 << IRQ_H_EXT)
+#define MIP_MEIP            	(1 << IRQ_M_EXT)
+
+/* MILMB and MDLMB */
+#define	MILMB_IEN		(0x1UL)
+#define	MDLMB_DEN		(0x1UL)
+
+#if __riscv_xlen == 64
+# define SLL32    		sllw
+# define STORE    		sd
+# define LOAD     		ld
+# define LWU      		lwu
+# define LOG_REGBYTES 		3
+#else
+# define SLL32    		sll
+# define STORE    		sw
+# define LOAD     		lw
+# define LWU      		lw
+# define LOG_REGBYTES		2
+#endif
+#define REGBYTES		(1 << LOG_REGBYTES)
+
+#if __riscv_flen == 64
+# define FPSTORE		fsd
+# define FPLOAD			fld
+# define LOG_FPREGBYTES		3
+#else
+# define FPSTORE		fsw
+# define FPLOAD			flw
+# define LOG_FPREGBYTES		2
+#endif
+#define FPREGBYTES              (1 << LOG_FPREGBYTES)
+
+#define STR(S)			#S
+#define XSTR(S)			STR(S)
+
+#define PUSH			XSTR(STORE)
+#define POP			XSTR(LOAD)
+#define REGSIZE			XSTR(REGBYTES)
+#define FPPUSH			XSTR(FPSTORE)
+#define FPPOP			XSTR(FPLOAD)
+#define FPREGSIZE		XSTR(FPREGBYTES)
+
+#ifndef __ASSEMBLER__
+
+
+#define read_csr(reg)		__nds__csrr(reg)
+#define write_csr(reg, val)	__nds__csrw(val, reg)
+#define swap_csr(reg, val)	__nds__csrrw(val, reg)
+#define set_csr(reg, bit)	__nds__csrrs(bit, reg)
+#define clear_csr(reg, bit)	__nds__csrrc(bit, reg)
+
+#endif
+
+#endif	// __CORE_V5_H__
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_eclic.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_eclic.h
new file mode 100644
index 0000000000..a91c3aafc4
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_eclic.h
@@ -0,0 +1,47 @@
+// See LICENSE file for licence details
+
+#ifndef N22_ECLIC_H
+#define N22_ECLIC_H
+#include <riscv_const.h>
+
+#define ECLICINTCTLBITS  4
+
+//ECLIC memory map
+//   Offset
+//  0x0000       1B          RW        ecliccfg
+#define ECLIC_CFG_OFFSET            0x0
+//  0x0004       4B          R         eclicinfo
+#define ECLIC_INFO_OFFSET           0x4
+//  0x000B       1B          RW        mintthresh 
+#define ECLIC_MTH_OFFSET            0xB
+//
+//  0x1000+4*i   1B/input    RW        eclicintip[i]
+#define ECLIC_INT_IP_OFFSET            _AC(0x1000,UL)
+//  0x1001+4*i   1B/input    RW        eclicintie[i]
+#define ECLIC_INT_IE_OFFSET            _AC(0x1001,UL)
+//  0x1002+4*i   1B/input    RW        eclicintattr[i]
+#define ECLIC_INT_ATTR_OFFSET          _AC(0x1002,UL)
+
+#define ECLIC_INT_ATTR_SHV              0x01
+#define ECLIC_INT_ATTR_TRIG_LEVEL       0x00
+#define ECLIC_INT_ATTR_TRIG_EDGE        0x02
+#define ECLIC_INT_ATTR_TRIG_POS         0x00
+#define ECLIC_INT_ATTR_TRIG_NEG         0x04
+
+//  0x1003+4*i   1B/input    RW        eclicintctl[i]
+#define ECLIC_INT_CTRL_OFFSET          _AC(0x1003,UL)
+//
+//  ...
+//
+#define ECLIC_ADDR_BASE           0xd2000000
+
+
+#define ECLIC_CFG_NLBITS_MASK          _AC(0x1E,UL)
+#define ECLIC_CFG_NLBITS_LSB     (1u)
+
+#define MSIP_HANDLER    eclic_msip_handler
+#define MTIME_HANDLER   eclic_mtip_handler
+#define BWEI_HANDLER    eclic_bwei_handler
+#define PMOVI_HANDLER   eclic_pmovi_handler
+
+#endif
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.c b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.c
new file mode 100644
index 0000000000..1f89ffd8da
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.c
@@ -0,0 +1,279 @@
+// See LICENSE for license details.
+#include <gd32vf103.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "riscv_encoding.h"
+#include "n22_func.h"
+
+void switch_m2u_mode() {
+    clear_csr(mstatus, MSTATUS_MPP);
+    //printf("\nIn the m2u function, the mstatus is 0x%x\n", read_csr(mstatus));
+    //printf("\nIn the m2u function, the mepc is 0x%x\n", read_csr(mepc));
+    asm volatile ("la x6, 1f    ":::"x6");
+    asm volatile ("csrw mepc, x6":::);
+    asm volatile ("mret":::);
+    asm volatile ("1:":::);
+}
+
+uint32_t mtime_lo(void) {
+    return *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME);
+}
+
+uint32_t mtime_hi(void) {
+    return *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 4);
+}
+
+void enable_timer_interrupt(void) {
+    *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 0xffc) = 1;
+}
+
+void clear_timer_interrupt(void) {
+    *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 0xffc) = 0;
+}
+
+void close_timer(void) {
+    *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 0xff8) = 1;
+}
+
+void open_timer(void) {
+    *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 0xff8) = 0;
+}
+
+uint64_t get_timer_value() {
+    while (1) {
+        uint32_t hi = mtime_hi();
+        uint32_t lo = mtime_lo();
+
+        if (hi == mtime_hi())
+            return ((uint64_t) hi << 32) | lo;
+    }
+}
+
+uint32_t get_timer_freq() {
+    return TMR_FREQ;
+}
+
+uint64_t get_instret_value() {
+    while (1) {
+        uint32_t hi = read_csr(minstreth);
+        uint32_t lo = read_csr(minstret);
+        if (hi == read_csr(minstreth))
+            return ((uint64_t) hi << 32) | lo;
+    }
+}
+
+uint64_t get_cycle_value() {
+    while (1) {
+        uint32_t hi = read_csr(mcycleh);
+        uint32_t lo = read_csr(mcycle);
+        if (hi == read_csr(mcycleh))
+            return ((uint64_t) hi << 32) | lo;
+    }
+}
+// Note that there are no assertions or bounds checking on these
+// parameter values.
+
+void eclic_init(uint32_t num_irq) {
+    typedef volatile uint32_t vuint32_t;
+
+    //clear cfg register 
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET) = 0;
+
+    //clear minthresh register 
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET) = 0;
+
+    //clear all IP/IE/ATTR/CTRL bits for all interrupt sources
+    vuint32_t * ptr;
+
+    vuint32_t * base = (vuint32_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET);
+    vuint32_t * upper = (vuint32_t*) (base + num_irq * 4);
+
+    for (ptr = base; ptr < upper; ptr = ptr + 4) {
+        *ptr = 0;
+    }
+    eclic_set_nlbits(ECLIC_GROUP_LEVEL2_PRIO2);
+}
+
+void eclic_enable_interrupt(uint32_t source) {
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IE_OFFSET + source * 4) =
+            1;
+}
+
+void eclic_disable_interrupt(uint32_t source) {
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IE_OFFSET + source * 4) =
+            0;
+}
+
+void eclic_set_pending(uint32_t source) {
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET + source * 4) =
+            1;
+}
+
+void eclic_clear_pending(uint32_t source) {
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET + source * 4) =
+            0;
+}
+
+void eclic_set_intctrl(uint32_t source, uint8_t intctrl) {
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_CTRL_OFFSET + source * 4) =
+            intctrl;
+}
+
+uint8_t eclic_get_intctrl(uint32_t source) {
+    return *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_CTRL_OFFSET
+            + source * 4);
+}
+
+void eclic_set_intattr(uint32_t source, uint8_t intattr) {
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_ATTR_OFFSET + source * 4) =
+            intattr;
+}
+
+uint8_t eclic_get_intattr(uint32_t source) {
+    return *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_ATTR_OFFSET
+            + source * 4);
+}
+
+void eclic_set_ecliccfg(uint8_t ecliccfg) {
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET) = ecliccfg;
+}
+
+uint8_t eclic_get_ecliccfg() {
+    return *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET);
+}
+
+void eclic_set_mth(uint8_t mth) {
+    *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET) = mth;
+}
+
+uint8_t eclic_get_mth() {
+    return *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET);
+}
+
+void eclic_set_nlbits(uint8_t nlbits) {
+    //shift nlbits to correct position
+    uint8_t nlbits_shifted = nlbits << ECLIC_CFG_NLBITS_LSB;
+
+    //read the current ecliccfg
+    uint8_t old_ecliccfg = eclic_get_ecliccfg();
+    uint8_t new_ecliccfg = (old_ecliccfg & (~ECLIC_CFG_NLBITS_MASK))
+            | (ECLIC_CFG_NLBITS_MASK & nlbits_shifted);
+
+    eclic_set_ecliccfg(new_ecliccfg);
+}
+
+uint8_t eclic_get_nlbits(void) {
+    //extract nlbits
+    uint8_t nlbits = eclic_get_ecliccfg();
+    nlbits = (nlbits & ECLIC_CFG_NLBITS_MASK) >> ECLIC_CFG_NLBITS_LSB;
+    return nlbits;
+}
+
+//sets an interrupt level based encoding of nlbits and ECLICINTCTLBITS
+uint8_t eclic_set_int_level(uint32_t source, uint8_t level) {
+    //extract nlbits
+    uint8_t nlbits = eclic_get_nlbits();
+    if (nlbits > ECLICINTCTLBITS) {
+        nlbits = ECLICINTCTLBITS;
+    }
+
+    //shift level into correct bit position
+    level = level << (8 - nlbits);
+
+    //write to eclicintctrl
+    uint8_t current_intctrl = eclic_get_intctrl(source);
+    //shift intctrl left to mask off unused bits
+    current_intctrl = current_intctrl << nlbits;
+    //shift intctrl into correct bit position
+    current_intctrl = current_intctrl >> nlbits;
+
+    eclic_set_intctrl(source, (current_intctrl | level));
+
+    return level;
+}
+
+//gets an interrupt level based encoding of nlbits
+uint8_t eclic_get_int_level(uint32_t source) {
+    //extract nlbits
+    uint8_t nlbits = eclic_get_nlbits();
+    if (nlbits > ECLICINTCTLBITS) {
+        nlbits = ECLICINTCTLBITS;
+    }
+
+    uint8_t intctrl = eclic_get_intctrl(source);
+
+    //shift intctrl
+    intctrl = intctrl >> (8 - nlbits);
+    //shift intctrl
+    uint8_t level = intctrl << (8 - nlbits);
+
+    return level;
+}
+
+//sets an interrupt priority based encoding of nlbits and ECLICINTCTLBITS
+uint8_t eclic_set_int_priority(uint32_t source, uint8_t priority) {
+    //extract nlbits
+    uint8_t nlbits = eclic_get_nlbits();
+    if (nlbits >= ECLICINTCTLBITS) {
+        nlbits = ECLICINTCTLBITS;
+        return 0;
+    }
+
+    //shift priority into correct bit position
+    priority = priority << (8 - ECLICINTCTLBITS);
+
+    //write to eclicintctrl
+    uint8_t current_intctrl = eclic_get_intctrl(source);
+    //shift intctrl right to mask off unused bits
+    current_intctrl = current_intctrl >> (8 - nlbits);
+    //shift intctrl into correct bit position
+    current_intctrl = current_intctrl << (8 - nlbits);
+
+    eclic_set_intctrl(source, (current_intctrl | priority));
+
+    return priority;
+}
+
+//gets an interrupt priority based encoding of nlbits
+uint8_t eclic_get_int_priority(uint32_t source) {
+    //extract nlbits
+    uint8_t nlbits = eclic_get_nlbits();
+    if (nlbits > ECLICINTCTLBITS) {
+        nlbits = ECLICINTCTLBITS;
+    }
+
+    uint8_t intctrl = eclic_get_intctrl(source);
+
+    //shift intctrl
+    intctrl = intctrl << nlbits;
+    //shift intctrl
+    uint8_t priority = intctrl >> (nlbits + (8 - ECLICINTCTLBITS));
+
+    return priority;
+}
+
+void eclic_mode_enable() {
+    uint32_t mtvec_value = read_csr(mtvec);
+    mtvec_value = mtvec_value & 0xFFFFFFC0;
+    mtvec_value = mtvec_value | 0x00000003;
+    write_csr(mtvec, mtvec_value);
+}
+
+void eclic_set_shv(uint32_t source, uint8_t shv) {
+    uint8_t attr = eclic_get_intattr(source);
+    if (shv) {
+        attr |= 0x01;
+        eclic_set_intattr(source, attr);
+    }
+}
+
+void eclic_set_trig(uint32_t source, uint8_t trig) {
+    uint8_t attr = eclic_get_intattr(source);
+    if ((trig & 0x1)) {
+        attr |= (trig << 1);
+        eclic_set_intattr(source, attr);
+    }
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.h
new file mode 100644
index 0000000000..614efebec0
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.h
@@ -0,0 +1,82 @@
+// See LICENSE file for licence details
+
+#ifndef N22_FUNC_H
+#define N22_FUNC_H
+
+
+#include "n22_tmr.h"
+#include "n22_eclic.h"
+
+#define	ECLIC_GROUP_LEVEL0_PRIO4	0
+#define	ECLIC_GROUP_LEVEL1_PRIO3	1
+#define	ECLIC_GROUP_LEVEL2_PRIO2	2
+#define	ECLIC_GROUP_LEVEL3_PRIO1	3
+#define	ECLIC_GROUP_LEVEL4_PRIO0	4
+
+void switch_m2u_mode();
+uint32_t get_tmr_freq();
+uint32_t mtime_lo(void);
+uint32_t mtime_hi(void);
+uint64_t get_timer_value();
+uint64_t get_instret_value();
+uint64_t get_cycle_value();
+
+void eclic_init(uint32_t num_irq);
+
+void eclic_enable_interrupt(uint32_t source);
+void eclic_disable_interrupt(uint32_t source);
+
+void eclic_set_pending(uint32_t source);
+void eclic_clear_pending(uint32_t source);
+
+void eclic_set_intctrl(uint32_t source, uint8_t intctrl);
+uint8_t eclic_get_intctrl(uint32_t source);
+
+void eclic_set_intattr(uint32_t source, uint8_t intattr);
+uint8_t eclic_get_intattr(uint32_t source);
+
+void eclic_set_ecliccfg(uint8_t ecliccfg);
+uint8_t eclic_get_ecliccfg();
+
+void eclic_set_mth(uint8_t mth);
+uint8_t eclic_get_mth();
+
+void eclic_set_nlbits(uint8_t nlbits);
+uint8_t eclic_get_nlbits();
+
+uint8_t eclic_set_int_level(uint32_t source, uint8_t level);
+uint8_t eclic_get_int_level(uint32_t source);
+
+uint8_t eclic_set_int_priority(uint32_t source, uint8_t priority);
+uint8_t eclic_get_int_priority(uint32_t source);
+
+void eclic_mode_enable();
+void eclic_set_shv(uint32_t source, uint8_t shv);
+void eclic_set_trig(uint32_t source, uint8_t trig);
+
+///** \brief  Wait For Interrupt
+//
+//    Wait For Interrupt is a hint instruction that suspends execution
+//    until one of a number of events occurs.
+// */
+__attribute__( ( always_inline ) ) static inline void __WFI(void) {
+	__asm volatile ("wfi");
+}
+//
+//
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static inline  void __WFE(void)
+{
+  __asm volatile ("wfi");
+}
+
+void close_timer(void);
+void open_timer(void);
+void enable_timer_interrupt(void);
+void clear_timer_interrupt(void);
+
+#endif
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_tmr.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_tmr.h
new file mode 100644
index 0000000000..2645f73304
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_tmr.h
@@ -0,0 +1,17 @@
+// See LICENSE file for licence details
+
+#ifndef N22_TMR_H
+#define N22_TMR_H
+
+#define TMR_MSIP 0xFFC
+#define TMR_MSIP_size   0x4
+#define TMR_MTIMECMP 0x8
+#define TMR_MTIMECMP_size 0x8
+#define TMR_MTIME 0x0
+#define TMR_MTIME_size 0x8
+
+#define TMR_CTRL_ADDR           0xd1000000
+#define TMR_REG(offset)         _REG32(TMR_CTRL_ADDR, offset)
+#define TMR_FREQ	            ((uint32_t)SystemCoreClock/4)  //units HZ
+
+#endif
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_bits.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_bits.h
new file mode 100644
index 0000000000..bfe656feb0
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_bits.h
@@ -0,0 +1,36 @@
+// See LICENSE for license details.
+#ifndef _RISCV_BITS_H
+#define _RISCV_BITS_H
+
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+
+#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
+#define ROUNDDOWN(a, b) ((a)/(b)*(b))
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+
+#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define STR(x) XSTR(x)
+#define XSTR(x) #x
+
+#if __riscv_xlen == 64
+# define SLL32    sllw
+# define STORE    sd
+# define LOAD     ld
+# define LWU      lwu
+# define LOG_REGBYTES 3
+#else
+# define SLL32    sll
+# define STORE    sw
+# define LOAD     lw
+# define LWU      lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#endif
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_const.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_const.h
new file mode 100644
index 0000000000..d5dec8acaa
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_const.h
@@ -0,0 +1,18 @@
+// See LICENSE for license details.
+/* Derived from <linux/const.h> */
+
+#ifndef _RISCV_CONST_H
+#define _RISCV_CONST_H
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y)        X
+#define _AT(T,X)        X
+#else
+#define _AC(X,Y)        (X##Y)
+#define _AT(T,X)        ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x)       (_AC(1,UL) << (x))
+#define _BITULL(x)      (_AC(1,ULL) << (x))
+
+#endif /* _NUCLEI_CONST_H */
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_encoding.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_encoding.h
new file mode 100644
index 0000000000..6f0ac416ca
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_encoding.h
@@ -0,0 +1,1342 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_PUM         0x00040000
+#define MSTATUS_MXR         0x00080000
+#define MSTATUS_VM          0x1F000000
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS64_SD        0x8000000000000000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_PUM         0x00040000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define DCSR_XDEBUGVER      (3U<<30)
+#define DCSR_NDRESET        (1<<29)
+#define DCSR_FULLRESET      (1<<28)
+#define DCSR_EBREAKM        (1<<15)
+#define DCSR_EBREAKH        (1<<14)
+#define DCSR_EBREAKS        (1<<13)
+#define DCSR_EBREAKU        (1<<12)
+#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STOPTIME       (1<<9)
+#define DCSR_CAUSE          (7<<6)
+#define DCSR_DEBUGINT       (1<<5)
+#define DCSR_HALT           (1<<3)
+#define DCSR_STEP           (1<<2)
+#define DCSR_PRV            (3<<0)
+
+#define DCSR_CAUSE_NONE     0
+#define DCSR_CAUSE_SWBP     1
+#define DCSR_CAUSE_HWBP     2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP     4
+#define DCSR_CAUSE_HALT     5
+
+#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT     (1<<19)
+#define MCONTROL_TIMING     (1<<18)
+#define MCONTROL_ACTION     (0x3f<<12)
+#define MCONTROL_CHAIN      (1<<11)
+#define MCONTROL_MATCH      (0xf<<7)
+#define MCONTROL_M          (1<<6)
+#define MCONTROL_H          (1<<5)
+#define MCONTROL_S          (1<<4)
+#define MCONTROL_U          (1<<3)
+#define MCONTROL_EXECUTE    (1<<2)
+#define MCONTROL_STORE      (1<<1)
+#define MCONTROL_LOAD       (1<<0)
+
+#define MCONTROL_TYPE_NONE      0
+#define MCONTROL_TYPE_MATCH     2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
+#define MCONTROL_ACTION_DEBUG_MODE        1
+#define MCONTROL_ACTION_TRACE_START       2
+#define MCONTROL_ACTION_TRACE_STOP        3
+#define MCONTROL_ACTION_TRACE_EMIT        4
+
+#define MCONTROL_MATCH_EQUAL     0
+#define MCONTROL_MATCH_NAPOT     1
+#define MCONTROL_MATCH_GE        2
+#define MCONTROL_MATCH_LT        3
+#define MCONTROL_MATCH_MASK_LOW  4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP            (1 << IRQ_S_SOFT)
+#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_STIP            (1 << IRQ_S_TIMER)
+#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_SEIP            (1 << IRQ_S_EXT)
+#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_MEIP            (1 << IRQ_M_EXT)
+
+#define MIE_SSIE            MIP_SSIP 
+#define MIE_HSIE            MIP_HSIP 
+#define MIE_MSIE            MIP_MSIP 
+#define MIE_STIE            MIP_STIP 
+#define MIE_HTIE            MIP_HTIP 
+#define MIE_MTIE            MIP_MTIP 
+#define MIE_SEIE            MIP_SEIP 
+#define MIE_HEIE            MIP_HEIP 
+#define MIE_MEIE            MIP_MEIP 
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB   1
+#define VM_MBBID 2
+#define VM_SV32  8
+#define VM_SV39  9
+#define VM_SV48  10
+
+#define IRQ_S_SOFT   1
+#define IRQ_H_SOFT   2
+#define IRQ_M_SOFT   3
+#define IRQ_S_TIMER  5
+#define IRQ_H_TIMER  6
+#define IRQ_M_TIMER  7
+#define IRQ_S_EXT    9
+#define IRQ_H_EXT    10
+#define IRQ_M_EXT    11
+#define IRQ_COP      12
+#define IRQ_HOST     13
+
+#define DEFAULT_RSTVEC     0x00001000
+#define DEFAULT_NMIVEC     0x00001004
+#define DEFAULT_MTVEC      0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE        0x40000000
+#define DRAM_BASE          0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V     0x001 // Valid
+#define PTE_R     0x002 // Read
+#define PTE_W     0x004 // Write
+#define PTE_X     0x008 // Execute
+#define PTE_U     0x010 // User
+#define PTE_G     0x020 // Global
+#define PTE_A     0x040 // Accessed
+#define PTE_D     0x080 // Dirty
+#define PTE_SOFT  0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define write_csr(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+    asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+    asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+  else \
+    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+  __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ  0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE  0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT  0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE  0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU  0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU  0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR  0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL  0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI  0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC  0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI  0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI  0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI  0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU  0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI  0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI  0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI  0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI  0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI  0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD  0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB  0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL  0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT  0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU  0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR  0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL  0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA  0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR  0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND  0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW  0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW  0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW  0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW  0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW  0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW  0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW  0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW  0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW  0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB  0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH  0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW  0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD  0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU  0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU  0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU  0x707f
+#define MATCH_SB 0x23
+#define MASK_SB  0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH  0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW  0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD  0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE  0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I  0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL  0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH  0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU  0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU  0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV  0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU  0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM  0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU  0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW  0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW  0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW  0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW  0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW  0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W  0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W  0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W  0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W  0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W  0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W  0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W  0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W  0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W  0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W  0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W  0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D  0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D  0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D  0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D  0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D  0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D  0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D  0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D  0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D  0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D  0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D  0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL  0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK  0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET  0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET  0xffffffff
+#define MATCH_HRET 0x20200073
+#define MASK_HRET  0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET  0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET  0xffffffff
+#define MATCH_SFENCE_VM 0x10400073
+#define MASK_SFENCE_VM  0xfff07fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI  0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW  0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS  0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC  0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI  0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI  0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI  0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S  0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S  0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S  0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S  0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S  0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S  0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S  0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S  0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S  0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S  0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D  0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D  0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D  0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D  0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D  0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D  0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D  0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D  0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D  0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D  0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S  0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D  0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S  0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S  0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S  0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D  0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D  0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D  0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S  0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S  0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S  0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S  0xfff0007f
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S  0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S  0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D  0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D  0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D  0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D  0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D  0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D  0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W  0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU  0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L  0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU  0xfff0007f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X  0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W  0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU  0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L  0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU  0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X  0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW  0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD  0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW  0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD  0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S  0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S  0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S  0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S  0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D  0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D  0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D  0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D  0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP  0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP  0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR  0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR  0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK  0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD  0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD  0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW  0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP  0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP  0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN  0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD  0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW  0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW  0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD  0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW  0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW  0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI  0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL  0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI  0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI  0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI  0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI  0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI  0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB  0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR  0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR  0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND  0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW  0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW  0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J  0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ  0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ  0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI  0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP  0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP  0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP  0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV  0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD  0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP  0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP  0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP  0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0  0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1  0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2  0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD  0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1  0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1  0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1  0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2  0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD  0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1  0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2  0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1  0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2  0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD  0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1  0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3  0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1  0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2  0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD  0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1  0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+
+#define CSR_MTVT               0x307
+#define CSR_MNXTI              0x345
+
+#define CSR_MNVEC              0x7C3
+
+#define CSR_MIRQ_ENTRY           0x7EC
+#define CSR_MINTSEL_JAL          0x7ED
+#define CSR_PUSHMCAUSE           0x7EE
+#define CSR_PUSHMEPC             0x7EF
+#define CSR_PUSHMXSTATUS         0x7EB
+#define CSR_WFE            0x810
+#define CSR_SLEEPVALUE     0x811
+#define CSR_TXEVT          0x812
+
+#define CSR_MMISC_CTL      0x7d0
+#define CSR_MXSTATUS       0x7c4
+
+
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/sections.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/sections.h
new file mode 100644
index 0000000000..6e1f0518bc
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/drivers/sections.h
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+#ifndef _SECTIONS_H
+#define _SECTIONS_H
+
+extern unsigned char _rom[];
+extern unsigned char _rom_end[];
+
+extern unsigned char _ram[];
+extern unsigned char _ram_end[];
+
+extern unsigned char _ftext[];
+extern unsigned char _etext[];
+extern unsigned char _fbss[];
+extern unsigned char _ebss[];
+extern unsigned char _end[];
+
+#endif /* _SECTIONS_H */
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds
new file mode 100644
index 0000000000..fc3d331ede
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds
@@ -0,0 +1,175 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{ 
+	/* Run in FLASH */ 
+	flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k
+	ram   (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k 
+
+	/* Run in RAM */ 
+/*	flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k
+	ram   (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K
+*/	
+}
+
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
+
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash 
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash 
+
+  .ialign         :
+  {
+    PROVIDE( _ilm = . );
+  } >flash AT>flash 
+
+  .text           :
+  {
+    *(.rodata .rodata.*)
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash 
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash 
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);/*0x80022c8*/
+  PROVIDE (etext = .);/*0x80022c8*/
+  PROVIDE( _eilm = . );
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash 
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash 
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash 
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash 
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash 
+
+    . = ALIGN(4);
+    PROVIDE( _eilm = . );
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash 
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash 
+  
+  
+  .data          :
+  {
+    *(.rdata) 
+   
+    *(.gnu.linkonce.r.*)
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800); 
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash 
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . ); /*0X200052A0  0X200002A0*/
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram 
+
+  . = ALIGN(8);
+  PROVIDE( _end = . ); /*0X2000,0340*/
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . ); 
+    . = __stack_size;  
+    PROVIDE( _sp = . ); 
+  } >ram AT>ram 
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds
new file mode 100644
index 0000000000..3cfe58ac5f
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds
@@ -0,0 +1,175 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{ 
+	/* Run in FLASH */ 
+	flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k
+	ram   (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k 
+
+	/* Run in RAM */ 
+/*	flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k
+	ram   (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K
+*/	
+}
+
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
+
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash 
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash 
+
+  .ialign         :
+  {
+    PROVIDE( _ilm = . );
+  } >flash AT>flash 
+
+  .text           :
+  {
+    *(.rodata .rodata.*)  
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash 
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash 
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);/*0x80022c8*/
+  PROVIDE (etext = .);/*0x80022c8*/
+  PROVIDE( _eilm = . );
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash 
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash 
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash 
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash 
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash 
+
+    . = ALIGN(4);
+    PROVIDE( _eilm = . );
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash 
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash 
+  
+  
+  .data          :
+  {
+    *(.rdata) 
+   
+    *(.gnu.linkonce.r.*)
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800); 
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash 
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . ); /*0X200052A0  0X200002A0*/
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram 
+
+  . = ALIGN(8);
+  PROVIDE( _end = . ); /*0X2000,0340*/
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . ); 
+    . = __stack_size;  
+    PROVIDE( _sp = . ); 
+  } >ram AT>ram 
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds
new file mode 100644
index 0000000000..a10769dc86
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds
@@ -0,0 +1,175 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{ 
+	/* Run in FLASH */ 
+	flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
+	ram   (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k 
+
+	/* Run in RAM */ 
+/*	flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k
+	ram   (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K
+*/	
+}
+
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash 
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash 
+
+  .ialign         :
+  {
+    PROVIDE( _ilm = . );
+  } >flash AT>flash 
+
+  .text           :
+  {
+    *(.rodata .rodata.*)  
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash 
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash 
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);/*0x80022c8*/
+  PROVIDE (etext = .);/*0x80022c8*/
+  PROVIDE( _eilm = . );
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash 
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash 
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash 
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash 
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash 
+
+    . = ALIGN(4);
+    PROVIDE( _eilm = . );
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash 
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash 
+  
+  
+  .data          :
+  {
+    *(.rdata) 
+   
+    *(.gnu.linkonce.r.*)
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800); 
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash 
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . ); /*0X200052A0  0X200002A0*/
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram 
+
+  . = ALIGN(8);
+  PROVIDE( _end = . ); /*0X2000,0340*/
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . ); 
+    . = __stack_size;  
+    PROVIDE( _sp = . ); 
+  } >ram AT>ram 
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds
new file mode 100644
index 0000000000..b418fdfcb1
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds
@@ -0,0 +1,199 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{ 
+	/* Run in FLASH */ 
+	flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
+	ram   (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K 
+
+	/* Run in RAM */ 
+/*	flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
+	ram   (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
+*/	
+}
+
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash 
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash 
+
+  .ialign         :
+  {
+    PROVIDE( _ilm = . );
+  } >flash AT>flash 
+
+  .text           :
+  {
+    *(.rodata .rodata.*)  
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+   
+    /* section information for finsh shell */
+    . = ALIGN(4);
+    __fsymtab_start = .;
+    KEEP(*(FSymTab))
+    __fsymtab_end = .;
+    . = ALIGN(4);
+    __vsymtab_start = .;
+    KEEP(*(VSymTab))
+    __vsymtab_end = .;
+    . = ALIGN(4);
+    
+    /* section information for initial. */
+    . = ALIGN(4);
+    __rt_init_start = .;
+    KEEP(*(SORT(.rti_fn*)))
+    __rt_init_end = .;
+    . = ALIGN(4);
+
+    /* section information for modules */
+    . = ALIGN(4);
+    __rtmsymtab_start = .;
+    KEEP(*(RTMSymTab))
+    __rtmsymtab_end = .;
+  } >flash AT>flash 
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash 
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);/*0x80022c8*/
+  PROVIDE (etext = .);/*0x80022c8*/
+  PROVIDE( _eilm = . );
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash 
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash 
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash 
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash 
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash 
+
+    . = ALIGN(4);
+    PROVIDE( _eilm = . );
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash 
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash 
+  
+  
+  .data          :
+  {
+    *(.rdata) 
+   
+    *(.gnu.linkonce.r.*)
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800); 
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash 
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . ); /*0X200052A0  0X200002A0*/
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram 
+
+  . = ALIGN(8);
+  PROVIDE( _end = . ); /*0X2000,0340*/
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . ); 
+    . = __stack_size;  
+    PROVIDE( _sp = . ); 
+  } >ram AT>ram 
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds
new file mode 100644
index 0000000000..f273c1930d
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds
@@ -0,0 +1,182 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{ 
+	/* Run in FLASH */ 
+	flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
+	ram   (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K 
+
+	/* Run in RAM */ 
+/*	flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
+	ram   (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
+*/	
+}
+
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash 
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash 
+
+  .ialign         :
+  {
+    PROVIDE( _ilm = . );
+  } >flash AT>flash 
+
+  .PrgData ALIGN(0x08004000,4) : AT(ALIGN(0x08004000,4))
+  {
+		KEEP(*(.PrgData))
+  }
+  
+  .text           :
+  {
+    *(.rodata .rodata.*)  
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+    *(.sdata2 .sdata2. *)
+  } >flash AT>flash 
+
+  
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash 
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);/*0x80022c8*/
+  PROVIDE (etext = .);/*0x80022c8*/
+  PROVIDE( _eilm = . );
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash 
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash 
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash 
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash 
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash 
+
+    . = ALIGN(4);
+    PROVIDE( _eilm = . );
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash 
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash 
+  
+  
+  .data          :
+  {
+    *(.rdata) 
+   
+    *(.gnu.linkonce.r.*)
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800); 
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash 
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . ); /*0X200052A0  0X200002A0*/
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram 
+
+  . = ALIGN(8);
+  PROVIDE( _end = . ); /*0X2000,0340*/
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . ); 
+    . = __stack_size;  
+    PROVIDE( _sp = . ); 
+  } >ram AT>ram 
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/entry.S b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/entry.S
new file mode 100644
index 0000000000..f6b18aa71b
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/entry.S
@@ -0,0 +1,204 @@
+// See LICENSE for license details
+
+#ifndef ENTRY_S
+#define ENTRY_S
+
+#include "riscv_encoding.h"
+#include "riscv_bits.h"
+#include "n22_eclic.h"
+#include "n22_tmr.h"
+
+###############################################
+###############################################
+# Disable Interrupt
+#
+.macro DISABLE_MIE
+  csrc CSR_MSTATUS, MSTATUS_MIE
+.endm
+
+
+###############################################
+###############################################
+#Save caller registers
+.macro SAVE_CONTEXT
+
+  STORE x1,  0*REGBYTES(sp)
+  STORE x5,  1*REGBYTES(sp)
+  STORE x6,  2*REGBYTES(sp)
+  STORE x7,  3*REGBYTES(sp)
+  STORE x10, 4*REGBYTES(sp)
+  STORE x11, 5*REGBYTES(sp)
+  STORE x12, 6*REGBYTES(sp)
+  STORE x13, 7*REGBYTES(sp)
+  STORE x14, 8*REGBYTES(sp)
+  STORE x15, 9*REGBYTES(sp)
+  STORE x16, 10*REGBYTES(sp)
+  STORE x17, 11*REGBYTES(sp)
+  STORE x28, 12*REGBYTES(sp)
+  STORE x29, 13*REGBYTES(sp)
+  STORE x30, 14*REGBYTES(sp)
+  STORE x31, 15*REGBYTES(sp)
+.endm
+
+
+###############################################
+###############################################
+#restore caller registers
+.macro RESTORE_CONTEXT
+  LOAD x1,  0*REGBYTES(sp)
+  LOAD x5,  1*REGBYTES(sp)
+  LOAD x6,  2*REGBYTES(sp)
+  LOAD x7,  3*REGBYTES(sp)
+  LOAD x10, 4*REGBYTES(sp)
+  LOAD x11, 5*REGBYTES(sp)
+  LOAD x12, 6*REGBYTES(sp)
+  LOAD x13, 7*REGBYTES(sp)
+  LOAD x14, 8*REGBYTES(sp)
+  LOAD x15, 9*REGBYTES(sp)
+  LOAD x16, 10*REGBYTES(sp)
+  LOAD x17, 11*REGBYTES(sp)
+  LOAD x28, 12*REGBYTES(sp)
+  LOAD x29, 13*REGBYTES(sp)
+  LOAD x30, 14*REGBYTES(sp)
+  LOAD x31, 15*REGBYTES(sp)
+
+.endm
+
+###############################################
+###############################################
+#restore caller registers
+.macro RESTORE_CONTEXT_EXCPT_X5
+  LOAD x1,  0*REGBYTES(sp)
+  LOAD x6,  2*REGBYTES(sp)
+  LOAD x7,  3*REGBYTES(sp)
+  LOAD x10, 4*REGBYTES(sp)
+  LOAD x11, 5*REGBYTES(sp)
+  LOAD x12, 6*REGBYTES(sp)
+  LOAD x13, 7*REGBYTES(sp)
+  LOAD x14, 8*REGBYTES(sp)
+  LOAD x15, 9*REGBYTES(sp)
+  LOAD x16, 10*REGBYTES(sp)
+  LOAD x17, 11*REGBYTES(sp)
+  LOAD x28, 12*REGBYTES(sp)
+  LOAD x29, 13*REGBYTES(sp)
+  LOAD x30, 14*REGBYTES(sp)
+  LOAD x31, 15*REGBYTES(sp)
+
+.endm
+
+###############################################
+###############################################
+#restore caller registers
+.macro RESTORE_CONTEXT_ONLY_X5
+  LOAD x5,  1*REGBYTES(sp)
+.endm
+
+###############################################
+###############################################
+# Save the mepc and mstatus
+#
+.macro SAVE_MEPC_MSTATUS
+  csrr x5, CSR_MEPC
+  STORE x5,  16*REGBYTES(sp)
+  csrr x5, CSR_MSTATUS
+  STORE x5,  17*REGBYTES(sp)
+  csrr x5, CSR_MXSTATUS
+  STORE x5,  18*REGBYTES(sp)
+.endm
+
+###############################################
+###############################################
+# Restore the mepc and mstatus
+#
+.macro RESTORE_MEPC_MSTATUS
+  LOAD x5,  16*REGBYTES(sp)
+  csrw CSR_MEPC, x5
+  LOAD x5,  17*REGBYTES(sp)
+  csrw CSR_MSTATUS, x5
+  LOAD x5,  18*REGBYTES(sp)
+  csrw CSR_MXSTATUS, x5
+.endm
+
+###############################################
+###############################################
+// trap entry point
+//
+  .section      .text.entry
+  .align 6 // In ECLIC mode, the trap entry must be 64bytes aligned
+  .global trap_entry
+.weak trap_entry
+trap_entry:
+   // Allocate the stack space
+  addi sp, sp, -19*REGBYTES
+
+  // Save the caller saving registers (context)
+  SAVE_CONTEXT
+  // Save the MEPC/MStatus reg
+  SAVE_MEPC_MSTATUS
+
+     // Set the function argument
+  csrr a0, mcause
+  mv a1, sp
+     // Call the function
+  call handle_trap
+
+  // Restore the MEPC/MStatus reg
+  RESTORE_MEPC_MSTATUS
+  // Restore the caller saving registers (context)
+  RESTORE_CONTEXT
+
+  // De-allocate the stack space
+  addi sp, sp, 19*REGBYTES
+  // Return to regular code
+  mret
+###############################################
+###############################################
+// IRQ entry point
+//
+  .section      .text.irq
+  .align 2
+  .global irq_entry
+.weak irq_entry
+irq_entry: // -------------> This label will be set to MTVT2 register
+  // Allocate the stack space
+  addi sp, sp, -19*REGBYTES
+
+  SAVE_CONTEXT// Save 16 regs
+
+  //------This special CSR read operation, which is actually use mcause as operand to directly store it to memory
+  csrrwi  x0, CSR_PUSHMCAUSE, 16
+  //------This special CSR read operation, which is actually use mepc as operand to directly store it to memory
+  csrrwi  x0, CSR_PUSHMEPC, 17
+  //------This special CSR read operation, which is actually use mxstatus as operand to directly store it to memory
+  csrrwi  x0, CSR_PUSHMXSTATUS, 18
+
+service_loop:
+  //------This special CSR read/write operation, which is actually Claim the ECLIC to find its pending highest
+  // ID, if the ID is not 0, then automatically enable the mstatus.MIE, and jump to its vector-entry-label, and
+  // update the link register
+  csrrw ra, CSR_MINTSEL_JAL, ra
+
+  RESTORE_CONTEXT_EXCPT_X5
+
+  #---- Critical section with interrupts disabled -----------------------
+  DISABLE_MIE # Disable interrupts
+
+  LOAD x5,  18*REGBYTES(sp)
+  csrw CSR_MXSTATUS, x5
+  LOAD x5,  17*REGBYTES(sp)
+  csrw CSR_MEPC, x5
+  LOAD x5,  16*REGBYTES(sp)
+  csrw CSR_MCAUSE, x5
+
+
+  RESTORE_CONTEXT_ONLY_X5
+
+  // De-allocate the stack space
+  addi sp, sp, 19*REGBYTES
+  // Return to regular code
+  mret
+
+
+
+
+#endif
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/handlers.c b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/handlers.c
new file mode 100644
index 0000000000..10ff5a7949
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/handlers.c
@@ -0,0 +1,24 @@
+//See LICENSE for license details.
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+#include "riscv_encoding.h"
+#include "n22_func.h"
+__attribute__((weak))  uintptr_t handle_nmi() {
+    write(1, "nmi\n", 5);
+    _exit(1);
+    return 0;
+}
+
+__attribute__((weak))  uintptr_t handle_trap(uintptr_t mcause, uintptr_t sp) {
+    if (mcause == 0xFFF) {
+        handle_nmi();
+    }
+    write(1, "trap\n", 5);
+    printf("In trap handler, the mcause is %d\n", mcause);
+    printf("In trap handler, the mepc is 0x%x\n", read_csr(mepc));
+    printf("In trap handler, the mtval is 0x%x\n", read_csr(mbadaddr));
+    _exit(mcause);
+    return 0;
+}
+
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/init.c b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/init.c
new file mode 100644
index 0000000000..ada05ba2c7
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/init.c
@@ -0,0 +1,28 @@
+//See LICENSE for license details.
+#include <gd32vf103.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+#include "riscv_encoding.h"
+#include "n22_func.h"
+
+void _init() {
+    SystemInit();
+
+    //ECLIC init
+    eclic_init(ECLIC_NUM_INTERRUPTS);
+    eclic_mode_enable();
+    set_csr(mstatus, MSTATUS_MIE);
+
+    //printf("After ECLIC mode enabled, the mtvec value is %x \n\n\r", read_csr(mtvec));
+
+    // // It must be NOTED:
+    //  //    * In the RISC-V arch, if user mode and PMP supported, then by default if PMP is not configured
+    //  //      with valid entries, then user mode cannot access any memory, and cannot execute any instructions.
+    //  //    * So if switch to user-mode and still want to continue, then you must configure PMP first
+    //pmp_open_all_space();
+    //switch_m2u_mode();
+}
+
+void _fini() {
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/start.S b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/start.S
new file mode 100644
index 0000000000..953adf3139
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/start.S
@@ -0,0 +1,247 @@
+// See LICENSE for license details.
+
+// See LICENSE for license details.
+
+#include "riscv_encoding.h"
+
+	.section .init
+
+    .weak  eclic_msip_handler
+    .weak  eclic_mtip_handler
+    .weak  eclic_bwei_handler
+    .weak  eclic_pmovi_handler
+    .weak  WWDGT_IRQHandler
+    .weak  LVD_IRQHandler
+    .weak  TAMPER_IRQHandler
+    .weak  RTC_IRQHandler
+    .weak  FMC_IRQHandler
+    .weak  RCU_IRQHandler
+    .weak  EXTI0_IRQHandler
+    .weak  EXTI1_IRQHandler
+    .weak  EXTI2_IRQHandler
+    .weak  EXTI3_IRQHandler
+    .weak  EXTI4_IRQHandler
+    .weak  DMA0_Channel0_IRQHandler
+    .weak  DMA0_Channel1_IRQHandler
+    .weak  DMA0_Channel2_IRQHandler
+    .weak  DMA0_Channel3_IRQHandler
+    .weak  DMA0_Channel4_IRQHandler
+    .weak  DMA0_Channel5_IRQHandler
+    .weak  DMA0_Channel6_IRQHandler
+    .weak  ADC0_1_IRQHandler
+    .weak  CAN0_TX_IRQHandler
+    .weak  CAN0_RX0_IRQHandler
+    .weak  CAN0_RX1_IRQHandler
+    .weak  CAN0_EWMC_IRQHandler
+    .weak  EXTI5_9_IRQHandler
+    .weak  TIMER0_BRK_IRQHandler
+    .weak  TIMER0_UP_IRQHandler
+    .weak  TIMER0_TRG_CMT_IRQHandler
+    .weak  TIMER0_Channel_IRQHandler
+    .weak  TIMER1_IRQHandler
+    .weak  TIMER2_IRQHandler
+    .weak  TIMER3_IRQHandler
+    .weak  I2C0_EV_IRQHandler
+    .weak  I2C0_ER_IRQHandler
+    .weak  I2C1_EV_IRQHandler
+    .weak  I2C1_ER_IRQHandler
+    .weak  SPI0_IRQHandler
+    .weak  SPI1_IRQHandler
+    .weak  USART0_IRQHandler
+    .weak  USART1_IRQHandler
+    .weak  USART2_IRQHandler
+    .weak  EXTI10_15_IRQHandler
+    .weak  RTC_Alarm_IRQHandler
+    .weak  USBFS_WKUP_IRQHandler
+    .weak  EXMC_IRQHandler
+    .weak  TIMER4_IRQHandler
+    .weak  SPI2_IRQHandler
+    .weak  UART3_IRQHandler
+    .weak  UART4_IRQHandler
+    .weak  TIMER5_IRQHandler
+    .weak  TIMER6_IRQHandler
+    .weak  DMA1_Channel0_IRQHandler
+    .weak  DMA1_Channel1_IRQHandler
+    .weak  DMA1_Channel2_IRQHandler
+    .weak  DMA1_Channel3_IRQHandler
+    .weak  DMA1_Channel4_IRQHandler
+    .weak  CAN1_TX_IRQHandler
+    .weak  CAN1_RX0_IRQHandler
+    .weak  CAN1_RX1_IRQHandler
+    .weak  CAN1_EWMC_IRQHandler
+    .weak  USBFS_IRQHandler
+
+
+vector_base:
+    j _start
+    .align    2
+    .word     0
+    .word     0
+    .word     eclic_msip_handler
+    .word     0
+    .word     0
+    .word  	  0
+    .word  	  eclic_mtip_handler
+    .word  	  0
+    .word  	  0
+    .word  	  0
+    .word  	  0
+    .word  	  0
+    .word  	  0
+    .word  	  0
+    .word 	  0
+    .word  	  0
+    .word  	  eclic_bwei_handler
+    .word  	  eclic_pmovi_handler
+    .word  	  WWDGT_IRQHandler
+	.word     LVD_IRQHandler
+	.word     TAMPER_IRQHandler
+	.word     RTC_IRQHandler
+	.word     FMC_IRQHandler
+	.word     RCU_IRQHandler
+	.word     EXTI0_IRQHandler
+	.word     EXTI1_IRQHandler
+	.word     EXTI2_IRQHandler
+	.word     EXTI3_IRQHandler
+	.word     EXTI4_IRQHandler
+	.word     DMA0_Channel0_IRQHandler
+	.word     DMA0_Channel1_IRQHandler
+	.word     DMA0_Channel2_IRQHandler
+	.word     DMA0_Channel3_IRQHandler
+	.word     DMA0_Channel4_IRQHandler
+	.word     DMA0_Channel5_IRQHandler
+	.word     DMA0_Channel6_IRQHandler
+	.word     ADC0_1_IRQHandler
+	.word     CAN0_TX_IRQHandler
+	.word     CAN0_RX0_IRQHandler
+	.word     CAN0_RX1_IRQHandler
+	.word     CAN0_EWMC_IRQHandler
+	.word     EXTI5_9_IRQHandler
+	.word     TIMER0_BRK_IRQHandler
+	.word     TIMER0_UP_IRQHandler
+	.word     TIMER0_TRG_CMT_IRQHandler
+	.word     TIMER0_Channel_IRQHandler
+	.word     TIMER1_IRQHandler
+	.word     TIMER2_IRQHandler
+	.word     TIMER3_IRQHandler
+	.word     I2C0_EV_IRQHandler
+	.word     I2C0_ER_IRQHandler
+	.word     I2C1_EV_IRQHandler
+	.word     I2C1_ER_IRQHandler
+	.word     SPI0_IRQHandler
+	.word     SPI1_IRQHandler
+	.word     USART0_IRQHandler
+	.word     USART1_IRQHandler
+	.word     USART2_IRQHandler
+	.word     EXTI10_15_IRQHandler
+	.word     RTC_Alarm_IRQHandler
+	.word     USBFS_WKUP_IRQHandler
+    .word     0
+    .word     0
+    .word     0
+    .word     0
+	.word     0
+	.word     EXMC_IRQHandler
+	.word     0
+	.word     TIMER4_IRQHandler
+	.word     SPI2_IRQHandler
+	.word     UART3_IRQHandler
+	.word     UART4_IRQHandler
+	.word     TIMER5_IRQHandler
+	.word     TIMER6_IRQHandler
+	.word     DMA1_Channel0_IRQHandler
+	.word     DMA1_Channel1_IRQHandler
+	.word     DMA1_Channel2_IRQHandler
+	.word     DMA1_Channel3_IRQHandler
+	.word     DMA1_Channel4_IRQHandler
+    .word     0
+    .word     0
+	.word     CAN1_TX_IRQHandler
+	.word     CAN1_RX0_IRQHandler
+	.word     CAN1_RX1_IRQHandler
+	.word     CAN1_EWMC_IRQHandler
+	.word     USBFS_IRQHandler
+
+	.globl _start
+	.type _start,@function
+
+_start:
+
+	/* Jump to logical address first to ensure correct operation of RAM region  */
+    la		a0,	_start
+    li		a1,	1
+	slli	a1,	a1, 29
+    bleu	a1, a0, _start0800
+    srli	a1,	a1, 2
+    bleu	a1, a0, _start0800
+    la		a0,	_start0800
+    add		a0, a0, a1
+	jr      a0
+
+_start0800:
+
+    /* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
+    li t0, 0x200
+    csrs CSR_MMISC_CTL, t0
+
+	/* Intial the mtvt*/
+    la t0, vector_base
+    csrw CSR_MTVT, t0
+
+	/* Intial the mtvt2 and enable it*/
+    la t0, irq_entry
+    csrw CSR_MIRQ_ENTRY, t0
+    csrs CSR_MIRQ_ENTRY, 0x1
+
+    /* Intial the CSR MTVEC for the Trap ane NMI base addr*/
+    la t0, trap_entry
+    csrw CSR_MTVEC, t0
+
+#ifdef __riscv_flen
+	/* Enable FPU */
+	li t0, MSTATUS_FS
+	csrs mstatus, t0
+	csrw fcsr, x0
+#endif
+
+.option push
+.option norelax
+	la gp, __global_pointer$
+.option pop
+	la sp, _sp
+
+	/* Load data section */
+	la a0, _data_lma
+	la a1, _data
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+	/* Clear bss section */
+	la a0, __bss_start
+	la a1, _end
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+	/* Call global constructors */
+	la a0, __libc_fini_array
+	call atexit
+	call __libc_init_array
+
+
+	/* argc = argv = 0 */
+	li a0, 0
+	li a1, 0
+	call entry
+	tail exit
+
+1:
+	j 1b
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/_exit.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/_exit.c
new file mode 100644
index 0000000000..8d49dc21f6
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/_exit.c
@@ -0,0 +1,17 @@
+/* See LICENSE of license details. */
+
+#include <unistd.h>
+
+#include "stub.h"
+
+
+void _exit(int code)
+{
+  const char message[] = "\nProgram has exited with code:";
+
+  write(STDERR_FILENO, message, sizeof(message) - 1);
+//  write_hex(STDERR_FILENO, code);
+//  write(STDERR_FILENO, "\n", 1);
+
+  for (;;);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/close.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/close.c
new file mode 100644
index 0000000000..618cc6de96
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/close.c
@@ -0,0 +1,8 @@
+/* See LICENSE of license details. */
+
+#include <errno.h>
+#include "stub.h"
+
+int _close(int fd) {
+    return _stub(EBADF);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/fstat.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/fstat.c
new file mode 100644
index 0000000000..c30d27cba6
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/fstat.c
@@ -0,0 +1,16 @@
+/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <unistd.h>
+#include <sys/stat.h>
+#include "stub.h"
+
+int _fstat(int fd, struct stat* st)
+{
+  if (isatty(fd)) {
+    st->st_mode = S_IFCHR;
+    return 0;
+  }
+
+  return _stub(EBADF);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/isatty.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/isatty.c
new file mode 100644
index 0000000000..8bb63e1e37
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/isatty.c
@@ -0,0 +1,10 @@
+/* See LICENSE of license details. */
+
+#include <unistd.h>
+
+int _isatty(int fd) {
+    if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
+        return 1;
+
+    return 0;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/lseek.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/lseek.c
new file mode 100644
index 0000000000..c7be7a93c6
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/lseek.c
@@ -0,0 +1,13 @@
+/* See LICENSE of license details. */
+
+#include <errno.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include "stub.h"
+
+off_t _lseek(int fd, off_t ptr, int dir) {
+    if (isatty(fd))
+        return 0;
+
+    return _stub(EBADF);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/read.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/read.c
new file mode 100644
index 0000000000..54e15f6a30
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/read.c
@@ -0,0 +1,31 @@
+/* See LICENSE of license details. */
+
+#include <stdint.h>
+#include <errno.h>
+#include <unistd.h>
+#include <sys/types.h>
+
+#include "stub.h"
+
+ssize_t _read(int fd, void* ptr, size_t len)
+{
+    // The below code was copied from freedom-e-sdk, but seems it is definitely wrong, so just comment it out
+    //   Need to implement this function in the future, otherwise cannot use the C scanf function
+  //uint8_t * current = (uint8_t *)ptr;
+  //volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
+  //volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
+
+  //ssize_t result = 0;
+
+  //if (isatty(fd)) {
+  //  for (current = (uint8_t *)ptr;
+  //      (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
+  //      current ++) {
+  //    *current = *uart_rx;
+  //    result++;
+  //  }
+  //  return result;
+  //}
+
+  return _stub(EBADF);
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/sbrk.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/sbrk.c
new file mode 100644
index 0000000000..e86debdec6
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/sbrk.c
@@ -0,0 +1,19 @@
+/* See LICENSE of license details. */
+
+#include <stddef.h>
+
+void *_sbrk(ptrdiff_t incr) {
+    extern char _end[];
+
+    static char *curbrk = _end;
+#ifndef __ANDES__
+    extern char _heap_end[];
+    if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+#else
+	if ((curbrk + incr < _end) )
+#endif
+        return NULL - 1;
+
+    curbrk += incr;
+    return curbrk - incr;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/stub.h b/bsp/gd32vf103v-eval/libraries/n22/stubs/stub.h
new file mode 100644
index 0000000000..e075daeb8c
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/stub.h
@@ -0,0 +1,15 @@
+/* See LICENSE of license details. */
+#ifndef _NUCLEI_SYS_STUB_H
+#define _NUCLEI_SYS_STUB_H
+
+#include <stdint.h>
+#include <unistd.h>
+
+void write_hex(int fd, unsigned long int hex);
+
+static inline int _stub(int err)
+{
+  return -1;
+}
+
+#endif /* _NUCLEI_SYS_STUB_H */
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/write.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/write.c
new file mode 100644
index 0000000000..699ba193f9
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/write.c
@@ -0,0 +1,45 @@
+/* See LICENSE of license details. */
+
+#include <stdint.h>
+#include <string.h>
+#include <errno.h>
+#include <gd32vf103.h>
+#include <unistd.h>
+#include <sys/types.h>
+
+#include "stub.h"
+#include "gd32vf103.h"
+
+typedef unsigned int size_t;
+
+extern int _put_char(int ch) __attribute__((weak));
+
+ssize_t _write(int fd, const void* ptr, size_t len) {
+    const uint8_t * current = (const uint8_t *) ptr;
+
+//	if (isatty(fd)) 
+    {
+        for (size_t jj = 0; jj < len; jj++) {
+            _put_char(current[jj]);
+
+            if (current[jj] == '\n') {
+                _put_char('\r');
+            }
+        }
+        return len;
+    }
+
+    return _stub(EBADF);
+}
+
+int puts(const char* string) {
+    return _write(0, (const void *) string, strlen(string));
+}
+
+int _put_char(int ch) {
+    usart_data_transmit(USART0, (uint8_t) ch);
+    while (usart_flag_get(USART0, USART_FLAG_TBE) == RESET) {
+    }
+
+    return ch;
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/write_hex.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/write_hex.c
new file mode 100644
index 0000000000..2f499b5ee5
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/stubs/write_hex.c
@@ -0,0 +1,17 @@
+/* See LICENSE of license details. */
+
+#include <stdint.h>
+#include <unistd.h>
+
+void write_hex(int fd, unsigned long int hex) {
+    uint8_t ii;
+    uint8_t jj;
+    char towrite;
+    write(fd, "0x", 2);
+    for (ii = sizeof(unsigned long int) * 2; ii > 0; ii--) {
+        jj = ii - 1;
+        uint8_t digit = ((hex & (0xF << (jj * 4))) >> (jj * 4));
+        towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA));
+        write(fd, &towrite, 1);
+    }
+}
diff --git a/bsp/gd32vf103v-eval/libraries/n22/tools/openocd_upload.sh b/bsp/gd32vf103v-eval/libraries/n22/tools/openocd_upload.sh
new file mode 100644
index 0000000000..3e987a7bf9
--- /dev/null
+++ b/bsp/gd32vf103v-eval/libraries/n22/tools/openocd_upload.sh
@@ -0,0 +1,5 @@
+#! /bin/bash -x
+
+work/build/openocd/prefix/bin/openocd -f ${2} \
+	-c "flash protect 0 0 last off; program ${1} verify; resume 0x20000000; exit" \
+	2>&1 | tee openocd_upload.log
diff --git a/bsp/gd32vf103v-eval/rtconfig.h b/bsp/gd32vf103v-eval/rtconfig.h
new file mode 100644
index 0000000000..178ccbfc1f
--- /dev/null
+++ b/bsp/gd32vf103v-eval/rtconfig.h
@@ -0,0 +1,171 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDEL_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x40002
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_RB_BUFSZ 64
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_AT24CXX
+#define PKG_USING_AT24CXX_LATEST_VERSION
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Privated Packages of RealThread */
+
+
+/* Network Utilities */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_STM32F429IG
+
+/* Onboard Peripheral Drivers */
+
+#define BSP_USING_USART
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART0
+
+/* Board extended module Drivers */
+
+
+#endif
diff --git a/bsp/gd32vf103v-eval/rtconfig.py b/bsp/gd32vf103v-eval/rtconfig.py
new file mode 100644
index 0000000000..2d767412bb
--- /dev/null
+++ b/bsp/gd32vf103v-eval/rtconfig.py
@@ -0,0 +1,63 @@
+import os
+ARCH     = 'risc-v'
+CPU      = 'bumblebee'
+# toolchains options
+CROSS_TOOL  = 'gcc'
+
+#------- toolchains path -------------------------------------------------------
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/unknown-gcc/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+CORE = 'risc-v'
+MAP_FILE = 'rtthread.map'
+LINK_FILE = './libraries/n22/env_Eclipse/GD32VF103xB.lds'
+TARGET_NAME = 'rtthread.bin'
+
+#------- GCC settings ----------------------------------------------------------
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'riscv-none-embed-'
+    CC = PREFIX + 'gcc'
+    CXX= PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L.  -nostartfiles  -lc '
+    CFLAGS = DEVICE
+    CFLAGS += ' -save-temps=obj'
+    AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
+    AFLAGS += ' -Iplatform -Ilibraries/n22/include -Ilibraries/n22/env_Eclipse'
+    LFLAGS = DEVICE
+    LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
+    LFLAGS += ' -T ' + LINK_FILE
+    LFLAGS += ' -Wl,-wrap=memset'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
+    POST_ACTION += SIZE + ' $TARGET\n'
diff --git a/libcpu/risc-v/bumblebee/SConscript b/libcpu/risc-v/bumblebee/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/risc-v/bumblebee/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/bumblebee/interrupt_gcc.S b/libcpu/risc-v/bumblebee/interrupt_gcc.S
new file mode 100644
index 0000000000..5a86e7d748
--- /dev/null
+++ b/libcpu/risc-v/bumblebee/interrupt_gcc.S
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+ 
+#include "cpuport.h"
+
+ .section      .text.entry
+  .align 6     /* In ECLIC mode, the trap entry must be 64bytes aligned */
+  .global irq_entry
+irq_entry:
+
+    /* save all from thread context */
+    addi sp, sp, -32 * REGBYTES
+
+    STORE x1,   1 * REGBYTES(sp)
+    li    t0,   0x80
+    STORE t0,   2 * REGBYTES(sp)
+
+    STORE x4,   4 * REGBYTES(sp)
+    STORE x5,   5 * REGBYTES(sp)
+    STORE x6,   6 * REGBYTES(sp)
+    STORE x7,   7 * REGBYTES(sp)
+    STORE x8,   8 * REGBYTES(sp)
+    STORE x9,   9 * REGBYTES(sp)
+    STORE x10, 10 * REGBYTES(sp)
+    STORE x11, 11 * REGBYTES(sp)
+    STORE x12, 12 * REGBYTES(sp)
+    STORE x13, 13 * REGBYTES(sp)
+    STORE x14, 14 * REGBYTES(sp)
+    STORE x15, 15 * REGBYTES(sp)
+    STORE x16, 16 * REGBYTES(sp)
+    STORE x17, 17 * REGBYTES(sp)
+    STORE x18, 18 * REGBYTES(sp)
+    STORE x19, 19 * REGBYTES(sp)
+    STORE x20, 20 * REGBYTES(sp)
+    STORE x21, 21 * REGBYTES(sp)
+    STORE x22, 22 * REGBYTES(sp)
+    STORE x23, 23 * REGBYTES(sp)
+    STORE x24, 24 * REGBYTES(sp)
+    STORE x25, 25 * REGBYTES(sp)
+    STORE x26, 26 * REGBYTES(sp)
+    STORE x27, 27 * REGBYTES(sp)
+    STORE x28, 28 * REGBYTES(sp)
+    STORE x29, 29 * REGBYTES(sp)
+    STORE x30, 30 * REGBYTES(sp)
+    STORE x31, 31 * REGBYTES(sp)
+
+    move  s0, sp
+
+    /* switch to interrupt stack */
+    la    sp, _sp
+
+    /* interrupt handle */
+    call  rt_interrupt_enter
+    csrr  a0, mcause
+    csrr  a1, mepc
+    mv    a2, sp
+    csrrw ra, 0x07ED, ra
+    call  rt_interrupt_leave
+
+    /* switch to from thread stack */
+    move  sp, s0
+
+    /* need to switch new thread */
+    la    s0, rt_thread_switch_interrupt_flag
+    lw    s2, 0(s0)
+    beqz  s2, spurious_interrupt
+    /* clear switch interrupt flag */
+    sw    zero, 0(s0)
+
+    csrr  a0, mepc
+    STORE a0, 0 * REGBYTES(sp)
+
+    la    s0, rt_interrupt_from_thread
+    LOAD  s1, 0(s0)
+    STORE sp, 0(s1)
+
+    la    s0, rt_interrupt_to_thread
+    LOAD  s1, 0(s0)
+    LOAD  sp, 0(s1)
+
+    LOAD  a0,  0 * REGBYTES(sp)
+    csrw  mepc, a0
+
+spurious_interrupt:
+    LOAD  x1,   1 * REGBYTES(sp)
+
+    /* Remain in M-mode after mret */
+    li    t0, 0x00001800
+    csrs  mstatus, t0
+    LOAD  t0,   2 * REGBYTES(sp)
+    csrs  mstatus, t0
+
+    LOAD  x4,   4 * REGBYTES(sp)
+    LOAD  x5,   5 * REGBYTES(sp)
+    LOAD  x6,   6 * REGBYTES(sp)
+    LOAD  x7,   7 * REGBYTES(sp)
+    LOAD  x8,   8 * REGBYTES(sp)
+    LOAD  x9,   9 * REGBYTES(sp)
+    LOAD  x10, 10 * REGBYTES(sp)
+    LOAD  x11, 11 * REGBYTES(sp)
+    LOAD  x12, 12 * REGBYTES(sp)
+    LOAD  x13, 13 * REGBYTES(sp)
+    LOAD  x14, 14 * REGBYTES(sp)
+    LOAD  x15, 15 * REGBYTES(sp)
+    LOAD  x16, 16 * REGBYTES(sp)
+    LOAD  x17, 17 * REGBYTES(sp)
+    LOAD  x18, 18 * REGBYTES(sp)
+    LOAD  x19, 19 * REGBYTES(sp)
+    LOAD  x20, 20 * REGBYTES(sp)
+    LOAD  x21, 21 * REGBYTES(sp)
+    LOAD  x22, 22 * REGBYTES(sp)
+    LOAD  x23, 23 * REGBYTES(sp)
+    LOAD  x24, 24 * REGBYTES(sp)
+    LOAD  x25, 25 * REGBYTES(sp)
+    LOAD  x26, 26 * REGBYTES(sp)
+    LOAD  x27, 27 * REGBYTES(sp)
+    LOAD  x28, 28 * REGBYTES(sp)
+    LOAD  x29, 29 * REGBYTES(sp)
+    LOAD  x30, 30 * REGBYTES(sp)
+    LOAD  x31, 31 * REGBYTES(sp)
+
+    addi  sp, sp, 32 * REGBYTES
+    mret
-- 
cgit v1.3.1


From ab818cda3025c439914f8e78cea09887ea228ecf Mon Sep 17 00:00:00 2001
From: liufeilong <443199460@qq.com>
Date: Wed, 21 Aug 2019 13:44:55 +0800
Subject: 参照龙芯1c手册更正看门狗寄存器宏定义
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/mips/loongson_1c/ls1c.h | 150 ++++++++++++++++++++---------------------
 1 file changed, 75 insertions(+), 75 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/loongson_1c/ls1c.h b/libcpu/mips/loongson_1c/ls1c.h
index a203810c37..963f774cf7 100644
--- a/libcpu/mips/loongson_1c/ls1c.h
+++ b/libcpu/mips/loongson_1c/ls1c.h
@@ -18,36 +18,36 @@
 
 #include "../common/mipsregs.h"
 
-#define LS1C_ACPI_IRQ	0
-#define LS1C_HPET_IRQ	1
-//#define LS1C_UART0_IRQ	3  // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ��
-#define LS1C_UART1_IRQ	4
-#define LS1C_UART2_IRQ	5
-#define LS1C_CAN0_IRQ	6
-#define LS1C_CAN1_IRQ	7
-#define LS1C_SPI0_IRQ	8
-#define LS1C_SPI1_IRQ	9
-#define LS1C_AC97_IRQ	10
-#define LS1C_MS_IRQ		11
-#define LS1C_KB_IRQ		12
-#define LS1C_DMA0_IRQ	13
-#define LS1C_DMA1_IRQ	14
-#define LS1C_DMA2_IRQ   15
-#define LS1C_NAND_IRQ	16
-#define LS1C_PWM0_IRQ	17
-#define LS1C_PWM1_IRQ	18
-#define LS1C_PWM2_IRQ	19
-#define LS1C_PWM3_IRQ	20
+#define LS1C_ACPI_IRQ    0
+#define LS1C_HPET_IRQ    1
+//#define LS1C_UART0_IRQ    3  // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ��
+#define LS1C_UART1_IRQ   4
+#define LS1C_UART2_IRQ   5
+#define LS1C_CAN0_IRQ    6
+#define LS1C_CAN1_IRQ    7
+#define LS1C_SPI0_IRQ    8
+#define LS1C_SPI1_IRQ    9
+#define LS1C_AC97_IRQ    10
+#define LS1C_MS_IRQ      11
+#define LS1C_KB_IRQ      12
+#define LS1C_DMA0_IRQ    13
+#define LS1C_DMA1_IRQ    14
+#define LS1C_DMA2_IRQ    15
+#define LS1C_NAND_IRQ    16
+#define LS1C_PWM0_IRQ    17
+#define LS1C_PWM1_IRQ    18
+#define LS1C_PWM2_IRQ    19
+#define LS1C_PWM3_IRQ    20
 #define LS1C_RTC_INT0_IRQ  21
 #define LS1C_RTC_INT1_IRQ  22
 #define LS1C_RTC_INT2_IRQ  23
-#define LS1C_UART3_IRQ  29
-#define LS1C_ADC_IRQ    30
-#define LS1C_SDIO_IRQ   31
+#define LS1C_UART3_IRQ   29
+#define LS1C_ADC_IRQ     30
+#define LS1C_SDIO_IRQ    31
 
 
-#define LS1C_EHCI_IRQ	(32+0)
-#define LS1C_OHCI_IRQ	(32+1)
+#define LS1C_EHCI_IRQ   (32+0)
+#define LS1C_OHCI_IRQ   (32+1)
 #define LS1C_OTG_IRQ    (32+2)
 #define LS1C_MAC_IRQ    (32+3)
 #define LS1C_CAM_IRQ    (32+4)
@@ -64,7 +64,7 @@
 #define LS1C_I2C0_IRQ   (32+19)
 
 
-#define LS1C_GPIO_IRQ 64
+#define LS1C_GPIO_IRQ       64
 #define LS1C_GPIO_FIRST_IRQ 64
 #define LS1C_GPIO_IRQ_COUNT 96
 #define LS1C_GPIO_LAST_IRQ  (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
@@ -84,72 +84,72 @@
 
 struct ls1c_intc_regs
 {
-	volatile unsigned int int_isr;
-	volatile unsigned int int_en;
-	volatile unsigned int int_set;
-	volatile unsigned int int_clr;		/* offset 0x10*/
-	volatile unsigned int int_pol;
-   	volatile unsigned int int_edge;		/* offset 0 */
+    volatile unsigned int int_isr;
+    volatile unsigned int int_en;
+    volatile unsigned int int_set;
+    volatile unsigned int int_clr;        /* offset 0x10*/
+    volatile unsigned int int_pol;
+    volatile unsigned int int_edge;        /* offset 0 */
 }; 
 
 struct ls1c_cop_global_regs
 {
-	volatile unsigned int control;
-	volatile unsigned int rd_inten;
-	volatile unsigned int wr_inten;
-	volatile unsigned int rd_intisr;		/* offset 0x10*/
-	volatile unsigned int wr_intisr;
-	unsigned int unused[11];
+    volatile unsigned int control;
+    volatile unsigned int rd_inten;
+    volatile unsigned int wr_inten;
+    volatile unsigned int rd_intisr;        /* offset 0x10*/
+    volatile unsigned int wr_intisr;
+    unsigned int unused[11];
 } ; 
 
 struct ls1c_cop_channel_regs
 {
-	volatile unsigned int rd_control;
-	volatile unsigned int rd_src;
-	volatile unsigned int rd_cnt;
-	volatile unsigned int rd_status;		/* offset 0x10*/
-	volatile unsigned int wr_control;
-	volatile unsigned int wr_src;
-	volatile unsigned int wr_cnt;
-	volatile unsigned int wr_status;		/* offset 0x10*/
+    volatile unsigned int rd_control;
+    volatile unsigned int rd_src;
+    volatile unsigned int rd_cnt;
+    volatile unsigned int rd_status;        /* offset 0x10*/
+    volatile unsigned int wr_control;
+    volatile unsigned int wr_src;
+    volatile unsigned int wr_cnt;
+    volatile unsigned int wr_status;        /* offset 0x10*/
 } ; 
 
 struct ls1c_cop_regs
 {
-	struct ls1c_cop_global_regs global;
-	struct ls1c_cop_channel_regs chan[8][2];
+    struct ls1c_cop_global_regs global;
+    struct ls1c_cop_channel_regs chan[8][2];
 } ;
 
-#define __REG8(addr)		*((volatile unsigned char *)(addr))
-#define __REG16(addr)		*((volatile unsigned short *)(addr))
-#define __REG32(addr)		*((volatile unsigned int *)(addr))
-
-#define GMAC0_BASE			0xBFE10000
-#define GMAC0_DMA_BASE		0xBFE11000
-#define GMAC1_BASE			0xBFE20000
-#define GMAC1_DMA_BASE		0xBFE21000
-#define I2C0_BASE			0xBFE58000
-#define PWM0_BASE			0xBFE5C000
-#define PWM1_BASE			0xBFE5C010
-#define PWM2_BASE			0xBFE5C020
-#define PWM3_BASE			0xBFE5C030
-#define WDT_BASE			0xBFE5C060
-#define RTC_BASE			0xBFE64000
-#define I2C1_BASE			0xBFE68000
-#define I2C2_BASE			0xBFE70000
-#define AC97_BASE			0xBFE74000
-#define NAND_BASE			0xBFE78000
-#define SPI_BASE			0xBFE80000
-#define CAN1_BASE			0xBF004300
-#define CAN0_BASE			0xBF004400
+#define __REG8(addr)        *((volatile unsigned char *)(addr))
+#define __REG16(addr)       *((volatile unsigned short *)(addr))
+#define __REG32(addr)       *((volatile unsigned int *)(addr))
+
+#define GMAC0_BASE            0xBFE10000
+#define GMAC0_DMA_BASE        0xBFE11000
+#define GMAC1_BASE            0xBFE20000
+#define GMAC1_DMA_BASE        0xBFE21000
+#define I2C0_BASE             0xBFE58000
+#define PWM0_BASE             0xBFE5C000
+#define PWM1_BASE             0xBFE5C010
+#define PWM2_BASE             0xBFE5C020
+#define PWM3_BASE             0xBFE5C030
+#define WDT_BASE              0xBFE5C060
+#define RTC_BASE              0xBFE64000
+#define I2C1_BASE             0xBFE68000
+#define I2C2_BASE             0xBFE70000
+#define AC97_BASE             0xBFE74000
+#define NAND_BASE             0xBFE78000
+#define SPI_BASE              0xBFE80000
+#define CAN1_BASE             0xBF004300
+#define CAN0_BASE             0xBF004400
 
 /* Watch Dog registers */
-#define WDT_EN				__REG32(WDT_BASE + 0x00)
-#define WDT_SET				__REG32(WDT_BASE + 0x04)
-#define WDT_TIMER			__REG32(WDT_BASE + 0x08)
+#define WDT_EN               __REG32(WDT_BASE + 0x00)
+#define WDT_SET              __REG32(WDT_BASE + 0x08)
+#define WDT_TIMER            __REG32(WDT_BASE + 0x04)
 
-#define PLL_FREQ 				__REG32(0xbfe78030)
-#define PLL_DIV_PARAM 			__REG32(0xbfe78034)
+#define PLL_FREQ             __REG32(0xbfe78030)
+#define PLL_DIV_PARAM        __REG32(0xbfe78034)
 
 #endif
 
-- 
cgit v1.3.1


From a101327d24f9deed087e8c1421ca50b9f45e4203 Mon Sep 17 00:00:00 2001
From: xuzhuoyi <xzy476386434@vip.qq.com>
Date: Sat, 24 Aug 2019 18:42:54 +0800
Subject: [bsp][tms320f28379d] Fix an issue that interrupts are disabled in the
 thread

---
 bsp/tms320f28379d/applications/startup.c | 2 --
 bsp/tms320f28379d/drivers/drv_sci.c      | 1 -
 libcpu/ti-dsp/c28x/cpuport.c             | 2 +-
 3 files changed, 1 insertion(+), 4 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/tms320f28379d/applications/startup.c b/bsp/tms320f28379d/applications/startup.c
index 523a45b3b7..301e63a00a 100644
--- a/bsp/tms320f28379d/applications/startup.c
+++ b/bsp/tms320f28379d/applications/startup.c
@@ -47,8 +47,6 @@ void rtthread_startup(void)
     /* init board */
     rt_hw_board_init();
 
-    rt_hw_interrupt_disable();
-
     /* show version */
     rt_show_version();
 
diff --git a/bsp/tms320f28379d/drivers/drv_sci.c b/bsp/tms320f28379d/drivers/drv_sci.c
index 0920d382f5..b9f23acc48 100644
--- a/bsp/tms320f28379d/drivers/drv_sci.c
+++ b/bsp/tms320f28379d/drivers/drv_sci.c
@@ -223,7 +223,6 @@ int rt_hw_sci_init(void)
     PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
     PieCtrlRegs.PIEIER9.bit.INTx1 = 1;   // PIE Group 9, INT1
     IER |= 0x100;                        // Enable CPU INT
-    EINT;
 
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
     rt_err_t result = 0;
diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c
index e34556c524..3f88606c65 100644
--- a/libcpu/ti-dsp/c28x/cpuport.c
+++ b/libcpu/ti-dsp/c28x/cpuport.c
@@ -78,7 +78,7 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
     stack_frame->exception_stack_frame.acc     = 0x33332222;
     stack_frame->exception_stack_frame.ar1_ar0 = 0x00001111 & (unsigned long)parameter; /* ar0 : argument */
     stack_frame->exception_stack_frame.p       = 0x55554444;                            /* p */
-    stack_frame->exception_stack_frame.dp_st1  = (0x00000000) | rt_hw_get_st1();        /* dp_st1 */
+    stack_frame->exception_stack_frame.dp_st1  = (0x00000000) | rt_hw_get_st1() & 0xFFFFFFFE;        /* dp_st1 */
     stack_frame->exception_stack_frame.dbgstat_ier    = 0;                              /* dbgstat_ier */
     stack_frame->exception_stack_frame.return_address = (unsigned long)tentry;          /* return_address */
     stack_frame->rpc = (unsigned long)texit;
-- 
cgit v1.3.1


From 94551979e069f681d53e530c62403e5b2c96b72c Mon Sep 17 00:00:00 2001
From: xiaofan <xfan1024@live.com>
Date: Sat, 7 Sep 2019 21:19:10 +0800
Subject: Fix Cortex-M0 Cannot Execute Reboot

Signed-off-by: xiaofan <xfan1024@live.com>
---
 libcpu/arm/cortex-m0/cpuport.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m0/cpuport.c b/libcpu/arm/cortex-m0/cpuport.c
index 5d36fa11fe..19aec42230 100644
--- a/libcpu/arm/cortex-m0/cpuport.c
+++ b/libcpu/arm/cortex-m0/cpuport.c
@@ -119,7 +119,7 @@ void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
 #define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
 #define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
 #define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
-#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED00)  /* Reset control Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED0C)  /* Reset control Address Register */
 #define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
 
 #define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
-- 
cgit v1.3.1


From 8316646b8580362bf00715a91686721e7981fd59 Mon Sep 17 00:00:00 2001
From: tangyuxin <462747508@qq.com>
Date: Thu, 19 Sep 2019 18:27:07 +0800
Subject: [libcpu][arm] 修复因提前返回,导致sp指针不对称问题
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/arm/cortex-m3/cpuport.c | 1 -
 libcpu/arm/cortex-m4/cpuport.c | 1 -
 libcpu/arm/cortex-m7/cpuport.c | 1 -
 3 files changed, 3 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c
index 0a948c528b..d17d4fdf2e 100644
--- a/libcpu/arm/cortex-m3/cpuport.c
+++ b/libcpu/arm/cortex-m3/cpuport.c
@@ -395,7 +395,6 @@ int __rt_ffs(int value)
         "ADDS    r0, r0, #0x01        \n"
 
         "exit:                        \n"
-        "BX      lr                   \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c
index 71a7fb16f9..f556ba0c26 100644
--- a/libcpu/arm/cortex-m4/cpuport.c
+++ b/libcpu/arm/cortex-m4/cpuport.c
@@ -479,7 +479,6 @@ int __rt_ffs(int value)
         "ADDS    r0, r0, #0x01        \n"
 
         "exit:                        \n"
-        "BX      lr                   \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c
index 85960baede..c22242f140 100644
--- a/libcpu/arm/cortex-m7/cpuport.c
+++ b/libcpu/arm/cortex-m7/cpuport.c
@@ -479,7 +479,6 @@ int __rt_ffs(int value)
         "ADDS    r0, r0, #0x01        \n"
 
         "exit:                        \n"
-        "BX      lr                   \n"
 
         : "=r"(value)
         : "r"(value)
-- 
cgit v1.3.1


From cb07e5fb24afebdf233847da551d3ede80727345 Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Thu, 26 Sep 2019 18:13:07 +0800
Subject: 开放spinlock相关函数
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 include/rtdef.h                  |   1 +
 include/rthw.h                   |  14 +++++
 libcpu/arm/cortex-a/cpu.c        |   6 +++
 libcpu/risc-v/k210/cpuport_smp.c |   5 ++
 src/cpu.c                        | 113 +++++++++++++++++++++++++++++++++++++++
 src/scheduler.c                  |  11 ++--
 src/thread.c                     |   1 +
 7 files changed, 148 insertions(+), 3 deletions(-)

(limited to 'libcpu')

diff --git a/include/rtdef.h b/include/rtdef.h
index b25a6a87d5..3dc8a2a2a9 100644
--- a/include/rtdef.h
+++ b/include/rtdef.h
@@ -577,6 +577,7 @@ struct rt_thread
 
     rt_uint16_t scheduler_lock_nest;                    /**< scheduler lock count */
     rt_uint16_t cpus_lock_nest;                         /**< cpus lock count */
+    rt_uint16_t critical_lock_nest;                     /**< critical lock count */
 #endif /*RT_USING_SMP*/
 
     /* priority */
diff --git a/include/rthw.h b/include/rthw.h
index ef3dc087ad..a77f2c1e46 100644
--- a/include/rthw.h
+++ b/include/rthw.h
@@ -143,6 +143,12 @@ typedef union {
     } tickets;
 } rt_hw_spinlock_t;
 
+typedef struct
+{
+    rt_hw_spinlock_t lock;
+} rt_spinlock_t;
+
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock);
 void rt_hw_spin_lock(rt_hw_spinlock_t *lock);
 void rt_hw_spin_unlock(rt_hw_spinlock_t *lock);
 
@@ -181,8 +187,16 @@ void rt_hw_secondary_cpu_idle_exec(void);
 #define rt_hw_spin_lock(lock)     *(lock) = rt_hw_interrupt_disable()
 #define rt_hw_spin_unlock(lock)   rt_hw_interrupt_enable(*(lock))
 
+typedef int rt_spinlock_t;
+
 #endif
 
+void rt_spin_lock_init(rt_spinlock_t *lock);
+void rt_spin_lock(rt_spinlock_t *lock);
+void rt_spin_unlock(rt_spinlock_t *lock);
+rt_base_t rt_spin_lock_irqsave(rt_spinlock_t *lock);
+void rt_spin_unlock_irqrestore(rt_spinlock_t *lock, rt_base_t level);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c
index 6b129f89ee..7c6bf58a4b 100644
--- a/libcpu/arm/cortex-a/cpu.c
+++ b/libcpu/arm/cortex-a/cpu.c
@@ -14,6 +14,7 @@
 #include <board.h>
 
 #ifdef RT_USING_SMP
+
 int rt_hw_cpu_id(void)
 {
     int cpu_id;
@@ -25,6 +26,11 @@ int rt_hw_cpu_id(void)
     return cpu_id;
 };
 
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    lock->slock = 0;
+}
+
 void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
 {
     unsigned long tmp;
diff --git a/libcpu/risc-v/k210/cpuport_smp.c b/libcpu/risc-v/k210/cpuport_smp.c
index a31314a13f..8c57dfeafc 100644
--- a/libcpu/risc-v/k210/cpuport_smp.c
+++ b/libcpu/risc-v/k210/cpuport_smp.c
@@ -25,6 +25,11 @@ int rt_hw_cpu_id(void)
     return read_csr(mhartid);
 }
 
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    ((spinlock_t *)lock)->lock = 0;
+}
+
 void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
 {
     spinlock_lock((spinlock_t *)lock);
diff --git a/src/cpu.c b/src/cpu.c
index fe3ba21bb0..a4075108e1 100644
--- a/src/cpu.c
+++ b/src/cpu.c
@@ -11,6 +11,119 @@
 #include <rtthread.h>
 #include <rthw.h>
 
+#ifdef RT_USING_SMP
+/***********************************
+ * disable scheduler
+ ***********************************/
+static void rt_preempt_disable(void)
+{
+	register rt_base_t level;
+	struct rt_thread *current_thread;
+
+	/* disable interrupt */
+	level = rt_hw_local_irq_disable();
+
+	current_thread = rt_cpu_self()->current_thread;
+	if (!current_thread)
+	{
+		rt_hw_local_irq_enable(level);
+		return;
+	}
+
+	/* lock scheduler for local cpu */
+	current_thread->scheduler_lock_nest ++;
+
+	/* enable interrupt */
+	rt_hw_local_irq_enable(level);
+}
+
+/***********************************
+ * restore scheduler
+ ***********************************/
+static void rt_preempt_enable(void)
+{
+	register rt_base_t level;
+	struct rt_thread *current_thread;
+
+	/* disable interrupt */
+	level = rt_hw_local_irq_disable();
+
+	current_thread = rt_cpu_self()->current_thread;
+	if (!current_thread)
+	{
+		rt_hw_local_irq_enable(level);
+		return;
+	}
+
+	/* unlock scheduler for local cpu */
+	current_thread->scheduler_lock_nest --;
+
+	rt_schedule();
+	/* enable interrupt */
+	rt_hw_local_irq_enable(level);
+}
+#endif
+
+void rt_spin_lock_init(rt_spinlock_t *lock)
+{
+#ifdef RT_USING_SMP
+	rt_hw_spin_lock_init(&lock->lock);
+#endif
+}
+RTM_EXPORT(rt_spin_lock_init)
+
+void rt_spin_lock(rt_spinlock_t *lock)
+{
+#ifdef RT_USING_SMP
+	rt_preempt_disable();
+	rt_hw_spin_lock(&lock->lock);
+#else
+    rt_enter_critical();
+#endif
+}
+RTM_EXPORT(rt_spin_lock)
+
+void rt_spin_unlock(rt_spinlock_t *lock)
+{
+#ifdef RT_USING_SMP
+	rt_hw_spin_unlock(&lock->lock);
+	rt_preempt_enable();
+#else
+    rt_exit_critical();
+#endif
+}
+RTM_EXPORT(rt_spin_unlock)
+
+rt_base_t rt_spin_lock_irqsave(rt_spinlock_t *lock)
+{
+	unsigned long level;
+
+#ifdef RT_USING_SMP
+	rt_preempt_disable();
+
+	level = rt_hw_local_irq_disable();
+	rt_hw_spin_lock(&lock->lock);
+
+	return level;
+#else
+    return rt_hw_interrupt_disable();
+#endif
+}
+RTM_EXPORT(rt_spin_lock_irqsave)
+
+void rt_spin_unlock_irqrestore(rt_spinlock_t *lock, rt_base_t level)
+{
+#ifdef RT_USING_SMP
+	rt_hw_spin_unlock(&lock->lock);
+	rt_hw_local_irq_enable(level);
+
+	rt_preempt_enable();
+#else
+    rt_hw_interrupt_enable(level);
+#endif
+}
+RTM_EXPORT(rt_spin_unlock_irqrestore)
+
 #ifdef RT_USING_SMP
 
 static struct rt_cpu rt_cpus[RT_CPUS_NR];
diff --git a/src/scheduler.c b/src/scheduler.c
index b487bd4b60..0faafaa2fc 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -840,11 +840,14 @@ void rt_enter_critical(void)
      */
 
     /* lock scheduler for all cpus */
-    if (current_thread->scheduler_lock_nest == !!current_thread->cpus_lock_nest)
+    if (current_thread->critical_lock_nest == 0)
     {
         rt_hw_spin_lock(&_rt_critical_lock);
     }
 
+    /* critical for local cpu */
+    current_thread->critical_lock_nest ++;
+
     /* lock scheduler for local cpu */
     current_thread->scheduler_lock_nest ++;
 
@@ -892,7 +895,9 @@ void rt_exit_critical(void)
 
     current_thread->scheduler_lock_nest --;
 
-    if (current_thread->scheduler_lock_nest == !!current_thread->cpus_lock_nest)
+    current_thread->critical_lock_nest --;
+
+    if (current_thread->critical_lock_nest == 0)
     {
         rt_hw_spin_unlock(&_rt_critical_lock);
     }
@@ -951,7 +956,7 @@ rt_uint16_t rt_critical_level(void)
 #ifdef RT_USING_SMP
     struct rt_thread *current_thread = rt_cpu_self()->current_thread;
 
-    return current_thread->scheduler_lock_nest;
+    return current_thread->critical_lock_nest;
 #else
 	return rt_scheduler_lock_nest;
 #endif /*RT_USING_SMP*/
diff --git a/src/thread.c b/src/thread.c
index ab203b1d49..a88729e52c 100644
--- a/src/thread.c
+++ b/src/thread.c
@@ -172,6 +172,7 @@ static rt_err_t _rt_thread_init(struct rt_thread *thread,
     /* lock init */
     thread->scheduler_lock_nest = 0;
     thread->cpus_lock_nest = 0;
+    thread->critical_lock_nest = 0;
 #endif /*RT_USING_SMP*/
 
     /* initialize cleanup function and user data */
-- 
cgit v1.3.1


From 525d353403c0c665328ea52416922c82ae2eaac5 Mon Sep 17 00:00:00 2001
From: aozima <wuyangyong@gmail.com>
Date: Tue, 22 Oct 2019 09:47:41 +0800
Subject: fixed linker script and stack align issues.

---
 bsp/allwinner_tina/link.lds              | 4 ++--
 bsp/beaglebone/beaglebone_ram.lds        | 4 ++--
 bsp/imx6sx/cortex-a9/cpu/start_gcc.S     | 1 +
 bsp/imx6sx/cortex-a9/imx6.lds            | 4 ++--
 bsp/imx6ul/imx6.lds                      | 6 +++---
 bsp/lpc2478/lpc2478_ram.lds              | 6 +++---
 bsp/qemu-vexpress-a9/link.lds            | 6 +++---
 bsp/qemu-vexpress-gemini/cpu/start_gcc.S | 1 +
 bsp/qemu-vexpress-gemini/vexpress.lds    | 6 +++---
 bsp/raspi2/cpu/start_gcc.S               | 1 +
 bsp/realview-a8/realview.lds             | 6 +++---
 libcpu/arm/am335x/start_gcc.S            | 1 +
 libcpu/arm/cortex-a/start_gcc.S          | 1 +
 libcpu/arm/cortex-r4/start_gcc.S         | 1 +
 libcpu/arm/realview-a8-vmm/start_gcc.S   | 1 +
 libcpu/arm/zynq7000/start_gcc.S          | 1 +
 16 files changed, 29 insertions(+), 21 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/allwinner_tina/link.lds b/bsp/allwinner_tina/link.lds
index eb974dea0f..8fb0e9e84d 100644
--- a/bsp/allwinner_tina/link.lds
+++ b/bsp/allwinner_tina/link.lds
@@ -82,8 +82,8 @@ SECTIONS
         PROVIDE(__dtors_end__ = .);
     }
 
+    . = ALIGN(8);
     __data_start = .;
-    . = ALIGN(4);
     .data :
     {
         *(.data)
@@ -118,7 +118,7 @@ SECTIONS
     }
     __data_end = .;
 
-    . = ALIGN(4);
+    . = ALIGN(8);
     __bss_start = .;
     .bss       :
     {
diff --git a/bsp/beaglebone/beaglebone_ram.lds b/bsp/beaglebone/beaglebone_ram.lds
index cf9bf6944d..5847cb08dd 100644
--- a/bsp/beaglebone/beaglebone_ram.lds
+++ b/bsp/beaglebone/beaglebone_ram.lds
@@ -57,8 +57,8 @@ SECTIONS
         PROVIDE(__dtors_end__ = .);
     }
 
+    . = ALIGN(8);
     __data_start = .;
-    . = ALIGN(4);
     .data :
     {
         *(.data)
@@ -66,7 +66,7 @@ SECTIONS
     }
     __data_end = .;
 
-    . = ALIGN(4);
+    . = ALIGN(8);
     __bss_start = .;
     .bss       :
     {
diff --git a/bsp/imx6sx/cortex-a9/cpu/start_gcc.S b/bsp/imx6sx/cortex-a9/cpu/start_gcc.S
index 2f16d16807..3ff5a755d5 100644
--- a/bsp/imx6sx/cortex-a9/cpu/start_gcc.S
+++ b/bsp/imx6sx/cortex-a9/cpu/start_gcc.S
@@ -34,6 +34,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept ISR_Stack_Size
 .byte 0
diff --git a/bsp/imx6sx/cortex-a9/imx6.lds b/bsp/imx6sx/cortex-a9/imx6.lds
index e05132025b..a889774f85 100644
--- a/bsp/imx6sx/cortex-a9/imx6.lds
+++ b/bsp/imx6sx/cortex-a9/imx6.lds
@@ -65,8 +65,8 @@ SECTIONS
         . += 16K;
     }
 
+    . = ALIGN(8);
     __data_start = .;
-    . = ALIGN(4);
     .data :
     {
         *(.data)
@@ -74,7 +74,7 @@ SECTIONS
     }
     __data_end = .;
 
-    . = ALIGN(4);
+    . = ALIGN(8);
     __bss_start = .;
     .bss       :
     {
diff --git a/bsp/imx6ul/imx6.lds b/bsp/imx6ul/imx6.lds
index d8d7480006..a889774f85 100644
--- a/bsp/imx6ul/imx6.lds
+++ b/bsp/imx6ul/imx6.lds
@@ -65,8 +65,8 @@ SECTIONS
         . += 16K;
     }
 
+    . = ALIGN(8);
     __data_start = .;
-    . = ALIGN(4);
     .data :
     {
         *(.data)
@@ -74,8 +74,8 @@ SECTIONS
     }
     __data_end = .;
 
-    . = ALIGN(4);
-    __bss_start = __data_end;
+    . = ALIGN(8);
+    __bss_start = .;
     .bss       :
     {
     *(.bss)
diff --git a/bsp/lpc2478/lpc2478_ram.lds b/bsp/lpc2478/lpc2478_ram.lds
index ffdada7a2a..28e8cdd7f5 100644
--- a/bsp/lpc2478/lpc2478_ram.lds
+++ b/bsp/lpc2478/lpc2478_ram.lds
@@ -19,8 +19,8 @@ SECTIONS
   __rodata_end = .;
 	
 	. = 0xa0100000;
+  . = ALIGN(8);
   __data_start = .;
-  . = ALIGN(4);
   .data : 
   {	
     	*(.data)
@@ -28,8 +28,8 @@ SECTIONS
   }
   __data_end = .;
 
-  . = ALIGN(4);
-  __bss_start = __data_end;
+  . = ALIGN(8);
+  __bss_start = .;
   .bss       :
   {
    *(.bss)
diff --git a/bsp/qemu-vexpress-a9/link.lds b/bsp/qemu-vexpress-a9/link.lds
index 13854a2c01..797cd7e3ef 100644
--- a/bsp/qemu-vexpress-a9/link.lds
+++ b/bsp/qemu-vexpress-a9/link.lds
@@ -67,8 +67,8 @@ SECTIONS
         PROVIDE(__dtors_end__ = .);
     }
 
+    . = ALIGN(8);
     __data_start = .;
-    . = ALIGN(4);
     .data :
     {
         *(.data)
@@ -76,8 +76,8 @@ SECTIONS
     }
     __data_end = .;
 
-    . = ALIGN(4);
-    __bss_start = __data_end;
+    . = ALIGN(8);
+    __bss_start = .;
     .bss       :
     {
     *(.bss)
diff --git a/bsp/qemu-vexpress-gemini/cpu/start_gcc.S b/bsp/qemu-vexpress-gemini/cpu/start_gcc.S
index ca8c1f930f..0c64d9fecf 100644
--- a/bsp/qemu-vexpress-gemini/cpu/start_gcc.S
+++ b/bsp/qemu-vexpress-gemini/cpu/start_gcc.S
@@ -48,6 +48,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept ISR_Stack_Size
 .byte 0
diff --git a/bsp/qemu-vexpress-gemini/vexpress.lds b/bsp/qemu-vexpress-gemini/vexpress.lds
index 96863d3f89..2e631aa4ae 100644
--- a/bsp/qemu-vexpress-gemini/vexpress.lds
+++ b/bsp/qemu-vexpress-gemini/vexpress.lds
@@ -57,8 +57,8 @@ SECTIONS
         PROVIDE(__dtors_end__ = .);
     }
 
+    . = ALIGN(8);
     __data_start = .;
-    . = ALIGN(4);
     .data :
     {
         *(.data)
@@ -66,8 +66,8 @@ SECTIONS
     }
     __data_end = .;
 
-    . = ALIGN(4);
-    __bss_start = __data_end;
+    . = ALIGN(8);
+    __bss_start = .;
     .bss       :
     {
     *(.bss)
diff --git a/bsp/raspi2/cpu/start_gcc.S b/bsp/raspi2/cpu/start_gcc.S
index e64563c91e..b60ad6a38f 100644
--- a/bsp/raspi2/cpu/start_gcc.S
+++ b/bsp/raspi2/cpu/start_gcc.S
@@ -48,6 +48,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept ISR_Stack_Size
 .byte 0
diff --git a/bsp/realview-a8/realview.lds b/bsp/realview-a8/realview.lds
index ceaead6969..f586228840 100644
--- a/bsp/realview-a8/realview.lds
+++ b/bsp/realview-a8/realview.lds
@@ -57,8 +57,8 @@ SECTIONS
         PROVIDE(__dtors_end__ = .);
     }
 
+    . = ALIGN(8);
     __data_start = .;
-    . = ALIGN(4);
     .data :
     {
         *(.data)
@@ -66,8 +66,8 @@ SECTIONS
     }
     __data_end = .;
 
-    . = ALIGN(4);
-    __bss_start = __data_end;
+    . = ALIGN(8);
+    __bss_start = .;
     .bss       :
     {
     *(.bss)
diff --git a/libcpu/arm/am335x/start_gcc.S b/libcpu/arm/am335x/start_gcc.S
index 6b76fb04a4..7e996e2a80 100644
--- a/libcpu/arm/am335x/start_gcc.S
+++ b/libcpu/arm/am335x/start_gcc.S
@@ -33,6 +33,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept ISR_Stack_Size
 .long 0
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 91faa0e3ff..268cc7ef56 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -41,6 +41,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept ISR_Stack_Size
 .byte 0
diff --git a/libcpu/arm/cortex-r4/start_gcc.S b/libcpu/arm/cortex-r4/start_gcc.S
index ab77b98781..a347503ec0 100644
--- a/libcpu/arm/cortex-r4/start_gcc.S
+++ b/libcpu/arm/cortex-r4/start_gcc.S
@@ -36,6 +36,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
 .byte 0
diff --git a/libcpu/arm/realview-a8-vmm/start_gcc.S b/libcpu/arm/realview-a8-vmm/start_gcc.S
index 2ec7fe6c86..879cf992a8 100644
--- a/libcpu/arm/realview-a8-vmm/start_gcc.S
+++ b/libcpu/arm/realview-a8-vmm/start_gcc.S
@@ -47,6 +47,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept ISR_Stack_Size
 .byte 0
diff --git a/libcpu/arm/zynq7000/start_gcc.S b/libcpu/arm/zynq7000/start_gcc.S
index 6904c45587..18056f0ad9 100644
--- a/libcpu/arm/zynq7000/start_gcc.S
+++ b/libcpu/arm/zynq7000/start_gcc.S
@@ -33,6 +33,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 .bss
 stack_start:
 .rept ISR_Stack_Size
-- 
cgit v1.3.1


From cabdbf5bbf8faadee94d01316509ce6e1e82c56f Mon Sep 17 00:00:00 2001
From: ZYH <lymz@foxmail.com>
Date: Wed, 23 Oct 2019 15:04:30 +0800
Subject: [libcpu][M7]修复cache编译警告
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: ZYH <lymz@foxmail.com>
---
 libcpu/arm/cortex-m7/cpu_cache.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c
index 4a1a9c2201..350b819c00 100644
--- a/libcpu/arm/cortex-m7/cpu_cache.c
+++ b/libcpu/arm/cortex-m7/cpu_cache.c
@@ -72,15 +72,15 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
 
     if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
     {
-        SCB_CleanInvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+        SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte);
     }
     else if (ops & RT_HW_CACHE_FLUSH)
     {
-        SCB_CleanDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+        SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size_byte);
     }
     else if (ops & RT_HW_CACHE_INVALIDATE)
     {
-        SCB_InvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+        SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte);
     }
     else
     {
-- 
cgit v1.3.1


From a16f27d84e098934c22faba621322943ee8a061f Mon Sep 17 00:00:00 2001
From: tangyuxin <462747508@qq.com>
Date: Tue, 29 Oct 2019 09:45:17 +0800
Subject: [libcpu][cm33] support cortex-m33

---
 libcpu/arm/cortex-m33/SConscript     |  23 ++
 libcpu/arm/cortex-m33/context_gcc.S  | 293 ++++++++++++++++++++
 libcpu/arm/cortex-m33/context_iar.S  | 300 +++++++++++++++++++++
 libcpu/arm/cortex-m33/context_rvds.S | 306 +++++++++++++++++++++
 libcpu/arm/cortex-m33/cpuport.c      | 510 +++++++++++++++++++++++++++++++++++
 libcpu/arm/cortex-m33/syscall_gcc.S  |  59 ++++
 libcpu/arm/cortex-m33/syscall_iar.S  |  63 +++++
 libcpu/arm/cortex-m33/syscall_rvds.S |  74 +++++
 libcpu/arm/cortex-m33/trustzone.c    | 123 +++++++++
 9 files changed, 1751 insertions(+)
 create mode 100644 libcpu/arm/cortex-m33/SConscript
 create mode 100644 libcpu/arm/cortex-m33/context_gcc.S
 create mode 100644 libcpu/arm/cortex-m33/context_iar.S
 create mode 100644 libcpu/arm/cortex-m33/context_rvds.S
 create mode 100644 libcpu/arm/cortex-m33/cpuport.c
 create mode 100644 libcpu/arm/cortex-m33/syscall_gcc.S
 create mode 100644 libcpu/arm/cortex-m33/syscall_iar.S
 create mode 100644 libcpu/arm/cortex-m33/syscall_rvds.S
 create mode 100644 libcpu/arm/cortex-m33/trustzone.c

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m33/SConscript b/libcpu/arm/cortex-m33/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/arm/cortex-m33/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S
new file mode 100644
index 0000000000..3c7dcfa3d7
--- /dev/null
+++ b/libcpu/arm/cortex-m33/context_gcc.S
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-10-11     Bernard      first version
+ * 2012-01-01     aozima       support context switch load/store FPU register.
+ * 2013-06-18     aozima       add restore MSP feature.
+ * 2013-06-23     aozima       support lazy stack optimized.
+ * 2018-07-24     aozima       enhancement hard fault exception handler.
+ */
+
+/**
+ * @addtogroup cortex-m4
+ */
+/*@{*/
+
+.cpu cortex-m4
+.syntax unified
+.thumb
+.text
+
+.equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
+.equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
+.equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
+.equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
+.equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.global rt_hw_interrupt_disable
+.type rt_hw_interrupt_disable, %function
+rt_hw_interrupt_disable:
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.global rt_hw_interrupt_enable
+.type rt_hw_interrupt_enable, %function
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, r0
+    BX      LR
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.global rt_hw_context_switch_interrupt
+.type rt_hw_context_switch_interrupt, %function
+.global rt_hw_context_switch
+.type rt_hw_context_switch, %function
+
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    /* set rt_thread_switch_interrupt_flag to 1 */
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
+    STR     r0, [r2]
+
+_reswitch:
+    LDR     r2, =rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
+    STR     r1, [r2]
+
+    LDR r0, =NVIC_INT_CTRL              /* trigger the PendSV exception (causes context switch) */
+    LDR r1, =NVIC_PENDSVSET
+    STR r1, [r0]
+    BX  LR
+
+/* r0 --> switch from thread stack
+ * r1 --> switch to thread stack
+ * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+ */
+.global PendSV_Handler
+.type PendSV_Handler, %function
+PendSV_Handler:
+    /* disable interrupt to protect context switch */
+    MRS r2, PRIMASK
+    CPSID   I
+
+    /* get rt_thread_switch_interrupt_flag */
+    LDR     r0, =rt_thread_switch_interrupt_flag    /* r0 = &rt_thread_switch_interrupt_flag */
+    LDR     r1, [r0]                                /* r1 = *r1 */
+    CMP     r1, #0x00                               /* compare r1 == 0x00 */
+    BNE     schedule
+    MSR     PRIMASK, r2                             /* if r1 == 0x00, do msr PRIMASK, r2 */
+    BX      lr                                      /* if r1 == 0x00, do bx lr */
+
+schedule
+    PUSH    {r2}                                    /* store interrupt state */
+
+    /* clear rt_thread_switch_interrupt_flag to 0 */
+    MOV     r1, #0x00                               /* r1 = 0x00 */
+    STR     r1, [r0]                                /* *r0 = r1 */
+
+    /* skip register save at the first time */
+    LDR     r0, =rt_interrupt_from_thread           /* r0 = &rt_interrupt_from_thread */
+    LDR     r1, [r0]                                /* r1 = *r0 */
+    CBZ     r1, switch_to_thread                    /* if r1 == 0, goto switch_to_thread */
+
+    /* Whether TrustZone thread stack exists */
+    LDR     r1,  =rt_trustzone_current_context      /* r1 = &rt_secure_current_context */
+    LDR     r1, [r1]                                /* r1 = *r1 */
+    CBZ     r1, contex_ns_store                     /* if r1 == 0, goto contex_ns_store */
+
+    /*call TrustZone fun, Save TrustZone stack */
+    STMFD   sp!, {r0-r1, lr}                        /* push register */
+    MOV     r0, r1                                  /* r0 = rt_secure_current_context */
+    BL rt_trustzone_context_store                   /* call TrustZone store fun */
+    LDMFD   sp!, {r0-r1, lr}                        /* pop register */
+
+    /* check break from TrustZone */
+    MOV     r2, lr                                  /* r2 = lr */
+    TST     r2, #0x40                               /* if EXC_RETURN[6] is 1, TrustZone stack was used */
+    BEQ     contex_ns_store                         /* if r2 & 0x40 == 0, goto contex_ns_store */
+
+    /* push PSPLIM CONTROL PSP LR current_context to stack */
+    MRS     r3, psplim                              /* r3 = psplim */
+    MRS     r4, control                             /* r4 = control */
+    MRS     r5, psp                                 /* r5 = psp */
+    STMFD   r5!, {r1-r4}                            /* push to thread stack */
+
+    /* update from thread stack pointer */
+    LDR     r0, [r0]                                /* r0 = rt_thread_switch_interrupt_flag */
+    STR     r5, [r0]                                /* *r0 = r5 */
+    b switch_to_thread                              /* goto switch_to_thread */
+
+contex_ns_store:
+
+    MRS     r1, psp                                 /* get from thread stack pointer */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    TST     lr, #0x10                               /* if(!EXC_RETURN[4]) */
+    VSTMDBEQ  r1!, {d8 - d15}                       /* push FPU register s16~s31 */
+#endif
+
+    STMFD   r1!, {r4 - r11}                         /* push r4 - r11 register */
+
+    LDR     r2,  =rt_trustzone_current_context      /* r2 = &rt_secure_current_context */
+    LDR     r2, [r2]                                /* r2 = *r2 */
+    MOV     r3, lr                                  /* r3 = lr */
+    MRS     r4, psplim                              /* r4 = psplim */
+    MRS     r5, control                             /* r5 = control */
+    STMFD   r1!, {r2-r5}                            /* push to thread stack */
+
+    LDR     r0, [r0]
+    STR     r1, [r0]                                /* update from thread stack pointer */
+
+switch_to_thread:
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                                /* load thread stack pointer */
+
+    /* update current TrustZone context */
+    LDMFD   r1!, {r2-r5}                            /* pop thread stack */
+    MSR     psplim, r4                              /* psplim = r4 */
+    MSR     control, r5                             /* control = r5 */
+    MOV     lr, r3                                  /* lr = r3 */
+    LDR     r6,  =rt_trustzone_current_context      /* r6 = &rt_secure_current_context */
+    STR     r2, [r6]                                /* *r6 = r2 */
+    MOV     r0, r2                                  /* r0 = r2 */
+
+    /* Whether TrustZone thread stack exists */
+    CBZ     r0, contex_ns_load                      /* if r0 == 0, goto contex_ns_load */
+    PUSH    {r1, r3}                                /* push lr, thread_stack */
+    BL rt_trustzone_context_load                    /* call TrustZone load fun */
+    POP     {r1, r3}                                /* pop lr, thread_stack */
+    MOV     lr, r3                                  /* lr = r1 */
+    TST     r3, #0x40                               /* if EXC_RETURN[6] is 1, TrustZone stack was used */
+    BEQ     contex_ns_load                          /* if r1 & 0x40 == 0, goto contex_ns_load */
+    B pendsv_exit
+
+contex_ns_load:
+    LDMFD   r1!, {r4 - r11}                         /* pop r4 - r11 register */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    TST     lr, #0x10                               /* if(!EXC_RETURN[4]) */
+    VLDMIAEQ  r1!, {d8 - d15}                       /* pop FPU register s16~s31 */
+#endif
+
+pendsv_exit:
+    MSR     psp, r1                                 /* update stack pointer */
+    /* restore interrupt */
+    POP    {r2}
+    MSR     PRIMASK, r2
+
+    BX      lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.global rt_hw_context_switch_to
+.type rt_hw_context_switch_to, %function
+rt_hw_context_switch_to:
+    LDR r1, =rt_interrupt_to_thread
+    STR r0, [r1]
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    /* CLEAR CONTROL.FPCA */
+    MRS     r2, CONTROL         /* read */
+    BIC     r2, #0x04           /* modify */
+    MSR     CONTROL, r2         /* write-back */
+#endif
+
+    /* set from thread to 0 */
+    LDR r1, =rt_interrupt_from_thread
+    MOV r0, #0x0
+    STR r0, [r1]
+
+    /* set interrupt flag to 1 */
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    /* set the PendSV exception priority */
+    LDR r0, =NVIC_SYSPRI2
+    LDR r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       /* read       */
+    ORR     r1,r1,r2             /* modify     */
+    STR     r1, [r0]             /* write-back */
+
+    LDR r0, =NVIC_INT_CTRL      /* trigger the PendSV exception (causes context switch) */
+    LDR r1, =NVIC_PENDSVSET
+    STR r1, [r0]
+
+    /* restore MSP */
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    /* enable interrupts at processor level */
+    CPSIE   F
+    CPSIE   I
+
+    /* never reach here! */
+
+/* compatible with old version */
+.global rt_hw_interrupt_thread_switch
+.type rt_hw_interrupt_thread_switch, %function
+rt_hw_interrupt_thread_switch:
+    BX  lr
+    NOP
+
+.global HardFault_Handler
+.type HardFault_Handler, %function
+HardFault_Handler:
+    /* get current context */
+    MRS     r0, msp                                 /* get fault context from handler. */
+    TST     lr, #0x04                               /* if(!EXC_RETURN[2]) */
+    BEQ     get_sp_done
+    MRS     r0, psp                                 /* get fault context from thread. */
+get_sp_done:
+
+    STMFD   r0!, {r4 - r11}                         /* push r4 - r11 register */
+
+    LDR     r2,  =rt_trustzone_current_context      /* r2 = &rt_secure_current_context */
+    LDR     r2, [r2]                                /* r2 = *r2 */
+    MOV     r3, lr                                  /* r3 = lr */
+    MRS     r4, psplim                              /* r4 = psplim */
+    MRS     r5, control                             /* r5 = control */
+    STMFD   r0!, {r2-r5}                            /* push to thread stack */
+
+    STMFD   r0!, {lr}                               /* push exec_return register */
+
+    TST     lr, #0x04                               /* if(!EXC_RETURN[2]) */
+    BEQ     update_msp
+    MSR     psp, r0                                 /* update stack pointer to PSP. */
+    B       update_done
+update_msp:
+    MSR     msp, r0                                 /* update stack pointer to MSP. */
+update_done:
+
+    PUSH    {LR}
+    BL      rt_hw_hard_fault_exception
+    POP     {LR}
+
+    ORR     lr, lr, #0x04
+    BX      lr
diff --git a/libcpu/arm/cortex-m33/context_iar.S b/libcpu/arm/cortex-m33/context_iar.S
new file mode 100644
index 0000000000..4a32c5bcef
--- /dev/null
+++ b/libcpu/arm/cortex-m33/context_iar.S
@@ -0,0 +1,300 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version
+; * 2009-09-27     Bernard      add protect when contex switch occurs
+; * 2012-01-01     aozima       support context switch load/store FPU register.
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2013-06-23     aozima       support lazy stack optimized.
+; * 2018-07-24     aozima       enhancement hard fault exception handler.
+; */
+
+;/**
+; * @addtogroup cortex-m33
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+    IMPORT rt_trustzone_current_context
+    IMPORT rt_trustzone_context_load
+    IMPORT rt_trustzone_context_store
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+    EXPORT rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+    EXPORT  rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, r0
+    BX      LR
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+    EXPORT rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+    EXPORT PendSV_Handler
+PendSV_Handler:
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK
+    CPSID   I
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag    ; r0 = &rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]                                ; r1 = *r1
+    CMP     r1, #0x00                               ; compare r1 == 0x00
+    BNE     schedule
+    MSR     PRIMASK, r2                             ; if r1 == 0x00, do msr PRIMASK, r2
+    BX      lr                                      ; if r1 == 0x00, do bx lr
+
+schedule
+    PUSH    {r2}                                    ; store interrupt state
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOV     r1, #0x00                               ; r1 = 0x00
+    STR     r1, [r0]                                ; *r0 = r1
+
+    ; skip register save at the first time
+    LDR     r0, =rt_interrupt_from_thread           ; r0 = &rt_interrupt_from_thread
+    LDR     r1, [r0]                                ; r1 = *r0
+    CBZ     r1, switch_to_thread                    ; if r1 == 0, goto switch_to_thread
+
+    ; Whether TrustZone thread stack exists
+    LDR     r1,  =rt_trustzone_current_context      ; r1 = &rt_secure_current_context
+    LDR     r1, [r1]                                ; r1 = *r1
+    CBZ     r1, contex_ns_store                     ; if r1 == 0, goto contex_ns_store
+
+    ;call TrustZone fun, Save TrustZone stack
+    STMFD   sp!, {r0-r1, lr}                        ; push register
+    MOV     r0, r1                                  ; r0 = rt_secure_current_context
+    BL rt_trustzone_context_store                   ; call TrustZone store fun
+    LDMFD   sp!, {r0-r1, lr}                        ; pop register
+
+    ; check break from TrustZone
+    MOV     r2, lr                                  ; r2 = lr
+    TST     r2, #0x40                               ; if EXC_RETURN[6] is 1, TrustZone stack was used
+    BEQ     contex_ns_store                         ; if r2 & 0x40 == 0, goto contex_ns_store
+
+    ; push PSPLIM CONTROL PSP LR current_context to stack
+    MRS     r3, psplim                              ; r3 = psplim
+    MRS     r4, control                             ; r4 = control
+    MRS     r5, psp                                 ; r5 = psp
+    STMFD   r5!, {r1-r4}                            ; push to thread stack
+
+    ; update from thread stack pointer
+    LDR     r0, [r0]                                ; r0 = rt_thread_switch_interrupt_flag
+    STR     r5, [r0]                                ; *r0 = r5
+    b switch_to_thread                              ; goto switch_to_thread
+
+contex_ns_store
+
+    MRS     r1, psp                                 ; get from thread stack pointer
+
+#if defined ( __ARMVFP__ )
+    TST     lr, #0x10                               ; if(!EXC_RETURN[4])
+    BNE     skip_push_fpu
+    VSTMDB  r1!, {d8 - d15}                         ; push FPU register s16~s31
+skip_push_fpu
+#endif
+
+    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
+
+    LDR     r2,  =rt_trustzone_current_context      ; r2 = &rt_secure_current_context
+    LDR     r2, [r2]                                ; r2 = *r2
+    MOV     r3, lr                                  ; r3 = lr
+    MRS     r4, psplim                              ; r4 = psplim
+    MRS     r5, control                             ; r5 = control
+    STMFD   r1!, {r2-r5}                            ; push to thread stack
+
+    LDR     r0, [r0]
+    STR     r1, [r0]                                ; update from thread stack pointer
+
+switch_to_thread
+
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                ; load thread stack pointer
+
+    ; update current TrustZone context
+    LDMFD   r1!, {r2-r5}                            ; pop thread stack
+    MSR     psplim, r4                              ; psplim = r4
+    MSR     control, r5                             ; control = r5
+    MOV     lr, r3                                  ; lr = r3
+    LDR     r6,  =rt_trustzone_current_context      ; r6 = &rt_secure_current_context
+    STR     r2, [r6]                                ; *r6 = r2
+    MOV     r0, r2                                  ; r0 = r2
+
+    ; Whether TrustZone thread stack exists
+    CBZ     r0, contex_ns_load                      ; if r0 == 0, goto contex_ns_load
+    PUSH    {r1, r3}                                ; push lr, thread_stack
+    BL rt_trustzone_context_load                    ; call TrustZone load fun
+    POP     {r1, r3}                                ; pop lr, thread_stack
+    MOV     lr, r3                                  ; lr = r1
+    TST     r3, #0x40                               ; if EXC_RETURN[6] is 1, TrustZone stack was used
+    BEQ     contex_ns_load                          ; if r1 & 0x40 == 0, goto contex_ns_load
+    B pendsv_exit
+
+contex_ns_load
+    LDMFD   r1!, {r4 - r11}                         ; pop r4 - r11 register
+
+#if defined ( __ARMVFP__ )
+    TST     lr, #0x10                               ; if(!EXC_RETURN[4])
+    BNE     skip_pop_fpu
+    VLDMIA  r1!, {d8 - d15}                         ; pop FPU register s16~s31
+skip_pop_fpu
+#endif
+
+pendsv_exit
+    MSR     psp, r1                                 ; update stack pointer
+    ; restore interrupt
+    POP    {r2}
+    MSR     PRIMASK, r2
+
+    BX      lr
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; */
+    EXPORT rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+#if defined ( __ARMVFP__ )
+    ; CLEAR CONTROL.FPCA
+    MRS     r2, CONTROL             ; read
+    BIC     r2, r2, #0x04           ; modify
+    MSR     CONTROL, r2             ; write-back
+#endif
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOV     r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    LDR     r0, =NVIC_INT_CTRL      ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   F
+    CPSIE   I
+
+    ; never reach here!
+
+; compatible with old version
+    EXPORT rt_hw_interrupt_thread_switch
+rt_hw_interrupt_thread_switch:
+    BX      lr
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler:
+
+    ; get current context
+    MRS     r0, msp                                 ; get fault context from handler.
+    TST     lr, #0x04                               ; if(!EXC_RETURN[2])
+    BEQ     get_sp_done
+    MRS     r0, psp                                 ; get fault context from thread.
+get_sp_done
+
+    STMFD   r0!, {r4 - r11}                         ; push r4 - r11 register
+    
+    LDR     r2,  =rt_trustzone_current_context      ; r2 = &rt_secure_current_context
+    LDR     r2, [r2]                                ; r2 = *r2
+    MOV     r3, lr                                  ; r3 = lr
+    MRS     r4, psplim                              ; r4 = psplim
+    MRS     r5, control                             ; r5 = control
+    STMFD   r0!, {r2-r5}                            ; push to thread stack
+
+    STMFD   r0!, {lr}                               ; push exec_return register
+
+    TST     lr, #0x04                               ; if(!EXC_RETURN[2])
+    BEQ     update_msp
+    MSR     psp, r0                                 ; update stack pointer to PSP.
+    B       update_done
+update_msp
+    MSR     msp, r0                                 ; update stack pointer to MSP.
+update_done
+
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+
+    END
diff --git a/libcpu/arm/cortex-m33/context_rvds.S b/libcpu/arm/cortex-m33/context_rvds.S
new file mode 100644
index 0000000000..7ca43933f2
--- /dev/null
+++ b/libcpu/arm/cortex-m33/context_rvds.S
@@ -0,0 +1,306 @@
+;/*
+;* Copyright (c) 2006-2018, RT-Thread Development Team
+;*
+;* SPDX-License-Identifier: Apache-2.0
+;*
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version.
+; * 2012-01-01     aozima       support context switch load/store FPU register.
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2013-06-23     aozima       support lazy stack optimized.
+; * 2018-07-24     aozima       enhancement hard fault exception handler.
+; */
+
+;/**
+; * @addtogroup cortex-m33
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+    IMPORT rt_trustzone_current_context
+    IMPORT rt_trustzone_context_load
+    IMPORT rt_trustzone_context_store
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable    PROC
+    EXPORT  rt_hw_interrupt_disable
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable    PROC
+    EXPORT  rt_hw_interrupt_enable
+    MSR     PRIMASK, r0
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch_interrupt
+rt_hw_context_switch    PROC
+    EXPORT rt_hw_context_switch
+
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+    ENDP
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+PendSV_Handler   PROC
+    EXPORT PendSV_Handler
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK                             ; R2 = PRIMASK
+    CPSID   I                                       ; disable all interrupt
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag    ; r0 = &rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]                                ; r1 = *r1
+    CMP     r1, #0x00                               ; compare r1 == 0x00
+    BNE     schedule
+    MSR     PRIMASK, r2                             ; if r1 == 0x00, do msr PRIMASK, r2
+    BX      lr                                      ; if r1 == 0x00, do bx lr
+
+schedule
+    PUSH    {r2}                                    ; store interrupt state
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOV     r1, #0x00                               ; r1 = 0x00
+    STR     r1, [r0]                                ; *r0 = r1
+
+    ; skip register save at the first time
+    LDR     r0, =rt_interrupt_from_thread           ; r0 = &rt_interrupt_from_thread
+    LDR     r1, [r0]                                ; r1 = *r0
+    CBZ     r1, switch_to_thread                    ; if r1 == 0, goto switch_to_thread
+
+    ; Whether TrustZone thread stack exists
+    LDR     r1,  =rt_trustzone_current_context      ; r1 = &rt_secure_current_context
+    LDR     r1, [r1]                                ; r1 = *r1
+    CBZ     r1, contex_ns_store                     ; if r1 == 0, goto contex_ns_store
+
+    ;call TrustZone fun, Save TrustZone stack
+    STMFD   sp!, {r0-r1, lr}                        ; push register
+    MOV     r0, r1                                  ; r0 = rt_secure_current_context
+    BL rt_trustzone_context_store                   ; call TrustZone store fun
+    LDMFD   sp!, {r0-r1, lr}                        ; pop register
+
+    ; check break from TrustZone
+    MOV     r2, lr                                  ; r2 = lr
+    TST     r2, #0x40                               ; if EXC_RETURN[6] is 1, TrustZone stack was used
+    BEQ     contex_ns_store                         ; if r2 & 0x40 == 0, goto contex_ns_store
+
+    ; push PSPLIM CONTROL PSP LR current_context to stack
+    MRS     r3, psplim                              ; r3 = psplim
+    MRS     r4, control                             ; r4 = control
+    MRS     r5, psp                                 ; r5 = psp
+    STMFD   r5!, {r1-r4}                            ; push to thread stack
+
+    ; update from thread stack pointer
+    LDR     r0, [r0]                                ; r0 = rt_thread_switch_interrupt_flag
+    STR     r5, [r0]                                ; *r0 = r5
+    b switch_to_thread                              ; goto switch_to_thread
+
+contex_ns_store
+
+    MRS     r1, psp                                 ; get from thread stack pointer
+
+    IF      {FPU} != "SoftVFP"
+    TST     lr, #0x10                               ; if(!EXC_RETURN[4])
+    VSTMFDEQ  r1!, {d8 - d15}                       ; push FPU register s16~s31
+    ENDIF
+
+    STMFD   r1!, {r4 - r11}                         ; push r4 - r11 register
+
+    LDR     r2,  =rt_trustzone_current_context      ; r2 = &rt_secure_current_context
+    LDR     r2, [r2]                                ; r2 = *r2
+    MOV     r3, lr                                  ; r3 = lr
+    MRS     r4, psplim                              ; r4 = psplim
+    MRS     r5, control                             ; r5 = control
+    STMFD   r1!, {r2-r5}                            ; push to thread stack
+
+    LDR     r0, [r0]
+    STR     r1, [r0]                                ; update from thread stack pointer
+
+switch_to_thread
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                                ; load thread stack pointer
+
+    ; update current TrustZone context
+    LDMFD   r1!, {r2-r5}                            ; pop thread stack
+    MSR     psplim, r4                              ; psplim = r4
+    MSR     control, r5                             ; control = r5
+    MOV     lr, r3                                  ; lr = r3
+    LDR     r6,  =rt_trustzone_current_context      ; r6 = &rt_secure_current_context
+    STR     r2, [r6]                                ; *r6 = r2
+    MOV     r0, r2                                  ; r0 = r2
+
+    ; Whether TrustZone thread stack exists
+    CBZ     r0, contex_ns_load                      ; if r0 == 0, goto contex_ns_load
+    PUSH    {r1, r3}                                ; push lr, thread_stack
+    BL rt_trustzone_context_load                    ; call TrustZone load fun
+    POP     {r1, r3}                                ; pop lr, thread_stack
+    MOV     lr, r3                                  ; lr = r1
+    TST     r3, #0x40                               ; if EXC_RETURN[6] is 1, TrustZone stack was used
+    BEQ     contex_ns_load                          ; if r1 & 0x40 == 0, goto contex_ns_load
+    B pendsv_exit
+
+contex_ns_load
+    LDMFD   r1!, {r4 - r11}                         ; pop r4 - r11 register
+
+    IF      {FPU} != "SoftVFP"
+    TST     lr, #0x10                               ; if(!EXC_RETURN[4])
+    VLDMFDEQ  r1!, {d8 - d15}                       ; pop FPU register s16~s31
+    ENDIF
+
+pendsv_exit
+    MSR     psp, r1                                 ; update stack pointer
+    ; restore interrupt
+    POP    {r2}
+    MSR     PRIMASK, r2
+
+    BX      lr
+    ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to    PROC
+    EXPORT rt_hw_context_switch_to
+    ; set to thread
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+    IF      {FPU} != "SoftVFP"
+    ; CLEAR CONTROL.FPCA
+    MRS     r2, CONTROL             ; read
+    BIC     r2, #0x04               ; modify
+    MSR     CONTROL, r2             ; write-back
+    ENDIF
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOV     r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    ; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   F
+    CPSIE   I
+
+    ; never reach here!
+    ENDP
+
+; compatible with old version
+rt_hw_interrupt_thread_switch PROC
+    EXPORT rt_hw_interrupt_thread_switch
+    BX      lr
+    ENDP
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler    PROC
+
+    ; get current context
+    MRS     r0, msp                 ;get fault context from handler
+    TST     lr, #0x04               ;if(!EXC_RETURN[2])
+    BEQ     get_sp_done
+    MRS     r0, psp                 ;get fault context from thread
+get_sp_done
+
+    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
+
+    LDR     r2,  =rt_trustzone_current_context      ; r2 = &rt_secure_current_context
+    LDR     r2, [r2]                                ; r2 = *r2
+    MOV     r3, lr                                  ; r3 = lr
+    MRS     r4, psplim                              ; r4 = psplim
+    MRS     r5, control                             ; r5 = control
+    STMFD   r0!, {r2-r5}                            ; push to thread stack
+
+    STMFD   r0!, {lr}               ; push exec_return register
+
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    BEQ     update_msp
+    MSR     psp, r0                 ; update stack pointer to PSP
+    B       update_done
+update_msp
+    MSR     msp, r0                 ; update stack pointer to MSP
+update_done
+
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+    ENDP
+
+    ALIGN   4
+
+    END
diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c
new file mode 100644
index 0000000000..415f560911
--- /dev/null
+++ b/libcpu/arm/cortex-m33/cpuport.c
@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-10-21     Bernard      the first version.
+ * 2011-10-27     aozima       update for cortex-M4 FPU.
+ * 2011-12-31     aozima       fixed stack align issues.
+ * 2012-01-01     aozima       support context switch load/store FPU register.
+ * 2012-12-11     lgnq         fixed the coding style.
+ * 2012-12-23     aozima       stack addr align to 8byte.
+ * 2012-12-29     Bernard      Add exception hook.
+ * 2013-06-23     aozima       support lazy stack optimized.
+ * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
+ */
+
+#include <rtthread.h>
+
+#if               /* ARMCC */ (  (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP ))    \
+                  /* Clang */ || (defined ( __CLANG_ARM ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \
+                  /* IAR */   || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ ))        \
+                  /* GNU */   || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) )
+#define USE_FPU   1
+#else
+#define USE_FPU   0
+#endif
+
+/* exception and interrupt handler table */
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+/* exception hook */
+static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
+
+struct exception_stack_frame
+{
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r12;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t psr;
+};
+
+struct stack_frame
+{
+    rt_uint32_t tz;
+    rt_uint32_t lr;
+    rt_uint32_t psplim;
+    rt_uint32_t control;
+
+    /* r4 ~ r11 register */
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+
+    struct exception_stack_frame exception_stack_frame;
+};
+
+struct exception_stack_frame_fpu
+{
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r12;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t psr;
+
+#if USE_FPU
+    /* FPU register */
+    rt_uint32_t S0;
+    rt_uint32_t S1;
+    rt_uint32_t S2;
+    rt_uint32_t S3;
+    rt_uint32_t S4;
+    rt_uint32_t S5;
+    rt_uint32_t S6;
+    rt_uint32_t S7;
+    rt_uint32_t S8;
+    rt_uint32_t S9;
+    rt_uint32_t S10;
+    rt_uint32_t S11;
+    rt_uint32_t S12;
+    rt_uint32_t S13;
+    rt_uint32_t S14;
+    rt_uint32_t S15;
+    rt_uint32_t FPSCR;
+    rt_uint32_t NO_NAME;
+#endif
+};
+
+struct stack_frame_fpu
+{
+    rt_uint32_t flag;
+
+    /* r4 ~ r11 register */
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+
+#if USE_FPU
+    /* FPU register s16 ~ s31 */
+    rt_uint32_t s16;
+    rt_uint32_t s17;
+    rt_uint32_t s18;
+    rt_uint32_t s19;
+    rt_uint32_t s20;
+    rt_uint32_t s21;
+    rt_uint32_t s22;
+    rt_uint32_t s23;
+    rt_uint32_t s24;
+    rt_uint32_t s25;
+    rt_uint32_t s26;
+    rt_uint32_t s27;
+    rt_uint32_t s28;
+    rt_uint32_t s29;
+    rt_uint32_t s30;
+    rt_uint32_t s31;
+#endif
+
+    struct exception_stack_frame_fpu exception_stack_frame;
+};
+
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct stack_frame *stack_frame;
+    rt_uint8_t         *stk;
+    unsigned long       i;
+
+    stk  = stack_addr + sizeof(rt_uint32_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
+    stk -= sizeof(struct stack_frame);
+
+    stack_frame = (struct stack_frame *)stk;
+
+    /* init all register */
+    for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
+    {
+        ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
+    }
+
+    stack_frame->exception_stack_frame.r0  = (unsigned long)parameter; /* r0 : argument */
+    stack_frame->exception_stack_frame.r1  = 0;                        /* r1 */
+    stack_frame->exception_stack_frame.r2  = 0;                        /* r2 */
+    stack_frame->exception_stack_frame.r3  = 0;                        /* r3 */
+    stack_frame->exception_stack_frame.r12 = 0;                        /* r12 */
+    stack_frame->exception_stack_frame.lr  = (unsigned long)texit;     /* lr */
+    stack_frame->exception_stack_frame.pc  = (unsigned long)tentry;    /* entry point, pc */
+    stack_frame->exception_stack_frame.psr = 0x01000000L;              /* PSR */
+
+    stack_frame->tz = 0x00;
+    stack_frame->lr = 0xFFFFFFBC;
+    stack_frame->psplim = 0x00;
+    stack_frame->control = 0x00;
+
+    /* return task's current stack address */
+    return stk;
+}
+
+/**
+ * This function set the hook, which is invoked on fault exception handling.
+ *
+ * @param exception_handle the exception handling hook function.
+ */
+void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
+{
+    rt_exception_hook = exception_handle;
+}
+
+#define SCB_CFSR        (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
+#define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
+#define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
+#define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED0C)  /* Reset control Address Register */
+#define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
+
+#define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
+#define SCB_CFSR_BFSR   (*(volatile const unsigned char*)0xE000ED29)  /* Bus Fault Status Register */
+#define SCB_CFSR_UFSR   (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
+
+#ifdef RT_USING_FINSH
+static void usage_fault_track(void)
+{
+    rt_kprintf("usage fault:\n");
+    rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
+
+    if(SCB_CFSR_UFSR & (1<<0))
+    {
+        /* [0]:UNDEFINSTR */
+        rt_kprintf("UNDEFINSTR ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<1))
+    {
+        /* [1]:INVSTATE */
+        rt_kprintf("INVSTATE ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<2))
+    {
+        /* [2]:INVPC */
+        rt_kprintf("INVPC ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<3))
+    {
+        /* [3]:NOCP */
+        rt_kprintf("NOCP ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<8))
+    {
+        /* [8]:UNALIGNED */
+        rt_kprintf("UNALIGNED ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<9))
+    {
+        /* [9]:DIVBYZERO */
+        rt_kprintf("DIVBYZERO ");
+    }
+
+    rt_kprintf("\n");
+}
+
+static void bus_fault_track(void)
+{
+    rt_kprintf("bus fault:\n");
+    rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
+
+    if(SCB_CFSR_BFSR & (1<<0))
+    {
+        /* [0]:IBUSERR */
+        rt_kprintf("IBUSERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<1))
+    {
+        /* [1]:PRECISERR */
+        rt_kprintf("PRECISERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<2))
+    {
+        /* [2]:IMPRECISERR */
+        rt_kprintf("IMPRECISERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<3))
+    {
+        /* [3]:UNSTKERR */
+        rt_kprintf("UNSTKERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<4))
+    {
+        /* [4]:STKERR */
+        rt_kprintf("STKERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<7))
+    {
+        rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR);
+    }
+    else
+    {
+        rt_kprintf("\n");
+    }
+}
+
+static void mem_manage_fault_track(void)
+{
+    rt_kprintf("mem manage fault:\n");
+    rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
+
+    if(SCB_CFSR_MFSR & (1<<0))
+    {
+        /* [0]:IACCVIOL */
+        rt_kprintf("IACCVIOL ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<1))
+    {
+        /* [1]:DACCVIOL */
+        rt_kprintf("DACCVIOL ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<3))
+    {
+        /* [3]:MUNSTKERR */
+        rt_kprintf("MUNSTKERR ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<4))
+    {
+        /* [4]:MSTKERR */
+        rt_kprintf("MSTKERR ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<7))
+    {
+        /* [7]:MMARVALID */
+        rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR);
+    }
+    else
+    {
+        rt_kprintf("\n");
+    }
+}
+
+static void hard_fault_track(void)
+{
+    if(SCB_HFSR & (1UL<<1))
+    {
+        /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */
+        rt_kprintf("failed vector fetch\n");
+    }
+
+    if(SCB_HFSR & (1UL<<30))
+    {
+        /* [30]:FORCED, Indicates hard fault is taken because of bus fault,
+                        memory management fault, or usage fault. */
+        if(SCB_CFSR_BFSR)
+        {
+            bus_fault_track();
+        }
+
+        if(SCB_CFSR_MFSR)
+        {
+            mem_manage_fault_track();
+        }
+
+        if(SCB_CFSR_UFSR)
+        {
+            usage_fault_track();
+        }
+    }
+
+    if(SCB_HFSR & (1UL<<31))
+    {
+        /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */
+        rt_kprintf("debug event\n");
+    }
+}
+#endif /* RT_USING_FINSH */
+
+struct exception_info
+{
+    rt_uint32_t exc_return;
+    struct stack_frame stack_frame;
+};
+
+void rt_hw_hard_fault_exception(struct exception_info *exception_info)
+{
+    extern long list_thread(void);
+    struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame;
+    struct stack_frame *context = &exception_info->stack_frame;
+
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(exception_stack);
+        if (result == RT_EOK) return;
+    }
+
+    rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr);
+
+    rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0);
+    rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1);
+    rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2);
+    rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3);
+    rt_kprintf("r04: 0x%08x\n", context->r4);
+    rt_kprintf("r05: 0x%08x\n", context->r5);
+    rt_kprintf("r06: 0x%08x\n", context->r6);
+    rt_kprintf("r07: 0x%08x\n", context->r7);
+    rt_kprintf("r08: 0x%08x\n", context->r8);
+    rt_kprintf("r09: 0x%08x\n", context->r9);
+    rt_kprintf("r10: 0x%08x\n", context->r10);
+    rt_kprintf("r11: 0x%08x\n", context->r11);
+    rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12);
+    rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr);
+    rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc);
+
+    if (exception_info->exc_return & (1 << 2))
+    {
+        rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name);
+
+#ifdef RT_USING_FINSH
+        list_thread();
+#endif
+    }
+    else
+    {
+        rt_kprintf("hard fault on handler\r\n\r\n");
+    }
+
+    if ( (exception_info->exc_return & 0x10) == 0)
+    {
+        rt_kprintf("FPU active!\r\n");
+    }
+
+#ifdef RT_USING_FINSH
+    hard_fault_track();
+#endif /* RT_USING_FINSH */
+
+    while (1);
+}
+
+/**
+ * shutdown CPU
+ */
+void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    RT_ASSERT(0);
+}
+
+/**
+ * reset CPU
+ */
+RT_WEAK void rt_hw_cpu_reset(void)
+{
+    SCB_AIRCR = SCB_RESET_VALUE;
+}
+
+#ifdef RT_USING_CPU_FFS
+/**
+ * This function finds the first bit set (beginning with the least significant bit)
+ * in value and return the index of that bit.
+ *
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
+ * zero from any of these functions means that the argument was zero.
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
+ * shall return 0.
+ */
+#if defined(__CC_ARM) 
+__asm int __rt_ffs(int value)
+{
+    CMP     r0, #0x00
+    BEQ     exit
+
+    RBIT    r0, r0
+    CLZ     r0, r0
+    ADDS    r0, r0, #0x01
+
+exit
+    BX      lr
+}
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     exit                 \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "exit:                        \n"
+        "BX      lr                   \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+int __rt_ffs(int value)
+{
+    if (value == 0) return value;
+
+    asm("RBIT %0, %1" : "=r"(value) : "r"(value));
+    asm("CLZ  %0, %1" : "=r"(value) : "r"(value));
+    asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value));
+
+    return value;
+}
+#elif defined(__GNUC__)
+int __rt_ffs(int value)
+{
+    return __builtin_ffs(value);
+}
+#endif
+
+#endif
diff --git a/libcpu/arm/cortex-m33/syscall_gcc.S b/libcpu/arm/cortex-m33/syscall_gcc.S
new file mode 100644
index 0000000000..d7d16fb8a0
--- /dev/null
+++ b/libcpu/arm/cortex-m33/syscall_gcc.S
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-10-25     tyx          first version
+ */
+
+.cpu cortex-m4
+.syntax unified
+.thumb
+.text
+
+/*
+ * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
+ */
+.global tzcall
+.type tzcall, %function
+tzcall:
+	SVC     1                       /* call SVC 1 */
+    BX      LR
+
+tzcall_entry:
+    PUSH    {R1, R4, LR}
+    MOV     R4, R1                  /* copy thread SP to R4 */
+    LDMFD   R4!, {r0 - r3}          /* pop user stack, get input arg0, arg1, arg2 */
+    STMFD   R4!, {r0 - r3}          /* push stack, user stack recovery */
+    BL      rt_secure_svc_handle    /* call fun */
+    POP     {R1, R4, LR}
+    STR     R0, [R1]                /* update return value */
+    BX      LR                      /* return to thread */
+
+syscall_entry:
+    BX      LR                      /* return to user app */
+
+.global SVC_Handler
+.type SVC_Handler, %function
+SVC_Handler:
+
+    /* get SP, save to R1 */
+    MRS     R1, MSP                 /* get fault context from handler. */
+    TST     LR, #0x04               /* if(!EXC_RETURN[2]) */
+    BEQ     get_sp_done
+    MRS     R1, PSP                 /* get fault context from thread. */
+get_sp_done:
+
+    /* get svc index */
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]
+
+    /* if svc == 0, do system call */
+    CMP     R0, #0x0
+    BEQ    syscall_entry
+
+    /* if svc == 1, do TrustZone call */
+    CMP     R0, #0x1
+    BEQ    tzcall_entry
diff --git a/libcpu/arm/cortex-m33/syscall_iar.S b/libcpu/arm/cortex-m33/syscall_iar.S
new file mode 100644
index 0000000000..aa30ead9e3
--- /dev/null
+++ b/libcpu/arm/cortex-m33/syscall_iar.S
@@ -0,0 +1,63 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2019-10-25     tyx          first version
+; */
+
+;/*
+; * @addtogroup cortex-m33
+; */
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+;/*
+; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
+; */
+.global tzcall
+.type tzcall, %function
+tzcall:
+	SVC     1                       ;/* call SVC 1 */
+    BX      LR
+
+tzcall_entry:
+    PUSH    {R1, R4, LR}
+    MOV     R4, R1                  ;/* copy thread SP to R4 */
+    LDMFD   R4!, {r0 - r3}          ;/* pop user stack, get input arg0, arg1, arg2 */
+    STMFD   R4!, {r0 - r3}          ;/* push stack, user stack recovery */
+    BL      rt_secure_svc_handle    ;/* call fun */
+    POP     {R1, R4, LR}
+    STR     R0, [R1]                ;/* update return value */
+    BX      LR                      ;/* return to thread */
+
+syscall_entry:
+    BX      LR                      ;/* return to user app */
+
+.global SVC_Handler
+.type SVC_Handler, %function
+SVC_Handler:
+
+    ;/* get SP, save to R1 */
+    MRS     R1, MSP                 ;/* get fault context from handler. */
+    TST     LR, #0x04               ;/* if(!EXC_RETURN[2]) */
+    BEQ     get_sp_done
+    MRS     R1, PSP                 ;/* get fault context from thread. */
+get_sp_done:
+
+    ;/* get svc index */
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]
+
+    ;/* if svc == 0, do system call */
+    CMP     R0, #0x0
+    BEQ    syscall_entry
+
+    ;/* if svc == 1, do TrustZone call */
+    CMP     R0, #0x1
+    BEQ    tzcall_entry
diff --git a/libcpu/arm/cortex-m33/syscall_rvds.S b/libcpu/arm/cortex-m33/syscall_rvds.S
new file mode 100644
index 0000000000..95ee247ee5
--- /dev/null
+++ b/libcpu/arm/cortex-m33/syscall_rvds.S
@@ -0,0 +1,74 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2019-10-25     tyx          first version
+; */
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_secure_svc_handle
+
+;/*
+; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
+; */
+tzcall PROC
+    EXPORT tzcall
+	SVC     1                       ;call SVC 1
+    BX      LR
+
+    ENDP
+
+tzcall_entry     PROC
+    PUSH    {R1, R4, LR}
+    MOV     R4, R1                  ; copy thread SP to R4
+    LDMFD   R4!, {r0 - r3}          ; pop user stack, get input arg0, arg1, arg2 
+    STMFD   R4!, {r0 - r3}          ; push stack, user stack recovery
+    BL      rt_secure_svc_handle    ; call fun
+    POP     {R1, R4, LR}
+    STR     R0, [R1]                ; update return value
+    BX      LR                      ; return to thread
+
+    ENDP
+
+syscall_entry     PROC
+    BX      LR                      ; return to user app
+
+    ENDP
+
+;/*
+; * void SVC_Handler(void);
+; */
+SVC_Handler    PROC
+    EXPORT SVC_Handler
+
+    ; get SP, save to R1
+    MRS     R1, MSP                 ;get fault context from handler
+    TST     LR, #0x04               ;if(!EXC_RETURN[2])
+    BEQ     get_sp_done
+    MRS     R1, PSP                 ;get fault context from thread
+get_sp_done
+
+    ; get svc index
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]
+
+    ;if svc == 0, do system call
+    CMP     R0, #0x0
+    BEQ    syscall_entry
+
+    ;if svc == 1, do TrustZone call
+    CMP     R0, #0x1
+    BEQ    tzcall_entry
+
+    ENDP
+
+    ALIGN
+
+    END
\ No newline at end of file
diff --git a/libcpu/arm/cortex-m33/trustzone.c b/libcpu/arm/cortex-m33/trustzone.c
new file mode 100644
index 0000000000..86654a7199
--- /dev/null
+++ b/libcpu/arm/cortex-m33/trustzone.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-10-28     tyx          the first version.
+ */
+
+#include <rtthread.h>
+
+extern void TZ_InitContextSystem_S(void);
+extern rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module);
+extern rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id);
+extern rt_uint32_t TZ_LoadContext_S(rt_uint32_t id);
+extern rt_uint32_t TZ_StoreContext_S(rt_uint32_t id);
+extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
+
+#define TZ_INIT_CONTEXT_ID     (0x1001)
+#define TZ_ALLOC_CONTEXT_ID    (0x1002)
+#define TZ_FREE_CONTEXT_ID     (0x1003)
+
+rt_ubase_t rt_trustzone_current_context;
+
+#if defined(__CC_ARM) 
+static __inline rt_uint32_t __get_IPSR(void)
+{
+  register rt_uint32_t result          __asm("ipsr");
+  return(result);
+}
+#elif defined(__CLANG_ARM)
+__attribute__((always_inline)) static __inline rt_uint32_t __get_IPSR(void)
+{
+    rt_uint32_t result;
+
+    __asm volatile ("MRS %0, ipsr" : "=r" (result) );
+    return(result);
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+_Pragma("inline=forced") static inline int __get_IPSR(int value)
+{
+    rt_uint32_t result;
+
+    asm("MRS  %0, ipsr" : "=r"(result));
+    return result;
+}
+#elif defined(__GNUC__)
+__attribute__((always_inline)) static inline rt_uint32_t __get_IPSR(void)
+{
+  rt_uint32_t result;
+
+  __asm volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+#endif
+
+void rt_trustzone_init(void)
+{
+    static rt_uint8_t _init;
+
+    if (_init)
+        return;
+    tzcall(TZ_INIT_CONTEXT_ID, 0, 0, 0);
+    _init = 1;
+}
+
+rt_err_t rt_trustzone_enter(rt_ubase_t module)
+{
+    rt_trustzone_init();
+    if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0))
+    {
+        return RT_EOK; 
+    }
+    return -RT_ERROR;
+}
+
+rt_err_t rt_trustzone_exit(void)
+{
+    tzcall(TZ_FREE_CONTEXT_ID, 0, 0, 0);
+    return RT_EOK;
+}
+
+void rt_trustzone_context_store(rt_ubase_t context)
+{
+    TZ_StoreContext_S(context);
+}
+
+void rt_trustzone_context_load(rt_ubase_t context)
+{
+    TZ_LoadContext_S(context);
+}
+
+int rt_secure_svc_handle(int svc_id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2)
+{
+    rt_ubase_t tmp;
+    int res = 0;
+
+    switch (svc_id)
+    {
+    case TZ_INIT_CONTEXT_ID:
+        TZ_InitContextSystem_S();
+        break;
+    case TZ_ALLOC_CONTEXT_ID:
+        res = TZ_AllocModuleContext_S(arg0);
+        if (res <= 0)
+        {
+            rt_kprintf("Alloc Context Failed\n");
+        }
+        else
+        {
+            rt_trustzone_current_context = res;
+            TZ_LoadContext_S(res);
+        }
+        break;
+    case TZ_FREE_CONTEXT_ID:
+        TZ_FreeModuleContext_S(rt_trustzone_current_context);
+        rt_trustzone_current_context = 0;
+        break;
+    }
+    return res;
+}
+
-- 
cgit v1.3.1


From 80a4912baf79d46c696ab4a5c7da92fb511d8cd9 Mon Sep 17 00:00:00 2001
From: ZhangTao <zhangtao@canaan-creative.com>
Date: Tue, 5 Nov 2019 10:30:47 +0800
Subject: 修改了上下文切换退出时的bug，该bug会导致中断被提前打开造成死锁
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/risc-v/common/context_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S
index f28b15319b..5c9f05c4e8 100644
--- a/libcpu/risc-v/common/context_gcc.S
+++ b/libcpu/risc-v/common/context_gcc.S
@@ -175,7 +175,7 @@ rt_hw_context_switch_exit:
     LOAD x1,   1 * REGBYTES(sp)
 
     li    t0, 0x00001800
-    csrs  mstatus, t0
+    csrw  mstatus, t0
     LOAD a0,   2 * REGBYTES(sp)
     csrs mstatus, a0
 
-- 
cgit v1.3.1


From a972fcc0b54ebf274cc2d16d0866385ae5e6c7cf Mon Sep 17 00:00:00 2001
From: Bernard Xiong <bernard.xiong@gmail.com>
Date: Wed, 11 Dec 2019 11:01:40 +0800
Subject: [BSP] move libcpu/mips/x1000 to bsp/x1000/cpu

---
 bsp/x1000/SConstruct                   |    2 +-
 bsp/x1000/cpu/SConscript               |   18 +
 bsp/x1000/cpu/common/SConscript        |   14 +
 bsp/x1000/cpu/common/asm.h             |  220 +++
 bsp/x1000/cpu/common/exception.h       |  166 +++
 bsp/x1000/cpu/common/mips.h            |   25 +
 bsp/x1000/cpu/common/mips.inc          |   52 +
 bsp/x1000/cpu/common/mips_addrspace.h  |  207 +++
 bsp/x1000/cpu/common/mips_asm.h        |  447 +++++++
 bsp/x1000/cpu/common/mips_cache.c      |  153 +++
 bsp/x1000/cpu/common/mips_cache.h      |  234 ++++
 bsp/x1000/cpu/common/mips_cfg.h        |   48 +
 bsp/x1000/cpu/common/mips_context.h    |  280 ++++
 bsp/x1000/cpu/common/mips_def.h        | 2296 ++++++++++++++++++++++++++++++++
 bsp/x1000/cpu/common/mips_excpt.h      |   39 +
 bsp/x1000/cpu/common/mips_regs.h       | 1168 ++++++++++++++++
 bsp/x1000/cpu/common/mips_types.h      |  118 ++
 bsp/x1000/cpu/common/mipscfg.h         |   32 +
 bsp/x1000/cpu/common/mipsregs.h        |  706 ++++++++++
 bsp/x1000/cpu/common/stackframe.h      |  228 ++++
 bsp/x1000/cpu/x1000/SConscript         |   14 +
 bsp/x1000/cpu/x1000/cache.c            |  217 +++
 bsp/x1000/cpu/x1000/cache.h            |   41 +
 bsp/x1000/cpu/x1000/cpu.c              |  131 ++
 bsp/x1000/cpu/x1000/interrupt.c        |  215 +++
 bsp/x1000/cpu/x1000/mips_backtrace.c   |  208 +++
 bsp/x1000/cpu/x1000/mips_cache_gcc.S   |   48 +
 bsp/x1000/cpu/x1000/mips_context_gcc.S |   81 ++
 bsp/x1000/cpu/x1000/mips_excpt.c       |  382 ++++++
 bsp/x1000/cpu/x1000/mips_excpt_gcc.S   |   88 ++
 bsp/x1000/cpu/x1000/mips_fp_gcc.S      |  183 +++
 bsp/x1000/cpu/x1000/stack.c            |   82 ++
 bsp/x1000/cpu/x1000/startup_gcc.S      |  314 +++++
 bsp/x1000/cpu/x1000/x1000.h            |  284 ++++
 bsp/x1000/cpu/x1000/x1000_aic.h        |  794 +++++++++++
 bsp/x1000/cpu/x1000/x1000_cpm.h        |  511 +++++++
 bsp/x1000/cpu/x1000/x1000_intc.h       |  120 ++
 bsp/x1000/cpu/x1000/x1000_otg_dwc.h    |  306 +++++
 bsp/x1000/cpu/x1000/x1000_slcdc.h      |  463 +++++++
 bsp/x1000/rtconfig.py                  |    2 +-
 libcpu/mips/x1000/SConscript           |   14 -
 libcpu/mips/x1000/cache.c              |  217 ---
 libcpu/mips/x1000/cache.h              |   41 -
 libcpu/mips/x1000/cpu.c                |  131 --
 libcpu/mips/x1000/interrupt.c          |  215 ---
 libcpu/mips/x1000/mips_backtrace.c     |  208 ---
 libcpu/mips/x1000/mips_cache_gcc.S     |   48 -
 libcpu/mips/x1000/mips_context_gcc.S   |   81 --
 libcpu/mips/x1000/mips_excpt.c         |  382 ------
 libcpu/mips/x1000/mips_excpt_gcc.S     |   88 --
 libcpu/mips/x1000/mips_fp_gcc.S        |  183 ---
 libcpu/mips/x1000/stack.c              |   82 --
 libcpu/mips/x1000/startup_gcc.S        |  314 -----
 libcpu/mips/x1000/x1000.h              |  284 ----
 libcpu/mips/x1000/x1000_aic.h          |  794 -----------
 libcpu/mips/x1000/x1000_cpm.h          |  511 -------
 libcpu/mips/x1000/x1000_intc.h         |  120 --
 libcpu/mips/x1000/x1000_otg_dwc.h      |  306 -----
 libcpu/mips/x1000/x1000_slcdc.h        |  463 -------
 libcpu/mips/xburst/SConscript          |   11 -
 libcpu/mips/xburst/cache.c             |  118 --
 libcpu/mips/xburst/cache.h             |   62 -
 libcpu/mips/xburst/cache_gcc.S         |   51 -
 libcpu/mips/xburst/context_gcc.S       |  155 ---
 libcpu/mips/xburst/cpu.c               |   75 --
 libcpu/mips/xburst/exception.c         |   81 --
 libcpu/mips/xburst/interrupt.c         |  249 ----
 libcpu/mips/xburst/mipscfg.c           |  358 -----
 libcpu/mips/xburst/stack.c             |  103 --
 libcpu/mips/xburst/stack.h             |   28 -
 libcpu/mips/xburst/start_gcc.S         |  158 ---
 libcpu/mips/xburst/x1000.h             |  329 -----
 72 files changed, 10935 insertions(+), 6262 deletions(-)
 create mode 100644 bsp/x1000/cpu/SConscript
 create mode 100644 bsp/x1000/cpu/common/SConscript
 create mode 100644 bsp/x1000/cpu/common/asm.h
 create mode 100644 bsp/x1000/cpu/common/exception.h
 create mode 100644 bsp/x1000/cpu/common/mips.h
 create mode 100644 bsp/x1000/cpu/common/mips.inc
 create mode 100644 bsp/x1000/cpu/common/mips_addrspace.h
 create mode 100644 bsp/x1000/cpu/common/mips_asm.h
 create mode 100644 bsp/x1000/cpu/common/mips_cache.c
 create mode 100644 bsp/x1000/cpu/common/mips_cache.h
 create mode 100644 bsp/x1000/cpu/common/mips_cfg.h
 create mode 100644 bsp/x1000/cpu/common/mips_context.h
 create mode 100644 bsp/x1000/cpu/common/mips_def.h
 create mode 100644 bsp/x1000/cpu/common/mips_excpt.h
 create mode 100644 bsp/x1000/cpu/common/mips_regs.h
 create mode 100644 bsp/x1000/cpu/common/mips_types.h
 create mode 100644 bsp/x1000/cpu/common/mipscfg.h
 create mode 100644 bsp/x1000/cpu/common/mipsregs.h
 create mode 100644 bsp/x1000/cpu/common/stackframe.h
 create mode 100644 bsp/x1000/cpu/x1000/SConscript
 create mode 100644 bsp/x1000/cpu/x1000/cache.c
 create mode 100644 bsp/x1000/cpu/x1000/cache.h
 create mode 100644 bsp/x1000/cpu/x1000/cpu.c
 create mode 100644 bsp/x1000/cpu/x1000/interrupt.c
 create mode 100644 bsp/x1000/cpu/x1000/mips_backtrace.c
 create mode 100644 bsp/x1000/cpu/x1000/mips_cache_gcc.S
 create mode 100644 bsp/x1000/cpu/x1000/mips_context_gcc.S
 create mode 100644 bsp/x1000/cpu/x1000/mips_excpt.c
 create mode 100644 bsp/x1000/cpu/x1000/mips_excpt_gcc.S
 create mode 100644 bsp/x1000/cpu/x1000/mips_fp_gcc.S
 create mode 100644 bsp/x1000/cpu/x1000/stack.c
 create mode 100644 bsp/x1000/cpu/x1000/startup_gcc.S
 create mode 100644 bsp/x1000/cpu/x1000/x1000.h
 create mode 100644 bsp/x1000/cpu/x1000/x1000_aic.h
 create mode 100644 bsp/x1000/cpu/x1000/x1000_cpm.h
 create mode 100644 bsp/x1000/cpu/x1000/x1000_intc.h
 create mode 100644 bsp/x1000/cpu/x1000/x1000_otg_dwc.h
 create mode 100644 bsp/x1000/cpu/x1000/x1000_slcdc.h
 delete mode 100644 libcpu/mips/x1000/SConscript
 delete mode 100644 libcpu/mips/x1000/cache.c
 delete mode 100644 libcpu/mips/x1000/cache.h
 delete mode 100644 libcpu/mips/x1000/cpu.c
 delete mode 100644 libcpu/mips/x1000/interrupt.c
 delete mode 100644 libcpu/mips/x1000/mips_backtrace.c
 delete mode 100644 libcpu/mips/x1000/mips_cache_gcc.S
 delete mode 100644 libcpu/mips/x1000/mips_context_gcc.S
 delete mode 100644 libcpu/mips/x1000/mips_excpt.c
 delete mode 100644 libcpu/mips/x1000/mips_excpt_gcc.S
 delete mode 100644 libcpu/mips/x1000/mips_fp_gcc.S
 delete mode 100644 libcpu/mips/x1000/stack.c
 delete mode 100644 libcpu/mips/x1000/startup_gcc.S
 delete mode 100644 libcpu/mips/x1000/x1000.h
 delete mode 100644 libcpu/mips/x1000/x1000_aic.h
 delete mode 100644 libcpu/mips/x1000/x1000_cpm.h
 delete mode 100644 libcpu/mips/x1000/x1000_intc.h
 delete mode 100644 libcpu/mips/x1000/x1000_otg_dwc.h
 delete mode 100644 libcpu/mips/x1000/x1000_slcdc.h
 delete mode 100644 libcpu/mips/xburst/SConscript
 delete mode 100644 libcpu/mips/xburst/cache.c
 delete mode 100644 libcpu/mips/xburst/cache.h
 delete mode 100644 libcpu/mips/xburst/cache_gcc.S
 delete mode 100644 libcpu/mips/xburst/context_gcc.S
 delete mode 100644 libcpu/mips/xburst/cpu.c
 delete mode 100644 libcpu/mips/xburst/exception.c
 delete mode 100644 libcpu/mips/xburst/interrupt.c
 delete mode 100644 libcpu/mips/xburst/mipscfg.c
 delete mode 100644 libcpu/mips/xburst/stack.c
 delete mode 100644 libcpu/mips/xburst/stack.h
 delete mode 100644 libcpu/mips/xburst/start_gcc.S
 delete mode 100644 libcpu/mips/xburst/x1000.h

(limited to 'libcpu')

diff --git a/bsp/x1000/SConstruct b/bsp/x1000/SConstruct
index 053d160121..4b71cda8b1 100644
--- a/bsp/x1000/SConstruct
+++ b/bsp/x1000/SConstruct
@@ -28,7 +28,7 @@ Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
 
 if GetDepend('RT_USING_HARD_FLOAT'):
     env['CCFLAGS']   = env['CCFLAGS'].replace('-msoft-float', '-mhard-float')
diff --git a/bsp/x1000/cpu/SConscript b/bsp/x1000/cpu/SConscript
new file mode 100644
index 0000000000..640e46a4fb
--- /dev/null
+++ b/bsp/x1000/cpu/SConscript
@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join('common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/bsp/x1000/cpu/common/SConscript b/bsp/x1000/cpu/common/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/bsp/x1000/cpu/common/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/bsp/x1000/cpu/common/asm.h b/bsp/x1000/cpu/common/asm.h
new file mode 100644
index 0000000000..190e8b110e
--- /dev/null
+++ b/bsp/x1000/cpu/common/asm.h
@@ -0,0 +1,220 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 1999 by Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ *
+ * Some useful macros for MIPS assembler code
+ *
+ * Some of the routines below contain useless nops that will be optimized
+ * away by gas in -O mode. These nops are however required to fill delay
+ * slots in noreorder mode.
+ */
+#ifndef __ASM_H__
+#define __ASM_H__
+
+/*
+ * LEAF - declare leaf routine
+ */
+#define	LEAF(symbol)                        \
+		.globl	symbol;                     \
+		.align	2;                          \
+		.type	symbol,@function;           \
+		.ent	symbol,0;                   \
+symbol:		.frame	sp,0,ra
+
+/*
+ * NESTED - declare nested routine entry point
+ */
+#define	NESTED(symbol, framesize, rpc)      \
+		.globl	symbol;                     \
+		.align	2;                          \
+		.type	symbol,@function;           \
+		.ent	symbol,0;                   \
+symbol:		.frame	sp, framesize, rpc
+
+/*
+ * END - mark end of function
+ */
+#define	END(function)                       \
+		.end	function;		        	\
+		.size	function,.-function
+
+/*
+ * EXPORT - export definition of symbol
+ */
+#define EXPORT(symbol)						\
+		.globl	symbol;                     \
+symbol:
+
+/*
+ * FEXPORT - export definition of a function symbol
+ */
+#define FEXPORT(symbol)						\
+		.globl	symbol;						\
+		.type	symbol,@function;			\
+symbol:
+
+/*
+ * Global data declaration with size.
+ */
+#define EXPORTS(name,sz) 		\
+  	.globl name; 				\
+  	.type name,@object; 		\
+  	.size name,sz; 				\
+name:
+
+/*
+ * Weak data declaration with size.
+ */
+#define WEXPORT(name,sz) 		\
+  	.weakext name; 				\
+  	.type name,@object; 		\
+  	.size name,sz; 				\
+name:
+
+/*
+ * Global data reference with size.
+ */
+#define	IMPORT(name, size) 		\
+	.extern	name,size
+
+/*
+ * Global zeroed data.
+ */
+#define BSS(name,size) 			\
+  	.type name,@object; 		\
+	.comm	name,size
+
+/*
+ * Local zeroed data.
+ */
+#define LBSS(name,size) 		\
+  	.lcomm	name,size
+
+
+/*
+ * ABS - export absolute symbol
+ */
+#define	ABS(symbol,value)       \
+		.globl	symbol;         \
+symbol		=	value
+
+
+#define	TEXT(msg)               \
+		.pushsection .data;		\
+8:		.asciiz	msg;            \
+		.popsection;
+
+
+#define ENTRY(name) 			\
+  .globl name;					\
+  .align 2;						\
+  .ent name,0;					\
+  name##:
+
+/*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ */
+
+/*
+ * Size of a register
+ */
+#define SZREG	4
+
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#define REG_S		sw
+#define REG_L		lw
+#define REG_SUBU	subu
+#define REG_ADDU	addu
+
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#define INT_ADD		add
+#define INT_ADDU	addu
+#define INT_ADDI	addi
+#define INT_ADDIU	addiu
+#define INT_SUB		sub
+#define INT_SUBU	subu
+#define INT_L		lw
+#define INT_S		sw
+#define INT_SLL		sll
+#define INT_SLLV	sllv
+#define INT_SRL		srl
+#define INT_SRLV	srlv
+#define INT_SRA		sra
+#define INT_SRAV	srav
+
+
+
+/*
+ * How to add/sub/load/store/shift C long variables.
+ */
+#define LONG_ADD	add
+#define LONG_ADDU	addu
+#define LONG_ADDI	addi
+#define LONG_ADDIU	addiu
+#define LONG_SUB	sub
+#define LONG_SUBU	subu
+#define LONG_L		lw
+#define LONG_S		sw
+#define LONG_SLL	sll
+#define LONG_SLLV	sllv
+#define LONG_SRL	srl
+#define LONG_SRLV	srlv
+#define LONG_SRA	sra
+#define LONG_SRAV	srav
+
+#define LONG		.word
+#define LONGSIZE	4
+#define LONGMASK	3
+#define LONGLOG		2
+
+
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#define PTR_ADD		add
+#define PTR_ADDU	addu
+#define PTR_ADDI	addi
+#define PTR_ADDIU	addiu
+#define PTR_SUB		sub
+#define PTR_SUBU	subu
+#define PTR_L		lw
+#define PTR_S		sw
+#define PTR_LA		la
+#define PTR_SLL		sll
+#define PTR_SLLV	sllv
+#define PTR_SRL		srl
+#define PTR_SRLV	srlv
+#define PTR_SRA		sra
+#define PTR_SRAV	srav
+
+#define PTR_SCALESHIFT	2
+
+#define PTR			.word
+#define PTRSIZE		4
+#define PTRLOG		2
+
+
+/*
+ * Some cp0 registers were extended to 64bit for MIPS III.
+ */
+#define MFC0		mfc0
+#define MTC0		mtc0
+
+
+#define SSNOP		sll zero, zero, 1
+
+#endif /* end of __ASM_H__ */
diff --git a/bsp/x1000/cpu/common/exception.h b/bsp/x1000/cpu/common/exception.h
new file mode 100644
index 0000000000..2cb03d20e7
--- /dev/null
+++ b/bsp/x1000/cpu/common/exception.h
@@ -0,0 +1,166 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-17     swkyer       first version
+ */
+#ifndef __EXCEPTION_H__
+#define __EXCEPTION_H__
+
+
+/*
+ * important register numbers
+ */
+#define REG_EPC				37
+#define REG_FP				72
+#define REG_SP				29
+
+/*
+ * Stack layout for the GDB exception handler
+ * Derived from the stack layout described in asm-mips/stackframe.h
+ *
+ * The first PTRSIZE*6 bytes are argument save space for C subroutines.
+ */
+#define NUMREGS				90
+
+#define GDB_FR_REG0			(PTRSIZE*6)			/* 0 */
+#define GDB_FR_REG1			((GDB_FR_REG0) + LONGSIZE)	/* 1 */
+#define GDB_FR_REG2			((GDB_FR_REG1) + LONGSIZE)	/* 2 */
+#define GDB_FR_REG3			((GDB_FR_REG2) + LONGSIZE)	/* 3 */
+#define GDB_FR_REG4			((GDB_FR_REG3) + LONGSIZE)	/* 4 */
+#define GDB_FR_REG5			((GDB_FR_REG4) + LONGSIZE)	/* 5 */
+#define GDB_FR_REG6			((GDB_FR_REG5) + LONGSIZE)	/* 6 */
+#define GDB_FR_REG7			((GDB_FR_REG6) + LONGSIZE)	/* 7 */
+#define GDB_FR_REG8			((GDB_FR_REG7) + LONGSIZE)	/* 8 */
+#define GDB_FR_REG9	        ((GDB_FR_REG8) + LONGSIZE)	/* 9 */
+#define GDB_FR_REG10		((GDB_FR_REG9) + LONGSIZE)	/* 10 */
+#define GDB_FR_REG11		((GDB_FR_REG10) + LONGSIZE)	/* 11 */
+#define GDB_FR_REG12		((GDB_FR_REG11) + LONGSIZE)	/* 12 */
+#define GDB_FR_REG13		((GDB_FR_REG12) + LONGSIZE)	/* 13 */
+#define GDB_FR_REG14		((GDB_FR_REG13) + LONGSIZE)	/* 14 */
+#define GDB_FR_REG15		((GDB_FR_REG14) + LONGSIZE)	/* 15 */
+#define GDB_FR_REG16		((GDB_FR_REG15) + LONGSIZE)	/* 16 */
+#define GDB_FR_REG17		((GDB_FR_REG16) + LONGSIZE)	/* 17 */
+#define GDB_FR_REG18		((GDB_FR_REG17) + LONGSIZE)	/* 18 */
+#define GDB_FR_REG19		((GDB_FR_REG18) + LONGSIZE)	/* 19 */
+#define GDB_FR_REG20		((GDB_FR_REG19) + LONGSIZE)	/* 20 */
+#define GDB_FR_REG21		((GDB_FR_REG20) + LONGSIZE)	/* 21 */
+#define GDB_FR_REG22		((GDB_FR_REG21) + LONGSIZE)	/* 22 */
+#define GDB_FR_REG23		((GDB_FR_REG22) + LONGSIZE)	/* 23 */
+#define GDB_FR_REG24		((GDB_FR_REG23) + LONGSIZE)	/* 24 */
+#define GDB_FR_REG25		((GDB_FR_REG24) + LONGSIZE)	/* 25 */
+#define GDB_FR_REG26		((GDB_FR_REG25) + LONGSIZE)	/* 26 */
+#define GDB_FR_REG27		((GDB_FR_REG26) + LONGSIZE)	/* 27 */
+#define GDB_FR_REG28		((GDB_FR_REG27) + LONGSIZE)	/* 28 */
+#define GDB_FR_REG29		((GDB_FR_REG28) + LONGSIZE)	/* 29 */
+#define GDB_FR_REG30		((GDB_FR_REG29) + LONGSIZE)	/* 30 */
+#define GDB_FR_REG31		((GDB_FR_REG30) + LONGSIZE)	/* 31 */
+
+/*
+ * Saved special registers
+ */
+#define GDB_FR_STATUS		((GDB_FR_REG31) + LONGSIZE)	/* 32 */
+#define GDB_FR_LO			((GDB_FR_STATUS) + LONGSIZE)	/* 33 */
+#define GDB_FR_HI			((GDB_FR_LO) + LONGSIZE)	/* 34 */
+#define GDB_FR_BADVADDR		((GDB_FR_HI) + LONGSIZE)	/* 35 */
+#define GDB_FR_CAUSE		((GDB_FR_BADVADDR) + LONGSIZE)	/* 36 */
+#define GDB_FR_EPC			((GDB_FR_CAUSE) + LONGSIZE)	/* 37 */
+
+///*
+// * Saved floating point registers
+// */
+//#define GDB_FR_FPR0		((GDB_FR_EPC) + LONGSIZE)	/* 38 */
+//#define GDB_FR_FPR1		((GDB_FR_FPR0) + LONGSIZE)	/* 39 */
+//#define GDB_FR_FPR2		((GDB_FR_FPR1) + LONGSIZE)	/* 40 */
+//#define GDB_FR_FPR3		((GDB_FR_FPR2) + LONGSIZE)	/* 41 */
+//#define GDB_FR_FPR4		((GDB_FR_FPR3) + LONGSIZE)	/* 42 */
+//#define GDB_FR_FPR5		((GDB_FR_FPR4) + LONGSIZE)	/* 43 */
+//#define GDB_FR_FPR6		((GDB_FR_FPR5) + LONGSIZE)	/* 44 */
+//#define GDB_FR_FPR7		((GDB_FR_FPR6) + LONGSIZE)	/* 45 */
+//#define GDB_FR_FPR8		((GDB_FR_FPR7) + LONGSIZE)	/* 46 */
+//#define GDB_FR_FPR9		((GDB_FR_FPR8) + LONGSIZE)	/* 47 */
+//#define GDB_FR_FPR10		((GDB_FR_FPR9) + LONGSIZE)	/* 48 */
+//#define GDB_FR_FPR11		((GDB_FR_FPR10) + LONGSIZE)	/* 49 */
+//#define GDB_FR_FPR12		((GDB_FR_FPR11) + LONGSIZE)	/* 50 */
+//#define GDB_FR_FPR13		((GDB_FR_FPR12) + LONGSIZE)	/* 51 */
+//#define GDB_FR_FPR14		((GDB_FR_FPR13) + LONGSIZE)	/* 52 */
+//#define GDB_FR_FPR15		((GDB_FR_FPR14) + LONGSIZE)	/* 53 */
+//#define GDB_FR_FPR16		((GDB_FR_FPR15) + LONGSIZE)	/* 54 */
+//#define GDB_FR_FPR17		((GDB_FR_FPR16) + LONGSIZE)	/* 55 */
+//#define GDB_FR_FPR18		((GDB_FR_FPR17) + LONGSIZE)	/* 56 */
+//#define GDB_FR_FPR19		((GDB_FR_FPR18) + LONGSIZE)	/* 57 */
+//#define GDB_FR_FPR20		((GDB_FR_FPR19) + LONGSIZE)	/* 58 */
+//#define GDB_FR_FPR21		((GDB_FR_FPR20) + LONGSIZE)	/* 59 */
+//#define GDB_FR_FPR22		((GDB_FR_FPR21) + LONGSIZE)	/* 60 */
+//#define GDB_FR_FPR23		((GDB_FR_FPR22) + LONGSIZE)	/* 61 */
+//#define GDB_FR_FPR24		((GDB_FR_FPR23) + LONGSIZE)	/* 62 */
+//#define GDB_FR_FPR25		((GDB_FR_FPR24) + LONGSIZE)	/* 63 */
+//#define GDB_FR_FPR26		((GDB_FR_FPR25) + LONGSIZE)	/* 64 */
+//#define GDB_FR_FPR27		((GDB_FR_FPR26) + LONGSIZE)	/* 65 */
+//#define GDB_FR_FPR28		((GDB_FR_FPR27) + LONGSIZE)	/* 66 */
+//#define GDB_FR_FPR29		((GDB_FR_FPR28) + LONGSIZE)	/* 67 */
+//#define GDB_FR_FPR30		((GDB_FR_FPR29) + LONGSIZE)	/* 68 */
+//#define GDB_FR_FPR31		((GDB_FR_FPR30) + LONGSIZE)	/* 69 */
+//
+//#define GDB_FR_FSR		((GDB_FR_FPR31) + LONGSIZE)	/* 70 */
+//#define GDB_FR_FIR		((GDB_FR_FSR) + LONGSIZE)	/* 71 */
+//#define GDB_FR_FRP		((GDB_FR_FIR) + LONGSIZE)	/* 72 */
+//
+//#define GDB_FR_DUMMY		((GDB_FR_FRP) + LONGSIZE)	/* 73, unused ??? */
+//
+///*
+// * Again, CP0 registers
+// */
+//#define GDB_FR_CP0_INDEX	((GDB_FR_DUMMY) + LONGSIZE)	/* 74 */
+#define GDB_FR_FRP			((GDB_FR_EPC) + LONGSIZE)	/* 72 */
+#define GDB_FR_CP0_INDEX	((GDB_FR_FRP) + LONGSIZE)	/* 74 */
+
+#define GDB_FR_CP0_RANDOM	((GDB_FR_CP0_INDEX) + LONGSIZE)	/* 75 */
+#define GDB_FR_CP0_ENTRYLO0	((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
+#define GDB_FR_CP0_ENTRYLO1	((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
+#define GDB_FR_CP0_CONTEXT	((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
+#define GDB_FR_CP0_PAGEMASK	((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
+#define GDB_FR_CP0_WIRED	((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
+#define GDB_FR_CP0_REG7		((GDB_FR_CP0_WIRED) + LONGSIZE)	/* 81 */
+#define GDB_FR_CP0_REG8		((GDB_FR_CP0_REG7) + LONGSIZE)	/* 82 */
+#define GDB_FR_CP0_REG9		((GDB_FR_CP0_REG8) + LONGSIZE)	/* 83 */
+#define GDB_FR_CP0_ENTRYHI	((GDB_FR_CP0_REG9) + LONGSIZE)	/* 84 */
+#define GDB_FR_CP0_REG11	((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
+#define GDB_FR_CP0_REG12	((GDB_FR_CP0_REG11) + LONGSIZE)	/* 86 */
+#define GDB_FR_CP0_REG13	((GDB_FR_CP0_REG12) + LONGSIZE)	/* 87 */
+#define GDB_FR_CP0_REG14	((GDB_FR_CP0_REG13) + LONGSIZE)	/* 88 */
+#define GDB_FR_CP0_PRID		((GDB_FR_CP0_REG14) + LONGSIZE)	/* 89 */
+
+#define GDB_FR_SIZE			((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
+
+/*
+ * This is the same as above, but for the high-level
+ * part of the INT stub.
+ */
+typedef struct pt_regs_s
+{
+	/* Saved main processor registers. */
+	rt_base_t regs[32];
+	/* Saved special registers. */
+	rt_base_t cp0_status;
+	rt_base_t hi;
+	rt_base_t lo;
+	rt_base_t cp0_badvaddr;
+	rt_base_t cp0_cause;
+	rt_base_t cp0_epc;
+} pt_regs_t;
+
+typedef void (* exception_func_t)(pt_regs_t *regs);
+
+extern exception_func_t sys_exception_handlers[];
+exception_func_t rt_set_except_vector(int n, exception_func_t func);
+void install_default_execpt_handle(void);
+
+#endif /* end of __EXCEPTION_H__ */
diff --git a/bsp/x1000/cpu/common/mips.h b/bsp/x1000/cpu/common/mips.h
new file mode 100644
index 0000000000..a4bc74a050
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-07     Urey         first version
+ */
+
+#ifndef _COMMON_MIPS_H_
+#define _COMMON_MIPS_H_
+
+#include "mips_cfg.h"
+
+#include "mips_types.h"
+#include "mips_asm.h"
+#include "mips_def.h"
+#include "mips_regs.h"
+#include "mips_addrspace.h"
+#include "mips_cache.h"
+#include "mips_context.h"
+#include "mips_excpt.h"
+
+#endif /* _COMMON_MIPS_H_ */
diff --git a/bsp/x1000/cpu/common/mips.inc b/bsp/x1000/cpu/common/mips.inc
new file mode 100644
index 0000000000..a4cd55911e
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips.inc
@@ -0,0 +1,52 @@
+/*
+ * File      : mips.inc
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-17     sangwei      first version
+ */
+#ifndef __MIPS_INC__
+#define __MIPS_INC__
+
+#define zero    $0		/* wired zero */
+// #define at      $1
+#define v0      $2		/* return value */
+#define v1      $3
+#define a0      $4		/* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define t0      $8		/* caller saved */
+#define t1      $9
+#define t2      $10
+#define t3      $11
+#define t4      $12
+#define t5      $13
+#define t6      $14
+#define t7      $15
+#define s0      $16		/* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24		/* caller saved */
+#define t9      $25
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel scratch */
+#define k1      $27
+#define gp      $28     /* global pointer */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8		$30		/* same like fp! */
+#define ra      $31     /* return address */
+
+#endif /* end of __MIPS_INC__   */
diff --git a/bsp/x1000/cpu/common/mips_addrspace.h b/bsp/x1000/cpu/common/mips_addrspace.h
new file mode 100644
index 0000000000..3b82a4e371
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_addrspace.h
@@ -0,0 +1,207 @@
+/*
+ * File      : mips_addrspace.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��12��     Urey         the first version
+ */
+
+#ifndef _MIPS_ADDRSPACE_H_
+#define _MIPS_ADDRSPACE_H_
+
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ATYPE_
+#define _ATYPE32_
+#define _ATYPE64_
+#define _CONST64_(x)	x
+#else
+#define _ATYPE_		__PTRDIFF_TYPE__
+#define _ATYPE32_	int
+#define _ATYPE64_	__s64
+#ifdef CONFIG_64BIT
+#define _CONST64_(x)	x ## L
+#else
+#define _CONST64_(x)	x ## LL
+#endif
+#endif
+
+/*
+ *  32-bit MIPS address spaces
+ */
+#ifdef __ASSEMBLY__
+#define _ACAST32_
+#define _ACAST64_
+#else
+#define _ACAST32_		(_ATYPE_)(_ATYPE32_)	/* widen if necessary */
+#define _ACAST64_		(_ATYPE64_)		/* do _not_ narrow */
+#endif
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#define KSEGX(a)		((_ACAST32_ (a)) & 0xe0000000)
+
+/*
+ * Returns the physical address of a CKSEGx / XKPHYS address
+ */
+#define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a)		((_ACAST64_(a)) &			\
+				 _CONST64_(0x000000ffffffffff))
+
+#ifdef CONFIG_64BIT
+
+/*
+ * Memory segments (64bit kernel mode addresses)
+ * The compatibility segments use the full 64-bit sign extended value.  Note
+ * the R8000 doesn't have them so don't reference these in generic MIPS code.
+ */
+#define XKUSEG			_CONST64_(0x0000000000000000)
+#define XKSSEG			_CONST64_(0x4000000000000000)
+#define XKPHYS			_CONST64_(0x8000000000000000)
+#define XKSEG			_CONST64_(0xc000000000000000)
+#define CKSEG0			_CONST64_(0xffffffff80000000)
+#define CKSEG1			_CONST64_(0xffffffffa0000000)
+#define CKSSEG			_CONST64_(0xffffffffc0000000)
+#define CKSEG3			_CONST64_(0xffffffffe0000000)
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
+
+#else
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0BASE)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1BASE)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2BASE)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3BASE)
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0BASE)
+#define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1BASE)
+#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2BASE)
+#define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3BASE)
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
+ */
+//#define KUSEGBASE			0x00000000
+//#define KSEG0BASE			0x80000000
+//#define KSEG1BASE			0xa0000000
+//#define KSEG2BASE			0xc0000000
+//#define KSEG3BASE			0xe0000000
+
+#define CKUSEG			0x00000000
+#define CKSEG0			0x80000000
+#define CKSEG1			0xa0000000
+#define CKSEG2			0xc0000000
+#define CKSEG3			0xe0000000
+
+#endif
+
+/*
+ * Cache modes for XKPHYS address conversion macros
+ */
+#define K_CALG_COH_EXCL1_NOL2	0
+#define K_CALG_COH_SHRL1_NOL2	1
+#define K_CALG_UNCACHED		2
+#define K_CALG_NONCOHERENT	3
+#define K_CALG_COH_EXCL		4
+#define K_CALG_COH_SHAREABLE	5
+#define K_CALG_NOTUSED		6
+#define K_CALG_UNCACHED_ACCEL	7
+
+/*
+ * 64-bit address conversions
+ */
+#define PHYS_TO_XKSEG_UNCACHED(p)	PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a)		(_CONST64_(0x8000000000000000) | \
+					 (_CONST64_(cm) << 59) | (a))
+
+/*
+ * Returns the uncached address of a sdram address
+ */
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
+/* We use a 36 bit physical address map here and
+   cannot access physical memory directly from core */
+#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
+#else	/* !CONFIG_SOC_AU1X00 */
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
+#endif	/* CONFIG_SOC_AU1X00 */
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
+ * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
+ * R8000 implements most with its 48-bit physical address space.
+ */
+#define TO_PHYS_MASK	_CONST64_(0x07ffffffffffffff)	/* 2^^59 - 1 */
+
+#ifndef CONFIG_CPU_R8000
+
+/*
+ * The R8000 doesn't have the 32-bit compat spaces so we don't define them
+ * in order to catch bugs in the source code.
+ */
+
+#define COMPAT_K1BASE32		_CONST64_(0xffffffffa0000000)
+#define PHYS_TO_COMPATK1(x)	((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+
+#endif
+
+#define KDM_TO_PHYS(x)		(_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x)		(_ACAST64_ (x) | CAC_BASE)
+
+
+#ifndef __ASSEMBLY__
+/*
+ * Change virtual addresses to physical addresses and vv.
+ * These are trivial on the 1:1 Linux/MIPS mapping
+ */
+static inline phys_addr_t virt_to_phys(volatile void * address)
+{
+#ifndef CONFIG_64BIT
+	return CPHYSADDR(address);
+#else
+	return XPHYSADDR(address);
+#endif
+}
+
+static inline void * phys_to_virt(unsigned long address)
+{
+#ifndef CONFIG_64BIT
+	return (void *)KSEG0ADDR(address);
+#else
+	return (void *)CKSEG0ADDR(address);
+#endif
+}
+#endif
+
+
+#endif /* _MIPS_ADDRSPACE_H_ */
diff --git a/bsp/x1000/cpu/common/mips_asm.h b/bsp/x1000/cpu/common/mips_asm.h
new file mode 100644
index 0000000000..8f97e370ab
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_asm.h
@@ -0,0 +1,447 @@
+/*
+ * File      : mips_asm.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��7��     Urey         the first version
+ */
+
+#ifndef _MIPS_ASM_H_
+#define _MIPS_ASM_H_
+
+
+/* ********************************************************************* */
+/* Interface macro & data definition */
+
+#ifdef __ASSEMBLY__
+
+/******** ASSEMBLER SPECIFIC DEFINITIONS ********/
+
+#ifdef  __ghs__
+#define ALIGN(x) .##align (1 << (x))
+#else
+#define ALIGN(x) .##align (x)
+#endif
+
+#ifdef __ghs__
+#define SET_MIPS3()
+#define SET_MIPS0()
+#define SET_PUSH()
+#define SET_POP()
+#else
+#define SET_MIPS3() .##set mips3
+#define SET_MIPS0() .##set mips0
+#define SET_PUSH()  .##set push
+#define SET_POP()   .##set pop
+#endif
+
+/*  Different assemblers have different requirements for how to
+ *  indicate that the next section is bss :
+ *
+ *  Some use :   .bss
+ *  Others use : .section bss
+ *
+ *  We select which to use based on _BSS_OLD_, which may be defined
+ *  in makefile.
+ */
+#ifdef _BSS_OLD_
+#define BSS	.##section bss
+#else
+#define BSS	.##bss
+#endif
+
+#define LEAF(name)\
+  		.##text;\
+  		.##globl	name;\
+  		.##ent	name;\
+name:
+
+
+#define SLEAF(name)\
+  		.##text;\
+  		.##ent	name;\
+name:
+
+
+#ifdef __ghs__
+#define END(name)\
+  		.##end	name
+#else
+#define END(name)\
+  		.##size name,.-name;\
+  		.##end	name
+#endif
+
+
+#define EXTERN(name)
+
+#else
+
+#define U64 unsigned long long
+#define U32 unsigned int
+#define U16 unsigned short
+#define U8  unsigned char
+#define S64 signed long long
+#define S32 int
+#define S16 short int
+#define S8  signed char
+//#define bool U8
+
+#ifndef _SIZE_T_
+#define _SIZE_T_
+#ifdef __ghs__
+   typedef unsigned int size_t;
+#else
+   typedef unsigned long size_t;
+#endif
+#endif
+
+/* Sets the result on bPort */
+#define BIT_SET(bPort,bBitMask)        (bPort |= bBitMask)
+#define BIT_CLR(bPort,bBitMask)        (bPort &= ~bBitMask)
+
+/* Returns the result */
+#define GET_BIT_SET(bPort,bBitMask)    (bPort | bBitMask)
+#define GET_BIT_CLR(bPort,bBitMask)    (bPort & ~bBitMask)
+
+/* Returns 0 if the condition is False & a non-zero value if it is True */
+#define TEST_BIT_SET(bPort,bBitMask)   (bPort & bBitMask)
+#define TEST_BIT_CLR(bPort,bBitMask)   ((~bPort) & bBitMask)
+
+/* Split union definitions */
+typedef union tunSU16
+{
+        U16 hwHW;
+        struct tst2U8
+        {
+                U8 bB0;
+                U8 bB1;
+        }st2U8;
+}tunSU16;
+
+typedef union tunSU32
+{
+        U32 wW;
+        struct tst2U16
+        {
+                U16 hwHW0;
+                U16 hwHW1;
+        }st2U16;
+        struct tst4U8
+        {
+                U8 bB0;
+                U8 bB1;
+                U8 bB2;
+                U8 bB3;
+        }st4U8;
+}tunSU32;
+
+#endif /* #ifdef __ASSEMBLY__ */
+
+
+/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/
+
+
+#define  NO_ERR             0x00000000     /* operation completed successfully */
+#define  ERR                0xffffffff     /* operation completed not successfully */
+
+#define False 0
+#define True !False
+
+#ifndef NULL
+#define NULL		      	((void *)0)
+#endif//NULL
+
+#ifndef MIN
+#define MIN(x,y)           ((x) < (y) ? (x) : (y))
+#endif//MIN
+
+#ifndef MAX
+#define MAX(x,y)      		((x) > (y) ? (x) : (y))
+#endif//MAX
+
+#define MAXUINT(w)	(\
+		((w) == sizeof(U8))  ? 0xFFU :\
+		((w) == sizeof(U16)) ? 0xFFFFU :\
+		((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\
+		        )
+
+#define MAXINT(w)	(\
+		((w) == sizeof(S8))  ? 0x7F :\
+		((w) == sizeof(S16)) ? 0x7FFF :\
+		((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\
+		        )
+
+#define MSK(n)			  ((1 << (n)) - 1)
+
+#define KUSEG_MSK		  0x80000000
+#define KSEG_MSK		  0xE0000000
+
+#define KUSEGBASE		  0x00000000
+#define KSEG0BASE		  0x80000000
+#define KSEG1BASE		  0xA0000000
+#define KSSEGBASE		  0xC0000000
+#define KSEG3BASE		  0xE0000000
+
+/*  Below macros perform the following functions :
+ *
+ *  KSEG0    : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0.
+ *  KSEG1    : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1.
+ *  PHYS     : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address.
+ *  KSSEG    : Not relevant for converting, but used for determining range.
+ *  KSEG3    : Not relevant for converting, but used for determining range.
+ *  KUSEG    : Not relevant for converting, but used for determining range.
+ *  KSEG0A   : Same as KSEG0 but operates on register rather than constant.
+ *  KSEG1A   : Same as KSEG1 but operates on register rather than constant.
+ *  PHYSA    : Same as PHYS  but operates on register rather than constant.
+ *  CACHED   : Alias for KSEG0 macro .
+ *	       (Note that KSEG0 cache attribute is determined by K0
+ *	       field of Config register, but this is typically cached).
+ *  UNCACHED : Alias for KSEG1 macro .
+ */
+#ifdef __ASSEMBLY__
+#define KSEG0(addr)     (((addr) & ~KSEG_MSK)  | KSEG0BASE)
+#define KSEG1(addr)     (((addr) & ~KSEG_MSK)  | KSEG1BASE)
+#define KSSEG(addr)     (((addr) & ~KSEG_MSK)  | KSSEGBASE)
+#define KSEG3(addr)     (((addr) & ~KSEG_MSK)  | KSEG3BASE)
+#define KUSEG(addr)     (((addr) & ~KUSEG_MSK) | KUSEGBASE)
+#define PHYS(addr)      ( (addr) & ~KSEG_MSK)
+#define KSEG0A(reg) 	and reg, ~KSEG_MSK; or reg, KSEG0BASE
+#define KSEG1A(reg) 	and reg, ~KSEG_MSK; or reg, KSEG1BASE
+#define PHYSA(reg)	and reg, ~KSEG_MSK
+#else
+#define KSEG0(addr)     (((U32)(addr) & ~KSEG_MSK)  | KSEG0BASE)
+#define KSEG1(addr)     (((U32)(addr) & ~KSEG_MSK)  | KSEG1BASE)
+#define KSSEG(addr)	(((U32)(addr) & ~KSEG_MSK)  | KSSEGBASE)
+#define KSEG3(addr)	(((U32)(addr) & ~KSEG_MSK)  | KSEG3BASE)
+#define KUSEG(addr)	(((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE)
+#define PHYS(addr) 	((U32)(addr)  & ~KSEG_MSK)
+#endif
+
+#define CACHED(addr)	KSEG0(addr)
+#define UNCACHED(addr)	KSEG1(addr)
+
+
+#ifdef __ASSEMBLY__
+/* Macroes to access variables at constant addresses
+ * Compensates for signed 16 bit displacement
+ * Typical use:	li	a0, HIKSEG1(ATLAS_ASCIIWORD)
+ *		sw	v1, LO_OFFS(ATLAS_ASCIIWORD)(a0)
+ */
+#define HIKSEG0(addr)	((KSEG0(addr) + 0x8000) & 0xffff0000)
+#define HIKSEG1(addr)	((KSEG1(addr) + 0x8000) & 0xffff0000)
+#define HI_PART(addr)	(((addr) + 0x8000) & 0xffff0000)
+#define LO_OFFS(addr)	((addr) & 0xffff)
+#endif
+
+
+/* Most/Least significant 32 bit from 64 bit double word */
+#define HI32(data64)		  ((U32)(data64 >> 32))
+#define LO32(data64)		  ((U32)(data64 & 0xFFFFFFFF))
+
+#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY)))
+#define REG8( addr )		  (*(volatile U8 *) (addr))
+#define REG16( addr )		  (*(volatile U16 *)(addr))
+#define REG32( addr )		  (*(volatile U32 *)(addr))
+#define REG64( addr )		  (*(volatile U64 *)(addr))
+#endif
+
+/* Register field mapping */
+#define REGFIELD(reg, rfld)	  (((reg) & rfld##_MSK) >> rfld##_SHF)
+
+/* absolute register address, access 					*/
+#define	REGA(addr)		  REG32(addr)
+
+/* physical register address, access: base address + offsett		*/
+#define	REGP(base,phys)	REG32( (U32)(base) + (phys) )
+
+/* relative register address, access: base address + offsett		*/
+#define REG(base,offs)  REG32( (U32)(base) + offs##_##OFS )
+
+/* relative register address, access: base address + offsett		*/
+#define REG_8(base,offs)  REG8( (U32)(base) + offs##_##OFS )
+
+/* relative register address, access: base address + offsett		*/
+#define REG_16(base,offs)  REG16( (U32)(base) + offs##_##OFS )
+
+/* relative register address, access: base address + offsett		*/
+#define REG_64(base,offs)  REG64( (U32)(base) + offs##_##OFS )
+
+/**************************************
+ * Macroes not used by YAMON any more
+ * (kept for backwards compatibility)
+ */
+/* register read field							*/
+#define	REGARD(addr,fld)	((REGA(addr) & addr##_##fld##_##MSK) 	\
+			 >> addr##_##fld##_##SHF)
+
+/* register write numeric field value					*/
+#define	REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
+				 | ((intval) << addr##_##fld##_##SHF))
+
+/* register write enumerated field value				*/
+#define	REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
+			| ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF))
+
+
+/* Examples:
+ *
+ *	exccode = REGARD(CPU_CAUSE,EXC);
+ *
+ *	REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17)
+ *			 | REGAWRE(OSG_CONTROL,DTYPE,PC1);
+ */
+
+
+/* register read field							*/
+#define	REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) 	\
+			 >> offs##_##fld##_##SHF)
+
+/* register write numeric field value					*/
+#define	REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\
+                                 | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK))
+
+/* register write enumerated field value				*/
+#define	REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\
+				| ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF))
+
+
+/* physical register read field							*/
+#define	REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) 	\
+			 >> phys##_##fld##_##SHF)
+
+/* physical register write numeric field value					*/
+#define	REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\
+				 | ((intval) << phys##_##fld##_##SHF))
+
+/* physical register write enumerated field value				*/
+#define	REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\
+				| ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF))
+/*
+ * End of macroes not used by YAMON any more
+ *********************************************/
+
+/* Endian related macros */
+
+#define SWAP_BYTEADDR32( addr )   ( (addr) ^ 0x3 )
+#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 )
+
+/* Set byte address to little endian format */
+#ifdef EL
+#define SWAP_BYTEADDR_EL(addr) 	  addr
+#else
+#define SWAP_BYTEADDR_EL(addr)    SWAP_BYTEADDR32( addr )
+#endif
+
+/* Set byte address to big endian format */
+#ifdef EB
+#define SWAP_BYTEADDR_EB(addr) 	  addr
+#else
+#define SWAP_BYTEADDR_EB(addr)    SWAP_BYTEADDR32( addr )
+#endif
+
+/* Set U16 address to little endian format */
+#ifdef EL
+#define SWAP_U16ADDR_EL(addr)  addr
+#else
+#define SWAP_U16ADDR_EL(addr)  SWAP_U16ADDR32( addr )
+#endif
+
+/* Set U16 address to big endian format */
+#ifdef EB
+#define SWAP_U16ADDR_EB(addr)  addr
+#else
+#define SWAP_U16ADDR_EB(addr)  SWAP_U16ADDR32( addr )
+#endif
+
+#ifdef EL
+#define REGW32LE(addr, data)      REG32(addr) = (data)
+#define REGR32LE(addr, data)      (data)      = REG32(addr)
+#else
+#define REGW32LE(addr, data)      REG32(addr) = SWAPEND32(data)
+#define REGR32LE(addr, data)      (data)      = REG32(addr), (data) = SWAPEND32(data)
+#endif
+
+/* Set of 'LE'-macros, convert by BE: */
+#ifdef EL
+#define CPU_TO_LE32( value ) (value)
+#define LE32_TO_CPU( value ) (value)
+
+#define CPU_TO_LE16( value ) (value)
+#define LE16_TO_CPU( value ) (value)
+#else
+#define CPU_TO_LE32( value ) ( (                ((U32)value)  << 24) |   \
+                               ((0x0000FF00UL & ((U32)value)) <<  8) |   \
+                               ((0x00FF0000UL & ((U32)value)) >>  8) |   \
+                               (                ((U32)value)  >> 24)   )
+#define LE32_TO_CPU( value ) CPU_TO_LE32( value )
+
+#define CPU_TO_LE16( value ) ( ((U16)(((U16)value)  << 8)) |   \
+                               ((U16)(((U16)value)  >> 8))   )
+#define LE16_TO_CPU( value ) CPU_TO_LE16( value )
+#endif
+
+/* Set of 'BE'-macros, convert by LE: */
+#ifdef EB
+#define CPU_TO_BE32( value ) (value)
+#define BE32_TO_CPU( value ) (value)
+
+#define CPU_TO_BE16( value ) (value)
+#define BE16_TO_CPU( value ) (value)
+#else
+#define CPU_TO_BE32( value ) ( (                ((U32)value)  << 24) |   \
+                               ((0x0000FF00UL & ((U32)value)) <<  8) |   \
+                               ((0x00FF0000UL & ((U32)value)) >>  8) |   \
+                               (                ((U32)value)  >> 24)   )
+#define BE32_TO_CPU( value ) CPU_TO_BE32( value )
+
+#define CPU_TO_BE16( value ) ( ((U16)(((U16)value)  << 8)) |   \
+                               ((U16)(((U16)value)  >> 8))   )
+#define BE16_TO_CPU( value ) CPU_TO_BE16( value )
+#endif
+
+
+/* Control characters */
+#define CTRL_A          ('A'-0x40)
+#define CTRL_B          ('B'-0x40)
+#define CTRL_C          ('C'-0x40)
+#define CTRL_D          ('D'-0x40)
+#define CTRL_E          ('E'-0x40)
+#define CTRL_F          ('F'-0x40)
+#define CTRL_H          ('H'-0x40)
+#define CTRL_K          ('K'-0x40)
+#define CTRL_N          ('N'-0x40)
+#define CTRL_P          ('P'-0x40)
+#define CTRL_U          ('U'-0x40)
+#define BACKSPACE       0x08
+#define DEL             0x7F
+#define TAB             0x09
+#define CR              0x0D /* Enter Key */
+#define LF              0x0A
+#define ESC             0x1B
+#define SP              0x20
+#define CSI             0x9B
+
+
+/* DEF2STR(x) converts #define symbol to string */
+#define DEF2STR1(x) #x
+#define DEF2STR(x)  DEF2STR1(x)
+
+
+#endif /* _MIPS_ASM_H_ */
diff --git a/bsp/x1000/cpu/common/mips_cache.c b/bsp/x1000/cpu/common/mips_cache.c
new file mode 100644
index 0000000000..1c979b7106
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_cache.c
@@ -0,0 +1,153 @@
+/*
+ * File      : mips_cache.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��7��     Urey         the first version
+ */
+
+#include <rtthread.h>
+#include "mips.h"
+
+extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
+void r4k_cache_init(void)
+{
+//	cache_init(dcache_size, cpu_dcache_line_size);
+}
+
+void r4k_cache_flush_all(void)
+{
+    blast_dcache16();
+    blast_icache16();
+}
+
+
+void r4k_icache_flush_all(void)
+{
+    blast_icache16();
+}
+
+void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
+{
+	rt_ubase_t end, a;
+
+    if (size > g_mips_core.icache_size)
+    {
+        blast_icache16();
+    }
+    else
+    {
+    	rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
+
+        a = addr & ~(ic_lsize - 1);
+        end = ((addr + size) - 1) & ~(ic_lsize - 1);
+        while (1)
+        {
+            flush_icache_line(a);
+            if (a == end)
+                break;
+            a += ic_lsize;
+        }
+    }
+}
+
+void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
+{
+	rt_ubase_t end, a;
+	rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
+
+    a = addr & ~(ic_lsize - 1);
+    end = ((addr + size) - 1) & ~(ic_lsize - 1);
+    while (1)
+    {
+        lock_icache_line(a);
+        if (a == end)
+            break;
+        a += ic_lsize;
+    }
+}
+
+void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
+{
+	rt_ubase_t end, a;
+    rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
+
+    a = addr & ~(dc_lsize - 1);
+    end = ((addr + size) - 1) & ~(dc_lsize - 1);
+    while (1)
+    {
+        invalidate_dcache_line(a);
+        if (a == end)
+            break;
+        a += dc_lsize;
+    }
+}
+
+void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
+{
+	rt_ubase_t end, a;
+
+    if (size >= g_mips_core.dcache_size)
+    {
+        blast_dcache16();
+    }
+    else
+    {
+    	rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
+
+        a = addr & ~(dc_lsize - 1);
+        end = ((addr + size) - 1) & ~(dc_lsize - 1);
+        while (1)
+        {
+            flush_dcache_line(a);
+            if (a == end)
+                break;
+            a += dc_lsize;
+        }
+    }
+}
+
+#define dma_cache_wback_inv(start,size) \
+    do { (void) (start); (void) (size); } while (0)
+#define dma_cache_wback(start,size) \
+    do { (void) (start); (void) (size); } while (0)
+#define dma_cache_inv(start,size)   \
+    do { (void) (start); (void) (size); } while (0)
+
+
+void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction)
+{
+    switch (direction)
+    {
+        case DMA_TO_DEVICE:
+            r4k_dcache_wback_inv(addr, size);
+        break;
+
+        case DMA_FROM_DEVICE:
+            r4k_dcache_wback_inv(addr, size);
+        break;
+
+        case DMA_BIDIRECTIONAL:
+            dma_cache_wback_inv(addr, size);
+        break;
+        default:
+            RT_ASSERT(0) ;
+    }
+}
+
diff --git a/bsp/x1000/cpu/common/mips_cache.h b/bsp/x1000/cpu/common/mips_cache.h
new file mode 100644
index 0000000000..a947041073
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_cache.h
@@ -0,0 +1,234 @@
+/*
+ * File      : mips_cache.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��10��     Urey         the first version
+ */
+
+#ifndef _MIPS_CACHE_H_
+#define _MIPS_CACHE_H_
+
+#ifndef __ASSEMBLER__
+#include <rtdef.h>
+#include <mips_cfg.h>
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define INDEX_INVALIDATE_I      0x00
+#define INDEX_WRITEBACK_INV_D   0x01
+#define INDEX_LOAD_TAG_I        0x04
+#define INDEX_LOAD_TAG_D        0x05
+#define INDEX_STORE_TAG_I       0x08
+#define INDEX_STORE_TAG_D       0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define HIT_INVALIDATE_I        0x00
+#else
+#define HIT_INVALIDATE_I        0x10
+#endif
+#define HIT_INVALIDATE_D        0x11
+#define HIT_WRITEBACK_INV_D     0x15
+
+/*
+ *The lock state is cleared by executing an Index
+Invalidate, Index Writeback Invalidate, Hit
+Invalidate, or Hit Writeback Invalidate
+operation to the locked line, or via an Index
+Store Tag operation with the lock bit reset in
+the TagLo register.
+ */
+#define FETCH_AND_LOCK_I        0x1c
+#define FETCH_AND_LOCK_D        0x1d
+
+
+enum dma_data_direction
+{
+    DMA_BIDIRECTIONAL = 0,
+    DMA_TO_DEVICE = 1,
+    DMA_FROM_DEVICE = 2,
+    DMA_NONE = 3,
+};
+
+/*
+ * R4000-specific cacheops
+ */
+#define CREATE_DIRTY_EXCL_D     0x0d
+#define FILL                    0x14
+#define HIT_WRITEBACK_I         0x18
+#define HIT_WRITEBACK_D         0x19
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define INDEX_INVALIDATE_SI     0x02
+#define INDEX_WRITEBACK_INV_SD  0x03
+#define INDEX_LOAD_TAG_SI       0x06
+#define INDEX_LOAD_TAG_SD       0x07
+#define INDEX_STORE_TAG_SI      0x0A
+#define INDEX_STORE_TAG_SD      0x0B
+#define CREATE_DIRTY_EXCL_SD    0x0f
+#define HIT_INVALIDATE_SI       0x12
+#define HIT_INVALIDATE_SD       0x13
+#define HIT_WRITEBACK_INV_SD    0x17
+#define HIT_WRITEBACK_SD        0x1b
+#define HIT_SET_VIRTUAL_SI      0x1e
+#define HIT_SET_VIRTUAL_SD      0x1f
+
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_PAGE_INVALIDATE_S   0x17
+
+/*
+ * RM7000-specific cacheops
+ */
+#define PAGE_INVALIDATE_T       0x16
+
+/*
+ * R10000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define INDEX_WRITEBACK_INV_S   0x03
+#define INDEX_LOAD_TAG_S        0x07
+#define INDEX_STORE_TAG_S       0x0B
+#define HIT_INVALIDATE_S        0x13
+#define CACHE_BARRIER           0x14
+#define HIT_WRITEBACK_INV_S     0x17
+#define INDEX_LOAD_DATA_I       0x18
+#define INDEX_LOAD_DATA_D       0x19
+#define INDEX_LOAD_DATA_S       0x1b
+#define INDEX_STORE_DATA_I      0x1c
+#define INDEX_STORE_DATA_D      0x1d
+#define INDEX_STORE_DATA_S      0x1f
+
+#define cache_op(op, addr)		    \
+    __asm__ __volatile__(        \
+        ".set   push\n"             \
+        ".set   noreorder\n"        \
+        ".set   mips3\n"            \
+        "cache  %0, %1\n"           \
+        ".set   pop\n"              \
+        :                           \
+        : "i" (op), "R" (*(unsigned char *)(addr)))
+
+#define cache16_unroll32(base, op)					\
+	__asm__ __volatile__(						\
+	"	.set noreorder					\n"	\
+	"	.set mips3					\n"	\
+	"	cache %1, 0x000(%0); cache %1, 0x010(%0)	\n"	\
+	"	cache %1, 0x020(%0); cache %1, 0x030(%0)	\n"	\
+	"	cache %1, 0x040(%0); cache %1, 0x050(%0)	\n"	\
+	"	cache %1, 0x060(%0); cache %1, 0x070(%0)	\n"	\
+	"	cache %1, 0x080(%0); cache %1, 0x090(%0)	\n"	\
+	"	cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)	\n"	\
+	"	cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)	\n"	\
+	"	cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)	\n"	\
+	"	cache %1, 0x100(%0); cache %1, 0x110(%0)	\n"	\
+	"	cache %1, 0x120(%0); cache %1, 0x130(%0)	\n"	\
+	"	cache %1, 0x140(%0); cache %1, 0x150(%0)	\n"	\
+	"	cache %1, 0x160(%0); cache %1, 0x170(%0)	\n"	\
+	"	cache %1, 0x180(%0); cache %1, 0x190(%0)	\n"	\
+	"	cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)	\n"	\
+	"	cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)	\n"	\
+	"	cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)	\n"	\
+	"	.set mips0					\n"	\
+	"	.set reorder					\n"	\
+		:							\
+		: "r" (base),						\
+		  "i" (op));
+
+
+static inline void flush_icache_line_indexed(rt_ubase_t addr)
+{
+	cache_op(INDEX_INVALIDATE_I, addr);
+}
+
+static inline void flush_dcache_line_indexed(rt_ubase_t addr)
+{
+	cache_op(INDEX_WRITEBACK_INV_D, addr);
+}
+
+static inline void flush_icache_line(rt_ubase_t addr)
+{
+	cache_op(HIT_INVALIDATE_I, addr);
+}
+
+static inline void lock_icache_line(rt_ubase_t addr)
+{
+	cache_op(FETCH_AND_LOCK_I, addr);
+}
+
+static inline void lock_dcache_line(rt_ubase_t addr)
+{
+	cache_op(FETCH_AND_LOCK_D, addr);
+}
+
+static inline void flush_dcache_line(rt_ubase_t addr)
+{
+	cache_op(HIT_WRITEBACK_INV_D, addr);
+}
+
+static inline void invalidate_dcache_line(rt_ubase_t addr)
+{
+	cache_op(HIT_INVALIDATE_D, addr);
+}
+static inline void blast_dcache16(void)
+{
+	rt_ubase_t start = KSEG0BASE;
+	rt_ubase_t end = start + g_mips_core.dcache_size;
+	rt_ubase_t addr;
+
+	for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
+		cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
+}
+
+static inline void inv_dcache16(void)
+{
+	rt_ubase_t start = KSEG0BASE;
+	rt_ubase_t end = start + g_mips_core.dcache_size;
+	rt_ubase_t addr;
+
+	for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
+		cache16_unroll32(addr, HIT_INVALIDATE_D);
+}
+
+static inline void blast_icache16(void)
+{
+	rt_ubase_t start = KSEG0BASE;
+	rt_ubase_t end = start + g_mips_core.icache_size;
+	rt_ubase_t addr;
+
+	for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
+		cache16_unroll32(addr, INDEX_INVALIDATE_I);
+}
+
+void r4k_cache_init(void);
+void r4k_cache_flush_all(void);
+void r4k_icache_flush_all(void);
+void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
+void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
+void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
+void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
+void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction);
+#endif
+
+#endif /* _MIPS_CACHE_H_ */
diff --git a/bsp/x1000/cpu/common/mips_cfg.h b/bsp/x1000/cpu/common/mips_cfg.h
new file mode 100644
index 0000000000..3f0575d65a
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_cfg.h
@@ -0,0 +1,48 @@
+/*
+ * File      : mips_cfg.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��10��     Urey         the first version
+ */
+
+#ifndef _MIPS_CFG_H_
+#define _MIPS_CFG_H_
+
+#ifndef __ASSEMBLY__
+#include <stdint.h>
+typedef struct mips32_core_cfg
+{
+    uint16_t icache_line_size;
+//    uint16_t icache_lines_per_way;
+//    uint16_t icache_ways;
+    uint16_t icache_size;
+    uint16_t dcache_line_size;
+//    uint16_t dcache_lines_per_way;
+//    uint16_t dcache_ways;
+    uint16_t dcache_size;
+
+    uint16_t max_tlb_entries;	/* number of tlb entry */
+} mips32_core_cfg_t;
+
+extern mips32_core_cfg_t g_mips_core;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _MIPS_CFG_H_ */
diff --git a/bsp/x1000/cpu/common/mips_context.h b/bsp/x1000/cpu/common/mips_context.h
new file mode 100644
index 0000000000..60d573784d
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_context.h
@@ -0,0 +1,280 @@
+/*
+ * File      : mips_context_asm.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��7��     Urey         the first version
+ */
+
+#ifndef _MIPS_CONTEXT_ASM_H_
+#define _MIPS_CONTEXT_ASM_H_
+
+#define CONTEXT_SIZE	( STK_CTX_SIZE + FPU_ADJ )
+#ifdef __mips_hard_float
+#define FPU_ADJ			(32 * 4 + 8)		/* FP0-FP31 + CP1_STATUS */
+#define FPU_CTX			( CONTEXT_SIZE - FPU_ADJ )
+#else
+#define FPU_ADJ			0
+#endif
+
+
+
+#ifdef __ASSEMBLY__
+
+#ifdef __mips_hard_float
+.global _fpctx_save
+.global _fpctx_load
+#endif
+
+.macro SAVE_CONTEXT
+	.set    push
+	.set    noat
+	.set    noreorder
+	.set    volatile
+
+	//save SP
+	move	k1, 	sp
+	move	k0, 	sp
+	subu 	sp, 	k1, 	CONTEXT_SIZE
+	sw		k0, 	(29 * 4)(sp)
+
+	//save REG
+	sw		$0, 	( 0 * 4)(sp)
+	sw		$1, 	( 1 * 4)(sp)
+	sw		$2, 	( 2 * 4)(sp)
+	sw		$3, 	( 3 * 4)(sp)
+	sw		$4, 	( 4 * 4)(sp)
+	sw		$5, 	( 5 * 4)(sp)
+	sw		$6, 	( 6 * 4)(sp)
+	sw		$7, 	( 7 * 4)(sp)
+	sw		$8,     ( 8 * 4)(sp)
+	sw		$9,     ( 9 * 4)(sp)
+	sw		$10,    (10 * 4)(sp)
+	sw		$11,    (11 * 4)(sp)
+	sw		$12,    (12 * 4)(sp)
+	sw		$13,    (13 * 4)(sp)
+	sw		$14,    (14 * 4)(sp)
+	sw		$15,    (15 * 4)(sp)
+	sw		$16,    (16 * 4)(sp)
+	sw		$17,    (17 * 4)(sp)
+	sw		$18,    (18 * 4)(sp)
+	sw		$19,    (19 * 4)(sp)
+	sw		$20,    (20 * 4)(sp)
+	sw		$21,    (21 * 4)(sp)
+	sw		$22,    (22 * 4)(sp)
+	sw		$23,    (23 * 4)(sp)
+	sw		$24,    (24 * 4)(sp)
+	sw		$25, 	(25 * 4)(sp)
+	/* K0 K1 */
+	sw		$28, 	(28 * 4)(sp)
+	/* SP */
+	sw		$30,    (30 * 4)(sp)
+	sw		$31, 	(31 * 4)(sp)
+
+	/* STATUS CAUSE EPC.... */
+	mfc0	$2, 	CP0_STATUS
+	sw		$2, 	STK_OFFSET_SR(sp)
+
+	mfc0	$2, 	CP0_CAUSE
+	sw		$2, 	STK_OFFSET_CAUSE(sp)
+
+	mfc0	$2, 	CP0_BADVADDR
+	sw		$2, 	STK_OFFSET_BADVADDR(sp)
+
+	MFC0	$2, 	CP0_EPC
+	sw		$2, 	STK_OFFSET_EPC(sp)
+
+	mfhi	$2
+	sw		$2,     STK_OFFSET_HI(sp)
+
+	mflo	$2
+	sw		$2,     STK_OFFSET_LO(sp)
+#ifdef __mips_hard_float
+	add		a0,		sp,STK_CTX_SIZE
+
+    mfc0 	t0, 	CP0_STATUS
+    .set	push
+    .set	at
+    or      t0,   	M_StatusCU1
+    .set 	push
+    mtc0 	t0, 	CP0_STATUS
+
+    cfc1 	t0,  	CP1_STATUS
+    sw      t0   ,  0x00(a0)
+	swc1    $f0,(0x04 *  1)(a0)
+	swc1    $f1,(0x04 *  2)(a0)
+	swc1    $f2,(0x04 *  3)(a0)
+	swc1    $f3,(0x04 *  4)(a0)
+	swc1    $f4,(0x04 *  5)(a0)
+	swc1    $f5,(0x04 *  6)(a0)
+	swc1    $f6,(0x04 *  7)(a0)
+	swc1    $f7,(0x04 *  8)(a0)
+	swc1    $f8,(0x04 *  9)(a0)
+	swc1    $f9,(0x04 * 10)(a0)
+	swc1   $f10,(0x04 * 11)(a0)
+	swc1   $f11,(0x04 * 12)(a0)
+	swc1   $f12,(0x04 * 13)(a0)
+	swc1   $f13,(0x04 * 14)(a0)
+	swc1   $f14,(0x04 * 15)(a0)
+	swc1   $f15,(0x04 * 16)(a0)
+	swc1   $f16,(0x04 * 17)(a0)
+	swc1   $f17,(0x04 * 18)(a0)
+	swc1   $f18,(0x04 * 19)(a0)
+	swc1   $f19,(0x04 * 20)(a0)
+	swc1   $f20,(0x04 * 21)(a0)
+	swc1   $f21,(0x04 * 22)(a0)
+	swc1   $f22,(0x04 * 23)(a0)
+	swc1   $f23,(0x04 * 24)(a0)
+	swc1   $f24,(0x04 * 25)(a0)
+	swc1   $f25,(0x04 * 26)(a0)
+	swc1   $f26,(0x04 * 27)(a0)
+	swc1   $f27,(0x04 * 28)(a0)
+	swc1   $f28,(0x04 * 29)(a0)
+	swc1   $f29,(0x04 * 30)(a0)
+	swc1   $f30,(0x04 * 31)(a0)
+	swc1   $f31,(0x04 * 32)(a0)
+
+	nop
+#endif
+
+	//restore a0
+	lw		a0,		(REG_A0 * 4)(sp)
+
+	.set	pop
+.endm
+
+
+.macro RESTORE_CONTEXT
+	.set    push
+	.set    noat
+	.set    noreorder
+	.set    volatile
+
+#ifdef __mips_hard_float
+	add		a0,	sp,STK_CTX_SIZE
+
+    mfc0 	t0, CP0_STATUS
+    .set	push
+    .set	at
+    or      t0, M_StatusCU1
+    .set	noat
+    mtc0	t0, CP0_STATUS
+
+    lw      t0   ,   0x00(a0)
+	lwc1    $f0,(0x04 *  1)(a0)
+	lwc1    $f1,(0x04 *  2)(a0)
+	lwc1    $f2,(0x04 *  3)(a0)
+	lwc1    $f3,(0x04 *  4)(a0)
+	lwc1    $f4,(0x04 *  5)(a0)
+	lwc1    $f5,(0x04 *  6)(a0)
+	lwc1    $f6,(0x04 *  7)(a0)
+	lwc1    $f7,(0x04 *  8)(a0)
+	lwc1    $f8,(0x04 *  9)(a0)
+	lwc1    $f9,(0x04 * 10)(a0)
+	lwc1   $f10,(0x04 * 11)(a0)
+	lwc1   $f11,(0x04 * 12)(a0)
+	lwc1   $f12,(0x04 * 13)(a0)
+	lwc1   $f13,(0x04 * 14)(a0)
+	lwc1   $f14,(0x04 * 15)(a0)
+	lwc1   $f15,(0x04 * 16)(a0)
+	lwc1   $f16,(0x04 * 17)(a0)
+	lwc1   $f17,(0x04 * 18)(a0)
+	lwc1   $f18,(0x04 * 19)(a0)
+	lwc1   $f19,(0x04 * 20)(a0)
+	lwc1   $f20,(0x04 * 21)(a0)
+	lwc1   $f21,(0x04 * 22)(a0)
+	lwc1   $f22,(0x04 * 23)(a0)
+	lwc1   $f23,(0x04 * 24)(a0)
+	lwc1   $f24,(0x04 * 25)(a0)
+	lwc1   $f25,(0x04 * 26)(a0)
+	lwc1   $f26,(0x04 * 27)(a0)
+	lwc1   $f27,(0x04 * 28)(a0)
+	lwc1   $f28,(0x04 * 29)(a0)
+	lwc1   $f29,(0x04 * 30)(a0)
+	lwc1   $f30,(0x04 * 31)(a0)
+	lwc1   $f31,(0x04 * 32)(a0)
+    ctc1 	t0,     CP1_STATUS                                            ;/*  restore fpp status reg      */
+
+	nop
+#endif
+
+	/* ͨ�üĴ��� */
+	/* ZERO */
+	lw		$1,  	( 1 * 4)(sp)
+	/* V0   */
+	lw		$3,  	( 3 * 4)(sp)
+	lw		$4,  	( 4 * 4)(sp)
+	lw		$5,  	( 5 * 4)(sp)
+	lw		$6,  	( 6 * 4)(sp)
+	lw		$7,  	( 7 * 4)(sp)
+	lw		$8, 	( 8 * 4)(sp)
+	lw		$9, 	( 9 * 4)(sp)
+	lw		$10,    (10 * 4)(sp)
+	lw		$11,    (11 * 4)(sp)
+	lw		$12,    (12 * 4)(sp)
+	lw		$13,    (13 * 4)(sp)
+	lw		$14,    (14 * 4)(sp)
+	lw		$15,    (15 * 4)(sp)
+	lw		$16,    (16 * 4)(sp)
+	lw		$17,    (17 * 4)(sp)
+	lw		$18,    (18 * 4)(sp)
+	lw		$19,    (19 * 4)(sp)
+	lw		$20,    (20 * 4)(sp)
+	lw		$21,    (21 * 4)(sp)
+	lw		$22,    (22 * 4)(sp)
+	lw		$23, 	(23 * 4)(sp)
+	lw		$24, 	(24 * 4)(sp)
+	lw		$25, 	(25 * 4)(sp)
+	lw		$26, 	(26 * 4)(sp)
+	lw		$27, 	(27 * 4)(sp)
+	lw		$28, 	(28 * 4)(sp)
+	/* SP */
+	lw		$30, 	(30 * 4)(sp)
+	lw		$31, 	(31 * 4)(sp)
+
+
+	/* STATUS CAUSE EPC.... */
+	lw		$2,    STK_OFFSET_HI(sp)
+	mthi	$2
+	lw		$2, 	STK_OFFSET_LO(sp)
+	mtlo	$2
+
+	lw		$2, 	STK_OFFSET_SR(sp)
+	mtc0	$2, 	CP0_STATUS
+
+	lw		$2, 	STK_OFFSET_BADVADDR(sp)
+	mtc0	$2, 	CP0_BADVADDR
+
+	lw		$2, 	STK_OFFSET_CAUSE(sp)
+	mtc0	$2, 	CP0_CAUSE
+
+	lw		$2, 	STK_OFFSET_EPC(sp)
+	MTC0	$2, 	CP0_EPC
+
+	//restore $2
+	lw		$2,  	( 2 * 4)(sp)
+	//restore sp
+	lw		$29, 	(29 * 4)(sp)
+
+	eret
+	nop
+    .set    pop
+.endm
+#endif
+#endif /* _MIPS_CONTEXT_ASM_H_ */
diff --git a/bsp/x1000/cpu/common/mips_def.h b/bsp/x1000/cpu/common/mips_def.h
new file mode 100644
index 0000000000..1727684f50
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_def.h
@@ -0,0 +1,2296 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-07     Urey         first version
+ */
+
+#ifndef _COMMON_MIPS_DEF_H_
+#define _COMMON_MIPS_DEF_H_
+
+
+/*
+ ************************************************************************
+ *                I N S T R U C T I O N   F O R M A T S                 *
+ ************************************************************************
+ *
+ * The following definitions describe each field in an instruction.  There
+ * is one diagram for each type of instruction, with field definitions
+ * following the diagram for that instruction.  Note that if a field of
+ * the same name and position is defined in an earlier diagram, it is
+ * not defined again in the subsequent diagram.  Only new fields are
+ * defined for each diagram.
+ *
+ * R-Type (operate)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |           |   rs    |   rt    |   rd    |   sa    |           |
+ * |   Opcode  |         |         |       Tcode       |   func    |
+ * |           |                  Bcode                |     | sel |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnOpcode		26
+#define M_InstnOpcode		(0x3f << S_InstnOpcode)
+#define S_InstnRS			21
+#define M_InstnRS			(0x1f << S_InstnRS)
+#define S_InstnRT			16
+#define M_InstnRT			(0x1f << S_InstnRT)
+#define S_InstnRD			11
+#define M_InstnRD			(0x1f << S_InstnRD)
+#define S_InstnSA			6
+#define M_InstnSA			(0x1f << S_InstnSA)
+#define S_InstnTcode		6
+#define M_InstnTcode		(0x3ff << S_InstnTcode)
+#define S_InstnBcode		6
+#define M_InstnBcode		(0xfffff << S_InstnBcode)
+#define S_InstnFunc		0
+#define M_InstnFunc		(0x3f << S_InstnFunc)
+#define S_InstnSel			0
+#define M_InstnSel			(0x7 << S_InstnSel)
+
+/*
+ * I-Type (load, store, branch, immediate)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   rs    |   rt    |             Offset            |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnOffset		0
+#define M_InstnOffset		(0xffff << S_InstnOffset)
+
+/*
+ * I-Type (pref)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   rs    |  hint   |             Offset            |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnHint		S_InstnRT
+#define M_InstnHint		M_InstnRT
+
+/*
+ * J-Type (jump)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |                    JIndex                         |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnJIndex		0
+#define M_InstnJIndex		(0x03ffffff << S_InstnJIndex)
+
+/*
+ * FP R-Type (operate)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   fmt   |   ft    |   fs    |   fd    |   func    |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnFmt		S_InstnRS
+#define M_InstnFmt		M_InstnRS
+#define S_InstnFT		S_InstnRT
+#define M_InstnFT		M_InstnRT
+#define S_InstnFS		S_InstnRD
+#define M_InstnFS		M_InstnRD
+#define S_InstnFD		S_InstnSA
+#define M_InstnFD		M_InstnSA
+
+/*
+ * FP R-Type (cpu <-> cpu data movement))
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   sub   |   rt    |   fs    |          0          |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnSub		S_InstnRS
+#define M_InstnSub		M_InstnRS
+
+/*
+ * FP R-Type (compare)
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |           |         |         |         |     | |C|           |
+ * |   Opcode  |   fmt   |   ft    |   fs    |  cc |0|A|   func    |
+ * |           |         |         |         |     | |B|           |
+ * |           |         |         |         |     | |S|           |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnCCcmp		8
+#define M_InstnCCcmp		(0x7 << S_InstnCCcmp)
+#define S_InstnCABS		6
+#define M_InstnCABS		(0x1 << S_InstnCABS)
+
+/*
+ * FP R-Type (FPR conditional move on FP cc)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   fmt   |  cc |n|t|   fs    |   fd    |   func    |
+ * |           |         |     |d|f|         |         |           |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnCC		18
+#define M_InstnCC		(0x7 << S_InstnCC)
+#define S_InstnND		17
+#define M_InstnND		(0x1 << S_InstnND)
+#define S_InstnTF		16
+#define M_InstnTF		(0x1 << S_InstnTF)
+
+/*
+ * FP R-Type (3-operand operate)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   fr    |   ft    |   fs    |   fd    | op4 | fmt3|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnFR		S_InstnRS
+#define M_InstnFR		M_InstnRS
+#define S_InstnOp4		3
+#define M_InstnOp4		(0x7 << S_InstnOp4)
+#define S_InstnFmt3		0
+#define M_InstnFmt3		(0x7 << S_InstnFmt3)
+
+/*
+ * FP R-Type (Indexed load, store)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   rs    |   rt    |   0     |   fd    |   func    |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+/*
+ * FP R-Type (prefx)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   rs    |   rt    |  hint   |    0    |   func    |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define S_InstnHintX		S_InstnRD
+#define M_InstnHintX		M_InstnRD
+
+/*
+ * FP R-Type (GPR conditional move on FP cc)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |    rs   |  cc |n|t|   rd    |    0    |   func    |
+ * |           |         |     |d|f|         |         |           |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+/*
+ * FP I-Type (load, store)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   rs    |    ft   |           Offset              |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+/*
+ * FP I-Type (branch)
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |   Opcode  |   fmt   |  cc |n|t|           Offset              |
+ * |           |         |     |d|f|                               |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+
+/*
+ *************************************************************************
+ *         V I R T U A L   A D D R E S S   D E F I N I T I O N S         *
+ *************************************************************************
+ */
+
+#ifdef MIPSADDR64
+#define A_K0BASE		UNS64Const(0xffffffff80000000)
+#define A_K1BASE		UNS64Const(0xffffffffa0000000)
+#define A_K2BASE		UNS64Const(0xffffffffc0000000)
+#define A_K3BASE		UNS64Const(0xffffffffe0000000)
+#define A_REGION		UNS64Const(0xc000000000000000)
+#define A_XKPHYS_ATTR		UNS64Const(0x3800000000000000)
+#else
+#define A_K0BASE		0x80000000
+#define A_K1BASE		0xa0000000
+#define A_K2BASE		0xc0000000
+#define A_K3BASE		0xe0000000
+#endif
+#define M_KMAPPED		0x40000000		/* KnSEG address is mapped if bit is one */
+
+
+#ifdef MIPS_Model64
+
+#define S_VMAP64                62
+#define M_VMAP64                UNS64Const(0xc000000000000000)
+
+#define K_VMode11               3
+#define K_VMode10               2
+#define K_VMode01               1
+#define K_VMode00               0
+
+#define S_KSEG3                 29
+#define M_KSEG3                 (0x7 << S_KSEG3)
+#define K_KSEG3                 7
+
+#define S_SSEG                  29
+#define M_SSEG                  (0x7 << S_KSEG3)
+#define K_SSEG                  6
+
+#define S_KSSEG                 29
+#define M_KSSEG                 (0x7 << S_KSEG3)
+#define K_KSSEG                 6
+
+#define S_KSEG1                 29
+#define M_KSEG1                 (0x7 << S_KSEG3)
+#define K_KSEG1                 5
+
+#define S_KSEG0                 29
+#define M_KSEG0                 (0x7 << S_KSEG3)
+#define K_KSEG0                 4
+
+#define S_XKSEG                 29
+#define M_XKSEG                 (0x7 << S_KSEG3)
+#define K_XKSEG                 3
+
+#define S_USEG                  31
+#define M_USEG                  (0x1 << S_USEG)
+#define K_USEG                  0
+
+#define S_EjtagProbeMem         20
+#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
+#define K_EjtagProbeMem         0
+
+
+
+#else
+
+#define S_KSEG3                 29
+#define M_KSEG3                 (0x7 << S_KSEG3)
+#define K_KSEG3                 7
+
+#define S_KSSEG                 29
+#define M_KSSEG                 (0x7 << S_KSSEG)
+#define K_KSSEG                 6
+
+#define S_SSEG                  29
+#define M_SSEG                  (0x7 << S_SSEG)
+#define K_SSEG                  6
+
+#define S_KSEG1                 29
+#define M_KSEG1                 (0x7 << S_KSEG1)
+#define K_KSEG1                 5
+
+#define S_KSEG0                 29
+#define M_KSEG0                 (0x7 << S_KSEG0)
+#define K_KSEG0                 4
+
+#define S_KUSEG                 31
+#define M_KUSEG                 (0x1 << S_KUSEG)
+#define K_KUSEG                 0
+
+#define S_SUSEG                 31
+#define M_SUSEG                 (0x1 << S_SUSEG)
+#define K_SUSEG                 0
+
+#define S_USEG                  31
+#define M_USEG                  (0x1 << S_USEG)
+#define K_USEG                  0
+
+#define K_EjtagLower            0xff200000
+#define K_EjtagUpper            0xff3fffff
+
+#define S_EjtagProbeMem         20
+#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
+#define K_EjtagProbeMem         0
+
+#endif
+
+
+
+/*
+ *************************************************************************
+ *   C A C H E   I N S T R U C T I O N   O P E R A T I O N   C O D E S   *
+ *************************************************************************
+ */
+
+/*
+ * Cache encodings
+ */
+#define K_CachePriI		0			/* Primary Icache */
+#define K_CachePriD		1			/* Primary Dcache */
+#define K_CachePriU		1			/* Unified primary */
+#define K_CacheTerU		2			/* Unified Tertiary */
+#define K_CacheSecU		3			/* Unified secondary */
+
+
+/*
+ * Function encodings
+ */
+#define S_CacheFunc		2			/* Amount to shift function encoding within 5-bit field */
+#define K_CacheIndexInv		0			/* Index invalidate */
+#define K_CacheIndexWBInv       0			/* Index writeback invalidate */
+#define K_CacheIndexLdTag	1			/* Index load tag */
+#define K_CacheIndexStTag	2			/* Index store tag */
+#define K_CacheHitInv		4			/* Hit Invalidate */
+#define K_CacheFill		5			/* Fill (Icache only) */
+#define K_CacheHitWBInv		5			/* Hit writeback invalidate */
+#define K_CacheHitWB		6			/* Hit writeback */
+#define K_CacheFetchLock	7			/* Fetch and lock */
+
+#define ICIndexInv		((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
+#define DCIndexWBInv		((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
+#define DCIndexInv		DCIndexWBInv
+#define ICIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
+#define DCIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
+#define ICIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
+#define DCIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
+#define ICHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
+#define DCHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
+#define ICFill			((K_CacheFill << S_CacheFunc) | K_CachePriI)
+#define DCHitWBInv		((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
+#define DCHitWB			((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
+#define ICFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
+#define DCFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)
+
+
+/*
+ *************************************************************************
+ *          P R E F E T C H   I N S T R U C T I O N   H I N T S          *
+ *************************************************************************
+ */
+
+#define PrefLoad		0
+#define PrefStore		1
+#define PrefLoadStreamed	4
+#define PrefStoreStreamed	5
+#define PrefLoadRetained	6
+#define PrefStoreRetained	7
+#define PrefWBInval		25
+#define PrefNudge		25
+
+
+/*
+ *************************************************************************
+ *             C P U   R E G I S T E R   D E F I N I T I O N S           *
+ *************************************************************************
+ */
+
+
+/*
+ *************************************************************************
+ *                  S O F T W A R E   G P R   N A M E S                  *
+ *************************************************************************
+ */
+#ifdef __ASSEMBLY__
+#define zero			 $0
+#define AT			 $1
+#define v0			 $2
+#define v1			 $3
+#define a0			 $4
+#define a1			 $5
+#define a2			 $6
+#define a3			 $7
+#define t0			 $8
+#define t1			 $9
+#define t2			$10
+#define t3			$11
+#define t4			$12
+#define t5			$13
+#define t6			$14
+#define t7			$15
+#define s0			$16
+#define s1			$17
+#define s2			$18
+#define s3			$19
+#define s4			$20
+#define s5			$21
+#define s6			$22
+#define s7			$23
+#define t8			$24
+#define t9			$25
+#define k0			$26
+#define k1			$27
+#define gp			$28
+#define sp			$29
+#define fp			$30
+#define ra			$31
+
+/*
+ * The following registers are used by the AVP environment and
+ * are not part of the normal software definitions.
+ */
+
+#ifdef MIPSAVPENV
+#define repc			$25			/* Expected exception PC */
+#define tid			$30			/* Current test case address */
+#endif
+
+
+/*
+ *************************************************************************
+ *                  H A R D W A R E   G P R   N A M E S                  *
+ *************************************************************************
+ *
+ * In the AVP environment, several of the `r' names are removed from the
+ * name space because they are used by the kernel for special purposes.
+ * Removing them causes assembly rather than runtime errors for tests that
+ * use the `r' names.
+ *
+ *	- r25 (repc) is used as the expected PC on an exception
+ *	- r26-r27 (k0, k1) are used in the exception handler
+ *	- r30 (tid) is used as the current test address
+ */
+
+#define r0			 $0
+#define r1			 $1
+#define r2			 $2
+#define r3			 $3
+#define r4			 $4
+#define r5			 $5
+#define r6			 $6
+#define r7			 $7
+#define r8			 $8
+#define r9			 $9
+#define r10			$10
+#define r11			$11
+#define r12			$12
+#define r13			$13
+#define r14			$14
+#define r15			$15
+#define r16			$16
+#define r17			$17
+#define r18			$18
+#define r19			$19
+#define r20			$20
+#define r21			$21
+#define r22			$22
+#define r23			$23
+#define r24			$24
+#ifdef MIPSAVPENV
+#define r25			r25_unknown
+#define r26			r26_unknown
+#define r27			r27_unknown
+#else
+#define r25			$25
+#define r26			$26
+#define r27			$27
+#endif
+#define r28			$28
+#define r29			$29
+#ifdef MIPSAVPENV
+#define r30			r30_unknown
+#else
+#define r30			$30
+#endif
+#define r31			$31
+
+#endif
+
+/*
+ *************************************************************************
+ *                H A R D W A R E   G P R   I N D I C E S                *
+ *************************************************************************
+ *
+ * These definitions provide the index (number) of the GPR, as opposed
+ * to the assembler register name ($n).
+ */
+
+#define R_r0			 0
+#define R_r1			 1
+#define R_r2			 2
+#define R_r3			 3
+#define R_r4			 4
+#define R_r5			 5
+#define R_r6			 6
+#define R_r7			 7
+#define R_r8			 8
+#define R_r9			 9
+#define R_r10			10
+#define R_r11			11
+#define R_r12			12
+#define R_r13			13
+#define R_r14			14
+#define R_r15			15
+#define R_r16			16
+#define R_r17			17
+#define R_r18			18
+#define R_r19			19
+#define R_r20			20
+#define R_r21			21
+#define R_r22			22
+#define R_r23			23
+#define R_r24			24
+#define R_r25			25
+#define R_r26			26
+#define R_r27			27
+#define R_r28			28
+#define R_r29			29
+#define R_r30			30
+#define R_r31			31
+#define R_hi			32			/* Hi register */
+#define R_lo			33			/* Lo register */
+
+
+/*
+ *************************************************************************
+ *                  S O F T W A R E   G P R   M A S K S                  *
+ *************************************************************************
+ *
+ * These definitions provide the bit mask corresponding to the GPR number
+ */
+
+#define M_AT			 (1<<1)
+#define M_v0			 (1<<2)
+#define M_v1			 (1<<3)
+#define M_a0			 (1<<4)
+#define M_a1			 (1<<5)
+#define M_a2			 (1<<6)
+#define M_a3			 (1<<7)
+#define M_t0			 (1<<8)
+#define M_t1			 (1<<9)
+#define M_t2			(1<<10)
+#define M_t3			(1<<11)
+#define M_t4			(1<<12)
+#define M_t5			(1<<13)
+#define M_t6			(1<<14)
+#define M_t7			(1<<15)
+#define M_s0			(1<<16)
+#define M_s1			(1<<17)
+#define M_s2			(1<<18)
+#define M_s3			(1<<19)
+#define M_s4			(1<<20)
+#define M_s5			(1<<21)
+#define M_s6			(1<<22)
+#define M_s7			(1<<23)
+#define M_t8			(1<<24)
+#define M_t9			(1<<25)
+#define M_k0			(1<<26)
+#define M_k1			(1<<27)
+#define M_gp			(1<<28)
+#define M_sp			(1<<29)
+#define M_fp			(1<<30)
+#define M_ra			(1<<31)
+
+
+/*
+ *************************************************************************
+ *             C P 0   R E G I S T E R   D E F I N I T I O N S           *
+ *************************************************************************
+ * Each register has the following definitions:
+ *
+ *	C0_rrr		The register number (as a $n value)
+ *	R_C0_rrr	The register index (as an integer corresponding
+ *			to the register number)
+ *
+ * Each field in a register has the following definitions:
+ *
+ *	S_rrrfff	The shift count required to right-justify
+ *			the field.  This corresponds to the bit
+ *			number of the right-most bit in the field.
+ *	M_rrrfff	The Mask required to isolate the field.
+ *
+ * Register diagrams included below as comments correspond to the
+ * MIPS32 and MIPS64 architecture specifications.  Refer to other
+ * sources for register diagrams for older architectures.
+ */
+
+
+/*
+ ************************************************************************
+ *                 I N D E X   R E G I S T E R   ( 0 )                  *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |P|                         0                       |   Index   | Index
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Index		$0
+#define R_C0_Index		0
+#define C0_INX			C0_Index		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_IndexP		31			/* Probe failure (R)*/
+#define M_IndexP		(0x1 << S_IndexP)
+
+#define S_IndexIndex		0			/* TLB index (R/W)*/
+#define M_IndexIndex		(0x3f << S_IndexIndex)
+
+#define M_Index0Fields		0x7fffffc0
+#define M_IndexRFields		0x80000000
+
+
+/*
+ ************************************************************************
+ *                R A N D O M   R E G I S T E R   ( 1 )                 *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                            0                      |   Index   | Random
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Random		$1
+#define R_C0_Random		1
+#define C0_RAND			$1			/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_RandomIndex		0			/* TLB random index (R)*/
+#define M_RandomIndex		(0x3f << S_RandomIndex)
+
+#define M_Random0Fields		0xffffffc0
+#define M_RandomRFields		0x0000003f
+
+
+/*
+ ************************************************************************
+ *              E N T R Y L O 0   R E G I S T E R   ( 2 )               *
+ ************************************************************************
+ *
+ *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Fill (0) //| 0 |                     PFN                       |  C  |D|V|G| EntryLo0
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_EntryLo0		$2
+#define R_C0_EntryLo0		2
+#define C0_TLBLO_0		C0_EntryLo0		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_EntryLoPFN		6			/* PFN (R/W) */
+#define M_EntryLoPFN		(0xffffff << S_EntryLoPFN)
+#define S_EntryLoC		3			/* Coherency attribute (R/W) */
+#define M_EntryLoC		(0x7 << S_EntryLoC)
+#define S_EntryLoD		2			/* Dirty (R/W) */
+#define M_EntryLoD		(0x1 << S_EntryLoD)
+#define S_EntryLoV		1			/* Valid (R/W) */
+#define M_EntryLoV		(0x1 << S_EntryLoV)
+#define S_EntryLoG		0			/* Global (R/W) */
+#define M_EntryLoG		(0x1 << S_EntryLoG)
+#define M_EntryLoOddPFN		(0x1 << S_EntryLoPFN)	/* Odd PFN bit */
+#define S_EntryLo_RS		K_PageAlign		/* Right-justify PFN */
+#define S_EntryLo_LS		S_EntryLoPFN		/* Position PFN to appropriate position */
+
+#define M_EntryLo0Fields	0x00000000
+#define M_EntryLoRFields	0xc0000000
+#define M_EntryLo0Fields64	UNS64Const(0x0000000000000000)
+#define M_EntryLoRFields64	UNS64Const(0xffffffffc0000000)
+
+/*
+ * Cache attribute values in the C field of EntryLo and the
+ * K0 field of Config
+ */
+#define K_CacheAttrCWTnWA	0			/* Cacheable, write-thru, no write allocate */
+#define K_CacheAttrCWTWA	1			/* Cacheable, write-thru, write allocate */
+#define K_CacheAttrU		2			/* Uncached */
+#define K_CacheAttrC		3			/* Cacheable */
+#define K_CacheAttrCN		3			/* Cacheable, non-coherent */
+#define K_CacheAttrCCE		4			/* Cacheable, coherent, exclusive */
+#define K_CacheAttrCCS		5			/* Cacheable, coherent, shared */
+#define K_CacheAttrCCU		6			/* Cacheable, coherent, update */
+#define K_CacheAttrUA		7			/* Uncached accelerated */
+
+
+/*
+ ************************************************************************
+ *              E N T R Y L O 1   R E G I S T E R   ( 3 )               *
+ ************************************************************************
+ *
+ *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Fill (0) //| 0 |                     PFN                       |  C  |D|V|G| EntryLo1
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_EntryLo1		$3
+#define R_C0_EntryLo1		3
+#define C0_TLBLO_1		C0_EntryLo1		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+/*
+ * Field definitions are as given for EntryLo0 above
+ */
+
+
+/*
+ ************************************************************************
+ *               C O N T E X T   R E G I S T E R   ( 4 )                *
+ ************************************************************************
+ *
+ *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  //       PTEBase    |            BadVPN<31:13>            |   0   | Context
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Context		$4
+#define R_C0_Context		4
+#define C0_CTXT			C0_Context		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_ContextPTEBase	23			/* PTE base (R/W) */
+#define M_ContextPTEBase	(0x1ff << S_ContextPTEBase)
+#define S_ContextBadVPN		4			/* BadVPN2 (R) */
+#define M_ContextBadVPN		(0x7ffff << S_ContextBadVPN)
+#define S_ContextBadVPN_LS	9			/* Position BadVPN to bit 31 */
+#define S_ContextBadVPN_RS	13			/* Right-justify shifted BadVPN field */
+
+#define M_Context0Fields	0x0000000f
+#define M_ContextRFields	0x007ffff0
+#define M_Context0Fields64	UNS64Const(0x000000000000000f)
+#define M_ContextRFields64	UNS64Const(0x00000000007ffff0)
+
+
+/*
+ ************************************************************************
+ *              P A G E M A S K   R E G I S T E R   ( 5 )               *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |      0      |        Mask           |            0            | PageMask
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_PageMask		$5
+#define R_C0_PageMask		5			/* Mask (R/W) */
+#define C0_PGMASK		C0_PageMask		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_PageMaskMask		13
+#define M_PageMaskMask		(0xfff << S_PageMaskMask)
+
+#define M_PageMask0Fields	0xfe001fff
+#define M_PageMaskRFields	0x00000000
+
+/*
+ * Values in the Mask field
+ */
+#define K_PageMask4K		0x000			/* K_PageMasknn values are values for use */
+#define K_PageMask16K		0x003			/* with KReqPageAttributes or KReqPageMask macros */
+#define K_PageMask64K		0x00f
+#define K_PageMask256K		0x03f
+#define K_PageMask1M		0x0ff
+#define K_PageMask4M		0x3ff
+#define K_PageMask16M		0xfff
+
+#define M_PageMask4K		(K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */
+#define M_PageMask16K		(K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */
+#define M_PageMask64K		(K_PageMask64K << S_PageMaskMask)
+#define M_PageMask256K		(K_PageMask256K << S_PageMaskMask)
+#define M_PageMask1M		(K_PageMask1M << S_PageMaskMask)
+#define M_PageMask4M		(K_PageMask4M << S_PageMaskMask)
+#define M_PageMask16M		(K_PageMask16M << S_PageMaskMask)
+
+
+/*
+ ************************************************************************
+ *                 W I R E D   R E G I S T E R   ( 6 )                  *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                            0                      |   Index   | Wired
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Wired		$6
+#define R_C0_Wired		6
+#define C0_TLBWIRED		C0_Wired		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_WiredIndex		0			/* TLB wired boundary (R/W) */
+#define M_WiredIndex		(0x3f << S_WiredIndex)
+
+#define M_Wired0Fields		0xffffffc0
+#define M_WiredRFields		0x00000000
+
+
+/*
+ ************************************************************************
+ *              B A D V A D D R   R E G I S T E R   ( 8 )               *
+ ************************************************************************
+ *
+ *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  //                     Bad Virtual Address                        | BadVAddr
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_BadVAddr		$8
+#define R_C0_BadVAddr		8
+#define C0_BADVADDR		C0_BadVAddr		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_BadVAddrOddPage	K_PageSize		/* Even/Odd VA bit for pair of PAs */
+
+#define M_BadVAddr0Fields	0x00000000
+#define M_BadVAddrRFields	0xffffffff
+#define M_BadVAddr0Fields64	UNS64Const(0x0000000000000000)
+#define M_BadVAddrRFields64	UNS64Const(0xffffffffffffffff)
+
+/*
+ ************************************************************************
+ *                 C O U N T   R E G I S T E R   ( 9 )                  *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                         Count Value                           | Count
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Count		$9
+#define R_C0_Count		9
+#define C0_COUNT		C0_Count		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_Count0Fields		0x00000000
+#define M_CountRFields		0x00000000
+
+
+/*
+ ************************************************************************
+ *              E N T R Y H I   R E G I S T E R   ( 1 0 )               *
+ ************************************************************************
+ *
+ *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | R | Fill //                 VPN2                 |    0    |     ASID      | EntryHi
+ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_EntryHi		$10
+#define R_C0_EntryHi		10
+#define C0_TLBHI		C0_EntryHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_EntryHiR64		62			/* Region (R/W) */
+#define M_EntryHiR64		UNS64Const(0xc000000000000000)
+#define S_EntryHiVPN2		13			/* VPN/2 (R/W) */
+#define M_EntryHiVPN2		(0x7ffff << S_EntryHiVPN2)
+#define M_EntryHiVPN264		UNS64Const(0x000000ffffffe000)
+#define S_EntryHiASID		0			/* ASID (R/W) */
+#define M_EntryHiASID		(0xff << S_EntryHiASID)
+#define S_EntryHiVPN_Shf	S_EntryHiVPN2
+
+#define M_EntryHi0Fields	0x00001f00
+#define M_EntryHiRFields	0x00000000
+#define M_EntryHi0Fields64	UNS64Const(0x0000000000001f00)
+#define M_EntryHiRFields64	UNS64Const(0x3fffff0000000000)
+
+
+/*
+ ************************************************************************
+ *              C O M P A R E   R E G I S T E R   ( 1 1 )               *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                        Compare Value                          | Compare
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Compare		$11
+#define R_C0_Compare		11
+#define C0_COMPARE		C0_Compare		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_Compare0Fields	0x00000000
+#define M_CompareRFields	0x00000000
+
+
+/*
+ ************************************************************************
+ *               S T A T U S   R E G I S T E R   ( 1 2 )                *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I|
+ * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status
+ * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Status		$12
+#define R_C0_Status		12
+#define C0_SR			C0_Status		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_StatusCU		28			/* Coprocessor enable (R/W) */
+#define M_StatusCU		(0xf << S_StatusCU)
+#define S_StatusCU3		31
+#define M_StatusCU3     	(0x1 << S_StatusCU3)
+#define S_StatusCU2		30
+#define M_StatusCU2		(0x1 << S_StatusCU2)
+#define S_StatusCU1		29
+#define M_StatusCU1		(0x1 << S_StatusCU1)
+#define S_StatusCU0		28
+#define M_StatusCU0		(0x1 << S_StatusCU0)
+#define S_StatusRP		27			/* Enable reduced power mode (R/W) */
+#define M_StatusRP		(0x1 << S_StatusRP)
+#define S_StatusFR		26			/* Enable 64-bit FPRs (MIPS64 only) (R/W) */
+#define M_StatusFR		(0x1 << S_StatusFR)
+#define S_StatusRE		25			/* Enable reverse endian (R/W) */
+#define M_StatusRE		(0x1 << S_StatusRE)
+#define S_StatusMX		24			/* Enable access to MDMX resources (MIPS64 only) (R/W) */
+#define M_StatusMX		(0x1 << S_StatusMX)
+#define S_StatusPX		23			/* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */
+#define M_StatusPX		(0x1 << S_StatusPX)
+#define S_StatusBEV		22			/* Enable Boot Exception Vectors (R/W) */
+#define M_StatusBEV		(0x1 << S_StatusBEV)
+#define S_StatusTS		21			/* Denote TLB shutdown (R/W) */
+#define M_StatusTS		(0x1 << S_StatusTS)
+#define S_StatusSR		20			/* Denote soft reset (R/W) */
+#define M_StatusSR		(0x1 << S_StatusSR)
+#define S_StatusNMI		19
+#define M_StatusNMI		(0x1 << S_StatusNMI)	/* Denote NMI (R/W) */
+#define S_StatusIM		8			/* Interrupt mask (R/W) */
+#define M_StatusIM		(0xff << S_StatusIM)
+#define S_StatusIM7		15
+#define M_StatusIM7		(0x1 << S_StatusIM7)
+#define S_StatusIM6		14
+#define M_StatusIM6		(0x1 << S_StatusIM6)
+#define S_StatusIM5		13
+#define M_StatusIM5		(0x1 << S_StatusIM5)
+#define S_StatusIM4		12
+#define M_StatusIM4		(0x1 << S_StatusIM4)
+#define S_StatusIM3		11
+#define M_StatusIM3		(0x1 << S_StatusIM3)
+#define S_StatusIM2		10
+#define M_StatusIM2		(0x1 << S_StatusIM2)
+#define S_StatusIM1		9
+#define M_StatusIM1		(0x1 << S_StatusIM1)
+#define S_StatusIM0		8
+#define M_StatusIM0		(0x1 << S_StatusIM0)
+#define S_StatusKX		7			/* Enable access to extended kernel addresses (MIPS64 only) (R/W) */
+#define M_StatusKX		(0x1 << S_StatusKX)
+#define S_StatusSX		6			/* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */
+#define M_StatusSX		(0x1 << S_StatusSX)
+#define S_StatusUX		5			/* Enable access to extended user addresses (MIPS64 only) (R/W) */
+#define M_StatusUX		(0x1 << S_StatusUX)
+#define S_StatusKSU		3			/* Two-bit current mode (R/W) */
+#define M_StatusKSU		(0x3 << S_StatusKSU)
+#define S_StatusUM		4			/* User mode if supervisor mode not implemented (R/W) */
+#define M_StatusUM		(0x1 << S_StatusUM)
+#define S_StatusSM		3			/* Supervisor mode (R/W) */
+#define M_StatusSM		(0x1 << S_StatusSM)
+#define S_StatusERL		2			/* Denotes error level (R/W) */
+#define M_StatusERL		(0x1 << S_StatusERL)
+#define S_StatusEXL		1			/* Denotes exception level (R/W) */
+#define M_StatusEXL		(0x1 << S_StatusEXL)
+#define S_StatusIE		0			/* Enables interrupts (R/W) */
+#define M_StatusIE		(0x1 << S_StatusIE)
+
+#define M_Status0Fields		0x00040000
+#define M_StatusRFields		0x058000e0		/* FR, MX, PX, KX, SX, UX unused in MIPS32 */
+#define M_Status0Fields64	0x00040000
+#define M_StatusRFields64	0x00000000
+
+/*
+ * Values in the KSU field
+ */
+#define K_StatusKSU_U		2			/* User mode in KSU field */
+#define K_StatusKSU_S		1			/* Supervisor mode in KSU field */
+#define K_StatusKSU_K		0			/* Kernel mode in KSU field */
+
+
+/*
+ ************************************************************************
+ *                C A U S E   R E G I S T E R   ( 1 3 )                 *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |B| | C |       |I|W|           |I|I|I|I|I|I|I|I| |         | R |
+ * |D| | E | Rsvd  |V|P|    Rsvd   |P|P|P|P|P|P|P|P| | ExcCode | s | Cause
+ * | | |   |       | | |           |7|6|5|4|3|2|1|0| |         | v |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Cause		$13
+#define R_C0_Cause		13
+#define C0_CAUSE		C0_Cause		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_CauseBD		31
+#define M_CauseBD		(0x1 << S_CauseBD)
+#define S_CauseCE		28
+#define M_CauseCE		(0x3<< S_CauseCE)
+#define S_CauseIV		23
+#define M_CauseIV		(0x1 << S_CauseIV)
+#define S_CauseWP		22
+#define M_CauseWP		(0x1 << S_CauseWP)
+#define S_CauseIP		8
+#define M_CauseIP		(0xff << S_CauseIP)
+#define S_CauseIPEXT		10
+#define M_CauseIPEXT		(0x3f << S_CauseIPEXT)
+#define S_CauseIP7		15
+#define M_CauseIP7		(0x1 << S_CauseIP7)
+#define S_CauseIP6		14
+#define M_CauseIP6		(0x1 << S_CauseIP6)
+#define S_CauseIP5		13
+#define M_CauseIP5		(0x1 << S_CauseIP5)
+#define S_CauseIP4		12
+#define M_CauseIP4		(0x1 << S_CauseIP4)
+#define S_CauseIP3		11
+#define M_CauseIP3		(0x1 << S_CauseIP3)
+#define S_CauseIP2		10
+#define M_CauseIP2		(0x1 << S_CauseIP2)
+#define S_CauseIP1		9
+#define M_CauseIP1		(0x1 << S_CauseIP1)
+#define S_CauseIP0		8
+#define M_CauseIP0		(0x1 << S_CauseIP0)
+#define S_CauseExcCode		2
+#define M_CauseExcCode		(0x1f << S_CauseExcCode)
+
+#define M_Cause0Fields		0x4f3f0083
+#define M_CauseRFields		0xb000fc7c
+
+/*
+ * Values in the CE field
+ */
+#define K_CauseCE0		0			/* Coprocessor 0 in the CE field */
+#define K_CauseCE1		1			/* Coprocessor 1 in the CE field */
+#define K_CauseCE2		2			/* Coprocessor 2 in the CE field */
+#define K_CauseCE3		3			/* Coprocessor 3 in the CE field */
+
+/*
+ * Values in the ExcCode field
+ */
+#define	EX_INT			0			/* Interrupt */
+#define	EXC_INT			(EX_INT << S_CauseExcCode)
+#define	EX_MOD			1			/* TLB modified */
+#define	EXC_MOD			(EX_MOD << S_CauseExcCode)
+#define	EX_TLBL		        2			/* TLB exception (load or ifetch) */
+#define	EXC_TLBL		(EX_TLBL << S_CauseExcCode)
+#define	EX_TLBS		        3			/* TLB exception (store) */
+#define	EXC_TLBS		(EX_TLBS << S_CauseExcCode)
+#define	EX_ADEL		        4			/* Address error (load or ifetch) */
+#define	EXC_ADEL		(EX_ADEL << S_CauseExcCode)
+#define	EX_ADES		        5			/* Address error (store) */
+#define	EXC_ADES		(EX_ADES << S_CauseExcCode)
+#define	EX_IBE			6			/* Instruction Bus Error */
+#define	EXC_IBE			(EX_IBE << S_CauseExcCode)
+#define	EX_DBE			7			/* Data Bus Error */
+#define	EXC_DBE			(EX_DBE << S_CauseExcCode)
+#define	EX_SYS			8			/* Syscall */
+#define	EXC_SYS			(EX_SYS << S_CauseExcCode)
+#define	EX_SYSCALL		EX_SYS
+#define	EXC_SYSCALL		EXC_SYS
+#define	EX_BP			9			/* Breakpoint */
+#define	EXC_BP			(EX_BP << S_CauseExcCode)
+#define	EX_BREAK		EX_BP
+#define	EXC_BREAK		EXC_BP
+#define	EX_RI			10			/* Reserved instruction */
+#define	EXC_RI			(EX_RI << S_CauseExcCode)
+#define	EX_CPU			11			/* CoProcessor Unusable */
+#define	EXC_CPU			(EX_CPU << S_CauseExcCode)
+#define	EX_OV			12			/* OVerflow */
+#define	EXC_OV			(EX_OV << S_CauseExcCode)
+#define	EX_TR		    	13			/* Trap instruction */
+#define	EXC_TR			(EX_TR << S_CauseExcCode)
+#define	EX_TRAP			EX_TR
+#define	EXC_TRAP		EXC_TR
+#define EX_FPE			15			/* floating point exception */
+#define EXC_FPE			(EX_FPE << S_CauseExcCode)
+#define EX_C2E			18			/* COP2 exception */
+#define EXC_C2E			(EX_C2E << S_CauseExcCode)
+#define EX_MDMX			22			/* MDMX exception */
+#define EXC_MDMX		(EX_MDMX << S_CauseExcCode)
+#define EX_WATCH		23			/* Watch exception */
+#define EXC_WATCH		(EX_WATCH << S_CauseExcCode)
+#define	EX_MCHECK	        24			/* Machine check exception */
+#define	EXC_MCHECK 		(EX_MCHECK << S_CauseExcCode)
+#define	EX_CacheErr	        30			/* Cache error caused re-entry to Debug Mode */
+#define	EXC_CacheErr 		(EX_CacheErr << S_CauseExcCode)
+
+
+/*
+ ************************************************************************
+ *                   E P C   R E G I S T E R   ( 1 4 )                  *
+ ************************************************************************
+ *
+ *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  //                        Exception PC                            | EPC
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_EPC			$14
+#define R_C0_EPC		14
+
+#define M_EPC0Fields		0x00000000
+#define M_EPCRFields		0x00000000
+#define M_EPC0Fields64		UNS64Const(0x0000000000000000)
+#define M_EPCRFields64		UNS64Const(0x0000000000000000)
+
+/*
+ ************************************************************************
+ *                  P R I D   R E G I S T E R   ( 1 5 )                 *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  Company Opts |   Company ID  |  Procesor ID  |   Revision    | PRId
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_PRId			$15
+#define R_C0_PRId		15
+#define C0_PRID			C0_PRID			/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_PRIdCoOpt		24			/* Company options (R) */
+#define M_PRIdCoOpt		(0xff << S_PRIdCoOpt)
+#define S_PRIdCoID		16			/* Company ID (R) */
+#define M_PRIdCoID		(0xff << S_PRIdCoID)
+#define S_PRIdImp		8			/* Implementation ID (R) */
+#define M_PRIdImp		(0xff << S_PRIdImp)
+#define S_PRIdRev		0			/* Revision (R) */
+#define M_PRIdRev		(0xff << S_PRIdRev)
+
+#define M_PRId0Fields		0x00000000
+#define M_PRIdRFields		0xffffffff
+/*
+ * Values in the Company ID field
+ */
+#define K_PRIdCoID_MIPS	1
+#define K_PRIdCoID_Broadcom 2
+#define K_PRIdCoID_Alchemy 3
+#define K_PRIdCoID_SiByte 4
+#define K_PRIdCoID_SandCraft 5
+#define K_PRIdCoID_Philips 6
+#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */
+
+
+/*
+ * Values in the implementation number field
+ */
+#define K_PRIdImp_Jade		0x80
+#define K_PRIdImp_Opal		0x81
+#define K_PRIdImp_Ruby		0x82
+#define K_PRIdImp_JadeLite	0x83
+#define K_PRIdImp_4KEc          0x84    /* Emerald with TLB MMU */
+#define K_PRIdImp_4KEmp         0x85    /* Emerald with FM MMU */
+#define K_PRIdImp_4KSc          0x86    /* Coral */
+
+#define K_PRIdImp_R3000		0x01
+#define K_PRIdImp_R4000		0x04
+#define K_PRIdImp_R10000	0x09
+#define K_PRIdImp_R4300		0x0b
+#define K_PRIdImp_R5000		0x23
+#define K_PRIdImp_R5200		0x28
+#define K_PRIdImp_R5400		0x54
+
+/*
+ ************************************************************************
+ *               C O N F I G   R E G I S T E R   ( 1 6 )                *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |M|                             |B| A |  A  |               | K | Config
+ * | | Reserved for Implementations|E| T |  R  |    Reserved   | 0 |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Config		$16
+#define R_C0_Config		16
+#define C0_CONFIG		C0_Config		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_ConfigMore		31			/* Additional config registers present (R) */
+#define M_ConfigMore		(0x1 << S_ConfigMore)
+#define S_ConfigImpl		16			/* Implementation-specific fields */
+#define M_ConfigImpl		(0x7fff << S_ConfigImpl)
+#define S_ConfigBE		15			/* Denotes big-endian operation (R) */
+#define M_ConfigBE		(0x1 << S_ConfigBE)
+#define S_ConfigAT		13			/* Architecture type (R) */
+#define M_ConfigAT		(0x3 << S_ConfigAT)
+#define S_ConfigAR		10			/* Architecture revision (R) */
+#define M_ConfigAR		(0x7 << S_ConfigAR)
+#define S_ConfigMT		7			/* MMU Type (R) */
+#define M_ConfigMT		(0x7 << S_ConfigMT)
+#define S_ConfigK0		0			/* Kseg0 coherency algorithm (R/W) */
+#define M_ConfigK0		(0x7 << S_ConfigK0)
+
+/*
+ * The following definitions are technically part of the "reserved for
+ * implementations" field, but are the semi-standard definition used in
+ * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3
+ * references.  For that reason, they are included here, but may be
+ * overridden by true implementation-specific definitions
+ */
+#define S_ConfigK23		28			/* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */
+#define M_ConfigK23		(0x7 << S_ConfigK23)
+#define S_ConfigKU		25			/* Kuseg coherency algorithm (FM MMU only) (R/W) */
+#define M_ConfigKU		(0x7 << S_ConfigKU)
+
+#define M_Config0Fields		0x00000078
+#define M_ConfigRFields		0x8000ff80
+
+/*
+ * Values in the AT field
+ */
+#define K_ConfigAT_MIPS32	0			/* MIPS32 */
+#define K_ConfigAT_MIPS64S	1			/* MIPS64 with 32-bit addresses */
+#define K_ConfigAT_MIPS64	2			/* MIPS64 with 32/64-bit addresses */
+
+/*
+ * Values in the MT field
+ */
+#define K_ConfigMT_NoMMU	0			/* No MMU */
+#define K_ConfigMT_TLBMMU	1			/* Standard TLB MMU */
+#define K_ConfigMT_BATMMU	2			/* Standard BAT MMU */
+#define K_ConfigMT_FMMMU	3			/* Standard Fixed Mapping MMU */
+
+
+/*
+ ************************************************************************
+ *         C O N F I G 1   R E G I S T E R   ( 1 6, SELECT 1 )          *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |M|  MMU Size |  IS |  IL |  IA |  DS |  DL |  DA |C|M|P|W|C|E|F| Config1
+ * | |           |     |     |     |     |     |     |2|D|C|R|A|P|P|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Config1		$16,1
+#define R_C0_Config1		16
+
+#define S_Config1More		31			/* Additional Config registers present (R) */
+#define M_Config1More		(0x1 << S_Config1More)
+#define S_Config1MMUSize 	25			/* Number of MMU entries - 1 (R) */
+#define M_Config1MMUSize 	(0x3f << S_Config1MMUSize)
+#define S_Config1IS		22			/* Icache sets per way (R) */
+#define M_Config1IS		(0x7 << S_Config1IS)
+#define S_Config1IL		19			/* Icache line size (R) */
+#define M_Config1IL		(0x7 << S_Config1IL)
+#define S_Config1IA		16			/* Icache associativity - 1 (R) */
+#define M_Config1IA		(0x7 << S_Config1IA)
+#define S_Config1DS		13			/* Dcache sets per way (R) */
+#define M_Config1DS		(0x7 << S_Config1DS)
+#define S_Config1DL		10			/* Dcache line size (R) */
+#define M_Config1DL		(0x7 << S_Config1DL)
+#define S_Config1DA		7			/* Dcache associativity (R) */
+#define M_Config1DA		(0x7 << S_Config1DA)
+#define S_Config1C2		6			/* Coprocessor 2 present (R) */
+#define M_Config1C2		(0x1 << S_Config1C2)
+#define S_Config1MD		5			/* Denotes MDMX present (R) */
+#define M_Config1MD		(0x1 << S_Config1MD)
+#define S_Config1PC		4			/* Denotes performance counters present (R) */
+#define M_Config1PC		(0x1 << S_Config1PC)
+#define S_Config1WR		3			/* Denotes watch registers present (R) */
+#define M_Config1WR		(0x1 << S_Config1WR)
+#define S_Config1CA		2			/* Denotes MIPS-16 present (R) */
+#define M_Config1CA		(0x1 << S_Config1CA)
+#define S_Config1EP		1			/* Denotes EJTAG present (R) */
+#define M_Config1EP		(0x1 << S_Config1EP)
+#define S_Config1FP		0			/* Denotes floating point present (R) */
+#define M_Config1FP		(0x1 << S_Config1FP)
+
+#define M_Config10Fields	0x00000060
+#define M_Config1RFields	0x7fffff9f
+
+/*
+ * The following macro generates a table that is indexed
+ * by the Icache or Dcache sets field in Config1 and
+ * contains the decoded value of sets per way
+ */
+#define Config1CacheSets()	\
+	HALF(64);		\
+	HALF(128);		\
+	HALF(256);		\
+	HALF(512);		\
+	HALF(1024);		\
+	HALF(2048);		\
+	HALF(4096);		\
+	HALF(8192);
+
+/*
+ * The following macro generates a table that is indexed
+ * by the Icache or Dcache line size field in Config1 and
+ * contains the decoded value of the cache line size, in bytes
+ */
+#define Config1CacheLineSize()	\
+	HALF(0);		\
+	HALF(4);		\
+	HALF(8);		\
+	HALF(16);		\
+	HALF(32);		\
+	HALF(64);		\
+	HALF(128);		\
+	HALF(256);
+
+
+/*
+ ************************************************************************
+ *         C O N F I G 2   R E G I S T E R   ( 1 6, SELECT 2 )          *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |M|           |     |     |     |     |     |     | | | | | |S|T| Config1
+ * | |           |     |     |     |     |     |     | | | | | |M|L|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Config2		$16,2
+#define R_C0_Config2		16
+
+#define S_Config2More		31			/* Additional Config registers present (R) */
+#define M_Config2More		(0x1 << S_Config2More)
+#define S_Config2SM		1			/* Denotes SmartMIPS ASE present (R) */
+#define M_Config2SM		(0x1 << S_Config2SM)
+#define S_Config2TL		0			/* Denotes Tracing Logic present (R) */
+#define M_Config2TL		(0x1 << S_Config2TL)
+
+#define M_Config20Fields	0xfffffffc
+#define M_Config2RFields	0x00000003
+
+/*
+ ************************************************************************
+ *                L L A D D R   R E G I S T E R   ( 1 7 )               *
+ ************************************************************************
+ *
+ *  6 6    3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 2    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |    //                      LL Physical Address                       | LLAddr
+ * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_LLAddr		$17
+#define R_C0_LLAddr		17
+#define C0_LLADDR		C0_LLAddr		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_LLAddr0Fields		0x00000000
+#define M_LLAddrRFields		0x00000000
+#define M_LLAddr0Fields64	UNS64Const(0x0000000000000000)
+#define M_LLAddrRFields64	UNS64Const(0x0000000000000000)
+
+
+/*
+ ************************************************************************
+ *               W A T C H L O   R E G I S T E R   ( 1 8 )              *
+ ************************************************************************
+ *
+ *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  //                    Watch Virtual Address                 |I|R|W| WatchLo
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_WatchLo		$18
+#define R_C0_WatchLo		18
+#define C0_WATCHLO		C0_WatchLo		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_WatchLoVAddr		3			/* Watch virtual address (R/W) */
+#define M_WatchLoVAddr		(0x1fffffff << S_WatchLoVAddr)
+#define S_WatchLoI		2			/* Enable Istream watch (R/W) */
+#define M_WatchLoI		(0x1 << S_WatchLoI)
+#define S_WatchLoR		1			/* Enable data read watch (R/W) */
+#define M_WatchLoR		(0x1 << S_WatchLoR)
+#define S_WatchLoW		0			/* Enable data write watch (R/W) */
+#define M_WatchLoW		(0x1 << S_WatchLoW)
+
+#define M_WatchLo0Fields	0x00000000
+#define M_WatchLoRFields	0x00000000
+#define M_WatchLo0Fields64	UNS64Const(0x0000000000000000)
+#define M_WatchLoRFields64	UNS64Const(0x0000000000000000)
+
+#define M_WatchLoEnables	(M_WatchLoI | M_WatchLoR | M_WatchLoW)
+
+
+/*
+ ************************************************************************
+ *               W A T C H H I   R E G I S T E R   ( 1 9 )              *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |M|G|    Rsvd   |      ASID     |  Rsvd |       Mask      |  0  | WatchHi
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_WatchHi		$19
+#define R_C0_WatchHi		19
+#define C0_WATCHHI		C0_WatchHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_WatchHiM		31			/* Denotes additional Watch registers present (R) */
+#define M_WatchHiM		(0x1 << S_WatchHiM)
+#define S_WatchHiG		30			/* Enable ASID-independent Watch match (R/W) */
+#define M_WatchHiG		(0x1 << S_WatchHiG)
+#define S_WatchHiASID		16			/* ASID value to match (R/W) */
+#define M_WatchHiASID		(0xff << S_WatchHiASID)
+#define S_WatchHiMask		3			/* Address inhibit mask (R/W) */
+#define M_WatchHiMask		(0x1ff << S_WatchHiMask)
+
+#define M_WatchHi0Fields	0x3f00f007
+#define M_WatchHiRFields	0x80000000
+
+
+/*
+ ************************************************************************
+ *             X C O N T E X T   R E G I S T E R   ( 2 0 )              *
+ ************************************************************************
+ *
+ *  6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  // PTEBase  | R |                      BadVPN2<39:13>                 |   0   | XContext
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_XContext		$20
+#define R_C0_XContext		20
+#define C0_EXTCTXT		C0_XContext		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_XContextBadVPN2	4			/* BadVPN2 (R) */
+#define S_XContextBadVPN	S_XContextBadVPN2
+
+#define M_XContext0Fields	0x0000000f
+
+
+/*
+ ************************************************************************
+ *                 D E B U G   R E G I S T E R   ( 2 3 )                *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |D|D|N|L|D|H|C|I|M|C|D|I|D|D|     |         |N|S|   |D|D|D|D|D|D|
+ * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S|   |I|I|D|D|B|S|
+ * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver |         |S|t|   |N|B|B|B|p|S|
+ * | | |C|M|e|t|n|s|e|h|s|I|S|L|     |         |S| | 0 |T| |S|L| | | Debug
+ * | | |R| | | |t|E|c|e|E| |I|I|     |         |t| |   | | | | | | |
+ * | | | | | | |D|P|k|E|P| |m|m|     |         | | |   | | | | | | |
+ * | | | | | | |M| |P|P| | |p|p|     |         | | |   | | | | | | |
+ * | | | | | | | | | | | | |r|r|     |         | | |   | | | | | | |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_Debug		$23	/* EJTAG */
+#define R_C0_Debug		23
+
+#define S_DebugDBD		31			/* Debug branch delay (R) */
+#define M_DebugDBD		(0x1 << S_DebugDBD)
+#define S_DebugDM		30			/* Debug mode (R) */
+#define M_DebugDM		(0x1 << S_DebugDM)
+#define S_DebugNoDCR		29			/* No debug control register present (R) */
+#define M_DebugNoDCR		(0x1 << S_DebugNoDCR)
+#define S_DebugLSNM		28			/* Load/Store Normal Memory (R/W) */
+#define M_DebugLSNM		(0x1 << S_DebugLSNM)
+#define S_DebugDoze		27			/* Doze (R) */
+#define M_DebugDoze		(0x1 << S_DebugDoze)
+#define S_DebugHalt		26			/* Halt (R) */
+#define M_DebugHalt		(0x1 << S_DebugHalt)
+#define S_DebugCountDM		25			/* Count register behavior in debug mode (R/W) */
+#define M_DebugCountDM		(0x1 << S_DebugCountDM)
+#define S_DebugIBusEP		24			/* Imprecise Instn Bus Error Pending (R/W) */
+#define M_DebugIBusEP		(0x1 << S_DebugIBusEP)
+#define S_DebugMCheckP		23			/* Imprecise Machine Check Pending (R/W) */
+#define M_DebugMCheckP		(0x1 << S_DebugMCheckP)
+#define S_DebugCacheEP		22			/* Imprecise Cache Error Pending (R/W) */
+#define M_DebugCacheEP		(0x1 << S_DebugCacheEP)
+#define S_DebugDBusEP		21			/* Imprecise Data Bus Error Pending (R/W) */
+#define M_DebugDBusEP		(0x1 << S_DebugDBusEP)
+#define S_DebugIEXI		20			/* Imprecise Exception Inhibit (R/W) */
+#define M_DebugIEXI		(0x1 << S_DebugIEXI)
+#define S_DebugDDBSImpr		19			/* Debug data break store imprecise (R) */
+#define M_DebugDDBSImpr		(0x1 << S_DebugDDBSImpr)
+#define S_DebugDDBLImpr		18			/* Debug data break load imprecise (R) */
+#define M_DebugDDBLImpr		(0x1 << S_DebugDDBLImpr)
+#define S_DebugEJTAGver		15			/* EJTAG version number (R) */
+#define M_DebugEJTAGver		(0x7 << S_DebugEJTAGver)
+#define S_DebugDExcCode		10			/* Debug exception code (R) */
+#define M_DebugDExcCode		(0x1f << S_DebugDExcCode)
+#define S_DebugNoSSt		9			/* No single step implemented (R) */
+#define M_DebugNoSSt		(0x1 << S_DebugNoSSt)
+#define S_DebugSSt		8			/* Single step enable (R/W) */
+#define M_DebugSSt		(0x1 << S_DebugSSt)
+#define S_DebugDINT		5			/* Debug interrupt (R) */
+#define M_DebugDINT		(0x1 << S_DebugDINT)
+#define S_DebugDIB		4			/* Debug instruction break (R) */
+#define M_DebugDIB		(0x1 << S_DebugDIB)
+#define S_DebugDDBS		3			/* Debug data break store (R) */
+#define M_DebugDDBS		(0x1 << S_DebugDDBS)
+#define S_DebugDDBL		2			/* Debug data break load (R) */
+#define M_DebugDDBL		(0x1 << S_DebugDDBL)
+#define S_DebugDBp		1			/* Debug breakpoint (R) */
+#define M_DebugDBp		(0x1 << S_DebugDBp)
+#define S_DebugDSS		0			/* Debug single step (R) */
+#define M_DebugDSS		(0x1 << S_DebugDSS)
+
+#define M_Debug0Fields	0x01f000c0
+#define M_DebugRFields	0xec0ffe3f
+
+
+/*
+ ************************************************************************
+ *                 D E P C   R E G I S T E R   ( 2 4 )                  *
+ ************************************************************************
+ *
+ *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  //                  EJTAG Debug Exception PC                      | DEPC
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+
+#define C0_DEPC			$24
+#define R_C0_DEPC		24
+
+#define M_DEEPC0Fields		0x00000000
+#define M_DEEPCRFields		0x00000000
+#define M_DEEPC0Fields64	UNS64Const(0x0000000000000000)
+#define M_DEEPCRFields64	UNS64Const(0x0000000000000000)
+
+
+/*
+ ************************************************************************
+ *              P E R F C N T   R E G I S T E R   ( 2 5 )               *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | |                                       |           |I| | | |E|
+ * |M|                    0                  |   Event   |E|U|S|K|X| PerfCnt
+ * | |                                       |           | | | | |L|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                          Event Count                          | PerfCnt
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_PerfCnt		$25
+#define R_C0_PerfCnt		25
+#define C0_PRFCNT0		C0_PerfCnt		/* OBSOLETE - DO NOT USE IN NEW CODE */
+#define C0_PRFCNT1		C0_PerfCnt		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define S_PerfCntM		31			/* More performance counters exist (R) */
+#define M_PerfCntM		(1 << S_PerfCntM)
+#define S_PerfCntEvent		5			/* Enabled event (R/W) */
+#define M_PerfCntEvent		(0x3f << S_PerfCntEvent)
+#define S_PerfCntIE		4			/* Interrupt Enable (R/W) */
+#define M_PerfCntIE		(1 << S_PerfCntIE)
+#define S_PerfCntU		3			/* Enable counting in User Mode (R/W) */
+#define M_PerfCntU		(1 << S_PerfCntU)
+#define S_PerfCntS		2			/* Enable counting in Supervisor Mode (R/W) */
+#define M_PerfCntS		(1 << S_PerfCntS)
+#define S_PerfCntK		1			/* Enable counting in Kernel Mode (R/W) */
+#define M_PerfCntK		(1 << S_PerfCntK)
+#define S_PerfCntEXL		0			/* Enable counting while EXL==1 (R/W) */
+#define M_PerfCntEXL		(1 << S_PerfCntEXL)
+
+#define M_PerfCnt0Fields	0x7ffff800
+#define M_PerfCntRFields	0x80000000
+
+
+/*
+ ************************************************************************
+ *               E R R C T L   R E G I S T E R   ( 2 6 )                *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                        Error Control                          | ErrCtl
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_ErrCtl		$26
+#define R_C0_ErrCtl		26
+#define C0_ECC			$26		/* OBSOLETE - DO NOT USE IN NEW CODE */
+#define R_C0_ECC		26		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_ErrCtl0Fields		0x00000000
+#define M_ErrCtlRFields		0x00000000
+
+
+/*
+ ************************************************************************
+ *             C A C H E E R R   R E G I S T E R   ( 2 7 )              * CacheErr
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                     Cache Error Control                       | CacheErr
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_CacheErr		$27
+#define R_C0_CacheErr		27
+#define C0_CACHE_ERR		C0_CacheErr		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_CacheErr0Fields	0x00000000
+#define M_CachErrRFields	0x00000000
+
+
+/*
+ ************************************************************************
+ *                T A G L O   R E G I S T E R   ( 2 8 )                 * TagLo
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                            TagLo                              | TagLo
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_TagLo		$28
+#define R_C0_TagLo		28
+#define C0_TAGLO		C0_TagLo		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+/*
+ * Some implementations use separate TagLo registers for the
+ * instruction and data caches.  In those cases, the following
+ * definitions can be used in relevant code
+ */
+
+#define C0_ITagLo		$28,0
+#define C0_DTagLo		$28,2
+
+#define M_TagLo0Fields		0x00000000
+#define M_TagLoRFields		0x00000000
+
+
+/*
+ ************************************************************************
+ *        D A T A L O   R E G I S T E R   ( 2 8, SELECT 1 )             * DataLo
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                           DataLo                              | DataLo
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_DataLo		$28,1
+#define R_C0_DataLo		28
+
+/*
+ * Some implementations use separate DataLo registers for the
+ * instruction and data caches.  In those cases, the following
+ * definitions can be used in relevant code
+ */
+
+#define C0_IDataLo		$28,1
+#define C0_DDataLo		$28,3
+
+#define M_DataLo0Fields		0x00000000
+#define M_DataLoRFields		0xffffffff
+
+
+/*
+ ************************************************************************
+ *                T A G H I   R E G I S T E R   ( 2 9 )                 * TagHi
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                            TagHi                              | TagHi
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_TagHi		$29
+#define R_C0_TagHi		29
+#define C0_TAGHI		C0_TagHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+/*
+ * Some implementations use separate TagHi registers for the
+ * instruction and data caches.  In those cases, the following
+ * definitions can be used in relevant code
+ */
+
+#define C0_ITagHi		$29,0
+#define C0_DTagHi		$29,2
+
+#define M_TagHi0Fields		0x00000000
+#define M_TagHiRFields		0x00000000
+
+
+/*
+ ************************************************************************
+ *        D A T A H I   R E G I S T E R   ( 2 9, SELECT 1 )             * DataHi
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                           DataHi                              | DataHi
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_DataHi		$29,1
+#define R_C0_DataHi		29
+
+/*
+ * Some implementations use separate DataHi registers for the
+ * instruction and data caches.  In those cases, the following
+ * definitions can be used in relevant code
+ */
+
+#define C0_IDataHi		$29,1
+#define C0_DDataHi		$29,3
+
+#define M_DataHi0Fields		0x00000000
+#define M_DataHiRFields		0xffffffff
+
+
+/*
+ ************************************************************************
+ *            E R R O R E P C   R E G I S T E R   ( 3 0 )               *
+ ************************************************************************
+ *
+ *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  //                          Error PC                              | ErrorEPC
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_ErrorEPC		$30
+#define R_C0_ErrorEPC		30
+#define C0_ERROR_EPC		C0_ErrorEPC		/* OBSOLETE - DO NOT USE IN NEW CODE */
+
+#define M_ErrorEPC0Fields	0x00000000
+#define M_ErrorEPCRFields	0x00000000
+#define M_ErrorEPC0Fields64	UNS64Const(0x0000000000000000)
+#define M_ErrorEPCRFields64	UNS64Const(0x0000000000000000)
+
+
+/*
+ ************************************************************************
+ *            D E S A V E   R E G I S T E R   ( 3 1 )                   *
+ ************************************************************************
+ *
+ *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |  //                   EJTAG Register Save Value                    | DESAVE
+ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C0_DESAVE		$31
+#define R_C0_DESAVE		31
+
+#define M_DESAVE0Fields		0x00000000
+#define M_DESAVERFields		0x00000000
+#define M_DESAVE0Fields64	UNS64Const(0x0000000000000000)
+#define M_DESAVERFields64	UNS64Const(0x0000000000000000)
+
+
+/*
+ *************************************************************************
+ *             C P 1   R E G I S T E R   D E F I N I T I O N S           *
+ *************************************************************************
+ */
+
+
+/*
+ *************************************************************************
+ *                  H A R D W A R E   F P R   N A M E S                  *
+ *************************************************************************
+ */
+
+#define fp0			$f0
+#define fp1			$f1
+#define fp2			$f2
+#define fp3			$f3
+#define fp4			$f4
+#define fp5			$f5
+#define fp6			$f6
+#define fp7			$f7
+#define fp8			$f8
+#define fp9			$f9
+#define fp10			$f10
+#define fp11			$f11
+#define fp12			$f12
+#define fp13			$f13
+#define fp14			$f14
+#define fp15			$f15
+#define fp16			$f16
+#define fp17			$f17
+#define fp18			$f18
+#define fp19			$f19
+#define fp20			$f20
+#define fp21			$f21
+#define fp22			$f22
+#define fp23			$f23
+#define fp24			$f24
+#define fp25			$f25
+#define fp26			$f26
+#define fp27			$f27
+#define fp28			$f28
+#define fp29			$f29
+#define fp30			$f30
+#define fp31			$f31
+
+/*
+ * The following definitions are used to convert an FPR name
+ * into the corresponding even or odd name, respectively.
+ * This is used in macro substitution in the AVPs.
+ */
+
+#define fp1_even		$f0
+#define fp3_even		$f2
+#define fp5_even		$f4
+#define fp7_even		$f6
+#define fp9_even		$f8
+#define fp11_even		$f10
+#define fp13_even		$f12
+#define fp15_even		$f14
+#define fp17_even		$f16
+#define fp19_even		$f18
+#define fp21_even		$f20
+#define fp23_even		$f22
+#define fp25_even		$f24
+#define fp27_even		$f26
+#define fp29_even		$f28
+#define fp31_even		$f30
+
+#define fp0_odd			$f1
+#define fp2_odd			$f3
+#define fp4_odd			$f5
+#define fp6_odd			$f7
+#define fp8_odd			$f9
+#define fp10_odd		$f11
+#define fp12_odd		$f13
+#define fp14_odd		$f15
+#define fp16_odd		$f17
+#define fp18_odd		$f19
+#define fp20_odd		$f21
+#define fp22_odd		$f23
+#define fp24_odd		$f25
+#define fp26_odd		$f27
+#define fp28_odd		$f29
+#define fp30_odd		$f31
+
+
+/*
+ *************************************************************************
+ *                H A R D W A R E   F P R   I N D I C E S                *
+ *************************************************************************
+ *
+ * These definitions provide the index (number) of the FPR, as opposed
+ * to the assembler register name ($n).
+ */
+
+#define R_fp0			 0
+#define R_fp1			 1
+#define R_fp2			 2
+#define R_fp3			 3
+#define R_fp4			 4
+#define R_fp5			 5
+#define R_fp6			 6
+#define R_fp7			 7
+#define R_fp8			 8
+#define R_fp9			 9
+#define R_fp10			10
+#define R_fp11			11
+#define R_fp12			12
+#define R_fp13			13
+#define R_fp14			14
+#define R_fp15			15
+#define R_fp16			16
+#define R_fp17			17
+#define R_fp18			18
+#define R_fp19			19
+#define R_fp20			20
+#define R_fp21			21
+#define R_fp22			22
+#define R_fp23			23
+#define R_fp24			24
+#define R_fp25			25
+#define R_fp26			26
+#define R_fp27			27
+#define R_fp28			28
+#define R_fp29			29
+#define R_fp30			30
+#define R_fp31			31
+
+
+/*
+ *************************************************************************
+ *                  H A R D W A R E   F C R   N A M E S                  *
+ *************************************************************************
+ */
+
+#define fc0			$0
+#define fc25			$25
+#define fc26			$26
+#define fc28			$28
+#define fc31			$31
+
+
+/*
+ *************************************************************************
+ *                H A R D W A R E   F C R   I N D I C E S                *
+ *************************************************************************
+ *
+ * These definitions provide the index (number) of the FCR, as opposed
+ * to the assembler register name ($n).
+ */
+
+#define R_fc0			 0
+#define R_fc25			25
+#define R_fc26			26
+#define R_fc28			28
+#define R_fc31			31
+
+
+/*
+ *************************************************************************
+ *                  H A R D W A R E   F C C   N A M E S                  *
+ *************************************************************************
+ */
+
+#define cc0			$fcc0
+#define cc1			$fcc1
+#define cc2			$fcc2
+#define cc3			$fcc3
+#define cc4			$fcc4
+#define cc5			$fcc5
+#define cc6			$fcc6
+#define cc7			$fcc7
+
+
+/*
+ *************************************************************************
+ *                H A R D W A R E   F C C   I N D I C E S                *
+ *************************************************************************
+ *
+ * These definitions provide the index (number) of the CC, as opposed
+ * to the assembler register name ($n).
+ */
+
+#define R_cc0			0
+#define R_cc1			1
+#define R_cc2			2
+#define R_cc3			3
+#define R_cc4			4
+#define R_cc5			5
+#define R_cc6			6
+#define R_cc7			7
+
+
+/*
+ ************************************************************************
+ *             I M P L E M E N T A T I O N   R E G I S T E R            *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |Reserved for Additional|3|P|D|S| Implementation|   Revision    | FIR
+ * |  Configuration Bits   |D|S| | |               |               |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FIR			$0
+#define R_C1_FIR			0
+
+#define S_FIRConfigS		16
+#define M_FIRConfigS		(0x1 << S_FIRConfigS)
+#define S_FIRConfigD		17
+#define M_FIRConfigD		(0x1 << S_FIRConfigD)
+#define S_FIRConfigPS		18
+#define M_FIRConfigPS   	(0x1 << S_FIRConfigPS)
+#define S_FIRConfig3D		19
+#define M_FIRConfig3D		(0x1 << S_FIRConfig3D)
+#define M_FIRConfigAll		(M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D)
+
+#define S_FIRImp		8
+#define M_FIRImp		(0xff << S_FIRImp)
+
+#define S_FIRRev		0
+#define M_FIRRev		(0xff << S_FIRRev)
+
+#define M_FIR0Fields		0xfff00000
+#define M_FIRRFields		0x000fffff
+
+/*
+ ************************************************************************
+ *          C O N D I T I O N   C O D E S   R E G I S T E R             *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                      0                        |      CC       | FCCR
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FCCR			$25
+#define R_C1_FCCR		25
+
+#define S_FCCRCC		0
+#define M_FCCRCC		(0xff << S_FCCRCC)
+#define S_FCCRCC7		7
+#define M_FCCRCC7		(0x1 << S_FCCRCC7)
+#define S_FCCRCC6		6
+#define M_FCCRCC6		(0x1 << S_FCCRCC6)
+#define S_FCCRCC5		5
+#define M_FCCRCC5		(0x1 << S_FCCRCC5)
+#define S_FCCRCC4		4
+#define M_FCCRCC4		(0x1 << S_FCCRCC4)
+#define S_FCCRCC3		3
+#define M_FCCRCC3		(0x1 << S_FCCRCC3)
+#define S_FCCRCC2		2
+#define M_FCCRCC2		(0x1 << S_FCCRCC2)
+#define S_FCCRCC1		1
+#define M_FCCRCC1		(0x1 << S_FCCRCC1)
+#define S_FCCRCC0		0
+#define M_FCCRCC0		(0x1 << S_FCCRCC0)
+
+#define M_FCCR0Fields		0xffffff00
+#define M_FCCRRFields		0x000000ff
+
+
+/*
+ ************************************************************************
+ *                 E X C E P T I O N S   R E G I S T E R                *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |             0             |   Cause   |    0    |  Flags  | 0 | FEXR
+ * |                           |E|V|Z|O|U|I|         |V|Z|O|U|I|   |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FEXR			$26
+#define R_C1_FEXR		26
+
+#define S_FEXRExc		12
+#define M_FEXRExc		(0x3f << S_FEXRExc)
+#define S_FEXRExcE		17
+#define M_FEXRExcE		(0x1 << S_FEXRExcE)
+#define S_FEXRExcV		16
+#define M_FEXRExcV		(0x1 << S_FEXRExcV)
+#define S_FEXRExcZ		15
+#define M_FEXRExcZ		(0x1 << S_FEXRExcZ)
+#define S_FEXRExcO		14
+#define M_FEXRExcO		(0x1 << S_FEXRExcO)
+#define S_FEXRExcU		13
+#define M_FEXRExcU		(0x1 << S_FEXRExcU)
+#define S_FEXRExcI		12
+#define M_FEXRExcI		(0x1 << S_FEXRExcI)
+
+#define S_FEXRFlg		2
+#define M_FEXRFlg		(0x1f << S_FEXRFlg)
+#define S_FEXRFlgV		6
+#define M_FEXRFlgV		(0x1 << S_FEXRFlgV)
+#define S_FEXRFlgZ		5
+#define M_FEXRFlgZ		(0x1 << S_FEXRFlgZ)
+#define S_FEXRFlgO		4
+#define M_FEXRFlgO		(0x1 << S_FEXRFlgO)
+#define S_FEXRFlgU		3
+#define M_FEXRFlgU		(0x1 << S_FEXRFlgU)
+#define S_FEXRFlgI		2
+#define M_FEXRFlgI		(0x1 << S_FEXRFlgI)
+
+#define M_FEXR0Fields		0xfffc0f83
+#define M_FEXRRFields		0x00000000
+
+
+/*
+ ************************************************************************
+ *                    E N A B L E S   R E G I S T E R                   *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |                   0                   | Enables |   0   |F|RM | FENR
+ * |                                       |V|Z|O|U|I|       |S|   |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FENR			$28
+#define R_C1_FENR		28
+
+#define S_FENREna		7
+#define M_FENREna		(0x1f << S_FENREna)
+#define S_FENREnaV		11
+#define M_FENREnaV		(0x1 << S_FENREnaV)
+#define S_FENREnaZ		10
+#define M_FENREnaZ		(0x1 << S_FENREnaZ)
+#define S_FENREnaO		9
+#define M_FENREnaO		(0x1 << S_FENREnaO)
+#define S_FENREnaU		8
+#define M_FENREnaU		(0x1 << S_FENREnaU)
+#define S_FENREnaI		7
+#define M_FENREnaI		(0x1 << S_FENREnaI)
+
+#define S_FENRFS		2
+#define M_FENRFS		(0x1 << S_FENRFS)
+
+#define S_FENRRM		0
+#define M_FENRRM		(0x3 << S_FENRRM)
+
+#define M_FENR0Fields		0xfffff078
+#define M_FENRRFields		0x00000000
+
+
+/*
+ ************************************************************************
+ *           C O N T R O L  /  S T A T U S   R E G I S T E R            *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |     FCC     |F|C|Imp|  0  |   Cause   | Enables |  Flags  | RM| FCSR
+ * |7|6|5|4|3|2|1|S|C|   |     |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I|   |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define C1_FCSR			$31
+#define R_C1_FCSR		31
+
+#define S_FCSRFCC7_1		25			/* Floating point condition codes 7..1 (R/W) */
+#define M_FCSRFCC7_1		(0x7f << S_FCSRFCC7_1)
+#define S_FCSRCC7		31
+#define M_FCSRCC7		(0x1 << S_FCSRCC7)
+#define S_FCSRCC6		30
+#define M_FCSRCC6		(0x1 << S_FCSRCC6)
+#define S_FCSRCC5		29
+#define M_FCSRCC5		(0x1 << S_FCSRCC5)
+#define S_FCSRCC4		28
+#define M_FCSRCC4		(0x1 << S_FCSRCC4)
+#define S_FCSRCC3		27
+#define M_FCSRCC3		(0x1 << S_FCSRCC3)
+#define S_FCSRCC2		26
+#define M_FCSRCC2		(0x1 << S_FCSRCC2)
+#define S_FCSRCC1		25
+#define M_FCSRCC1		(0x1 << S_FCSRCC1)
+
+#define S_FCSRFS		24			/* Flush denorms to zero (R/W) */
+#define M_FCSRFS		(0x1 << S_FCSRFS)
+
+#define S_FCSRCC0		23			/* Floating point condition code 0 (R/W) */
+#define M_FCSRCC0		(0x1 << S_FCSRCC0)
+#define S_FCSRCC		S_FCSRCC0
+#define M_FCSRCC		M_FCSRCC0
+
+#define S_FCSRImpl		21			/* Implementation-specific control bits (R/W) */
+#define M_FCSRImpl		(0x3 << S_FCSRImpl)
+
+#define S_FCSRExc		12			/* Exception cause (R/W) */
+#define M_FCSRExc		(0x3f << S_FCSRExc)
+#define S_FCSRExcE		17
+#define M_FCSRExcE		(0x1 << S_FCSRExcE)
+#define S_FCSRExcV		16
+#define M_FCSRExcV		(0x1 << S_FCSRExcV)
+#define S_FCSRExcZ		15
+#define M_FCSRExcZ		(0x1 << S_FCSRExcZ)
+#define S_FCSRExcO		14
+#define M_FCSRExcO		(0x1 << S_FCSRExcO)
+#define S_FCSRExcU		13
+#define M_FCSRExcU		(0x1 << S_FCSRExcU)
+#define S_FCSRExcI		12
+#define M_FCSRExcI		(0x1 << S_FCSRExcI)
+
+#define S_FCSREna		7			/* Exception enable (R/W) */
+#define M_FCSREna		(0x1f << S_FCSREna)
+#define S_FCSREnaV		11
+#define M_FCSREnaV		(0x1 << S_FCSREnaV)
+#define S_FCSREnaZ		10
+#define M_FCSREnaZ		(0x1 << S_FCSREnaZ)
+#define S_FCSREnaO		9
+#define M_FCSREnaO		(0x1 << S_FCSREnaO)
+#define S_FCSREnaU		8
+#define M_FCSREnaU		(0x1 << S_FCSREnaU)
+#define S_FCSREnaI		7
+#define M_FCSREnaI		(0x1 << S_FCSREnaI)
+
+#define S_FCSRFlg		2			/* Exception flags (R/W) */
+#define M_FCSRFlg		(0x1f << S_FCSRFlg)
+#define S_FCSRFlgV		6
+#define M_FCSRFlgV		(0x1 << S_FCSRFlgV)
+#define S_FCSRFlgZ		5
+#define M_FCSRFlgZ		(0x1 << S_FCSRFlgZ)
+#define S_FCSRFlgO		4
+#define M_FCSRFlgO		(0x1 << S_FCSRFlgO)
+#define S_FCSRFlgU		3
+#define M_FCSRFlgU		(0x1 << S_FCSRFlgU)
+#define S_FCSRFlgI		2
+#define M_FCSRFlgI		(0x1 << S_FCSRFlgI)
+
+#define S_FCSRRM		0			/* Rounding mode (R/W) */
+#define M_FCSRRM		(0x3 << S_FCSRRM)
+
+#define M_FCSR0Fields		0x001c0000
+#define M_FCSRRFields		0x00000000
+
+/*
+ * Values in the rounding mode field (of both FCSR and FCCR)
+ */
+#define K_FCSRRM_RN		0
+#define K_FCSRRM_RZ		1
+#define K_FCSRRM_RP		2
+#define K_FCSRRM_RM		3
+
+#endif /* _COMMON_MIPS_DEF_H_ */
diff --git a/bsp/x1000/cpu/common/mips_excpt.h b/bsp/x1000/cpu/common/mips_excpt.h
new file mode 100644
index 0000000000..868b046d3c
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_excpt.h
@@ -0,0 +1,39 @@
+/*
+ * File      : mips_excpt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��7��     Urey         the first version
+ */
+
+#ifndef _MIPS_EXCPT_H_
+#define _MIPS_EXCPT_H_
+
+#include "mips_regs.h"
+
+#ifndef __ASSEMBLY__
+typedef void (* exception_func_t)(mips_reg_ctx *regs);
+
+//extern exception_func_t mips_exception_handlers[];
+
+int rt_hw_exception_init(void);
+exception_func_t rt_set_except_vector(int n, exception_func_t func);
+void install_default_execpt_handle(void);
+#endif /* __ASSEMBLY__ */
+#endif /* _MIPS_EXCPT_H_ */
diff --git a/bsp/x1000/cpu/common/mips_regs.h b/bsp/x1000/cpu/common/mips_regs.h
new file mode 100644
index 0000000000..7ea07d3869
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_regs.h
@@ -0,0 +1,1168 @@
+/*
+ * File      : mips_regs.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��7��     Urey         the first version
+ */
+
+#ifndef _MIPS_REGS_H_
+#define _MIPS_REGS_H_
+
+
+#if !defined(__ASSEMBLY__) && !defined(ASSEMBLY)
+#include <rtdef.h>
+
+#define MIPS_REG_NR             32
+typedef struct {
+    rt_uint32_t  regs[MIPS_REG_NR];                             	/*  32 ��ͨ��Ŀ�ļĴ���         */
+    rt_uint32_t  CP0Status;                                        	/*  CP0 Э������״̬�Ĵ���      */
+    rt_uint32_t  CP0DataHI;                                        	/*  ������λ�Ĵ���              */
+    rt_uint32_t  CP0DataLO;                                        	/*  ������λ�Ĵ���              */
+    rt_uint32_t  CP0BadVAddr;                                      	/*  ������ַ�Ĵ���              */
+    rt_uint32_t  CP0Cause;                                         	/*  �����жϻ����쳣�鿴�ļĴ���*/
+    rt_uint32_t  CP0EPC;                                           	/*  ����������Ĵ���			*/
+} mips_reg_ctx;
+
+#define MIPS_ARG_REG_NR         4
+typedef struct
+{
+	rt_uint32_t  args[MIPS_ARG_REG_NR];                              /*  4 �������Ĵ���              */
+} mips_arg_ctx;
+
+struct linkctx
+{
+	rt_uint32_t id;
+	struct linkctx *next;
+};
+
+struct fpctx
+{
+  struct linkctx link;
+  rt_uint32_t fcsr;
+  rt_uint32_t reserved;
+};
+
+
+struct fp32ctx
+{
+  struct fpctx fp;
+  union
+    {
+      double d[16];	/* even doubles */
+      float s[32];	/* even singles, padded */
+    };
+};
+
+struct fp64ctx
+{
+  struct fpctx fp;
+  union
+    {
+      double d[32];	/* even doubles, followed by odd doubles */
+      float s[64];	/* even singles, followed by odd singles, padded */
+    };
+};
+
+#endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */
+
+#define MIPS_STK_CTX_WORD_SIZE			38
+#define SZREG			4
+/*********************************************************************************************************
+  MIPS �ļĴ�������
+*********************************************************************************************************/
+#define REG_ZERO                0                                       /*  wired zero                  */
+#define REG_AT                  1                                       /*  assembler temp              */
+#define REG_V0                  2                                       /*  return reg 0                */
+#define REG_V1                  3                                       /*  return reg 1                */
+#define REG_A0                  4                                       /*  arg reg 0                   */
+#define REG_A1                  5                                       /*  arg reg 1                   */
+#define REG_A2                  6                                       /*  arg reg 2                   */
+#define REG_A3                  7                                       /*  arg reg 3                   */
+#define REG_T0                  8                                       /*  caller saved 0              */
+#define REG_T1                  9                                       /*  caller saved 1              */
+#define REG_T2                  10                                      /*  caller saved 2              */
+#define REG_T3                  11                                      /*  caller saved 3              */
+#define REG_T4                  12                                      /*  caller saved 4              */
+#define REG_T5                  13                                      /*  caller saved 5              */
+#define REG_T6                  14                                      /*  caller saved 6              */
+#define REG_T7                  15                                      /*  caller saved 7              */
+#define REG_S0                  16                                      /*  callee saved 0              */
+#define REG_S1                  17                                      /*  callee saved 1              */
+#define REG_S2                  18                                      /*  callee saved 2              */
+#define REG_S3                  19                                      /*  callee saved 3              */
+#define REG_S4                  20                                      /*  callee saved 4              */
+#define REG_S5                  21                                      /*  callee saved 5              */
+#define REG_S6                  22                                      /*  callee saved 6              */
+#define REG_S7                  23                                      /*  callee saved 7              */
+#define REG_T8                  24                                      /*  caller saved 8              */
+#define REG_T9                  25                                      /*  caller saved 9              */
+#define REG_K0                  26                                      /*  kernel temp 0               */
+#define REG_K1                  27                                      /*  kernel temp 1               */
+#define REG_GP                  28                                      /*  global pointer              */
+#define REG_SP                  29                                      /*  stack pointer               */
+#define REG_S8                  30                                      /*  callee saved 8              */
+#define REG_FP                  REG_S8                                  /*  callee saved 8              */
+#define REG_RA                  31                                      /*  return address              */
+
+#define STK_CTX_SIZE            (MIPS_STK_CTX_WORD_SIZE * SZREG)
+#define STK_OFFSET_SR           ((32 + 0) * SZREG)
+#define STK_OFFSET_HI           ((32 + 1) * SZREG)
+#define STK_OFFSET_LO           ((32 + 2) * SZREG)
+#define STK_OFFSET_BADVADDR     ((32 + 3) * SZREG)
+#define STK_OFFSET_CAUSE        ((32 + 4) * SZREG)
+#define STK_OFFSET_EPC          ((32 + 5) * SZREG)
+
+#define STK_OFFSET_LAST         ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG)
+
+#define FP32CTX_CSR	((SZREG)*2)
+#define FP64CTX_CSR	((SZREG)*2)
+
+#define LINKCTX_ID      ((SZREG)*0)
+#define LINKCTX_NEXT    ((SZREG)*1)
+#define LINKCTX_TYPE_MSA        0x004D5341
+#define LINKCTX_TYPE_FP32       0x46503332
+#define LINKCTX_TYPE_FP64       0x46503634
+#define LINKCTX_TYPE_FMSA       0x463D5341
+#define LINKCTX_TYPE_DSP        0x00445350
+#define LINKCTX_TYPE_STKSWP     0x53574150
+#define LINKCTX_TYPE_XPA	0x00585041
+
+#define FP32CTX_0	((SZREG)*4)
+#define FP32CTX_2	(FP32CTX_0 + (1 * 8))
+#define FP32CTX_4	(FP32CTX_0 + (2 * 8))
+#define FP32CTX_6	(FP32CTX_0 + (3 * 8))
+#define FP32CTX_8	(FP32CTX_0 + (4 * 8))
+#define FP32CTX_10	(FP32CTX_0 + (5 * 8))
+#define FP32CTX_12	(FP32CTX_0 + (6 * 8))
+#define FP32CTX_14	(FP32CTX_0 + (7 * 8))
+#define FP32CTX_16	(FP32CTX_0 + (8 * 8))
+#define FP32CTX_18	(FP32CTX_0 + (9 * 8))
+#define FP32CTX_20	(FP32CTX_0 + (10 * 8))
+#define FP32CTX_22	(FP32CTX_0 + (11 * 8))
+#define FP32CTX_24	(FP32CTX_0 + (12 * 8))
+#define FP32CTX_26	(FP32CTX_0 + (13 * 8))
+#define FP32CTX_28	(FP32CTX_0 + (14 * 8))
+#define FP32CTX_30	(FP32CTX_0 + (15 * 8))
+#define FP32CTX_SIZE	(FP32CTX_30 + (17 * 8))
+
+#define FP64CTX_0	((SZREG)*4)
+#define FP64CTX_2	(FP64CTX_0 + (1 * 8))
+#define FP64CTX_4	(FP64CTX_0 + (2 * 8))
+#define FP64CTX_6	(FP64CTX_0 + (3 * 8))
+#define FP64CTX_8	(FP64CTX_0 + (4 * 8))
+#define FP64CTX_10	(FP64CTX_0 + (5 * 8))
+#define FP64CTX_12	(FP64CTX_0 + (6 * 8))
+#define FP64CTX_14	(FP64CTX_0 + (7 * 8))
+#define FP64CTX_16	(FP64CTX_0 + (8 * 8))
+#define FP64CTX_18	(FP64CTX_0 + (9 * 8))
+#define FP64CTX_20	(FP64CTX_0 + (10 * 8))
+#define FP64CTX_22	(FP64CTX_0 + (11 * 8))
+#define FP64CTX_24	(FP64CTX_0 + (12 * 8))
+#define FP64CTX_26	(FP64CTX_0 + (13 * 8))
+#define FP64CTX_28	(FP64CTX_0 + (14 * 8))
+#define FP64CTX_30	(FP64CTX_0 + (15 * 8))
+#define FP64CTX_1	(FP64CTX_30 + (1 * 8))
+#define FP64CTX_3	(FP64CTX_30 + (2 * 8))
+#define FP64CTX_5	(FP64CTX_30 + (3 * 8))
+#define FP64CTX_7	(FP64CTX_30 + (4 * 8))
+#define FP64CTX_9	(FP64CTX_30 + (5 * 8))
+#define FP64CTX_11	(FP64CTX_30 + (6 * 8))
+#define FP64CTX_13	(FP64CTX_30 + (7 * 8))
+#define FP64CTX_15	(FP64CTX_30 + (8 * 8))
+#define FP64CTX_17	(FP64CTX_30 + (9 * 8))
+#define FP64CTX_19	(FP64CTX_30 + (10 * 8))
+#define FP64CTX_21	(FP64CTX_30 + (11 * 8))
+#define FP64CTX_23	(FP64CTX_30 + (12 * 8))
+#define FP64CTX_25	(FP64CTX_30 + (13 * 8))
+#define FP64CTX_27	(FP64CTX_30 + (14 * 8))
+#define FP64CTX_29	(FP64CTX_30 + (15 * 8))
+#define FP64CTX_31	(FP64CTX_30 + (16 * 8))
+#define FP64CTX_SIZE	(FP64CTX_31 + (17 * 8))
+
+#define FPCTX_SIZE()	(mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE)
+
+/*
+ * The following macros are especially useful for __asm__
+ * inline assembler.
+ */
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ULCAST_
+#else
+#define _ULCAST_ (unsigned long)
+#endif
+
+/*
+ * Coprocessor 0 register names
+ */
+#define CP0_INDEX $0
+#define CP0_RANDOM $1
+#define CP0_ENTRYLO0 $2
+#define CP0_ENTRYLO1 $3
+#define CP0_CONF $3
+#define CP0_CONTEXT $4
+#define CP0_PAGEMASK $5
+#define CP0_WIRED $6
+#define CP0_INFO $7
+#define CP0_BADVADDR $8
+#define CP0_COUNT $9
+#define CP0_ENTRYHI $10
+#define CP0_COMPARE $11
+#define CP0_STATUS $12
+#define CP0_CAUSE $13
+#define CP0_EPC $14
+#define CP0_PRID $15
+#define CP0_CONFIG $16
+#define CP0_LLADDR $17
+#define CP0_WATCHLO $18
+#define CP0_WATCHHI $19
+#define CP0_XCONTEXT $20
+#define CP0_FRAMEMASK $21
+#define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
+#define CP0_PERFORMANCE $25
+#define CP0_ECC $26
+#define CP0_CACHEERR $27
+#define CP0_TAGLO $28
+#define CP0_TAGHI $29
+#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
+
+/*
+ * R4640/R4650 cp0 register names.  These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux.  A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE $0
+#define CP0_IBOUND $1
+#define CP0_DBASE $2
+#define CP0_DBOUND $3
+#define CP0_CALG $17
+#define CP0_IWATCH $18
+#define CP0_DWATCH $19
+
+/*
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+#define CP0_S1_INTCONTROL $20
+
+/*
+ *  TX39 Series
+ */
+#define CP0_TX39_CACHE	$7
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION   $0
+#define CP1_STATUS     $31
+
+/*
+ * FPU Status Register Values
+ */
+/*
+ * Status Register Values
+ */
+
+#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
+#define FPU_CSR_COND    0x00800000      /* $fcc0 */
+#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
+#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
+#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
+#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
+#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
+#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
+#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
+#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X   0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
+
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
+
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
+
+/* rounding mode */
+#define FPU_CSR_RN      0x0     /* nearest */
+#define FPU_CSR_RZ      0x1     /* towards zero */
+#define FPU_CSR_RU      0x2     /* towards +Infinity */
+#define FPU_CSR_RD      0x3     /* towards -Infinity */
+
+
+/*
+ * Values for PageMask register
+ */
+#ifdef CONFIG_CPU_VR41XX
+
+/* Why doesn't stupidity hurt ... */
+
+#define PM_1K		0x00000000
+#define PM_4K		0x00001800
+#define PM_16K		0x00007800
+#define PM_64K		0x0001f800
+#define PM_256K		0x0007f800
+
+#else
+
+#define PM_4K		0x00000000
+#define PM_16K		0x00006000
+#define PM_64K		0x0001e000
+#define PM_256K		0x0007e000
+#define PM_1M		0x001fe000
+#define PM_4M		0x007fe000
+#define PM_16M		0x01ffe000
+#define PM_64M		0x07ffe000
+#define PM_256M		0x1fffe000
+
+#endif
+
+/*
+ * Values used for computation of new tlb entries
+ */
+#define PL_4K		12
+#define PL_16K		14
+#define PL_64K		16
+#define PL_256K		18
+#define PL_1M		20
+#define PL_4M		22
+#define PL_16M		24
+#define PL_64M		26
+#define PL_256M		28
+
+/*
+ * R4x00 interrupt enable / cause bits
+ */
+#define IE_SW0          (_ULCAST_(1) <<  8)
+#define IE_SW1          (_ULCAST_(1) <<  9)
+#define IE_IRQ0         (_ULCAST_(1) << 10)
+#define IE_IRQ1         (_ULCAST_(1) << 11)
+#define IE_IRQ2         (_ULCAST_(1) << 12)
+#define IE_IRQ3         (_ULCAST_(1) << 13)
+#define IE_IRQ4         (_ULCAST_(1) << 14)
+#define IE_IRQ5         (_ULCAST_(1) << 15)
+
+/*
+ * R4x00 interrupt cause bits
+ */
+#define C_SW0           (_ULCAST_(1) <<  8)
+#define C_SW1           (_ULCAST_(1) <<  9)
+#define C_IRQ0          (_ULCAST_(1) << 10)
+#define C_IRQ1          (_ULCAST_(1) << 11)
+#define C_IRQ2          (_ULCAST_(1) << 12)
+#define C_IRQ3          (_ULCAST_(1) << 13)
+#define C_IRQ4          (_ULCAST_(1) << 14)
+#define C_IRQ5          (_ULCAST_(1) << 15)
+
+/*
+ * Bitfields in the R4xx0 cp0 status register
+ */
+#define ST0_IE			0x00000001
+#define ST0_EXL			0x00000002
+#define ST0_ERL			0x00000004
+#define ST0_KSU			0x00000018
+#  define KSU_USER		0x00000010
+#  define KSU_SUPERVISOR	0x00000008
+#  define KSU_KERNEL		0x00000000
+#define ST0_UX			0x00000020
+#define ST0_SX			0x00000040
+#define ST0_KX 			0x00000080
+#define ST0_DE			0x00010000
+#define ST0_CE			0x00020000
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_IEC                 0x00000001
+#define ST0_KUC			0x00000002
+#define ST0_IEP			0x00000004
+#define ST0_KUP			0x00000008
+#define ST0_IEO			0x00000010
+#define ST0_KUO			0x00000020
+/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC			0x00010000
+#define ST0_SWC			0x00020000
+#define ST0_CM			0x00080000
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM			(_ULCAST_(1) <<  4)
+#define ST0_IL			(_ULCAST_(1) << 23)
+#define ST0_DL			(_ULCAST_(1) << 24)
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT	19
+#define TX39_CONF_ICS_MASK	0x00380000
+#define TX39_CONF_ICS_1KB 	0x00000000
+#define TX39_CONF_ICS_2KB 	0x00080000
+#define TX39_CONF_ICS_4KB 	0x00100000
+#define TX39_CONF_ICS_8KB 	0x00180000
+#define TX39_CONF_ICS_16KB 	0x00200000
+
+#define TX39_CONF_DCS_SHIFT	16
+#define TX39_CONF_DCS_MASK	0x00070000
+#define TX39_CONF_DCS_1KB 	0x00000000
+#define TX39_CONF_DCS_2KB 	0x00010000
+#define TX39_CONF_DCS_4KB 	0x00020000
+#define TX39_CONF_DCS_8KB 	0x00030000
+#define TX39_CONF_DCS_16KB 	0x00040000
+
+#define TX39_CONF_CWFON 	0x00004000
+#define TX39_CONF_WBON  	0x00002000
+#define TX39_CONF_RF_SHIFT	10
+#define TX39_CONF_RF_MASK	0x00000c00
+#define TX39_CONF_DOZE		0x00000200
+#define TX39_CONF_HALT		0x00000100
+#define TX39_CONF_LOCK		0x00000080
+#define TX39_CONF_ICE		0x00000020
+#define TX39_CONF_DCE		0x00000010
+#define TX39_CONF_IRSIZE_SHIFT	2
+#define TX39_CONF_IRSIZE_MASK	0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT	0
+#define TX39_CONF_DRSIZE_MASK	0x00000003
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define ST0_IM			0x0000ff00
+#define  STATUSB_IP0		8
+#define  STATUSF_IP0		(_ULCAST_(1) <<  8)
+#define  STATUSB_IP1		9
+#define  STATUSF_IP1		(_ULCAST_(1) <<  9)
+#define  STATUSB_IP2		10
+#define  STATUSF_IP2		(_ULCAST_(1) << 10)
+#define  STATUSB_IP3		11
+#define  STATUSF_IP3		(_ULCAST_(1) << 11)
+#define  STATUSB_IP4		12
+#define  STATUSF_IP4		(_ULCAST_(1) << 12)
+#define  STATUSB_IP5		13
+#define  STATUSF_IP5		(_ULCAST_(1) << 13)
+#define  STATUSB_IP6		14
+#define  STATUSF_IP6		(_ULCAST_(1) << 14)
+#define  STATUSB_IP7		15
+#define  STATUSF_IP7		(_ULCAST_(1) << 15)
+#define  STATUSB_IP8		0
+#define  STATUSF_IP8		(_ULCAST_(1) <<  0)
+#define  STATUSB_IP9		1
+#define  STATUSF_IP9		(_ULCAST_(1) <<  1)
+#define  STATUSB_IP10		2
+#define  STATUSF_IP10		(_ULCAST_(1) <<  2)
+#define  STATUSB_IP11		3
+#define  STATUSF_IP11		(_ULCAST_(1) <<  3)
+#define  STATUSB_IP12		4
+#define  STATUSF_IP12		(_ULCAST_(1) <<  4)
+#define  STATUSB_IP13		5
+#define  STATUSF_IP13		(_ULCAST_(1) <<  5)
+#define  STATUSB_IP14		6
+#define  STATUSF_IP14		(_ULCAST_(1) <<  6)
+#define  STATUSB_IP15		7
+#define  STATUSF_IP15		(_ULCAST_(1) <<  7)
+#define ST0_CH			0x00040000
+#define ST0_SR			0x00100000
+#define ST0_TS			0x00200000
+#define ST0_BEV			0x00400000
+#define ST0_RE			0x02000000
+#define ST0_FR			0x04000000
+#define ST0_CU			0xf0000000
+#define ST0_CU0			0x10000000
+#define ST0_CU1			0x20000000
+#define ST0_CU1_SHIFT			29
+#define ST0_CU2			0x40000000
+#define ST0_CU3			0x80000000
+#define ST0_XX			0x80000000	/* MIPS IV naming */
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 cause register.
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define  CAUSEB_EXCCODE		2
+#define  CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
+#define  CAUSEB_IP		8
+#define  CAUSEF_IP		(_ULCAST_(255) <<  8)
+#define  CAUSEB_IP0		8
+#define  CAUSEF_IP0		(_ULCAST_(1)   <<  8)
+#define  CAUSEB_IP1		9
+#define  CAUSEF_IP1		(_ULCAST_(1)   <<  9)
+#define  CAUSEB_IP2		10
+#define  CAUSEF_IP2		(_ULCAST_(1)   << 10)
+#define  CAUSEB_IP3		11
+#define  CAUSEF_IP3		(_ULCAST_(1)   << 11)
+#define  CAUSEB_IP4		12
+#define  CAUSEF_IP4		(_ULCAST_(1)   << 12)
+#define  CAUSEB_IP5		13
+#define  CAUSEF_IP5		(_ULCAST_(1)   << 13)
+#define  CAUSEB_IP6		14
+#define  CAUSEF_IP6		(_ULCAST_(1)   << 14)
+#define  CAUSEB_IP7		15
+#define  CAUSEF_IP7		(_ULCAST_(1)   << 15)
+#define  CAUSEB_IV		23
+#define  CAUSEF_IV		(_ULCAST_(1)   << 23)
+#define  CAUSEB_CE		28
+#define  CAUSEF_CE		(_ULCAST_(3)   << 28)
+#define  CAUSEB_BD		31
+#define  CAUSEF_BD		(_ULCAST_(1)   << 31)
+
+/*
+ * Bits in the coprocessor 0 config register.
+ */
+/* Generic bits.  */
+#define CONF_CM_CACHABLE_NO_WA		0
+#define CONF_CM_CACHABLE_WA		1
+#define CONF_CM_UNCACHED		2
+#define CONF_CM_CACHABLE_NONCOHERENT	3
+#define CONF_CM_CACHABLE_CE		4
+#define CONF_CM_CACHABLE_COW		5
+#define CONF_CM_CACHABLE_CUW		6
+#define CONF_CM_CACHABLE_ACCELERATED	7
+#define CONF_CM_CMASK			7
+#define CONF_BE			(_ULCAST_(1) << 15)
+
+/* Bits common to various processors.  */
+#define CONF_CU			(_ULCAST_(1) <<  3)
+#define CONF_DB			(_ULCAST_(1) <<  4)
+#define CONF_IB			(_ULCAST_(1) <<  5)
+#define CONF_DC			(_ULCAST_(7) <<  6)
+#define CONF_IC			(_ULCAST_(7) <<  9)
+#define CONF_EB			(_ULCAST_(1) << 13)
+#define CONF_EM			(_ULCAST_(1) << 14)
+#define CONF_SM			(_ULCAST_(1) << 16)
+#define CONF_SC			(_ULCAST_(1) << 17)
+#define CONF_EW			(_ULCAST_(3) << 18)
+#define CONF_EP			(_ULCAST_(15)<< 24)
+#define CONF_EC			(_ULCAST_(7) << 28)
+#define CONF_CM			(_ULCAST_(1) << 31)
+
+/* Bits specific to the R4xx0.  */
+#define R4K_CONF_SW		(_ULCAST_(1) << 20)
+#define R4K_CONF_SS		(_ULCAST_(1) << 21)
+#define R4K_CONF_SB		(_ULCAST_(3) << 22)
+
+/* Bits specific to the R5000.  */
+#define R5K_CONF_SE		(_ULCAST_(1) << 12)
+#define R5K_CONF_SS		(_ULCAST_(3) << 20)
+
+/* Bits specific to the R10000.  */
+#define R10K_CONF_DN		(_ULCAST_(3) <<  3)
+#define R10K_CONF_CT		(_ULCAST_(1) <<  5)
+#define R10K_CONF_PE		(_ULCAST_(1) <<  6)
+#define R10K_CONF_PM		(_ULCAST_(3) <<  7)
+#define R10K_CONF_EC		(_ULCAST_(15)<<  9)
+#define R10K_CONF_SB		(_ULCAST_(1) << 13)
+#define R10K_CONF_SK		(_ULCAST_(1) << 14)
+#define R10K_CONF_SS		(_ULCAST_(7) << 16)
+#define R10K_CONF_SC		(_ULCAST_(7) << 19)
+#define R10K_CONF_DC		(_ULCAST_(7) << 26)
+#define R10K_CONF_IC		(_ULCAST_(7) << 29)
+
+/* Bits specific to the VR41xx.  */
+#define VR41_CONF_CS		(_ULCAST_(1) << 12)
+#define VR41_CONF_M16		(_ULCAST_(1) << 20)
+#define VR41_CONF_AD		(_ULCAST_(1) << 23)
+
+/* Bits specific to the R30xx.  */
+#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
+#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
+#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
+#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
+#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
+
+/* Bits specific to the TX49.  */
+#define TX49_CONF_DC		(_ULCAST_(1) << 16)
+#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
+#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
+
+/* Bits specific to the MIPS32/64 PRA.  */
+#define MIPS_CONF_MT		(_ULCAST_(7) <<  7)
+#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
+#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
+#define MIPS_CONF_M		(_ULCAST_(1) << 31)
+
+/*
+ * R10000 performance counter definitions.
+ *
+ * FIXME: The R10000 performance counter opens a nice way to implement CPU
+ *        time accounting with a precission of one cycle.  I don't have
+ *        R10000 silicon but just a manual, so ...
+ */
+
+/*
+ * Events counted by counter #0
+ */
+#define CE0_CYCLES			0
+#define CE0_INSN_ISSUED			1
+#define CE0_LPSC_ISSUED			2
+#define CE0_S_ISSUED			3
+#define CE0_SC_ISSUED			4
+#define CE0_SC_FAILED			5
+#define CE0_BRANCH_DECODED		6
+#define CE0_QW_WB_SECONDARY		7
+#define CE0_CORRECTED_ECC_ERRORS	8
+#define CE0_ICACHE_MISSES		9
+#define CE0_SCACHE_I_MISSES		10
+#define CE0_SCACHE_I_WAY_MISSPREDICTED	11
+#define CE0_EXT_INTERVENTIONS_REQ	12
+#define CE0_EXT_INVALIDATE_REQ		13
+#define CE0_VIRTUAL_COHERENCY_COND	14
+#define CE0_INSN_GRADUATED		15
+
+/*
+ * Events counted by counter #1
+ */
+#define CE1_CYCLES			0
+#define CE1_INSN_GRADUATED		1
+#define CE1_LPSC_GRADUATED		2
+#define CE1_S_GRADUATED			3
+#define CE1_SC_GRADUATED		4
+#define CE1_FP_INSN_GRADUATED		5
+#define CE1_QW_WB_PRIMARY		6
+#define CE1_TLB_REFILL			7
+#define CE1_BRANCH_MISSPREDICTED	8
+#define CE1_DCACHE_MISS			9
+#define CE1_SCACHE_D_MISSES		10
+#define CE1_SCACHE_D_WAY_MISSPREDICTED	11
+#define CE1_EXT_INTERVENTION_HITS	12
+#define CE1_EXT_INVALIDATE_REQ		13
+#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS	14
+#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS	15
+
+/*
+ * These flags define in which priviledge mode the counters count events
+ */
+#define CEB_USER	8	/* Count events in user mode, EXL = ERL = 0 */
+#define CEB_SUPERVISOR	4	/* Count events in supvervisor mode EXL = ERL = 0 */
+#define CEB_KERNEL	2	/* Count events in kernel mode EXL = ERL = 0 */
+#define CEB_EXL		1	/* Count events with EXL = 1, ERL = 0 */
+
+#ifndef __ASSEMBLY__
+
+#define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE)
+#define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2))
+
+/*
+ * Functions to access the r10k performance counter and control registers
+ */
+#define read_r10k_perf_cntr(counter)                            \
+({ unsigned int __res;                                          \
+        __asm__ __volatile__(                                   \
+        "mfpc\t%0, "STR(counter)                                \
+        : "=r" (__res));                                        \
+        __res;})
+
+#define write_r10k_perf_cntr(counter,val)                       \
+        __asm__ __volatile__(                                   \
+        "mtpc\t%0, "STR(counter)                                \
+        : : "r" (val));
+
+#define read_r10k_perf_cntl(counter)                            \
+({ unsigned int __res;                                          \
+        __asm__ __volatile__(                                   \
+        "mfps\t%0, "STR(counter)                                \
+        : "=r" (__res));                                        \
+        __res;})
+
+#define write_r10k_perf_cntl(counter,val)                       \
+        __asm__ __volatile__(                                   \
+        "mtps\t%0, "STR(counter)                                \
+        : : "r" (val));
+
+/*
+ * Macros to access the system control coprocessor
+ */
+
+#define __read_32bit_c0_register(source, sel)				\
+({ int __res;								\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mfc0\t%0, " #source "\n\t"			\
+			: "=r" (__res));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mfc0\t%0, " #source ", " #sel "\n\t"		\
+			".set\tmips0\n\t"				\
+			: "=r" (__res));				\
+	__res;								\
+})
+
+#define __read_64bit_c0_register(source, sel)				\
+({ unsigned long __res;							\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			".set\tmips3\n\t"				\
+			"dmfc0\t%0, " #source "\n\t"			\
+			".set\tmips0"					\
+			: "=r" (__res));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
+			".set\tmips0"					\
+			: "=r" (__res));				\
+	__res;								\
+})
+
+#define __write_32bit_c0_register(register, sel, value)			\
+do {									\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mtc0\t%z0, " #register "\n\t"			\
+			: : "Jr" (value));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
+			".set\tmips0"					\
+			: : "Jr" (value));				\
+} while (0)
+
+#define __write_64bit_c0_register(register, sel, value)			\
+do {									\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			".set\tmips3\n\t"				\
+			"dmtc0\t%z0, " #register "\n\t"			\
+			".set\tmips0"					\
+			: : "Jr" (value));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
+			".set\tmips0"					\
+			: : "Jr" (value));				\
+} while (0)
+
+#define __read_ulong_c0_register(reg, sel)				\
+	((sizeof(unsigned long) == 4) ?					\
+	__read_32bit_c0_register(reg, sel) :				\
+	__read_64bit_c0_register(reg, sel))
+
+#define __write_ulong_c0_register(reg, sel, val)			\
+do {									\
+	if (sizeof(unsigned long) == 4)					\
+		__write_32bit_c0_register(reg, sel, val);		\
+	else								\
+		__write_64bit_c0_register(reg, sel, val);		\
+} while (0)
+
+/*
+ * These versions are only needed for systems with more than 38 bits of
+ * physical address space running the 32-bit kernel.  That's none atm :-)
+ */
+#define __read_64bit_c0_split(source, sel)				\
+({									\
+	unsigned long long val;						\
+	unsigned long flags;						\
+									\
+	local_irq_save(flags);						\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dmfc0\t%M0, " #source "\n\t"			\
+			"dsll\t%L0, %M0, 32\n\t"			\
+			"dsrl\t%M0, %M0, 32\n\t"			\
+			"dsrl\t%L0, %L0, 32\n\t"			\
+			".set\tmips0"					\
+			: "=r" (val));					\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dmfc0\t%M0, " #source ", " #sel "\n\t"		\
+			"dsll\t%L0, %M0, 32\n\t"			\
+			"dsrl\t%M0, %M0, 32\n\t"			\
+			"dsrl\t%L0, %L0, 32\n\t"			\
+			".set\tmips0"					\
+			: "=r" (val));					\
+	local_irq_restore(flags);					\
+									\
+	val;								\
+})
+
+#define __write_64bit_c0_split(source, sel, val)			\
+do {									\
+	unsigned long flags;						\
+									\
+	local_irq_save(flags);						\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dsll\t%L0, %L0, 32\n\t"			\
+			"dsrl\t%L0, %L0, 32\n\t"			\
+			"dsll\t%M0, %M0, 32\n\t"			\
+			"or\t%L0, %L0, %M0\n\t"				\
+			"dmtc0\t%L0, " #source "\n\t"			\
+			".set\tmips0"					\
+			: : "r" (val));					\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dsll\t%L0, %L0, 32\n\t"			\
+			"dsrl\t%L0, %L0, 32\n\t"			\
+			"dsll\t%M0, %M0, 32\n\t"			\
+			"or\t%L0, %L0, %M0\n\t"				\
+			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
+			".set\tmips0"					\
+			: : "r" (val));					\
+	local_irq_restore(flags);					\
+} while (0)
+
+#define read_c0_index()		__read_32bit_c0_register($0, 0)
+#define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
+
+#define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
+
+#define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
+
+#define read_c0_conf()		__read_32bit_c0_register($3, 0)
+#define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
+
+#define read_c0_context()	__read_ulong_c0_register($4, 0)
+#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
+
+#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
+
+#define read_c0_wired()		__read_32bit_c0_register($6, 0)
+#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info()		__read_32bit_c0_register($7, 0)
+
+#define read_c0_cache()		__read_32bit_c0_register($7, 0)	/* TX39xx */
+#define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
+
+#define read_c0_count()		__read_32bit_c0_register($9, 0)
+#define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
+
+#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
+
+#define read_c0_compare()	__read_32bit_c0_register($11, 0)
+#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
+
+#define read_c0_status()	__read_32bit_c0_register($12, 0)
+#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
+
+#define read_c0_cause()		__read_32bit_c0_register($13, 0)
+#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
+
+#define read_c0_prid()		__read_32bit_c0_register($15, 0)
+
+#define read_c0_config()	__read_32bit_c0_register($16, 0)
+#define read_c0_config1()	__read_32bit_c0_register($16, 1)
+#define read_c0_config2()	__read_32bit_c0_register($16, 2)
+#define read_c0_config3()	__read_32bit_c0_register($16, 3)
+#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
+
+/*
+ * The WatchLo register.  There may be upto 8 of them.
+ */
+#define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
+
+/*
+ * The WatchHi register.  There may be upto 8 of them.
+ */
+#define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
+
+#define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
+
+#define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
+
+#define read_c0_intcontrol()	__read_32bit_c0_register($20, 1)
+#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
+
+#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val)	__write_32bit_c0_register($21, 0, val)
+
+#define read_c0_debug()		__read_32bit_c0_register($23, 0)
+#define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
+
+#define read_c0_depc()		__read_ulong_c0_register($24, 0)
+#define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
+
+#define read_c0_ecc()		__read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
+
+#define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val)	__write_ulong_c0_register($26, 1, val)
+
+#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
+
+#define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val)	__write_ulong_c0_register($27, 1, val)
+
+#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
+
+#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
+
+#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
+
+#define read_c0_epc()		__read_ulong_c0_register($14, 0)
+#define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
+
+#if 1
+/*
+ * Macros to access the system control coprocessor
+ */
+#define read_32bit_cp0_register(source)                         \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+        "mfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+
+#define read_32bit_cp0_set1_register(source)                    \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+        "cfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+
+/*
+ * For now use this only with interrupts disabled!
+ */
+#define read_64bit_cp0_register(source)                         \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+        ".set\tmips3\n\t"                                       \
+        "dmfc0\t%0,"STR(source)"\n\t"                           \
+        ".set\tmips0"                                           \
+        : "=r" (__res));                                        \
+        __res;})
+
+#define write_32bit_cp0_register(register,value)                \
+        __asm__ __volatile__(                                   \
+        "mtc0\t%0,"STR(register)"\n\t"				\
+	"nop"							\
+        : : "r" (value));
+
+#define write_32bit_cp0_set1_register(register,value)           \
+        __asm__ __volatile__(                                   \
+        "ctc0\t%0,"STR(register)"\n\t"				\
+	"nop"							\
+        : : "r" (value));
+
+#define write_64bit_cp0_register(register,value)                \
+        __asm__ __volatile__(                                   \
+        ".set\tmips3\n\t"                                       \
+        "dmtc0\t%0,"STR(register)"\n\t"                         \
+        ".set\tmips0"                                           \
+        : : "r" (value))
+
+/*
+ * This should be changed when we get a compiler that support the MIPS32 ISA.
+ */
+#define read_mips32_cp0_config1()                               \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tnoreorder\n\t"                                   \
+	".set\tnoat\n\t"                                        \
+	"#.set\tmips64\n\t"					\
+	"#mfc0\t$1, $16, 1\n\t"					\
+	"#.set\tmips0\n\t"					\
+     	".word\t0x40018001\n\t"                                 \
+	"move\t%0,$1\n\t"                                       \
+	".set\tat\n\t"                                          \
+	".set\treorder"                                         \
+	:"=r" (__res));                                         \
+        __res;})
+
+#endif
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define read_32bit_cp1_register(source)                         \
+({ int __res;                                                   \
+	__asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+        "cfc1\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+
+/* TLB operations. */
+static inline void tlb_probe(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbp\n\t"
+		".set reorder");
+}
+
+static inline void tlb_read(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbr\n\t"
+		".set reorder");
+}
+
+static inline void tlb_write_indexed(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbwi\n\t"
+		".set reorder");
+}
+
+static inline void tlb_write_random(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbwr\n\t"
+		".set reorder");
+}
+
+/*
+ * Manipulate bits in a c0 register.
+ */
+#define __BUILD_SET_C0(name,register)				\
+static inline unsigned int					\
+set_c0_##name(unsigned int set)					\
+{								\
+	unsigned int res;					\
+								\
+	res = read_c0_##name();					\
+	res |= set;						\
+	write_c0_##name(res);					\
+								\
+	return res;						\
+}								\
+								\
+static inline unsigned int					\
+clear_c0_##name(unsigned int clear)				\
+{								\
+	unsigned int res;					\
+								\
+	res = read_c0_##name();					\
+	res &= ~clear;						\
+	write_c0_##name(res);					\
+								\
+	return res;						\
+}								\
+								\
+static inline unsigned int					\
+change_c0_##name(unsigned int change, unsigned int new)		\
+{								\
+	unsigned int res;					\
+								\
+	res = read_c0_##name();					\
+	res &= ~change;						\
+	res |= (new & change);					\
+	write_c0_##name(res);					\
+								\
+	return res;						\
+}
+
+__BUILD_SET_C0(status,CP0_STATUS)
+__BUILD_SET_C0(cause,CP0_CAUSE)
+__BUILD_SET_C0(config,CP0_CONFIG)
+
+#define set_cp0_status(x)	set_c0_status(x)
+#define set_cp0_cause(x)	set_c0_cause(x)
+#define set_cp0_config(x)	set_c0_config(x)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _MIPS_REGS_H_ */
diff --git a/bsp/x1000/cpu/common/mips_types.h b/bsp/x1000/cpu/common/mips_types.h
new file mode 100644
index 0000000000..7f0b8a6855
--- /dev/null
+++ b/bsp/x1000/cpu/common/mips_types.h
@@ -0,0 +1,118 @@
+/*
+ * File      : mips_types.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��7��     Urey         the first version
+ */
+
+#ifndef _MIPS_TYPES_H_
+#define _MIPS_TYPES_H_
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char     __s8;
+typedef unsigned char       __u8;
+
+typedef __signed__ short    __s16;
+typedef unsigned short      __u16;
+
+typedef __signed__ int      __s32;
+typedef unsigned int        __u32;
+
+#if (_MIPS_SZLONG == 64)
+
+typedef __signed__ long     __s64;
+typedef unsigned long       __u64;
+
+#else
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+
+#define BITS_PER_LONG _MIPS_SZLONG
+
+
+typedef __signed char s8;
+typedef unsigned char u8;
+
+typedef __signed short s16;
+typedef unsigned short u16;
+
+typedef __signed int s32;
+typedef unsigned int u32;
+
+#if (_MIPS_SZLONG == 64)
+
+typedef __signed__ long s64;
+typedef unsigned long u64;
+
+#else
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+#endif
+
+#endif
+
+#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
+    || defined(CONFIG_64BIT)
+typedef u64 dma_addr_t;
+
+typedef u64 phys_addr_t;
+typedef u64 phys_size_t;
+
+#else
+typedef u32 dma_addr_t;
+
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
+
+#endif
+typedef u64 dma64_addr_t;
+
+/*
+ * Don't use phys_t.  You've been warned.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+typedef unsigned long long phys_t;
+#else
+typedef unsigned long phys_t;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* _MIPS_TYPES_H_ */
diff --git a/bsp/x1000/cpu/common/mipscfg.h b/bsp/x1000/cpu/common/mipscfg.h
new file mode 100644
index 0000000000..b4f30615f8
--- /dev/null
+++ b/bsp/x1000/cpu/common/mipscfg.h
@@ -0,0 +1,32 @@
+/*
+ * File      : mipscfg.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-27     swkyer       first version
+ */
+#ifndef __MIPSCFG_H__
+#define __MIPSCFG_H__
+
+
+typedef struct mips32_core_cfg
+{
+    rt_uint16_t icache_line_size;
+    rt_uint16_t icache_lines_per_way;
+    rt_uint16_t icache_ways;
+    rt_uint16_t dcache_line_size;
+    rt_uint16_t dcache_lines_per_way;
+    rt_uint16_t dcache_ways;
+
+    rt_uint16_t max_tlb_entries;	/* number of tlb entry */
+} mips32_core_cfg_t;
+
+extern mips32_core_cfg_t g_mips_core;
+
+#endif /* end of __MIPSCFG_H__ */
diff --git a/bsp/x1000/cpu/common/mipsregs.h b/bsp/x1000/cpu/common/mipsregs.h
new file mode 100644
index 0000000000..22e5754b8b
--- /dev/null
+++ b/bsp/x1000/cpu/common/mipsregs.h
@@ -0,0 +1,706 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Modified for further R[236]000 support by Paul M. Antoine, 1996.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ * Copyright (C) 2003, 2004  Maciej W. Rozycki
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ *
+ */
+#ifndef __MIPSREGS_H__
+#define __MIPSREGS_H__
+
+/*
+ * The following macros are especially useful for __asm__
+ * inline assembler.
+ */
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ULCAST_
+#else
+#define _ULCAST_ (unsigned long)
+#endif
+
+/*
+ * Coprocessor 0 register names
+ */
+#define CP0_INDEX 			$0
+#define CP0_RANDOM		 	$1
+#define CP0_ENTRYLO0 		$2
+#define CP0_ENTRYLO1 		$3
+#define CP0_CONF 			$3
+#define CP0_CONTEXT 		$4
+#define CP0_PAGEMASK 		$5
+#define CP0_WIRED 			$6
+#define CP0_INFO 			$7
+#define CP0_BADVADDR 		$8
+#define CP0_COUNT 			$9
+#define CP0_ENTRYHI 		$10
+#define CP0_COMPARE 		$11
+#define CP0_STATUS 			$12
+#define CP0_CAUSE 			$13
+#define CP0_EPC 			$14
+#define CP0_PRID 			$15
+#define CP0_CONFIG 			$16
+#define CP0_LLADDR 			$17
+#define CP0_WATCHLO 		$18
+#define CP0_WATCHHI 		$19
+#define CP0_XCONTEXT 		$20
+#define CP0_FRAMEMASK 		$21
+#define CP0_DIAGNOSTIC 		$22
+#define CP0_DEBUG 			$23
+#define CP0_DEPC 			$24
+#define CP0_PERFORMANCE 	$25
+#define CP0_ECC 			$26
+#define CP0_CACHEERR 		$27
+#define CP0_TAGLO 			$28
+#define CP0_TAGHI 			$29
+#define CP0_ERROREPC 		$30
+#define CP0_DESAVE 			$31
+
+/*
+ * R4640/R4650 cp0 register names.  These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux.  A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE 			$0
+#define CP0_IBOUND 			$1
+#define CP0_DBASE 			$2
+#define CP0_DBOUND 			$3
+#define CP0_CALG 			$17
+#define CP0_IWATCH 			$18
+#define CP0_DWATCH 			$19
+
+/*
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  	$26
+#define CP0_S1_DERRADDR1  	$27
+#define CP0_S1_INTCONTROL 	$20
+
+/*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL	  	$12	/* MIPSR2 */
+
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP	  	$12	/* MIPSR2 */
+
+/*
+ *  TX39 Series
+ */
+#define CP0_TX39_CACHE		$7
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION   		$0
+#define CP1_STATUS     		$31
+
+/*
+ * FPU Status Register Values
+ */
+/*
+ * Status Register Values
+ */
+
+#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
+#define FPU_CSR_COND    0x00800000      /* $fcc0 */
+#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
+#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
+#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
+#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
+#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
+#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
+#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
+#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+
+
+/* FS/FO/FN */
+#define FPU_CSR_FS      0x01000000
+#define FPU_CSR_FO      0x00400000
+#define FPU_CSR_FN      0x00200000
+
+/*
+ * Bits 18 - 20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD	0x001c0000
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X   0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
+
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
+
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM	0x00000003
+#define FPU_CSR_RN      0x0     /* nearest */
+#define FPU_CSR_RZ      0x1     /* towards zero */
+#define FPU_CSR_RU      0x2     /* towards +Infinity */
+#define FPU_CSR_RD      0x3     /* towards -Infinity */
+
+
+/*
+ * R4x00 interrupt enable / cause bits
+ */
+#define IE_SW0          (_ULCAST_(1) <<  8)
+#define IE_SW1          (_ULCAST_(1) <<  9)
+#define IE_IRQ0         (_ULCAST_(1) << 10)
+#define IE_IRQ1         (_ULCAST_(1) << 11)
+#define IE_IRQ2         (_ULCAST_(1) << 12)
+#define IE_IRQ3         (_ULCAST_(1) << 13)
+#define IE_IRQ4         (_ULCAST_(1) << 14)
+#define IE_IRQ5         (_ULCAST_(1) << 15)
+
+/*
+ * R4x00 interrupt cause bits
+ */
+#define C_SW0           (_ULCAST_(1) <<  8)
+#define C_SW1           (_ULCAST_(1) <<  9)
+#define C_IRQ0          (_ULCAST_(1) << 10)
+#define C_IRQ1          (_ULCAST_(1) << 11)
+#define C_IRQ2          (_ULCAST_(1) << 12)
+#define C_IRQ3          (_ULCAST_(1) << 13)
+#define C_IRQ4          (_ULCAST_(1) << 14)
+#define C_IRQ5          (_ULCAST_(1) << 15)
+
+/*
+ * Bitfields in the R4xx0 cp0 status register
+ */
+#define ST0_IE					0x00000001
+#define ST0_EXL					0x00000002
+#define ST0_ERL					0x00000004
+#define ST0_KSU					0x00000018
+#  define KSU_USER					0x00000010
+#  define KSU_SUPERVISOR			0x00000008
+#  define KSU_KERNEL				0x00000000
+#define ST0_UX					0x00000020
+#define ST0_SX					0x00000040
+#define ST0_KX 					0x00000080
+#define ST0_DE					0x00010000
+#define ST0_CE					0x00020000
+
+/*
+ * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
+ * cacheops in userspace.  This bit exists only on RM7000 and RM9000
+ * processors.
+ */
+#define ST0_CO					0x08000000
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_IEC                 0x00000001
+#define ST0_KUC					0x00000002
+#define ST0_IEP					0x00000004
+#define ST0_KUP					0x00000008
+#define ST0_IEO					0x00000010
+#define ST0_KUO					0x00000020
+/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC					0x00010000
+#define ST0_SWC					0x00020000
+#define ST0_CM					0x00080000
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM					(_ULCAST_(1) <<  4)
+#define ST0_IL					(_ULCAST_(1) << 23)
+#define ST0_DL					(_ULCAST_(1) << 24)
+
+/*
+ * Enable the MIPS DSP ASE
+ */
+#define ST0_MX					0x01000000
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT		19
+#define TX39_CONF_ICS_MASK		0x00380000
+#define TX39_CONF_ICS_1KB 		0x00000000
+#define TX39_CONF_ICS_2KB 		0x00080000
+#define TX39_CONF_ICS_4KB 		0x00100000
+#define TX39_CONF_ICS_8KB 		0x00180000
+#define TX39_CONF_ICS_16KB 		0x00200000
+
+#define TX39_CONF_DCS_SHIFT		16
+#define TX39_CONF_DCS_MASK		0x00070000
+#define TX39_CONF_DCS_1KB 		0x00000000
+#define TX39_CONF_DCS_2KB 		0x00010000
+#define TX39_CONF_DCS_4KB 		0x00020000
+#define TX39_CONF_DCS_8KB 		0x00030000
+#define TX39_CONF_DCS_16KB 		0x00040000
+
+#define TX39_CONF_CWFON 		0x00004000
+#define TX39_CONF_WBON  		0x00002000
+#define TX39_CONF_RF_SHIFT		10
+#define TX39_CONF_RF_MASK		0x00000c00
+#define TX39_CONF_DOZE			0x00000200
+#define TX39_CONF_HALT			0x00000100
+#define TX39_CONF_LOCK			0x00000080
+#define TX39_CONF_ICE			0x00000020
+#define TX39_CONF_DCE			0x00000010
+#define TX39_CONF_IRSIZE_SHIFT	2
+#define TX39_CONF_IRSIZE_MASK	0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT	0
+#define TX39_CONF_DRSIZE_MASK	0x00000003
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define  ST0_IM			    0x0000ff00
+#define  STATUSB_IP0		8
+#define  STATUSF_IP0		(_ULCAST_(1) <<  8)
+#define  STATUSB_IP1		9
+#define  STATUSF_IP1		(_ULCAST_(1) <<  9)
+#define  STATUSB_IP2		10
+#define  STATUSF_IP2		(_ULCAST_(1) << 10)
+#define  STATUSB_IP3		11
+#define  STATUSF_IP3		(_ULCAST_(1) << 11)
+#define  STATUSB_IP4		12
+#define  STATUSF_IP4		(_ULCAST_(1) << 12)
+#define  STATUSB_IP5		13
+#define  STATUSF_IP5		(_ULCAST_(1) << 13)
+#define  STATUSB_IP6		14
+#define  STATUSF_IP6		(_ULCAST_(1) << 14)
+#define  STATUSB_IP7		15
+#define  STATUSF_IP7		(_ULCAST_(1) << 15)
+#define  STATUSB_IP8		0
+#define  STATUSF_IP8		(_ULCAST_(1) <<  0)
+#define  STATUSB_IP9		1
+#define  STATUSF_IP9		(_ULCAST_(1) <<  1)
+#define  STATUSB_IP10		2
+#define  STATUSF_IP10		(_ULCAST_(1) <<  2)
+#define  STATUSB_IP11		3
+#define  STATUSF_IP11		(_ULCAST_(1) <<  3)
+#define  STATUSB_IP12		4
+#define  STATUSF_IP12		(_ULCAST_(1) <<  4)
+#define  STATUSB_IP13		5
+#define  STATUSF_IP13		(_ULCAST_(1) <<  5)
+#define  STATUSB_IP14		6
+#define  STATUSF_IP14		(_ULCAST_(1) <<  6)
+#define  STATUSB_IP15		7
+#define  STATUSF_IP15		(_ULCAST_(1) <<  7)
+#define  ST0_CH				0x00040000
+#define  ST0_SR				0x00100000
+#define  ST0_TS				0x00200000
+#define  ST0_BEV			0x00400000
+#define  ST0_RE				0x02000000
+#define  ST0_FR				0x04000000
+#define  ST0_CU				0xf0000000
+#define  ST0_CU0			0x10000000
+#define  ST0_CU1			0x20000000
+#define  ST0_CU2			0x40000000
+#define  ST0_CU3			0x80000000
+#define  ST0_XX				0x80000000	/* MIPS IV naming */
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 cause register.
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define  CAUSEB_EXCCODE		2
+#define  CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
+#define  CAUSEB_IP			8
+#define  CAUSEF_IP			(_ULCAST_(255) <<  8)
+#define  CAUSEB_IP0			8
+#define  CAUSEF_IP0			(_ULCAST_(1)   <<  8)
+#define  CAUSEB_IP1			9
+#define  CAUSEF_IP1			(_ULCAST_(1)   <<  9)
+#define  CAUSEB_IP2			10
+#define  CAUSEF_IP2			(_ULCAST_(1)   << 10)
+#define  CAUSEB_IP3			11
+#define  CAUSEF_IP3			(_ULCAST_(1)   << 11)
+#define  CAUSEB_IP4			12
+#define  CAUSEF_IP4			(_ULCAST_(1)   << 12)
+#define  CAUSEB_IP5			13
+#define  CAUSEF_IP5			(_ULCAST_(1)   << 13)
+#define  CAUSEB_IP6			14
+#define  CAUSEF_IP6			(_ULCAST_(1)   << 14)
+#define  CAUSEB_IP7			15
+#define  CAUSEF_IP7			(_ULCAST_(1)   << 15)
+#define  CAUSEB_IV			23
+#define  CAUSEF_IV			(_ULCAST_(1)   << 23)
+#define  CAUSEB_CE			28
+#define  CAUSEF_CE			(_ULCAST_(3)   << 28)
+#define  CAUSEB_BD			31
+#define  CAUSEF_BD			(_ULCAST_(1)   << 31)
+
+/*
+ * Bits in the coprocessor 0 config register.
+ */
+/* Generic bits.  */
+#define CONF_CM_CACHABLE_NO_WA			0
+#define CONF_CM_CACHABLE_WA				1
+#define CONF_CM_UNCACHED				2
+#define CONF_CM_CACHABLE_NONCOHERENT	3
+#define CONF_CM_CACHABLE_CE				4
+#define CONF_CM_CACHABLE_COW			5
+#define CONF_CM_CACHABLE_CUW			6
+#define CONF_CM_CACHABLE_ACCELERATED	7
+#define CONF_CM_CMASK					7
+#define CONF_BE							(_ULCAST_(1) << 15)
+
+/* Bits common to various processors.  */
+#define CONF_CU				(_ULCAST_(1) <<  3)
+#define CONF_DB				(_ULCAST_(1) <<  4)
+#define CONF_IB				(_ULCAST_(1) <<  5)
+#define CONF_DC				(_ULCAST_(7) <<  6)
+#define CONF_IC				(_ULCAST_(7) <<  9)
+#define CONF_EB				(_ULCAST_(1) << 13)
+#define CONF_EM				(_ULCAST_(1) << 14)
+#define CONF_SM				(_ULCAST_(1) << 16)
+#define CONF_SC				(_ULCAST_(1) << 17)
+#define CONF_EW				(_ULCAST_(3) << 18)
+#define CONF_EP				(_ULCAST_(15)<< 24)
+#define CONF_EC				(_ULCAST_(7) << 28)
+#define CONF_CM				(_ULCAST_(1) << 31)
+
+/* Bits specific to the R4xx0.  */
+#define R4K_CONF_SW			(_ULCAST_(1) << 20)
+#define R4K_CONF_SS			(_ULCAST_(1) << 21)
+#define R4K_CONF_SB			(_ULCAST_(3) << 22)
+
+/* Bits specific to the R5000.  */
+#define R5K_CONF_SE			(_ULCAST_(1) << 12)
+#define R5K_CONF_SS			(_ULCAST_(3) << 20)
+
+/* Bits specific to the RM7000.  */
+#define RM7K_CONF_SE		(_ULCAST_(1) <<  3)
+#define RM7K_CONF_TE		(_ULCAST_(1) << 12)
+#define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
+#define RM7K_CONF_TC		(_ULCAST_(1) << 17)
+#define RM7K_CONF_SI		(_ULCAST_(3) << 20)
+#define RM7K_CONF_SC		(_ULCAST_(1) << 31)
+
+/* Bits specific to the R10000.  */
+#define R10K_CONF_DN		(_ULCAST_(3) <<  3)
+#define R10K_CONF_CT		(_ULCAST_(1) <<  5)
+#define R10K_CONF_PE		(_ULCAST_(1) <<  6)
+#define R10K_CONF_PM		(_ULCAST_(3) <<  7)
+#define R10K_CONF_EC		(_ULCAST_(15)<<  9)
+#define R10K_CONF_SB		(_ULCAST_(1) << 13)
+#define R10K_CONF_SK		(_ULCAST_(1) << 14)
+#define R10K_CONF_SS		(_ULCAST_(7) << 16)
+#define R10K_CONF_SC		(_ULCAST_(7) << 19)
+#define R10K_CONF_DC		(_ULCAST_(7) << 26)
+#define R10K_CONF_IC		(_ULCAST_(7) << 29)
+
+/* Bits specific to the VR41xx.  */
+#define VR41_CONF_CS		(_ULCAST_(1) << 12)
+#define VR41_CONF_M16		(_ULCAST_(1) << 20)
+#define VR41_CONF_AD		(_ULCAST_(1) << 23)
+
+/* Bits specific to the R30xx.  */
+#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
+#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
+#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
+#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
+#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
+
+/* Bits specific to the TX49.  */
+#define TX49_CONF_DC		(_ULCAST_(1) << 16)
+#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
+#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
+
+/* Bits specific to the MIPS32/64 PRA.  */
+#define MIPS_CONF_MT		(_ULCAST_(7) <<  7)
+#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
+#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
+#define MIPS_CONF_M			(_ULCAST_(1) << 31)
+
+/*
+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
+ */
+#define MIPS_CONF1_FP		(_ULCAST_(1) <<  0)
+#define MIPS_CONF1_EP		(_ULCAST_(1) <<  1)
+#define MIPS_CONF1_CA		(_ULCAST_(1) <<  2)
+#define MIPS_CONF1_WR		(_ULCAST_(1) <<  3)
+#define MIPS_CONF1_PC		(_ULCAST_(1) <<  4)
+#define MIPS_CONF1_MD		(_ULCAST_(1) <<  5)
+#define MIPS_CONF1_C2		(_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA		(_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
+#define MIPS_CONF1_TLBS		(_ULCAST_(63)<< 25)
+
+#define MIPS_CONF2_SA		(_ULCAST_(15)<<  0)
+#define MIPS_CONF2_SL		(_ULCAST_(15)<<  4)
+#define MIPS_CONF2_SS		(_ULCAST_(15)<<  8)
+#define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
+#define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
+#define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
+#define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
+#define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
+
+#define MIPS_CONF3_TL		(_ULCAST_(1) <<  0)
+#define MIPS_CONF3_SM		(_ULCAST_(1) <<  1)
+#define MIPS_CONF3_MT		(_ULCAST_(1) <<  2)
+#define MIPS_CONF3_SP		(_ULCAST_(1) <<  4)
+#define MIPS_CONF3_VINT		(_ULCAST_(1) <<  5)
+#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<  6)
+#define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)
+#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S			(_ULCAST_(1) << 16)
+#define MIPS_FPIR_D			(_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
+#define MIPS_FPIR_W			(_ULCAST_(1) << 20)
+#define MIPS_FPIR_L			(_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
+
+/*
+ * R10000 performance counter definitions.
+ *
+ * FIXME: The R10000 performance counter opens a nice way to implement CPU
+ *        time accounting with a precission of one cycle.  I don't have
+ *        R10000 silicon but just a manual, so ...
+ */
+
+/*
+ * Events counted by counter #0
+ */
+#define CE0_CYCLES						0
+#define CE0_INSN_ISSUED					1
+#define CE0_LPSC_ISSUED					2
+#define CE0_S_ISSUED					3
+#define CE0_SC_ISSUED					4
+#define CE0_SC_FAILED					5
+#define CE0_BRANCH_DECODED				6
+#define CE0_QW_WB_SECONDARY				7
+#define CE0_CORRECTED_ECC_ERRORS		8
+#define CE0_ICACHE_MISSES				9
+#define CE0_SCACHE_I_MISSES				10
+#define CE0_SCACHE_I_WAY_MISSPREDICTED	11
+#define CE0_EXT_INTERVENTIONS_REQ		12
+#define CE0_EXT_INVALIDATE_REQ			13
+#define CE0_VIRTUAL_COHERENCY_COND		14
+#define CE0_INSN_GRADUATED				15
+
+/*
+ * Events counted by counter #1
+ */
+#define CE1_CYCLES						0
+#define CE1_INSN_GRADUATED				1
+#define CE1_LPSC_GRADUATED				2
+#define CE1_S_GRADUATED					3
+#define CE1_SC_GRADUATED				4
+#define CE1_FP_INSN_GRADUATED			5
+#define CE1_QW_WB_PRIMARY				6
+#define CE1_TLB_REFILL					7
+#define CE1_BRANCH_MISSPREDICTED		8
+#define CE1_DCACHE_MISS					9
+#define CE1_SCACHE_D_MISSES				10
+#define CE1_SCACHE_D_WAY_MISSPREDICTED	11
+#define CE1_EXT_INTERVENTION_HITS		12
+#define CE1_EXT_INVALIDATE_REQ			13
+#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS	14
+#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS	15
+
+/*
+ * These flags define in which privilege mode the counters count events
+ */
+#define CEB_USER		8	/* Count events in user mode, EXL = ERL = 0 */
+#define CEB_SUPERVISOR	4	/* Count events in supvervisor mode EXL = ERL = 0 */
+#define CEB_KERNEL		2	/* Count events in kernel mode EXL = ERL = 0 */
+#define CEB_EXL			1	/* Count events with EXL = 1, ERL = 0 */
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Macros to access the system control coprocessor
+ */
+#define __read_32bit_c0_register(source, sel)				\
+({ int __res;								\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mfc0\t%0, " #source "\n\t"			\
+			: "=r" (__res));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mfc0\t%0, " #source ", " #sel "\n\t"		\
+			".set\tmips0\n\t"				\
+			: "=r" (__res));				\
+	__res;								\
+})
+
+#define __write_32bit_c0_register(register, sel, value)			\
+do {									\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mtc0\t%z0, " #register "\n\t"			\
+			: : "Jr" ((unsigned int)(value)));		\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
+			".set\tmips0"					\
+			: : "Jr" ((unsigned int)(value)));		\
+} while (0)
+
+#define read_c0_index()			__read_32bit_c0_register($0, 0)
+#define write_c0_index(val)		__write_32bit_c0_register($0, 0, val)
+
+#define read_c0_random()		__read_32bit_c0_register($1, 0)
+#define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
+
+#define read_c0_entrylo0()		__read_32bit_c0_register($2, 0)
+#define write_c0_entrylo0(val)	__write_32bit_c0_register($2, 0, val)
+
+#define read_c0_entrylo1()		__read_32bit_c0_register($3, 0)
+#define write_c0_entrylo1(val)	__write_32bit_c0_register($3, 0, val)
+
+#define read_c0_conf()			__read_32bit_c0_register($3, 0)
+#define write_c0_conf(val)		__write_32bit_c0_register($3, 0, val)
+
+#define read_c0_context()		__read_32bit_c0_register($4, 0)
+#define write_c0_context(val)	__write_32bit_c0_register($4, 0, val)
+
+#define read_c0_userlocal()		__read_32bit_c0_register($4, 2)
+#define write_c0_userlocal(val)	__write_32bit_c0_register($4, 2, val)
+
+#define read_c0_pagemask()		__read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
+
+#define read_c0_wired()			__read_32bit_c0_register($6, 0)
+#define write_c0_wired(val)		__write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info()			__read_32bit_c0_register($7, 0)
+
+#define read_c0_cache()			__read_32bit_c0_register($7, 0)	/* TX39xx */
+#define write_c0_cache(val)		__write_32bit_c0_register($7, 0, val)
+
+#define read_c0_badvaddr()		__read_32bit_c0_register($8, 0)
+#define write_c0_badvaddr(val)	__write_32bit_c0_register($8, 0, val)
+
+#define read_c0_count()			__read_32bit_c0_register($9, 0)
+#define write_c0_count(val)		__write_32bit_c0_register($9, 0, val)
+
+#define read_c0_count2()		__read_32bit_c0_register($9, 6) /* pnx8550 */
+#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
+
+#define read_c0_count3()		__read_32bit_c0_register($9, 7) /* pnx8550 */
+#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
+
+#define read_c0_entryhi()		__read_32bit_c0_register($10, 0)
+#define write_c0_entryhi(val)	__write_32bit_c0_register($10, 0, val)
+
+#define read_c0_compare()		__read_32bit_c0_register($11, 0)
+#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
+
+#define read_c0_compare2()		__read_32bit_c0_register($11, 6) /* pnx8550 */
+#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
+
+#define read_c0_compare3()		__read_32bit_c0_register($11, 7) /* pnx8550 */
+#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
+
+#define read_c0_status()		__read_32bit_c0_register($12, 0)
+#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
+
+#define read_c0_cause()			__read_32bit_c0_register($13, 0)
+#define write_c0_cause(val)		__write_32bit_c0_register($13, 0, val)
+
+#define read_c0_epc()			__read_32bit_c0_register($14, 0)
+#define write_c0_epc(val)		__write_32bit_c0_register($14, 0, val)
+
+#define read_c0_prid()			__read_32bit_c0_register($15, 0)
+
+#define read_c0_ebase()			__read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val)		__write_32bit_c0_register($15, 1, val)
+
+#define read_c0_config()		__read_32bit_c0_register($16, 0)
+#define read_c0_config1()		__read_32bit_c0_register($16, 1)
+#define read_c0_config2()		__read_32bit_c0_register($16, 2)
+#define read_c0_config3()		__read_32bit_c0_register($16, 3)
+#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
+
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define read_32bit_cp1_register(source)                         \
+({ int __res;                                                   \
+	__asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
+	".set\tmips1\n\t"					\
+        "cfc1\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+#define write_32bit_cp1_register(register, value)   \
+do {                                        \
+    __asm__ __volatile__(                   \
+        "ctc1\t%z0, "STR(register)"\n\t"      \
+        : : "Jr" ((unsigned int)(value)));  \
+} while (0)
+        
+#define read_c1_status()            read_32bit_cp1_register(CP1_STATUS)
+#define read_c1_revision()          read_32bit_cp1_register(CP1_REVISION);
+#define write_c1_status(val)        write_32bit_cp1_register(CP1_STATUS, val)
+
+
+#endif /* end of __ASSEMBLY__ */
+
+#endif /* end of __MIPSREGS_H__ */
+
diff --git a/bsp/x1000/cpu/common/stackframe.h b/bsp/x1000/cpu/common/stackframe.h
new file mode 100644
index 0000000000..96b69ab14f
--- /dev/null
+++ b/bsp/x1000/cpu/common/stackframe.h
@@ -0,0 +1,228 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef __STACKFRAME_H__
+#define __STACKFRAME_H__
+
+#include "asm.h"
+#include "mipsregs.h"
+
+/*
+ * Stack layout for the INT exception handler
+ * Derived from the stack layout described in asm-mips/stackframe.h
+ *
+ * The first PTRSIZE*6 bytes are argument save space for C subroutines.
+ */
+
+//#define PT_R0		(PTRSIZE*6)			/* 0 */
+#define PT_R0		(0)						/* 0 */
+#define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
+#define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
+#define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
+#define PT_R4		((PT_R3) + LONGSIZE)	/* 4 */
+#define PT_R5		((PT_R4) + LONGSIZE)	/* 5 */
+#define PT_R6		((PT_R5) + LONGSIZE)	/* 6 */
+#define PT_R7		((PT_R6) + LONGSIZE)	/* 7 */
+#define PT_R8		((PT_R7) + LONGSIZE)	/* 8 */
+#define PT_R9		((PT_R8) + LONGSIZE)	/* 9 */
+#define PT_R10		((PT_R9) + LONGSIZE)	/* 10 */
+#define PT_R11		((PT_R10) + LONGSIZE)	/* 11 */
+#define PT_R12		((PT_R11) + LONGSIZE)	/* 12 */
+#define PT_R13		((PT_R12) + LONGSIZE)	/* 13 */
+#define PT_R14		((PT_R13) + LONGSIZE)	/* 14 */
+#define PT_R15		((PT_R14) + LONGSIZE)	/* 15 */
+#define PT_R16		((PT_R15) + LONGSIZE)	/* 16 */
+#define PT_R17		((PT_R16) + LONGSIZE)	/* 17 */
+#define PT_R18		((PT_R17) + LONGSIZE)	/* 18 */
+#define PT_R19		((PT_R18) + LONGSIZE)	/* 19 */
+#define PT_R20		((PT_R19) + LONGSIZE)	/* 20 */
+#define PT_R21		((PT_R20) + LONGSIZE)	/* 21 */
+#define PT_R22		((PT_R21) + LONGSIZE)	/* 22 */
+#define PT_R23		((PT_R22) + LONGSIZE)	/* 23 */
+#define PT_R24		((PT_R23) + LONGSIZE)	/* 24 */
+#define PT_R25		((PT_R24) + LONGSIZE)	/* 25 */
+#define PT_R26		((PT_R25) + LONGSIZE)	/* 26 */
+#define PT_R27		((PT_R26) + LONGSIZE)	/* 27 */
+#define PT_R28		((PT_R27) + LONGSIZE)	/* 28 */
+#define PT_R29		((PT_R28) + LONGSIZE)	/* 29 */
+#define PT_R30		((PT_R29) + LONGSIZE)	/* 30 */
+#define PT_R31		((PT_R30) + LONGSIZE)	/* 31 */
+
+/*
+ * Saved special registers
+ */
+#define PT_STATUS	((PT_R31) + LONGSIZE)	/* 32 */
+#define PT_HI		((PT_STATUS) + LONGSIZE)	/* 33 */
+#define PT_LO		((PT_HI) + LONGSIZE)	/* 34 */
+#define PT_BADVADDR	((PT_LO) + LONGSIZE)	/* 35 */
+#define PT_CAUSE	((PT_BADVADDR) + LONGSIZE)	/* 36 */
+#define PT_EPC		((PT_CAUSE) + LONGSIZE)	/* 37 */
+
+#define PT_SIZE		((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
+
+
+		.macro	SAVE_AT
+		.set	push
+		.set	noat
+		LONG_S	$1, PT_R1(sp)
+		.set	pop
+		.endm
+
+		.macro	SAVE_TEMP
+		mfhi	v1
+		LONG_S	$8, PT_R8(sp)
+		LONG_S	$9, PT_R9(sp)
+		LONG_S	v1, PT_HI(sp)
+		mflo	v1
+		LONG_S	$10, PT_R10(sp)
+		LONG_S	$11, PT_R11(sp)
+		LONG_S	v1,  PT_LO(sp)
+		LONG_S	$12, PT_R12(sp)
+		LONG_S	$13, PT_R13(sp)
+		LONG_S	$14, PT_R14(sp)
+		LONG_S	$15, PT_R15(sp)
+		LONG_S	$24, PT_R24(sp)
+		.endm
+
+		.macro	SAVE_STATIC
+		LONG_S	$16, PT_R16(sp)
+		LONG_S	$17, PT_R17(sp)
+		LONG_S	$18, PT_R18(sp)
+		LONG_S	$19, PT_R19(sp)
+		LONG_S	$20, PT_R20(sp)
+		LONG_S	$21, PT_R21(sp)
+		LONG_S	$22, PT_R22(sp)
+		LONG_S	$23, PT_R23(sp)
+		LONG_S	$30, PT_R30(sp)
+		.endm
+
+		.macro	get_saved_sp
+		nop
+		.endm
+
+		.macro	SAVE_SOME
+		.set	push
+		.set	noat
+		.set	reorder
+        move	k1, sp
+8:		move	k0, sp
+		PTR_SUBU sp, k1, PT_SIZE
+		LONG_S	k0, PT_R29(sp)
+		LONG_S	$3, PT_R3(sp)
+		LONG_S	$0, PT_R0(sp)
+		mfc0	v1, CP0_STATUS
+		LONG_S	$2, PT_R2(sp)
+		LONG_S	v1, PT_STATUS(sp)
+		LONG_S	$4, PT_R4(sp)
+		mfc0	v1, CP0_CAUSE
+		LONG_S	$5, PT_R5(sp)
+		LONG_S	v1, PT_CAUSE(sp)
+		LONG_S	$6, PT_R6(sp)
+		MFC0	v1, CP0_EPC
+		LONG_S	$7, PT_R7(sp)
+		LONG_S	v1, PT_EPC(sp)
+		LONG_S	$25, PT_R25(sp)
+		LONG_S	$28, PT_R28(sp)
+		LONG_S	$31, PT_R31(sp)
+		.set	pop
+		.endm
+
+		.macro	SAVE_ALL
+		SAVE_SOME
+		SAVE_AT
+		SAVE_TEMP
+		SAVE_STATIC
+		.endm
+
+		.macro	RESTORE_AT
+		.set	push
+		.set	noat
+		LONG_L	$1,  PT_R1(sp)
+		.set	pop
+		.endm
+
+		.macro	RESTORE_TEMP
+		LONG_L	$24, PT_LO(sp)
+		LONG_L	$8, PT_R8(sp)
+		LONG_L	$9, PT_R9(sp)
+		mtlo	$24
+		LONG_L	$24, PT_HI(sp)
+		LONG_L	$10, PT_R10(sp)
+		LONG_L	$11, PT_R11(sp)
+		mthi	$24
+		LONG_L	$12, PT_R12(sp)
+		LONG_L	$13, PT_R13(sp)
+		LONG_L	$14, PT_R14(sp)
+		LONG_L	$15, PT_R15(sp)
+		LONG_L	$24, PT_R24(sp)
+		.endm
+
+		.macro	RESTORE_STATIC
+		LONG_L	$16, PT_R16(sp)
+		LONG_L	$17, PT_R17(sp)
+		LONG_L	$18, PT_R18(sp)
+		LONG_L	$19, PT_R19(sp)
+		LONG_L	$20, PT_R20(sp)
+		LONG_L	$21, PT_R21(sp)
+		LONG_L	$22, PT_R22(sp)
+		LONG_L	$23, PT_R23(sp)
+		LONG_L	$30, PT_R30(sp)
+		.endm
+
+		.macro	RESTORE_SOME
+		.set	push
+		.set	reorder
+		.set	noat
+		LONG_L	v0, PT_STATUS(sp)
+		mtc0	v0, CP0_STATUS
+		LONG_L	v1, PT_EPC(sp)
+		MTC0	v1, CP0_EPC
+		LONG_L	$31, PT_R31(sp)
+		LONG_L	$28, PT_R28(sp)
+		LONG_L	$25, PT_R25(sp)
+		LONG_L	$7,  PT_R7(sp)
+		LONG_L	$6,  PT_R6(sp)
+		LONG_L	$5,  PT_R5(sp)
+		LONG_L	$4,  PT_R4(sp)
+		LONG_L	$3,  PT_R3(sp)
+		LONG_L	$2,  PT_R2(sp)
+		.set	pop
+		.endm
+
+		.macro	RESTORE_SP_AND_RET
+		LONG_L	sp, PT_R29(sp)
+		.set	mips3
+		eret
+		.set	mips0
+		.endm
+
+
+		.macro	RESTORE_SP
+		LONG_L	sp, PT_R29(sp)
+		.endm
+
+		.macro	RESTORE_ALL
+		RESTORE_TEMP
+		RESTORE_STATIC
+		RESTORE_AT
+		RESTORE_SOME
+		RESTORE_SP
+		.endm
+
+		.macro	RESTORE_ALL_AND_RET
+		RESTORE_TEMP
+		RESTORE_STATIC
+		RESTORE_AT
+		RESTORE_SOME
+		RESTORE_SP_AND_RET
+		.endm
+
+#endif /* end of __STACKFRAME_H__ */
+
diff --git a/bsp/x1000/cpu/x1000/SConscript b/bsp/x1000/cpu/x1000/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/bsp/x1000/cpu/x1000/cache.c b/bsp/x1000/cpu/x1000/cache.c
new file mode 100644
index 0000000000..5fc9682810
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/cache.c
@@ -0,0 +1,217 @@
+/*
+ * File      : cache.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016/11/02     Urey         the first version
+ */
+
+#include <rtthread.h>
+#include <board.h>
+#include <rthw.h>
+
+#include "../common/mips.h"
+
+
+#define CONFIG_SYS_DCACHE_SIZE      16384
+#define CONFIG_SYS_ICACHE_SIZE      16384
+#define CONFIG_SYS_CACHELINE_SIZE   32
+
+#define K0_TO_K1()                      \
+do {                                    \
+    unsigned long __k0_addr;            \
+                                        \
+    __asm__ __volatile__(               \
+    "la %0, 1f\n\t"                     \
+    "or %0, %0, %1\n\t"                 \
+    "jr %0\n\t"                         \
+    "nop\n\t"                           \
+    "1: nop\n"                          \
+    : "=&r"(__k0_addr)                  \
+    : "r" (0x20000000) );               \
+} while(0)
+
+#define K1_TO_K0()                      \
+do {                                    \
+    unsigned long __k0_addr;            \
+    __asm__ __volatile__(               \
+    "nop;nop;nop;nop;nop;nop;nop\n\t"       \
+    "la %0, 1f\n\t"             \
+    "jr %0\n\t"                 \
+    "nop\n\t"                   \
+    "1: nop\n"                  \
+    : "=&r" (__k0_addr));       \
+} while (0)
+
+#define INVALIDATE_BTB()        \
+do {                            \
+    unsigned long tmp;         \
+    __asm__ __volatile__(     \
+    ".set mips32\n\t"           \
+    "mfc0 %0, $16, 7\n\t"       \
+    "nop\n\t"                   \
+    "ori %0, 2\n\t"             \
+    "mtc0 %0, $16, 7\n\t"       \
+    "nop\n\t"                   \
+    ".set mips2\n\t"            \
+    : "=&r" (tmp));             \
+} while (0)
+
+#define __sync()                \
+    __asm__ __volatile__(           \
+        ".set   push\n\t"       \
+        ".set   noreorder\n\t"      \
+        ".set   mips2\n\t"      \
+        "sync\n\t"          \
+        ".set   pop"            \
+        : /* no output */       \
+        : /* no input */        \
+        : "memory")
+
+#if defined(JZ4775) || defined(X1000)
+#define SYNC_WB()               \
+do {                        \
+    __asm__ __volatile__ (          \
+    "sync\n\t"              \
+    "lw $0, %0\n\t"             \
+    :                   \
+    :"m"(*(int *)0xa0000000)        \
+    :"memory");             \
+} while (0)
+#else
+#error "not define sync wb"
+#define SYNC_WB() __asm__ __volatile__ ("sync")
+#endif
+
+
+#undef cache_op
+#define cache_op(op, addr)      \
+    __asm__ __volatile__(       \
+        ".set   push\n"     \
+        ".set   noreorder\n"    \
+        ".set   mips3\n"    \
+        "cache  %0, %1\n"   \
+        ".set   pop\n"      \
+        :           \
+        : "i" (op), "R" (*(unsigned char *)(addr)))
+
+
+void rt_hw_dcache_flush_line(rt_uint32_t addr)
+{
+	cache_op(HIT_WRITEBACK_INV_D, addr);
+	SYNC_WB();
+}
+
+void rt_hw_dcache_flush_range(rt_uint32_t start_addr, rt_uint32_t size)
+{
+    rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE;
+    rt_uint32_t addr = start_addr & ~(lsize - 1);
+    rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1);
+    rt_uint32_t writebuffer;
+
+    for (; addr <= aend; addr += lsize)
+    {
+        cache_op(HIT_WRITEBACK_INV_D, addr);
+    }
+    SYNC_WB();
+}
+
+void rt_hw_dcache_flush_all(void)
+{
+    rt_uint32_t addr;
+
+    for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
+    {
+        cache_op(INDEX_WRITEBACK_INV_D, addr);
+    }
+
+    SYNC_WB();
+}
+
+void rt_hw_dcache_invalidate_range(rt_uint32_t start_addr,rt_uint32_t size)
+{
+    rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE;
+    rt_uint32_t addr = start_addr & ~(lsize - 1);
+    rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1);
+
+    for (; addr <= aend; addr += lsize)
+        cache_op(HIT_INVALIDATE_D, addr);
+}
+
+void rt_hw_dcache_invalidate_all(void)
+{
+    rt_uint32_t addr;
+
+    for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
+    {
+        cache_op(INDEX_STORE_TAG_D, addr);
+    }
+
+    SYNC_WB();
+}
+
+void rt_hw_icache_flush_line(rt_uint32_t addr)
+{
+    cache_op(HIT_INVALIDATE_I, addr);
+}
+
+void rt_hw_icache_flush_all(void)
+{
+    rt_uint32_t addr;
+
+    asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
+    asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
+
+    for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
+    {
+        cache_op(INDEX_STORE_TAG_I, addr);
+    }
+
+    INVALIDATE_BTB();
+}
+
+void rt_hw_icache_invalidate_all(void)
+{
+    rt_uint32_t i;
+
+    K0_TO_K1();
+
+    asm volatile (".set noreorder\n"
+              ".set mips32\n\t"
+              "mtc0\t$0,$28\n\t"
+              "mtc0\t$0,$29\n"
+              ".set mips0\n"
+              ".set reorder\n");
+    for (i = CKSEG0; i < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; i += CONFIG_SYS_CACHELINE_SIZE)
+        cache_op(INDEX_STORE_TAG_I, i);
+
+    K1_TO_K0();
+
+    INVALIDATE_BTB();
+}
+
+
+void rt_hw_flush_cache_all(void)
+{
+    rt_hw_dcache_flush_all();
+    rt_hw_icache_flush_all();
+}
+
+
+
diff --git a/bsp/x1000/cpu/x1000/cache.h b/bsp/x1000/cpu/x1000/cache.h
new file mode 100644
index 0000000000..0454527d91
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/cache.h
@@ -0,0 +1,41 @@
+/*
+ * File      : cache.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��19��     Urey         the first version
+ */
+
+#ifndef _X1000_CACHE_H_
+#define _X1000_CACHE_H_
+
+#include "../common/mips.h"
+#include "../common/mips_cache.h"
+
+
+void rt_hw_icache_invalidate_all(void);
+void rt_hw_icache_flush_all(void);
+
+void rt_hw_dcache_flush_all(void);
+void rt_hw_dcache_flush_range(rt_uint32_t addr, rt_uint32_t size);
+void rt_hw_dcache_invalidate_all(void);
+void rt_hw_dcache_invalidate_range(rt_uint32_t addr,rt_uint32_t size);
+
+void rt_hw_flush_cache_all(void);
+#endif /* _X1000_CACHE_H_ */
diff --git a/bsp/x1000/cpu/x1000/cpu.c b/bsp/x1000/cpu/x1000/cpu.c
new file mode 100644
index 0000000000..e1a51b9fe7
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/cpu.c
@@ -0,0 +1,131 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��8��     Urey         the first version
+ */
+
+
+#include <rtthread.h>
+#include <board.h>
+#include <rthw.h>
+
+#include "../common/mips.h"
+
+mips32_core_cfg_t g_mips_core =
+{
+	.icache_line_size 	= 32,
+	.icache_size		= 16384,
+
+	.dcache_line_size 	= 32,
+	.dcache_size		= 16384,
+
+	.max_tlb_entries 	= 16,		/* max_tlb_entries */
+};
+
+void rt_hw_tlb_init(void)
+{
+//----------------------------------------------------------------------------------
+//cchappy tlb  0x30000000 to 0xC0000000
+//----------------------------------------------------------------------------------
+	unsigned int pagemask = 0x007fe000;//0x01ffe000; /* 4MB */
+	/* cached D:allow-W V:valid G */
+	unsigned int entrylo0 = (0x30000000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
+	unsigned int entrylo1 = (0x30400000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
+	unsigned int entryhi 	= 0xc0000000; /* kseg2 base */
+	int i;
+	__write_32bit_c0_register($5, 4, 0xa9000000);
+	write_c0_pagemask(pagemask);
+	write_c0_wired(0);
+/* indexed write 32 tlb entry */
+	for(i = 0; i < 32; i++)
+	{
+		asm (
+		".macro _ssnop; sll $0, $0, 1; .endm\n\t"
+		".macro _ehb; sll $0, $0, 3; .endm\n\t"
+		".macro mtc0_tlbw_hazard; _ssnop; _ssnop; _ehb; .endm\n\t"
+		".macro tlbw_use_hazard; _ssnop; _ssnop; _ssnop; _ehb; .endm\n\t"
+		"\n\t"
+		"mtc0 %0, $0\n\t" /* write Index */
+		"tlbw_use_hazard\n\t"
+		"mtc0 %1, $5\n\t" /* write PageMask */
+		"mtc0 %2, $10\n\t" /* write EntryHi */
+		"mtc0 %3, $2\n\t" /* write EntryLo0 */
+		"mtc0 %4, $3\n\t" /* write EntryLo1 */
+		"mtc0_tlbw_hazard\n\t"
+		"tlbwi \n\t" /* TLB indexed write */
+		"tlbw_use_hazard\n\t"
+		: : "Jr" (i), "r" (pagemask), "r" (entryhi),
+		"r" (entrylo0), "r" (entrylo1)
+		);
+		entryhi += 0x0800000; /* 32MB */
+		entrylo0 += (0x0800000 >> 6);
+		entrylo1 += (0x0800000 >> 6);
+	}
+}
+
+void rt_hw_cache_init(void)
+{
+	r4k_cache_flush_all();
+}
+
+/**
+ * this function will reset CPU
+ *
+ */
+RT_WEAK void rt_hw_cpu_reset()
+{
+    /* open the watch-dog */
+    REG_WDT_TCSR  = WDT_TCSR_EXT_EN;
+    REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
+    REG_WDT_TDR   = 0x03;
+    REG_WDT_TCNT  = 0x00;
+    REG_WDT_TCER |= WDT_TCER_TCEN;
+
+    rt_kprintf("reboot system...\n");
+    rt_hw_interrupt_disable();
+    while (1);
+}
+
+/**
+ * this function will shutdown CPU
+ *
+ */
+RT_WEAK void rt_hw_cpu_shutdown()
+{
+	rt_kprintf("shutdown...\n");
+	rt_hw_interrupt_disable();
+	while (1);
+}
+
+/**
+ * This function finds the first bit set (beginning with the least significant bit)
+ * in value and return the index of that bit.
+ *
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
+ * zero from any of these functions means that the argument was zero.
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
+ * shall return 0.
+ */
+RT_WEAK int __rt_ffs(int value)
+{
+    return __builtin_ffs(value);
+}
diff --git a/bsp/x1000/cpu/x1000/interrupt.c b/bsp/x1000/cpu/x1000/interrupt.c
new file mode 100644
index 0000000000..2a7a42e792
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/interrupt.c
@@ -0,0 +1,215 @@
+/*
+ * File      : cpu_intc.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016/09/07     Urey         the first version
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "../common/mips.h"
+
+#define INTERRUPTS_MAX	64
+
+extern rt_uint32_t rt_interrupt_nest;
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+static struct rt_irq_desc isr_table[INTERRUPTS_MAX];
+
+static void rt_hw_interrupt_handler(int vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+void rt_hw_interrupt_init(void)
+{
+    rt_int32_t idx;
+
+	clear_c0_status(0xff04); /* clear ERL */
+	set_c0_status(0x0400);   /* set IP2 */
+
+
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+    for (idx = 0; idx < INTERRUPTS_MAX; idx ++)
+    {
+        isr_table[idx].handler = rt_hw_interrupt_handler;
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest               = 0;
+    rt_interrupt_from_thread        = 0;
+    rt_interrupt_to_thread          = 0;
+    rt_thread_switch_interrupt_flag = 0;
+
+	/* enable cpu interrupt mask */
+	set_c0_status(IE_IRQ0 | IE_IRQ1);
+}
+
+void rt_hw_interrupt_mask(int vector)
+{
+    /* mask interrupt */
+    __intc_mask_irq(vector);
+}
+
+void rt_hw_interrupt_umask(int vector)
+{
+    __intc_unmask_irq(vector);
+}
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector < INTERRUPTS_MAX)
+    {
+        old_handler = isr_table[vector].handler;
+
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+        isr_table[vector].handler = handler;
+        isr_table[vector].param = param;
+    }
+
+    return old_handler;
+}
+
+rt_inline int fls(int x)
+{
+    __asm__("clz %0, %1" : "=r" (x) : "r" (x));
+
+    return 32 - x;
+}
+
+void rt_interrupt_dispatch(void *ptreg)
+{
+    void *param;
+    rt_isr_handler_t irq_func;
+
+    int irq = 0, group;
+    rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0;
+
+    rt_uint32_t c0_status, c0_cause;
+    rt_uint32_t pending_im;
+
+    /* check os timer */
+    c0_status = read_c0_status();
+    c0_cause = read_c0_cause();
+
+	pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM);
+
+    if (pending_im & CAUSEF_IP3)
+    {
+		extern void rt_hw_ost_handler(void);
+        rt_hw_ost_handler();
+        return;
+    }
+    if (pending_im & CAUSEF_IP2)
+    {
+        intc_ipr0 = REG_INTC_IPR(0);
+        intc_ipr1 = REG_INTC_IPR(1);
+
+        if (intc_ipr0)
+        {
+            irq = fls(intc_ipr0) - 1;
+            intc_ipr0 &= ~(1<<irq);
+        }
+        else if(intc_ipr1)
+        {
+            irq = fls(intc_ipr1) - 1;
+            intc_ipr1 &= ~(1<<irq);
+            irq += 32;
+        }
+        else
+        {
+        	//VPU
+        }
+
+        if (irq >= INTERRUPTS_MAX)
+            rt_kprintf("max interrupt, irq=%d\n", irq);
+
+        /* do interrupt */
+        irq_func = isr_table[irq].handler;
+        param = isr_table[irq].param;
+        (*irq_func)(irq, param);
+
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif /* RT_USING_INTERRUPT_INFO */
+
+        /* ack interrupt */
+        __intc_ack_irq(irq);
+    }
+
+    if (pending_im & CAUSEF_IP0)
+        rt_kprintf("CAUSEF_IP0\n");
+    if (pending_im & CAUSEF_IP1)
+        rt_kprintf("CAUSEF_IP1\n");
+    if (pending_im & CAUSEF_IP4)
+        rt_kprintf("CAUSEF_IP4\n");
+    if (pending_im & CAUSEF_IP5)
+        rt_kprintf("CAUSEF_IP5\n");
+    if (pending_im & CAUSEF_IP6)
+        rt_kprintf("CAUSEF_IP6\n");
+    if (pending_im & CAUSEF_IP7)
+        rt_kprintf("CAUSEF_IP7\n");
+}
+
+#ifdef RT_USING_INTERRUPT_INFO
+#include <finsh.h>
+int list_irqs(void)
+{
+    int index;
+
+    rt_kprintf("interrupt list:\n");
+    rt_kprintf("----------------\n");
+    rt_kprintf("name     counter\n");
+    for (index = 0; index < INTERRUPTS_MAX; index ++)
+    {
+        if (isr_table[index].handler != rt_hw_interrupt_handler)
+        {
+            rt_kprintf("%-*.*s %d\n", RT_NAME_MAX, RT_NAME_MAX, isr_table[index].name, isr_table[index].counter);
+        }
+    }
+
+    return 0;
+}
+MSH_CMD_EXPORT(list_irqs, list interrupt counter);
+#endif
+
+unsigned int spin_lock_irqsave(void)
+{
+	register unsigned int t;
+	t = read_c0_status();
+	write_c0_status((t & (~1)));
+	return (t);
+}
+
+void spin_unlock_irqrestore(unsigned int val)
+{
+	write_c0_status(val);
+}
diff --git a/bsp/x1000/cpu/x1000/mips_backtrace.c b/bsp/x1000/cpu/x1000/mips_backtrace.c
new file mode 100644
index 0000000000..b8a861bad5
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/mips_backtrace.c
@@ -0,0 +1,208 @@
+/*
+ * File      : mips_backtrace.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��11��     Urey         the first version
+ */
+
+#include <rtthread.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+
+#include "mips.h"
+
+/*********************************************************************************************************
+  ָ���
+*********************************************************************************************************/
+#define ADDUI_SP_INST           0x27bd0000
+#define SW_RA_INST              0xafbf0000
+#define JR_RA_INST              0x03e00008
+
+#define INST_OP_MASK            0xffff0000
+#define INST_OFFSET_MASK        0x0000ffff
+
+#define abs(s) ((s) < 0 ? -(s):(s))
+
+int backtrace_ctx(mips_reg_ctx *ctx)
+{
+	unsigned long *addr;
+	unsigned long *pc, *ra, *sp;
+	size_t ra_offset;
+	size_t stack_size;
+	int depth;
+	int size = 8;
+
+	pc = (unsigned long *)(unsigned long)ctx->CP0EPC;
+	ra = (unsigned long *)(unsigned long)ctx->regs[REG_RA];
+	sp = (unsigned long *)(unsigned long)ctx->regs[REG_SP];
+
+	rt_kprintf("[0x%08x]\n", pc);
+
+	if (size == 1) return 1;
+
+	ra_offset = stack_size = 0;
+
+	for (addr = ra; !ra_offset || !stack_size; --addr)
+	{
+		switch (*addr & INST_OP_MASK) {
+			case ADDUI_SP_INST:
+				stack_size = abs((short)(*addr&INST_OFFSET_MASK));
+				break;
+
+			case SW_RA_INST:
+				ra_offset = (short)(*addr&INST_OFFSET_MASK);
+				break;
+
+			case 0x3c1c0000:
+				goto out_of_loop;
+
+			default:
+				break;
+		}
+	}
+
+out_of_loop:
+	if (ra_offset)  ra = *(unsigned long **)((unsigned long)sp + ra_offset);
+	if (stack_size) sp = (unsigned long *)((unsigned long)sp + stack_size);
+
+	// repeat backwar scanning
+	for (depth = 1; depth < size && ra && ra != (unsigned long *)0xffffffff; ++depth)
+	{
+		rt_kprintf("RA[%2d] : [0x%08x]\n", depth ,ra);
+
+		ra_offset = 0;
+		stack_size = 0;
+
+		for ( addr = ra; !ra_offset || !stack_size; -- addr )
+		{
+			switch( *addr & INST_OP_MASK)
+			{
+				case ADDUI_SP_INST:
+					stack_size = abs((short)(*addr&INST_OFFSET_MASK));
+					break;
+
+				case SW_RA_INST:
+					ra_offset = abs((short)(*addr&INST_OFFSET_MASK));
+					break;
+
+				case 0x3c1c0000:
+					return depth +1;
+
+				default:
+					break;
+			}
+		}
+
+		ra = *(unsigned long **)((unsigned long)sp + ra_offset);
+		sp = (unsigned long *)((unsigned long)sp + stack_size);
+	}
+
+	return depth;
+}
+
+int backtrace(void)
+{
+	unsigned long *addr;
+	unsigned long *ra;
+	unsigned long *sp;
+	int size = 8, depth;
+
+	size_t ra_offset;
+	size_t stack_size;
+
+	// get current $a and $sp
+	__asm__ __volatile__ (
+			" move %0, $ra\n"
+			" move %1, $sp\n"
+			: "=r"(ra), "=r"(sp)
+			);
+
+	// scanning to find the size of hte current stack frame
+	stack_size  = 0;
+
+	for ( addr = (unsigned long *)backtrace; !stack_size; ++addr)
+	{
+		if ((*addr & INST_OP_MASK ) == ADDUI_SP_INST )
+			stack_size = abs((short)(*addr&INST_OFFSET_MASK));
+		else if ( *addr == JR_RA_INST )
+			break;
+	}
+
+	sp = (unsigned long *) (( unsigned long )sp + stack_size);
+
+	// repeat backwar scanning
+	for ( depth = 0; depth < size && ((( unsigned long )ra > KSEG0BASE) && (( unsigned long )ra < KSEG1BASE)); ++ depth )
+	{
+		rt_kprintf("RA[%2d] : [0x%08x]\n", depth, ra);
+		{
+			extern void rt_thread_exit(void);
+			if ((uint32_t)ra == (uint32_t)(rt_thread_exit))
+				return depth;
+		}
+
+		ra_offset = 0;
+		stack_size = 0;
+
+		for ( addr = ra; !ra_offset || !stack_size; -- addr )
+		{
+			switch( *addr & INST_OP_MASK)
+			{
+				case ADDUI_SP_INST:
+					stack_size = abs((short)(*addr&INST_OFFSET_MASK));
+					break;
+
+				case SW_RA_INST:
+					ra_offset = (short)(*addr&INST_OFFSET_MASK);
+					break;
+
+				case 0x3c1c0000:
+					return depth +1;
+
+				default:
+					break;
+			}
+		}
+
+		ra = *(unsigned long **)((unsigned long)sp + ra_offset);
+		sp = (unsigned long*) ((unsigned long)sp+stack_size );
+	}
+
+	return depth;
+}
+
+#include <rtthread.h>
+extern long list_thread(void);
+void assert_hook(const char* ex, const char* func, rt_size_t line)
+{
+	backtrace();
+
+	list_thread();
+	rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex, func, line);
+}
+
+int backtrace_init(void)
+{
+#ifdef RT_DEBUG
+	rt_assert_set_hook(assert_hook);
+#endif
+	return 0;
+}
+INIT_DEVICE_EXPORT(backtrace_init);
diff --git a/bsp/x1000/cpu/x1000/mips_cache_gcc.S b/bsp/x1000/cpu/x1000/mips_cache_gcc.S
new file mode 100644
index 0000000000..cc69cba1a6
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/mips_cache_gcc.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-19     Urey         first version
+ */
+
+#ifndef __ASSEMBLY__
+#define	__ASSEMBLY__
+#endif
+
+#include "../common/mips.h"
+
+    .text
+    .set noreorder
+
+    .globl  cache_init
+    .ent    cache_init
+cache_init:
+    .set    noreorder
+    mtc0    zero, CP0_TAGLO
+    move    t0, a0                  // cache total size
+    move    t1, a1                  // cache line size
+    li      t2, 0x80000000
+    addu    t3, t0, t2
+
+_cache_init_loop:
+    cache   8, 0(t2)                // icache_index_store_tag
+    cache   9, 0(t2)                // dcache_index_store_tag
+    addu    t2, t1
+    bne     t2, t3, _cache_init_loop
+    nop
+
+    mfc0    t0, CP0_CONFIG
+    li      t1, 0x7
+    not     t1
+    and     t0, t0, t1
+    or      t0, 0x3                 // cacheable, noncoherent, write-back, write allocate
+    mtc0    t0, CP0_CONFIG
+
+    jr      ra
+    nop
+
+    .set    reorder
+    .end    cache_init
diff --git a/bsp/x1000/cpu/x1000/mips_context_gcc.S b/bsp/x1000/cpu/x1000/mips_context_gcc.S
new file mode 100644
index 0000000000..5cb473a72a
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/mips_context_gcc.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-07     Urey         first version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips.h"
+
+	.global	rt_thread_switch_interrupt_flag
+    .global	rt_interrupt_from_thread
+    .global	rt_interrupt_to_thread
+
+    .section .text,"ax",@progbits
+    .set noreorder
+    .set noat
+
+    .globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mfc0 	v0,CP0_STATUS
+    srl 	v1,v0,1
+    sll 	v1,v1,1
+#	and 	v1,v0,0xfffffffe
+    mtc0 	v1,CP0_STATUS
+    jr 		ra
+    nop
+
+LEAF(rt_hw_interrupt_enable)
+    mtc0 	a0,CP0_STATUS
+    jr 		ra
+    nop
+END(rt_hw_interrupt_enable)
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to)/*
+ * a0 --> to
+ */
+LEAF(rt_hw_context_switch_to)
+	lw 	sp ,	0(a0)                 	/* switch to the new stack */
+    RESTORE_CONTEXT
+END(rt_hw_context_switch_to)
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
+ * a0 --> from
+ * a1 --> to
+ */
+LEAF(rt_hw_context_switch)
+	mtc0    ra, CP0_EPC
+    SAVE_CONTEXT
+
+    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
+    lw      sp, 0(a1)       /* get new task stack pointer */
+
+	RESTORE_CONTEXT
+END(rt_hw_context_switch)
+
+LEAF(rt_hw_context_switch_interrupt)
+    la      t0, rt_thread_switch_interrupt_flag
+    lw      t1, 0(t0)
+    nop
+    bnez    t1, _reswitch
+    nop
+    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
+    sw      t1, 0(t0)
+    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
+    sw      a0, 0(t0)
+_reswitch:
+    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
+    sw      a1, 0(t0)
+    jr      ra
+    nop
+END(rt_hw_context_switch_interrupt)
+
diff --git a/bsp/x1000/cpu/x1000/mips_excpt.c b/bsp/x1000/cpu/x1000/mips_excpt.c
new file mode 100644
index 0000000000..5d2a3dce6d
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/mips_excpt.c
@@ -0,0 +1,382 @@
+/*
+ * File      : mips_excpt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��7��     Urey         the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <stdio.h>
+
+#include "mips.h"
+#include "mips_excpt.h"
+
+extern int backtrace(void);
+int backtrace_ctx(mips_reg_ctx *ctx);
+
+extern long list_thread(void);
+
+const static char *regstr[] = {
+	"$0  zero", "$1  at", "$2  v0", "$3  v1", "$4  a0", "$5  a1", "$6  a2", "$7  a3",
+	"$8  t0", "$9  t1", "$10 t2", "$11 t3", "$12 t4", "$13 t5", "$14 t6", "$15 t7",
+	"$16 s0", "$17 s1", "$18 s2", "$19 s3", "$20 s4", "$21 s5", "$22 s6", "$23 s7",
+	"$24 t8", "$25 t9", "$26 k0", "$27 k1", "$28 gp", "$29 sp", "$30 fp", "$31 ra"
+};
+
+static const char *cause_strings[32] =
+{
+  /*  0 */ "Int",
+  /*  1 */ "TLB Mods",
+  /*  2 */ "TLB Load",
+  /*  3 */ "TLB Store",
+  /*  4 */ "Address Load",
+  /*  5 */ "Address Store",
+  /*  6 */ "Instruction Bus Error",
+  /*  7 */ "Data Bus Error",
+  /*  8 */ "Syscall",
+  /*  9 */ "Breakpoint",
+  /* 10 */ "Reserved Instruction",
+  /* 11 */ "Coprocessor Unuseable",
+  /* 12 */ "Overflow",
+  /* 13 */ "Trap",
+  /* 14 */ "Instruction Virtual Coherency Error",
+  /* 15 */ "FP Exception",
+  /* 16 */ "Reserved 16",
+  /* 17 */ "Reserved 17",
+  /* 18 */ "Reserved 18",
+  /* 19 */ "Reserved 19",
+  /* 20 */ "Reserved 20",
+  /* 21 */ "Reserved 21",
+  /* 22 */ "Reserved 22",
+  /* 23 */ "Watch",
+  /* 24 */ "Reserved 24",
+  /* 25 */ "Reserved 25",
+  /* 26 */ "Reserved 26",
+  /* 27 */ "Reserved 27",
+  /* 28 */ "Reserved 28",
+  /* 29 */ "Reserved 29",
+  /* 30 */ "Reserved 30",
+  /* 31 */ "Data Virtual Coherency Error"
+};
+
+
+/**
+ * exception handle table
+ */
+exception_func_t sys_exception_handlers[32];
+
+static void mod_handler(mips_reg_ctx *regs)
+{
+    rt_kprintf("tlb modification exception\n");
+    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
+    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
+
+    list_thread();
+
+    printf("-----------------------------------------------------\n");
+    printf("BACKTRACE:\n");
+    backtrace();
+    printf("-----------------------------------------------------\n");
+
+    rt_hw_cpu_shutdown();
+}
+
+static void tlbl_handler(mips_reg_ctx *regs)
+{
+    rt_kprintf("tlb exception: load\n");
+    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
+    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
+
+    list_thread();
+
+    printf("-----------------------------------------------------\n");
+    printf("BACKTRACE:\n");
+    backtrace();
+    printf("-----------------------------------------------------\n");
+
+    rt_hw_cpu_shutdown();
+}
+
+static void tlbs_handler(mips_reg_ctx *regs)
+{
+    rt_kprintf("tlb exception: store\n");
+    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
+    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
+
+    list_thread();
+
+    printf("-----------------------------------------------------\n");
+    printf("BACKTRACE:\n");
+    backtrace();
+    printf("-----------------------------------------------------\n");
+
+    rt_hw_cpu_shutdown();
+}
+
+static void adel_handler(mips_reg_ctx *regs)
+{
+    rt_kprintf("address error exception: load\n");
+    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
+    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
+
+    list_thread();
+    rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, rt_thread_self()->name);
+
+    printf("-----------------------------------------------------\n");
+    printf("BACKTRACE:\n");
+    backtrace();
+    printf("-----------------------------------------------------\n");
+
+    rt_hw_cpu_shutdown();
+}
+
+static void ades_handler(mips_reg_ctx *regs)
+{
+    rt_kprintf("address error exception: store\n");
+    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
+    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
+
+    list_thread();
+
+    printf("-----------------------------------------------------\n");
+    printf("BACKTRACE:\n");
+    backtrace();
+    printf("-----------------------------------------------------\n");
+
+    rt_hw_cpu_shutdown();
+}
+
+static void fpe_handler(mips_reg_ctx *regs)
+{
+    rt_kprintf("floating point exception\n");
+    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
+    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
+
+    list_thread();
+
+    printf("-----------------------------------------------------\n");
+    printf("BACKTRACE:\n");
+    backtrace();
+    printf("-----------------------------------------------------\n");
+
+    rt_hw_cpu_shutdown();
+}
+
+
+static void unhandled_exception_handle(mips_reg_ctx *regs)
+{
+	int i;
+	unsigned int cause = read_c0_cause();
+	unsigned int exc = (cause >> 2) & 0x1f;
+
+	rt_kprintf("exception happens, epc: 0x%08x\n", regs->CP0EPC);
+	rt_kprintf("                 cause: 0x%08x\n", regs->CP0Cause);
+
+	for (i = 0; i < 32; i++)
+	{
+		if (i % 4 == 0)
+			printf("\n");
+		printf("%8s %08x ", regstr[i], regs->regs[i]);
+	}
+	printf("\n");
+
+	list_thread();
+	rt_hw_cpu_shutdown();
+}
+
+static void install_default_exception_handler(void)
+{
+    int i;
+
+    for (i=0; i<sizeof(sys_exception_handlers)/sizeof(sys_exception_handlers[0]); i++)
+        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
+
+    sys_exception_handlers[EX_MOD]  = mod_handler;
+    sys_exception_handlers[EX_TLBL] = tlbl_handler;
+    sys_exception_handlers[EX_TLBS] = tlbs_handler;
+    sys_exception_handlers[EX_ADEL] = adel_handler;
+    sys_exception_handlers[EX_ADES] = ades_handler;
+    sys_exception_handlers[EX_FPE]  = fpe_handler;
+}
+
+int rt_hw_exception_init(void)
+{
+    /* install the default exception handler */
+    install_default_exception_handler();
+
+    return RT_EOK;
+}
+
+/**
+ * setup the exception handle
+ */
+exception_func_t rt_set_except_vector(int n, exception_func_t func)
+{
+    exception_func_t old_handler = sys_exception_handlers[n];
+
+    if ((n == 0) || (n > 32) || (!func))
+    {
+        return 0;
+    }
+
+    sys_exception_handlers[n] = func;
+
+    return old_handler;
+}
+
+void mips_exception_handler(mips_reg_ctx *ctx)
+{
+	static int read_epc_count = 0;
+	static int epc_save = 0;
+	int 	i;
+	unsigned int epc;
+
+	//��� read_epc_count>0 ˵�� c_except_handler �ڶ� epc ʱ�����ˣ����� epc ������һ���µ��쳣
+	if (read_epc_count > 0)
+	{
+		printf("ERROR: read epc fail when except handle\n");
+		epc = epc_save;
+		read_epc_count = 0;
+	}
+	else
+	{
+		read_epc_count++;
+		epc_save 	= 0;
+		epc 		= read_c0_epc();
+		epc_save 	= epc;
+
+		if (epc != 0)
+		{
+			printf("-----------------------------------------------------\n");
+			for (i = 0; i < 4; i++)
+			{
+				printf("%08x:\t%08x\n",
+				       (epc - 4 * 4 + i * 4),
+				       *(unsigned int *) ((epc - 4 * 4 + i * 4) | 0xa0000000));
+			}
+			for (i = 0; i < 4; i++)
+			{
+				printf("%08x:\t%08x\n",
+				       (epc + i * 4),
+				       *(unsigned int *) ((epc + i * 4) | 0xa0000000));
+			}
+			printf("-----------------------------------------------------\n");
+		}
+
+		read_epc_count--;
+	}
+
+	printf("-----------------------------------------------------\n");
+	unsigned int cause = read_c0_cause();
+	unsigned int exc = (cause >> 2) & 0x1f;
+	printf("CAUSE=%08x --> %s\n", cause, cause_strings[exc]);
+	printf("EPC=%08x\n", epc);
+
+	for (i = 0; i < 32; i++)
+	{
+		if ((i != 0) && (i % 4 == 0))
+			printf("\n");
+		printf("%8s %08x ", regstr[i], ctx->regs[i]);
+	}
+	printf("\n-----------------------------------------------------\n");
+	printf("%s: \t %8x\n","CP0Status  ",	ctx->CP0Status);
+	printf("%s: \t %8x\n","CP0DataHI  ",	ctx->CP0DataHI);
+	printf("%s: \t %8x\n","CP0DataLO  ",	ctx->CP0DataLO);
+	printf("%s: \t %8x\n","CP0BadVAddr",	ctx->CP0BadVAddr);
+	printf("%s: \t %8x\n","CP0Cause   ",	ctx->CP0Cause);
+	printf("%s: \t %8x\n","CP0EPC     ",	ctx->CP0EPC);
+	printf("-----------------------------------------------------\n");
+
+#if 0
+	switch (exc)
+	{
+	case EX_MOD:
+	 /*  TLB modified                */
+		break;
+
+    case EX_TLBL:                                                       /*  TLB exc(load or ifetch)     */
+    case EX_TLBS:                                                       /*  TLB exception (store)       */
+
+    	break;
+
+    case EX_ADEL:                                                       /*  Address err(load or ifetch) */
+    case EX_ADES:                                                       /*  Address error (store)       */
+
+    	break;
+
+    case EX_IBE:                                                        /*  Instruction Bus Error       */
+    case EX_DBE:                                                        /*  Data Bus Error              */
+
+    	break;
+
+    case EX_SYS:                                                        /*  Syscall                     */
+
+    	break;
+
+    case EX_BP:                                                         /*  Breakpoint                  */
+    case EX_TR:                                                         /*  Trap instruction            */
+
+    	break;
+    case EX_RI:                                                         /*  Reserved instruction        */
+
+    	break;
+    case EX_FPE:                                                        /*  floating point exception    */
+    	break;
+
+    case EX_CPU:                                                        /*  CoProcessor Unusable        */
+
+    	break;
+    case EX_OV:                                                         /*  OVerflow                    */
+    case EX_C2E:                                                        /*  COP2 exception              */
+    case EX_MDMX:                                                       /*  MDMX exception              */
+    case EX_WATCH:                                                      /*  Watch exception             */
+    case EX_MCHECK:                                                     /*  Machine check exception     */
+    case EX_CacheErr:                                                   /*  Cache error caused re-entry */
+                                                                        /*  to Debug Mode               */
+
+    	break;
+    default:
+    	rt_kprintf("Unknow exception: %d\r\n", exc);
+    	break;
+	}
+#else
+	sys_exception_handlers[exc](ctx);
+#endif
+
+	rt_hw_cpu_shutdown();
+}
+
+
+void mips_cache_error_handler (unsigned int  Addr)
+{
+	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
+	list_thread();
+	rt_hw_cpu_shutdown();
+}
+
+void mips_tlb_refill_handler(void)
+{
+	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
+	rt_kprintf("                cause: 0x%08x\n", read_c0_cause());
+	list_thread();
+	rt_kprintf("current thread: %s\n", rt_thread_self()->name);
+	rt_hw_cpu_shutdown();
+}
diff --git a/bsp/x1000/cpu/x1000/mips_excpt_gcc.S b/bsp/x1000/cpu/x1000/mips_excpt_gcc.S
new file mode 100644
index 0000000000..bca6fd1956
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/mips_excpt_gcc.S
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-07     Urey         first version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips.h"
+
+#define _EXC_STKSIZE 	20*1024
+
+;/*********************************************************************************************************
+;  PTE BASE ��ض���
+;*********************************************************************************************************/
+
+#define PTE_BASE_OFFSET                 23
+#define PTE_BASE_SIZE                   9
+#define MIPS32_BADVPN2_SHIFT            2
+
+
+    .section ".text", "ax"
+    .set	noreorder
+
+LEAF(mips_tlb_refill_handlerx)
+    .set    push
+    .set    noat
+    .set    noreorder
+    .set    volatile
+
+    ;/*
+    ; * K1 = CP0_CTXT
+    ; * K0 = K1
+    ; */
+    mfc0    k1 , CP0_CONTEXT                                            ;/*  K1 ���� Context �Ĵ���      */
+    ehb
+    move    k0 , k1                                                     ;/*  K0 ���� Context �Ĵ���      */
+
+    ;/*
+    ; * K1 <<= PTE_BASE_SIZE
+    ; * K1 >>= PTE_BASE_SIZE
+    ; * K1 >>= 4
+    ; * K1 >>= MIPS32_BADVPN2_SHIFT
+    ; * K1 <<= 3
+    ; */
+    sll     k1 , PTE_BASE_SIZE
+    srl     k1 , (PTE_BASE_SIZE + 4 + MIPS32_BADVPN2_SHIFT)             ;/*  K1 Ϊ BAD VPN2              */
+    sll     k1 , (4 - 1)
+
+    ;/*
+    ; * K0 >>= PTE_BASE_OFFSET
+    ; * K0 <<= PTE_BASE_OFFSET
+    ; */
+    srl     k0 , PTE_BASE_OFFSET
+    sll     k0 , PTE_BASE_OFFSET                                        ;/*  K0 Ϊ PTE BASE              */
+
+    ;/*
+    ; * K1 = K1 | K0
+    ; */
+    or      k1 , k1 , k0                                                ;/*  �ϳ�                        */
+
+    ;/*
+    ; * K0 = *K1
+    ; * K1 = *(K1 + 4)
+    ; */
+    lw      k0 , 0(k1)
+    lw      k1 , 4(k1)
+
+    ;/*
+    ; * CP0_TLBLO0 = K0
+    ; * CP0_TLBLO1 = K1
+    ; */
+    mtc0    k0 , CP0_ENTRYLO0                                             ;/*  EntryLo0                    */
+    mtc0    k1 , CP0_ENTRYLO1                                             ;/*  EntryLo1                    */
+    ehb
+
+    tlbwr                                                               ;/*  TLB ����滻                */
+
+    eret                                                                ;/*  �쳣����                    */
+
+    .set    pop
+END(mips_tlb_refill_handlerx)
diff --git a/bsp/x1000/cpu/x1000/mips_fp_gcc.S b/bsp/x1000/cpu/x1000/mips_fp_gcc.S
new file mode 100644
index 0000000000..303519afe4
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/mips_fp_gcc.S
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-09     Urey         first version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#ifdef __mips_hard_float
+
+.module hardfloat
+.module doublefloat
+.set nomips16
+
+#include "../common/mips.h"
+#undef fp
+
+	.global mips_vfp32_init
+LEAF(mips_vfp32_init)
+    mfc0 	t0, CP0_STATUS
+    or      t0 , M_StatusCU1
+    mtc0 	t0, CP0_STATUS
+    jr      ra
+    nop
+END(mips_vfp32_init)
+
+#
+# FUNCTION:	_fpctx_save
+#
+# DESCRIPTION:	save floating point registers to memory starting at a0
+#
+# RETURNS:	int
+#			0:	No context saved
+#			CTX_*:	Type of context stored
+#
+	.global _fpctx_save
+LEAF(_fpctx_save)
+	sw 		zero, LINKCTX_NEXT(a0)
+	mfc0	t0, CP0_STATUS
+	li		t1, M_StatusCU1
+	and		t1, t0, t1
+	bnez	t1, 1f
+	# FP not enabled, bail out
+	move	v0, zero
+	jr		ra
+
+1:	# Save FP32 base
+	li		t1, ST0_FR
+	and		t0, t0, t1
+	cfc1	t2, $31
+	sw		t2, FP32CTX_CSR(a0)
+	sdc1	$f0, FP32CTX_0(a0)
+	sdc1	$f2, FP32CTX_2(a0)
+	sdc1	$f4, FP32CTX_4(a0)
+	sdc1	$f6, FP32CTX_6(a0)
+	sdc1	$f8, FP32CTX_8(a0)
+	sdc1	$f10, FP32CTX_10(a0)
+	sdc1	$f12, FP32CTX_12(a0)
+	sdc1	$f14, FP32CTX_14(a0)
+	sdc1	$f16, FP32CTX_16(a0)
+	sdc1	$f18, FP32CTX_18(a0)
+	sdc1	$f20, FP32CTX_20(a0)
+	sdc1	$f22, FP32CTX_22(a0)
+	sdc1	$f24, FP32CTX_24(a0)
+	sdc1	$f26, FP32CTX_26(a0)
+	sdc1	$f28, FP32CTX_28(a0)
+	sdc1	$f30, FP32CTX_30(a0)
+	bnez	t0, 2f
+	li		v0, LINKCTX_TYPE_FP32
+	sw		v0, LINKCTX_ID(a0)
+	jr		ra
+
+2:	# Save FP64 extra
+.set	push
+.set	fp=64
+	sdc1	$f1, FP64CTX_1(a0)
+	sdc1	$f3, FP64CTX_3(a0)
+	sdc1	$f5, FP64CTX_5(a0)
+	sdc1	$f7, FP64CTX_7(a0)
+	sdc1	$f9, FP64CTX_9(a0)
+	sdc1	$f11, FP64CTX_11(a0)
+	sdc1	$f13, FP64CTX_13(a0)
+	sdc1	$f15, FP64CTX_15(a0)
+	sdc1	$f17, FP64CTX_17(a0)
+	sdc1	$f19, FP64CTX_19(a0)
+	sdc1	$f21, FP64CTX_21(a0)
+	sdc1	$f23, FP64CTX_23(a0)
+	sdc1	$f25, FP64CTX_25(a0)
+	sdc1	$f27, FP64CTX_27(a0)
+	sdc1	$f29, FP64CTX_29(a0)
+	sdc1	$f31, FP64CTX_31(a0)
+.set	pop
+	li	v0, LINKCTX_TYPE_FP64
+	sw	v0, LINKCTX_ID(a0)
+	jr	ra
+END(_fpctx_save)
+
+#
+# FUNCTION:	_fpctx_load
+#
+# DESCRIPTION:	load floating point registers from context chain starting at a0
+#
+# RETURNS:	int
+#			0:	Unrecognised context
+#			CTX_*:	Type of context restored
+#
+	.global _fpctx_load
+LEAF(_fpctx_load)
+	lw	v0, LINKCTX_ID(a0)
+	# Detect type
+	li	t0, LINKCTX_TYPE_FP64
+	li	t1, LINKCTX_TYPE_FP32
+	li	t2, M_StatusCU1
+	beq	v0, t0, 0f
+	beq	v0, t1, 1f
+	# Don't recognise this context, fail
+	move	v0, zero
+	jr	ra
+
+0: 	# FP64 context
+	# Enable CU1
+	di	t3
+	ehb
+	or	t3, t3, t2
+	mtc0	t3, CP0_STATUS
+	ehb
+	# Load FP64 extra
+.set	push
+.set	fp=64
+	ldc1	$f1, FP64CTX_1(a0)
+	ldc1	$f3, FP64CTX_3(a0)
+	ldc1	$f5, FP64CTX_5(a0)
+	ldc1	$f7, FP64CTX_7(a0)
+	ldc1	$f9, FP64CTX_9(a0)
+	ldc1	$f11, FP64CTX_11(a0)
+	ldc1	$f13, FP64CTX_13(a0)
+	ldc1	$f15, FP64CTX_15(a0)
+	ldc1	$f17, FP64CTX_17(a0)
+	ldc1	$f19, FP64CTX_19(a0)
+	ldc1	$f21, FP64CTX_21(a0)
+	ldc1	$f23, FP64CTX_23(a0)
+	ldc1	$f25, FP64CTX_25(a0)
+	ldc1	$f27, FP64CTX_27(a0)
+	ldc1	$f29, FP64CTX_29(a0)
+	ldc1	$f31, FP64CTX_31(a0)
+.set	pop
+1: 	# FP32 context
+	# Enable CU1
+	di	t3
+	ehb
+	or	t3, t3, t2
+	mtc0	t3, CP0_STATUS
+	ehb
+	# Load FP32 base
+	lw	t1, FP32CTX_CSR(a0)
+	ctc1	t1, $31
+	ldc1	$f0, FP32CTX_0(a0)
+	ldc1	$f2, FP32CTX_2(a0)
+	ldc1	$f4, FP32CTX_4(a0)
+	ldc1	$f6, FP32CTX_6(a0)
+	ldc1	$f8, FP32CTX_8(a0)
+	ldc1	$f10, FP32CTX_10(a0)
+	ldc1	$f12, FP32CTX_12(a0)
+	ldc1	$f14, FP32CTX_14(a0)
+	ldc1	$f16, FP32CTX_16(a0)
+	ldc1	$f18, FP32CTX_18(a0)
+	ldc1	$f20, FP32CTX_20(a0)
+	ldc1	$f22, FP32CTX_22(a0)
+	ldc1	$f24, FP32CTX_24(a0)
+	ldc1	$f26, FP32CTX_26(a0)
+	ldc1	$f28, FP32CTX_28(a0)
+	ldc1	$f30, FP32CTX_30(a0)
+	# Return CTX_FP32/64
+	jr	ra
+END(_fpctx_load)
+
+#endif
diff --git a/bsp/x1000/cpu/x1000/stack.c b/bsp/x1000/cpu/x1000/stack.c
new file mode 100644
index 0000000000..0043ea2a21
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/stack.c
@@ -0,0 +1,82 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016��9��8��     Urey         the first version
+ */
+
+#include <rtthread.h>
+
+#include "../common/mips.h"
+
+register U32 $GP __asm__ ("$28");
+
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
+{
+    static rt_uint32_t wSR=0;
+    static rt_uint32_t wGP;
+
+	mips_reg_ctx	*regCtx;
+	mips_arg_ctx	*argCtx;
+	rt_uint32_t i;
+
+	if (wSR == 0)
+	{
+		wSR = read_c0_status();
+		wSR &= 0xfffffffe;
+		wSR |= 0x0403;
+
+		wGP = $GP;
+	}
+
+	if ((rt_uint32_t) stack_addr & 0x7)
+	{
+		stack_addr = (rt_uint8_t *)((rt_uint32_t)stack_addr - 4);
+	}
+
+	argCtx = (mips_arg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx));
+	regCtx = (mips_reg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx) - sizeof(mips_reg_ctx));
+
+	for (i = 0; i < 4; ++i)
+	{
+		argCtx->args[i] = i;
+	}
+
+	//����ͨ�üĴ���
+	for (i = 0; i < 32; ++i)
+	{
+		regCtx->regs[i] = i;
+	}
+
+	regCtx->regs[REG_SP] = (rt_uint32_t)stack_addr;
+	regCtx->regs[REG_A0] = (rt_uint32_t)parameter;
+	regCtx->regs[REG_GP] = (rt_uint32_t)wGP;
+	regCtx->regs[REG_FP] = (rt_uint32_t)0x0;
+	regCtx->regs[REG_RA] = (rt_uint32_t)texit;
+
+    regCtx->CP0DataLO	= 0x00;
+    regCtx->CP0DataHI	= 0x00;
+    regCtx->CP0Cause	= read_c0_cause();
+    regCtx->CP0Status	= wSR;
+    regCtx->CP0EPC		= (rt_uint32_t)tentry;
+    regCtx->CP0BadVAddr= 0x00;
+
+	return (rt_uint8_t *)(regCtx);
+}
diff --git a/bsp/x1000/cpu/x1000/startup_gcc.S b/bsp/x1000/cpu/x1000/startup_gcc.S
new file mode 100644
index 0000000000..c5112614fc
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/startup_gcc.S
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-07     Urey         first version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips.h"
+
+#define IRQ_STACK_SIZE		0x2000
+#define EXC_STACK_SIZE		0x2000
+
+
+	.section ".bss"
+    ALIGN(4)
+irq_stack_low:
+	.space IRQ_STACK_SIZE
+irq_stack_top:
+	.space 8
+
+	    ALIGN(4)
+exc_stack_low:
+	.space EXC_STACK_SIZE
+exc_stack_top:
+	.space 8
+
+#define SYSTEM_STACK		0x80003fe8
+
+;/*********************************************************************************************************
+;  ���
+;*********************************************************************************************************/
+	.global	rtthread_startup
+	.global 	mips_vfp32_init
+
+	.global	_start
+    .section ".start", "ax"
+    .set noreorder
+_start:
+    .set    noreorder
+    la      ra, _start
+
+    li      t1, 0x00800000
+    mtc0    t1, CP0_CAUSE
+
+    /* init cp0 registers. */
+    li      t0, 0x1000FC00 /* BEV = 0 and mask all interrupt */
+    mtc0    t0, CP0_STATUS
+
+#ifdef __mips_hard_float
+	jal 	mips_vfp32_init
+	nop
+#endif
+
+    /* setup stack pointer */
+    li      sp, SYSTEM_STACK
+    la      gp, _gp
+
+_cache_init:
+    /* init caches, assumes a 4way * 128set * 32byte I/D cache */
+    mtc0    zero, CP0_TAGLO  /* TAGLO reg */
+    mtc0    zero, CP0_TAGHI  /* TAGHI reg */
+    li      t0, 3            /* enable cache for kseg0 accesses */
+    mtc0    t0, CP0_CONFIG   /* CONFIG reg */
+    la      t0, 0x80000000   /* an idx op should use an unmappable address */
+    ori     t1, t0, 0x4000   /* 16kB cache */
+
+_cache_loop:
+    cache   0x8, 0(t0)       /* index store icache tag */
+    cache   0x9, 0(t0)       /* index store dcache tag */
+    bne     t0, t1, _cache_loop
+    addiu   t0, t0, 0x20     /* 32 bytes per cache line */
+    nop
+
+    /* invalidate BTB */
+    mfc0    t0, CP0_CONFIG
+    nop
+    ori     t0, 2
+    mtc0    t0, CP0_CONFIG
+    nop
+
+
+    /* jump to RT-Thread RTOS */
+    jal     rtthread_startup
+    nop
+
+    /* restart, never die */
+    j       _start
+    nop
+    .set    reorder
+
+
+;/*********************************************************************************************************
+;  �쳣������
+;*********************************************************************************************************/
+    /* 0x0 - TLB refill handler */
+    .section .vectors.1, "ax", %progbits
+    j       mips_tlb_refill_entry
+    nop
+
+    /* 0x100 - Cache error handler */
+    .section .vectors.2, "ax", %progbits
+    j       mips_cache_error_entry
+    nop
+
+    /* 0x180 - Exception/Interrupt handler */
+    .section .vectors.3, "ax", %progbits
+    j       mips_exception_entry
+    nop
+
+    /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
+    .section .vectors.4, "ax", %progbits
+    j       mips_interrupt_entry
+    nop
+    .section .vectors, "ax", %progbits
+
+	.global	mips_exception_handler
+//	.global	mips_syscall
+LEAF(mips_exception_entry)
+    .set    push
+    .set    noat
+    .set    noreorder
+    .set    volatile
+
+	mfc0	k0, C0_CAUSE
+	andi	k0, k0, 0x7c
+	beq		zero, k0, except_do_intr
+	nop
+
+	andi	k0,(0x08 << 2)
+	beq		zero,k0,except_do
+	nop
+except_do_intr:
+	la		k0,mips_interrupt_entry
+	jr		k0
+	nop
+except_do_syscall:
+//	la		k0,mips_syscall
+//	jr		k0
+	nop
+except_do:
+	//save sp
+	move	k0,sp
+	//la		sp,	exc_stack_top
+	subu 	sp, sp, CONTEXT_SIZE
+	//save context
+	sw	$0, (4*0)(sp);
+	sw	$1, (4*1)(sp);
+	sw	$2, (4*2)(sp);
+	sw	$3, (4*3)(sp);
+	sw	$4, (4*4)(sp);
+	sw	$5, (4*5)(sp);
+	sw	$6, (4*6)(sp);
+	sw	$7, (4*7)(sp);
+	sw	$8, (4*8)(sp);
+	sw	$9, (4*9)(sp);
+	sw	$10, (4*10)(sp);
+	sw	$11, (4*11)(sp);
+	sw	$12, (4*12)(sp);
+	sw	$13, (4*13)(sp);
+	sw	$14, (4*14)(sp);
+	sw	$15, (4*15)(sp);
+	sw	$16, (4*16)(sp);
+	sw	$17, (4*17)(sp);
+	sw	$18, (4*18)(sp);
+	sw	$19, (4*19)(sp);
+	sw	$20, (4*20)(sp);
+	sw	$21, (4*21)(sp);
+	sw	$22, (4*22)(sp);
+	sw	$23, (4*23)(sp);
+	sw	$24, (4*24)(sp);
+	sw	$25, (4*25)(sp);
+	sw	$26, (4*26)(sp);
+	sw	$27, (4*27)(sp);
+	sw	$28, (4*28)(sp);
+	sw	k0,  (4*29)(sp);	//old sp
+	sw	$30, (4*30)(sp);
+	sw	$31, (4*31)(sp);
+
+	/* STATUS CAUSE EPC.... */
+	mfc0	$2, CP0_STATUS
+	sw		$2, STK_OFFSET_SR(sp)
+
+	mfc0	$2, CP0_CAUSE
+	sw		$2, STK_OFFSET_CAUSE(sp)
+
+	mfc0	$2, CP0_BADVADDR
+	sw		$2, STK_OFFSET_BADVADDR(sp)
+
+	MFC0	$2, CP0_EPC
+	sw		$2, STK_OFFSET_EPC(sp)
+
+	mfhi	$2
+	sw		$2, STK_OFFSET_HI(sp)
+
+	mflo	$2
+	sw		$2, STK_OFFSET_LO(sp)
+
+	move	a0, sp
+	la		k0,	mips_exception_handler
+	j		k0
+	nop
+
+	//
+
+	.set	pop
+END(mips_exception_entry)
+
+	.global	mips_tlb_refill_handler
+LEAF(mips_tlb_refill_entry)
+    .set    push
+    .set    noat
+    .set    noreorder
+    .set    volatile
+
+	la		k0,mips_tlb_refill_handler
+	jr		k0
+
+	nop
+    eret
+	nop
+
+	.set	pop
+END(mips_tlb_refill_entry)
+
+	.global	mips_cache_error_handler
+LEAF(mips_cache_error_entry)
+    .set    push
+    .set    noat
+    .set    noreorder
+    .set    volatile
+
+	la		k0,mips_cache_error_handler
+	jr		k0
+    nop
+    eret
+	nop
+
+	.set	pop
+END(mips_cache_error_entry)
+
+
+
+.global	rt_interrupt_dispatch
+.global	rt_interrupt_enter
+.global	rt_interrupt_leave
+LEAF(mips_interrupt_entry)
+    .set    push
+    .set    noat
+    .set    noreorder
+    .set    volatile
+
+    //mfc0	k0,CP0_EPC
+    SAVE_CONTEXT
+
+    mfc0    t0, CP0_CAUSE
+    mfc0    t1, CP0_STATUS
+    and     t0, t1
+
+    andi    t0, 0xff00
+    beqz    t0, spurious_interrupt
+    nop
+
+	/* let k0 keep the current context sp */
+	move 	k0, sp
+
+	/* switch to kernel stack */
+	la 		sp, irq_stack_top
+	jal 	rt_interrupt_enter
+	nop
+    jal     rt_interrupt_dispatch
+    nop
+    jal     rt_interrupt_leave
+    nop
+
+    /* switch sp back to thread's context */
+    move    sp, k0
+
+    /*
+     * if rt_thread_switch_interrupt_flag set, jump to
+     * rt_hw_context_switch_interrupt_do and don't return
+     */
+    la      k0, rt_thread_switch_interrupt_flag
+    lw      k1, 0(k0)
+    beqz    k1, spurious_interrupt
+    nop
+    sw      zero, 0(k0)                     /* clear flag */
+    nop
+
+    /*
+     * switch to the new thread
+     */
+    la      k0, rt_interrupt_from_thread
+    lw      k1, 0(k0)
+    nop
+    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
+
+    la      k0, rt_interrupt_to_thread
+    lw      k1, 0(k0)
+    nop
+    lw      sp, 0(k1)                       /* get new task's stack pointer */
+    j       spurious_interrupt
+    nop
+spurious_interrupt:
+    RESTORE_CONTEXT
+
+	.set	pop
+END(mips_interrupt_entry)
diff --git a/bsp/x1000/cpu/x1000/x1000.h b/bsp/x1000/cpu/x1000/x1000.h
new file mode 100644
index 0000000000..aa18297395
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/x1000.h
@@ -0,0 +1,284 @@
+/*
+ * File      : x1000.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-11-19     Urey         the first version
+ */
+
+#ifndef __X1000_H__
+#define __X1000_H__
+
+#include "../common/mips.h"
+
+#ifndef __ASSEMBLY__
+
+#define cache_unroll(base,op)               \
+    __asm__ __volatile__("                  \
+        .set noreorder;                     \
+        .set mips3;                         \
+        cache %1, (%0);                     \
+        .set mips0;                         \
+        .set reorder"                       \
+        :                                   \
+        : "r" (base),                       \
+          "i" (op));
+
+/* cpu pipeline flush */
+static inline void jz_sync(void)
+{
+    __asm__ volatile ("sync");
+}
+
+static inline void writeb(u8 value, u32 address)
+{
+    *((volatile u8 *) address) = value;
+}
+static inline void writew( u16 value, u32 address)
+{
+    *((volatile u16 *) address) = value;
+}
+static inline void writel(u32 value, u32 address)
+{
+    *((volatile u32 *) address) = value;
+}
+
+static inline u8 readb(u32 address)
+{
+    return *((volatile u8 *)address);
+}
+
+static inline u16 readw(u32 address)
+{
+    return *((volatile u16 *)address);
+}
+
+static inline u32 readl(u32 address)
+{
+    return *((volatile u32 *)address);
+}
+
+static inline void jz_writeb(u32 address, u8 value)
+{
+    *((volatile u8 *)address) = value;
+}
+
+static inline void jz_writew(u32 address, u16 value)
+{
+    *((volatile u16 *)address) = value;
+}
+
+static inline void jz_writel(u32 address, u32 value)
+{
+    *((volatile u32 *)address) = value;
+}
+
+static inline u8 jz_readb(u32 address)
+{
+    return *((volatile u8 *)address);
+}
+
+static inline u16 jz_readw(u32 address)
+{
+    return *((volatile u16 *)address);
+}
+
+static inline u32 jz_readl(u32 address)
+{
+    return *((volatile u32 *)address);
+}
+
+#define BIT(n)          (0x01u << (n))
+#define BIT0            (0x01u <<  0)
+#define BIT1            (0x01u <<  1)
+#define BIT2            (0x01u <<  2)
+#define BIT3            (0x01u <<  3)
+#define BIT4            (0x01u <<  4)
+#define BIT5            (0x01u <<  5)
+#define BIT6            (0x01u <<  6)
+#define BIT7            (0x01u <<  7)
+#define BIT8            (0x01u <<  8)
+#define BIT9            (0x01u <<  9)
+#define BIT10           (0x01u << 10)
+#define BIT11           (0x01u << 11)
+#define BIT12           (0x01u << 12)
+#define BIT13           (0x01u << 13)
+#define BIT14           (0x01u << 14)
+#define BIT15           (0x01u << 15)
+#define BIT16           (0x01u << 16)
+#define BIT17           (0x01u << 17)
+#define BIT18           (0x01u << 18)
+#define BIT19           (0x01u << 19)
+#define BIT20           (0x01u << 20)
+#define BIT21           (0x01u << 21)
+#define BIT22           (0x01u << 22)
+#define BIT23           (0x01u << 23)
+#define BIT24           (0x01u << 24)
+#define BIT25           (0x01u << 25)
+#define BIT26           (0x01u << 26)
+#define BIT27           (0x01u << 27)
+#define BIT28           (0x01u << 28)
+#define BIT29           (0x01u << 29)
+#define BIT30           (0x01u << 30)
+#define BIT31           (0x01u << 31)
+
+/* Generate the bit field mask from msb to lsb */
+#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
+
+
+/* Get the bit field value from the data which is read from the register */
+#define get_bf_value(data, lsb, mask)  (((data) & (mask)) >> (lsb))
+
+#endif /* !ASSEMBLY */
+
+
+//----------------------------------------------------------------------
+// Register Definitions
+//
+/* AHB0 BUS Devices Base */
+#define HARB0_BASE  0xB3000000
+#define EMC_BASE    0xB3010000
+#define DDRC_BASE   0xB3020000
+#define MDMAC_BASE  0xB3030000
+#define LCD_BASE    0xB3050000
+#define TVE_BASE    0xB3050000
+#define SLCD_BASE   0xB3050000
+#define CIM_BASE    0xB3060000
+#define IPU_BASE    0xB3080000
+/* AHB1 BUS Devices Base */
+#define HARB1_BASE  0xB3200000
+#define DMAGP0_BASE 0xB3210000
+#define DMAGP1_BASE 0xB3220000
+#define DMAGP2_BASE 0xB3230000
+#define MC_BASE     0xB3250000
+#define ME_BASE     0xB3260000
+#define DEBLK_BASE  0xB3270000
+#define IDCT_BASE   0xB3280000
+#define CABAC_BASE  0xB3290000
+#define TCSM0_BASE  0xB32B0000
+#define TCSM1_BASE  0xB32C0000
+#define SRAM_BASE   0xB32D0000
+/* AHB2 BUS Devices Base */
+#define HARB2_BASE  0xB3400000
+#define NEMC_BASE   0xB3410000
+#define DMAC_BASE   0xB3420000
+#define UHC_BASE    0xB3430000
+//#define UDC_BASE    0xB3440000
+#define SFC_BASE	 0xB3440000
+#define GPS_BASE    0xB3480000
+#define ETHC_BASE   0xB34B0000
+#define BCH_BASE    0xB34D0000
+#define MSC0_BASE   0xB3450000
+#define MSC1_BASE   0xB3460000
+#define MSC2_BASE   0xB3470000
+#define OTG_BASE    0xb3500000
+
+/* APB BUS Devices Base */
+#define CPM_BASE    0xB0000000
+#define INTC_BASE   0xB0001000
+#define TCU_BASE    0xB0002000
+#define WDT_BASE    0xB0002000
+#define OST_BASE    0xB2000000      /* OS Timer */
+#define RTC_BASE    0xB0003000
+#define GPIO_BASE   0xB0010000
+#define AIC_BASE    0xB0020000
+#define DMIC_BASE   0xB0021000
+#define ICDC_BASE   0xB0020000
+#define UART0_BASE  0xB0030000
+#define UART1_BASE  0xB0031000
+#define UART2_BASE  0xB0032000
+#define SCC_BASE    0xB0040000
+#define SSI0_BASE   0xB0043000
+#define SSI1_BASE   0xB0044000
+#define SSI2_BASE   0xB0045000
+#define I2C0_BASE   0xB0050000
+#define I2C1_BASE   0xB0051000
+#define I2C2_BASE   0xB0052000
+#define PS2_BASE    0xB0060000
+#define SADC_BASE   0xB0070000
+#define OWI_BASE    0xB0072000
+#define TSSI_BASE   0xB0073000
+
+/* NAND CHIP Base Address*/
+#define NEMC_CS1_IOBASE 0Xbb000000
+#define NEMC_CS2_IOBASE 0Xba000000
+#define NEMC_CS3_IOBASE 0Xb9000000
+#define NEMC_CS4_IOBASE 0Xb8000000
+#define NEMC_CS5_IOBASE 0Xb7000000
+#define NEMC_CS6_IOBASE 0Xb6000000
+
+/*********************************************************************************************************
+**   WDT
+*********************************************************************************************************/
+#define WDT_TDR         (0x00)
+#define WDT_TCER        (0x04)
+#define WDT_TCNT        (0x08)
+#define WDT_TCSR        (0x0C)
+
+#define REG_WDT_TDR     REG16(WDT_BASE + WDT_TDR)
+#define REG_WDT_TCER    REG8(WDT_BASE + WDT_TCER)
+#define REG_WDT_TCNT    REG16(WDT_BASE + WDT_TCNT)
+#define REG_WDT_TCSR    REG16(WDT_BASE + WDT_TCSR)
+
+#define WDT_TSCR_WDTSC          (1 << 16)
+
+#define WDT_TCSR_PRESCALE_1         (0 << 3)
+#define WDT_TCSR_PRESCALE_4         (1 << 3)
+#define WDT_TCSR_PRESCALE_16        (2 << 3)
+#define WDT_TCSR_PRESCALE_64        (3 << 3)
+#define WDT_TCSR_PRESCALE_256       (4 << 3)
+#define WDT_TCSR_PRESCALE_1024      (5 << 3)
+
+#define WDT_TCSR_EXT_EN         (1 << 2)
+#define WDT_TCSR_RTC_EN         (1 << 1)
+#define WDT_TCSR_PCK_EN         (1 << 0)
+
+#define WDT_TCER_TCEN           (1 << 0)
+
+/* RTC Reg */
+#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
+#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
+#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
+#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
+#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
+#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
+#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
+#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
+#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
+#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
+#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
+#define RTC_CKPCR		(0x40)  /* rw, 32, 0x00000010 */
+#define RTC_OWIPCR		(0x44)  /* rw, 32, 0x00000010 */
+#define RTC_PWRONCR		(0x48)  /* rw, 32, 0x???????? */
+
+#define RTCCR_WRDY				BIT(7)
+#define WENR_WEN                BIT(31)
+
+#define RECOVERY_SIGNATURE	(0x001a1a)
+#define REBOOT_SIGNATURE	(0x003535)
+#define UNMSAK_SIGNATURE	(0x7c0000)//do not use these bits
+
+
+#include "x1000_cpm.h"
+#include "x1000_intc.h"
+#include "x1000_otg_dwc.h"
+#include "x1000_aic.h"
+#include "x1000_slcdc.h"
+
+#endif /* _JZ_M150_H_ */
diff --git a/bsp/x1000/cpu/x1000/x1000_aic.h b/bsp/x1000/cpu/x1000/x1000_aic.h
new file mode 100644
index 0000000000..ed2c8e6f73
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/x1000_aic.h
@@ -0,0 +1,794 @@
+/**
+  ******************************************************************************
+  * @file    x1000_aic.h
+  * @author  Urey
+  * @version V1.0.0
+  * @date    2017��2��20��
+  * @brief   TODO
+  ******************************************************************************         
+**/ 
+
+
+#ifndef _X1000_AIC_H_
+#define _X1000_AIC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AIC_FR      (AIC_BASE + 0x00)
+#define AIC_CR      (AIC_BASE + 0x04)
+#define AIC_ACCR1   (AIC_BASE + 0x08)
+#define AIC_ACCR2   (AIC_BASE + 0x0c)
+#define AIC_I2SCR   (AIC_BASE + 0x10)
+#define AIC_SR      (AIC_BASE + 0x14)
+#define AIC_ACSR    (AIC_BASE + 0x18)
+#define AIC_I2SSR   (AIC_BASE + 0x1c)
+#define AIC_ACCAR   (AIC_BASE + 0x20)
+#define AIC_ACCDR   (AIC_BASE + 0x24)
+#define AIC_ACSAR   (AIC_BASE + 0x28)
+#define AIC_ACSDR   (AIC_BASE + 0x2c)
+#define AIC_I2SDIV  (AIC_BASE + 0x30)
+#define AIC_DR      (AIC_BASE + 0x34)
+
+#define SPDIF_ENA   (AIC_BASE + 0x80)
+#define SPDIF_CTRL  (AIC_BASE + 0x84)
+#define SPDIF_STATE (AIC_BASE + 0x88)
+#define SPDIF_CFG1  (AIC_BASE + 0x8c)
+#define SPDIF_CFG2  (AIC_BASE + 0x90)
+#define SPDIF_FIFO  (AIC_BASE + 0x94)
+
+#define ICDC_CKCFG  (AIC_BASE + 0xa0)
+#define ICDC_RGADW  (AIC_BASE + 0xa4)
+#define ICDC_RGDATA (AIC_BASE + 0xa8)
+
+
+/* AIC_FR definition */
+#define AIC_FR_RFTH_LSB     24
+#define AIC_FR_RFTH(x)  ( ( (x)/2 - 1 ) << AIC_FR_RFTH_LSB)     // 2, 4, ..., 32
+#define AIC_FR_RFTH_MASK    BITS_H2L(27, AIC_FR_RFTH_LSB)
+
+#define AIC_FR_TFTH_LSB     16
+#define AIC_FR_TFTH(x)      ( ( (x)/2 ) << AIC_FR_TFTH_LSB)     // 2, 4, ..., 32
+#define AIC_FR_TFTH_MASK    BITS_H2L(20, AIC_FR_TFTH_LSB)
+
+/* new@4770 */
+#define AIC_FR_IBCKD        BIT10
+
+/* new@4770 */
+#define AIC_FR_ISYNCD       BIT9
+
+/* new@4770 */
+#define IC_FR_DMODE     BIT8
+
+#define AIC_FR_LSMP     BIT6
+#define AIC_FR_ICDC     BIT5
+#define AIC_FR_AUSEL        BIT4
+#define AIC_FR_RST      BIT3
+#define AIC_FR_BCKD     BIT2
+#define AIC_FR_SYNCD        BIT1
+#define AIC_FR_ENB      BIT0
+
+
+/* AIC_CR definition */
+#define AIC_CR_PACK16       BIT28
+
+#define AIC_CR_CHANNEL_LSB  24
+#define AIC_CR_CHANNEL_MASK BITS_H2L(26, 24)
+#define AIC_CR_CHANNEL_MONO   (0x0 << AIC_CR_CHANNEL_LSB)
+#define AIC_CR_CHANNEL_STEREO (0x1 << AIC_CR_CHANNEL_LSB)
+#define AIC_CR_CHANNEL_4CHNL  (0x3 << AIC_CR_CHANNEL_LSB)
+#define AIC_CR_CHANNEL_6CHNL  (0x5 << AIC_CR_CHANNEL_LSB)
+#define AIC_CR_CHANNEL_8CHNL  (0x7 << AIC_CR_CHANNEL_LSB)
+
+#define AIC_CR_OSS_LSB      19
+#define AIC_CR_OSS_MASK     BITS_H2L(21, AIC_CR_OSS_LSB)
+#define AIC_CR_OSS(n)       (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB)  /* n = 8, 16, 18, 20, 24 */
+
+#define AIC_CR_ISS_LSB      16
+#define AIC_CR_ISS_MASK     BITS_H2L(18, AIC_CR_ISS_LSB)
+#define AIC_CR_ISS(n)       (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB)  /* n = 8, 16, 18, 20, 24 */
+
+#define AIC_CR_RDMS     BIT15
+#define AIC_CR_TDMS     BIT14
+#define AIC_CR_M2S      BIT11
+#define AIC_CR_ENDSW        BIT10
+#define AIC_CR_AVSTSU       BIT9
+#define AIC_CR_TFLUSH       BIT8
+#define AIC_CR_RFLUSH       BIT7
+#define AIC_CR_EROR     BIT6
+#define AIC_CR_ETUR     BIT5
+#define AIC_CR_ERFS     BIT4
+#define AIC_CR_ETFS     BIT3
+#define AIC_CR_ENLBF        BIT2
+#define AIC_CR_ERPL     BIT1
+#define AIC_CR_EREC     BIT0
+
+/* AIC controller AC-link control register 1(ACCR1) */
+#define AIC_ACCR1_RS_LSB    16
+#define AIC_ACCR1_RS_MASK   BITS_H2L(25, AIC_ACCR1_RS_LSB)
+#define AIC_ACCR1_RS_SLOT(n)    ((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB)  /* n = 3 .. 12 */
+
+#define AIC_ACCR1_XS_LSB    0
+#define AIC_ACCR1_XS_MASK   BITS_H2L(9, AIC_ACCR1_XS_LSB)
+#define AIC_ACCR1_XS_SLOT(n)    ((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB)  /* n = 3 .. 12 */
+
+/* AIC controller AC-link control register 2 (ACCR2) */
+#define AIC_ACCR2_ERSTO     BIT18
+#define AIC_ACCR2_ESADR     BIT17
+#define AIC_ACCR2_ECADT     BIT16
+#define AIC_ACCR2_SO        BIT3
+#define AIC_ACCR2_SR        BIT2
+#define AIC_ACCR2_SS        BIT1
+#define AIC_ACCR2_SA        BIT0
+
+/* AIC controller i2s/msb-justified control register (I2SCR) */
+#define AIC_I2SCR_RFIRST    BIT17
+#define AIC_I2SCR_SWLH      BIT16
+#define AIC_I2SCR_ISTPBK    BIT13
+#define AIC_I2SCR_STPBK     BIT12
+#define AIC_I2SCR_ESCLK     BIT4
+#define AIC_I2SCR_AMSL      BIT0
+
+/* AIC controller FIFO status register (AICSR) */
+#define AIC_SR_RFL_LSB      24
+#define AIC_SR_RFL_MASK     BITS_H2L(29, AIC_SR_RFL_LSB)
+
+#define AIC_SR_TFL_LSB      8
+#define AIC_SR_TFL_MASK     BITS_H2L(13, AIC_SR_TFL_LSB)
+
+#define AIC_SR_ROR      BIT6
+#define AIC_SR_TUR      BIT5
+#define AIC_SR_RFS      BIT4
+#define AIC_SR_TFS      BIT3
+
+/* AIC controller AC-link status register (ACSR) */
+#define AIC_ACSR_SLTERR     BIT21
+#define AIC_ACSR_CRDY       BIT20
+#define AIC_ACSR_CLPM       BIT19
+#define AIC_ACSR_RSTO       BIT18
+#define AIC_ACSR_SADR       BIT17
+#define AIC_ACSR_CADT       BIT16
+
+/* AIC controller I2S/MSB-justified status register (I2SSR) */
+#define AIC_I2SSR_CHBSY     BIT5
+#define AIC_I2SSR_TBSY      BIT4
+#define AIC_I2SSR_RBSY      BIT3
+#define AIC_I2SSR_BSY       BIT2
+
+/* AIC controller AC97 codec command address register (ACCAR) */
+#define AIC_ACCAR_CAR_LSB   0
+#define AIC_ACCAR_CAR_MASK  BITS_H2L(19, AIC_ACCAR_CAR_LSB)
+
+
+/* AIC controller AC97 codec command data register (ACCDR) */
+#define AIC_ACCDR_CDR_LSB   0
+#define AIC_ACCDR_CDR_MASK  BITS_H2L(19, AIC_ACCDR_CDR_LSB)
+
+/* AC97 read and write macro based on ACCAR and ACCDR */
+#define AC97_READ_CMD       BIT19
+#define AC97_WRITE_CMD      (BIT19 & ~BIT19)
+
+#define AC97_INDEX_LSB      12
+#define AC97_INDEX_MASK     BITS_H2L(18, AC97_INDEX_LSB)
+
+#define AC97_DATA_LSB       4
+#define AC97_DATA_MASK      BITS_H2L(19, AC97_DATA_LSB)
+
+/* AIC controller AC97 codec status address register (ACSAR) */
+#define AIC_ACSAR_SAR_LSB   0
+#define AIC_ACSAR_SAR_MASK  BITS_H2L(19, AIC_ACSAR_SAR_LSB)
+
+/* AIC controller AC97 codec status data register (ACSDR) */
+#define AIC_ACSDR_SDR_LSB   0
+#define AIC_ACSDR_SDR_MASK  BITS_H2L(19, AIC_ACSDR_SDR_LSB)
+
+/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */
+#define AIC_I2SDIV_IDIV_LSB 16
+#define AIC_I2SDIV_IDIV_MASK    BITS_H2L(24, AIC_I2SDIV_IDIV_LSB)
+#define AIC_I2SDIV_DIV_LSB  0
+#define AIC_I2SDIV_DIV_MASK BITS_H2L(8, AIC_I2SDIV_DIV_LSB)
+
+/* SPDIF enable register (SPDIF_ENA) */
+#define SPDIF_ENA_SPEN      BIT0
+
+/* SPDIF control register (SPDIF_CTRL) */
+#define SPDIF_CTRL_DMAEN        BIT15
+#define SPDIF_CTRL_DTYPE        BIT14
+#define SPDIF_CTRL_SIGN         BIT13
+#define SPDIF_CTRL_INVALID      BIT12
+#define SPDIF_CTRL_RST          BIT11
+#define SPDIF_CTRL_SPDIFI2S     BIT10
+#define SPDIF_CTRL_MTRIG        BIT1
+#define SPDIF_CTRL_MFFUR        BIT0
+
+/* SPDIF state register (SPDIF_STAT) */
+#define SPDIF_STAT_BUSY     BIT7
+#define SPDIF_STAT_FTRIG    BIT1
+#define SPDIF_STAT_FUR      BIT0
+
+#define SPDIF_STAT_FLVL_LSB 8
+#define SPDIF_STAT_FLVL_MASK    BITS_H2L(14, SPDIF_STAT_FLVL_LSB)
+
+/* SPDIF configure 1 register (SPDIF_CFG1) */
+#define SPDIF_CFG1_INITLVL  BIT17
+#define SPDIF_CFG1_ZROVLD   BIT16
+
+#define SPDIF_CFG1_TRIG_LSB 12
+#define SPDIF_CFG1_TRIG_MASK    BITS_H2L(13, SPDIF_CFG1_TRIG_LSB)
+#define SPDIF_CFG1_TRIG(n)  (((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB) /* n = 4, 8, 16, 32 */
+
+#define SPDIF_CFG1_SRCNUM_LSB   8
+#define SPDIF_CFG1_SRCNUM_MASK  BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB)
+
+#define SPDIF_CFG1_CH1NUM_LSB   4
+#define SPDIF_CFG1_CH1NUM_MASK  BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB)
+
+#define SPDIF_CFG1_CH2NUM_LSB   0
+#define SPDIF_CFG1_CH2NUM_MASK  BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB)
+
+/* SPDIF configure 2 register (SPDIF_CFG2) */
+#define SPDIF_CFG2_MAXWL    BIT18
+#define SPDIF_CFG2_PRE      BIT3
+#define SPDIF_CFG2_COPYN    BIT2
+#define SPDIF_CFG2_AUDION   BIT1
+#define SPDIF_CFG2_CONPRO   BIT0
+
+#define SPDIF_CFG2_FS_LSB   26
+#define SPDIF_CFG2_FS_MASK  BITS_H2L(29, SPDIF_CFG2_FS_LSB)
+
+#define SPDIF_CFG2_ORGFRQ_LSB   22
+#define SPDIF_CFG2_ORGFRQ_MASK  BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB)
+
+#define SPDIF_CFG2_SAMWL_LSB    19
+#define SPDIF_CFG2_SAMWL_MASK   BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB)
+
+#define SPDIF_CFG2_CLKACU_LSB   16
+#define SPDIF_CFG2_CLKACU_MASK  BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB)
+
+#define SPDIF_CFG2_CATCODE_LSB  8
+#define SPDIF_CFG2_CATCODE_MASK BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB)
+
+#define SPDIF_CFG2_CHMD_LSB 6
+#define SPDIF_CFG2_CHMD_MASK    BITS_H2L(7, SPDIF_CFG2_CHMD_LSB)
+
+/* ICDC internal register access control register(RGADW) */
+#define ICDC_RGADW_RGWR     BIT16
+
+#define ICDC_RGADW_RGADDR_LSB   8
+#define ICDC_RGADW_RGADDR_MASK  BITS_H2L(14, ICDC_RGADW_RGADDR_LSB)
+
+#define ICDC_RGADW_RGDIN_LSB    0
+#define ICDC_RGADW_RGDIN_MASK   BITS_H2L(7, ICDC_RGADW_RGDIN_LSB)
+
+
+/* ICDC internal register data output register (RGDATA)*/
+#define ICDC_RGDATA_IRQ     BIT8
+
+#define ICDC_RGDATA_RGDOUT_LSB  0
+#define ICDC_RGDATA_RGDOUT_MASK BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB)
+
+
+#ifndef __MIPS_ASSEMBLER
+
+
+#define REG_AIC_FR      REG32(AIC_FR)
+#define REG_AIC0_FR     REG32(AIC0_FR)
+#define REG_AIC_CR      REG32(AIC_CR)
+#define REG_AIC_ACCR1       REG32(AIC_ACCR1)
+#define REG_AIC_ACCR2       REG32(AIC_ACCR2)
+#define REG_AIC_I2SCR       REG32(AIC_I2SCR)
+#define REG_AIC_SR      REG32(AIC_SR)
+#define REG_AIC_ACSR        REG32(AIC_ACSR)
+#define REG_AIC_I2SSR       REG32(AIC_I2SSR)
+#define REG_AIC_ACCAR       REG32(AIC_ACCAR)
+#define REG_AIC_ACCDR       REG32(AIC_ACCDR)
+#define REG_AIC_ACSAR       REG32(AIC_ACSAR)
+#define REG_AIC_ACSDR       REG32(AIC_ACSDR)
+#define REG_AIC_I2SDIV      REG32(AIC_I2SDIV)
+#define REG_AIC_DR      REG32(AIC_DR)
+
+#define REG_SPDIF_ENA       REG32(SPDIF_ENA)
+#define REG_SPDIF_CTRL      REG32(SPDIF_CTRL)
+#define REG_SPDIF_STATE     REG32(SPDIF_STATE)
+#define REG_SPDIF_CFG1      REG32(SPDIF_CFG1)
+#define REG_SPDIF_CFG2      REG32(SPDIF_CFG2)
+#define REG_SPDIF_FIFO      REG32(SPDIF_FIFO)
+
+#define REG_ICDC_RGADW      REG32(ICDC_RGADW)
+#define REG_ICDC_RGDATA     REG32(ICDC_RGDATA)
+
+#if 0
+#define __aic_enable()      ( REG_AIC_FR |= AIC_FR_ENB )
+#define __aic_disable()     ( REG_AIC_FR &= ~AIC_FR_ENB )
+
+#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
+#define __aic_select_i2s()  ( REG_AIC_FR |= AIC_FR_AUSEL )
+
+#define __aic_play_zero()   ( REG_AIC_FR &= ~AIC_FR_LSMP )
+#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
+
+#define __i2s_as_master()   ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
+#define __i2s_as_slave()    ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
+
+#define jz_aic_ibck_in      (CLRREG32(AIC_FR, AIC_FR_IBCKD))
+#define jz_aic_ibck_out     (SETREG32(AIC_FR, AIC_FR_IBCKD))
+
+#define jz_aic_isync_in     (CLRREG32(AIC_FR, AIC_FR_ISYNCD))
+#define jz_aic_isync_out    (SETREG32(AIC_FR, AIC_FR_ISYNCD))
+
+#define jz_aic_enable_dmode (SETREG32(AIC_FR, AIC_FR_DMODE))
+#define jz_aic_disable_dmode    (CLRREG32(AIC_FR, AIC_FR_DMODE))
+
+#define __aic_reset_status()          ( REG_AIC_FR & AIC_FR_RST )
+
+#define __aic_reset()                                   \
+do {                                                    \
+        REG_AIC_FR |= AIC_FR_RST;                       \
+} while(0)
+
+
+#define __aic_set_transmit_trigger(n)           \
+do {                            \
+    REG_AIC_FR &= ~AIC_FR_TFTH_MASK;        \
+    REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB);     \
+} while(0)
+
+#define __aic_set_receive_trigger(n)            \
+do {                            \
+    REG_AIC_FR &= ~AIC_FR_RFTH_MASK;        \
+    REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB);     \
+} while(0)
+
+#define __aic_enable_oldstyle()
+#define __aic_enable_newstyle()
+#define __aic_enable_pack16()   ( REG_AIC_CR |= AIC_CR_PACK16 )
+#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16)
+
+#define jz_aic_set_channel(n)                       \
+    do {                                \
+        switch((n)) {                       \
+        case 1:                         \
+        case 2:                         \
+        case 4:                         \
+        case 6:                         \
+        case 8:                         \
+            CLRREG32(AIC_CR, AIC_CR_CHANNEL_MASK);      \
+            SETREG32(AIC_CR, ((((n) - 1) << 24) & AIC_CR_CHANNEL_MASK)); \
+            break;                      \
+        default:                        \
+            printk("invalid aic channel, must be 1, 2, 4, 6, or 8\n"); \
+            break;                      \
+        }                           \
+    } while(0)
+
+/* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */
+#define __aic_out_channel_select(n)                    \
+do {                                                   \
+    REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK;            \
+        REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB );                \
+} while(0)
+
+#define __aic_enable_record()   ( REG_AIC_CR |= AIC_CR_EREC )
+#define __aic_disable_record()  ( REG_AIC_CR &= ~AIC_CR_EREC )
+#define __aic_enable_replay()   ( REG_AIC_CR |= AIC_CR_ERPL )
+#define __aic_disable_replay()  ( REG_AIC_CR &= ~AIC_CR_ERPL )
+#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
+#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
+
+#define __aic_flush_tfifo() ( REG_AIC_CR |= AIC_CR_TFLUSH )
+#define __aic_unflush_tfifo()   ( REG_AIC_CR &= ~AIC_CR_TFLUSH )
+#define __aic_flush_rfifo() ( REG_AIC_CR |= AIC_CR_RFLUSH )
+#define __aic_unflush_rfifo()   ( REG_AIC_CR &= ~AIC_CR_RFLUSH )
+
+#define __aic_enable_transmit_intr() \
+  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
+#define __aic_disable_transmit_intr() \
+  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
+#define __aic_enable_receive_intr() \
+  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
+#define __aic_disable_receive_intr() \
+  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
+
+#define __aic_enable_transmit_dma()  ( REG_AIC_CR |= AIC_CR_TDMS )
+#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
+#define __aic_enable_receive_dma()   ( REG_AIC_CR |= AIC_CR_RDMS )
+#define __aic_disable_receive_dma()  ( REG_AIC_CR &= ~AIC_CR_RDMS )
+
+#define __aic_enable_mono2stereo()   ( REG_AIC_CR |= AIC_CR_M2S )
+#define __aic_disable_mono2stereo()  ( REG_AIC_CR &= ~AIC_CR_M2S )
+#define __aic_enable_byteswap()      ( REG_AIC_CR |= AIC_CR_ENDSW )
+#define __aic_disable_byteswap()     ( REG_AIC_CR &= ~AIC_CR_ENDSW )
+#define __aic_enable_unsignadj()     ( REG_AIC_CR |= AIC_CR_AVSTSU )
+#define __aic_disable_unsignadj()    ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
+
+#define AC97_PCM_XS_L_FRONT     AIC_ACCR1_XS_SLOT(3)
+#define AC97_PCM_XS_R_FRONT     AIC_ACCR1_XS_SLOT(4)
+#define AC97_PCM_XS_CENTER      AIC_ACCR1_XS_SLOT(6)
+#define AC97_PCM_XS_L_SURR      AIC_ACCR1_XS_SLOT(7)
+#define AC97_PCM_XS_R_SURR      AIC_ACCR1_XS_SLOT(8)
+#define AC97_PCM_XS_LFE         AIC_ACCR1_XS_SLOT(9)
+
+#define AC97_PCM_RS_L_FRONT     AIC_ACCR1_RS_SLOT(3)
+#define AC97_PCM_RS_R_FRONT     AIC_ACCR1_RS_SLOT(4)
+#define AC97_PCM_RS_CENTER      AIC_ACCR1_RS_SLOT(6)
+#define AC97_PCM_RS_L_SURR      AIC_ACCR1_RS_SLOT(7)
+#define AC97_PCM_RS_R_SURR      AIC_ACCR1_RS_SLOT(8)
+#define AC97_PCM_RS_LFE         AIC_ACCR1_RS_SLOT(9)
+
+#define __ac97_set_xs_none()    ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
+#define __ac97_set_xs_mono()                        \
+do {                                    \
+    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;                \
+    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT;               \
+} while(0)
+#define __ac97_set_xs_stereo()                      \
+do {                                    \
+    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;                \
+    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
+} while(0)
+
+/* In fact, only stereo is support now. */
+#define __ac97_set_rs_none()    ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
+#define __ac97_set_rs_mono()                        \
+do {                                    \
+    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;                \
+    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT;               \
+} while(0)
+#define __ac97_set_rs_stereo()                      \
+do {                                    \
+    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;                \
+    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
+} while(0)
+
+#define __ac97_warm_reset_codec()       \
+ do {                       \
+    REG_AIC_ACCR2 |= AIC_ACCR2_SA;      \
+    REG_AIC_ACCR2 |= AIC_ACCR2_SS;      \
+    udelay(2);              \
+    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS;     \
+    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA;     \
+ } while (0)
+
+#define __ac97_cold_reset_codec()       \
+ do {                       \
+    REG_AIC_ACCR2 |=  AIC_ACCR2_SR;     \
+    udelay(2);              \
+    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR;     \
+ } while (0)
+
+/* n=8,16,18,20 */
+#define __ac97_set_iass(n) \
+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
+#define __ac97_set_oass(n) \
+ ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
+
+/* This bit should only be set in 2 channels configuration */
+#define __i2s_send_rfirst()   ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST )  /* RL */
+#define __i2s_send_lfirst()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */
+
+/* This bit should only be set in 2 channels configuration and 16bit-packed mode */
+#define __i2s_switch_lr()     ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH )
+#define __i2s_unswitch_lr()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH )
+
+#define __i2s_select_i2s()            ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
+#define __i2s_select_msbjustified()   ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
+
+/* n=8,16,18,20,24 */
+/*#define __i2s_set_sample_size(n) \
+ ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
+
+#define __i2s_out_channel_select(n) __aic_out_channel_select(n)
+
+#define __i2s_set_oss_sample_size(n) \
+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n))
+#define __i2s_set_iss_sample_size(n) \
+ ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n))
+
+#define __i2s_stop_bitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
+#define __i2s_start_bitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
+
+#define __i2s_stop_ibitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_ISTPBK )
+#define __i2s_start_ibitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_ISTPBK )
+
+#define __aic_transmit_request()  ( REG_AIC_SR & AIC_SR_TFS )
+#define __aic_receive_request()   ( REG_AIC_SR & AIC_SR_RFS )
+#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
+#define __aic_receive_overrun()   ( REG_AIC_SR & AIC_SR_ROR )
+
+#define __aic_clear_errors()      ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
+
+#define __aic_get_transmit_resident() \
+  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB )
+#define __aic_get_receive_count() \
+  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB )
+
+#define __ac97_command_transmitted()     ( REG_AIC_ACSR & AIC_ACSR_CADT )
+#define __ac97_status_received()         ( REG_AIC_ACSR & AIC_ACSR_SADR )
+#define __ac97_status_receive_timeout()  ( REG_AIC_ACSR & AIC_ACSR_RSTO )
+#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
+#define __ac97_codec_is_ready()          ( REG_AIC_ACSR & AIC_ACSR_CRDY )
+#define __ac97_slot_error_detected()     ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
+#define __ac97_clear_slot_error()        ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
+
+#define __i2s_is_busy()         ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
+
+#define __ac97_out_rcmd_addr(reg)                   \
+do {                                    \
+    REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB);  \
+} while (0)
+
+#define __ac97_out_wcmd_addr(reg)                   \
+do {                                    \
+    REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB);     \
+} while (0)
+
+#define __ac97_out_data(value)                      \
+do {                                    \
+    REG_AIC_ACCDR = ((value) << AC97_DATA_LSB);             \
+} while (0)
+
+#define __ac97_in_data() \
+ ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB )
+
+#define __ac97_in_status_addr() \
+ ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB )
+
+#define __i2s_set_sample_rate(i2sclk, sync) \
+  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
+
+#define __aic_write_tfifo(v)  ( REG_AIC_DR = (v) )
+#define __aic_read_rfifo()    ( REG_AIC_DR )
+
+#define __aic_internal_codec()  ( REG_AIC_FR |= AIC_FR_ICDC )
+#define __aic_external_codec()  ( REG_AIC_FR &= ~AIC_FR_ICDC )
+#define __aic0_internal_codec()  ( REG_AIC0_FR |= AIC_FR_ICDC )
+#define __aic0_external_codec()  ( REG_AIC0_FR &= ~AIC_FR_ICDC )
+
+//
+// Define next ops for AC97 compatible
+//
+
+#define AC97_ACSR   AIC_ACSR
+
+#define __ac97_enable()     __aic_enable(); __aic_select_ac97()
+#define __ac97_disable()    __aic_disable()
+#define __ac97_reset()      __aic_reset()
+
+#define __ac97_set_transmit_trigger(n)  __aic_set_transmit_trigger(n)
+#define __ac97_set_receive_trigger(n)   __aic_set_receive_trigger(n)
+
+#define __ac97_enable_record()      __aic_enable_record()
+#define __ac97_disable_record()     __aic_disable_record()
+#define __ac97_enable_replay()      __aic_enable_replay()
+#define __ac97_disable_replay()     __aic_disable_replay()
+#define __ac97_enable_loopback()    __aic_enable_loopback()
+#define __ac97_disable_loopback()   __aic_disable_loopback()
+
+#define __ac97_enable_transmit_dma()    __aic_enable_transmit_dma()
+#define __ac97_disable_transmit_dma()   __aic_disable_transmit_dma()
+#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
+#define __ac97_disable_receive_dma()    __aic_disable_receive_dma()
+
+#define __ac97_transmit_request()   __aic_transmit_request()
+#define __ac97_receive_request()    __aic_receive_request()
+#define __ac97_transmit_underrun()  __aic_transmit_underrun()
+#define __ac97_receive_overrun()    __aic_receive_overrun()
+
+#define __ac97_clear_errors()       __aic_clear_errors()
+
+#define __ac97_get_transmit_resident()  __aic_get_transmit_resident()
+#define __ac97_get_receive_count()  __aic_get_receive_count()
+
+#define __ac97_enable_transmit_intr()   __aic_enable_transmit_intr()
+#define __ac97_disable_transmit_intr()  __aic_disable_transmit_intr()
+#define __ac97_enable_receive_intr()    __aic_enable_receive_intr()
+#define __ac97_disable_receive_intr()   __aic_disable_receive_intr()
+
+#define __ac97_write_tfifo(v)       __aic_write_tfifo(v)
+#define __ac97_read_rfifo()     __aic_read_rfifo()
+
+//
+// Define next ops for I2S compatible
+//
+
+#define I2S_ACSR    AIC_I2SSR
+
+#define __i2s_enable()       __aic_enable(); __aic_select_i2s()
+#define __i2s_disable()     __aic_disable()
+#define __i2s_reset()       __aic_reset()
+
+#define __i2s_set_transmit_trigger(n)   __aic_set_transmit_trigger(n)
+#define __i2s_set_receive_trigger(n)    __aic_set_receive_trigger(n)
+
+#define __i2s_enable_record()       __aic_enable_record()
+#define __i2s_disable_record()      __aic_disable_record()
+#define __i2s_enable_replay()       __aic_enable_replay()
+#define __i2s_disable_replay()      __aic_disable_replay()
+#define __i2s_enable_loopback()     __aic_enable_loopback()
+#define __i2s_disable_loopback()    __aic_disable_loopback()
+
+#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
+#define __i2s_disable_transmit_dma()    __aic_disable_transmit_dma()
+#define __i2s_enable_receive_dma()  __aic_enable_receive_dma()
+#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
+
+#define __i2s_transmit_request()    __aic_transmit_request()
+#define __i2s_receive_request()     __aic_receive_request()
+#define __i2s_transmit_underrun()   __aic_transmit_underrun()
+#define __i2s_receive_overrun()     __aic_receive_overrun()
+
+#define __i2s_clear_errors()        __aic_clear_errors()
+
+#define __i2s_get_transmit_resident()   __aic_get_transmit_resident()
+#define __i2s_get_receive_count()   __aic_get_receive_count()
+
+#define __i2s_enable_transmit_intr()    __aic_enable_transmit_intr()
+#define __i2s_disable_transmit_intr()   __aic_disable_transmit_intr()
+#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
+#define __i2s_disable_receive_intr()    __aic_disable_receive_intr()
+
+#define __i2s_write_tfifo(v)        __aic_write_tfifo(v)
+#define __i2s_read_rfifo()      __aic_read_rfifo()
+
+#define __i2s_reset_codec()         \
+ do {                       \
+ } while (0)
+
+
+/*************************************************************************
+ * SPDIF INTERFACE in AIC Controller
+ *************************************************************************/
+
+#define __spdif_enable()        ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN )
+#define __spdif_disable()       ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN )
+
+#define __spdif_enable_transmit_dma()     ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN )
+#define __spdif_disable_transmit_dma()    ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN )
+#define __spdif_enable_dtype()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE )
+#define __spdif_disable_dtype()           ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE )
+#define __spdif_enable_sign()             ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN )
+#define __spdif_disable_sign()            ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN )
+#define __spdif_enable_invalid()          ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID )
+#define __spdif_disable_invalid()         ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID )
+#define __spdif_enable_reset()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST )
+#define __spdif_select_spdif()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S )
+#define __spdif_select_i2s()              ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S )
+#define __spdif_enable_MTRIGmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG )
+#define __spdif_disable_MTRIGmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG )
+#define __spdif_enable_MFFURmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR )
+#define __spdif_disable_MFFURmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR )
+
+#define __spdif_enable_initlvl_high()     ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_INITLVL )
+#define __spdif_enable_initlvl_low()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_INITLVL )
+#define __spdif_enable_zrovld_invald()    ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_ZROVLD )
+#define __spdif_enable_zrovld_vald()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_ZROVLD )
+
+/* 0, 1, 2, 3 */
+#define __spdif_set_transmit_trigger(n)         \
+do {                            \
+    REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK;    \
+    REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n);   \
+} while(0)
+
+/* 1 ~ 15 */
+#define __spdif_set_srcnum(n)               \
+do {                            \
+    REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK;  \
+    REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB);   \
+} while(0)
+
+/* 1 ~ 15 */
+#define __spdif_set_ch1num(n)               \
+do {                            \
+    REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK;  \
+    REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB);   \
+} while(0)
+
+/* 1 ~ 15 */
+#define __spdif_set_ch2num(n)               \
+do {                            \
+    REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK;  \
+    REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB);   \
+} while(0)
+
+/* 0x0, 0x2, 0x3, 0xa, 0xe */
+#define __spdif_set_fs(n)               \
+do {                            \
+    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK;      \
+    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB);   \
+} while(0)
+
+/* 0xd, 0xc, 0x5, 0x1 */
+#define __spdif_set_orgfrq(n)               \
+do {                            \
+    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK;      \
+    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB);   \
+} while(0)
+
+/* 0x1, 0x6, 0x2, 0x4, 0x5 */
+#define __spdif_set_samwl(n)                \
+do {                            \
+    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK;       \
+    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB);    \
+} while(0)
+
+#define __spdif_enable_samwl_24()    ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL )
+#define __spdif_enable_samwl_20()    ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL )
+
+/* 0x1, 0x1, 0x2, 0x3 */
+#define __spdif_set_clkacu(n)               \
+do {                            \
+    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK;      \
+    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB);   \
+} while(0)
+
+/* see IEC60958-3 */
+#define __spdif_set_catcode(n)              \
+do {                            \
+    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK;     \
+    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB);  \
+} while(0)
+
+/* n = 0x0, */
+#define __spdif_set_chmode(n)               \
+do {                            \
+    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK;    \
+    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB); \
+} while(0)
+
+#define __spdif_enable_pre()       ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE )
+#define __spdif_disable_pre()      ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE )
+#define __spdif_enable_copyn()     ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN )
+#define __spdif_disable_copyn()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN )
+/* audio sample word represents linear PCM samples */
+#define __spdif_enable_audion()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION )
+/* udio sample word used for other purpose */
+#define __spdif_disable_audion()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION )
+#define __spdif_enable_conpro()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO )
+#define __spdif_disable_conpro()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO )
+
+/***************************************************************************
+ * ICDC
+ ***************************************************************************/
+#define __i2s_internal_codec()         __aic_internal_codec()
+#define __i2s_external_codec()         __aic_external_codec()
+
+#define __icdc_clk_ready()             ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY )
+#define __icdc_sel_adc()               ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD )
+#define __icdc_sel_dac()               ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD )
+
+#define __icdc_set_rgwr()              ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR )
+#define __icdc_clear_rgwr()            ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR )
+#define __icdc_rgwr_ready()            ( REG_ICDC_RGADW & ICDC_RGADW_RGWR )
+
+#define AIC_RW_CODEC_START()        while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR)
+#define AIC_RW_CODEC_STOP()     while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR)
+
+
+#define __icdc_set_addr(n)              \
+do {                                \
+    REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK;  \
+    REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB; \
+} while(0)
+
+#define __icdc_set_cmd(n)               \
+do {                                \
+    REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK;   \
+    REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB;  \
+} while(0)
+
+#define __icdc_irq_pending()            ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ )
+#define __icdc_get_value()              ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK )
+
+
+
+#endif /* __MIPS_ASSEMBLER */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _X1000_AIC_H_ */
diff --git a/bsp/x1000/cpu/x1000/x1000_cpm.h b/bsp/x1000/cpu/x1000/x1000_cpm.h
new file mode 100644
index 0000000000..da2cc964e5
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/x1000_cpm.h
@@ -0,0 +1,511 @@
+/*
+ * File      : x1000_cpm.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-02-03     Urey         the first version
+ */
+
+#ifndef _X1000_CPM_H_
+#define _X1000_CPM_H_
+
+#define CPM_CPCCR       (0x00)
+#define CPM_CPCSR       (0xd4)
+
+#define CPM_DDRCDR      (0x2c)
+#define CPM_I2SCDR      (0x60)
+#define CPM_I2SCDR1     (0x70)
+#define CPM_LPCDR       (0x64)
+#define CPM_MSC0CDR     (0x68)
+#define CPM_MSC1CDR     (0xa4)
+#define CPM_USBCDR      (0x50)
+#define CPM_MACCDR      (0x54)
+#define CPM_UHCCDR      (0x6c)
+#define CPM_SFCCDR      (0x74)
+#define CPM_CIMCDR      (0x7c)
+#define CPM_PCMCDR      (0x84)
+#define CPM_PCMCDR1     (0xe0)
+#define CPM_MPHYC       (0xe8)
+
+#define CPM_INTR        (0xb0)
+#define CPM_INTRE       (0xb4)
+#define CPM_DRCG        (0xd0)
+#define CPM_CPSPPR      (0x38)
+#define CPM_CPPSR       (0x34)
+
+#define CPM_USBPCR      (0x3c)
+#define CPM_USBRDT      (0x40)
+#define CPM_USBVBFIL    (0x44)
+#define CPM_USBPCR1     (0x48)
+
+#define CPM_CPAPCR      (0x10)
+#define CPM_CPMPCR      (0x14)
+
+#define CPM_LCR         (0x04)
+#define CPM_PSWC0ST     (0x90)
+#define CPM_PSWC1ST     (0x94)
+#define CPM_PSWC2ST     (0x98)
+#define CPM_PSWC3ST     (0x9c)
+#define CPM_CLKGR       (0x20)
+#define CPM_CLKGR0       (0x20)
+#define CPM_MESTSEL     (0xec)
+#define CPM_SRBC        (0xc4)
+#define CPM_ERNG        (0xd8)
+#define CPM_RNG         (0xdc)
+#define CPM_SLBC        (0xc8)
+#define CPM_SLPC        (0xcc)
+#define CPM_OPCR        (0x24)
+#define CPM_RSR         (0x08)
+
+
+
+
+/*
+ * CPM registers common define
+ */
+
+/* Clock control register(CPCCR) */
+#define CPCCR_SEL_SRC_LSB       30
+#define CPCCR_SEL_SRC_MASK      BITS_H2L(31, CPCCR_SEL_SRC_LSB)
+
+#define CPCCR_SEL_CPLL_LSB      28
+#define CPCCR_SEL_CPLL_MASK     BITS_H2L(29, CPCCR_SEL_CPLL_LSB)
+
+#define CPCCR_SEL_H0PLL_LSB     26
+#define CPCCR_SEL_H0PLL_MASK    BITS_H2L(27, CPCCR_SEL_H0PLL_LSB)
+
+#define CPCCR_SEL_H2PLL_LSB     24
+#define CPCCR_SEL_H2PLL_MASK    BITS_H2L(25, CPCCR_SEL_H2PLL_LSB)
+
+#define CPCCR_CE_CPU            BIT22
+#define CPCCR_CE_AHB0           BIT21
+#define CPCCR_CE_AHB2           BIT20
+#define CPCCR_CE                (CPCCR_CE_CPU | CPCCR_CE_AHB0 | CPCCR_CE_AHB2)
+
+#define CPCCR_PDIV_LSB          16
+#define CPCCR_PDIV_MASK         BITS_H2L(19, CPCCR_PDIV_LSB)
+
+#define CPCCR_H2DIV_LSB         12
+#define CPCCR_H2DIV_MASK        BITS_H2L(15, CPCCR_H2DIV_LSB)
+
+#define CPCCR_H0DIV_LSB         8
+#define CPCCR_H0DIV_MASK        BITS_H2L(11, CPCCR_H0DIV_LSB)
+
+#define CPCCR_L2DIV_LSB         4
+#define CPCCR_L2DIV_MASK        BITS_H2L(7,  CPCCR_L2DIV_LSB)
+
+#define CPCCR_CDIV_LSB          0
+#define CPCCR_CDIV_MASK         BITS_H2L(3,  CPCCR_CDIV_LSB)
+
+#define CPM_SRC_SEL_APLL        1
+#define CPM_PLL_SEL_SRC         1
+#define CPM_PLL_SEL_MPLL        2
+
+/* Clock Status register(CPCSR) */
+#define CPCSR_SRC_MUX           BIT31
+#define CPCSR_CPU_MUX           BIT30
+#define CPCSR_AHB0_MUX          BIT29
+#define CPCSR_AHB2_MUX          BIT28
+#define CPCSR_DDR_MUX           BIT27
+#define CPCSR_H2DIV_BUSY        BIT2
+#define CPCSR_H0DIV_BUSY        BIT1
+#define CPCSR_CDIV_BUSY         BIT0
+#define CPCSR_DIV_BUSY          (CPCSR_H2DIV_BUSY | CPCSR_H0DIV_BUSY | CPCSR_CDIV_BUSY)
+
+/* DDR clock divider register(DDCDR) */
+#define DDCDR_DCS_LSB           30
+#define DDCDR_DCS_MASK          BITS_H2L(31, DDCDR_DCS_LSB)
+#define DDCDR_DCS_STOP          (0 << DDCDR_DCS_LSB)
+#define DDCDR_DCS_APLL          (1 << DDCDR_DCS_LSB)
+#define DDCDR_DCS_MPLL          (2 << DDCDR_DCS_LSB)
+#define DDCDR_CE_DDR            BIT29
+#define DDCDR_DDR_BUSY          BIT28
+#define DDCDR_DDR_STOP          BIT27
+#define DDCDR_GATE_EN           BIT26
+#define DDCDR_DDR_CHANGE_EN     BIT25
+#define DDCDR_DDR               BIT24
+#define DDCDR_DDRDIV_LSB        0
+#define DDCDR_DDRDIV_MASK       BITS_H2L(3, DDCDR_DDRDIV_LSB)
+
+/*MACPHY clock divider Register (MACCDR)*/
+#define MACCDR_MACPCS           BIT31
+#define MACCDR_CE_MAC           BIT29
+#define MACCDR_MAC_BUSY         BIT28
+#define MACCDR_MAC_STOP         BIT27
+#define MACCDR_MACCDR_LSB       BIT0
+#define MACCDR_MACCDR_MASK      BITS_H2L(7,MACCDR_MACCDR_LSB)
+
+/* I2S device clock divider register(I2SCDR) */
+#define I2SCDR_I2PCS            BIT31
+#define I2SCDR_I2CS             BIT30
+
+#define I2SCDR_I2SDIV_M_LSB     13
+#define I2SCDR_I2SDIV_M_MASK    BITS_H2L(21,I2SCDR_I2SDIV_M_LSB)
+#define I2SCDR_I2SDIV_N_LSB     0       /* I2SCDR bit */
+#define I2SCDR_I2SDIV_N_MASK    BITS_H2L(7, I2SCDR_I2SDIV_N_LSB)
+
+
+/* I2S device clock divider register(I2SCDR1) */
+#define I2SCDR1_NEN             BIT31
+#define I2SCDR1_DEN             BIT30
+#define I2SCDR1_I2SDIV_D_LSB    0
+#define I2SCDR1_I2SDIV_D_MASK   BITS_H2L(12,I2SCDR1_I2SDIV_D_LSB)
+
+/* LCD pix clock divider register(LPCDR) */
+#define LPCDR_LPCS_LSB          31
+#define LPCDR_LPCS_APLL         (0 << LPCDR_LPCS_LSB)
+#define LPCDR_LPCS_MPLL         (1 << LPCDR_LPCS_LSB)
+#define LPCDR_CE_LCD            BIT28
+#define LPCDR_LCD_BUSY          BIT27
+#define LPCDR_LCD_STOP          BIT26
+
+#define LPCDR_PIXDIV_LSB        0       /* LPCDR bit */
+#define LPCDR_PIXDIV_MASK       BITS_H2L(7, LPCDR_PIXDIV_LSB)
+
+/* MSC clock divider register(MSCCDR) */
+#define MSCCDR_MPCS_LSB         31       /* MPCS bit */
+#define MSCCDR_MPCS_APLL        (0 << MSCCDR_MPCS_LSB)
+#define MSCCDR_MPCS_MPLL        (1 << MSCCDR_MPCS_LSB)
+
+#define MSCCDR_CE_MSC           BIT29
+#define MSCCDR_MSC_BUSY         BIT28
+#define MSCCDR_MSC_STOP         BIT27
+#define MSCCDR_S_CLK0_SEL       BIT15
+
+#define MSCCDR_MSCDIV_LSB       0       /* MSCCDR bit */
+#define MSCCDR_MSCDIV_MASK      BITS_H2L(7, MSCCDR_MSCDIV_LSB)
+
+
+/* OTG PHY clock divider register(USBCDR) */
+#define USBCDR_UCS              BIT31
+#define USBCDR_UPCS             BIT30
+#define USBCDR_CE_USB           BIT29
+#define USBCDR_USB_BUSY         BIT28
+#define USBCDR_USB_STOP         BIT27
+
+#define USBCDR_OTGDIV_LSB       0       /* USBCDR bit */
+#define USBCDR_OTGDIV_MASK      BITS_H2L(7, USBCDR_OTGDIV_LSB)
+
+/* SSI clock divider register(SSICDR) */
+#define SSICDR_SPCS             BIT31
+#define SSICDR_SCS              BIT30
+#define SSICDR_CE_SSI           BIT29
+#define SSICDR_SSI_BUSY         BIT28
+#define SSICDR_SSI_STOP         BIT27
+#define SSICDR_SSIDIV_LSB       0       /* SSICDR bit */
+#define SSICDR_SSIDIV_MASK      BITS_H2L(7, SSICDR_SSIDIV_LSB)
+
+/* CIM mclk clock divider register(CIMCDR) */
+#define CIMCDR_CIMPCS_APLL      (0 << 31)
+#define CIMCDR_CIMPCS_MPLL      BIT31
+#define CIMCDR_CE_CIM           BIT29
+#define CIMCDR_CIM_BUSY         BIT28
+#define CIMCDR_CIM_STOP         BIT27
+
+#define CIMCDR_CIMDIV_LSB       0       /* CIMCDR bit */
+#define CIMCDR_CIMDIV_MASK      BITS_H2L(7, CIMCDR_CIMDIV_LSB)
+
+
+/* PCM device clock divider register(PCMCDR) */
+#define PCMCDR_PCMPCS_LSB       30
+#define PCMCDR_PCMPCS_MASK      BITS_H2L(31,PCMCDR_PCMPCS_LSB)
+#define PCMCDR_PCMPCS_SCLK_A    0 << PCMCDR_PCMPCS_LSB
+#define PCMCDR_PCMPCS_EXTCLK    1 << PCMCDR_PCMPCS_LSB
+#define PCMCDR_PCMPCS_MPLL      2 << PCMCDR_PCMPCS_LSB
+#define PCMCDR_CE_PCM           BIT29
+#define PCMCDR_PCMDIV_M_LSB     13
+#define PCMCDR_PCMDIV_M_MASK    BITS_H2L(21,PCMCDR_PCMDIV_M_LSB)
+#define PCMCDR_PCMDIV_N_LSB     0
+#define PCMCDR_PCMDIV_N_MASK    BITS_H2L(12,PCMCDR_PCMDIV_N_LSB)
+
+/* PCM device clock divider register(PCMCDR1) */
+
+#define PCMCDR1_PCM_NEN         BIT31
+#define PCMCDR1_PCM_DEN         BIT30
+#define PCMCDR1_PCMDIV_D_LSB    0
+#define PCMCDR1_PCMDIV_D_MASK   BITS_H2L(12,PCMCDR1_PCMDIV_D_LSB)
+
+/* MAC PHY Control Register (MPHYC) */
+#define MPHYC_MODE_SEL          BIT31  //useless now
+#define MPHYC_MAC_SPEED_LSB     29
+#define MPHYC_MAC_SPEED_MASK    BITS_H2L(30,MPHYC_MAC_SPEED_LSB)
+#define MPHYC_SOFT_RST          BIT3
+#define MPHYC_PHY_INTF_LSB      0
+#define MPHYC_PHY_INTF_MASK     BITS_H2L(2,MPHYC_PHY_INTF_MASK) //useless now
+
+/* CPM Interrupt Register (CPM_INTR)*/
+#define CPM_INTR_VBUS_INTR      BIT1
+#define CPM_INTR_ADEV_INTR      BIT0
+
+/* CPM Interrupt Enable Register (CPM_INTRE)*/
+#define CPM_INTRE_VBUS_INTRE    BIT1
+#define CPM_INTRE_ADEV_INTRE    BIT0
+
+/* CPM scratch pad protected register(CPSPPR) */
+#define CPSPPR_CPSPR_WRITABLE   (0x00005a5a)
+
+/* OTG parameter control register(USBPCR) */
+#define USBPCR_USB_MODE         BIT31
+#define USBPCR_AVLD_REG         BIT30
+#define USBPCR_INCRM            BIT27   /* INCR_MASK bit */
+#define USBPCR_TXRISE_TUNE      BIT26
+#define USBPCR_COMMONONN        BIT25
+#define USBPCR_VBUSVLDEXT       BIT24
+#define USBPCR_VBUSVLDEXTSEL    BIT23
+#define USBPCR_POR              BIT22
+#define USBPCR_SIDDQ            BIT21
+#define USBPCR_OTG_DISABLE      BIT20
+#define USBPCR_TXPREEMPHTUNE    BIT6
+
+#define USBPCR_IDPULLUP_LSB     28   /* IDPULLUP_MASK bit */
+#define USBPCR_IDPULLUP_MASK    BITS_H2L(29, USBPCR_IDPULLUP_LSB)
+
+#define USBPCR_COMPDISTUNE_LSB  17
+#define USBPCR_COMPDISTUNE_MASK BITS_H2L(19, USBPCR_COMPDISTUNE_LSB)
+
+#define USBPCR_OTGTUNE_LSB      14
+#define USBPCR_OTGTUNE_MASK     BITS_H2L(16, USBPCR_OTGTUNE_LSB)
+
+#define USBPCR_SQRXTUNE_LSB     11
+#define USBPCR_SQRXTUNE_MASK    BITS_H2L(13, USBPCR_SQRXTUNE_LSB)
+
+#define USBPCR_TXFSLSTUNE_LSB   7
+#define USBPCR_TXFSLSTUNE_MASK  BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB)
+
+#define USBPCR_TXRISETUNE_LSB   4
+#define USBPCR_TXRISETUNE_MASK  BITS_H2L(5, USBPCR_TXRISETUNE_LSB)
+
+#define USBPCR_TXVREFTUNE_LSB   0
+#define USBPCR_TXVREFTUNE_MASK  BITS_H2L(3, USBPCR_TXVREFTUNE_LSB)
+
+/* OTG reset detect timer register(USBRDT) */
+#define USBRDT_HB_MASK          BIT26
+#define USBRDT_VBFIL_LD_EN      BIT25
+#define USBRDT_IDDIG_EN         BIT24
+#define USBRDT_IDDIG_REG        BIT23
+
+#define USBRDT_USBRDT_LSB       0
+#define USBRDT_USBRDT_MASK      BITS_H2L(22, USBRDT_USBRDT_LSB)
+
+/* OTG parameter control register(USBPCR1) */
+#define USBPCR1_REG             BIT31
+#define USBPCR1_USB_SEL         BIT28
+#define USBPCR1_REFCLKSEL_LSB   26
+#define USBPCR1_REFCLKSEL_MASK  BITS_H2L(27, USBPCR1_REFCLKSEL_LSB)
+
+#define USBPCR1_REFCLKDIV_LSB   24
+#define USBPCR1_REFCLKDIV_MASK  BITS_H2L(25, USBPCR1_REFCLKDIV_LSB)
+
+#define USBPCR1_PORT_RST        BIT21
+
+#define USBPCR1_WORD_IF0        BIT19
+#define USBPCR1_WORD_IF1        BIT18
+
+
+/* APLL control register (CPXPCR) */
+#define CPAPCR_BS               BIT31
+#define CPAPCR_M_LSB            24
+#define CPAPCR_M_MASK           BITS_H2L(30, CPAPCR_M_LSB)
+
+#define CPAPCR_N_LSB            18
+#define CPAPCR_N_MASK           BITS_H2L(22, CPAPCR_N_LSB)
+
+#define CPAPCR_OD_LSB           16
+#define CPAPCR_OD_MASK          BITS_H2L(17, CPAPCR_OD_LSB)
+
+#define CPAPCR_LOCK             BIT15   /* LOCK bit */
+#define CPAPCR_ON               BIT10
+#define CPAPCR_BP               BIT9
+#define CPAPCR_EN               BIT8
+#define CPAPCR_PLLST_LSB        0
+#define CPAPCR_PLLST_MASK       BITS_H2L(7,CPAPCR_PLLST_LSB)
+
+#define CPM_CPAPCR_EN           CPAPCR_EN
+#define CPM_CPAPCR_ON           CPAPCR_ON
+
+/* MPLL control register (CPXPCR) */
+#define CPMPCR_BS               BIT31
+#define CPMPCR_M_LSB            24
+#define CPMPCR_M_MASK           BITS_H2L(30, CPAPCR_M_LSB)
+
+#define CPMPCR_N_LSB            18
+#define CPMPCR_N_MASK           BITS_H2L(22, CPAPCR_N_LSB)
+
+#define CPMPCR_OD_LSB           16
+#define CPMPCR_OD_MASK          BITS_H2L(17, CPAPCR_OD_LSB)
+
+#define CPMPCR_EN               BIT7
+#define CPMPCR_BP               BIT6
+#define CPMPCR_LOCK             BIT1    /* LOCK bit */
+#define CPMPCR_ON               BIT0
+
+#define CPM_CPMPCR_EN           CPMPCR_EN
+#define CPM_CPMPCR_ON           CPMPCR_ON
+
+
+
+/* Low power control register(LCR) */
+#define LCR_PST_LSB             8
+#define LCD_PST_MASK            BITS_H2L(19,LCR_PST_LSB)
+#define LCR_LPM_LSB             0
+#define LCR_LPM_MASK            BITS_H2L(1,LCR_LPM_LSB)
+
+/* Clock gate register 0(CGR0) */
+#define CLKGR0_DDR              BIT31
+#define CLKGR0_CPU              BIT30
+#define CLKGR0_AHB0             BIT29
+#define CLKGR0_APB0             BIT28
+#define CLKGR0_RTC              BIT27
+#define CLKGR0_PCM              BIT26
+#define CLKGR0_MAC              BIT25
+#define CLKGR0_AES              BIT24
+#define CLKGR0_LCD              BIT23
+#define CLKGR0_CIM              BIT22
+#define CLKGR0_PDMA             BIT21
+#define CLKGR0_OST              BIT20
+#define CLKGR0_SSI              BIT19
+#define CLKGR0_TCU              BIT18
+#define CLKGR0_DMIC             BIT17
+#define CLKGR0_UART2            BIT16
+#define CLKGR0_UART1            BIT15
+#define CLKGR0_UART0            BIT14
+#define CLKGR0_SADC             BIT13
+#define CLKGR0_JPEG             BIT12
+#define CLKGR0_AIC              BIT11
+#define CLKGR0_I2C3             BIT10
+#define CLKGR0_I2C2             BIT9
+#define CLKGR0_I2C1             BIT8
+#define CLKGR0_I2C0             BIT7
+#define CLKGR0_SCC              BIT6
+#define CLKGR0_MSC1             BIT5
+#define CLKGR0_MSC0             BIT4
+#define CLKGR0_OTG              BIT3
+#define CLKGR0_SFC              BIT2
+#define CLKGR0_EFUSE            BIT1
+#define CLKGR0_NEMC             BIT0
+
+/* CPM MEST SEL Register */
+
+#define MEST_SEL_TST8           BIT8
+#define MEST_SEL_TST7           BIT7
+#define MEST_SEL_TST4           BIT4
+#define MEST_SEL_TST3           BIT3
+#define MEST_SEL_TST1           BIT1
+#define MEST_SEL_TST0           BIT0
+
+/*Soft Reset and Bus Control Register (SRBC)*/
+
+#define SRBC_JPEG_SR            BIT31
+#define SRBC_JPEG_STP           BIT30
+#define SRBC_JPEG_ACK           BIT29
+#define SRBC_LCD_SR             BIT25
+#define SRBC_LCD_STP            BIT24
+#define SRBC_LCD_ACK            BIT23
+#define SRBC_CIM_STP            BIT21
+#define SRBC_CIM_ACK            BIT20
+#define SRBC_CPU_STP            BIT15
+#define SRBC_CPU_ACK            BIT14
+#define SRBC_OTG_SR             BIT12
+#define SRBC_AHB2_STP           BIT8
+#define SRBC_AHB2_ACK           BIT7
+#define SRBC_DDR_STP            BIT6
+#define SRBC_DDR_ACK            BIT5
+
+
+/* Oscillator and power control register(OPCR) */
+#define OPCR_IDLE_DIS           BIT31
+#define OPCR_MASK_INT           BIT30
+#define OPCR_MASK_VPU           BIT29  //ONLY FOR DEBUG
+#define OPCR_GATE_SCLK_ABUS     BIT28
+#define OPCR_L2C_PD             BIT25
+#define OPCR_REQ_MODE           BIT24
+#define OPCR_GATE_USBPHY_CLK    BIT23
+#define OPCR_DIS_STOP_MUX       BIT22
+#define OPCR_O1ST_LSB           8
+#define OPCR_O1ST_MASK          BITS_H2L(19, OPCR_O1ST_LSB)
+#define OPCR_OTGPHY0_ENABLE     BIT7    /* otg */
+#define OPCR_OTGPHY1_ENABLE     BIT6    /* uhc */
+#define OPCR_USBPHY_ENABLE      (OPCR_OTGPHY0_ENABLE | OPCR_OTGPHY1_ENABLE)
+#define OPCR_O1SE               BIT4
+#define OPCR_PD                 BIT3
+#define OPCR_ERCS               BIT2
+#define OPCR_BUSMODE            BIT1
+
+
+
+/* Reset status register(RSR) */
+#define RSR_HR                  BIT3
+#define RSR_P0R                 BIT2
+#define RSR_WR                  BIT1
+#define RSR_PR                  BIT0
+
+
+#ifndef __ASSEMBLY__
+
+#define REG_CPM_CPCCR           REG32(CPM_BASE + CPM_CPCCR)
+#define REG_CPM_CPCSR           REG32(CPM_BASE + CPM_CPCSR)
+#define REG_CPM_DDCDR           REG32(CPM_BASE + CPM_DDCDR)
+#define REG_CPM_MACCDR          REG32(CPM_BASE + CPM_MACCDR)
+#define REG_CPM_I2SCDR          REG32(CPM_BASE + CPM_I2SCDR)
+#define REG_CPM_I2SCDR1         REG32(CPM_BASE + CPM_I2SCDR1)
+#define REG_CPM_LPCDR           REG32(CPM_BASE + CPM_LPCDR)
+#define REG_CPM_MSC0CDR         REG32(CPM_BASE + CPM_MSC0CDR)
+#define REG_CPM_MSC1CDR         REG32(CPM_BASE + CPM_MSC1CDR)
+#define REG_CPM_USBCDR          REG32(CPM_BASE + CPM_USBCDR)
+#define REG_CPM_SSICDR          REG32(CPM_BASE + CPM_SSICDR)
+#define REG_CPM_CIMCDR          REG32(CPM_BASE + CPM_CIMCDR)
+#define REG_CPM_PCMCDR          REG32(CPM_BASE + CPM_PCMCDR)
+#define REG_CPM_PCMCDR1         REG32(CPM_BASE + CPM_PCMCDR1)
+#define REG_CPM_MPHYC           REG32(CPM_BASE + CPM_MPHYC)
+#define REG_CPM_INTRCDR         REG32(CPM_BASE + CPM_INTRCDR)
+#define REG_CPM_INTRECDR        REG32(CPM_BASE + CPM_INTRECDR)
+#define REG_CPM_CPSPR           REG32(CPM_BASE + CPM_CPSPR)
+#define REG_CPM_CPSPPR          REG32(CPM_BASE + CPM_CPSPPR)
+#define REG_CPM_USBPCR          REG32(CPM_BASE + CPM_USBPCR)
+#define REG_CPM_USBRDT          REG32(CPM_BASE + CPM_USBRDT)
+#define REG_CPM_USBVBFIL        REG32(CPM_BASE + CPM_USBVBFIL)
+#define REG_CPM_USBPCR1         REG32(CPM_BASE + CPM_USBPCR1)
+#define REG_CPM_CPAPCR          REG32(CPM_BASE + CPM_CPAPCR)
+#define REG_CPM_CPMPCR          REG32(CPM_BASE + CPM_CPMPCR)
+
+#define REG_CPM_LCR             REG32(CPM_BASE + CPM_LCR)
+#define REG_CPM_PSWC0ST         REG32(CPM_BASE + CPM_PSWC0ST)
+#define REG_CPM_PSWC1ST         REG32(CPM_BASE + CPM_PSWC1ST)
+#define REG_CPM_PSWC2ST         REG32(CPM_BASE + CPM_PSWC2ST)
+#define REG_CPM_PSWC3ST         REG32(CPM_BASE + CPM_PSWC3ST)
+#define REG_CPM_CLKGR0          REG32(CPM_BASE + CPM_CLKGR0)
+#define REG_CPM_SRBC            REG32(CPM_BASE + CPM_SRBC)
+#define REG_CPM_SLBC            REG32(CPM_BASE + CPM_SLBC)
+#define REG_CPM_SLPC            REG32(CPM_BASE + CPM_SLPC)
+#define REG_CPM_OPCR            REG32(CPM_BASE + CPM_OPCR)
+#define REG_CPM_RSR             REG32(CPM_BASE + CPM_RSR)
+
+#define _REG_CPM_MSCCDR(n)      REG_CPM_MSC##n##CDR
+#define REG_CPM_MSCCDR(n)       _REG_CPM_MSCCDR(n)
+
+/* CPM read write */
+#define cpm_inl(off)            readl(CPM_BASE + off)
+#define cpm_outl(val,off)       writel(val, CPM_BASE + off)
+#define cpm_test_bit(bit,off)   (cpm_inl(off) & 0x1<<(bit))
+#define cpm_set_bit(bit,off)    (cpm_outl((cpm_inl(off) | 0x1<<(bit)),off))
+#define cpm_clear_bit(bit,off)  (cpm_outl(cpm_inl(off) & ~(0x1 << bit), off))
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _X1000_CPM_H_ */
diff --git a/bsp/x1000/cpu/x1000/x1000_intc.h b/bsp/x1000/cpu/x1000/x1000_intc.h
new file mode 100644
index 0000000000..1644b90777
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/x1000_intc.h
@@ -0,0 +1,120 @@
+/*
+ * File      : x1000_intc.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-02-03     Urey         the first version
+ */
+
+#ifndef _X1000_INTC_H_
+#define _X1000_INTC_H_
+
+
+/*
+ * INTC (Interrupt Controller)
+ */
+#define INTC_ISR(n)             (INTC_BASE + 0x00 + (n) * 0x20)
+#define INTC_IMR(n)             (INTC_BASE + 0x04 + (n) * 0x20)
+#define INTC_IMSR(n)            (INTC_BASE + 0x08 + (n) * 0x20)
+#define INTC_IMCR(n)            (INTC_BASE + 0x0c + (n) * 0x20)
+#define INTC_IPR(n)             (INTC_BASE + 0x10 + (n) * 0x20)
+
+#define REG_INTC_ISR(n)         REG32(INTC_ISR((n)))
+#define REG_INTC_IMR(n)         REG32(INTC_IMR((n)))
+#define REG_INTC_IMSR(n)        REG32(INTC_IMSR((n)))
+#define REG_INTC_IMCR(n)        REG32(INTC_IMCR((n)))
+#define REG_INTC_IPR(n)         REG32(INTC_IPR((n)))
+
+// interrupt controller interrupts
+#define IRQ_DMIC                0
+#define IRQ_AIC0                1
+#define IRQ_RESERVED2           2
+#define IRQ_RESERVED3           3
+#define IRQ_RESERVED4           4
+#define IRQ_RESERVED5           5
+#define IRQ_RESERVED6           6
+#define IRQ_SFC                 7
+#define IRQ_SSI0                8
+#define IRQ_RESERVED9           9
+#define IRQ_PDMA                10
+#define IRQ_PDMAD               11
+#define IRQ_RESERVED12          12
+#define IRQ_RESERVED13          13
+#define IRQ_GPIO3               14
+#define IRQ_GPIO2               15
+#define IRQ_GPIO1               16
+#define IRQ_GPIO0               17
+#define IRQ_RESERVED18          18
+#define IRQ_RESERVED19          19
+#define IRQ_RESERVED20          20
+#define IRQ_OTG                 21
+#define IRQ_RESERVED22          22
+#define IRQ_AES                 23
+#define IRQ_RESERVED24          24
+#define IRQ_TCU2                25
+#define IRQ_TCU1                26
+#define IRQ_TCU0                27
+#define IRQ_RESERVED28          28
+#define IRQ_RESERVED29          29
+#define IRQ_CIM                 30
+#define IRQ_LCD                 31
+#define IRQ_RTC                 32
+#define IRQ_RESERVED33          33
+#define IRQ_RESERVED34          34
+#define IRQ_RESERVED35          35
+#define IRQ_MSC1                36
+#define IRQ_MSC0                37
+#define IRQ_SCC                 38
+#define IRQ_RESERVED39          39
+#define IRQ_PCM0                40
+#define IRQ_RESERVED41          41
+#define IRQ_RESERVED42          42
+#define IRQ_RESERVED43          43
+#define IRQ_HARB2               44
+#define IRQ_RESERVED45          45
+#define IRQ_HARB0               46
+#define IRQ_CPM                 47
+#define IRQ_RESERVED48          48
+#define IRQ_UART2               49
+#define IRQ_UART1               50
+#define IRQ_UART0               51
+#define IRQ_DDR                 52
+#define IRQ_RESERVED53          53
+#define IRQ_EFUSE               54
+#define IRQ_MAC                 55
+#define IRQ_RESERVED56          56
+#define IRQ_RESERVED57          57
+#define IRQ_I2C2                58
+#define IRQ_I2C1                59
+#define IRQ_I2C0                60
+#define IRQ_PDMAM               61
+#define IRQ_JPEG                62
+#define IRQ_RESERVED63          63
+
+#define IRQ_INTC_MAX            63
+
+#ifndef __ASSEMBLY__
+
+#define __intc_unmask_irq(n)    (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
+#define __intc_mask_irq(n)      (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
+#define __intc_ack_irq(n)       (REG_INTC_IPR((n)/32) = (1 << ((n)%32)))        /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _X1000_INTC_H_ */
diff --git a/bsp/x1000/cpu/x1000/x1000_otg_dwc.h b/bsp/x1000/cpu/x1000/x1000_otg_dwc.h
new file mode 100644
index 0000000000..bb77981daa
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/x1000_otg_dwc.h
@@ -0,0 +1,306 @@
+/*
+ * File      : x1000_otg_dwc.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-02-03     Urey         the first version
+ */
+
+#ifndef _X1000_OTG_DWC_H_
+#define _X1000_OTG_DWC_H_
+
+/* Globle Regs define */
+#define GOTG_CTL        (OTG_BASE + 0x00)
+#define GOTG_INTR       (OTG_BASE + 0x04)
+#define GAHB_CFG        (OTG_BASE + 0x08)
+#define GUSB_CFG        (OTG_BASE + 0x0c)
+#define GRST_CTL        (OTG_BASE + 0x10)
+#define GINT_STS        (OTG_BASE + 0x14)
+#define GINT_MASK       (OTG_BASE + 0x18)
+#define GRXSTS_READ     (OTG_BASE + 0x1c)
+#define GRXSTS_POP      (OTG_BASE + 0x20)
+#define GRXFIFO_SIZE        (OTG_BASE + 0x24)
+#define GNPTXFIFO_SIZE      (OTG_BASE + 0x28)
+#define GDTXFIFO_SIZE       (OTG_BASE + 0x104)
+#define GHW_CFG1        (OTG_BASE + 0x44)
+#define GHW_CFG2        (OTG_BASE + 0x48)
+#define GHW_CFG3        (OTG_BASE + 0x4c)
+#define GHW_CFG4        (OTG_BASE + 0x50)
+#define GDFIFO_CFG      (OTG_BASE + 0x5c)
+#define PCGC_CTL        (OTG_BASE + 0xe00)
+
+/* Fifo number 1 ~ 15 */
+#define GDEIP_TXF(n)    (OTG_BASE + (0x104 + ((n-1) * 0x4)))
+
+#define REG_GOTG_CTL        REG32(GOTG_CTL)
+#define REG_GOTG_INTR       REG32(GOTG_INTR)
+#define REG_GAHB_CFG        REG32(GAHB_CFG)
+#define REG_GUSB_CFG        REG32(GUSB_CFG)
+#define REG_GRST_CTL        REG32(GRST_CTL)
+#define REG_GINT_STS        REG32(GINT_STS)
+#define REG_GINT_MASK       REG32(GINT_MASK)
+#define REG_GRXSTS_READ     REG32(GRXSTS_READ)
+#define REG_GRXSTS_POP      REG32(GRXSTS_POP)
+#define REG_GRXFIFO_SIZE    REG32(GRXFIFO_SIZE)
+#define REG_GNPTXFIFO_SIZE  REG32(GNPTXFIFO_SIZE)
+#define REG_GDTXFIFO_SIZE   REG32(GDTXFIFO_SIZE)
+#define REG_GHW_CFG1        REG32(GHW_CFG1)
+#define REG_GHW_CFG2        REG32(GHW_CFG2)
+#define REG_GHW_CFG3        REG32(GHW_CFG3)
+#define REG_GHW_CFG4        REG32(GHW_CFG4)
+#define REG_GDFIFO_CFG      REG32(GDFIFO_CFG)
+#define REG_GDIEP_TXF(n)    REG32(GDEIP_TXF(n))
+#define REG_PCGC_CTL        REG32(PCGC_CTL)
+/* Device Regs define */
+#define EP_FIFO(n)      (OTG_BASE + (n+1)*0x1000) // FiX ME
+#define REG_EP_FIFO(n)      REG32(EP_FIFO(n))
+
+
+#define OTG_DCFG        (OTG_BASE + 0x800)
+#define OTG_DCTL        (OTG_BASE + 0x804)
+#define OTG_DSTS        (OTG_BASE + 0x808)
+#define DIEP_MASK       (OTG_BASE + 0x810)
+#define DOEP_MASK       (OTG_BASE + 0x814)
+#define OTG_DAINT       (OTG_BASE + 0x818)
+#define DAINT_MASK      (OTG_BASE + 0x81c)
+
+#define DIEP_EMPMSK     (OTG_BASE + 0x834)
+
+
+/* It's used in OTG_MULT_PROC_INTRPT = 1
+#define DEACH_INT       (OTG_BASE + 0x838)
+#define DEACH_INTMASK       (OTG_BASE + 0x83c)
+#define DIEP0_INTMASK       (OTG_BASE + 0x840)
+#define DIEP1_INTMASK       (OTG_BASE + 0x844)
+#define DOEP0_INTMASK       (OTG_BASE + 0x880)
+#define DOEP1_INTMASK       (OTG_BASE + 0x884)
+*/
+
+#define DIEP_CTL(n)     (OTG_BASE + (0x900 + (n)*0x20))
+#define DOEP_CTL(n)     (OTG_BASE + (0xb00 + (n)*0x20))
+
+#define DIEP_INT(n)     (OTG_BASE + (0x908 + (n)*0x20))
+#define DOEP_INT(n)     (OTG_BASE + (0xb08 + (n)*0x20))
+
+#define DIEP_SIZE(n)        (OTG_BASE + (0x910 + (n)*0x20))
+#define DOEP_SIZE(n)        (OTG_BASE + (0xb10 + (n)*0x20))
+
+#define DIEP_TXFSTS(n)      (OTG_BASE + (0x918 + (n)*0x20))
+
+#define DIEP_DMA(n)         (OTG_BASE + (0x914 + (n)*0x20))
+#define DOEP_DMA(n)         (OTG_BASE + (0xb14 + (n)*0x20))
+
+#define REG_OTG_DCFG        REG32(OTG_DCFG)
+#define REG_OTG_DCTL        REG32(OTG_DCTL)
+#define REG_OTG_DSTS        REG32(OTG_DSTS)
+#define REG_DIEP_MASK       REG32(DIEP_MASK)
+#define REG_DOEP_MASK       REG32(DOEP_MASK)
+#define REG_OTG_DAINT       REG32(OTG_DAINT)
+#define REG_DAINT_MASK      REG32(DAINT_MASK)
+#define REG_DIEP_EMPMSK     REG32(DIEP_EMPMSK)
+
+#define REG_DIEP_CTL(n)     REG32(DIEP_CTL(n))
+#define REG_DOEP_CTL(n)     REG32(DOEP_CTL(n))
+
+#define REG_DIEP_INT(n)     REG32(DIEP_INT(n))
+#define REG_DOEP_INT(n)     REG32(DOEP_INT(n))
+
+#define REG_DIEP_SIZE(n)    REG32(DIEP_SIZE(n))
+#define REG_DOEP_SIZE(n)    REG32(DOEP_SIZE(n))
+
+#define REG_DIEP_TXFSTS(n)  REG32(DIEP_TXFSTS(n))
+
+#define REG_DIEP_DMA(n)     REG32(DIEP_DMA(n))
+#define REG_DOEP_DMA(n)     REG32(DOEP_DMA(n))
+
+/* Regs macro define */
+/*************************************************/
+#define AHBCFG_TXFE_LVL     BIT7
+#define AHBCFG_DMA_ENA      BIT5
+#define AHBCFG_GLOBLE_INTRMASK  BIT0
+#define USBCFG_FORCE_DEVICE BIT30
+#define USBCFG_TRDTIME_MASK (0xf << 10)
+#define USBCFG_TRDTIME_9    (9 << 10)
+#define USBCFG_TRDTIME_6    (6 << 10)
+
+/* GRSTCTL */
+#define RSTCTL_AHB_IDLE     BIT31
+#define RSTCTL_TXFNUM_ALL   (0x10 << 6)
+#define RSTCTL_TXFIFO_FLUSH BIT5
+#define RSTCTL_RXFIFO_FLUSH BIT4
+#define RSTCTL_INTK_FLUSH   BIT3
+#define RSTCTL_FRMCNT_RST   BIT2
+#define RSTCTL_CORE_RST     BIT0
+
+/* GINTMSK */
+#define GINTMSK_RSUME_DETE  BIT31
+#define GINTMSK_CONID_STSCHG    BIT28
+#define GINTMSK_RESET_DETE  BIT23
+#define GINTMSK_FETCH_SUSPEND   BIT22
+#define GINTMSK_OEP_INTR    BIT19
+#define GINTMSK_IEP_INTR    BIT18
+#define GINTMSK_EP_MISMATCH BIT17
+#define GINTMSK_ENUM_DONE   BIT13
+#define GINTMSK_USB_RESET   BIT12
+#define GINTMSK_USB_SUSPEND BIT11
+#define GINTMSK_USB_EARLYSUSPEND    BIT10
+#define GINTMSK_I2C_INT     BIT9
+#define GINTMSK_ULPK_CKINT  BIT8
+#define GINTMSK_GOUTNAK_EFF BIT7
+#define GINTMSK_GINNAK_EFF  BIT6
+#define GINTMSK_NPTXFIFO_EMPTY  BIT5
+#define GINTMSK_RXFIFO_NEMPTY   BIT4
+#define GINTMSK_START_FRAM  BIT3
+#define GINTMSK_OTG_INTR    BIT2
+#define GINTMSK_MODE_MISMATCH   BIT1
+
+/* GINTSTS */
+#define GINTSTS_RSUME_DETE  BIT31
+#define GINTSTS_CONID_STSCHG    BIT28
+#define GINTSTS_RESET_DETE  BIT23
+#define GINTSTS_FETCH_SUSPEND   BIT22
+#define GINTSTS_OEP_INTR    BIT19
+#define GINTSTS_IEP_INTR    BIT18
+#define GINTSTS_EP_MISMATCH BIT17
+#define GINTSTS_ENUM_DONE   BIT13
+#define GINTSTS_USB_RESET   BIT12
+#define GINTSTS_USB_SUSPEND BIT11
+#define GINTSTS_USB_EARLYSUSPEND    BIT10
+#define GINTSTS_I2C_INT     BIT9
+#define GINTSTS_ULPK_CKINT  BIT8
+#define GINTSTS_GOUTNAK_EFF BIT7
+#define GINTSTS_GINNAK_EFF  BIT6
+#define GINTSTS_NPTXFIFO_EMPTY  BIT5
+#define GINTSTS_RXFIFO_NEMPTY   BIT4
+#define GINTSTS_START_FRAM  BIT3
+#define GINTSTS_OTG_INTR    BIT2
+#define GINTSTS_MODE_MISMATCH   BIT1
+
+/* DCTL */
+#define DCTL_CGOUTNAK       BIT10
+#define DCTL_CLR_GNPINNAK   BIT8
+#define DCTL_SGNPINNAK      BIT7
+#define DCTL_SOFT_DISCONN   BIT1
+#define DCTL_SGOUTNAK       BIT9
+/* DCFG */
+#define DCFG_DEV_ADDR_MASK  (0x7f << 4)
+#define DCFG_DEV_ADDR_BIT   4
+#define DCFG_DEV_DESC_DMA   (1 << 23)
+/* DSTS */
+#define DSTS_ERRATIC_ERROR          BIT3
+#define DSTS_ENUM_SPEED_MASK        (0x3 << 1)
+#define DSTS_ENUM_SPEED_BIT         BIT1
+#define DSTS_ENUM_SPEED_HIGH        (0x0 << 1)
+#define DSTS_ENUM_SPEED_FULL_30OR60 (0x1 << 1)
+#define DSTS_ENUM_SPEED_LOW         (0x2 << 1)
+#define DSTS_ENUM_SPEED_FULL_48     (0x3 << 1)
+
+/* GRXSTSR/GRXSTSP */
+#define GRXSTSP_PKSTS_MASK      (0xf << 17)
+#define GRXSTSP_PKSTS_GOUT_NAK      (0x1 << 17)
+#define GRXSTSP_PKSTS_GOUT_RECV     (0x2 << 17)
+#define GRXSTSP_PKSTS_TX_COMP       (0x3 << 17)
+#define GRXSTSP_PKSTS_SETUP_COMP    (0x4 << 17)
+#define GRXSTSP_PKSTS_SETUP_RECV    (0x6 << 17)
+#define GRXSTSP_BYTE_CNT_MASK       (0x7ff << 4)
+#define GRXSTSP_BYTE_CNT_BIT        4
+#define GRXSTSP_EPNUM_MASK      (0xf)
+#define GRXSTSP_EPNUM_BIT       BIT0
+
+
+/* DIOEPCTL */
+// ep0
+#define DEP_EP0_MAXPKET_SIZE    64
+#define DEP_EP0_MPS_64      (0x0)
+#define DEP_EP0_MPS_32      (0x1)
+#define DEP_EP0_MPS_16      (0x2)
+#define DEP_EP0_MPS_8       (0x3)
+
+#define DEP_ENA_BIT     BIT31
+#define DEP_DISENA_BIT      BIT30
+#define DEP_SET_NAK         BIT27
+#define DEP_CLEAR_NAK       BIT26
+#define DEP_SET_STALL       BIT21
+#define DEP_TYPE_MASK       (0x3 << 18)
+#define DEP_TYPE_CNTL       (0x0 << 18)
+#define DEP_TYPE_ISO        (0x1 << 18)
+#define DEP_TYPE_BULK       (0x2 << 18)
+#define DEP_TYPE_INTR       (0x3 << 18)
+#define USB_ACTIVE_EP       BIT15
+#define DEP_PKTSIZE_MASK    0x7ff
+#define DEP_FS_PKTSIZE      64
+#define DEP_HS_PKTSIZE      512
+
+/* DIOEPINT */
+#define DEP_NYET_INT        BIT14
+#define DEP_NAK_INT     BIT13
+#define DEP_BABBLE_ERR_INT  BIT12
+#define DEP_PKT_DROP_STATUS BIT11
+#define DEP_BNA_INT     BIT9
+#define DEP_TXFIFO_UNDRN    BIT8        // Only for INEP
+#define DEP_OUTPKT_ERR      BIT8        // Only for OUTEP
+#define DEP_TXFIFO_EMPTY    BIT7
+#define DEP_INEP_NAKEFF     BIT6        // Only for INEP
+#define DEP_B2B_SETUP_RECV  BIT6        // Only for OUTEP0
+#define DEP_INTOKEN_EPMISATCH   BIT5        // Only for INEP
+#define DEP_STATUS_PHASE_RECV   BIT5        // Only for OUTEP0
+#define DEP_INTOKEN_RECV_TXFIFO_EMPTY   BIT4    // Only for INEP
+#define DEP_OUTTOKEN_RECV_EPDIS BIT4        // Only for OUTEP
+#define DEP_TIME_OUT        BIT3        // Only for INEP
+#define DEP_SETUP_PHASE_DONE    BIT3        // Only for OUTEP0
+#define DEP_AHB_ERR     BIT2
+#define DEP_EPDIS_INT       BIT1
+#define DEP_XFER_COMP       BIT0        // Used by INEP and OUTEP
+
+/* DOEPSIZ0 */
+#define DOEPSIZE0_SUPCNT_1  (0x1 << 29)
+#define DOEPSIZE0_SUPCNT_2  (0x2 << 29)
+#define DOEPSIZE0_SUPCNT_3  (0x3 << 29)
+#define DOEPSIZE0_PKTCNT_BIT    BIT19
+
+
+#define DEP_RXFIFO_SIZE     1064
+#define DEP_NPTXFIFO_SIZE   1024
+#define DEP_DTXFIFO_SIZE    768
+
+
+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE    0
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR      1
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4     3
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8     5
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16    7
+
+#define DWC_GAHBCFG_EXT_DMA_BURST_1word     0x0
+#define DWC_GAHBCFG_EXT_DMA_BURST_4word     0x1
+#define DWC_GAHBCFG_EXT_DMA_BURST_8word     0x2
+#define DWC_GAHBCFG_EXT_DMA_BURST_16word    0x3
+#define DWC_GAHBCFG_EXT_DMA_BURST_32word    0x4
+#define DWC_GAHBCFG_EXT_DMA_BURST_64word    0x5
+#define DWC_GAHBCFG_EXT_DMA_BURST_128word   0x6
+#define DWC_GAHBCFG_EXT_DMA_BURST_256word   0x7
+
+#define DEP_NUM         2
+
+#if 0
+#define UTMI_PHY_WIDTH      8
+#else
+#define UTMI_PHY_WIDTH      16
+#endif
+
+#endif /* _X1000_OTG_DWC_H_ */
diff --git a/bsp/x1000/cpu/x1000/x1000_slcdc.h b/bsp/x1000/cpu/x1000/x1000_slcdc.h
new file mode 100644
index 0000000000..fab76ffad9
--- /dev/null
+++ b/bsp/x1000/cpu/x1000/x1000_slcdc.h
@@ -0,0 +1,463 @@
+/*
+ * File      : x1000_slcdc.h
+ * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017��3��20��     Urey         the first version
+ */
+#ifndef _X1000_SLCDC_H_
+#define _X1000_SLCDC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*************************************************************************
+ * SLCD (Smart LCD Controller)
+ *************************************************************************/
+#define LCDC0_BASE  LCD_BASE
+
+#define SLCDC_CFG       (LCDC0_BASE + 0xA0)  /* SLCDC Configure Register */
+#define SLCDC_CTRL      (LCDC0_BASE + 0xA4)  /* SLCDC Control Register */
+#define SLCDC_STATE     (LCDC0_BASE + 0xA8)  /* SLCDC Status Register */
+#define SLCDC_DATA      (LCDC0_BASE + 0xAC)  /* SLCDC Data Register */
+
+#define SLCDC_CFG_NEW   (LCDC0_BASE + 0xB8)
+#define SLCDC_WTIME     (LCDC0_BASE + 0xB0)
+#define SLCDC_TAS       (LCDC0_BASE + 0xB4)
+#define SLCDC_SLOW_TIME (LCDC0_BASE + 0xBC)
+
+/* SLCDC Configure Register */
+#define SLCDC_CFG_DWIDTH_BIT            10
+#define SLCDC_CFG_DWIDTH_MASK           (0x7 << SLCDC_CFG_DWIDTH_BIT)
+#define SLCDC_CFG_DWIDTH_18BIT          (0 << SLCDC_CFG_DWIDTH_BIT)
+#define SLCDC_CFG_DWIDTH_16BIT          (1 << SLCDC_CFG_DWIDTH_BIT)
+#define SLCDC_CFG_DWIDTH_8BIT_x3        (2 << SLCDC_CFG_DWIDTH_BIT)
+#define SLCDC_CFG_DWIDTH_8BIT_x2        (3 << SLCDC_CFG_DWIDTH_BIT)
+#define SLCDC_CFG_DWIDTH_8BIT_x1        (4 << SLCDC_CFG_DWIDTH_BIT)
+#define SLCDC_CFG_DWIDTH_24BIT          (5 << SLCDC_CFG_DWIDTH_BIT)
+#define SLCDC_CFG_DWIDTH_9BIT_x2        (7 << SLCDC_CFG_DWIDTH_BIT)
+#define SLCDC_CFG_CWIDTH_BIT            (8)
+#define SLCDC_CFG_CWIDTH_MASK           (0x3 << SLCDC_CFG_CWIDTH_BIT)
+#define SLCDC_CFG_CWIDTH_16BIT          (0 << SLCDC_CFG_CWIDTH_BIT)
+#define SLCDC_CFG_CWIDTH_8BIT           (1 << SLCDC_CFG_CWIDTH_BIT)
+#define SLCDC_CFG_CWIDTH_18BIT          (2 << SLCDC_CFG_CWIDTH_BIT)
+#define SLCDC_CFG_CWIDTH_24BIT          (3 << SLCDC_CFG_CWIDTH_BIT)
+#define SLCDC_CFG_CS_ACTIVE_LOW         (0 << 4)
+#define SLCDC_CFG_CS_ACTIVE_HIGH        (1 << 4)
+#define SLCDC_CFG_RS_CMD_LOW            (0 << 3)
+#define SLCDC_CFG_RS_CMD_HIGH           (1 << 3)
+#define SLCDC_CFG_CLK_ACTIVE_FALLING    (0 << 1)
+#define SLCDC_CFG_CLK_ACTIVE_RISING     (1 << 1)
+#define SLCDC_CFG_TYPE_PARALLEL         (0 << 0)
+#define SLCDC_CFG_TYPE_SERIAL           (1 << 0)
+
+/* SLCD New Configure Register */
+#define SLCDC_NEW_CFG_DWIDTH_BIT        13
+#define SLCDC_NEW_CFG_DWIDTH_MASK       (0x7 << SLCDC_NEW_CFG_DWIDTH_BIT)
+#define SLCDC_NEW_CFG_DWIDTH_8BIT       (0 << SLCDC_NEW_CFG_DWIDTH_BIT)
+#define SLCDC_NEW_CFG_DWIDTH_9BIT       (1 << SLCDC_NEW_CFG_DWIDTH_BIT)
+#define SLCDC_NEW_CFG_DWIDTH_16BIT      (2 << SLCDC_NEW_CFG_DWIDTH_BIT)
+#define SLCDC_NEW_CFG_DWIDTH_18BIT      (3 << SLCDC_NEW_CFG_DWIDTH_BIT)
+#define SLCDC_NEW_CFG_DWIDTH_24BIT      (4 << SLCDC_NEW_CFG_DWIDTH_BIT)
+#define SLCDC_NEW_CFG_6800_MD           (1 << 11)
+#define SLCDC_NEW_CFG_CMD_9BIT          (1 << 10)       /* only use in old slcd */
+#define SLCDC_NEW_CFG_CMD_16BIT         (0 << 10)       /* only use in old slcd */
+#define SLCDC_NEW_CFG_DTIME_BIT         8
+#define SLCDC_NEW_CFG_DTIME_MASK        (0x3 << SLCDC_NEW_CFG_DTIME_BIT)
+#define SLCDC_NEW_CFG_DTIME_ONCE        (0 << SLCDC_NEW_CFG_DTIME_BIT)
+#define SLCDC_NEW_CFG_DTIME_TWICE       (1 << SLCDC_NEW_CFG_DTIME_BIT)
+#define SLCDC_NEW_CFG_DTIME_THREE       (2 << SLCDC_NEW_CFG_DTIME_BIT)
+#define SLCDC_NEW_CFG_CS_HIGH_IDLE      (0 << 5)
+#define SLCDC_NEW_CFG_CS_LOW_IDLE       (1 << 5)
+#define SLCDC_NEW_CFG_RS_CMD_LOW        (0 << 4)
+#define SLCDC_NEW_CFG_RS_CMD_HIGH       (1 << 4)
+#define SLCDC_NEW_CFG_CLK_ACTIVE_FALLING        (0 << 3)
+#define SLCDC_NEW_CFG_CLK_ACTIVE_RISING (1 << 3)
+#define SLCDC_NEW_CFG_DTYPE_PARALLEL    (0 << 2)
+#define SLCDC_NEW_CFG_DTYPE_SERIAL      (1 << 2)
+#define SLCDC_NEW_CFG_CTYPE_PARALLEL    (0 << 1)
+#define SLCDC_NEW_CFG_CTYPE_SERIAL      (1 << 1)
+#define SLCDC_NEW_CFG_FMT_CONV_EN       (1 << 0)
+
+/* SLCD Control Register */
+#define SLCDC_CTRL_TE_INV           	(1 << 9)
+#define SLCDC_CTRL_NOT_USE_TE           (1 << 8)
+#define SLCDC_CTRL_DCSI_SEL             (1 << 7)
+#define SLCDC_CTRL_MIPI_MODE            (1 << 6)
+#define SLCDC_CTRL_NEW_MODE             (1 << 5)
+#define SLCDC_CTRL_FAST_MODE            (1 << 4)
+#define SLCDC_CTRL_GATE_MASK            (1 << 3)
+#define SLCDC_CTRL_DMA_MODE             (1 << 2)
+#define SLCDC_CTRL_DMA_START            (1 << 1)
+#define SLCDC_CTRL_DMA_EN               (1 << 0)
+
+/* SLCD Status Register */
+#define SLCDC_STATE_BUSY                (1 << 0)
+
+/* SLCD Data Register */
+#define SLCDC_DATA_RS_DATA              (0 << 30)
+#define SLCDC_DATA_RS_COMMAND           (1 << 30)
+
+/*************************************************************************
+ * LCDC (LCD Controller)
+ *************************************************************************/
+
+#define LCDC_CFG    (LCDC0_BASE + 0x00)
+#define LCDC_CTRL   (LCDC0_BASE + 0x30)
+#define LCDC_STATE  (LCDC0_BASE + 0x34)
+#define LCDC_OSDC   (LCDC0_BASE + 0x100)
+#define LCDC_OSDCTRL    (LCDC0_BASE + 0x104)
+#define LCDC_OSDS   (LCDC0_BASE + 0x108)
+#define LCDC_BGC0   (LCDC0_BASE + 0x10C)
+#define LCDC_BGC1   (LCDC0_BASE + 0x2C4)
+#define LCDC_KEY0   (LCDC0_BASE + 0x110)
+#define LCDC_KEY1   (LCDC0_BASE + 0x114)
+#define LCDC_ALPHA  (LCDC0_BASE + 0x118)
+#define LCDC_RGBC   (LCDC0_BASE + 0x90)
+#define LCDC_VAT    (LCDC0_BASE + 0x0c)
+#define LCDC_DAH    (LCDC0_BASE + 0x10)
+#define LCDC_DAV    (LCDC0_BASE + 0x14)
+#define LCDC_XYP0   (LCDC0_BASE + 0x120)
+#define LCDC_XYP1   (LCDC0_BASE + 0x124)
+#define LCDC_SIZE0  (LCDC0_BASE + 0x128)
+#define LCDC_SIZE1  (LCDC0_BASE + 0x12C)
+#define LCDC_VSYNC  (LCDC0_BASE + 0x04)
+#define LCDC_HSYNC  (LCDC0_BASE + 0x08)
+#define LCDC_PS     (LCDC0_BASE + 0x18)
+#define LCDC_CLS    (LCDC0_BASE + 0x1c)
+#define LCDC_SPL    (LCDC0_BASE + 0x20)
+#define LCDC_REV    (LCDC0_BASE + 0x24)
+#define LCDC_IID    (LCDC0_BASE + 0x38)
+#define LCDC_DA0    (LCDC0_BASE + 0x40)
+#define LCDC_SA0    (LCDC0_BASE + 0x44)
+#define LCDC_FID0   (LCDC0_BASE + 0x48)
+#define LCDC_CMD0   (LCDC0_BASE + 0x4c)
+#define LCDC_DA1    (LCDC0_BASE + 0x50)
+#define LCDC_SA1    (LCDC0_BASE + 0x54)
+#define LCDC_FID1   (LCDC0_BASE + 0x58)
+#define LCDC_CMD1   (LCDC0_BASE + 0x5c)
+#define LCDC_OFFS0  (LCDC0_BASE + 0x60)
+#define LCDC_PW0    (LCDC0_BASE + 0x64)
+#define LCDC_CNUM0  (LCDC0_BASE + 0x68)
+#define LCDC_DESSIZE0   (LCDC0_BASE + 0x6C)
+#define LCDC_OFFS1  (LCDC0_BASE + 0x70)
+#define LCDC_PW1    (LCDC0_BASE + 0x74)
+#define LCDC_CNUM1  (LCDC0_BASE + 0x78)
+#define LCDC_DESSIZE1   (LCDC0_BASE + 0x7C)
+#define LCDC_PCFG   (LCDC0_BASE + 0x2C0)
+#define LCDC_CPOS1      (0x78)
+#define LCDC_DUAL_CTRL      (0x2c8)
+#define LCDC_ENH_CFG        (0x400)
+#define LCDC_ENH_CSCCFG     (0x404)
+#define LCDC_ENH_LUMACFG    (0x408)
+#define LCDC_ENH_CHROCFG0   (0x40c)
+#define LCDC_ENH_CHROCFG1   (0x410)
+#define LCDC_ENH_DITHERCFG  (0x414)
+#define LCDC_ENH_STATUS     (0x418)
+#define LCDC_ENH_GAMMA      (0x800)
+#define LCDC_ENH_VEE        (0x1000)
+
+/* LCD Configure Register */
+#define LCDC_CFG_LCDPIN_BIT 31
+#define LCDC_CFG_LCDPIN_MASK    (0x1 << LCDC_CFG_LCDPIN_BIT)
+#define LCDC_CFG_LCDPIN_LCD (0x0 << LCDC_CFG_LCDPIN_BIT)
+#define LCDC_CFG_LCDPIN_SLCD    (0x1 << LCDC_CFG_LCDPIN_BIT)
+#define LCDC_CFG_TVEPEH     (1 << 30)
+#define LCDC_CFG_NEWDES     (1 << 28)
+#define LCDC_CFG_PALBP      (1 << 27)
+#define LCDC_CFG_TVEN       (1 << 26)
+#define LCDC_CFG_RECOVER    (1 << 25)
+#define LCDC_CFG_PSM        (1 << 23)
+#define LCDC_CFG_CLSM       (1 << 22)
+#define LCDC_CFG_SPLM       (1 << 21)
+#define LCDC_CFG_REVM       (1 << 20)
+#define LCDC_CFG_HSYNM      (1 << 19)
+#define LCDC_CFG_PCLKM      (1 << 18)
+#define LCDC_CFG_INVDAT     (1 << 17)
+#define LCDC_CFG_SYNDIR_IN  (1 << 16)
+#define LCDC_CFG_PSP        (1 << 15)
+#define LCDC_CFG_CLSP       (1 << 14)
+#define LCDC_CFG_SPLP       (1 << 13)
+#define LCDC_CFG_REVP       (1 << 12)
+#define LCDC_CFG_HSP        (1 << 11)
+#define LCDC_CFG_PCP        (1 << 10)
+#define LCDC_CFG_DEP        (1 << 9)
+#define LCDC_CFG_VSP        (1 << 8)
+#define LCDC_CFG_MODE_TFT_18BIT     (1 << 7)
+#define LCDC_CFG_MODE_TFT_16BIT     (0 << 7)
+#define LCDC_CFG_MODE_TFT_24BIT     (1 << 6)
+#define LCDC_CFG_MODE_BIT   0
+#define LCDC_CFG_MODE_MASK  (0x0f << LCDC_CFG_MODE_BIT)
+#define LCDC_CFG_MODE_GENERIC_TFT   (0 << LCDC_CFG_MODE_BIT)
+#define LCDC_CFG_MODE_SPECIAL_TFT_1 (1 << LCDC_CFG_MODE_BIT)
+#define LCDC_CFG_MODE_SPECIAL_TFT_2 (2 << LCDC_CFG_MODE_BIT)
+#define LCDC_CFG_MODE_SPECIAL_TFT_3 (3 << LCDC_CFG_MODE_BIT)
+#define LCDC_CFG_MODE_NONINTER_CCIR656  (4 << LCDC_CFG_MODE_BIT)
+#define LCDC_CFG_MODE_INTER_CCIR656 (6 << LCDC_CFG_MODE_BIT)
+#define LCDC_CFG_MODE_SERIAL_TFT    (12 << LCDC_CFG_MODE_BIT)
+#define LCDC_CFG_MODE_LCM       (13 << LCDC_CFG_MODE_BIT)
+/* LCD Control Register */
+#define LCDC_CTRL_PINMD     (1 << 31)
+#define LCDC_CTRL_BST_BIT   28
+#define LCDC_CTRL_BST_MASK  (0x7 << LCDC_CTRL_BST_BIT)
+#define LCDC_CTRL_BST_4     (0 << LCDC_CTRL_BST_BIT)
+#define LCDC_CTRL_BST_8     (1 << LCDC_CTRL_BST_BIT)
+#define LCDC_CTRL_BST_16    (2 << LCDC_CTRL_BST_BIT)
+#define LCDC_CTRL_BST_32    (3 << LCDC_CTRL_BST_BIT)
+#define LCDC_CTRL_BST_64    (4 << LCDC_CTRL_BST_BIT)
+#define LCDC_CTRL_RGB565        (0 << 27)
+#define LCDC_CTRL_RGB555        (1 << 27)
+#define LCDC_CTRL_OFUP      (1 << 26)
+#define LCDC_CTRL_PDD_BIT   16
+#define LCDC_CTRL_PDD_MASK  (0xff << LCDC_CTRL_PDD_BIT)
+#define LCDC_CTRL_DACTE     (1 << 14)
+#define LCDC_CTRL_EOFM      (1 << 13)
+#define LCDC_CTRL_SOFM      (1 << 12)
+#define LCDC_CTRL_OFUM      (1 << 11)
+#define LCDC_CTRL_IFUM0     (1 << 10)
+#define LCDC_CTRL_IFUM1     (1 << 9)
+#define LCDC_CTRL_LDDM      (1 << 8)
+#define LCDC_CTRL_QDM       (1 << 7)
+#define LCDC_CTRL_BEDN      (1 << 6)
+#define LCDC_CTRL_PEDN      (1 << 5)
+#define LCDC_CTRL_DIS       (1 << 4)
+#define LCDC_CTRL_ENA       (1 << 3)
+#define LCDC_CTRL_BPP_BIT   0
+#define LCDC_CTRL_BPP_MASK  (0x07 << LCDC_CTRL_BPP_BIT)
+#define LCDC_CTRL_BPP_1     (0 << LCDC_CTRL_BPP_BIT)
+#define LCDC_CTRL_BPP_2     (1 << LCDC_CTRL_BPP_BIT)
+#define LCDC_CTRL_BPP_4     (2 << LCDC_CTRL_BPP_BIT)
+#define LCDC_CTRL_BPP_8     (3 << LCDC_CTRL_BPP_BIT)
+#define LCDC_CTRL_BPP_16    (4 << LCDC_CTRL_BPP_BIT)
+#define LCDC_CTRL_BPP_18_24 (5 << LCDC_CTRL_BPP_BIT)
+#define LCDC_CTRL_BPP_CMPS_24   (6 << LCDC_CTRL_BPP_BIT)
+#define LCDC_CTRL_BPP_30    (7 << LCDC_CTRL_BPP_BIT)
+/* LCD Status Register */
+#define LCDC_STATE_QD       (1 << 7)
+#define LCDC_STATE_EOF      (1 << 5)
+#define LCDC_STATE_SOF      (1 << 4)
+#define LCDC_STATE_OFU      (1 << 3)
+#define LCDC_STATE_IFU0     (1 << 2)
+#define LCDC_STATE_IFU1     (1 << 1)
+#define LCDC_STATE_LDD      (1 << 0)
+/* OSD Configure Register */
+#define LCDC_OSDC_PREMULTI1     (1 << 23)
+#define LCDC_OSDC_COEF_SLE1_BIT     21
+#define LCDC_OSDC_COEF_SLE1_MASK    (0x03 << LCDC_OSDC_COEF_SLE1_BIT)
+#define LCDC_OSDC_COEF_SLE1_0       (0 << LCDC_OSDC_COEF_SLE1_BIT)
+#define LCDC_OSDC_COEF_SLE1_1       (1 << LCDC_OSDC_COEF_SLE1_BIT)
+#define LCDC_OSDC_COEF_SLE1_2       (2 << LCDC_OSDC_COEF_SLE1_BIT)
+#define LCDC_OSDC_COEF_SLE1_3       (3 << LCDC_OSDC_COEF_SLE1_BIT)
+#define LCDC_OSDC_PREMULTI0     (1 << 20)
+#define LCDC_OSDC_COEF_SLE0_BIT     18
+#define LCDC_OSDC_COEF_SLE0_MASK    (0x03 << LCDC_OSDC_COEF_SLE0_BIT)
+#define LCDC_OSDC_COEF_SLE0_0       (0 << LCDC_OSDC_COEF_SLE0_BIT)
+#define LCDC_OSDC_COEF_SLE0_1       (1 << LCDC_OSDC_COEF_SLE0_BIT)
+#define LCDC_OSDC_COEF_SLE0_2       (2 << LCDC_OSDC_COEF_SLE0_BIT)
+#define LCDC_OSDC_COEF_SLE0_3       (3 << LCDC_OSDC_COEF_SLE0_BIT)
+#define LCDC_OSDC_ALPHAMD1      (1 << 17)
+#define LCDC_OSDC_SOFM1     (1 << 15)
+#define LCDC_OSDC_EOFM1     (1 << 14)
+#define LCDC_OSDC_SOFM0     (1 << 11)
+#define LCDC_OSDC_EOFM0     (1 << 10)
+#define LCDC_OSDC_DENDM     (1 << 9)
+#define LCDC_OSDC_F1EN      (1 << 4)
+#define LCDC_OSDC_F0EN      (1 << 3)
+#define LCDC_OSDC_ALPHAEN   (1 << 2)
+#define LCDC_OSDC_ALPHAMD0  (1 << 1)
+#define LCDC_OSDC_OSDEN     (1 << 0)
+/* OSD Controll Register */
+#define LCDC_OSDCTRL_IPU_CLKEN  (1 << 15)
+#define LCDC_OSDCTRL_RGB0_RGB565    (0 << 5)
+#define LCDC_OSDCTRL_RGB0_RGB555    (1 << 5)
+#define LCDC_OSDCTRL_RGB1_RGB565    (0 << 4)
+#define LCDC_OSDCTRL_RGB1_RGB555    (1 << 4)
+#define LCDC_OSDCTRL_BPP_BIT    0
+#define LCDC_OSDCTRL_BPP_MASK   (0x7<<LCDC_OSDCTRL_BPP_BIT)
+#define LCDC_OSDCTRL_BPP_15_16  (4 << LCDC_OSDCTRL_BPP_BIT)
+#define LCDC_OSDCTRL_BPP_18_24  (5 << LCDC_OSDCTRL_BPP_BIT)
+#define LCDC_OSDCTRL_BPP_CMPS_24    (6 << LCDC_OSDCTRL_BPP_BIT)
+#define LCDC_OSDCTRL_BPP_30     (7 << LCDC_OSDCTRL_BPP_BIT)
+/* OSD State Register */
+#define LCDC_OSDS_SOF1      (1 << 15)
+#define LCDC_OSDS_EOF1      (1 << 14)
+#define LCDC_OSDS_SOF0      (1 << 11)
+#define LCDC_OSDS_EOF0      (1 << 10)
+#define LCDC_OSDS_DEND      (1 << 8)
+/* Background 0 or Background 1 Color Register */
+#define LCDC_BGC_RED_OFFSET 16
+#define LCDC_BGC_RED_MASK   (0xFF << LCDC_BGC_RED_OFFSET)
+#define LCDC_BGC_GREEN_OFFSET    8
+#define LCDC_BGC_GREEN_MASK (0xFF << LCDC_BGC_GREEN_OFFSET)
+#define LCDC_BGC_BLUE_OFFSET    0
+#define LCDC_BGC_BLUE_MASK  (0xFF << LCDC_BGC_BLUE_OFFSET)
+/* Foreground 0 or Foreground 1 Color Key Register */
+#define LCDC_KEY_KEYEN      (1 << 31)
+#define LCDC_KEY_KEYMD      (1 << 30)
+#define LCDC_KEY_RED_OFFSET 16
+#define LCDC_KEY_RED_MASK   (0xFF << LCDC_KEY_RED_OFFSET)
+#define LCDC_KEY_GREEN_OFFSET   8
+#define LCDC_KEY_GREEN_MASK (0xFF << LCDC_KEY_GREEN_OFFSET)
+#define LCDC_KEY_BLUE_OFFSET    0
+#define LCDC_KEY_BLUE_MASK  (0xFF << LCDC_KEY_BLUE_OFFSET)
+#define LCDC_KEY_MASK       (LCDC_KEY_RED_MASK | LCDC_KEY_GREEN_MASK\
+/* ALPHA Register */
+#define LCDC_ALPHA1_OFFSET  8
+#define LCDC_ALPHA1_MASK        (0xFF << LCDC_ALPHA1_OFFSET)
+#define LCDC_ALPHA0_OFFSET  0
+#define LCDC_ALPHA0_MASK        (0xFF << LCDC_ALPHA0_OFFSET)
+/* IPU Restart Register */
+#define LCDC_IPUR_IPUREN        (1 << 31)
+#define LCDC_IPUR_IPURMASK  (0xFFFFFF)
+/* RGB Control Register */
+#define LCDC_RGBC_RGBDM     (1 << 15)
+#define LCDC_RGBC_DMM       (1 << 14)
+#define LCDC_RGBC_RGBFMT    (1 << 7)
+#define LCDC_RGBC_ODDRGB_BIT    4
+#define LCDC_RGBC_ODDRGB_MASK   (0x7 << LCDC_RGBC_ODDRGB_BIT)
+#define LCDC_RGBC_ODD_RGB   (0 << LCDC_RGBC_ODDRGB_BIT)
+#define LCDC_RGBC_ODD_RBG   (1 << LCDC_RGBC_ODDRGB_BIT)
+#define LCDC_RGBC_ODD_GRB   (2 << LCDC_RGBC_ODDRGB_BIT)
+#define LCDC_RGBC_ODD_GBR   (3 << LCDC_RGBC_ODDRGB_BIT)
+#define LCDC_RGBC_ODD_BRG   (4 << LCDC_RGBC_ODDRGB_BIT)
+#define LCDC_RGBC_ODD_BGR   (5 << LCDC_RGBC_ODDRGB_BIT)
+#define LCDC_RGBC_EVENRGB_BIT   0
+#define LCDC_RGBC_EVENRGB_MASK  (0x7<<LCDC_RGBC_EVENRGB_BIT)
+#define LCDC_RGBC_EVEN_RGB  0
+#define LCDC_RGBC_EVEN_RBG  1
+#define LCDC_RGBC_EVEN_GRB  2
+#define LCDC_RGBC_EVEN_GBR  3
+#define LCDC_RGBC_EVEN_BRG  4
+#define LCDC_RGBC_EVEN_BGR  5
+/* Vertical Synchronize Register */
+#define LCDC_VSYNC_VPS_BIT  16
+#define LCDC_VSYNC_VPS_MASK (0xfff << LCDC_VSYNC_VPS_BIT)
+#define LCDC_VSYNC_VPE_BIT  0
+#define LCDC_VSYNC_VPE_MASK (0xfff << LCDC_VSYNC_VPE_BIT)
+/* Horizontal Synchronize Register */
+#define LCDC_HSYNC_HPS_BIT  16
+#define LCDC_HSYNC_HPS_MASK (0xfff << LCDC_HSYNC_HPS_BIT)
+#define LCDC_HSYNC_HPE_BIT  0
+#define LCDC_HSYNC_HPE_MASK (0xfff << LCDC_HSYNC_HPE_BIT)
+/* Virtual Area Setting Register */
+#define LCDC_VAT_HT_BIT     16
+#define LCDC_VAT_HT_MASK        (0xfff << LCDC_VAT_HT_BIT)
+#define LCDC_VAT_VT_BIT     0
+#define LCDC_VAT_VT_MASK        (0xfff << LCDC_VAT_VT_BIT)
+/* Display Area Horizontal Start/End Point Register */
+#define LCDC_DAH_HDS_BIT        16
+#define LCDC_DAH_HDS_MASK   (0xfff << LCDC_DAH_HDS_BIT)
+#define LCDC_DAH_HDE_BIT        0
+#define LCDC_DAH_HDE_MASK   (0xfff << LCDC_DAH_HDE_BIT)
+/* Display Area Vertical Start/End Point Register */
+#define LCDC_DAV_VDS_BIT        16
+#define LCDC_DAV_VDS_MASK   (0xfff << LCDC_DAV_VDS_BIT)
+#define LCDC_DAV_VDE_BIT        0
+#define LCDC_DAV_VDE_MASK   (0xfff << LCDC_DAV_VDE_BIT)
+/* Foreground 0 or Foreground 1 XY Position Register */
+#define LCDC_XYP_YPOS_BIT   16
+#define LCDC_XYP_YPOS_MASK  (0xfff << LCDC_XYP_YPOS_BIT)
+#define LCDC_XYP_XPOS_BIT   0
+#define LCDC_XYP_XPOS_MASK  (0xfff << LCDC_XYP_XPOS_BIT)
+/* Foreground 0 or Foreground 1 Size Register */
+#define LCDC_SIZE_HEIGHT_BIT    16
+#define LCDC_SIZE_HEIGHT_MASK   (0xfff << LCDC_SIZE_HEIGHT_BIT)
+#define LCDC_SIZE_WIDTH_BIT 0
+#define LCDC_SIZE_WIDTH_MASK    (0xfff << LCDC_SIZE_WIDTH_BIT)
+/* PS Signal Setting */
+#define LCDC_PS_PSS_BIT     16
+#define LCDC_PS_PSS_MASK        (0xfff << LCDC_PS_PSS_BIT)
+#define LCDC_PS_PSE_BIT     0
+#define LCDC_PS_PSE_MASK        (0xfff << LCDC_PS_PSE_BIT)
+/* CLS Signal Setting */
+#define LCDC_CLS_CLSS_BIT   16
+#define LCDC_CLS_CLSS_MASK  (0xfff << LCDC_CLS_CLSS_BIT)
+#define LCDC_CLS_CLSE_BIT   0
+#define LCDC_CLS_CLSE_MASK  (0xfff << LCDC_CLS_CLSE_BIT)
+/* SPL Signal Setting */
+#define LCDC_SPL_SPLS_BIT   16
+#define LCDC_SPL_SPLS_MASK  (0xfff << LCDC_SPL_SPLS_BIT)
+#define LCDC_SPL_SPLE_BIT   0
+#define LCDC_SPL_SPLE_MASK  (0xfff << LCDC_SPL_SPLE_BIT)
+/* REV Signal Setting */
+#define LCDC_REV_REVS_BIT   16
+#define LCDC_REV_REVS_MASK  (0xfff << LCDC_REV_REVS_BIT)
+/* DMA Command 0 or 1 Register */
+#define LCDC_CMD_SOFINT     (1 << 31)
+#define LCDC_CMD_EOFINT     (1 << 30)
+#define LCDC_CMD_CMD        (1 << 29)
+#define LCDC_CMD_PAL        (1 << 28)
+#define LCDC_CMD_COMPEN     (1 << 27)
+#define LCDC_CMD_FRM_EN     (1 << 26)
+#define LCDC_CMD_FIELD_SEL  (1 << 25)
+#define LCDC_CMD_16X16BLOCK (1 << 24)
+#define LCDC_CMD_LEN_BIT        0
+#define LCDC_CMD_LEN_MASK   (0xffffff << LCDC_CMD_LEN_BIT)
+/* DMA Offsize Register 0,1 */
+#define LCDC_OFFS_BIT       0
+#define LCDC_OFFS_OFFSIZE_MASK  (0xffffff << LCDC_OFFS_BIT)
+/* DMA Page Width Register 0,1 */
+#define LCDC_PW_BIT     0
+#define LCDC_PW_PAGEWIDTH_MASK  (0xffffff << LCDC_PW_BIT)
+/* DMA Command Counter Register 0,1 */
+#define LCDC_CNUM_BIT        0
+#define LCDC_CNUM_CNUM_MASK (0xff << LCDC_CNUM_BIT)
+#define LCDC_CPOS_ALPHAMD1  (1 << 31)
+#define LCDC_CPOS_RGB_RGB565    (0 << 30)
+#define LCDC_CPOS_RGB_RGB555    (1 << 30)
+#define LCDC_CPOS_BPP_BIT   27
+#define LCDC_CPOS_BPP_MASK  (0x07 << LCDC_CPOS_BPP_BIT)
+#define LCDC_CPOS_BPP_16    (4 << LCDC_CPOS_BPP_BIT)
+#define LCDC_CPOS_BPP_18_24 (5 << LCDC_CPOS_BPP_BIT)
+#define LCDC_CPOS_BPP_CMPS_24   (6 << LCDC_CPOS_BPP_BIT)
+#define LCDC_CPOS_BPP_30    (7 << LCDC_CPOS_BPP_BIT)
+#define LCDC_CPOS_PREMULTI  (1 << 26)
+#define LCDC_CPOS_COEF_SLE_BIT  24
+#define LCDC_CPOS_COEF_SLE_MASK (0x3 << LCDC_CPOS_COEF_SLE_BIT)
+#define LCDC_CPOS_COEF_SLE_0    (0 << LCDC_CPOS_COEF_SLE_BIT)
+#define LCDC_CPOS_COEF_SLE_1    (1 << LCDC_CPOS_COEF_SLE_BIT)
+#define LCDC_CPOS_COEF_SLE_2    (2 << LCDC_CPOS_COEF_SLE_BIT)
+#define LCDC_CPOS_COEF_SLE_3    (3 << LCDC_CPOS_COEF_SLE_BIT)
+#define LCDC_CPOS_YPOS_BIT  12
+#define LCDC_CPOS_YPOS_MASK (0xfff << LCDC_CPOS_YPOS_BIT)
+#define LCDC_CPOS_XPOS_BIT  0
+#define LCDC_CPOS_XPOS_MASK (0xfff << LCDC_CPOS_XPOS_BIT)
+/* Foreground 0,1 Size Register */
+#define LCDC_DESSIZE_ALPHA_BIT  24
+#define LCDC_DESSIZE_ALPHA_MASK (0xff << LCDC_DESSIZE_ALPHA_BIT)
+#define LCDC_DESSIZE_HEIGHT_BIT 12
+#define LCDC_DESSIZE_HEIGHT_MASK    (0xfff << LCDC_DESSIZE_HEIGHT_BIT)
+#define LCDC_DESSIZE_WIDTH_BIT  0
+#define LCDC_DESSIZE_WIDTH_MASK (0xfff << LCDC_DESSIZE_WIDTH_BIT)
+/* Priority level threshold configure Register */
+#define LCDC_PCFG_LCDC_PRI_MD   (1 << 31)
+#define LCDC_PCFG_HP_BST_BIT    28
+#define LCDC_PCFG_HP_BST_MASK   (0x7 << LCDC_PCFG_HP_BST_BIT)
+#define LCDC_PCFG_HP_BST_4  (0 << LCDC_PCFG_HP_BST_BIT)
+#define LCDC_PCFG_HP_BST_8  (1 << LCDC_PCFG_HP_BST_BIT)
+#define LCDC_PCFG_HP_BST_16 (2 << LCDC_PCFG_HP_BST_BIT)
+#define LCDC_PCFG_HP_BST_32 (3 << LCDC_PCFG_HP_BST_BIT)
+#define LCDC_PCFG_HP_BST_C16    (5 << LCDC_PCFG_HP_BST_BIT)
+#define LCDC_PCFG_HP_BST_64 (4 << LCDC_PCFG_HP_BST_BIT)
+#define LCDC_PCFG_HP_BST_DIS    (7 << LCDC_PCFG_HP_BST_BIT)
+#define LCDC_PCFG_PCFG2_BIT 18
+#define LCDC_PCFG_PCFG2_MASK    (0x1ff << LCDC_PCFG_PCFG2_BIT)
+#define LCDC_PCFG_PCFG1_BIT 9
+#define LCDC_PCFG_PCFG1_MASK    (0x1ff << LCDC_PCFG_PCFG1_BIT)
+#define LCDC_PCFG_PCFG0_BIT 0
+#define LCDC_PCFG_PCFG0_MASK    (0x1ff << LCDC_PCFG_PCFG0_BIT)
+/* Dual LCDC Channel Control register */
+#define LCDC_DUAL_CTRL_IPU_WR_SEL   (1 << 8)
+#define LCDC_DUAL_CTRL_TFT_SEL      (1 << 6)
+#define LCDC_DUAL_CTRL_PRI_IPU_EN   (1 << 5)
+#define LCDC_DUAL_CTRL_PRI_IPU_BIT  3
+#define LCDC_DUAL_CTRL_PRI_IPU_MASK (0x3 << LCDC_DUAL_CTRL_PRI_IPU_BIT)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _X1000_SLCDC_H_ */
diff --git a/bsp/x1000/rtconfig.py b/bsp/x1000/rtconfig.py
index b935d7bc4e..6d08af4c0a 100644
--- a/bsp/x1000/rtconfig.py
+++ b/bsp/x1000/rtconfig.py
@@ -10,7 +10,7 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM    = 'gcc'
-    EXEC_PATH   = r'E:\work\env\tools\gnu_gcc\mips_gcc\mips-2016.05\bin'
+    EXEC_PATH   = r'/opt/mips-2016.05/bin/'
 else:
     print('Please make sure your toolchains is GNU GCC!')
     exit(0)
diff --git a/libcpu/mips/x1000/SConscript b/libcpu/mips/x1000/SConscript
deleted file mode 100644
index b0ae20ba02..0000000000
--- a/libcpu/mips/x1000/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ''
-
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')
diff --git a/libcpu/mips/x1000/cache.c b/libcpu/mips/x1000/cache.c
deleted file mode 100644
index 5fc9682810..0000000000
--- a/libcpu/mips/x1000/cache.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * File      : cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016/11/02     Urey         the first version
- */
-
-#include <rtthread.h>
-#include <board.h>
-#include <rthw.h>
-
-#include "../common/mips.h"
-
-
-#define CONFIG_SYS_DCACHE_SIZE      16384
-#define CONFIG_SYS_ICACHE_SIZE      16384
-#define CONFIG_SYS_CACHELINE_SIZE   32
-
-#define K0_TO_K1()                      \
-do {                                    \
-    unsigned long __k0_addr;            \
-                                        \
-    __asm__ __volatile__(               \
-    "la %0, 1f\n\t"                     \
-    "or %0, %0, %1\n\t"                 \
-    "jr %0\n\t"                         \
-    "nop\n\t"                           \
-    "1: nop\n"                          \
-    : "=&r"(__k0_addr)                  \
-    : "r" (0x20000000) );               \
-} while(0)
-
-#define K1_TO_K0()                      \
-do {                                    \
-    unsigned long __k0_addr;            \
-    __asm__ __volatile__(               \
-    "nop;nop;nop;nop;nop;nop;nop\n\t"       \
-    "la %0, 1f\n\t"             \
-    "jr %0\n\t"                 \
-    "nop\n\t"                   \
-    "1: nop\n"                  \
-    : "=&r" (__k0_addr));       \
-} while (0)
-
-#define INVALIDATE_BTB()        \
-do {                            \
-    unsigned long tmp;         \
-    __asm__ __volatile__(     \
-    ".set mips32\n\t"           \
-    "mfc0 %0, $16, 7\n\t"       \
-    "nop\n\t"                   \
-    "ori %0, 2\n\t"             \
-    "mtc0 %0, $16, 7\n\t"       \
-    "nop\n\t"                   \
-    ".set mips2\n\t"            \
-    : "=&r" (tmp));             \
-} while (0)
-
-#define __sync()                \
-    __asm__ __volatile__(           \
-        ".set   push\n\t"       \
-        ".set   noreorder\n\t"      \
-        ".set   mips2\n\t"      \
-        "sync\n\t"          \
-        ".set   pop"            \
-        : /* no output */       \
-        : /* no input */        \
-        : "memory")
-
-#if defined(JZ4775) || defined(X1000)
-#define SYNC_WB()               \
-do {                        \
-    __asm__ __volatile__ (          \
-    "sync\n\t"              \
-    "lw $0, %0\n\t"             \
-    :                   \
-    :"m"(*(int *)0xa0000000)        \
-    :"memory");             \
-} while (0)
-#else
-#error "not define sync wb"
-#define SYNC_WB() __asm__ __volatile__ ("sync")
-#endif
-
-
-#undef cache_op
-#define cache_op(op, addr)      \
-    __asm__ __volatile__(       \
-        ".set   push\n"     \
-        ".set   noreorder\n"    \
-        ".set   mips3\n"    \
-        "cache  %0, %1\n"   \
-        ".set   pop\n"      \
-        :           \
-        : "i" (op), "R" (*(unsigned char *)(addr)))
-
-
-void rt_hw_dcache_flush_line(rt_uint32_t addr)
-{
-	cache_op(HIT_WRITEBACK_INV_D, addr);
-	SYNC_WB();
-}
-
-void rt_hw_dcache_flush_range(rt_uint32_t start_addr, rt_uint32_t size)
-{
-    rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE;
-    rt_uint32_t addr = start_addr & ~(lsize - 1);
-    rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1);
-    rt_uint32_t writebuffer;
-
-    for (; addr <= aend; addr += lsize)
-    {
-        cache_op(HIT_WRITEBACK_INV_D, addr);
-    }
-    SYNC_WB();
-}
-
-void rt_hw_dcache_flush_all(void)
-{
-    rt_uint32_t addr;
-
-    for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
-    {
-        cache_op(INDEX_WRITEBACK_INV_D, addr);
-    }
-
-    SYNC_WB();
-}
-
-void rt_hw_dcache_invalidate_range(rt_uint32_t start_addr,rt_uint32_t size)
-{
-    rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE;
-    rt_uint32_t addr = start_addr & ~(lsize - 1);
-    rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1);
-
-    for (; addr <= aend; addr += lsize)
-        cache_op(HIT_INVALIDATE_D, addr);
-}
-
-void rt_hw_dcache_invalidate_all(void)
-{
-    rt_uint32_t addr;
-
-    for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
-    {
-        cache_op(INDEX_STORE_TAG_D, addr);
-    }
-
-    SYNC_WB();
-}
-
-void rt_hw_icache_flush_line(rt_uint32_t addr)
-{
-    cache_op(HIT_INVALIDATE_I, addr);
-}
-
-void rt_hw_icache_flush_all(void)
-{
-    rt_uint32_t addr;
-
-    asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
-    asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
-
-    for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
-    {
-        cache_op(INDEX_STORE_TAG_I, addr);
-    }
-
-    INVALIDATE_BTB();
-}
-
-void rt_hw_icache_invalidate_all(void)
-{
-    rt_uint32_t i;
-
-    K0_TO_K1();
-
-    asm volatile (".set noreorder\n"
-              ".set mips32\n\t"
-              "mtc0\t$0,$28\n\t"
-              "mtc0\t$0,$29\n"
-              ".set mips0\n"
-              ".set reorder\n");
-    for (i = CKSEG0; i < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; i += CONFIG_SYS_CACHELINE_SIZE)
-        cache_op(INDEX_STORE_TAG_I, i);
-
-    K1_TO_K0();
-
-    INVALIDATE_BTB();
-}
-
-
-void rt_hw_flush_cache_all(void)
-{
-    rt_hw_dcache_flush_all();
-    rt_hw_icache_flush_all();
-}
-
-
-
diff --git a/libcpu/mips/x1000/cache.h b/libcpu/mips/x1000/cache.h
deleted file mode 100644
index 0454527d91..0000000000
--- a/libcpu/mips/x1000/cache.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * File      : cache.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016��9��19��     Urey         the first version
- */
-
-#ifndef _X1000_CACHE_H_
-#define _X1000_CACHE_H_
-
-#include "../common/mips.h"
-#include "../common/mips_cache.h"
-
-
-void rt_hw_icache_invalidate_all(void);
-void rt_hw_icache_flush_all(void);
-
-void rt_hw_dcache_flush_all(void);
-void rt_hw_dcache_flush_range(rt_uint32_t addr, rt_uint32_t size);
-void rt_hw_dcache_invalidate_all(void);
-void rt_hw_dcache_invalidate_range(rt_uint32_t addr,rt_uint32_t size);
-
-void rt_hw_flush_cache_all(void);
-#endif /* _X1000_CACHE_H_ */
diff --git a/libcpu/mips/x1000/cpu.c b/libcpu/mips/x1000/cpu.c
deleted file mode 100644
index e1a51b9fe7..0000000000
--- a/libcpu/mips/x1000/cpu.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016��9��8��     Urey         the first version
- */
-
-
-#include <rtthread.h>
-#include <board.h>
-#include <rthw.h>
-
-#include "../common/mips.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	.icache_line_size 	= 32,
-	.icache_size		= 16384,
-
-	.dcache_line_size 	= 32,
-	.dcache_size		= 16384,
-
-	.max_tlb_entries 	= 16,		/* max_tlb_entries */
-};
-
-void rt_hw_tlb_init(void)
-{
-//----------------------------------------------------------------------------------
-//cchappy tlb  0x30000000 to 0xC0000000
-//----------------------------------------------------------------------------------
-	unsigned int pagemask = 0x007fe000;//0x01ffe000; /* 4MB */
-	/* cached D:allow-W V:valid G */
-	unsigned int entrylo0 = (0x30000000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
-	unsigned int entrylo1 = (0x30400000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
-	unsigned int entryhi 	= 0xc0000000; /* kseg2 base */
-	int i;
-	__write_32bit_c0_register($5, 4, 0xa9000000);
-	write_c0_pagemask(pagemask);
-	write_c0_wired(0);
-/* indexed write 32 tlb entry */
-	for(i = 0; i < 32; i++)
-	{
-		asm (
-		".macro _ssnop; sll $0, $0, 1; .endm\n\t"
-		".macro _ehb; sll $0, $0, 3; .endm\n\t"
-		".macro mtc0_tlbw_hazard; _ssnop; _ssnop; _ehb; .endm\n\t"
-		".macro tlbw_use_hazard; _ssnop; _ssnop; _ssnop; _ehb; .endm\n\t"
-		"\n\t"
-		"mtc0 %0, $0\n\t" /* write Index */
-		"tlbw_use_hazard\n\t"
-		"mtc0 %1, $5\n\t" /* write PageMask */
-		"mtc0 %2, $10\n\t" /* write EntryHi */
-		"mtc0 %3, $2\n\t" /* write EntryLo0 */
-		"mtc0 %4, $3\n\t" /* write EntryLo1 */
-		"mtc0_tlbw_hazard\n\t"
-		"tlbwi \n\t" /* TLB indexed write */
-		"tlbw_use_hazard\n\t"
-		: : "Jr" (i), "r" (pagemask), "r" (entryhi),
-		"r" (entrylo0), "r" (entrylo1)
-		);
-		entryhi += 0x0800000; /* 32MB */
-		entrylo0 += (0x0800000 >> 6);
-		entrylo1 += (0x0800000 >> 6);
-	}
-}
-
-void rt_hw_cache_init(void)
-{
-	r4k_cache_flush_all();
-}
-
-/**
- * this function will reset CPU
- *
- */
-RT_WEAK void rt_hw_cpu_reset()
-{
-    /* open the watch-dog */
-    REG_WDT_TCSR  = WDT_TCSR_EXT_EN;
-    REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
-    REG_WDT_TDR   = 0x03;
-    REG_WDT_TCNT  = 0x00;
-    REG_WDT_TCER |= WDT_TCER_TCEN;
-
-    rt_kprintf("reboot system...\n");
-    rt_hw_interrupt_disable();
-    while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-RT_WEAK void rt_hw_cpu_shutdown()
-{
-	rt_kprintf("shutdown...\n");
-	rt_hw_interrupt_disable();
-	while (1);
-}
-
-/**
- * This function finds the first bit set (beginning with the least significant bit)
- * in value and return the index of that bit.
- *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of
- * zero from any of these functions means that the argument was zero.
- *
- * @return return the index of the first bit set. If value is 0, then this function
- * shall return 0.
- */
-RT_WEAK int __rt_ffs(int value)
-{
-    return __builtin_ffs(value);
-}
diff --git a/libcpu/mips/x1000/interrupt.c b/libcpu/mips/x1000/interrupt.c
deleted file mode 100644
index 2a7a42e792..0000000000
--- a/libcpu/mips/x1000/interrupt.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * File      : cpu_intc.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016/09/07     Urey         the first version
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <board.h>
-
-#include "../common/mips.h"
-
-#define INTERRUPTS_MAX	64
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc isr_table[INTERRUPTS_MAX];
-
-static void rt_hw_interrupt_handler(int vector, void *param)
-{
-    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-void rt_hw_interrupt_init(void)
-{
-    rt_int32_t idx;
-
-	clear_c0_status(0xff04); /* clear ERL */
-	set_c0_status(0x0400);   /* set IP2 */
-
-
-    rt_memset(isr_table, 0x00, sizeof(isr_table));
-    for (idx = 0; idx < INTERRUPTS_MAX; idx ++)
-    {
-        isr_table[idx].handler = rt_hw_interrupt_handler;
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest               = 0;
-    rt_interrupt_from_thread        = 0;
-    rt_interrupt_to_thread          = 0;
-    rt_thread_switch_interrupt_flag = 0;
-
-	/* enable cpu interrupt mask */
-	set_c0_status(IE_IRQ0 | IE_IRQ1);
-}
-
-void rt_hw_interrupt_mask(int vector)
-{
-    /* mask interrupt */
-    __intc_mask_irq(vector);
-}
-
-void rt_hw_interrupt_umask(int vector)
-{
-    __intc_unmask_irq(vector);
-}
-
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if(vector < INTERRUPTS_MAX)
-    {
-        old_handler = isr_table[vector].handler;
-
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-        isr_table[vector].handler = handler;
-        isr_table[vector].param = param;
-    }
-
-    return old_handler;
-}
-
-rt_inline int fls(int x)
-{
-    __asm__("clz %0, %1" : "=r" (x) : "r" (x));
-
-    return 32 - x;
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    void *param;
-    rt_isr_handler_t irq_func;
-
-    int irq = 0, group;
-    rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0;
-
-    rt_uint32_t c0_status, c0_cause;
-    rt_uint32_t pending_im;
-
-    /* check os timer */
-    c0_status = read_c0_status();
-    c0_cause = read_c0_cause();
-
-	pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM);
-
-    if (pending_im & CAUSEF_IP3)
-    {
-		extern void rt_hw_ost_handler(void);
-        rt_hw_ost_handler();
-        return;
-    }
-    if (pending_im & CAUSEF_IP2)
-    {
-        intc_ipr0 = REG_INTC_IPR(0);
-        intc_ipr1 = REG_INTC_IPR(1);
-
-        if (intc_ipr0)
-        {
-            irq = fls(intc_ipr0) - 1;
-            intc_ipr0 &= ~(1<<irq);
-        }
-        else if(intc_ipr1)
-        {
-            irq = fls(intc_ipr1) - 1;
-            intc_ipr1 &= ~(1<<irq);
-            irq += 32;
-        }
-        else
-        {
-        	//VPU
-        }
-
-        if (irq >= INTERRUPTS_MAX)
-            rt_kprintf("max interrupt, irq=%d\n", irq);
-
-        /* do interrupt */
-        irq_func = isr_table[irq].handler;
-        param = isr_table[irq].param;
-        (*irq_func)(irq, param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-        isr_table[irq].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-        /* ack interrupt */
-        __intc_ack_irq(irq);
-    }
-
-    if (pending_im & CAUSEF_IP0)
-        rt_kprintf("CAUSEF_IP0\n");
-    if (pending_im & CAUSEF_IP1)
-        rt_kprintf("CAUSEF_IP1\n");
-    if (pending_im & CAUSEF_IP4)
-        rt_kprintf("CAUSEF_IP4\n");
-    if (pending_im & CAUSEF_IP5)
-        rt_kprintf("CAUSEF_IP5\n");
-    if (pending_im & CAUSEF_IP6)
-        rt_kprintf("CAUSEF_IP6\n");
-    if (pending_im & CAUSEF_IP7)
-        rt_kprintf("CAUSEF_IP7\n");
-}
-
-#ifdef RT_USING_INTERRUPT_INFO
-#include <finsh.h>
-int list_irqs(void)
-{
-    int index;
-
-    rt_kprintf("interrupt list:\n");
-    rt_kprintf("----------------\n");
-    rt_kprintf("name     counter\n");
-    for (index = 0; index < INTERRUPTS_MAX; index ++)
-    {
-        if (isr_table[index].handler != rt_hw_interrupt_handler)
-        {
-            rt_kprintf("%-*.*s %d\n", RT_NAME_MAX, RT_NAME_MAX, isr_table[index].name, isr_table[index].counter);
-        }
-    }
-
-    return 0;
-}
-MSH_CMD_EXPORT(list_irqs, list interrupt counter);
-#endif
-
-unsigned int spin_lock_irqsave(void)
-{
-	register unsigned int t;
-	t = read_c0_status();
-	write_c0_status((t & (~1)));
-	return (t);
-}
-
-void spin_unlock_irqrestore(unsigned int val)
-{
-	write_c0_status(val);
-}
diff --git a/libcpu/mips/x1000/mips_backtrace.c b/libcpu/mips/x1000/mips_backtrace.c
deleted file mode 100644
index b8a861bad5..0000000000
--- a/libcpu/mips/x1000/mips_backtrace.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * File      : mips_backtrace.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016��9��11��     Urey         the first version
- */
-
-#include <rtthread.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <stdint.h>
-
-#include "mips.h"
-
-/*********************************************************************************************************
-  ָ���
-*********************************************************************************************************/
-#define ADDUI_SP_INST           0x27bd0000
-#define SW_RA_INST              0xafbf0000
-#define JR_RA_INST              0x03e00008
-
-#define INST_OP_MASK            0xffff0000
-#define INST_OFFSET_MASK        0x0000ffff
-
-#define abs(s) ((s) < 0 ? -(s):(s))
-
-int backtrace_ctx(mips_reg_ctx *ctx)
-{
-	unsigned long *addr;
-	unsigned long *pc, *ra, *sp;
-	size_t ra_offset;
-	size_t stack_size;
-	int depth;
-	int size = 8;
-
-	pc = (unsigned long *)(unsigned long)ctx->CP0EPC;
-	ra = (unsigned long *)(unsigned long)ctx->regs[REG_RA];
-	sp = (unsigned long *)(unsigned long)ctx->regs[REG_SP];
-
-	rt_kprintf("[0x%08x]\n", pc);
-
-	if (size == 1) return 1;
-
-	ra_offset = stack_size = 0;
-
-	for (addr = ra; !ra_offset || !stack_size; --addr)
-	{
-		switch (*addr & INST_OP_MASK) {
-			case ADDUI_SP_INST:
-				stack_size = abs((short)(*addr&INST_OFFSET_MASK));
-				break;
-
-			case SW_RA_INST:
-				ra_offset = (short)(*addr&INST_OFFSET_MASK);
-				break;
-
-			case 0x3c1c0000:
-				goto out_of_loop;
-
-			default:
-				break;
-		}
-	}
-
-out_of_loop:
-	if (ra_offset)  ra = *(unsigned long **)((unsigned long)sp + ra_offset);
-	if (stack_size) sp = (unsigned long *)((unsigned long)sp + stack_size);
-
-	// repeat backwar scanning
-	for (depth = 1; depth < size && ra && ra != (unsigned long *)0xffffffff; ++depth)
-	{
-		rt_kprintf("RA[%2d] : [0x%08x]\n", depth ,ra);
-
-		ra_offset = 0;
-		stack_size = 0;
-
-		for ( addr = ra; !ra_offset || !stack_size; -- addr )
-		{
-			switch( *addr & INST_OP_MASK)
-			{
-				case ADDUI_SP_INST:
-					stack_size = abs((short)(*addr&INST_OFFSET_MASK));
-					break;
-
-				case SW_RA_INST:
-					ra_offset = abs((short)(*addr&INST_OFFSET_MASK));
-					break;
-
-				case 0x3c1c0000:
-					return depth +1;
-
-				default:
-					break;
-			}
-		}
-
-		ra = *(unsigned long **)((unsigned long)sp + ra_offset);
-		sp = (unsigned long *)((unsigned long)sp + stack_size);
-	}
-
-	return depth;
-}
-
-int backtrace(void)
-{
-	unsigned long *addr;
-	unsigned long *ra;
-	unsigned long *sp;
-	int size = 8, depth;
-
-	size_t ra_offset;
-	size_t stack_size;
-
-	// get current $a and $sp
-	__asm__ __volatile__ (
-			" move %0, $ra\n"
-			" move %1, $sp\n"
-			: "=r"(ra), "=r"(sp)
-			);
-
-	// scanning to find the size of hte current stack frame
-	stack_size  = 0;
-
-	for ( addr = (unsigned long *)backtrace; !stack_size; ++addr)
-	{
-		if ((*addr & INST_OP_MASK ) == ADDUI_SP_INST )
-			stack_size = abs((short)(*addr&INST_OFFSET_MASK));
-		else if ( *addr == JR_RA_INST )
-			break;
-	}
-
-	sp = (unsigned long *) (( unsigned long )sp + stack_size);
-
-	// repeat backwar scanning
-	for ( depth = 0; depth < size && ((( unsigned long )ra > KSEG0BASE) && (( unsigned long )ra < KSEG1BASE)); ++ depth )
-	{
-		rt_kprintf("RA[%2d] : [0x%08x]\n", depth, ra);
-		{
-			extern void rt_thread_exit(void);
-			if ((uint32_t)ra == (uint32_t)(rt_thread_exit))
-				return depth;
-		}
-
-		ra_offset = 0;
-		stack_size = 0;
-
-		for ( addr = ra; !ra_offset || !stack_size; -- addr )
-		{
-			switch( *addr & INST_OP_MASK)
-			{
-				case ADDUI_SP_INST:
-					stack_size = abs((short)(*addr&INST_OFFSET_MASK));
-					break;
-
-				case SW_RA_INST:
-					ra_offset = (short)(*addr&INST_OFFSET_MASK);
-					break;
-
-				case 0x3c1c0000:
-					return depth +1;
-
-				default:
-					break;
-			}
-		}
-
-		ra = *(unsigned long **)((unsigned long)sp + ra_offset);
-		sp = (unsigned long*) ((unsigned long)sp+stack_size );
-	}
-
-	return depth;
-}
-
-#include <rtthread.h>
-extern long list_thread(void);
-void assert_hook(const char* ex, const char* func, rt_size_t line)
-{
-	backtrace();
-
-	list_thread();
-	rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex, func, line);
-}
-
-int backtrace_init(void)
-{
-#ifdef RT_DEBUG
-	rt_assert_set_hook(assert_hook);
-#endif
-	return 0;
-}
-INIT_DEVICE_EXPORT(backtrace_init);
diff --git a/libcpu/mips/x1000/mips_cache_gcc.S b/libcpu/mips/x1000/mips_cache_gcc.S
deleted file mode 100644
index cc69cba1a6..0000000000
--- a/libcpu/mips/x1000/mips_cache_gcc.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016-09-19     Urey         first version
- */
-
-#ifndef __ASSEMBLY__
-#define	__ASSEMBLY__
-#endif
-
-#include "../common/mips.h"
-
-    .text
-    .set noreorder
-
-    .globl  cache_init
-    .ent    cache_init
-cache_init:
-    .set    noreorder
-    mtc0    zero, CP0_TAGLO
-    move    t0, a0                  // cache total size
-    move    t1, a1                  // cache line size
-    li      t2, 0x80000000
-    addu    t3, t0, t2
-
-_cache_init_loop:
-    cache   8, 0(t2)                // icache_index_store_tag
-    cache   9, 0(t2)                // dcache_index_store_tag
-    addu    t2, t1
-    bne     t2, t3, _cache_init_loop
-    nop
-
-    mfc0    t0, CP0_CONFIG
-    li      t1, 0x7
-    not     t1
-    and     t0, t0, t1
-    or      t0, 0x3                 // cacheable, noncoherent, write-back, write allocate
-    mtc0    t0, CP0_CONFIG
-
-    jr      ra
-    nop
-
-    .set    reorder
-    .end    cache_init
diff --git a/libcpu/mips/x1000/mips_context_gcc.S b/libcpu/mips/x1000/mips_context_gcc.S
deleted file mode 100644
index 5cb473a72a..0000000000
--- a/libcpu/mips/x1000/mips_context_gcc.S
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016-09-07     Urey         first version
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips.h"
-
-	.global	rt_thread_switch_interrupt_flag
-    .global	rt_interrupt_from_thread
-    .global	rt_interrupt_to_thread
-
-    .section .text,"ax",@progbits
-    .set noreorder
-    .set noat
-
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0 	v0,CP0_STATUS
-    srl 	v1,v0,1
-    sll 	v1,v1,1
-#	and 	v1,v0,0xfffffffe
-    mtc0 	v1,CP0_STATUS
-    jr 		ra
-    nop
-
-LEAF(rt_hw_interrupt_enable)
-    mtc0 	a0,CP0_STATUS
-    jr 		ra
-    nop
-END(rt_hw_interrupt_enable)
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-LEAF(rt_hw_context_switch_to)
-	lw 	sp ,	0(a0)                 	/* switch to the new stack */
-    RESTORE_CONTEXT
-END(rt_hw_context_switch_to)
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-LEAF(rt_hw_context_switch)
-	mtc0    ra, CP0_EPC
-    SAVE_CONTEXT
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-	RESTORE_CONTEXT
-END(rt_hw_context_switch)
-
-LEAF(rt_hw_context_switch_interrupt)
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-END(rt_hw_context_switch_interrupt)
-
diff --git a/libcpu/mips/x1000/mips_excpt.c b/libcpu/mips/x1000/mips_excpt.c
deleted file mode 100644
index 5d2a3dce6d..0000000000
--- a/libcpu/mips/x1000/mips_excpt.c
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * File      : mips_excpt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <stdio.h>
-
-#include "mips.h"
-#include "mips_excpt.h"
-
-extern int backtrace(void);
-int backtrace_ctx(mips_reg_ctx *ctx);
-
-extern long list_thread(void);
-
-const static char *regstr[] = {
-	"$0  zero", "$1  at", "$2  v0", "$3  v1", "$4  a0", "$5  a1", "$6  a2", "$7  a3",
-	"$8  t0", "$9  t1", "$10 t2", "$11 t3", "$12 t4", "$13 t5", "$14 t6", "$15 t7",
-	"$16 s0", "$17 s1", "$18 s2", "$19 s3", "$20 s4", "$21 s5", "$22 s6", "$23 s7",
-	"$24 t8", "$25 t9", "$26 k0", "$27 k1", "$28 gp", "$29 sp", "$30 fp", "$31 ra"
-};
-
-static const char *cause_strings[32] =
-{
-  /*  0 */ "Int",
-  /*  1 */ "TLB Mods",
-  /*  2 */ "TLB Load",
-  /*  3 */ "TLB Store",
-  /*  4 */ "Address Load",
-  /*  5 */ "Address Store",
-  /*  6 */ "Instruction Bus Error",
-  /*  7 */ "Data Bus Error",
-  /*  8 */ "Syscall",
-  /*  9 */ "Breakpoint",
-  /* 10 */ "Reserved Instruction",
-  /* 11 */ "Coprocessor Unuseable",
-  /* 12 */ "Overflow",
-  /* 13 */ "Trap",
-  /* 14 */ "Instruction Virtual Coherency Error",
-  /* 15 */ "FP Exception",
-  /* 16 */ "Reserved 16",
-  /* 17 */ "Reserved 17",
-  /* 18 */ "Reserved 18",
-  /* 19 */ "Reserved 19",
-  /* 20 */ "Reserved 20",
-  /* 21 */ "Reserved 21",
-  /* 22 */ "Reserved 22",
-  /* 23 */ "Watch",
-  /* 24 */ "Reserved 24",
-  /* 25 */ "Reserved 25",
-  /* 26 */ "Reserved 26",
-  /* 27 */ "Reserved 27",
-  /* 28 */ "Reserved 28",
-  /* 29 */ "Reserved 29",
-  /* 30 */ "Reserved 30",
-  /* 31 */ "Data Virtual Coherency Error"
-};
-
-
-/**
- * exception handle table
- */
-exception_func_t sys_exception_handlers[32];
-
-static void mod_handler(mips_reg_ctx *regs)
-{
-    rt_kprintf("tlb modification exception\n");
-    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
-    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
-
-    list_thread();
-
-    printf("-----------------------------------------------------\n");
-    printf("BACKTRACE:\n");
-    backtrace();
-    printf("-----------------------------------------------------\n");
-
-    rt_hw_cpu_shutdown();
-}
-
-static void tlbl_handler(mips_reg_ctx *regs)
-{
-    rt_kprintf("tlb exception: load\n");
-    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
-    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
-
-    list_thread();
-
-    printf("-----------------------------------------------------\n");
-    printf("BACKTRACE:\n");
-    backtrace();
-    printf("-----------------------------------------------------\n");
-
-    rt_hw_cpu_shutdown();
-}
-
-static void tlbs_handler(mips_reg_ctx *regs)
-{
-    rt_kprintf("tlb exception: store\n");
-    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
-    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
-
-    list_thread();
-
-    printf("-----------------------------------------------------\n");
-    printf("BACKTRACE:\n");
-    backtrace();
-    printf("-----------------------------------------------------\n");
-
-    rt_hw_cpu_shutdown();
-}
-
-static void adel_handler(mips_reg_ctx *regs)
-{
-    rt_kprintf("address error exception: load\n");
-    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
-    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
-
-    list_thread();
-    rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, rt_thread_self()->name);
-
-    printf("-----------------------------------------------------\n");
-    printf("BACKTRACE:\n");
-    backtrace();
-    printf("-----------------------------------------------------\n");
-
-    rt_hw_cpu_shutdown();
-}
-
-static void ades_handler(mips_reg_ctx *regs)
-{
-    rt_kprintf("address error exception: store\n");
-    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
-    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
-
-    list_thread();
-
-    printf("-----------------------------------------------------\n");
-    printf("BACKTRACE:\n");
-    backtrace();
-    printf("-----------------------------------------------------\n");
-
-    rt_hw_cpu_shutdown();
-}
-
-static void fpe_handler(mips_reg_ctx *regs)
-{
-    rt_kprintf("floating point exception\n");
-    rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
-    rt_kprintf("                 cause: 0x%08x\n", read_c0_cause());
-
-    list_thread();
-
-    printf("-----------------------------------------------------\n");
-    printf("BACKTRACE:\n");
-    backtrace();
-    printf("-----------------------------------------------------\n");
-
-    rt_hw_cpu_shutdown();
-}
-
-
-static void unhandled_exception_handle(mips_reg_ctx *regs)
-{
-	int i;
-	unsigned int cause = read_c0_cause();
-	unsigned int exc = (cause >> 2) & 0x1f;
-
-	rt_kprintf("exception happens, epc: 0x%08x\n", regs->CP0EPC);
-	rt_kprintf("                 cause: 0x%08x\n", regs->CP0Cause);
-
-	for (i = 0; i < 32; i++)
-	{
-		if (i % 4 == 0)
-			printf("\n");
-		printf("%8s %08x ", regstr[i], regs->regs[i]);
-	}
-	printf("\n");
-
-	list_thread();
-	rt_hw_cpu_shutdown();
-}
-
-static void install_default_exception_handler(void)
-{
-    int i;
-
-    for (i=0; i<sizeof(sys_exception_handlers)/sizeof(sys_exception_handlers[0]); i++)
-        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-
-    sys_exception_handlers[EX_MOD]  = mod_handler;
-    sys_exception_handlers[EX_TLBL] = tlbl_handler;
-    sys_exception_handlers[EX_TLBS] = tlbs_handler;
-    sys_exception_handlers[EX_ADEL] = adel_handler;
-    sys_exception_handlers[EX_ADES] = ades_handler;
-    sys_exception_handlers[EX_FPE]  = fpe_handler;
-}
-
-int rt_hw_exception_init(void)
-{
-    /* install the default exception handler */
-    install_default_exception_handler();
-
-    return RT_EOK;
-}
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > 32) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void mips_exception_handler(mips_reg_ctx *ctx)
-{
-	static int read_epc_count = 0;
-	static int epc_save = 0;
-	int 	i;
-	unsigned int epc;
-
-	//��� read_epc_count>0 ˵�� c_except_handler �ڶ� epc ʱ�����ˣ����� epc ������һ���µ��쳣
-	if (read_epc_count > 0)
-	{
-		printf("ERROR: read epc fail when except handle\n");
-		epc = epc_save;
-		read_epc_count = 0;
-	}
-	else
-	{
-		read_epc_count++;
-		epc_save 	= 0;
-		epc 		= read_c0_epc();
-		epc_save 	= epc;
-
-		if (epc != 0)
-		{
-			printf("-----------------------------------------------------\n");
-			for (i = 0; i < 4; i++)
-			{
-				printf("%08x:\t%08x\n",
-				       (epc - 4 * 4 + i * 4),
-				       *(unsigned int *) ((epc - 4 * 4 + i * 4) | 0xa0000000));
-			}
-			for (i = 0; i < 4; i++)
-			{
-				printf("%08x:\t%08x\n",
-				       (epc + i * 4),
-				       *(unsigned int *) ((epc + i * 4) | 0xa0000000));
-			}
-			printf("-----------------------------------------------------\n");
-		}
-
-		read_epc_count--;
-	}
-
-	printf("-----------------------------------------------------\n");
-	unsigned int cause = read_c0_cause();
-	unsigned int exc = (cause >> 2) & 0x1f;
-	printf("CAUSE=%08x --> %s\n", cause, cause_strings[exc]);
-	printf("EPC=%08x\n", epc);
-
-	for (i = 0; i < 32; i++)
-	{
-		if ((i != 0) && (i % 4 == 0))
-			printf("\n");
-		printf("%8s %08x ", regstr[i], ctx->regs[i]);
-	}
-	printf("\n-----------------------------------------------------\n");
-	printf("%s: \t %8x\n","CP0Status  ",	ctx->CP0Status);
-	printf("%s: \t %8x\n","CP0DataHI  ",	ctx->CP0DataHI);
-	printf("%s: \t %8x\n","CP0DataLO  ",	ctx->CP0DataLO);
-	printf("%s: \t %8x\n","CP0BadVAddr",	ctx->CP0BadVAddr);
-	printf("%s: \t %8x\n","CP0Cause   ",	ctx->CP0Cause);
-	printf("%s: \t %8x\n","CP0EPC     ",	ctx->CP0EPC);
-	printf("-----------------------------------------------------\n");
-
-#if 0
-	switch (exc)
-	{
-	case EX_MOD:
-	 /*  TLB modified                */
-		break;
-
-    case EX_TLBL:                                                       /*  TLB exc(load or ifetch)     */
-    case EX_TLBS:                                                       /*  TLB exception (store)       */
-
-    	break;
-
-    case EX_ADEL:                                                       /*  Address err(load or ifetch) */
-    case EX_ADES:                                                       /*  Address error (store)       */
-
-    	break;
-
-    case EX_IBE:                                                        /*  Instruction Bus Error       */
-    case EX_DBE:                                                        /*  Data Bus Error              */
-
-    	break;
-
-    case EX_SYS:                                                        /*  Syscall                     */
-
-    	break;
-
-    case EX_BP:                                                         /*  Breakpoint                  */
-    case EX_TR:                                                         /*  Trap instruction            */
-
-    	break;
-    case EX_RI:                                                         /*  Reserved instruction        */
-
-    	break;
-    case EX_FPE:                                                        /*  floating point exception    */
-    	break;
-
-    case EX_CPU:                                                        /*  CoProcessor Unusable        */
-
-    	break;
-    case EX_OV:                                                         /*  OVerflow                    */
-    case EX_C2E:                                                        /*  COP2 exception              */
-    case EX_MDMX:                                                       /*  MDMX exception              */
-    case EX_WATCH:                                                      /*  Watch exception             */
-    case EX_MCHECK:                                                     /*  Machine check exception     */
-    case EX_CacheErr:                                                   /*  Cache error caused re-entry */
-                                                                        /*  to Debug Mode               */
-
-    	break;
-    default:
-    	rt_kprintf("Unknow exception: %d\r\n", exc);
-    	break;
-	}
-#else
-	sys_exception_handlers[exc](ctx);
-#endif
-
-	rt_hw_cpu_shutdown();
-}
-
-
-void mips_cache_error_handler (unsigned int  Addr)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	list_thread();
-	rt_hw_cpu_shutdown();
-}
-
-void mips_tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_kprintf("                cause: 0x%08x\n", read_c0_cause());
-	list_thread();
-	rt_kprintf("current thread: %s\n", rt_thread_self()->name);
-	rt_hw_cpu_shutdown();
-}
diff --git a/libcpu/mips/x1000/mips_excpt_gcc.S b/libcpu/mips/x1000/mips_excpt_gcc.S
deleted file mode 100644
index bca6fd1956..0000000000
--- a/libcpu/mips/x1000/mips_excpt_gcc.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016-09-07     Urey         first version
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips.h"
-
-#define _EXC_STKSIZE 	20*1024
-
-;/*********************************************************************************************************
-;  PTE BASE ��ض���
-;*********************************************************************************************************/
-
-#define PTE_BASE_OFFSET                 23
-#define PTE_BASE_SIZE                   9
-#define MIPS32_BADVPN2_SHIFT            2
-
-
-    .section ".text", "ax"
-    .set	noreorder
-
-LEAF(mips_tlb_refill_handlerx)
-    .set    push
-    .set    noat
-    .set    noreorder
-    .set    volatile
-
-    ;/*
-    ; * K1 = CP0_CTXT
-    ; * K0 = K1
-    ; */
-    mfc0    k1 , CP0_CONTEXT                                            ;/*  K1 ���� Context �Ĵ���      */
-    ehb
-    move    k0 , k1                                                     ;/*  K0 ���� Context �Ĵ���      */
-
-    ;/*
-    ; * K1 <<= PTE_BASE_SIZE
-    ; * K1 >>= PTE_BASE_SIZE
-    ; * K1 >>= 4
-    ; * K1 >>= MIPS32_BADVPN2_SHIFT
-    ; * K1 <<= 3
-    ; */
-    sll     k1 , PTE_BASE_SIZE
-    srl     k1 , (PTE_BASE_SIZE + 4 + MIPS32_BADVPN2_SHIFT)             ;/*  K1 Ϊ BAD VPN2              */
-    sll     k1 , (4 - 1)
-
-    ;/*
-    ; * K0 >>= PTE_BASE_OFFSET
-    ; * K0 <<= PTE_BASE_OFFSET
-    ; */
-    srl     k0 , PTE_BASE_OFFSET
-    sll     k0 , PTE_BASE_OFFSET                                        ;/*  K0 Ϊ PTE BASE              */
-
-    ;/*
-    ; * K1 = K1 | K0
-    ; */
-    or      k1 , k1 , k0                                                ;/*  �ϳ�                        */
-
-    ;/*
-    ; * K0 = *K1
-    ; * K1 = *(K1 + 4)
-    ; */
-    lw      k0 , 0(k1)
-    lw      k1 , 4(k1)
-
-    ;/*
-    ; * CP0_TLBLO0 = K0
-    ; * CP0_TLBLO1 = K1
-    ; */
-    mtc0    k0 , CP0_ENTRYLO0                                             ;/*  EntryLo0                    */
-    mtc0    k1 , CP0_ENTRYLO1                                             ;/*  EntryLo1                    */
-    ehb
-
-    tlbwr                                                               ;/*  TLB ����滻                */
-
-    eret                                                                ;/*  �쳣����                    */
-
-    .set    pop
-END(mips_tlb_refill_handlerx)
diff --git a/libcpu/mips/x1000/mips_fp_gcc.S b/libcpu/mips/x1000/mips_fp_gcc.S
deleted file mode 100644
index 303519afe4..0000000000
--- a/libcpu/mips/x1000/mips_fp_gcc.S
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016-09-09     Urey         first version
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#ifdef __mips_hard_float
-
-.module hardfloat
-.module doublefloat
-.set nomips16
-
-#include "../common/mips.h"
-#undef fp
-
-	.global mips_vfp32_init
-LEAF(mips_vfp32_init)
-    mfc0 	t0, CP0_STATUS
-    or      t0 , M_StatusCU1
-    mtc0 	t0, CP0_STATUS
-    jr      ra
-    nop
-END(mips_vfp32_init)
-
-#
-# FUNCTION:	_fpctx_save
-#
-# DESCRIPTION:	save floating point registers to memory starting at a0
-#
-# RETURNS:	int
-#			0:	No context saved
-#			CTX_*:	Type of context stored
-#
-	.global _fpctx_save
-LEAF(_fpctx_save)
-	sw 		zero, LINKCTX_NEXT(a0)
-	mfc0	t0, CP0_STATUS
-	li		t1, M_StatusCU1
-	and		t1, t0, t1
-	bnez	t1, 1f
-	# FP not enabled, bail out
-	move	v0, zero
-	jr		ra
-
-1:	# Save FP32 base
-	li		t1, ST0_FR
-	and		t0, t0, t1
-	cfc1	t2, $31
-	sw		t2, FP32CTX_CSR(a0)
-	sdc1	$f0, FP32CTX_0(a0)
-	sdc1	$f2, FP32CTX_2(a0)
-	sdc1	$f4, FP32CTX_4(a0)
-	sdc1	$f6, FP32CTX_6(a0)
-	sdc1	$f8, FP32CTX_8(a0)
-	sdc1	$f10, FP32CTX_10(a0)
-	sdc1	$f12, FP32CTX_12(a0)
-	sdc1	$f14, FP32CTX_14(a0)
-	sdc1	$f16, FP32CTX_16(a0)
-	sdc1	$f18, FP32CTX_18(a0)
-	sdc1	$f20, FP32CTX_20(a0)
-	sdc1	$f22, FP32CTX_22(a0)
-	sdc1	$f24, FP32CTX_24(a0)
-	sdc1	$f26, FP32CTX_26(a0)
-	sdc1	$f28, FP32CTX_28(a0)
-	sdc1	$f30, FP32CTX_30(a0)
-	bnez	t0, 2f
-	li		v0, LINKCTX_TYPE_FP32
-	sw		v0, LINKCTX_ID(a0)
-	jr		ra
-
-2:	# Save FP64 extra
-.set	push
-.set	fp=64
-	sdc1	$f1, FP64CTX_1(a0)
-	sdc1	$f3, FP64CTX_3(a0)
-	sdc1	$f5, FP64CTX_5(a0)
-	sdc1	$f7, FP64CTX_7(a0)
-	sdc1	$f9, FP64CTX_9(a0)
-	sdc1	$f11, FP64CTX_11(a0)
-	sdc1	$f13, FP64CTX_13(a0)
-	sdc1	$f15, FP64CTX_15(a0)
-	sdc1	$f17, FP64CTX_17(a0)
-	sdc1	$f19, FP64CTX_19(a0)
-	sdc1	$f21, FP64CTX_21(a0)
-	sdc1	$f23, FP64CTX_23(a0)
-	sdc1	$f25, FP64CTX_25(a0)
-	sdc1	$f27, FP64CTX_27(a0)
-	sdc1	$f29, FP64CTX_29(a0)
-	sdc1	$f31, FP64CTX_31(a0)
-.set	pop
-	li	v0, LINKCTX_TYPE_FP64
-	sw	v0, LINKCTX_ID(a0)
-	jr	ra
-END(_fpctx_save)
-
-#
-# FUNCTION:	_fpctx_load
-#
-# DESCRIPTION:	load floating point registers from context chain starting at a0
-#
-# RETURNS:	int
-#			0:	Unrecognised context
-#			CTX_*:	Type of context restored
-#
-	.global _fpctx_load
-LEAF(_fpctx_load)
-	lw	v0, LINKCTX_ID(a0)
-	# Detect type
-	li	t0, LINKCTX_TYPE_FP64
-	li	t1, LINKCTX_TYPE_FP32
-	li	t2, M_StatusCU1
-	beq	v0, t0, 0f
-	beq	v0, t1, 1f
-	# Don't recognise this context, fail
-	move	v0, zero
-	jr	ra
-
-0: 	# FP64 context
-	# Enable CU1
-	di	t3
-	ehb
-	or	t3, t3, t2
-	mtc0	t3, CP0_STATUS
-	ehb
-	# Load FP64 extra
-.set	push
-.set	fp=64
-	ldc1	$f1, FP64CTX_1(a0)
-	ldc1	$f3, FP64CTX_3(a0)
-	ldc1	$f5, FP64CTX_5(a0)
-	ldc1	$f7, FP64CTX_7(a0)
-	ldc1	$f9, FP64CTX_9(a0)
-	ldc1	$f11, FP64CTX_11(a0)
-	ldc1	$f13, FP64CTX_13(a0)
-	ldc1	$f15, FP64CTX_15(a0)
-	ldc1	$f17, FP64CTX_17(a0)
-	ldc1	$f19, FP64CTX_19(a0)
-	ldc1	$f21, FP64CTX_21(a0)
-	ldc1	$f23, FP64CTX_23(a0)
-	ldc1	$f25, FP64CTX_25(a0)
-	ldc1	$f27, FP64CTX_27(a0)
-	ldc1	$f29, FP64CTX_29(a0)
-	ldc1	$f31, FP64CTX_31(a0)
-.set	pop
-1: 	# FP32 context
-	# Enable CU1
-	di	t3
-	ehb
-	or	t3, t3, t2
-	mtc0	t3, CP0_STATUS
-	ehb
-	# Load FP32 base
-	lw	t1, FP32CTX_CSR(a0)
-	ctc1	t1, $31
-	ldc1	$f0, FP32CTX_0(a0)
-	ldc1	$f2, FP32CTX_2(a0)
-	ldc1	$f4, FP32CTX_4(a0)
-	ldc1	$f6, FP32CTX_6(a0)
-	ldc1	$f8, FP32CTX_8(a0)
-	ldc1	$f10, FP32CTX_10(a0)
-	ldc1	$f12, FP32CTX_12(a0)
-	ldc1	$f14, FP32CTX_14(a0)
-	ldc1	$f16, FP32CTX_16(a0)
-	ldc1	$f18, FP32CTX_18(a0)
-	ldc1	$f20, FP32CTX_20(a0)
-	ldc1	$f22, FP32CTX_22(a0)
-	ldc1	$f24, FP32CTX_24(a0)
-	ldc1	$f26, FP32CTX_26(a0)
-	ldc1	$f28, FP32CTX_28(a0)
-	ldc1	$f30, FP32CTX_30(a0)
-	# Return CTX_FP32/64
-	jr	ra
-END(_fpctx_load)
-
-#endif
diff --git a/libcpu/mips/x1000/stack.c b/libcpu/mips/x1000/stack.c
deleted file mode 100644
index 0043ea2a21..0000000000
--- a/libcpu/mips/x1000/stack.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016��9��8��     Urey         the first version
- */
-
-#include <rtthread.h>
-
-#include "../common/mips.h"
-
-register U32 $GP __asm__ ("$28");
-
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-    static rt_uint32_t wSR=0;
-    static rt_uint32_t wGP;
-
-	mips_reg_ctx	*regCtx;
-	mips_arg_ctx	*argCtx;
-	rt_uint32_t i;
-
-	if (wSR == 0)
-	{
-		wSR = read_c0_status();
-		wSR &= 0xfffffffe;
-		wSR |= 0x0403;
-
-		wGP = $GP;
-	}
-
-	if ((rt_uint32_t) stack_addr & 0x7)
-	{
-		stack_addr = (rt_uint8_t *)((rt_uint32_t)stack_addr - 4);
-	}
-
-	argCtx = (mips_arg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx));
-	regCtx = (mips_reg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx) - sizeof(mips_reg_ctx));
-
-	for (i = 0; i < 4; ++i)
-	{
-		argCtx->args[i] = i;
-	}
-
-	//����ͨ�üĴ���
-	for (i = 0; i < 32; ++i)
-	{
-		regCtx->regs[i] = i;
-	}
-
-	regCtx->regs[REG_SP] = (rt_uint32_t)stack_addr;
-	regCtx->regs[REG_A0] = (rt_uint32_t)parameter;
-	regCtx->regs[REG_GP] = (rt_uint32_t)wGP;
-	regCtx->regs[REG_FP] = (rt_uint32_t)0x0;
-	regCtx->regs[REG_RA] = (rt_uint32_t)texit;
-
-    regCtx->CP0DataLO	= 0x00;
-    regCtx->CP0DataHI	= 0x00;
-    regCtx->CP0Cause	= read_c0_cause();
-    regCtx->CP0Status	= wSR;
-    regCtx->CP0EPC		= (rt_uint32_t)tentry;
-    regCtx->CP0BadVAddr= 0x00;
-
-	return (rt_uint8_t *)(regCtx);
-}
diff --git a/libcpu/mips/x1000/startup_gcc.S b/libcpu/mips/x1000/startup_gcc.S
deleted file mode 100644
index c5112614fc..0000000000
--- a/libcpu/mips/x1000/startup_gcc.S
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016-09-07     Urey         first version
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips.h"
-
-#define IRQ_STACK_SIZE		0x2000
-#define EXC_STACK_SIZE		0x2000
-
-
-	.section ".bss"
-    ALIGN(4)
-irq_stack_low:
-	.space IRQ_STACK_SIZE
-irq_stack_top:
-	.space 8
-
-	    ALIGN(4)
-exc_stack_low:
-	.space EXC_STACK_SIZE
-exc_stack_top:
-	.space 8
-
-#define SYSTEM_STACK		0x80003fe8
-
-;/*********************************************************************************************************
-;  ���
-;*********************************************************************************************************/
-	.global	rtthread_startup
-	.global 	mips_vfp32_init
-
-	.global	_start
-    .section ".start", "ax"
-    .set noreorder
-_start:
-    .set    noreorder
-    la      ra, _start
-
-    li      t1, 0x00800000
-    mtc0    t1, CP0_CAUSE
-
-    /* init cp0 registers. */
-    li      t0, 0x1000FC00 /* BEV = 0 and mask all interrupt */
-    mtc0    t0, CP0_STATUS
-
-#ifdef __mips_hard_float
-	jal 	mips_vfp32_init
-	nop
-#endif
-
-    /* setup stack pointer */
-    li      sp, SYSTEM_STACK
-    la      gp, _gp
-
-_cache_init:
-    /* init caches, assumes a 4way * 128set * 32byte I/D cache */
-    mtc0    zero, CP0_TAGLO  /* TAGLO reg */
-    mtc0    zero, CP0_TAGHI  /* TAGHI reg */
-    li      t0, 3            /* enable cache for kseg0 accesses */
-    mtc0    t0, CP0_CONFIG   /* CONFIG reg */
-    la      t0, 0x80000000   /* an idx op should use an unmappable address */
-    ori     t1, t0, 0x4000   /* 16kB cache */
-
-_cache_loop:
-    cache   0x8, 0(t0)       /* index store icache tag */
-    cache   0x9, 0(t0)       /* index store dcache tag */
-    bne     t0, t1, _cache_loop
-    addiu   t0, t0, 0x20     /* 32 bytes per cache line */
-    nop
-
-    /* invalidate BTB */
-    mfc0    t0, CP0_CONFIG
-    nop
-    ori     t0, 2
-    mtc0    t0, CP0_CONFIG
-    nop
-
-
-    /* jump to RT-Thread RTOS */
-    jal     rtthread_startup
-    nop
-
-    /* restart, never die */
-    j       _start
-    nop
-    .set    reorder
-
-
-;/*********************************************************************************************************
-;  �쳣������
-;*********************************************************************************************************/
-    /* 0x0 - TLB refill handler */
-    .section .vectors.1, "ax", %progbits
-    j       mips_tlb_refill_entry
-    nop
-
-    /* 0x100 - Cache error handler */
-    .section .vectors.2, "ax", %progbits
-    j       mips_cache_error_entry
-    nop
-
-    /* 0x180 - Exception/Interrupt handler */
-    .section .vectors.3, "ax", %progbits
-    j       mips_exception_entry
-    nop
-
-    /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-    .section .vectors.4, "ax", %progbits
-    j       mips_interrupt_entry
-    nop
-    .section .vectors, "ax", %progbits
-
-	.global	mips_exception_handler
-//	.global	mips_syscall
-LEAF(mips_exception_entry)
-    .set    push
-    .set    noat
-    .set    noreorder
-    .set    volatile
-
-	mfc0	k0, C0_CAUSE
-	andi	k0, k0, 0x7c
-	beq		zero, k0, except_do_intr
-	nop
-
-	andi	k0,(0x08 << 2)
-	beq		zero,k0,except_do
-	nop
-except_do_intr:
-	la		k0,mips_interrupt_entry
-	jr		k0
-	nop
-except_do_syscall:
-//	la		k0,mips_syscall
-//	jr		k0
-	nop
-except_do:
-	//save sp
-	move	k0,sp
-	//la		sp,	exc_stack_top
-	subu 	sp, sp, CONTEXT_SIZE
-	//save context
-	sw	$0, (4*0)(sp);
-	sw	$1, (4*1)(sp);
-	sw	$2, (4*2)(sp);
-	sw	$3, (4*3)(sp);
-	sw	$4, (4*4)(sp);
-	sw	$5, (4*5)(sp);
-	sw	$6, (4*6)(sp);
-	sw	$7, (4*7)(sp);
-	sw	$8, (4*8)(sp);
-	sw	$9, (4*9)(sp);
-	sw	$10, (4*10)(sp);
-	sw	$11, (4*11)(sp);
-	sw	$12, (4*12)(sp);
-	sw	$13, (4*13)(sp);
-	sw	$14, (4*14)(sp);
-	sw	$15, (4*15)(sp);
-	sw	$16, (4*16)(sp);
-	sw	$17, (4*17)(sp);
-	sw	$18, (4*18)(sp);
-	sw	$19, (4*19)(sp);
-	sw	$20, (4*20)(sp);
-	sw	$21, (4*21)(sp);
-	sw	$22, (4*22)(sp);
-	sw	$23, (4*23)(sp);
-	sw	$24, (4*24)(sp);
-	sw	$25, (4*25)(sp);
-	sw	$26, (4*26)(sp);
-	sw	$27, (4*27)(sp);
-	sw	$28, (4*28)(sp);
-	sw	k0,  (4*29)(sp);	//old sp
-	sw	$30, (4*30)(sp);
-	sw	$31, (4*31)(sp);
-
-	/* STATUS CAUSE EPC.... */
-	mfc0	$2, CP0_STATUS
-	sw		$2, STK_OFFSET_SR(sp)
-
-	mfc0	$2, CP0_CAUSE
-	sw		$2, STK_OFFSET_CAUSE(sp)
-
-	mfc0	$2, CP0_BADVADDR
-	sw		$2, STK_OFFSET_BADVADDR(sp)
-
-	MFC0	$2, CP0_EPC
-	sw		$2, STK_OFFSET_EPC(sp)
-
-	mfhi	$2
-	sw		$2, STK_OFFSET_HI(sp)
-
-	mflo	$2
-	sw		$2, STK_OFFSET_LO(sp)
-
-	move	a0, sp
-	la		k0,	mips_exception_handler
-	j		k0
-	nop
-
-	//
-
-	.set	pop
-END(mips_exception_entry)
-
-	.global	mips_tlb_refill_handler
-LEAF(mips_tlb_refill_entry)
-    .set    push
-    .set    noat
-    .set    noreorder
-    .set    volatile
-
-	la		k0,mips_tlb_refill_handler
-	jr		k0
-
-	nop
-    eret
-	nop
-
-	.set	pop
-END(mips_tlb_refill_entry)
-
-	.global	mips_cache_error_handler
-LEAF(mips_cache_error_entry)
-    .set    push
-    .set    noat
-    .set    noreorder
-    .set    volatile
-
-	la		k0,mips_cache_error_handler
-	jr		k0
-    nop
-    eret
-	nop
-
-	.set	pop
-END(mips_cache_error_entry)
-
-
-
-.global	rt_interrupt_dispatch
-.global	rt_interrupt_enter
-.global	rt_interrupt_leave
-LEAF(mips_interrupt_entry)
-    .set    push
-    .set    noat
-    .set    noreorder
-    .set    volatile
-
-    //mfc0	k0,CP0_EPC
-    SAVE_CONTEXT
-
-    mfc0    t0, CP0_CAUSE
-    mfc0    t1, CP0_STATUS
-    and     t0, t1
-
-    andi    t0, 0xff00
-    beqz    t0, spurious_interrupt
-    nop
-
-	/* let k0 keep the current context sp */
-	move 	k0, sp
-
-	/* switch to kernel stack */
-	la 		sp, irq_stack_top
-	jal 	rt_interrupt_enter
-	nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-    nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-spurious_interrupt:
-    RESTORE_CONTEXT
-
-	.set	pop
-END(mips_interrupt_entry)
diff --git a/libcpu/mips/x1000/x1000.h b/libcpu/mips/x1000/x1000.h
deleted file mode 100644
index aa18297395..0000000000
--- a/libcpu/mips/x1000/x1000.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * File      : x1000.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-11-19     Urey         the first version
- */
-
-#ifndef __X1000_H__
-#define __X1000_H__
-
-#include "../common/mips.h"
-
-#ifndef __ASSEMBLY__
-
-#define cache_unroll(base,op)               \
-    __asm__ __volatile__("                  \
-        .set noreorder;                     \
-        .set mips3;                         \
-        cache %1, (%0);                     \
-        .set mips0;                         \
-        .set reorder"                       \
-        :                                   \
-        : "r" (base),                       \
-          "i" (op));
-
-/* cpu pipeline flush */
-static inline void jz_sync(void)
-{
-    __asm__ volatile ("sync");
-}
-
-static inline void writeb(u8 value, u32 address)
-{
-    *((volatile u8 *) address) = value;
-}
-static inline void writew( u16 value, u32 address)
-{
-    *((volatile u16 *) address) = value;
-}
-static inline void writel(u32 value, u32 address)
-{
-    *((volatile u32 *) address) = value;
-}
-
-static inline u8 readb(u32 address)
-{
-    return *((volatile u8 *)address);
-}
-
-static inline u16 readw(u32 address)
-{
-    return *((volatile u16 *)address);
-}
-
-static inline u32 readl(u32 address)
-{
-    return *((volatile u32 *)address);
-}
-
-static inline void jz_writeb(u32 address, u8 value)
-{
-    *((volatile u8 *)address) = value;
-}
-
-static inline void jz_writew(u32 address, u16 value)
-{
-    *((volatile u16 *)address) = value;
-}
-
-static inline void jz_writel(u32 address, u32 value)
-{
-    *((volatile u32 *)address) = value;
-}
-
-static inline u8 jz_readb(u32 address)
-{
-    return *((volatile u8 *)address);
-}
-
-static inline u16 jz_readw(u32 address)
-{
-    return *((volatile u16 *)address);
-}
-
-static inline u32 jz_readl(u32 address)
-{
-    return *((volatile u32 *)address);
-}
-
-#define BIT(n)          (0x01u << (n))
-#define BIT0            (0x01u <<  0)
-#define BIT1            (0x01u <<  1)
-#define BIT2            (0x01u <<  2)
-#define BIT3            (0x01u <<  3)
-#define BIT4            (0x01u <<  4)
-#define BIT5            (0x01u <<  5)
-#define BIT6            (0x01u <<  6)
-#define BIT7            (0x01u <<  7)
-#define BIT8            (0x01u <<  8)
-#define BIT9            (0x01u <<  9)
-#define BIT10           (0x01u << 10)
-#define BIT11           (0x01u << 11)
-#define BIT12           (0x01u << 12)
-#define BIT13           (0x01u << 13)
-#define BIT14           (0x01u << 14)
-#define BIT15           (0x01u << 15)
-#define BIT16           (0x01u << 16)
-#define BIT17           (0x01u << 17)
-#define BIT18           (0x01u << 18)
-#define BIT19           (0x01u << 19)
-#define BIT20           (0x01u << 20)
-#define BIT21           (0x01u << 21)
-#define BIT22           (0x01u << 22)
-#define BIT23           (0x01u << 23)
-#define BIT24           (0x01u << 24)
-#define BIT25           (0x01u << 25)
-#define BIT26           (0x01u << 26)
-#define BIT27           (0x01u << 27)
-#define BIT28           (0x01u << 28)
-#define BIT29           (0x01u << 29)
-#define BIT30           (0x01u << 30)
-#define BIT31           (0x01u << 31)
-
-/* Generate the bit field mask from msb to lsb */
-#define BITS_H2L(msb, lsb)  ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
-
-
-/* Get the bit field value from the data which is read from the register */
-#define get_bf_value(data, lsb, mask)  (((data) & (mask)) >> (lsb))
-
-#endif /* !ASSEMBLY */
-
-
-//----------------------------------------------------------------------
-// Register Definitions
-//
-/* AHB0 BUS Devices Base */
-#define HARB0_BASE  0xB3000000
-#define EMC_BASE    0xB3010000
-#define DDRC_BASE   0xB3020000
-#define MDMAC_BASE  0xB3030000
-#define LCD_BASE    0xB3050000
-#define TVE_BASE    0xB3050000
-#define SLCD_BASE   0xB3050000
-#define CIM_BASE    0xB3060000
-#define IPU_BASE    0xB3080000
-/* AHB1 BUS Devices Base */
-#define HARB1_BASE  0xB3200000
-#define DMAGP0_BASE 0xB3210000
-#define DMAGP1_BASE 0xB3220000
-#define DMAGP2_BASE 0xB3230000
-#define MC_BASE     0xB3250000
-#define ME_BASE     0xB3260000
-#define DEBLK_BASE  0xB3270000
-#define IDCT_BASE   0xB3280000
-#define CABAC_BASE  0xB3290000
-#define TCSM0_BASE  0xB32B0000
-#define TCSM1_BASE  0xB32C0000
-#define SRAM_BASE   0xB32D0000
-/* AHB2 BUS Devices Base */
-#define HARB2_BASE  0xB3400000
-#define NEMC_BASE   0xB3410000
-#define DMAC_BASE   0xB3420000
-#define UHC_BASE    0xB3430000
-//#define UDC_BASE    0xB3440000
-#define SFC_BASE	 0xB3440000
-#define GPS_BASE    0xB3480000
-#define ETHC_BASE   0xB34B0000
-#define BCH_BASE    0xB34D0000
-#define MSC0_BASE   0xB3450000
-#define MSC1_BASE   0xB3460000
-#define MSC2_BASE   0xB3470000
-#define OTG_BASE    0xb3500000
-
-/* APB BUS Devices Base */
-#define CPM_BASE    0xB0000000
-#define INTC_BASE   0xB0001000
-#define TCU_BASE    0xB0002000
-#define WDT_BASE    0xB0002000
-#define OST_BASE    0xB2000000      /* OS Timer */
-#define RTC_BASE    0xB0003000
-#define GPIO_BASE   0xB0010000
-#define AIC_BASE    0xB0020000
-#define DMIC_BASE   0xB0021000
-#define ICDC_BASE   0xB0020000
-#define UART0_BASE  0xB0030000
-#define UART1_BASE  0xB0031000
-#define UART2_BASE  0xB0032000
-#define SCC_BASE    0xB0040000
-#define SSI0_BASE   0xB0043000
-#define SSI1_BASE   0xB0044000
-#define SSI2_BASE   0xB0045000
-#define I2C0_BASE   0xB0050000
-#define I2C1_BASE   0xB0051000
-#define I2C2_BASE   0xB0052000
-#define PS2_BASE    0xB0060000
-#define SADC_BASE   0xB0070000
-#define OWI_BASE    0xB0072000
-#define TSSI_BASE   0xB0073000
-
-/* NAND CHIP Base Address*/
-#define NEMC_CS1_IOBASE 0Xbb000000
-#define NEMC_CS2_IOBASE 0Xba000000
-#define NEMC_CS3_IOBASE 0Xb9000000
-#define NEMC_CS4_IOBASE 0Xb8000000
-#define NEMC_CS5_IOBASE 0Xb7000000
-#define NEMC_CS6_IOBASE 0Xb6000000
-
-/*********************************************************************************************************
-**   WDT
-*********************************************************************************************************/
-#define WDT_TDR         (0x00)
-#define WDT_TCER        (0x04)
-#define WDT_TCNT        (0x08)
-#define WDT_TCSR        (0x0C)
-
-#define REG_WDT_TDR     REG16(WDT_BASE + WDT_TDR)
-#define REG_WDT_TCER    REG8(WDT_BASE + WDT_TCER)
-#define REG_WDT_TCNT    REG16(WDT_BASE + WDT_TCNT)
-#define REG_WDT_TCSR    REG16(WDT_BASE + WDT_TCSR)
-
-#define WDT_TSCR_WDTSC          (1 << 16)
-
-#define WDT_TCSR_PRESCALE_1         (0 << 3)
-#define WDT_TCSR_PRESCALE_4         (1 << 3)
-#define WDT_TCSR_PRESCALE_16        (2 << 3)
-#define WDT_TCSR_PRESCALE_64        (3 << 3)
-#define WDT_TCSR_PRESCALE_256       (4 << 3)
-#define WDT_TCSR_PRESCALE_1024      (5 << 3)
-
-#define WDT_TCSR_EXT_EN         (1 << 2)
-#define WDT_TCSR_RTC_EN         (1 << 1)
-#define WDT_TCSR_PCK_EN         (1 << 0)
-
-#define WDT_TCER_TCEN           (1 << 0)
-
-/* RTC Reg */
-#define RTC_RTCCR		(0x00)	/* rw, 32, 0x00000081 */
-#define RTC_RTCSR		(0x04)	/* rw, 32, 0x???????? */
-#define RTC_RTCSAR		(0x08)	/* rw, 32, 0x???????? */
-#define RTC_RTCGR		(0x0c)	/* rw, 32, 0x0??????? */
-#define RTC_HCR			(0x20)  /* rw, 32, 0x00000000 */
-#define RTC_HWFCR		(0x24)  /* rw, 32, 0x0000???0 */
-#define RTC_HRCR		(0x28)  /* rw, 32, 0x00000??0 */
-#define RTC_HWCR		(0x2c)  /* rw, 32, 0x00000008 */
-#define RTC_HWRSR		(0x30)  /* rw, 32, 0x00000000 */
-#define RTC_HSPR		(0x34)  /* rw, 32, 0x???????? */
-#define RTC_WENR		(0x3c)  /* rw, 32, 0x00000000 */
-#define RTC_CKPCR		(0x40)  /* rw, 32, 0x00000010 */
-#define RTC_OWIPCR		(0x44)  /* rw, 32, 0x00000010 */
-#define RTC_PWRONCR		(0x48)  /* rw, 32, 0x???????? */
-
-#define RTCCR_WRDY				BIT(7)
-#define WENR_WEN                BIT(31)
-
-#define RECOVERY_SIGNATURE	(0x001a1a)
-#define REBOOT_SIGNATURE	(0x003535)
-#define UNMSAK_SIGNATURE	(0x7c0000)//do not use these bits
-
-
-#include "x1000_cpm.h"
-#include "x1000_intc.h"
-#include "x1000_otg_dwc.h"
-#include "x1000_aic.h"
-#include "x1000_slcdc.h"
-
-#endif /* _JZ_M150_H_ */
diff --git a/libcpu/mips/x1000/x1000_aic.h b/libcpu/mips/x1000/x1000_aic.h
deleted file mode 100644
index ed2c8e6f73..0000000000
--- a/libcpu/mips/x1000/x1000_aic.h
+++ /dev/null
@@ -1,794 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    x1000_aic.h
-  * @author  Urey
-  * @version V1.0.0
-  * @date    2017��2��20��
-  * @brief   TODO
-  ******************************************************************************         
-**/ 
-
-
-#ifndef _X1000_AIC_H_
-#define _X1000_AIC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define AIC_FR      (AIC_BASE + 0x00)
-#define AIC_CR      (AIC_BASE + 0x04)
-#define AIC_ACCR1   (AIC_BASE + 0x08)
-#define AIC_ACCR2   (AIC_BASE + 0x0c)
-#define AIC_I2SCR   (AIC_BASE + 0x10)
-#define AIC_SR      (AIC_BASE + 0x14)
-#define AIC_ACSR    (AIC_BASE + 0x18)
-#define AIC_I2SSR   (AIC_BASE + 0x1c)
-#define AIC_ACCAR   (AIC_BASE + 0x20)
-#define AIC_ACCDR   (AIC_BASE + 0x24)
-#define AIC_ACSAR   (AIC_BASE + 0x28)
-#define AIC_ACSDR   (AIC_BASE + 0x2c)
-#define AIC_I2SDIV  (AIC_BASE + 0x30)
-#define AIC_DR      (AIC_BASE + 0x34)
-
-#define SPDIF_ENA   (AIC_BASE + 0x80)
-#define SPDIF_CTRL  (AIC_BASE + 0x84)
-#define SPDIF_STATE (AIC_BASE + 0x88)
-#define SPDIF_CFG1  (AIC_BASE + 0x8c)
-#define SPDIF_CFG2  (AIC_BASE + 0x90)
-#define SPDIF_FIFO  (AIC_BASE + 0x94)
-
-#define ICDC_CKCFG  (AIC_BASE + 0xa0)
-#define ICDC_RGADW  (AIC_BASE + 0xa4)
-#define ICDC_RGDATA (AIC_BASE + 0xa8)
-
-
-/* AIC_FR definition */
-#define AIC_FR_RFTH_LSB     24
-#define AIC_FR_RFTH(x)  ( ( (x)/2 - 1 ) << AIC_FR_RFTH_LSB)     // 2, 4, ..., 32
-#define AIC_FR_RFTH_MASK    BITS_H2L(27, AIC_FR_RFTH_LSB)
-
-#define AIC_FR_TFTH_LSB     16
-#define AIC_FR_TFTH(x)      ( ( (x)/2 ) << AIC_FR_TFTH_LSB)     // 2, 4, ..., 32
-#define AIC_FR_TFTH_MASK    BITS_H2L(20, AIC_FR_TFTH_LSB)
-
-/* new@4770 */
-#define AIC_FR_IBCKD        BIT10
-
-/* new@4770 */
-#define AIC_FR_ISYNCD       BIT9
-
-/* new@4770 */
-#define IC_FR_DMODE     BIT8
-
-#define AIC_FR_LSMP     BIT6
-#define AIC_FR_ICDC     BIT5
-#define AIC_FR_AUSEL        BIT4
-#define AIC_FR_RST      BIT3
-#define AIC_FR_BCKD     BIT2
-#define AIC_FR_SYNCD        BIT1
-#define AIC_FR_ENB      BIT0
-
-
-/* AIC_CR definition */
-#define AIC_CR_PACK16       BIT28
-
-#define AIC_CR_CHANNEL_LSB  24
-#define AIC_CR_CHANNEL_MASK BITS_H2L(26, 24)
-#define AIC_CR_CHANNEL_MONO   (0x0 << AIC_CR_CHANNEL_LSB)
-#define AIC_CR_CHANNEL_STEREO (0x1 << AIC_CR_CHANNEL_LSB)
-#define AIC_CR_CHANNEL_4CHNL  (0x3 << AIC_CR_CHANNEL_LSB)
-#define AIC_CR_CHANNEL_6CHNL  (0x5 << AIC_CR_CHANNEL_LSB)
-#define AIC_CR_CHANNEL_8CHNL  (0x7 << AIC_CR_CHANNEL_LSB)
-
-#define AIC_CR_OSS_LSB      19
-#define AIC_CR_OSS_MASK     BITS_H2L(21, AIC_CR_OSS_LSB)
-#define AIC_CR_OSS(n)       (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB)  /* n = 8, 16, 18, 20, 24 */
-
-#define AIC_CR_ISS_LSB      16
-#define AIC_CR_ISS_MASK     BITS_H2L(18, AIC_CR_ISS_LSB)
-#define AIC_CR_ISS(n)       (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB)  /* n = 8, 16, 18, 20, 24 */
-
-#define AIC_CR_RDMS     BIT15
-#define AIC_CR_TDMS     BIT14
-#define AIC_CR_M2S      BIT11
-#define AIC_CR_ENDSW        BIT10
-#define AIC_CR_AVSTSU       BIT9
-#define AIC_CR_TFLUSH       BIT8
-#define AIC_CR_RFLUSH       BIT7
-#define AIC_CR_EROR     BIT6
-#define AIC_CR_ETUR     BIT5
-#define AIC_CR_ERFS     BIT4
-#define AIC_CR_ETFS     BIT3
-#define AIC_CR_ENLBF        BIT2
-#define AIC_CR_ERPL     BIT1
-#define AIC_CR_EREC     BIT0
-
-/* AIC controller AC-link control register 1(ACCR1) */
-#define AIC_ACCR1_RS_LSB    16
-#define AIC_ACCR1_RS_MASK   BITS_H2L(25, AIC_ACCR1_RS_LSB)
-#define AIC_ACCR1_RS_SLOT(n)    ((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB)  /* n = 3 .. 12 */
-
-#define AIC_ACCR1_XS_LSB    0
-#define AIC_ACCR1_XS_MASK   BITS_H2L(9, AIC_ACCR1_XS_LSB)
-#define AIC_ACCR1_XS_SLOT(n)    ((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB)  /* n = 3 .. 12 */
-
-/* AIC controller AC-link control register 2 (ACCR2) */
-#define AIC_ACCR2_ERSTO     BIT18
-#define AIC_ACCR2_ESADR     BIT17
-#define AIC_ACCR2_ECADT     BIT16
-#define AIC_ACCR2_SO        BIT3
-#define AIC_ACCR2_SR        BIT2
-#define AIC_ACCR2_SS        BIT1
-#define AIC_ACCR2_SA        BIT0
-
-/* AIC controller i2s/msb-justified control register (I2SCR) */
-#define AIC_I2SCR_RFIRST    BIT17
-#define AIC_I2SCR_SWLH      BIT16
-#define AIC_I2SCR_ISTPBK    BIT13
-#define AIC_I2SCR_STPBK     BIT12
-#define AIC_I2SCR_ESCLK     BIT4
-#define AIC_I2SCR_AMSL      BIT0
-
-/* AIC controller FIFO status register (AICSR) */
-#define AIC_SR_RFL_LSB      24
-#define AIC_SR_RFL_MASK     BITS_H2L(29, AIC_SR_RFL_LSB)
-
-#define AIC_SR_TFL_LSB      8
-#define AIC_SR_TFL_MASK     BITS_H2L(13, AIC_SR_TFL_LSB)
-
-#define AIC_SR_ROR      BIT6
-#define AIC_SR_TUR      BIT5
-#define AIC_SR_RFS      BIT4
-#define AIC_SR_TFS      BIT3
-
-/* AIC controller AC-link status register (ACSR) */
-#define AIC_ACSR_SLTERR     BIT21
-#define AIC_ACSR_CRDY       BIT20
-#define AIC_ACSR_CLPM       BIT19
-#define AIC_ACSR_RSTO       BIT18
-#define AIC_ACSR_SADR       BIT17
-#define AIC_ACSR_CADT       BIT16
-
-/* AIC controller I2S/MSB-justified status register (I2SSR) */
-#define AIC_I2SSR_CHBSY     BIT5
-#define AIC_I2SSR_TBSY      BIT4
-#define AIC_I2SSR_RBSY      BIT3
-#define AIC_I2SSR_BSY       BIT2
-
-/* AIC controller AC97 codec command address register (ACCAR) */
-#define AIC_ACCAR_CAR_LSB   0
-#define AIC_ACCAR_CAR_MASK  BITS_H2L(19, AIC_ACCAR_CAR_LSB)
-
-
-/* AIC controller AC97 codec command data register (ACCDR) */
-#define AIC_ACCDR_CDR_LSB   0
-#define AIC_ACCDR_CDR_MASK  BITS_H2L(19, AIC_ACCDR_CDR_LSB)
-
-/* AC97 read and write macro based on ACCAR and ACCDR */
-#define AC97_READ_CMD       BIT19
-#define AC97_WRITE_CMD      (BIT19 & ~BIT19)
-
-#define AC97_INDEX_LSB      12
-#define AC97_INDEX_MASK     BITS_H2L(18, AC97_INDEX_LSB)
-
-#define AC97_DATA_LSB       4
-#define AC97_DATA_MASK      BITS_H2L(19, AC97_DATA_LSB)
-
-/* AIC controller AC97 codec status address register (ACSAR) */
-#define AIC_ACSAR_SAR_LSB   0
-#define AIC_ACSAR_SAR_MASK  BITS_H2L(19, AIC_ACSAR_SAR_LSB)
-
-/* AIC controller AC97 codec status data register (ACSDR) */
-#define AIC_ACSDR_SDR_LSB   0
-#define AIC_ACSDR_SDR_MASK  BITS_H2L(19, AIC_ACSDR_SDR_LSB)
-
-/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */
-#define AIC_I2SDIV_IDIV_LSB 16
-#define AIC_I2SDIV_IDIV_MASK    BITS_H2L(24, AIC_I2SDIV_IDIV_LSB)
-#define AIC_I2SDIV_DIV_LSB  0
-#define AIC_I2SDIV_DIV_MASK BITS_H2L(8, AIC_I2SDIV_DIV_LSB)
-
-/* SPDIF enable register (SPDIF_ENA) */
-#define SPDIF_ENA_SPEN      BIT0
-
-/* SPDIF control register (SPDIF_CTRL) */
-#define SPDIF_CTRL_DMAEN        BIT15
-#define SPDIF_CTRL_DTYPE        BIT14
-#define SPDIF_CTRL_SIGN         BIT13
-#define SPDIF_CTRL_INVALID      BIT12
-#define SPDIF_CTRL_RST          BIT11
-#define SPDIF_CTRL_SPDIFI2S     BIT10
-#define SPDIF_CTRL_MTRIG        BIT1
-#define SPDIF_CTRL_MFFUR        BIT0
-
-/* SPDIF state register (SPDIF_STAT) */
-#define SPDIF_STAT_BUSY     BIT7
-#define SPDIF_STAT_FTRIG    BIT1
-#define SPDIF_STAT_FUR      BIT0
-
-#define SPDIF_STAT_FLVL_LSB 8
-#define SPDIF_STAT_FLVL_MASK    BITS_H2L(14, SPDIF_STAT_FLVL_LSB)
-
-/* SPDIF configure 1 register (SPDIF_CFG1) */
-#define SPDIF_CFG1_INITLVL  BIT17
-#define SPDIF_CFG1_ZROVLD   BIT16
-
-#define SPDIF_CFG1_TRIG_LSB 12
-#define SPDIF_CFG1_TRIG_MASK    BITS_H2L(13, SPDIF_CFG1_TRIG_LSB)
-#define SPDIF_CFG1_TRIG(n)  (((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB) /* n = 4, 8, 16, 32 */
-
-#define SPDIF_CFG1_SRCNUM_LSB   8
-#define SPDIF_CFG1_SRCNUM_MASK  BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB)
-
-#define SPDIF_CFG1_CH1NUM_LSB   4
-#define SPDIF_CFG1_CH1NUM_MASK  BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB)
-
-#define SPDIF_CFG1_CH2NUM_LSB   0
-#define SPDIF_CFG1_CH2NUM_MASK  BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB)
-
-/* SPDIF configure 2 register (SPDIF_CFG2) */
-#define SPDIF_CFG2_MAXWL    BIT18
-#define SPDIF_CFG2_PRE      BIT3
-#define SPDIF_CFG2_COPYN    BIT2
-#define SPDIF_CFG2_AUDION   BIT1
-#define SPDIF_CFG2_CONPRO   BIT0
-
-#define SPDIF_CFG2_FS_LSB   26
-#define SPDIF_CFG2_FS_MASK  BITS_H2L(29, SPDIF_CFG2_FS_LSB)
-
-#define SPDIF_CFG2_ORGFRQ_LSB   22
-#define SPDIF_CFG2_ORGFRQ_MASK  BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB)
-
-#define SPDIF_CFG2_SAMWL_LSB    19
-#define SPDIF_CFG2_SAMWL_MASK   BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB)
-
-#define SPDIF_CFG2_CLKACU_LSB   16
-#define SPDIF_CFG2_CLKACU_MASK  BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB)
-
-#define SPDIF_CFG2_CATCODE_LSB  8
-#define SPDIF_CFG2_CATCODE_MASK BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB)
-
-#define SPDIF_CFG2_CHMD_LSB 6
-#define SPDIF_CFG2_CHMD_MASK    BITS_H2L(7, SPDIF_CFG2_CHMD_LSB)
-
-/* ICDC internal register access control register(RGADW) */
-#define ICDC_RGADW_RGWR     BIT16
-
-#define ICDC_RGADW_RGADDR_LSB   8
-#define ICDC_RGADW_RGADDR_MASK  BITS_H2L(14, ICDC_RGADW_RGADDR_LSB)
-
-#define ICDC_RGADW_RGDIN_LSB    0
-#define ICDC_RGADW_RGDIN_MASK   BITS_H2L(7, ICDC_RGADW_RGDIN_LSB)
-
-
-/* ICDC internal register data output register (RGDATA)*/
-#define ICDC_RGDATA_IRQ     BIT8
-
-#define ICDC_RGDATA_RGDOUT_LSB  0
-#define ICDC_RGDATA_RGDOUT_MASK BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB)
-
-
-#ifndef __MIPS_ASSEMBLER
-
-
-#define REG_AIC_FR      REG32(AIC_FR)
-#define REG_AIC0_FR     REG32(AIC0_FR)
-#define REG_AIC_CR      REG32(AIC_CR)
-#define REG_AIC_ACCR1       REG32(AIC_ACCR1)
-#define REG_AIC_ACCR2       REG32(AIC_ACCR2)
-#define REG_AIC_I2SCR       REG32(AIC_I2SCR)
-#define REG_AIC_SR      REG32(AIC_SR)
-#define REG_AIC_ACSR        REG32(AIC_ACSR)
-#define REG_AIC_I2SSR       REG32(AIC_I2SSR)
-#define REG_AIC_ACCAR       REG32(AIC_ACCAR)
-#define REG_AIC_ACCDR       REG32(AIC_ACCDR)
-#define REG_AIC_ACSAR       REG32(AIC_ACSAR)
-#define REG_AIC_ACSDR       REG32(AIC_ACSDR)
-#define REG_AIC_I2SDIV      REG32(AIC_I2SDIV)
-#define REG_AIC_DR      REG32(AIC_DR)
-
-#define REG_SPDIF_ENA       REG32(SPDIF_ENA)
-#define REG_SPDIF_CTRL      REG32(SPDIF_CTRL)
-#define REG_SPDIF_STATE     REG32(SPDIF_STATE)
-#define REG_SPDIF_CFG1      REG32(SPDIF_CFG1)
-#define REG_SPDIF_CFG2      REG32(SPDIF_CFG2)
-#define REG_SPDIF_FIFO      REG32(SPDIF_FIFO)
-
-#define REG_ICDC_RGADW      REG32(ICDC_RGADW)
-#define REG_ICDC_RGDATA     REG32(ICDC_RGDATA)
-
-#if 0
-#define __aic_enable()      ( REG_AIC_FR |= AIC_FR_ENB )
-#define __aic_disable()     ( REG_AIC_FR &= ~AIC_FR_ENB )
-
-#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
-#define __aic_select_i2s()  ( REG_AIC_FR |= AIC_FR_AUSEL )
-
-#define __aic_play_zero()   ( REG_AIC_FR &= ~AIC_FR_LSMP )
-#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
-
-#define __i2s_as_master()   ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
-#define __i2s_as_slave()    ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
-
-#define jz_aic_ibck_in      (CLRREG32(AIC_FR, AIC_FR_IBCKD))
-#define jz_aic_ibck_out     (SETREG32(AIC_FR, AIC_FR_IBCKD))
-
-#define jz_aic_isync_in     (CLRREG32(AIC_FR, AIC_FR_ISYNCD))
-#define jz_aic_isync_out    (SETREG32(AIC_FR, AIC_FR_ISYNCD))
-
-#define jz_aic_enable_dmode (SETREG32(AIC_FR, AIC_FR_DMODE))
-#define jz_aic_disable_dmode    (CLRREG32(AIC_FR, AIC_FR_DMODE))
-
-#define __aic_reset_status()          ( REG_AIC_FR & AIC_FR_RST )
-
-#define __aic_reset()                                   \
-do {                                                    \
-        REG_AIC_FR |= AIC_FR_RST;                       \
-} while(0)
-
-
-#define __aic_set_transmit_trigger(n)           \
-do {                            \
-    REG_AIC_FR &= ~AIC_FR_TFTH_MASK;        \
-    REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB);     \
-} while(0)
-
-#define __aic_set_receive_trigger(n)            \
-do {                            \
-    REG_AIC_FR &= ~AIC_FR_RFTH_MASK;        \
-    REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB);     \
-} while(0)
-
-#define __aic_enable_oldstyle()
-#define __aic_enable_newstyle()
-#define __aic_enable_pack16()   ( REG_AIC_CR |= AIC_CR_PACK16 )
-#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16)
-
-#define jz_aic_set_channel(n)                       \
-    do {                                \
-        switch((n)) {                       \
-        case 1:                         \
-        case 2:                         \
-        case 4:                         \
-        case 6:                         \
-        case 8:                         \
-            CLRREG32(AIC_CR, AIC_CR_CHANNEL_MASK);      \
-            SETREG32(AIC_CR, ((((n) - 1) << 24) & AIC_CR_CHANNEL_MASK)); \
-            break;                      \
-        default:                        \
-            printk("invalid aic channel, must be 1, 2, 4, 6, or 8\n"); \
-            break;                      \
-        }                           \
-    } while(0)
-
-/* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */
-#define __aic_out_channel_select(n)                    \
-do {                                                   \
-    REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK;            \
-        REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB );                \
-} while(0)
-
-#define __aic_enable_record()   ( REG_AIC_CR |= AIC_CR_EREC )
-#define __aic_disable_record()  ( REG_AIC_CR &= ~AIC_CR_EREC )
-#define __aic_enable_replay()   ( REG_AIC_CR |= AIC_CR_ERPL )
-#define __aic_disable_replay()  ( REG_AIC_CR &= ~AIC_CR_ERPL )
-#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
-#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
-
-#define __aic_flush_tfifo() ( REG_AIC_CR |= AIC_CR_TFLUSH )
-#define __aic_unflush_tfifo()   ( REG_AIC_CR &= ~AIC_CR_TFLUSH )
-#define __aic_flush_rfifo() ( REG_AIC_CR |= AIC_CR_RFLUSH )
-#define __aic_unflush_rfifo()   ( REG_AIC_CR &= ~AIC_CR_RFLUSH )
-
-#define __aic_enable_transmit_intr() \
-  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
-#define __aic_disable_transmit_intr() \
-  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
-#define __aic_enable_receive_intr() \
-  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
-#define __aic_disable_receive_intr() \
-  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
-
-#define __aic_enable_transmit_dma()  ( REG_AIC_CR |= AIC_CR_TDMS )
-#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
-#define __aic_enable_receive_dma()   ( REG_AIC_CR |= AIC_CR_RDMS )
-#define __aic_disable_receive_dma()  ( REG_AIC_CR &= ~AIC_CR_RDMS )
-
-#define __aic_enable_mono2stereo()   ( REG_AIC_CR |= AIC_CR_M2S )
-#define __aic_disable_mono2stereo()  ( REG_AIC_CR &= ~AIC_CR_M2S )
-#define __aic_enable_byteswap()      ( REG_AIC_CR |= AIC_CR_ENDSW )
-#define __aic_disable_byteswap()     ( REG_AIC_CR &= ~AIC_CR_ENDSW )
-#define __aic_enable_unsignadj()     ( REG_AIC_CR |= AIC_CR_AVSTSU )
-#define __aic_disable_unsignadj()    ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
-
-#define AC97_PCM_XS_L_FRONT     AIC_ACCR1_XS_SLOT(3)
-#define AC97_PCM_XS_R_FRONT     AIC_ACCR1_XS_SLOT(4)
-#define AC97_PCM_XS_CENTER      AIC_ACCR1_XS_SLOT(6)
-#define AC97_PCM_XS_L_SURR      AIC_ACCR1_XS_SLOT(7)
-#define AC97_PCM_XS_R_SURR      AIC_ACCR1_XS_SLOT(8)
-#define AC97_PCM_XS_LFE         AIC_ACCR1_XS_SLOT(9)
-
-#define AC97_PCM_RS_L_FRONT     AIC_ACCR1_RS_SLOT(3)
-#define AC97_PCM_RS_R_FRONT     AIC_ACCR1_RS_SLOT(4)
-#define AC97_PCM_RS_CENTER      AIC_ACCR1_RS_SLOT(6)
-#define AC97_PCM_RS_L_SURR      AIC_ACCR1_RS_SLOT(7)
-#define AC97_PCM_RS_R_SURR      AIC_ACCR1_RS_SLOT(8)
-#define AC97_PCM_RS_LFE         AIC_ACCR1_RS_SLOT(9)
-
-#define __ac97_set_xs_none()    ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
-#define __ac97_set_xs_mono()                        \
-do {                                    \
-    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;                \
-    REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT;               \
-} while(0)
-#define __ac97_set_xs_stereo()                      \
-do {                                    \
-    REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;                \
-    REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
-} while(0)
-
-/* In fact, only stereo is support now. */
-#define __ac97_set_rs_none()    ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
-#define __ac97_set_rs_mono()                        \
-do {                                    \
-    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;                \
-    REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT;               \
-} while(0)
-#define __ac97_set_rs_stereo()                      \
-do {                                    \
-    REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;                \
-    REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
-} while(0)
-
-#define __ac97_warm_reset_codec()       \
- do {                       \
-    REG_AIC_ACCR2 |= AIC_ACCR2_SA;      \
-    REG_AIC_ACCR2 |= AIC_ACCR2_SS;      \
-    udelay(2);              \
-    REG_AIC_ACCR2 &= ~AIC_ACCR2_SS;     \
-    REG_AIC_ACCR2 &= ~AIC_ACCR2_SA;     \
- } while (0)
-
-#define __ac97_cold_reset_codec()       \
- do {                       \
-    REG_AIC_ACCR2 |=  AIC_ACCR2_SR;     \
-    udelay(2);              \
-    REG_AIC_ACCR2 &= ~AIC_ACCR2_SR;     \
- } while (0)
-
-/* n=8,16,18,20 */
-#define __ac97_set_iass(n) \
- ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
-#define __ac97_set_oass(n) \
- ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
-
-/* This bit should only be set in 2 channels configuration */
-#define __i2s_send_rfirst()   ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST )  /* RL */
-#define __i2s_send_lfirst()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */
-
-/* This bit should only be set in 2 channels configuration and 16bit-packed mode */
-#define __i2s_switch_lr()     ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH )
-#define __i2s_unswitch_lr()   ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH )
-
-#define __i2s_select_i2s()            ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
-#define __i2s_select_msbjustified()   ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
-
-/* n=8,16,18,20,24 */
-/*#define __i2s_set_sample_size(n) \
- ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
-
-#define __i2s_out_channel_select(n) __aic_out_channel_select(n)
-
-#define __i2s_set_oss_sample_size(n) \
- ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n))
-#define __i2s_set_iss_sample_size(n) \
- ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n))
-
-#define __i2s_stop_bitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
-#define __i2s_start_bitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
-
-#define __i2s_stop_ibitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_ISTPBK )
-#define __i2s_start_ibitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_ISTPBK )
-
-#define __aic_transmit_request()  ( REG_AIC_SR & AIC_SR_TFS )
-#define __aic_receive_request()   ( REG_AIC_SR & AIC_SR_RFS )
-#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
-#define __aic_receive_overrun()   ( REG_AIC_SR & AIC_SR_ROR )
-
-#define __aic_clear_errors()      ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
-
-#define __aic_get_transmit_resident() \
-  ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB )
-#define __aic_get_receive_count() \
-  ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB )
-
-#define __ac97_command_transmitted()     ( REG_AIC_ACSR & AIC_ACSR_CADT )
-#define __ac97_status_received()         ( REG_AIC_ACSR & AIC_ACSR_SADR )
-#define __ac97_status_receive_timeout()  ( REG_AIC_ACSR & AIC_ACSR_RSTO )
-#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
-#define __ac97_codec_is_ready()          ( REG_AIC_ACSR & AIC_ACSR_CRDY )
-#define __ac97_slot_error_detected()     ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
-#define __ac97_clear_slot_error()        ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
-
-#define __i2s_is_busy()         ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
-
-#define __ac97_out_rcmd_addr(reg)                   \
-do {                                    \
-    REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB);  \
-} while (0)
-
-#define __ac97_out_wcmd_addr(reg)                   \
-do {                                    \
-    REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB);     \
-} while (0)
-
-#define __ac97_out_data(value)                      \
-do {                                    \
-    REG_AIC_ACCDR = ((value) << AC97_DATA_LSB);             \
-} while (0)
-
-#define __ac97_in_data() \
- ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB )
-
-#define __ac97_in_status_addr() \
- ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB )
-
-#define __i2s_set_sample_rate(i2sclk, sync) \
-  ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
-
-#define __aic_write_tfifo(v)  ( REG_AIC_DR = (v) )
-#define __aic_read_rfifo()    ( REG_AIC_DR )
-
-#define __aic_internal_codec()  ( REG_AIC_FR |= AIC_FR_ICDC )
-#define __aic_external_codec()  ( REG_AIC_FR &= ~AIC_FR_ICDC )
-#define __aic0_internal_codec()  ( REG_AIC0_FR |= AIC_FR_ICDC )
-#define __aic0_external_codec()  ( REG_AIC0_FR &= ~AIC_FR_ICDC )
-
-//
-// Define next ops for AC97 compatible
-//
-
-#define AC97_ACSR   AIC_ACSR
-
-#define __ac97_enable()     __aic_enable(); __aic_select_ac97()
-#define __ac97_disable()    __aic_disable()
-#define __ac97_reset()      __aic_reset()
-
-#define __ac97_set_transmit_trigger(n)  __aic_set_transmit_trigger(n)
-#define __ac97_set_receive_trigger(n)   __aic_set_receive_trigger(n)
-
-#define __ac97_enable_record()      __aic_enable_record()
-#define __ac97_disable_record()     __aic_disable_record()
-#define __ac97_enable_replay()      __aic_enable_replay()
-#define __ac97_disable_replay()     __aic_disable_replay()
-#define __ac97_enable_loopback()    __aic_enable_loopback()
-#define __ac97_disable_loopback()   __aic_disable_loopback()
-
-#define __ac97_enable_transmit_dma()    __aic_enable_transmit_dma()
-#define __ac97_disable_transmit_dma()   __aic_disable_transmit_dma()
-#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
-#define __ac97_disable_receive_dma()    __aic_disable_receive_dma()
-
-#define __ac97_transmit_request()   __aic_transmit_request()
-#define __ac97_receive_request()    __aic_receive_request()
-#define __ac97_transmit_underrun()  __aic_transmit_underrun()
-#define __ac97_receive_overrun()    __aic_receive_overrun()
-
-#define __ac97_clear_errors()       __aic_clear_errors()
-
-#define __ac97_get_transmit_resident()  __aic_get_transmit_resident()
-#define __ac97_get_receive_count()  __aic_get_receive_count()
-
-#define __ac97_enable_transmit_intr()   __aic_enable_transmit_intr()
-#define __ac97_disable_transmit_intr()  __aic_disable_transmit_intr()
-#define __ac97_enable_receive_intr()    __aic_enable_receive_intr()
-#define __ac97_disable_receive_intr()   __aic_disable_receive_intr()
-
-#define __ac97_write_tfifo(v)       __aic_write_tfifo(v)
-#define __ac97_read_rfifo()     __aic_read_rfifo()
-
-//
-// Define next ops for I2S compatible
-//
-
-#define I2S_ACSR    AIC_I2SSR
-
-#define __i2s_enable()       __aic_enable(); __aic_select_i2s()
-#define __i2s_disable()     __aic_disable()
-#define __i2s_reset()       __aic_reset()
-
-#define __i2s_set_transmit_trigger(n)   __aic_set_transmit_trigger(n)
-#define __i2s_set_receive_trigger(n)    __aic_set_receive_trigger(n)
-
-#define __i2s_enable_record()       __aic_enable_record()
-#define __i2s_disable_record()      __aic_disable_record()
-#define __i2s_enable_replay()       __aic_enable_replay()
-#define __i2s_disable_replay()      __aic_disable_replay()
-#define __i2s_enable_loopback()     __aic_enable_loopback()
-#define __i2s_disable_loopback()    __aic_disable_loopback()
-
-#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
-#define __i2s_disable_transmit_dma()    __aic_disable_transmit_dma()
-#define __i2s_enable_receive_dma()  __aic_enable_receive_dma()
-#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
-
-#define __i2s_transmit_request()    __aic_transmit_request()
-#define __i2s_receive_request()     __aic_receive_request()
-#define __i2s_transmit_underrun()   __aic_transmit_underrun()
-#define __i2s_receive_overrun()     __aic_receive_overrun()
-
-#define __i2s_clear_errors()        __aic_clear_errors()
-
-#define __i2s_get_transmit_resident()   __aic_get_transmit_resident()
-#define __i2s_get_receive_count()   __aic_get_receive_count()
-
-#define __i2s_enable_transmit_intr()    __aic_enable_transmit_intr()
-#define __i2s_disable_transmit_intr()   __aic_disable_transmit_intr()
-#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
-#define __i2s_disable_receive_intr()    __aic_disable_receive_intr()
-
-#define __i2s_write_tfifo(v)        __aic_write_tfifo(v)
-#define __i2s_read_rfifo()      __aic_read_rfifo()
-
-#define __i2s_reset_codec()         \
- do {                       \
- } while (0)
-
-
-/*************************************************************************
- * SPDIF INTERFACE in AIC Controller
- *************************************************************************/
-
-#define __spdif_enable()        ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN )
-#define __spdif_disable()       ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN )
-
-#define __spdif_enable_transmit_dma()     ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN )
-#define __spdif_disable_transmit_dma()    ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN )
-#define __spdif_enable_dtype()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE )
-#define __spdif_disable_dtype()           ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE )
-#define __spdif_enable_sign()             ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN )
-#define __spdif_disable_sign()            ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN )
-#define __spdif_enable_invalid()          ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID )
-#define __spdif_disable_invalid()         ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID )
-#define __spdif_enable_reset()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST )
-#define __spdif_select_spdif()            ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S )
-#define __spdif_select_i2s()              ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S )
-#define __spdif_enable_MTRIGmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG )
-#define __spdif_disable_MTRIGmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG )
-#define __spdif_enable_MFFURmask()        ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR )
-#define __spdif_disable_MFFURmask()       ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR )
-
-#define __spdif_enable_initlvl_high()     ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_INITLVL )
-#define __spdif_enable_initlvl_low()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_INITLVL )
-#define __spdif_enable_zrovld_invald()    ( REG_SPDIF_CFG1 |=  SPDIF_CFG1_ZROVLD )
-#define __spdif_enable_zrovld_vald()      ( REG_SPDIF_CFG1 &=  ~SPDIF_CFG1_ZROVLD )
-
-/* 0, 1, 2, 3 */
-#define __spdif_set_transmit_trigger(n)         \
-do {                            \
-    REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK;    \
-    REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n);   \
-} while(0)
-
-/* 1 ~ 15 */
-#define __spdif_set_srcnum(n)               \
-do {                            \
-    REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK;  \
-    REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB);   \
-} while(0)
-
-/* 1 ~ 15 */
-#define __spdif_set_ch1num(n)               \
-do {                            \
-    REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK;  \
-    REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB);   \
-} while(0)
-
-/* 1 ~ 15 */
-#define __spdif_set_ch2num(n)               \
-do {                            \
-    REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK;  \
-    REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB);   \
-} while(0)
-
-/* 0x0, 0x2, 0x3, 0xa, 0xe */
-#define __spdif_set_fs(n)               \
-do {                            \
-    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK;      \
-    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB);   \
-} while(0)
-
-/* 0xd, 0xc, 0x5, 0x1 */
-#define __spdif_set_orgfrq(n)               \
-do {                            \
-    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK;      \
-    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB);   \
-} while(0)
-
-/* 0x1, 0x6, 0x2, 0x4, 0x5 */
-#define __spdif_set_samwl(n)                \
-do {                            \
-    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK;       \
-    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB);    \
-} while(0)
-
-#define __spdif_enable_samwl_24()    ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL )
-#define __spdif_enable_samwl_20()    ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL )
-
-/* 0x1, 0x1, 0x2, 0x3 */
-#define __spdif_set_clkacu(n)               \
-do {                            \
-    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK;      \
-    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB);   \
-} while(0)
-
-/* see IEC60958-3 */
-#define __spdif_set_catcode(n)              \
-do {                            \
-    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK;     \
-    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB);  \
-} while(0)
-
-/* n = 0x0, */
-#define __spdif_set_chmode(n)               \
-do {                            \
-    REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK;    \
-    REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB); \
-} while(0)
-
-#define __spdif_enable_pre()       ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE )
-#define __spdif_disable_pre()      ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE )
-#define __spdif_enable_copyn()     ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN )
-#define __spdif_disable_copyn()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN )
-/* audio sample word represents linear PCM samples */
-#define __spdif_enable_audion()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION )
-/* udio sample word used for other purpose */
-#define __spdif_disable_audion()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION )
-#define __spdif_enable_conpro()    ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO )
-#define __spdif_disable_conpro()   ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO )
-
-/***************************************************************************
- * ICDC
- ***************************************************************************/
-#define __i2s_internal_codec()         __aic_internal_codec()
-#define __i2s_external_codec()         __aic_external_codec()
-
-#define __icdc_clk_ready()             ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY )
-#define __icdc_sel_adc()               ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD )
-#define __icdc_sel_dac()               ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD )
-
-#define __icdc_set_rgwr()              ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR )
-#define __icdc_clear_rgwr()            ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR )
-#define __icdc_rgwr_ready()            ( REG_ICDC_RGADW & ICDC_RGADW_RGWR )
-
-#define AIC_RW_CODEC_START()        while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR)
-#define AIC_RW_CODEC_STOP()     while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR)
-
-
-#define __icdc_set_addr(n)              \
-do {                                \
-    REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK;  \
-    REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB; \
-} while(0)
-
-#define __icdc_set_cmd(n)               \
-do {                                \
-    REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK;   \
-    REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB;  \
-} while(0)
-
-#define __icdc_irq_pending()            ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ )
-#define __icdc_get_value()              ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK )
-
-
-
-#endif /* __MIPS_ASSEMBLER */
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _X1000_AIC_H_ */
diff --git a/libcpu/mips/x1000/x1000_cpm.h b/libcpu/mips/x1000/x1000_cpm.h
deleted file mode 100644
index da2cc964e5..0000000000
--- a/libcpu/mips/x1000/x1000_cpm.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/*
- * File      : x1000_cpm.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-02-03     Urey         the first version
- */
-
-#ifndef _X1000_CPM_H_
-#define _X1000_CPM_H_
-
-#define CPM_CPCCR       (0x00)
-#define CPM_CPCSR       (0xd4)
-
-#define CPM_DDRCDR      (0x2c)
-#define CPM_I2SCDR      (0x60)
-#define CPM_I2SCDR1     (0x70)
-#define CPM_LPCDR       (0x64)
-#define CPM_MSC0CDR     (0x68)
-#define CPM_MSC1CDR     (0xa4)
-#define CPM_USBCDR      (0x50)
-#define CPM_MACCDR      (0x54)
-#define CPM_UHCCDR      (0x6c)
-#define CPM_SFCCDR      (0x74)
-#define CPM_CIMCDR      (0x7c)
-#define CPM_PCMCDR      (0x84)
-#define CPM_PCMCDR1     (0xe0)
-#define CPM_MPHYC       (0xe8)
-
-#define CPM_INTR        (0xb0)
-#define CPM_INTRE       (0xb4)
-#define CPM_DRCG        (0xd0)
-#define CPM_CPSPPR      (0x38)
-#define CPM_CPPSR       (0x34)
-
-#define CPM_USBPCR      (0x3c)
-#define CPM_USBRDT      (0x40)
-#define CPM_USBVBFIL    (0x44)
-#define CPM_USBPCR1     (0x48)
-
-#define CPM_CPAPCR      (0x10)
-#define CPM_CPMPCR      (0x14)
-
-#define CPM_LCR         (0x04)
-#define CPM_PSWC0ST     (0x90)
-#define CPM_PSWC1ST     (0x94)
-#define CPM_PSWC2ST     (0x98)
-#define CPM_PSWC3ST     (0x9c)
-#define CPM_CLKGR       (0x20)
-#define CPM_CLKGR0       (0x20)
-#define CPM_MESTSEL     (0xec)
-#define CPM_SRBC        (0xc4)
-#define CPM_ERNG        (0xd8)
-#define CPM_RNG         (0xdc)
-#define CPM_SLBC        (0xc8)
-#define CPM_SLPC        (0xcc)
-#define CPM_OPCR        (0x24)
-#define CPM_RSR         (0x08)
-
-
-
-
-/*
- * CPM registers common define
- */
-
-/* Clock control register(CPCCR) */
-#define CPCCR_SEL_SRC_LSB       30
-#define CPCCR_SEL_SRC_MASK      BITS_H2L(31, CPCCR_SEL_SRC_LSB)
-
-#define CPCCR_SEL_CPLL_LSB      28
-#define CPCCR_SEL_CPLL_MASK     BITS_H2L(29, CPCCR_SEL_CPLL_LSB)
-
-#define CPCCR_SEL_H0PLL_LSB     26
-#define CPCCR_SEL_H0PLL_MASK    BITS_H2L(27, CPCCR_SEL_H0PLL_LSB)
-
-#define CPCCR_SEL_H2PLL_LSB     24
-#define CPCCR_SEL_H2PLL_MASK    BITS_H2L(25, CPCCR_SEL_H2PLL_LSB)
-
-#define CPCCR_CE_CPU            BIT22
-#define CPCCR_CE_AHB0           BIT21
-#define CPCCR_CE_AHB2           BIT20
-#define CPCCR_CE                (CPCCR_CE_CPU | CPCCR_CE_AHB0 | CPCCR_CE_AHB2)
-
-#define CPCCR_PDIV_LSB          16
-#define CPCCR_PDIV_MASK         BITS_H2L(19, CPCCR_PDIV_LSB)
-
-#define CPCCR_H2DIV_LSB         12
-#define CPCCR_H2DIV_MASK        BITS_H2L(15, CPCCR_H2DIV_LSB)
-
-#define CPCCR_H0DIV_LSB         8
-#define CPCCR_H0DIV_MASK        BITS_H2L(11, CPCCR_H0DIV_LSB)
-
-#define CPCCR_L2DIV_LSB         4
-#define CPCCR_L2DIV_MASK        BITS_H2L(7,  CPCCR_L2DIV_LSB)
-
-#define CPCCR_CDIV_LSB          0
-#define CPCCR_CDIV_MASK         BITS_H2L(3,  CPCCR_CDIV_LSB)
-
-#define CPM_SRC_SEL_APLL        1
-#define CPM_PLL_SEL_SRC         1
-#define CPM_PLL_SEL_MPLL        2
-
-/* Clock Status register(CPCSR) */
-#define CPCSR_SRC_MUX           BIT31
-#define CPCSR_CPU_MUX           BIT30
-#define CPCSR_AHB0_MUX          BIT29
-#define CPCSR_AHB2_MUX          BIT28
-#define CPCSR_DDR_MUX           BIT27
-#define CPCSR_H2DIV_BUSY        BIT2
-#define CPCSR_H0DIV_BUSY        BIT1
-#define CPCSR_CDIV_BUSY         BIT0
-#define CPCSR_DIV_BUSY          (CPCSR_H2DIV_BUSY | CPCSR_H0DIV_BUSY | CPCSR_CDIV_BUSY)
-
-/* DDR clock divider register(DDCDR) */
-#define DDCDR_DCS_LSB           30
-#define DDCDR_DCS_MASK          BITS_H2L(31, DDCDR_DCS_LSB)
-#define DDCDR_DCS_STOP          (0 << DDCDR_DCS_LSB)
-#define DDCDR_DCS_APLL          (1 << DDCDR_DCS_LSB)
-#define DDCDR_DCS_MPLL          (2 << DDCDR_DCS_LSB)
-#define DDCDR_CE_DDR            BIT29
-#define DDCDR_DDR_BUSY          BIT28
-#define DDCDR_DDR_STOP          BIT27
-#define DDCDR_GATE_EN           BIT26
-#define DDCDR_DDR_CHANGE_EN     BIT25
-#define DDCDR_DDR               BIT24
-#define DDCDR_DDRDIV_LSB        0
-#define DDCDR_DDRDIV_MASK       BITS_H2L(3, DDCDR_DDRDIV_LSB)
-
-/*MACPHY clock divider Register (MACCDR)*/
-#define MACCDR_MACPCS           BIT31
-#define MACCDR_CE_MAC           BIT29
-#define MACCDR_MAC_BUSY         BIT28
-#define MACCDR_MAC_STOP         BIT27
-#define MACCDR_MACCDR_LSB       BIT0
-#define MACCDR_MACCDR_MASK      BITS_H2L(7,MACCDR_MACCDR_LSB)
-
-/* I2S device clock divider register(I2SCDR) */
-#define I2SCDR_I2PCS            BIT31
-#define I2SCDR_I2CS             BIT30
-
-#define I2SCDR_I2SDIV_M_LSB     13
-#define I2SCDR_I2SDIV_M_MASK    BITS_H2L(21,I2SCDR_I2SDIV_M_LSB)
-#define I2SCDR_I2SDIV_N_LSB     0       /* I2SCDR bit */
-#define I2SCDR_I2SDIV_N_MASK    BITS_H2L(7, I2SCDR_I2SDIV_N_LSB)
-
-
-/* I2S device clock divider register(I2SCDR1) */
-#define I2SCDR1_NEN             BIT31
-#define I2SCDR1_DEN             BIT30
-#define I2SCDR1_I2SDIV_D_LSB    0
-#define I2SCDR1_I2SDIV_D_MASK   BITS_H2L(12,I2SCDR1_I2SDIV_D_LSB)
-
-/* LCD pix clock divider register(LPCDR) */
-#define LPCDR_LPCS_LSB          31
-#define LPCDR_LPCS_APLL         (0 << LPCDR_LPCS_LSB)
-#define LPCDR_LPCS_MPLL         (1 << LPCDR_LPCS_LSB)
-#define LPCDR_CE_LCD            BIT28
-#define LPCDR_LCD_BUSY          BIT27
-#define LPCDR_LCD_STOP          BIT26
-
-#define LPCDR_PIXDIV_LSB        0       /* LPCDR bit */
-#define LPCDR_PIXDIV_MASK       BITS_H2L(7, LPCDR_PIXDIV_LSB)
-
-/* MSC clock divider register(MSCCDR) */
-#define MSCCDR_MPCS_LSB         31       /* MPCS bit */
-#define MSCCDR_MPCS_APLL        (0 << MSCCDR_MPCS_LSB)
-#define MSCCDR_MPCS_MPLL        (1 << MSCCDR_MPCS_LSB)
-
-#define MSCCDR_CE_MSC           BIT29
-#define MSCCDR_MSC_BUSY         BIT28
-#define MSCCDR_MSC_STOP         BIT27
-#define MSCCDR_S_CLK0_SEL       BIT15
-
-#define MSCCDR_MSCDIV_LSB       0       /* MSCCDR bit */
-#define MSCCDR_MSCDIV_MASK      BITS_H2L(7, MSCCDR_MSCDIV_LSB)
-
-
-/* OTG PHY clock divider register(USBCDR) */
-#define USBCDR_UCS              BIT31
-#define USBCDR_UPCS             BIT30
-#define USBCDR_CE_USB           BIT29
-#define USBCDR_USB_BUSY         BIT28
-#define USBCDR_USB_STOP         BIT27
-
-#define USBCDR_OTGDIV_LSB       0       /* USBCDR bit */
-#define USBCDR_OTGDIV_MASK      BITS_H2L(7, USBCDR_OTGDIV_LSB)
-
-/* SSI clock divider register(SSICDR) */
-#define SSICDR_SPCS             BIT31
-#define SSICDR_SCS              BIT30
-#define SSICDR_CE_SSI           BIT29
-#define SSICDR_SSI_BUSY         BIT28
-#define SSICDR_SSI_STOP         BIT27
-#define SSICDR_SSIDIV_LSB       0       /* SSICDR bit */
-#define SSICDR_SSIDIV_MASK      BITS_H2L(7, SSICDR_SSIDIV_LSB)
-
-/* CIM mclk clock divider register(CIMCDR) */
-#define CIMCDR_CIMPCS_APLL      (0 << 31)
-#define CIMCDR_CIMPCS_MPLL      BIT31
-#define CIMCDR_CE_CIM           BIT29
-#define CIMCDR_CIM_BUSY         BIT28
-#define CIMCDR_CIM_STOP         BIT27
-
-#define CIMCDR_CIMDIV_LSB       0       /* CIMCDR bit */
-#define CIMCDR_CIMDIV_MASK      BITS_H2L(7, CIMCDR_CIMDIV_LSB)
-
-
-/* PCM device clock divider register(PCMCDR) */
-#define PCMCDR_PCMPCS_LSB       30
-#define PCMCDR_PCMPCS_MASK      BITS_H2L(31,PCMCDR_PCMPCS_LSB)
-#define PCMCDR_PCMPCS_SCLK_A    0 << PCMCDR_PCMPCS_LSB
-#define PCMCDR_PCMPCS_EXTCLK    1 << PCMCDR_PCMPCS_LSB
-#define PCMCDR_PCMPCS_MPLL      2 << PCMCDR_PCMPCS_LSB
-#define PCMCDR_CE_PCM           BIT29
-#define PCMCDR_PCMDIV_M_LSB     13
-#define PCMCDR_PCMDIV_M_MASK    BITS_H2L(21,PCMCDR_PCMDIV_M_LSB)
-#define PCMCDR_PCMDIV_N_LSB     0
-#define PCMCDR_PCMDIV_N_MASK    BITS_H2L(12,PCMCDR_PCMDIV_N_LSB)
-
-/* PCM device clock divider register(PCMCDR1) */
-
-#define PCMCDR1_PCM_NEN         BIT31
-#define PCMCDR1_PCM_DEN         BIT30
-#define PCMCDR1_PCMDIV_D_LSB    0
-#define PCMCDR1_PCMDIV_D_MASK   BITS_H2L(12,PCMCDR1_PCMDIV_D_LSB)
-
-/* MAC PHY Control Register (MPHYC) */
-#define MPHYC_MODE_SEL          BIT31  //useless now
-#define MPHYC_MAC_SPEED_LSB     29
-#define MPHYC_MAC_SPEED_MASK    BITS_H2L(30,MPHYC_MAC_SPEED_LSB)
-#define MPHYC_SOFT_RST          BIT3
-#define MPHYC_PHY_INTF_LSB      0
-#define MPHYC_PHY_INTF_MASK     BITS_H2L(2,MPHYC_PHY_INTF_MASK) //useless now
-
-/* CPM Interrupt Register (CPM_INTR)*/
-#define CPM_INTR_VBUS_INTR      BIT1
-#define CPM_INTR_ADEV_INTR      BIT0
-
-/* CPM Interrupt Enable Register (CPM_INTRE)*/
-#define CPM_INTRE_VBUS_INTRE    BIT1
-#define CPM_INTRE_ADEV_INTRE    BIT0
-
-/* CPM scratch pad protected register(CPSPPR) */
-#define CPSPPR_CPSPR_WRITABLE   (0x00005a5a)
-
-/* OTG parameter control register(USBPCR) */
-#define USBPCR_USB_MODE         BIT31
-#define USBPCR_AVLD_REG         BIT30
-#define USBPCR_INCRM            BIT27   /* INCR_MASK bit */
-#define USBPCR_TXRISE_TUNE      BIT26
-#define USBPCR_COMMONONN        BIT25
-#define USBPCR_VBUSVLDEXT       BIT24
-#define USBPCR_VBUSVLDEXTSEL    BIT23
-#define USBPCR_POR              BIT22
-#define USBPCR_SIDDQ            BIT21
-#define USBPCR_OTG_DISABLE      BIT20
-#define USBPCR_TXPREEMPHTUNE    BIT6
-
-#define USBPCR_IDPULLUP_LSB     28   /* IDPULLUP_MASK bit */
-#define USBPCR_IDPULLUP_MASK    BITS_H2L(29, USBPCR_IDPULLUP_LSB)
-
-#define USBPCR_COMPDISTUNE_LSB  17
-#define USBPCR_COMPDISTUNE_MASK BITS_H2L(19, USBPCR_COMPDISTUNE_LSB)
-
-#define USBPCR_OTGTUNE_LSB      14
-#define USBPCR_OTGTUNE_MASK     BITS_H2L(16, USBPCR_OTGTUNE_LSB)
-
-#define USBPCR_SQRXTUNE_LSB     11
-#define USBPCR_SQRXTUNE_MASK    BITS_H2L(13, USBPCR_SQRXTUNE_LSB)
-
-#define USBPCR_TXFSLSTUNE_LSB   7
-#define USBPCR_TXFSLSTUNE_MASK  BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB)
-
-#define USBPCR_TXRISETUNE_LSB   4
-#define USBPCR_TXRISETUNE_MASK  BITS_H2L(5, USBPCR_TXRISETUNE_LSB)
-
-#define USBPCR_TXVREFTUNE_LSB   0
-#define USBPCR_TXVREFTUNE_MASK  BITS_H2L(3, USBPCR_TXVREFTUNE_LSB)
-
-/* OTG reset detect timer register(USBRDT) */
-#define USBRDT_HB_MASK          BIT26
-#define USBRDT_VBFIL_LD_EN      BIT25
-#define USBRDT_IDDIG_EN         BIT24
-#define USBRDT_IDDIG_REG        BIT23
-
-#define USBRDT_USBRDT_LSB       0
-#define USBRDT_USBRDT_MASK      BITS_H2L(22, USBRDT_USBRDT_LSB)
-
-/* OTG parameter control register(USBPCR1) */
-#define USBPCR1_REG             BIT31
-#define USBPCR1_USB_SEL         BIT28
-#define USBPCR1_REFCLKSEL_LSB   26
-#define USBPCR1_REFCLKSEL_MASK  BITS_H2L(27, USBPCR1_REFCLKSEL_LSB)
-
-#define USBPCR1_REFCLKDIV_LSB   24
-#define USBPCR1_REFCLKDIV_MASK  BITS_H2L(25, USBPCR1_REFCLKDIV_LSB)
-
-#define USBPCR1_PORT_RST        BIT21
-
-#define USBPCR1_WORD_IF0        BIT19
-#define USBPCR1_WORD_IF1        BIT18
-
-
-/* APLL control register (CPXPCR) */
-#define CPAPCR_BS               BIT31
-#define CPAPCR_M_LSB            24
-#define CPAPCR_M_MASK           BITS_H2L(30, CPAPCR_M_LSB)
-
-#define CPAPCR_N_LSB            18
-#define CPAPCR_N_MASK           BITS_H2L(22, CPAPCR_N_LSB)
-
-#define CPAPCR_OD_LSB           16
-#define CPAPCR_OD_MASK          BITS_H2L(17, CPAPCR_OD_LSB)
-
-#define CPAPCR_LOCK             BIT15   /* LOCK bit */
-#define CPAPCR_ON               BIT10
-#define CPAPCR_BP               BIT9
-#define CPAPCR_EN               BIT8
-#define CPAPCR_PLLST_LSB        0
-#define CPAPCR_PLLST_MASK       BITS_H2L(7,CPAPCR_PLLST_LSB)
-
-#define CPM_CPAPCR_EN           CPAPCR_EN
-#define CPM_CPAPCR_ON           CPAPCR_ON
-
-/* MPLL control register (CPXPCR) */
-#define CPMPCR_BS               BIT31
-#define CPMPCR_M_LSB            24
-#define CPMPCR_M_MASK           BITS_H2L(30, CPAPCR_M_LSB)
-
-#define CPMPCR_N_LSB            18
-#define CPMPCR_N_MASK           BITS_H2L(22, CPAPCR_N_LSB)
-
-#define CPMPCR_OD_LSB           16
-#define CPMPCR_OD_MASK          BITS_H2L(17, CPAPCR_OD_LSB)
-
-#define CPMPCR_EN               BIT7
-#define CPMPCR_BP               BIT6
-#define CPMPCR_LOCK             BIT1    /* LOCK bit */
-#define CPMPCR_ON               BIT0
-
-#define CPM_CPMPCR_EN           CPMPCR_EN
-#define CPM_CPMPCR_ON           CPMPCR_ON
-
-
-
-/* Low power control register(LCR) */
-#define LCR_PST_LSB             8
-#define LCD_PST_MASK            BITS_H2L(19,LCR_PST_LSB)
-#define LCR_LPM_LSB             0
-#define LCR_LPM_MASK            BITS_H2L(1,LCR_LPM_LSB)
-
-/* Clock gate register 0(CGR0) */
-#define CLKGR0_DDR              BIT31
-#define CLKGR0_CPU              BIT30
-#define CLKGR0_AHB0             BIT29
-#define CLKGR0_APB0             BIT28
-#define CLKGR0_RTC              BIT27
-#define CLKGR0_PCM              BIT26
-#define CLKGR0_MAC              BIT25
-#define CLKGR0_AES              BIT24
-#define CLKGR0_LCD              BIT23
-#define CLKGR0_CIM              BIT22
-#define CLKGR0_PDMA             BIT21
-#define CLKGR0_OST              BIT20
-#define CLKGR0_SSI              BIT19
-#define CLKGR0_TCU              BIT18
-#define CLKGR0_DMIC             BIT17
-#define CLKGR0_UART2            BIT16
-#define CLKGR0_UART1            BIT15
-#define CLKGR0_UART0            BIT14
-#define CLKGR0_SADC             BIT13
-#define CLKGR0_JPEG             BIT12
-#define CLKGR0_AIC              BIT11
-#define CLKGR0_I2C3             BIT10
-#define CLKGR0_I2C2             BIT9
-#define CLKGR0_I2C1             BIT8
-#define CLKGR0_I2C0             BIT7
-#define CLKGR0_SCC              BIT6
-#define CLKGR0_MSC1             BIT5
-#define CLKGR0_MSC0             BIT4
-#define CLKGR0_OTG              BIT3
-#define CLKGR0_SFC              BIT2
-#define CLKGR0_EFUSE            BIT1
-#define CLKGR0_NEMC             BIT0
-
-/* CPM MEST SEL Register */
-
-#define MEST_SEL_TST8           BIT8
-#define MEST_SEL_TST7           BIT7
-#define MEST_SEL_TST4           BIT4
-#define MEST_SEL_TST3           BIT3
-#define MEST_SEL_TST1           BIT1
-#define MEST_SEL_TST0           BIT0
-
-/*Soft Reset and Bus Control Register (SRBC)*/
-
-#define SRBC_JPEG_SR            BIT31
-#define SRBC_JPEG_STP           BIT30
-#define SRBC_JPEG_ACK           BIT29
-#define SRBC_LCD_SR             BIT25
-#define SRBC_LCD_STP            BIT24
-#define SRBC_LCD_ACK            BIT23
-#define SRBC_CIM_STP            BIT21
-#define SRBC_CIM_ACK            BIT20
-#define SRBC_CPU_STP            BIT15
-#define SRBC_CPU_ACK            BIT14
-#define SRBC_OTG_SR             BIT12
-#define SRBC_AHB2_STP           BIT8
-#define SRBC_AHB2_ACK           BIT7
-#define SRBC_DDR_STP            BIT6
-#define SRBC_DDR_ACK            BIT5
-
-
-/* Oscillator and power control register(OPCR) */
-#define OPCR_IDLE_DIS           BIT31
-#define OPCR_MASK_INT           BIT30
-#define OPCR_MASK_VPU           BIT29  //ONLY FOR DEBUG
-#define OPCR_GATE_SCLK_ABUS     BIT28
-#define OPCR_L2C_PD             BIT25
-#define OPCR_REQ_MODE           BIT24
-#define OPCR_GATE_USBPHY_CLK    BIT23
-#define OPCR_DIS_STOP_MUX       BIT22
-#define OPCR_O1ST_LSB           8
-#define OPCR_O1ST_MASK          BITS_H2L(19, OPCR_O1ST_LSB)
-#define OPCR_OTGPHY0_ENABLE     BIT7    /* otg */
-#define OPCR_OTGPHY1_ENABLE     BIT6    /* uhc */
-#define OPCR_USBPHY_ENABLE      (OPCR_OTGPHY0_ENABLE | OPCR_OTGPHY1_ENABLE)
-#define OPCR_O1SE               BIT4
-#define OPCR_PD                 BIT3
-#define OPCR_ERCS               BIT2
-#define OPCR_BUSMODE            BIT1
-
-
-
-/* Reset status register(RSR) */
-#define RSR_HR                  BIT3
-#define RSR_P0R                 BIT2
-#define RSR_WR                  BIT1
-#define RSR_PR                  BIT0
-
-
-#ifndef __ASSEMBLY__
-
-#define REG_CPM_CPCCR           REG32(CPM_BASE + CPM_CPCCR)
-#define REG_CPM_CPCSR           REG32(CPM_BASE + CPM_CPCSR)
-#define REG_CPM_DDCDR           REG32(CPM_BASE + CPM_DDCDR)
-#define REG_CPM_MACCDR          REG32(CPM_BASE + CPM_MACCDR)
-#define REG_CPM_I2SCDR          REG32(CPM_BASE + CPM_I2SCDR)
-#define REG_CPM_I2SCDR1         REG32(CPM_BASE + CPM_I2SCDR1)
-#define REG_CPM_LPCDR           REG32(CPM_BASE + CPM_LPCDR)
-#define REG_CPM_MSC0CDR         REG32(CPM_BASE + CPM_MSC0CDR)
-#define REG_CPM_MSC1CDR         REG32(CPM_BASE + CPM_MSC1CDR)
-#define REG_CPM_USBCDR          REG32(CPM_BASE + CPM_USBCDR)
-#define REG_CPM_SSICDR          REG32(CPM_BASE + CPM_SSICDR)
-#define REG_CPM_CIMCDR          REG32(CPM_BASE + CPM_CIMCDR)
-#define REG_CPM_PCMCDR          REG32(CPM_BASE + CPM_PCMCDR)
-#define REG_CPM_PCMCDR1         REG32(CPM_BASE + CPM_PCMCDR1)
-#define REG_CPM_MPHYC           REG32(CPM_BASE + CPM_MPHYC)
-#define REG_CPM_INTRCDR         REG32(CPM_BASE + CPM_INTRCDR)
-#define REG_CPM_INTRECDR        REG32(CPM_BASE + CPM_INTRECDR)
-#define REG_CPM_CPSPR           REG32(CPM_BASE + CPM_CPSPR)
-#define REG_CPM_CPSPPR          REG32(CPM_BASE + CPM_CPSPPR)
-#define REG_CPM_USBPCR          REG32(CPM_BASE + CPM_USBPCR)
-#define REG_CPM_USBRDT          REG32(CPM_BASE + CPM_USBRDT)
-#define REG_CPM_USBVBFIL        REG32(CPM_BASE + CPM_USBVBFIL)
-#define REG_CPM_USBPCR1         REG32(CPM_BASE + CPM_USBPCR1)
-#define REG_CPM_CPAPCR          REG32(CPM_BASE + CPM_CPAPCR)
-#define REG_CPM_CPMPCR          REG32(CPM_BASE + CPM_CPMPCR)
-
-#define REG_CPM_LCR             REG32(CPM_BASE + CPM_LCR)
-#define REG_CPM_PSWC0ST         REG32(CPM_BASE + CPM_PSWC0ST)
-#define REG_CPM_PSWC1ST         REG32(CPM_BASE + CPM_PSWC1ST)
-#define REG_CPM_PSWC2ST         REG32(CPM_BASE + CPM_PSWC2ST)
-#define REG_CPM_PSWC3ST         REG32(CPM_BASE + CPM_PSWC3ST)
-#define REG_CPM_CLKGR0          REG32(CPM_BASE + CPM_CLKGR0)
-#define REG_CPM_SRBC            REG32(CPM_BASE + CPM_SRBC)
-#define REG_CPM_SLBC            REG32(CPM_BASE + CPM_SLBC)
-#define REG_CPM_SLPC            REG32(CPM_BASE + CPM_SLPC)
-#define REG_CPM_OPCR            REG32(CPM_BASE + CPM_OPCR)
-#define REG_CPM_RSR             REG32(CPM_BASE + CPM_RSR)
-
-#define _REG_CPM_MSCCDR(n)      REG_CPM_MSC##n##CDR
-#define REG_CPM_MSCCDR(n)       _REG_CPM_MSCCDR(n)
-
-/* CPM read write */
-#define cpm_inl(off)            readl(CPM_BASE + off)
-#define cpm_outl(val,off)       writel(val, CPM_BASE + off)
-#define cpm_test_bit(bit,off)   (cpm_inl(off) & 0x1<<(bit))
-#define cpm_set_bit(bit,off)    (cpm_outl((cpm_inl(off) | 0x1<<(bit)),off))
-#define cpm_clear_bit(bit,off)  (cpm_outl(cpm_inl(off) & ~(0x1 << bit), off))
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _X1000_CPM_H_ */
diff --git a/libcpu/mips/x1000/x1000_intc.h b/libcpu/mips/x1000/x1000_intc.h
deleted file mode 100644
index 1644b90777..0000000000
--- a/libcpu/mips/x1000/x1000_intc.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * File      : x1000_intc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-02-03     Urey         the first version
- */
-
-#ifndef _X1000_INTC_H_
-#define _X1000_INTC_H_
-
-
-/*
- * INTC (Interrupt Controller)
- */
-#define INTC_ISR(n)             (INTC_BASE + 0x00 + (n) * 0x20)
-#define INTC_IMR(n)             (INTC_BASE + 0x04 + (n) * 0x20)
-#define INTC_IMSR(n)            (INTC_BASE + 0x08 + (n) * 0x20)
-#define INTC_IMCR(n)            (INTC_BASE + 0x0c + (n) * 0x20)
-#define INTC_IPR(n)             (INTC_BASE + 0x10 + (n) * 0x20)
-
-#define REG_INTC_ISR(n)         REG32(INTC_ISR((n)))
-#define REG_INTC_IMR(n)         REG32(INTC_IMR((n)))
-#define REG_INTC_IMSR(n)        REG32(INTC_IMSR((n)))
-#define REG_INTC_IMCR(n)        REG32(INTC_IMCR((n)))
-#define REG_INTC_IPR(n)         REG32(INTC_IPR((n)))
-
-// interrupt controller interrupts
-#define IRQ_DMIC                0
-#define IRQ_AIC0                1
-#define IRQ_RESERVED2           2
-#define IRQ_RESERVED3           3
-#define IRQ_RESERVED4           4
-#define IRQ_RESERVED5           5
-#define IRQ_RESERVED6           6
-#define IRQ_SFC                 7
-#define IRQ_SSI0                8
-#define IRQ_RESERVED9           9
-#define IRQ_PDMA                10
-#define IRQ_PDMAD               11
-#define IRQ_RESERVED12          12
-#define IRQ_RESERVED13          13
-#define IRQ_GPIO3               14
-#define IRQ_GPIO2               15
-#define IRQ_GPIO1               16
-#define IRQ_GPIO0               17
-#define IRQ_RESERVED18          18
-#define IRQ_RESERVED19          19
-#define IRQ_RESERVED20          20
-#define IRQ_OTG                 21
-#define IRQ_RESERVED22          22
-#define IRQ_AES                 23
-#define IRQ_RESERVED24          24
-#define IRQ_TCU2                25
-#define IRQ_TCU1                26
-#define IRQ_TCU0                27
-#define IRQ_RESERVED28          28
-#define IRQ_RESERVED29          29
-#define IRQ_CIM                 30
-#define IRQ_LCD                 31
-#define IRQ_RTC                 32
-#define IRQ_RESERVED33          33
-#define IRQ_RESERVED34          34
-#define IRQ_RESERVED35          35
-#define IRQ_MSC1                36
-#define IRQ_MSC0                37
-#define IRQ_SCC                 38
-#define IRQ_RESERVED39          39
-#define IRQ_PCM0                40
-#define IRQ_RESERVED41          41
-#define IRQ_RESERVED42          42
-#define IRQ_RESERVED43          43
-#define IRQ_HARB2               44
-#define IRQ_RESERVED45          45
-#define IRQ_HARB0               46
-#define IRQ_CPM                 47
-#define IRQ_RESERVED48          48
-#define IRQ_UART2               49
-#define IRQ_UART1               50
-#define IRQ_UART0               51
-#define IRQ_DDR                 52
-#define IRQ_RESERVED53          53
-#define IRQ_EFUSE               54
-#define IRQ_MAC                 55
-#define IRQ_RESERVED56          56
-#define IRQ_RESERVED57          57
-#define IRQ_I2C2                58
-#define IRQ_I2C1                59
-#define IRQ_I2C0                60
-#define IRQ_PDMAM               61
-#define IRQ_JPEG                62
-#define IRQ_RESERVED63          63
-
-#define IRQ_INTC_MAX            63
-
-#ifndef __ASSEMBLY__
-
-#define __intc_unmask_irq(n)    (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
-#define __intc_mask_irq(n)      (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
-#define __intc_ack_irq(n)       (REG_INTC_IPR((n)/32) = (1 << ((n)%32)))        /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _X1000_INTC_H_ */
diff --git a/libcpu/mips/x1000/x1000_otg_dwc.h b/libcpu/mips/x1000/x1000_otg_dwc.h
deleted file mode 100644
index bb77981daa..0000000000
--- a/libcpu/mips/x1000/x1000_otg_dwc.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * File      : x1000_otg_dwc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-02-03     Urey         the first version
- */
-
-#ifndef _X1000_OTG_DWC_H_
-#define _X1000_OTG_DWC_H_
-
-/* Globle Regs define */
-#define GOTG_CTL        (OTG_BASE + 0x00)
-#define GOTG_INTR       (OTG_BASE + 0x04)
-#define GAHB_CFG        (OTG_BASE + 0x08)
-#define GUSB_CFG        (OTG_BASE + 0x0c)
-#define GRST_CTL        (OTG_BASE + 0x10)
-#define GINT_STS        (OTG_BASE + 0x14)
-#define GINT_MASK       (OTG_BASE + 0x18)
-#define GRXSTS_READ     (OTG_BASE + 0x1c)
-#define GRXSTS_POP      (OTG_BASE + 0x20)
-#define GRXFIFO_SIZE        (OTG_BASE + 0x24)
-#define GNPTXFIFO_SIZE      (OTG_BASE + 0x28)
-#define GDTXFIFO_SIZE       (OTG_BASE + 0x104)
-#define GHW_CFG1        (OTG_BASE + 0x44)
-#define GHW_CFG2        (OTG_BASE + 0x48)
-#define GHW_CFG3        (OTG_BASE + 0x4c)
-#define GHW_CFG4        (OTG_BASE + 0x50)
-#define GDFIFO_CFG      (OTG_BASE + 0x5c)
-#define PCGC_CTL        (OTG_BASE + 0xe00)
-
-/* Fifo number 1 ~ 15 */
-#define GDEIP_TXF(n)    (OTG_BASE + (0x104 + ((n-1) * 0x4)))
-
-#define REG_GOTG_CTL        REG32(GOTG_CTL)
-#define REG_GOTG_INTR       REG32(GOTG_INTR)
-#define REG_GAHB_CFG        REG32(GAHB_CFG)
-#define REG_GUSB_CFG        REG32(GUSB_CFG)
-#define REG_GRST_CTL        REG32(GRST_CTL)
-#define REG_GINT_STS        REG32(GINT_STS)
-#define REG_GINT_MASK       REG32(GINT_MASK)
-#define REG_GRXSTS_READ     REG32(GRXSTS_READ)
-#define REG_GRXSTS_POP      REG32(GRXSTS_POP)
-#define REG_GRXFIFO_SIZE    REG32(GRXFIFO_SIZE)
-#define REG_GNPTXFIFO_SIZE  REG32(GNPTXFIFO_SIZE)
-#define REG_GDTXFIFO_SIZE   REG32(GDTXFIFO_SIZE)
-#define REG_GHW_CFG1        REG32(GHW_CFG1)
-#define REG_GHW_CFG2        REG32(GHW_CFG2)
-#define REG_GHW_CFG3        REG32(GHW_CFG3)
-#define REG_GHW_CFG4        REG32(GHW_CFG4)
-#define REG_GDFIFO_CFG      REG32(GDFIFO_CFG)
-#define REG_GDIEP_TXF(n)    REG32(GDEIP_TXF(n))
-#define REG_PCGC_CTL        REG32(PCGC_CTL)
-/* Device Regs define */
-#define EP_FIFO(n)      (OTG_BASE + (n+1)*0x1000) // FiX ME
-#define REG_EP_FIFO(n)      REG32(EP_FIFO(n))
-
-
-#define OTG_DCFG        (OTG_BASE + 0x800)
-#define OTG_DCTL        (OTG_BASE + 0x804)
-#define OTG_DSTS        (OTG_BASE + 0x808)
-#define DIEP_MASK       (OTG_BASE + 0x810)
-#define DOEP_MASK       (OTG_BASE + 0x814)
-#define OTG_DAINT       (OTG_BASE + 0x818)
-#define DAINT_MASK      (OTG_BASE + 0x81c)
-
-#define DIEP_EMPMSK     (OTG_BASE + 0x834)
-
-
-/* It's used in OTG_MULT_PROC_INTRPT = 1
-#define DEACH_INT       (OTG_BASE + 0x838)
-#define DEACH_INTMASK       (OTG_BASE + 0x83c)
-#define DIEP0_INTMASK       (OTG_BASE + 0x840)
-#define DIEP1_INTMASK       (OTG_BASE + 0x844)
-#define DOEP0_INTMASK       (OTG_BASE + 0x880)
-#define DOEP1_INTMASK       (OTG_BASE + 0x884)
-*/
-
-#define DIEP_CTL(n)     (OTG_BASE + (0x900 + (n)*0x20))
-#define DOEP_CTL(n)     (OTG_BASE + (0xb00 + (n)*0x20))
-
-#define DIEP_INT(n)     (OTG_BASE + (0x908 + (n)*0x20))
-#define DOEP_INT(n)     (OTG_BASE + (0xb08 + (n)*0x20))
-
-#define DIEP_SIZE(n)        (OTG_BASE + (0x910 + (n)*0x20))
-#define DOEP_SIZE(n)        (OTG_BASE + (0xb10 + (n)*0x20))
-
-#define DIEP_TXFSTS(n)      (OTG_BASE + (0x918 + (n)*0x20))
-
-#define DIEP_DMA(n)         (OTG_BASE + (0x914 + (n)*0x20))
-#define DOEP_DMA(n)         (OTG_BASE + (0xb14 + (n)*0x20))
-
-#define REG_OTG_DCFG        REG32(OTG_DCFG)
-#define REG_OTG_DCTL        REG32(OTG_DCTL)
-#define REG_OTG_DSTS        REG32(OTG_DSTS)
-#define REG_DIEP_MASK       REG32(DIEP_MASK)
-#define REG_DOEP_MASK       REG32(DOEP_MASK)
-#define REG_OTG_DAINT       REG32(OTG_DAINT)
-#define REG_DAINT_MASK      REG32(DAINT_MASK)
-#define REG_DIEP_EMPMSK     REG32(DIEP_EMPMSK)
-
-#define REG_DIEP_CTL(n)     REG32(DIEP_CTL(n))
-#define REG_DOEP_CTL(n)     REG32(DOEP_CTL(n))
-
-#define REG_DIEP_INT(n)     REG32(DIEP_INT(n))
-#define REG_DOEP_INT(n)     REG32(DOEP_INT(n))
-
-#define REG_DIEP_SIZE(n)    REG32(DIEP_SIZE(n))
-#define REG_DOEP_SIZE(n)    REG32(DOEP_SIZE(n))
-
-#define REG_DIEP_TXFSTS(n)  REG32(DIEP_TXFSTS(n))
-
-#define REG_DIEP_DMA(n)     REG32(DIEP_DMA(n))
-#define REG_DOEP_DMA(n)     REG32(DOEP_DMA(n))
-
-/* Regs macro define */
-/*************************************************/
-#define AHBCFG_TXFE_LVL     BIT7
-#define AHBCFG_DMA_ENA      BIT5
-#define AHBCFG_GLOBLE_INTRMASK  BIT0
-#define USBCFG_FORCE_DEVICE BIT30
-#define USBCFG_TRDTIME_MASK (0xf << 10)
-#define USBCFG_TRDTIME_9    (9 << 10)
-#define USBCFG_TRDTIME_6    (6 << 10)
-
-/* GRSTCTL */
-#define RSTCTL_AHB_IDLE     BIT31
-#define RSTCTL_TXFNUM_ALL   (0x10 << 6)
-#define RSTCTL_TXFIFO_FLUSH BIT5
-#define RSTCTL_RXFIFO_FLUSH BIT4
-#define RSTCTL_INTK_FLUSH   BIT3
-#define RSTCTL_FRMCNT_RST   BIT2
-#define RSTCTL_CORE_RST     BIT0
-
-/* GINTMSK */
-#define GINTMSK_RSUME_DETE  BIT31
-#define GINTMSK_CONID_STSCHG    BIT28
-#define GINTMSK_RESET_DETE  BIT23
-#define GINTMSK_FETCH_SUSPEND   BIT22
-#define GINTMSK_OEP_INTR    BIT19
-#define GINTMSK_IEP_INTR    BIT18
-#define GINTMSK_EP_MISMATCH BIT17
-#define GINTMSK_ENUM_DONE   BIT13
-#define GINTMSK_USB_RESET   BIT12
-#define GINTMSK_USB_SUSPEND BIT11
-#define GINTMSK_USB_EARLYSUSPEND    BIT10
-#define GINTMSK_I2C_INT     BIT9
-#define GINTMSK_ULPK_CKINT  BIT8
-#define GINTMSK_GOUTNAK_EFF BIT7
-#define GINTMSK_GINNAK_EFF  BIT6
-#define GINTMSK_NPTXFIFO_EMPTY  BIT5
-#define GINTMSK_RXFIFO_NEMPTY   BIT4
-#define GINTMSK_START_FRAM  BIT3
-#define GINTMSK_OTG_INTR    BIT2
-#define GINTMSK_MODE_MISMATCH   BIT1
-
-/* GINTSTS */
-#define GINTSTS_RSUME_DETE  BIT31
-#define GINTSTS_CONID_STSCHG    BIT28
-#define GINTSTS_RESET_DETE  BIT23
-#define GINTSTS_FETCH_SUSPEND   BIT22
-#define GINTSTS_OEP_INTR    BIT19
-#define GINTSTS_IEP_INTR    BIT18
-#define GINTSTS_EP_MISMATCH BIT17
-#define GINTSTS_ENUM_DONE   BIT13
-#define GINTSTS_USB_RESET   BIT12
-#define GINTSTS_USB_SUSPEND BIT11
-#define GINTSTS_USB_EARLYSUSPEND    BIT10
-#define GINTSTS_I2C_INT     BIT9
-#define GINTSTS_ULPK_CKINT  BIT8
-#define GINTSTS_GOUTNAK_EFF BIT7
-#define GINTSTS_GINNAK_EFF  BIT6
-#define GINTSTS_NPTXFIFO_EMPTY  BIT5
-#define GINTSTS_RXFIFO_NEMPTY   BIT4
-#define GINTSTS_START_FRAM  BIT3
-#define GINTSTS_OTG_INTR    BIT2
-#define GINTSTS_MODE_MISMATCH   BIT1
-
-/* DCTL */
-#define DCTL_CGOUTNAK       BIT10
-#define DCTL_CLR_GNPINNAK   BIT8
-#define DCTL_SGNPINNAK      BIT7
-#define DCTL_SOFT_DISCONN   BIT1
-#define DCTL_SGOUTNAK       BIT9
-/* DCFG */
-#define DCFG_DEV_ADDR_MASK  (0x7f << 4)
-#define DCFG_DEV_ADDR_BIT   4
-#define DCFG_DEV_DESC_DMA   (1 << 23)
-/* DSTS */
-#define DSTS_ERRATIC_ERROR          BIT3
-#define DSTS_ENUM_SPEED_MASK        (0x3 << 1)
-#define DSTS_ENUM_SPEED_BIT         BIT1
-#define DSTS_ENUM_SPEED_HIGH        (0x0 << 1)
-#define DSTS_ENUM_SPEED_FULL_30OR60 (0x1 << 1)
-#define DSTS_ENUM_SPEED_LOW         (0x2 << 1)
-#define DSTS_ENUM_SPEED_FULL_48     (0x3 << 1)
-
-/* GRXSTSR/GRXSTSP */
-#define GRXSTSP_PKSTS_MASK      (0xf << 17)
-#define GRXSTSP_PKSTS_GOUT_NAK      (0x1 << 17)
-#define GRXSTSP_PKSTS_GOUT_RECV     (0x2 << 17)
-#define GRXSTSP_PKSTS_TX_COMP       (0x3 << 17)
-#define GRXSTSP_PKSTS_SETUP_COMP    (0x4 << 17)
-#define GRXSTSP_PKSTS_SETUP_RECV    (0x6 << 17)
-#define GRXSTSP_BYTE_CNT_MASK       (0x7ff << 4)
-#define GRXSTSP_BYTE_CNT_BIT        4
-#define GRXSTSP_EPNUM_MASK      (0xf)
-#define GRXSTSP_EPNUM_BIT       BIT0
-
-
-/* DIOEPCTL */
-// ep0
-#define DEP_EP0_MAXPKET_SIZE    64
-#define DEP_EP0_MPS_64      (0x0)
-#define DEP_EP0_MPS_32      (0x1)
-#define DEP_EP0_MPS_16      (0x2)
-#define DEP_EP0_MPS_8       (0x3)
-
-#define DEP_ENA_BIT     BIT31
-#define DEP_DISENA_BIT      BIT30
-#define DEP_SET_NAK         BIT27
-#define DEP_CLEAR_NAK       BIT26
-#define DEP_SET_STALL       BIT21
-#define DEP_TYPE_MASK       (0x3 << 18)
-#define DEP_TYPE_CNTL       (0x0 << 18)
-#define DEP_TYPE_ISO        (0x1 << 18)
-#define DEP_TYPE_BULK       (0x2 << 18)
-#define DEP_TYPE_INTR       (0x3 << 18)
-#define USB_ACTIVE_EP       BIT15
-#define DEP_PKTSIZE_MASK    0x7ff
-#define DEP_FS_PKTSIZE      64
-#define DEP_HS_PKTSIZE      512
-
-/* DIOEPINT */
-#define DEP_NYET_INT        BIT14
-#define DEP_NAK_INT     BIT13
-#define DEP_BABBLE_ERR_INT  BIT12
-#define DEP_PKT_DROP_STATUS BIT11
-#define DEP_BNA_INT     BIT9
-#define DEP_TXFIFO_UNDRN    BIT8        // Only for INEP
-#define DEP_OUTPKT_ERR      BIT8        // Only for OUTEP
-#define DEP_TXFIFO_EMPTY    BIT7
-#define DEP_INEP_NAKEFF     BIT6        // Only for INEP
-#define DEP_B2B_SETUP_RECV  BIT6        // Only for OUTEP0
-#define DEP_INTOKEN_EPMISATCH   BIT5        // Only for INEP
-#define DEP_STATUS_PHASE_RECV   BIT5        // Only for OUTEP0
-#define DEP_INTOKEN_RECV_TXFIFO_EMPTY   BIT4    // Only for INEP
-#define DEP_OUTTOKEN_RECV_EPDIS BIT4        // Only for OUTEP
-#define DEP_TIME_OUT        BIT3        // Only for INEP
-#define DEP_SETUP_PHASE_DONE    BIT3        // Only for OUTEP0
-#define DEP_AHB_ERR     BIT2
-#define DEP_EPDIS_INT       BIT1
-#define DEP_XFER_COMP       BIT0        // Used by INEP and OUTEP
-
-/* DOEPSIZ0 */
-#define DOEPSIZE0_SUPCNT_1  (0x1 << 29)
-#define DOEPSIZE0_SUPCNT_2  (0x2 << 29)
-#define DOEPSIZE0_SUPCNT_3  (0x3 << 29)
-#define DOEPSIZE0_PKTCNT_BIT    BIT19
-
-
-#define DEP_RXFIFO_SIZE     1064
-#define DEP_NPTXFIFO_SIZE   1024
-#define DEP_DTXFIFO_SIZE    768
-
-
-#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE    0
-#define DWC_GAHBCFG_INT_DMA_BURST_INCR      1
-#define DWC_GAHBCFG_INT_DMA_BURST_INCR4     3
-#define DWC_GAHBCFG_INT_DMA_BURST_INCR8     5
-#define DWC_GAHBCFG_INT_DMA_BURST_INCR16    7
-
-#define DWC_GAHBCFG_EXT_DMA_BURST_1word     0x0
-#define DWC_GAHBCFG_EXT_DMA_BURST_4word     0x1
-#define DWC_GAHBCFG_EXT_DMA_BURST_8word     0x2
-#define DWC_GAHBCFG_EXT_DMA_BURST_16word    0x3
-#define DWC_GAHBCFG_EXT_DMA_BURST_32word    0x4
-#define DWC_GAHBCFG_EXT_DMA_BURST_64word    0x5
-#define DWC_GAHBCFG_EXT_DMA_BURST_128word   0x6
-#define DWC_GAHBCFG_EXT_DMA_BURST_256word   0x7
-
-#define DEP_NUM         2
-
-#if 0
-#define UTMI_PHY_WIDTH      8
-#else
-#define UTMI_PHY_WIDTH      16
-#endif
-
-#endif /* _X1000_OTG_DWC_H_ */
diff --git a/libcpu/mips/x1000/x1000_slcdc.h b/libcpu/mips/x1000/x1000_slcdc.h
deleted file mode 100644
index fab76ffad9..0000000000
--- a/libcpu/mips/x1000/x1000_slcdc.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * File      : x1000_slcdc.h
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017��3��20��     Urey         the first version
- */
-#ifndef _X1000_SLCDC_H_
-#define _X1000_SLCDC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*************************************************************************
- * SLCD (Smart LCD Controller)
- *************************************************************************/
-#define LCDC0_BASE  LCD_BASE
-
-#define SLCDC_CFG       (LCDC0_BASE + 0xA0)  /* SLCDC Configure Register */
-#define SLCDC_CTRL      (LCDC0_BASE + 0xA4)  /* SLCDC Control Register */
-#define SLCDC_STATE     (LCDC0_BASE + 0xA8)  /* SLCDC Status Register */
-#define SLCDC_DATA      (LCDC0_BASE + 0xAC)  /* SLCDC Data Register */
-
-#define SLCDC_CFG_NEW   (LCDC0_BASE + 0xB8)
-#define SLCDC_WTIME     (LCDC0_BASE + 0xB0)
-#define SLCDC_TAS       (LCDC0_BASE + 0xB4)
-#define SLCDC_SLOW_TIME (LCDC0_BASE + 0xBC)
-
-/* SLCDC Configure Register */
-#define SLCDC_CFG_DWIDTH_BIT            10
-#define SLCDC_CFG_DWIDTH_MASK           (0x7 << SLCDC_CFG_DWIDTH_BIT)
-#define SLCDC_CFG_DWIDTH_18BIT          (0 << SLCDC_CFG_DWIDTH_BIT)
-#define SLCDC_CFG_DWIDTH_16BIT          (1 << SLCDC_CFG_DWIDTH_BIT)
-#define SLCDC_CFG_DWIDTH_8BIT_x3        (2 << SLCDC_CFG_DWIDTH_BIT)
-#define SLCDC_CFG_DWIDTH_8BIT_x2        (3 << SLCDC_CFG_DWIDTH_BIT)
-#define SLCDC_CFG_DWIDTH_8BIT_x1        (4 << SLCDC_CFG_DWIDTH_BIT)
-#define SLCDC_CFG_DWIDTH_24BIT          (5 << SLCDC_CFG_DWIDTH_BIT)
-#define SLCDC_CFG_DWIDTH_9BIT_x2        (7 << SLCDC_CFG_DWIDTH_BIT)
-#define SLCDC_CFG_CWIDTH_BIT            (8)
-#define SLCDC_CFG_CWIDTH_MASK           (0x3 << SLCDC_CFG_CWIDTH_BIT)
-#define SLCDC_CFG_CWIDTH_16BIT          (0 << SLCDC_CFG_CWIDTH_BIT)
-#define SLCDC_CFG_CWIDTH_8BIT           (1 << SLCDC_CFG_CWIDTH_BIT)
-#define SLCDC_CFG_CWIDTH_18BIT          (2 << SLCDC_CFG_CWIDTH_BIT)
-#define SLCDC_CFG_CWIDTH_24BIT          (3 << SLCDC_CFG_CWIDTH_BIT)
-#define SLCDC_CFG_CS_ACTIVE_LOW         (0 << 4)
-#define SLCDC_CFG_CS_ACTIVE_HIGH        (1 << 4)
-#define SLCDC_CFG_RS_CMD_LOW            (0 << 3)
-#define SLCDC_CFG_RS_CMD_HIGH           (1 << 3)
-#define SLCDC_CFG_CLK_ACTIVE_FALLING    (0 << 1)
-#define SLCDC_CFG_CLK_ACTIVE_RISING     (1 << 1)
-#define SLCDC_CFG_TYPE_PARALLEL         (0 << 0)
-#define SLCDC_CFG_TYPE_SERIAL           (1 << 0)
-
-/* SLCD New Configure Register */
-#define SLCDC_NEW_CFG_DWIDTH_BIT        13
-#define SLCDC_NEW_CFG_DWIDTH_MASK       (0x7 << SLCDC_NEW_CFG_DWIDTH_BIT)
-#define SLCDC_NEW_CFG_DWIDTH_8BIT       (0 << SLCDC_NEW_CFG_DWIDTH_BIT)
-#define SLCDC_NEW_CFG_DWIDTH_9BIT       (1 << SLCDC_NEW_CFG_DWIDTH_BIT)
-#define SLCDC_NEW_CFG_DWIDTH_16BIT      (2 << SLCDC_NEW_CFG_DWIDTH_BIT)
-#define SLCDC_NEW_CFG_DWIDTH_18BIT      (3 << SLCDC_NEW_CFG_DWIDTH_BIT)
-#define SLCDC_NEW_CFG_DWIDTH_24BIT      (4 << SLCDC_NEW_CFG_DWIDTH_BIT)
-#define SLCDC_NEW_CFG_6800_MD           (1 << 11)
-#define SLCDC_NEW_CFG_CMD_9BIT          (1 << 10)       /* only use in old slcd */
-#define SLCDC_NEW_CFG_CMD_16BIT         (0 << 10)       /* only use in old slcd */
-#define SLCDC_NEW_CFG_DTIME_BIT         8
-#define SLCDC_NEW_CFG_DTIME_MASK        (0x3 << SLCDC_NEW_CFG_DTIME_BIT)
-#define SLCDC_NEW_CFG_DTIME_ONCE        (0 << SLCDC_NEW_CFG_DTIME_BIT)
-#define SLCDC_NEW_CFG_DTIME_TWICE       (1 << SLCDC_NEW_CFG_DTIME_BIT)
-#define SLCDC_NEW_CFG_DTIME_THREE       (2 << SLCDC_NEW_CFG_DTIME_BIT)
-#define SLCDC_NEW_CFG_CS_HIGH_IDLE      (0 << 5)
-#define SLCDC_NEW_CFG_CS_LOW_IDLE       (1 << 5)
-#define SLCDC_NEW_CFG_RS_CMD_LOW        (0 << 4)
-#define SLCDC_NEW_CFG_RS_CMD_HIGH       (1 << 4)
-#define SLCDC_NEW_CFG_CLK_ACTIVE_FALLING        (0 << 3)
-#define SLCDC_NEW_CFG_CLK_ACTIVE_RISING (1 << 3)
-#define SLCDC_NEW_CFG_DTYPE_PARALLEL    (0 << 2)
-#define SLCDC_NEW_CFG_DTYPE_SERIAL      (1 << 2)
-#define SLCDC_NEW_CFG_CTYPE_PARALLEL    (0 << 1)
-#define SLCDC_NEW_CFG_CTYPE_SERIAL      (1 << 1)
-#define SLCDC_NEW_CFG_FMT_CONV_EN       (1 << 0)
-
-/* SLCD Control Register */
-#define SLCDC_CTRL_TE_INV           	(1 << 9)
-#define SLCDC_CTRL_NOT_USE_TE           (1 << 8)
-#define SLCDC_CTRL_DCSI_SEL             (1 << 7)
-#define SLCDC_CTRL_MIPI_MODE            (1 << 6)
-#define SLCDC_CTRL_NEW_MODE             (1 << 5)
-#define SLCDC_CTRL_FAST_MODE            (1 << 4)
-#define SLCDC_CTRL_GATE_MASK            (1 << 3)
-#define SLCDC_CTRL_DMA_MODE             (1 << 2)
-#define SLCDC_CTRL_DMA_START            (1 << 1)
-#define SLCDC_CTRL_DMA_EN               (1 << 0)
-
-/* SLCD Status Register */
-#define SLCDC_STATE_BUSY                (1 << 0)
-
-/* SLCD Data Register */
-#define SLCDC_DATA_RS_DATA              (0 << 30)
-#define SLCDC_DATA_RS_COMMAND           (1 << 30)
-
-/*************************************************************************
- * LCDC (LCD Controller)
- *************************************************************************/
-
-#define LCDC_CFG    (LCDC0_BASE + 0x00)
-#define LCDC_CTRL   (LCDC0_BASE + 0x30)
-#define LCDC_STATE  (LCDC0_BASE + 0x34)
-#define LCDC_OSDC   (LCDC0_BASE + 0x100)
-#define LCDC_OSDCTRL    (LCDC0_BASE + 0x104)
-#define LCDC_OSDS   (LCDC0_BASE + 0x108)
-#define LCDC_BGC0   (LCDC0_BASE + 0x10C)
-#define LCDC_BGC1   (LCDC0_BASE + 0x2C4)
-#define LCDC_KEY0   (LCDC0_BASE + 0x110)
-#define LCDC_KEY1   (LCDC0_BASE + 0x114)
-#define LCDC_ALPHA  (LCDC0_BASE + 0x118)
-#define LCDC_RGBC   (LCDC0_BASE + 0x90)
-#define LCDC_VAT    (LCDC0_BASE + 0x0c)
-#define LCDC_DAH    (LCDC0_BASE + 0x10)
-#define LCDC_DAV    (LCDC0_BASE + 0x14)
-#define LCDC_XYP0   (LCDC0_BASE + 0x120)
-#define LCDC_XYP1   (LCDC0_BASE + 0x124)
-#define LCDC_SIZE0  (LCDC0_BASE + 0x128)
-#define LCDC_SIZE1  (LCDC0_BASE + 0x12C)
-#define LCDC_VSYNC  (LCDC0_BASE + 0x04)
-#define LCDC_HSYNC  (LCDC0_BASE + 0x08)
-#define LCDC_PS     (LCDC0_BASE + 0x18)
-#define LCDC_CLS    (LCDC0_BASE + 0x1c)
-#define LCDC_SPL    (LCDC0_BASE + 0x20)
-#define LCDC_REV    (LCDC0_BASE + 0x24)
-#define LCDC_IID    (LCDC0_BASE + 0x38)
-#define LCDC_DA0    (LCDC0_BASE + 0x40)
-#define LCDC_SA0    (LCDC0_BASE + 0x44)
-#define LCDC_FID0   (LCDC0_BASE + 0x48)
-#define LCDC_CMD0   (LCDC0_BASE + 0x4c)
-#define LCDC_DA1    (LCDC0_BASE + 0x50)
-#define LCDC_SA1    (LCDC0_BASE + 0x54)
-#define LCDC_FID1   (LCDC0_BASE + 0x58)
-#define LCDC_CMD1   (LCDC0_BASE + 0x5c)
-#define LCDC_OFFS0  (LCDC0_BASE + 0x60)
-#define LCDC_PW0    (LCDC0_BASE + 0x64)
-#define LCDC_CNUM0  (LCDC0_BASE + 0x68)
-#define LCDC_DESSIZE0   (LCDC0_BASE + 0x6C)
-#define LCDC_OFFS1  (LCDC0_BASE + 0x70)
-#define LCDC_PW1    (LCDC0_BASE + 0x74)
-#define LCDC_CNUM1  (LCDC0_BASE + 0x78)
-#define LCDC_DESSIZE1   (LCDC0_BASE + 0x7C)
-#define LCDC_PCFG   (LCDC0_BASE + 0x2C0)
-#define LCDC_CPOS1      (0x78)
-#define LCDC_DUAL_CTRL      (0x2c8)
-#define LCDC_ENH_CFG        (0x400)
-#define LCDC_ENH_CSCCFG     (0x404)
-#define LCDC_ENH_LUMACFG    (0x408)
-#define LCDC_ENH_CHROCFG0   (0x40c)
-#define LCDC_ENH_CHROCFG1   (0x410)
-#define LCDC_ENH_DITHERCFG  (0x414)
-#define LCDC_ENH_STATUS     (0x418)
-#define LCDC_ENH_GAMMA      (0x800)
-#define LCDC_ENH_VEE        (0x1000)
-
-/* LCD Configure Register */
-#define LCDC_CFG_LCDPIN_BIT 31
-#define LCDC_CFG_LCDPIN_MASK    (0x1 << LCDC_CFG_LCDPIN_BIT)
-#define LCDC_CFG_LCDPIN_LCD (0x0 << LCDC_CFG_LCDPIN_BIT)
-#define LCDC_CFG_LCDPIN_SLCD    (0x1 << LCDC_CFG_LCDPIN_BIT)
-#define LCDC_CFG_TVEPEH     (1 << 30)
-#define LCDC_CFG_NEWDES     (1 << 28)
-#define LCDC_CFG_PALBP      (1 << 27)
-#define LCDC_CFG_TVEN       (1 << 26)
-#define LCDC_CFG_RECOVER    (1 << 25)
-#define LCDC_CFG_PSM        (1 << 23)
-#define LCDC_CFG_CLSM       (1 << 22)
-#define LCDC_CFG_SPLM       (1 << 21)
-#define LCDC_CFG_REVM       (1 << 20)
-#define LCDC_CFG_HSYNM      (1 << 19)
-#define LCDC_CFG_PCLKM      (1 << 18)
-#define LCDC_CFG_INVDAT     (1 << 17)
-#define LCDC_CFG_SYNDIR_IN  (1 << 16)
-#define LCDC_CFG_PSP        (1 << 15)
-#define LCDC_CFG_CLSP       (1 << 14)
-#define LCDC_CFG_SPLP       (1 << 13)
-#define LCDC_CFG_REVP       (1 << 12)
-#define LCDC_CFG_HSP        (1 << 11)
-#define LCDC_CFG_PCP        (1 << 10)
-#define LCDC_CFG_DEP        (1 << 9)
-#define LCDC_CFG_VSP        (1 << 8)
-#define LCDC_CFG_MODE_TFT_18BIT     (1 << 7)
-#define LCDC_CFG_MODE_TFT_16BIT     (0 << 7)
-#define LCDC_CFG_MODE_TFT_24BIT     (1 << 6)
-#define LCDC_CFG_MODE_BIT   0
-#define LCDC_CFG_MODE_MASK  (0x0f << LCDC_CFG_MODE_BIT)
-#define LCDC_CFG_MODE_GENERIC_TFT   (0 << LCDC_CFG_MODE_BIT)
-#define LCDC_CFG_MODE_SPECIAL_TFT_1 (1 << LCDC_CFG_MODE_BIT)
-#define LCDC_CFG_MODE_SPECIAL_TFT_2 (2 << LCDC_CFG_MODE_BIT)
-#define LCDC_CFG_MODE_SPECIAL_TFT_3 (3 << LCDC_CFG_MODE_BIT)
-#define LCDC_CFG_MODE_NONINTER_CCIR656  (4 << LCDC_CFG_MODE_BIT)
-#define LCDC_CFG_MODE_INTER_CCIR656 (6 << LCDC_CFG_MODE_BIT)
-#define LCDC_CFG_MODE_SERIAL_TFT    (12 << LCDC_CFG_MODE_BIT)
-#define LCDC_CFG_MODE_LCM       (13 << LCDC_CFG_MODE_BIT)
-/* LCD Control Register */
-#define LCDC_CTRL_PINMD     (1 << 31)
-#define LCDC_CTRL_BST_BIT   28
-#define LCDC_CTRL_BST_MASK  (0x7 << LCDC_CTRL_BST_BIT)
-#define LCDC_CTRL_BST_4     (0 << LCDC_CTRL_BST_BIT)
-#define LCDC_CTRL_BST_8     (1 << LCDC_CTRL_BST_BIT)
-#define LCDC_CTRL_BST_16    (2 << LCDC_CTRL_BST_BIT)
-#define LCDC_CTRL_BST_32    (3 << LCDC_CTRL_BST_BIT)
-#define LCDC_CTRL_BST_64    (4 << LCDC_CTRL_BST_BIT)
-#define LCDC_CTRL_RGB565        (0 << 27)
-#define LCDC_CTRL_RGB555        (1 << 27)
-#define LCDC_CTRL_OFUP      (1 << 26)
-#define LCDC_CTRL_PDD_BIT   16
-#define LCDC_CTRL_PDD_MASK  (0xff << LCDC_CTRL_PDD_BIT)
-#define LCDC_CTRL_DACTE     (1 << 14)
-#define LCDC_CTRL_EOFM      (1 << 13)
-#define LCDC_CTRL_SOFM      (1 << 12)
-#define LCDC_CTRL_OFUM      (1 << 11)
-#define LCDC_CTRL_IFUM0     (1 << 10)
-#define LCDC_CTRL_IFUM1     (1 << 9)
-#define LCDC_CTRL_LDDM      (1 << 8)
-#define LCDC_CTRL_QDM       (1 << 7)
-#define LCDC_CTRL_BEDN      (1 << 6)
-#define LCDC_CTRL_PEDN      (1 << 5)
-#define LCDC_CTRL_DIS       (1 << 4)
-#define LCDC_CTRL_ENA       (1 << 3)
-#define LCDC_CTRL_BPP_BIT   0
-#define LCDC_CTRL_BPP_MASK  (0x07 << LCDC_CTRL_BPP_BIT)
-#define LCDC_CTRL_BPP_1     (0 << LCDC_CTRL_BPP_BIT)
-#define LCDC_CTRL_BPP_2     (1 << LCDC_CTRL_BPP_BIT)
-#define LCDC_CTRL_BPP_4     (2 << LCDC_CTRL_BPP_BIT)
-#define LCDC_CTRL_BPP_8     (3 << LCDC_CTRL_BPP_BIT)
-#define LCDC_CTRL_BPP_16    (4 << LCDC_CTRL_BPP_BIT)
-#define LCDC_CTRL_BPP_18_24 (5 << LCDC_CTRL_BPP_BIT)
-#define LCDC_CTRL_BPP_CMPS_24   (6 << LCDC_CTRL_BPP_BIT)
-#define LCDC_CTRL_BPP_30    (7 << LCDC_CTRL_BPP_BIT)
-/* LCD Status Register */
-#define LCDC_STATE_QD       (1 << 7)
-#define LCDC_STATE_EOF      (1 << 5)
-#define LCDC_STATE_SOF      (1 << 4)
-#define LCDC_STATE_OFU      (1 << 3)
-#define LCDC_STATE_IFU0     (1 << 2)
-#define LCDC_STATE_IFU1     (1 << 1)
-#define LCDC_STATE_LDD      (1 << 0)
-/* OSD Configure Register */
-#define LCDC_OSDC_PREMULTI1     (1 << 23)
-#define LCDC_OSDC_COEF_SLE1_BIT     21
-#define LCDC_OSDC_COEF_SLE1_MASK    (0x03 << LCDC_OSDC_COEF_SLE1_BIT)
-#define LCDC_OSDC_COEF_SLE1_0       (0 << LCDC_OSDC_COEF_SLE1_BIT)
-#define LCDC_OSDC_COEF_SLE1_1       (1 << LCDC_OSDC_COEF_SLE1_BIT)
-#define LCDC_OSDC_COEF_SLE1_2       (2 << LCDC_OSDC_COEF_SLE1_BIT)
-#define LCDC_OSDC_COEF_SLE1_3       (3 << LCDC_OSDC_COEF_SLE1_BIT)
-#define LCDC_OSDC_PREMULTI0     (1 << 20)
-#define LCDC_OSDC_COEF_SLE0_BIT     18
-#define LCDC_OSDC_COEF_SLE0_MASK    (0x03 << LCDC_OSDC_COEF_SLE0_BIT)
-#define LCDC_OSDC_COEF_SLE0_0       (0 << LCDC_OSDC_COEF_SLE0_BIT)
-#define LCDC_OSDC_COEF_SLE0_1       (1 << LCDC_OSDC_COEF_SLE0_BIT)
-#define LCDC_OSDC_COEF_SLE0_2       (2 << LCDC_OSDC_COEF_SLE0_BIT)
-#define LCDC_OSDC_COEF_SLE0_3       (3 << LCDC_OSDC_COEF_SLE0_BIT)
-#define LCDC_OSDC_ALPHAMD1      (1 << 17)
-#define LCDC_OSDC_SOFM1     (1 << 15)
-#define LCDC_OSDC_EOFM1     (1 << 14)
-#define LCDC_OSDC_SOFM0     (1 << 11)
-#define LCDC_OSDC_EOFM0     (1 << 10)
-#define LCDC_OSDC_DENDM     (1 << 9)
-#define LCDC_OSDC_F1EN      (1 << 4)
-#define LCDC_OSDC_F0EN      (1 << 3)
-#define LCDC_OSDC_ALPHAEN   (1 << 2)
-#define LCDC_OSDC_ALPHAMD0  (1 << 1)
-#define LCDC_OSDC_OSDEN     (1 << 0)
-/* OSD Controll Register */
-#define LCDC_OSDCTRL_IPU_CLKEN  (1 << 15)
-#define LCDC_OSDCTRL_RGB0_RGB565    (0 << 5)
-#define LCDC_OSDCTRL_RGB0_RGB555    (1 << 5)
-#define LCDC_OSDCTRL_RGB1_RGB565    (0 << 4)
-#define LCDC_OSDCTRL_RGB1_RGB555    (1 << 4)
-#define LCDC_OSDCTRL_BPP_BIT    0
-#define LCDC_OSDCTRL_BPP_MASK   (0x7<<LCDC_OSDCTRL_BPP_BIT)
-#define LCDC_OSDCTRL_BPP_15_16  (4 << LCDC_OSDCTRL_BPP_BIT)
-#define LCDC_OSDCTRL_BPP_18_24  (5 << LCDC_OSDCTRL_BPP_BIT)
-#define LCDC_OSDCTRL_BPP_CMPS_24    (6 << LCDC_OSDCTRL_BPP_BIT)
-#define LCDC_OSDCTRL_BPP_30     (7 << LCDC_OSDCTRL_BPP_BIT)
-/* OSD State Register */
-#define LCDC_OSDS_SOF1      (1 << 15)
-#define LCDC_OSDS_EOF1      (1 << 14)
-#define LCDC_OSDS_SOF0      (1 << 11)
-#define LCDC_OSDS_EOF0      (1 << 10)
-#define LCDC_OSDS_DEND      (1 << 8)
-/* Background 0 or Background 1 Color Register */
-#define LCDC_BGC_RED_OFFSET 16
-#define LCDC_BGC_RED_MASK   (0xFF << LCDC_BGC_RED_OFFSET)
-#define LCDC_BGC_GREEN_OFFSET    8
-#define LCDC_BGC_GREEN_MASK (0xFF << LCDC_BGC_GREEN_OFFSET)
-#define LCDC_BGC_BLUE_OFFSET    0
-#define LCDC_BGC_BLUE_MASK  (0xFF << LCDC_BGC_BLUE_OFFSET)
-/* Foreground 0 or Foreground 1 Color Key Register */
-#define LCDC_KEY_KEYEN      (1 << 31)
-#define LCDC_KEY_KEYMD      (1 << 30)
-#define LCDC_KEY_RED_OFFSET 16
-#define LCDC_KEY_RED_MASK   (0xFF << LCDC_KEY_RED_OFFSET)
-#define LCDC_KEY_GREEN_OFFSET   8
-#define LCDC_KEY_GREEN_MASK (0xFF << LCDC_KEY_GREEN_OFFSET)
-#define LCDC_KEY_BLUE_OFFSET    0
-#define LCDC_KEY_BLUE_MASK  (0xFF << LCDC_KEY_BLUE_OFFSET)
-#define LCDC_KEY_MASK       (LCDC_KEY_RED_MASK | LCDC_KEY_GREEN_MASK\
-/* ALPHA Register */
-#define LCDC_ALPHA1_OFFSET  8
-#define LCDC_ALPHA1_MASK        (0xFF << LCDC_ALPHA1_OFFSET)
-#define LCDC_ALPHA0_OFFSET  0
-#define LCDC_ALPHA0_MASK        (0xFF << LCDC_ALPHA0_OFFSET)
-/* IPU Restart Register */
-#define LCDC_IPUR_IPUREN        (1 << 31)
-#define LCDC_IPUR_IPURMASK  (0xFFFFFF)
-/* RGB Control Register */
-#define LCDC_RGBC_RGBDM     (1 << 15)
-#define LCDC_RGBC_DMM       (1 << 14)
-#define LCDC_RGBC_RGBFMT    (1 << 7)
-#define LCDC_RGBC_ODDRGB_BIT    4
-#define LCDC_RGBC_ODDRGB_MASK   (0x7 << LCDC_RGBC_ODDRGB_BIT)
-#define LCDC_RGBC_ODD_RGB   (0 << LCDC_RGBC_ODDRGB_BIT)
-#define LCDC_RGBC_ODD_RBG   (1 << LCDC_RGBC_ODDRGB_BIT)
-#define LCDC_RGBC_ODD_GRB   (2 << LCDC_RGBC_ODDRGB_BIT)
-#define LCDC_RGBC_ODD_GBR   (3 << LCDC_RGBC_ODDRGB_BIT)
-#define LCDC_RGBC_ODD_BRG   (4 << LCDC_RGBC_ODDRGB_BIT)
-#define LCDC_RGBC_ODD_BGR   (5 << LCDC_RGBC_ODDRGB_BIT)
-#define LCDC_RGBC_EVENRGB_BIT   0
-#define LCDC_RGBC_EVENRGB_MASK  (0x7<<LCDC_RGBC_EVENRGB_BIT)
-#define LCDC_RGBC_EVEN_RGB  0
-#define LCDC_RGBC_EVEN_RBG  1
-#define LCDC_RGBC_EVEN_GRB  2
-#define LCDC_RGBC_EVEN_GBR  3
-#define LCDC_RGBC_EVEN_BRG  4
-#define LCDC_RGBC_EVEN_BGR  5
-/* Vertical Synchronize Register */
-#define LCDC_VSYNC_VPS_BIT  16
-#define LCDC_VSYNC_VPS_MASK (0xfff << LCDC_VSYNC_VPS_BIT)
-#define LCDC_VSYNC_VPE_BIT  0
-#define LCDC_VSYNC_VPE_MASK (0xfff << LCDC_VSYNC_VPE_BIT)
-/* Horizontal Synchronize Register */
-#define LCDC_HSYNC_HPS_BIT  16
-#define LCDC_HSYNC_HPS_MASK (0xfff << LCDC_HSYNC_HPS_BIT)
-#define LCDC_HSYNC_HPE_BIT  0
-#define LCDC_HSYNC_HPE_MASK (0xfff << LCDC_HSYNC_HPE_BIT)
-/* Virtual Area Setting Register */
-#define LCDC_VAT_HT_BIT     16
-#define LCDC_VAT_HT_MASK        (0xfff << LCDC_VAT_HT_BIT)
-#define LCDC_VAT_VT_BIT     0
-#define LCDC_VAT_VT_MASK        (0xfff << LCDC_VAT_VT_BIT)
-/* Display Area Horizontal Start/End Point Register */
-#define LCDC_DAH_HDS_BIT        16
-#define LCDC_DAH_HDS_MASK   (0xfff << LCDC_DAH_HDS_BIT)
-#define LCDC_DAH_HDE_BIT        0
-#define LCDC_DAH_HDE_MASK   (0xfff << LCDC_DAH_HDE_BIT)
-/* Display Area Vertical Start/End Point Register */
-#define LCDC_DAV_VDS_BIT        16
-#define LCDC_DAV_VDS_MASK   (0xfff << LCDC_DAV_VDS_BIT)
-#define LCDC_DAV_VDE_BIT        0
-#define LCDC_DAV_VDE_MASK   (0xfff << LCDC_DAV_VDE_BIT)
-/* Foreground 0 or Foreground 1 XY Position Register */
-#define LCDC_XYP_YPOS_BIT   16
-#define LCDC_XYP_YPOS_MASK  (0xfff << LCDC_XYP_YPOS_BIT)
-#define LCDC_XYP_XPOS_BIT   0
-#define LCDC_XYP_XPOS_MASK  (0xfff << LCDC_XYP_XPOS_BIT)
-/* Foreground 0 or Foreground 1 Size Register */
-#define LCDC_SIZE_HEIGHT_BIT    16
-#define LCDC_SIZE_HEIGHT_MASK   (0xfff << LCDC_SIZE_HEIGHT_BIT)
-#define LCDC_SIZE_WIDTH_BIT 0
-#define LCDC_SIZE_WIDTH_MASK    (0xfff << LCDC_SIZE_WIDTH_BIT)
-/* PS Signal Setting */
-#define LCDC_PS_PSS_BIT     16
-#define LCDC_PS_PSS_MASK        (0xfff << LCDC_PS_PSS_BIT)
-#define LCDC_PS_PSE_BIT     0
-#define LCDC_PS_PSE_MASK        (0xfff << LCDC_PS_PSE_BIT)
-/* CLS Signal Setting */
-#define LCDC_CLS_CLSS_BIT   16
-#define LCDC_CLS_CLSS_MASK  (0xfff << LCDC_CLS_CLSS_BIT)
-#define LCDC_CLS_CLSE_BIT   0
-#define LCDC_CLS_CLSE_MASK  (0xfff << LCDC_CLS_CLSE_BIT)
-/* SPL Signal Setting */
-#define LCDC_SPL_SPLS_BIT   16
-#define LCDC_SPL_SPLS_MASK  (0xfff << LCDC_SPL_SPLS_BIT)
-#define LCDC_SPL_SPLE_BIT   0
-#define LCDC_SPL_SPLE_MASK  (0xfff << LCDC_SPL_SPLE_BIT)
-/* REV Signal Setting */
-#define LCDC_REV_REVS_BIT   16
-#define LCDC_REV_REVS_MASK  (0xfff << LCDC_REV_REVS_BIT)
-/* DMA Command 0 or 1 Register */
-#define LCDC_CMD_SOFINT     (1 << 31)
-#define LCDC_CMD_EOFINT     (1 << 30)
-#define LCDC_CMD_CMD        (1 << 29)
-#define LCDC_CMD_PAL        (1 << 28)
-#define LCDC_CMD_COMPEN     (1 << 27)
-#define LCDC_CMD_FRM_EN     (1 << 26)
-#define LCDC_CMD_FIELD_SEL  (1 << 25)
-#define LCDC_CMD_16X16BLOCK (1 << 24)
-#define LCDC_CMD_LEN_BIT        0
-#define LCDC_CMD_LEN_MASK   (0xffffff << LCDC_CMD_LEN_BIT)
-/* DMA Offsize Register 0,1 */
-#define LCDC_OFFS_BIT       0
-#define LCDC_OFFS_OFFSIZE_MASK  (0xffffff << LCDC_OFFS_BIT)
-/* DMA Page Width Register 0,1 */
-#define LCDC_PW_BIT     0
-#define LCDC_PW_PAGEWIDTH_MASK  (0xffffff << LCDC_PW_BIT)
-/* DMA Command Counter Register 0,1 */
-#define LCDC_CNUM_BIT        0
-#define LCDC_CNUM_CNUM_MASK (0xff << LCDC_CNUM_BIT)
-#define LCDC_CPOS_ALPHAMD1  (1 << 31)
-#define LCDC_CPOS_RGB_RGB565    (0 << 30)
-#define LCDC_CPOS_RGB_RGB555    (1 << 30)
-#define LCDC_CPOS_BPP_BIT   27
-#define LCDC_CPOS_BPP_MASK  (0x07 << LCDC_CPOS_BPP_BIT)
-#define LCDC_CPOS_BPP_16    (4 << LCDC_CPOS_BPP_BIT)
-#define LCDC_CPOS_BPP_18_24 (5 << LCDC_CPOS_BPP_BIT)
-#define LCDC_CPOS_BPP_CMPS_24   (6 << LCDC_CPOS_BPP_BIT)
-#define LCDC_CPOS_BPP_30    (7 << LCDC_CPOS_BPP_BIT)
-#define LCDC_CPOS_PREMULTI  (1 << 26)
-#define LCDC_CPOS_COEF_SLE_BIT  24
-#define LCDC_CPOS_COEF_SLE_MASK (0x3 << LCDC_CPOS_COEF_SLE_BIT)
-#define LCDC_CPOS_COEF_SLE_0    (0 << LCDC_CPOS_COEF_SLE_BIT)
-#define LCDC_CPOS_COEF_SLE_1    (1 << LCDC_CPOS_COEF_SLE_BIT)
-#define LCDC_CPOS_COEF_SLE_2    (2 << LCDC_CPOS_COEF_SLE_BIT)
-#define LCDC_CPOS_COEF_SLE_3    (3 << LCDC_CPOS_COEF_SLE_BIT)
-#define LCDC_CPOS_YPOS_BIT  12
-#define LCDC_CPOS_YPOS_MASK (0xfff << LCDC_CPOS_YPOS_BIT)
-#define LCDC_CPOS_XPOS_BIT  0
-#define LCDC_CPOS_XPOS_MASK (0xfff << LCDC_CPOS_XPOS_BIT)
-/* Foreground 0,1 Size Register */
-#define LCDC_DESSIZE_ALPHA_BIT  24
-#define LCDC_DESSIZE_ALPHA_MASK (0xff << LCDC_DESSIZE_ALPHA_BIT)
-#define LCDC_DESSIZE_HEIGHT_BIT 12
-#define LCDC_DESSIZE_HEIGHT_MASK    (0xfff << LCDC_DESSIZE_HEIGHT_BIT)
-#define LCDC_DESSIZE_WIDTH_BIT  0
-#define LCDC_DESSIZE_WIDTH_MASK (0xfff << LCDC_DESSIZE_WIDTH_BIT)
-/* Priority level threshold configure Register */
-#define LCDC_PCFG_LCDC_PRI_MD   (1 << 31)
-#define LCDC_PCFG_HP_BST_BIT    28
-#define LCDC_PCFG_HP_BST_MASK   (0x7 << LCDC_PCFG_HP_BST_BIT)
-#define LCDC_PCFG_HP_BST_4  (0 << LCDC_PCFG_HP_BST_BIT)
-#define LCDC_PCFG_HP_BST_8  (1 << LCDC_PCFG_HP_BST_BIT)
-#define LCDC_PCFG_HP_BST_16 (2 << LCDC_PCFG_HP_BST_BIT)
-#define LCDC_PCFG_HP_BST_32 (3 << LCDC_PCFG_HP_BST_BIT)
-#define LCDC_PCFG_HP_BST_C16    (5 << LCDC_PCFG_HP_BST_BIT)
-#define LCDC_PCFG_HP_BST_64 (4 << LCDC_PCFG_HP_BST_BIT)
-#define LCDC_PCFG_HP_BST_DIS    (7 << LCDC_PCFG_HP_BST_BIT)
-#define LCDC_PCFG_PCFG2_BIT 18
-#define LCDC_PCFG_PCFG2_MASK    (0x1ff << LCDC_PCFG_PCFG2_BIT)
-#define LCDC_PCFG_PCFG1_BIT 9
-#define LCDC_PCFG_PCFG1_MASK    (0x1ff << LCDC_PCFG_PCFG1_BIT)
-#define LCDC_PCFG_PCFG0_BIT 0
-#define LCDC_PCFG_PCFG0_MASK    (0x1ff << LCDC_PCFG_PCFG0_BIT)
-/* Dual LCDC Channel Control register */
-#define LCDC_DUAL_CTRL_IPU_WR_SEL   (1 << 8)
-#define LCDC_DUAL_CTRL_TFT_SEL      (1 << 6)
-#define LCDC_DUAL_CTRL_PRI_IPU_EN   (1 << 5)
-#define LCDC_DUAL_CTRL_PRI_IPU_BIT  3
-#define LCDC_DUAL_CTRL_PRI_IPU_MASK (0x3 << LCDC_DUAL_CTRL_PRI_IPU_BIT)
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _X1000_SLCDC_H_ */
diff --git a/libcpu/mips/xburst/SConscript b/libcpu/mips/xburst/SConscript
deleted file mode 100644
index 0f06c299bb..0000000000
--- a/libcpu/mips/xburst/SConscript
+++ /dev/null
@@ -1,11 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-cwd = GetCurrentDir()
-src = Glob('*.c') + Glob('*.S')
-CPPPATH = [cwd]
-
-group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/libcpu/mips/xburst/cache.c b/libcpu/mips/xburst/cache.c
deleted file mode 100644
index cd37f69993..0000000000
--- a/libcpu/mips/xburst/cache.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * File      : cache.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
-*/
-
-#include "../xburst/cache.h"
-
-#include <board.h>
-
-#define CACHE_SIZE              16*1024
-#define CACHE_LINE_SIZE         32
-#define KSEG0                   0x80000000
-
-#define K0_TO_K1()              \
-do {                        \
-    unsigned long __k0_addr;        \
-                        \
-    __asm__ __volatile__(           \
-    "la %0, 1f\n\t"             \
-    "or %0, %0, %1\n\t"         \
-    "jr %0\n\t"             \
-    "nop\n\t"               \
-    "1: nop\n"              \
-    : "=&r"(__k0_addr)          \
-    : "r" (0x20000000) );           \
-} while(0)
-
-#define K1_TO_K0()              \
-do {                        \
-    unsigned long __k0_addr;        \
-    __asm__ __volatile__(           \
-    "nop;nop;nop;nop;nop;nop;nop\n\t"   \
-    "la %0, 1f\n\t"             \
-    "jr %0\n\t"             \
-    "nop\n\t"               \
-    "1: nop\n"              \
-    : "=&r" (__k0_addr));           \
-} while (0)
-
-#define INVALIDATE_BTB()            \
-do {                        \
-    unsigned long tmp;          \
-    __asm__ __volatile__(           \
-    ".set mips32\n\t"           \
-    "mfc0 %0, $16, 7\n\t"           \
-    "nop\n\t"               \
-    "ori %0, 2\n\t"             \
-    "mtc0 %0, $16, 7\n\t"           \
-    "nop\n\t"               \
-    ".set mips2\n\t"            \
-    : "=&r" (tmp));             \
-} while (0)
-
-#define SYNC_WB() __asm__ __volatile__ ("sync")
-
-#define cache_op(op,addr)                       \
-    __asm__ __volatile__(                       \
-    "   .set    noreorder       \n"         \
-    "   .set    mips32\n\t      \n"         \
-    "   cache   %0, %1          \n"         \
-    "   .set    mips0           \n"         \
-    "   .set    reorder"                    \
-    :                                       \
-    : "i" (op), "m" (*(unsigned char *)(addr)))
-
-void __icache_invalidate_all(void)
-{
-    unsigned int i;
-
-    K0_TO_K1();
-
-    asm volatile (".set noreorder\n"
-              ".set mips32\n\t"
-              "mtc0\t$0,$28\n\t"
-              "mtc0\t$0,$29\n"
-              ".set mips0\n"
-              ".set reorder\n");
-    for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
-        cache_op(Index_Store_Tag_I, i);
-
-    K1_TO_K0();
-
-    INVALIDATE_BTB();
-}
-
-void __dcache_writeback_all(void)
-{
-    unsigned int i;
-
-    for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
-        cache_op(Index_Writeback_Inv_D, i);
-
-    SYNC_WB();
-}
-
-void rt_hw_cache_init(void)
-{
-    __dcache_writeback_all();
-    __icache_invalidate_all();
-}
-
diff --git a/libcpu/mips/xburst/cache.h b/libcpu/mips/xburst/cache.h
deleted file mode 100644
index c0f8a1f424..0000000000
--- a/libcpu/mips/xburst/cache.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * File      : cache.h
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
-*/
-
-#ifndef __CACHE_H__
-#define __CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I          0x00
-#define Index_Writeback_Inv_D    0x01
-#define Index_Invalidate_SI         0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I        0x04
-#define Index_Load_Tag_D        0x05
-#define Index_Load_Tag_SI       0x06
-#define Index_Load_Tag_SD       0x07
-#define Index_Store_Tag_I       0x08
-#define Index_Store_Tag_D       0x09
-#define Index_Store_Tag_SI      0x0A
-#define Index_Store_Tag_SD      0x0B
-#define Create_Dirty_Excl_D     0x0d
-#define Create_Dirty_Excl_SD        0x0f
-#define Hit_Invalidate_I            0x10
-#define Hit_Invalidate_D            0x11
-#define Hit_Invalidate_SI           0x12
-#define Hit_Invalidate_SD           0x13
-#define Fill                        0x14
-#define Hit_Writeback_Inv_D     0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD        0x17
-#define Hit_Writeback_I         0x18
-#define Hit_Writeback_D         0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD            0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI      0x1e
-#define Hit_Set_Virtual_SD      0x1f
-
-void rt_hw_cache_init(void);
-
-#endif
diff --git a/libcpu/mips/xburst/cache_gcc.S b/libcpu/mips/xburst/cache_gcc.S
deleted file mode 100644
index a8d215764c..0000000000
--- a/libcpu/mips/xburst/cache_gcc.S
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/mipsregs.h"
-#include "../common/stackframe.h"
-
-    .text
-    .set noreorder
-
-    .globl  cache_init
-    .ent    cache_init
-cache_init:
-    .set    noreorder
-    mtc0    zero, CP0_TAGLO
-    move    t0, a0                  // cache total size
-    move    t1, a1                  // cache line size
-    li      t2, 0x80000000
-    addu    t3, t0, t2
-
-_cache_init_loop:
-    cache   8, 0(t2)                // icache_index_store_tag
-    cache   9, 0(t2)                // dcache_index_store_tag
-    addu    t2, t1
-    bne     t2, t3, _cache_init_loop
-    nop
-
-    mfc0    t0, CP0_CONFIG
-    li      t1, 0x7
-    not     t1
-    and     t0, t0, t1
-    or      t0, 0x3                 // cacheable, noncoherent, write-back, write allocate
-    mtc0    t0, CP0_CONFIG
-
-    jr      ra
-    nop
-
-    .set    reorder
-    .end    cache_init
diff --git a/libcpu/mips/xburst/context_gcc.S b/libcpu/mips/xburst/context_gcc.S
deleted file mode 100644
index a44d3bdcc7..0000000000
--- a/libcpu/mips/xburst/context_gcc.S
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to JZ4755
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-#include "stack.h"
-
-    .section ".text", "ax"
-    .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    mtc0    a0, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-    .globl rt_hw_context_switch
-rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
-    SAVE_ALL
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-    .globl rt_thread_switch_interrupt_flag
-    .globl rt_interrupt_from_thread
-    .globl rt_interrupt_to_thread
-    .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-
-    .globl system_dump
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
-    .globl rt_interrupt_enter
-    .globl rt_interrupt_leave
-    .globl mips_irq_handle
-mips_irq_handle:
-    SAVE_ALL
-
-    mfc0    t0, CP0_CAUSE
-    mfc0    t1, CP0_STATUS
-    and     t0, t1
-
-    andi    t0, 0xff00
-    beqz    t0, spurious_interrupt
-    nop
-
-    /* let k0 keep the current context sp */
-    move    k0, sp 
-    /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
-
-    jal     rt_interrupt_enter
-    nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-    nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-
-spurious_interrupt:
-    RESTORE_ALL_AND_RET
-
-    .set reorder
diff --git a/libcpu/mips/xburst/cpu.c b/libcpu/mips/xburst/cpu.c
deleted file mode 100644
index 88137535d9..0000000000
--- a/libcpu/mips/xburst/cpu.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * File      : cpu.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2010-09-11     Bernard      add CPU reset implementation
- */
-#include <rtthread.h>
-#include <board.h>
-
-/**
- * @addtogroup Ingenic
- */
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset()
-{
-    /* open the watch-dog */
-    REG_WDT_TCSR  = WDT_TCSR_EXT_EN;
-    REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
-    REG_WDT_TDR   = 0x03;
-    REG_WDT_TCNT  = 0x00;
-    REG_WDT_TCER |= WDT_TCER_TCEN;
-
-    rt_kprintf("reboot system...\n");
-    while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
-    rt_kprintf("shutdown...\n");
-
-    while (1);
-}
-
-/**
- * This function finds the first bit set (beginning with the least significant bit)
- * in value and return the index of that bit.
- *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of
- * zero from any of these functions means that the argument was zero.
- *
- * @return return the index of the first bit set. If value is 0, then this function
- * shall return 0.
- */
-int __rt_ffs(int value)
-{
-    return __builtin_ffs(value);
-}
-
-/*@}*/
diff --git a/libcpu/mips/xburst/exception.c b/libcpu/mips/xburst/exception.c
deleted file mode 100644
index aebdf704ea..0000000000
--- a/libcpu/mips/xburst/exception.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * File      : exception.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Ingenic
- */
-/*@{*/
-
-/**
- * exception handle table
- */
-exception_func_t sys_exception_handlers[33];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > 32) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-    rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-    rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-    rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-    rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-    rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
-}
-
-void install_default_execpt_handle(void)
-{
-    rt_int32_t i;
-
-    for (i=0; i<33; i++)
-        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-/*@}*/
-
diff --git a/libcpu/mips/xburst/interrupt.c b/libcpu/mips/xburst/interrupt.c
deleted file mode 100644
index 337646c735..0000000000
--- a/libcpu/mips/xburst/interrupt.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * File      : interrupt.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * 2010-07-09     Bernard      first version
- * 2013-03-29     aozima       Modify the interrupt interface implementations.
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <board.h>
-
-#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
-#define INTERRUPTS_MAX 64
-#else
-#define INTERRUPTS_MAX 32
-#endif
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc isr_table[INTERRUPTS_MAX];
-
-/**
- * @addtogroup Ingenic
- */
-/*@{*/
-
-static void rt_hw_interrupt_handler(int vector, void *param)
-{
-    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    rt_int32_t idx;
-
-    rt_memset(isr_table, 0x00, sizeof(isr_table));
-    for (idx = 0; idx < INTERRUPTS_MAX; idx ++)
-    {
-        isr_table[idx].handler = rt_hw_interrupt_handler;
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest               = 0;
-    rt_interrupt_from_thread        = 0;
-    rt_interrupt_to_thread          = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-    /* mask interrupt */
-    __intc_mask_irq(vector);
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    __intc_unmask_irq(vector);
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param handler the interrupt service routine to be installed
- * @param param the interrupt service function parameter
- * @param name the interrupt name
- * @return old handler
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if(vector < INTERRUPTS_MAX)
-    {
-        old_handler = isr_table[vector].handler;
-
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-        isr_table[vector].handler = handler;
-        isr_table[vector].param = param;
-    }
-
-    return old_handler;
-}
-
-#if  defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
-/*
- * fls - find last bit set.
- * @word: The word to search
- *
- * This is defined the same way as ffs.
- * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
- */
-rt_inline int fls(int x)
-{
-    __asm__("clz %0, %1" : "=r" (x) : "r" (x));
-
-    return 32 - x;
-}
-#endif
-
-#include <mipsregs.h>
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int i;
-    void *param;
-    rt_isr_handler_t irq_func;
-
-#if  defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
-    int irq = 0, group;
-    rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0;
-
-    rt_uint32_t c0_status, c0_cause;
-    rt_uint32_t pending_im;
-
-    /* check os timer */
-    c0_status = read_c0_status();
-    c0_cause = read_c0_cause();
-
-    pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM);
-
-    if (pending_im & CAUSEF_IP3)
-    {
-        extern void rt_hw_ost_handler(void);
-        rt_hw_ost_handler();
-        return;
-    }
-
-    if (pending_im & CAUSEF_IP2)
-    {
-        intc_ipr0 = REG_INTC_IPR(0);
-        intc_ipr1 = REG_INTC_IPR(1);
-
-        if (intc_ipr0)
-        {
-            irq = fls(intc_ipr0) - 1;
-            intc_ipr0 &= ~(1<<irq);
-        }
-        else if(intc_ipr1)
-        {
-            irq = fls(intc_ipr1) - 1;
-            intc_ipr1 &= ~(1<<irq);
-            irq += 32;
-        }
-#ifndef RT_USING_JZ_X1000 /* X1000 has no VPU */
-        else
-        {
-            __asm__ __volatile__ (
-                "mfc0  %0, $13,  0   \n\t"
-                "nop                  \n\t"
-                :"=r"(vpu_pending)
-                :);
-
-            if(vpu_pending & 0x800)
-                irq = IRQ_VPU;
-            else
-                return;
-        }
-#endif
-
-        if (irq >= INTERRUPTS_MAX)
-            rt_kprintf("max interrupt, irq=%d\n", irq);
-
-        /* do interrupt */
-        irq_func = isr_table[irq].handler;
-        param = isr_table[irq].param;
-        (*irq_func)(irq, param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-        isr_table[i].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-        /* ack interrupt */
-        __intc_ack_irq(irq);
-    }
-
-    if (pending_im & CAUSEF_IP0)
-        rt_kprintf("CAUSEF_IP0\n");
-    if (pending_im & CAUSEF_IP1)
-        rt_kprintf("CAUSEF_IP1\n");
-    if (pending_im & CAUSEF_IP4)
-        rt_kprintf("CAUSEF_IP4\n");
-    if (pending_im & CAUSEF_IP5)
-        rt_kprintf("CAUSEF_IP5\n");
-    if (pending_im & CAUSEF_IP6)
-        rt_kprintf("CAUSEF_IP6\n");
-    if (pending_im & CAUSEF_IP7)
-        rt_kprintf("CAUSEF_IP7\n");
-#else
-    static rt_uint32_t pending = 0;
-
-    /* the hardware interrupt */
-    pending |= REG_INTC_IPR;
-    if (!pending) return;
-
-    for (i = INTERRUPTS_MAX; i > 0; --i)
-    {
-        if ((pending & (1<<i)))
-        {
-            pending &= ~(1<<i);
-
-            /* do interrupt */
-            irq_func = isr_table[i].handler;
-            param = isr_table[i].param;
-            (*irq_func)(i, param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-            isr_table[i].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-            /* ack interrupt */
-            __intc_ack_irq(i);
-        }
-    }
-#endif
-}
-
-/*@}*/
diff --git a/libcpu/mips/xburst/mipscfg.c b/libcpu/mips/xburst/mipscfg.c
deleted file mode 100644
index 1e9b0c032f..0000000000
--- a/libcpu/mips/xburst/mipscfg.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * File      : mipscfg.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-    16,     /* icache_line_size */
-    256,    /* icache_lines_per_way */
-    4,      /* icache_ways */
-    16,     /* dcache_line_size */
-    256,    /* dcache_lines_per_way */
-    4,      /* dcache_ways */
-    16,     /* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-    rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-    rt_uint16_t val;
-    rt_uint32_t cp0_config1;
-
-    cp0_config1 = read_c0_config();
-    if (cp0_config1 & 0x80000000)
-    {
-        cp0_config1 = read_c0_config1();
-
-        val = (cp0_config1 & (7<<22))>>22;
-        g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-        val = (cp0_config1 & (7<<19))>>19;
-        g_mips_core.icache_line_size = 2 * m_pow(2, val);
-        val = (cp0_config1 & (7<<16))>>16;
-        g_mips_core.icache_ways = val + 1;
-
-        val = (cp0_config1 & (7<<13))>>13;
-        g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-        val = (cp0_config1 & (7<<10))>>10;
-        g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-        val = (cp0_config1 & (7<<7))>>7;
-        g_mips_core.dcache_ways = val + 1;
-
-        val = (cp0_config1 & (0x3F<<25))>>25;
-        g_mips_core.max_tlb_entries = val + 1;
-    }
-}
-
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-static void CP0_status_analyze(unsigned long value)
-{
-    if(value & (1<<26))
-        rt_kprintf(" FR");
-    if(value & (1<<23))
-        rt_kprintf(" PX");
-    if(value & (1<<22))
-        rt_kprintf(" BEV");
-    if(value & (1<<20))
-        rt_kprintf(" SR");
-    if(value & (1<<19))
-        rt_kprintf(" NMI");
-    if(value & (1<<20))
-        rt_kprintf(" SR");
-    if(value & (0xFF<<8))
-        rt_kprintf(" IM:0x%02X", (value >> 8) & 0xFF);
-    if(value & (1<<7))
-        rt_kprintf(" KX");
-    if(value & (1<<6))
-        rt_kprintf(" SX");
-    if(value & (1<<5))
-        rt_kprintf(" UX");
-    if(value & (0x03<<3))
-        rt_kprintf(" KSU:0x%02X", (value >> 3) & 0x03);
-    if(value & (1<<2))
-        rt_kprintf(" ERL");
-    if(value & (1<<1))
-        rt_kprintf(" EXL");
-    if(value & (1<<0))
-        rt_kprintf(" IE");
-}
-
-static void CP0_config0_analyze(unsigned long value)
-{
-    /* [31] M */
-    if(value & (1UL<<31))
-        rt_kprintf(" M");
-
-    /* [15] BE */
-    if(value & (1<<15))
-        rt_kprintf(" big-endian");
-    else
-        rt_kprintf(" little-endian");
-
-    /* [14:13] AT */
-    {
-        int AT = (value >> 13) & 0x03;
-
-        if(AT == 0)
-        {
-            rt_kprintf(" MIPS32");
-        }
-        else if(AT == 1)
-        {
-            rt_kprintf(" MIPS64/A32");
-        }
-        else if(AT == 2)
-        {
-            rt_kprintf(" MIPS64/A64");
-        }
-        else
-        {
-            rt_kprintf(" unkown");
-        }
-    }
-
-    /* [12:10] AR */
-    {
-        int AR = (value >> 10) & 0x07;
-
-        if(AR == 0)
-        {
-            rt_kprintf(" R1");
-        }
-        else if(AR == 1)
-        {
-            rt_kprintf(" R2");
-        }
-        else
-        {
-            rt_kprintf(" reserve");
-        }
-    }
-
-    /* [3] VI */
-    if(value & (1UL<<31))
-        rt_kprintf(" VI");
-
-    /* [2:0] K0 */
-    {
-        int K0 = value & 0x07;
-
-        if(K0 == 2)
-        {
-            rt_kprintf(" uncached");
-        }
-        else if(K0 == 3)
-        {
-            rt_kprintf(" cacheable");
-        }
-        else
-        {
-            rt_kprintf(" K0:reserve");
-        }
-    }
-}
-
-static void CP0_config1_analyze(unsigned long value)
-{
-    /* [31] M */
-    if(value & (1UL<<31))
-        rt_kprintf(" M");
-
-    /* [30:25] MMU size */
-    {
-        int MMU_size = (value >> 25) & 0x3F;
-        rt_kprintf(" TLB:%d", MMU_size + 1);
-    }
-
-    /* [24:22] IS, [21:19] IL, [18:16] IA */
-    {
-        int IS = (value >> 22) & 0x07;
-        int IL = (value >> 19) & 0x07;
-        int IA = (value >> 16) & 0x07;
-
-        IA = IA + 1;
-        IS = 64 << IS;
-        IL = 2 << IL;
-        rt_kprintf(" Icache-%dKB:%dway*%dset*%dbyte",
-                   (IA*IS*IL) >> 10, IA, IS, IL);
-    }
-
-    /* [15:13] DS, [12:10] DL, [9:7] DA */
-    {
-        int DS = (value >> 13) & 0x07;
-        int DL = (value >> 10) & 0x07;
-        int DA = (value >> 7)  & 0x07;
-
-        DA = DA + 1;
-        DS = 64 << DS;
-        DL = 2 << DL;
-        rt_kprintf(" Dcache-%dKB:%dway*%dset*%dbyte",
-                   (DA*DS*DL) >> 10, DA, DS, DL);
-    }
-
-    /* [6] C2 */
-    if(value & (1UL<<6))
-        rt_kprintf(" CP2");
-
-    /* [5] MD */
-    if(value & (1UL<<5))
-        rt_kprintf(" MDMX-ASE");
-
-    /* [4] PC */
-    if(value & (1UL<<4))
-        rt_kprintf(" performa-count");
-
-    /* [3] WR */
-    if(value & (1UL<<3))
-        rt_kprintf(" Watch");
-
-    /* [2] CA */
-    if(value & (1UL<<2))
-        rt_kprintf(" MIPS16e");
-
-    /* [1] EP */
-    if(value & (1UL<<1))
-        rt_kprintf(" EJTAG");
-
-    /* [0] FP */
-    if(value & (1UL<<0))
-        rt_kprintf(" FPU");
-}
-
-static void CP0_config2_analyze(unsigned long value)
-{
-    /* [31] M */
-    if(value & (1UL<<31))
-        rt_kprintf(" M");
-}
-
-static void CP0_config3_analyze(unsigned long value)
-{
-    /* [31] M */
-    if(value & (1UL<<31))
-        rt_kprintf(" M");
-}
-
-static void list_mips(void)
-{
-    unsigned long value;
-    unsigned long num = 0;
-
-    rt_kprintf("MIPS coprocessor register:\r\n");
-
-    rt_kprintf("( 0,0) INDEX     : 0x%08X\r\n", read_c0_index());
-    rt_kprintf("( 1,0) RANDOM    : 0x%08X\r\n", read_c0_random());
-    rt_kprintf("( 2,0) ENTRYLO0  : 0x%08X\r\n", read_c0_entrylo0());
-    rt_kprintf("( 3,0) ENTRYLO1  : 0x%08X\r\n", read_c0_entrylo1());
-    rt_kprintf("( 4,0) CONTEXT   : 0x%08X\r\n", read_c0_context());
-    rt_kprintf("( 5,0) PAGEMASK  : 0x%08X\r\n", read_c0_pagemask());
-    rt_kprintf("( 6,0) WIRED     : 0x%08X\r\n", read_c0_wired());
-    rt_kprintf("( 7,0) INFO      : 0x%08X\r\n", read_c0_info());
-    rt_kprintf("( 8,0) BADVADDR  : 0x%08X\r\n", read_c0_badvaddr());
-    rt_kprintf("( 9,0) COUNT     : 0x%08X\r\n", read_c0_count());
-    rt_kprintf("(10,0) ENTRYHI   : 0x%08X\r\n", read_c0_entryhi());
-    rt_kprintf("(11,0) COMPARE   : 0x%08X\r\n", read_c0_compare());
-
-    value = read_c0_status();
-    rt_kprintf("(12,0) STATUS    : 0x%08X", value);
-    CP0_status_analyze(value);
-    rt_kprintf("\r\n");
-
-    /*
-    rt_kprintf("(12,1) INTCTL    : 0x%08X\r\n", __read_32bit_c0_register(12, 1));
-    rt_kprintf("(12,2) SRSCTL    : 0x%08X\r\n", __read_32bit_c0_register(12, 2));
-    */
-
-    rt_kprintf("(13,0) CAUSE     : 0x%08X\r\n", read_c0_cause());
-    rt_kprintf("(14,0) EPC       : 0x%08X\r\n", read_c0_epc());
-    rt_kprintf("(15,0) PRID      : 0x%08X\r\n", read_c0_prid());
-    rt_kprintf("(15,1) EBASE     : 0x%08X\r\n", read_c0_ebase());
-
-    value = read_c0_config();
-    rt_kprintf("(16,0) CONFIG    : 0x%08X", value);
-    CP0_config0_analyze(value);
-    rt_kprintf("\r\n");
-    if(value & (1UL << 31))
-    {
-        value = read_c0_config1();
-        rt_kprintf("(16,1) CONFIG1   : 0x%08X", value);
-        CP0_config1_analyze(value);
-        rt_kprintf("\r\n");
-
-        if(value & (1UL << 31))
-        {
-            value = read_c0_config2();
-            rt_kprintf("(16,2) CONFIG2   : 0x%08X\r\n", value);
-            CP0_config2_analyze(value);
-            rt_kprintf("\r\n");
-
-            if(value & (1UL << 31))
-            {
-                value = read_c0_config3();
-                rt_kprintf("(16,3) CONFIG3   : 0x%08X\r\n", value);
-                CP0_config3_analyze(value);
-                rt_kprintf("\r\n");
-            }
-        }
-    }
-
-    rt_kprintf("(17,0) LLADDR    : 0x%08X\r\n", __read_32bit_c0_register($17, 0));
-    rt_kprintf("(18,0) WATCHLO   : 0x%08X\r\n", __read_32bit_c0_register($18, 0));
-    rt_kprintf("(19,0) WATCHHI   : 0x%08X\r\n", __read_32bit_c0_register($19, 0));
-    rt_kprintf("(20,0) XCONTEXT  : 0x%08X\r\n", __read_32bit_c0_register($20, 0));
-    rt_kprintf("(21,0) FRAMEMASK : 0x%08X\r\n", __read_32bit_c0_register($21, 0));
-    rt_kprintf("(22,0) DIAGNOSTIC: 0x%08X\r\n", __read_32bit_c0_register($22, 0));
-    rt_kprintf("(23,0) DEBUG     : 0x%08X\r\n", __read_32bit_c0_register($23, 0));
-    rt_kprintf("(24,0) DEPC      : 0x%08X\r\n", __read_32bit_c0_register($24, 0));
-
-    rt_kprintf("(25,0) PERFCTL0  : 0x%08X\r\n", __read_32bit_c0_register($25, 0));
-    rt_kprintf("(26,0) ECC       : 0x%08X\r\n", __read_32bit_c0_register($26, 0));
-    rt_kprintf("(27,0) CACHEERR  : 0x%08X\r\n", __read_32bit_c0_register($27, 0));
-    rt_kprintf("(28,0) TAGLO     : 0x%08X\r\n", __read_32bit_c0_register($28, 0));
-    rt_kprintf("(29,0) TAGHI     : 0x%08X\r\n", __read_32bit_c0_register($29, 0));
-
-    /*
-    rt_kprintf("(30,0) ERROREPC  : 0x%08X\r\n", __read_32bit_c0_register($30, 0));
-    rt_kprintf("(31,0) DESAVE    : 0x%08X\r\n", __read_32bit_c0_register($31, 0));
-    */
-
-
-    rt_kprintf("\r\n");
-}
-FINSH_FUNCTION_EXPORT(list_mips, list  CPU info)
-#endif /* RT_USING_FINSH */
-
diff --git a/libcpu/mips/xburst/stack.c b/libcpu/mips/xburst/stack.c
deleted file mode 100644
index ceba8b9d9d..0000000000
--- a/libcpu/mips/xburst/stack.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * File      : stack.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-07-07     Bernard      porting to Ingenic CPU
- */
-#include <rtthread.h>
-
-/**
- * @addtogroup Ingenic
- */
-/*@{*/
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-    rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-
-    if (g_sr == 0)
-    {
-        g_sr = cp0_get_status();
-        g_sr &= 0xfffffffe;
-        g_sr |= 0x0403;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-    *(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-    *(--stk) = (rt_uint32_t) 0xeeee;        /* c0_cause */
-    *(--stk) = (rt_uint32_t) 0xffff;        /* c0_badvaddr */
-    *(--stk) = (rt_uint32_t) cp0_get_lo();  /* lo */
-    *(--stk) = (rt_uint32_t) cp0_get_hi();  /* hi */
-    *(--stk) = (rt_uint32_t) g_sr;          /* C0_SR: HW2 = En, IE = En */
-    *(--stk) = (rt_uint32_t) texit;         /* ra */
-    *(--stk) = (rt_uint32_t) 0x0000001e;    /* s8 */
-    *(--stk) = (rt_uint32_t) stack_addr;    /* sp */
-    *(--stk) = (rt_uint32_t) 0x0000001c;    /* gp */
-    *(--stk) = (rt_uint32_t) 0x0000001b;    /* k1 */
-    *(--stk) = (rt_uint32_t) 0x0000001a;    /* k0 */
-    *(--stk) = (rt_uint32_t) 0x00000019;    /* t9 */
-    *(--stk) = (rt_uint32_t) 0x00000018;    /* t8 */
-    *(--stk) = (rt_uint32_t) 0x00000017;    /* s7 */
-    *(--stk) = (rt_uint32_t) 0x00000016;    /* s6 */
-    *(--stk) = (rt_uint32_t) 0x00000015;    /* s5 */
-    *(--stk) = (rt_uint32_t) 0x00000014;    /* s4 */
-    *(--stk) = (rt_uint32_t) 0x00000013;    /* s3 */
-    *(--stk) = (rt_uint32_t) 0x00000012;    /* s2 */
-    *(--stk) = (rt_uint32_t) 0x00000011;    /* s1 */
-    *(--stk) = (rt_uint32_t) 0x00000010;    /* s0 */
-    *(--stk) = (rt_uint32_t) 0x0000000f;    /* t7 */
-    *(--stk) = (rt_uint32_t) 0x0000000e;    /* t6 */
-    *(--stk) = (rt_uint32_t) 0x0000000d;    /* t5 */
-    *(--stk) = (rt_uint32_t) 0x0000000c;    /* t4 */
-    *(--stk) = (rt_uint32_t) 0x0000000b;    /* t3 */
-    *(--stk) = (rt_uint32_t) 0x0000000a;    /* t2 */
-    *(--stk) = (rt_uint32_t) 0x00000009;    /* t1 */
-    *(--stk) = (rt_uint32_t) 0x00000008;    /* t0 */
-    *(--stk) = (rt_uint32_t) 0x00000007;    /* a3 */
-    *(--stk) = (rt_uint32_t) 0x00000006;    /* a2 */
-    *(--stk) = (rt_uint32_t) 0x00000005;    /* a1 */
-    *(--stk) = (rt_uint32_t) parameter;     /* a0 */
-    *(--stk) = (rt_uint32_t) 0x00000003;    /* v1 */
-    *(--stk) = (rt_uint32_t) 0x00000002;    /* v0 */
-    *(--stk) = (rt_uint32_t) 0x00000001;    /* at */
-    *(--stk) = (rt_uint32_t) 0x00000000;    /* zero */
-
-    /* return task's current stack address */
-    return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/libcpu/mips/xburst/stack.h b/libcpu/mips/xburst/stack.h
deleted file mode 100644
index 5bb7206c11..0000000000
--- a/libcpu/mips/xburst/stack.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * File      : stack.h
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
-*/
-
-#ifndef __STACK_H__
-#define __STACK_H__
-
-#define SYSTEM_STACK          0x80003fe8		/* the kernel system stack address */
-
-#endif
diff --git a/libcpu/mips/xburst/start_gcc.S b/libcpu/mips/xburst/start_gcc.S
deleted file mode 100644
index da8bfa9251..0000000000
--- a/libcpu/mips/xburst/start_gcc.S
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to JZ47xx
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-#include "stack.h"
-
-    .section ".start", "ax"
-    .set noreorder
-
-    /* the program entry */
-    .globl  _start
-_start:
-    .set    noreorder
-    la      ra, _start
-
-    li      t1, 0x00800000
-    mtc0    t1, CP0_CAUSE
-
-    /* init cp0 registers. */
-    li      t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
-    mtc0    t0, CP0_STATUS
-
-    /* setup stack pointer */
-    li      sp, SYSTEM_STACK
-    la      gp, _gp
-
-    /* init caches, assumes a 4way * 128set * 32byte I/D cache */
-    mtc0    zero, CP0_TAGLO  /* TAGLO reg */
-    mtc0    zero, CP0_TAGHI  /* TAGHI reg */
-    li      t0, 3            /* enable cache for kseg0 accesses */
-    mtc0    t0, CP0_CONFIG   /* CONFIG reg */
-    la      t0, 0x80000000   /* an idx op should use an unmappable address */
-    ori     t1, t0, 0x4000   /* 16kB cache */
-
-_cache_loop:
-    cache   0x8, 0(t0)       /* index store icache tag */
-    cache   0x9, 0(t0)       /* index store dcache tag */
-    bne     t0, t1, _cache_loop
-    addiu   t0, t0, 0x20     /* 32 bytes per cache line */
-    nop
-
-    /* invalidate BTB */
-    mfc0    t0, CP0_CONFIG
-    nop
-    ori     t0, 2
-    mtc0    t0, CP0_CONFIG
-    nop
-
-    /* copy IRAM section */
-    la     t0, _iramcopy
-    la     t1, _iramstart
-    la     t2, _iramend
-_iram_loop:
-    lw     t3, 0(t0)
-    sw     t3, 0(t1)
-    addiu  t1, 4
-    bne    t1, t2, _iram_loop
-    addiu  t0, 4
-    /* clear bss */
-    la      t0, __bss_start
-    la      t1, __bss_end
-_clr_bss_loop:
-    sw      zero, 0(t0)
-    bne     t0, t1, _clr_bss_loop
-    addiu   t0, t0, 4
-
-    /* jump to RT-Thread RTOS */
-    jal     rtthread_startup
-    nop
-
-    /* restart, never die */
-    j       _start
-    nop
-    .set    reorder
-
-    .globl  cp0_get_cause
-cp0_get_cause:
-    mfc0    v0, CP0_CAUSE
-    jr      ra
-    nop
-
-    .globl  cp0_get_status
-cp0_get_status:
-    mfc0    v0, CP0_STATUS
-    jr      ra
-    nop
-
-    .globl  cp0_get_hi
-cp0_get_hi:
-    mfhi    v0
-    jr      ra
-    nop
-
-    .globl  cp0_get_lo
-cp0_get_lo:
-    mflo    v0
-    jr      ra
-    nop
-
-    .extern tlb_refill_handler
-    .extern cache_error_handler
-
-    /* Exception Handler */
-    /* 0x0 - TLB refill handler */
-    .section .vectors.1, "ax", %progbits
-    j      tlb_refill_handler
-    nop
-    
-    /* 0x100 - Cache error handler */
-    .section .vectors.2, "ax", %progbits
-    j      cache_error_handler
-    nop
-    
-    /* 0x180 - Exception/Interrupt handler */
-    .section .vectors.3, "ax", %progbits
-    j      _general_exception_handler
-    nop
-    
-    /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-    .section .vectors.4, "ax", %progbits
-    j      _irq_handler
-    nop
-    
-    .section .vectors, "ax", %progbits
-    .extern mips_irq_handle
-
-    /* general exception handler */
-_general_exception_handler:
-    .set    noreorder
-    mfc0    k1, CP0_CAUSE
-    andi    k1, k1, 0x7c
-    srl     k1, k1, 2
-    lw      k0, sys_exception_handlers(k1)
-    jr      k0
-    nop
-    .set    reorder
-
-    /* interrupt handler */
-_irq_handler:
-    .set    noreorder
-    la      k0, mips_irq_handle
-    jr      k0
-    nop
-    .set    reorder
diff --git a/libcpu/mips/xburst/x1000.h b/libcpu/mips/xburst/x1000.h
deleted file mode 100644
index 71d11783a3..0000000000
--- a/libcpu/mips/xburst/x1000.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * File      : x1000.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-11-19     Urey         the first version
- */
-
-#ifndef X1000_H__
-#define X1000_H__
-
-#ifndef __ASSEMBLY__
-
-// typedef unsigned int size_t;
-#define u64 unsigned long long
-#define u32 unsigned int
-#define u16 unsigned short
-#define u8  unsigned char
-
-#define U64 unsigned long long
-#define U32 unsigned int
-#define U16 unsigned short
-#define U8  unsigned char
-
-#define S64 signed long long
-#define S32 int
-#define S16 short int
-#define S8  signed char
-
-#define cache_unroll(base,op)               \
-    __asm__ __volatile__("                  \
-        .set noreorder;                     \
-        .set mips3;                         \
-        cache %1, (%0);                     \
-        .set mips0;                         \
-        .set reorder"                       \
-        :                                   \
-        : "r" (base),                       \
-          "i" (op));
-
-/* cpu pipeline flush */
-static inline void jz_sync(void)
-{
-    __asm__ volatile ("sync");
-}
-
-static inline void writeb(u8 value, u32 address)
-{
-    *((volatile u8 *) address) = value;
-}
-static inline void writew( u16 value, u32 address)
-{
-    *((volatile u16 *) address) = value;
-}
-static inline void writel(u32 value, u32 address)
-{
-    *((volatile u32 *) address) = value;
-}
-
-static inline u8 readb(u32 address)
-{
-    return *((volatile u8 *)address);
-}
-
-static inline u16 readw(u32 address)
-{
-    return *((volatile u16 *)address);
-}
-
-static inline u32 readl(u32 address)
-{
-    return *((volatile u32 *)address);
-}
-
-static inline void jz_writeb(u32 address, u8 value)
-{
-    *((volatile u8 *)address) = value;
-}
-
-static inline void jz_writew(u32 address, u16 value)
-{
-    *((volatile u16 *)address) = value;
-}
-
-static inline void jz_writel(u32 address, u32 value)
-{
-    *((volatile u32 *)address) = value;
-}
-
-static inline u8 jz_readb(u32 address)
-{
-    return *((volatile u8 *)address);
-}
-
-static inline u16 jz_readw(u32 address)
-{
-    return *((volatile u16 *)address);
-}
-
-static inline u32 jz_readl(u32 address)
-{
-    return *((volatile u32 *)address);
-}
-
-#define REG8(addr)      *((volatile u8 *)(addr))
-#define REG16(addr)     *((volatile u16 *)(addr))
-#define REG32(addr)     *((volatile u32 *)(addr))
-
-#define BIT(n)          (0x01u << (n))
-
-#else
-
-#define REG8(addr)  (addr)
-#define REG16(addr) (addr)
-#define REG32(addr) (addr)
-
-#endif /* !ASSEMBLY */
-
-
-//----------------------------------------------------------------------
-// Register Definitions
-//
-/* AHB0 BUS Devices Base */
-#define HARB0_BASE  0xB3000000
-#define EMC_BASE    0xB3010000
-#define DDRC_BASE   0xB3020000
-#define MDMAC_BASE  0xB3030000
-#define LCD_BASE    0xB3050000
-#define TVE_BASE    0xB3050000
-#define SLCD_BASE   0xB3050000
-#define CIM_BASE    0xB3060000
-#define IPU_BASE    0xB3080000
-/* AHB1 BUS Devices Base */
-#define HARB1_BASE  0xB3200000
-#define DMAGP0_BASE 0xB3210000
-#define DMAGP1_BASE 0xB3220000
-#define DMAGP2_BASE 0xB3230000
-#define MC_BASE     0xB3250000
-#define ME_BASE     0xB3260000
-#define DEBLK_BASE  0xB3270000
-#define IDCT_BASE   0xB3280000
-#define CABAC_BASE  0xB3290000
-#define TCSM0_BASE  0xB32B0000
-#define TCSM1_BASE  0xB32C0000
-#define SRAM_BASE   0xB32D0000
-/* AHB2 BUS Devices Base */
-#define HARB2_BASE  0xB3400000
-#define NEMC_BASE   0xB3410000
-#define DMAC_BASE   0xB3420000
-#define UHC_BASE    0xB3430000
-#define UDC_BASE    0xB3440000
-#define GPS_BASE    0xB3480000
-#define ETHC_BASE   0xB34B0000
-#define BCH_BASE    0xB34D0000
-#define MSC0_BASE   0xB3450000
-#define MSC1_BASE   0xB3460000
-#define MSC2_BASE   0xB3470000
-
-/* APB BUS Devices Base */
-#define CPM_BASE    0xB0000000
-#define INTC_BASE   0xB0001000
-#define TCU_BASE    0xB0002000
-#define WDT_BASE    0xB0002000
-#define OST_BASE    0xB2000000      /* OS Timer */
-#define RTC_BASE    0xB0003000
-#define GPIO_BASE   0xB0010000
-#define AIC_BASE    0xB0020000
-#define DMIC_BASE   0xB0021000
-#define ICDC_BASE   0xB0020000
-#define UART0_BASE  0xB0030000
-#define UART1_BASE  0xB0031000
-#define UART2_BASE  0xB0032000
-#define UART3_BASE  0xB0033000
-#define SCC_BASE    0xB0040000
-#define SSI0_BASE   0xB0043000
-#define SSI1_BASE   0xB0044000
-#define SSI2_BASE   0xB0045000
-#define I2C0_BASE   0xB0050000
-#define I2C1_BASE   0xB0051000
-#define PS2_BASE    0xB0060000
-#define SADC_BASE   0xB0070000
-#define OWI_BASE    0xB0072000
-#define TSSI_BASE   0xB0073000
-
-/* NAND CHIP Base Address*/
-#define NEMC_CS1_IOBASE 0Xbb000000
-#define NEMC_CS2_IOBASE 0Xba000000
-#define NEMC_CS3_IOBASE 0Xb9000000
-#define NEMC_CS4_IOBASE 0Xb8000000
-#define NEMC_CS5_IOBASE 0Xb7000000
-#define NEMC_CS6_IOBASE 0Xb6000000
-
-/*********************************************************************************************************
-**   WDT
-*********************************************************************************************************/
-#define WDT_TDR         (WDT_BASE + 0x00)
-#define WDT_TCER        (WDT_BASE + 0x04)
-#define WDT_TCNT        (WDT_BASE + 0x08)
-#define WDT_TCSR        (WDT_BASE + 0x0C)
-
-#define REG_WDT_TDR     REG16(WDT_TDR)
-#define REG_WDT_TCER    REG8(WDT_TCER)
-#define REG_WDT_TCNT    REG16(WDT_TCNT)
-#define REG_WDT_TCSR    REG16(WDT_TCSR)
-
-#define WDT_TSCR_WDTSC          (1 << 16)
-
-#define WDT_TCSR_PRESCALE_1         (0 << 3)
-#define WDT_TCSR_PRESCALE_4         (1 << 3)
-#define WDT_TCSR_PRESCALE_16        (2 << 3)
-#define WDT_TCSR_PRESCALE_64        (3 << 3)
-#define WDT_TCSR_PRESCALE_256       (4 << 3)
-#define WDT_TCSR_PRESCALE_1024      (5 << 3)
-
-#define WDT_TCSR_EXT_EN         (1 << 2)
-#define WDT_TCSR_RTC_EN         (1 << 1)
-#define WDT_TCSR_PCK_EN         (1 << 0)
-
-#define WDT_TCER_TCEN           (1 << 0)
-
-/*********************************************************************************************************
-**   �ж�Դ
-*********************************************************************************************************/
-/* INTC (Interrupt Controller) */
-#define INTC_ISR(n)             (INTC_BASE + 0x00 + (n) * 0x20)
-#define INTC_IMR(n)             (INTC_BASE + 0x04 + (n) * 0x20)
-#define INTC_IMSR(n)            (INTC_BASE + 0x08 + (n) * 0x20)
-#define INTC_IMCR(n)            (INTC_BASE + 0x0c + (n) * 0x20)
-#define INTC_IPR(n)             (INTC_BASE + 0x10 + (n) * 0x20)
-
-#define REG_INTC_ISR(n)         REG32(INTC_ISR((n)))
-#define REG_INTC_IMR(n)         REG32(INTC_IMR((n)))
-#define REG_INTC_IMSR(n)        REG32(INTC_IMSR((n)))
-#define REG_INTC_IMCR(n)        REG32(INTC_IMCR((n)))
-#define REG_INTC_IPR(n)         REG32(INTC_IPR((n)))
-
-// interrupt controller interrupts
-#define IRQ_DMIC                0
-#define IRQ_AIC0                1
-#define IRQ_RESERVED2           2
-#define IRQ_RESERVED3           3
-#define IRQ_RESERVED4           4
-#define IRQ_RESERVED5           5
-#define IRQ_RESERVED6           6
-#define IRQ_SFC                 7
-#define IRQ_SSI0                8
-#define IRQ_RESERVED9           9
-#define IRQ_PDMA                10
-#define IRQ_PDMAD               11
-#define IRQ_RESERVED12          12
-#define IRQ_RESERVED13          13
-#define IRQ_GPIO3               14
-#define IRQ_GPIO2               15
-#define IRQ_GPIO1               16
-#define IRQ_GPIO0               17
-#define IRQ_RESERVED18          18
-#define IRQ_RESERVED19          19
-#define IRQ_RESERVED20          20
-#define IRQ_OTG                 21
-#define IRQ_RESERVED22          22
-#define IRQ_AES                 23
-#define IRQ_RESERVED24          24
-#define IRQ_TCU2                25
-#define IRQ_TCU1                26
-#define IRQ_TCU0                27
-#define IRQ_RESERVED28          28
-#define IRQ_RESERVED29          29
-#define IRQ_CIM                 30
-#define IRQ_LCD                 31
-#define IRQ_RTC                 32
-#define IRQ_RESERVED33          33
-#define IRQ_RESERVED34          34
-#define IRQ_RESERVED35          35
-#define IRQ_MSC1                36
-#define IRQ_MSC0                37
-#define IRQ_SCC                 38
-#define IRQ_RESERVED39          39
-#define IRQ_PCM0                40
-#define IRQ_RESERVED41          41
-#define IRQ_RESERVED42          42
-#define IRQ_RESERVED43          43
-#define IRQ_HARB2               44
-#define IRQ_RESERVED45          45
-#define IRQ_HARB0               46
-#define IRQ_CPM                 47
-#define IRQ_RESERVED48          48
-#define IRQ_UART2               49
-#define IRQ_UART1               50
-#define IRQ_UART0               51
-#define IRQ_DDR                 52
-#define IRQ_RESERVED53          53
-#define IRQ_EFUSE               54
-#define IRQ_MAC                 55
-#define IRQ_RESERVED56          56
-#define IRQ_RESERVED57          57
-#define IRQ_I2C2                58
-#define IRQ_I2C1                59
-#define IRQ_I2C0                60
-#define IRQ_PDMAM               61
-#define IRQ_JPEG                62
-#define IRQ_RESERVED63          63
-
-#define IRQ_INTC_MAX            63
-
-#ifndef __ASSEMBLY__
-
-#define __intc_unmask_irq(n)    (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
-#define __intc_mask_irq(n)      (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
-#define __intc_ack_irq(n)       (REG_INTC_IPR((n)/32) = (1 << ((n)%32)))        /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _JZ_M150_H_ */
-- 
cgit v1.3.1


From 7c6650186100add61ef16c13fb120ad1161f6f1d Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Sat, 7 Dec 2019 00:54:03 +0800
Subject: [libcpu] Refine MIPS common code

MIPS common code was highly duplicated, This commit
is a attempt to clean-up and refine these code.

The context and exception handle flow is mostly identical
with Linux, but a notable difference is that when FPU enabled,
we save FP registers in stackframe unconditionally.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 libcpu/mips/SConscript              |    3 +-
 libcpu/mips/common/Kconfig          |    9 +
 libcpu/mips/common/asm.h            |   71 +-
 libcpu/mips/common/context_gcc.S    |  123 ++
 libcpu/mips/common/entry_gcc.S      |   55 +
 libcpu/mips/common/exception.c      |  159 +++
 libcpu/mips/common/exception.h      |  162 +--
 libcpu/mips/common/exception_gcc.S  |   59 +
 libcpu/mips/common/mips.h           |    8 +-
 libcpu/mips/common/mips_addrspace.h |   75 +-
 libcpu/mips/common/mips_asm.h       |  447 -------
 libcpu/mips/common/mips_cache.c     |    2 +-
 libcpu/mips/common/mips_cache.h     |    6 +-
 libcpu/mips/common/mips_cfg.h       |   10 +-
 libcpu/mips/common/mips_context.h   |  280 -----
 libcpu/mips/common/mips_def.h       | 2296 -----------------------------------
 libcpu/mips/common/mips_excpt.h     |   39 -
 libcpu/mips/common/mips_fpu.h       |   46 +
 libcpu/mips/common/mips_regs.h      |  816 ++++++-------
 libcpu/mips/common/mips_types.h     |   17 +-
 libcpu/mips/common/mipscfg.h        |   32 -
 libcpu/mips/common/mipsregs.h       |  706 -----------
 libcpu/mips/common/ptrace.h         |  126 ++
 libcpu/mips/common/stack.c          |   60 +
 libcpu/mips/common/stackframe.h     |  458 +++----
 25 files changed, 1325 insertions(+), 4740 deletions(-)
 create mode 100644 libcpu/mips/common/Kconfig
 create mode 100644 libcpu/mips/common/context_gcc.S
 create mode 100644 libcpu/mips/common/entry_gcc.S
 create mode 100644 libcpu/mips/common/exception.c
 create mode 100644 libcpu/mips/common/exception_gcc.S
 delete mode 100644 libcpu/mips/common/mips_asm.h
 delete mode 100644 libcpu/mips/common/mips_context.h
 delete mode 100644 libcpu/mips/common/mips_def.h
 delete mode 100644 libcpu/mips/common/mips_excpt.h
 create mode 100644 libcpu/mips/common/mips_fpu.h
 delete mode 100644 libcpu/mips/common/mipscfg.h
 delete mode 100644 libcpu/mips/common/mipsregs.h
 create mode 100644 libcpu/mips/common/ptrace.h
 create mode 100644 libcpu/mips/common/stack.c

(limited to 'libcpu')

diff --git a/libcpu/mips/SConscript b/libcpu/mips/SConscript
index 640e46a4fb..5fca2b473b 100644
--- a/libcpu/mips/SConscript
+++ b/libcpu/mips/SConscript
@@ -13,6 +13,7 @@ list  = os.listdir(cwd)
 group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+if rtconfig.CPU != 'common':
+    group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/mips/common/Kconfig b/libcpu/mips/common/Kconfig
new file mode 100644
index 0000000000..a4dd748214
--- /dev/null
+++ b/libcpu/mips/common/Kconfig
@@ -0,0 +1,9 @@
+menu "RT-Thread MIPS CPU"
+
+    config RT_USING_FPU
+        bool "Using Float Point Unit"
+        default n
+        help
+            Using Float Point Unit in code.
+
+endmenu
diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h
index 190e8b110e..ec451650d2 100644
--- a/libcpu/mips/common/asm.h
+++ b/libcpu/mips/common/asm.h
@@ -1,19 +1,16 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * Assembly Macros For MIPS
  *
- * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
- * Copyright (C) 1999 by Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- * Copyright (C) 2002  Maciej W. Rozycki
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * Some useful macros for MIPS assembler code
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Some of the routines below contain useless nops that will be optimized
- * away by gas in -O mode. These nops are however required to fill delay
- * slots in noreorder mode.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
+
+
 #ifndef __ASM_H__
 #define __ASM_H__
 
@@ -21,94 +18,94 @@
  * LEAF - declare leaf routine
  */
 #define	LEAF(symbol)                        \
-		.globl	symbol;                     \
-		.align	2;                          \
-		.type	symbol,@function;           \
-		.ent	symbol,0;                   \
+        .globl	symbol;                     \
+        .align	2;                          \
+        .type	symbol,@function;           \
+        .ent	symbol,0;                   \
 symbol:		.frame	sp,0,ra
 
 /*
  * NESTED - declare nested routine entry point
  */
 #define	NESTED(symbol, framesize, rpc)      \
-		.globl	symbol;                     \
-		.align	2;                          \
-		.type	symbol,@function;           \
-		.ent	symbol,0;                   \
+        .globl	symbol;                     \
+        .align	2;                          \
+        .type	symbol,@function;           \
+        .ent	symbol,0;                   \
 symbol:		.frame	sp, framesize, rpc
 
 /*
  * END - mark end of function
  */
 #define	END(function)                       \
-		.end	function;		        	\
-		.size	function,.-function
+        .end	function;		        	\
+        .size	function,.-function
 
 /*
  * EXPORT - export definition of symbol
  */
 #define EXPORT(symbol)						\
-		.globl	symbol;                     \
+        .globl	symbol;                     \
 symbol:
 
 /*
  * FEXPORT - export definition of a function symbol
  */
 #define FEXPORT(symbol)						\
-		.globl	symbol;						\
-		.type	symbol,@function;			\
+        .globl	symbol;						\
+        .type	symbol,@function;			\
 symbol:
 
 /*
  * Global data declaration with size.
  */
 #define EXPORTS(name,sz) 		\
-  	.globl name; 				\
-  	.type name,@object; 		\
-  	.size name,sz; 				\
+      .globl name; 				\
+      .type name,@object; 		\
+      .size name,sz; 				\
 name:
 
 /*
  * Weak data declaration with size.
  */
 #define WEXPORT(name,sz) 		\
-  	.weakext name; 				\
-  	.type name,@object; 		\
-  	.size name,sz; 				\
+      .weakext name; 				\
+      .type name,@object; 		\
+      .size name,sz; 				\
 name:
 
 /*
  * Global data reference with size.
  */
 #define	IMPORT(name, size) 		\
-	.extern	name,size
+    .extern	name,size
 
 /*
  * Global zeroed data.
  */
 #define BSS(name,size) 			\
-  	.type name,@object; 		\
-	.comm	name,size
+      .type name,@object; 		\
+    .comm	name,size
 
 /*
  * Local zeroed data.
  */
 #define LBSS(name,size) 		\
-  	.lcomm	name,size
+      .lcomm	name,size
 
 
 /*
  * ABS - export absolute symbol
  */
 #define	ABS(symbol,value)       \
-		.globl	symbol;         \
+        .globl	symbol;         \
 symbol		=	value
 
 
 #define	TEXT(msg)               \
-		.pushsection .data;		\
+        .pushsection .data;		\
 8:		.asciiz	msg;            \
-		.popsection;
+        .popsection;
 
 
 #define ENTRY(name) 			\
diff --git a/libcpu/mips/common/context_gcc.S b/libcpu/mips/common/context_gcc.S
new file mode 100644
index 0000000000..251fc81c3c
--- /dev/null
+++ b/libcpu/mips/common/context_gcc.S
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "mips_regs.h"
+#include "stackframe.h"
+
+    .section ".text", "ax"
+    .set noreorder
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
+ * a0 --> from
+ * a1 --> to
+ */
+    .globl rt_hw_context_switch
+rt_hw_context_switch:
+    mtc0    ra, CP0_EPC
+    SAVE_ALL
+
+    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
+    lw      sp, 0(a1)       /* get new task stack pointer */
+
+    RESTORE_ALL_AND_RET
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to)/*
+ * a0 --> to
+ */
+    .globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    lw      sp, 0(a0)       /* get new task stack pointer */
+    RESTORE_ALL_AND_RET
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
+ */
+    .globl rt_thread_switch_interrupt_flag
+    .globl rt_interrupt_from_thread
+    .globl rt_interrupt_to_thread
+    .globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    la      t0, rt_thread_switch_interrupt_flag
+    lw      t1, 0(t0)
+    nop
+    bnez    t1, _reswitch
+    nop
+    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
+    sw      t1, 0(t0)
+    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
+    sw      a0, 0(t0)
+_reswitch:
+    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
+    sw      a1, 0(t0)
+    jr      ra
+    nop
+
+/*
+ * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
+ */
+    .globl rt_interrupt_enter
+    .globl rt_interrupt_leave
+    .globl rt_general_exc_dispatch
+    .globl mips_irq_handle
+mips_irq_handle:
+    SAVE_ALL
+
+    /* let k0 keep the current context sp */
+    move    k0, sp
+    /* switch to kernel stack */
+    la      sp, _system_stack
+
+    jal     rt_interrupt_enter
+    nop
+    /* Get Old SP from k0 as paremeter in a0 */
+    move	a0, k0
+    jal     rt_general_exc_dispatch
+    nop
+    jal     rt_interrupt_leave
+    nop
+
+    /* switch sp back to thread context */
+    move    sp, k0
+
+    /*
+    * if rt_thread_switch_interrupt_flag set, jump to
+    * rt_hw_context_switch_interrupt_do and do not return
+    */
+    la      k0, rt_thread_switch_interrupt_flag
+    lw      k1, 0(k0)
+    beqz    k1, spurious_interrupt
+    nop
+    sw      zero, 0(k0)                     /* clear flag */
+    nop
+
+    /*
+    * switch to the new thread
+    */
+    la      k0, rt_interrupt_from_thread
+    lw      k1, 0(k0)
+    nop
+    sw      sp, 0(k1)                       /* store sp in preempted task TCB */
+
+    la      k0, rt_interrupt_to_thread
+    lw      k1, 0(k0)
+    nop
+    lw      sp, 0(k1)                       /* get new task stack pointer */
+    j       spurious_interrupt
+    nop
+
+spurious_interrupt:
+    RESTORE_ALL_AND_RET
+    .set reorder
diff --git a/libcpu/mips/common/entry_gcc.S b/libcpu/mips/common/entry_gcc.S
new file mode 100644
index 0000000000..b6f758e273
--- /dev/null
+++ b/libcpu/mips/common/entry_gcc.S
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+#include <rtconfig.h>
+
+    .section ".start", "ax"
+    .set noreorder
+
+    /* the program entry */
+    .globl  _rtthread_entry
+_rtthread_entry:
+#ifndef RT_USING_SELF_BOOT
+    .globl  _start
+_start:
+#endif
+    la	ra, _rtthread_entry
+
+    /* disable interrupt */
+    mtc0	zero, CP0_CAUSE
+    mtc0	zero, CP0_STATUS	# Set CPU to disable interrupt.
+    ehb
+    /* setup stack pointer */
+    la	sp, _system_stack
+    la	gp, _gp
+
+    bal	rt_cpu_early_init
+    nop
+
+    /* clear bss */
+    la	t0, __bss_start
+    la	t1, __bss_end
+_clr_bss_loop:
+    sw	zero, 0(t0)
+    bne	t0, t1, _clr_bss_loop
+    addiu	t0, t0, 4
+
+    /* jump to RT-Thread RTOS */
+    jal	rtthread_startup
+    nop
+
+    /* restart, never die */
+    j	_start
+    nop
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
new file mode 100644
index 0000000000..de67e98199
--- /dev/null
+++ b/libcpu/mips/common/exception.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include "exception.h"
+#include "mips_regs.h"
+
+/**
+ * @addtogroup MIPS
+ */
+
+/*@{*/
+
+extern rt_uint32_t __ebase_entry;
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    rt_base_t status = read_c0_status();
+    clear_c0_status(ST0_IE);
+    return status;
+}
+
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    write_c0_status(level);
+}
+
+/**
+ * exception handle table
+ */
+#define RT_EXCEPTION_MAX	31
+exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
+
+/**
+ * setup the exception handle
+ */
+exception_func_t rt_set_except_vector(int n, exception_func_t func)
+{
+    exception_func_t old_handler = sys_exception_handlers[n];
+
+    if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
+    {
+        return 0;
+    }
+
+    sys_exception_handlers[n] = func;
+
+    return old_handler;
+}
+
+void mips_dump_regs(struct pt_regs *regs) {
+    int i, j;
+    for(i = 0; i < 32 / 4; i++) {
+        for(j = 0; j < 4; j++) {
+            int reg = 4 * i + j;
+            rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]);
+        }
+        rt_kprintf("\n");
+    }
+}
+
+void tlb_refill_handler(void)
+{
+    rt_kprintf("TLB-Miss Happens, EPC: 0x%08x\n", read_c0_epc());
+    rt_hw_cpu_shutdown();
+}
+
+void cache_error_handler(void)
+{
+    rt_kprintf("Cache Exception Happens, EPC: 0x%08x\n", read_c0_epc());
+    rt_hw_cpu_shutdown();
+}
+
+static void unhandled_exception_handle(struct pt_regs *regs)
+{
+    rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause());
+    rt_kprintf("ST0: 0x%08x ",regs->cp0_status);
+    rt_kprintf("ErrorPC: 0x%08x\n",read_c0_errorepc());
+    mips_dump_regs(regs);
+    rt_hw_cpu_shutdown();
+}
+
+static void install_default_exception_handler(void)
+{
+    rt_int32_t i;
+
+    for (i=0; i<RT_EXCEPTION_MAX; i++)
+        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
+}
+
+int rt_hw_exception_init(void)
+{
+    rt_uint32_t ebase = (rt_uint32_t)&__ebase_entry;
+    write_c0_ebase(ebase);
+    clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL);
+    clear_c0_status(ST0_IM | ST0_IE);
+    set_c0_status(ST0_CU0);
+    /* install the default exception handler */
+    install_default_exception_handler();
+
+    return RT_EOK;
+}
+
+void rt_general_exc_dispatch(struct pt_regs *regs)
+{
+    rt_uint32_t cause, exccode;
+
+    exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
+
+    if (exccode == 0) {
+        rt_uint32_t status, pending;
+        status = read_c0_status();
+        pending = (cause & CAUSEF_IP) & (status & ST0_IM);
+        if (pending & CAUSEF_IP0)
+            rt_do_mips_cpu_irq(0);
+        if (pending & CAUSEF_IP1)
+            rt_do_mips_cpu_irq(1);
+        if (pending & CAUSEF_IP2)
+            rt_do_mips_cpu_irq(2);
+        if (pending & CAUSEF_IP3)
+            rt_do_mips_cpu_irq(3);
+        if (pending & CAUSEF_IP4)
+            rt_do_mips_cpu_irq(4);
+        if (pending & CAUSEF_IP5)
+            rt_do_mips_cpu_irq(5);
+        if (pending & CAUSEF_IP6)
+            rt_do_mips_cpu_irq(6);
+        if (pending & CAUSEF_IP7)
+            rt_do_mips_cpu_irq(7);
+    } else {
+        if (sys_exception_handlers[exccode])
+            sys_exception_handlers[exccode](regs);
+    }
+}
+
+/* Mask means disable the interrupt */
+void mips_mask_cpu_irq(rt_uint32_t irq)
+{
+    clear_c0_status(1 << (STATUSB_IP0 + irq));
+}
+
+/* Unmask means enable the interrupt */
+void mips_unmask_cpu_irq(rt_uint32_t irq)
+{
+    set_c0_status(1 << (STATUSB_IP0 + irq));
+}
+
+/*@}*/
diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h
index 2cb03d20e7..68107f6235 100644
--- a/libcpu/mips/common/exception.h
+++ b/libcpu/mips/common/exception.h
@@ -1,166 +1,28 @@
 /*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2010-05-17     swkyer       first version
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
+
 #ifndef __EXCEPTION_H__
 #define __EXCEPTION_H__
 
+#include "ptrace.h"
 
-/*
- * important register numbers
- */
-#define REG_EPC				37
-#define REG_FP				72
-#define REG_SP				29
-
-/*
- * Stack layout for the GDB exception handler
- * Derived from the stack layout described in asm-mips/stackframe.h
- *
- * The first PTRSIZE*6 bytes are argument save space for C subroutines.
- */
-#define NUMREGS				90
-
-#define GDB_FR_REG0			(PTRSIZE*6)			/* 0 */
-#define GDB_FR_REG1			((GDB_FR_REG0) + LONGSIZE)	/* 1 */
-#define GDB_FR_REG2			((GDB_FR_REG1) + LONGSIZE)	/* 2 */
-#define GDB_FR_REG3			((GDB_FR_REG2) + LONGSIZE)	/* 3 */
-#define GDB_FR_REG4			((GDB_FR_REG3) + LONGSIZE)	/* 4 */
-#define GDB_FR_REG5			((GDB_FR_REG4) + LONGSIZE)	/* 5 */
-#define GDB_FR_REG6			((GDB_FR_REG5) + LONGSIZE)	/* 6 */
-#define GDB_FR_REG7			((GDB_FR_REG6) + LONGSIZE)	/* 7 */
-#define GDB_FR_REG8			((GDB_FR_REG7) + LONGSIZE)	/* 8 */
-#define GDB_FR_REG9	        ((GDB_FR_REG8) + LONGSIZE)	/* 9 */
-#define GDB_FR_REG10		((GDB_FR_REG9) + LONGSIZE)	/* 10 */
-#define GDB_FR_REG11		((GDB_FR_REG10) + LONGSIZE)	/* 11 */
-#define GDB_FR_REG12		((GDB_FR_REG11) + LONGSIZE)	/* 12 */
-#define GDB_FR_REG13		((GDB_FR_REG12) + LONGSIZE)	/* 13 */
-#define GDB_FR_REG14		((GDB_FR_REG13) + LONGSIZE)	/* 14 */
-#define GDB_FR_REG15		((GDB_FR_REG14) + LONGSIZE)	/* 15 */
-#define GDB_FR_REG16		((GDB_FR_REG15) + LONGSIZE)	/* 16 */
-#define GDB_FR_REG17		((GDB_FR_REG16) + LONGSIZE)	/* 17 */
-#define GDB_FR_REG18		((GDB_FR_REG17) + LONGSIZE)	/* 18 */
-#define GDB_FR_REG19		((GDB_FR_REG18) + LONGSIZE)	/* 19 */
-#define GDB_FR_REG20		((GDB_FR_REG19) + LONGSIZE)	/* 20 */
-#define GDB_FR_REG21		((GDB_FR_REG20) + LONGSIZE)	/* 21 */
-#define GDB_FR_REG22		((GDB_FR_REG21) + LONGSIZE)	/* 22 */
-#define GDB_FR_REG23		((GDB_FR_REG22) + LONGSIZE)	/* 23 */
-#define GDB_FR_REG24		((GDB_FR_REG23) + LONGSIZE)	/* 24 */
-#define GDB_FR_REG25		((GDB_FR_REG24) + LONGSIZE)	/* 25 */
-#define GDB_FR_REG26		((GDB_FR_REG25) + LONGSIZE)	/* 26 */
-#define GDB_FR_REG27		((GDB_FR_REG26) + LONGSIZE)	/* 27 */
-#define GDB_FR_REG28		((GDB_FR_REG27) + LONGSIZE)	/* 28 */
-#define GDB_FR_REG29		((GDB_FR_REG28) + LONGSIZE)	/* 29 */
-#define GDB_FR_REG30		((GDB_FR_REG29) + LONGSIZE)	/* 30 */
-#define GDB_FR_REG31		((GDB_FR_REG30) + LONGSIZE)	/* 31 */
-
-/*
- * Saved special registers
- */
-#define GDB_FR_STATUS		((GDB_FR_REG31) + LONGSIZE)	/* 32 */
-#define GDB_FR_LO			((GDB_FR_STATUS) + LONGSIZE)	/* 33 */
-#define GDB_FR_HI			((GDB_FR_LO) + LONGSIZE)	/* 34 */
-#define GDB_FR_BADVADDR		((GDB_FR_HI) + LONGSIZE)	/* 35 */
-#define GDB_FR_CAUSE		((GDB_FR_BADVADDR) + LONGSIZE)	/* 36 */
-#define GDB_FR_EPC			((GDB_FR_CAUSE) + LONGSIZE)	/* 37 */
-
-///*
-// * Saved floating point registers
-// */
-//#define GDB_FR_FPR0		((GDB_FR_EPC) + LONGSIZE)	/* 38 */
-//#define GDB_FR_FPR1		((GDB_FR_FPR0) + LONGSIZE)	/* 39 */
-//#define GDB_FR_FPR2		((GDB_FR_FPR1) + LONGSIZE)	/* 40 */
-//#define GDB_FR_FPR3		((GDB_FR_FPR2) + LONGSIZE)	/* 41 */
-//#define GDB_FR_FPR4		((GDB_FR_FPR3) + LONGSIZE)	/* 42 */
-//#define GDB_FR_FPR5		((GDB_FR_FPR4) + LONGSIZE)	/* 43 */
-//#define GDB_FR_FPR6		((GDB_FR_FPR5) + LONGSIZE)	/* 44 */
-//#define GDB_FR_FPR7		((GDB_FR_FPR6) + LONGSIZE)	/* 45 */
-//#define GDB_FR_FPR8		((GDB_FR_FPR7) + LONGSIZE)	/* 46 */
-//#define GDB_FR_FPR9		((GDB_FR_FPR8) + LONGSIZE)	/* 47 */
-//#define GDB_FR_FPR10		((GDB_FR_FPR9) + LONGSIZE)	/* 48 */
-//#define GDB_FR_FPR11		((GDB_FR_FPR10) + LONGSIZE)	/* 49 */
-//#define GDB_FR_FPR12		((GDB_FR_FPR11) + LONGSIZE)	/* 50 */
-//#define GDB_FR_FPR13		((GDB_FR_FPR12) + LONGSIZE)	/* 51 */
-//#define GDB_FR_FPR14		((GDB_FR_FPR13) + LONGSIZE)	/* 52 */
-//#define GDB_FR_FPR15		((GDB_FR_FPR14) + LONGSIZE)	/* 53 */
-//#define GDB_FR_FPR16		((GDB_FR_FPR15) + LONGSIZE)	/* 54 */
-//#define GDB_FR_FPR17		((GDB_FR_FPR16) + LONGSIZE)	/* 55 */
-//#define GDB_FR_FPR18		((GDB_FR_FPR17) + LONGSIZE)	/* 56 */
-//#define GDB_FR_FPR19		((GDB_FR_FPR18) + LONGSIZE)	/* 57 */
-//#define GDB_FR_FPR20		((GDB_FR_FPR19) + LONGSIZE)	/* 58 */
-//#define GDB_FR_FPR21		((GDB_FR_FPR20) + LONGSIZE)	/* 59 */
-//#define GDB_FR_FPR22		((GDB_FR_FPR21) + LONGSIZE)	/* 60 */
-//#define GDB_FR_FPR23		((GDB_FR_FPR22) + LONGSIZE)	/* 61 */
-//#define GDB_FR_FPR24		((GDB_FR_FPR23) + LONGSIZE)	/* 62 */
-//#define GDB_FR_FPR25		((GDB_FR_FPR24) + LONGSIZE)	/* 63 */
-//#define GDB_FR_FPR26		((GDB_FR_FPR25) + LONGSIZE)	/* 64 */
-//#define GDB_FR_FPR27		((GDB_FR_FPR26) + LONGSIZE)	/* 65 */
-//#define GDB_FR_FPR28		((GDB_FR_FPR27) + LONGSIZE)	/* 66 */
-//#define GDB_FR_FPR29		((GDB_FR_FPR28) + LONGSIZE)	/* 67 */
-//#define GDB_FR_FPR30		((GDB_FR_FPR29) + LONGSIZE)	/* 68 */
-//#define GDB_FR_FPR31		((GDB_FR_FPR30) + LONGSIZE)	/* 69 */
-//
-//#define GDB_FR_FSR		((GDB_FR_FPR31) + LONGSIZE)	/* 70 */
-//#define GDB_FR_FIR		((GDB_FR_FSR) + LONGSIZE)	/* 71 */
-//#define GDB_FR_FRP		((GDB_FR_FIR) + LONGSIZE)	/* 72 */
-//
-//#define GDB_FR_DUMMY		((GDB_FR_FRP) + LONGSIZE)	/* 73, unused ??? */
-//
-///*
-// * Again, CP0 registers
-// */
-//#define GDB_FR_CP0_INDEX	((GDB_FR_DUMMY) + LONGSIZE)	/* 74 */
-#define GDB_FR_FRP			((GDB_FR_EPC) + LONGSIZE)	/* 72 */
-#define GDB_FR_CP0_INDEX	((GDB_FR_FRP) + LONGSIZE)	/* 74 */
-
-#define GDB_FR_CP0_RANDOM	((GDB_FR_CP0_INDEX) + LONGSIZE)	/* 75 */
-#define GDB_FR_CP0_ENTRYLO0	((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
-#define GDB_FR_CP0_ENTRYLO1	((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
-#define GDB_FR_CP0_CONTEXT	((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
-#define GDB_FR_CP0_PAGEMASK	((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
-#define GDB_FR_CP0_WIRED	((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
-#define GDB_FR_CP0_REG7		((GDB_FR_CP0_WIRED) + LONGSIZE)	/* 81 */
-#define GDB_FR_CP0_REG8		((GDB_FR_CP0_REG7) + LONGSIZE)	/* 82 */
-#define GDB_FR_CP0_REG9		((GDB_FR_CP0_REG8) + LONGSIZE)	/* 83 */
-#define GDB_FR_CP0_ENTRYHI	((GDB_FR_CP0_REG9) + LONGSIZE)	/* 84 */
-#define GDB_FR_CP0_REG11	((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
-#define GDB_FR_CP0_REG12	((GDB_FR_CP0_REG11) + LONGSIZE)	/* 86 */
-#define GDB_FR_CP0_REG13	((GDB_FR_CP0_REG12) + LONGSIZE)	/* 87 */
-#define GDB_FR_CP0_REG14	((GDB_FR_CP0_REG13) + LONGSIZE)	/* 88 */
-#define GDB_FR_CP0_PRID		((GDB_FR_CP0_REG14) + LONGSIZE)	/* 89 */
-
-#define GDB_FR_SIZE			((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
-
-/*
- * This is the same as above, but for the high-level
- * part of the INT stub.
- */
-typedef struct pt_regs_s
-{
-	/* Saved main processor registers. */
-	rt_base_t regs[32];
-	/* Saved special registers. */
-	rt_base_t cp0_status;
-	rt_base_t hi;
-	rt_base_t lo;
-	rt_base_t cp0_badvaddr;
-	rt_base_t cp0_cause;
-	rt_base_t cp0_epc;
-} pt_regs_t;
+#ifndef __ASSEMBLY__
 
-typedef void (* exception_func_t)(pt_regs_t *regs);
+typedef void (* exception_func_t)(struct pt_regs *regs);
 
+extern int rt_hw_exception_init(void);
 extern exception_func_t sys_exception_handlers[];
+extern void rt_do_mips_cpu_irq(rt_uint32_t ip);
 exception_func_t rt_set_except_vector(int n, exception_func_t func);
-void install_default_execpt_handle(void);
+extern void mips_mask_cpu_irq(rt_uint32_t irq);
+extern void mips_unmask_cpu_irq(rt_uint32_t irq);
+#endif
 
 #endif /* end of __EXCEPTION_H__ */
diff --git a/libcpu/mips/common/exception_gcc.S b/libcpu/mips/common/exception_gcc.S
new file mode 100644
index 0000000000..176b60e594
--- /dev/null
+++ b/libcpu/mips/common/exception_gcc.S
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+    .section ".exc_vectors", "ax"
+    .extern tlb_refill_handler
+    .extern cache_error_handler
+    .extern mips_irq_handle
+
+    /* 0x0 - TLB refill handler */
+    .global tlb_refill_exception
+    .type	tlb_refill_exception,@function
+ebase_start:
+tlb_refill_exception:
+    b	_general_exception_handler
+    nop
+
+    /* 0x100 - Cache error handler */
+    .org ebase_start + 0x100
+    j	cache_error_handler
+    nop
+
+    /* 0x180 - Exception/Interrupt handler */
+    .global general_exception
+    .type	general_exception,@function
+    .org ebase_start + 0x180
+general_exception:
+    b	_general_exception_handler
+    nop
+
+    /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
+    .global irq_exception
+    .type	irq_exception,@function
+    .org ebase_start + 0x200
+irq_exception:
+    b	_general_exception_handler
+    nop
+
+    /* general exception handler */
+_general_exception_handler:
+    .set	noreorder
+    la	$k0, mips_irq_handle
+    jr	$k0
+    nop
+    .set	reorder
+
+    /* interrupt handler */
+_irq_handler:
+    .set	noreorder
+    la	$k0, mips_irq_handle
+    jr	$k0
+    nop
+    .set	reorder
diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h
index a4bc74a050..94f664308c 100644
--- a/libcpu/mips/common/mips.h
+++ b/libcpu/mips/common/mips.h
@@ -12,14 +12,12 @@
 #define _COMMON_MIPS_H_
 
 #include "mips_cfg.h"
-
+#include "ptrace.h"
 #include "mips_types.h"
-#include "mips_asm.h"
-#include "mips_def.h"
+#include "asm.h"
 #include "mips_regs.h"
 #include "mips_addrspace.h"
 #include "mips_cache.h"
-#include "mips_context.h"
-#include "mips_excpt.h"
+#include "exception.h"
 
 #endif /* _COMMON_MIPS_H_ */
diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h
index 3b82a4e371..10fc2d6593 100644
--- a/libcpu/mips/common/mips_addrspace.h
+++ b/libcpu/mips/common/mips_addrspace.h
@@ -1,25 +1,11 @@
 /*
- * File      : mips_addrspace.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��12��     Urey         the first version
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
 
 #ifndef _MIPS_ADDRSPACE_H_
@@ -108,11 +94,11 @@
  * Memory segments (32bit kernel mode addresses)
  * These are the traditional names used in the 32-bit universe.
  */
-//#define KUSEGBASE			0x00000000
-//#define KSEG0BASE			0x80000000
-//#define KSEG1BASE			0xa0000000
-//#define KSEG2BASE			0xc0000000
-//#define KSEG3BASE			0xe0000000
+#define KUSEGBASE			0x00000000
+#define KSEG0BASE			0x80000000
+#define KSEG1BASE			0xa0000000
+#define KSEG2BASE			0xc0000000
+#define KSEG3BASE			0xe0000000
 
 #define CKUSEG			0x00000000
 #define CKSEG0			0x80000000
@@ -147,14 +133,6 @@
  * Returns the uncached address of a sdram address
  */
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
-/* We use a 36 bit physical address map here and
-   cannot access physical memory directly from core */
-#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else	/* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
-#endif	/* CONFIG_SOC_AU1X00 */
-#endif	/* __ASSEMBLY__ */
 
 /*
  * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
@@ -162,46 +140,19 @@
  * R8000 implements most with its 48-bit physical address space.
  */
 #define TO_PHYS_MASK	_CONST64_(0x07ffffffffffffff)	/* 2^^59 - 1 */
-
-#ifndef CONFIG_CPU_R8000
-
-/*
- * The R8000 doesn't have the 32-bit compat spaces so we don't define them
- * in order to catch bugs in the source code.
- */
-
 #define COMPAT_K1BASE32		_CONST64_(0xffffffffa0000000)
 #define PHYS_TO_COMPATK1(x)	((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
 
-#endif
-
 #define KDM_TO_PHYS(x)		(_ACAST64_ (x) & TO_PHYS_MASK)
 #define PHYS_TO_K0(x)		(_ACAST64_ (x) | CAC_BASE)
+#endif
 
 
 #ifndef __ASSEMBLY__
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are trivial on the 1:1 Linux/MIPS mapping
- */
-static inline phys_addr_t virt_to_phys(volatile void * address)
-{
-#ifndef CONFIG_64BIT
-	return CPHYSADDR(address);
-#else
-	return XPHYSADDR(address);
+#define REG8( addr )		  (*(volatile u8 *) (addr))
+#define REG16( addr )		  (*(volatile u16 *)(addr))
+#define REG32( addr )		  (*(volatile u32 *)(addr))
+#define REG64( addr )		  (*(volatile u64 *)(addr))
 #endif
-}
-
-static inline void * phys_to_virt(unsigned long address)
-{
-#ifndef CONFIG_64BIT
-	return (void *)KSEG0ADDR(address);
-#else
-	return (void *)CKSEG0ADDR(address);
-#endif
-}
-#endif
-
 
 #endif /* _MIPS_ADDRSPACE_H_ */
diff --git a/libcpu/mips/common/mips_asm.h b/libcpu/mips/common/mips_asm.h
deleted file mode 100644
index 8f97e370ab..0000000000
--- a/libcpu/mips/common/mips_asm.h
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * File      : mips_asm.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
- */
-
-#ifndef _MIPS_ASM_H_
-#define _MIPS_ASM_H_
-
-
-/* ********************************************************************* */
-/* Interface macro & data definition */
-
-#ifdef __ASSEMBLY__
-
-/******** ASSEMBLER SPECIFIC DEFINITIONS ********/
-
-#ifdef  __ghs__
-#define ALIGN(x) .##align (1 << (x))
-#else
-#define ALIGN(x) .##align (x)
-#endif
-
-#ifdef __ghs__
-#define SET_MIPS3()
-#define SET_MIPS0()
-#define SET_PUSH()
-#define SET_POP()
-#else
-#define SET_MIPS3() .##set mips3
-#define SET_MIPS0() .##set mips0
-#define SET_PUSH()  .##set push
-#define SET_POP()   .##set pop
-#endif
-
-/*  Different assemblers have different requirements for how to
- *  indicate that the next section is bss :
- *
- *  Some use :   .bss
- *  Others use : .section bss
- *
- *  We select which to use based on _BSS_OLD_, which may be defined
- *  in makefile.
- */
-#ifdef _BSS_OLD_
-#define BSS	.##section bss
-#else
-#define BSS	.##bss
-#endif
-
-#define LEAF(name)\
-  		.##text;\
-  		.##globl	name;\
-  		.##ent	name;\
-name:
-
-
-#define SLEAF(name)\
-  		.##text;\
-  		.##ent	name;\
-name:
-
-
-#ifdef __ghs__
-#define END(name)\
-  		.##end	name
-#else
-#define END(name)\
-  		.##size name,.-name;\
-  		.##end	name
-#endif
-
-
-#define EXTERN(name)
-
-#else
-
-#define U64 unsigned long long
-#define U32 unsigned int
-#define U16 unsigned short
-#define U8  unsigned char
-#define S64 signed long long
-#define S32 int
-#define S16 short int
-#define S8  signed char
-//#define bool U8
-
-#ifndef _SIZE_T_
-#define _SIZE_T_
-#ifdef __ghs__
-   typedef unsigned int size_t;
-#else
-   typedef unsigned long size_t;
-#endif
-#endif
-
-/* Sets the result on bPort */
-#define BIT_SET(bPort,bBitMask)        (bPort |= bBitMask)
-#define BIT_CLR(bPort,bBitMask)        (bPort &= ~bBitMask)
-
-/* Returns the result */
-#define GET_BIT_SET(bPort,bBitMask)    (bPort | bBitMask)
-#define GET_BIT_CLR(bPort,bBitMask)    (bPort & ~bBitMask)
-
-/* Returns 0 if the condition is False & a non-zero value if it is True */
-#define TEST_BIT_SET(bPort,bBitMask)   (bPort & bBitMask)
-#define TEST_BIT_CLR(bPort,bBitMask)   ((~bPort) & bBitMask)
-
-/* Split union definitions */
-typedef union tunSU16
-{
-        U16 hwHW;
-        struct tst2U8
-        {
-                U8 bB0;
-                U8 bB1;
-        }st2U8;
-}tunSU16;
-
-typedef union tunSU32
-{
-        U32 wW;
-        struct tst2U16
-        {
-                U16 hwHW0;
-                U16 hwHW1;
-        }st2U16;
-        struct tst4U8
-        {
-                U8 bB0;
-                U8 bB1;
-                U8 bB2;
-                U8 bB3;
-        }st4U8;
-}tunSU32;
-
-#endif /* #ifdef __ASSEMBLY__ */
-
-
-/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/
-
-
-#define  NO_ERR             0x00000000     /* operation completed successfully */
-#define  ERR                0xffffffff     /* operation completed not successfully */
-
-#define False 0
-#define True !False
-
-#ifndef NULL
-#define NULL		      	((void *)0)
-#endif//NULL
-
-#ifndef MIN
-#define MIN(x,y)           ((x) < (y) ? (x) : (y))
-#endif//MIN
-
-#ifndef MAX
-#define MAX(x,y)      		((x) > (y) ? (x) : (y))
-#endif//MAX
-
-#define MAXUINT(w)	(\
-		((w) == sizeof(U8))  ? 0xFFU :\
-		((w) == sizeof(U16)) ? 0xFFFFU :\
-		((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\
-		        )
-
-#define MAXINT(w)	(\
-		((w) == sizeof(S8))  ? 0x7F :\
-		((w) == sizeof(S16)) ? 0x7FFF :\
-		((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\
-		        )
-
-#define MSK(n)			  ((1 << (n)) - 1)
-
-#define KUSEG_MSK		  0x80000000
-#define KSEG_MSK		  0xE0000000
-
-#define KUSEGBASE		  0x00000000
-#define KSEG0BASE		  0x80000000
-#define KSEG1BASE		  0xA0000000
-#define KSSEGBASE		  0xC0000000
-#define KSEG3BASE		  0xE0000000
-
-/*  Below macros perform the following functions :
- *
- *  KSEG0    : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0.
- *  KSEG1    : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1.
- *  PHYS     : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address.
- *  KSSEG    : Not relevant for converting, but used for determining range.
- *  KSEG3    : Not relevant for converting, but used for determining range.
- *  KUSEG    : Not relevant for converting, but used for determining range.
- *  KSEG0A   : Same as KSEG0 but operates on register rather than constant.
- *  KSEG1A   : Same as KSEG1 but operates on register rather than constant.
- *  PHYSA    : Same as PHYS  but operates on register rather than constant.
- *  CACHED   : Alias for KSEG0 macro .
- *	       (Note that KSEG0 cache attribute is determined by K0
- *	       field of Config register, but this is typically cached).
- *  UNCACHED : Alias for KSEG1 macro .
- */
-#ifdef __ASSEMBLY__
-#define KSEG0(addr)     (((addr) & ~KSEG_MSK)  | KSEG0BASE)
-#define KSEG1(addr)     (((addr) & ~KSEG_MSK)  | KSEG1BASE)
-#define KSSEG(addr)     (((addr) & ~KSEG_MSK)  | KSSEGBASE)
-#define KSEG3(addr)     (((addr) & ~KSEG_MSK)  | KSEG3BASE)
-#define KUSEG(addr)     (((addr) & ~KUSEG_MSK) | KUSEGBASE)
-#define PHYS(addr)      ( (addr) & ~KSEG_MSK)
-#define KSEG0A(reg) 	and reg, ~KSEG_MSK; or reg, KSEG0BASE
-#define KSEG1A(reg) 	and reg, ~KSEG_MSK; or reg, KSEG1BASE
-#define PHYSA(reg)	and reg, ~KSEG_MSK
-#else
-#define KSEG0(addr)     (((U32)(addr) & ~KSEG_MSK)  | KSEG0BASE)
-#define KSEG1(addr)     (((U32)(addr) & ~KSEG_MSK)  | KSEG1BASE)
-#define KSSEG(addr)	(((U32)(addr) & ~KSEG_MSK)  | KSSEGBASE)
-#define KSEG3(addr)	(((U32)(addr) & ~KSEG_MSK)  | KSEG3BASE)
-#define KUSEG(addr)	(((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE)
-#define PHYS(addr) 	((U32)(addr)  & ~KSEG_MSK)
-#endif
-
-#define CACHED(addr)	KSEG0(addr)
-#define UNCACHED(addr)	KSEG1(addr)
-
-
-#ifdef __ASSEMBLY__
-/* Macroes to access variables at constant addresses
- * Compensates for signed 16 bit displacement
- * Typical use:	li	a0, HIKSEG1(ATLAS_ASCIIWORD)
- *		sw	v1, LO_OFFS(ATLAS_ASCIIWORD)(a0)
- */
-#define HIKSEG0(addr)	((KSEG0(addr) + 0x8000) & 0xffff0000)
-#define HIKSEG1(addr)	((KSEG1(addr) + 0x8000) & 0xffff0000)
-#define HI_PART(addr)	(((addr) + 0x8000) & 0xffff0000)
-#define LO_OFFS(addr)	((addr) & 0xffff)
-#endif
-
-
-/* Most/Least significant 32 bit from 64 bit double word */
-#define HI32(data64)		  ((U32)(data64 >> 32))
-#define LO32(data64)		  ((U32)(data64 & 0xFFFFFFFF))
-
-#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY)))
-#define REG8( addr )		  (*(volatile U8 *) (addr))
-#define REG16( addr )		  (*(volatile U16 *)(addr))
-#define REG32( addr )		  (*(volatile U32 *)(addr))
-#define REG64( addr )		  (*(volatile U64 *)(addr))
-#endif
-
-/* Register field mapping */
-#define REGFIELD(reg, rfld)	  (((reg) & rfld##_MSK) >> rfld##_SHF)
-
-/* absolute register address, access 					*/
-#define	REGA(addr)		  REG32(addr)
-
-/* physical register address, access: base address + offsett		*/
-#define	REGP(base,phys)	REG32( (U32)(base) + (phys) )
-
-/* relative register address, access: base address + offsett		*/
-#define REG(base,offs)  REG32( (U32)(base) + offs##_##OFS )
-
-/* relative register address, access: base address + offsett		*/
-#define REG_8(base,offs)  REG8( (U32)(base) + offs##_##OFS )
-
-/* relative register address, access: base address + offsett		*/
-#define REG_16(base,offs)  REG16( (U32)(base) + offs##_##OFS )
-
-/* relative register address, access: base address + offsett		*/
-#define REG_64(base,offs)  REG64( (U32)(base) + offs##_##OFS )
-
-/**************************************
- * Macroes not used by YAMON any more
- * (kept for backwards compatibility)
- */
-/* register read field							*/
-#define	REGARD(addr,fld)	((REGA(addr) & addr##_##fld##_##MSK) 	\
-			 >> addr##_##fld##_##SHF)
-
-/* register write numeric field value					*/
-#define	REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
-				 | ((intval) << addr##_##fld##_##SHF))
-
-/* register write enumerated field value				*/
-#define	REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
-			| ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF))
-
-
-/* Examples:
- *
- *	exccode = REGARD(CPU_CAUSE,EXC);
- *
- *	REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17)
- *			 | REGAWRE(OSG_CONTROL,DTYPE,PC1);
- */
-
-
-/* register read field							*/
-#define	REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) 	\
-			 >> offs##_##fld##_##SHF)
-
-/* register write numeric field value					*/
-#define	REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\
-                                 | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK))
-
-/* register write enumerated field value				*/
-#define	REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\
-				| ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF))
-
-
-/* physical register read field							*/
-#define	REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) 	\
-			 >> phys##_##fld##_##SHF)
-
-/* physical register write numeric field value					*/
-#define	REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\
-				 | ((intval) << phys##_##fld##_##SHF))
-
-/* physical register write enumerated field value				*/
-#define	REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\
-				| ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF))
-/*
- * End of macroes not used by YAMON any more
- *********************************************/
-
-/* Endian related macros */
-
-#define SWAP_BYTEADDR32( addr )   ( (addr) ^ 0x3 )
-#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 )
-
-/* Set byte address to little endian format */
-#ifdef EL
-#define SWAP_BYTEADDR_EL(addr) 	  addr
-#else
-#define SWAP_BYTEADDR_EL(addr)    SWAP_BYTEADDR32( addr )
-#endif
-
-/* Set byte address to big endian format */
-#ifdef EB
-#define SWAP_BYTEADDR_EB(addr) 	  addr
-#else
-#define SWAP_BYTEADDR_EB(addr)    SWAP_BYTEADDR32( addr )
-#endif
-
-/* Set U16 address to little endian format */
-#ifdef EL
-#define SWAP_U16ADDR_EL(addr)  addr
-#else
-#define SWAP_U16ADDR_EL(addr)  SWAP_U16ADDR32( addr )
-#endif
-
-/* Set U16 address to big endian format */
-#ifdef EB
-#define SWAP_U16ADDR_EB(addr)  addr
-#else
-#define SWAP_U16ADDR_EB(addr)  SWAP_U16ADDR32( addr )
-#endif
-
-#ifdef EL
-#define REGW32LE(addr, data)      REG32(addr) = (data)
-#define REGR32LE(addr, data)      (data)      = REG32(addr)
-#else
-#define REGW32LE(addr, data)      REG32(addr) = SWAPEND32(data)
-#define REGR32LE(addr, data)      (data)      = REG32(addr), (data) = SWAPEND32(data)
-#endif
-
-/* Set of 'LE'-macros, convert by BE: */
-#ifdef EL
-#define CPU_TO_LE32( value ) (value)
-#define LE32_TO_CPU( value ) (value)
-
-#define CPU_TO_LE16( value ) (value)
-#define LE16_TO_CPU( value ) (value)
-#else
-#define CPU_TO_LE32( value ) ( (                ((U32)value)  << 24) |   \
-                               ((0x0000FF00UL & ((U32)value)) <<  8) |   \
-                               ((0x00FF0000UL & ((U32)value)) >>  8) |   \
-                               (                ((U32)value)  >> 24)   )
-#define LE32_TO_CPU( value ) CPU_TO_LE32( value )
-
-#define CPU_TO_LE16( value ) ( ((U16)(((U16)value)  << 8)) |   \
-                               ((U16)(((U16)value)  >> 8))   )
-#define LE16_TO_CPU( value ) CPU_TO_LE16( value )
-#endif
-
-/* Set of 'BE'-macros, convert by LE: */
-#ifdef EB
-#define CPU_TO_BE32( value ) (value)
-#define BE32_TO_CPU( value ) (value)
-
-#define CPU_TO_BE16( value ) (value)
-#define BE16_TO_CPU( value ) (value)
-#else
-#define CPU_TO_BE32( value ) ( (                ((U32)value)  << 24) |   \
-                               ((0x0000FF00UL & ((U32)value)) <<  8) |   \
-                               ((0x00FF0000UL & ((U32)value)) >>  8) |   \
-                               (                ((U32)value)  >> 24)   )
-#define BE32_TO_CPU( value ) CPU_TO_BE32( value )
-
-#define CPU_TO_BE16( value ) ( ((U16)(((U16)value)  << 8)) |   \
-                               ((U16)(((U16)value)  >> 8))   )
-#define BE16_TO_CPU( value ) CPU_TO_BE16( value )
-#endif
-
-
-/* Control characters */
-#define CTRL_A          ('A'-0x40)
-#define CTRL_B          ('B'-0x40)
-#define CTRL_C          ('C'-0x40)
-#define CTRL_D          ('D'-0x40)
-#define CTRL_E          ('E'-0x40)
-#define CTRL_F          ('F'-0x40)
-#define CTRL_H          ('H'-0x40)
-#define CTRL_K          ('K'-0x40)
-#define CTRL_N          ('N'-0x40)
-#define CTRL_P          ('P'-0x40)
-#define CTRL_U          ('U'-0x40)
-#define BACKSPACE       0x08
-#define DEL             0x7F
-#define TAB             0x09
-#define CR              0x0D /* Enter Key */
-#define LF              0x0A
-#define ESC             0x1B
-#define SP              0x20
-#define CSI             0x9B
-
-
-/* DEF2STR(x) converts #define symbol to string */
-#define DEF2STR1(x) #x
-#define DEF2STR(x)  DEF2STR1(x)
-
-
-#endif /* _MIPS_ASM_H_ */
diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c
index 1c979b7106..8c86bb131a 100644
--- a/libcpu/mips/common/mips_cache.c
+++ b/libcpu/mips/common/mips_cache.c
@@ -19,7 +19,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07    Urey         the first version
  */
 
 #include <rtthread.h>
diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h
index a947041073..438dd76cde 100644
--- a/libcpu/mips/common/mips_cache.h
+++ b/libcpu/mips/common/mips_cache.h
@@ -19,7 +19,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��10��     Urey         the first version
+ * 2016-09-07     Urey         the first version
  */
 
 #ifndef _MIPS_CACHE_H_
@@ -38,11 +38,7 @@
 #define INDEX_LOAD_TAG_D        0x05
 #define INDEX_STORE_TAG_I       0x08
 #define INDEX_STORE_TAG_D       0x09
-#if defined(CONFIG_CPU_LOONGSON2)
-#define HIT_INVALIDATE_I        0x00
-#else
 #define HIT_INVALIDATE_I        0x10
-#endif
 #define HIT_INVALIDATE_D        0x11
 #define HIT_WRITEBACK_INV_D     0x15
 
diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h
index 3f0575d65a..f7e38b4af4 100644
--- a/libcpu/mips/common/mips_cfg.h
+++ b/libcpu/mips/common/mips_cfg.h
@@ -19,7 +19,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��10��     Urey         the first version
+ * 2016-09-07     Urey         the first version
  */
 
 #ifndef _MIPS_CFG_H_
@@ -30,12 +30,12 @@
 typedef struct mips32_core_cfg
 {
     uint16_t icache_line_size;
-//    uint16_t icache_lines_per_way;
-//    uint16_t icache_ways;
+    uint16_t icache_lines_per_way;
+    uint16_t icache_ways;
     uint16_t icache_size;
     uint16_t dcache_line_size;
-//    uint16_t dcache_lines_per_way;
-//    uint16_t dcache_ways;
+    uint16_t dcache_lines_per_way;
+    uint16_t dcache_ways;
     uint16_t dcache_size;
 
     uint16_t max_tlb_entries;	/* number of tlb entry */
diff --git a/libcpu/mips/common/mips_context.h b/libcpu/mips/common/mips_context.h
deleted file mode 100644
index 60d573784d..0000000000
--- a/libcpu/mips/common/mips_context.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * File      : mips_context_asm.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
- */
-
-#ifndef _MIPS_CONTEXT_ASM_H_
-#define _MIPS_CONTEXT_ASM_H_
-
-#define CONTEXT_SIZE	( STK_CTX_SIZE + FPU_ADJ )
-#ifdef __mips_hard_float
-#define FPU_ADJ			(32 * 4 + 8)		/* FP0-FP31 + CP1_STATUS */
-#define FPU_CTX			( CONTEXT_SIZE - FPU_ADJ )
-#else
-#define FPU_ADJ			0
-#endif
-
-
-
-#ifdef __ASSEMBLY__
-
-#ifdef __mips_hard_float
-.global _fpctx_save
-.global _fpctx_load
-#endif
-
-.macro SAVE_CONTEXT
-	.set    push
-	.set    noat
-	.set    noreorder
-	.set    volatile
-
-	//save SP
-	move	k1, 	sp
-	move	k0, 	sp
-	subu 	sp, 	k1, 	CONTEXT_SIZE
-	sw		k0, 	(29 * 4)(sp)
-
-	//save REG
-	sw		$0, 	( 0 * 4)(sp)
-	sw		$1, 	( 1 * 4)(sp)
-	sw		$2, 	( 2 * 4)(sp)
-	sw		$3, 	( 3 * 4)(sp)
-	sw		$4, 	( 4 * 4)(sp)
-	sw		$5, 	( 5 * 4)(sp)
-	sw		$6, 	( 6 * 4)(sp)
-	sw		$7, 	( 7 * 4)(sp)
-	sw		$8,     ( 8 * 4)(sp)
-	sw		$9,     ( 9 * 4)(sp)
-	sw		$10,    (10 * 4)(sp)
-	sw		$11,    (11 * 4)(sp)
-	sw		$12,    (12 * 4)(sp)
-	sw		$13,    (13 * 4)(sp)
-	sw		$14,    (14 * 4)(sp)
-	sw		$15,    (15 * 4)(sp)
-	sw		$16,    (16 * 4)(sp)
-	sw		$17,    (17 * 4)(sp)
-	sw		$18,    (18 * 4)(sp)
-	sw		$19,    (19 * 4)(sp)
-	sw		$20,    (20 * 4)(sp)
-	sw		$21,    (21 * 4)(sp)
-	sw		$22,    (22 * 4)(sp)
-	sw		$23,    (23 * 4)(sp)
-	sw		$24,    (24 * 4)(sp)
-	sw		$25, 	(25 * 4)(sp)
-	/* K0 K1 */
-	sw		$28, 	(28 * 4)(sp)
-	/* SP */
-	sw		$30,    (30 * 4)(sp)
-	sw		$31, 	(31 * 4)(sp)
-
-	/* STATUS CAUSE EPC.... */
-	mfc0	$2, 	CP0_STATUS
-	sw		$2, 	STK_OFFSET_SR(sp)
-
-	mfc0	$2, 	CP0_CAUSE
-	sw		$2, 	STK_OFFSET_CAUSE(sp)
-
-	mfc0	$2, 	CP0_BADVADDR
-	sw		$2, 	STK_OFFSET_BADVADDR(sp)
-
-	MFC0	$2, 	CP0_EPC
-	sw		$2, 	STK_OFFSET_EPC(sp)
-
-	mfhi	$2
-	sw		$2,     STK_OFFSET_HI(sp)
-
-	mflo	$2
-	sw		$2,     STK_OFFSET_LO(sp)
-#ifdef __mips_hard_float
-	add		a0,		sp,STK_CTX_SIZE
-
-    mfc0 	t0, 	CP0_STATUS
-    .set	push
-    .set	at
-    or      t0,   	M_StatusCU1
-    .set 	push
-    mtc0 	t0, 	CP0_STATUS
-
-    cfc1 	t0,  	CP1_STATUS
-    sw      t0   ,  0x00(a0)
-	swc1    $f0,(0x04 *  1)(a0)
-	swc1    $f1,(0x04 *  2)(a0)
-	swc1    $f2,(0x04 *  3)(a0)
-	swc1    $f3,(0x04 *  4)(a0)
-	swc1    $f4,(0x04 *  5)(a0)
-	swc1    $f5,(0x04 *  6)(a0)
-	swc1    $f6,(0x04 *  7)(a0)
-	swc1    $f7,(0x04 *  8)(a0)
-	swc1    $f8,(0x04 *  9)(a0)
-	swc1    $f9,(0x04 * 10)(a0)
-	swc1   $f10,(0x04 * 11)(a0)
-	swc1   $f11,(0x04 * 12)(a0)
-	swc1   $f12,(0x04 * 13)(a0)
-	swc1   $f13,(0x04 * 14)(a0)
-	swc1   $f14,(0x04 * 15)(a0)
-	swc1   $f15,(0x04 * 16)(a0)
-	swc1   $f16,(0x04 * 17)(a0)
-	swc1   $f17,(0x04 * 18)(a0)
-	swc1   $f18,(0x04 * 19)(a0)
-	swc1   $f19,(0x04 * 20)(a0)
-	swc1   $f20,(0x04 * 21)(a0)
-	swc1   $f21,(0x04 * 22)(a0)
-	swc1   $f22,(0x04 * 23)(a0)
-	swc1   $f23,(0x04 * 24)(a0)
-	swc1   $f24,(0x04 * 25)(a0)
-	swc1   $f25,(0x04 * 26)(a0)
-	swc1   $f26,(0x04 * 27)(a0)
-	swc1   $f27,(0x04 * 28)(a0)
-	swc1   $f28,(0x04 * 29)(a0)
-	swc1   $f29,(0x04 * 30)(a0)
-	swc1   $f30,(0x04 * 31)(a0)
-	swc1   $f31,(0x04 * 32)(a0)
-
-	nop
-#endif
-
-	//restore a0
-	lw		a0,		(REG_A0 * 4)(sp)
-
-	.set	pop
-.endm
-
-
-.macro RESTORE_CONTEXT
-	.set    push
-	.set    noat
-	.set    noreorder
-	.set    volatile
-
-#ifdef __mips_hard_float
-	add		a0,	sp,STK_CTX_SIZE
-
-    mfc0 	t0, CP0_STATUS
-    .set	push
-    .set	at
-    or      t0, M_StatusCU1
-    .set	noat
-    mtc0	t0, CP0_STATUS
-
-    lw      t0   ,   0x00(a0)
-	lwc1    $f0,(0x04 *  1)(a0)
-	lwc1    $f1,(0x04 *  2)(a0)
-	lwc1    $f2,(0x04 *  3)(a0)
-	lwc1    $f3,(0x04 *  4)(a0)
-	lwc1    $f4,(0x04 *  5)(a0)
-	lwc1    $f5,(0x04 *  6)(a0)
-	lwc1    $f6,(0x04 *  7)(a0)
-	lwc1    $f7,(0x04 *  8)(a0)
-	lwc1    $f8,(0x04 *  9)(a0)
-	lwc1    $f9,(0x04 * 10)(a0)
-	lwc1   $f10,(0x04 * 11)(a0)
-	lwc1   $f11,(0x04 * 12)(a0)
-	lwc1   $f12,(0x04 * 13)(a0)
-	lwc1   $f13,(0x04 * 14)(a0)
-	lwc1   $f14,(0x04 * 15)(a0)
-	lwc1   $f15,(0x04 * 16)(a0)
-	lwc1   $f16,(0x04 * 17)(a0)
-	lwc1   $f17,(0x04 * 18)(a0)
-	lwc1   $f18,(0x04 * 19)(a0)
-	lwc1   $f19,(0x04 * 20)(a0)
-	lwc1   $f20,(0x04 * 21)(a0)
-	lwc1   $f21,(0x04 * 22)(a0)
-	lwc1   $f22,(0x04 * 23)(a0)
-	lwc1   $f23,(0x04 * 24)(a0)
-	lwc1   $f24,(0x04 * 25)(a0)
-	lwc1   $f25,(0x04 * 26)(a0)
-	lwc1   $f26,(0x04 * 27)(a0)
-	lwc1   $f27,(0x04 * 28)(a0)
-	lwc1   $f28,(0x04 * 29)(a0)
-	lwc1   $f29,(0x04 * 30)(a0)
-	lwc1   $f30,(0x04 * 31)(a0)
-	lwc1   $f31,(0x04 * 32)(a0)
-    ctc1 	t0,     CP1_STATUS                                            ;/*  restore fpp status reg      */
-
-	nop
-#endif
-
-	/* ͨ�üĴ��� */
-	/* ZERO */
-	lw		$1,  	( 1 * 4)(sp)
-	/* V0   */
-	lw		$3,  	( 3 * 4)(sp)
-	lw		$4,  	( 4 * 4)(sp)
-	lw		$5,  	( 5 * 4)(sp)
-	lw		$6,  	( 6 * 4)(sp)
-	lw		$7,  	( 7 * 4)(sp)
-	lw		$8, 	( 8 * 4)(sp)
-	lw		$9, 	( 9 * 4)(sp)
-	lw		$10,    (10 * 4)(sp)
-	lw		$11,    (11 * 4)(sp)
-	lw		$12,    (12 * 4)(sp)
-	lw		$13,    (13 * 4)(sp)
-	lw		$14,    (14 * 4)(sp)
-	lw		$15,    (15 * 4)(sp)
-	lw		$16,    (16 * 4)(sp)
-	lw		$17,    (17 * 4)(sp)
-	lw		$18,    (18 * 4)(sp)
-	lw		$19,    (19 * 4)(sp)
-	lw		$20,    (20 * 4)(sp)
-	lw		$21,    (21 * 4)(sp)
-	lw		$22,    (22 * 4)(sp)
-	lw		$23, 	(23 * 4)(sp)
-	lw		$24, 	(24 * 4)(sp)
-	lw		$25, 	(25 * 4)(sp)
-	lw		$26, 	(26 * 4)(sp)
-	lw		$27, 	(27 * 4)(sp)
-	lw		$28, 	(28 * 4)(sp)
-	/* SP */
-	lw		$30, 	(30 * 4)(sp)
-	lw		$31, 	(31 * 4)(sp)
-
-
-	/* STATUS CAUSE EPC.... */
-	lw		$2,    STK_OFFSET_HI(sp)
-	mthi	$2
-	lw		$2, 	STK_OFFSET_LO(sp)
-	mtlo	$2
-
-	lw		$2, 	STK_OFFSET_SR(sp)
-	mtc0	$2, 	CP0_STATUS
-
-	lw		$2, 	STK_OFFSET_BADVADDR(sp)
-	mtc0	$2, 	CP0_BADVADDR
-
-	lw		$2, 	STK_OFFSET_CAUSE(sp)
-	mtc0	$2, 	CP0_CAUSE
-
-	lw		$2, 	STK_OFFSET_EPC(sp)
-	MTC0	$2, 	CP0_EPC
-
-	//restore $2
-	lw		$2,  	( 2 * 4)(sp)
-	//restore sp
-	lw		$29, 	(29 * 4)(sp)
-
-	eret
-	nop
-    .set    pop
-.endm
-#endif
-#endif /* _MIPS_CONTEXT_ASM_H_ */
diff --git a/libcpu/mips/common/mips_def.h b/libcpu/mips/common/mips_def.h
deleted file mode 100644
index 1727684f50..0000000000
--- a/libcpu/mips/common/mips_def.h
+++ /dev/null
@@ -1,2296 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016-09-07     Urey         first version
- */
-
-#ifndef _COMMON_MIPS_DEF_H_
-#define _COMMON_MIPS_DEF_H_
-
-
-/*
- ************************************************************************
- *                I N S T R U C T I O N   F O R M A T S                 *
- ************************************************************************
- *
- * The following definitions describe each field in an instruction.  There
- * is one diagram for each type of instruction, with field definitions
- * following the diagram for that instruction.  Note that if a field of
- * the same name and position is defined in an earlier diagram, it is
- * not defined again in the subsequent diagram.  Only new fields are
- * defined for each diagram.
- *
- * R-Type (operate)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |           |   rs    |   rt    |   rd    |   sa    |           |
- * |   Opcode  |         |         |       Tcode       |   func    |
- * |           |                  Bcode                |     | sel |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnOpcode		26
-#define M_InstnOpcode		(0x3f << S_InstnOpcode)
-#define S_InstnRS			21
-#define M_InstnRS			(0x1f << S_InstnRS)
-#define S_InstnRT			16
-#define M_InstnRT			(0x1f << S_InstnRT)
-#define S_InstnRD			11
-#define M_InstnRD			(0x1f << S_InstnRD)
-#define S_InstnSA			6
-#define M_InstnSA			(0x1f << S_InstnSA)
-#define S_InstnTcode		6
-#define M_InstnTcode		(0x3ff << S_InstnTcode)
-#define S_InstnBcode		6
-#define M_InstnBcode		(0xfffff << S_InstnBcode)
-#define S_InstnFunc		0
-#define M_InstnFunc		(0x3f << S_InstnFunc)
-#define S_InstnSel			0
-#define M_InstnSel			(0x7 << S_InstnSel)
-
-/*
- * I-Type (load, store, branch, immediate)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |   rt    |             Offset            |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnOffset		0
-#define M_InstnOffset		(0xffff << S_InstnOffset)
-
-/*
- * I-Type (pref)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |  hint   |             Offset            |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnHint		S_InstnRT
-#define M_InstnHint		M_InstnRT
-
-/*
- * J-Type (jump)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |                    JIndex                         |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnJIndex		0
-#define M_InstnJIndex		(0x03ffffff << S_InstnJIndex)
-
-/*
- * FP R-Type (operate)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   fmt   |   ft    |   fs    |   fd    |   func    |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnFmt		S_InstnRS
-#define M_InstnFmt		M_InstnRS
-#define S_InstnFT		S_InstnRT
-#define M_InstnFT		M_InstnRT
-#define S_InstnFS		S_InstnRD
-#define M_InstnFS		M_InstnRD
-#define S_InstnFD		S_InstnSA
-#define M_InstnFD		M_InstnSA
-
-/*
- * FP R-Type (cpu <-> cpu data movement))
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   sub   |   rt    |   fs    |          0          |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnSub		S_InstnRS
-#define M_InstnSub		M_InstnRS
-
-/*
- * FP R-Type (compare)
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |           |         |         |         |     | |C|           |
- * |   Opcode  |   fmt   |   ft    |   fs    |  cc |0|A|   func    |
- * |           |         |         |         |     | |B|           |
- * |           |         |         |         |     | |S|           |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnCCcmp		8
-#define M_InstnCCcmp		(0x7 << S_InstnCCcmp)
-#define S_InstnCABS		6
-#define M_InstnCABS		(0x1 << S_InstnCABS)
-
-/*
- * FP R-Type (FPR conditional move on FP cc)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   fmt   |  cc |n|t|   fs    |   fd    |   func    |
- * |           |         |     |d|f|         |         |           |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnCC		18
-#define M_InstnCC		(0x7 << S_InstnCC)
-#define S_InstnND		17
-#define M_InstnND		(0x1 << S_InstnND)
-#define S_InstnTF		16
-#define M_InstnTF		(0x1 << S_InstnTF)
-
-/*
- * FP R-Type (3-operand operate)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   fr    |   ft    |   fs    |   fd    | op4 | fmt3|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnFR		S_InstnRS
-#define M_InstnFR		M_InstnRS
-#define S_InstnOp4		3
-#define M_InstnOp4		(0x7 << S_InstnOp4)
-#define S_InstnFmt3		0
-#define M_InstnFmt3		(0x7 << S_InstnFmt3)
-
-/*
- * FP R-Type (Indexed load, store)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |   rt    |   0     |   fd    |   func    |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-/*
- * FP R-Type (prefx)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |   rt    |  hint   |    0    |   func    |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnHintX		S_InstnRD
-#define M_InstnHintX		M_InstnRD
-
-/*
- * FP R-Type (GPR conditional move on FP cc)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |    rs   |  cc |n|t|   rd    |    0    |   func    |
- * |           |         |     |d|f|         |         |           |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-/*
- * FP I-Type (load, store)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |    ft   |           Offset              |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-/*
- * FP I-Type (branch)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   fmt   |  cc |n|t|           Offset              |
- * |           |         |     |d|f|                               |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-
-/*
- *************************************************************************
- *         V I R T U A L   A D D R E S S   D E F I N I T I O N S         *
- *************************************************************************
- */
-
-#ifdef MIPSADDR64
-#define A_K0BASE		UNS64Const(0xffffffff80000000)
-#define A_K1BASE		UNS64Const(0xffffffffa0000000)
-#define A_K2BASE		UNS64Const(0xffffffffc0000000)
-#define A_K3BASE		UNS64Const(0xffffffffe0000000)
-#define A_REGION		UNS64Const(0xc000000000000000)
-#define A_XKPHYS_ATTR		UNS64Const(0x3800000000000000)
-#else
-#define A_K0BASE		0x80000000
-#define A_K1BASE		0xa0000000
-#define A_K2BASE		0xc0000000
-#define A_K3BASE		0xe0000000
-#endif
-#define M_KMAPPED		0x40000000		/* KnSEG address is mapped if bit is one */
-
-
-#ifdef MIPS_Model64
-
-#define S_VMAP64                62
-#define M_VMAP64                UNS64Const(0xc000000000000000)
-
-#define K_VMode11               3
-#define K_VMode10               2
-#define K_VMode01               1
-#define K_VMode00               0
-
-#define S_KSEG3                 29
-#define M_KSEG3                 (0x7 << S_KSEG3)
-#define K_KSEG3                 7
-
-#define S_SSEG                  29
-#define M_SSEG                  (0x7 << S_KSEG3)
-#define K_SSEG                  6
-
-#define S_KSSEG                 29
-#define M_KSSEG                 (0x7 << S_KSEG3)
-#define K_KSSEG                 6
-
-#define S_KSEG1                 29
-#define M_KSEG1                 (0x7 << S_KSEG3)
-#define K_KSEG1                 5
-
-#define S_KSEG0                 29
-#define M_KSEG0                 (0x7 << S_KSEG3)
-#define K_KSEG0                 4
-
-#define S_XKSEG                 29
-#define M_XKSEG                 (0x7 << S_KSEG3)
-#define K_XKSEG                 3
-
-#define S_USEG                  31
-#define M_USEG                  (0x1 << S_USEG)
-#define K_USEG                  0
-
-#define S_EjtagProbeMem         20
-#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
-#define K_EjtagProbeMem         0
-
-
-
-#else
-
-#define S_KSEG3                 29
-#define M_KSEG3                 (0x7 << S_KSEG3)
-#define K_KSEG3                 7
-
-#define S_KSSEG                 29
-#define M_KSSEG                 (0x7 << S_KSSEG)
-#define K_KSSEG                 6
-
-#define S_SSEG                  29
-#define M_SSEG                  (0x7 << S_SSEG)
-#define K_SSEG                  6
-
-#define S_KSEG1                 29
-#define M_KSEG1                 (0x7 << S_KSEG1)
-#define K_KSEG1                 5
-
-#define S_KSEG0                 29
-#define M_KSEG0                 (0x7 << S_KSEG0)
-#define K_KSEG0                 4
-
-#define S_KUSEG                 31
-#define M_KUSEG                 (0x1 << S_KUSEG)
-#define K_KUSEG                 0
-
-#define S_SUSEG                 31
-#define M_SUSEG                 (0x1 << S_SUSEG)
-#define K_SUSEG                 0
-
-#define S_USEG                  31
-#define M_USEG                  (0x1 << S_USEG)
-#define K_USEG                  0
-
-#define K_EjtagLower            0xff200000
-#define K_EjtagUpper            0xff3fffff
-
-#define S_EjtagProbeMem         20
-#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
-#define K_EjtagProbeMem         0
-
-#endif
-
-
-
-/*
- *************************************************************************
- *   C A C H E   I N S T R U C T I O N   O P E R A T I O N   C O D E S   *
- *************************************************************************
- */
-
-/*
- * Cache encodings
- */
-#define K_CachePriI		0			/* Primary Icache */
-#define K_CachePriD		1			/* Primary Dcache */
-#define K_CachePriU		1			/* Unified primary */
-#define K_CacheTerU		2			/* Unified Tertiary */
-#define K_CacheSecU		3			/* Unified secondary */
-
-
-/*
- * Function encodings
- */
-#define S_CacheFunc		2			/* Amount to shift function encoding within 5-bit field */
-#define K_CacheIndexInv		0			/* Index invalidate */
-#define K_CacheIndexWBInv       0			/* Index writeback invalidate */
-#define K_CacheIndexLdTag	1			/* Index load tag */
-#define K_CacheIndexStTag	2			/* Index store tag */
-#define K_CacheHitInv		4			/* Hit Invalidate */
-#define K_CacheFill		5			/* Fill (Icache only) */
-#define K_CacheHitWBInv		5			/* Hit writeback invalidate */
-#define K_CacheHitWB		6			/* Hit writeback */
-#define K_CacheFetchLock	7			/* Fetch and lock */
-
-#define ICIndexInv		((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
-#define DCIndexWBInv		((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
-#define DCIndexInv		DCIndexWBInv
-#define ICIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
-#define DCIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
-#define ICIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
-#define DCIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
-#define ICHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
-#define DCHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
-#define ICFill			((K_CacheFill << S_CacheFunc) | K_CachePriI)
-#define DCHitWBInv		((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
-#define DCHitWB			((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
-#define ICFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
-#define DCFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)
-
-
-/*
- *************************************************************************
- *          P R E F E T C H   I N S T R U C T I O N   H I N T S          *
- *************************************************************************
- */
-
-#define PrefLoad		0
-#define PrefStore		1
-#define PrefLoadStreamed	4
-#define PrefStoreStreamed	5
-#define PrefLoadRetained	6
-#define PrefStoreRetained	7
-#define PrefWBInval		25
-#define PrefNudge		25
-
-
-/*
- *************************************************************************
- *             C P U   R E G I S T E R   D E F I N I T I O N S           *
- *************************************************************************
- */
-
-
-/*
- *************************************************************************
- *                  S O F T W A R E   G P R   N A M E S                  *
- *************************************************************************
- */
-#ifdef __ASSEMBLY__
-#define zero			 $0
-#define AT			 $1
-#define v0			 $2
-#define v1			 $3
-#define a0			 $4
-#define a1			 $5
-#define a2			 $6
-#define a3			 $7
-#define t0			 $8
-#define t1			 $9
-#define t2			$10
-#define t3			$11
-#define t4			$12
-#define t5			$13
-#define t6			$14
-#define t7			$15
-#define s0			$16
-#define s1			$17
-#define s2			$18
-#define s3			$19
-#define s4			$20
-#define s5			$21
-#define s6			$22
-#define s7			$23
-#define t8			$24
-#define t9			$25
-#define k0			$26
-#define k1			$27
-#define gp			$28
-#define sp			$29
-#define fp			$30
-#define ra			$31
-
-/*
- * The following registers are used by the AVP environment and
- * are not part of the normal software definitions.
- */
-
-#ifdef MIPSAVPENV
-#define repc			$25			/* Expected exception PC */
-#define tid			$30			/* Current test case address */
-#endif
-
-
-/*
- *************************************************************************
- *                  H A R D W A R E   G P R   N A M E S                  *
- *************************************************************************
- *
- * In the AVP environment, several of the `r' names are removed from the
- * name space because they are used by the kernel for special purposes.
- * Removing them causes assembly rather than runtime errors for tests that
- * use the `r' names.
- *
- *	- r25 (repc) is used as the expected PC on an exception
- *	- r26-r27 (k0, k1) are used in the exception handler
- *	- r30 (tid) is used as the current test address
- */
-
-#define r0			 $0
-#define r1			 $1
-#define r2			 $2
-#define r3			 $3
-#define r4			 $4
-#define r5			 $5
-#define r6			 $6
-#define r7			 $7
-#define r8			 $8
-#define r9			 $9
-#define r10			$10
-#define r11			$11
-#define r12			$12
-#define r13			$13
-#define r14			$14
-#define r15			$15
-#define r16			$16
-#define r17			$17
-#define r18			$18
-#define r19			$19
-#define r20			$20
-#define r21			$21
-#define r22			$22
-#define r23			$23
-#define r24			$24
-#ifdef MIPSAVPENV
-#define r25			r25_unknown
-#define r26			r26_unknown
-#define r27			r27_unknown
-#else
-#define r25			$25
-#define r26			$26
-#define r27			$27
-#endif
-#define r28			$28
-#define r29			$29
-#ifdef MIPSAVPENV
-#define r30			r30_unknown
-#else
-#define r30			$30
-#endif
-#define r31			$31
-
-#endif
-
-/*
- *************************************************************************
- *                H A R D W A R E   G P R   I N D I C E S                *
- *************************************************************************
- *
- * These definitions provide the index (number) of the GPR, as opposed
- * to the assembler register name ($n).
- */
-
-#define R_r0			 0
-#define R_r1			 1
-#define R_r2			 2
-#define R_r3			 3
-#define R_r4			 4
-#define R_r5			 5
-#define R_r6			 6
-#define R_r7			 7
-#define R_r8			 8
-#define R_r9			 9
-#define R_r10			10
-#define R_r11			11
-#define R_r12			12
-#define R_r13			13
-#define R_r14			14
-#define R_r15			15
-#define R_r16			16
-#define R_r17			17
-#define R_r18			18
-#define R_r19			19
-#define R_r20			20
-#define R_r21			21
-#define R_r22			22
-#define R_r23			23
-#define R_r24			24
-#define R_r25			25
-#define R_r26			26
-#define R_r27			27
-#define R_r28			28
-#define R_r29			29
-#define R_r30			30
-#define R_r31			31
-#define R_hi			32			/* Hi register */
-#define R_lo			33			/* Lo register */
-
-
-/*
- *************************************************************************
- *                  S O F T W A R E   G P R   M A S K S                  *
- *************************************************************************
- *
- * These definitions provide the bit mask corresponding to the GPR number
- */
-
-#define M_AT			 (1<<1)
-#define M_v0			 (1<<2)
-#define M_v1			 (1<<3)
-#define M_a0			 (1<<4)
-#define M_a1			 (1<<5)
-#define M_a2			 (1<<6)
-#define M_a3			 (1<<7)
-#define M_t0			 (1<<8)
-#define M_t1			 (1<<9)
-#define M_t2			(1<<10)
-#define M_t3			(1<<11)
-#define M_t4			(1<<12)
-#define M_t5			(1<<13)
-#define M_t6			(1<<14)
-#define M_t7			(1<<15)
-#define M_s0			(1<<16)
-#define M_s1			(1<<17)
-#define M_s2			(1<<18)
-#define M_s3			(1<<19)
-#define M_s4			(1<<20)
-#define M_s5			(1<<21)
-#define M_s6			(1<<22)
-#define M_s7			(1<<23)
-#define M_t8			(1<<24)
-#define M_t9			(1<<25)
-#define M_k0			(1<<26)
-#define M_k1			(1<<27)
-#define M_gp			(1<<28)
-#define M_sp			(1<<29)
-#define M_fp			(1<<30)
-#define M_ra			(1<<31)
-
-
-/*
- *************************************************************************
- *             C P 0   R E G I S T E R   D E F I N I T I O N S           *
- *************************************************************************
- * Each register has the following definitions:
- *
- *	C0_rrr		The register number (as a $n value)
- *	R_C0_rrr	The register index (as an integer corresponding
- *			to the register number)
- *
- * Each field in a register has the following definitions:
- *
- *	S_rrrfff	The shift count required to right-justify
- *			the field.  This corresponds to the bit
- *			number of the right-most bit in the field.
- *	M_rrrfff	The Mask required to isolate the field.
- *
- * Register diagrams included below as comments correspond to the
- * MIPS32 and MIPS64 architecture specifications.  Refer to other
- * sources for register diagrams for older architectures.
- */
-
-
-/*
- ************************************************************************
- *                 I N D E X   R E G I S T E R   ( 0 )                  *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |P|                         0                       |   Index   | Index
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Index		$0
-#define R_C0_Index		0
-#define C0_INX			C0_Index		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_IndexP		31			/* Probe failure (R)*/
-#define M_IndexP		(0x1 << S_IndexP)
-
-#define S_IndexIndex		0			/* TLB index (R/W)*/
-#define M_IndexIndex		(0x3f << S_IndexIndex)
-
-#define M_Index0Fields		0x7fffffc0
-#define M_IndexRFields		0x80000000
-
-
-/*
- ************************************************************************
- *                R A N D O M   R E G I S T E R   ( 1 )                 *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                            0                      |   Index   | Random
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Random		$1
-#define R_C0_Random		1
-#define C0_RAND			$1			/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_RandomIndex		0			/* TLB random index (R)*/
-#define M_RandomIndex		(0x3f << S_RandomIndex)
-
-#define M_Random0Fields		0xffffffc0
-#define M_RandomRFields		0x0000003f
-
-
-/*
- ************************************************************************
- *              E N T R Y L O 0   R E G I S T E R   ( 2 )               *
- ************************************************************************
- *
- *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * | Fill (0) //| 0 |                     PFN                       |  C  |D|V|G| EntryLo0
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_EntryLo0		$2
-#define R_C0_EntryLo0		2
-#define C0_TLBLO_0		C0_EntryLo0		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_EntryLoPFN		6			/* PFN (R/W) */
-#define M_EntryLoPFN		(0xffffff << S_EntryLoPFN)
-#define S_EntryLoC		3			/* Coherency attribute (R/W) */
-#define M_EntryLoC		(0x7 << S_EntryLoC)
-#define S_EntryLoD		2			/* Dirty (R/W) */
-#define M_EntryLoD		(0x1 << S_EntryLoD)
-#define S_EntryLoV		1			/* Valid (R/W) */
-#define M_EntryLoV		(0x1 << S_EntryLoV)
-#define S_EntryLoG		0			/* Global (R/W) */
-#define M_EntryLoG		(0x1 << S_EntryLoG)
-#define M_EntryLoOddPFN		(0x1 << S_EntryLoPFN)	/* Odd PFN bit */
-#define S_EntryLo_RS		K_PageAlign		/* Right-justify PFN */
-#define S_EntryLo_LS		S_EntryLoPFN		/* Position PFN to appropriate position */
-
-#define M_EntryLo0Fields	0x00000000
-#define M_EntryLoRFields	0xc0000000
-#define M_EntryLo0Fields64	UNS64Const(0x0000000000000000)
-#define M_EntryLoRFields64	UNS64Const(0xffffffffc0000000)
-
-/*
- * Cache attribute values in the C field of EntryLo and the
- * K0 field of Config
- */
-#define K_CacheAttrCWTnWA	0			/* Cacheable, write-thru, no write allocate */
-#define K_CacheAttrCWTWA	1			/* Cacheable, write-thru, write allocate */
-#define K_CacheAttrU		2			/* Uncached */
-#define K_CacheAttrC		3			/* Cacheable */
-#define K_CacheAttrCN		3			/* Cacheable, non-coherent */
-#define K_CacheAttrCCE		4			/* Cacheable, coherent, exclusive */
-#define K_CacheAttrCCS		5			/* Cacheable, coherent, shared */
-#define K_CacheAttrCCU		6			/* Cacheable, coherent, update */
-#define K_CacheAttrUA		7			/* Uncached accelerated */
-
-
-/*
- ************************************************************************
- *              E N T R Y L O 1   R E G I S T E R   ( 3 )               *
- ************************************************************************
- *
- *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * | Fill (0) //| 0 |                     PFN                       |  C  |D|V|G| EntryLo1
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_EntryLo1		$3
-#define R_C0_EntryLo1		3
-#define C0_TLBLO_1		C0_EntryLo1		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-/*
- * Field definitions are as given for EntryLo0 above
- */
-
-
-/*
- ************************************************************************
- *               C O N T E X T   R E G I S T E R   ( 4 )                *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //       PTEBase    |            BadVPN<31:13>            |   0   | Context
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Context		$4
-#define R_C0_Context		4
-#define C0_CTXT			C0_Context		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_ContextPTEBase	23			/* PTE base (R/W) */
-#define M_ContextPTEBase	(0x1ff << S_ContextPTEBase)
-#define S_ContextBadVPN		4			/* BadVPN2 (R) */
-#define M_ContextBadVPN		(0x7ffff << S_ContextBadVPN)
-#define S_ContextBadVPN_LS	9			/* Position BadVPN to bit 31 */
-#define S_ContextBadVPN_RS	13			/* Right-justify shifted BadVPN field */
-
-#define M_Context0Fields	0x0000000f
-#define M_ContextRFields	0x007ffff0
-#define M_Context0Fields64	UNS64Const(0x000000000000000f)
-#define M_ContextRFields64	UNS64Const(0x00000000007ffff0)
-
-
-/*
- ************************************************************************
- *              P A G E M A S K   R E G I S T E R   ( 5 )               *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |      0      |        Mask           |            0            | PageMask
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_PageMask		$5
-#define R_C0_PageMask		5			/* Mask (R/W) */
-#define C0_PGMASK		C0_PageMask		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_PageMaskMask		13
-#define M_PageMaskMask		(0xfff << S_PageMaskMask)
-
-#define M_PageMask0Fields	0xfe001fff
-#define M_PageMaskRFields	0x00000000
-
-/*
- * Values in the Mask field
- */
-#define K_PageMask4K		0x000			/* K_PageMasknn values are values for use */
-#define K_PageMask16K		0x003			/* with KReqPageAttributes or KReqPageMask macros */
-#define K_PageMask64K		0x00f
-#define K_PageMask256K		0x03f
-#define K_PageMask1M		0x0ff
-#define K_PageMask4M		0x3ff
-#define K_PageMask16M		0xfff
-
-#define M_PageMask4K		(K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */
-#define M_PageMask16K		(K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */
-#define M_PageMask64K		(K_PageMask64K << S_PageMaskMask)
-#define M_PageMask256K		(K_PageMask256K << S_PageMaskMask)
-#define M_PageMask1M		(K_PageMask1M << S_PageMaskMask)
-#define M_PageMask4M		(K_PageMask4M << S_PageMaskMask)
-#define M_PageMask16M		(K_PageMask16M << S_PageMaskMask)
-
-
-/*
- ************************************************************************
- *                 W I R E D   R E G I S T E R   ( 6 )                  *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                            0                      |   Index   | Wired
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Wired		$6
-#define R_C0_Wired		6
-#define C0_TLBWIRED		C0_Wired		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_WiredIndex		0			/* TLB wired boundary (R/W) */
-#define M_WiredIndex		(0x3f << S_WiredIndex)
-
-#define M_Wired0Fields		0xffffffc0
-#define M_WiredRFields		0x00000000
-
-
-/*
- ************************************************************************
- *              B A D V A D D R   R E G I S T E R   ( 8 )               *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                     Bad Virtual Address                        | BadVAddr
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_BadVAddr		$8
-#define R_C0_BadVAddr		8
-#define C0_BADVADDR		C0_BadVAddr		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_BadVAddrOddPage	K_PageSize		/* Even/Odd VA bit for pair of PAs */
-
-#define M_BadVAddr0Fields	0x00000000
-#define M_BadVAddrRFields	0xffffffff
-#define M_BadVAddr0Fields64	UNS64Const(0x0000000000000000)
-#define M_BadVAddrRFields64	UNS64Const(0xffffffffffffffff)
-
-/*
- ************************************************************************
- *                 C O U N T   R E G I S T E R   ( 9 )                  *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                         Count Value                           | Count
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Count		$9
-#define R_C0_Count		9
-#define C0_COUNT		C0_Count		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_Count0Fields		0x00000000
-#define M_CountRFields		0x00000000
-
-
-/*
- ************************************************************************
- *              E N T R Y H I   R E G I S T E R   ( 1 0 )               *
- ************************************************************************
- *
- *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * | R | Fill //                 VPN2                 |    0    |     ASID      | EntryHi
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_EntryHi		$10
-#define R_C0_EntryHi		10
-#define C0_TLBHI		C0_EntryHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_EntryHiR64		62			/* Region (R/W) */
-#define M_EntryHiR64		UNS64Const(0xc000000000000000)
-#define S_EntryHiVPN2		13			/* VPN/2 (R/W) */
-#define M_EntryHiVPN2		(0x7ffff << S_EntryHiVPN2)
-#define M_EntryHiVPN264		UNS64Const(0x000000ffffffe000)
-#define S_EntryHiASID		0			/* ASID (R/W) */
-#define M_EntryHiASID		(0xff << S_EntryHiASID)
-#define S_EntryHiVPN_Shf	S_EntryHiVPN2
-
-#define M_EntryHi0Fields	0x00001f00
-#define M_EntryHiRFields	0x00000000
-#define M_EntryHi0Fields64	UNS64Const(0x0000000000001f00)
-#define M_EntryHiRFields64	UNS64Const(0x3fffff0000000000)
-
-
-/*
- ************************************************************************
- *              C O M P A R E   R E G I S T E R   ( 1 1 )               *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                        Compare Value                          | Compare
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Compare		$11
-#define R_C0_Compare		11
-#define C0_COMPARE		C0_Compare		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_Compare0Fields	0x00000000
-#define M_CompareRFields	0x00000000
-
-
-/*
- ************************************************************************
- *               S T A T U S   R E G I S T E R   ( 1 2 )                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I|
- * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status
- * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Status		$12
-#define R_C0_Status		12
-#define C0_SR			C0_Status		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_StatusCU		28			/* Coprocessor enable (R/W) */
-#define M_StatusCU		(0xf << S_StatusCU)
-#define S_StatusCU3		31
-#define M_StatusCU3     	(0x1 << S_StatusCU3)
-#define S_StatusCU2		30
-#define M_StatusCU2		(0x1 << S_StatusCU2)
-#define S_StatusCU1		29
-#define M_StatusCU1		(0x1 << S_StatusCU1)
-#define S_StatusCU0		28
-#define M_StatusCU0		(0x1 << S_StatusCU0)
-#define S_StatusRP		27			/* Enable reduced power mode (R/W) */
-#define M_StatusRP		(0x1 << S_StatusRP)
-#define S_StatusFR		26			/* Enable 64-bit FPRs (MIPS64 only) (R/W) */
-#define M_StatusFR		(0x1 << S_StatusFR)
-#define S_StatusRE		25			/* Enable reverse endian (R/W) */
-#define M_StatusRE		(0x1 << S_StatusRE)
-#define S_StatusMX		24			/* Enable access to MDMX resources (MIPS64 only) (R/W) */
-#define M_StatusMX		(0x1 << S_StatusMX)
-#define S_StatusPX		23			/* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */
-#define M_StatusPX		(0x1 << S_StatusPX)
-#define S_StatusBEV		22			/* Enable Boot Exception Vectors (R/W) */
-#define M_StatusBEV		(0x1 << S_StatusBEV)
-#define S_StatusTS		21			/* Denote TLB shutdown (R/W) */
-#define M_StatusTS		(0x1 << S_StatusTS)
-#define S_StatusSR		20			/* Denote soft reset (R/W) */
-#define M_StatusSR		(0x1 << S_StatusSR)
-#define S_StatusNMI		19
-#define M_StatusNMI		(0x1 << S_StatusNMI)	/* Denote NMI (R/W) */
-#define S_StatusIM		8			/* Interrupt mask (R/W) */
-#define M_StatusIM		(0xff << S_StatusIM)
-#define S_StatusIM7		15
-#define M_StatusIM7		(0x1 << S_StatusIM7)
-#define S_StatusIM6		14
-#define M_StatusIM6		(0x1 << S_StatusIM6)
-#define S_StatusIM5		13
-#define M_StatusIM5		(0x1 << S_StatusIM5)
-#define S_StatusIM4		12
-#define M_StatusIM4		(0x1 << S_StatusIM4)
-#define S_StatusIM3		11
-#define M_StatusIM3		(0x1 << S_StatusIM3)
-#define S_StatusIM2		10
-#define M_StatusIM2		(0x1 << S_StatusIM2)
-#define S_StatusIM1		9
-#define M_StatusIM1		(0x1 << S_StatusIM1)
-#define S_StatusIM0		8
-#define M_StatusIM0		(0x1 << S_StatusIM0)
-#define S_StatusKX		7			/* Enable access to extended kernel addresses (MIPS64 only) (R/W) */
-#define M_StatusKX		(0x1 << S_StatusKX)
-#define S_StatusSX		6			/* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */
-#define M_StatusSX		(0x1 << S_StatusSX)
-#define S_StatusUX		5			/* Enable access to extended user addresses (MIPS64 only) (R/W) */
-#define M_StatusUX		(0x1 << S_StatusUX)
-#define S_StatusKSU		3			/* Two-bit current mode (R/W) */
-#define M_StatusKSU		(0x3 << S_StatusKSU)
-#define S_StatusUM		4			/* User mode if supervisor mode not implemented (R/W) */
-#define M_StatusUM		(0x1 << S_StatusUM)
-#define S_StatusSM		3			/* Supervisor mode (R/W) */
-#define M_StatusSM		(0x1 << S_StatusSM)
-#define S_StatusERL		2			/* Denotes error level (R/W) */
-#define M_StatusERL		(0x1 << S_StatusERL)
-#define S_StatusEXL		1			/* Denotes exception level (R/W) */
-#define M_StatusEXL		(0x1 << S_StatusEXL)
-#define S_StatusIE		0			/* Enables interrupts (R/W) */
-#define M_StatusIE		(0x1 << S_StatusIE)
-
-#define M_Status0Fields		0x00040000
-#define M_StatusRFields		0x058000e0		/* FR, MX, PX, KX, SX, UX unused in MIPS32 */
-#define M_Status0Fields64	0x00040000
-#define M_StatusRFields64	0x00000000
-
-/*
- * Values in the KSU field
- */
-#define K_StatusKSU_U		2			/* User mode in KSU field */
-#define K_StatusKSU_S		1			/* Supervisor mode in KSU field */
-#define K_StatusKSU_K		0			/* Kernel mode in KSU field */
-
-
-/*
- ************************************************************************
- *                C A U S E   R E G I S T E R   ( 1 3 )                 *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |B| | C |       |I|W|           |I|I|I|I|I|I|I|I| |         | R |
- * |D| | E | Rsvd  |V|P|    Rsvd   |P|P|P|P|P|P|P|P| | ExcCode | s | Cause
- * | | |   |       | | |           |7|6|5|4|3|2|1|0| |         | v |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Cause		$13
-#define R_C0_Cause		13
-#define C0_CAUSE		C0_Cause		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_CauseBD		31
-#define M_CauseBD		(0x1 << S_CauseBD)
-#define S_CauseCE		28
-#define M_CauseCE		(0x3<< S_CauseCE)
-#define S_CauseIV		23
-#define M_CauseIV		(0x1 << S_CauseIV)
-#define S_CauseWP		22
-#define M_CauseWP		(0x1 << S_CauseWP)
-#define S_CauseIP		8
-#define M_CauseIP		(0xff << S_CauseIP)
-#define S_CauseIPEXT		10
-#define M_CauseIPEXT		(0x3f << S_CauseIPEXT)
-#define S_CauseIP7		15
-#define M_CauseIP7		(0x1 << S_CauseIP7)
-#define S_CauseIP6		14
-#define M_CauseIP6		(0x1 << S_CauseIP6)
-#define S_CauseIP5		13
-#define M_CauseIP5		(0x1 << S_CauseIP5)
-#define S_CauseIP4		12
-#define M_CauseIP4		(0x1 << S_CauseIP4)
-#define S_CauseIP3		11
-#define M_CauseIP3		(0x1 << S_CauseIP3)
-#define S_CauseIP2		10
-#define M_CauseIP2		(0x1 << S_CauseIP2)
-#define S_CauseIP1		9
-#define M_CauseIP1		(0x1 << S_CauseIP1)
-#define S_CauseIP0		8
-#define M_CauseIP0		(0x1 << S_CauseIP0)
-#define S_CauseExcCode		2
-#define M_CauseExcCode		(0x1f << S_CauseExcCode)
-
-#define M_Cause0Fields		0x4f3f0083
-#define M_CauseRFields		0xb000fc7c
-
-/*
- * Values in the CE field
- */
-#define K_CauseCE0		0			/* Coprocessor 0 in the CE field */
-#define K_CauseCE1		1			/* Coprocessor 1 in the CE field */
-#define K_CauseCE2		2			/* Coprocessor 2 in the CE field */
-#define K_CauseCE3		3			/* Coprocessor 3 in the CE field */
-
-/*
- * Values in the ExcCode field
- */
-#define	EX_INT			0			/* Interrupt */
-#define	EXC_INT			(EX_INT << S_CauseExcCode)
-#define	EX_MOD			1			/* TLB modified */
-#define	EXC_MOD			(EX_MOD << S_CauseExcCode)
-#define	EX_TLBL		        2			/* TLB exception (load or ifetch) */
-#define	EXC_TLBL		(EX_TLBL << S_CauseExcCode)
-#define	EX_TLBS		        3			/* TLB exception (store) */
-#define	EXC_TLBS		(EX_TLBS << S_CauseExcCode)
-#define	EX_ADEL		        4			/* Address error (load or ifetch) */
-#define	EXC_ADEL		(EX_ADEL << S_CauseExcCode)
-#define	EX_ADES		        5			/* Address error (store) */
-#define	EXC_ADES		(EX_ADES << S_CauseExcCode)
-#define	EX_IBE			6			/* Instruction Bus Error */
-#define	EXC_IBE			(EX_IBE << S_CauseExcCode)
-#define	EX_DBE			7			/* Data Bus Error */
-#define	EXC_DBE			(EX_DBE << S_CauseExcCode)
-#define	EX_SYS			8			/* Syscall */
-#define	EXC_SYS			(EX_SYS << S_CauseExcCode)
-#define	EX_SYSCALL		EX_SYS
-#define	EXC_SYSCALL		EXC_SYS
-#define	EX_BP			9			/* Breakpoint */
-#define	EXC_BP			(EX_BP << S_CauseExcCode)
-#define	EX_BREAK		EX_BP
-#define	EXC_BREAK		EXC_BP
-#define	EX_RI			10			/* Reserved instruction */
-#define	EXC_RI			(EX_RI << S_CauseExcCode)
-#define	EX_CPU			11			/* CoProcessor Unusable */
-#define	EXC_CPU			(EX_CPU << S_CauseExcCode)
-#define	EX_OV			12			/* OVerflow */
-#define	EXC_OV			(EX_OV << S_CauseExcCode)
-#define	EX_TR		    	13			/* Trap instruction */
-#define	EXC_TR			(EX_TR << S_CauseExcCode)
-#define	EX_TRAP			EX_TR
-#define	EXC_TRAP		EXC_TR
-#define EX_FPE			15			/* floating point exception */
-#define EXC_FPE			(EX_FPE << S_CauseExcCode)
-#define EX_C2E			18			/* COP2 exception */
-#define EXC_C2E			(EX_C2E << S_CauseExcCode)
-#define EX_MDMX			22			/* MDMX exception */
-#define EXC_MDMX		(EX_MDMX << S_CauseExcCode)
-#define EX_WATCH		23			/* Watch exception */
-#define EXC_WATCH		(EX_WATCH << S_CauseExcCode)
-#define	EX_MCHECK	        24			/* Machine check exception */
-#define	EXC_MCHECK 		(EX_MCHECK << S_CauseExcCode)
-#define	EX_CacheErr	        30			/* Cache error caused re-entry to Debug Mode */
-#define	EXC_CacheErr 		(EX_CacheErr << S_CauseExcCode)
-
-
-/*
- ************************************************************************
- *                   E P C   R E G I S T E R   ( 1 4 )                  *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                        Exception PC                            | EPC
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_EPC			$14
-#define R_C0_EPC		14
-
-#define M_EPC0Fields		0x00000000
-#define M_EPCRFields		0x00000000
-#define M_EPC0Fields64		UNS64Const(0x0000000000000000)
-#define M_EPCRFields64		UNS64Const(0x0000000000000000)
-
-/*
- ************************************************************************
- *                  P R I D   R E G I S T E R   ( 1 5 )                 *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  Company Opts |   Company ID  |  Procesor ID  |   Revision    | PRId
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_PRId			$15
-#define R_C0_PRId		15
-#define C0_PRID			C0_PRID			/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_PRIdCoOpt		24			/* Company options (R) */
-#define M_PRIdCoOpt		(0xff << S_PRIdCoOpt)
-#define S_PRIdCoID		16			/* Company ID (R) */
-#define M_PRIdCoID		(0xff << S_PRIdCoID)
-#define S_PRIdImp		8			/* Implementation ID (R) */
-#define M_PRIdImp		(0xff << S_PRIdImp)
-#define S_PRIdRev		0			/* Revision (R) */
-#define M_PRIdRev		(0xff << S_PRIdRev)
-
-#define M_PRId0Fields		0x00000000
-#define M_PRIdRFields		0xffffffff
-/*
- * Values in the Company ID field
- */
-#define K_PRIdCoID_MIPS	1
-#define K_PRIdCoID_Broadcom 2
-#define K_PRIdCoID_Alchemy 3
-#define K_PRIdCoID_SiByte 4
-#define K_PRIdCoID_SandCraft 5
-#define K_PRIdCoID_Philips 6
-#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */
-
-
-/*
- * Values in the implementation number field
- */
-#define K_PRIdImp_Jade		0x80
-#define K_PRIdImp_Opal		0x81
-#define K_PRIdImp_Ruby		0x82
-#define K_PRIdImp_JadeLite	0x83
-#define K_PRIdImp_4KEc          0x84    /* Emerald with TLB MMU */
-#define K_PRIdImp_4KEmp         0x85    /* Emerald with FM MMU */
-#define K_PRIdImp_4KSc          0x86    /* Coral */
-
-#define K_PRIdImp_R3000		0x01
-#define K_PRIdImp_R4000		0x04
-#define K_PRIdImp_R10000	0x09
-#define K_PRIdImp_R4300		0x0b
-#define K_PRIdImp_R5000		0x23
-#define K_PRIdImp_R5200		0x28
-#define K_PRIdImp_R5400		0x54
-
-/*
- ************************************************************************
- *               C O N F I G   R E G I S T E R   ( 1 6 )                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |M|                             |B| A |  A  |               | K | Config
- * | | Reserved for Implementations|E| T |  R  |    Reserved   | 0 |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Config		$16
-#define R_C0_Config		16
-#define C0_CONFIG		C0_Config		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_ConfigMore		31			/* Additional config registers present (R) */
-#define M_ConfigMore		(0x1 << S_ConfigMore)
-#define S_ConfigImpl		16			/* Implementation-specific fields */
-#define M_ConfigImpl		(0x7fff << S_ConfigImpl)
-#define S_ConfigBE		15			/* Denotes big-endian operation (R) */
-#define M_ConfigBE		(0x1 << S_ConfigBE)
-#define S_ConfigAT		13			/* Architecture type (R) */
-#define M_ConfigAT		(0x3 << S_ConfigAT)
-#define S_ConfigAR		10			/* Architecture revision (R) */
-#define M_ConfigAR		(0x7 << S_ConfigAR)
-#define S_ConfigMT		7			/* MMU Type (R) */
-#define M_ConfigMT		(0x7 << S_ConfigMT)
-#define S_ConfigK0		0			/* Kseg0 coherency algorithm (R/W) */
-#define M_ConfigK0		(0x7 << S_ConfigK0)
-
-/*
- * The following definitions are technically part of the "reserved for
- * implementations" field, but are the semi-standard definition used in
- * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3
- * references.  For that reason, they are included here, but may be
- * overridden by true implementation-specific definitions
- */
-#define S_ConfigK23		28			/* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */
-#define M_ConfigK23		(0x7 << S_ConfigK23)
-#define S_ConfigKU		25			/* Kuseg coherency algorithm (FM MMU only) (R/W) */
-#define M_ConfigKU		(0x7 << S_ConfigKU)
-
-#define M_Config0Fields		0x00000078
-#define M_ConfigRFields		0x8000ff80
-
-/*
- * Values in the AT field
- */
-#define K_ConfigAT_MIPS32	0			/* MIPS32 */
-#define K_ConfigAT_MIPS64S	1			/* MIPS64 with 32-bit addresses */
-#define K_ConfigAT_MIPS64	2			/* MIPS64 with 32/64-bit addresses */
-
-/*
- * Values in the MT field
- */
-#define K_ConfigMT_NoMMU	0			/* No MMU */
-#define K_ConfigMT_TLBMMU	1			/* Standard TLB MMU */
-#define K_ConfigMT_BATMMU	2			/* Standard BAT MMU */
-#define K_ConfigMT_FMMMU	3			/* Standard Fixed Mapping MMU */
-
-
-/*
- ************************************************************************
- *         C O N F I G 1   R E G I S T E R   ( 1 6, SELECT 1 )          *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |M|  MMU Size |  IS |  IL |  IA |  DS |  DL |  DA |C|M|P|W|C|E|F| Config1
- * | |           |     |     |     |     |     |     |2|D|C|R|A|P|P|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Config1		$16,1
-#define R_C0_Config1		16
-
-#define S_Config1More		31			/* Additional Config registers present (R) */
-#define M_Config1More		(0x1 << S_Config1More)
-#define S_Config1MMUSize 	25			/* Number of MMU entries - 1 (R) */
-#define M_Config1MMUSize 	(0x3f << S_Config1MMUSize)
-#define S_Config1IS		22			/* Icache sets per way (R) */
-#define M_Config1IS		(0x7 << S_Config1IS)
-#define S_Config1IL		19			/* Icache line size (R) */
-#define M_Config1IL		(0x7 << S_Config1IL)
-#define S_Config1IA		16			/* Icache associativity - 1 (R) */
-#define M_Config1IA		(0x7 << S_Config1IA)
-#define S_Config1DS		13			/* Dcache sets per way (R) */
-#define M_Config1DS		(0x7 << S_Config1DS)
-#define S_Config1DL		10			/* Dcache line size (R) */
-#define M_Config1DL		(0x7 << S_Config1DL)
-#define S_Config1DA		7			/* Dcache associativity (R) */
-#define M_Config1DA		(0x7 << S_Config1DA)
-#define S_Config1C2		6			/* Coprocessor 2 present (R) */
-#define M_Config1C2		(0x1 << S_Config1C2)
-#define S_Config1MD		5			/* Denotes MDMX present (R) */
-#define M_Config1MD		(0x1 << S_Config1MD)
-#define S_Config1PC		4			/* Denotes performance counters present (R) */
-#define M_Config1PC		(0x1 << S_Config1PC)
-#define S_Config1WR		3			/* Denotes watch registers present (R) */
-#define M_Config1WR		(0x1 << S_Config1WR)
-#define S_Config1CA		2			/* Denotes MIPS-16 present (R) */
-#define M_Config1CA		(0x1 << S_Config1CA)
-#define S_Config1EP		1			/* Denotes EJTAG present (R) */
-#define M_Config1EP		(0x1 << S_Config1EP)
-#define S_Config1FP		0			/* Denotes floating point present (R) */
-#define M_Config1FP		(0x1 << S_Config1FP)
-
-#define M_Config10Fields	0x00000060
-#define M_Config1RFields	0x7fffff9f
-
-/*
- * The following macro generates a table that is indexed
- * by the Icache or Dcache sets field in Config1 and
- * contains the decoded value of sets per way
- */
-#define Config1CacheSets()	\
-	HALF(64);		\
-	HALF(128);		\
-	HALF(256);		\
-	HALF(512);		\
-	HALF(1024);		\
-	HALF(2048);		\
-	HALF(4096);		\
-	HALF(8192);
-
-/*
- * The following macro generates a table that is indexed
- * by the Icache or Dcache line size field in Config1 and
- * contains the decoded value of the cache line size, in bytes
- */
-#define Config1CacheLineSize()	\
-	HALF(0);		\
-	HALF(4);		\
-	HALF(8);		\
-	HALF(16);		\
-	HALF(32);		\
-	HALF(64);		\
-	HALF(128);		\
-	HALF(256);
-
-
-/*
- ************************************************************************
- *         C O N F I G 2   R E G I S T E R   ( 1 6, SELECT 2 )          *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |M|           |     |     |     |     |     |     | | | | | |S|T| Config1
- * | |           |     |     |     |     |     |     | | | | | |M|L|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Config2		$16,2
-#define R_C0_Config2		16
-
-#define S_Config2More		31			/* Additional Config registers present (R) */
-#define M_Config2More		(0x1 << S_Config2More)
-#define S_Config2SM		1			/* Denotes SmartMIPS ASE present (R) */
-#define M_Config2SM		(0x1 << S_Config2SM)
-#define S_Config2TL		0			/* Denotes Tracing Logic present (R) */
-#define M_Config2TL		(0x1 << S_Config2TL)
-
-#define M_Config20Fields	0xfffffffc
-#define M_Config2RFields	0x00000003
-
-/*
- ************************************************************************
- *                L L A D D R   R E G I S T E R   ( 1 7 )               *
- ************************************************************************
- *
- *  6 6    3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 2    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |    //                      LL Physical Address                       | LLAddr
- * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_LLAddr		$17
-#define R_C0_LLAddr		17
-#define C0_LLADDR		C0_LLAddr		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_LLAddr0Fields		0x00000000
-#define M_LLAddrRFields		0x00000000
-#define M_LLAddr0Fields64	UNS64Const(0x0000000000000000)
-#define M_LLAddrRFields64	UNS64Const(0x0000000000000000)
-
-
-/*
- ************************************************************************
- *               W A T C H L O   R E G I S T E R   ( 1 8 )              *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                    Watch Virtual Address                 |I|R|W| WatchLo
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_WatchLo		$18
-#define R_C0_WatchLo		18
-#define C0_WATCHLO		C0_WatchLo		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_WatchLoVAddr		3			/* Watch virtual address (R/W) */
-#define M_WatchLoVAddr		(0x1fffffff << S_WatchLoVAddr)
-#define S_WatchLoI		2			/* Enable Istream watch (R/W) */
-#define M_WatchLoI		(0x1 << S_WatchLoI)
-#define S_WatchLoR		1			/* Enable data read watch (R/W) */
-#define M_WatchLoR		(0x1 << S_WatchLoR)
-#define S_WatchLoW		0			/* Enable data write watch (R/W) */
-#define M_WatchLoW		(0x1 << S_WatchLoW)
-
-#define M_WatchLo0Fields	0x00000000
-#define M_WatchLoRFields	0x00000000
-#define M_WatchLo0Fields64	UNS64Const(0x0000000000000000)
-#define M_WatchLoRFields64	UNS64Const(0x0000000000000000)
-
-#define M_WatchLoEnables	(M_WatchLoI | M_WatchLoR | M_WatchLoW)
-
-
-/*
- ************************************************************************
- *               W A T C H H I   R E G I S T E R   ( 1 9 )              *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |M|G|    Rsvd   |      ASID     |  Rsvd |       Mask      |  0  | WatchHi
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_WatchHi		$19
-#define R_C0_WatchHi		19
-#define C0_WATCHHI		C0_WatchHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_WatchHiM		31			/* Denotes additional Watch registers present (R) */
-#define M_WatchHiM		(0x1 << S_WatchHiM)
-#define S_WatchHiG		30			/* Enable ASID-independent Watch match (R/W) */
-#define M_WatchHiG		(0x1 << S_WatchHiG)
-#define S_WatchHiASID		16			/* ASID value to match (R/W) */
-#define M_WatchHiASID		(0xff << S_WatchHiASID)
-#define S_WatchHiMask		3			/* Address inhibit mask (R/W) */
-#define M_WatchHiMask		(0x1ff << S_WatchHiMask)
-
-#define M_WatchHi0Fields	0x3f00f007
-#define M_WatchHiRFields	0x80000000
-
-
-/*
- ************************************************************************
- *             X C O N T E X T   R E G I S T E R   ( 2 0 )              *
- ************************************************************************
- *
- *  6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  // PTEBase  | R |                      BadVPN2<39:13>                 |   0   | XContext
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_XContext		$20
-#define R_C0_XContext		20
-#define C0_EXTCTXT		C0_XContext		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_XContextBadVPN2	4			/* BadVPN2 (R) */
-#define S_XContextBadVPN	S_XContextBadVPN2
-
-#define M_XContext0Fields	0x0000000f
-
-
-/*
- ************************************************************************
- *                 D E B U G   R E G I S T E R   ( 2 3 )                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |D|D|N|L|D|H|C|I|M|C|D|I|D|D|     |         |N|S|   |D|D|D|D|D|D|
- * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S|   |I|I|D|D|B|S|
- * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver |         |S|t|   |N|B|B|B|p|S|
- * | | |C|M|e|t|n|s|e|h|s|I|S|L|     |         |S| | 0 |T| |S|L| | | Debug
- * | | |R| | | |t|E|c|e|E| |I|I|     |         |t| |   | | | | | | |
- * | | | | | | |D|P|k|E|P| |m|m|     |         | | |   | | | | | | |
- * | | | | | | |M| |P|P| | |p|p|     |         | | |   | | | | | | |
- * | | | | | | | | | | | | |r|r|     |         | | |   | | | | | | |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Debug		$23	/* EJTAG */
-#define R_C0_Debug		23
-
-#define S_DebugDBD		31			/* Debug branch delay (R) */
-#define M_DebugDBD		(0x1 << S_DebugDBD)
-#define S_DebugDM		30			/* Debug mode (R) */
-#define M_DebugDM		(0x1 << S_DebugDM)
-#define S_DebugNoDCR		29			/* No debug control register present (R) */
-#define M_DebugNoDCR		(0x1 << S_DebugNoDCR)
-#define S_DebugLSNM		28			/* Load/Store Normal Memory (R/W) */
-#define M_DebugLSNM		(0x1 << S_DebugLSNM)
-#define S_DebugDoze		27			/* Doze (R) */
-#define M_DebugDoze		(0x1 << S_DebugDoze)
-#define S_DebugHalt		26			/* Halt (R) */
-#define M_DebugHalt		(0x1 << S_DebugHalt)
-#define S_DebugCountDM		25			/* Count register behavior in debug mode (R/W) */
-#define M_DebugCountDM		(0x1 << S_DebugCountDM)
-#define S_DebugIBusEP		24			/* Imprecise Instn Bus Error Pending (R/W) */
-#define M_DebugIBusEP		(0x1 << S_DebugIBusEP)
-#define S_DebugMCheckP		23			/* Imprecise Machine Check Pending (R/W) */
-#define M_DebugMCheckP		(0x1 << S_DebugMCheckP)
-#define S_DebugCacheEP		22			/* Imprecise Cache Error Pending (R/W) */
-#define M_DebugCacheEP		(0x1 << S_DebugCacheEP)
-#define S_DebugDBusEP		21			/* Imprecise Data Bus Error Pending (R/W) */
-#define M_DebugDBusEP		(0x1 << S_DebugDBusEP)
-#define S_DebugIEXI		20			/* Imprecise Exception Inhibit (R/W) */
-#define M_DebugIEXI		(0x1 << S_DebugIEXI)
-#define S_DebugDDBSImpr		19			/* Debug data break store imprecise (R) */
-#define M_DebugDDBSImpr		(0x1 << S_DebugDDBSImpr)
-#define S_DebugDDBLImpr		18			/* Debug data break load imprecise (R) */
-#define M_DebugDDBLImpr		(0x1 << S_DebugDDBLImpr)
-#define S_DebugEJTAGver		15			/* EJTAG version number (R) */
-#define M_DebugEJTAGver		(0x7 << S_DebugEJTAGver)
-#define S_DebugDExcCode		10			/* Debug exception code (R) */
-#define M_DebugDExcCode		(0x1f << S_DebugDExcCode)
-#define S_DebugNoSSt		9			/* No single step implemented (R) */
-#define M_DebugNoSSt		(0x1 << S_DebugNoSSt)
-#define S_DebugSSt		8			/* Single step enable (R/W) */
-#define M_DebugSSt		(0x1 << S_DebugSSt)
-#define S_DebugDINT		5			/* Debug interrupt (R) */
-#define M_DebugDINT		(0x1 << S_DebugDINT)
-#define S_DebugDIB		4			/* Debug instruction break (R) */
-#define M_DebugDIB		(0x1 << S_DebugDIB)
-#define S_DebugDDBS		3			/* Debug data break store (R) */
-#define M_DebugDDBS		(0x1 << S_DebugDDBS)
-#define S_DebugDDBL		2			/* Debug data break load (R) */
-#define M_DebugDDBL		(0x1 << S_DebugDDBL)
-#define S_DebugDBp		1			/* Debug breakpoint (R) */
-#define M_DebugDBp		(0x1 << S_DebugDBp)
-#define S_DebugDSS		0			/* Debug single step (R) */
-#define M_DebugDSS		(0x1 << S_DebugDSS)
-
-#define M_Debug0Fields	0x01f000c0
-#define M_DebugRFields	0xec0ffe3f
-
-
-/*
- ************************************************************************
- *                 D E P C   R E G I S T E R   ( 2 4 )                  *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                  EJTAG Debug Exception PC                      | DEPC
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-
-#define C0_DEPC			$24
-#define R_C0_DEPC		24
-
-#define M_DEEPC0Fields		0x00000000
-#define M_DEEPCRFields		0x00000000
-#define M_DEEPC0Fields64	UNS64Const(0x0000000000000000)
-#define M_DEEPCRFields64	UNS64Const(0x0000000000000000)
-
-
-/*
- ************************************************************************
- *              P E R F C N T   R E G I S T E R   ( 2 5 )               *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * | |                                       |           |I| | | |E|
- * |M|                    0                  |   Event   |E|U|S|K|X| PerfCnt
- * | |                                       |           | | | | |L|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- *
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                          Event Count                          | PerfCnt
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_PerfCnt		$25
-#define R_C0_PerfCnt		25
-#define C0_PRFCNT0		C0_PerfCnt		/* OBSOLETE - DO NOT USE IN NEW CODE */
-#define C0_PRFCNT1		C0_PerfCnt		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_PerfCntM		31			/* More performance counters exist (R) */
-#define M_PerfCntM		(1 << S_PerfCntM)
-#define S_PerfCntEvent		5			/* Enabled event (R/W) */
-#define M_PerfCntEvent		(0x3f << S_PerfCntEvent)
-#define S_PerfCntIE		4			/* Interrupt Enable (R/W) */
-#define M_PerfCntIE		(1 << S_PerfCntIE)
-#define S_PerfCntU		3			/* Enable counting in User Mode (R/W) */
-#define M_PerfCntU		(1 << S_PerfCntU)
-#define S_PerfCntS		2			/* Enable counting in Supervisor Mode (R/W) */
-#define M_PerfCntS		(1 << S_PerfCntS)
-#define S_PerfCntK		1			/* Enable counting in Kernel Mode (R/W) */
-#define M_PerfCntK		(1 << S_PerfCntK)
-#define S_PerfCntEXL		0			/* Enable counting while EXL==1 (R/W) */
-#define M_PerfCntEXL		(1 << S_PerfCntEXL)
-
-#define M_PerfCnt0Fields	0x7ffff800
-#define M_PerfCntRFields	0x80000000
-
-
-/*
- ************************************************************************
- *               E R R C T L   R E G I S T E R   ( 2 6 )                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                        Error Control                          | ErrCtl
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_ErrCtl		$26
-#define R_C0_ErrCtl		26
-#define C0_ECC			$26		/* OBSOLETE - DO NOT USE IN NEW CODE */
-#define R_C0_ECC		26		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_ErrCtl0Fields		0x00000000
-#define M_ErrCtlRFields		0x00000000
-
-
-/*
- ************************************************************************
- *             C A C H E E R R   R E G I S T E R   ( 2 7 )              * CacheErr
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                     Cache Error Control                       | CacheErr
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_CacheErr		$27
-#define R_C0_CacheErr		27
-#define C0_CACHE_ERR		C0_CacheErr		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_CacheErr0Fields	0x00000000
-#define M_CachErrRFields	0x00000000
-
-
-/*
- ************************************************************************
- *                T A G L O   R E G I S T E R   ( 2 8 )                 * TagLo
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                            TagLo                              | TagLo
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_TagLo		$28
-#define R_C0_TagLo		28
-#define C0_TAGLO		C0_TagLo		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-/*
- * Some implementations use separate TagLo registers for the
- * instruction and data caches.  In those cases, the following
- * definitions can be used in relevant code
- */
-
-#define C0_ITagLo		$28,0
-#define C0_DTagLo		$28,2
-
-#define M_TagLo0Fields		0x00000000
-#define M_TagLoRFields		0x00000000
-
-
-/*
- ************************************************************************
- *        D A T A L O   R E G I S T E R   ( 2 8, SELECT 1 )             * DataLo
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                           DataLo                              | DataLo
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_DataLo		$28,1
-#define R_C0_DataLo		28
-
-/*
- * Some implementations use separate DataLo registers for the
- * instruction and data caches.  In those cases, the following
- * definitions can be used in relevant code
- */
-
-#define C0_IDataLo		$28,1
-#define C0_DDataLo		$28,3
-
-#define M_DataLo0Fields		0x00000000
-#define M_DataLoRFields		0xffffffff
-
-
-/*
- ************************************************************************
- *                T A G H I   R E G I S T E R   ( 2 9 )                 * TagHi
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                            TagHi                              | TagHi
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_TagHi		$29
-#define R_C0_TagHi		29
-#define C0_TAGHI		C0_TagHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-/*
- * Some implementations use separate TagHi registers for the
- * instruction and data caches.  In those cases, the following
- * definitions can be used in relevant code
- */
-
-#define C0_ITagHi		$29,0
-#define C0_DTagHi		$29,2
-
-#define M_TagHi0Fields		0x00000000
-#define M_TagHiRFields		0x00000000
-
-
-/*
- ************************************************************************
- *        D A T A H I   R E G I S T E R   ( 2 9, SELECT 1 )             * DataHi
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                           DataHi                              | DataHi
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_DataHi		$29,1
-#define R_C0_DataHi		29
-
-/*
- * Some implementations use separate DataHi registers for the
- * instruction and data caches.  In those cases, the following
- * definitions can be used in relevant code
- */
-
-#define C0_IDataHi		$29,1
-#define C0_DDataHi		$29,3
-
-#define M_DataHi0Fields		0x00000000
-#define M_DataHiRFields		0xffffffff
-
-
-/*
- ************************************************************************
- *            E R R O R E P C   R E G I S T E R   ( 3 0 )               *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                          Error PC                              | ErrorEPC
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_ErrorEPC		$30
-#define R_C0_ErrorEPC		30
-#define C0_ERROR_EPC		C0_ErrorEPC		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_ErrorEPC0Fields	0x00000000
-#define M_ErrorEPCRFields	0x00000000
-#define M_ErrorEPC0Fields64	UNS64Const(0x0000000000000000)
-#define M_ErrorEPCRFields64	UNS64Const(0x0000000000000000)
-
-
-/*
- ************************************************************************
- *            D E S A V E   R E G I S T E R   ( 3 1 )                   *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                   EJTAG Register Save Value                    | DESAVE
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_DESAVE		$31
-#define R_C0_DESAVE		31
-
-#define M_DESAVE0Fields		0x00000000
-#define M_DESAVERFields		0x00000000
-#define M_DESAVE0Fields64	UNS64Const(0x0000000000000000)
-#define M_DESAVERFields64	UNS64Const(0x0000000000000000)
-
-
-/*
- *************************************************************************
- *             C P 1   R E G I S T E R   D E F I N I T I O N S           *
- *************************************************************************
- */
-
-
-/*
- *************************************************************************
- *                  H A R D W A R E   F P R   N A M E S                  *
- *************************************************************************
- */
-
-#define fp0			$f0
-#define fp1			$f1
-#define fp2			$f2
-#define fp3			$f3
-#define fp4			$f4
-#define fp5			$f5
-#define fp6			$f6
-#define fp7			$f7
-#define fp8			$f8
-#define fp9			$f9
-#define fp10			$f10
-#define fp11			$f11
-#define fp12			$f12
-#define fp13			$f13
-#define fp14			$f14
-#define fp15			$f15
-#define fp16			$f16
-#define fp17			$f17
-#define fp18			$f18
-#define fp19			$f19
-#define fp20			$f20
-#define fp21			$f21
-#define fp22			$f22
-#define fp23			$f23
-#define fp24			$f24
-#define fp25			$f25
-#define fp26			$f26
-#define fp27			$f27
-#define fp28			$f28
-#define fp29			$f29
-#define fp30			$f30
-#define fp31			$f31
-
-/*
- * The following definitions are used to convert an FPR name
- * into the corresponding even or odd name, respectively.
- * This is used in macro substitution in the AVPs.
- */
-
-#define fp1_even		$f0
-#define fp3_even		$f2
-#define fp5_even		$f4
-#define fp7_even		$f6
-#define fp9_even		$f8
-#define fp11_even		$f10
-#define fp13_even		$f12
-#define fp15_even		$f14
-#define fp17_even		$f16
-#define fp19_even		$f18
-#define fp21_even		$f20
-#define fp23_even		$f22
-#define fp25_even		$f24
-#define fp27_even		$f26
-#define fp29_even		$f28
-#define fp31_even		$f30
-
-#define fp0_odd			$f1
-#define fp2_odd			$f3
-#define fp4_odd			$f5
-#define fp6_odd			$f7
-#define fp8_odd			$f9
-#define fp10_odd		$f11
-#define fp12_odd		$f13
-#define fp14_odd		$f15
-#define fp16_odd		$f17
-#define fp18_odd		$f19
-#define fp20_odd		$f21
-#define fp22_odd		$f23
-#define fp24_odd		$f25
-#define fp26_odd		$f27
-#define fp28_odd		$f29
-#define fp30_odd		$f31
-
-
-/*
- *************************************************************************
- *                H A R D W A R E   F P R   I N D I C E S                *
- *************************************************************************
- *
- * These definitions provide the index (number) of the FPR, as opposed
- * to the assembler register name ($n).
- */
-
-#define R_fp0			 0
-#define R_fp1			 1
-#define R_fp2			 2
-#define R_fp3			 3
-#define R_fp4			 4
-#define R_fp5			 5
-#define R_fp6			 6
-#define R_fp7			 7
-#define R_fp8			 8
-#define R_fp9			 9
-#define R_fp10			10
-#define R_fp11			11
-#define R_fp12			12
-#define R_fp13			13
-#define R_fp14			14
-#define R_fp15			15
-#define R_fp16			16
-#define R_fp17			17
-#define R_fp18			18
-#define R_fp19			19
-#define R_fp20			20
-#define R_fp21			21
-#define R_fp22			22
-#define R_fp23			23
-#define R_fp24			24
-#define R_fp25			25
-#define R_fp26			26
-#define R_fp27			27
-#define R_fp28			28
-#define R_fp29			29
-#define R_fp30			30
-#define R_fp31			31
-
-
-/*
- *************************************************************************
- *                  H A R D W A R E   F C R   N A M E S                  *
- *************************************************************************
- */
-
-#define fc0			$0
-#define fc25			$25
-#define fc26			$26
-#define fc28			$28
-#define fc31			$31
-
-
-/*
- *************************************************************************
- *                H A R D W A R E   F C R   I N D I C E S                *
- *************************************************************************
- *
- * These definitions provide the index (number) of the FCR, as opposed
- * to the assembler register name ($n).
- */
-
-#define R_fc0			 0
-#define R_fc25			25
-#define R_fc26			26
-#define R_fc28			28
-#define R_fc31			31
-
-
-/*
- *************************************************************************
- *                  H A R D W A R E   F C C   N A M E S                  *
- *************************************************************************
- */
-
-#define cc0			$fcc0
-#define cc1			$fcc1
-#define cc2			$fcc2
-#define cc3			$fcc3
-#define cc4			$fcc4
-#define cc5			$fcc5
-#define cc6			$fcc6
-#define cc7			$fcc7
-
-
-/*
- *************************************************************************
- *                H A R D W A R E   F C C   I N D I C E S                *
- *************************************************************************
- *
- * These definitions provide the index (number) of the CC, as opposed
- * to the assembler register name ($n).
- */
-
-#define R_cc0			0
-#define R_cc1			1
-#define R_cc2			2
-#define R_cc3			3
-#define R_cc4			4
-#define R_cc5			5
-#define R_cc6			6
-#define R_cc7			7
-
-
-/*
- ************************************************************************
- *             I M P L E M E N T A T I O N   R E G I S T E R            *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |Reserved for Additional|3|P|D|S| Implementation|   Revision    | FIR
- * |  Configuration Bits   |D|S| | |               |               |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FIR			$0
-#define R_C1_FIR			0
-
-#define S_FIRConfigS		16
-#define M_FIRConfigS		(0x1 << S_FIRConfigS)
-#define S_FIRConfigD		17
-#define M_FIRConfigD		(0x1 << S_FIRConfigD)
-#define S_FIRConfigPS		18
-#define M_FIRConfigPS   	(0x1 << S_FIRConfigPS)
-#define S_FIRConfig3D		19
-#define M_FIRConfig3D		(0x1 << S_FIRConfig3D)
-#define M_FIRConfigAll		(M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D)
-
-#define S_FIRImp		8
-#define M_FIRImp		(0xff << S_FIRImp)
-
-#define S_FIRRev		0
-#define M_FIRRev		(0xff << S_FIRRev)
-
-#define M_FIR0Fields		0xfff00000
-#define M_FIRRFields		0x000fffff
-
-/*
- ************************************************************************
- *          C O N D I T I O N   C O D E S   R E G I S T E R             *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                      0                        |      CC       | FCCR
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FCCR			$25
-#define R_C1_FCCR		25
-
-#define S_FCCRCC		0
-#define M_FCCRCC		(0xff << S_FCCRCC)
-#define S_FCCRCC7		7
-#define M_FCCRCC7		(0x1 << S_FCCRCC7)
-#define S_FCCRCC6		6
-#define M_FCCRCC6		(0x1 << S_FCCRCC6)
-#define S_FCCRCC5		5
-#define M_FCCRCC5		(0x1 << S_FCCRCC5)
-#define S_FCCRCC4		4
-#define M_FCCRCC4		(0x1 << S_FCCRCC4)
-#define S_FCCRCC3		3
-#define M_FCCRCC3		(0x1 << S_FCCRCC3)
-#define S_FCCRCC2		2
-#define M_FCCRCC2		(0x1 << S_FCCRCC2)
-#define S_FCCRCC1		1
-#define M_FCCRCC1		(0x1 << S_FCCRCC1)
-#define S_FCCRCC0		0
-#define M_FCCRCC0		(0x1 << S_FCCRCC0)
-
-#define M_FCCR0Fields		0xffffff00
-#define M_FCCRRFields		0x000000ff
-
-
-/*
- ************************************************************************
- *                 E X C E P T I O N S   R E G I S T E R                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |             0             |   Cause   |    0    |  Flags  | 0 | FEXR
- * |                           |E|V|Z|O|U|I|         |V|Z|O|U|I|   |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FEXR			$26
-#define R_C1_FEXR		26
-
-#define S_FEXRExc		12
-#define M_FEXRExc		(0x3f << S_FEXRExc)
-#define S_FEXRExcE		17
-#define M_FEXRExcE		(0x1 << S_FEXRExcE)
-#define S_FEXRExcV		16
-#define M_FEXRExcV		(0x1 << S_FEXRExcV)
-#define S_FEXRExcZ		15
-#define M_FEXRExcZ		(0x1 << S_FEXRExcZ)
-#define S_FEXRExcO		14
-#define M_FEXRExcO		(0x1 << S_FEXRExcO)
-#define S_FEXRExcU		13
-#define M_FEXRExcU		(0x1 << S_FEXRExcU)
-#define S_FEXRExcI		12
-#define M_FEXRExcI		(0x1 << S_FEXRExcI)
-
-#define S_FEXRFlg		2
-#define M_FEXRFlg		(0x1f << S_FEXRFlg)
-#define S_FEXRFlgV		6
-#define M_FEXRFlgV		(0x1 << S_FEXRFlgV)
-#define S_FEXRFlgZ		5
-#define M_FEXRFlgZ		(0x1 << S_FEXRFlgZ)
-#define S_FEXRFlgO		4
-#define M_FEXRFlgO		(0x1 << S_FEXRFlgO)
-#define S_FEXRFlgU		3
-#define M_FEXRFlgU		(0x1 << S_FEXRFlgU)
-#define S_FEXRFlgI		2
-#define M_FEXRFlgI		(0x1 << S_FEXRFlgI)
-
-#define M_FEXR0Fields		0xfffc0f83
-#define M_FEXRRFields		0x00000000
-
-
-/*
- ************************************************************************
- *                    E N A B L E S   R E G I S T E R                   *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                   0                   | Enables |   0   |F|RM | FENR
- * |                                       |V|Z|O|U|I|       |S|   |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FENR			$28
-#define R_C1_FENR		28
-
-#define S_FENREna		7
-#define M_FENREna		(0x1f << S_FENREna)
-#define S_FENREnaV		11
-#define M_FENREnaV		(0x1 << S_FENREnaV)
-#define S_FENREnaZ		10
-#define M_FENREnaZ		(0x1 << S_FENREnaZ)
-#define S_FENREnaO		9
-#define M_FENREnaO		(0x1 << S_FENREnaO)
-#define S_FENREnaU		8
-#define M_FENREnaU		(0x1 << S_FENREnaU)
-#define S_FENREnaI		7
-#define M_FENREnaI		(0x1 << S_FENREnaI)
-
-#define S_FENRFS		2
-#define M_FENRFS		(0x1 << S_FENRFS)
-
-#define S_FENRRM		0
-#define M_FENRRM		(0x3 << S_FENRRM)
-
-#define M_FENR0Fields		0xfffff078
-#define M_FENRRFields		0x00000000
-
-
-/*
- ************************************************************************
- *           C O N T R O L  /  S T A T U S   R E G I S T E R            *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |     FCC     |F|C|Imp|  0  |   Cause   | Enables |  Flags  | RM| FCSR
- * |7|6|5|4|3|2|1|S|C|   |     |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I|   |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FCSR			$31
-#define R_C1_FCSR		31
-
-#define S_FCSRFCC7_1		25			/* Floating point condition codes 7..1 (R/W) */
-#define M_FCSRFCC7_1		(0x7f << S_FCSRFCC7_1)
-#define S_FCSRCC7		31
-#define M_FCSRCC7		(0x1 << S_FCSRCC7)
-#define S_FCSRCC6		30
-#define M_FCSRCC6		(0x1 << S_FCSRCC6)
-#define S_FCSRCC5		29
-#define M_FCSRCC5		(0x1 << S_FCSRCC5)
-#define S_FCSRCC4		28
-#define M_FCSRCC4		(0x1 << S_FCSRCC4)
-#define S_FCSRCC3		27
-#define M_FCSRCC3		(0x1 << S_FCSRCC3)
-#define S_FCSRCC2		26
-#define M_FCSRCC2		(0x1 << S_FCSRCC2)
-#define S_FCSRCC1		25
-#define M_FCSRCC1		(0x1 << S_FCSRCC1)
-
-#define S_FCSRFS		24			/* Flush denorms to zero (R/W) */
-#define M_FCSRFS		(0x1 << S_FCSRFS)
-
-#define S_FCSRCC0		23			/* Floating point condition code 0 (R/W) */
-#define M_FCSRCC0		(0x1 << S_FCSRCC0)
-#define S_FCSRCC		S_FCSRCC0
-#define M_FCSRCC		M_FCSRCC0
-
-#define S_FCSRImpl		21			/* Implementation-specific control bits (R/W) */
-#define M_FCSRImpl		(0x3 << S_FCSRImpl)
-
-#define S_FCSRExc		12			/* Exception cause (R/W) */
-#define M_FCSRExc		(0x3f << S_FCSRExc)
-#define S_FCSRExcE		17
-#define M_FCSRExcE		(0x1 << S_FCSRExcE)
-#define S_FCSRExcV		16
-#define M_FCSRExcV		(0x1 << S_FCSRExcV)
-#define S_FCSRExcZ		15
-#define M_FCSRExcZ		(0x1 << S_FCSRExcZ)
-#define S_FCSRExcO		14
-#define M_FCSRExcO		(0x1 << S_FCSRExcO)
-#define S_FCSRExcU		13
-#define M_FCSRExcU		(0x1 << S_FCSRExcU)
-#define S_FCSRExcI		12
-#define M_FCSRExcI		(0x1 << S_FCSRExcI)
-
-#define S_FCSREna		7			/* Exception enable (R/W) */
-#define M_FCSREna		(0x1f << S_FCSREna)
-#define S_FCSREnaV		11
-#define M_FCSREnaV		(0x1 << S_FCSREnaV)
-#define S_FCSREnaZ		10
-#define M_FCSREnaZ		(0x1 << S_FCSREnaZ)
-#define S_FCSREnaO		9
-#define M_FCSREnaO		(0x1 << S_FCSREnaO)
-#define S_FCSREnaU		8
-#define M_FCSREnaU		(0x1 << S_FCSREnaU)
-#define S_FCSREnaI		7
-#define M_FCSREnaI		(0x1 << S_FCSREnaI)
-
-#define S_FCSRFlg		2			/* Exception flags (R/W) */
-#define M_FCSRFlg		(0x1f << S_FCSRFlg)
-#define S_FCSRFlgV		6
-#define M_FCSRFlgV		(0x1 << S_FCSRFlgV)
-#define S_FCSRFlgZ		5
-#define M_FCSRFlgZ		(0x1 << S_FCSRFlgZ)
-#define S_FCSRFlgO		4
-#define M_FCSRFlgO		(0x1 << S_FCSRFlgO)
-#define S_FCSRFlgU		3
-#define M_FCSRFlgU		(0x1 << S_FCSRFlgU)
-#define S_FCSRFlgI		2
-#define M_FCSRFlgI		(0x1 << S_FCSRFlgI)
-
-#define S_FCSRRM		0			/* Rounding mode (R/W) */
-#define M_FCSRRM		(0x3 << S_FCSRRM)
-
-#define M_FCSR0Fields		0x001c0000
-#define M_FCSRRFields		0x00000000
-
-/*
- * Values in the rounding mode field (of both FCSR and FCCR)
- */
-#define K_FCSRRM_RN		0
-#define K_FCSRRM_RZ		1
-#define K_FCSRRM_RP		2
-#define K_FCSRRM_RM		3
-
-#endif /* _COMMON_MIPS_DEF_H_ */
diff --git a/libcpu/mips/common/mips_excpt.h b/libcpu/mips/common/mips_excpt.h
deleted file mode 100644
index 868b046d3c..0000000000
--- a/libcpu/mips/common/mips_excpt.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * File      : mips_excpt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
- */
-
-#ifndef _MIPS_EXCPT_H_
-#define _MIPS_EXCPT_H_
-
-#include "mips_regs.h"
-
-#ifndef __ASSEMBLY__
-typedef void (* exception_func_t)(mips_reg_ctx *regs);
-
-//extern exception_func_t mips_exception_handlers[];
-
-int rt_hw_exception_init(void);
-exception_func_t rt_set_except_vector(int n, exception_func_t func);
-void install_default_execpt_handle(void);
-#endif /* __ASSEMBLY__ */
-#endif /* _MIPS_EXCPT_H_ */
diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h
new file mode 100644
index 0000000000..d6351f7655
--- /dev/null
+++ b/libcpu/mips/common/mips_fpu.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef _MIPS_FPU_H_
+#define _MIPS_FPU_H_
+
+#ifndef __ASSEMBLY__
+
+#include <mips_regs.h>
+/**
+ * init hardware FPU
+ */
+#ifdef RT_USING_FPU
+inline void rt_hw_fpu_init(void)
+{
+    rt_uint32_t c0_status = 0;
+    rt_uint32_t c1_status = 0;
+
+    /* Enable CU1 */
+    c0_status = read_c0_status();
+    c0_status |= (ST0_CU1 | ST0_FR);
+    write_c0_status(c0_status);
+
+    /* FCSR Configs */
+    c1_status = read_c1_status();
+    c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN);    /* Set FS, FO, FN */
+    c1_status &= ~(FPU_CSR_ALL_E);                          /* Disable exception */
+    c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN;   /* Set RN */
+    write_c1_status(c1_status);
+
+    return ;
+}
+#else
+    inline void rt_hw_fpu_init(void){} /* Do nothing */
+#endif
+
+#endif
+
+#endif
diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h
index 7ea07d3869..7e1359fa33 100644
--- a/libcpu/mips/common/mips_regs.h
+++ b/libcpu/mips/common/mips_regs.h
@@ -1,202 +1,96 @@
 /*
- * File      : mips_regs.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
 
 #ifndef _MIPS_REGS_H_
 #define _MIPS_REGS_H_
 
+#define REG_A0	4
+#define REG_SP	29
+#define REG_GP	28
+#define REG_FP	30
+#define REG_RA	31
+
+#define zero	$0	/* wired zero */
+#define AT	$1	/* assembler temp  - uppercase because of ".set at" */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define ta0	$12
+#define t5	$13
+#define ta1	$13
+#define t6	$14
+#define ta2	$14
+#define t7	$15
+#define ta3	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* caller saved */
+#define t9	$25
+#define jp	$25	/* PIC jump register */
+#define k0	$26	/* kernel scratch */
+#define k1	$27
+#define gp	$28	/* global pointer */
+#define sp	$29	/* stack pointer */
+#define fp	$30	/* frame pointer */
+#define s8	$30	/* same like fp! */
+#define ra	$31	/* return address */
+
+#define fv0	$f0	 /* return value */
+#define fv0f	$f1
+#define fv1	$f2
+#define fv1f	$f3
+#define fa0	$f12	 /* argument registers */
+#define fa0f	$f13
+#define fa1	$f14
+#define fa1f	$f15
+#define ft0	$f4	 /* caller saved */
+#define ft0f	$f5
+#define ft1	$f6
+#define ft1f	$f7
+#define ft2	$f8
+#define ft2f	$f9
+#define ft3	$f10
+#define ft3f	$f11
+#define ft4	$f16
+#define ft4f	$f17
+#define ft5	$f18
+#define ft5f	$f19
+#define fs0	$f20	 /* callee saved */
+#define fs0f	$f21
+#define fs1	$f22
+#define fs1f	$f23
+#define fs2	$f24
+#define fs2f	$f25
+#define fs3	$f26
+#define fs3f	$f27
+#define fs4	$f28
+#define fs4f	$f29
+#define fs5	$f30
+#define fs5f	$f31
+
+#define fcr31	$31	 /* FPU status register */
 
-#if !defined(__ASSEMBLY__) && !defined(ASSEMBLY)
-#include <rtdef.h>
-
-#define MIPS_REG_NR             32
-typedef struct {
-    rt_uint32_t  regs[MIPS_REG_NR];                             	/*  32 ��ͨ��Ŀ�ļĴ���         */
-    rt_uint32_t  CP0Status;                                        	/*  CP0 Э������״̬�Ĵ���      */
-    rt_uint32_t  CP0DataHI;                                        	/*  ������λ�Ĵ���              */
-    rt_uint32_t  CP0DataLO;                                        	/*  ������λ�Ĵ���              */
-    rt_uint32_t  CP0BadVAddr;                                      	/*  ������ַ�Ĵ���              */
-    rt_uint32_t  CP0Cause;                                         	/*  �����жϻ����쳣�鿴�ļĴ���*/
-    rt_uint32_t  CP0EPC;                                           	/*  ����������Ĵ���			*/
-} mips_reg_ctx;
-
-#define MIPS_ARG_REG_NR         4
-typedef struct
-{
-	rt_uint32_t  args[MIPS_ARG_REG_NR];                              /*  4 �������Ĵ���              */
-} mips_arg_ctx;
-
-struct linkctx
-{
-	rt_uint32_t id;
-	struct linkctx *next;
-};
-
-struct fpctx
-{
-  struct linkctx link;
-  rt_uint32_t fcsr;
-  rt_uint32_t reserved;
-};
-
-
-struct fp32ctx
-{
-  struct fpctx fp;
-  union
-    {
-      double d[16];	/* even doubles */
-      float s[32];	/* even singles, padded */
-    };
-};
-
-struct fp64ctx
-{
-  struct fpctx fp;
-  union
-    {
-      double d[32];	/* even doubles, followed by odd doubles */
-      float s[64];	/* even singles, followed by odd singles, padded */
-    };
-};
-
-#endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */
-
-#define MIPS_STK_CTX_WORD_SIZE			38
-#define SZREG			4
-/*********************************************************************************************************
-  MIPS �ļĴ�������
-*********************************************************************************************************/
-#define REG_ZERO                0                                       /*  wired zero                  */
-#define REG_AT                  1                                       /*  assembler temp              */
-#define REG_V0                  2                                       /*  return reg 0                */
-#define REG_V1                  3                                       /*  return reg 1                */
-#define REG_A0                  4                                       /*  arg reg 0                   */
-#define REG_A1                  5                                       /*  arg reg 1                   */
-#define REG_A2                  6                                       /*  arg reg 2                   */
-#define REG_A3                  7                                       /*  arg reg 3                   */
-#define REG_T0                  8                                       /*  caller saved 0              */
-#define REG_T1                  9                                       /*  caller saved 1              */
-#define REG_T2                  10                                      /*  caller saved 2              */
-#define REG_T3                  11                                      /*  caller saved 3              */
-#define REG_T4                  12                                      /*  caller saved 4              */
-#define REG_T5                  13                                      /*  caller saved 5              */
-#define REG_T6                  14                                      /*  caller saved 6              */
-#define REG_T7                  15                                      /*  caller saved 7              */
-#define REG_S0                  16                                      /*  callee saved 0              */
-#define REG_S1                  17                                      /*  callee saved 1              */
-#define REG_S2                  18                                      /*  callee saved 2              */
-#define REG_S3                  19                                      /*  callee saved 3              */
-#define REG_S4                  20                                      /*  callee saved 4              */
-#define REG_S5                  21                                      /*  callee saved 5              */
-#define REG_S6                  22                                      /*  callee saved 6              */
-#define REG_S7                  23                                      /*  callee saved 7              */
-#define REG_T8                  24                                      /*  caller saved 8              */
-#define REG_T9                  25                                      /*  caller saved 9              */
-#define REG_K0                  26                                      /*  kernel temp 0               */
-#define REG_K1                  27                                      /*  kernel temp 1               */
-#define REG_GP                  28                                      /*  global pointer              */
-#define REG_SP                  29                                      /*  stack pointer               */
-#define REG_S8                  30                                      /*  callee saved 8              */
-#define REG_FP                  REG_S8                                  /*  callee saved 8              */
-#define REG_RA                  31                                      /*  return address              */
-
-#define STK_CTX_SIZE            (MIPS_STK_CTX_WORD_SIZE * SZREG)
-#define STK_OFFSET_SR           ((32 + 0) * SZREG)
-#define STK_OFFSET_HI           ((32 + 1) * SZREG)
-#define STK_OFFSET_LO           ((32 + 2) * SZREG)
-#define STK_OFFSET_BADVADDR     ((32 + 3) * SZREG)
-#define STK_OFFSET_CAUSE        ((32 + 4) * SZREG)
-#define STK_OFFSET_EPC          ((32 + 5) * SZREG)
-
-#define STK_OFFSET_LAST         ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG)
-
-#define FP32CTX_CSR	((SZREG)*2)
-#define FP64CTX_CSR	((SZREG)*2)
-
-#define LINKCTX_ID      ((SZREG)*0)
-#define LINKCTX_NEXT    ((SZREG)*1)
-#define LINKCTX_TYPE_MSA        0x004D5341
-#define LINKCTX_TYPE_FP32       0x46503332
-#define LINKCTX_TYPE_FP64       0x46503634
-#define LINKCTX_TYPE_FMSA       0x463D5341
-#define LINKCTX_TYPE_DSP        0x00445350
-#define LINKCTX_TYPE_STKSWP     0x53574150
-#define LINKCTX_TYPE_XPA	0x00585041
-
-#define FP32CTX_0	((SZREG)*4)
-#define FP32CTX_2	(FP32CTX_0 + (1 * 8))
-#define FP32CTX_4	(FP32CTX_0 + (2 * 8))
-#define FP32CTX_6	(FP32CTX_0 + (3 * 8))
-#define FP32CTX_8	(FP32CTX_0 + (4 * 8))
-#define FP32CTX_10	(FP32CTX_0 + (5 * 8))
-#define FP32CTX_12	(FP32CTX_0 + (6 * 8))
-#define FP32CTX_14	(FP32CTX_0 + (7 * 8))
-#define FP32CTX_16	(FP32CTX_0 + (8 * 8))
-#define FP32CTX_18	(FP32CTX_0 + (9 * 8))
-#define FP32CTX_20	(FP32CTX_0 + (10 * 8))
-#define FP32CTX_22	(FP32CTX_0 + (11 * 8))
-#define FP32CTX_24	(FP32CTX_0 + (12 * 8))
-#define FP32CTX_26	(FP32CTX_0 + (13 * 8))
-#define FP32CTX_28	(FP32CTX_0 + (14 * 8))
-#define FP32CTX_30	(FP32CTX_0 + (15 * 8))
-#define FP32CTX_SIZE	(FP32CTX_30 + (17 * 8))
-
-#define FP64CTX_0	((SZREG)*4)
-#define FP64CTX_2	(FP64CTX_0 + (1 * 8))
-#define FP64CTX_4	(FP64CTX_0 + (2 * 8))
-#define FP64CTX_6	(FP64CTX_0 + (3 * 8))
-#define FP64CTX_8	(FP64CTX_0 + (4 * 8))
-#define FP64CTX_10	(FP64CTX_0 + (5 * 8))
-#define FP64CTX_12	(FP64CTX_0 + (6 * 8))
-#define FP64CTX_14	(FP64CTX_0 + (7 * 8))
-#define FP64CTX_16	(FP64CTX_0 + (8 * 8))
-#define FP64CTX_18	(FP64CTX_0 + (9 * 8))
-#define FP64CTX_20	(FP64CTX_0 + (10 * 8))
-#define FP64CTX_22	(FP64CTX_0 + (11 * 8))
-#define FP64CTX_24	(FP64CTX_0 + (12 * 8))
-#define FP64CTX_26	(FP64CTX_0 + (13 * 8))
-#define FP64CTX_28	(FP64CTX_0 + (14 * 8))
-#define FP64CTX_30	(FP64CTX_0 + (15 * 8))
-#define FP64CTX_1	(FP64CTX_30 + (1 * 8))
-#define FP64CTX_3	(FP64CTX_30 + (2 * 8))
-#define FP64CTX_5	(FP64CTX_30 + (3 * 8))
-#define FP64CTX_7	(FP64CTX_30 + (4 * 8))
-#define FP64CTX_9	(FP64CTX_30 + (5 * 8))
-#define FP64CTX_11	(FP64CTX_30 + (6 * 8))
-#define FP64CTX_13	(FP64CTX_30 + (7 * 8))
-#define FP64CTX_15	(FP64CTX_30 + (8 * 8))
-#define FP64CTX_17	(FP64CTX_30 + (9 * 8))
-#define FP64CTX_19	(FP64CTX_30 + (10 * 8))
-#define FP64CTX_21	(FP64CTX_30 + (11 * 8))
-#define FP64CTX_23	(FP64CTX_30 + (12 * 8))
-#define FP64CTX_25	(FP64CTX_30 + (13 * 8))
-#define FP64CTX_27	(FP64CTX_30 + (14 * 8))
-#define FP64CTX_29	(FP64CTX_30 + (15 * 8))
-#define FP64CTX_31	(FP64CTX_30 + (16 * 8))
-#define FP64CTX_SIZE	(FP64CTX_31 + (17 * 8))
-
-#define FPCTX_SIZE()	(mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE)
 
 /*
  * The following macros are especially useful for __asm__
@@ -284,75 +178,128 @@ struct fp64ctx
 /*
  * Coprocessor 1 (FPU) register names
  */
-#define CP1_REVISION   $0
-#define CP1_STATUS     $31
+#define CP1_REVISION	$0
+#define CP1_UFR		$1
+#define CP1_UNFR	$4
+#define CP1_FCCR	$25
+#define CP1_FEXR	$26
+#define CP1_FENR	$28
+#define CP1_STATUS	$31
+
 
 /*
- * FPU Status Register Values
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  */
+#define MIPS_FPIR_S		(_ULCAST_(1) << 16)
+#define MIPS_FPIR_D		(_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
+#define MIPS_FPIR_W		(_ULCAST_(1) << 20)
+#define MIPS_FPIR_L		(_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)
+
 /*
- * Status Register Values
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
  */
-
-#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
-#define FPU_CSR_COND    0x00800000      /* $fcc0 */
-#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
-#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
-#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
-#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
-#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
-#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
-#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
-#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+#define MIPS_FCCR_CONDX_S	0
+#define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S	0
+#define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S	1
+#define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S	2
+#define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S	3
+#define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S	4
+#define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S	5
+#define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S	6
+#define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S	7
+#define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)
 
 /*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
-*/
-#define FPU_CSR_ALL_X   0x0003f000
-#define FPU_CSR_UNI_X   0x00020000
-#define FPU_CSR_INV_X   0x00010000
-#define FPU_CSR_DIV_X   0x00008000
-#define FPU_CSR_OVF_X   0x00004000
-#define FPU_CSR_UDF_X   0x00002000
-#define FPU_CSR_INE_X   0x00001000
-
-#define FPU_CSR_ALL_E   0x00000f80
-#define FPU_CSR_INV_E   0x00000800
-#define FPU_CSR_DIV_E   0x00000400
-#define FPU_CSR_OVF_E   0x00000200
-#define FPU_CSR_UDF_E   0x00000100
-#define FPU_CSR_INE_E   0x00000080
-
-#define FPU_CSR_ALL_S   0x0000007c
-#define FPU_CSR_INV_S   0x00000040
-#define FPU_CSR_DIV_S   0x00000020
-#define FPU_CSR_OVF_S   0x00000010
-#define FPU_CSR_UDF_S   0x00000008
-#define FPU_CSR_INE_S   0x00000004
-
-/* rounding mode */
-#define FPU_CSR_RN      0x0     /* nearest */
-#define FPU_CSR_RZ      0x1     /* towards zero */
-#define FPU_CSR_RU      0x2     /* towards +Infinity */
-#define FPU_CSR_RD      0x3     /* towards -Infinity */
-
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
+ */
+#define MIPS_FENR_FS_S		2
+#define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)
 
 /*
- * Values for PageMask register
+ * FPU Status Register Values
  */
-#ifdef CONFIG_CPU_VR41XX
+#define FPU_CSR_COND_S	23					/* $fcc0 */
+#define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)
+
+#define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
+#define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)
+
+#define FPU_CSR_FO      0x00400000
+#define FPU_CSR_FN      0x00200000
+
+#define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
+#define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S	25					/* $fcc1 */
+#define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S	26					/* $fcc2 */
+#define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S	27					/* $fcc3 */
+#define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S	28					/* $fcc4 */
+#define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S	29					/* $fcc5 */
+#define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S	30					/* $fcc6 */
+#define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S	31					/* $fcc7 */
+#define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
 
-/* Why doesn't stupidity hurt ... */
+/*
+ * Bits 22:20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
 
-#define PM_1K		0x00000000
-#define PM_4K		0x00001800
-#define PM_16K		0x00007800
-#define PM_64K		0x0001f800
-#define PM_256K		0x0007f800
+#define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
 
-#else
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X	0x0003f000
+#define FPU_CSR_UNI_X	0x00020000
+#define FPU_CSR_INV_X	0x00010000
+#define FPU_CSR_DIV_X	0x00008000
+#define FPU_CSR_OVF_X	0x00004000
+#define FPU_CSR_UDF_X	0x00002000
+#define FPU_CSR_INE_X	0x00001000
+
+#define FPU_CSR_ALL_E	0x00000f80
+#define FPU_CSR_INV_E	0x00000800
+#define FPU_CSR_DIV_E	0x00000400
+#define FPU_CSR_OVF_E	0x00000200
+#define FPU_CSR_UDF_E	0x00000100
+#define FPU_CSR_INE_E	0x00000080
+
+#define FPU_CSR_ALL_S	0x0000007c
+#define FPU_CSR_INV_S	0x00000040
+#define FPU_CSR_DIV_S	0x00000020
+#define FPU_CSR_OVF_S	0x00000010
+#define FPU_CSR_UDF_S	0x00000008
+#define FPU_CSR_INE_S	0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM	0x00000003
+#define FPU_CSR_RN	0x0	/* nearest */
+#define FPU_CSR_RZ	0x1	/* towards zero */
+#define FPU_CSR_RU	0x2	/* towards +Infinity */
+#define FPU_CSR_RD	0x3	/* towards -Infinity */
 
 #define PM_4K		0x00000000
 #define PM_16K		0x00006000
@@ -364,7 +311,6 @@ struct fp64ctx
 #define PM_64M		0x07ffe000
 #define PM_256M		0x1fffe000
 
-#endif
 
 /*
  * Values used for computation of new tlb entries
@@ -440,38 +386,6 @@ struct fp64ctx
 #define ST0_IL			(_ULCAST_(1) << 23)
 #define ST0_DL			(_ULCAST_(1) << 24)
 
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT	19
-#define TX39_CONF_ICS_MASK	0x00380000
-#define TX39_CONF_ICS_1KB 	0x00000000
-#define TX39_CONF_ICS_2KB 	0x00080000
-#define TX39_CONF_ICS_4KB 	0x00100000
-#define TX39_CONF_ICS_8KB 	0x00180000
-#define TX39_CONF_ICS_16KB 	0x00200000
-
-#define TX39_CONF_DCS_SHIFT	16
-#define TX39_CONF_DCS_MASK	0x00070000
-#define TX39_CONF_DCS_1KB 	0x00000000
-#define TX39_CONF_DCS_2KB 	0x00010000
-#define TX39_CONF_DCS_4KB 	0x00020000
-#define TX39_CONF_DCS_8KB 	0x00030000
-#define TX39_CONF_DCS_16KB 	0x00040000
-
-#define TX39_CONF_CWFON 	0x00004000
-#define TX39_CONF_WBON  	0x00002000
-#define TX39_CONF_RF_SHIFT	10
-#define TX39_CONF_RF_MASK	0x00000c00
-#define TX39_CONF_DOZE		0x00000200
-#define TX39_CONF_HALT		0x00000100
-#define TX39_CONF_LOCK		0x00000080
-#define TX39_CONF_ICE		0x00000020
-#define TX39_CONF_DCE		0x00000010
-#define TX39_CONF_IRSIZE_SHIFT	2
-#define TX39_CONF_IRSIZE_MASK	0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT	0
-#define TX39_CONF_DRSIZE_MASK	0x00000003
 
 /*
  * Status register bits available in all MIPS CPUs.
@@ -729,77 +643,77 @@ struct fp64ctx
 
 #define __read_32bit_c0_register(source, sel)				\
 ({ int __res;								\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mfc0\t%0, " #source "\n\t"			\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	__res;								\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            "mfc0\t%0, " #source "\n\t"			\
+            : "=r" (__res));				\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips32\n\t"				\
+            "mfc0\t%0, " #source ", " #sel "\n\t"		\
+            ".set\tmips0\n\t"				\
+            : "=r" (__res));				\
+    __res;								\
 })
 
 #define __read_64bit_c0_register(source, sel)				\
 ({ unsigned long __res;							\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips3\n\t"				\
-			"dmfc0\t%0, " #source "\n\t"			\
-			".set\tmips0"					\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0"					\
-			: "=r" (__res));				\
-	__res;								\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            ".set\tmips3\n\t"				\
+            "dmfc0\t%0, " #source "\n\t"			\
+            ".set\tmips0"					\
+            : "=r" (__res));				\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dmfc0\t%0, " #source ", " #sel "\n\t"		\
+            ".set\tmips0"					\
+            : "=r" (__res));				\
+    __res;								\
 })
 
 #define __write_32bit_c0_register(register, sel, value)			\
 do {									\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mtc0\t%z0, " #register "\n\t"			\
-			: : "Jr" (value));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0"					\
-			: : "Jr" (value));				\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            "mtc0\t%z0, " #register "\n\t"			\
+            : : "Jr" (value));				\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips32\n\t"				\
+            "mtc0\t%z0, " #register ", " #sel "\n\t"	\
+            ".set\tmips0"					\
+            : : "Jr" (value));				\
 } while (0)
 
 #define __write_64bit_c0_register(register, sel, value)			\
 do {									\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips3\n\t"				\
-			"dmtc0\t%z0, " #register "\n\t"			\
-			".set\tmips0"					\
-			: : "Jr" (value));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0"					\
-			: : "Jr" (value));				\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            ".set\tmips3\n\t"				\
+            "dmtc0\t%z0, " #register "\n\t"			\
+            ".set\tmips0"					\
+            : : "Jr" (value));				\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dmtc0\t%z0, " #register ", " #sel "\n\t"	\
+            ".set\tmips0"					\
+            : : "Jr" (value));				\
 } while (0)
 
 #define __read_ulong_c0_register(reg, sel)				\
-	((sizeof(unsigned long) == 4) ?					\
-	__read_32bit_c0_register(reg, sel) :				\
-	__read_64bit_c0_register(reg, sel))
+    ((sizeof(unsigned long) == 4) ?					\
+    __read_32bit_c0_register(reg, sel) :				\
+    __read_64bit_c0_register(reg, sel))
 
 #define __write_ulong_c0_register(reg, sel, val)			\
 do {									\
-	if (sizeof(unsigned long) == 4)					\
-		__write_32bit_c0_register(reg, sel, val);		\
-	else								\
-		__write_64bit_c0_register(reg, sel, val);		\
+    if (sizeof(unsigned long) == 4)					\
+        __write_32bit_c0_register(reg, sel, val);		\
+    else								\
+        __write_64bit_c0_register(reg, sel, val);		\
 } while (0)
 
 /*
@@ -808,59 +722,59 @@ do {									\
  */
 #define __read_64bit_c0_split(source, sel)				\
 ({									\
-	unsigned long long val;						\
-	unsigned long flags;						\
-									\
-	local_irq_save(flags);						\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%M0, " #source "\n\t"			\
-			"dsll\t%L0, %M0, 32\n\t"			\
-			"dsrl\t%M0, %M0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			".set\tmips0"					\
-			: "=r" (val));					\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%M0, " #source ", " #sel "\n\t"		\
-			"dsll\t%L0, %M0, 32\n\t"			\
-			"dsrl\t%M0, %M0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			".set\tmips0"					\
-			: "=r" (val));					\
-	local_irq_restore(flags);					\
-									\
-	val;								\
+    unsigned long long val;						\
+    unsigned long flags;						\
+                                    \
+    local_irq_save(flags);						\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dmfc0\t%M0, " #source "\n\t"			\
+            "dsll\t%L0, %M0, 32\n\t"			\
+            "dsrl\t%M0, %M0, 32\n\t"			\
+            "dsrl\t%L0, %L0, 32\n\t"			\
+            ".set\tmips0"					\
+            : "=r" (val));					\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dmfc0\t%M0, " #source ", " #sel "\n\t"		\
+            "dsll\t%L0, %M0, 32\n\t"			\
+            "dsrl\t%M0, %M0, 32\n\t"			\
+            "dsrl\t%L0, %L0, 32\n\t"			\
+            ".set\tmips0"					\
+            : "=r" (val));					\
+    local_irq_restore(flags);					\
+                                    \
+    val;								\
 })
 
 #define __write_64bit_c0_split(source, sel, val)			\
 do {									\
-	unsigned long flags;						\
-									\
-	local_irq_save(flags);						\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc0\t%L0, " #source "\n\t"			\
-			".set\tmips0"					\
-			: : "r" (val));					\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
-			".set\tmips0"					\
-			: : "r" (val));					\
-	local_irq_restore(flags);					\
+    unsigned long flags;						\
+                                    \
+    local_irq_save(flags);						\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dsll\t%L0, %L0, 32\n\t"			\
+            "dsrl\t%L0, %L0, 32\n\t"			\
+            "dsll\t%M0, %M0, 32\n\t"			\
+            "or\t%L0, %L0, %M0\n\t"				\
+            "dmtc0\t%L0, " #source "\n\t"			\
+            ".set\tmips0"					\
+            : : "r" (val));					\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dsll\t%L0, %L0, 32\n\t"			\
+            "dsrl\t%L0, %L0, 32\n\t"			\
+            "dsll\t%M0, %M0, 32\n\t"			\
+            "or\t%L0, %L0, %M0\n\t"				\
+            "dmtc0\t%L0, " #source ", " #sel "\n\t"		\
+            ".set\tmips0"					\
+            : : "r" (val));					\
+    local_irq_restore(flags);					\
 } while (0)
 
 #define read_c0_index()		__read_32bit_c0_register($0, 0)
@@ -906,6 +820,9 @@ do {									\
 
 #define read_c0_prid()		__read_32bit_c0_register($15, 0)
 
+#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
+
 #define read_c0_config()	__read_32bit_c0_register($16, 0)
 #define read_c0_config1()	__read_32bit_c0_register($16, 1)
 #define read_c0_config2()	__read_32bit_c0_register($16, 2)
@@ -1001,20 +918,20 @@ do {									\
 #define read_32bit_cp0_register(source)                         \
 ({ int __res;                                                   \
         __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
+    ".set\tpush\n\t"					\
+    ".set\treorder\n\t"					\
         "mfc0\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
+    ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
 #define read_32bit_cp0_set1_register(source)                    \
 ({ int __res;                                                   \
         __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
+    ".set\tpush\n\t"					\
+    ".set\treorder\n\t"					\
         "cfc0\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
+    ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
@@ -1033,13 +950,13 @@ do {									\
 #define write_32bit_cp0_register(register,value)                \
         __asm__ __volatile__(                                   \
         "mtc0\t%0,"STR(register)"\n\t"				\
-	"nop"							\
+    "nop"							\
         : : "r" (value));
 
 #define write_32bit_cp0_set1_register(register,value)           \
         __asm__ __volatile__(                                   \
         "ctc0\t%0,"STR(register)"\n\t"				\
-	"nop"							\
+    "nop"							\
         : : "r" (value));
 
 #define write_64bit_cp0_register(register,value)                \
@@ -1055,16 +972,16 @@ do {									\
 #define read_mips32_cp0_config1()                               \
 ({ int __res;                                                   \
         __asm__ __volatile__(                                   \
-	".set\tnoreorder\n\t"                                   \
-	".set\tnoat\n\t"                                        \
-	"#.set\tmips64\n\t"					\
-	"#mfc0\t$1, $16, 1\n\t"					\
-	"#.set\tmips0\n\t"					\
-     	".word\t0x40018001\n\t"                                 \
-	"move\t%0,$1\n\t"                                       \
-	".set\tat\n\t"                                          \
-	".set\treorder"                                         \
-	:"=r" (__res));                                         \
+    ".set\tnoreorder\n\t"                                   \
+    ".set\tnoat\n\t"                                        \
+    "#.set\tmips64\n\t"					\
+    "#mfc0\t$1, $16, 1\n\t"					\
+    "#.set\tmips0\n\t"					\
+         ".word\t0x40018001\n\t"                                 \
+    "move\t%0,$1\n\t"                                       \
+    ".set\tat\n\t"                                          \
+    ".set\treorder"                                         \
+    :"=r" (__res));                                         \
         __res;})
 
 #endif
@@ -1073,45 +990,51 @@ do {									\
  */
 #define read_32bit_cp1_register(source)                         \
 ({ int __res;                                                   \
-	__asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
+    __asm__ __volatile__(                                   \
+    ".set\tpush\n\t"					\
+    ".set\treorder\n\t"					\
         "cfc1\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
+    ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
+#define write_32bit_cp1_register(register,value)                \
+        __asm__ __volatile__(                                   \
+        "ctc1\t%0,"STR(register)"\n\t"				\
+    "nop"							\
+        : : "r" (value));
+
 /* TLB operations. */
 static inline void tlb_probe(void)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbp\n\t"
-		".set reorder");
+    __asm__ __volatile__(
+        ".set noreorder\n\t"
+        "tlbp\n\t"
+        ".set reorder");
 }
 
 static inline void tlb_read(void)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbr\n\t"
-		".set reorder");
+    __asm__ __volatile__(
+        ".set noreorder\n\t"
+        "tlbr\n\t"
+        ".set reorder");
 }
 
 static inline void tlb_write_indexed(void)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbwi\n\t"
-		".set reorder");
+    __asm__ __volatile__(
+        ".set noreorder\n\t"
+        "tlbwi\n\t"
+        ".set reorder");
 }
 
 static inline void tlb_write_random(void)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbwr\n\t"
-		".set reorder");
+    __asm__ __volatile__(
+        ".set noreorder\n\t"
+        "tlbwr\n\t"
+        ".set reorder");
 }
 
 /*
@@ -1121,38 +1044,38 @@ static inline void tlb_write_random(void)
 static inline unsigned int					\
 set_c0_##name(unsigned int set)					\
 {								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res |= set;						\
-	write_c0_##name(res);					\
-								\
-	return res;						\
+    unsigned int res;					\
+                                \
+    res = read_c0_##name();					\
+    res |= set;						\
+    write_c0_##name(res);					\
+                                \
+    return res;						\
 }								\
-								\
+                                \
 static inline unsigned int					\
 clear_c0_##name(unsigned int clear)				\
 {								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res &= ~clear;						\
-	write_c0_##name(res);					\
-								\
-	return res;						\
+    unsigned int res;					\
+                                \
+    res = read_c0_##name();					\
+    res &= ~clear;						\
+    write_c0_##name(res);					\
+                                \
+    return res;						\
 }								\
-								\
+                                \
 static inline unsigned int					\
 change_c0_##name(unsigned int change, unsigned int new)		\
 {								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res &= ~change;						\
-	res |= (new & change);					\
-	write_c0_##name(res);					\
-								\
-	return res;						\
+    unsigned int res;					\
+                                \
+    res = read_c0_##name();					\
+    res &= ~change;						\
+    res |= (new & change);					\
+    write_c0_##name(res);					\
+                                \
+    return res;						\
 }
 
 __BUILD_SET_C0(status,CP0_STATUS)
@@ -1163,6 +1086,17 @@ __BUILD_SET_C0(config,CP0_CONFIG)
 #define set_cp0_cause(x)	set_c0_cause(x)
 #define set_cp0_config(x)	set_c0_config(x)
 
+#define read_c1_status()	read_32bit_cp1_register(31)
+#define write_c1_status(x)	write_32bit_cp1_register(31, x)
+
+#define readb(reg)		(*((volatile unsigned char *) (reg)))
+#define readw(reg)		(*((volatile unsigned short *) (reg)))
+#define readl(reg)		(*((volatile unsigned int *) (reg)))
+
+#define writeb(data, reg)	((*((volatile unsigned char *)(reg))) = (unsigned char)(data))
+#define writew(data, reg)	((*((volatile unsigned short *)(reg))) = (unsigned short)(data))
+#define writel(data, reg)	((*((volatile unsigned int *)(reg))) = (unsigned int)(data))
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _MIPS_REGS_H_ */
diff --git a/libcpu/mips/common/mips_types.h b/libcpu/mips/common/mips_types.h
index 7f0b8a6855..cc12d44391 100644
--- a/libcpu/mips/common/mips_types.h
+++ b/libcpu/mips/common/mips_types.h
@@ -19,7 +19,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         the first version
  */
 
 #ifndef _MIPS_TYPES_H_
@@ -87,30 +87,17 @@ typedef unsigned long long u64;
 
 #endif
 
-#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
-    || defined(CONFIG_64BIT)
-typedef u64 dma_addr_t;
-
-typedef u64 phys_addr_t;
-typedef u64 phys_size_t;
-
-#else
 typedef u32 dma_addr_t;
 
 typedef u32 phys_addr_t;
 typedef u32 phys_size_t;
 
-#endif
-typedef u64 dma64_addr_t;
 
 /*
  * Don't use phys_t.  You've been warned.
  */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-typedef unsigned long long phys_t;
-#else
+
 typedef unsigned long phys_t;
-#endif
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/libcpu/mips/common/mipscfg.h b/libcpu/mips/common/mipscfg.h
deleted file mode 100644
index b4f30615f8..0000000000
--- a/libcpu/mips/common/mipscfg.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * File      : mipscfg.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#ifndef __MIPSCFG_H__
-#define __MIPSCFG_H__
-
-
-typedef struct mips32_core_cfg
-{
-    rt_uint16_t icache_line_size;
-    rt_uint16_t icache_lines_per_way;
-    rt_uint16_t icache_ways;
-    rt_uint16_t dcache_line_size;
-    rt_uint16_t dcache_lines_per_way;
-    rt_uint16_t dcache_ways;
-
-    rt_uint16_t max_tlb_entries;	/* number of tlb entry */
-} mips32_core_cfg_t;
-
-extern mips32_core_cfg_t g_mips_core;
-
-#endif /* end of __MIPSCFG_H__ */
diff --git a/libcpu/mips/common/mipsregs.h b/libcpu/mips/common/mipsregs.h
deleted file mode 100644
index 22e5754b8b..0000000000
--- a/libcpu/mips/common/mipsregs.h
+++ /dev/null
@@ -1,706 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Modified for further R[236]000 support by Paul M. Antoine, 1996.
- * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- * Copyright (C) 2003, 2004  Maciej W. Rozycki
- *
- * Change Logs:
- * Date           Author       Notes
- *
- */
-#ifndef __MIPSREGS_H__
-#define __MIPSREGS_H__
-
-/*
- * The following macros are especially useful for __asm__
- * inline assembler.
- */
-#ifndef __STR
-#define __STR(x) #x
-#endif
-#ifndef STR
-#define STR(x) __STR(x)
-#endif
-
-/*
- *  Configure language
- */
-#ifdef __ASSEMBLY__
-#define _ULCAST_
-#else
-#define _ULCAST_ (unsigned long)
-#endif
-
-/*
- * Coprocessor 0 register names
- */
-#define CP0_INDEX 			$0
-#define CP0_RANDOM		 	$1
-#define CP0_ENTRYLO0 		$2
-#define CP0_ENTRYLO1 		$3
-#define CP0_CONF 			$3
-#define CP0_CONTEXT 		$4
-#define CP0_PAGEMASK 		$5
-#define CP0_WIRED 			$6
-#define CP0_INFO 			$7
-#define CP0_BADVADDR 		$8
-#define CP0_COUNT 			$9
-#define CP0_ENTRYHI 		$10
-#define CP0_COMPARE 		$11
-#define CP0_STATUS 			$12
-#define CP0_CAUSE 			$13
-#define CP0_EPC 			$14
-#define CP0_PRID 			$15
-#define CP0_CONFIG 			$16
-#define CP0_LLADDR 			$17
-#define CP0_WATCHLO 		$18
-#define CP0_WATCHHI 		$19
-#define CP0_XCONTEXT 		$20
-#define CP0_FRAMEMASK 		$21
-#define CP0_DIAGNOSTIC 		$22
-#define CP0_DEBUG 			$23
-#define CP0_DEPC 			$24
-#define CP0_PERFORMANCE 	$25
-#define CP0_ECC 			$26
-#define CP0_CACHEERR 		$27
-#define CP0_TAGLO 			$28
-#define CP0_TAGHI 			$29
-#define CP0_ERROREPC 		$30
-#define CP0_DESAVE 			$31
-
-/*
- * R4640/R4650 cp0 register names.  These registers are listed
- * here only for completeness; without MMU these CPUs are not useable
- * by Linux.  A future ELKS port might take make Linux run on them
- * though ...
- */
-#define CP0_IBASE 			$0
-#define CP0_IBOUND 			$1
-#define CP0_DBASE 			$2
-#define CP0_DBOUND 			$3
-#define CP0_CALG 			$17
-#define CP0_IWATCH 			$18
-#define CP0_DWATCH 			$19
-
-/*
- * Coprocessor 0 Set 1 register names
- */
-#define CP0_S1_DERRADDR0  	$26
-#define CP0_S1_DERRADDR1  	$27
-#define CP0_S1_INTCONTROL 	$20
-
-/*
- * Coprocessor 0 Set 2 register names
- */
-#define CP0_S2_SRSCTL	  	$12	/* MIPSR2 */
-
-/*
- * Coprocessor 0 Set 3 register names
- */
-#define CP0_S3_SRSMAP	  	$12	/* MIPSR2 */
-
-/*
- *  TX39 Series
- */
-#define CP0_TX39_CACHE		$7
-
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION   		$0
-#define CP1_STATUS     		$31
-
-/*
- * FPU Status Register Values
- */
-/*
- * Status Register Values
- */
-
-#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
-#define FPU_CSR_COND    0x00800000      /* $fcc0 */
-#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
-#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
-#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
-#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
-#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
-#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
-#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
-#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
-
-
-/* FS/FO/FN */
-#define FPU_CSR_FS      0x01000000
-#define FPU_CSR_FO      0x00400000
-#define FPU_CSR_FN      0x00200000
-
-/*
- * Bits 18 - 20 of the FPU Status Register will be read as 0,
- * and should be written as zero.
- */
-#define FPU_CSR_RSVD	0x001c0000
-
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
-*/
-#define FPU_CSR_ALL_X   0x0003f000
-#define FPU_CSR_UNI_X   0x00020000
-#define FPU_CSR_INV_X   0x00010000
-#define FPU_CSR_DIV_X   0x00008000
-#define FPU_CSR_OVF_X   0x00004000
-#define FPU_CSR_UDF_X   0x00002000
-#define FPU_CSR_INE_X   0x00001000
-
-#define FPU_CSR_ALL_E   0x00000f80
-#define FPU_CSR_INV_E   0x00000800
-#define FPU_CSR_DIV_E   0x00000400
-#define FPU_CSR_OVF_E   0x00000200
-#define FPU_CSR_UDF_E   0x00000100
-#define FPU_CSR_INE_E   0x00000080
-
-#define FPU_CSR_ALL_S   0x0000007c
-#define FPU_CSR_INV_S   0x00000040
-#define FPU_CSR_DIV_S   0x00000020
-#define FPU_CSR_OVF_S   0x00000010
-#define FPU_CSR_UDF_S   0x00000008
-#define FPU_CSR_INE_S   0x00000004
-
-/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
-#define FPU_CSR_RM	0x00000003
-#define FPU_CSR_RN      0x0     /* nearest */
-#define FPU_CSR_RZ      0x1     /* towards zero */
-#define FPU_CSR_RU      0x2     /* towards +Infinity */
-#define FPU_CSR_RD      0x3     /* towards -Infinity */
-
-
-/*
- * R4x00 interrupt enable / cause bits
- */
-#define IE_SW0          (_ULCAST_(1) <<  8)
-#define IE_SW1          (_ULCAST_(1) <<  9)
-#define IE_IRQ0         (_ULCAST_(1) << 10)
-#define IE_IRQ1         (_ULCAST_(1) << 11)
-#define IE_IRQ2         (_ULCAST_(1) << 12)
-#define IE_IRQ3         (_ULCAST_(1) << 13)
-#define IE_IRQ4         (_ULCAST_(1) << 14)
-#define IE_IRQ5         (_ULCAST_(1) << 15)
-
-/*
- * R4x00 interrupt cause bits
- */
-#define C_SW0           (_ULCAST_(1) <<  8)
-#define C_SW1           (_ULCAST_(1) <<  9)
-#define C_IRQ0          (_ULCAST_(1) << 10)
-#define C_IRQ1          (_ULCAST_(1) << 11)
-#define C_IRQ2          (_ULCAST_(1) << 12)
-#define C_IRQ3          (_ULCAST_(1) << 13)
-#define C_IRQ4          (_ULCAST_(1) << 14)
-#define C_IRQ5          (_ULCAST_(1) << 15)
-
-/*
- * Bitfields in the R4xx0 cp0 status register
- */
-#define ST0_IE					0x00000001
-#define ST0_EXL					0x00000002
-#define ST0_ERL					0x00000004
-#define ST0_KSU					0x00000018
-#  define KSU_USER					0x00000010
-#  define KSU_SUPERVISOR			0x00000008
-#  define KSU_KERNEL				0x00000000
-#define ST0_UX					0x00000020
-#define ST0_SX					0x00000040
-#define ST0_KX 					0x00000080
-#define ST0_DE					0x00010000
-#define ST0_CE					0x00020000
-
-/*
- * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
- * cacheops in userspace.  This bit exists only on RM7000 and RM9000
- * processors.
- */
-#define ST0_CO					0x08000000
-
-/*
- * Bitfields in the R[23]000 cp0 status register.
- */
-#define ST0_IEC                 0x00000001
-#define ST0_KUC					0x00000002
-#define ST0_IEP					0x00000004
-#define ST0_KUP					0x00000008
-#define ST0_IEO					0x00000010
-#define ST0_KUO					0x00000020
-/* bits 6 & 7 are reserved on R[23]000 */
-#define ST0_ISC					0x00010000
-#define ST0_SWC					0x00020000
-#define ST0_CM					0x00080000
-
-/*
- * Bits specific to the R4640/R4650
- */
-#define ST0_UM					(_ULCAST_(1) <<  4)
-#define ST0_IL					(_ULCAST_(1) << 23)
-#define ST0_DL					(_ULCAST_(1) << 24)
-
-/*
- * Enable the MIPS DSP ASE
- */
-#define ST0_MX					0x01000000
-
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT		19
-#define TX39_CONF_ICS_MASK		0x00380000
-#define TX39_CONF_ICS_1KB 		0x00000000
-#define TX39_CONF_ICS_2KB 		0x00080000
-#define TX39_CONF_ICS_4KB 		0x00100000
-#define TX39_CONF_ICS_8KB 		0x00180000
-#define TX39_CONF_ICS_16KB 		0x00200000
-
-#define TX39_CONF_DCS_SHIFT		16
-#define TX39_CONF_DCS_MASK		0x00070000
-#define TX39_CONF_DCS_1KB 		0x00000000
-#define TX39_CONF_DCS_2KB 		0x00010000
-#define TX39_CONF_DCS_4KB 		0x00020000
-#define TX39_CONF_DCS_8KB 		0x00030000
-#define TX39_CONF_DCS_16KB 		0x00040000
-
-#define TX39_CONF_CWFON 		0x00004000
-#define TX39_CONF_WBON  		0x00002000
-#define TX39_CONF_RF_SHIFT		10
-#define TX39_CONF_RF_MASK		0x00000c00
-#define TX39_CONF_DOZE			0x00000200
-#define TX39_CONF_HALT			0x00000100
-#define TX39_CONF_LOCK			0x00000080
-#define TX39_CONF_ICE			0x00000020
-#define TX39_CONF_DCE			0x00000010
-#define TX39_CONF_IRSIZE_SHIFT	2
-#define TX39_CONF_IRSIZE_MASK	0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT	0
-#define TX39_CONF_DRSIZE_MASK	0x00000003
-
-/*
- * Status register bits available in all MIPS CPUs.
- */
-#define  ST0_IM			    0x0000ff00
-#define  STATUSB_IP0		8
-#define  STATUSF_IP0		(_ULCAST_(1) <<  8)
-#define  STATUSB_IP1		9
-#define  STATUSF_IP1		(_ULCAST_(1) <<  9)
-#define  STATUSB_IP2		10
-#define  STATUSF_IP2		(_ULCAST_(1) << 10)
-#define  STATUSB_IP3		11
-#define  STATUSF_IP3		(_ULCAST_(1) << 11)
-#define  STATUSB_IP4		12
-#define  STATUSF_IP4		(_ULCAST_(1) << 12)
-#define  STATUSB_IP5		13
-#define  STATUSF_IP5		(_ULCAST_(1) << 13)
-#define  STATUSB_IP6		14
-#define  STATUSF_IP6		(_ULCAST_(1) << 14)
-#define  STATUSB_IP7		15
-#define  STATUSF_IP7		(_ULCAST_(1) << 15)
-#define  STATUSB_IP8		0
-#define  STATUSF_IP8		(_ULCAST_(1) <<  0)
-#define  STATUSB_IP9		1
-#define  STATUSF_IP9		(_ULCAST_(1) <<  1)
-#define  STATUSB_IP10		2
-#define  STATUSF_IP10		(_ULCAST_(1) <<  2)
-#define  STATUSB_IP11		3
-#define  STATUSF_IP11		(_ULCAST_(1) <<  3)
-#define  STATUSB_IP12		4
-#define  STATUSF_IP12		(_ULCAST_(1) <<  4)
-#define  STATUSB_IP13		5
-#define  STATUSF_IP13		(_ULCAST_(1) <<  5)
-#define  STATUSB_IP14		6
-#define  STATUSF_IP14		(_ULCAST_(1) <<  6)
-#define  STATUSB_IP15		7
-#define  STATUSF_IP15		(_ULCAST_(1) <<  7)
-#define  ST0_CH				0x00040000
-#define  ST0_SR				0x00100000
-#define  ST0_TS				0x00200000
-#define  ST0_BEV			0x00400000
-#define  ST0_RE				0x02000000
-#define  ST0_FR				0x04000000
-#define  ST0_CU				0xf0000000
-#define  ST0_CU0			0x10000000
-#define  ST0_CU1			0x20000000
-#define  ST0_CU2			0x40000000
-#define  ST0_CU3			0x80000000
-#define  ST0_XX				0x80000000	/* MIPS IV naming */
-
-/*
- * Bitfields and bit numbers in the coprocessor 0 cause register.
- *
- * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
- */
-#define  CAUSEB_EXCCODE		2
-#define  CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
-#define  CAUSEB_IP			8
-#define  CAUSEF_IP			(_ULCAST_(255) <<  8)
-#define  CAUSEB_IP0			8
-#define  CAUSEF_IP0			(_ULCAST_(1)   <<  8)
-#define  CAUSEB_IP1			9
-#define  CAUSEF_IP1			(_ULCAST_(1)   <<  9)
-#define  CAUSEB_IP2			10
-#define  CAUSEF_IP2			(_ULCAST_(1)   << 10)
-#define  CAUSEB_IP3			11
-#define  CAUSEF_IP3			(_ULCAST_(1)   << 11)
-#define  CAUSEB_IP4			12
-#define  CAUSEF_IP4			(_ULCAST_(1)   << 12)
-#define  CAUSEB_IP5			13
-#define  CAUSEF_IP5			(_ULCAST_(1)   << 13)
-#define  CAUSEB_IP6			14
-#define  CAUSEF_IP6			(_ULCAST_(1)   << 14)
-#define  CAUSEB_IP7			15
-#define  CAUSEF_IP7			(_ULCAST_(1)   << 15)
-#define  CAUSEB_IV			23
-#define  CAUSEF_IV			(_ULCAST_(1)   << 23)
-#define  CAUSEB_CE			28
-#define  CAUSEF_CE			(_ULCAST_(3)   << 28)
-#define  CAUSEB_BD			31
-#define  CAUSEF_BD			(_ULCAST_(1)   << 31)
-
-/*
- * Bits in the coprocessor 0 config register.
- */
-/* Generic bits.  */
-#define CONF_CM_CACHABLE_NO_WA			0
-#define CONF_CM_CACHABLE_WA				1
-#define CONF_CM_UNCACHED				2
-#define CONF_CM_CACHABLE_NONCOHERENT	3
-#define CONF_CM_CACHABLE_CE				4
-#define CONF_CM_CACHABLE_COW			5
-#define CONF_CM_CACHABLE_CUW			6
-#define CONF_CM_CACHABLE_ACCELERATED	7
-#define CONF_CM_CMASK					7
-#define CONF_BE							(_ULCAST_(1) << 15)
-
-/* Bits common to various processors.  */
-#define CONF_CU				(_ULCAST_(1) <<  3)
-#define CONF_DB				(_ULCAST_(1) <<  4)
-#define CONF_IB				(_ULCAST_(1) <<  5)
-#define CONF_DC				(_ULCAST_(7) <<  6)
-#define CONF_IC				(_ULCAST_(7) <<  9)
-#define CONF_EB				(_ULCAST_(1) << 13)
-#define CONF_EM				(_ULCAST_(1) << 14)
-#define CONF_SM				(_ULCAST_(1) << 16)
-#define CONF_SC				(_ULCAST_(1) << 17)
-#define CONF_EW				(_ULCAST_(3) << 18)
-#define CONF_EP				(_ULCAST_(15)<< 24)
-#define CONF_EC				(_ULCAST_(7) << 28)
-#define CONF_CM				(_ULCAST_(1) << 31)
-
-/* Bits specific to the R4xx0.  */
-#define R4K_CONF_SW			(_ULCAST_(1) << 20)
-#define R4K_CONF_SS			(_ULCAST_(1) << 21)
-#define R4K_CONF_SB			(_ULCAST_(3) << 22)
-
-/* Bits specific to the R5000.  */
-#define R5K_CONF_SE			(_ULCAST_(1) << 12)
-#define R5K_CONF_SS			(_ULCAST_(3) << 20)
-
-/* Bits specific to the RM7000.  */
-#define RM7K_CONF_SE		(_ULCAST_(1) <<  3)
-#define RM7K_CONF_TE		(_ULCAST_(1) << 12)
-#define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
-#define RM7K_CONF_TC		(_ULCAST_(1) << 17)
-#define RM7K_CONF_SI		(_ULCAST_(3) << 20)
-#define RM7K_CONF_SC		(_ULCAST_(1) << 31)
-
-/* Bits specific to the R10000.  */
-#define R10K_CONF_DN		(_ULCAST_(3) <<  3)
-#define R10K_CONF_CT		(_ULCAST_(1) <<  5)
-#define R10K_CONF_PE		(_ULCAST_(1) <<  6)
-#define R10K_CONF_PM		(_ULCAST_(3) <<  7)
-#define R10K_CONF_EC		(_ULCAST_(15)<<  9)
-#define R10K_CONF_SB		(_ULCAST_(1) << 13)
-#define R10K_CONF_SK		(_ULCAST_(1) << 14)
-#define R10K_CONF_SS		(_ULCAST_(7) << 16)
-#define R10K_CONF_SC		(_ULCAST_(7) << 19)
-#define R10K_CONF_DC		(_ULCAST_(7) << 26)
-#define R10K_CONF_IC		(_ULCAST_(7) << 29)
-
-/* Bits specific to the VR41xx.  */
-#define VR41_CONF_CS		(_ULCAST_(1) << 12)
-#define VR41_CONF_M16		(_ULCAST_(1) << 20)
-#define VR41_CONF_AD		(_ULCAST_(1) << 23)
-
-/* Bits specific to the R30xx.  */
-#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
-#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
-#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
-#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
-#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
-#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
-#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
-#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
-#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
-
-/* Bits specific to the TX49.  */
-#define TX49_CONF_DC		(_ULCAST_(1) << 16)
-#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
-#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
-#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
-
-/* Bits specific to the MIPS32/64 PRA.  */
-#define MIPS_CONF_MT		(_ULCAST_(7) <<  7)
-#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
-#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
-#define MIPS_CONF_M			(_ULCAST_(1) << 31)
-
-/*
- * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
- */
-#define MIPS_CONF1_FP		(_ULCAST_(1) <<  0)
-#define MIPS_CONF1_EP		(_ULCAST_(1) <<  1)
-#define MIPS_CONF1_CA		(_ULCAST_(1) <<  2)
-#define MIPS_CONF1_WR		(_ULCAST_(1) <<  3)
-#define MIPS_CONF1_PC		(_ULCAST_(1) <<  4)
-#define MIPS_CONF1_MD		(_ULCAST_(1) <<  5)
-#define MIPS_CONF1_C2		(_ULCAST_(1) <<  6)
-#define MIPS_CONF1_DA		(_ULCAST_(7) <<  7)
-#define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
-#define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
-#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
-#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
-#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS		(_ULCAST_(63)<< 25)
-
-#define MIPS_CONF2_SA		(_ULCAST_(15)<<  0)
-#define MIPS_CONF2_SL		(_ULCAST_(15)<<  4)
-#define MIPS_CONF2_SS		(_ULCAST_(15)<<  8)
-#define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
-#define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
-#define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
-#define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
-#define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
-
-#define MIPS_CONF3_TL		(_ULCAST_(1) <<  0)
-#define MIPS_CONF3_SM		(_ULCAST_(1) <<  1)
-#define MIPS_CONF3_MT		(_ULCAST_(1) <<  2)
-#define MIPS_CONF3_SP		(_ULCAST_(1) <<  4)
-#define MIPS_CONF3_VINT		(_ULCAST_(1) <<  5)
-#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<  6)
-#define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)
-#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
-
-/*
- * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
- */
-#define MIPS_FPIR_S			(_ULCAST_(1) << 16)
-#define MIPS_FPIR_D			(_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
-#define MIPS_FPIR_W			(_ULCAST_(1) << 20)
-#define MIPS_FPIR_L			(_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
-
-/*
- * R10000 performance counter definitions.
- *
- * FIXME: The R10000 performance counter opens a nice way to implement CPU
- *        time accounting with a precission of one cycle.  I don't have
- *        R10000 silicon but just a manual, so ...
- */
-
-/*
- * Events counted by counter #0
- */
-#define CE0_CYCLES						0
-#define CE0_INSN_ISSUED					1
-#define CE0_LPSC_ISSUED					2
-#define CE0_S_ISSUED					3
-#define CE0_SC_ISSUED					4
-#define CE0_SC_FAILED					5
-#define CE0_BRANCH_DECODED				6
-#define CE0_QW_WB_SECONDARY				7
-#define CE0_CORRECTED_ECC_ERRORS		8
-#define CE0_ICACHE_MISSES				9
-#define CE0_SCACHE_I_MISSES				10
-#define CE0_SCACHE_I_WAY_MISSPREDICTED	11
-#define CE0_EXT_INTERVENTIONS_REQ		12
-#define CE0_EXT_INVALIDATE_REQ			13
-#define CE0_VIRTUAL_COHERENCY_COND		14
-#define CE0_INSN_GRADUATED				15
-
-/*
- * Events counted by counter #1
- */
-#define CE1_CYCLES						0
-#define CE1_INSN_GRADUATED				1
-#define CE1_LPSC_GRADUATED				2
-#define CE1_S_GRADUATED					3
-#define CE1_SC_GRADUATED				4
-#define CE1_FP_INSN_GRADUATED			5
-#define CE1_QW_WB_PRIMARY				6
-#define CE1_TLB_REFILL					7
-#define CE1_BRANCH_MISSPREDICTED		8
-#define CE1_DCACHE_MISS					9
-#define CE1_SCACHE_D_MISSES				10
-#define CE1_SCACHE_D_WAY_MISSPREDICTED	11
-#define CE1_EXT_INTERVENTION_HITS		12
-#define CE1_EXT_INVALIDATE_REQ			13
-#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS	14
-#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS	15
-
-/*
- * These flags define in which privilege mode the counters count events
- */
-#define CEB_USER		8	/* Count events in user mode, EXL = ERL = 0 */
-#define CEB_SUPERVISOR	4	/* Count events in supvervisor mode EXL = ERL = 0 */
-#define CEB_KERNEL		2	/* Count events in kernel mode EXL = ERL = 0 */
-#define CEB_EXL			1	/* Count events with EXL = 1, ERL = 0 */
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * Macros to access the system control coprocessor
- */
-#define __read_32bit_c0_register(source, sel)				\
-({ int __res;								\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mfc0\t%0, " #source "\n\t"			\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	__res;								\
-})
-
-#define __write_32bit_c0_register(register, sel, value)			\
-do {									\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mtc0\t%z0, " #register "\n\t"			\
-			: : "Jr" ((unsigned int)(value)));		\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0"					\
-			: : "Jr" ((unsigned int)(value)));		\
-} while (0)
-
-#define read_c0_index()			__read_32bit_c0_register($0, 0)
-#define write_c0_index(val)		__write_32bit_c0_register($0, 0, val)
-
-#define read_c0_random()		__read_32bit_c0_register($1, 0)
-#define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
-
-#define read_c0_entrylo0()		__read_32bit_c0_register($2, 0)
-#define write_c0_entrylo0(val)	__write_32bit_c0_register($2, 0, val)
-
-#define read_c0_entrylo1()		__read_32bit_c0_register($3, 0)
-#define write_c0_entrylo1(val)	__write_32bit_c0_register($3, 0, val)
-
-#define read_c0_conf()			__read_32bit_c0_register($3, 0)
-#define write_c0_conf(val)		__write_32bit_c0_register($3, 0, val)
-
-#define read_c0_context()		__read_32bit_c0_register($4, 0)
-#define write_c0_context(val)	__write_32bit_c0_register($4, 0, val)
-
-#define read_c0_userlocal()		__read_32bit_c0_register($4, 2)
-#define write_c0_userlocal(val)	__write_32bit_c0_register($4, 2, val)
-
-#define read_c0_pagemask()		__read_32bit_c0_register($5, 0)
-#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
-
-#define read_c0_wired()			__read_32bit_c0_register($6, 0)
-#define write_c0_wired(val)		__write_32bit_c0_register($6, 0, val)
-
-#define read_c0_info()			__read_32bit_c0_register($7, 0)
-
-#define read_c0_cache()			__read_32bit_c0_register($7, 0)	/* TX39xx */
-#define write_c0_cache(val)		__write_32bit_c0_register($7, 0, val)
-
-#define read_c0_badvaddr()		__read_32bit_c0_register($8, 0)
-#define write_c0_badvaddr(val)	__write_32bit_c0_register($8, 0, val)
-
-#define read_c0_count()			__read_32bit_c0_register($9, 0)
-#define write_c0_count(val)		__write_32bit_c0_register($9, 0, val)
-
-#define read_c0_count2()		__read_32bit_c0_register($9, 6) /* pnx8550 */
-#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
-
-#define read_c0_count3()		__read_32bit_c0_register($9, 7) /* pnx8550 */
-#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
-
-#define read_c0_entryhi()		__read_32bit_c0_register($10, 0)
-#define write_c0_entryhi(val)	__write_32bit_c0_register($10, 0, val)
-
-#define read_c0_compare()		__read_32bit_c0_register($11, 0)
-#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
-
-#define read_c0_compare2()		__read_32bit_c0_register($11, 6) /* pnx8550 */
-#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
-
-#define read_c0_compare3()		__read_32bit_c0_register($11, 7) /* pnx8550 */
-#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
-
-#define read_c0_status()		__read_32bit_c0_register($12, 0)
-#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
-
-#define read_c0_cause()			__read_32bit_c0_register($13, 0)
-#define write_c0_cause(val)		__write_32bit_c0_register($13, 0, val)
-
-#define read_c0_epc()			__read_32bit_c0_register($14, 0)
-#define write_c0_epc(val)		__write_32bit_c0_register($14, 0, val)
-
-#define read_c0_prid()			__read_32bit_c0_register($15, 0)
-
-#define read_c0_ebase()			__read_32bit_c0_register($15, 1)
-#define write_c0_ebase(val)		__write_32bit_c0_register($15, 1, val)
-
-#define read_c0_config()		__read_32bit_c0_register($16, 0)
-#define read_c0_config1()		__read_32bit_c0_register($16, 1)
-#define read_c0_config2()		__read_32bit_c0_register($16, 2)
-#define read_c0_config3()		__read_32bit_c0_register($16, 3)
-#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
-#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
-#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
-#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
-
-
-/*
- * Macros to access the floating point coprocessor control registers
- */
-#define read_32bit_cp1_register(source)                         \
-({ int __res;                                                   \
-	__asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
-	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
-	".set\tmips1\n\t"					\
-        "cfc1\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
-        : "=r" (__res));                                        \
-        __res;})
-#define write_32bit_cp1_register(register, value)   \
-do {                                        \
-    __asm__ __volatile__(                   \
-        "ctc1\t%z0, "STR(register)"\n\t"      \
-        : : "Jr" ((unsigned int)(value)));  \
-} while (0)
-        
-#define read_c1_status()            read_32bit_cp1_register(CP1_STATUS)
-#define read_c1_revision()          read_32bit_cp1_register(CP1_REVISION);
-#define write_c1_status(val)        write_32bit_cp1_register(CP1_STATUS, val)
-
-
-#endif /* end of __ASSEMBLY__ */
-
-#endif /* end of __MIPSREGS_H__ */
-
diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h
new file mode 100644
index 0000000000..cae57cbf4c
--- /dev/null
+++ b/libcpu/mips/common/ptrace.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef _MIPS_PTRACE_H
+#define _MIPS_PTRACE_H
+
+#include "asm.h"
+#include "mips_regs.h"
+
+#define FP_REG_SIZE 8
+#define NUM_FPU_REGS 16
+
+#ifndef __ASSEMBLY__
+#include <rtthread.h>
+
+struct mips_fpu_struct {
+    rt_uint64_t	fpr[NUM_FPU_REGS];
+    rt_uint32_t	fcr31;
+    rt_uint32_t	pad;
+};
+
+struct pt_regs {
+    /* Only O32 Need This! */
+    /* Pad bytes for argument save space on the stack. */
+    rt_uint32_t pad0[8];
+
+    /* Saved main processor registers. */
+    rt_uint32_t regs[32];
+
+    /* Saved special registers. */
+    rt_uint32_t cp0_status;
+    rt_uint32_t hi;
+    rt_uint32_t lo;
+    rt_uint32_t cp0_badvaddr;
+    rt_uint32_t cp0_cause;
+    rt_uint32_t cp0_epc;
+
+#ifdef RT_USING_FPU
+    /* FPU Registers */
+    /* Unlike Linux Kernel, we save these registers unconditionally,
+     * so it should be a part of pt_regs */
+    struct mips_fpu_struct fpu;
+#endif
+} __aligned(8);
+#endif
+
+/* Note: For call stack o32 ABI has 0x8 shadowsoace Here  */
+#define PT_R0		(0x8 * LONGSIZE)	/* 0 */
+#define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
+#define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
+#define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
+#define PT_R4		((PT_R3) + LONGSIZE)	/* 4 */
+#define PT_R5		((PT_R4) + LONGSIZE)	/* 5 */
+#define PT_R6		((PT_R5) + LONGSIZE)	/* 6 */
+#define PT_R7		((PT_R6) + LONGSIZE)	/* 7 */
+#define PT_R8		((PT_R7) + LONGSIZE)	/* 8 */
+#define PT_R9		((PT_R8) + LONGSIZE)	/* 9 */
+#define PT_R10		((PT_R9) + LONGSIZE)	/* 10 */
+#define PT_R11		((PT_R10) + LONGSIZE)	/* 11 */
+#define PT_R12		((PT_R11) + LONGSIZE)	/* 12 */
+#define PT_R13		((PT_R12) + LONGSIZE)	/* 13 */
+#define PT_R14		((PT_R13) + LONGSIZE)	/* 14 */
+#define PT_R15		((PT_R14) + LONGSIZE)	/* 15 */
+#define PT_R16		((PT_R15) + LONGSIZE)	/* 16 */
+#define PT_R17		((PT_R16) + LONGSIZE)	/* 17 */
+#define PT_R18		((PT_R17) + LONGSIZE)	/* 18 */
+#define PT_R19		((PT_R18) + LONGSIZE)	/* 19 */
+#define PT_R20		((PT_R19) + LONGSIZE)	/* 20 */
+#define PT_R21		((PT_R20) + LONGSIZE)	/* 21 */
+#define PT_R22		((PT_R21) + LONGSIZE)	/* 22 */
+#define PT_R23		((PT_R22) + LONGSIZE)	/* 23 */
+#define PT_R24		((PT_R23) + LONGSIZE)	/* 24 */
+#define PT_R25		((PT_R24) + LONGSIZE)	/* 25 */
+#define PT_R26		((PT_R25) + LONGSIZE)	/* 26 */
+#define PT_R27		((PT_R26) + LONGSIZE)	/* 27 */
+#define PT_R28		((PT_R27) + LONGSIZE)	/* 28 */
+#define PT_R29		((PT_R28) + LONGSIZE)	/* 29 */
+#define PT_R30		((PT_R29) + LONGSIZE)	/* 30 */
+#define PT_R31		((PT_R30) + LONGSIZE)	/* 31 */
+
+/*
+ * Saved special registers
+ */
+#define PT_STATUS	((PT_R31) + LONGSIZE)	/* 32 */
+#define PT_HI		((PT_STATUS) + LONGSIZE)	/* 33 */
+#define PT_LO		((PT_HI) + LONGSIZE)	/* 34 */
+#define PT_BADVADDR	((PT_LO) + LONGSIZE)	/* 35 */
+#define PT_CAUSE	((PT_BADVADDR) + LONGSIZE)	/* 36 */
+#define PT_EPC		((PT_CAUSE) + LONGSIZE)	/* 37 */
+
+#define PT_REG_END		((PT_EPC) + LONGSIZE) /* Align already ensured manually */
+
+#ifdef RT_USING_FPU
+#define PT_FPU_R0               (PT_REG_END)
+#define PT_FPU_R2               ((PT_FPU_R0) + FP_REG_SIZE)
+#define PT_FPU_R4               ((PT_FPU_R2) + FP_REG_SIZE)
+#define PT_FPU_R6               ((PT_FPU_R4) + FP_REG_SIZE)
+#define PT_FPU_R8               ((PT_FPU_R6) + FP_REG_SIZE)
+#define PT_FPU_R10              ((PT_FPU_R8) + FP_REG_SIZE)
+#define PT_FPU_R12              ((PT_FPU_R10) + FP_REG_SIZE)
+#define PT_FPU_R14              ((PT_FPU_R12) + FP_REG_SIZE)
+#define PT_FPU_R16              ((PT_FPU_R14) + FP_REG_SIZE)
+#define PT_FPU_R18              ((PT_FPU_R16) + FP_REG_SIZE)
+#define PT_FPU_R20              ((PT_FPU_R18) + FP_REG_SIZE)
+#define PT_FPU_R22              ((PT_FPU_R20) + FP_REG_SIZE)
+#define PT_FPU_R24              ((PT_FPU_R22) + FP_REG_SIZE)
+#define PT_FPU_R26              ((PT_FPU_R24) + FP_REG_SIZE)
+#define PT_FPU_R28              ((PT_FPU_R26) + FP_REG_SIZE)
+#define PT_FPU_R30              ((PT_FPU_R28) + FP_REG_SIZE)
+#define PT_FPU_FCSR31           ((PT_FPU_R30) + FP_REG_SIZE)
+#define PT_FPU_PAD0             ((PT_FPU_FCSR31) + LONGSIZE)
+
+#define PT_FPU_END     	        ((PT_FPU_PAD0) + LONGSIZE)
+#define PT_SIZE			PT_FPU_END
+#else
+#define PT_SIZE			PT_REG_END
+#endif
+
+#endif
\ No newline at end of file
diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c
new file mode 100644
index 0000000000..b0e613c7a7
--- /dev/null
+++ b/libcpu/mips/common/stack.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#include <rtthread.h>
+
+#include "mips.h"
+
+register rt_uint32_t $GP __asm__ ("$28");
+
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
+{
+    static rt_uint32_t wSR=0;
+    static rt_uint32_t wGP;
+    rt_uint8_t *stk;
+
+    struct pt_regs *pt;
+
+    rt_uint32_t i;
+
+    /* Get stack aligned */
+    stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk -= sizeof(struct pt_regs);
+    pt =  (struct pt_regs*)stk;
+
+    for (i = 0; i < 8; ++i)
+    {
+        pt->pad0[i] = 0xdeadbeef;
+    }
+
+    /* Fill Stack register numbers */
+    for (i = 0; i < 32; ++i)
+    {
+        pt->regs[i] = 0xdeadbeef;
+    }
+
+    pt->regs[REG_SP] = (rt_uint32_t)stk;
+    pt->regs[REG_A0] = (rt_uint32_t)parameter;
+    pt->regs[REG_GP] = (rt_uint32_t)$GP;
+    pt->regs[REG_FP] = (rt_uint32_t)0x0;
+    pt->regs[REG_RA] = (rt_uint32_t)texit;
+
+    pt->hi	= 0x0;
+    pt->lo	= 0x0;
+    pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM);
+#ifdef RT_USING_FPU
+    pt->cp0_status |= (ST0_CU1 | ST0_FR);
+#endif
+    pt->cp0_cause	= read_c0_cause();
+    pt->cp0_epc	= (rt_uint32_t)tentry;
+    pt->cp0_badvaddr	= 0x0;
+
+    return stk;
+}
diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h
index 96b69ab14f..77d55f6934 100644
--- a/libcpu/mips/common/stackframe.h
+++ b/libcpu/mips/common/stackframe.h
@@ -1,228 +1,250 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
- * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2007  Maciej W. Rozycki
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
+
 #ifndef __STACKFRAME_H__
 #define __STACKFRAME_H__
 
 #include "asm.h"
-#include "mipsregs.h"
-
-/*
- * Stack layout for the INT exception handler
- * Derived from the stack layout described in asm-mips/stackframe.h
- *
- * The first PTRSIZE*6 bytes are argument save space for C subroutines.
- */
-
-//#define PT_R0		(PTRSIZE*6)			/* 0 */
-#define PT_R0		(0)						/* 0 */
-#define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
-#define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
-#define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
-#define PT_R4		((PT_R3) + LONGSIZE)	/* 4 */
-#define PT_R5		((PT_R4) + LONGSIZE)	/* 5 */
-#define PT_R6		((PT_R5) + LONGSIZE)	/* 6 */
-#define PT_R7		((PT_R6) + LONGSIZE)	/* 7 */
-#define PT_R8		((PT_R7) + LONGSIZE)	/* 8 */
-#define PT_R9		((PT_R8) + LONGSIZE)	/* 9 */
-#define PT_R10		((PT_R9) + LONGSIZE)	/* 10 */
-#define PT_R11		((PT_R10) + LONGSIZE)	/* 11 */
-#define PT_R12		((PT_R11) + LONGSIZE)	/* 12 */
-#define PT_R13		((PT_R12) + LONGSIZE)	/* 13 */
-#define PT_R14		((PT_R13) + LONGSIZE)	/* 14 */
-#define PT_R15		((PT_R14) + LONGSIZE)	/* 15 */
-#define PT_R16		((PT_R15) + LONGSIZE)	/* 16 */
-#define PT_R17		((PT_R16) + LONGSIZE)	/* 17 */
-#define PT_R18		((PT_R17) + LONGSIZE)	/* 18 */
-#define PT_R19		((PT_R18) + LONGSIZE)	/* 19 */
-#define PT_R20		((PT_R19) + LONGSIZE)	/* 20 */
-#define PT_R21		((PT_R20) + LONGSIZE)	/* 21 */
-#define PT_R22		((PT_R21) + LONGSIZE)	/* 22 */
-#define PT_R23		((PT_R22) + LONGSIZE)	/* 23 */
-#define PT_R24		((PT_R23) + LONGSIZE)	/* 24 */
-#define PT_R25		((PT_R24) + LONGSIZE)	/* 25 */
-#define PT_R26		((PT_R25) + LONGSIZE)	/* 26 */
-#define PT_R27		((PT_R26) + LONGSIZE)	/* 27 */
-#define PT_R28		((PT_R27) + LONGSIZE)	/* 28 */
-#define PT_R29		((PT_R28) + LONGSIZE)	/* 29 */
-#define PT_R30		((PT_R29) + LONGSIZE)	/* 30 */
-#define PT_R31		((PT_R30) + LONGSIZE)	/* 31 */
-
-/*
- * Saved special registers
- */
-#define PT_STATUS	((PT_R31) + LONGSIZE)	/* 32 */
-#define PT_HI		((PT_STATUS) + LONGSIZE)	/* 33 */
-#define PT_LO		((PT_HI) + LONGSIZE)	/* 34 */
-#define PT_BADVADDR	((PT_LO) + LONGSIZE)	/* 35 */
-#define PT_CAUSE	((PT_BADVADDR) + LONGSIZE)	/* 36 */
-#define PT_EPC		((PT_CAUSE) + LONGSIZE)	/* 37 */
-
-#define PT_SIZE		((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
-
-
-		.macro	SAVE_AT
-		.set	push
-		.set	noat
-		LONG_S	$1, PT_R1(sp)
-		.set	pop
-		.endm
-
-		.macro	SAVE_TEMP
-		mfhi	v1
-		LONG_S	$8, PT_R8(sp)
-		LONG_S	$9, PT_R9(sp)
-		LONG_S	v1, PT_HI(sp)
-		mflo	v1
-		LONG_S	$10, PT_R10(sp)
-		LONG_S	$11, PT_R11(sp)
-		LONG_S	v1,  PT_LO(sp)
-		LONG_S	$12, PT_R12(sp)
-		LONG_S	$13, PT_R13(sp)
-		LONG_S	$14, PT_R14(sp)
-		LONG_S	$15, PT_R15(sp)
-		LONG_S	$24, PT_R24(sp)
-		.endm
-
-		.macro	SAVE_STATIC
-		LONG_S	$16, PT_R16(sp)
-		LONG_S	$17, PT_R17(sp)
-		LONG_S	$18, PT_R18(sp)
-		LONG_S	$19, PT_R19(sp)
-		LONG_S	$20, PT_R20(sp)
-		LONG_S	$21, PT_R21(sp)
-		LONG_S	$22, PT_R22(sp)
-		LONG_S	$23, PT_R23(sp)
-		LONG_S	$30, PT_R30(sp)
-		.endm
-
-		.macro	get_saved_sp
-		nop
-		.endm
-
-		.macro	SAVE_SOME
-		.set	push
-		.set	noat
-		.set	reorder
-        move	k1, sp
-8:		move	k0, sp
-		PTR_SUBU sp, k1, PT_SIZE
-		LONG_S	k0, PT_R29(sp)
-		LONG_S	$3, PT_R3(sp)
-		LONG_S	$0, PT_R0(sp)
-		mfc0	v1, CP0_STATUS
-		LONG_S	$2, PT_R2(sp)
-		LONG_S	v1, PT_STATUS(sp)
-		LONG_S	$4, PT_R4(sp)
-		mfc0	v1, CP0_CAUSE
-		LONG_S	$5, PT_R5(sp)
-		LONG_S	v1, PT_CAUSE(sp)
-		LONG_S	$6, PT_R6(sp)
-		MFC0	v1, CP0_EPC
-		LONG_S	$7, PT_R7(sp)
-		LONG_S	v1, PT_EPC(sp)
-		LONG_S	$25, PT_R25(sp)
-		LONG_S	$28, PT_R28(sp)
-		LONG_S	$31, PT_R31(sp)
-		.set	pop
-		.endm
-
-		.macro	SAVE_ALL
-		SAVE_SOME
-		SAVE_AT
-		SAVE_TEMP
-		SAVE_STATIC
-		.endm
-
-		.macro	RESTORE_AT
-		.set	push
-		.set	noat
-		LONG_L	$1,  PT_R1(sp)
-		.set	pop
-		.endm
-
-		.macro	RESTORE_TEMP
-		LONG_L	$24, PT_LO(sp)
-		LONG_L	$8, PT_R8(sp)
-		LONG_L	$9, PT_R9(sp)
-		mtlo	$24
-		LONG_L	$24, PT_HI(sp)
-		LONG_L	$10, PT_R10(sp)
-		LONG_L	$11, PT_R11(sp)
-		mthi	$24
-		LONG_L	$12, PT_R12(sp)
-		LONG_L	$13, PT_R13(sp)
-		LONG_L	$14, PT_R14(sp)
-		LONG_L	$15, PT_R15(sp)
-		LONG_L	$24, PT_R24(sp)
-		.endm
-
-		.macro	RESTORE_STATIC
-		LONG_L	$16, PT_R16(sp)
-		LONG_L	$17, PT_R17(sp)
-		LONG_L	$18, PT_R18(sp)
-		LONG_L	$19, PT_R19(sp)
-		LONG_L	$20, PT_R20(sp)
-		LONG_L	$21, PT_R21(sp)
-		LONG_L	$22, PT_R22(sp)
-		LONG_L	$23, PT_R23(sp)
-		LONG_L	$30, PT_R30(sp)
-		.endm
-
-		.macro	RESTORE_SOME
-		.set	push
-		.set	reorder
-		.set	noat
-		LONG_L	v0, PT_STATUS(sp)
-		mtc0	v0, CP0_STATUS
-		LONG_L	v1, PT_EPC(sp)
-		MTC0	v1, CP0_EPC
-		LONG_L	$31, PT_R31(sp)
-		LONG_L	$28, PT_R28(sp)
-		LONG_L	$25, PT_R25(sp)
-		LONG_L	$7,  PT_R7(sp)
-		LONG_L	$6,  PT_R6(sp)
-		LONG_L	$5,  PT_R5(sp)
-		LONG_L	$4,  PT_R4(sp)
-		LONG_L	$3,  PT_R3(sp)
-		LONG_L	$2,  PT_R2(sp)
-		.set	pop
-		.endm
-
-		.macro	RESTORE_SP_AND_RET
-		LONG_L	sp, PT_R29(sp)
-		.set	mips3
-		eret
-		.set	mips0
-		.endm
-
-
-		.macro	RESTORE_SP
-		LONG_L	sp, PT_R29(sp)
-		.endm
-
-		.macro	RESTORE_ALL
-		RESTORE_TEMP
-		RESTORE_STATIC
-		RESTORE_AT
-		RESTORE_SOME
-		RESTORE_SP
-		.endm
-
-		.macro	RESTORE_ALL_AND_RET
-		RESTORE_TEMP
-		RESTORE_STATIC
-		RESTORE_AT
-		RESTORE_SOME
-		RESTORE_SP_AND_RET
-		.endm
+#include "mips_regs.h"
+#include "ptrace.h"
+
+/* You MUST ensure FP is enabled before SAVE_FPU! */
+    .macro SAVE_FPU
+    .set push
+    .set noreorder
+#ifdef RT_USING_FPU
+    /* Ensure CU1 (FPU) is enabled */
+    MFC0 v1, CP0_STATUS
+    ori v1, ST0_CU1
+    MTC0 v1, CP0_STATUS
+    SSNOP
+    cfc1 v1, fcr31
+    /* Store as delay slot */
+    s.d $f0, PT_FPU_R0(sp)
+    s.d $f2, PT_FPU_R2(sp)
+    s.d $f4, PT_FPU_R4(sp)
+    s.d $f6, PT_FPU_R6(sp)
+    s.d $f8, PT_FPU_R8(sp)
+    s.d $f10, PT_FPU_R10(sp)
+    s.d $f12, PT_FPU_R12(sp)
+    s.d $f14, PT_FPU_R14(sp)
+    s.d $f16, PT_FPU_R16(sp)
+    s.d $f18, PT_FPU_R18(sp)
+    s.d $f20, PT_FPU_R20(sp)
+    s.d $f22, PT_FPU_R22(sp)
+    s.d $f24, PT_FPU_R24(sp)
+    s.d $f26, PT_FPU_R26(sp)
+    s.d $f28, PT_FPU_R28(sp)
+    s.d $f30, PT_FPU_R30(sp)
+    LONG_S v1, PT_FPU_FCSR31(sp)
+#endif
+    .set reorder
+    .set pop
+    .endm
+
+    .macro	SAVE_AT
+    .set	push
+    .set	noat
+    LONG_S	$1, PT_R1(sp)
+    .set	pop
+    .endm
+
+    .macro	SAVE_TEMP
+    mfhi	v1
+    LONG_S	$8, PT_R8(sp)
+    LONG_S	$9, PT_R9(sp)
+    LONG_S	v1, PT_HI(sp)
+    mflo	v1
+    LONG_S	$10, PT_R10(sp)
+    LONG_S	$11, PT_R11(sp)
+    LONG_S	v1,  PT_LO(sp)
+    LONG_S	$12, PT_R12(sp)
+    LONG_S	$13, PT_R13(sp)
+    LONG_S	$14, PT_R14(sp)
+    LONG_S	$15, PT_R15(sp)
+    LONG_S	$24, PT_R24(sp)
+    .endm
+
+    .macro	SAVE_STATIC
+    LONG_S	$16, PT_R16(sp)
+    LONG_S	$17, PT_R17(sp)
+    LONG_S	$18, PT_R18(sp)
+    LONG_S	$19, PT_R19(sp)
+    LONG_S	$20, PT_R20(sp)
+    LONG_S	$21, PT_R21(sp)
+    LONG_S	$22, PT_R22(sp)
+    LONG_S	$23, PT_R23(sp)
+    LONG_S	$30, PT_R30(sp)
+    .endm
+
+    .macro	SAVE_SOME
+    .set	push
+    .set	noat
+    .set	reorder
+    move	k1, sp
+    move	k0, sp
+    PTR_SUBU sp, k1, PT_SIZE
+    LONG_S	k0, PT_R29(sp)
+    LONG_S	$3, PT_R3(sp)
+    LONG_S	$0, PT_R0(sp)
+    MFC0	v1, CP0_STATUS
+    LONG_S	$2, PT_R2(sp)
+    LONG_S	v1, PT_STATUS(sp)
+    LONG_S	$4, PT_R4(sp)
+    MFC0	v1, CP0_CAUSE
+    LONG_S	$5, PT_R5(sp)
+    LONG_S	v1, PT_CAUSE(sp)
+    LONG_S	$6, PT_R6(sp)
+    MFC0	v1, CP0_EPC
+    LONG_S	$7, PT_R7(sp)
+    LONG_S	v1, PT_EPC(sp)
+    LONG_S	$25, PT_R25(sp)
+    LONG_S	$28, PT_R28(sp)
+    LONG_S	$31, PT_R31(sp)
+    .set	pop
+    .endm
+
+    .macro	SAVE_ALL
+    SAVE_SOME
+    SAVE_AT
+    SAVE_TEMP
+    SAVE_FPU
+    SAVE_STATIC
+    .endm
+
+    .macro RESTORE_FPU
+    .set push
+    .set noreorder
+#ifdef RT_USING_FPU
+    /* Ensure CU1 (FPU) is enabled */
+    MFC0 v1, CP0_STATUS
+    ori v1, ST0_CU1
+    MTC0 v1, CP0_STATUS
+    SSNOP
+    LONG_L v1, PT_FPU_FCSR31(sp)
+    ctc1 v1, fcsr31
+    l.d $f0, PT_FPU_R0(sp)
+    l.d $f2, PT_FPU_R2(sp)
+    l.d $f4, PT_FPU_R4(sp)
+    l.d $f6, PT_FPU_R6(sp)
+    l.d $f8, PT_FPU_R8(sp)
+    l.d $f10, PT_FPU_R10(sp)
+    l.d $f12, PT_FPU_R12(sp)
+    l.d $f14, PT_FPU_R14(sp)
+    l.d $f16, PT_FPU_R16(sp)
+    l.d $f18, PT_FPU_R18(sp)
+    l.d $f20, PT_FPU_R20(sp)
+    l.d $f22, PT_FPU_R22(sp)
+    l.d $f24, PT_FPU_R24(sp)
+    l.d $f26, PT_FPU_R26(sp)
+    l.d $f28, PT_FPU_R28(sp)
+    l.d $f30, PT_FPU_R30(sp)
+#endif
+    .set reorder
+    .set pop
+    .endm
+
+    .macro	RESTORE_AT
+    .set	push
+    .set	noat
+    LONG_L	$1,  PT_R1(sp)
+    .set	pop
+    .endm
+
+    .macro	RESTORE_TEMP
+    LONG_L	$24, PT_LO(sp)
+    LONG_L	$8, PT_R8(sp)
+    LONG_L	$9, PT_R9(sp)
+    mtlo	$24
+    LONG_L	$24, PT_HI(sp)
+    LONG_L	$10, PT_R10(sp)
+    LONG_L	$11, PT_R11(sp)
+    mthi	$24
+    LONG_L	$12, PT_R12(sp)
+    LONG_L	$13, PT_R13(sp)
+    LONG_L	$14, PT_R14(sp)
+    LONG_L	$15, PT_R15(sp)
+    LONG_L	$24, PT_R24(sp)
+    .endm
+
+    .macro	RESTORE_STATIC
+    LONG_L	$16, PT_R16(sp)
+    LONG_L	$17, PT_R17(sp)
+    LONG_L	$18, PT_R18(sp)
+    LONG_L	$19, PT_R19(sp)
+    LONG_L	$20, PT_R20(sp)
+    LONG_L	$21, PT_R21(sp)
+    LONG_L	$22, PT_R22(sp)
+    LONG_L	$23, PT_R23(sp)
+    LONG_L	$30, PT_R30(sp)
+    .endm
+
+#define STATMASK 0x1f
+
+    .macro	RESTORE_SOME
+    .set	push
+    .set	reorder
+    .set	noat
+    mfc0	a0, CP0_STATUS
+    ori	a0, STATMASK
+    xori	a0, STATMASK
+    mtc0	a0, CP0_STATUS
+    li	v1, (ST0_CU1 | ST0_FR | ST0_IM)
+    and	a0, v1, a0
+    LONG_L	v0, PT_STATUS(sp)
+    li	v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
+    and	v0, v1
+    or	v0, a0
+    mtc0	v0, CP0_STATUS
+    LONG_L	v1, PT_EPC(sp)
+    MTC0	v1, CP0_EPC
+    LONG_L	$31, PT_R31(sp)
+    LONG_L	$28, PT_R28(sp)
+    LONG_L	$25, PT_R25(sp)
+    LONG_L	$7,  PT_R7(sp)
+    LONG_L	$6,  PT_R6(sp)
+    LONG_L	$5,  PT_R5(sp)
+    LONG_L	$4,  PT_R4(sp)
+    LONG_L	$3,  PT_R3(sp)
+    LONG_L	$2,  PT_R2(sp)
+    .set	pop
+    .endm
+
+    .macro	RESTORE_SP_AND_RET
+    LONG_L	sp, PT_R29(sp)
+    eret
+    nop
+    .endm
+
+
+    .macro	RESTORE_SP
+    LONG_L	sp, PT_R29(sp)
+    .endm
+
+    .macro	RESTORE_ALL
+    RESTORE_TEMP
+    RESTORE_FPU
+    RESTORE_STATIC
+    RESTORE_AT
+    RESTORE_SOME
+    RESTORE_SP
+    .endm
+
+    .macro	RESTORE_ALL_AND_RET
+    RESTORE_TEMP
+    RESTORE_FPU
+    RESTORE_STATIC
+    RESTORE_AT
+    RESTORE_SOME
+    RESTORE_SP_AND_RET
+    .endm
 
 #endif /* end of __STACKFRAME_H__ */
 
-- 
cgit v1.3.1


From 9ef986929cb2c39485da89ec39ad80316a5a9965 Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Sat, 7 Dec 2019 00:55:46 +0800
Subject: [libcpu] mips: Merge loongson_1 into gs232

Previously Loongson 1B and Loongson 1C have their own libcpu
implemention, but they're almost identical. So we merge them
into gs232 and adapt to new common code.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 libcpu/mips/gs232/SConscript             |  14 +
 libcpu/mips/gs232/cache.c                | 231 ++++++++++++++
 libcpu/mips/gs232/cache.h                |  51 +++
 libcpu/mips/gs232/cache_gcc.S            | 218 +++++++++++++
 libcpu/mips/gs232/cpuinit_gcc.S          |  23 ++
 libcpu/mips/gs232/cpuport.c              |  72 +++++
 libcpu/mips/gs232/gs232.h                |  67 ++++
 libcpu/mips/gs232/interrupt.c            | 162 ++++++++++
 libcpu/mips/gs232/ls1b.h                 |  67 ++++
 libcpu/mips/gs232/ls1c.h                 |  81 +++++
 libcpu/mips/gs232/mipscfg.c              |  77 +++++
 libcpu/mips/gs232/timer.c                |  41 +++
 libcpu/mips/loongson_1b/SConscript       |  14 -
 libcpu/mips/loongson_1b/cache.c          | 230 --------------
 libcpu/mips/loongson_1b/cache.h          |  52 ---
 libcpu/mips/loongson_1b/cache_gcc.S      | 219 -------------
 libcpu/mips/loongson_1b/context_gcc.S    | 150 ---------
 libcpu/mips/loongson_1b/cpuport.c        | 124 --------
 libcpu/mips/loongson_1b/exception.c      |  91 ------
 libcpu/mips/loongson_1b/interrupt.c      | 188 -----------
 libcpu/mips/loongson_1b/ls1b.h           | 140 --------
 libcpu/mips/loongson_1b/mipscfg.c        |  82 -----
 libcpu/mips/loongson_1b/start_gcc.S      | 138 --------
 libcpu/mips/loongson_1c/SConscript       |  14 -
 libcpu/mips/loongson_1c/cache.c          | 233 --------------
 libcpu/mips/loongson_1c/cache.h          |  52 ---
 libcpu/mips/loongson_1c/cache_gcc.S      | 220 -------------
 libcpu/mips/loongson_1c/context_gcc.S    | 163 ----------
 libcpu/mips/loongson_1c/cpuport.c        | 166 ----------
 libcpu/mips/loongson_1c/exception.c      |  91 ------
 libcpu/mips/loongson_1c/interrupt.c      | 226 -------------
 libcpu/mips/loongson_1c/ls1c.h           | 155 ---------
 libcpu/mips/loongson_1c/mipscfg.c        |  82 -----
 libcpu/mips/loongson_1c/sdram_cfg.h      |  85 -----
 libcpu/mips/loongson_1c/stackframe_fpu.h |  98 ------
 libcpu/mips/loongson_1c/start_gcc.S      | 530 -------------------------------
 36 files changed, 1104 insertions(+), 3543 deletions(-)
 create mode 100644 libcpu/mips/gs232/SConscript
 create mode 100644 libcpu/mips/gs232/cache.c
 create mode 100644 libcpu/mips/gs232/cache.h
 create mode 100644 libcpu/mips/gs232/cache_gcc.S
 create mode 100644 libcpu/mips/gs232/cpuinit_gcc.S
 create mode 100644 libcpu/mips/gs232/cpuport.c
 create mode 100644 libcpu/mips/gs232/gs232.h
 create mode 100644 libcpu/mips/gs232/interrupt.c
 create mode 100644 libcpu/mips/gs232/ls1b.h
 create mode 100644 libcpu/mips/gs232/ls1c.h
 create mode 100644 libcpu/mips/gs232/mipscfg.c
 create mode 100644 libcpu/mips/gs232/timer.c
 delete mode 100644 libcpu/mips/loongson_1b/SConscript
 delete mode 100644 libcpu/mips/loongson_1b/cache.c
 delete mode 100644 libcpu/mips/loongson_1b/cache.h
 delete mode 100644 libcpu/mips/loongson_1b/cache_gcc.S
 delete mode 100644 libcpu/mips/loongson_1b/context_gcc.S
 delete mode 100644 libcpu/mips/loongson_1b/cpuport.c
 delete mode 100644 libcpu/mips/loongson_1b/exception.c
 delete mode 100644 libcpu/mips/loongson_1b/interrupt.c
 delete mode 100644 libcpu/mips/loongson_1b/ls1b.h
 delete mode 100644 libcpu/mips/loongson_1b/mipscfg.c
 delete mode 100644 libcpu/mips/loongson_1b/start_gcc.S
 delete mode 100644 libcpu/mips/loongson_1c/SConscript
 delete mode 100644 libcpu/mips/loongson_1c/cache.c
 delete mode 100644 libcpu/mips/loongson_1c/cache.h
 delete mode 100644 libcpu/mips/loongson_1c/cache_gcc.S
 delete mode 100644 libcpu/mips/loongson_1c/context_gcc.S
 delete mode 100644 libcpu/mips/loongson_1c/cpuport.c
 delete mode 100644 libcpu/mips/loongson_1c/exception.c
 delete mode 100644 libcpu/mips/loongson_1c/interrupt.c
 delete mode 100644 libcpu/mips/loongson_1c/ls1c.h
 delete mode 100644 libcpu/mips/loongson_1c/mipscfg.c
 delete mode 100644 libcpu/mips/loongson_1c/sdram_cfg.h
 delete mode 100644 libcpu/mips/loongson_1c/stackframe_fpu.h
 delete mode 100644 libcpu/mips/loongson_1c/start_gcc.S

(limited to 'libcpu')

diff --git a/libcpu/mips/gs232/SConscript b/libcpu/mips/gs232/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/gs232/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/gs232/cache.c b/libcpu/mips/gs232/cache.c
new file mode 100644
index 0000000000..484d3816f4
--- /dev/null
+++ b/libcpu/mips/gs232/cache.c
@@ -0,0 +1,231 @@
+/*
+ * Cache Ops For Loongson GS232
+ *
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-07-09     Bernard        first version
+ * 2011-08-08     lgnq             modified for LS1B
+ * 2015-07-08     chinesebear   modified for loongson 1c
+ */
+
+#include <rtthread.h>
+#include <mips.h>
+
+#define K0BASE			0x80000000
+#define PRID_LS1C		0x4220
+
+extern void Clear_TagLo (void);
+extern void Invalidate_Icache_Ls1c(unsigned int);
+extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
+extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
+extern void Writeback_Invalidate_Dcache(unsigned int);
+extern void enable_cpu_cache(void);
+
+typedef struct cacheinfo_t
+{
+    unsigned int	icache_size;
+    unsigned int	dcache_size;
+    unsigned int	icacheline_size;
+    unsigned int	dcacheline_size;
+} cacheinfo_t ;
+
+typedef struct cacheop_t
+{
+    void (*Clear_TagLo) (void);
+    void (*Invalidate_Icache) (unsigned int);
+    void (*Invalidate_Dcache_Fill) (unsigned int);
+    void (*Invalidate_Dcache_ClearTag) (unsigned int);
+    void (*Init_Cache)(void);
+} cacheop_t ;
+
+static cacheop_t cacheop, *pcacheop;
+static cacheinfo_t cacheinfo, *pcacheinfo;
+
+int identify_cpu(void)
+{
+    unsigned int cpu_id;
+
+    pcacheop = &cacheop;
+    pcacheinfo = &cacheinfo;
+
+    rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
+    cpu_id = read_c0_prid();
+    switch (cpu_id)
+    {
+    case PRID_LS1C:
+        rt_kprintf("CPU:Loongson 1C\n");
+        pcacheop->Clear_TagLo = Clear_TagLo;
+        pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
+        pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
+        pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
+        break;
+    default:
+        rt_kprintf("Unknown CPU type, system halted!\n");
+        while (1)
+        {
+            ;
+        }
+        break;
+    }
+
+    return 0;
+}
+
+void probe_cache(void)
+{
+    unsigned int config1 = read_c0_config1();
+    unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
+    unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
+
+    if ((icache_line_size = ((config1 >> 19) & 7)))
+        icache_line_size = 2 << icache_line_size;
+    else
+        icache_line_size = icache_line_size;
+    icache_sets = 64 << ((config1 >> 22) & 7);
+    icache_ways = 1 + ((config1 >> 16) & 7);
+    icache_size = icache_sets * icache_ways * icache_line_size;
+
+    if ((dcache_line_size = ((config1 >> 10) & 7)))
+        dcache_line_size = 2 << dcache_line_size;
+    else
+        dcache_line_size = dcache_line_size;
+    dcache_sets = 64 << ((config1 >> 13) & 7);
+    dcache_ways = 1 + ((config1 >> 7) & 7);
+    dcache_size = dcache_sets * dcache_ways * dcache_line_size;
+
+    rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
+    rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
+
+    pcacheinfo->icache_size = icache_size;
+    pcacheinfo->dcache_size = dcache_size;
+    pcacheinfo->icacheline_size = icache_line_size;
+    pcacheinfo->dcacheline_size = dcache_line_size;
+
+    return ;
+}
+
+void invalidate_writeback_dcache_all(void)
+{
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->dcache_size);
+
+    while (start < end)
+    {
+        Writeback_Invalidate_Dcache(start);  //hit writeback invalidate
+        start += pcacheinfo->dcacheline_size;
+    }
+}
+
+void invalidate_writeback_dcache(unsigned long addr, int size)
+{
+    unsigned long start, end;
+
+    start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
+    end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
+
+    while (start <end)
+    {
+        Writeback_Invalidate_Dcache(start);
+        start += pcacheinfo->dcacheline_size;
+    }
+}
+
+void invalidate_icache_all(void)
+{
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->icache_size);
+
+    while (start < end)
+    {
+        pcacheop->Invalidate_Icache(start);
+        start += pcacheinfo->icacheline_size;
+    }
+}
+
+void invalidate_dcache_all(void)
+{
+    unsigned int start = K0BASE;
+    unsigned int end  = (start + pcacheinfo->dcache_size);
+    while (start <end)
+    {
+        Invalidate_Dcache_Fill_Ls1c(start);
+        start += pcacheinfo->icacheline_size;
+    }
+}
+
+//with cache disabled
+void init_dcache(void)
+{
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->dcache_size);
+
+    while (start < end)
+    {
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
+    }
+
+}
+
+void rt_hw_cache_init(void)
+{
+    unsigned int start, end;
+
+    /* 1. identify cpu and probe cache */
+    identify_cpu();
+    probe_cache();
+
+    start = K0BASE;
+    end = (start + pcacheinfo->icache_size);
+
+    /*
+     *	2. clear CP0 taglo/taghi register;
+     */
+    pcacheop->Clear_TagLo();
+
+    /*
+     *	3. invalidate instruction cache;
+     */
+    while (start < end)
+    {
+        pcacheop->Invalidate_Icache(start); //index invalidate icache
+        start += pcacheinfo->icacheline_size;
+    }
+
+    /*
+     *	4. invalidate data cache;
+     */
+    start = K0BASE;
+    end = (start + pcacheinfo->dcache_size);
+    while(start < end)
+    {
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
+    }
+
+    start = K0BASE;
+    while(start < end)
+    {
+        pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
+        start += pcacheinfo->dcacheline_size;
+    }
+
+    start = K0BASE;
+    while(start < end)
+    {
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
+    }
+
+    /* enable cache */
+    enable_cpu_cache();
+    rt_kprintf("enable cpu cache done\n");
+
+    return ;
+}
+
+
diff --git a/libcpu/mips/gs232/cache.h b/libcpu/mips/gs232/cache.h
new file mode 100644
index 0000000000..381298e4df
--- /dev/null
+++ b/libcpu/mips/gs232/cache.h
@@ -0,0 +1,51 @@
+/*
+ * Cache Ops For Loongson GS232
+ * 
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-07-09     Bernard        first version
+ * 2011-08-08     lgnq             modified for LS1B
+ * 2015-07-08     chinesebear   modified for loongson 1c
+ */
+
+#ifndef	__CACHE_H__
+#define	__CACHE_H__
+/*
+ * Cache Operations
+ */
+#define Index_Invalidate_I      0x00
+#define Index_Writeback_Inv_D   0x01
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_I		0x04
+#define Index_Load_Tag_D		0x05
+#define Index_Load_Tag_SI		0x06
+#define Index_Load_Tag_SD		0x07
+#define Index_Store_Tag_I		0x08
+#define Index_Store_Tag_D		0x09
+#define Index_Store_Tag_SI		0x0A
+#define Index_Store_Tag_SD		0x0B
+#define Create_Dirty_Excl_D		0x0d
+#define Create_Dirty_Excl_SD	0x0f
+#define Hit_Invalidate_I		0x10
+#define Hit_Invalidate_D		0x11
+#define Hit_Invalidate_SI		0x12
+#define Hit_Invalidate_SD		0x13
+#define Fill					0x14
+#define Hit_Writeback_Inv_D		0x15
+/* 0x16 is unused */
+#define Hit_Writeback_Inv_SD	0x17
+#define Hit_Writeback_I			0x18
+#define Hit_Writeback_D			0x19
+/* 0x1a is unused */
+#define Hit_Writeback_SD		0x1b
+/* 0x1c is unused */
+/* 0x1e is unused */
+#define Hit_Set_Virtual_SI		0x1e
+#define Hit_Set_Virtual_SD		0x1f
+
+#endif
diff --git a/libcpu/mips/gs232/cache_gcc.S b/libcpu/mips/gs232/cache_gcc.S
new file mode 100644
index 0000000000..10a41652a3
--- /dev/null
+++ b/libcpu/mips/gs232/cache_gcc.S
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-17     swkyer       first version
+ * 2010-09-11     bernard      port to Loongson SoC3210
+ * 2011-08-08     lgnq         port to Loongson LS1B
+ * 2015-07-08     chinesebear  port to Loongson LS1C
+ * 2019-07-19     Zhou Yanjie  clean up code
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+#include "cache.h"
+
+    .ent	cache_init
+    .global cache_init
+    .set noreorder
+cache_init:
+        move t1,ra
+####part 2####
+cache_detect_4way:
+        mfc0    t4, CP0_CONFIG
+        andi    t5, t4, 0x0e00
+        srl     t5, t5, 9     #ic
+        andi    t6, t4, 0x01c0
+        srl     t6, t6, 6     #dc
+        addiu   t8, $0, 1
+        addiu   t9, $0, 2
+                                #set dcache way
+        beq     t6, $0,  cache_d1way
+        addiu   t7, $0, 1       #1 way
+        beq     t6, t8,  cache_d2way
+        addiu   t7, $0, 2       #2 way
+        beq     $0, $0, cache_d4way
+        addiu   t7, $0, 4       #4 way
+cache_d1way:
+        beq     $0, $0, 1f
+        addiu   t6, t6, 12      #1 way
+cache_d2way:
+        beq     $0, $0, 1f
+        addiu   t6, t6, 11      #2 way
+cache_d4way:
+        addiu   t6, t6, 10      #4 way (10), 2 way(11), 1 way(12)
+1:                              #set icache way
+        beq     t5, $0,  cache_i1way
+        addiu   t3, $0, 1       #1 way
+        beq     t5, t8,  cache_i2way
+        addiu   t3, $0, 2       #2 way
+        beq     $0, $0, cache_i4way
+        addiu   t3, $0, 4       #4 way
+cache_i1way:
+        beq     $0, $0, 1f
+        addiu   t5, t5, 12
+cache_i2way:
+        beq     $0, $0, 1f
+        addiu   t5, t5, 11
+cache_i4way:
+        addiu   t5, t5, 10      #4 way (10), 2 way(11), 1 way(12)
+
+1:      addiu   t4, $0, 1
+        sllv    t6, t4, t6
+        sllv    t5, t4, t5
+#if 0
+    la	t0, memvar
+    sw	t7, 0x0(t0) #ways
+    sw	t5, 0x4(t0) #icache size
+    sw	t6, 0x8(t0) #dcache size
+#endif
+####part 3####
+    .set	mips3
+    lui	a0, 0x8000
+    addu	a1, $0, t5
+    addu	a2, $0, t6
+cache_init_d2way:
+#a0=0x80000000, a1=icache_size, a2=dcache_size
+#a3, v0 and v1 used as local registers
+    mtc0	$0, CP0_TAGHI
+    addu	v0, $0, a0
+    addu	v1, a0, a2
+1:	slt	a3, v0, v1
+    beq	a3, $0, 1f
+    nop
+    mtc0	$0, CP0_TAGLO
+    beq	t7, 1, 4f
+    cache	Index_Store_Tag_D, 0x0(v0)	# 1 way
+    beq	t7, 2 ,4f
+    cache	Index_Store_Tag_D, 0x1(v0)	# 2 way
+    cache	Index_Store_Tag_D, 0x2(v0)	# 4 way
+    cache	Index_Store_Tag_D, 0x3(v0)
+4:	beq	$0, $0, 1b
+    addiu	v0, v0, 0x20
+1:
+cache_flush_i2way:
+    addu	v0, $0, a0
+    addu	v1, a0, a1
+1:	slt	a3, v0, v1
+    beq	a3, $0, 1f
+    nop
+    beq	t3, 1, 4f
+    cache	Index_Invalidate_I, 0x0(v0)	# 1 way
+    beq	t3, 2, 4f
+    cache	Index_Invalidate_I, 0x1(v0)	# 2 way
+    cache	Index_Invalidate_I, 0x2(v0)
+    cache	Index_Invalidate_I, 0x3(v0)	# 4 way
+4:	beq	$0, $0, 1b
+    addiu	v0, v0, 0x20
+1:
+cache_flush_d2way:
+    addu	v0, $0, a0
+    addu	v1, a0, a2
+1:	slt	a3, v0, v1
+    beq	a3, $0, 1f
+    nop
+    beq	t7, 1, 4f
+    cache	Index_Writeback_Inv_D, 0x0(v0) 	#1 way
+    beq	t7, 2, 4f
+    cache	Index_Writeback_Inv_D, 0x1(v0)	# 2 way
+    cache	Index_Writeback_Inv_D, 0x2(v0)
+    cache	Index_Writeback_Inv_D, 0x3(v0)	# 4 way
+4:	beq	$0, $0, 1b
+    addiu	v0, v0, 0x20
+1:
+cache_init_finish:
+    jr	t1
+    nop
+    .set reorder
+    .end cache_init
+
+###########################
+#  Enable CPU cache       #
+###########################
+
+LEAF(enable_cpu_cache)
+    .set noreorder
+    mfc0	t0, CP0_CONFIG
+    nop
+    and		t0, ~0x03
+    or		t0, 0x03
+    mtc0	t0, CP0_CONFIG
+    nop
+    .set reorder
+    j	ra
+END (enable_cpu_cache)
+    
+###########################
+#  disable CPU cache      #
+###########################
+
+LEAF(disable_cpu_cache)
+    .set noreorder
+    mfc0	t0, CP0_CONFIG
+    nop
+    and		t0, ~0x03
+    or 		t0, 0x2
+    mtc0	t0, CP0_CONFIG
+    nop
+    .set reorder
+    j	ra
+END (disable_cpu_cache)
+
+/**********************************/
+/* Invalidate Instruction Cache	  */
+/**********************************/
+LEAF(Clear_TagLo)
+    .set 	noreorder
+    mtc0	zero, CP0_TAGLO
+    nop
+    .set 	reorder
+    j		ra
+END(Clear_TagLo)
+
+    .set mips3
+/**********************************/
+/* Invalidate Instruction Cache	  */
+/**********************************/
+LEAF(Invalidate_Icache_Ls1c)
+    .set	noreorder
+    cache	Index_Invalidate_I,0(a0)
+    cache	Index_Invalidate_I,1(a0)
+    cache	Index_Invalidate_I,2(a0)
+    cache	Index_Invalidate_I,3(a0)
+    .set	reorder
+    j		ra
+END(Invalidate_Icache_Ls1c)
+
+/**********************************/
+/* Invalidate Data Cache		  */
+/**********************************/
+LEAF(Invalidate_Dcache_ClearTag_Ls1c)
+    .set	noreorder
+    cache	Index_Store_Tag_D, 0(a0)	# BDSLOT: clear tag
+    cache	Index_Store_Tag_D, 1(a0)	# BDSLOT: clear tag
+    .set	reorder
+    j		ra
+END(Invalidate_Dcache_ClearTag_Ls1c)
+
+LEAF(Invalidate_Dcache_Fill_Ls1c)
+    .set	noreorder
+    cache	Index_Writeback_Inv_D, 0(a0)	# BDSLOT: clear tag
+    cache	Index_Writeback_Inv_D, 1(a0)	# BDSLOT: clear tag
+    .set	reorder
+    j		ra
+END(Invalidate_Dcache_Fill_Ls1c)
+
+LEAF(Writeback_Invalidate_Dcache)
+    .set noreorder
+    cache	Hit_Writeback_Inv_D, (a0)
+    .set reorder
+    j	ra
+END(Writeback_Invalidate_Dcache)
+    .set mips0
diff --git a/libcpu/mips/gs232/cpuinit_gcc.S b/libcpu/mips/gs232/cpuinit_gcc.S
new file mode 100644
index 0000000000..3379d7dae4
--- /dev/null
+++ b/libcpu/mips/gs232/cpuinit_gcc.S
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+
+    .section ".start", "ax"
+    .set noreorder
+
+    .globl  rt_cpu_early_init
+rt_cpu_early_init:
+     jr	ra
+     nop
\ No newline at end of file
diff --git a/libcpu/mips/gs232/cpuport.c b/libcpu/mips/gs232/cpuport.c
new file mode 100644
index 0000000000..1b13719449
--- /dev/null
+++ b/libcpu/mips/gs232/cpuport.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * Change Logs:
+ * Date                Author         Notes
+ * 2010-07-09     Bernard        first version
+ * 2010-09-11     Bernard        add CPU reset implementation
+ * 2015-07-06     chinesebear  modified for loongson 1c
+ */
+
+#include <rtthread.h>
+#include "gs232.h"
+
+/**
+ * @addtogroup Loongson GS232
+ */
+
+/*@{*/
+
+/**
+ * this function will reset CPU
+ *
+ */
+void rt_hw_cpu_reset(void)
+{
+    /* open the watch-dog */
+    WDT_EN = 0x01; 		/* watch dog enable */
+    WDT_TIMER = 0x01;	/* watch dog will be timeout after 1 tick */
+    WDT_SET = 0x01;		/* watch dog start */
+
+    rt_kprintf("reboot system...\n");
+    while (1);
+}
+
+/**
+ * this function will shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    while (1);
+}
+
+
+#define Hit_Invalidate_I    0x10
+#define Hit_Invalidate_D    0x11
+#define CONFIG_SYS_CACHELINE_SIZE   32
+#define Hit_Writeback_Inv_D 0x15
+
+
+void flush_cache(unsigned long start_addr, unsigned long size)
+{
+    unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+    unsigned long addr = start_addr & ~(lsize - 1);
+    unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+    while (1) {
+        cache_op(Hit_Writeback_Inv_D, addr);
+        cache_op(Hit_Invalidate_I, addr);
+        if (addr == aend)
+            break;
+        addr += lsize;
+    }
+}
+
+
+/*@}*/
+
diff --git a/libcpu/mips/gs232/gs232.h b/libcpu/mips/gs232/gs232.h
new file mode 100644
index 0000000000..6e90f7ba66
--- /dev/null
+++ b/libcpu/mips/gs232/gs232.h
@@ -0,0 +1,67 @@
+/*
+ * Misc define for GS232
+ * 
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __GS232_H__
+#define __GS232_H__
+
+#include <mips.h>
+
+#define INTC_BASE			0xBFD01040
+
+#define GS232_INTC_CELLS		5
+#define GS232_NR_IRQS			(32 * GS232_INTC_CELLS)
+
+#define GMAC0_BASE			0xBFE10000
+#define GMAC0_DMA_BASE		0xBFE11000
+#define GMAC1_BASE			0xBFE20000
+#define GMAC1_DMA_BASE		0xBFE21000
+#define I2C0_BASE			0xBFE58000
+#define PWM0_BASE			0xBFE5C000
+#define PWM1_BASE			0xBFE5C010
+#define PWM2_BASE			0xBFE5C020
+#define PWM3_BASE			0xBFE5C030
+#define WDT_BASE			0xBFE5C060
+#define RTC_BASE			0xBFE64000
+#define I2C1_BASE			0xBFE68000
+#define I2C2_BASE			0xBFE70000
+#define AC97_BASE			0xBFE74000
+#define NAND_BASE			0xBFE78000
+#define SPI_BASE			0xBFE80000
+#define CAN1_BASE			0xBF004300
+#define CAN0_BASE			0xBF004400
+
+#ifndef __ASSEMBLY__
+#include <rthw.h>
+
+/* Watch Dog registers */
+#define WDT_EN				HWREG32(WDT_BASE + 0x00)
+#define WDT_SET				HWREG32(WDT_BASE + 0x04)
+#define WDT_TIMER			HWREG32(WDT_BASE + 0x08)
+
+#define PLL_FREQ 			HWREG32(0xbfe78030)
+#define PLL_DIV_PARAM 		HWREG32(0xbfe78034)
+
+struct gs232_intc_regs
+{
+    volatile unsigned int int_isr;
+    volatile unsigned int int_en;
+    volatile unsigned int int_set;
+    volatile unsigned int int_clr;        /* offset 0x10*/
+    volatile unsigned int int_pol;
+    volatile unsigned int int_edge;        /* offset 0 */
+}; 
+
+extern void rt_hw_timer_init(void);
+
+#endif
+
+#endif
\ No newline at end of file
diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c
new file mode 100644
index 0000000000..f3e0f80763
--- /dev/null
+++ b/libcpu/mips/gs232/interrupt.c
@@ -0,0 +1,162 @@
+/*
+ * Interrupt handle for GS232
+ * 
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-10-15     Bernard      first version
+ * 2010-10-15     lgnq           modified for LS1B
+ * 2013-03-29     aozima       Modify the interrupt interface implementations.
+ * 2015-07-06     chinesebear modified for loongson 1c
+ * 2019-12-04     Jiaxun Yang   Generialize
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include "gs232.h"
+
+
+#define MAX_INTR            (GS232_NR_IRQS)
+
+static struct rt_irq_desc irq_handle_table[MAX_INTR];
+void rt_interrupt_dispatch(void *ptreg);
+void rt_hw_timer_handler();
+
+static struct gs232_intc_regs volatile *gs232_hw0_icregs
+= (struct gs232_intc_regs volatile *)(INTC_BASE);
+
+/**
+ * @addtogroup Loongson GS232
+ */
+
+/*@{*/
+
+static void rt_hw_interrupt_handler(int vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_int32_t idx;
+    rt_int32_t i;
+    rt_uint32_t c0_status = 0;
+
+    for (i=0; i < GS232_INTC_CELLS; i++)
+    {
+        /* Disable */
+        (gs232_hw0_icregs+i)->int_en = 0x0;
+        /* Trigger active low */
+        (gs232_hw0_icregs+i)->int_pol = -1;	   /* Must be done here */
+        /* Make all interrupts level triggered */
+        (gs232_hw0_icregs+i)->int_edge = 0x00000000;
+        /* Mask all interrupts */
+        (gs232_hw0_icregs+i)->int_clr = 0xffffffff;
+        mips_unmask_cpu_irq(i + 2);
+    }
+
+    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
+    for (idx = 0; idx < MAX_INTR; idx ++)
+    {
+        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
+    }
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    /* mask interrupt */
+    (gs232_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    (gs232_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                         void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector >= 0 && vector < MAX_INTR)
+    {
+        old_handler = irq_handle_table[vector].handler;
+
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+        irq_handle_table[vector].handler = handler;
+        irq_handle_table[vector].param = param;
+    }
+
+    return old_handler;
+}
+
+
+/**
+ * ִ Call ISR
+ * @IRQn ID of IRQ
+ */
+void gs232_do_IRQ(int IRQn)
+{
+    rt_isr_handler_t irq_func;
+    void *param;
+
+    irq_func = irq_handle_table[IRQn].handler;
+    param    = irq_handle_table[IRQn].param;
+
+    irq_func(IRQn, param);
+
+#ifdef RT_USING_INTERRUPT_INFO
+    irq_handle_table[IRQn].counter++;
+#endif
+
+    return ;
+}
+
+
+void rt_do_mips_cpu_irq(rt_uint32_t ip)
+{
+    rt_uint32_t intstatus, irq, n;
+
+    if (ip == 7) {
+        rt_hw_timer_handler();
+    } else {
+        n = ip - 2;
+        /* Receive interrupt signal, compute the irq */
+        intstatus = (gs232_hw0_icregs+n)->int_isr & (gs232_hw0_icregs+n)->int_en;
+        if (0 == intstatus)
+            return ;
+
+        irq = __rt_ffs(intstatus) - 1;
+        gs232_do_IRQ((n<<5) + irq);
+
+        /* ack interrupt */
+        (gs232_hw0_icregs+n)->int_clr |= (1 << irq);
+    }
+}
+
+
+/*@}*/
+
+
diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h
new file mode 100644
index 0000000000..071a4aeb82
--- /dev/null
+++ b/libcpu/mips/gs232/ls1b.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-08-08     lgnq         first version
+ */
+
+#ifndef __LS1B_H__
+#define __LS1B_H__
+
+#include <gs232.h>
+
+#define LS1B_ACPI_IRQ	0
+#define LS1B_HPET_IRQ	1
+#define LS1B_UART0_IRQ	2
+#define LS1B_UART1_IRQ	3
+#define LS1B_UART2_IRQ	4
+#define LS1B_UART3_IRQ	5
+#define LS1B_CAN0_IRQ	6
+#define LS1B_CAN1_IRQ	7
+#define LS1B_SPI0_IRQ	8
+#define LS1B_SPI1_IRQ	9
+#define LS1B_AC97_IRQ	10
+#define LS1B_MS_IRQ		11
+#define LS1B_KB_IRQ		12
+#define LS1B_DMA0_IRQ	13
+#define LS1B_DMA1_IRQ	14
+#define LS1B_NAND_IRQ	15
+#define LS1B_I2C0_IRQ	16
+#define LS1B_I2C1_IRQ	17
+#define LS1B_PWM0_IRQ	18
+#define LS1B_PWM1_IRQ	19
+#define LS1B_PWM2_IRQ	20
+#define LS1B_PWM3_IRQ	21
+#define LS1B_LPC_IRQ	22
+#define LS1B_EHCI_IRQ	32
+#define LS1B_OHCI_IRQ	33
+#define LS1B_GMAC1_IRQ	34
+#define LS1B_GMAC2_IRQ	35
+#define LS1B_SATA_IRQ	36
+#define LS1B_GPU_IRQ	37
+#define LS1B_PCI_INTA_IRQ 38
+#define LS1B_PCI_INTB_IRQ 39
+#define LS1B_PCI_INTC_IRQ 40
+#define LS1B_PCI_INTD_IRQ 41
+
+#define LS1B_GPIO_IRQ 64
+#define LS1B_GPIO_FIRST_IRQ 64
+#define LS1B_GPIO_IRQ_COUNT 96
+#define LS1B_GPIO_LAST_IRQ  (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
+
+#define INT_PCI_INTA	(1<<6)
+#define INT_PCI_INTB	(1<<7)
+#define INT_PCI_INTC	(1<<8)
+#define INT_PCI_INTD	(1<<9)
+
+#define LS1B_LAST_IRQ 159
+#define MIPS_CPU_TIMER_IRQ	167
+#define LS1B_INTREG_BASE 0xbfd01040
+
+#define LS1B_DMA_IRQ_BASE 168
+#define LS1B_DMA_IRQ_COUNT 16
+
+#endif
diff --git a/libcpu/mips/gs232/ls1c.h b/libcpu/mips/gs232/ls1c.h
new file mode 100644
index 0000000000..54c7e36e99
--- /dev/null
+++ b/libcpu/mips/gs232/ls1c.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date               Author             Notes
+ * 2011-08-08     lgnq                first version
+ * 2015-07-06     chinesebear      modified for loongson 1c
+ */
+
+#ifndef __LS1C_H__
+#define __LS1C_H__
+
+#include <gs232.h>
+
+#define LS1C_ACPI_IRQ    0
+#define LS1C_HPET_IRQ    1
+//#define LS1C_UART0_IRQ    3  // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ��
+#define LS1C_UART1_IRQ   4
+#define LS1C_UART2_IRQ   5
+#define LS1C_CAN0_IRQ    6
+#define LS1C_CAN1_IRQ    7
+#define LS1C_SPI0_IRQ    8
+#define LS1C_SPI1_IRQ    9
+#define LS1C_AC97_IRQ    10
+#define LS1C_MS_IRQ      11
+#define LS1C_KB_IRQ      12
+#define LS1C_DMA0_IRQ    13
+#define LS1C_DMA1_IRQ    14
+#define LS1C_DMA2_IRQ    15
+#define LS1C_NAND_IRQ    16
+#define LS1C_PWM0_IRQ    17
+#define LS1C_PWM1_IRQ    18
+#define LS1C_PWM2_IRQ    19
+#define LS1C_PWM3_IRQ    20
+#define LS1C_RTC_INT0_IRQ  21
+#define LS1C_RTC_INT1_IRQ  22
+#define LS1C_RTC_INT2_IRQ  23
+#define LS1C_UART3_IRQ   29
+#define LS1C_ADC_IRQ     30
+#define LS1C_SDIO_IRQ    31
+
+
+#define LS1C_EHCI_IRQ   (32+0)
+#define LS1C_OHCI_IRQ   (32+1)
+#define LS1C_OTG_IRQ    (32+2)
+#define LS1C_MAC_IRQ    (32+3)
+#define LS1C_CAM_IRQ    (32+4)
+#define LS1C_UART4_IRQ  (32+5)
+#define LS1C_UART5_IRQ  (32+6)
+#define LS1C_UART6_IRQ  (32+7)
+#define LS1C_UART7_IRQ  (32+8)
+#define LS1C_UART8_IRQ  (32+9)
+#define LS1C_UART9_IRQ  (32+13)
+#define LS1C_UART10_IRQ (32+14)
+#define LS1C_UART11_IRQ (32+15)
+#define LS1C_I2C2_IRQ   (32+17)
+#define LS1C_I2C1_IRQ   (32+18)
+#define LS1C_I2C0_IRQ   (32+19)
+
+
+#define LS1C_GPIO_IRQ       64
+#define LS1C_GPIO_FIRST_IRQ 64
+#define LS1C_GPIO_IRQ_COUNT 96
+#define LS1C_GPIO_LAST_IRQ  (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
+
+
+#define LS1C_LAST_IRQ 159
+#define LS1C_INTREG_BASE 0xbfd01040
+
+// ��о1c���жϷ�Ϊ���飬ÿ��32��
+#define LS1C_NR_IRQS    (32*5)
+
+
+// GPIO��ź��жϺ�֮��Ļ���ת��
+#define LS1C_GPIO_TO_IRQ(GPIOn)     (LS1C_GPIO_FIRST_IRQ + (GPIOn))
+#define LS1C_IRQ_TO_GPIO(IRQn)      ((IRQn) - LS1C_GPIO_FIRST_IRQ)
+
+#endif
+
diff --git a/libcpu/mips/gs232/mipscfg.c b/libcpu/mips/gs232/mipscfg.c
new file mode 100644
index 0000000000..85e0e633ea
--- /dev/null
+++ b/libcpu/mips/gs232/mipscfg.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-27     swkyer       first version
+ */
+#include <rtthread.h>
+#include <mips.h>
+
+mips32_core_cfg_t g_mips_core =
+{
+    16,		/* icache_line_size */
+    256,	/* icache_lines_per_way */
+    4,		/* icache_ways */
+    16,		/* dcache_line_size */
+    256,	/* dcache_lines_per_way */
+    4,		/* dcache_ways */
+    16,		/* max_tlb_entries */
+};
+
+static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
+{
+    rt_uint16_t rets = 1;
+
+    while (n--)
+        rets *= b;
+
+    return rets;
+}
+
+static rt_uint16_t m_log2(rt_uint16_t b)
+{
+    rt_uint16_t rets = 0;
+
+    while (b != 1)
+    {
+        b /= 2;
+        rets++;
+    }
+
+    return rets;
+}
+
+/**
+ * read core attribute
+ */
+void mips32_cfg_init(void)
+{
+    rt_uint16_t val;
+    rt_uint32_t cp0_config1;
+
+    cp0_config1 = read_c0_config();
+    if (cp0_config1 & 0x80000000)
+    {
+        cp0_config1 = read_c0_config1();
+
+        val = (cp0_config1 & (7<<22))>>22;
+        g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
+        val = (cp0_config1 & (7<<19))>>19;
+        g_mips_core.icache_line_size = 2 * m_pow(2, val);
+        val = (cp0_config1 & (7<<16))>>16;
+        g_mips_core.icache_ways = val + 1;
+
+        val = (cp0_config1 & (7<<13))>>13;
+        g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
+        val = (cp0_config1 & (7<<10))>>10;
+        g_mips_core.dcache_line_size = 2 * m_pow(2, val);
+        val = (cp0_config1 & (7<<7))>>7;
+        g_mips_core.dcache_ways = val + 1;
+
+        val = (cp0_config1 & (0x3F<<25))>>25;
+        g_mips_core.max_tlb_entries = val + 1;
+    }
+}
diff --git a/libcpu/mips/gs232/timer.c b/libcpu/mips/gs232/timer.c
new file mode 100644
index 0000000000..8879b82ccf
--- /dev/null
+++ b/libcpu/mips/gs232/timer.c
@@ -0,0 +1,41 @@
+/*
+ * Assembly Macros For MIPS
+ *
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <mips.h>
+#include <board.h>
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void rt_hw_timer_handler(void)
+{
+	unsigned int count;
+
+	count = read_c0_compare();
+	write_c0_compare(count);
+	write_c0_count(0);
+
+	/* increase a OS tick */
+	rt_tick_increase();
+}
+
+/**
+ * This function will initial OS timer
+ */
+void rt_hw_timer_init(void)
+{
+	write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
+	write_c0_count(0);
+	mips_unmask_cpu_irq(7);
+}
\ No newline at end of file
diff --git a/libcpu/mips/loongson_1b/SConscript b/libcpu/mips/loongson_1b/SConscript
deleted file mode 100644
index b0ae20ba02..0000000000
--- a/libcpu/mips/loongson_1b/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ''
-
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')
diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c
deleted file mode 100644
index 842f392cb7..0000000000
--- a/libcpu/mips/loongson_1b/cache.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * File      : cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2011-08-08     lgnq         modified for LS1B
- */
- 
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-
-#define K0BASE			0x80000000
-#define PRID_LS1B		0x4220
-
-extern void Clear_TagLo (void);
-extern void Invalidate_Icache_Ls1b(unsigned int);
-extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
-extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
-extern void Writeback_Invalidate_Dcache(unsigned int);
-extern void enable_cpu_cache(void);
-
-typedef struct cacheinfo_t 
-{
-	unsigned int	icache_size;
-	unsigned int	dcache_size;
-	unsigned int	icacheline_size;
-	unsigned int	dcacheline_size;
-} cacheinfo_t ;
-
-typedef struct cacheop_t 
-{
-	void (*Clear_TagLo) (void);
-	void (*Invalidate_Icache) (unsigned int);
-	void (*Invalidate_Dcache_Fill) (unsigned int);
-	void (*Invalidate_Dcache_ClearTag) (unsigned int);
-	void (*Init_Cache)(void);
-} cacheop_t ;
-
-static cacheop_t cacheop, *pcacheop;
-static cacheinfo_t cacheinfo, *pcacheinfo;
-
-int identify_cpu(void)
-{
-    unsigned int cpu_id;
-
-    pcacheop = &cacheop;
-    pcacheinfo = &cacheinfo;
-
-	rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
-    cpu_id = read_c0_prid();
-    switch (cpu_id)
-	{
-	case PRID_LS1B:       
-	    rt_kprintf("CPU:LS1B\n");
-	    pcacheop->Clear_TagLo = Clear_TagLo;
-	    pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b;
-	    pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b;
-	    pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b;
-	    break;
-	default:
-	    rt_kprintf("Unknown CPU type, system halted!\n");
-	    while (1) 
-	    {
-	    	;
-	    }
-	    break;
-    }
-
-    return 0;
-}
-
-void probe_cache(void)
-{
-    unsigned int config1 = read_c0_config1();
-    unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
-    unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
-
-    if ((icache_line_size = ((config1 >> 19) & 7)))
-        icache_line_size = 2 << icache_line_size;
-    else
-        icache_line_size = icache_line_size;
-    icache_sets = 64 << ((config1 >> 22) & 7);
-    icache_ways = 1 + ((config1 >> 16) & 7);
-    icache_size = icache_sets * icache_ways * icache_line_size;
-    
-    if ((dcache_line_size = ((config1 >> 10) & 7)))
-        dcache_line_size = 2 << dcache_line_size;
-    else
-        dcache_line_size = dcache_line_size;
-    dcache_sets = 64 << ((config1 >> 13) & 7);
-    dcache_ways = 1 + ((config1 >> 7) & 7);
-    dcache_size = dcache_sets * dcache_ways * dcache_line_size;
-    
-    rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
-    rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
-
-    pcacheinfo->icache_size = icache_size;
-    pcacheinfo->dcache_size = dcache_size;
-    pcacheinfo->icacheline_size = icache_line_size;
-    pcacheinfo->dcacheline_size = dcache_line_size;
-
-    return ;
-}
-
-void invalidate_writeback_dcache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while (start < end) 
-	{
-		Writeback_Invalidate_Dcache(start);  //hit writeback invalidate 
-		start += pcacheinfo->dcacheline_size;
-	}
-}
-
-void invalidate_writeback_dcache(unsigned long addr, int size)
-{
-	unsigned long start, end;
-			
-	start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
-	end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-	
-	while (start <end)
-	{
-		Writeback_Invalidate_Dcache(start);
-		start += pcacheinfo->dcacheline_size;
-	}		
-}
-
-void invalidate_icache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->icache_size);
-
-	while (start < end) 
-	{
-		pcacheop->Invalidate_Icache(start); 
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-void invalidate_dcache_all(void)
-{ 
-	unsigned int start = K0BASE;
-	unsigned int end  = (start + pcacheinfo->dcache_size);
-	while (start <end)
-	{
-		Invalidate_Dcache_Fill_Ls1b(start);
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-//with cache disabled
-void init_dcache(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while (start < end)
-	{
-		pcacheop->Invalidate_Dcache_ClearTag(start);
-		start += pcacheinfo->dcacheline_size;
-	}
-
-}
-
-void rt_hw_cache_init(void)
-{
-    unsigned int start, end;
-	
-	/* 1. identify cpu and probe cache */
-	identify_cpu();
-	probe_cache();
-
-	start = K0BASE;
-	end = (start + pcacheinfo->icache_size);
-
-    /*
-     *	2. clear CP0 taglo/taghi register;
-     */
-    pcacheop->Clear_TagLo();
-
-	/*
-     *	3. invalidate instruction cache;
-     */
-    while (start < end) 
-    {
-		pcacheop->Invalidate_Icache(start); //index invalidate icache 
-		start += pcacheinfo->icacheline_size;
-    }
-
-    /*
-     *	4. invalidate data cache;
-     */
-    start = K0BASE;
-    end = (start + pcacheinfo->dcache_size);
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-	/* enable cache */
-	enable_cpu_cache();
-	rt_kprintf("enable cpu cache done\n");
-
-	return ;
-}
diff --git a/libcpu/mips/loongson_1b/cache.h b/libcpu/mips/loongson_1b/cache.h
deleted file mode 100644
index b5c2d4501e..0000000000
--- a/libcpu/mips/loongson_1b/cache.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * File      : cache.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2011-08-08     lgnq         modified for LS1B
- */
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-#endif
diff --git a/libcpu/mips/loongson_1b/cache_gcc.S b/libcpu/mips/loongson_1b/cache_gcc.S
deleted file mode 100644
index 1e718c9883..0000000000
--- a/libcpu/mips/loongson_1b/cache_gcc.S
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- * 2011-08-08     lgnq         port to Loongson LS1B
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mipsregs.h"
-#include "../common/mips_def.h"
-#include "../common/asm.h"
-#include "cache.h"
-
-	.ent	cache_init
-    .global cache_init
-    .set noreorder
-cache_init:
-        move t1,ra
-####part 2####
-cache_detect_4way:
-        mfc0    t4, CP0_CONFIG
-        andi    t5, t4, 0x0e00
-        srl     t5, t5, 9     #ic
-        andi    t6, t4, 0x01c0
-        srl     t6, t6, 6     #dc
-        addiu   t8, $0, 1
-        addiu   t9, $0, 2
-                                #set dcache way
-        beq     t6, $0,  cache_d1way
-        addiu   t7, $0, 1       #1 way
-        beq     t6, t8,  cache_d2way
-        addiu   t7, $0, 2       #2 way
-        beq     $0, $0, cache_d4way
-        addiu   t7, $0, 4       #4 way
-cache_d1way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 12      #1 way
-cache_d2way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 11      #2 way
-cache_d4way:
-        addiu   t6, t6, 10      #4 way (10), 2 way(11), 1 way(12)
-1:                              #set icache way
-        beq     t5, $0,  cache_i1way
-        addiu   t3, $0, 1       #1 way
-        beq     t5, t8,  cache_i2way
-        addiu   t3, $0, 2       #2 way
-        beq     $0, $0, cache_i4way
-        addiu   t3, $0, 4       #4 way
-cache_i1way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 12
-cache_i2way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 11
-cache_i4way:
-        addiu   t5, t5, 10      #4 way (10), 2 way(11), 1 way(12)
-
-1:      addiu   t4, $0, 1
-        sllv    t6, t4, t6
-        sllv    t5, t4, t5
-#if 0
-    la	t0, memvar
-	sw	t7, 0x0(t0) #ways
-	sw	t5, 0x4(t0) #icache size
-	sw	t6, 0x8(t0) #dcache size
-#endif
-####part 3####
-	.set	mips3
-	lui	a0, 0x8000
-	addu	a1, $0, t5
-	addu	a2, $0, t6
-cache_init_d2way:
-#a0=0x80000000, a1=icache_size, a2=dcache_size
-#a3, v0 and v1 used as local registers
-	mtc0	$0, CP0_TAGHI
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	mtc0	$0, CP0_TAGLO
-	beq	t7, 1, 4f
-	cache	Index_Store_Tag_D, 0x0(v0)	# 1 way
-	beq	t7, 2 ,4f
-	cache	Index_Store_Tag_D, 0x1(v0)	# 2 way
-	cache	Index_Store_Tag_D, 0x2(v0)	# 4 way
-	cache	Index_Store_Tag_D, 0x3(v0)
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_i2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a1
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t3, 1, 4f
-	cache	Index_Invalidate_I, 0x0(v0)	# 1 way
-	beq	t3, 2, 4f
-	cache	Index_Invalidate_I, 0x1(v0)	# 2 way
-	cache	Index_Invalidate_I, 0x2(v0)
-	cache	Index_Invalidate_I, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_d2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t7, 1, 4f
-	cache	Index_Writeback_Inv_D, 0x0(v0) 	#1 way
-	beq	t7, 2, 4f
-	cache	Index_Writeback_Inv_D, 0x1(v0)	# 2 way
-	cache	Index_Writeback_Inv_D, 0x2(v0)
-	cache	Index_Writeback_Inv_D, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_init_finish:
-	jr	t1
-    nop
-    .set reorder
-	.end cache_init
-
-###########################
-#  Enable CPU cache       #
-###########################
-
-LEAF(enable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or		t0, 0x03
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (enable_cpu_cache)
-    
-###########################
-#  disable CPU cache      #
-###########################
-
-LEAF(disable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or 		t0, 0x2
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (disable_cpu_cache)
-
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Clear_TagLo)
-	.set 	noreorder
-	mtc0	zero, CP0_TAGLO
-	nop
-	.set 	reorder
-	j		ra
-END(Clear_TagLo)
-
-    .set mips3
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Invalidate_Icache_Ls1b)
-	.set	noreorder
-	cache	Index_Invalidate_I,0(a0)
-	cache	Index_Invalidate_I,1(a0)
-	cache	Index_Invalidate_I,2(a0)
-	cache	Index_Invalidate_I,3(a0)
-	.set	reorder
-	j		ra
-END(Invalidate_Icache_Ls1b)
-
-/**********************************/
-/* Invalidate Data Cache		  */
-/**********************************/
-LEAF(Invalidate_Dcache_ClearTag_Ls1b)
-	.set	noreorder
-	cache	Index_Store_Tag_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Store_Tag_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_ClearTag_Ls1b)
-
-LEAF(Invalidate_Dcache_Fill_Ls1b)
-	.set	noreorder
-	cache	Index_Writeback_Inv_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Writeback_Inv_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_Fill_Ls1b)
-
-LEAF(Writeback_Invalidate_Dcache)
-	.set noreorder
-	cache	Hit_Writeback_Inv_D, (a0)
-	.set reorder
-	j	ra
-END(Writeback_Invalidate_Dcache)
-    .set mips0
diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S
deleted file mode 100644
index bed2c13252..0000000000
--- a/libcpu/mips/loongson_1b/context_gcc.S
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- * 2011-08-08     lgnq         port to Loongson LS1B
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-
-    .section ".text", "ax"
-    .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    mtc0    a0, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-    .globl rt_hw_context_switch
-rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
-    SAVE_ALL
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-    .globl rt_thread_switch_interrupt_flag
-    .globl rt_interrupt_from_thread
-    .globl rt_interrupt_to_thread
-    .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
-    .globl rt_interrupt_enter
-    .globl rt_interrupt_leave
-    .globl mips_irq_handle
-mips_irq_handle:
-    SAVE_ALL
-
-    mfc0    t0, CP0_CAUSE
-    and     t1, t0, 0xff
-	bnez	t1, spurious_interrupt		/* check exception */
-	nop
-
-	/* let k0 keep the current context sp */
-    move    k0, sp 
-    /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
-
-    jal     rt_interrupt_enter
-    nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-	nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-
-spurious_interrupt:
-    RESTORE_ALL_AND_RET
-
-    .set reorder
diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c
deleted file mode 100644
index c095c04814..0000000000
--- a/libcpu/mips/loongson_1b/cpuport.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * File      : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2010-09-11     Bernard      add CPU reset implementation
- */
-
-#include <rtthread.h>
-#include "ls1b.h"
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset(void)
-{
-	/* open the watch-dog */
-	WDT_EN = 0x01; 		/* watch dog enable */
-	WDT_TIMER = 0x01;	/* watch dog will be timeout after 1 tick */
-	WDT_SET = 0x01;		/* watch dog start */
-
-	rt_kprintf("reboot system...\n");
-	while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown(void)
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-	rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-
-    if (g_sr == 0)
-    {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x8401;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) 0x0000001c;	/* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-/*@}*/
-
diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c
deleted file mode 100644
index 4a3745cbc5..0000000000
--- a/libcpu/mips/loongson_1b/exception.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Loongson
- */
-
-/*@{*/
-
-/**
- * exception handle table
- */
-#define RT_EXCEPTION_MAX	8
-exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-	rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
-}
-
-void install_default_execpt_handle(void)
-{
-	rt_int32_t i;
-
-	for (i=0; i<RT_EXCEPTION_MAX; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-void exception_handler(pt_regs_t *regs)
-{
-	rt_uint32_t cause;
-	rt_uint32_t index;
-
-	cause = (read_c0_cause() & read_c0_config());
-	cause = (cause & 0xfc00) >> 8;
-
-	for (index = RT_EXCEPTION_MAX; index > 0; index --)
-	{
-		if (cause & (1 << index))
-		{
-			sys_exception_handlers[index](regs);
-			cause &= ~(1 << index);
-		}
-	}
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c
deleted file mode 100644
index 998d1e4918..0000000000
--- a/libcpu/mips/loongson_1b/interrupt.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-10-15     Bernard      first version
- * 2010-10-15     lgnq         modified for LS1B
- * 2013-03-29     aozima       Modify the interrupt interface implementations.
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include "ls1b.h"
-
-#define MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc irq_handle_table[MAX_INTR];
-void rt_interrupt_dispatch(void *ptreg);
-void rt_hw_timer_handler();
-
-static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
-= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-static void rt_hw_interrupt_handler(int vector, void *param)
-{
-    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    rt_int32_t idx;
-
-    /* pci active low */
-    ls1b_hw0_icregs->int_pol = -1;	   //must be done here 20110802 lgnq
-    /* make all interrupts level triggered */
-    (ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
-    /* mask all interrupts */
-    (ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
-
-    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-    for (idx = 0; idx < MAX_INTR; idx ++)
-    {
-        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-    /* mask interrupt */
-    (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                         void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector >= 0 && vector < MAX_INTR)
-    {
-        old_handler = irq_handle_table[vector].handler;
-
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-        irq_handle_table[vector].handler = handler;
-        irq_handle_table[vector].param = param;
-    }
-
-    return old_handler;
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int irq;
-    void *param;
-    rt_isr_handler_t irq_func;
-    static rt_uint32_t status = 0;
-    rt_uint32_t c0_status;
-    rt_uint32_t c0_cause;
-    volatile rt_uint32_t cause_im;
-    volatile rt_uint32_t status_im;
-    rt_uint32_t pending_im;
-
-    /* check os timer */
-    c0_status = read_c0_status();
-    c0_cause = read_c0_cause();
-
-    cause_im = c0_cause & ST0_IM;
-    status_im = c0_status & ST0_IM;
-    pending_im = cause_im & status_im;
-
-    if (pending_im & CAUSEF_IP7)
-    {
-        rt_hw_timer_handler();
-    }
-
-    if (pending_im & CAUSEF_IP2)
-    {
-        /* the hardware interrupt */
-        status = ls1b_hw0_icregs->int_isr;
-        if (!status)
-            return;
-
-        for (irq = MAX_INTR; irq > 0; --irq)
-        {
-            if ((status & (1 << irq)))
-            {
-                status &= ~(1 << irq);
-
-                irq_func = irq_handle_table[irq].handler;
-                param = irq_handle_table[irq].param;
-
-                /* do interrupt */
-                irq_func(irq, param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-                irq_handle_table[irq].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-                /* ack interrupt */
-                ls1b_hw0_icregs->int_clr |= (1 << irq);
-            }
-        }
-    }
-    else if (pending_im & CAUSEF_IP3)
-    {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-    }
-    else if (pending_im & CAUSEF_IP4)
-    {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-    }
-    else if (pending_im & CAUSEF_IP5)
-    {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-    }
-    else if (pending_im & CAUSEF_IP6)
-    {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson_1b/ls1b.h b/libcpu/mips/loongson_1b/ls1b.h
deleted file mode 100644
index 34393a3448..0000000000
--- a/libcpu/mips/loongson_1b/ls1b.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * File      : ls1b.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-08-08     lgnq         first version
- */
-
-#ifndef __LS1B_H__
-#define __LS1B_H__
-
-#include "../common/mipsregs.h"
-
-#define LS1B_ACPI_IRQ	0
-#define LS1B_HPET_IRQ	1
-#define LS1B_UART0_IRQ	2
-#define LS1B_UART1_IRQ	3
-#define LS1B_UART2_IRQ	4
-#define LS1B_UART3_IRQ	5
-#define LS1B_CAN0_IRQ	6
-#define LS1B_CAN1_IRQ	7
-#define LS1B_SPI0_IRQ	8
-#define LS1B_SPI1_IRQ	9
-#define LS1B_AC97_IRQ	10
-#define LS1B_MS_IRQ		11
-#define LS1B_KB_IRQ		12
-#define LS1B_DMA0_IRQ	13
-#define LS1B_DMA1_IRQ	14
-#define LS1B_NAND_IRQ	15
-#define LS1B_I2C0_IRQ	16
-#define LS1B_I2C1_IRQ	17
-#define LS1B_PWM0_IRQ	18
-#define LS1B_PWM1_IRQ	19
-#define LS1B_PWM2_IRQ	20
-#define LS1B_PWM3_IRQ	21
-#define LS1B_LPC_IRQ	22
-#define LS1B_EHCI_IRQ	32
-#define LS1B_OHCI_IRQ	33
-#define LS1B_GMAC1_IRQ	34
-#define LS1B_GMAC2_IRQ	35
-#define LS1B_SATA_IRQ	36
-#define LS1B_GPU_IRQ	37
-#define LS1B_PCI_INTA_IRQ 38
-#define LS1B_PCI_INTB_IRQ 39
-#define LS1B_PCI_INTC_IRQ 40
-#define LS1B_PCI_INTD_IRQ 41
-
-#define LS1B_GPIO_IRQ 64
-#define LS1B_GPIO_FIRST_IRQ 64
-#define LS1B_GPIO_IRQ_COUNT 96
-#define LS1B_GPIO_LAST_IRQ  (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
-
-#define INT_PCI_INTA	(1<<6)
-#define INT_PCI_INTB	(1<<7)
-#define INT_PCI_INTC	(1<<8)
-#define INT_PCI_INTD	(1<<9)
-
-#define LS1B_LAST_IRQ 159
-#define MIPS_CPU_TIMER_IRQ	167
-#define LS1B_INTREG_BASE 0xbfd01040
-
-#define LS1B_DMA_IRQ_BASE 168
-#define LS1B_DMA_IRQ_COUNT 16
-
-struct ls1b_intc_regs
-{
-	volatile unsigned int int_isr;
-	volatile unsigned int int_en;
-	volatile unsigned int int_set;
-	volatile unsigned int int_clr;		/* offset 0x10*/
-	volatile unsigned int int_pol;
-   	volatile unsigned int int_edge;		/* offset 0 */
-}; 
-
-struct ls1b_cop_global_regs
-{
-	volatile unsigned int control;
-	volatile unsigned int rd_inten;
-	volatile unsigned int wr_inten;
-	volatile unsigned int rd_intisr;		/* offset 0x10*/
-	volatile unsigned int wr_intisr;
-	unsigned int unused[11];
-} ; 
-
-struct ls1b_cop_channel_regs
-{
-	volatile unsigned int rd_control;
-	volatile unsigned int rd_src;
-	volatile unsigned int rd_cnt;
-	volatile unsigned int rd_status;		/* offset 0x10*/
-	volatile unsigned int wr_control;
-	volatile unsigned int wr_src;
-	volatile unsigned int wr_cnt;
-	volatile unsigned int wr_status;		/* offset 0x10*/
-} ; 
-
-struct ls1b_cop_regs
-{
-	struct ls1b_cop_global_regs global;
-	struct ls1b_cop_channel_regs chan[8][2];
-} ;
-
-#define __REG8(addr)		*((volatile unsigned char *)(addr))
-#define __REG16(addr)		*((volatile unsigned short *)(addr))
-#define __REG32(addr)		*((volatile unsigned int *)(addr))
-
-#define GMAC0_BASE			0xBFE10000
-#define GMAC0_DMA_BASE		0xBFE11000
-#define GMAC1_BASE			0xBFE20000
-#define GMAC1_DMA_BASE		0xBFE21000
-#define I2C0_BASE			0xBFE58000
-#define PWM0_BASE			0xBFE5C000
-#define PWM1_BASE			0xBFE5C010
-#define PWM2_BASE			0xBFE5C020
-#define PWM3_BASE			0xBFE5C030
-#define WDT_BASE			0xBFE5C060
-#define RTC_BASE			0xBFE64000
-#define I2C1_BASE			0xBFE68000
-#define I2C2_BASE			0xBFE70000
-#define AC97_BASE			0xBFE74000
-#define NAND_BASE			0xBFE78000
-#define SPI_BASE			0xBFE80000
-#define CAN1_BASE			0xBF004300
-#define CAN0_BASE			0xBF004400
-
-/* Watch Dog registers */
-#define WDT_EN				__REG32(WDT_BASE + 0x00)
-#define WDT_SET				__REG32(WDT_BASE + 0x04)
-#define WDT_TIMER			__REG32(WDT_BASE + 0x08)
-
-#define PLL_FREQ 				__REG32(0xbfe78030)
-#define PLL_DIV_PARAM 			__REG32(0xbfe78034)
-
-#endif
diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c
deleted file mode 100644
index 10dd3fee9e..0000000000
--- a/libcpu/mips/loongson_1b/mipscfg.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-	rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
-	rt_uint16_t rets = 0;
-
-    while (b != 1)
-    {
-        b /= 2;
-        rets++;
-    }
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
-
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
-
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
-
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
-
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
-}
diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S
deleted file mode 100644
index f54fbb9a1d..0000000000
--- a/libcpu/mips/loongson_1b/start_gcc.S
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-
-	.section ".start", "ax"
-	.set noreorder
-
-	/* the program entry */
-	.globl  _start
-_start:
-	.set	noreorder
-	la	ra, _start
-
-	/* disable interrupt */
-	mfc0	t0, CP0_STATUS
-	and 	t0, 0xfffffffe	# By default it will be disabled.
-	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.
-	nop
-
-	/* disable cache */
-	mfc0	t0, CP0_CONFIG
-	and	t0, 0xfffffff8
-	or	t0, 0x2		# disable,!default value is not it!
-	mtc0	t0, CP0_CONFIG	# Set CPU to disable cache.
-	nop
-
-	/* setup stack pointer */
-	li	sp, SYSTEM_STACK
-	la	gp, _gp
-
-	/* clear bss */
-	la	t0, __bss_start
-	la	t1, __bss_end
-_clr_bss_loop:
-	sw	zero, 0(t0)
-	bne	t0, t1, _clr_bss_loop
-	addiu	t0, t0, 4
-
-	/* jump to RT-Thread RTOS */
-	jal	rtthread_startup
-	nop
-
-	/* restart, never die */
-	j	_start
-	nop
-	.set	reorder
-
-	.globl  cp0_get_cause
-cp0_get_cause:
-	mfc0	v0, CP0_CAUSE
-	jr	ra
-	nop
-
-	.globl  cp0_get_status
-cp0_get_status:
-	mfc0	v0, CP0_STATUS
-	jr	ra
-	nop
-
-	.globl	cp0_get_hi
-cp0_get_hi:
-	mfhi	v0
-	jr	ra
-	nop
-
-	.globl	cp0_get_lo
-cp0_get_lo:
-	mflo	v0
-	jr	ra
-	nop
-
-	.extern tlb_refill_handler
-	.extern cache_error_handler
-
-	/* Exception Handler */
-
-	/* 0x0 - TLB refill handler */
-	.section .vectors.1, "ax", %progbits
-	.global tlb_refill_exception
-	.type	tlb_refill_exception,@function
-tlb_refill_exception:
-	j	tlb_refill_handler
-	nop
-	
-	/* 0x100 - Cache error handler */
-	.section .vectors.2, "ax", %progbits
-	j	cache_error_handler
-	nop
-    
-	/* 0x180 - Exception/Interrupt handler */
-	.section .vectors.3, "ax", %progbits
-	.global general_exception
-	.type	general_exception,@function
-general_exception:
-	j	_general_exception_handler
-	nop
-    
-	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-	.section .vectors.4, "ax", %progbits
-	.global irq_exception
-	.type	irq_exception,@function
-irq_exception:
-	j	_irq_handler
-	nop
-	
-	.section .vectors, "ax", %progbits
-	.extern mips_irq_handle
-
-	/* general exception handler */
-_general_exception_handler:
-	.set	noreorder
-	la	k0, mips_irq_handle
-	jr	k0
-	nop
-	.set	reorder
-
-	/* interrupt handler */
-_irq_handler:
-	.set	noreorder
-	la	k0, mips_irq_handle
-	jr	k0
-	nop
-	.set	reorder
diff --git a/libcpu/mips/loongson_1c/SConscript b/libcpu/mips/loongson_1c/SConscript
deleted file mode 100644
index b0ae20ba02..0000000000
--- a/libcpu/mips/loongson_1c/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ''
-
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')
diff --git a/libcpu/mips/loongson_1c/cache.c b/libcpu/mips/loongson_1c/cache.c
deleted file mode 100644
index bf97db9b4e..0000000000
--- a/libcpu/mips/loongson_1c/cache.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * File      : cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date                Author            Notes
- * 2010-07-09     Bernard        first version
- * 2011-08-08     lgnq             modified for LS1B
- * 2015-07-08     chinesebear   modified for loongson 1c
- */
- 
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-
-#define K0BASE			0x80000000
-#define PRID_LS1C		0x4220
-
-extern void Clear_TagLo (void);
-extern void Invalidate_Icache_Ls1c(unsigned int);
-extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
-extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
-extern void Writeback_Invalidate_Dcache(unsigned int);
-extern void enable_cpu_cache(void);
-
-typedef struct cacheinfo_t 
-{
-	unsigned int	icache_size;
-	unsigned int	dcache_size;
-	unsigned int	icacheline_size;
-	unsigned int	dcacheline_size;
-} cacheinfo_t ;
-
-typedef struct cacheop_t 
-{
-	void (*Clear_TagLo) (void);
-	void (*Invalidate_Icache) (unsigned int);
-	void (*Invalidate_Dcache_Fill) (unsigned int);
-	void (*Invalidate_Dcache_ClearTag) (unsigned int);
-	void (*Init_Cache)(void);
-} cacheop_t ;
-
-static cacheop_t cacheop, *pcacheop;
-static cacheinfo_t cacheinfo, *pcacheinfo;
-
-int identify_cpu(void)
-{
-    unsigned int cpu_id;
-
-    pcacheop = &cacheop;
-    pcacheinfo = &cacheinfo;
-
-	rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
-    cpu_id = read_c0_prid();
-    switch (cpu_id)
-	{
-	case PRID_LS1C:       
-	    rt_kprintf("CPU:Loongson 1C\n");
-	    pcacheop->Clear_TagLo = Clear_TagLo;
-	    pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
-	    pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
-	    pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
-	    break;
-	default:
-	    rt_kprintf("Unknown CPU type, system halted!\n");
-	    while (1) 
-	    {
-	    	;
-	    }
-	    break;
-    }
-
-    return 0;
-}
-
-void probe_cache(void)
-{
-    unsigned int config1 = read_c0_config1();
-    unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
-    unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
-
-    if ((icache_line_size = ((config1 >> 19) & 7)))
-        icache_line_size = 2 << icache_line_size;
-    else
-        icache_line_size = icache_line_size;
-    icache_sets = 64 << ((config1 >> 22) & 7);
-    icache_ways = 1 + ((config1 >> 16) & 7);
-    icache_size = icache_sets * icache_ways * icache_line_size;
-    
-    if ((dcache_line_size = ((config1 >> 10) & 7)))
-        dcache_line_size = 2 << dcache_line_size;
-    else
-        dcache_line_size = dcache_line_size;
-    dcache_sets = 64 << ((config1 >> 13) & 7);
-    dcache_ways = 1 + ((config1 >> 7) & 7);
-    dcache_size = dcache_sets * dcache_ways * dcache_line_size;
-    
-    rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
-    rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
-
-    pcacheinfo->icache_size = icache_size;
-    pcacheinfo->dcache_size = dcache_size;
-    pcacheinfo->icacheline_size = icache_line_size;
-    pcacheinfo->dcacheline_size = dcache_line_size;
-
-    return ;
-}
-
-void invalidate_writeback_dcache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while (start < end) 
-	{
-		Writeback_Invalidate_Dcache(start);  //hit writeback invalidate 
-		start += pcacheinfo->dcacheline_size;
-	}
-}
-
-void invalidate_writeback_dcache(unsigned long addr, int size)
-{
-	unsigned long start, end;
-			
-	start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
-	end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-	
-	while (start <end)
-	{
-		Writeback_Invalidate_Dcache(start);
-		start += pcacheinfo->dcacheline_size;
-	}		
-}
-
-void invalidate_icache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->icache_size);
-
-	while (start < end) 
-	{
-		pcacheop->Invalidate_Icache(start); 
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-void invalidate_dcache_all(void)
-{ 
-	unsigned int start = K0BASE;
-	unsigned int end  = (start + pcacheinfo->dcache_size);
-	while (start <end)
-	{
-		Invalidate_Dcache_Fill_Ls1c(start);
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-//with cache disabled
-void init_dcache(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while (start < end)
-	{
-		pcacheop->Invalidate_Dcache_ClearTag(start);
-		start += pcacheinfo->dcacheline_size;
-	}
-
-}
-
-void rt_hw_cache_init(void)
-{
-    unsigned int start, end;
-	
-	/* 1. identify cpu and probe cache */
-	identify_cpu();
-	probe_cache();
-
-	start = K0BASE;
-	end = (start + pcacheinfo->icache_size);
-
-    /*
-     *	2. clear CP0 taglo/taghi register;
-     */
-    pcacheop->Clear_TagLo();
-
-	/*
-     *	3. invalidate instruction cache;
-     */
-    while (start < end) 
-    {
-		pcacheop->Invalidate_Icache(start); //index invalidate icache 
-		start += pcacheinfo->icacheline_size;
-    }
-
-    /*
-     *	4. invalidate data cache;
-     */
-    start = K0BASE;
-    end = (start + pcacheinfo->dcache_size);
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-	/* enable cache */
-	enable_cpu_cache();
-	rt_kprintf("enable cpu cache done\n");
-
-	return ;
-}
-
-
diff --git a/libcpu/mips/loongson_1c/cache.h b/libcpu/mips/loongson_1c/cache.h
deleted file mode 100644
index b5c2d4501e..0000000000
--- a/libcpu/mips/loongson_1c/cache.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * File      : cache.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2011-08-08     lgnq         modified for LS1B
- */
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-#endif
diff --git a/libcpu/mips/loongson_1c/cache_gcc.S b/libcpu/mips/loongson_1c/cache_gcc.S
deleted file mode 100644
index 649a88b67b..0000000000
--- a/libcpu/mips/loongson_1c/cache_gcc.S
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- * 2011-08-08     lgnq         port to Loongson LS1B
- * 2015-07-08     chinesebear  port to Loongson LS1C
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mipsregs.h"
-#include "../common/mips_def.h"
-#include "../common/asm.h"
-#include "cache.h"
-
-	.ent	cache_init
-    .global cache_init
-    .set noreorder
-cache_init:
-        move t1,ra
-####part 2####
-cache_detect_4way:
-        mfc0    t4, CP0_CONFIG
-        andi    t5, t4, 0x0e00
-        srl     t5, t5, 9     #ic
-        andi    t6, t4, 0x01c0
-        srl     t6, t6, 6     #dc
-        addiu   t8, $0, 1
-        addiu   t9, $0, 2
-                                #set dcache way
-        beq     t6, $0,  cache_d1way
-        addiu   t7, $0, 1       #1 way
-        beq     t6, t8,  cache_d2way
-        addiu   t7, $0, 2       #2 way
-        beq     $0, $0, cache_d4way
-        addiu   t7, $0, 4       #4 way
-cache_d1way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 12      #1 way
-cache_d2way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 11      #2 way
-cache_d4way:
-        addiu   t6, t6, 10      #4 way (10), 2 way(11), 1 way(12)
-1:                              #set icache way
-        beq     t5, $0,  cache_i1way
-        addiu   t3, $0, 1       #1 way
-        beq     t5, t8,  cache_i2way
-        addiu   t3, $0, 2       #2 way
-        beq     $0, $0, cache_i4way
-        addiu   t3, $0, 4       #4 way
-cache_i1way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 12
-cache_i2way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 11
-cache_i4way:
-        addiu   t5, t5, 10      #4 way (10), 2 way(11), 1 way(12)
-
-1:      addiu   t4, $0, 1
-        sllv    t6, t4, t6
-        sllv    t5, t4, t5
-#if 0
-    la	t0, memvar
-	sw	t7, 0x0(t0) #ways
-	sw	t5, 0x4(t0) #icache size
-	sw	t6, 0x8(t0) #dcache size
-#endif
-####part 3####
-	.set	mips3
-	lui	a0, 0x8000
-	addu	a1, $0, t5
-	addu	a2, $0, t6
-cache_init_d2way:
-#a0=0x80000000, a1=icache_size, a2=dcache_size
-#a3, v0 and v1 used as local registers
-	mtc0	$0, CP0_TAGHI
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	mtc0	$0, CP0_TAGLO
-	beq	t7, 1, 4f
-	cache	Index_Store_Tag_D, 0x0(v0)	# 1 way
-	beq	t7, 2 ,4f
-	cache	Index_Store_Tag_D, 0x1(v0)	# 2 way
-	cache	Index_Store_Tag_D, 0x2(v0)	# 4 way
-	cache	Index_Store_Tag_D, 0x3(v0)
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_i2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a1
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t3, 1, 4f
-	cache	Index_Invalidate_I, 0x0(v0)	# 1 way
-	beq	t3, 2, 4f
-	cache	Index_Invalidate_I, 0x1(v0)	# 2 way
-	cache	Index_Invalidate_I, 0x2(v0)
-	cache	Index_Invalidate_I, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_d2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t7, 1, 4f
-	cache	Index_Writeback_Inv_D, 0x0(v0) 	#1 way
-	beq	t7, 2, 4f
-	cache	Index_Writeback_Inv_D, 0x1(v0)	# 2 way
-	cache	Index_Writeback_Inv_D, 0x2(v0)
-	cache	Index_Writeback_Inv_D, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_init_finish:
-	jr	t1
-    nop
-    .set reorder
-	.end cache_init
-
-###########################
-#  Enable CPU cache       #
-###########################
-
-LEAF(enable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or		t0, 0x03
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (enable_cpu_cache)
-    
-###########################
-#  disable CPU cache      #
-###########################
-
-LEAF(disable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or 		t0, 0x2
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (disable_cpu_cache)
-
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Clear_TagLo)
-	.set 	noreorder
-	mtc0	zero, CP0_TAGLO
-	nop
-	.set 	reorder
-	j		ra
-END(Clear_TagLo)
-
-    .set mips3
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Invalidate_Icache_Ls1c)
-	.set	noreorder
-	cache	Index_Invalidate_I,0(a0)
-	cache	Index_Invalidate_I,1(a0)
-	cache	Index_Invalidate_I,2(a0)
-	cache	Index_Invalidate_I,3(a0)
-	.set	reorder
-	j		ra
-END(Invalidate_Icache_Ls1c)
-
-/**********************************/
-/* Invalidate Data Cache		  */
-/**********************************/
-LEAF(Invalidate_Dcache_ClearTag_Ls1c)
-	.set	noreorder
-	cache	Index_Store_Tag_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Store_Tag_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_ClearTag_Ls1c)
-
-LEAF(Invalidate_Dcache_Fill_Ls1c)
-	.set	noreorder
-	cache	Index_Writeback_Inv_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Writeback_Inv_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_Fill_Ls1c)
-
-LEAF(Writeback_Invalidate_Dcache)
-	.set noreorder
-	cache	Hit_Writeback_Inv_D, (a0)
-	.set reorder
-	j	ra
-END(Writeback_Invalidate_Dcache)
-    .set mips0
diff --git a/libcpu/mips/loongson_1c/context_gcc.S b/libcpu/mips/loongson_1c/context_gcc.S
deleted file mode 100644
index 53bce723e7..0000000000
--- a/libcpu/mips/loongson_1c/context_gcc.S
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- * 2011-08-08     lgnq         port to Loongson LS1B
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-#include "stackframe_fpu.h"
-
-    .section ".text", "ax"
-    .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    ori     a0, 0x00000800   
-    mtc0    a0, CP0_STATUS
-    ehb
-    mfc0    v0, CP0_CAUSE
-    ehb
-    or      v1, v0, 0x800000                 //EBASE + 0x200                                                                                                 
-    mtc0    v1, CP0_CAUSE
-    ehb
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-    .globl rt_hw_context_switch
-rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
-    SAVE_ALL
-    SAVE_FPU
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-    RESTORE_FPU
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
-
-    RESTORE_FPU
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-    .globl rt_thread_switch_interrupt_flag
-    .globl rt_interrupt_from_thread
-    .globl rt_interrupt_to_thread
-    .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
-    .globl rt_interrupt_enter
-    .globl rt_interrupt_leave
-    .globl mips_irq_handle
-mips_irq_handle:
-    SAVE_ALL
-    SAVE_FPU
-
-    mfc0    t0, CP0_CAUSE
-    and     t1, t0, 0xff
-	bnez	t1, spurious_interrupt		/* check exception */
-	nop
-
-	/* let k0 keep the current context sp */
-    move    k0, sp 
-    /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
-
-    jal     rt_interrupt_enter
-    nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-	nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-
-spurious_interrupt:
-    RESTORE_FPU
-    RESTORE_ALL_AND_RET
-
-    .set reorder
diff --git a/libcpu/mips/loongson_1c/cpuport.c b/libcpu/mips/loongson_1c/cpuport.c
deleted file mode 100644
index 03fdc2a514..0000000000
--- a/libcpu/mips/loongson_1c/cpuport.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * File      : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date                Author         Notes
- * 2010-07-09     Bernard        first version
- * 2010-09-11     Bernard        add CPU reset implementation
- * 2015-07-06     chinesebear  modified for loongson 1c
- */
-
-#include <rtthread.h>
-#include "ls1c.h"
-
-register rt_uint32_t $GP __asm__ ("$28");
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset(void)
-{
-	/* open the watch-dog */
-	WDT_EN = 0x01; 		/* watch dog enable */
-	WDT_TIMER = 0x01;	/* watch dog will be timeout after 1 tick */
-	WDT_SET = 0x01;		/* watch dog start */
-
-	rt_kprintf("reboot system...\n");
-	while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown(void)
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-	rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-	static rt_uint32_t g_gp = 0;
-
-    if (g_sr == 0)
-    {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x8401;
-
-		g_gp = $GP;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) g_gp;	        /* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-#define cache_op(op,addr)                       \
-	    __asm__ __volatile__(                       \
-				    "   .set    push                    \n" \
-				    "   .set    noreorder               \n" \
-				    "   .set    mips3\n\t               \n" \
-				    "   cache   %0, %1                  \n" \
-				    "   .set    pop                 \n" \
-				    :                               \
-				    : "i" (op), "R" (*(unsigned char *)(addr)))
-
-#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I    0x00
-#else
-#define Hit_Invalidate_I    0x10
-#endif
-#define Hit_Invalidate_D    0x11
-#define CONFIG_SYS_CACHELINE_SIZE   32
-#define Hit_Writeback_Inv_D 0x15
-
-
-void flush_cache(unsigned long start_addr, unsigned long size)
-{
-	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-	unsigned long addr = start_addr & ~(lsize - 1); 
-	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); 
-
-	while (1) {
-		cache_op(Hit_Writeback_Inv_D, addr);
-		cache_op(Hit_Invalidate_I, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}   
-}
-
-
-/*@}*/
-
diff --git a/libcpu/mips/loongson_1c/exception.c b/libcpu/mips/loongson_1c/exception.c
deleted file mode 100644
index 4a3745cbc5..0000000000
--- a/libcpu/mips/loongson_1c/exception.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Loongson
- */
-
-/*@{*/
-
-/**
- * exception handle table
- */
-#define RT_EXCEPTION_MAX	8
-exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-	rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
-}
-
-void install_default_execpt_handle(void)
-{
-	rt_int32_t i;
-
-	for (i=0; i<RT_EXCEPTION_MAX; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-void exception_handler(pt_regs_t *regs)
-{
-	rt_uint32_t cause;
-	rt_uint32_t index;
-
-	cause = (read_c0_cause() & read_c0_config());
-	cause = (cause & 0xfc00) >> 8;
-
-	for (index = RT_EXCEPTION_MAX; index > 0; index --)
-	{
-		if (cause & (1 << index))
-		{
-			sys_exception_handlers[index](regs);
-			cause &= ~(1 << index);
-		}
-	}
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson_1c/interrupt.c b/libcpu/mips/loongson_1c/interrupt.c
deleted file mode 100644
index 407580d89e..0000000000
--- a/libcpu/mips/loongson_1c/interrupt.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date                  Author       Notes
- * 2010-10-15     Bernard      first version
- * 2010-10-15     lgnq           modified for LS1B
- * 2013-03-29     aozima       Modify the interrupt interface implementations.
- * 2015-07-06     chinesebear modified for loongson 1c
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include "ls1c.h"
-#include "ls1c_public.h"
-
-
-#define MAX_INTR            (LS1C_NR_IRQS)
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc irq_handle_table[MAX_INTR];
-void rt_interrupt_dispatch(void *ptreg);
-void rt_hw_timer_handler();
-
-static struct ls1c_intc_regs volatile *ls1c_hw0_icregs
-= (struct ls1c_intc_regs volatile *)(LS1C_INTREG_BASE);
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-static void rt_hw_interrupt_handler(int vector, void *param)
-{
-    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    rt_int32_t idx;
-    rt_int32_t i;
-    rt_uint32_t c0_status = 0;
-
-    // ����Э������0��״̬�Ĵ���SR��IM7-2�������ж�
-    c0_status = read_c0_status();
-    c0_status |= 0xFC00;
-    write_c0_status(c0_status);
-
-    // ��о1c���жϷ�Ϊ����
-    for (i=0; i<5; i++)
-    {
-        /* disable */
-        (ls1c_hw0_icregs+i)->int_en = 0x0;
-        /* pci active low */
-        (ls1c_hw0_icregs+i)->int_pol = -1;	   //must be done here 20110802 lgnq
-        /* make all interrupts level triggered */
-        (ls1c_hw0_icregs+i)->int_edge = 0x00000000;
-        /* mask all interrupts */
-        (ls1c_hw0_icregs+i)->int_clr = 0xffffffff;
-    }
-
-    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-    for (idx = 0; idx < MAX_INTR; idx ++)
-    {
-        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-    /* mask interrupt */
-    (ls1c_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    (ls1c_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                         void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector >= 0 && vector < MAX_INTR)
-    {
-        old_handler = irq_handle_table[vector].handler;
-
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-        irq_handle_table[vector].handler = handler;
-        irq_handle_table[vector].param = param;
-    }
-
-    return old_handler;
-}
-
-
-/**
- * ִ���жϴ�������
- * @IRQn �жϺ�
- */
-void ls1c_do_IRQ(int IRQn)
-{
-    rt_isr_handler_t irq_func;
-    void *param;
-
-    // �ҵ��жϴ�������
-    irq_func = irq_handle_table[IRQn].handler;
-    param    = irq_handle_table[IRQn].param;
-
-    // ִ���жϴ�������
-    irq_func(IRQn, param);
-    
-#ifdef RT_USING_INTERRUPT_INFO
-    irq_handle_table[IRQn].counter++;
-#endif
-
-    return ;
-}
-
-
-void ls1c_irq_dispatch(int n)
-{
-    rt_uint32_t intstatus, irq;
-
-    /* Receive interrupt signal, compute the irq */
-    intstatus = (ls1c_hw0_icregs+n)->int_isr & (ls1c_hw0_icregs+n)->int_en;
-    if (0 == intstatus)
-        return ;
-
-    // ִ���жϴ�������
-    irq = ls1c_ffs(intstatus) - 1;
-    ls1c_do_IRQ((n<<5) + irq);
-
-    /* ack interrupt */
-    (ls1c_hw0_icregs+n)->int_clr |= (1 << irq);
-
-    return ;
-}
-
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int irq;
-    void *param;
-    rt_isr_handler_t irq_func;
-    static rt_uint32_t status = 0;
-    rt_uint32_t c0_status;
-    rt_uint32_t c0_cause;
-    volatile rt_uint32_t cause_im;
-    volatile rt_uint32_t status_im;
-    rt_uint32_t pending_im;
-
-    /* check os timer */
-    c0_status = read_c0_status();
-    c0_cause = read_c0_cause();
-
-    cause_im = c0_cause & ST0_IM;
-    status_im = c0_status & ST0_IM;
-    pending_im = cause_im & status_im;
-
-    if (pending_im & CAUSEF_IP7)
-    {
-        rt_hw_timer_handler();
-    }
-    else if (pending_im & CAUSEF_IP2)
-    {
-        ls1c_irq_dispatch(0);
-    }
-    else if (pending_im & CAUSEF_IP3)
-    {
-        ls1c_irq_dispatch(1);
-    }
-    else if (pending_im & CAUSEF_IP4)
-    {
-        ls1c_irq_dispatch(2);
-    }
-    else if (pending_im & CAUSEF_IP5)
-    {
-        ls1c_irq_dispatch(3);
-    }
-    else if (pending_im & CAUSEF_IP6)
-    {
-        ls1c_irq_dispatch(4);
-    }
-}
-
-/*@}*/
-
-
diff --git a/libcpu/mips/loongson_1c/ls1c.h b/libcpu/mips/loongson_1c/ls1c.h
deleted file mode 100644
index 963f774cf7..0000000000
--- a/libcpu/mips/loongson_1c/ls1c.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * File      : ls1c.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date               Author             Notes
- * 2011-08-08     lgnq                first version
- * 2015-07-06     chinesebear      modified for loongson 1c
- */
-
-#ifndef __LS1C_H__
-#define __LS1C_H__
-
-#include "../common/mipsregs.h"
-
-#define LS1C_ACPI_IRQ    0
-#define LS1C_HPET_IRQ    1
-//#define LS1C_UART0_IRQ    3  // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ��
-#define LS1C_UART1_IRQ   4
-#define LS1C_UART2_IRQ   5
-#define LS1C_CAN0_IRQ    6
-#define LS1C_CAN1_IRQ    7
-#define LS1C_SPI0_IRQ    8
-#define LS1C_SPI1_IRQ    9
-#define LS1C_AC97_IRQ    10
-#define LS1C_MS_IRQ      11
-#define LS1C_KB_IRQ      12
-#define LS1C_DMA0_IRQ    13
-#define LS1C_DMA1_IRQ    14
-#define LS1C_DMA2_IRQ    15
-#define LS1C_NAND_IRQ    16
-#define LS1C_PWM0_IRQ    17
-#define LS1C_PWM1_IRQ    18
-#define LS1C_PWM2_IRQ    19
-#define LS1C_PWM3_IRQ    20
-#define LS1C_RTC_INT0_IRQ  21
-#define LS1C_RTC_INT1_IRQ  22
-#define LS1C_RTC_INT2_IRQ  23
-#define LS1C_UART3_IRQ   29
-#define LS1C_ADC_IRQ     30
-#define LS1C_SDIO_IRQ    31
-
-
-#define LS1C_EHCI_IRQ   (32+0)
-#define LS1C_OHCI_IRQ   (32+1)
-#define LS1C_OTG_IRQ    (32+2)
-#define LS1C_MAC_IRQ    (32+3)
-#define LS1C_CAM_IRQ    (32+4)
-#define LS1C_UART4_IRQ  (32+5)
-#define LS1C_UART5_IRQ  (32+6)
-#define LS1C_UART6_IRQ  (32+7)
-#define LS1C_UART7_IRQ  (32+8)
-#define LS1C_UART8_IRQ  (32+9)
-#define LS1C_UART9_IRQ  (32+13)
-#define LS1C_UART10_IRQ (32+14)
-#define LS1C_UART11_IRQ (32+15)
-#define LS1C_I2C2_IRQ   (32+17)
-#define LS1C_I2C1_IRQ   (32+18)
-#define LS1C_I2C0_IRQ   (32+19)
-
-
-#define LS1C_GPIO_IRQ       64
-#define LS1C_GPIO_FIRST_IRQ 64
-#define LS1C_GPIO_IRQ_COUNT 96
-#define LS1C_GPIO_LAST_IRQ  (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
-
-
-#define LS1C_LAST_IRQ 159
-#define LS1C_INTREG_BASE 0xbfd01040
-
-// ��о1c���жϷ�Ϊ���飬ÿ��32��
-#define LS1C_NR_IRQS    (32*5)
-
-
-// GPIO��ź��жϺ�֮��Ļ���ת��
-#define LS1C_GPIO_TO_IRQ(GPIOn)     (LS1C_GPIO_FIRST_IRQ + (GPIOn))
-#define LS1C_IRQ_TO_GPIO(IRQn)      ((IRQn) - LS1C_GPIO_FIRST_IRQ)
-
-
-struct ls1c_intc_regs
-{
-    volatile unsigned int int_isr;
-    volatile unsigned int int_en;
-    volatile unsigned int int_set;
-    volatile unsigned int int_clr;        /* offset 0x10*/
-    volatile unsigned int int_pol;
-    volatile unsigned int int_edge;        /* offset 0 */
-}; 
-
-struct ls1c_cop_global_regs
-{
-    volatile unsigned int control;
-    volatile unsigned int rd_inten;
-    volatile unsigned int wr_inten;
-    volatile unsigned int rd_intisr;        /* offset 0x10*/
-    volatile unsigned int wr_intisr;
-    unsigned int unused[11];
-} ; 
-
-struct ls1c_cop_channel_regs
-{
-    volatile unsigned int rd_control;
-    volatile unsigned int rd_src;
-    volatile unsigned int rd_cnt;
-    volatile unsigned int rd_status;        /* offset 0x10*/
-    volatile unsigned int wr_control;
-    volatile unsigned int wr_src;
-    volatile unsigned int wr_cnt;
-    volatile unsigned int wr_status;        /* offset 0x10*/
-} ; 
-
-struct ls1c_cop_regs
-{
-    struct ls1c_cop_global_regs global;
-    struct ls1c_cop_channel_regs chan[8][2];
-} ;
-
-#define __REG8(addr)        *((volatile unsigned char *)(addr))
-#define __REG16(addr)       *((volatile unsigned short *)(addr))
-#define __REG32(addr)       *((volatile unsigned int *)(addr))
-
-#define GMAC0_BASE            0xBFE10000
-#define GMAC0_DMA_BASE        0xBFE11000
-#define GMAC1_BASE            0xBFE20000
-#define GMAC1_DMA_BASE        0xBFE21000
-#define I2C0_BASE             0xBFE58000
-#define PWM0_BASE             0xBFE5C000
-#define PWM1_BASE             0xBFE5C010
-#define PWM2_BASE             0xBFE5C020
-#define PWM3_BASE             0xBFE5C030
-#define WDT_BASE              0xBFE5C060
-#define RTC_BASE              0xBFE64000
-#define I2C1_BASE             0xBFE68000
-#define I2C2_BASE             0xBFE70000
-#define AC97_BASE             0xBFE74000
-#define NAND_BASE             0xBFE78000
-#define SPI_BASE              0xBFE80000
-#define CAN1_BASE             0xBF004300
-#define CAN0_BASE             0xBF004400
-
-/* Watch Dog registers */
-#define WDT_EN               __REG32(WDT_BASE + 0x00)
-#define WDT_SET              __REG32(WDT_BASE + 0x08)
-#define WDT_TIMER            __REG32(WDT_BASE + 0x04)
-
-#define PLL_FREQ             __REG32(0xbfe78030)
-#define PLL_DIV_PARAM        __REG32(0xbfe78034)
-
-#endif
-
diff --git a/libcpu/mips/loongson_1c/mipscfg.c b/libcpu/mips/loongson_1c/mipscfg.c
deleted file mode 100644
index 10dd3fee9e..0000000000
--- a/libcpu/mips/loongson_1c/mipscfg.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-	rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
-	rt_uint16_t rets = 0;
-
-    while (b != 1)
-    {
-        b /= 2;
-        rets++;
-    }
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
-
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
-
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
-
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
-
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
-}
diff --git a/libcpu/mips/loongson_1c/sdram_cfg.h b/libcpu/mips/loongson_1c/sdram_cfg.h
deleted file mode 100644
index 3f88f26623..0000000000
--- a/libcpu/mips/loongson_1c/sdram_cfg.h
+++ /dev/null
@@ -1,85 +0,0 @@
-
-#ifndef __OPENLOONGSON_SDRAM_CFG_H
-#define __OPENLOONGSON_SDRAM_CFG_H
-
-
-//#define	SD_FREQ	(6 * PLL_M) / (2 * SDRAM_PARAM_DIV_NUM)
-#define	SD_FREQ	(((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
-
- 
-/* 颗粒行数 */
-#define	ROW_1K		0x7
-#define	ROW_2K		0x0
-#define	ROW_4K		0x1
-#define	ROW_8K		0x2
-#define	ROW_16K		0x3
-/* 颗粒列数 */
-#define	COL_256		0x7
-#define	COL_512		0x0
-#define	COL_1K		0x1
-#define	COL_2K		0x2
-#define	COL_4K		0x3
-/* 颗粒位宽 */
-#define	WIDTH_8		0x0
-#define	WIDTH_16	0x1
-#define	WIDTH_32	0x2
-
-#define	TRCD		3
-#define	TCL			3
-#define	TRP			3
-#define	TRFC		8
-#define	TRAS		6
-#define	TREF		0x818
-#define	TWR			2
-
-#define	DEF_SEL		0x1
-#define	DEF_SEL_N	0x0
-#define	HANG_UP		0x1
-#define	HANG_UP_N	0x0
-#define	CFG_VALID	0x1
-
-
-#if 0
-// 白菜板8MB
-/*
-    以型号为IS42S16400的SDRAM为例，
-    物理参数为，
-    容量：8MB
-    位宽：16位
-    列宽：8位，即2的8次方，即256
-    行宽：12位，即2的12次方，即4K
-
-    所以，
-    颗粒的位宽=WIDTH_16
-    颗粒的列数=COL_256
-    颗粒的行数=ROW_4K
-
-    再结合宏SD_PARA0和芯片手册中寄存器SD_CONFIG，相信一看就能明白
-    替换宏SD_PARA0中的行宽、列宽和位宽
-*/
-#define SDRAM_WIDTH         (WIDTH_16)
-#define SDRAM_COL           (COL_256)
-#define SDRAM_ROW           (ROW_4K)
-
-#else
-
-// 智龙32MByte
-#define SDRAM_WIDTH         (WIDTH_16)
-#define SDRAM_COL           (COL_512)
-#define SDRAM_ROW           (ROW_8K)
-
-#endif
-
-#define	SD_PARA0	(0x7f<<25 | \
-					(TRAS << 21) | \
-					(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
-					(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
-					SDRAM_ROW)
-
-#define	SD_PARA1	((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
-
-#define	SD_PARA1_EN	((CFG_VALID << 9) | (HANG_UP_N << 8) | \
-					(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
-
-
-#endif
diff --git a/libcpu/mips/loongson_1c/stackframe_fpu.h b/libcpu/mips/loongson_1c/stackframe_fpu.h
deleted file mode 100644
index 93b8ef10c3..0000000000
--- a/libcpu/mips/loongson_1c/stackframe_fpu.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * ls1c FPU's stackframe
- * �ʼ���룬��������뵽stackframe.h�е�SAVE_ALL, RESTORE_ALL��RESTORE_ALL_AND_RET�У�
- * �����ǵ�Դ�ļ�"stackframe.h"λ��Ŀ¼"libcpu\mips\common"�ڣ���Ӱ�쵽����mips cpu
- * ���ԣ������½���Դ�ļ�
- */
-#ifndef __OPENLOONGSON_STACKFRAME_FPU_H
-#define __OPENLOONGSON_STACKFRAME_FPU_H
-
-
-#include "../common/asm.h"
-#include "../common/mipsregs.h"
-#include "../common/stackframe.h"
-
-
-
-#define PT_FPU_R0               (0)
-#define PT_FPU_R2               ((PT_FPU_R0) + 2*LONGSIZE)
-#define PT_FPU_R4               ((PT_FPU_R2) + 2*LONGSIZE)
-#define PT_FPU_R6               ((PT_FPU_R4) + 2*LONGSIZE)
-#define PT_FPU_R8               ((PT_FPU_R6) + 2*LONGSIZE)
-#define PT_FPU_R10              ((PT_FPU_R8) + 2*LONGSIZE)
-#define PT_FPU_R12              ((PT_FPU_R10) + 2*LONGSIZE)
-#define PT_FPU_R14              ((PT_FPU_R12) + 2*LONGSIZE)
-#define PT_FPU_R16              ((PT_FPU_R14) + 2*LONGSIZE)
-#define PT_FPU_R18              ((PT_FPU_R16) + 2*LONGSIZE)
-#define PT_FPU_R20              ((PT_FPU_R18) + 2*LONGSIZE)
-#define PT_FPU_R22              ((PT_FPU_R20) + 2*LONGSIZE)
-#define PT_FPU_R24              ((PT_FPU_R22) + 2*LONGSIZE)
-#define PT_FPU_R26              ((PT_FPU_R24) + 2*LONGSIZE)
-#define PT_FPU_R28              ((PT_FPU_R26) + 2*LONGSIZE)
-#define PT_FPU_R30              ((PT_FPU_R28) + 2*LONGSIZE)
-
-#define PT_FPU_SIZE             ((((PT_FPU_R30) + 2*LONGSIZE) + (2*PTRSIZE-1)) & ~(2*PTRSIZE-1))
-
-
-    .macro SAVE_FPU
-    .set push
-    .set noreorder
-#ifdef RT_USING_FPU
-    move k1, sp                     /* �����ֳ� */
-    and k0, k1, 0xFFFFFFF8          /* 8�ֽڶ��� */    
-    PTR_SUBU sp, k0, PT_FPU_SIZE    /* ����ջ�� */
-    s.d $f0, PT_FPU_R0(sp)
-    s.d $f2, PT_FPU_R2(sp)
-    s.d $f4, PT_FPU_R4(sp)
-    s.d $f6, PT_FPU_R6(sp)
-    s.d $f8, PT_FPU_R8(sp)
-    s.d $f10, PT_FPU_R10(sp)
-    s.d $f12, PT_FPU_R12(sp)
-    s.d $f14, PT_FPU_R14(sp)
-    s.d $f16, PT_FPU_R16(sp)
-    s.d $f18, PT_FPU_R18(sp)
-    s.d $f20, PT_FPU_R20(sp)
-    s.d $f22, PT_FPU_R22(sp)
-    s.d $f24, PT_FPU_R24(sp)
-    s.d $f26, PT_FPU_R26(sp)
-    s.d $f28, PT_FPU_R28(sp)
-    s.d $f30, PT_FPU_R30(sp)
-    move sp, k1                     /* �ָ��ֳ� */
-#endif
-    .set reorder
-    .set pop
-    .endm
-
-
-    .macro RESTORE_FPU
-    .set push
-    .set noreorder
-#ifdef RT_USING_FPU
-    move k1, sp                     /* �����ֳ� */
-    and k0, k1, 0xFFFFFFF8          /* 8�ֽڶ��� */
-    PTR_SUBU sp, k0, PT_FPU_SIZE    /* ����ջ��*/
-    l.d $f0, PT_FPU_R0(sp)
-    l.d $f2, PT_FPU_R2(sp)
-    l.d $f4, PT_FPU_R4(sp)
-    l.d $f6, PT_FPU_R6(sp)
-    l.d $f8, PT_FPU_R8(sp)
-    l.d $f10, PT_FPU_R10(sp)
-    l.d $f12, PT_FPU_R12(sp)
-    l.d $f14, PT_FPU_R14(sp)
-    l.d $f16, PT_FPU_R16(sp)
-    l.d $f18, PT_FPU_R18(sp)
-    l.d $f20, PT_FPU_R20(sp)
-    l.d $f22, PT_FPU_R22(sp)
-    l.d $f24, PT_FPU_R24(sp)
-    l.d $f26, PT_FPU_R26(sp)
-    l.d $f28, PT_FPU_R28(sp)
-    l.d $f30, PT_FPU_R30(sp)
-    move sp, k1                     /* �ָ��ֳ� */
-#endif
-    .set reorder
-    .set pop
-    .endm
-
-
-#endif
-
diff --git a/libcpu/mips/loongson_1c/start_gcc.S b/libcpu/mips/loongson_1c/start_gcc.S
deleted file mode 100644
index 1d13ef7f0f..0000000000
--- a/libcpu/mips/loongson_1c/start_gcc.S
+++ /dev/null
@@ -1,530 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to JZ47xx
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-#include "sdram_cfg.h"
-#include "cache.h"
-#include "rtconfig.h"
-
-#define SR_BOOT_EXC_VEC		0x00400000
-
-
-/* config pll div for cpu and sdram */
-#define PLL_MULT            (0x54)  // 晶振为24Mhz时，PLL=504Mhz
-#define SDRAM_DIV           (0)     // SDRAM为CPU的2分频
-#define CPU_DIV             (2)     // CPU为PLL的2分频
-
-	// 配置内存大小
-#define MEM_SIZE    (0x02000000)        // 32MByte
-
-	/* Delay macro */
-#define	DELAY(count)	\
-		li v0, count;	\
-	99: 		\
-		bnez	v0, 99b;\
-		addiu	v0, -1
-
-
-#define msize		s2
-#define	output_en	s3
-
-
-
-
-	.section ".start", "ax"
-	.set noreorder
-
-	/* the program entry */
-	.globl  _start
-_start:
-	.set	noreorder
-	la	ra, _start
-
-#if !defined(RT_USING_SELF_BOOT)
-
-	/* disable interrupt */
-	mfc0	t0, CP0_STATUS
-	and 	t0, 0xfffffffe	# By default it will be disabled.
-	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.
-	nop
-
-	/* disable cache */
-	mfc0	t0, CP0_CONFIG
-	and	t0, 0xfffffff8
-	or	t0, 0x2		# disable,!default value is not it!
-	mtc0	t0, CP0_CONFIG	# Set CPU to disable cache.
-	nop
-
-	/* setup stack pointer */
-	li	sp, SYSTEM_STACK
-	la	gp, _gp
-
-	/* clear bss */
-	la	t0, __bss_start
-	la	t1, __bss_end
-_clr_bss_loop:
-	sw	zero, 0(t0)
-	bne	t0, t1, _clr_bss_loop
-	addiu	t0, t0, 4
-
-	/* jump to RT-Thread RTOS */
-	jal	rtthread_startup
-	nop
-
-	/* restart, never die */
-	j	_start
-	nop
-	
-#else
-
-	mtc0	zero, CP0_STATUS	// 清零cp0 status寄存器
-	mtc0	zero, CP0_CAUSE		// 清零cp0 cause寄存器
-
-	/*
-	设置启动异常向量入口地址为ROM地址(0xbfc00000)
-	将寄存器cp0 status的BEV置1，使CPU采用ROM(kseg1)空间的异常入口点
-	*/
-	li	t0, SR_BOOT_EXC_VEC /* Exception to Boostrap Location */
-	mtc0	t0, CP0_STATUS
-
-	/* setup stack pointer */
-	li	sp, SYSTEM_STACK
-	la	gp, _gp
-		
-	/* initialize spi */
-	li	t0, 0xbfe80000		//地址0xbfe80000为SPI0的寄存器基地址
-	li	t1, 0x17			// div 4, fast_read + burst_en + memory_en double I/O 模式 部分SPI flash可能不支持
-	sb	t1, 0x4(t0) 		// 设置寄存器sfc_param
-	li	t1, 0x05
-	sb	t1, 0x6(t0) 		// 设置寄存器sfc_timing
-
-	/* 设置sdram cs1复用关系，开发板使用ejtag_sel gpio_0引脚(第五复用)作为第二片sdram的片选
-	  注意sw2拨码开关的设置，使用ejtag烧录pmon时需要调整拨码开关，烧录完再调整回来 */
-	li	a0, 0xbfd011c0
-	lw	a1, 0x40(a0)
-	ori a1, 0x01
-	sw	a1, 0x40(a0)
-
-
-	bal locate
-	nop
-
-	/* restart, never die */
-	j	_start
-	nop
-#endif
-
-	.set	reorder
-
-	.globl  cp0_get_cause
-cp0_get_cause:
-	mfc0	v0, CP0_CAUSE
-	jr	ra
-	nop
-
-	.globl  cp0_get_status
-cp0_get_status:
-	mfc0	v0, CP0_STATUS
-	jr	ra
-	nop
-
-	.globl	cp0_get_hi
-cp0_get_hi:
-	mfhi	v0
-	jr	ra
-	nop
-
-	.globl	cp0_get_lo
-cp0_get_lo:
-	mflo	v0
-	jr	ra
-	nop
-
-#if defined(RT_USING_SELF_BOOT)
-
-/****************************************LOCATE*********************************/
-
-/*
- *  We get here from executing a bal to get the PC value of the current execute
- *  location into ra. Check to see if we run from ROM or if this is ramloaded.
- *  寄存器ra内保持着函数的返回地址，根据ra的值来判断当前是从ROM冷启动，还是从RAM热复位的
- *  ROM冷启动由通电引起，RAM热复位为各种异常引起，比如看门狗引起的复位等，
- *  也就是RAM热复位之前CPU已经开始运行了
- *  如果是从ROM冷启动，则寄存器ra的值为指令"bal	locate"所在位置加8字节，大概在0xBFC00000附近
- *  如果是从RAM热复位，则集成器ra的值为0x80xxxxxx
- */
-locate:
-//	la		s0, uncached
-//	subu	s0, ra, s0
-    /*
-     * start.s的这段汇编程序在ROM（入口点为0xBFC00000）中运行
-     * 而编译链接时指定的起始地址是0x80100000，所以需要修正一下地址
-     * s0中保存着ra与start的差值，在后续的代码中可以起到修正地址的作用
-     * 在看看文件开始的时候，对寄存器s0用途的描述是“         link versus load offset, used to relocate absolute adresses”
-     * 除了修正地址外，还通过s0的值来判断是从ROM冷启动，还是从RAM热启动
-     */
-		
-	la		s0, _start           // s0 = _start， 其中start的地址为编译链接时，指定的0x80010000
-	subu	s0, ra, s0          // s0 = ra - s0，其中ra的值在ROM入口地址0xBFC00000附近
-	and	s0, 0xffff0000          // s0 = s0 & 0xffff0000
-
-    /*
-     * 初始化cp0的status寄存器和cause寄存器
-     * 在异常引起的(从RAM)热复位后，需要重新初始化cp0的status和cause，
-     * 如果是从ROM冷启动的，那么前面已经初始化了，这里是再次重复初始化，没有影响的
-     */
-	li		t0, SR_BOOT_EXC_VEC
-	mtc0	t0, CP0_CONFIG        // 重新初始化cp0的status寄存器
-	mtc0	zero, CP0_CAUSE       // 重新清零cp0的cause寄存器
-	.set	noreorder
-    
-	li	t0, 0xbfe78030          // 地址0xbfe78030为PLL/SDRAM频率配置寄存器的地址
-	/* 设置PLL倍频 及SDRAM分频 */
-	li	t2, (0x80000008 | (PLL_MULT << 8) | (0x3 << 2) | SDRAM_DIV)
-	/* 设置CPU分频 */
-	li	t3, (0x00008003 | (CPU_DIV << 8))
-	/* 注意：首先需要把分频使能位清零 */
-	li	t1, 0x2
-	sw	t1, 0x4(t0)         // 清零CPU_DIV_VALID，即disable
-	sw	t2, 0x0(t0)         // 写寄存器START_FREQ
-	sw	t3, 0x4(t0)         // 写寄存器CLK_DIV_PARAM
-	DELAY(2000)
-
-	/* 芯片上电默认使用gpio(输入模式）但大多时候是使用模块的功能，如lcd i2c spi ac97等
-	   所以这里把gpio都关闭，方便使用模块功能。如果上电后需要gpio输出一个确定电平，
-	   如继电器、LDE等，可以修改这里的代码。*/
-	/* disable all gpio */
-	li a0,0xbfd00000
-	sw zero,0x10c0(a0)	/* disable gpio 0-31 */
-	sw zero,0x10c4(a0)	/* disable gpio 32-63 */
-	sw zero,0x10c8(a0)	/* disable gpio 64-95 */
-	sw zero,0x10cc(a0)
-
-	li t0, 0xffffffff
-	sw t0, 0x10d0(a0)
-	sw t0, 0x10d4(a0)
-	sw t0, 0x10d8(a0)
-	sw t0, 0x10dc(a0)
-
-	sw t0, 0x10f0(a0)
-	sw t0, 0x10f4(a0)
-	sw t0, 0x10f8(a0)
-	sw t0, 0x10fc(a0)
-
-
-	/* lcd soft_reset and panel config & timing */
-#ifdef DC_FB0
-/*	li a0, 0xbc301240
-	li a1, 0x00100103
-	sw a1, 0x0(a0)
-	li a1, 0x00000103
-	sw a1, 0x0(a0)		//soft_reset
-	li a1, 0x00100103
-	sw a1, 0x0(a0)
-
-	li a1, 0x80001111
-	sw a1, 0x180(a0)	//panel config
-	li a1, 0x33333333
-	sw a1, 0x1a0(a0)*/
-#endif
-
-	li output_en, 0x1
-#ifdef FAST_STARTUP
-	li a1, 0x03000000
-	sw a1, 0x10c4(a0)
-	sw a1, 0x10d4(a0)
-	lw a2, 0x10e4(a0)
-	and a2, a1
-	beq a2, a1, get_pin_val_finish
-	nop
-	li output_en, 0x1
-
-get_pin_val_finish:
-
-#endif
-
-	/* Initializing. Standby... */
-    /*
-     *  根据s0的值判断是否为ROM冷启动
-     *  如果s0不等于0，则是ROM冷启动；如果等于0，则是RAM热复位
-     *  冷启动，则需要初始化内存，cache，加载代码到内存等
-     */
-	bnez s0, 1f     // 如果寄存器s0不等于0，则说明是ROM冷启动，则跳转到下一个标号1处进行彻底初始化
-	nop
-	li a0, 128
-
-	jal rtthread_startup    // 热复位，则直接跳转到函数main
-	nop
-1:
-
-/* use only 8wins */
-#define CPU_WIN_BASE 0xbfd00000
-#define CPU_WIN_MASK 0xbfd00040
-#define CPU_WIN_MMAP 0xbfd00080
-
-#define set_cpu_window(id, base, mask, mmap) \
-        li      t0, CPU_WIN_BASE          ;  \
-        sw      $0, 0x80+id*8(t0)         ;  \
-        li      t1, base                  ;  \
-        sw      t1, 0x00+id*8(t0)         ;  \
-        sw      $0, 0x04+id*8(t0)         ;  \
-        li      t1, mask                  ;  \
-        sw      t1, 0x40+id*8(t0)         ;  \
-        sw      $0, 0x44+id*8(t0)         ;  \
-        li      t1, mmap                  ;  \
-        sw      t1, 0x80+id*8(t0)         ;  \
-        sw      $0, 0x84+id*8(t0)
-
-/* fixup cpu window */
-cpu_win_fixup:
-	//
-	// hit         = (paddr & mask) == (mmap & mask)
-	// mapped_addr =  paddr &~mask | mmap & mask
-	//
-	// mmap[7] -> enable
-	// mmap[5] -> block trans enable
-	// mmap[4] -> cachable
-	// mmap[1:0] -> destination
-	//
-	// NOTE: the address windows has priority, win0 > win1 > ... > win7
-
-/*	set_cpu_window(0, 0x1c280000, 0xfff80000, 0x1c280083) // camera 512K
-	set_cpu_window(1, 0x1c300000, 0xfff00000, 0x1c300081) // dc 1M
-	set_cpu_window(2, 0x1fe10000, 0xffffe000, 0x1fe10082) // gmac0	8K
-	set_cpu_window(3, 0x1fe10000, 0xffff0000, 0x1fe100d0) // gmac0	64K
-	set_cpu_window(4, 0x1f000000, 0xff000000, 0x1f000082) // AXIMUX   16M
-	set_cpu_window(5, 0x00000000, 0x00000000, 0x000000f0) // ddr 0
-	set_cpu_window(6, 0x00000000, 0x00000000, 0x000000f0) // ddr 0
-	set_cpu_window(7, 0x00000000, 0x00000000, 0x000000f0) // ddr 0*/
-
-/*	set_cpu_window(0, 0x1c280000, 0xfff80000, 0x1c2800d3) // camera
-//	set_cpu_window(1, 0x1fc00000, 0xfff00000, 0x1fc000f2) //
-	set_cpu_window(2, 0x1c300000, 0xfff00000, 0x1c3000d1) // dc 1M
-//	set_cpu_window(3, 0x1f000000, 0xff000000, 0x1f0000d2) //
-	set_cpu_window(4, 0x00000000, 0x00000000, 0x000000f0)
-	set_cpu_window(5, 0x00000000, 0x00000000, 0x000000f0)
-	set_cpu_window(6, 0x00000000, 0x00000000, 0x000000f0) // ddr 0
-	set_cpu_window(7, 0x00000000, 0x00000000, 0x000000f0) // ddr 0*/
-
-	// after this fixup, the kernel code should be compiled with
-	// uncached instruction fetch patch
-
-	/* 配置内存 */
-	li msize, MEM_SIZE    
-#if !defined(NAND_BOOT_EN)
-
-    /* 
-       手册建议，先写寄存器SD_CONFIG[31:0]，然后再写寄存器的SD_CONFIG[63:32]，
-       即先写低32位，再写高32位。
-       写三次寄存器，最后一次将最高位置一，即使能
-    */
-
-    // 写第一次
-	li  	t1, 0xbfd00410      // 寄存器SD_CONFIG[31:0]的地址为0xbfd00410
-	li		a1, SD_PARA0        // 宏SD_PARA0在sdram_cfg.S中定义的
-	sw		a1, 0x0(t1)         // 将宏SD_PARA0的值写入寄存器SD_CONFIG[31:0]
-	li		a1, SD_PARA1
-	sw		a1, 0x4(t1)         // 同理，将宏SD_PARA1的值写入寄存器SD_CONFIG[63:32]
-
-	// 写第二次
-	li		a1, SD_PARA0
-	sw		a1, 0x0(t1)
-	li		a1, SD_PARA1
-	sw		a1, 0x4(t1)
-
-    // 写第三次	
-	li		a1, SD_PARA0
-	sw		a1, 0x0(t1)
-	li		a1, SD_PARA1_EN     // 使能
-	sw		a1, 0x4(t1)
-//	DELAY(100)
-#endif
-
-	/**************************************CACHE*****************************/
-	
-#define CF_7_SE         (1 << 3)        /* Secondary cache enable */
-#define CF_7_SC         (1 << 31)       /* Secondary cache not present */
-#define CF_7_TE         (1 << 12)       /* Tertiary cache enable */
-#define CF_7_TC         (1 << 17)       /* Tertiary cache not present */
-#define CF_7_TS         (3 << 20)       /* Tertiary cache size */
-#define CF_7_TS_AL      20              /* Shift to align */
-#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop
-	
-do_caches:
-	/* Init caches... */
-	li	s7, 0					/* no L2 cache */
-	li	s8, 0					/* no L3 cache */
-
-	bal 	cache_init			// 调用汇编函数cache_init
-	nop
-
-	mfc0   a0, CP0_CONFIG 		// 将协处理器0的config寄存器的值加载到寄存器a0
-	and    a0, a0, ~((1<<12) | 7)	// a0 = a0 & ~((1<<12) | 7)
-	or	   a0, a0, 2				// a0 |= 2
-	mtc0   a0, CP0_CONFIG 		// 将寄存器a0的值写入协处理器0的config寄存器
-
-/***********************MEMORY DEBUGGING AND COPY SELF TO RAM***********************/
-//#include "newtest.32/mydebug.S"
-bootnow:
-	/* copy program to sdram to make copy fast */
-	/* 先将执行拷贝pmon到内存任务的代码，拷贝到内存0xa0000000 */
-	
-	/* 先确定需要拷贝的代码段为标号121到标号122之间的代码
-	 * 由于链接时指定的起始地址是0x80010000，
-	 * 而目前正在ROM（SPI NOR FLASH，起始地址为0xBFC00000）运行
-	 * 所以需要用寄存器s0来修正一下地址
-	 */
-	la		t0, 121f			// 将下一个标号121所在地址，加载到寄存器t0
-	addu	t0, s0				// 使用寄存器s0修正t0中的(标号121的)地址
-	la		t1, 122f			// 将下一个标号122所在地址，加载到寄存器t1
-	addu	t1, s0				// 使用寄存器s0修正t1中的(标号122的)地址
-	
-	li		t2, 0xa0000000		// 将立即数0xa0000000（起始地址）加载到寄存器t2
-1:
-	lw		v0, (t0)			// 将寄存器t0所指的内存地址开始4字节的数据加载到寄存器v0
-	sw		v0, (t2)			// 将寄存器v0的内容保存到寄存器t2所指的内存中
-	addu	t0, 4				// 寄存器t0向后移4字节
-	addu	t2, 4				// 寄存器t2向后移4字节
-	ble t0, t1, 1b				// 如果t0 <= t1，则跳转到上一个标号1处，继续拷贝后面的4字节
-	nop
-
-	li		t0, 0xa0000000		// 将立即数0xa0000000加载到寄存器t0
-	jr		t0					// 跳转到起始地址0xa0000000处开始执行（拷贝任务）
-	nop 	
-
-121: 
-	/* Copy PMON to execute location... */
-	/* 将固件拷贝到起始地址为0xa0010000的内存空间
-	   由于kseg0(0x8000 0000 - 0x9FFF FFFF)和kseg1(0xA000 0000 - 0xBFFF FFFF)是映射到物理内存的相同区域
-	   即拷贝到0xA000 0000开始的kseg1，就相当于拷贝到0x8000 0000开始的kseg0
-	   这就是为什么链接时，指定的地址是0x8001 0000，而拷贝的目标起始地址是0xA001 0000
-	*/
-	la		a0, _start			// 加载符号start所在地址0x80010000加载到寄存器a0中
-	addu	a1, a0, s0			// 使用寄存器s0修正寄存器a0中的地址，a1=0xBFC00000
-	la		a2, __bss_start			// 加载_edata（链接脚本中的一个符号）到寄存器a2
-	or		a0, 0xa0000000		// a0 = a0 | 0xa0000000 = 0xa0010000
-	or		a2, 0xa0000000		// a2 = a2 | 0xa0000000，修正地址_edata
-	subu	t1, a2, a0			// t1 = a2 - a0，即计算从start到_edata之间的长度（字节数）
-	srl t1, t1, 2				// t1 >>= 2，即t1除以4。(和前面类似，每次拷贝4字节，所以除以4)
-								// 似乎t1计算结果没有被使用，马上就被后面的覆盖了
-
-	move	t0, a0				// t0 = a0 = 0xa0010000 (目标起始地址)
-	move	t1, a1				// t1 = a1 = 0xBFC00000 (start在ROM中的地址，源起始地址)
-	move	t2, a2				// t2 = a2 (_edata在ROM中的地址，源结束地址)
-
-	/* copy text section */
-1:	and t3, t0, 0x0000ffff		// t3 = t0 & 0x0000ffff，取低16位
-	bnez	t3, 2f				// 如果t3不等于0，则跳转到下一个标号2处继续执行，t3的计算结果似乎没被使用，就被后面的覆盖了
-	nop
-2:	lw		t3, 0(t1)			// 从源地址t1处加载4字节到寄存器t3中
-	nop
-	sw		t3, 0(t0)			// 将寄存器t3中的4字节数据保存到目标地址t0处
-	addu	t0, 4				// 目标地址t0后移4字节
-	addu	t1, 4				// 源地址t1	  后移4字节
-	bne t2, t0, 1b				// 如果t2不等于t0，则跳到上一个标号1处继续拷贝，总的来说就是判断拷贝是否结束
-	nop
-	/* copy text section done. */
-	
-	/* clear bss */
-	la	t0, __bss_start
-	la	t1, __bss_end
-_clr_bss_loop:
-	sw	zero, 0(t0)
-	bne	t0, t1, _clr_bss_loop
-	addiu	t0, t0, 4
-
-	/* disable interrupt */
-	mfc0	t0, CP0_STATUS
-	and 	t0, 0xfffffffe	# By default it will be disabled.
-	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.
-	nop
-
-	/* disable cache */
-	mfc0	t0, CP0_CONFIG
-	and t0, 0xfffffff8
-	or	t0, 0x2 	# disable,!default value is not it!
-	mtc0	t0, CP0_CONFIG	# Set CPU to disable cache.
-	nop
-
-	/* jump to RT-Thread RTOS */
-	jal	rtthread_startup
-	nop
-
-	/* restart, never die */
-	j	_start
-	nop
-	
-
-122:
-
-stuck:
-	b	stuck
-	nop
-#endif
-
-	.extern tlb_refill_handler
-	.extern cache_error_handler
-
-	/* Exception Handler */
-
-	/* 0x0 - TLB refill handler */
-	.section .vectors.1, "ax", %progbits
-	.global tlb_refill_exception
-	.type	tlb_refill_exception,@function
-tlb_refill_exception:
-	j	tlb_refill_handler
-	nop
-	
-	/* 0x100 - Cache error handler */
-	.section .vectors.2, "ax", %progbits
-	j	cache_error_handler
-	nop
-    
-	/* 0x180 - Exception/Interrupt handler */
-	.section .vectors.3, "ax", %progbits
-	.global general_exception
-	.type	general_exception,@function
-general_exception:
-	j	_general_exception_handler
-	nop
-    
-	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-	.section .vectors.4, "ax", %progbits
-	.global irq_exception
-	.type	irq_exception,@function
-irq_exception:
-	j	_irq_handler
-	nop
-	
-	.section .vectors, "ax", %progbits
-	.extern mips_irq_handle
-
-	/* general exception handler */
-_general_exception_handler:
-	.set	noreorder
-	la	k0, mips_irq_handle
-	jr	k0
-	nop
-	.set	reorder
-
-	/* interrupt handler */
-_irq_handler:
-	.set	noreorder
-	la	k0, mips_irq_handle
-	jr	k0
-	nop
-	.set	reorder
-- 
cgit v1.3.1


From fdde8ab1982adabc71ab651e55160993dbdd9365 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Fri, 10 Jan 2020 10:38:21 +0800
Subject: add raspi2 and raspi3 BSP

---
 bsp/raspberry-pi/raspi2/.config                    | 292 ++++++++++
 bsp/raspberry-pi/raspi2/Kconfig                    |  28 +
 bsp/raspberry-pi/raspi2/README.md                  | 106 ++++
 bsp/raspberry-pi/raspi2/SConscript                 |  14 +
 bsp/raspberry-pi/raspi2/SConstruct                 |  28 +
 bsp/raspberry-pi/raspi2/applications/SConscript    |   9 +
 bsp/raspberry-pi/raspi2/applications/main.c        |  36 ++
 bsp/raspberry-pi/raspi2/applications/mnt.c         |  29 +
 bsp/raspberry-pi/raspi2/driver/Kconfig             |   3 +
 bsp/raspberry-pi/raspi2/driver/SConscript          |  17 +
 bsp/raspberry-pi/raspi2/driver/bcm283x.h           | 125 ++++
 bsp/raspberry-pi/raspi2/driver/board.c             |  90 +++
 bsp/raspberry-pi/raspi2/driver/board.h             |  42 ++
 bsp/raspberry-pi/raspi2/driver/drv_uart.c          | 199 +++++++
 bsp/raspberry-pi/raspi2/driver/drv_uart.h          |  56 ++
 bsp/raspberry-pi/raspi2/figures/raspi2.png         | Bin 0 -> 901488 bytes
 bsp/raspberry-pi/raspi2/figures/raspi_uart.png     | Bin 0 -> 1067143 bytes
 bsp/raspberry-pi/raspi2/kernel7.img                | Bin 0 -> 91456 bytes
 bsp/raspberry-pi/raspi2/link.lds                   | 149 +++++
 bsp/raspberry-pi/raspi2/rtconfig.h                 | 259 +++++++++
 bsp/raspberry-pi/raspi2/rtconfig.py                |  53 ++
 bsp/raspberry-pi/raspi3-32/.config                 | 427 ++++++++++++++
 bsp/raspberry-pi/raspi3-32/Kconfig                 |  28 +
 bsp/raspberry-pi/raspi3-32/README.md               | 153 +++++
 bsp/raspberry-pi/raspi3-32/SConscript              |  14 +
 bsp/raspberry-pi/raspi3-32/SConstruct              |  28 +
 bsp/raspberry-pi/raspi3-32/applications/SConscript |   9 +
 bsp/raspberry-pi/raspi3-32/applications/main.c     |  18 +
 bsp/raspberry-pi/raspi3-32/applications/mnt.c      |  29 +
 .../raspi3-32/applications/test_device.c           | 462 +++++++++++++++
 bsp/raspberry-pi/raspi3-32/cpu/SConscript          |   9 +
 bsp/raspberry-pi/raspi3-32/cpu/armv7.h             |  74 +++
 bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S       | 183 ++++++
 bsp/raspberry-pi/raspi3-32/cpu/cp15.h              | 168 ++++++
 bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S          | 147 +++++
 bsp/raspberry-pi/raspi3-32/cpu/cpu.c               |  91 +++
 bsp/raspberry-pi/raspi3-32/cpu/interrupt.c         | 186 ++++++
 bsp/raspberry-pi/raspi3-32/cpu/interrupt.h         |  18 +
 bsp/raspberry-pi/raspi3-32/cpu/mmu.c               | 188 ++++++
 bsp/raspberry-pi/raspi3-32/cpu/mmu.h               |  51 ++
 bsp/raspberry-pi/raspi3-32/cpu/stack.c             |  72 +++
 bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S         | 459 +++++++++++++++
 bsp/raspberry-pi/raspi3-32/cpu/trap.c              | 219 +++++++
 bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S        |  51 ++
 bsp/raspberry-pi/raspi3-32/driver/Kconfig          | 103 ++++
 bsp/raspberry-pi/raspi3-32/driver/SConscript       |  31 +
 bsp/raspberry-pi/raspi3-32/driver/board.c          | 182 ++++++
 bsp/raspberry-pi/raspi3-32/driver/board.h          |  29 +
 bsp/raspberry-pi/raspi3-32/driver/drv_fb.c         | 508 ++++++++++++++++
 bsp/raspberry-pi/raspi3-32/driver/drv_fb.h         |  60 ++
 bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c       | 318 ++++++++++
 bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h       |  42 ++
 bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c        | 238 ++++++++
 bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h        |  43 ++
 bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c        | 301 ++++++++++
 bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h        |  21 +
 bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c       | 580 +++++++++++++++++++
 bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h       | 253 ++++++++
 bsp/raspberry-pi/raspi3-32/driver/drv_spi.c        | 287 +++++++++
 bsp/raspberry-pi/raspi3-32/driver/drv_spi.h        | 102 ++++
 bsp/raspberry-pi/raspi3-32/driver/drv_timer.c      | 154 +++++
 bsp/raspberry-pi/raspi3-32/driver/drv_timer.h      |  27 +
 bsp/raspberry-pi/raspi3-32/driver/drv_uart.c       | 183 ++++++
 bsp/raspberry-pi/raspi3-32/driver/drv_uart.h       |  41 ++
 bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c        | 117 ++++
 bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h        |  26 +
 bsp/raspberry-pi/raspi3-32/driver/mbox.c           |  54 ++
 bsp/raspberry-pi/raspi3-32/driver/mbox.h           |  63 ++
 bsp/raspberry-pi/raspi3-32/driver/raspi.h          | 432 ++++++++++++++
 .../raspi3-32/figures/GPIO-Pinout-Diagram-2.png    | Bin 0 -> 206936 bytes
 .../raspi3-32/figures/raspberrypi-console.png      | Bin 0 -> 1356117 bytes
 bsp/raspberry-pi/raspi3-32/figures/raspi3_b.jpg    | Bin 0 -> 184309 bytes
 bsp/raspberry-pi/raspi3-32/figures/raspi3_f.jpg    | Bin 0 -> 225139 bytes
 bsp/raspberry-pi/raspi3-32/link.lds                | 149 +++++
 bsp/raspberry-pi/raspi3-32/rtconfig.h              | 391 +++++++++++++
 bsp/raspberry-pi/raspi3-32/rtconfig.py             |  52 ++
 bsp/raspberry-pi/raspi3-64/.config                 | 418 ++++++++++++++
 bsp/raspberry-pi/raspi3-64/.cproject               | 150 +++++
 bsp/raspberry-pi/raspi3-64/.project                |  54 ++
 bsp/raspberry-pi/raspi3-64/Kconfig                 |  29 +
 bsp/raspberry-pi/raspi3-64/README.md               | 100 ++++
 bsp/raspberry-pi/raspi3-64/SConscript              |  14 +
 bsp/raspberry-pi/raspi3-64/SConstruct              |  30 +
 bsp/raspberry-pi/raspi3-64/applications/SConscript |   9 +
 bsp/raspberry-pi/raspi3-64/applications/main.c     |  19 +
 bsp/raspberry-pi/raspi3-64/applications/mnt.c      |  16 +
 .../raspi3-64/applications/test/gpio.h             |  45 ++
 .../raspi3-64/applications/test/uart.c             | 103 ++++
 .../raspi3-64/applications/test/uart.h             |  29 +
 bsp/raspberry-pi/raspi3-64/driver/Kconfig          | 112 ++++
 bsp/raspberry-pi/raspi3-64/driver/SConscript       |  32 +
 bsp/raspberry-pi/raspi3-64/driver/bcm283x.c        | 575 ++++++++++++++++++
 bsp/raspberry-pi/raspi3-64/driver/bcm283x.h        | 641 +++++++++++++++++++++
 bsp/raspberry-pi/raspi3-64/driver/board.c          | 298 ++++++++++
 bsp/raspberry-pi/raspi3-64/driver/board.h          |  29 +
 bsp/raspberry-pi/raspi3-64/driver/drv_fb.c         | 523 +++++++++++++++++
 bsp/raspberry-pi/raspi3-64/driver/drv_fb.h         |  60 ++
 bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c       | 473 +++++++++++++++
 bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h       |  42 ++
 bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c        | 177 ++++++
 bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h        |  43 ++
 bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c        | 135 +++++
 bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h        |  26 +
 bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c       | 532 +++++++++++++++++
 bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h       | 345 +++++++++++
 bsp/raspberry-pi/raspi3-64/driver/drv_spi.c        | 396 +++++++++++++
 bsp/raspberry-pi/raspi3-64/driver/drv_spi.h        |  68 +++
 bsp/raspberry-pi/raspi3-64/driver/drv_timer.c      | 141 +++++
 bsp/raspberry-pi/raspi3-64/driver/drv_timer.h      |  24 +
 bsp/raspberry-pi/raspi3-64/driver/drv_uart.c       | 184 ++++++
 bsp/raspberry-pi/raspi3-64/driver/drv_uart.h       |  42 ++
 bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c        | 140 +++++
 bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h        |  29 +
 bsp/raspberry-pi/raspi3-64/driver/mbox.c           |  53 ++
 bsp/raspberry-pi/raspi3-64/driver/mbox.h           |  62 ++
 bsp/raspberry-pi/raspi3-64/driver/raspi.h          |  70 +++
 bsp/raspberry-pi/raspi3-64/figures/raspi_uart.png  | Bin 0 -> 1067143 bytes
 bsp/raspberry-pi/raspi3-64/kernel8.img             | Bin 0 -> 163872 bytes
 bsp/raspberry-pi/raspi3-64/link.lds                | 151 +++++
 bsp/raspberry-pi/raspi3-64/qemu-64.bat             |   1 +
 bsp/raspberry-pi/raspi3-64/rtconfig.h              | 382 ++++++++++++
 bsp/raspberry-pi/raspi3-64/rtconfig.py             |  54 ++
 bsp/raspi2/.config                                 | 292 ----------
 bsp/raspi2/Kconfig                                 |  28 -
 bsp/raspi2/README.md                               | 106 ----
 bsp/raspi2/SConscript                              |  14 -
 bsp/raspi2/SConstruct                              |  28 -
 bsp/raspi2/applications/SConscript                 |   9 -
 bsp/raspi2/applications/main.c                     |  36 --
 bsp/raspi2/applications/mnt.c                      |  29 -
 bsp/raspi2/cpu/SConscript                          |   9 -
 bsp/raspi2/cpu/armv7.h                             |  64 --
 bsp/raspi2/cpu/context_gcc.S                       | 105 ----
 bsp/raspi2/cpu/cp15.h                              |  12 -
 bsp/raspi2/cpu/cp15_gcc.S                          | 140 -----
 bsp/raspi2/cpu/cpu.c                               |  37 --
 bsp/raspi2/cpu/interrupt.c                         | 136 -----
 bsp/raspi2/cpu/mmu.c                               | 207 -------
 bsp/raspi2/cpu/stack.c                             |  68 ---
 bsp/raspi2/cpu/start_gcc.S                         | 280 ---------
 bsp/raspi2/cpu/trap.c                              | 183 ------
 bsp/raspi2/cpu/vector_gcc.S                        |  65 ---
 bsp/raspi2/driver/Kconfig                          |   3 -
 bsp/raspi2/driver/SConscript                       |  17 -
 bsp/raspi2/driver/bcm283x.h                        | 125 ----
 bsp/raspi2/driver/board.c                          |  90 ---
 bsp/raspi2/driver/board.h                          |  42 --
 bsp/raspi2/driver/drv_uart.c                       | 199 -------
 bsp/raspi2/driver/drv_uart.h                       |  56 --
 bsp/raspi2/figures/raspi2.png                      | Bin 901488 -> 0 bytes
 bsp/raspi2/figures/raspi_uart.png                  | Bin 1067143 -> 0 bytes
 bsp/raspi2/link.lds                                | 149 -----
 bsp/raspi2/rtconfig.h                              | 259 ---------
 bsp/raspi2/rtconfig.py                             |  53 --
 libcpu/aarch64/SConscript                          |  16 +
 libcpu/aarch64/cortex-a53/SConscript               |  15 +
 libcpu/aarch64/cortex-a53/armv8.h                  |  63 ++
 libcpu/aarch64/cortex-a53/context_gcc.S            | 307 ++++++++++
 libcpu/aarch64/cortex-a53/cp15.h                   | 167 ++++++
 libcpu/aarch64/cortex-a53/cpu.c                    |  91 +++
 libcpu/aarch64/cortex-a53/cpu_gcc.S                |  78 +++
 libcpu/aarch64/cortex-a53/entry_point.S            | 102 ++++
 libcpu/aarch64/cortex-a53/interrupt.c              | 183 ++++++
 libcpu/aarch64/cortex-a53/interrupt.h              |  20 +
 libcpu/aarch64/cortex-a53/mmu.c                    | 186 ++++++
 libcpu/aarch64/cortex-a53/mmu.h                    |  51 ++
 libcpu/aarch64/cortex-a53/stack.c                  |  90 +++
 libcpu/aarch64/cortex-a53/startup_gcc.S            |  13 +
 libcpu/aarch64/cortex-a53/trap.c                   | 221 +++++++
 libcpu/aarch64/cortex-a53/vector_gcc.S             |  57 ++
 libcpu/arm/cortex-a53/SConscript                   |   9 +
 libcpu/arm/cortex-a53/armv7.h                      |  74 +++
 libcpu/arm/cortex-a53/context_gcc.S                | 183 ++++++
 libcpu/arm/cortex-a53/cp15.h                       | 168 ++++++
 libcpu/arm/cortex-a53/cp15_gcc.S                   | 147 +++++
 libcpu/arm/cortex-a53/cpu.c                        |  91 +++
 libcpu/arm/cortex-a53/interrupt.c                  | 186 ++++++
 libcpu/arm/cortex-a53/interrupt.h                  |  18 +
 libcpu/arm/cortex-a53/mmu.c                        | 188 ++++++
 libcpu/arm/cortex-a53/mmu.h                        |  51 ++
 libcpu/arm/cortex-a53/stack.c                      |  72 +++
 libcpu/arm/cortex-a53/start_gcc.S                  | 459 +++++++++++++++
 libcpu/arm/cortex-a53/trap.c                       | 219 +++++++
 libcpu/arm/cortex-a53/vector_gcc.S                 |  51 ++
 libcpu/arm/cortex-a7/SConscript                    |   9 +
 libcpu/arm/cortex-a7/armv7.h                       |  64 ++
 libcpu/arm/cortex-a7/context_gcc.S                 | 105 ++++
 libcpu/arm/cortex-a7/cp15.h                        |  12 +
 libcpu/arm/cortex-a7/cp15_gcc.S                    | 140 +++++
 libcpu/arm/cortex-a7/cpu.c                         |  37 ++
 libcpu/arm/cortex-a7/interrupt.c                   | 136 +++++
 libcpu/arm/cortex-a7/mmu.c                         | 207 +++++++
 libcpu/arm/cortex-a7/stack.c                       |  68 +++
 libcpu/arm/cortex-a7/start_gcc.S                   | 280 +++++++++
 libcpu/arm/cortex-a7/trap.c                        | 183 ++++++
 libcpu/arm/cortex-a7/vector_gcc.S                  |  65 +++
 196 files changed, 21144 insertions(+), 2841 deletions(-)
 create mode 100644 bsp/raspberry-pi/raspi2/.config
 create mode 100644 bsp/raspberry-pi/raspi2/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi2/README.md
 create mode 100644 bsp/raspberry-pi/raspi2/SConscript
 create mode 100644 bsp/raspberry-pi/raspi2/SConstruct
 create mode 100644 bsp/raspberry-pi/raspi2/applications/SConscript
 create mode 100644 bsp/raspberry-pi/raspi2/applications/main.c
 create mode 100644 bsp/raspberry-pi/raspi2/applications/mnt.c
 create mode 100644 bsp/raspberry-pi/raspi2/driver/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi2/driver/SConscript
 create mode 100644 bsp/raspberry-pi/raspi2/driver/bcm283x.h
 create mode 100644 bsp/raspberry-pi/raspi2/driver/board.c
 create mode 100644 bsp/raspberry-pi/raspi2/driver/board.h
 create mode 100644 bsp/raspberry-pi/raspi2/driver/drv_uart.c
 create mode 100644 bsp/raspberry-pi/raspi2/driver/drv_uart.h
 create mode 100644 bsp/raspberry-pi/raspi2/figures/raspi2.png
 create mode 100644 bsp/raspberry-pi/raspi2/figures/raspi_uart.png
 create mode 100755 bsp/raspberry-pi/raspi2/kernel7.img
 create mode 100644 bsp/raspberry-pi/raspi2/link.lds
 create mode 100644 bsp/raspberry-pi/raspi2/rtconfig.h
 create mode 100644 bsp/raspberry-pi/raspi2/rtconfig.py
 create mode 100644 bsp/raspberry-pi/raspi3-32/.config
 create mode 100644 bsp/raspberry-pi/raspi3-32/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi3-32/README.md
 create mode 100644 bsp/raspberry-pi/raspi3-32/SConscript
 create mode 100644 bsp/raspberry-pi/raspi3-32/SConstruct
 create mode 100644 bsp/raspberry-pi/raspi3-32/applications/SConscript
 create mode 100644 bsp/raspberry-pi/raspi3-32/applications/main.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/applications/mnt.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/applications/test_device.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/SConscript
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/armv7.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/cp15.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/cpu.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/interrupt.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/interrupt.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/mmu.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/mmu.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/stack.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/trap.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/SConscript
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/board.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/board.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_fb.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_fb.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_spi.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_spi.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_timer.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_timer.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_uart.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_uart.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/mbox.c
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/mbox.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/driver/raspi.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/figures/GPIO-Pinout-Diagram-2.png
 create mode 100644 bsp/raspberry-pi/raspi3-32/figures/raspberrypi-console.png
 create mode 100644 bsp/raspberry-pi/raspi3-32/figures/raspi3_b.jpg
 create mode 100644 bsp/raspberry-pi/raspi3-32/figures/raspi3_f.jpg
 create mode 100644 bsp/raspberry-pi/raspi3-32/link.lds
 create mode 100644 bsp/raspberry-pi/raspi3-32/rtconfig.h
 create mode 100644 bsp/raspberry-pi/raspi3-32/rtconfig.py
 create mode 100644 bsp/raspberry-pi/raspi3-64/.config
 create mode 100644 bsp/raspberry-pi/raspi3-64/.cproject
 create mode 100644 bsp/raspberry-pi/raspi3-64/.project
 create mode 100644 bsp/raspberry-pi/raspi3-64/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi3-64/README.md
 create mode 100644 bsp/raspberry-pi/raspi3-64/SConscript
 create mode 100644 bsp/raspberry-pi/raspi3-64/SConstruct
 create mode 100644 bsp/raspberry-pi/raspi3-64/applications/SConscript
 create mode 100644 bsp/raspberry-pi/raspi3-64/applications/main.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/applications/mnt.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/applications/test/gpio.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/applications/test/uart.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/applications/test/uart.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/SConscript
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/board.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/board.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_timer.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_uart.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/mbox.c
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/mbox.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/driver/raspi.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/figures/raspi_uart.png
 create mode 100755 bsp/raspberry-pi/raspi3-64/kernel8.img
 create mode 100644 bsp/raspberry-pi/raspi3-64/link.lds
 create mode 100644 bsp/raspberry-pi/raspi3-64/qemu-64.bat
 create mode 100644 bsp/raspberry-pi/raspi3-64/rtconfig.h
 create mode 100644 bsp/raspberry-pi/raspi3-64/rtconfig.py
 delete mode 100644 bsp/raspi2/.config
 delete mode 100644 bsp/raspi2/Kconfig
 delete mode 100644 bsp/raspi2/README.md
 delete mode 100644 bsp/raspi2/SConscript
 delete mode 100644 bsp/raspi2/SConstruct
 delete mode 100644 bsp/raspi2/applications/SConscript
 delete mode 100644 bsp/raspi2/applications/main.c
 delete mode 100644 bsp/raspi2/applications/mnt.c
 delete mode 100644 bsp/raspi2/cpu/SConscript
 delete mode 100644 bsp/raspi2/cpu/armv7.h
 delete mode 100644 bsp/raspi2/cpu/context_gcc.S
 delete mode 100644 bsp/raspi2/cpu/cp15.h
 delete mode 100644 bsp/raspi2/cpu/cp15_gcc.S
 delete mode 100644 bsp/raspi2/cpu/cpu.c
 delete mode 100644 bsp/raspi2/cpu/interrupt.c
 delete mode 100644 bsp/raspi2/cpu/mmu.c
 delete mode 100644 bsp/raspi2/cpu/stack.c
 delete mode 100644 bsp/raspi2/cpu/start_gcc.S
 delete mode 100644 bsp/raspi2/cpu/trap.c
 delete mode 100644 bsp/raspi2/cpu/vector_gcc.S
 delete mode 100644 bsp/raspi2/driver/Kconfig
 delete mode 100644 bsp/raspi2/driver/SConscript
 delete mode 100644 bsp/raspi2/driver/bcm283x.h
 delete mode 100644 bsp/raspi2/driver/board.c
 delete mode 100644 bsp/raspi2/driver/board.h
 delete mode 100644 bsp/raspi2/driver/drv_uart.c
 delete mode 100644 bsp/raspi2/driver/drv_uart.h
 delete mode 100644 bsp/raspi2/figures/raspi2.png
 delete mode 100644 bsp/raspi2/figures/raspi_uart.png
 delete mode 100644 bsp/raspi2/link.lds
 delete mode 100644 bsp/raspi2/rtconfig.h
 delete mode 100644 bsp/raspi2/rtconfig.py
 create mode 100644 libcpu/aarch64/SConscript
 create mode 100644 libcpu/aarch64/cortex-a53/SConscript
 create mode 100644 libcpu/aarch64/cortex-a53/armv8.h
 create mode 100644 libcpu/aarch64/cortex-a53/context_gcc.S
 create mode 100644 libcpu/aarch64/cortex-a53/cp15.h
 create mode 100644 libcpu/aarch64/cortex-a53/cpu.c
 create mode 100644 libcpu/aarch64/cortex-a53/cpu_gcc.S
 create mode 100644 libcpu/aarch64/cortex-a53/entry_point.S
 create mode 100644 libcpu/aarch64/cortex-a53/interrupt.c
 create mode 100644 libcpu/aarch64/cortex-a53/interrupt.h
 create mode 100644 libcpu/aarch64/cortex-a53/mmu.c
 create mode 100644 libcpu/aarch64/cortex-a53/mmu.h
 create mode 100644 libcpu/aarch64/cortex-a53/stack.c
 create mode 100644 libcpu/aarch64/cortex-a53/startup_gcc.S
 create mode 100644 libcpu/aarch64/cortex-a53/trap.c
 create mode 100644 libcpu/aarch64/cortex-a53/vector_gcc.S
 create mode 100644 libcpu/arm/cortex-a53/SConscript
 create mode 100644 libcpu/arm/cortex-a53/armv7.h
 create mode 100644 libcpu/arm/cortex-a53/context_gcc.S
 create mode 100644 libcpu/arm/cortex-a53/cp15.h
 create mode 100644 libcpu/arm/cortex-a53/cp15_gcc.S
 create mode 100644 libcpu/arm/cortex-a53/cpu.c
 create mode 100644 libcpu/arm/cortex-a53/interrupt.c
 create mode 100644 libcpu/arm/cortex-a53/interrupt.h
 create mode 100644 libcpu/arm/cortex-a53/mmu.c
 create mode 100644 libcpu/arm/cortex-a53/mmu.h
 create mode 100644 libcpu/arm/cortex-a53/stack.c
 create mode 100644 libcpu/arm/cortex-a53/start_gcc.S
 create mode 100644 libcpu/arm/cortex-a53/trap.c
 create mode 100644 libcpu/arm/cortex-a53/vector_gcc.S
 create mode 100644 libcpu/arm/cortex-a7/SConscript
 create mode 100644 libcpu/arm/cortex-a7/armv7.h
 create mode 100644 libcpu/arm/cortex-a7/context_gcc.S
 create mode 100644 libcpu/arm/cortex-a7/cp15.h
 create mode 100644 libcpu/arm/cortex-a7/cp15_gcc.S
 create mode 100644 libcpu/arm/cortex-a7/cpu.c
 create mode 100644 libcpu/arm/cortex-a7/interrupt.c
 create mode 100644 libcpu/arm/cortex-a7/mmu.c
 create mode 100644 libcpu/arm/cortex-a7/stack.c
 create mode 100644 libcpu/arm/cortex-a7/start_gcc.S
 create mode 100644 libcpu/arm/cortex-a7/trap.c
 create mode 100644 libcpu/arm/cortex-a7/vector_gcc.S

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi2/.config b/bsp/raspberry-pi/raspi2/.config
new file mode 100644
index 0000000000..e7ce89e6c8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/.config
@@ -0,0 +1,292 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+# CONFIG_RT_USING_MODULE is not set
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_A=y
+CONFIG_ARCH_ARM_CORTEX_A7=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_AUDIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_STM32F4_HAL is not set
+# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+# CONFIG_PKG_USING_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_BCM2836_SOC=y
+CONFIG_RT_USING_UART1=y
diff --git a/bsp/raspberry-pi/raspi2/Kconfig b/bsp/raspberry-pi/raspi2/Kconfig
new file mode 100644
index 0000000000..f7693c8378
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/Kconfig
@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2836_SOC
+    bool
+    select ARCH_ARM_CORTEX_A7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "driver/Kconfig"
diff --git a/bsp/raspberry-pi/raspi2/README.md b/bsp/raspberry-pi/raspi2/README.md
new file mode 100644
index 0000000000..d65a954728
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/README.md
@@ -0,0 +1,106 @@
+# Raspberry PI 2B板级支持包说明
+
+## 1. 简介
+
+树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派2采用4核Broadcom BCM2836 (ARMv7-A)芯片、双核VideoCore IV GPU和1GB内存。
+
+这份RT-Thread BSP是针对 Raspberry Pi 2B 的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+![raspi2](figures/raspi2.png)
+
+当前Raspberry Pi 2B对应的硬件特性：
+
+| 硬件   | 描述 |
+|------- | ------------------------------- |
+|  CPU   | ARM Cortex-A7（4核心） |
+|  主频  | 900M |
+| Memory | 1GB  (0x0000000 - 0x40000000) |
+| | 其中0x3f000000 - 0x40000000为peripheral |
+
+## 2. 编译说明
+
+Windows环境下推荐使用[env工具][1]进行编译。
+
+Linux下推荐使用gcc工具 [gcc-arm-none-eabi-4_8-2014q1_linux][2]，如果还没有编译工具，下载后，解开文件。
+
+```
+tar vxf gcc-arm-none-eabi-4_8-2014q1_linux.tar.bz2
+```
+
+Linux环境下需要修改编译器目录设置，修改`bsp/raspi2/rtconfig.py`中的
+
+```
+EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+```
+
+为编译工具的实际所在目录，这里注意要加上后缀 `/bin`
+
+进入到`rt-thread/bsp/raspi2`目录中，运行以下命令：
+
+```
+scons
+```
+
+来编译这个板级支持包。如果编译正确无误，会产生kernel.elf、kernel.img文件。
+kernel.img即是要cp到raspberry SD卡中根目录的文件
+
+## 3. 执行
+
+### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
+
+Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
+
+解开下载的镜像文件, linux下使用如下的命令
+
+```
+unzip 2018-06-27-raspbian-stretch-lite.zip
+```
+
+准备一张空SD卡，linux环境下，插入电脑并执行
+
+```
+sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
+```
+
+**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
+
+Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
+
+最后把kernel7.img放入SD boot分区，覆盖原来的文件。
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi2的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
+
+![raspi2](figures/raspi_uart.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+按上面的方法做好SD卡后，插入树莓派2B，通电可以在串口上看到如下所示的输出信息：
+
+```text
+ heap: 0x00020b20 - 0x00400000
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     3.1.0 build Aug 23 2018
+ 2006 - 2018 Copyright by rt-thread team
+Hello RT-Thread!
+msh >
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2
+  [3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+  [4]: https://etcher.io
+  [5]: https://github.com/BernardXiong
diff --git a/bsp/raspberry-pi/raspi2/SConscript b/bsp/raspberry-pi/raspi2/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/raspberry-pi/raspi2/SConstruct b/bsp/raspberry-pi/raspi2/SConstruct
new file mode 100644
index 0000000000..e94a364d9d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/SConstruct
@@ -0,0 +1,28 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/raspberry-pi/raspi2/applications/SConscript b/bsp/raspberry-pi/raspi2/applications/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi2/applications/main.c b/bsp/raspberry-pi/raspi2/applications/main.c
new file mode 100644
index 0000000000..101386fdfd
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/applications/main.c
@@ -0,0 +1,36 @@
+/*
+ * File      : main.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <rtthread.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hello RT-Thread!\n");
+
+    return 0;
+}
+
diff --git a/bsp/raspberry-pi/raspi2/applications/mnt.c b/bsp/raspberry-pi/raspi2/applications/mnt.c
new file mode 100644
index 0000000000..8da1dc1ece
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/applications/mnt.c
@@ -0,0 +1,29 @@
+/*
+ * File      : mnt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rtthread.h>
+
+int mnt_init(void)
+{
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi2/driver/Kconfig b/bsp/raspberry-pi/raspi2/driver/Kconfig
new file mode 100644
index 0000000000..95c536178d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/driver/Kconfig
@@ -0,0 +1,3 @@
+config RT_USING_UART1
+    bool "Enable UART1"
+    default y
diff --git a/bsp/raspberry-pi/raspi2/driver/SConscript b/bsp/raspberry-pi/raspi2/driver/SConscript
new file mode 100644
index 0000000000..25e7ef2e55
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/driver/SConscript
@@ -0,0 +1,17 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split('''
+board.c
+drv_uart.c
+''')
+CPPPATH = [cwd]
+
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi2/driver/bcm283x.h b/bsp/raspberry-pi/raspi2/driver/bcm283x.h
new file mode 100644
index 0000000000..85422e2a22
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/driver/bcm283x.h
@@ -0,0 +1,125 @@
+#ifndef BCM283X_H__
+#define BCM283X_H__
+
+#include <rthw.h>
+
+#define PER_BASE    		(0x3F000000)
+#define PER_BASE_40000000 	(0x40000000)
+
+/*
+ *  GPIO
+ */
+#define GPIO_BASE       (PER_BASE + 0x200000)
+#define GPIO_GPFSEL0    HWREG32(GPIO_BASE + 0x00)  /* GPIO Function Select 0 32bit R/W */
+#define GPIO_GPFSEL1    HWREG32(GPIO_BASE + 0x04)  /* GPIO Function Select 1 32bit R/W */
+#define GPIO_GPFSEL2    HWREG32(GPIO_BASE + 0x08)  /* GPIO Function Select 2 32bit R/W */
+#define GPIO_GPFSEL4    HWREG32(GPIO_BASE + 0x10)  /* GPIO Function Select 4 32bit R/W */
+#define GPIO_GPSET0     HWREG32(GPIO_BASE + 0x1C)
+#define GPIO_GPCLR0     HWREG32(GPIO_BASE + 0x28)
+#define GPIO_GPPUD      HWREG32(GPIO_BASE + 0x94)  /* GPIO Pin Pull-up/down Enable */
+#define GPIO_GPPUDCLK0  HWREG32(GPIO_BASE + 0x98)  /* GPIO Pin Pull-up/down Enable Clock 0 */
+#define GPIO_GPPUDCLK1  HWREG32(GPIO_BASE + 0x9C)  /* GPIO Pin Pull-up/down Enable Clock 1 */
+
+/*
+ *  Interrupt Controler
+ */
+#define IRQ_BASE            (PER_BASE + 0xB200)
+#define IRQ_PEND_BASIC      HWREG32(IRQ_BASE + 0x00)
+#define IRQ_PEND1           HWREG32(IRQ_BASE + 0x04)
+#define IRQ_PEND2           HWREG32(IRQ_BASE + 0x08)
+#define IRQ_FIQ_CONTROL     HWREG32(IRQ_BASE + 0x0C)
+#define IRQ_ENABLE1         HWREG32(IRQ_BASE + 0x10)
+#define IRQ_ENABLE2         HWREG32(IRQ_BASE + 0x14)
+#define IRQ_ENABLE_BASIC    HWREG32(IRQ_BASE + 0x18)
+#define IRQ_DISABLE1        HWREG32(IRQ_BASE + 0x1C)
+#define IRQ_DISABLE2        HWREG32(IRQ_BASE + 0x20)
+#define IRQ_DISABLE_BASIC   HWREG32(IRQ_BASE + 0x24)
+
+/*
+ *  System Timer
+ */
+#define STIMER_BASE         (PER_BASE  + 0x3000)
+#define STIMER_CS           HWREG32(STIMER_BASE + 0x00)
+#define STIMER_CLO          HWREG32(STIMER_BASE + 0x04)
+#define STIMER_CHI          HWREG32(STIMER_BASE + 0x08)
+#define STIMER_C0           HWREG32(STIMER_BASE + 0x0C)
+#define STIMER_C1           HWREG32(STIMER_BASE + 0x10)
+#define STIMER_C2           HWREG32(STIMER_BASE + 0x14)
+#define STIMER_C3           HWREG32(STIMER_BASE + 0x18)
+
+/*
+ * ARM Timer
+ */
+#define ARM_TIMER_BASE		(PER_BASE + 0xB000)
+
+#define ARM_TIMER_LOAD		HWREG32(ARM_TIMER_BASE + 0x400)
+#define ARM_TIMER_VALUE		HWREG32(ARM_TIMER_BASE + 0x404)
+#define ARM_TIMER_CTRL		HWREG32(ARM_TIMER_BASE + 0x408)
+#define ARM_TIMER_IRQCLR	HWREG32(ARM_TIMER_BASE + 0x40C)
+#define ARM_TIMER_RAWIRQ	HWREG32(ARM_TIMER_BASE + 0x410)
+#define ARM_TIMER_MASKIRQ	HWREG32(ARM_TIMER_BASE + 0x414)
+#define ARM_TIMER_RELOAD	HWREG32(ARM_TIMER_BASE + 0x418)
+#define ARM_TIMER_PREDIV	HWREG32(ARM_TIMER_BASE + 0x41C)
+#define ARM_TIMER_CNTR		HWREG32(ARM_TIMER_BASE + 0x420)
+
+/*
+ *  Core Timer
+ */
+#define CTIMER_CTL          HWREG32(PER_BASE_40000000 + 0x00)  /* Control register */
+#define CTIMER_PRE          HWREG32(PER_BASE_40000000 + 0x08)  /* Core timer prescaler */
+#define CTIMER_LS32B        HWREG32(PER_BASE_40000000 + 0x1C)  /* Core timer access LS 32 bits */
+#define CTIMER_MS32B        HWREG32(PER_BASE_40000000 + 0x20)  /* Core timer access MS 32 bits */
+
+/*
+ *  ARM Core Timer
+ */
+#define C0TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x40)  /* Core0 timers Interrupt control */
+#define C1TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x44)  /* Core1 timers Interrupt control */
+#define C2TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x48)  /* Core2 timers Interrupt control */
+#define C3TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x4C)  /* Core3 timers Interrupt control */
+
+/*
+ *  ARM Core Mailbox interrupt
+ */
+#define C0MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x50)  /* Core0 Mailboxes Interrupt control */
+#define C1MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x54)  /* Core1 Mailboxes Interrupt control */
+#define C2MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x58)  /* Core2 Mailboxes Interrupt control */
+#define C3MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x5C)  /* Core3 Mailboxes Interrupt control */
+
+/*
+ *  ARM Core IRQ/FIQ status
+ */
+#define C0_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x60)  /* Core0 IRQ Source */
+#define C1_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x64)  /* Core1 IRQ Source */
+#define C2_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x68)  /* Core2 IRQ Source */
+#define C3_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x6C)  /* Core3 IRQ Source */
+#define C0_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x70)  /* Core0 FIQ Source */
+#define C1_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x74)  /* Core1 FIQ Source */
+#define C2_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x78)  /* Core2 FIQ Source */
+#define C3_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x7C)  /* Core3 FIQ Source */
+
+#define IRQ_ARM_TIMER           0
+#define IRQ_ARM_MAILBOX         1
+#define IRQ_ARM_DB0             2
+#define IRQ_ARM_DB1             3
+#define IRQ_ARM_GPU0_HALT       4
+#define IRQ_ARM_GPU1_HALT       5
+#define IRQ_ARM_ILLEGAL_ACC1    6
+#define IRQ_ARM_ILLEGAL_ACC0    7
+
+#define IRQ_AUX                 29
+#define IRQ_IIC_SPI_SLV         43
+#define IRQ_PWA0                45
+#define IRQ_PWA1                46
+#define IRQ_SMI                 48
+#define IRQ_GPIO0               49
+#define IRQ_GPIO1               50
+#define IRQ_GPIO2               51
+#define IRQ_GPIO3               52
+#define IRQ_IIC                 53
+#define IRQ_SPI                 54
+#define IRQ_PCM                 55
+#define IRQ_UART                57
+
+#endif
+
diff --git a/bsp/raspberry-pi/raspi2/driver/board.c b/bsp/raspberry-pi/raspi2/driver/board.c
new file mode 100644
index 0000000000..30f8cd93a1
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/driver/board.c
@@ -0,0 +1,90 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    ARM_TIMER_IRQCLR = 0;
+
+    rt_tick_increase();
+}
+
+int rt_hw_timer_init(void)
+{
+    /* timer_clock = apb_clock/(pre_divider + 1) */
+    ARM_TIMER_PREDIV = (250 - 1);
+
+    ARM_TIMER_RELOAD = 0;
+    ARM_TIMER_LOAD   = 0;
+    ARM_TIMER_IRQCLR = 0;
+    ARM_TIMER_CTRL   = 0;
+
+    ARM_TIMER_RELOAD = 10000;
+    ARM_TIMER_LOAD   = 10000;
+
+    /* 23-bit counter, enable interrupt, enable timer */
+    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
+
+    rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IRQ_ARM_TIMER);
+
+    return 0;
+}
+
+void vector_copy(void)
+{
+    rt_memcpy((void*)0x0, (void*)0x8000, 64);
+}
+
+void rt_hw_board_init(void)
+{
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
+    vector_copy();
+
+    /* initialize uart */
+    rt_hw_uart_init();
+
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+    /* initialize timer for os tick */
+    // rt_hw_timer_init();
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
diff --git a/bsp/raspberry-pi/raspi2/driver/board.h b/bsp/raspberry-pi/raspi2/driver/board.h
new file mode 100644
index 0000000000..92ef5de76c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/driver/board.h
@@ -0,0 +1,42 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+
+#include <rthw.h>
+#include <bcm283x.h>
+
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(0x0 + 4 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
+
diff --git a/bsp/raspberry-pi/raspi2/driver/drv_uart.c b/bsp/raspberry-pi/raspi2/driver/drv_uart.c
new file mode 100644
index 0000000000..de7b987c2a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/driver/drv_uart.c
@@ -0,0 +1,199 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/5/5       Bernard      The first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include <rtdevice.h>
+
+#define AUX_BASE            (0x3F000000 + 0x215000)
+
+struct hw_uart_device
+{
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if (uart->hw_base == AUX_BASE)
+    {
+        uint32_t value;
+
+        /* GPIO function set */
+        value = GPIO_GPFSEL1;
+        value &= ~(7<<12); /* GPIO14 */
+        value |=    2<<12 ; /* ALT5 */
+        value &= ~(7<<15); /* GPIO15 */
+        value |=    2<<15 ; /* ALT5 */
+        GPIO_GPFSEL1 = value;
+
+        /* PullUD disable */
+        GPIO_GPPUD = 0;
+        GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15);
+        GPIO_GPPUDCLK0 = 0;
+
+        AUX_ENABLES(uart->hw_base)      = 1;    /* Enable UART1 */
+        AUX_MU_IER_REG(uart->hw_base)   = 0;    /* Disable interrupt */
+        AUX_MU_CNTL_REG(uart->hw_base)  = 0;    /* Disable Transmitter and Receiver */
+        AUX_MU_LCR_REG(uart->hw_base)   = 3;    /* Works in 8-bit mode */
+        AUX_MU_MCR_REG(uart->hw_base)   = 0;    /* Disable RTS */
+        AUX_MU_IIR_REG(uart->hw_base)   = 0xC6; /* Enable FIFO, Clear FIFO */
+        AUX_MU_BAUD_REG(uart->hw_base)  = 270;  /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
+        AUX_MU_CNTL_REG(uart->hw_base)  = 3;    /* Enable Transmitter and Receiver */
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        AUX_MU_IER_REG(uart->hw_base) = 0x0;
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        AUX_MU_IER_REG(uart->hw_base) = 0x1;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
+    AUX_MU_IO_REG(uart->hw_base) = c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
+    {
+        ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device*)param;
+
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+#ifdef RT_USING_UART0
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    RPI_UART0_BASE,
+    IRQ_PBA8_UART0,
+};
+static struct rt_serial_device _serial0;
+#endif
+
+#ifdef RT_USING_UART1
+/* UART1 device driver structure */
+static struct hw_uart_device _uart1_device =
+{
+    AUX_BASE,
+    IRQ_AUX,
+};
+static struct rt_serial_device _serial1;
+#endif
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART0
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
+#endif
+
+#ifdef RT_USING_UART1
+    uart = &_uart1_device;
+    _serial1.ops = &_uart_ops;
+    _serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+    /* enable Rx and Tx of UART */
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1");
+#endif
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi2/driver/drv_uart.h b/bsp/raspberry-pi/raspi2/driver/drv_uart.h
new file mode 100644
index 0000000000..e489eaae65
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/driver/drv_uart.h
@@ -0,0 +1,56 @@
+/*
+ * File      : drv_uart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+/*
+ *  Auxiliary
+ */
+#define AUX_IRQ(BASE)             HWREG32(BASE + 0x00)   /* Auxiliary Interrupt status 3 */
+#define AUX_ENABLES(BASE)         HWREG32(BASE + 0x04)   /* Auxiliary enables 3bit */
+#define AUX_MU_IO_REG(BASE)       HWREG32(BASE + 0x40)   /* Mini Uart I/O Data 8bit */
+#define AUX_MU_IER_REG(BASE)      HWREG32(BASE + 0x44)   /* Mini Uart Interrupt Enable 8bit */
+#define AUX_MU_IIR_REG(BASE)      HWREG32(BASE + 0x48)   /* Mini Uart Interrupt Identify 8bit */
+#define AUX_MU_LCR_REG(BASE)      HWREG32(BASE + 0x4C)   /* Mini Uart Line Control 8bit */
+#define AUX_MU_MCR_REG(BASE)      HWREG32(BASE + 0x50)   /* Mini Uart Modem Control 8bit */
+#define AUX_MU_LSR_REG(BASE)      HWREG32(BASE + 0x54)   /* Mini Uart Line Status 8bit */
+#define AUX_MU_MSR_REG(BASE)      HWREG32(BASE + 0x58)   /* Mini Uart Modem Status 8bit */
+#define AUX_MU_SCRATCH(BASE)      HWREG32(BASE + 0x5C)   /* Mini Uart Scratch 8bit */
+#define AUX_MU_CNTL_REG(BASE)     HWREG32(BASE + 0x60)   /* Mini Uart Extra Control 8bit */
+#define AUX_MU_STAT_REG(BASE)     HWREG32(BASE + 0x64)   /* Mini Uart Extra Status 32bit */
+#define AUX_MU_BAUD_REG(BASE)     HWREG32(BASE + 0x68)   /* Mini Uart Baudrate 16bit */
+#define AUX_SPI0_CNTL0_REG(BASE)  HWREG32(BASE + 0x80)   /* SPI 1 Control register 0 32bit */
+#define AUX_SPI0_CNTL1_REG(BASE)  HWREG32(BASE + 0x84)   /* SPI 1 Control register 1 8bit */
+#define AUX_SPI0_STAT_REG(BASE)   HWREG32(BASE + 0x88)   /* SPI 1 Status 32bit */
+#define AUX_SPI0_IO_REG(BASE)     HWREG32(BASE + 0x90)   /* SPI 1 Data 32bit */
+#define AUX_SPI0_PEEK_REG(BASE)   HWREG32(BASE + 0x94)   /* SPI 1 Peek 16bit */
+#define AUX_SPI1_CNTL0_REG(BASE)  HWREG32(BASE + 0xC0)   /* SPI 2 Control register 0 32bit */
+#define AUX_SPI1_CNTL1_REG(BASE)  HWREG32(BASE + 0xC4)   /* SPI 2 Control register 1 8bit */
+
+int rt_hw_uart_init(void);
+
+#endif /* DRV_UART_H__ */
+
diff --git a/bsp/raspberry-pi/raspi2/figures/raspi2.png b/bsp/raspberry-pi/raspi2/figures/raspi2.png
new file mode 100644
index 0000000000..2f2e25d9cb
Binary files /dev/null and b/bsp/raspberry-pi/raspi2/figures/raspi2.png differ
diff --git a/bsp/raspberry-pi/raspi2/figures/raspi_uart.png b/bsp/raspberry-pi/raspi2/figures/raspi_uart.png
new file mode 100644
index 0000000000..c6ae382182
Binary files /dev/null and b/bsp/raspberry-pi/raspi2/figures/raspi_uart.png differ
diff --git a/bsp/raspberry-pi/raspi2/kernel7.img b/bsp/raspberry-pi/raspi2/kernel7.img
new file mode 100755
index 0000000000..82e849b25d
Binary files /dev/null and b/bsp/raspberry-pi/raspi2/kernel7.img differ
diff --git a/bsp/raspberry-pi/raspi2/link.lds b/bsp/raspberry-pi/raspi2/link.lds
new file mode 100644
index 0000000000..75e0845943
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/link.lds
@@ -0,0 +1,149 @@
+/*
+ * File      : link.lds
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+SECTIONS
+{
+    . = 0x00008000;
+    . = ALIGN(4);
+    .text :
+    {
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    }
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(4);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(8);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(4);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+        PROVIDE(__bss_end = .);
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/raspberry-pi/raspi2/rtconfig.h b/bsp/raspberry-pi/raspi2/rtconfig.h
new file mode 100644
index 0000000000..a144bc0550
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/rtconfig.h
@@ -0,0 +1,259 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+/* RT_THREAD_PRIORITY_8 is not set */
+#define RT_THREAD_PRIORITY_32
+/* RT_THREAD_PRIORITY_256 is not set */
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+/* RT_USING_TIMER_SOFT is not set */
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+/* RT_DEBUG_INIT_CONFIG is not set */
+/* RT_DEBUG_THREAD_CONFIG is not set */
+/* RT_DEBUG_SCHEDULER_CONFIG is not set */
+/* RT_DEBUG_IPC_CONFIG is not set */
+/* RT_DEBUG_TIMER_CONFIG is not set */
+/* RT_DEBUG_IRQ_CONFIG is not set */
+/* RT_DEBUG_MEM_CONFIG is not set */
+/* RT_DEBUG_SLAB_CONFIG is not set */
+/* RT_DEBUG_MEMHEAP_CONFIG is not set */
+/* RT_DEBUG_MODULE_CONFIG is not set */
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* RT_USING_SIGNALS is not set */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+/* RT_USING_MEMHEAP is not set */
+/* RT_USING_NOHEAP is not set */
+#define RT_USING_SMALL_MEM
+/* RT_USING_SLAB is not set */
+/* RT_USING_MEMTRACE is not set */
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+/* RT_USING_DEVICE_OPS is not set */
+/* RT_USING_INTERRUPT_INFO is not set */
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+/* RT_USING_MODULE is not set */
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_A
+#define ARCH_ARM_CORTEX_A7
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+/* RT_USING_CPLUSPLUS is not set */
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+/* FINSH_ECHO_DISABLE_DEFAULT is not set */
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+/* FINSH_USING_AUTH is not set */
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+/* RT_USING_DFS is not set */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+/* RT_USING_CAN is not set */
+/* RT_USING_HWTIMER is not set */
+/* RT_USING_CPUTIME is not set */
+/* RT_USING_I2C is not set */
+/* RT_USING_PIN is not set */
+/* RT_USING_PWM is not set */
+/* RT_USING_MTD_NOR is not set */
+/* RT_USING_MTD_NAND is not set */
+/* RT_USING_RTC is not set */
+/* RT_USING_SDIO is not set */
+/* RT_USING_SPI is not set */
+/* RT_USING_WDT is not set */
+/* RT_USING_WIFI is not set */
+/* RT_USING_AUDIO is not set */
+
+/* Using USB */
+
+/* RT_USING_USB_HOST is not set */
+/* RT_USING_USB_DEVICE is not set */
+
+/* POSIX layer and C standard library */
+
+/* RT_USING_LIBC is not set */
+/* RT_USING_PTHREADS is not set */
+
+/* Network */
+
+/* Socket abstraction layer */
+
+/* RT_USING_SAL is not set */
+
+/* light weight TCP/IP stack */
+
+/* RT_USING_LWIP is not set */
+
+/* Modbus master and slave stack */
+
+/* RT_USING_MODBUS is not set */
+
+/* AT commands */
+
+/* RT_USING_AT is not set */
+
+/* VBUS(Virtual Software BUS) */
+
+/* RT_USING_VBUS is not set */
+
+/* Utilities */
+
+/* RT_USING_LOGTRACE is not set */
+/* RT_USING_RYM is not set */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+/* PKG_USING_PAHOMQTT is not set */
+/* PKG_USING_WEBCLIENT is not set */
+/* PKG_USING_MONGOOSE is not set */
+/* PKG_USING_WEBTERMINAL is not set */
+/* PKG_USING_CJSON is not set */
+/* PKG_USING_JSMN is not set */
+/* PKG_USING_LJSON is not set */
+/* PKG_USING_EZXML is not set */
+/* PKG_USING_NANOPB is not set */
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* PKG_USING_WLANMARVELL is not set */
+
+/* Wiced WiFi */
+
+/* PKG_USING_WLAN_WICED is not set */
+/* PKG_USING_COAP is not set */
+/* PKG_USING_NOPOLL is not set */
+/* PKG_USING_NETUTILS is not set */
+/* PKG_USING_AT_DEVICE is not set */
+
+/* IoT Cloud */
+
+/* PKG_USING_ONENET is not set */
+/* PKG_USING_GAGENT_CLOUD is not set */
+/* PKG_USING_ALI_IOTKIT is not set */
+/* PKG_USING_AZURE is not set */
+
+/* security packages */
+
+/* PKG_USING_MBEDTLS is not set */
+/* PKG_USING_libsodium is not set */
+/* PKG_USING_TINYCRYPT is not set */
+
+/* language packages */
+
+/* PKG_USING_LUA is not set */
+/* PKG_USING_JERRYSCRIPT is not set */
+/* PKG_USING_MICROPYTHON is not set */
+
+/* multimedia packages */
+
+/* PKG_USING_OPENMV is not set */
+/* PKG_USING_MUPDF is not set */
+
+/* tools packages */
+
+/* PKG_USING_CMBACKTRACE is not set */
+/* PKG_USING_EASYFLASH is not set */
+/* PKG_USING_EASYLOGGER is not set */
+/* PKG_USING_SYSTEMVIEW is not set */
+
+/* system packages */
+
+/* PKG_USING_GUIENGINE is not set */
+/* PKG_USING_PERSIMMON is not set */
+/* PKG_USING_CAIRO is not set */
+/* PKG_USING_PIXMAN is not set */
+/* PKG_USING_LWEXT4 is not set */
+/* PKG_USING_PARTITION is not set */
+/* PKG_USING_FAL is not set */
+/* PKG_USING_SQLITE is not set */
+/* PKG_USING_RTI is not set */
+/* PKG_USING_LITTLEVGL2RTT is not set */
+
+/* peripheral libraries and drivers */
+
+/* PKG_USING_STM32F4_HAL is not set */
+/* PKG_USING_STM32F4_DRIVERS is not set */
+/* PKG_USING_REALTEK_AMEBA is not set */
+/* PKG_USING_SHT2X is not set */
+/* PKG_USING_AHT10 is not set */
+
+/* miscellaneous packages */
+
+/* PKG_USING_LIBCSV is not set */
+/* PKG_USING_OPTPARSE is not set */
+/* PKG_USING_FASTLZ is not set */
+/* PKG_USING_MINILZO is not set */
+/* PKG_USING_QUICKLZ is not set */
+/* PKG_USING_MULTIBUTTON is not set */
+/* PKG_USING_CANFESTIVAL is not set */
+/* PKG_USING_ZLIB is not set */
+/* PKG_USING_DSTR is not set */
+
+/* sample package */
+
+/* PKG_USING_SAMPLES is not set */
+
+/* example package: hello */
+
+/* PKG_USING_HELLO is not set */
+#define BCM2836_SOC
+#define RT_USING_UART1
+
+#endif
diff --git a/bsp/raspberry-pi/raspi2/rtconfig.py b/bsp/raspberry-pi/raspi2/rtconfig.py
new file mode 100644
index 0000000000..8c827e8221
--- /dev/null
+++ b/bsp/raspberry-pi/raspi2/rtconfig.py
@@ -0,0 +1,53 @@
+import os
+
+# toolchains options
+ARCH        ='arm'
+CPU         ='cortex-a7'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-none-eabi-5_4-2016q3/bin'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -mfpu=neon-vfpv4 -mfloat-abi=softfp -march=armv7-a -mtune=cortex-a7 -ftree-vectorize -ffast-math'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/raspberry-pi/raspi3-32/.config b/bsp/raspberry-pi/raspi3-32/.config
new file mode 100644
index 0000000000..78d7e6fbaf
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/.config
@@ -0,0 +1,427 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=4
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+CONFIG_RT_USING_MEMTRACE=y
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+CONFIG_RT_USING_DEVICE_OPS=y
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40002
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_CORTEX_A=y
+CONFIG_ARCH_ARM_CORTEX_A7=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+CONFIG_RT_USING_HWTIMER=y
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_USING_I2C_BITOPS is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+CONFIG_RT_USING_SDIO=y
+CONFIG_RT_SDIO_STACK_SIZE=512
+CONFIG_RT_SDIO_THREAD_PRIORITY=15
+CONFIG_RT_MMCSD_STACK_SIZE=1024
+CONFIG_RT_MMCSD_THREAD_PREORITY=22
+CONFIG_RT_MMCSD_MAX_PARTITION=16
+# CONFIG_RT_SDIO_DEBUG is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+CONFIG_RT_USING_WDT=y
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_LCD_DRIVERS is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+CONFIG_BCM2836_SOC=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# BCM Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+# CONFIG_RT_USING_UART0 is not set
+CONFIG_RT_USING_UART1=y
+CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_SYSTIMER=y
+CONFIG_RT_USING_SYSTIMER1=y
+CONFIG_RT_USING_SYSTIMER3=y
+CONFIG_BSP_USING_I2C=y
+CONFIG_BSP_USING_I2C0=y
+CONFIG_BSP_USING_I2C1=y
+CONFIG_BSP_USING_SPI=y
+CONFIG_BSP_USING_SPI0_BUS=y
+CONFIG_BSP_USING_SPI0_DEVICE0=y
+CONFIG_BSP_USING_SPI0_DEVICE1=y
+CONFIG_BSP_USING_WDT=y
+CONFIG_BSP_USING_RTC=y
+# CONFIG_BSP_USING_ALARM is not set
+CONFIG_BSP_USING_SDIO=y
+CONFIG_BSP_USING_SDIO0=y
+CONFIG_BSP_USING_HDMI=y
diff --git a/bsp/raspberry-pi/raspi3-32/Kconfig b/bsp/raspberry-pi/raspi3-32/Kconfig
new file mode 100644
index 0000000000..06cbe1128f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/Kconfig
@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2836_SOC
+    bool
+    select ARCH_ARM_CORTEX_A7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "driver/Kconfig"
diff --git a/bsp/raspberry-pi/raspi3-32/README.md b/bsp/raspberry-pi/raspi3-32/README.md
new file mode 100644
index 0000000000..0fef644adf
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/README.md
@@ -0,0 +1,153 @@
+# Raspberry PI 3B(32位)板级支持包说明
+
+## 1. 简介
+
+树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3采用4核Broadcom BCM2837 (ARMv8)芯片、双核VideoCore IV GPU和1GB内存。
+
+这份RT-Thread BSP是针对 Raspberry Pi 3B （32位）的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+随着RT-Thread的发展，它越来越多的向一些Cortex-A等AP类处理器提供支持，例如全志的ARM9、Cortex-A处理器，Xilinx的Zynq处理器等。
+
+而RT-Thread也是一套高度社区化发展的操作系统，所以在一些方向推进上希望以社区化方式，大家一起来推动的方式向前发展，在这个过程中RT-Thread得到了不同开发者、不同领域的应用，一步步把RT-Thread推向成熟。而在Cortex-A平台上，目前最流行的硬件平台是树莓派，分树莓派[2B](https://www.raspberrypi.org/products/raspberry-pi-2-model-b/)、[3B](https://www.raspberrypi.org/products/raspberry-pi-3-model-b/)以及最新的[4B](https://www.raspberrypi.org/products/raspberry-pi-4-model-b/)等。
+
+RT-Thread对树莓派的支持主要从树莓派2B开始，它是一个四核Cortex-A7的平台，以32位单核的模式运行。后续将推动着RT-Thread向树莓派3，四核Cortex-A53 64位模式发展（中间当然也可能出现四核Cortex-A7模式执行的过渡性版本）。
+
+![raspi3_f](figures/raspi3_f.jpg)
+
+![raspi3_b](figures/raspi3_b.jpg)
+
+当前Raspberry Pi 3B对应的硬件特性：
+
+| 硬件   | 描述 |
+|------- | ------------------------------- |
+|  CPU   | quad-core ARM Cortex A53(ARMv8) |
+|  主频  | 1.2 GHz |
+| GPU | VideoCore IV |
+| GPU频率 | 400MHz |
+| Memory | 1GB  (0x0000000 - 0x40000000) |
+| | 其中0x3f000000 - 0x40000000为peripheral |
+
+硬件引脚分布情况
+
+![GPIO-Pinout-Diagram-2](figures/GPIO-Pinout-Diagram-2.png)
+
+## 2. 编译说明
+
+Windows环境下推荐使用[env工具][1]进行编译。
+
+Linux下推荐使用gcc工具 [gcc-arm-none-eabi-4_8-2014q1_linux][2]，如果还没有编译工具，下载后，解开文件。
+
+```
+tar vxf gcc-arm-none-eabi-4_8-2014q1_linux.tar.bz2
+```
+
+Linux环境下需要修改编译器目录设置，修改`bsp/raspi3-32/rtconfig.py`中的
+
+```
+EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+```
+
+为编译工具的实际所在目录，这里注意要加上后缀 `/bin`
+
+进入到`rt-thread/bsp/raspi3-32`目录中，运行以下命令：
+
+```
+scons
+```
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、kernel7.img文件。
+kernel7.img即是要cp到raspberry SD卡中根目录的文件
+
+### 2.1 eclipse 编码环境 ###
+第一步： 安装 eclipse cdt 
+第二步： 打开 eclipse cdt 设置workspace ,推荐设置于xxx\xxx\rt-thread\bsp
+第三步： Import 工程 General-> Existing Peojects into Workspace 然后 Browse.. 你的raspi3目录，点击Finish
+
+btw:编译依旧使用scons,目前不支持qemu debug,后期如果有大佬实现ARM JTAG调试
+
+## 3. 执行
+
+### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
+
+Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
+
+解开下载的镜像文件, linux下使用如下的命令
+
+```
+unzip 2018-06-27-raspbian-stretch-lite.zip
+```
+
+准备一张空SD卡，linux环境下，插入电脑并执行
+
+```
+sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
+```
+
+**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
+
+Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
+
+最后把kernel7.img放入SD boot分区，覆盖原来的文件。
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
+
+
+
+![raspberrypi-console](figures/raspberrypi-console.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+按上面的方法做好SD卡后，插入树莓派3B，通电可以在串口上看到如下所示的输出信息：
+
+```text
+heap: 0x0005d784 - 0x0045d784
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.2 build Jan  9 2020
+ 2006 - 2019 Copyright by rt-thread team
+[I/I2C] I2C bus [i2c0] registered
+[I/I2C] I2C bus [i2c1] registered
+[I/SDIO] SD card capacity 15558144 KB.
+found part[0], begin: 1048576, size: 63.0MB
+found part[1], begin: 67108864, size: 14.793GB
+file system initialization done!
+boot cpu:3
+msh />cpu = 0x00000003
+cpu 3 startup.
+start OK: CPU 3
+boot cpu:2
+cpu = 0x00000002
+cpu 2 startup.
+start OK: CPU 2
+boot cpu:1
+cpu = 0x00000001
+cpu 1 startup.
+start OK: CPU 1
+Hello RT-Thread!
+
+msh />
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+| GPIO | 支持 | |
+| IIC | 支持 | |
+| SPI | 支持 | |
+| CPU Timer | 支持 | |
+| SD卡驱动 | 支持 | |
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+[1]: https://www.rt-thread.org/page/download.html
+[2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2
+[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+[4]: https://etcher.io
+[5]: https://github.com/BernardXiong
diff --git a/bsp/raspberry-pi/raspi3-32/SConscript b/bsp/raspberry-pi/raspi3-32/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/raspberry-pi/raspi3-32/SConstruct b/bsp/raspberry-pi/raspi3-32/SConstruct
new file mode 100644
index 0000000000..e94a364d9d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/SConstruct
@@ -0,0 +1,28 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/raspberry-pi/raspi3-32/applications/SConscript b/bsp/raspberry-pi/raspi3-32/applications/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi3-32/applications/main.c b/bsp/raspberry-pi/raspi3-32/applications/main.c
new file mode 100644
index 0000000000..cda0e0d711
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/applications/main.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30     bernard       the first version
+ */
+
+#include <rtthread.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hello RT-Thread!\n");
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi3-32/applications/mnt.c b/bsp/raspberry-pi/raspi3-32/applications/mnt.c
new file mode 100644
index 0000000000..88b714022c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/applications/mnt.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30     bernard       the first version
+ */
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_SDIO0
+#include <dfs_fs.h>
+
+int mnt_init(void)
+{
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+    {
+        rt_kprintf("file system initialization done!\n");
+    }
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif
+
diff --git a/bsp/raspberry-pi/raspi3-32/applications/test_device.c b/bsp/raspberry-pi/raspi3-32/applications/test_device.c
new file mode 100644
index 0000000000..222bb2e822
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/applications/test_device.c
@@ -0,0 +1,462 @@
+/*
+ * File      : test_driver.h
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <string.h>
+#include <drivers/hwtimer.h>
+#include "raspi.h"
+
+#ifdef BSP_USING_HDMI
+#include "drv_fb.h"
+#endif
+
+void test_hdmi()
+{
+    rt_kprintf("Hello Test hdmi!\n");
+#ifdef BSP_USING_HDMI
+    print_fb_info();
+#ifdef BSP_USING_HDMI_DISPLAY
+    rt_kprintf("hdmi is tested!\n");
+#else
+    rt_console_set_device("hdmi");
+    rt_kprintf("hdmi is testing!\n");
+#endif
+    rt_kprintf("search hdmi device");
+    rt_device_t hdmi = rt_device_find("hdmi");
+    if (hdmi == RT_NULL)
+    {
+        rt_kprintf("cannot find hdmi device");
+    }
+    int color = COLOR_YELLOW;
+    rt_kprintf("begin test hdmi deivice");
+    rt_graphix_ops(hdmi) -> set_pixel((char *)&color, 5, 5);
+
+    rt_graphix_ops(hdmi) -> get_pixel((char *)&color, 5, 5);
+    rt_kprintf("color is %x\n",color);
+    rt_graphix_ops(hdmi) -> draw_hline((char *)&color, 10, 100, 10);
+    color = COLOR_GREEN;
+    rt_graphix_ops(hdmi) -> draw_vline((char *)&color, 10, 10, 100);
+    int colors[100];
+    int i=0;
+    for (; i < 20; i++)  colors[i] = COLOR_RED;
+    rt_graphix_ops(hdmi) -> blit_line((char *)colors, 20, 20, 20);
+    
+#endif
+}
+
+#ifdef RT_USING_SMP
+#define _CPUS_NR                RT_CPUS_NR
+#else
+#define _CPUS_NR                1
+#endif
+
+#ifdef RT_USING_SMP
+static rt_uint8_t rt_thread_stack[_CPUS_NR][128];
+static struct rt_thread smp[_CPUS_NR];
+void smp_test_entry()
+{
+    rt_kprintf("cpu %d is running.\n",rt_hw_cpu_id());
+}
+#endif
+
+void test_cpusmp(void)
+{
+    rt_kprintf("Hello Test SMP!\n");
+#ifdef RT_USING_SMP
+    int i;    
+    char test_name[RT_NAME_MAX]; 
+    for (i = 0; i < _CPUS_NR; i++)
+    {
+        rt_sprintf(test_name, "smp%d", i);
+        rt_thread_init(&smp[i],
+                test_name,
+                smp_test_entry,
+                RT_NULL,
+                &rt_thread_stack[i][0],
+                sizeof(rt_thread_stack[i]),
+                RT_THREAD_PRIORITY_MAX - 2,
+                32);
+        rt_thread_control(&smp[i], RT_THREAD_CTRL_BIND_CPU, (void*)i);
+        /* startup */
+        rt_thread_startup(&smp[i]);
+        rt_thread_delay(RT_TICK_PER_SECOND);
+    }
+#endif
+}
+
+#ifdef BSP_USING_PIN
+#define TEST_PIN_OUT 33
+#define TEST_PIN_IN 37
+
+void gpio_rising_test()
+{
+     rt_kprintf("gpio rising irq function ok!\n");
+}
+#endif
+
+void test_gpio(void)
+{
+#ifdef BSP_USING_PIN
+    rt_uint32_t ret;
+    rt_kprintf("Hello Test GPIO!\n");
+
+    rt_pin_mode(TEST_PIN_OUT, PIN_MODE_OUTPUT);
+    rt_pin_write(TEST_PIN_OUT, PIN_HIGH);
+    rt_pin_mode(TEST_PIN_IN, PIN_MODE_INPUT);
+
+    ret = rt_pin_read(TEST_PIN_IN);
+    rt_kprintf("common high input test read result: %d\n",ret);
+
+    rt_pin_write(TEST_PIN_OUT, PIN_LOW);
+    ret = rt_pin_read(TEST_PIN_IN);
+    rt_kprintf("common low input test read result: %d\n",ret);
+
+    rt_pin_mode(TEST_PIN_IN, PIN_MODE_INPUT_PULLDOWN);
+    rt_pin_attach_irq(TEST_PIN_IN, PIN_IRQ_MODE_RISING, gpio_rising_test, RT_NULL);
+    rt_pin_irq_enable(TEST_PIN_IN, PIN_IRQ_ENABLE);
+    rt_pin_write(TEST_PIN_OUT, PIN_HIGH);
+
+    rt_pin_irq_enable(TEST_PIN_IN, PIN_IRQ_DISABLE);
+#endif
+}
+
+#ifdef BSP_USING_I2C1
+#define DS3231_I2C_BUS_NAME      "i2c1"
+#define DS3231_ADDR               0x68
+struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+static rt_err_t read_regs(struct rt_i2c_bus_device *bus, rt_uint8_t len, rt_uint8_t *buf)
+{
+    struct rt_i2c_msg msgs;
+    msgs.addr = DS3231_ADDR;
+    msgs.flags = RT_I2C_RD;
+    msgs.buf = buf;
+    msgs.len = len;
+
+    if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+        return RT_EOK;
+    else
+        return -RT_ERROR;
+}
+#endif
+
+void test_i2c(void)
+{
+#ifdef BSP_USING_I2C1
+    rt_kprintf("Hello Test I2C!\n");
+    char name[RT_NAME_MAX];
+    rt_uint8_t  buf[]={0x00,0x00,0x43,0x15,0x05,0x01,0x03,0x19};
+
+    rt_strncpy(name, DS3231_I2C_BUS_NAME, RT_NAME_MAX);
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
+    if (i2c_bus == RT_NULL)
+        rt_kprintf("can't find %s device!\n", name);
+    else
+    {
+    	read_regs(i2c_bus, 7, buf);
+    	buf[0] = buf[0]&0x7F; //sec
+    	buf[1] = buf[1]&0x7F; //min
+    	buf[2] = buf[2]&0x3F; //hour
+    	buf[3] = buf[3]&0x07; //week
+    	buf[4] = buf[4]&0x3F; //day
+    	buf[5] = buf[5]&0x1F; //mouth
+    	//year/month/day
+    	rt_kprintf("20%02x-%02x-%02x ",buf[6],buf[5],buf[4]);
+    	//hour:minute/second
+    	rt_kprintf("%02x:%02x:%02x \n",buf[2],buf[1],buf[0]);
+    }
+#endif
+}
+
+#define W25Q_SPI_DEVICE_NAME     "spi0.0"
+void test_spi(void)
+{
+#ifdef BSP_USING_SPI
+    rt_kprintf("Hello Test SPI!\n");
+    struct rt_spi_device *spi0_dev0;
+    struct rt_spi_device *spi0_dev1;
+
+    char name0[RT_NAME_MAX];
+    char name1[RT_NAME_MAX];
+
+    rt_uint8_t w25x_read_id = 0x90;
+    rt_uint8_t id[5] = {0};
+
+    rt_strncpy(name0, "spi0.0", RT_NAME_MAX);
+    rt_strncpy(name1, "spi0.1", RT_NAME_MAX);
+
+    spi0_dev0 = (struct rt_spi_device *)rt_device_find(name0);
+    spi0_dev1 = (struct rt_spi_device *)rt_device_find(name1);
+
+
+    if (!spi0_dev0 || !spi0_dev1)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", name0);
+    }
+    else
+    {
+        struct rt_spi_message msg1, msg2;
+
+        msg1.send_buf   = &w25x_read_id;
+        msg1.recv_buf   = RT_NULL;
+        msg1.length     = 1;
+        msg1.cs_take    = 1;
+        msg1.cs_release = 0;
+        msg1.next       = &msg2;
+
+        msg2.send_buf   = RT_NULL;
+        msg2.recv_buf   = id;
+        msg2.length     = 5;
+        msg2.cs_take    = 0;
+        msg2.cs_release = 1;
+        msg2.next       = RT_NULL;
+
+        rt_spi_transfer_message(spi0_dev0, &msg1);
+        rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]);
+
+    }
+#endif
+}
+
+#ifdef BSP_USING_SYSTIMER
+#define TIMER   "timer1"
+
+static rt_err_t timer_timeout_cb(rt_device_t dev, rt_size_t size)
+{
+    rt_kprintf("enter hardware timer isr\n");
+    return 0;
+}
+#endif
+rt_err_t test_hwtimer(void)
+{
+#ifdef BSP_USING_SYSTIMER
+    rt_kprintf("Hello Test HW Timer!\n");
+    rt_err_t err;
+    rt_hwtimerval_t val;
+    rt_device_t dev = RT_NULL;
+    rt_tick_t tick;
+    rt_hwtimer_mode_t mode;
+    int t = 5;
+
+    if ((dev = rt_device_find(TIMER)) == RT_NULL)
+    {
+        rt_kprintf("No Device: %s\n", TIMER);
+        return -1;
+    }
+
+    if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK)
+    {
+        rt_kprintf("Open %s Fail\n", TIMER);
+        return -1;
+    }
+
+    mode = HWTIMER_MODE_PERIOD;
+    err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode);
+
+    tick = rt_tick_get();
+    rt_kprintf("Start Timer> Tick: %d\n", tick);
+
+    val.sec = t;
+    val.usec = 0;
+    rt_kprintf("SetTime: Sec %d, Usec %d\n", val.sec, val.usec);
+    if (rt_device_write(dev, 0, &val, sizeof(val)) != sizeof(val))
+    {
+        rt_kprintf("SetTime Fail\n");
+        goto EXIT;
+    }
+    rt_kprintf("Sleep %d sec\n", t);
+    rt_thread_delay(t*RT_TICK_PER_SECOND);
+
+    err = rt_device_control(dev, HWTIMER_CTRL_STOP, RT_NULL);
+    rt_kprintf("Timer Stoped\n");
+
+    rt_device_read(dev, 0, &val, sizeof(val));
+    rt_kprintf("Read: Sec = %d, Usec = %d\n", val.sec, val.usec);
+
+    rt_device_set_rx_indicate(dev, timer_timeout_cb);
+
+    mode = HWTIMER_MODE_PERIOD;
+    err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode);
+
+    val.sec = t;
+    val.usec = 0;
+    rt_kprintf("SetTime: Sec %d, Usec %d\n", val.sec, val.usec);
+    if (rt_device_write(dev, 0, &val, sizeof(val)) != sizeof(val))
+    {
+        rt_kprintf("SetTime Fail\n");
+        goto EXIT;
+    }
+
+    rt_thread_delay((t *5 + 1)*RT_TICK_PER_SECOND);
+
+EXIT:
+    err = rt_device_close(dev);
+    rt_kprintf("Close %s\n", TIMER);
+
+    return err;
+#endif
+}
+
+#ifdef RT_USING_WDT
+#define WDT_DEVICE_NAME    "wdg"    /* 鐪嬮棬鐙楄澶囧悕绉� */
+static rt_device_t wdg_dev;         /* 鐪嬮棬鐙楄澶囧彞鏌� */
+static void idle_hook(void)
+{
+    /* 鍦ㄧ┖闂茬嚎绋嬬殑鍥炶皟鍑芥暟閲屽杺鐙� */
+    rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, NULL);
+    //rt_kprintf("feed the dog!\n ");
+}
+
+rt_err_t test_wdt(void)
+{
+    rt_kprintf("Hello Test WDT!\n");
+    rt_err_t ret = RT_EOK;
+    rt_uint32_t timeout = 1;        /* 婧㈠嚭鏃堕棿锛屽崟浣嶏細绉� */
+    char device_name[RT_NAME_MAX];
+    rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX);
+    /* 鏍规嵁璁惧鍚嶇О鏌ユ壘鐪嬮棬鐙楄澶囷紝鑾峰彇璁惧鍙ユ焺 */
+    wdg_dev = rt_device_find(device_name);
+    if (!wdg_dev)
+    {
+        rt_kprintf("find %s failed!\n", device_name);
+        return RT_ERROR;
+    }
+    /* 鍒濆鍖栬澶� */
+    ret = rt_device_init(wdg_dev);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("initialize %s failed!\n", device_name);
+        return RT_ERROR;
+    }
+    /* 璁剧疆鐪嬮棬鐙楁孩鍑烘椂闂� */
+    ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("set %s timeout failed!\n", device_name);
+        return RT_ERROR;
+    }
+    /* 鍚姩鐪嬮棬鐙� */
+    ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("start %s failed!\n", device_name);
+        return -RT_ERROR;
+    }
+    /* 璁剧疆绌洪棽绾跨▼鍥炶皟鍑芥暟 */
+    rt_thread_idle_sethook(idle_hook);
+
+    return ret;
+
+}
+#else
+rt_err_t test_wdt(void)
+{
+    return RT_EOK;
+}
+#endif
+
+int test_rtc(void)
+{
+#ifdef BSP_USING_RTD
+    rt_kprintf("Hello Test RTC!\n");
+    uint8_t i;
+    time_t now;
+
+    rt_err_t ret = RT_EOK;
+
+    rt_kprintf("[RTC Test]RTC Test Start...\n");
+    rt_thread_delay(RT_TICK_PER_SECOND);
+    rt_kprintf("[RTC Test]Set RTC 2017-04-01 12:30:46\n\n");
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    ret = set_date(2017, 4, 1);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("[RTC Test]Set RTC Date failed\n");
+        return RT_ERROR;
+    }
+
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    ret = set_time(12, 30, 46);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("[RTC Test]Set RTC Time failed\n");
+        return RT_ERROR;
+    }
+
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    for (i = 0; i < 10; i++)
+    {
+        rt_kprintf("[RTC Test]Read RTC Date and Time: ");
+        now = time(RT_NULL);
+        rt_kprintf("%s", ctime(&now));
+
+        rt_thread_delay(RT_TICK_PER_SECOND);
+    }
+
+    rt_kprintf("\n");
+#endif
+    return RT_EOK;
+}
+
+void test_device(int argc, char**argv)
+{
+    if (0 == strcmp(argv[1],"smp"))
+    {
+        test_cpusmp();
+        return;
+    }
+    if (0 == strcmp(argv[1],"gpio"))
+    {
+        test_gpio();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"i2c"))
+    {
+        test_i2c();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"spi"))
+    {
+        test_spi();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"hwtimer"))
+    {
+        test_hwtimer();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"wdt"))
+    {
+        test_wdt();
+        return;
+    }
+
+    if (0 == strcmp(argv[1],"rtc"))
+    {
+        test_rtc();
+        return;
+    }
+    if (0 == strcmp(argv[1],"hdmi"))
+    {
+        test_hdmi();
+        return;
+    }
+    rt_kprintf("param err, please entry test_device <smp|gpio|i2c|spi|hwtimer|wdt|rtc|hdmi>\n");
+}
+MSH_CMD_EXPORT(test_device, sample: test_device <smp|gpio|i2c|spi|hwtimer|wdt|rtc>);
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/SConscript b/bsp/raspberry-pi/raspi3-32/cpu/SConscript
new file mode 100644
index 0000000000..eb4ee7a585
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/armv7.h b/bsp/raspberry-pi/raspi3-32/cpu/armv7.h
new file mode 100644
index 0000000000..859b0371b7
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/armv7.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+};
+
+struct rt_hw_stack
+{
+    unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long lr;
+    unsigned long pc;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S b/bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S
new file mode 100644
index 0000000000..cb95558f7a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "../rtconfig.h"
+.section .text, "ax"
+
+#ifdef RT_USING_SMP
+#define rt_hw_interrupt_disable rt_hw_local_irq_disable
+#define rt_hw_interrupt_enable  rt_hw_local_irq_enable
+#endif
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    cpsid i
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread);
+ * r0 --> to (thread stack)
+ * r1 --> to_thread
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+#ifdef RT_USING_SMP
+    mov     r0, r1
+    bl      rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+    b       rt_hw_context_switch_exit
+
+.section .bss.share.isr
+_guest_switch_lvl:
+    .word 0
+
+.globl vmm_virq_update
+
+.section .text.isr, "ax"
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread);
+ * r0 --> from (from_thread stack)
+ * r1 --> to (to_thread stack)
+ * r2 --> to_thread
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    orrne r4, r4, #0x20     @ it's thumb code
+
+    stmfd sp!, {r4}         @ push cpsr
+
+#ifdef RT_USING_LWP
+    stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
+    sub sp, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+#ifdef RT_USING_SMP
+    mov     r0, r2
+    bl      rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+    b       rt_hw_context_switch_exit
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+#ifdef RT_USING_SMP
+    /* r0 :svc_mod context
+     * r1 :addr of from_thread's sp
+     * r2 :addr of to_thread's sp
+     * r3 :to_thread's tcb
+     */
+
+    str     r0, [r1]
+
+    ldr     sp, [r2]
+    mov     r0, r3
+    bl      rt_cpus_lock_status_restore
+
+    b       rt_hw_context_switch_exit
+
+#else /*RT_USING_SMP*/
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r0, [ip]
+    str r3, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
+#endif /*RT_USING_SMP*/
+
+.global rt_hw_context_switch_exit
+rt_hw_context_switch_exit:
+
+#ifdef RT_USING_SMP
+#ifdef RT_USING_SIGNALS
+    mov     r0, sp
+    cps #Mode_IRQ
+    bl      rt_signal_check
+    cps #Mode_SVC
+    mov     sp, r0
+#endif
+#endif
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+
+#endif
+
+#ifdef RT_USING_LWP
+    ldmfd   sp, {r13, r14}^ /* usr_sp, usr_lr */
+    add     sp, #8
+#endif
+    ldmfd   sp!, {r4}
+    msr     spsr_cxsf, r4        /* original mode */
+    ldmfd   sp!, {r0-r12,lr,pc}^ /* irq return */
+
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cp15.h b/bsp/raspberry-pi/raspi3-32/cpu/cp15.h
new file mode 100644
index 0000000000..14b85b7e64
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/cp15.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+#include "raspi.h"
+#ifndef __CP15_H__
+#define __CP15_H__
+
+#ifndef   __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
+#endif
+
+#define __WFI()    __asm__ volatile ("wfi":::"memory")
+
+#define __WFE()    __asm__ volatile ("wfe":::"memory")
+
+#define __SEV()    __asm__ volatile ("sev")
+
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+    __asm__ volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+    __asm__ volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+    __asm__ volatile ("dmb 0xF":::"memory");
+}
+
+
+#ifdef RT_USING_SMP
+static inline void send_ipi_msg(int cpu, int ipi_vector)
+{
+    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
+}
+
+static inline void setup_bootstrap_addr(int cpu, int addr)
+{
+	CORE_MAILBOX3_SET(cpu) = addr;
+}
+
+static inline void enable_cpu_ipi_intr(int cpu)
+{
+    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
+}
+
+static inline void enable_cpu_timer_intr(int cpu)
+{
+	CORETIMER_INTCTL(cpu) = 0x8;
+}
+
+static inline void enable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline void disable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 0;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline  void mask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 2;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline void unmask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline rt_uint64_t read_cntvct(void)
+{
+    rt_uint32_t val,val1;
+    asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
+    return (val);
+}
+
+static inline rt_uint64_t read_cntvoff(void)
+{
+
+    rt_uint64_t val;
+    asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
+    return (val);
+}
+
+static inline rt_uint32_t read_cntv_tval(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
+    return val;
+}
+
+
+static inline  void write_cntv_tval(rt_uint32_t val)
+{
+    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
+    return;
+}
+
+static inline rt_uint32_t read_cntfrq(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
+    return val;
+}
+
+
+static inline  rt_uint32_t read_cntctrl(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
+    return val;
+}
+
+static inline uint32_t write_cntctrl(uint32_t val)
+{
+
+    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
+    return val;
+}
+#endif
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_dcache_clean_flush(void);
+void rt_cpu_icache_flush(void);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+void rt_hw_mmu_init(void);
+void rt_hw_vector_init(void);
+
+void set_timer_counter(unsigned int counter);
+void set_timer_control(unsigned int control);
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S b/bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S
new file mode 100644
index 0000000000..db2e6143ae
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    /* clear SCTRL.V to customize the vector address */
+    mrc     p15, #0, r1, c1, c0, #0
+    bic     r1, #(1 << 13)
+    mcr     p15, #0, r1, c1, c0, #0
+    /* set up the vector address */
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl set_timer_counter
+set_timer_counter:
+    mcr     p15, #0, r0, c14, c3, #0  @ write virtual timer timerval register
+    bx      lr
+.globl set_timer_control
+set_timer_control:
+    mcr     p15, #0, r0, c14, c3, #1  @ write virtual timer control register
+    bx      lr
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_cpu_icache_flush
+rt_cpu_icache_flush:
+    mov r0, #0
+    mcr p15, 0, r0, c7, c5, 0       @ I+BTB cache invalidate
+    dsb
+    isb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cpu.c b/bsp/raspberry-pi/raspi3-32/cpu/cpu.c
new file mode 100644
index 0000000000..4d02ca35e1
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/cpu.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+#include "cp15.h"
+
+int rt_hw_cpu_id(void)
+{
+    int cpu_id;
+    __asm__ volatile (
+            "mrc p15, 0, %0, c0, c0, 5"
+            :"=r"(cpu_id)
+            );
+    cpu_id &= 0xf;
+    return cpu_id;
+};
+
+
+#ifdef RT_USING_SMP
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    lock->slock = 0;
+}
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    unsigned long tmp;
+    unsigned long newval;
+    rt_hw_spinlock_t lockval;
+    __asm__ __volatile__(
+            "pld [%0]"
+            ::"r"(&lock->slock)
+            );
+
+    __asm__ __volatile__(
+            "1: ldrex   %0, [%3]\n"
+            "   add %1, %0, %4\n"
+            "   strex   %2, %1, [%3]\n"
+            "   teq %2, #0\n"
+            "   bne 1b"
+            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+            : "r" (&lock->slock), "I" (1 << 16)
+            : "cc");
+
+    while (lockval.tickets.next != lockval.tickets.owner) 
+    {
+        __WFE();
+        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
+    }
+
+    __DMB();
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    __DMB();
+    lock->tickets.owner++;
+    __DSB();
+    __SEV();
+}
+#endif /*RT_USING_SMP*/
+
+/**
+ * @addtogroup ARM CPU
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/*@}*/
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c
new file mode 100644
index 0000000000..c9e7c17f8f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/5/3       Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "cp15.h"
+#include <board.h>
+
+#define MAX_HANDLERS                72
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+const unsigned int VECTOR_BASE = 0x00;
+extern void rt_cpu_vector_set_base(unsigned int addr);
+extern int system_vectors;
+
+void rt_hw_vector_init(void)
+{
+    rt_cpu_vector_set_base((unsigned int)&system_vectors);
+}
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+extern int system_vectors;
+
+static void default_isr_handler(int vector, void *param)
+{
+#ifdef RT_USING_SMP
+    rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
+#else
+    rt_kprintf("unhandled irq: %d\n",vector);
+#endif
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_uint32_t index;
+
+    /* mask all of interrupts */
+    IRQ_DISABLE_BASIC = 0x000000ff;
+    IRQ_DISABLE1      = 0xffffffff;
+    IRQ_DISABLE2      = 0xffffffff;
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        isr_table[index].handler = default_isr_handler;
+        isr_table[index].param = NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
+        isr_table[index].counter = 0;
+#endif
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+
+    if (vector < 32)
+    {
+        IRQ_DISABLE1 = (1 << vector);
+    }
+    else if (vector < 64)
+    {
+        vector = vector % 32;
+        IRQ_DISABLE2 = (1 << vector);
+    }
+    else
+    {
+        vector = vector - 64;
+        IRQ_DISABLE_BASIC = (1 << vector);
+    }
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    if (vector < 32)
+    {
+        IRQ_ENABLE1 = (1 << vector);
+    }
+    else if (vector < 64)
+    {
+        vector = vector % 32;
+        IRQ_ENABLE2 = (1 << vector);
+    }
+    else
+    {
+        vector = vector - 64;
+        IRQ_ENABLE_BASIC = (1 << vector);
+    }
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+{
+    __DSB();
+    if (cpu_mask & 0x1)
+    {
+        send_ipi_msg(0, ipi_vector);
+    }
+    if (cpu_mask & 0x2)
+    {
+    	send_ipi_msg(1, ipi_vector);
+    }
+    if (cpu_mask & 0x4)
+    {
+    	send_ipi_msg(2, ipi_vector);
+    }
+    if (cpu_mask & 0x8)
+    {
+    	send_ipi_msg(3, ipi_vector);
+    }
+    __DSB();
+}
+#endif
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
+{
+    /* note: ipi_vector maybe different with irq_vector */
+    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
+}
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/interrupt.h b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.h
new file mode 100644
index 0000000000..9aae0f556a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.h
@@ -0,0 +1,18 @@
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/mmu.c b/bsp/raspberry-pi/raspi3-32/cpu/mmu.c
new file mode 100644
index 0000000000..b3541d2ad4
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/mmu.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "mmu.h"
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for (i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_init_mmu_table()
+{
+    /* set page table */
+    /* 4G 1:1 memory */
+    rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
+    /* IO memory region */
+    rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
+}
+
+void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
+                      rt_uint32_t size,
+                      rt_uint32_t paddrStart, rt_uint32_t attr)
+{
+    rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
+#ifndef RT_USING_SMP
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+#endif
+}
+
+
+void rt_hw_mmu_init(void)
+{
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/mmu.h b/bsp/raspberry-pi/raspi3-32/cpu/mmu.h
new file mode 100644
index 0000000000..6b0c25e990
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/mmu.h
@@ -0,0 +1,51 @@
+#ifndef MMU_H__
+#define MMU_H__
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3 << 2)  //cache_on, write_back
+#define CNB            (2 << 2)  //cache_on, write_through
+#define NCB            (1 << 2)  //cache_off,WR_BUF on
+#define NCNB           (0 << 2)  //cache_off,WR_BUF off
+#define AP_RW          (3 << 10) //supervisor=RW, user=RW
+#define AP_RO          (2 << 10) //supervisor=RW, user=RO
+#define XN             (1 << 4)  // eXecute Never
+#define SHARED         (1 << 16) /* shareable */
+#define SHAREDEVICE    (1 << 2)  /* shared device */
+#define STRONGORDER    (0 << 2)  /* strong ordered */
+#define MEMWBWA        ((1 << 12) | (3 << 2))     /* write back, write allocate */
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0 << 5)
+#define DOMAIN1        (0x1 << 5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK << 0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT << 2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW | DOMAIN0 | CB | DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW | DOMAIN0 | CNB | DESC_SEC)
+/* Read/Write without cache and write buffer */
+#define RW_NCNB        (AP_RW | DOMAIN0 | NCNB | DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW | DOMAIN0 | NCNB | DESC_SEC | XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW | DOMAIN1 | NCNB | DESC_SEC)
+
+/* device mapping type */
+#define DEVICE_MEM     (SHARED | SHAREDEVICE | RW_NCNBXN)
+/* normal memory mapping type */
+#define NORMAL_MEM     (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)
+#define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC)
+#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+
+void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
+                      rt_uint32_t size,
+                      rt_uint32_t paddrStart, rt_uint32_t attr);
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/stack.c b/bsp/raspberry-pi/raspi3-32/cpu/stack.c
new file mode 100644
index 0000000000..c2c60fbf49
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/stack.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+#include <armv7.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk      = (rt_uint32_t *)stack_addr;
+    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0xdeadbeef;                  /* r12 */
+    *(--stk) = 0xdeadbeef;                  /* r11 */
+    *(--stk) = 0xdeadbeef;                  /* r10 */
+    *(--stk) = 0xdeadbeef;                  /* r9 */
+    *(--stk) = 0xdeadbeef;                  /* r8 */
+    *(--stk) = 0xdeadbeef;                  /* r7 */
+    *(--stk) = 0xdeadbeef;                  /* r6 */
+    *(--stk) = 0xdeadbeef;                  /* r5 */
+    *(--stk) = 0xdeadbeef;                  /* r4 */
+    *(--stk) = 0xdeadbeef;                  /* r3 */
+    *(--stk) = 0xdeadbeef;                  /* r2 */
+    *(--stk) = 0xdeadbeef;                  /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+#ifdef RT_USING_LWP
+    *(--stk) = 0;       /* user lr */
+    *(--stk) = 0;       /* user sp*/
+#endif
+#ifdef RT_USING_FPU
+    *(--stk) = 0;       /* not use fpu*/
+#endif
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S b/bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S
new file mode 100644
index 0000000000..ec74213f07
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "../rtconfig.h"
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+#ifdef RT_USING_FPU
+.equ UND_Stack_Size,     0x00000400
+#else
+.equ UND_Stack_Size,     0x00000000
+#endif
+.equ SVC_Stack_Size,     0x00000400
+.equ ABT_Stack_Size,     0x00000000
+.equ RT_FIQ_STACK_PGSZ,  0x00000000
+.equ RT_IRQ_STACK_PGSZ,  0x00000800
+.equ USR_Stack_Size,     0x00000400
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
+
+.section .data.share.isr
+/* stack */
+
+#ifdef RT_USING_SMP
+.globl stack_start0
+.globl stack_top0
+.globl stack_start1
+.globl stack_top1
+.globl stack_start2
+.globl stack_top2
+.globl stack_start3
+.globl stack_top3
+stack_start0:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top0:
+
+stack_start1:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top1:
+
+stack_start2:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top2:
+
+stack_start3:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top3:
+
+.globl boot_indicate
+boot_indicate:
+.rept 16
+.byte 0
+.endr
+
+#else
+.globl stack_start
+.globl stack_top
+stack_start:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top:
+#endif
+
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+
+    /* Disable IRQ & FIQ */
+    cpsid if
+
+    /* Check for HYP mode */
+    mrs r0, cpsr_all
+    and r0, r0, #0x1F
+    mov r8, #0x1A
+    cmp r0, r8
+    beq overHyped
+    b continue
+
+overHyped: /* Get out of HYP mode */
+    ldr r1, =continue
+    msr ELR_hyp, r1
+    mrs r1, cpsr_all
+    and r1, r1, #0x1f    ;@ CPSR_MODE_MASK
+    orr r1, r1, #0x13    ;@ CPSR_MODE_SUPERVISOR
+    msr SPSR_hyp, r1
+    eret
+
+continue:
+
+    /* disable mmu */
+    bl      rt_cpu_mmu_disable
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+#ifdef RT_USING_SMP
+    mrc     p15, 0, r0, c0, c0, 5
+    ubfx    r0, r0, #0, #2
+    cmp     r0, #0
+    beq     1f
+    /* write boot indicate */
+    ldr     r5, = boot_indicate
+    str     r0, [r5, r0, lsl #2]
+    bl secondary_cpu_start
+    b .
+1:
+#endif
+    /* setup stack */
+#ifdef RT_USING_SMP
+    ldr     r0, =stack_top0
+#else
+    ldr     r0, =stack_top
+#endif
+    bl      stack_setup
+      
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+    bl rt_hw_init_mmu_table
+    bl init_mbox_mmu_map
+    bl rt_hw_mmu_init
+
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_FIQ_STACK_PGSZ
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_IRQ_STACK_PGSZ
+
+    /* come back to SVC mode */
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+    bx      lr
+
+.text
+
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+.section .text.isr, "ax"
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+.globl      rt_current_thread
+.globl      vmm_thread
+.globl      vmm_virq_check
+
+    .align  5
+.globl vector_irq
+vector_irq:
+#ifdef RT_USING_SMP
+    clrex
+      
+    stmfd   sp!, {r0, r1}
+    cps     #Mode_SVC
+    mov     r0, sp          /* svc_sp */
+    mov     r1, lr          /* svc_lr */
+
+    cps     #Mode_IRQ
+    sub     lr, lr, #4
+    stmfd   r0!, {r1, lr}       /* svc_lr, svc_pc */
+    stmfd   r0!, {r2 - r12}
+    ldmfd   sp!, {r1, r2}     /* original r0, r1 */
+    stmfd   r0!, {r1 - r2}
+    mrs     r1,  spsr         /* original mode */
+    stmfd   r0!, {r1}
+
+#ifdef RT_USING_LWP
+    stmfd   r0, {r13, r14}^ /* usr_sp, usr_lr */
+    sub   r0, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb r0!, {d0-d15}
+    vstmdb r0!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd r0!, {r5}
+1:
+    stmfd r0!, {r6}
+#endif
+    mov     r8, r0
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+    
+    cps     #Mode_SVC
+    mov     sp, r8
+    mov     r0, r8
+    
+    bl      rt_scheduler_do_irq_switch
+
+    b       rt_hw_context_switch_exit
+
+#else
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt. If the usr mode guest is
+    @ interrupted, this will just switch to the stack of kernel space.
+    @ save the registers in kernel space won't trigger data abort.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+#ifdef RT_USING_LWP
+    stmfd sp, {r13, r14}^  @push usr_sp, usr_lr
+    sub sp, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       @ get new task's stack pointer
+
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+1:
+#endif
+
+#ifdef RT_USING_LWP
+    ldmfd sp, {r13, r14}^  @pop usr_sp, usr_lr
+    add sp, #8
+#endif
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+#endif
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl  vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl  vector_undef
+vector_undef:
+    push_svc_reg
+    cps #Mode_UND
+    bl      rt_hw_trap_undef
+#ifdef RT_USING_FPU
+    ldr     lr, [sp, #15*4]
+    ldmia   sp, {r0 - r12}
+    add     sp, sp, #17 * 4
+    movs    pc, lr
+#endif
+    b       .
+
+    .align  5
+    .globl  vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl  vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl  vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .
+
+#ifdef RT_USING_SMP
+
+.global secondary_cpu_start
+secondary_cpu_start:
+    /* set vector base */
+    mrc p15, 0, r0, c1, c0, 0        
+    bic r0, #(1<<13)
+    mcr p15, 0, r0, c1, c0, 0
+    
+    /* setup stack */
+    mrc p15, 0, r0, c0, c0, 5
+    ubfx    r0, r0, #0, #2
+    ldr r1, =stack_top0
+    ldr r2, =ISR_Stack_Size
+    mul r3, r2, r0
+    add r0, r1, r3
+    bl  stack_setup
+    /* initialize the mmu table and enable mmu */
+    bl  rt_hw_mmu_init
+    b   secondary_cpu_c_start
+
+#endif
+
+;@ void arm_smp_enable(void);
+.globl arm_smp_enable
+arm_smp_enable:
+    mrc p15, 0, r0, c1, c0, 1   ;@ set SMP bit in ACTLR
+    orr r0, r0, #0x40
+    mcr p15, 0, r0, c1, c0, 1
+    bx lr
+/*
+    mrrc p15, 1, r0, r1, c15
+    orr r0, r0, #0x40
+    mcrr p15, 1, r0, r1, c15
+    dsb
+    isb
+    bx lr
+*/
+.text
+;@ void arm_smp_disable(void);
+.globl arm_smp_disable
+
+arm_smp_disable:
+    mrc p15, 0, r0, c1, c0, 1   ;@ clear SMP bit in ACTLR
+    bic r0, r0, #0x40
+    mcr p15, 0, r0, c1, c0, 1
+    bx lr
+/*
+    mrrc p15, 1, r0, r1, c15
+    bic r0, r0, #0x40
+    mcrr p15, 1, r0, r1, c15
+    bx lr
+*/
+
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/trap.c b/bsp/raspberry-pi/raspi3-32/cpu/trap.c
new file mode 100644
index 0000000000..f83f183695
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/trap.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
+ */
+
+#include <rthw.h>
+#include <board.h>
+#include <rtthread.h>
+
+#include "armv7.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    uint32_t irq;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+    uint32_t value = 0;
+    value = IRQ_PEND_BASIC & 0x3ff;
+#ifdef RT_USING_SMP
+    uint32_t mailbox_data;
+    uint32_t cpu_id = rt_hw_cpu_id();
+    uint32_t int_source = CORE_IRQSOURCE(cpu_id);
+    mailbox_data = IPI_MAILBOX_CLEAR(cpu_id);
+    if (int_source & 0x0f)
+    {
+        if (int_source & 0x08)
+        {
+            isr_func = isr_table[IRQ_ARM_TIMER].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_TIMER].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_TIMER].param;
+                isr_func(IRQ_ARM_TIMER, param);
+            }
+        }
+    }
+    if (int_source & 0xf0)
+    {
+        /*it's a ipi interrupt*/
+        if (mailbox_data & 0x1)
+        {
+            /* clear mailbox */
+            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;    
+            isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_MAILBOX].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_MAILBOX].param;
+                isr_func(IRQ_ARM_MAILBOX, param);
+            }
+        }
+        else 
+            CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
+    }
+#endif
+    /* local interrupt*/
+    if (value)
+    {
+        if (value & (1 << 8))
+        {
+            value = IRQ_PEND1;
+            irq = __rt_ffs(value) - 1;
+        }
+        else if (value & (1 << 9))
+        {
+            value = IRQ_PEND2;
+            irq = __rt_ffs(value) + 31;
+        }
+        else
+        {
+            value &= 0x0f;
+            irq = __rt_ffs(value) + 63;
+        }
+
+        /* get interrupt service routine */
+        isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif
+        if (isr_func)
+        {
+            /* Interrupt for myself. */
+            param = isr_table[irq].param;
+            /* turn to interrupt service routine */
+            isr_func(irq, param);
+        }
+    }
+}
+
+void rt_hw_trap_fiq(void)
+{
+
+}
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S b/bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S
new file mode 100644
index 0000000000..eebfe9c13b
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl    16,0xdeadbeef
diff --git a/bsp/raspberry-pi/raspi3-32/driver/Kconfig b/bsp/raspberry-pi/raspi3-32/driver/Kconfig
new file mode 100644
index 0000000000..aaa7110f1d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/Kconfig
@@ -0,0 +1,103 @@
+menu "Hardware Drivers Config"
+    menu "BCM Peripheral Drivers"
+        menuconfig BSP_USING_UART
+            bool "Using UART"
+            select RT_USING_SERIAL
+            default y
+
+            if BSP_USING_UART
+                config RT_USING_UART0
+                bool "Enabel UART 0"
+                default y
+
+                config RT_USING_UART1
+                    bool "Enabel UART 1"
+                    default n
+            endif
+         
+        config BSP_USING_PIN
+            bool "Using PIN"
+            select RT_USING_PIN
+            default y
+
+        menuconfig BSP_USING_SYSTIMER
+            bool "Enable SYSTIMER"
+            select RT_USING_HWTIMER
+            default n
+
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
+        endif
+
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C"
+            select RT_USING_I2C
+            default n
+
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                default n
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+        endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI"
+            select RT_USING_SPI
+            default n
+        
+        if BSP_USING_SPI   
+            config BSP_USING_SPI0_BUS
+                bool "Enable SPI0 BUS"
+                default n
+            config BSP_USING_SPI0_DEVICE0
+                bool "Enable SPI0 DEVICE0"
+                select BSP_USING_SPI0_BUS
+                default n
+            config BSP_USING_SPI0_DEVICE1
+                bool "Enable SPI0 DEVICE1"
+                select BSP_USING_SPI0_BUS
+                default n
+        endif
+
+        config BSP_USING_WDT
+            bool "Enable WDT"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+
+        if BSP_USING_RTC
+            config BSP_USING_ALARM
+                bool "Enable Alarm"
+                select RT_USING_ALARM
+                default n
+        endif
+        
+        menuconfig BSP_USING_SDIO
+            bool "Enable SDIO"
+            select RT_USING_SDIO
+            default n
+
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO0
+                bool "Enable SDIO0"
+                select RT_USING_SDIO
+                default n
+        endif
+        menuconfig BSP_USING_HDMI
+            bool "Enable HDMI"
+            select BSP_USING_SPI
+            default n
+    endmenu
+endmenu
diff --git a/bsp/raspberry-pi/raspi3-32/driver/SConscript b/bsp/raspberry-pi/raspi3-32/driver/SConscript
new file mode 100644
index 0000000000..c51b2c42bf
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/SConscript
@@ -0,0 +1,31 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split('''
+board.c
+drv_uart.c
+mbox.c
+''')
+CPPPATH = [cwd]
+
+if GetDepend('BSP_USING_SYSTIMER'):
+    src += ['drv_timer.c']
+if GetDepend('BSP_USING_PIN'):
+    src += ['drv_gpio.c']
+if GetDepend('BSP_USING_I2C'):
+    src += ['drv_i2c.c']
+if GetDepend('BSP_USING_WDT'):
+    src += ['drv_wdt.c']
+if GetDepend('BSP_USING_SPI'):
+    src += ['drv_spi.c']
+if GetDepend('BSP_USING_SDIO'):
+    src += ['drv_sdio.c']
+if GetDepend('BSP_USING_RTC'):
+    src += ['drv_rtc.c']
+if GetDepend('BSP_USING_HDMI'):
+    src += ['drv_fb.c']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi3-32/driver/board.c b/bsp/raspberry-pi/raspi3-32/driver/board.c
new file mode 100644
index 0000000000..a1b3d603c8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/board.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_timer.h"
+
+#include "cp15.h"
+
+#ifdef RT_USING_SMP
+unsigned int cntfrq;
+#endif
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    rt_tick_increase();
+#ifndef RT_USING_SMP
+    ARM_TIMER_IRQCLR = 0;
+#else
+    mask_cntv();
+    __DSB();
+    write_cntv_tval(cntfrq);
+    __DSB();
+    unmask_cntv();
+    __DSB();
+#endif
+}
+
+int rt_hw_timer_init()
+{
+#ifndef RT_USING_SMP
+    /* timer_clock = apb_clock/(pre_divider + 1) */
+    ARM_TIMER_PREDIV = (250 - 1);
+
+    ARM_TIMER_RELOAD = 0;
+    ARM_TIMER_LOAD   = 0;
+    ARM_TIMER_IRQCLR = 0;
+    ARM_TIMER_CTRL   = 0;
+
+    ARM_TIMER_RELOAD = 10000;
+    ARM_TIMER_LOAD   = 10000;
+
+    /* 23-bit counter, enable interrupt, enable timer */
+    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
+#else
+    __DSB();
+    cntfrq = 35000;
+    write_cntv_tval(cntfrq);
+    enable_cntv();
+    __DSB();
+    enable_cpu_timer_intr(rt_hw_cpu_id());
+#endif
+
+    rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IRQ_ARM_TIMER);
+    return 0;
+}
+#ifdef RT_USING_SMP
+extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
+
+void ipi_handler()
+{
+    rt_scheduler_ipi_handler(0,RT_NULL);
+}
+#endif
+void vector_copy(void)
+{
+    rt_memcpy((void*)0x0, (void*)0x8000, 64);
+}
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+void rt_hw_board_init(void)
+{
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
+    vector_copy();
+    rt_hw_vector_init();
+    /* initialize uart */
+    rt_hw_uart_init();
+    /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+#ifdef RT_USING_SMP
+    /* install IPI handle */
+    rt_hw_ipi_handler_install(IRQ_ARM_MAILBOX, ipi_handler);
+    rt_hw_interrupt_umask(IRQ_ARM_MAILBOX);
+    enable_cpu_ipi_intr(0);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+}
+
+
+void _reset(void);
+void secondary_cpu_start(void);
+
+#ifdef RT_USING_SMP
+void rt_hw_secondary_cpu_up(void)
+{
+    int i;
+    int retry,val;
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+    /*TODO maybe, there is some bug */
+    for (i = RT_CPUS_NR - 1; i>0; i-- )
+    {
+        rt_kprintf("boot cpu:%d\n", i);
+        setup_bootstrap_addr(i, (int)_reset);
+        __SEV();
+        __DSB();
+        __ISB();
+        retry = 10;
+        rt_thread_delay(RT_TICK_PER_SECOND/1000);
+        do
+        {
+            val = CORE_MAILBOX3_CLEAR(i);
+            if (val == 0)
+            {
+                rt_kprintf("start OK: CPU %d \n",i);
+                break;
+            }
+            rt_thread_delay(RT_TICK_PER_SECOND);
+
+            retry --;
+            if (retry <= 0)
+            {
+                rt_kprintf("can't start for CPU %d \n",i);
+                break;
+            }
+        } while (1);
+    }
+    __DSB();
+    __SEV();
+}
+
+void secondary_cpu_c_start(void)
+{
+    uint32_t id;
+    id = rt_hw_cpu_id();
+    rt_kprintf("cpu = 0x%08x\n",id);
+    rt_hw_timer_init();
+    rt_kprintf("cpu %d startup.\n",id);
+    rt_hw_vector_init();
+    enable_cpu_ipi_intr(id);
+    rt_hw_spin_lock(&_cpus_lock);
+    rt_system_scheduler_start();
+}
+
+void rt_hw_secondary_cpu_idle_exec(void)
+{
+    __WFE();
+}
+
+#endif
+
+
diff --git a/bsp/raspberry-pi/raspi3-32/driver/board.h b/bsp/raspberry-pi/raspi3-32/driver/board.h
new file mode 100644
index 0000000000..8736027c06
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/board.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+
+#include <rthw.h>
+#include  "raspi.h"
+
+#define __REG32 HWREG32
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 4 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
+
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c
new file mode 100644
index 0000000000..a24ca63377
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c
@@ -0,0 +1,508 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "mbox.h"
+#include "drv_fb.h"
+#include "mmu.h"
+
+#define CHAR_W          8
+#define CHAR_H          12
+
+#define COLOR_DELTA     0.05
+static struct rt_hdmi_fb_device _hdmi;
+
+// https://github.com/xinu-os/xinu/blob/1789b7a50b5b73c2ea76ebd764c54a034097d04d/device/framebuffer_rpi/font.c
+unsigned char FONT[] = {
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'!'*/
+0x00, 0x14, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'"'*/
+0x00, 0x00, 0x14, 0x14, 0x3e, 0x14, 0x3e, 0x14, 0x14, 0x00, 0x00, 0x00, /*'#'*/
+0x00, 0x00, 0x08, 0x3c, 0x0a, 0x1c, 0x28, 0x1e, 0x08, 0x00, 0x00, 0x00, /*'$'*/
+0x00, 0x00, 0x06, 0x26, 0x10, 0x08, 0x04, 0x32, 0x30, 0x00, 0x00, 0x00, /*'%'*/
+0x00, 0x00, 0x1c, 0x02, 0x02, 0x04, 0x2a, 0x12, 0x2c, 0x00, 0x00, 0x00, /*'&'*/
+0x00, 0x18, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'''*/
+0x20, 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x00, /*'('*/
+0x02, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x02, 0x00, /*')'*/
+0x00, 0x00, 0x00, 0x08, 0x2a, 0x1c, 0x2a, 0x08, 0x00, 0x00, 0x00, 0x00, /*'*'*/
+0x00, 0x00, 0x00, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /*'+'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*','*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'-'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*'.'*/
+0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x04, 0x04, 0x02, 0x02, 0x00, 0x00, /*'/'*/
+0x00, 0x1c, 0x22, 0x32, 0x2a, 0x26, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'0'*/
+0x00, 0x08, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'1'*/
+0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'2'*/
+0x00, 0x1c, 0x22, 0x20, 0x18, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'3'*/
+0x00, 0x10, 0x18, 0x18, 0x14, 0x14, 0x3e, 0x10, 0x38, 0x00, 0x00, 0x00, /*'4'*/
+0x00, 0x3e, 0x02, 0x02, 0x1e, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'5'*/
+0x00, 0x18, 0x04, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'6'*/
+0x00, 0x3e, 0x22, 0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x00, 0x00, 0x00, /*'7'*/
+0x00, 0x1c, 0x22, 0x22, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'8'*/
+0x00, 0x1c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x10, 0x0c, 0x00, 0x00, 0x00, /*'9'*/
+0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*':'*/
+0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*';'*/
+0x00, 0x00, 0x00, 0x30, 0x0c, 0x03, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, /*'<'*/
+0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, /*'='*/
+0x00, 0x00, 0x00, 0x03, 0x0c, 0x30, 0x0c, 0x03, 0x00, 0x00, 0x00, 0x00, /*'>'*/
+0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'?'*/
+0x00, 0x00, 0x1c, 0x22, 0x3a, 0x3a, 0x1a, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'@'*/
+0x00, 0x00, 0x08, 0x14, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x00, 0x00, 0x00, /*'A'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'B'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x02, 0x02, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'C'*/
+0x00, 0x00, 0x0e, 0x12, 0x22, 0x22, 0x22, 0x12, 0x0e, 0x00, 0x00, 0x00, /*'D'*/
+0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'E'*/
+0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'F'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x32, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'G'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'H'*/
+0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x3e, 0x00, 0x00, 0x00, /*'I'*/
+0x00, 0x00, 0x38, 0x20, 0x20, 0x20, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'J'*/
+0x00, 0x00, 0x22, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'K'*/
+0x00, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'L'*/
+0x00, 0x00, 0x22, 0x36, 0x2a, 0x2a, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'M'*/
+0x00, 0x00, 0x22, 0x26, 0x26, 0x2a, 0x32, 0x32, 0x22, 0x00, 0x00, 0x00, /*'N'*/
+0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'O'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'P'*/
+0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x30, 0x00, 0x00, /*'Q'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'R'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x1c, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'S'*/
+0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'T'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'U'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'V'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x2a, 0x2a, 0x36, 0x22, 0x00, 0x00, 0x00, /*'W'*/
+0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x14, 0x22, 0x22, 0x00, 0x00, 0x00, /*'X'*/
+0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'Y'*/
+0x00, 0x00, 0x3e, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'Z'*/
+0x38, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x38, 0x00, /*'['*/
+0x02, 0x02, 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x00, 0x00, /*'\'*/
+0x0e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x0e, 0x00, /*']'*/
+0x00, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'^'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, /*'_'*/
+0x00, 0x0c, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'`'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'a'*/
+0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'b'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x02, 0x02, 0x3c, 0x00, 0x00, 0x00, /*'c'*/
+0x00, 0x20, 0x20, 0x20, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'d'*/
+0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x3e, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'e'*/
+0x00, 0x38, 0x04, 0x04, 0x1e, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, /*'f'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'g'*/
+0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'h'*/
+0x00, 0x08, 0x08, 0x00, 0x0c, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'i'*/
+0x00, 0x10, 0x10, 0x00, 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0e, /*'j'*/
+0x00, 0x02, 0x02, 0x02, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x00, 0x00, 0x00, /*'k'*/
+0x00, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'l'*/
+0x00, 0x00, 0x00, 0x00, 0x16, 0x2a, 0x2a, 0x2a, 0x22, 0x00, 0x00, 0x00, /*'m'*/
+0x00, 0x00, 0x00, 0x00, 0x1a, 0x26, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'n'*/
+0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'o'*/
+0x00, 0x00, 0x00, 0x00, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, /*'p'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x20, /*'q'*/
+0x00, 0x00, 0x00, 0x00, 0x1a, 0x06, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'r'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x1c, 0x20, 0x1e, 0x00, 0x00, 0x00, /*'s'*/
+0x00, 0x08, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x08, 0x30, 0x00, 0x00, 0x00, /*'t'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'u'*/
+0x00, 0x00, 0x00, 0x00, 0x36, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'v'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x2a, 0x2a, 0x2a, 0x14, 0x00, 0x00, 0x00, /*'w'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x14, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, /*'x'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'y'*/
+0x00, 0x00, 0x00, 0x00, 0x3e, 0x10, 0x08, 0x04, 0x3e, 0x00, 0x00, 0x00, /*'z'*/
+0x20, 0x10, 0x10, 0x10, 0x10, 0x08, 0x10, 0x10, 0x10, 0x10, 0x20, 0x00, /*'{'*/
+0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, /*'|'*/
+0x02, 0x04, 0x04, 0x04, 0x04, 0x08, 0x04, 0x04, 0x04, 0x04, 0x02, 0x00, /*'}'*/
+0x00, 0x04, 0x2a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'~'*/
+0x00, 0x00, 0x00, 0x08, 0x08, 0x14, 0x14, 0x22, 0x3e, 0x00, 0x00, 0x00, /*DEL*/
+};
+
+void newline(fb_t* fb)
+{
+    uint8_t* to;
+    uint8_t* from;
+    int i;
+    fb->y++;
+    fb->x = 0;
+
+    if (fb->y == (fb->height / CHAR_H))
+    {
+
+        to = (uint8_t*) fb->addr;
+        from = to + (CHAR_H * fb->pitch);
+
+        for (i = 0; i < ((fb->height - CHAR_H) * fb->pitch); i++)
+        {
+            *to++ = *from++;
+        }
+
+        uint32_t *addr = (uint32_t*) (fb->addr) + (fb->height - CHAR_H) * fb->width;
+
+        for (i = 0; i < (CHAR_H * fb->width); i++)
+        {
+            *addr++ = fb->back;
+        }
+
+        fb->y--;
+    }
+}
+
+void clear_line(fb_t *fb, const int line)
+{
+    int i;
+    uint32_t* addr;
+    if (line > fb->height / CHAR_H)
+    {
+        fb->y = 0;
+    }
+    else
+    {
+        fb->y = line;
+    }
+
+    fb->x = 0;
+
+    addr = (uint32_t*) (fb->addr + (line * CHAR_H * fb->depth * fb->width));
+    for (i = 0; i < (CHAR_H * fb->width); i++)
+    {
+        *addr++ = fb->back;
+    }
+
+}
+
+void clear(fb_t *fb, const uint32_t color)
+{
+
+    uint32_t *addr = (uint32_t*) fb->addr;
+    uint32_t i;
+    for (i = 0; i < (fb->height * fb->width); i++)
+    {
+        *addr++ = color;
+    }
+    fb->x = 0;
+    fb->y = 0;
+
+}
+
+void fb_draw_char(fb_t *fb, char s)
+{
+    unsigned char* addr = (unsigned char*) fb->addr;
+    unsigned char *glyph = (unsigned char*) FONT + (s) * 12;
+    // calculate the offset on screen
+    int offs = (fb->y * CHAR_H * fb->pitch) + (fb->x * (CHAR_W + 1) * 4);
+    // variables
+    int i, j, line, mask, bytesperline = (CHAR_W + 7) / 8;
+    // display a character
+    for (j = 0; j < CHAR_H; j++)
+    {
+        // display one row
+        line = offs;
+        mask = 1;
+        for (i = 0; i < CHAR_W; i++)
+        {
+            // if bit set, we use white color, otherwise black
+            *((unsigned int*) (addr + line)) = ((int) *glyph) & mask ? fb->fore : fb->back;
+            mask <<= 1;
+            line += 4;
+        }
+        // adjust to next line
+        glyph += bytesperline;
+        offs += fb->pitch;
+    }
+}
+
+void fb_print(fb_t *fb, char *s)
+{
+
+    // draw next character if it's not zero
+    while (*s)
+    {
+        // handle carrige return
+        if (*s == '\r')
+        {
+            fb->x = 0;
+        }
+        else if (*s == '\n')
+        {
+            newline(fb);
+        }
+        else if (*s == '\t')
+        {
+            fb->x = ((fb->x + 4) >> 2) << 2;
+        }
+        else if (*s == '\b')
+        {
+            if (fb->x)
+            {
+                fb->x--;
+                fb_draw_char(fb, ' ');
+            }
+        }
+        else
+        {
+            fb_draw_char(fb, *s);
+            fb->x++;
+        }
+        // next character
+        if (fb->x == fb->width / CHAR_W)
+        {
+            newline(fb);
+        }
+        s++;
+    }
+}
+
+rt_err_t hdmi_fb_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+rt_err_t hdmi_fb_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size)
+{
+    return 0;
+}
+
+rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    fb_print(&_hdmi.fb, (char *) buffer);
+#ifdef BSP_USING_HDMI_DISPLAY
+    rt_device_t uart = rt_device_find("uart1");
+    int old_flag = uart->open_flag;
+    uart->open_flag |= RT_DEVICE_FLAG_STREAM;
+    rt_device_write(uart, 0, buffer, size);
+    uart->open_flag = old_flag;
+#endif
+    return size;
+}
+
+rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)
+{
+    return RT_EOK;
+}
+
+const static struct rt_device_ops hdmi_fb_ops = 
+{
+    RT_NULL,
+    hdmi_fb_open,
+    hdmi_fb_close,
+    hdmi_fb_read,
+    hdmi_fb_write,
+    hdmi_fb_control
+};
+
+static struct rt_device_graphic_info _hdmi_info;
+
+static void hdmi_draw_rect(const char* pixel, int x1, int y1, int x2, int y2)
+{
+    int i, j;
+    int line;
+    for (j = y1; j <= y2; j++)
+    {
+        line = (j * _hdmi.fb.pitch) + (x1 * 4);
+        for (i = x1; i <= x2; i++)
+        {
+            // if bit set, we use white color, otherwise black
+            *((unsigned int*) (_hdmi_info.framebuffer + line)) = *(unsigned int*) pixel;
+            line += 4;
+        }
+    }
+
+}
+
+static void hdmi_set_pixel(const char* pixel, int x, int y)
+{
+    *(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) = *(uint32_t *) pixel;
+}
+
+static void hdmi_get_pixel(char* pixel, int x, int y)
+{
+    uint32_t ret = 0;
+    ret = (*(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) & 0x00FFFFFF);
+    *pixel = ret;
+}
+
+static void hdmi_draw_hline(const char* pixel, int x1, int x2, int y)
+{
+    hdmi_draw_rect(pixel, x1, y, x2, y);
+}
+
+static void hdmi_draw_vline(const char* pixel, int x, int y1, int y2)
+{
+    hdmi_draw_rect(pixel, x, y1, x, y2);
+}
+
+static void hdmi_blit_line(const char* pixels, int x, int y, rt_size_t size)
+{
+    int i = 0;
+    uint32_t *pixel_base = (uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4));
+    uint32_t *colors = (uint32_t *) pixels;
+    for (i = 0; i < size; i++)
+    {
+        pixel_base[i] = colors[i];
+    }
+}
+
+static struct rt_device_graphic_ops hdmi_ops = 
+{
+    hdmi_set_pixel,
+    hdmi_get_pixel,
+    hdmi_draw_hline,
+    hdmi_draw_vline,
+    hdmi_blit_line
+};
+
+rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *name)
+{
+    struct rt_device *device;
+    RT_ASSERT(hdmi_fb != RT_NULL);
+
+    device = &hdmi_fb->parent;
+    device->user_data = &hdmi_ops;
+
+    /* set device type */
+    device->type = RT_Device_Class_Graphic;
+    /* initialize device interface */
+#ifdef RT_USING_DEVICE_OPS
+    device->ops = &hdmi_fb_ops;
+#else
+    device->init = RT_NULL;
+    device->open = hdmi_fb_open;
+    device->close = hdmi_fb_close;
+    device->read = hdmi_fb_read;
+    device->write = hdmi_fb_write;
+    device->control = hdmi_fb_control;
+#endif
+
+    /* register to device manager */
+    rt_device_register(device, name, RT_DEVICE_FLAG_RDWR);
+
+    return RT_EOK;
+}
+
+/**
+ * Show a picture
+ */
+void print_fb_info()
+{
+    rt_kprintf("FrameBuffer Info: \n \t width %x\t height %x\t depth %x\t addr %x\t size %x\t \n", fb_info.width,
+            fb_info.height, fb_info.depth, fb_info.addr, fb_info.size);
+    rt_kprintf("call mbox:%x,%x,%x,%x,%x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4]);
+}
+
+void hdmi_fb_init()
+{
+    unsigned int *mbox = (unsigned int*) MBOX_ADDR;
+    mbox[0] = 35 * 4;
+    mbox[1] = MBOX_REQUEST;
+
+    mbox[2] = 0x48003;  //set phy wh
+    mbox[3] = 8;
+    mbox[4] = 8;
+    mbox[5] = 640;         //FrameBufferInfo.width
+    mbox[6] = 480;          //FrameBufferInfo.height
+
+    mbox[7] = 0x48004;  //set virt wh
+    mbox[8] = 8;
+    mbox[9] = 8;
+    mbox[10] = 640;        //FrameBufferInfo.virtual_width
+    mbox[11] = 480;         //FrameBufferInfo.virtual_height
+
+    mbox[12] = 0x48009; //set virt offset
+    mbox[13] = 8;
+    mbox[14] = 8;
+    mbox[15] = 0;           //FrameBufferInfo.x_offset
+    mbox[16] = 0;           //FrameBufferInfo.y.offset
+
+    mbox[17] = 0x48005; //set depth
+    mbox[18] = 4;
+    mbox[19] = 4;
+    mbox[20] = 32;          //FrameBufferInfo.depth
+
+    mbox[21] = 0x48006; //set pixel order
+    mbox[22] = 4;
+    mbox[23] = 4;
+    mbox[24] = 1;           //RGB, not BGR preferably
+
+    mbox[25] = 0x40001; //get framebuffer, gets alignment on request
+    mbox[26] = 8;
+    mbox[27] = 8;
+    mbox[28] = 4096;        //FrameBufferInfo.pointer
+    mbox[29] = 0;           //FrameBufferInfo.size
+
+    mbox[30] = 0x40008; //get pitch
+    mbox[31] = 4;
+    mbox[32] = 4;
+    mbox[33] = 0;           //FrameBufferInfo.pitch
+
+    mbox[34] = MBOX_TAG_LAST;
+    if (mbox_call(MBOX_CH_PROP, MMU_DISABLE) && mbox[20] == 32 && mbox[28] != 0)
+    {
+        mbox[28] &= 0x3FFFFFFF;
+        _hdmi.fb.width = mbox[5];
+        _hdmi.fb.height = mbox[6];
+        _hdmi.fb.pitch = mbox[33];
+        //_hdmi.fb.addr = (void*)((unsigned long)mbox[28]);
+        _hdmi.fb.addr = (rt_uint32_t) mbox[28];
+        _hdmi.fb.size = mbox[29];
+        _hdmi.fb.depth = 32;
+        _hdmi.fb.x = 0;
+        _hdmi.fb.y = 0;
+        _hdmi.fb.fore = CONSOLE_WHITE;
+        _hdmi.fb.back = CONSOLE_BLACK;
+        rt_hdmi_fb_device_init(&_hdmi, "hdmi");
+        rt_hw_change_mmu_table(_hdmi.fb.addr, _hdmi.fb.size, _hdmi.fb.addr, DEVICE_MEM);
+        fb_info.width = _hdmi.fb.width;
+        fb_info.height = _hdmi.fb.height;
+        fb_info.addr = _hdmi.fb.addr;
+        fb_info.size = _hdmi.fb.size;
+        fb_info.pitch = _hdmi.fb.pitch;
+        fb_info.depth = _hdmi.fb.depth;
+        _hdmi_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888;
+        _hdmi_info.bits_per_pixel = _hdmi.fb.depth;
+        _hdmi_info.width = _hdmi.fb.width;
+        _hdmi_info.height = _hdmi.fb.height;
+        _hdmi_info.framebuffer = (rt_uint8_t *) _hdmi.fb.addr;
+    }
+}
+
+INIT_DEVICE_EXPORT(hdmi_fb_init);
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h
new file mode 100644
index 0000000000..b11589e769
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+#ifndef __DRV_FB_H__
+#define __DRV_FB_H__
+
+#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
+
+#define COLOR_BLACK RGB(0, 0, 0)
+
+#define COLOR_GREEN RGB(0, 255, 0)  
+ 
+#define COLOR_CYAN RGB(0, 255, 255) 
+
+#define COLOR_RED RGB(255, 0, 0)  
+
+#define COLOR_YELLOW RGB(255, 255, 0) 
+
+#define COLOR_WHITE RGB(255, 255, 255)   
+
+#define CONSOLE_WHITE COLOR_WHITE
+#define CONSOLE_BLACK COLOR_BLACK
+#define CONSOLE_GREEN COLOR_GREEN
+#define CONSOLE_CYAN COLOR_CYAN
+#define CONSOLE_RED COLOR_RED
+#define CONSOLE_YELLOW COLOR_YELLOW
+
+typedef struct
+{
+    rt_uint32_t width;
+    rt_uint32_t height;
+    rt_uint32_t vwidth;
+    rt_uint32_t vheight;
+    rt_uint32_t pitch;
+    rt_uint32_t depth;
+    rt_uint32_t fore;
+    rt_uint32_t back;
+    rt_uint32_t x;
+    rt_uint32_t y;
+    rt_uint32_t addr;
+    rt_uint32_t size;
+} fb_t;
+
+struct rt_hdmi_fb_device
+{
+    struct rt_device parent;
+    fb_t fb;
+};
+
+fb_t fb_info;
+void print_fb_info();
+void hdmi_fb_init();
+
+#endif/* __DRV_FB_H__ */
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c
new file mode 100644
index 0000000000..c239c56cf2
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_PIN
+/*
+ * gpio_int[0] for BANK0 (pins 0-27)
+ * gpio_int[1] for BANK1 (pins 28-45)
+ * gpio_int[2] for BANK2 (pins 46-53)
+ */
+static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM];
+
+void gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud)
+{
+    rt_uint8_t num = pin / 32;
+    rt_uint8_t shift = pin % 32;
+    BCM283X_GPIO_GPPUD = pud;
+    DELAY_MICROS(10);
+    BCM283X_GPIO_GPPUDCLK(num) = 1 << shift;
+    DELAY_MICROS(10);
+    BCM283X_GPIO_GPPUD = BCM283X_GPIO_PUD_OFF;
+    BCM283X_GPIO_GPPUDCLK(num) = 0 << shift;
+}
+
+static void gpio_ack_irq(int irq, bcm_gpio_pin pin)
+{
+    rt_uint32_t data;
+    data = IRQ_PEND2;
+    data &= (0x0 << (irq - 32));
+    IRQ_PEND2 = data;
+
+    data = IRQ_DISABLE2;
+    data |= (0x1 << (irq - 32));
+    IRQ_DISABLE2 = data;
+}
+
+void gpio_irq_disable(rt_uint8_t index, bcm_gpio_pin pin)
+{
+    int irq = 0;
+    rt_uint32_t  reg_value;
+    rt_uint8_t irq_type;
+    irq = IRQ_GPIO0 + index;
+
+    gpio_ack_irq(irq, pin);
+
+    irq_type = _g_gpio_irq_tbl[index].irq_type[pin];
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t mask = 1 << shift;
+
+    switch (irq_type)
+    {
+    case PIN_IRQ_MODE_RISING:
+        reg_value = BCM283X_GPIO_GPREN(pin /32);
+        BCM283X_GPIO_GPREN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_FALLING:
+        reg_value = BCM283X_GPIO_GPFEN(pin /32);
+        BCM283X_GPIO_GPFEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_RISING_FALLING:
+        reg_value = BCM283X_GPIO_GPAREN(pin /32);
+        BCM283X_GPIO_GPAREN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        reg_value = BCM283X_GPIO_GPAFEN(pin /32);
+        BCM283X_GPIO_GPAFEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_HIGH_LEVEL:
+        reg_value = BCM283X_GPIO_GPHEN(pin /32);
+        BCM283X_GPIO_GPHEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_LOW_LEVEL:
+        reg_value = BCM283X_GPIO_GPLEN(pin /32);
+        BCM283X_GPIO_GPLEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    }
+}
+
+void gpio_irq_enable(rt_uint8_t index, bcm_gpio_pin pin)
+{
+    rt_uint32_t offset;
+    rt_uint32_t data;
+
+    offset = pin;
+    if (index == 0)
+        offset = IRQ_GPIO0 - 32;
+    else if (index == 1)
+        offset = IRQ_GPIO1 - 32;
+    else
+        offset = IRQ_GPIO2 - 32;
+
+    data = IRQ_ENABLE2;
+    data |= 0x1 << offset;
+    IRQ_ENABLE2 = data;
+
+}
+
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    RT_ASSERT(!(mode & 0x8));
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_OUTP);
+        break;
+    case PIN_MODE_INPUT:
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case PIN_MODE_INPUT_PULLUP:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case PIN_MODE_INPUT_PULLDOWN:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_DOWN);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case PIN_MODE_OUTPUT_OD:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_OFF);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_OUTP);
+        break;
+    }
+}
+
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    RT_ASSERT(!(value & 0xE));
+
+    if (value)
+        BCM283X_GPIO_GPSET(pin / 32) |= (1 << (pin %32));
+    else
+        BCM283X_GPIO_GPCLR(pin / 32) |= (0 << (pin %32));
+
+}
+
+static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    return (BCM2835_GPIO_GPLEV(pin / 32) & (1 << (pin % 32)))? PIN_HIGH : PIN_LOW;
+}
+
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+
+    rt_uint8_t index;
+    rt_uint32_t  reg_value;
+    if (pin <= 27)
+        index = 0;
+    else if (pin <= 45)
+        index = 1;
+    else
+        index = 2;
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = hdr;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = args;
+    _g_gpio_irq_tbl[index].irq_type[pin]  = mode;
+
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t mask = 1 << shift;
+
+    switch (mode)
+    {
+    case PIN_IRQ_MODE_RISING:
+        reg_value = BCM283X_GPIO_GPREN(pin /32);
+        BCM283X_GPIO_GPREN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    case PIN_IRQ_MODE_FALLING:
+        reg_value = BCM283X_GPIO_GPFEN(pin /32);
+        BCM283X_GPIO_GPFEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    case PIN_IRQ_MODE_RISING_FALLING:
+        reg_value = BCM283X_GPIO_GPAREN(pin /32);
+        BCM283X_GPIO_GPAREN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        reg_value = BCM283X_GPIO_GPAFEN(pin /32);
+        BCM283X_GPIO_GPAFEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    case PIN_IRQ_MODE_HIGH_LEVEL:
+        reg_value = BCM283X_GPIO_GPHEN(pin /32);
+        BCM283X_GPIO_GPHEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    case PIN_IRQ_MODE_LOW_LEVEL:
+        reg_value = BCM283X_GPIO_GPLEN(pin /32);
+        BCM283X_GPIO_GPLEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        break;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+
+    rt_uint8_t index;
+    if (pin <= 27)
+        index = 0;
+    else if (pin <= 45)
+        index = 1;
+    else
+        index = 2;
+
+    gpio_irq_disable(index, pin);
+
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = RT_NULL;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = RT_NULL;
+    _g_gpio_irq_tbl[index].irq_type[pin]  = RT_NULL;
+
+    return RT_EOK;
+}
+
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+
+    rt_uint8_t index;
+    if (pin <= 27)
+        index = 0;
+    else if (pin <= 45)
+        index = 1;
+    else
+        index = 2;
+
+    if (enabled)
+        gpio_irq_enable(index, pin);
+    else
+        gpio_irq_disable(index, pin);
+
+    return RT_EOK;
+}
+
+static void gpio_irq_handler(int irq, void *param)
+{
+    struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param;
+    rt_uint32_t pin;
+    rt_uint32_t value;
+    rt_uint32_t tmpvalue;
+
+    if (irq == IRQ_GPIO0)
+    {
+        /* 0~27 */
+
+        value = BCM283X_GPIO_GPEDS(0);
+        value &= 0x0fffffff;
+        pin = 0;
+        BCM283X_GPIO_GPEDS(0) = 0;
+    }
+    else if (irq == IRQ_GPIO1)
+    {
+        /* 28-45 */
+        tmpvalue = BCM283X_GPIO_GPEDS(0);
+        tmpvalue &= (~0x0fffffff);
+
+        value = BCM283X_GPIO_GPEDS(1);
+        value &= 0x3fff;
+        value = (value<<4) | tmpvalue;
+        pin = 28;
+        BCM283X_GPIO_GPEDS(0) = 0;
+        BCM283X_GPIO_GPEDS(1) = 0;
+    }
+    else if (irq == IRQ_GPIO2)
+    {
+        /* 46-53 */
+        value = BCM283X_GPIO_GPEDS(1);
+        value &= (~0x3fff);
+        value &= 0xff600000;
+        pin = 46;
+        BCM283X_GPIO_GPEDS(1) = 0;
+    }
+
+    while (value)
+    {
+        if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL))
+        {
+            irq_def->irq_cb[pin](irq_def->irq_arg[pin]);
+            gpio_ack_irq(irq,pin);
+        }
+        pin++;
+        value = value >> 1;
+    }
+}
+
+static const struct rt_pin_ops ops =
+{
+    raspi_pin_mode,
+    raspi_pin_write,
+    raspi_pin_read,
+    raspi_pin_attach_irq,
+    raspi_pin_detach_irq,
+    raspi_pin_irq_enable,
+};
+#endif
+
+int rt_hw_gpio_init(void)
+{
+#ifdef BSP_USING_PIN
+    rt_device_pin_register("gpio", &ops, RT_NULL);
+
+    /* install ISR */
+    rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO0);
+
+    rt_hw_interrupt_install(IRQ_GPIO1, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO1);
+
+    rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO2);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gpio_init);
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h
new file mode 100644
index 0000000000..ce0be096e8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "interrupt.h"
+#include "board.h"
+
+#define GPIO_IRQ_NUM 3
+
+#define IRQ_GPIO0               49
+#define IRQ_GPIO1               50
+#define IRQ_GPIO2               51
+#define IRQ_GPIO3               52
+
+struct gpio_irq_def
+{
+    void  *irq_arg[32];
+    void (*irq_cb[32])(void *param);
+    rt_uint8_t irq_type[32];
+};
+
+enum gpio_irq_clock
+{
+    GPIO_IRQ_LOSC_32KHZ = 0,
+    GPIO_IRQ_HOSC_24MHZ
+};
+
+int rt_hw_gpio_init(void);
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c
new file mode 100644
index 0000000000..35ab7c36d7
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_i2c.h"
+
+//Maybe redefined
+typedef unsigned long                   rt_ubase_t;
+typedef rt_ubase_t                      rt_size_t;
+
+rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag)
+{
+    rt_uint32_t status;
+    rt_uint32_t remaining = len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    BCM283X_BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
+    /* Clear Status */
+    BCM283X_BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
+    /* Set Data Length */
+    BCM283X_BSC_DLEN(base) = len;
+    if (flag)
+    {
+        /* Start read */
+        BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ;
+        /* wait for transfer to complete */
+        while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
+        {
+            /* we must empty the FIFO as it is populated and not use any delay */
+            while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
+            {
+                /* Read from FIFO, no barrier */
+                buf[i] = BCM283X_BSC_FIFO(base);
+                i++;
+                remaining--;
+            }
+        }
+        /* transfer has finished - grab any remaining stuff in FIFO */
+        while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
+        {
+            /* Read from FIFO, no barrier */
+            buf[i] = BCM283X_BSC_FIFO(base);
+            i++;
+            remaining--;
+        }
+    }
+    else
+    {
+        /* pre populate FIFO with max buffer */
+        while (remaining && (i < BSC_FIFO_SIZE))
+        {
+            BCM283X_BSC_FIFO(base) = buf[i];
+            i++;
+            remaining--;
+        }
+
+        /* Enable device and start transfer */
+        BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST;
+
+        /* Transfer is over when BCM2835_BSC_S_DONE */
+        while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
+        {
+            while (remaining && (BCM283X_BSC_S(base) & BSC_S_TXD))
+            {
+                /* Write to FIFO */
+                BCM283X_BSC_FIFO(base) = buf[i];
+                i++;
+                remaining--;
+            }
+        }
+    }
+
+    status = BCM283X_BSC_S(base);
+    if (status & BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+    else if (status & BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+    BCM283X_BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE);
+
+    return reason;
+}
+
+struct raspi_i2c_hw_config
+{
+    rt_uint8_t bsc_num;
+    rt_uint8_t sdl_pin;
+    rt_uint8_t scl_pin;
+    rt_uint8_t sdl_mode;
+    rt_uint8_t scl_mode;
+};
+
+#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1))
+
+static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                      rt_uint32_t,
+                                      rt_uint32_t);
+
+static rt_uint32_t i2c_byte_wait_us = 0;
+static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    rt_size_t i;
+    rt_uint8_t reason;
+    RT_ASSERT(bus != RT_NULL);
+
+    volatile rt_uint32_t base = (volatile rt_uint32_t)(bus->parent.user_data);
+
+    if (bus->addr == 0)
+        base = BCM283X_BSC0_BASE;
+    else
+        base = BCM283X_BSC1_BASE;
+
+    BCM283X_BSC_A(base) = msgs->addr;
+
+    for (i = 0; i < num; i++)
+    {
+        if (msgs[i].flags & RT_I2C_RD)
+            reason = i2c_read_or_write(base, msgs->buf, msgs->len, 1);
+        else
+            reason = i2c_read_or_write(base, msgs->buf, msgs->len, 0);
+    }
+    return (reason == 0)? i : 0;
+}
+
+static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    return 0;
+}
+static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                      rt_uint32_t cmd,
+                                      rt_uint32_t arg)
+{
+    return RT_EOK;
+}
+
+static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
+{
+    .master_xfer = raspi_i2c_mst_xfer,
+    .slave_xfer = raspi_i2c_slv_xfer,
+    .i2c_bus_control = raspi_i2c_bus_control,
+};
+
+
+static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg)
+{
+    RT_ASSERT(cfg != RT_NULL);
+
+    volatile rt_uint32_t base = cfg->scl_mode ? BCM283X_BSC1_BASE : BCM283X_BSC0_BASE;
+
+    GPIO_FSEL(cfg->sdl_pin, cfg->sdl_mode); /* SDA */
+    GPIO_FSEL(cfg->scl_pin, cfg->scl_mode); /* SCL */
+
+    /* use 0xFFFE mask to limit a max value and round down any odd number */
+    rt_uint32_t divider = (BCM283X_CORE_CLK_HZ / 10000) & 0xFFFE;
+    BCM283X_BSC_DIV(base) = (rt_uint16_t) divider;
+    i2c_byte_wait_us = (divider * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
+
+    return RT_EOK;
+}
+#endif
+
+#if defined (BSP_USING_I2C0)
+#define I2C0_BUS_NAME    "i2c0"
+static struct raspi_i2c_hw_config hw_device0 =
+{
+    .bsc_num = 0,
+    .sdl_pin = RPI_GPIO_P1_27,
+    .scl_pin = RPI_GPIO_P1_28,
+    .sdl_mode = BCM283X_GPIO_FSEL_ALT0,
+    .scl_mode = BCM283X_GPIO_FSEL_ALT0,
+};
+
+struct rt_i2c_bus_device device0 =
+{
+    .ops = &raspi_i2c_ops,
+    .addr = 0,
+};
+
+#endif
+
+#if defined (BSP_USING_I2C1)
+#define I2C1_BUS_NAME    "i2c1"
+static struct raspi_i2c_hw_config hw_device1 =
+{
+    .bsc_num = 1,
+    .sdl_pin = RPI_GPIO_P1_03,
+    .scl_pin = RPI_GPIO_P1_05,
+    .sdl_mode = BCM283X_GPIO_FSEL_ALT0,
+    .scl_mode = BCM283X_GPIO_FSEL_ALT0,
+};
+struct rt_i2c_bus_device device1 =
+{
+    .ops = &raspi_i2c_ops,
+    .addr = 1,
+};
+
+#endif
+
+int rt_hw_i2c_init(void)
+{
+#if defined(BSP_USING_I2C0)
+    raspi_i2c_configure(&hw_device0);
+    rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME);
+#endif
+
+#if defined(BSP_USING_I2C1)
+    raspi_i2c_configure(&hw_device1);
+    rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h
new file mode 100644
index 0000000000..ff9e8ca724
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_I2C_H__
+#define __DRV_I2C_H__
+
+#include <rtdevice.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+struct raspi_master_config_t
+{
+    rt_uint8_t sdl_pin;
+    rt_uint8_t scl_pin;
+    rt_uint8_t sdl_pin_mode;
+    rt_uint8_t scl_pin_mode;
+    rt_uint8_t slave_address;
+    rt_uint32_t bsc_base;
+    rt_uint16_t clk_div;
+};
+
+struct raspi_i2c_bus
+{
+    struct rt_i2c_bus_device device;
+    struct rt_i2c_msg *msg;
+    rt_uint32_t msg_cnt;
+    volatile rt_uint32_t msg_ptr;
+    volatile rt_uint32_t dptr;
+    char *device_name;
+    struct raspi_master_config_t *cfg;
+};
+
+int rt_hw_i2c_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c
new file mode 100644
index 0000000000..8a33e2be64
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_rtc.h"
+
+#ifdef BSP_USING_RTC
+
+#define RTC_I2C_BUS_NAME      "i2c0"
+#define RTC_ADDR            0x68
+
+static struct rt_device rtc_device;
+static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+
+rt_uint8_t buf[]=
+{
+    0x00, 0x00, 0x43, 0x15, 0x05, 0x01, 0x03, 0x19
+};
+
+
+rt_uint8_t i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len)
+{
+    rt_uint32_t remaining = cmds_len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
+
+    /* Clear Status */
+    BCM283X_BSC_S(BCM283X_BSC0_BASE) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
+
+    /* Set Data Length */
+    BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = cmds_len;
+
+    /* pre populate FIFO with max buffer */
+    while (remaining && (i < BSC_FIFO_SIZE))
+    {
+        BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = cmds[i];
+        i++;
+        remaining--;
+    }
+
+    /* Enable device and start transfer */
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) |= BSC_C_I2CEN | BSC_C_ST;
+
+    /* poll for transfer has started (way to do repeated start, from BCM2835 datasheet) */
+    while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_TA))
+    {
+        /* Linux may cause us to miss entire transfer stage */
+        if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE)
+            break;
+    }
+
+    remaining = buf_len;
+    i = 0;
+
+    /* Send a repeated start with read bit set in address */
+    BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = buf_len;
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_C_I2CEN | BSC_C_ST  | BSC_C_READ;
+
+    /* Wait for write to complete and first byte back. */
+  //  DELAYMICROS(i2c_byte_wait_us * (cmds_len + 1));
+
+    /* wait for transfer to complete */
+    while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE))
+    {
+        /* we must empty the FIFO as it is populated and not use any delay */
+        while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_RXD))
+        {
+        /* Read from FIFO, no barrier */
+        buf[i] = BCM283X_BSC_FIFO(BCM283X_BSC0_BASE);
+        i++;
+        remaining--;
+        }
+    }
+
+    /* transfer has finished - grab any remaining stuff in FIFO */
+    while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_RXD))
+    {
+        /* Read from FIFO */
+        buf[i] = BCM283X_BSC_FIFO(BCM283X_BSC0_BASE);
+        i++;
+        remaining--;
+    }
+
+    /* Received a NACK */
+    if (BCM283X_BSC_S(BCM283X_BSC0_BASE)  & BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+
+    /* Received Clock Stretch Timeout */
+    else if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+
+    /* Not all data is sent */
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) = (BSC_S_DONE &BSC_S_DONE);
+
+    return reason;
+}
+
+rt_uint8_t i2c_write(rt_uint8_t* buf, rt_uint32_t len)
+{
+    rt_uint32_t remaining = len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    BCM283X_BSC_C(BCM283X_BSC0_BASE)  |= BSC_C_CLEAR_1 & BSC_C_CLEAR_1;
+    /* Clear Status */
+    BCM283X_BSC_S(BCM283X_BSC0_BASE) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
+    /* Set Data Length */
+    BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = len;
+    /* pre populate FIFO with max buffer */
+    while (remaining && (i < BSC_FIFO_SIZE))
+    {
+        BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = buf[i];
+        i++;
+        remaining--;
+    }
+
+    /* Enable device and start transfer */
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_C_I2CEN | BSC_C_ST;
+
+    /* Transfer is over when BCM2835_BSC_S_DONE */
+    while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE))
+    {
+        while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_TXD))
+        {
+        /* Write to FIFO */
+        BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = buf[i];
+        i++;
+        remaining--;
+        }
+    }
+
+    /* Received a NACK */
+    if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+
+    /* Received Clock Stretch Timeout */
+    else if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+
+    /* Not all data is sent */
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+
+    BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_S_DONE & BSC_S_DONE;
+    return reason;
+}
+
+
+static time_t raspi_get_timestamp(void)
+{
+    struct tm tm_new = {0};
+    buf[0] = 0;
+
+    i2c_write_read_rs((char*)buf, 1, (char*)buf, 7);
+
+    tm_new.tm_year = ((buf[6] / 16) + 0x30) * 10 + (buf[6] % 16) + 0x30;
+    tm_new.tm_mon  = ((buf[5] & 0x1F) / 16 + 0x30) + (buf[5] & 0x1F) % 16+ 0x30;
+    tm_new.tm_mday = ((buf[4] & 0x3F) / 16 + 0x30) + (buf[4] & 0x3F) % 16+ 0x30;
+    tm_new.tm_hour = ((buf[2] & 0x3F) / 16 + 0x30) + (buf[2] & 0x3F) % 16+ 0x30;
+    tm_new.tm_min  = ((buf[1] & 0x7F) / 16 + 0x30) + (buf[1] & 0x7F) % 16+ 0x30;
+    tm_new.tm_sec  = ((buf[0] & 0x7F) / 16 + 0x30) + (buf[0] & 0x7F) % 16+ 0x30;
+
+    return mktime(&tm_new);
+}
+
+static int raspi_set_timestamp(time_t timestamp)
+{
+    struct tm *tblock;
+    tblock = localtime(&timestamp);
+    buf[0] = 0;
+    buf[1] = tblock->tm_sec;
+    buf[2] = tblock->tm_min;
+    buf[3] = tblock->tm_hour;
+    buf[4] = tblock->tm_wday;
+    buf[5] = tblock->tm_mday;
+    buf[6] = tblock->tm_mon;
+    buf[7] = tblock->tm_year;
+
+    i2c_write(buf, 8);
+
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_init(rt_device_t dev)
+{
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(RTC_I2C_BUS_NAME);
+    raspi_set_timestamp(0);
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    GPIO_FSEL(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_ALT0); /* SDA */
+    GPIO_FSEL(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_ALT0); /* SCL */
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_close(rt_device_t dev)
+{
+    GPIO_FSEL(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_INPT); /* SDA */
+    GPIO_FSEL(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_INPT); /* SCL */
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+
+    RT_ASSERT(dev != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+        *(rt_uint32_t *)args = raspi_get_timestamp();
+        break;
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+        raspi_set_timestamp(*(time_t *)args);
+        break;
+    default:
+        return RT_EINVAL;
+    }
+    return RT_EOK;
+}
+
+static rt_size_t raspi_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer);
+    return size;
+}
+
+static rt_size_t raspi_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer);
+    return size;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops raspi_rtc_ops =
+{
+    .init = raspi_rtc_init,
+    .open = raspi_rtc_open,
+    .close = raspi_rtc_close,
+    .read = raspi_rtc_read,
+    .write = raspi_rtc_write,
+    .control = raspi_rtc_control
+};
+#endif
+
+int rt_hw_rtc_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+    rtc_device.type        = RT_Device_Class_RTC;
+    rtc_device.rx_indicate = RT_NULL;
+    rtc_device.tx_complete = RT_NULL;
+
+#ifdef RT_USING_DEVICE_OPS
+    rtc_device.ops        = &raspi_rtc_ops;
+#else
+    rtc_device.init    = raspi_rtc_init;
+    rtc_device.open    = raspi_rtc_open;
+    rtc_device.close   = raspi_rtc_close;
+    rtc_device.read    = raspi_rtc_read;
+    rtc_device.write   = raspi_rtc_write;
+    rtc_device.control = raspi_rtc_control;
+#endif
+
+    rtc_device.user_data   = RT_NULL;
+
+    /* register a rtc device */
+    ret = rt_device_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR);
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+#endif /* BSP_USING_RTC */
+
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h
new file mode 100644
index 0000000000..d850defa68
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_RTC_H__
+#define __DRV_RTC_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+
+int rt_hw_rtc_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c
new file mode 100644
index 0000000000..c547419ca2
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c
@@ -0,0 +1,580 @@
+/*
+ * File      : drv_sdio.c
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_sdio.h"
+
+static rt_uint32_t sdCommandTable[] = {
+    SD_CMD_INDEX(0),
+    SD_CMD_RESERVED(1),
+    SD_CMD_INDEX(2) | SD_RESP_R2,
+    SD_CMD_INDEX(3) | SD_RESP_R1,
+    SD_CMD_INDEX(4),
+    SD_CMD_RESERVED(5), //SD_CMD_INDEX(5) | SD_RESP_R4,
+    SD_CMD_INDEX(6) | SD_RESP_R1,
+    SD_CMD_INDEX(7) | SD_RESP_R1b,
+    SD_CMD_INDEX(8) | SD_RESP_R1,
+    SD_CMD_INDEX(9) | SD_RESP_R2,
+    SD_CMD_INDEX(10) | SD_RESP_R2,
+    SD_CMD_INDEX(11) | SD_RESP_R1,
+    SD_CMD_INDEX(12) | SD_RESP_R1b | SD_CMD_TYPE_ABORT,
+    SD_CMD_INDEX(13) | SD_RESP_R1,
+    SD_CMD_RESERVED(14),
+    SD_CMD_INDEX(15),
+    SD_CMD_INDEX(16) | SD_RESP_R1,
+    SD_CMD_INDEX(17) | SD_RESP_R1 | SD_DATA_READ,
+    SD_CMD_INDEX(18) | SD_RESP_R1 | SD_DATA_READ | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN,
+    SD_CMD_INDEX(19) | SD_RESP_R1 | SD_DATA_READ,
+    SD_CMD_INDEX(20) | SD_RESP_R1b,
+    SD_CMD_RESERVED(21),
+    SD_CMD_RESERVED(22),
+    SD_CMD_INDEX(23) | SD_RESP_R1,
+    SD_CMD_INDEX(24) | SD_RESP_R1 | SD_DATA_WRITE,
+    SD_CMD_INDEX(25) | SD_RESP_R1 | SD_DATA_WRITE | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN,
+    SD_CMD_INDEX(26) | SD_RESP_R1 | SD_DATA_WRITE, //add
+    SD_CMD_INDEX(27) | SD_RESP_R1 | SD_DATA_WRITE,
+    SD_CMD_INDEX(28) | SD_RESP_R1b,
+    SD_CMD_INDEX(29) | SD_RESP_R1b,
+    SD_CMD_INDEX(30) | SD_RESP_R1 | SD_DATA_READ,
+    SD_CMD_RESERVED(31),
+    SD_CMD_INDEX(32) | SD_RESP_R1,
+    SD_CMD_INDEX(33) | SD_RESP_R1,
+    SD_CMD_RESERVED(34),
+    SD_CMD_INDEX(35) | SD_RESP_R1, //add
+    SD_CMD_INDEX(36) | SD_RESP_R1, //add
+    SD_CMD_RESERVED(37),
+    SD_CMD_INDEX(38) | SD_RESP_R1b,
+    SD_CMD_INDEX(39) | SD_RESP_R4, //add
+    SD_CMD_INDEX(40) | SD_RESP_R5, //add
+    SD_CMD_INDEX(41) | SD_RESP_R3, //add, mov from harbote
+    SD_CMD_RESERVED(42) | SD_RESP_R1,
+    SD_CMD_RESERVED(43),
+    SD_CMD_RESERVED(44),
+    SD_CMD_RESERVED(45),
+    SD_CMD_RESERVED(46),
+    SD_CMD_RESERVED(47),
+    SD_CMD_RESERVED(48),
+    SD_CMD_RESERVED(49),
+    SD_CMD_RESERVED(50),
+    SD_CMD_INDEX(51) | SD_RESP_R1 | SD_DATA_READ,
+    SD_CMD_RESERVED(52),
+    SD_CMD_RESERVED(53),
+    SD_CMD_RESERVED(54),
+    SD_CMD_INDEX(55) | SD_RESP_R3,
+    SD_CMD_INDEX(56) | SD_RESP_R1 | SD_CMD_ISDATA,
+    SD_CMD_RESERVED(57),
+    SD_CMD_RESERVED(58),
+    SD_CMD_RESERVED(59),
+    SD_CMD_RESERVED(60),
+    SD_CMD_RESERVED(61),
+    SD_CMD_RESERVED(62),
+    SD_CMD_RESERVED(63)
+};
+
+static inline rt_uint32_t read32(rt_uint32_t addr)
+{
+    return (*((volatile rt_uint32_t *)(addr)));
+}
+
+static inline void write32(rt_uint32_t addr, rt_uint32_t value)
+{
+    *((volatile rt_uint32_t *)(addr)) = value;
+}
+
+rt_err_t sd_int(struct sdhci_pdata_t * pdat, unsigned int mask)
+{
+    unsigned int r;
+    unsigned int m = mask | INT_ERROR_MASK;
+    int cnt = 1000000;
+    while (!(read32(pdat->virt + EMMC_INTERRUPT) & (m | INT_ERROR_MASK)) && cnt--)
+        DELAY_MICROS(1);
+    r = read32(pdat->virt + EMMC_INTERRUPT);
+    if (cnt <= 0 || (r & INT_CMD_TIMEOUT) || (r & INT_DATA_TIMEOUT))
+    {
+        write32(pdat->virt + EMMC_INTERRUPT, r);
+        rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS));
+        return -RT_ETIMEOUT;
+    }
+    else if (r & INT_ERROR_MASK)
+    {
+        write32(pdat->virt + EMMC_INTERRUPT, r);
+        rt_kprintf("send cmd/data error %x -> %x\n",r, read32(pdat->virt + EMMC_INTERRUPT));
+        return -RT_ERROR;
+    }
+    write32(pdat->virt + EMMC_INTERRUPT, mask);
+    return RT_EOK;
+}
+
+rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask)
+{
+    int cnt = 500000;
+    while ((read32(pdat->virt + EMMC_STATUS) & mask) && !(read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) && cnt--)
+        DELAY_MICROS(1);
+    if (cnt <= 0)
+    {
+        return -RT_ETIMEOUT;
+    }
+    else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK)
+        return  -RT_ERROR;
+    return RT_EOK;
+}
+
+static rt_err_t raspi_transfer_command(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd)
+{
+
+    rt_uint32_t cmdidx;
+    rt_err_t ret = RT_EOK;
+    ret = sd_status(pdat, SR_CMD_INHIBIT);
+    if (ret)
+    {
+        rt_kprintf("ERROR: EMMC busy %d\n", ret);
+        return ret;
+    }
+
+    cmdidx = sdCommandTable[cmd->cmdidx];
+    if (cmdidx == 0xFFFFFFFF)
+        return -RT_EINVAL;
+    if (cmd->datarw == DATA_READ)
+        cmdidx |= SD_DATA_READ;
+    if (cmd->datarw == DATA_WRITE)
+        cmdidx |= SD_DATA_WRITE;
+    mmcsd_dbg("transfer cmd %x(%d) %x %x\n", cmdidx, cmd->cmdidx, cmd->cmdarg, read32(pdat->virt + EMMC_INTERRUPT));
+    write32(pdat->virt + EMMC_INTERRUPT,read32(pdat->virt + EMMC_INTERRUPT));
+    write32(pdat->virt + EMMC_ARG1, cmd->cmdarg);
+    write32(pdat->virt + EMMC_CMDTM, cmdidx);
+    if (cmd->cmdidx == SD_APP_OP_COND)
+        DELAY_MICROS(1000);
+    else if ((cmd->cmdidx == SD_SEND_IF_COND) || (cmd->cmdidx == APP_CMD))
+        DELAY_MICROS(100);
+    ret = sd_int(pdat, INT_CMD_DONE);
+    if (ret)
+    {
+        return ret;
+    }
+    if (cmd->resptype & RESP_MASK)
+    {
+
+        if (cmd->resptype & RESP_R2)
+        {
+            rt_uint32_t resp[4];
+            resp[0] = read32(pdat->virt + EMMC_RESP0);
+            resp[1] = read32(pdat->virt + EMMC_RESP1);
+            resp[2] = read32(pdat->virt + EMMC_RESP2);
+            resp[3] = read32(pdat->virt + EMMC_RESP3);
+            if (cmd->resptype == RESP_R2)
+            {
+                cmd->response[0] = resp[3]<<8 |((resp[2]>>24)&0xff);
+                cmd->response[1] = resp[2]<<8 |((resp[1]>>24)&0xff);
+                cmd->response[2] = resp[1]<<8 |((resp[0]>>24)&0xff);
+                cmd->response[3] = resp[0]<<8 ;
+            }
+            else
+            {
+                cmd->response[0] = resp[0];
+                cmd->response[1] = resp[1];
+                cmd->response[2] = resp[2];
+                cmd->response[3] = resp[3];
+            }
+        }
+        else
+            cmd->response[0] = read32(pdat->virt + EMMC_RESP0);
+    }
+    mmcsd_dbg("response: %x: %x %x %x %x (%x, %x)\n", cmd->resptype, cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3], read32(pdat->virt + EMMC_STATUS),read32(pdat->virt + EMMC_INTERRUPT));
+    return ret;
+}
+
+static rt_err_t read_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
+{
+    int c = 0;
+    rt_err_t ret;
+    int d;
+    while (c < blkcount)
+    {
+        if ((ret = sd_int(pdat, INT_READ_RDY)))
+        {
+            rt_kprintf("timeout happens when reading block %d\n",c);
+            return ret;
+        }
+        for (d=0; d < blksize / 4; d++)
+            if (read32(pdat->virt + EMMC_STATUS) & SR_READ_AVAILABLE)
+                buf[d] = read32(pdat->virt + EMMC_DATA);
+        c++;
+        buf += blksize / 4;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t write_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
+{
+    int c = 0;
+    rt_err_t ret;
+    int d;
+    while (c < blkcount)
+    {
+        if ((ret = sd_int(pdat, INT_WRITE_RDY)))
+        {
+            return ret;
+        }
+        for (d=0; d < blksize / 4; d++)
+            write32(pdat->virt + EMMC_DATA, buf[d]);
+        c++;
+        buf += blksize / 4;
+    }
+    if ((ret = sd_int(pdat, INT_DATA_DONE)))
+    {
+        return ret;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t raspi_transfer_data(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
+{
+    rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz);
+    rt_err_t ret = sd_status(pdat, SR_DAT_INHIBIT);
+    if (ret)
+    {
+        rt_kprintf("ERROR: EMMC busy\n");
+        return ret;
+    }
+    if (dat->blkcnt > 1)
+    {
+        struct sdhci_cmd_t newcmd;
+        newcmd.cmdidx = SET_BLOCK_COUNT;
+        newcmd.cmdarg = dat->blkcnt;
+        newcmd.resptype = RESP_R1;
+        ret = raspi_transfer_command(pdat, &newcmd);
+        if (ret) return ret;
+    }
+    write32(pdat->virt + EMMC_BLKSIZECNT, dlen | 1 << 16);
+
+    if (dat->flag & DATA_DIR_READ)
+    {
+        cmd->datarw = DATA_READ;
+        ret = raspi_transfer_command(pdat, cmd);
+        if (ret) return ret;
+        mmcsd_dbg("read_block %d, %d\n", dat->blkcnt, dat->blksz );
+        ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
+    }
+    else if (dat->flag & DATA_DIR_WRITE)
+    {
+        cmd->datarw = DATA_WRITE;
+        ret = raspi_transfer_command(pdat, cmd);
+        if (ret) return ret;
+        mmcsd_dbg("write_block %d, %d", dat->blkcnt, dat->blksz );
+        ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
+    }
+    return ret;
+}
+
+static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
+{
+    struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
+
+    if (!dat)
+        return raspi_transfer_command(pdat, cmd);
+
+    return raspi_transfer_data(pdat, cmd, dat);
+}
+
+static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data;
+    struct sdhci_cmd_t cmd;
+    struct sdhci_cmd_t stop;
+    struct sdhci_data_t dat;
+
+    rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t));
+    rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t));
+    rt_memset(&dat, 0, sizeof(struct sdhci_data_t));
+
+    cmd.cmdidx = req->cmd->cmd_code;
+    cmd.cmdarg = req->cmd->arg;
+    cmd.resptype =resp_type(req->cmd);
+    if (req->data)
+    {
+        dat.buf = (rt_uint8_t *)req->data->buf;
+        dat.flag = req->data->flags;
+        dat.blksz = req->data->blksize;
+        dat.blkcnt = req->data->blks;
+
+        req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat);
+    }
+    else
+    {
+        req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL);
+    }
+
+    req->cmd->resp[3] = cmd.response[3];
+    req->cmd->resp[2] = cmd.response[2];
+    req->cmd->resp[1] = cmd.response[1];
+    req->cmd->resp[0] = cmd.response[0];
+
+    if (req->stop)
+    {
+        stop.cmdidx = req->stop->cmd_code;
+        stop.cmdarg = req->stop->arg;
+        cmd.resptype =resp_type(req->stop);
+        req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL);
+    }
+
+    mmcsd_req_complete(host);
+}
+
+rt_int32_t mmc_card_status(struct rt_mmcsd_host *host)
+{
+    return 0;
+}
+
+void mmc_enable_irq(struct rt_mmcsd_host *host, rt_int32_t en)
+{
+
+}
+
+static rt_err_t sdhci_detect(struct sdhci_t * sdhci)
+{
+    return RT_EOK;
+}
+
+static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width)
+{
+    rt_uint32_t temp = 0;
+    struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
+    if (width == MMCSD_BUS_WIDTH_4)
+    {
+        temp = read32((pdat->virt + EMMC_CONTROL0));
+        temp |= C0_HCTL_HS_EN;
+        temp |= C0_HCTL_DWITDH;   // always use 4 data lines:
+        write32((pdat->virt + EMMC_CONTROL0), temp);
+    }
+    return RT_EOK;
+}
+
+static rt_uint32_t sdhci_getdivider(rt_uint32_t sdHostVer, rt_uint32_t freq)
+{
+    rt_uint32_t divisor;
+    rt_uint32_t closest = 41666666 / freq;
+    rt_uint32_t shiftcount = __rt_fls(closest - 1);
+
+
+    if (shiftcount > 0) shiftcount--;
+    if (shiftcount > 7) shiftcount = 7;
+    if (sdHostVer > HOST_SPEC_V2)
+        divisor = closest;
+    else
+        divisor = (1 << shiftcount);
+
+    if (divisor <= 2)
+    {
+        divisor = 2;
+        shiftcount = 0;
+    }
+
+    rt_uint32_t hi = 0;
+    if (sdHostVer > HOST_SPEC_V2)
+        hi = (divisor & 0x300) >> 2;
+    rt_uint32_t lo = (divisor & 0x0ff);
+    rt_uint32_t cdiv = (lo << 8) + hi;
+    return cdiv;
+}
+
+static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
+{
+    rt_uint32_t temp = 0;
+    rt_uint32_t sdHostVer = 0;
+    int count = 100000;
+    struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)(sdhci->priv);
+
+    while ((read32(pdat->virt + EMMC_STATUS) & (SR_CMD_INHIBIT | SR_DAT_INHIBIT)) && (--count))
+        DELAY_MICROS(1);
+    if (count <= 0)
+    {
+        rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n",read32(pdat->virt + EMMC_STATUS));
+        return RT_ERROR;
+    }
+
+    // Switch clock off.
+    temp = read32((pdat->virt + EMMC_CONTROL1));
+    temp &= ~C1_CLK_EN;
+    write32((pdat->virt + EMMC_CONTROL1),temp);
+    DELAY_MICROS(10);
+    // Request the new clock setting and enable the clock
+    temp = read32(pdat->virt + EMMC_SLOTISR_VER);
+    sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT;
+    int cdiv = sdhci_getdivider(sdHostVer, clock);
+    temp = read32((pdat->virt + EMMC_CONTROL1));
+    temp = (temp & 0xffff003f) | cdiv;
+    write32((pdat->virt + EMMC_CONTROL1),temp);
+    DELAY_MICROS(10);
+
+    // Enable the clock.
+    temp = read32(pdat->virt + EMMC_CONTROL1);
+    temp |= C1_CLK_EN;
+    write32((pdat->virt + EMMC_CONTROL1),temp);
+    DELAY_MICROS(10);
+    // Wait for clock to be stable.
+    count = 10000;
+    while (!(read32(pdat->virt + EMMC_CONTROL1) & C1_CLK_STABLE) && count--)
+        DELAY_MICROS(10);
+    if (count <= 0)
+    {
+        rt_kprintf("EMMC: ERROR: failed to get stable clock %d.\n", clock);
+        return RT_ERROR;
+    }
+    mmcsd_dbg("set stable clock %d.\n", clock);
+    return RT_EOK;
+}
+
+static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+    struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data;
+    sdhci_setclock(sdhci, io_cfg->clock);
+    sdhci_setwidth(sdhci, io_cfg->bus_width);
+}
+
+static const struct rt_mmcsd_host_ops ops =
+{
+    mmc_request_send,
+    mmc_set_iocfg,
+    RT_NULL,
+    RT_NULL,
+};
+
+static void sdmmc_gpio_init()
+{
+//    int pin;
+//    bcm283x_gpio_fsel(47,BCM283X_GPIO_FSEL_INPT);
+//    bcm283x_gpio_set_pud(47, BCM283X_GPIO_PUD_UP);
+//    bcm283x_peri_set_bits(BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN1, 1<<15, 1<<15);
+//    for (pin = 53; pin >= 48; pin--)
+//    {
+//        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_ALT3);
+//        bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
+//    }
+}
+
+static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat){
+    rt_uint32_t temp;
+    int cnt;
+    write32((pdat->virt + EMMC_CONTROL0),0);
+    temp = read32((pdat->virt + EMMC_CONTROL1));
+    temp |= C1_SRST_HC;
+    write32((pdat->virt + EMMC_CONTROL1),temp);
+    cnt = 10000;
+    do
+    {
+        DELAY_MICROS(10);
+    }
+    while ((read32((pdat->virt + EMMC_CONTROL1)) & C1_SRST_HC) && cnt--);
+
+    if (cnt <= 0)
+    {
+        rt_kprintf("ERROR: failed to reset EMMC\n");
+        return RT_ERROR;
+    }
+    temp = read32((pdat->virt + EMMC_CONTROL1));
+    temp |= C1_CLK_INTLEN | C1_TOUNIT_MAX;
+    write32((pdat->virt + EMMC_CONTROL1),temp);
+    DELAY_MICROS(10);
+    return RT_EOK;
+}
+
+#ifdef RT_MMCSD_DBG
+void dump_registers(struct sdhci_pdata_t * pdat){
+    rt_kprintf("EMMC registers:");
+    int i = EMMC_ARG2;
+    for (; i <= EMMC_CONTROL2; i += 4)
+        rt_kprintf("\t%x:%x\n", i, read32(pdat->virt + i));
+    rt_kprintf("\t%x:%x\n", 0x50, read32(pdat->virt + 0x50));
+    rt_kprintf("\t%x:%x\n", 0x70, read32(pdat->virt + 0x70));
+    rt_kprintf("\t%x:%x\n", 0x74, read32(pdat->virt + 0x74));
+    rt_kprintf("\t%x:%x\n", 0x80, read32(pdat->virt + 0x80));
+    rt_kprintf("\t%x:%x\n", 0x84, read32(pdat->virt + 0x84));
+    rt_kprintf("\t%x:%x\n", 0x88, read32(pdat->virt + 0x88));
+    rt_kprintf("\t%x:%x\n", 0x8c, read32(pdat->virt + 0x8c));
+    rt_kprintf("\t%x:%x\n", 0x90, read32(pdat->virt + 0x90));
+    rt_kprintf("\t%x:%x\n", 0xf0, read32(pdat->virt + 0xf0));
+    rt_kprintf("\t%x:%x\n", 0xfc, read32(pdat->virt + 0xfc));
+}
+#endif
+
+int raspi_sdmmc_init(void)
+{
+    rt_uint32_t virt;
+    struct rt_mmcsd_host * host = RT_NULL;
+    struct sdhci_pdata_t * pdat = RT_NULL;
+    struct sdhci_t * sdhci = RT_NULL;
+
+#ifdef BSP_USING_SDIO0
+    host = mmcsd_alloc_host();
+    if (!host)
+    {
+        rt_kprintf("alloc host failed");
+        goto err;
+    }
+
+    sdhci = rt_malloc(sizeof(struct sdhci_t));
+    if (!sdhci)
+    {
+        rt_kprintf("alloc sdhci failed");
+        goto err;
+    }
+    rt_memset(sdhci, 0, sizeof(struct sdhci_t));
+
+    sdmmc_gpio_init();
+
+    virt = MMC0_BASE_ADDR;
+
+    pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t));
+    RT_ASSERT(pdat != RT_NULL);
+
+    pdat->virt = (rt_uint32_t)virt;
+    reset_emmc(pdat);
+
+    sdhci->name = "sd0";
+    sdhci->voltages = VDD_33_34;
+    sdhci->width = MMCSD_BUSWIDTH_4;
+    sdhci->clock = 200 * 1000 * 1000;
+    sdhci->removeable = RT_TRUE;
+
+    sdhci->detect = sdhci_detect;
+    sdhci->setwidth = sdhci_setwidth;
+    sdhci->setclock = sdhci_setclock;
+    sdhci->transfer = sdhci_transfer;
+    sdhci->priv = pdat;
+
+    host->ops = &ops;
+    host->freq_min = 400000;
+    host->freq_max = 50000000;
+    host->valid_ocr = VDD_32_33 | VDD_33_34;
+    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
+    host->max_seg_size = 2048;
+    host->max_dma_segs = 10;
+    host->max_blk_size = 512;
+    host->max_blk_count = 4096;
+
+    host->private_data = sdhci;
+
+    write32((pdat->virt + EMMC_IRPT_EN),0xffffffff);
+    write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff);
+#ifdef RT_MMCSD_DBG
+    dump_registers(pdat);
+#endif
+    mmcsd_change(host);
+#endif
+    return RT_EOK;
+
+err:
+    if (host)  rt_free(host);
+    if (sdhci) rt_free(sdhci);
+
+    return -RT_EIO;
+}
+
+INIT_DEVICE_EXPORT(raspi_sdmmc_init);
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h
new file mode 100644
index 0000000000..5c052de90a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h
@@ -0,0 +1,253 @@
+/*
+ * File      : drv_sdio.h
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drivers/mmcsd_core.h>
+
+#include "board.h"
+
+#define MMC0_BASE_ADDR     0x3F300000
+
+/* Struct for Intrrrupt Information */
+#define SDXC_CmdDone       BIT(0)
+#define SDXC_DataDone      BIT(1)
+#define SDXC_BlockGap      BIT(2)
+#define SDXC_WriteRdy      BIT(4)
+#define SDXC_ReadRdy       BIT(5)
+#define SDXC_Card          BIT(8)
+#define SDXC_Retune        BIT(12)
+#define SDXC_BootAck       BIT(13)
+#define SDXC_EndBoot       BIT(14)
+#define SDXC_Err              BIT(15)
+#define SDXC_CTOErr        BIT(16)
+#define SDXC_CCRCErr       BIT(17)
+#define SDXC_CENDErr       BIT(18)
+#define SDXC_CBADErr       BIT(19)
+#define SDXC_DTOErr        BIT(20)
+#define SDXC_DCRCErr       BIT(21)
+#define SDXC_DENDErr       BIT(22)
+#define SDXC_ACMDErr       BIT(24)
+
+#define SDXC_BLKCNT_EN          BIT(1)
+#define SDXC_AUTO_CMD12_EN      BIT(2)
+#define SDXC_AUTO_CMD23_EN      BIT(3)
+#define SDXC_DAT_DIR              BIT(4)   //from card to host
+#define SDXC_MULTI_BLOCK        BIT(5)
+#define SDXC_CMD_RSPNS_136         BIT(16)
+#define SDXC_CMD_RSPNS_48         BIT(17)
+#define SDXC_CMD_RSPNS_48busy   BIT(16)|BIT(17)
+#define SDXC_CHECK_CRC_CMD      BIT(19)
+#define SDXC_CMD_IXCHK_EN       BIT(20)
+#define SDXC_CMD_ISDATA         BIT(21)
+#define SDXC_CMD_SUSPEND        BIT(22)
+#define SDXC_CMD_RESUME         BIT(23)
+#define SDXC_CMD_ABORT          BIT(23)|BIT(22)
+
+#define SDXC_CMD_INHIBIT    BIT(0)
+#define SDXC_DAT_INHIBIT    BIT(1)
+#define SDXC_DAT_ACTIVE     BIT(2)
+#define SDXC_WRITE_TRANSFER     BIT(8)
+#define SDXC_READ_TRANSFER     BIT(9)
+
+struct sdhci_cmd_t
+{
+    rt_uint32_t cmdidx;
+    rt_uint32_t cmdarg;
+    rt_uint32_t resptype;
+    rt_uint32_t datarw;
+#define DATA_READ 1
+#define DATA_WRITE 2
+    rt_uint32_t response[4];
+};
+
+struct sdhci_data_t
+{
+    rt_uint8_t * buf;
+    rt_uint32_t flag;
+    rt_uint32_t blksz;
+    rt_uint32_t blkcnt;
+};
+
+struct sdhci_t
+{
+    char * name;
+    rt_uint32_t voltages;
+    rt_uint32_t width;
+    rt_uint32_t clock;
+    rt_err_t removeable;
+    void * sdcard;
+
+    rt_err_t (*detect)(struct sdhci_t * sdhci);
+    rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width);
+    rt_err_t (*setclock)(struct sdhci_t * sdhci, rt_uint32_t clock);
+    rt_err_t (*transfer)(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat);
+    void * priv;
+};
+
+struct sdhci_pdata_t
+{
+    rt_uint32_t virt;
+};
+
+// EMMC command flags
+#define CMD_TYPE_NORMAL  0x00000000
+#define CMD_TYPE_SUSPEND 0x00400000
+#define CMD_TYPE_RESUME  0x00800000
+#define CMD_TYPE_ABORT   0x00c00000
+#define CMD_IS_DATA      0x00200000
+#define CMD_IXCHK_EN     0x00100000
+#define CMD_CRCCHK_EN    0x00080000
+#define CMD_RSPNS_NO     0x00000000
+#define CMD_RSPNS_136    0x00010000
+#define CMD_RSPNS_48     0x00020000
+#define CMD_RSPNS_48B    0x00030000
+#define TM_MULTI_BLOCK   0x00000020
+#define TM_DAT_DIR_HC    0x00000000
+#define TM_DAT_DIR_CH    0x00000010
+#define TM_AUTO_CMD23    0x00000008
+#define TM_AUTO_CMD12    0x00000004
+#define TM_BLKCNT_EN     0x00000002
+#define TM_MULTI_DATA    (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN)
+
+#define RCA_NO     1
+#define RCA_YES    2
+
+// INTERRUPT register settings
+#define INT_AUTO_ERROR   0x01000000
+#define INT_DATA_END_ERR 0x00400000
+#define INT_DATA_CRC_ERR 0x00200000
+#define INT_DATA_TIMEOUT 0x00100000
+#define INT_INDEX_ERROR  0x00080000
+#define INT_END_ERROR    0x00040000
+#define INT_CRC_ERROR    0x00020000
+#define INT_CMD_TIMEOUT  0x00010000
+#define INT_ERR          0x00008000
+#define INT_ENDBOOT      0x00004000
+#define INT_BOOTACK      0x00002000
+#define INT_RETUNE       0x00001000
+#define INT_CARD         0x00000100
+#define INT_READ_RDY     0x00000020
+#define INT_WRITE_RDY    0x00000010
+#define INT_BLOCK_GAP    0x00000004
+#define INT_DATA_DONE    0x00000002
+#define INT_CMD_DONE     0x00000001
+#define INT_ERROR_MASK   (INT_CRC_ERROR|INT_END_ERROR|INT_INDEX_ERROR| \
+                          INT_DATA_TIMEOUT|INT_DATA_CRC_ERR|INT_DATA_END_ERR| \
+                          INT_ERR|INT_AUTO_ERROR)
+#define INT_ALL_MASK     (INT_CMD_DONE|INT_DATA_DONE|INT_READ_RDY|INT_WRITE_RDY|INT_ERROR_MASK)
+
+#define EMMC_ARG2         (0x00)
+#define EMMC_BLKSIZECNT   (0x04)
+#define EMMC_ARG1         (0x08)
+#define EMMC_CMDTM        (0x0c)
+#define EMMC_RESP0        (0x10)
+#define EMMC_RESP1        (0x14)
+#define EMMC_RESP2        (0x18)
+#define EMMC_RESP3        (0x1c)
+#define EMMC_DATA         (0x20)
+#define EMMC_STATUS       (0x24)
+#define EMMC_CONTROL0     (0x28)
+#define EMMC_CONTROL1     (0x2c)
+#define EMMC_INTERRUPT    (0x30)
+#define EMMC_IRPT_MASK    (0x34)
+#define EMMC_IRPT_EN      (0x38)
+#define EMMC_CONTROL2     (0x3c)
+#define EMMC_BOOT_TIMEOUT (0x70)
+#define EMMC_EXRDFIFO_EN  (0x84)
+#define EMMC_SPI_INT_SPT  (0xf0)
+#define EMMC_SLOTISR_VER  (0xfc)
+
+// CONTROL register settings
+#define C0_SPI_MODE_EN   0x00100000
+#define C0_HCTL_HS_EN    0x00000004
+#define C0_HCTL_DWITDH   0x00000002
+
+#define C1_SRST_DATA     0x04000000
+#define C1_SRST_CMD      0x02000000
+#define C1_SRST_HC       0x01000000
+#define C1_TOUNIT_DIS    0x000f0000
+#define C1_TOUNIT_MAX    0x000e0000
+#define C1_CLK_GENSEL    0x00000020
+#define C1_CLK_EN        0x00000004
+#define C1_CLK_STABLE    0x00000002
+#define C1_CLK_INTLEN    0x00000001
+
+#define FREQ_SETUP           400000  // 400 Khz
+#define FREQ_NORMAL        25000000  // 25 Mhz
+
+// SLOTISR_VER values
+#define HOST_SPEC_NUM              0x00ff0000
+#define HOST_SPEC_NUM_SHIFT        16
+#define HOST_SPEC_V3               2
+#define HOST_SPEC_V2               1
+#define HOST_SPEC_V1               0
+
+// STATUS register settings
+#define SR_DAT_LEVEL1        0x1e000000
+#define SR_CMD_LEVEL         0x01000000
+#define SR_DAT_LEVEL0        0x00f00000
+#define SR_DAT3              0x00800000
+#define SR_DAT2              0x00400000
+#define SR_DAT1              0x00200000
+#define SR_DAT0              0x00100000
+#define SR_WRITE_PROT        0x00080000  // From SDHC spec v2, BCM says reserved
+#define SR_READ_AVAILABLE    0x00000800  // ???? undocumented
+#define SR_WRITE_AVAILABLE   0x00000400  // ???? undocumented
+#define SR_READ_TRANSFER     0x00000200
+#define SR_WRITE_TRANSFER    0x00000100
+#define SR_DAT_ACTIVE        0x00000004
+#define SR_DAT_INHIBIT       0x00000002
+#define SR_CMD_INHIBIT       0x00000001
+
+#define CONFIG_MMC_USE_DMA
+#define DMA_ALIGN       (32U)
+
+#define SD_CMD_INDEX(a)        ((a) << 24)
+#define SD_CMD_RESERVED(a)  0xffffffff
+#define SD_CMD_INDEX(a)        ((a) << 24)
+#define SD_CMD_TYPE_NORMAL    0x0
+#define SD_CMD_TYPE_SUSPEND    (1 << 22)
+#define SD_CMD_TYPE_RESUME    (2 << 22)
+#define SD_CMD_TYPE_ABORT    (3 << 22)
+#define SD_CMD_TYPE_MASK    (3 << 22)
+#define SD_CMD_ISDATA        (1 << 21)
+#define SD_CMD_IXCHK_EN        (1 << 20)
+#define SD_CMD_CRCCHK_EN    (1 << 19)
+#define SD_CMD_RSPNS_TYPE_NONE    0            // For no response
+#define SD_CMD_RSPNS_TYPE_136    (1 << 16)        // For response R2 (with CRC), R3,4 (no CRC)
+#define SD_CMD_RSPNS_TYPE_48    (2 << 16)        // For responses R1, R5, R6, R7 (with CRC)
+#define SD_CMD_RSPNS_TYPE_48B    (3 << 16)        // For responses R1b, R5b (with CRC)
+#define SD_CMD_RSPNS_TYPE_MASK  (3 << 16)
+#define SD_CMD_MULTI_BLOCK    (1 << 5)
+#define SD_CMD_DAT_DIR_HC    0
+#define SD_CMD_DAT_DIR_CH    (1 << 4)
+#define SD_CMD_AUTO_CMD_EN_NONE    0
+#define SD_CMD_AUTO_CMD_EN_CMD12    (1 << 2)
+#define SD_CMD_AUTO_CMD_EN_CMD23    (2 << 2)
+#define SD_CMD_BLKCNT_EN        (1 << 1)
+#define SD_CMD_DMA          1
+#define SD_RESP_NONE        SD_CMD_RSPNS_TYPE_NONE
+#define SD_RESP_R1          (SD_CMD_RSPNS_TYPE_48)           // | SD_CMD_CRCCHK_EN)
+#define SD_RESP_R1b         (SD_CMD_RSPNS_TYPE_48B)         // | SD_CMD_CRCCHK_EN)
+#define SD_RESP_R2          (SD_CMD_RSPNS_TYPE_136)           //| SD_CMD_CRCCHK_EN)
+#define SD_RESP_R3          SD_CMD_RSPNS_TYPE_48
+#define SD_RESP_R4          SD_CMD_RSPNS_TYPE_136
+#define SD_RESP_R5          (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN)
+#define SD_RESP_R5b         (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN)
+#define SD_RESP_R6          (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN)
+#define SD_RESP_R7          (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN)
+#define SD_DATA_READ        (SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH)
+#define SD_DATA_WRITE       (SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC)
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c
new file mode 100644
index 0000000000..32de9970e7
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+#include "drv_spi.h"
+
+#ifdef RT_USING_SPI
+
+#define RPI_CORE_CLK_HZ        250000000
+#define BSP_SPI_MAX_HZ (30* 1000 *1000)
+#define SPITIMEOUT 0x0FFF
+
+void spi_gpio_write(rt_uint8_t pin, rt_uint8_t val)
+{
+    if (val)
+        BCM283X_GPIO_GPSET(pin / 32) = 1 << (pin % 32);
+    else
+        BCM283X_GPIO_GPCLR(pin / 32) = 0 << (pin % 32);
+}
+
+struct raspi_spi_hw_config
+{
+    rt_uint8_t spi_num;
+    raspi_gpio_pin sclk_pin;
+    raspi_pin_select sclk_mode;
+    raspi_gpio_pin mosi_pin;
+    raspi_pin_select mosi_mode;
+    raspi_gpio_pin miso_pin;
+    raspi_pin_select miso_mode;
+#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0)
+    raspi_gpio_pin ce0_pin;
+    raspi_pin_select ce0_mode;
+#endif
+
+#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1)
+    raspi_gpio_pin ce1_pin;
+    raspi_pin_select ce1_mode;
+#endif
+
+#if defined (BSP_USING_SPI1_DEVICE2)
+    raspi_gpio_pin ce2_pin;
+    raspi_pin_select ce2_mode;
+#endif
+};
+
+struct raspi_spi_device
+{
+    char *device_name;
+    struct rt_spi_bus *spi_bus;
+    struct rt_spi_device *spi_device;
+    raspi_gpio_pin cs_pin;
+};
+
+static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
+{
+    RT_ASSERT(cfg != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
+    rt_uint16_t divider;
+
+    // spi clear fifo
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CLEAR;
+
+    if (cfg->mode & RT_SPI_CPOL)
+        BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CPOL;
+
+    if (cfg->mode & RT_SPI_CPHA)
+        BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CPHA;
+
+    if (cfg->mode & RT_SPI_CS_HIGH)
+        BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CSPOL;
+
+    //set clk
+    if (cfg->max_hz > BSP_SPI_MAX_HZ)
+        cfg->max_hz = BSP_SPI_MAX_HZ;
+
+    divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz);
+    divider &= 0xFFFE;
+
+    BCM283X_SPI0_CLK(BCM283X_SPI0_BASE) = divider;
+
+    return RT_EOK;
+}
+
+rt_uint8_t correct_order(rt_uint8_t b, rt_uint8_t flag)
+{
+    if (flag)
+        return raspi_byte_reverse_table[b];
+    else
+        return b;
+}
+
+static rt_err_t spi_transfernb(rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len, rt_uint8_t flag)
+{
+    rt_uint32_t TXCnt=0;
+    rt_uint32_t RXCnt=0;
+
+    /* Clear TX and RX fifos */
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (BCM283X_SPI0_CS_CLEAR & BCM283X_SPI0_CS_CLEAR);
+
+    /* Set TA = 1 */
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (BCM283X_SPI0_CS_TA & BCM283X_SPI0_CS_TA);
+
+
+    /* Use the FIFO's to reduce the interbyte times */
+    while ((TXCnt < len) || (RXCnt < len))
+    {
+        /* TX fifo not full, so add some more bytes */
+        while (((BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_TXD)) && (TXCnt < len))
+        {
+            BCM283X_SPI0_FIFO(BCM283X_SPI0_BASE) = correct_order(tbuf[TXCnt],flag);
+            TXCnt++;
+        }
+        /* Rx fifo not empty, so get the next received bytes */
+        while (((BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_RXD)) && (RXCnt < len))
+        {
+            rbuf[RXCnt] = correct_order(BCM283X_SPI0_FIFO(BCM283X_SPI0_BASE),flag);
+            RXCnt++;
+        }
+    }
+    /* Wait for DONE to be set */
+    while (!(BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_DONE));
+
+    /* Set TA = 0, and also set the barrier */
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (0 & BCM283X_SPI0_CS_TA);
+    return RT_EOK;
+}
+
+static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->parent.user_data != RT_NULL);
+    RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
+
+    rt_err_t res;
+    rt_uint8_t flag;
+    struct rt_spi_configuration config = device->config;
+    raspi_gpio_pin cs_pin = (raspi_gpio_pin)device->parent.user_data;
+
+    if (config.mode & RT_SPI_MSB)
+        flag = 0;
+    else
+        flag = 1;
+
+    if (message->cs_take)
+        (config.mode & RT_SPI_CS_HIGH)?
+                spi_gpio_write(cs_pin, 1):
+                spi_gpio_write(cs_pin, 0);
+
+    /* deal data */
+    res = spi_transfernb((rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
+            (rt_int32_t)message->length, flag);
+
+    if (message->cs_release)
+        (config.mode & RT_SPI_CS_HIGH)?
+                spi_gpio_write(cs_pin, 0):
+                spi_gpio_write(cs_pin, 1);
+
+    if (res != RT_EOK)
+           return RT_ERROR;
+
+    return message->length;
+}
+
+rt_err_t raspi_spi_bus_attach_device(const char *bus_name, struct raspi_spi_device *device)
+{
+    rt_err_t ret;
+    RT_ASSERT(device != RT_NULL);
+    ret = rt_spi_bus_attach_device(device->spi_device, device->device_name, bus_name, (void *)(device->cs_pin));
+    return ret;
+}
+
+rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg)
+{
+    GPIO_FSEL(hwcfg->sclk_pin, hwcfg->sclk_mode);
+    GPIO_FSEL(hwcfg->miso_pin, hwcfg->miso_mode);
+    GPIO_FSEL(hwcfg->mosi_pin, hwcfg->mosi_mode);
+
+#if defined (BSP_USING_SPI0_DEVICE0)
+    GPIO_FSEL(hwcfg->ce0_pin, hwcfg->ce0_mode);
+#endif
+
+#if defined (BSP_USING_SPI0_DEVICE1)
+    GPIO_FSEL(hwcfg->ce1_pin, hwcfg->ce1_mode);
+#endif
+
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) = 0;
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) = BCM283X_SPI0_CS_CLEAR;
+
+    //enable chip select
+#if defined (BSP_USING_SPI0_DEVICE0)
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= 0;
+#endif
+
+#if defined (BSP_USING_SPI0_DEVICE1)
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= 0x2;
+#endif
+
+#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1)
+    BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CS;
+#endif
+    return RT_EOK;
+}
+
+static struct rt_spi_ops raspi_spi_ops =
+{
+    .configure = raspi_spi_configure,
+    .xfer = raspi_spi_xfer
+};
+
+#if defined (BSP_USING_SPI0_BUS)
+#define SPI0_BUS_NAME  "spi0"
+#define SPI0_DEVICE0_NAME  "spi0.0"
+#define SPI0_DEVICE1_NAME  "spi0.1"
+
+struct rt_spi_bus spi0_bus;
+
+#if defined (BSP_USING_SPI0_DEVICE0)
+struct rt_spi_device spi0_device0;
+#endif
+
+#if defined (BSP_USING_SPI0_DEVICE1)
+static struct rt_spi_device spi0_device1;
+#endif
+
+struct raspi_spi_hw_config raspi_spi0_hw =
+{
+    .spi_num = 0,
+    .sclk_pin = RPI_GPIO_P1_23,
+    .sclk_mode = BCM283X_GPIO_FSEL_ALT0,
+    .mosi_pin = RPI_GPIO_P1_19,
+    .mosi_mode = BCM283X_GPIO_FSEL_ALT0,
+    .miso_pin = RPI_GPIO_P1_21,
+    .miso_mode = BCM283X_GPIO_FSEL_ALT0,
+
+#if defined (BSP_USING_SPI0_DEVICE0)
+    .ce0_pin = RPI_GPIO_P1_24,
+    .ce0_mode = BCM283X_GPIO_FSEL_ALT0,
+#endif
+
+#if defined (BSP_USING_SPI0_DEVICE1)
+    .ce1_pin = RPI_GPIO_P1_26,
+    .ce1_mode = BCM283X_GPIO_FSEL_ALT0,
+#endif
+};
+#endif
+
+int rt_hw_spi_init(void)
+{
+
+#if defined (BSP_USING_SPI0_BUS)
+    raspi_spi_hw_init(&raspi_spi0_hw);
+    rt_spi_bus_register(&spi0_bus, SPI0_BUS_NAME, &raspi_spi_ops);
+
+#if defined (BSP_USING_SPI0_DEVICE0)
+    struct raspi_spi_device raspi_spi0_device0 =
+    {
+        .device_name = SPI0_DEVICE0_NAME,
+        .spi_bus = &spi0_bus,
+        .spi_device = &spi0_device0,
+        .cs_pin = raspi_spi0_hw.ce0_pin,
+    };
+    raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device0);
+#endif
+
+#if defined (BSP_USING_SPI0_DEVICE1)
+    struct raspi_spi_device raspi_spi0_device1 =
+    {
+        .device_name = SPI0_DEVICE1_NAME,
+        .spi_bus = &spi0_bus,
+        .spi_device = &spi0_device1,
+        .cs_pin = raspi_spi0_hw.ce1_pin,
+    };
+    raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device1);
+#endif
+#endif
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_spi_init);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h
new file mode 100644
index 0000000000..9e4623b327
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+//#include <drivers/spi.h>
+#include "board.h"
+
+#define SPI0_BASE_ADDR     (PER_BASE + BCM283X_SPI0_BASE)
+
+static rt_uint8_t raspi_byte_reverse_table[] =
+{
+    0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+    0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+    0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+    0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+    0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+    0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+    0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+    0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+    0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+    0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+    0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+    0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+    0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+    0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+    0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+    0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+    0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+    0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+    0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+    0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+    0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+    0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+    0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+    0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+    0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+    0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+    0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+    0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+    0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+    0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+    0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+    0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
+};
+
+#define    SPI_CORE_CLK    250000000U
+#define    SPI_CS        0x00
+#define    SPI_CS_LEN_LONG        (1 << 25)
+#define    SPI_CS_DMA_LEN        (1 << 24)
+#define    SPI_CS_CSPOL2        (1 << 23)
+#define    SPI_CS_CSPOL1        (1 << 22)
+#define    SPI_CS_CSPOL0        (1 << 21)
+#define    SPI_CS_RXF        (1 << 20)
+#define    SPI_CS_RXR        (1 << 19)
+#define    SPI_CS_TXD        (1 << 18)
+#define    SPI_CS_RXD        (1 << 17)
+#define    SPI_CS_DONE        (1 << 16)
+#define    SPI_CS_LEN        (1 << 13)
+#define    SPI_CS_REN        (1 << 12)
+#define    SPI_CS_ADCS        (1 << 11)
+#define    SPI_CS_INTR        (1 << 10)
+#define    SPI_CS_INTD        (1 << 9)
+#define    SPI_CS_DMAEN        (1 << 8)
+#define    SPI_CS_TA        (1 << 7)
+#define    SPI_CS_CSPOL        (1 << 6)
+#define    SPI_CS_CLEAR_RXFIFO    (1 << 5)
+#define    SPI_CS_CLEAR_TXFIFO    (1 << 4)
+#define    SPI_CS_CPOL        (1 << 3)
+#define    SPI_CS_CPHA        (1 << 2)
+#define    SPI_CS_MASK        0x3
+#define    SPI_FIFO    0x04
+#define    SPI_CLK        0x08
+#define    SPI_CLK_MASK        0xffff
+#define    SPI_DLEN    0x0c
+#define    SPI_DLEN_MASK        0xffff
+#define    SPI_LTOH    0x10
+#define    SPI_LTOH_MASK        0xf
+#define    SPI_DC        0x14
+#define    SPI_DC_RPANIC_SHIFT    24
+#define    SPI_DC_RPANIC_MASK    (0xff << SPI_DC_RPANIC_SHIFT)
+#define    SPI_DC_RDREQ_SHIFT    16
+#define    SPI_DC_RDREQ_MASK    (0xff << SPI_DC_RDREQ_SHIFT)
+#define    SPI_DC_TPANIC_SHIFT    8
+#define    SPI_DC_TPANIC_MASK    (0xff << SPI_DC_TPANIC_SHIFT)
+#define    SPI_DC_TDREQ_SHIFT    0
+#define    SPI_DC_TDREQ_MASK    0xff
+
+int rt_hw_spi_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c
new file mode 100644
index 0000000000..36a4fd2baf
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_timer.h"
+
+#ifdef BSP_USING_SYSTIMER
+
+static void raspi_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state)
+{
+    if (state == 0)
+        hwtimer->ops->stop(hwtimer);
+}
+
+static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
+{
+    rt_err_t result = RT_EOK;
+    rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
+    int timer_id = timer->timer_id;
+
+    if (mode == HWTIMER_MODE_PERIOD)
+        timer->cnt = cnt;
+    else
+        timer->cnt = 0; 
+
+    __sync_synchronize();
+    if (timer_id == 1)
+    {
+        rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
+        STIMER_C1 = STIMER_CLO + cnt;
+    } 
+    else if (timer_id == 3)
+    {
+        rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
+        STIMER_C3 = STIMER_CLO + cnt;
+    }
+    else    
+        result = -RT_ERROR;
+
+    __sync_synchronize();
+         
+    return result;
+}
+
+static void raspi_systimer_stop(rt_hwtimer_t *hwtimer)
+{
+    rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
+    int timer_id = timer->timer_id;
+    if (timer_id == 1)
+        rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1);
+    else if (timer_id == 3)
+        rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3);
+ 
+}
+
+static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+    /* The frequency value is an immutable value. */
+    if (cmd == HWTIMER_CTRL_FREQ_SET)
+    {
+        return RT_EOK;
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+}
+
+
+void rt_device_systimer_isr(int vector, void *param)
+{
+    
+    rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param;
+    rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
+    RT_ASSERT(timer != RT_NULL);
+
+    int timer_id = timer->timer_id;
+
+    __sync_synchronize();
+    if (timer_id == 1)
+    {
+        STIMER_CS = 0x2;
+        STIMER_C1 = STIMER_CLO + timer->cnt;               
+    }   
+    else if (timer_id == 3)
+    {
+        STIMER_CS = 0x8;
+        STIMER_C3 = STIMER_CLO + timer->cnt;                 
+    }
+    __sync_synchronize();
+
+    rt_device_hwtimer_isr(hwtimer);
+}
+    
+static struct rt_hwtimer_device _hwtimer1;
+static struct rt_hwtimer_device _hwtimer3;
+
+static rt_systimer_t _systimer1;
+static rt_systimer_t _systimer3;
+
+const static struct rt_hwtimer_ops systimer_ops =
+{
+    raspi_systimer_init,
+    raspi_systimer_start,
+    raspi_systimer_stop,
+    RT_NULL,
+    raspi_systimer_ctrl
+};
+
+static const struct rt_hwtimer_info _info =
+{
+    1000000,            /* the maxinum count frequency can be set */
+    1000000,            /* the maxinum count frequency can be set */
+    0xFFFFFFFF,         /* the maximum counter value */
+    HWTIMER_CNTMODE_UP  /* count mode (inc/dec) */
+};
+
+#endif
+
+int rt_hw_systimer_init(void)
+{
+
+#ifdef BSP_USING_SYSTIMER
+
+#ifdef RT_USING_SYSTIMER1
+    _systimer1.timer_id =1;
+    _hwtimer1.ops = &systimer_ops;
+    _hwtimer1.info = &_info;
+    rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1);
+    rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_hwtimer1, "systimer1");
+    rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
+#endif
+
+#ifdef RT_USING_SYSTIMER3
+    _systimer3.timer_id =3;
+    _hwtimer3.ops = &systimer_ops;
+    _hwtimer3.info = &_info;
+    rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3);
+    rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_hwtimer3, "systimer3");
+    rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
+#endif
+
+#endif
+
+    return 0;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_systimer_init);
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h
new file mode 100644
index 0000000000..c85d4c9d1f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+#ifndef __DRV_TIMER_H__
+#define __DRV_TIMER_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+
+typedef struct rt_systimer_device
+{
+    int  timer_id;
+    rt_uint32_t cnt;
+} rt_systimer_t;
+
+int rt_hw_systimer_init(void);
+
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c
new file mode 100644
index 0000000000..18501b7849
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/5/5       Bernard      The first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include <rtdevice.h>
+
+#define AUX_BASE            (0x3F000000 + 0x215000)
+
+struct hw_uart_device
+{
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if (uart->hw_base == AUX_BASE)
+    {
+        rt_uint32_t value;
+
+        /* GPIO function set */
+        value = BCM283X_GPIO_GPFSEL(1);
+        value &= ~(7 << 12); /* GPIO14 */
+        value |= 2 << 12 ; /* ALT5 */
+        value &= ~(7 << 15); /* GPIO15 */
+        value |= 2 << 15 ; /* ALT5 */
+        BCM283X_GPIO_GPFSEL(1) = value;
+
+        BCM283X_GPIO_GPPUD = 0;
+        BCM283X_GPIO_GPPUDCLK(0) = (1 << 14) | (1 << 15);
+        BCM283X_GPIO_GPPUDCLK(0) = 0;
+
+        AUX_ENABLES(uart->hw_base)      = 1;    /* Enable UART1 */
+        AUX_MU_IER_REG(uart->hw_base)   = 0;    /* Disable interrupt */
+        AUX_MU_CNTL_REG(uart->hw_base)  = 0;    /* Disable Transmitter and Receiver */
+        AUX_MU_LCR_REG(uart->hw_base)   = 3;    /* Works in 8-bit mode */
+        AUX_MU_MCR_REG(uart->hw_base)   = 0;    /* Disable RTS */
+        AUX_MU_IIR_REG(uart->hw_base)   = 0xC6; /* Enable FIFO, Clear FIFO */
+        AUX_MU_BAUD_REG(uart->hw_base)  = 270;  /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
+        AUX_MU_CNTL_REG(uart->hw_base)  = 3;    /* Enable Transmitter and Receiver */
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        AUX_MU_IER_REG(uart->hw_base) = 0x0;
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        AUX_MU_IER_REG(uart->hw_base) = 0x1;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
+    AUX_MU_IO_REG(uart->hw_base) = c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
+    {
+        ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+#ifdef RT_USING_UART0
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    RPI_UART0_BASE,
+    IRQ_PBA8_UART0,
+};
+static struct rt_serial_device _serial0;
+#endif
+
+#ifdef RT_USING_UART1
+/* UART1 device driver structure */
+static struct hw_uart_device _uart1_device =
+{
+    AUX_BASE,
+    IRQ_AUX,
+};
+static struct rt_serial_device _serial1;
+#endif
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART0
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
+#endif
+
+#ifdef RT_USING_UART1
+    uart = &_uart1_device;
+    _serial1.ops = &_uart_ops;
+    _serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+    /* enable Rx and Tx of UART */
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1");
+#endif
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h
new file mode 100644
index 0000000000..5211c19989
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+/*
+ *  Auxiliary
+ */
+#define AUX_IRQ(BASE)             HWREG32(BASE + 0x00)   /* Auxiliary Interrupt status 3 */
+#define AUX_ENABLES(BASE)         HWREG32(BASE + 0x04)   /* Auxiliary enables 3bit */
+#define AUX_MU_IO_REG(BASE)       HWREG32(BASE + 0x40)   /* Mini Uart I/O Data 8bit */
+#define AUX_MU_IER_REG(BASE)      HWREG32(BASE + 0x44)   /* Mini Uart Interrupt Enable 8bit */
+#define AUX_MU_IIR_REG(BASE)      HWREG32(BASE + 0x48)   /* Mini Uart Interrupt Identify 8bit */
+#define AUX_MU_LCR_REG(BASE)      HWREG32(BASE + 0x4C)   /* Mini Uart Line Control 8bit */
+#define AUX_MU_MCR_REG(BASE)      HWREG32(BASE + 0x50)   /* Mini Uart Modem Control 8bit */
+#define AUX_MU_LSR_REG(BASE)      HWREG32(BASE + 0x54)   /* Mini Uart Line Status 8bit */
+#define AUX_MU_MSR_REG(BASE)      HWREG32(BASE + 0x58)   /* Mini Uart Modem Status 8bit */
+#define AUX_MU_SCRATCH(BASE)      HWREG32(BASE + 0x5C)   /* Mini Uart Scratch 8bit */
+#define AUX_MU_CNTL_REG(BASE)     HWREG32(BASE + 0x60)   /* Mini Uart Extra Control 8bit */
+#define AUX_MU_STAT_REG(BASE)     HWREG32(BASE + 0x64)   /* Mini Uart Extra Status 32bit */
+#define AUX_MU_BAUD_REG(BASE)     HWREG32(BASE + 0x68)   /* Mini Uart Baudrate 16bit */
+#define AUX_SPI0_CNTL0_REG(BASE)  HWREG32(BASE + 0x80)   /* SPI 1 Control register 0 32bit */
+#define AUX_SPI0_CNTL1_REG(BASE)  HWREG32(BASE + 0x84)   /* SPI 1 Control register 1 8bit */
+#define AUX_SPI0_STAT_REG(BASE)   HWREG32(BASE + 0x88)   /* SPI 1 Status 32bit */
+#define AUX_SPI0_IO_REG(BASE)     HWREG32(BASE + 0x90)   /* SPI 1 Data 32bit */
+#define AUX_SPI0_PEEK_REG(BASE)   HWREG32(BASE + 0x94)   /* SPI 1 Peek 16bit */
+#define AUX_SPI1_CNTL0_REG(BASE)  HWREG32(BASE + 0xC0)   /* SPI 2 Control register 0 32bit */
+#define AUX_SPI1_CNTL1_REG(BASE)  HWREG32(BASE + 0xC4)   /* SPI 2 Control register 1 8bit */
+
+int rt_hw_uart_init(void);
+
+#endif /* DRV_UART_H__ */
+
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
new file mode 100644
index 0000000000..31b242fab5
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+#include "drv_wdt.h"
+
+#ifdef BSP_USING_WDT
+
+#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
+#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
+
+static struct raspi_wdt_driver bcm_wdt;
+
+void raspi_watchdog_init(rt_uint32_t time_init)
+{
+    bcm_wdt.timeout = time_init;
+}
+
+void raspi_watchdog_start()
+{
+    volatile rt_uint32_t cur;
+    PM_WDOG = PM_PASSWORD | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET);
+    cur = PM_RSTC;
+    PM_RSTC = PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
+}
+
+void raspi_watchdog_stop()
+{
+    PM_RSTC = PM_PASSWORD | PM_RSTC_RESET;
+}
+
+void raspi_watchdog_clr()
+{
+    bcm_wdt.timeout = 0;
+}
+
+void raspi_watchdog_set_timeout(rt_uint32_t timeout_us)
+{
+    bcm_wdt.timeout = timeout_us;
+}
+
+rt_uint64_t raspi_watchdog_get_timeout()
+{
+    return bcm_wdt.timeout;
+}
+
+rt_uint64_t raspi_watchdog_get_timeleft()
+{
+    rt_uint32_t ret = PM_WDOG;
+    return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
+}
+
+static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt)
+{
+    /*init for 10S*/
+    raspi_watchdog_init(1000000);
+    raspi_watchdog_start();
+    raspi_watchdog_stop();
+    return RT_EOK;
+}
+
+static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    rt_uint64_t  timeout_us = 0;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        timeout_us = *((rt_uint32_t *)arg) * 1000000;
+        if (timeout_us >= 0xFFFFFFFF)
+            timeout_us = 0xFFFFFFFF;
+        raspi_watchdog_set_timeout((rt_uint32_t)timeout_us);
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        timeout_us = raspi_watchdog_get_timeout();
+        *((rt_uint32_t *)arg) = timeout_us / 1000000;
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
+        timeout_us = raspi_watchdog_get_timeleft();
+        *((rt_uint32_t *)arg) = timeout_us / 1000000;
+        break;
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        raspi_watchdog_clr();
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        raspi_watchdog_start();
+        break;
+    case RT_DEVICE_CTRL_WDT_STOP:
+        raspi_watchdog_stop();
+        break;
+    default:
+        return RT_EIO;
+    }
+    return RT_EOK;
+}
+
+static const struct rt_watchdog_ops raspi_wdg_pos =
+{
+    raspi_wdg_init,
+    raspi_wdg_control,
+};
+
+static rt_watchdog_t raspi_wdg;
+
+int rt_hw_wdt_init(void)
+{
+    raspi_wdg.ops = &raspi_wdg_pos;
+    rt_hw_watchdog_register(&raspi_wdg, "wdg", 0, RT_NULL);
+    return RT_EOK;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_wdt_init);
+#endif /*BSP_USING_WDT */
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h
new file mode 100644
index 0000000000..0b59ab79f3
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_WDT_H__
+#define __DRV_WDT_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+
+struct raspi_wdt_driver
+{
+    rt_uint32_t timeout;
+};
+
+int rt_hw_wdt_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/mbox.c b/bsp/raspberry-pi/raspi3-32/driver/mbox.c
new file mode 100644
index 0000000000..bbd5183aa8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/mbox.c
@@ -0,0 +1,54 @@
+/*
+ * File      : mbox.c
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+
+/* mailbox message buffer */
+#include "mbox.h"
+#include "mmu.h"
+
+volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR;
+/**
+ * Make a mailbox call. Returns 0 on failure, non-zero on success
+ */
+void init_mbox_mmu_map()
+{
+    rt_hw_change_mmu_table(MBOX_ADDR, 96, MBOX_ADDR, STRONG_ORDER_MEM);
+}
+
+int mbox_call(unsigned char ch, int mmu_enable)
+{
+    unsigned int r = (((MBOX_ADDR)&~0xF) | (ch&0xF));
+    if (mmu_enable)
+        r = BUS_ADDRESS(r);
+    /* wait until we can write to the mailbox */
+    do
+    {
+        asm volatile("nop");
+    } while (*MBOX_STATUS & MBOX_FULL);
+    /* write the address of our message to the mailbox with channel identifier */
+    *MBOX_WRITE = r;
+    /* now wait for the response */
+    while (1)
+    {
+        /* is there a response? */
+        do
+        {
+            asm volatile("nop");
+        } 
+        while (*MBOX_STATUS & MBOX_EMPTY);
+        /* is it a response to our message? */
+        if (r == *MBOX_READ)
+        {
+            /* is it a valid successful response? */
+            return mbox[1] == MBOX_RESPONSE;
+        }
+    }
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi3-32/driver/mbox.h b/bsp/raspberry-pi/raspi3-32/driver/mbox.h
new file mode 100644
index 0000000000..5c59fd608c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/mbox.h
@@ -0,0 +1,63 @@
+/*
+ * File      : mbox.h
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+
+#ifndef __MBOX_H__
+#define __MBOX_H__
+
+/* a properly aligned buffer */
+extern volatile unsigned int* mbox;
+
+#define MBOX_REQUEST    0
+
+/* channels */
+#define MBOX_CH_POWER   0
+#define MBOX_CH_FB      1
+#define MBOX_CH_VUART   2
+#define MBOX_CH_VCHIQ   3
+#define MBOX_CH_LEDS    4
+#define MBOX_CH_BTNS    5
+#define MBOX_CH_TOUCH   6
+#define MBOX_CH_COUNT   7
+#define MBOX_CH_PROP    8
+
+/* tags */
+#define MBOX_TAG_SETPOWER       0x28001
+#define MBOX_TAG_SETCLKRATE     0x38002
+#define MBOX_GET_MAC_ADDRESS    0x10003
+#define MBOX_GET_CLOCK_RATE        0x30002
+#define MBOX_SET_CLOCK_RATE        0x38002
+#define MBOX_TAG_LAST           0
+
+#define MMIO_BASE       0x3F000000
+#define VIDEOCORE_MBOX  (MMIO_BASE+0x0000B880)
+#define MBOX_READ       ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0))
+#define MBOX_POLL       ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10))
+#define MBOX_SENDER     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14))
+#define MBOX_STATUS     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18))
+#define MBOX_CONFIG     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C))
+#define MBOX_WRITE      ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20))
+#define MBOX_RESPONSE   0x80000000
+#define MBOX_FULL       0x80000000
+#define MBOX_EMPTY      0x40000000
+
+#define DEVICE_ID_SD_CARD    0
+#define DEVICE_ID_USB_HCD    3
+#define POWER_STATE_OFF        (0 << 0)
+#define POWER_STATE_ON        (1 << 0)
+#define POWER_STATE_WAIT    (1 << 1)
+#define POWER_STATE_NO_DEVICE    (1 << 1)    // in response
+#define MMU_ENABLE 1
+#define MMU_DISABLE 0
+
+#define MBOX_ADDR 0xc00000
+
+int mbox_call(unsigned char ch, int mmu_enable);
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/raspi.h b/bsp/raspberry-pi/raspi3-32/driver/raspi.h
new file mode 100644
index 0000000000..19daa3541d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/driver/raspi.h
@@ -0,0 +1,432 @@
+/*
+ * File      : rsapi.h
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date    Author  Notes
+ * 2019-07-29     zdzn    first version
+ */
+
+#ifndef __RASPI_H__
+#define __RASPI_H__
+
+/* define for bcm283x*/
+typedef enum
+{
+    BCM_GPIO_PIN_0 = 0,
+    BCM_GPIO_PIN_1,
+    BCM_GPIO_PIN_2,
+    BCM_GPIO_PIN_3,
+    BCM_GPIO_PIN_4,
+    BCM_GPIO_PIN_5,
+    BCM_GPIO_PIN_6,
+    BCM_GPIO_PIN_7,
+    BCM_GPIO_PIN_8,
+    BCM_GPIO_PIN_9,
+    BCM_GPIO_PIN_10,
+    BCM_GPIO_PIN_11,
+    BCM_GPIO_PIN_12,
+    BCM_GPIO_PIN_13,
+    BCM_GPIO_PIN_14,
+    BCM_GPIO_PIN_15,
+    BCM_GPIO_PIN_16,
+    BCM_GPIO_PIN_17,
+    BCM_GPIO_PIN_18,
+    BCM_GPIO_PIN_19,
+    BCM_GPIO_PIN_20,
+    BCM_GPIO_PIN_21,
+    BCM_GPIO_PIN_22,
+    BCM_GPIO_PIN_23,
+    BCM_GPIO_PIN_24,
+    BCM_GPIO_PIN_25,
+    BCM_GPIO_PIN_26,
+    BCM_GPIO_PIN_27,
+    BCM_GPIO_PIN_28,
+    BCM_GPIO_PIN_29,
+    BCM_GPIO_PIN_30,
+    BCM_GPIO_PIN_31,
+    BCM_GPIO_PIN_32,
+    BCM_GPIO_PIN_33,
+    BCM_GPIO_PIN_34,
+    BCM_GPIO_PIN_35,
+    BCM_GPIO_PIN_36,
+    BCM_GPIO_PIN_37,
+    BCM_GPIO_PIN_38,
+    BCM_GPIO_PIN_39,
+    BCM_GPIO_PIN_40,
+    BCM_GPIO_PIN_41,
+    BCM_GPIO_PIN_42,
+    BCM_GPIO_PIN_43,
+    BCM_GPIO_PIN_44,
+    BCM_GPIO_PIN_45,
+    BCM_GPIO_PIN_46,
+    BCM_GPIO_PIN_47,
+    BCM_GPIO_PIN_48,
+    BCM_GPIO_PIN_49,
+    BCM_GPIO_PIN_50,
+    BCM_GPIO_PIN_51,
+    BCM_GPIO_PIN_52,
+    BCM_GPIO_PIN_53,
+    BCM_GPIO_PIN_NULL,
+} bcm_gpio_pin;
+
+typedef enum
+{
+    BCM283X_GPIO_FSEL_INPT = 0x00,   /*!< Input 0b000 */
+    BCM283X_GPIO_FSEL_OUTP = 0x01,   /*!< Output 0b001 */
+    BCM283X_GPIO_FSEL_ALT0 = 0x04,   /*!< Alternate function 0 0b100 */
+    BCM283X_GPIO_FSEL_ALT1 = 0x05,   /*!< Alternate function 1 0b101 */
+    BCM283X_GPIO_FSEL_ALT2 = 0x06,   /*!< Alternate function 2 0b110, */
+    BCM283X_GPIO_FSEL_ALT3 = 0x07,   /*!< Alternate function 3 0b111 */
+    BCM283X_GPIO_FSEL_ALT4 = 0x03,   /*!< Alternate function 4 0b011 */
+    BCM283X_GPIO_FSEL_ALT5 = 0x02,   /*!< Alternate function 5 0b010 */
+    BCM283X_GPIO_FSEL_MASK = 0x07    /*!< Function select bits mask 0b111 */
+} gpio_function_select;
+
+typedef enum
+{
+    BCM283X_GPIO_PUD_OFF    = 0x00,   /*!< Off ? disable pull-up/down 0b00 */
+    BCM283X_GPIO_PUD_DOWN   = 0x01,   /*!< Enable Pull Down control 0b01 */
+    BCM283X_GPIO_PUD_UP     = 0x02    /*!< Enable Pull Up control 0b10  */
+} gpio_pud_mode;
+
+#define BCM283X_CORE_CLK_HZ 250000000    /* 50 MHz */
+
+/* Base Address */
+#define PER_BASE     (0x3F000000)
+#define PER_BASE_40000000    (0x40000000)
+//#define BCM283X_PERI_BASE     (0x3F000000)
+//#define BCM283X_PER_BASE_40000000    (0x40000000)
+
+/* Base Address Registers Offset */
+#define ST_BASE_OFFSET     (0x003000)
+#define GPIO_PAD_OFFSET     (0x100000)
+#define CLOCK_BASE_OFFSET (0x101000)
+#define GPIO_BASE_OFFSET (0x200000)
+#define SPI0_BASE_OFFSET (0x204000)
+#define BSC0_BASE_OFFSET (0x205000)
+#define GPIO_PWM_OFFSET     (0x20C000)
+#define AUX_BASE_OFFSET     (0x215000)
+#define SPI1_BASE_OFFSET (0x215080)
+#define SPI2_BASE_OFFSET (0x2150C0)
+#define BSC1_BASE_OFFSET (0x804000)
+#define BSC2_BASE_OFFSET (0x805000)
+
+/* IRQ */
+#define IRQ_SYSTEM_TIMER_0 0
+#define IRQ_SYSTEM_TIMER_1  1
+#define IRQ_SYSTEM_TIMER_2 2
+#define IRQ_SYSTEM_TIMER_3 3
+#define IRQ_USB      9
+#define IRQ_AUX      29
+#define IRQ_PCM      55
+#define IRQ_ARM_TIMER     64
+#define IRQ_ARM_MAILBOX     65
+
+/* Interrupt Controler */
+#define IRQ_BASE     (PER_BASE + 0xB200)
+#define IRQ_PEND_BASIC      HWREG32(IRQ_BASE + 0x0000)
+#define IRQ_PEND1    HWREG32(IRQ_BASE + 0x0004)
+#define IRQ_PEND2    HWREG32(IRQ_BASE + 0x0008)
+#define IRQ_FIQ_CONTROL     HWREG32(IRQ_BASE + 0x000C)
+#define IRQ_ENABLE1  HWREG32(IRQ_BASE + 0x0010)
+#define IRQ_ENABLE2  HWREG32(IRQ_BASE + 0x0014)
+#define IRQ_ENABLE_BASIC    HWREG32(IRQ_BASE + 0x0018)
+#define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x001C)
+#define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x0020)
+#define IRQ_DISABLE_BASIC   HWREG32(IRQ_BASE + 0x0024)
+
+
+/* Defines for WDT*/
+#define PM_BASE  (PER_BASE  + GPIO_PAD_OFFSET)
+#define PM_RSTC  HWREG32(PM_BASE + 0x001C)
+#define PM_RSTS  HWREG32(PM_BASE + 0x0020)
+#define PM_WDOG  HWREG32(PM_BASE + 0x0024)
+
+#define PM_PASSWORD     0x5a000000
+#define PM_WDOG_TIME_SET    0x000fffff
+#define PM_RSTC_WRCFG_CLR    0xffffffcf
+#define PM_RSTS_HADWRH_SET    0x00000040
+#define PM_RSTC_WRCFG_SET    0x00000030
+#define PM_RSTC_WRCFG_FULL_RESET    0x00000020
+#define PM_RSTC_RESET 0x00000102
+#define PM_RSTS_PARTITION_CLR 0xfffffaaa
+
+/* Defines for System Timer */
+#define STIMER_BASE  (PER_BASE  + ST_BASE_OFFSET)
+#define STIMER_CS    HWREG32(STIMER_BASE + 0x0000)
+#define STIMER_CLO   HWREG32(STIMER_BASE + 0x0004)
+#define STIMER_CHI   HWREG32(STIMER_BASE + 0x0008)
+#define STIMER_C0    HWREG32(STIMER_BASE + 0x000C)
+#define STIMER_C1    HWREG32(STIMER_BASE + 0x0010)
+#define STIMER_C2    HWREG32(STIMER_BASE + 0x0014)
+#define STIMER_C3    HWREG32(STIMER_BASE + 0x0018)
+
+#define DELAY_MICROS(micros) \
+    do{ \
+ rt_uint32_t compare = STIMER_CLO + micros * 25; \
+ while (STIMER_CLO < compare); \
+    } while (0) \
+
+/* Defines for GPIO */
+#define BCM283X_GPIO_BASE     (PER_BASE + GPIO_BASE_OFFSET)
+#define BCM283X_GPIO_GPFSEL(n) HWREG32(BCM283X_GPIO_BASE + 0x0000 + 0x4 * n) /* GPIO Function Select 32bit R/W */
+#define BCM283X_GPIO_GPSET(n) HWREG32(BCM283X_GPIO_BASE + 0x001C + 0x4 * n) /* GPIO Pin Output Set */
+#define BCM283X_GPIO_GPCLR(n) HWREG32(BCM283X_GPIO_BASE + 0x0028 + 0x4 * n) /* GPIO Pin Output Clear */
+#define BCM2835_GPIO_GPLEV(n) HWREG32(BCM283X_GPIO_BASE + 0x0034 + 0x4 * n) /* GPIO Pin Level */
+#define BCM283X_GPIO_GPEDS(n) HWREG32(BCM283X_GPIO_BASE + 0x0040 + 0x4 * n) /* GPIO Pin Event Detect Status */
+#define BCM283X_GPIO_GPREN(n) HWREG32(BCM283X_GPIO_BASE + 0x004c + 0x4 * n) /* GPIO Pin Rising Edge Detect Enable */
+#define BCM283X_GPIO_GPFEN(n) HWREG32(BCM283X_GPIO_BASE + 0x0058 + 0x4 * n) /* GPIO Pin Falling Edge Detect Enable */
+#define BCM283X_GPIO_GPHEN(n) HWREG32(BCM283X_GPIO_BASE + 0x0064 + 0x4 * n) /* GPIO Pin High Detect Enable  */
+#define BCM283X_GPIO_GPLEN(n) HWREG32(BCM283X_GPIO_BASE + 0x0070 + 0x4 * n) /* GPIO Pin Low Detect Enable */
+#define BCM283X_GPIO_GPAREN(n) HWREG32(BCM283X_GPIO_BASE + 0x007C + 0x4 * n) /* GPIO Pin Async. Rising Edge Detect */
+#define BCM283X_GPIO_GPAFEN(n) HWREG32(BCM283X_GPIO_BASE + 0x0088 + 0x4 * n) /* GPIO Pin Async. Falling Edge Detect */
+#define BCM283X_GPIO_GPPUD     HWREG32(BCM283X_GPIO_BASE + 0x0094)     /* GPIO Pin Pull-up/down Enable */
+#define BCM283X_GPIO_GPPUDCLK(n)    HWREG32(BCM283X_GPIO_BASE + 0x0098 + 0x4 * n) /* GPIO Pin Pull-up/down Enable Clock */
+
+#define GPIO_FSEL_NUM(pin)  (pin/10)
+#define GPIO_FSEL_SHIFT(pin)  ((pin%10)*3)
+#define GPIO_FSEL(pin, mode) \
+    do{ \
+ __sync_synchronize(); \
+ BCM283X_GPIO_GPFSEL(GPIO_FSEL_NUM(pin)) |= ((mode & BCM283X_GPIO_FSEL_MASK) << GPIO_FSEL_SHIFT(pin)); \
+    } while (0) \
+
+/* Defines for I2C */
+#define BCM283X_BSC0_BASE     (PER_BASE + BSC0_BASE_OFFSET)    //for i2c0
+#define BCM283X_BSC1_BASE     (PER_BASE + BSC1_BASE_OFFSET)    //for i2c1
+#define BCM283X_BSC2_BASE     (PER_BASE + BSC2_BASE_OFFSET)    //for hdmi i2c not use
+
+#define BCM283X_BSC_C(BASE)  HWREG32(BASE + 0x0000)    /* BSC Master Control */
+#define BCM283X_BSC_S(BASE)  HWREG32(BASE + 0x0004)    /* BSC Master Status */
+#define BCM283X_BSC_DLEN(BASE)      HWREG32(BASE + 0x0008)    /* BSC Master Data Length */
+#define BCM283X_BSC_A(BASE)  HWREG32(BASE + 0x000c)    /* BSC Master Slave Address */
+#define BCM283X_BSC_FIFO(BASE)      HWREG32(BASE + 0x0010)    /* BSC Master Data FIFO */
+#define BCM283X_BSC_DIV(BASE)       HWREG32(BASE + 0x0014)    /* BSC Master Clock Divider */
+#define BCM283X_BSC_DEL(BASE)       HWREG32(BASE + 0x0018)    /* BSC Master Data Delay */
+#define BCM283X_BSC_CLKT(BASE)      HWREG32(BASE + 0x001c)    /* BSC Master Clock Stretch Timeout */
+
+/* Register masks for C Register */
+#define BSC_C_I2CEN      0x00008000 /* I2C Enable, 0 = disabled, 1 = enabled */
+#define BSC_C_INTR      0x00000400 /* Interrupt on RX */
+#define BSC_C_INTT      0x00000200 /* Interrupt on TX */
+#define BSC_C_INTD      0x00000100 /* Interrupt on DONE */
+#define BSC_C_ST      0x00000080 /* Start transfer, 1 = Start a new transfer */
+#define BSC_C_CLEAR_1   0x00000020 /* Clear FIFO Clear */
+#define BSC_C_CLEAR_2   0x00000010 /* Clear FIFO Clear */
+#define BSC_C_READ       0x00000001 /* Read transfer */
+
+/* Register masks for S Register */
+#define BSC_S_CLKT      0x00000200 /* Clock stretch timeout */
+#define BSC_S_ERR      0x00000100 /* ACK error */
+#define BSC_S_RXF       0x00000080 /* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
+#define BSC_S_TXE       0x00000040 /* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
+#define BSC_S_RXD       0x00000020 /* RXD FIFO contains data */
+#define BSC_S_TXD       0x00000010 /* TXD FIFO can accept data */
+#define BSC_S_RXR      0x00000008 /* RXR FIFO needs reading (full) */
+#define BSC_S_TXW      0x00000004 /* TXW FIFO needs writing (full) */
+#define BSC_S_DONE      0x00000002 /* Transfer DONE */
+#define BSC_S_TA      0x00000001 /* Transfer Active */
+
+#define BSC_FIFO_SIZE  (16)  /* BSC FIFO size */
+
+/* Defines for SPI */
+#define BCM283X_SPI0_BASE     (PER_BASE + SPI0_BASE_OFFSET)
+#define BCM283X_SPI1_BASE     (PER_BASE + SPI1_BASE_OFFSET)
+#define BCM283X_SPI2_BASE     (PER_BASE + SPI2_BASE_OFFSET)
+
+#define BCM283X_SPI0_CS(BASE) HWREG32(BASE + 0x0000) /* SPI Master Control and Status */
+#define BCM283X_SPI0_FIFO(BASE) HWREG32(BASE + 0x0004) /* SPI Master TX and RX FIFOs */
+#define BCM283X_SPI0_CLK(BASE) HWREG32(BASE + 0x0008) /* SPI Master Clock Divider */
+#define BCM283X_SPI0_DLEN(BASE) HWREG32(BASE + 0x000c) /* SPI Master Data Length */
+#define BCM283X_SPI0_LTOH(BASE) HWREG32(BASE + 0x0010) /* SPI LOSSI mode TOH */
+#define BCM283X_SPI0_DC(BASE) HWREG32(BASE + 0x0014) /* SPI DMA DREQ Controls */
+
+/* Register masks for SPI0_CS */
+#define BCM283X_SPI0_CS_LEN_LONG    0x02000000 /* Enable Long data word in Lossi mode if DMA_LEN is set */
+#define BCM283X_SPI0_CS_DMA_LEN 0x01000000 /* Enable DMA mode in Lossi mode */
+#define BCM283X_SPI0_CS_CSPOL2 0x00800000 /* Chip Select 2 Polarity */
+#define BCM283X_SPI0_CS_CSPOL1 0x00400000 /* Chip Select 1 Polarity */
+#define BCM283X_SPI0_CS_CSPOL0 0x00200000 /* Chip Select 0 Polarity */
+#define BCM283X_SPI0_CS_RXF     0x00100000 /* RXF - RX FIFO Full */
+#define BCM283X_SPI0_CS_RXR     0x00080000 /* RXR RX FIFO needs Reading (full) */
+#define BCM283X_SPI0_CS_TXD     0x00040000 /* TXD TX FIFO can accept Data */
+#define BCM283X_SPI0_CS_RXD     0x00020000 /* RXD RX FIFO contains Data */
+#define BCM283X_SPI0_CS_DONE 0x00010000 /* Done transfer Done */
+#define BCM283X_SPI0_CS_TE_EN 0x00008000 /* Unused */
+#define BCM283X_SPI0_CS_LMONO 0x00004000 /* Unused */
+#define BCM283X_SPI0_CS_LEN     0x00002000 /* LEN LoSSI enable */
+#define BCM283X_SPI0_CS_REN     0x00001000 /* REN Read Enable */
+#define BCM283X_SPI0_CS_ADCS 0x00000800 /* ADCS Automatically Deassert Chip Select */
+#define BCM283X_SPI0_CS_INTR 0x00000400 /* INTR Interrupt on RXR */
+#define BCM283X_SPI0_CS_INTD 0x00000200 /* INTD Interrupt on Done */
+#define BCM283X_SPI0_CS_DMAEN 0x00000100 /* DMAEN DMA Enable */
+#define BCM283X_SPI0_CS_TA     0x00000080 /* Transfer Active */
+#define BCM283X_SPI0_CS_CSPOL 0x00000040 /* Chip Select Polarity */
+#define BCM283X_SPI0_CS_CLEAR 0x00000030 /* Clear FIFO Clear RX and TX */
+#define BCM283X_SPI0_CS_CLEAR_RX    0x00000020 /* Clear FIFO Clear RX  */
+#define BCM283X_SPI0_CS_CLEAR_TX    0x00000010 /* Clear FIFO Clear TX  */
+#define BCM283X_SPI0_CS_CPOL 0x00000008 /* Clock Polarity */
+#define BCM283X_SPI0_CS_CPHA 0x00000004 /* Clock Phase */
+#define BCM283X_SPI0_CS_CS     0x00000003 /* Chip Select */
+
+/* ARM Timer */
+#define ARM_TIMER_BASE  (PER_BASE + 0xB000)
+#define ARM_TIMER_LOAD  HWREG32(ARM_TIMER_BASE + 0x400)
+#define ARM_TIMER_VALUE  HWREG32(ARM_TIMER_BASE + 0x404)
+#define ARM_TIMER_CTRL  HWREG32(ARM_TIMER_BASE + 0x408)
+#define ARM_TIMER_IRQCLR     HWREG32(ARM_TIMER_BASE + 0x40C)
+#define ARM_TIMER_RAWIRQ     HWREG32(ARM_TIMER_BASE + 0x410)
+#define ARM_TIMER_MASKIRQ     HWREG32(ARM_TIMER_BASE + 0x414)
+#define ARM_TIMER_RELOAD     HWREG32(ARM_TIMER_BASE + 0x418)
+#define ARM_TIMER_PREDIV     HWREG32(ARM_TIMER_BASE + 0x41C)
+#define ARM_TIMER_CNTR  HWREG32(ARM_TIMER_BASE + 0x420)
+
+/* ARM Core Timer */
+#define C0TIMER_INTCTL   HWREG32(PER_BASE_40000000 + 0x40)  /* Core0 timers Interrupt control */
+#define C1TIMER_INTCTL  HWREG32(PER_BASE_40000000 + 0x44)  /* Core1 timers Interrupt control */
+#define C2TIMER_INTCTL  HWREG32(PER_BASE_40000000 + 0x48)  /* Core2 timers Interrupt control */
+#define C3TIMER_INTCTL  HWREG32(PER_BASE_40000000 + 0x4C)  /* Core3 timers Interrupt control */
+#define CORETIMER_INTCTL(n)     HWREG32(PER_BASE_40000000 + 0x40 + n*4)  /* Coren timers Interrupt control */
+
+/* ARM Core Mailbox interrupt */
+#define C0MB_INTCTL      HWREG32(PER_BASE_40000000 + 0x50)  /* Core0 Mailboxes Interrupt control */
+#define C1MB_INTCTL      HWREG32(PER_BASE_40000000 + 0x54)  /* Core1 Mailboxes Interrupt control */
+#define C2MB_INTCTL      HWREG32(PER_BASE_40000000 + 0x58)  /* Core2 Mailboxes Interrupt control */
+#define C3MB_INTCTL      HWREG32(PER_BASE_40000000 + 0x5C)  /* Core3 Mailboxes Interrupt control */
+#define COREMB_INTCTL(n)     HWREG32(PER_BASE_40000000 + 0x50 + 4*n)  /* Coren Mailboxes Interrupt control */
+
+/* ARM Core IRQ/FIQ status */
+#define C0_IRQSOURCE  HWREG32(PER_BASE_40000000 + 0x60)  /* Core0 IRQ Source */
+#define C1_IRQSOURCE  HWREG32(PER_BASE_40000000 + 0x64)  /* Core1 IRQ Source */
+#define C2_IRQSOURCE  HWREG32(PER_BASE_40000000 + 0x68)  /* Core2 IRQ Source */
+#define C3_IRQSOURCE  HWREG32(PER_BASE_40000000 + 0x6C)  /* Core3 IRQ Source */
+#define C0_FIQSOURCE  HWREG32(PER_BASE_40000000 + 0x70)  /* Core0 FIQ Source */
+#define C1_FIQSOURCE  HWREG32(PER_BASE_40000000 + 0x74)  /* Core1 FIQ Source */
+#define C2_FIQSOURCE  HWREG32(PER_BASE_40000000 + 0x78)  /* Core2 FIQ Source */
+#define C3_FIQSOURCE  HWREG32(PER_BASE_40000000 + 0x7C)  /* Core3 FIQ Source */
+#define CORE_IRQSOURCE(n)     HWREG32(PER_BASE_40000000 + 0x60+ n*0x4)
+#define CORE_FIQSOURCE(n)     HWREG32(PER_BASE_40000000 + 0x70+ n*0x4)
+
+#define CORE_MAILBOX3_SET(n) HWREG32(PER_BASE_40000000 + 0x8C + n*0x10)
+#define CORE_MAILBOX3_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xCC + n*0x10)
+#define CORE_MAILBOX2_SET(n) HWREG32(PER_BASE_40000000 + 0x88 + n*0x10)
+#define CORE_MAILBOX2_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC8 + n*0x10)
+#define CORE_MAILBOX1_SET(n) HWREG32(PER_BASE_40000000 + 0x84 + n*0x10)
+#define CORE_MAILBOX1_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC4 + n*0x10)
+#define CORE_MAILBOX0_SET(n) HWREG32(PER_BASE_40000000 + 0x80 + n*0x10)
+#define CORE_MAILBOX0_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC0 + n*0x10)
+
+/* For SMP IPI use MailBox0 */
+#define IPI_MAILBOX_SET  CORE_MAILBOX0_SET
+#define IPI_MAILBOX_CLEAR     CORE_MAILBOX0_CLEAR
+#define IPI_MAILBOX_INT_MASK (0x01)
+
+enum spi_bit_order
+{
+    BCM283X_SPI_BIT_ORDER_LSBFIRST = 0,  /*!< LSB First */
+    BCM283X_SPI_BIT_ORDER_MSBFIRST = 1   /*!< MSB First */
+};
+
+enum spi_mode
+{
+    BCM283X_SPI_MODE0 = 0,  /*!< CPOL = 0, CPHA = 0 */
+    BCM283X_SPI_MODE1 = 1,  /*!< CPOL = 0, CPHA = 1 */
+    BCM283X_SPI_MODE2 = 2,  /*!< CPOL = 1, CPHA = 0 */
+    BCM283X_SPI_MODE3 = 3   /*!< CPOL = 1, CPHA = 1 */
+};
+
+enum spi_chip_select
+{
+    BCM283X_SPI_CS0 = 0,     /*!< Chip Select 0 */
+    BCM283X_SPI_CS1 = 1,     /*!< Chip Select 1 */
+    BCM283X_SPI_CS2 = 2,     /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
+    BCM283X_SPI_CS_NONE = 3  /*!< No CS, control it yourself */
+};
+
+enum spi_clock_divider
+{
+    BCM283X_SPI_CLOCK_DIVIDER_65536 = 0,       /*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_32768 = 32768,   /*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_16384 = 16384,   /*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_8192 = 8192,    /*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_4096 = 4096,    /*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_2048 = 2048,    /*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_1024 = 1024,    /*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_512  = 512,     /*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_256  = 256,     /*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_128  = 128,     /*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_64   = 64,      /*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_32   = 32,      /*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_16   = 16,      /*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_8    = 8,       /*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_4    = 4,       /*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */
+    BCM283X_SPI_CLOCK_DIVIDER_2    = 2,       /*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/
+    BCM283X_SPI_CLOCK_DIVIDER_1    = 1 /*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */
+};
+
+/*redefine for raspi*/
+typedef gpio_function_select raspi_pin_select;
+typedef enum
+{
+    RPI_GPIO_P1_01 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_02 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_03 = BCM_GPIO_PIN_2,
+    RPI_GPIO_P1_04 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_05 = BCM_GPIO_PIN_3,
+    RPI_GPIO_P1_06 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_07 = BCM_GPIO_PIN_4,
+    RPI_GPIO_P1_08 = BCM_GPIO_PIN_14,
+    RPI_GPIO_P1_09 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_10 = BCM_GPIO_PIN_15,
+    RPI_GPIO_P1_11 = BCM_GPIO_PIN_17,
+    RPI_GPIO_P1_12 = BCM_GPIO_PIN_18,
+    RPI_GPIO_P1_13 = BCM_GPIO_PIN_27,
+    RPI_GPIO_P1_14 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_15 = BCM_GPIO_PIN_22,
+    RPI_GPIO_P1_16 = BCM_GPIO_PIN_23,
+    RPI_GPIO_P1_17 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_18 = BCM_GPIO_PIN_24,
+    RPI_GPIO_P1_19 = BCM_GPIO_PIN_10,
+    RPI_GPIO_P1_20 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_21 = BCM_GPIO_PIN_9,
+    RPI_GPIO_P1_22 = BCM_GPIO_PIN_25,
+    RPI_GPIO_P1_23 = BCM_GPIO_PIN_11,
+    RPI_GPIO_P1_24 = BCM_GPIO_PIN_8,
+    RPI_GPIO_P1_25 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_26 = BCM_GPIO_PIN_7,
+    RPI_GPIO_P1_27 = BCM_GPIO_PIN_0,
+    RPI_GPIO_P1_28 = BCM_GPIO_PIN_1,
+    RPI_GPIO_P1_29 = BCM_GPIO_PIN_5,
+    RPI_GPIO_P1_30 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_31 = BCM_GPIO_PIN_6,
+    RPI_GPIO_P1_32 = BCM_GPIO_PIN_12,
+    RPI_GPIO_P1_33 = BCM_GPIO_PIN_13,
+    RPI_GPIO_P1_34 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_35 = BCM_GPIO_PIN_19,
+    RPI_GPIO_P1_36 = BCM_GPIO_PIN_16,
+    RPI_GPIO_P1_37 = BCM_GPIO_PIN_26,
+    RPI_GPIO_P1_38 = BCM_GPIO_PIN_20,
+    RPI_GPIO_P1_39 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_40 = BCM_GPIO_PIN_21,
+} raspi_gpio_pin;
+
+typedef enum
+{
+    BCM283X_I2C_CLOCK_DIVIDER_2500  = 2500,      /* 2500 = 10us = 100 kHz */
+    BCM283X_I2C_CLOCK_DIVIDER_626   = 626,       /* 622 = 2.504us = 399.3610 kHz */
+    BCM283X_I2C_CLOCK_DIVIDER_150   = 150,       /* 150 = 60ns = 1.666 MHz (default at reset) */
+    BCM283X_I2C_CLOCK_DIVIDER_148   = 148 /* 148 = 59ns = 1.689 MHz */
+} i2c_clock_divider;
+
+typedef enum
+{
+    BCM283X_I2C_REASON_OK    = 0x00,      /* Success */
+    BCM283X_I2C_REASON_ERROR_NACK   = 0x01,      /* Received a NACK */
+    BCM283X_I2C_REASON_ERROR_CLKT   = 0x02,      /* Received Clock Stretch Timeout */
+    BCM283X_I2C_REASON_ERROR_DATA   = 0x04       /* Not all data is sent / received */
+} i2c_reason_codes;
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/figures/GPIO-Pinout-Diagram-2.png b/bsp/raspberry-pi/raspi3-32/figures/GPIO-Pinout-Diagram-2.png
new file mode 100644
index 0000000000..24238cc23d
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diff --git a/bsp/raspberry-pi/raspi3-32/figures/raspberrypi-console.png b/bsp/raspberry-pi/raspi3-32/figures/raspberrypi-console.png
new file mode 100644
index 0000000000..a36f6f75e0
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diff --git a/bsp/raspberry-pi/raspi3-32/figures/raspi3_b.jpg b/bsp/raspberry-pi/raspi3-32/figures/raspi3_b.jpg
new file mode 100644
index 0000000000..03db419bd8
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diff --git a/bsp/raspberry-pi/raspi3-32/figures/raspi3_f.jpg b/bsp/raspberry-pi/raspi3-32/figures/raspi3_f.jpg
new file mode 100644
index 0000000000..dd2f251332
Binary files /dev/null and b/bsp/raspberry-pi/raspi3-32/figures/raspi3_f.jpg differ
diff --git a/bsp/raspberry-pi/raspi3-32/link.lds b/bsp/raspberry-pi/raspi3-32/link.lds
new file mode 100644
index 0000000000..75e0845943
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/link.lds
@@ -0,0 +1,149 @@
+/*
+ * File      : link.lds
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+SECTIONS
+{
+    . = 0x00008000;
+    . = ALIGN(4);
+    .text :
+    {
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    }
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(4);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(8);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(4);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+        PROVIDE(__bss_end = .);
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/raspberry-pi/raspi3-32/rtconfig.h b/bsp/raspberry-pi/raspi3-32/rtconfig.h
new file mode 100644
index 0000000000..b861bf8827
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/rtconfig.h
@@ -0,0 +1,391 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+/* RT_USING_ARCH_DATA_TYPE is not set */
+#define RT_USING_SMP
+#define RT_CPUS_NR 4
+#define RT_ALIGN_SIZE 4
+/* RT_THREAD_PRIORITY_8 is not set */
+#define RT_THREAD_PRIORITY_32
+/* RT_THREAD_PRIORITY_256 is not set */
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+/* RT_USING_TIMER_SOFT is not set */
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+/* RT_DEBUG_INIT_CONFIG is not set */
+/* RT_DEBUG_THREAD_CONFIG is not set */
+/* RT_DEBUG_SCHEDULER_CONFIG is not set */
+/* RT_DEBUG_IPC_CONFIG is not set */
+/* RT_DEBUG_TIMER_CONFIG is not set */
+/* RT_DEBUG_IRQ_CONFIG is not set */
+/* RT_DEBUG_MEM_CONFIG is not set */
+/* RT_DEBUG_SLAB_CONFIG is not set */
+/* RT_DEBUG_MEMHEAP_CONFIG is not set */
+/* RT_DEBUG_MODULE_CONFIG is not set */
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* RT_USING_SIGNALS is not set */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_MEMHEAP
+/* RT_USING_NOHEAP is not set */
+#define RT_USING_SMALL_MEM
+/* RT_USING_SLAB is not set */
+/* RT_USING_MEMHEAP_AS_HEAP is not set */
+#define RT_USING_MEMTRACE
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
+/* RT_USING_INTERRUPT_INFO is not set */
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40002
+#define ARCH_ARM
+/* RT_USING_CPU_FFS is not set */
+#define ARCH_ARM_CORTEX_A
+#define ARCH_ARM_CORTEX_A7
+/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+/* RT_USING_CPLUSPLUS is not set */
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+/* FINSH_ECHO_DISABLE_DEFAULT is not set */
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+/* FINSH_USING_AUTH is not set */
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+/* RT_USING_DFS_MNTTABLE is not set */
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+/* RT_DFS_ELM_USE_LFN_0 is not set */
+/* RT_DFS_ELM_USE_LFN_1 is not set */
+/* RT_DFS_ELM_USE_LFN_2 is not set */
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+/* RT_DFS_ELM_USE_ERASE is not set */
+#define RT_DFS_ELM_REENTRANT
+#define RT_USING_DFS_DEVFS
+/* RT_USING_DFS_ROMFS is not set */
+/* RT_USING_DFS_RAMFS is not set */
+/* RT_USING_DFS_UFFS is not set */
+/* RT_USING_DFS_JFFS2 is not set */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+/* RT_USING_SYSTEM_WORKQUEUE is not set */
+#define RT_USING_SERIAL
+/* RT_SERIAL_USING_DMA is not set */
+#define RT_SERIAL_RB_BUFSZ 64
+/* RT_USING_CAN is not set */
+#define RT_USING_HWTIMER
+/* RT_USING_CPUTIME is not set */
+#define RT_USING_I2C
+/* RT_USING_I2C_BITOPS is not set */
+#define RT_USING_PIN
+/* RT_USING_ADC is not set */
+/* RT_USING_PWM is not set */
+/* RT_USING_MTD_NOR is not set */
+/* RT_USING_MTD_NAND is not set */
+/* RT_USING_PM is not set */
+#define RT_USING_RTC
+/* RT_USING_ALARM is not set */
+/* RT_USING_SOFT_RTC is not set */
+#define RT_USING_SDIO
+#define RT_SDIO_STACK_SIZE 512
+#define RT_SDIO_THREAD_PRIORITY 15
+#define RT_MMCSD_STACK_SIZE 1024
+#define RT_MMCSD_THREAD_PREORITY 22
+#define RT_MMCSD_MAX_PARTITION 16
+/* RT_SDIO_DEBUG is not set */
+#define RT_USING_SPI
+/* RT_USING_QSPI is not set */
+/* RT_USING_SPI_MSD is not set */
+/* RT_USING_SFUD is not set */
+/* RT_USING_ENC28J60 is not set */
+/* RT_USING_SPI_WIFI is not set */
+#define RT_USING_WDT
+/* RT_USING_AUDIO is not set */
+/* RT_USING_SENSOR is not set */
+/* RT_USING_TOUCH is not set */
+/* RT_USING_HWCRYPTO is not set */
+/* RT_USING_WIFI is not set */
+
+/* Using USB */
+
+/* RT_USING_USB_HOST is not set */
+/* RT_USING_USB_DEVICE is not set */
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+/* RT_USING_PTHREADS is not set */
+#define RT_USING_POSIX
+/* RT_USING_POSIX_MMAP is not set */
+/* RT_USING_POSIX_TERMIOS is not set */
+/* RT_USING_POSIX_AIO is not set */
+/* RT_USING_MODULE is not set */
+
+/* Network */
+
+/* Socket abstraction layer */
+
+/* RT_USING_SAL is not set */
+
+/* Network interface device */
+
+/* RT_USING_NETDEV is not set */
+
+/* light weight TCP/IP stack */
+
+/* RT_USING_LWIP is not set */
+
+/* AT commands */
+
+/* RT_USING_AT is not set */
+
+/* VBUS(Virtual Software BUS) */
+
+/* RT_USING_VBUS is not set */
+
+/* Utilities */
+
+/* RT_USING_RYM is not set */
+/* RT_USING_ULOG is not set */
+/* RT_USING_UTEST is not set */
+/* RT_USING_LWP is not set */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+/* PKG_USING_PAHOMQTT is not set */
+/* PKG_USING_WEBCLIENT is not set */
+/* PKG_USING_WEBNET is not set */
+/* PKG_USING_MONGOOSE is not set */
+/* PKG_USING_WEBTERMINAL is not set */
+/* PKG_USING_CJSON is not set */
+/* PKG_USING_JSMN is not set */
+/* PKG_USING_LIBMODBUS is not set */
+/* PKG_USING_FREEMODBUS is not set */
+/* PKG_USING_LJSON is not set */
+/* PKG_USING_EZXML is not set */
+/* PKG_USING_NANOPB is not set */
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* PKG_USING_WLANMARVELL is not set */
+
+/* Wiced WiFi */
+
+/* PKG_USING_WLAN_WICED is not set */
+/* PKG_USING_RW007 is not set */
+/* PKG_USING_COAP is not set */
+/* PKG_USING_NOPOLL is not set */
+/* PKG_USING_NETUTILS is not set */
+/* PKG_USING_AT_DEVICE is not set */
+/* PKG_USING_ATSRV_SOCKET is not set */
+/* PKG_USING_WIZNET is not set */
+
+/* IoT Cloud */
+
+/* PKG_USING_ONENET is not set */
+/* PKG_USING_GAGENT_CLOUD is not set */
+/* PKG_USING_ALI_IOTKIT is not set */
+/* PKG_USING_AZURE is not set */
+/* PKG_USING_TENCENT_IOTHUB is not set */
+/* PKG_USING_NIMBLE is not set */
+/* PKG_USING_OTA_DOWNLOADER is not set */
+/* PKG_USING_IPMSG is not set */
+/* PKG_USING_LSSDP is not set */
+/* PKG_USING_AIRKISS_OPEN is not set */
+/* PKG_USING_LIBRWS is not set */
+/* PKG_USING_TCPSERVER is not set */
+
+/* security packages */
+
+/* PKG_USING_MBEDTLS is not set */
+/* PKG_USING_libsodium is not set */
+/* PKG_USING_TINYCRYPT is not set */
+
+/* language packages */
+
+/* PKG_USING_LUA is not set */
+/* PKG_USING_JERRYSCRIPT is not set */
+/* PKG_USING_MICROPYTHON is not set */
+
+/* multimedia packages */
+
+/* PKG_USING_OPENMV is not set */
+/* PKG_USING_MUPDF is not set */
+/* PKG_USING_STEMWIN is not set */
+
+/* tools packages */
+
+/* PKG_USING_CMBACKTRACE is not set */
+/* PKG_USING_EASYFLASH is not set */
+/* PKG_USING_EASYLOGGER is not set */
+/* PKG_USING_SYSTEMVIEW is not set */
+/* PKG_USING_RDB is not set */
+/* PKG_USING_QRCODE is not set */
+/* PKG_USING_ULOG_EASYFLASH is not set */
+/* PKG_USING_ADBD is not set */
+
+/* system packages */
+
+/* PKG_USING_GUIENGINE is not set */
+/* PKG_USING_PERSIMMON is not set */
+/* PKG_USING_CAIRO is not set */
+/* PKG_USING_PIXMAN is not set */
+/* PKG_USING_LWEXT4 is not set */
+/* PKG_USING_PARTITION is not set */
+/* PKG_USING_FAL is not set */
+/* PKG_USING_SQLITE is not set */
+/* PKG_USING_RTI is not set */
+/* PKG_USING_LITTLEVGL2RTT is not set */
+/* PKG_USING_CMSIS is not set */
+/* PKG_USING_DFS_YAFFS is not set */
+/* PKG_USING_LITTLEFS is not set */
+/* PKG_USING_THREAD_POOL is not set */
+
+/* peripheral libraries and drivers */
+
+/* PKG_USING_SENSORS_DRIVERS is not set */
+/* PKG_USING_REALTEK_AMEBA is not set */
+/* PKG_USING_SHT2X is not set */
+/* PKG_USING_STM32_SDIO is not set */
+/* PKG_USING_ICM20608 is not set */
+/* PKG_USING_U8G2 is not set */
+/* PKG_USING_BUTTON is not set */
+/* PKG_USING_PCF8574 is not set */
+/* PKG_USING_SX12XX is not set */
+/* PKG_USING_SIGNAL_LED is not set */
+/* PKG_USING_LEDBLINK is not set */
+/* PKG_USING_WM_LIBRARIES is not set */
+/* PKG_USING_KENDRYTE_SDK is not set */
+/* PKG_USING_INFRARED is not set */
+/* PKG_USING_ROSSERIAL is not set */
+/* PKG_USING_AT24CXX is not set */
+/* PKG_USING_MOTIONDRIVER2RTT is not set */
+/* PKG_USING_AD7746 is not set */
+/* PKG_USING_PCA9685 is not set */
+/* PKG_USING_I2C_TOOLS is not set */
+/* PKG_USING_NRF24L01 is not set */
+/* PKG_USING_TOUCH_DRIVERS is not set */
+/* PKG_USING_LCD_DRIVERS is not set */
+
+/* miscellaneous packages */
+
+/* PKG_USING_LIBCSV is not set */
+/* PKG_USING_OPTPARSE is not set */
+/* PKG_USING_FASTLZ is not set */
+/* PKG_USING_MINILZO is not set */
+/* PKG_USING_QUICKLZ is not set */
+/* PKG_USING_MULTIBUTTON is not set */
+/* PKG_USING_CANFESTIVAL is not set */
+/* PKG_USING_ZLIB is not set */
+/* PKG_USING_DSTR is not set */
+/* PKG_USING_TINYFRAME is not set */
+/* PKG_USING_KENDRYTE_DEMO is not set */
+/* PKG_USING_DIGITALCTRL is not set */
+
+/* samples: kernel and components samples */
+
+/* PKG_USING_KERNEL_SAMPLES is not set */
+/* PKG_USING_FILESYSTEM_SAMPLES is not set */
+/* PKG_USING_NETWORK_SAMPLES is not set */
+/* PKG_USING_PERIPHERAL_SAMPLES is not set */
+/* PKG_USING_HELLO is not set */
+/* PKG_USING_VI is not set */
+/* PKG_USING_NNOM is not set */
+/* PKG_USING_LIBANN is not set */
+#define BCM2836_SOC
+
+/* Hardware Drivers Config */
+
+/* BCM Peripheral Drivers */
+
+#define BSP_USING_UART
+/* RT_USING_UART0 is not set */
+#define RT_USING_UART1
+#define BSP_USING_PIN
+#define BSP_USING_SYSTIMER
+#define RT_USING_SYSTIMER1
+#define RT_USING_SYSTIMER3
+#define BSP_USING_I2C
+#define BSP_USING_I2C0
+#define BSP_USING_I2C1
+#define BSP_USING_SPI
+#define BSP_USING_SPI0_BUS
+#define BSP_USING_SPI0_DEVICE0
+#define BSP_USING_SPI0_DEVICE1
+#define BSP_USING_WDT
+#define BSP_USING_RTC
+/* BSP_USING_ALARM is not set */
+#define BSP_USING_SDIO
+#define BSP_USING_SDIO0
+#define BSP_USING_HDMI
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-32/rtconfig.py b/bsp/raspberry-pi/raspi3-32/rtconfig.py
new file mode 100644
index 0000000000..fb37e92482
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-32/rtconfig.py
@@ -0,0 +1,52 @@
+import os
+
+# toolchains options
+ARCH        ='armv8-a'
+CPU         ='cortex-a53'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/usr/bin'
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -mfloat-abi=softfp -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -march=armv8-a -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/raspberry-pi/raspi3-64/.config b/bsp/raspberry-pi/raspi3-64/.config
new file mode 100644
index 0000000000..d51c923bf9
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/.config
@@ -0,0 +1,418 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+CONFIG_RT_USING_MEMTRACE=y
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+CONFIG_RT_USING_DEVICE_OPS=y
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40002
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_CORTEX_AARCH64=y
+CONFIG_ARCH_ARM_CORTEX_A53=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_LCD_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_BCM2836_SOC=y
+# CONFIG_BSP_SUPPORT_FPU is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# BCM Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+# CONFIG_RT_USING_UART0 is not set
+CONFIG_RT_USING_UART1=y
+CONFIG_BSP_USING_PIN=y
+# CONFIG_BSP_USING_SYSTIMER is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SDIO is not set
+
+#
+# Board Peripheral Drivers
+#
+# CONFIG_BSP_USING_HDMI is not set
diff --git a/bsp/raspberry-pi/raspi3-64/.cproject b/bsp/raspberry-pi/raspi3-64/.cproject
new file mode 100644
index 0000000000..403db1205c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/.cproject
@@ -0,0 +1,150 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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+        <externalSettings />
+        <extensions>
+          <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser" />
+          <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
+          <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
+          <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
+          <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser" />
+          <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
+        </extensions>
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+        <configuration artifactName="rtthread" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
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+              <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1461589245" name="GNU ARM Cross Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1937707052" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated" />
+              </tool>
+              <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.82359725" name="GNU ARM Cross Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.601724476" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean" />
+                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.692505279" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean" />
+                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.97345172" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean" />
+                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1342893377" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean" />
+                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1533725981" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean" />
+              </tool>
+              <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.1073550295" name="GNU ARM Cross Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+                <option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.946451386" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format" useByScannerDiscovery="false" />
+              </tool>
+              <tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1302177015" name="GNU ARM Cross C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler" />
+            </toolChain>
+          </folderInfo>
+          <sourceEntries>
+            <entry excluding="driver/drv_sdio.c|rt-thread/components/cplusplus|rt-thread/components/dfs/filesystems/elmfat|rt-thread/components/dfs/filesystems/jffs2|rt-thread/components/dfs/filesystems/nfs|rt-thread/components/dfs/filesystems/ramfs|rt-thread/components/dfs/filesystems/romfs|rt-thread/components/dfs/filesystems/skeleton|rt-thread/components/dfs/filesystems/uffs|rt-thread/components/drivers/audio|rt-thread/components/drivers/can|rt-thread/components/drivers/cputime|rt-thread/components/drivers/hwcrypto|rt-thread/components/drivers/i2c/i2c-bit-ops.c|rt-thread/components/drivers/misc/adc.c|rt-thread/components/drivers/misc/rt_drv_pwm.c|rt-thread/components/drivers/mtd|rt-thread/components/drivers/pm|rt-thread/components/drivers/rtc/alarm.c|rt-thread/components/drivers/rtc/soft_rtc.c|rt-thread/components/drivers/sensors|rt-thread/components/drivers/spi/enc28j60.c|rt-thread/components/drivers/spi/qspi_core.c|rt-thread/components/drivers/spi/sfud|rt-thread/components/drivers/spi/spi_flash_sfud.c|rt-thread/components/drivers/spi/spi_msd.c|rt-thread/components/drivers/spi/spi_wifi_rw009.c|rt-thread/components/drivers/touch|rt-thread/components/drivers/usb|rt-thread/components/drivers/wlan|rt-thread/components/finsh/finsh_compiler.c|rt-thread/components/finsh/finsh_error.c|rt-thread/components/finsh/finsh_heap.c|rt-thread/components/finsh/finsh_init.c|rt-thread/components/finsh/finsh_node.c|rt-thread/components/finsh/finsh_ops.c|rt-thread/components/finsh/finsh_parser.c|rt-thread/components/finsh/finsh_token.c|rt-thread/components/finsh/finsh_var.c|rt-thread/components/finsh/finsh_vm.c|rt-thread/components/finsh/symbol.c|rt-thread/components/libc/aio|rt-thread/components/libc/compilers/armlibc|rt-thread/components/libc/compilers/common|rt-thread/components/libc/compilers/dlib|rt-thread/components/libc/compilers/minilibc|rt-thread/components/libc/libdl|rt-thread/components/libc/mmap|rt-thread/components/libc/pthreads|rt-thread/components/libc/signal|rt-thread/components/libc/termios|rt-thread/components/libc/time|rt-thread/components/lwp|rt-thread/components/net|rt-thread/components/utilities|rt-thread/components/vbus|rt-thread/components/vmm|rt-thread/examples|rt-thread/libcpu|rt-thread/src/slab.c|rt-thread/tools" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="" />
+          </sourceEntries>
+        </configuration>
+      </storageModule>
+      <storageModule moduleId="org.eclipse.cdt.core.externalSettings" />
+    </cconfiguration>
+  </storageModule>
+  <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+    <project id="qemu-vexpress-a9.ilg.gnuarmeclipse.managedbuild.cross.target.elf.860020518" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf" />
+  </storageModule>
+  <storageModule moduleId="scannerConfiguration">
+    <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="" />
+    <scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.992053063">
+      <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="" />
+    </scannerConfigBuildInfo>
+  </storageModule>
+  <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders" />
+  <storageModule moduleId="refreshScope" versionNumber="2">
+    <configuration configurationName="Debug">
+      <resource resourceType="PROJECT" workspacePath="/qemu-a9" />
+    </configuration>
+  </storageModule>
+  <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets" />
+  <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings" />
+</cproject>
diff --git a/bsp/raspberry-pi/raspi3-64/.project b/bsp/raspberry-pi/raspi3-64/.project
new file mode 100644
index 0000000000..16586966cc
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/.project
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>raspi2</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.core.rttnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources>
+    <link>
+      <name>rt-thread</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/components</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/include</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-2-PROJECT_LOC%7D/include</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/libcpu</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-2-PROJECT_LOC%7D/libcpu</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/src</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-2-PROJECT_LOC%7D/src</locationURI>
+    </link>
+  </linkedResources>
+</projectDescription>
diff --git a/bsp/raspberry-pi/raspi3-64/Kconfig b/bsp/raspberry-pi/raspi3-64/Kconfig
new file mode 100644
index 0000000000..2122b45395
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/Kconfig
@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2836_SOC
+    bool
+    select ARCH_ARM_CORTEX_A53
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_CPU_64BIT
+    default y
+
+source "driver/Kconfig"
diff --git a/bsp/raspberry-pi/raspi3-64/README.md b/bsp/raspberry-pi/raspi3-64/README.md
new file mode 100644
index 0000000000..28e00f96c0
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/README.md
@@ -0,0 +1,100 @@
+# Raspberry PI 3-64板级支持包说明
+
+## 1. 简介
+
+树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3有三个发行版本：
+
+* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz，双核VideoCore IV GPU，1GB内存，100 Base-T Ethernet
+* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM， GigaE over USB 2.0
+* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM
+
+这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+
+## 2. 编译说明
+
+### 2.1 Window上的环境搭建
+
+Windows环境下推荐使用[env工具][1]进行编译。
+
+首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
+
+将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
+
+接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py`
+
+修改路径：
+
+```
+EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
+```
+
+然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。
+
+### 2.2 Linux上的环境搭建
+
+Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
+
+直接进入`bsp\raspberry-pi\raspi3-64`，输入scons编译即可。
+
+
+## 3. 执行
+
+### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
+
+Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
+
+解开下载的镜像文件, linux下使用如下的命令
+
+```
+unzip 2018-06-27-raspbian-stretch-lite.zip
+```
+
+准备一张空SD卡，linux环境下，插入电脑并执行
+
+```
+sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
+```
+
+**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
+
+Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
+
+最后把kernel8.img放入SD boot分区，删除其它 kernel*.img。
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示(图片中的板子是pi2，GPIO引脚是一样的)：
+
+![raspi2](figures/raspi_uart.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+按上面的方法做好SD卡后，插入树莓派，通电可以在串口上看到如下所示的输出信息：
+
+```text
+ heap: 0x00020b20 - 0x00400000
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     3.1.0 build Aug 23 2019
+ 2006 - 2019 Copyright by rt-thread team
+Hello RT-Thread!
+msh >
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+[1]: https://www.rt-thread.org/page/download.html
+[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
+[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+[4]: https://etcher.io
+[5]: https://github.com/BernardXiong
diff --git a/bsp/raspberry-pi/raspi3-64/SConscript b/bsp/raspberry-pi/raspi3-64/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/raspberry-pi/raspi3-64/SConstruct b/bsp/raspberry-pi/raspi3-64/SConstruct
new file mode 100644
index 0000000000..93f349aab8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/SConstruct
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)
+
diff --git a/bsp/raspberry-pi/raspi3-64/applications/SConscript b/bsp/raspberry-pi/raspi3-64/applications/SConscript
new file mode 100644
index 0000000000..fdf93d4235
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('test/*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi3-64/applications/main.c b/bsp/raspberry-pi/raspi3-64/applications/main.c
new file mode 100644
index 0000000000..bcccbecc00
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30     bernard       the first version
+ */
+
+#include <rtthread.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hi, this is RT-Thread!!\n");
+
+    return 0;
+}
+
diff --git a/bsp/raspberry-pi/raspi3-64/applications/mnt.c b/bsp/raspberry-pi/raspi3-64/applications/mnt.c
new file mode 100644
index 0000000000..8ec394eb8c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/applications/mnt.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30     bernard       the first version
+ */
+
+#include <rtthread.h>
+
+int mnt_init(void)
+{
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi3-64/applications/test/gpio.h b/bsp/raspberry-pi/raspi3-64/applications/test/gpio.h
new file mode 100644
index 0000000000..52fa671d0f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/applications/test/gpio.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2018 bzt (bztsrc@github)
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#define MMIO_BASE       0x3F000000
+
+#define GPFSEL0         ((volatile unsigned int*)(MMIO_BASE+0x00200000))
+#define GPFSEL1         ((volatile unsigned int*)(MMIO_BASE+0x00200004))
+#define GPFSEL2         ((volatile unsigned int*)(MMIO_BASE+0x00200008))
+#define GPFSEL3         ((volatile unsigned int*)(MMIO_BASE+0x0020000C))
+#define GPFSEL4         ((volatile unsigned int*)(MMIO_BASE+0x00200010))
+#define GPFSEL5         ((volatile unsigned int*)(MMIO_BASE+0x00200014))
+#define GPSET0          ((volatile unsigned int*)(MMIO_BASE+0x0020001C))
+#define GPSET1          ((volatile unsigned int*)(MMIO_BASE+0x00200020))
+#define GPCLR0          ((volatile unsigned int*)(MMIO_BASE+0x00200028))
+#define GPLEV0          ((volatile unsigned int*)(MMIO_BASE+0x00200034))
+#define GPLEV1          ((volatile unsigned int*)(MMIO_BASE+0x00200038))
+#define GPEDS0          ((volatile unsigned int*)(MMIO_BASE+0x00200040))
+#define GPEDS1          ((volatile unsigned int*)(MMIO_BASE+0x00200044))
+#define GPHEN0          ((volatile unsigned int*)(MMIO_BASE+0x00200064))
+#define GPHEN1          ((volatile unsigned int*)(MMIO_BASE+0x00200068))
+#define GPPUD           ((volatile unsigned int*)(MMIO_BASE+0x00200094))
+#define GPPUDCLK0       ((volatile unsigned int*)(MMIO_BASE+0x00200098))
+#define GPPUDCLK1       ((volatile unsigned int*)(MMIO_BASE+0x0020009C))
diff --git a/bsp/raspberry-pi/raspi3-64/applications/test/uart.c b/bsp/raspberry-pi/raspi3-64/applications/test/uart.c
new file mode 100644
index 0000000000..b3dd4da7ea
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/applications/test/uart.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2018 bzt (bztsrc@github)
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "gpio.h"
+
+/* Auxilary mini UART registers */
+#define AUX_ENABLE      ((volatile unsigned int*)(MMIO_BASE+0x00215004))
+#define AUX_MU_IO       ((volatile unsigned int*)(MMIO_BASE+0x00215040))
+#define AUX_MU_IER      ((volatile unsigned int*)(MMIO_BASE+0x00215044))
+#define AUX_MU_IIR      ((volatile unsigned int*)(MMIO_BASE+0x00215048))
+#define AUX_MU_LCR      ((volatile unsigned int*)(MMIO_BASE+0x0021504C))
+#define AUX_MU_MCR      ((volatile unsigned int*)(MMIO_BASE+0x00215050))
+#define AUX_MU_LSR      ((volatile unsigned int*)(MMIO_BASE+0x00215054))
+#define AUX_MU_MSR      ((volatile unsigned int*)(MMIO_BASE+0x00215058))
+#define AUX_MU_SCRATCH  ((volatile unsigned int*)(MMIO_BASE+0x0021505C))
+#define AUX_MU_CNTL     ((volatile unsigned int*)(MMIO_BASE+0x00215060))
+#define AUX_MU_STAT     ((volatile unsigned int*)(MMIO_BASE+0x00215064))
+#define AUX_MU_BAUD     ((volatile unsigned int*)(MMIO_BASE+0x00215068))
+
+/**
+ * Set baud rate and characteristics (115200 8N1) and map to GPIO
+ */
+void uart_init()
+{
+    register unsigned int r;
+
+    /* initialize UART */
+    *AUX_ENABLE |=1;       // enable UART1, AUX mini uart
+    *AUX_MU_CNTL = 0;
+    *AUX_MU_LCR = 3;       // 8 bits
+    *AUX_MU_MCR = 0;
+    *AUX_MU_IER = 0;
+    *AUX_MU_IIR = 0xc6;    // disable interrupts
+    *AUX_MU_BAUD = 270;    // 115200 baud
+    /* map UART1 to GPIO pins */
+    r=*GPFSEL1;
+    r&=~((7<<12)|(7<<15)); // gpio14, gpio15
+    r|=(2<<12)|(2<<15);    // alt5
+    *GPFSEL1 = r;
+    *GPPUD = 0;            // enable pins 14 and 15
+    r=150; while(r--) { asm volatile("nop"); }
+    *GPPUDCLK0 = (1<<14)|(1<<15);
+    r=150; while(r--) { asm volatile("nop"); }
+    *GPPUDCLK0 = 0;        // flush GPIO setup
+    *AUX_MU_CNTL = 3;      // enable Tx, Rx
+}
+
+/**
+ * Send a character
+ */
+void uart_send(unsigned int c) {
+    /* wait until we can send */
+    do{asm volatile("nop");}while(!(*AUX_MU_LSR&0x20));
+    /* write the character to the buffer */
+    *AUX_MU_IO=c;
+}
+
+/**
+ * Receive a character
+ */
+char uart_getc() {
+    char r;
+    /* wait until something is in the buffer */
+    do{asm volatile("nop");}while(!(*AUX_MU_LSR&0x01));
+    /* read it and return */
+    r=(char)(*AUX_MU_IO);
+    /* convert carrige return to newline */
+    return r=='\r'?'\n':r;
+}
+
+/**
+ * Display a string
+ */
+void uart_puts(char *s) {
+    while(*s) {
+        /* convert newline to carrige return + newline */
+        if(*s=='\n')
+            uart_send('\r');
+        uart_send(*s++);
+    }
+}
diff --git a/bsp/raspberry-pi/raspi3-64/applications/test/uart.h b/bsp/raspberry-pi/raspi3-64/applications/test/uart.h
new file mode 100644
index 0000000000..72f8e3151f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/applications/test/uart.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2018 bzt (bztsrc@github)
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+void uart_init();
+void uart_send(unsigned int c);
+char uart_getc();
+void uart_puts(char *s);
diff --git a/bsp/raspberry-pi/raspi3-64/driver/Kconfig b/bsp/raspberry-pi/raspi3-64/driver/Kconfig
new file mode 100644
index 0000000000..2deffef99c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/Kconfig
@@ -0,0 +1,112 @@
+
+config BSP_SUPPORT_FPU
+    bool "Using Float"
+    default n
+
+menu "Hardware Drivers Config"
+    menu "BCM Peripheral Drivers"
+        menuconfig BSP_USING_UART
+            bool "Using UART"
+            select RT_USING_SERIAL
+            default y
+
+            if BSP_USING_UART
+                config RT_USING_UART0
+                bool "Enabel UART 0"
+                default y
+
+                config RT_USING_UART1
+                    bool "Enabel UART 1"
+                    default n
+            endif
+         
+        config BSP_USING_PIN
+            bool "Using PIN"
+            select RT_USING_PIN
+            default y
+
+        menuconfig BSP_USING_SYSTIMER
+            bool "Enable SYSTIMER"
+            select BSP_USING_SYSTIMER
+            default n
+
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
+        endif
+
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C"
+            select RT_USING_I2C
+            default n
+
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                default n
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+        endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI"
+            select RT_USING_SPI
+            default n
+        
+        if BSP_USING_SPI
+            config BSP_USING_SPI0
+                bool "Enable SPI0"
+                default n
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                default n
+        endif
+
+        config BSP_USING_WDT
+            bool "Enable WDT"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+
+        if BSP_USING_RTC
+            config BSP_USING_ALARM
+                bool "Enable Alarm"
+                select RT_USING_ALARM
+                default n
+        endif
+        
+        menuconfig BSP_USING_SDIO
+            bool "Enable SDIO"
+            select RT_USING_SDIO
+            default n
+
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO0
+                bool "Enable SDIO0"
+                select RT_USING_SDIO
+                default n
+        endif
+    endmenu
+
+    menu "Board Peripheral Drivers"
+        menuconfig BSP_USING_HDMI
+            bool "Enable HDMI"
+            select BSP_USING_SPI
+            default n
+
+        if BSP_USING_HDMI
+            config BSP_USING_HDMI_DISPLAY
+                bool "HDMI DISPLAY"
+                default n
+        endif
+    endmenu
+endmenu
diff --git a/bsp/raspberry-pi/raspi3-64/driver/SConscript b/bsp/raspberry-pi/raspi3-64/driver/SConscript
new file mode 100644
index 0000000000..2c19b9436d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/SConscript
@@ -0,0 +1,32 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Split('''
+board.c
+bcm283x.c
+drv_uart.c
+mbox.c
+''')
+CPPPATH = [cwd]
+
+if GetDepend('BSP_USING_SYSTIMER'):
+    src += ['drv_timer.c']
+if GetDepend('BSP_USING_PIN'):
+    src += ['drv_gpio.c']
+if GetDepend('BSP_USING_I2C'):
+    src += ['drv_i2c.c']
+if GetDepend('BSP_USING_WDT'):
+    src += ['drv_wdt.c']
+if GetDepend('BSP_USING_SPI'):
+    src += ['drv_spi.c']
+if GetDepend('BSP_USING_SDIO'):
+    src += ['drv_sdio.c']
+if GetDepend('BSP_USING_RTC'):
+    src += ['drv_rtc.c']
+if GetDepend('BSP_USING_HDMI'):
+    src += ['drv_fb.c']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
new file mode 100644
index 0000000000..ea92c33a0f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
@@ -0,0 +1,575 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "bcm283x.h"
+
+rt_uint32_t bcm283x_peri_read(volatile rt_ubase_t addr)
+{
+    rt_uint32_t ret;
+    __sync_synchronize();
+    ret = HWREG32(addr);
+    __sync_synchronize();
+    return ret;
+}
+
+rt_uint32_t bcm283x_peri_read_nb(volatile rt_ubase_t addr)
+{
+    return HWREG32(addr);
+}
+
+void bcm283x_peri_write(volatile rt_ubase_t addr, rt_uint32_t value)
+{
+    __sync_synchronize();
+    HWREG32(addr) = value;
+    __sync_synchronize();
+}
+
+void bcm283x_peri_write_nb(volatile rt_ubase_t addr, rt_uint32_t value)
+{
+    HWREG32(addr) = value;
+}
+
+void bcm283x_peri_set_bits(volatile rt_ubase_t addr, rt_uint32_t value, rt_uint32_t mask)
+{
+    rt_uint32_t v = bcm283x_peri_read(addr);
+    v = (v & ~mask) | (value & mask);
+    bcm283x_peri_write(addr, v);
+}
+
+void bcm283x_gpio_fsel(rt_uint8_t pin, rt_uint8_t mode)
+{
+    volatile rt_ubase_t addr = (BCM283X_GPIO_BASE + BCM283X_GPIO_GPFSEL0 + (pin / 10) * 4);
+    rt_uint8_t   shift = (pin % 10) * 3;
+    rt_uint32_t  mask = BCM283X_GPIO_FSEL_MASK << shift;
+    rt_uint32_t  value = mode << shift;
+
+    bcm283x_peri_set_bits(addr, value, mask);
+}
+
+void bcm283x_gpio_set(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPSET0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    bcm283x_peri_write(addr, 1 << shift);
+}
+
+void bcm283x_gpio_clr(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPCLR0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    bcm283x_peri_write(addr, 1 << shift);
+}
+
+rt_uint8_t bcm283x_gpio_lev(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM2835_GPIO_GPLEV0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = bcm283x_peri_read(addr);
+    return (value & (1 << shift)) ? HIGH : LOW;
+}
+
+rt_uint8_t bcm283x_gpio_eds(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = bcm283x_peri_read(addr);
+    return (value & (1 << shift)) ? HIGH : LOW;
+}
+
+/* Write a 1 to clear the bit in EDS */
+void bcm283x_gpio_set_eds(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_write(addr, value);
+}
+
+/* Rising edge detect enable */
+void bcm283x_gpio_ren(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPREN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, value, value);
+}
+
+void bcm283x_gpio_clr_ren(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPREN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, 0, value);
+}
+
+/* Falling edge detect enable */
+void bcm283x_gpio_fen(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPFEN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, value, value);
+}
+void bcm283x_gpio_clr_fen(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPFEN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, 0, value);
+}
+
+/* High detect enable */
+void bcm283x_gpio_hen(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, value, value);
+}
+
+void bcm283x_gpio_clr_hen(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, 0, value);
+}
+
+/* Low detect enable */
+void bcm283x_gpio_len(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPLEN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, value, value);
+}
+
+void bcm283x_gpio_clr_len(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPLEN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, 0, value);
+}
+
+/* Async rising edge detect enable */
+void bcm283x_gpio_aren(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAREN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, value, value);
+}
+void bcm283x_gpio_clr_aren(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAREN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, 0, value);
+}
+
+/* Async falling edge detect enable */
+void bcm283x_gpio_afen(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAFEN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, value, value);
+}
+void bcm283x_gpio_clr_afen(rt_uint8_t pin)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAFEN0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t value = 1 << shift;
+    bcm283x_peri_set_bits(addr, 0, value);
+}
+
+/* Set pullup/down */
+void bcm283x_gpio_pud(rt_uint8_t pud)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPPUD;
+    bcm283x_peri_write(addr, pud);
+}
+
+/* Pullup/down clock
+// Clocks the value of pud into the GPIO pin
+*/
+void bcm283x_gpio_pudclk(rt_uint8_t pin, rt_uint8_t on)
+{
+    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPPUDCLK0 + (pin / 32) * 4;
+    rt_uint8_t shift = pin % 32;
+    bcm283x_peri_write(addr, (on? 1 : 0) << shift);
+}
+
+void bcm283x_gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud)
+{
+    bcm283x_gpio_pud(pud);
+    bcm283x_clo_delayMicros(10);
+
+    bcm283x_gpio_pudclk(pin, 1);
+    bcm283x_clo_delayMicros(10);
+
+    bcm283x_gpio_pud(BCM283X_GPIO_PUD_OFF);
+    bcm283x_gpio_pudclk(pin, 0);
+}
+
+
+void bcm283x_gpio_write(rt_uint8_t pin, rt_uint8_t val)
+{
+    if (val)
+        bcm283x_gpio_set(pin);
+    else
+        bcm283x_gpio_clr(pin);
+}
+
+rt_uint64_t bcm283x_st_read(void)
+{
+    volatile rt_ubase_t addr;
+    rt_uint32_t hi, lo;
+    rt_uint64_t st;
+
+    addr = BCM283X_ST_BASE + BCM283X_ST_CHI;
+    hi = bcm283x_peri_read(addr);
+
+    addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
+    lo = bcm283x_peri_read(addr);
+
+    addr = BCM283X_ST_BASE + BCM283X_ST_CHI;
+    st = bcm283x_peri_read(addr);
+
+    /* Test for overflow */
+    if (st == hi)
+    {
+        rt_kprintf(">> 1crash???\n");
+        st <<= 32;
+        st += lo;
+        rt_kprintf(">> 2crash!!!\n");
+    }
+    else
+    {
+        st <<= 32;
+        addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
+        st += bcm283x_peri_read(addr);
+    }
+    return st;
+}
+
+/* microseconds */
+void bcm283x_delayMicroseconds(rt_uint64_t micros)
+{
+    rt_uint64_t start;
+
+    start =  bcm283x_st_read();
+    rt_kprintf("bcm283x_st_read result: %d\n", start);
+
+    /* Not allowed to access timer registers (result is not as precise)*/
+    if (start==0)
+        return;
+
+    bcm283x_st_delay(start, micros);
+}
+
+void bcm283x_clo_delayMicros(rt_uint32_t micros)
+{
+    volatile rt_uint32_t addr;
+    rt_uint32_t compare;
+
+    addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
+    compare = bcm283x_peri_read(addr) + micros;
+    while(bcm283x_peri_read(addr) < compare);
+}
+
+void bcm283x_st_delay(rt_uint64_t offset_micros, rt_uint64_t micros)
+{
+    rt_uint64_t compare = offset_micros + micros;
+    while(bcm283x_st_read() < compare);
+}
+
+
+/* Read an number of bytes from I2C */
+rt_uint8_t bcm283x_i2c_read(rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len)
+{
+    volatile rt_uint32_t  dlen    = base + BCM283X_BSC_DLEN;
+    volatile rt_uint32_t  fifo    = base + BCM283X_BSC_FIFO;
+    volatile rt_uint32_t  status  = base + BCM283X_BSC_S;
+    volatile rt_uint32_t  control = base + BCM283X_BSC_C;
+
+    rt_uint32_t remaining = len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
+    /* Clear Status */
+    bcm283x_peri_write_nb(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
+    /* Set Data Length */
+    bcm283x_peri_write_nb(dlen, len);
+    /* Start read */
+    bcm283x_peri_write_nb(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST | BCM283X_BSC_C_READ);
+
+    /* wait for transfer to complete */
+    while (!(bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE))
+    {
+        /* we must empty the FIFO as it is populated and not use any delay */
+        while (remaining && bcm283x_peri_read_nb(status) & BCM283X_BSC_S_RXD)
+        {
+            /* Read from FIFO, no barrier */
+            buf[i] = bcm283x_peri_read_nb(fifo);
+            i++;
+            remaining--;
+        }
+    }
+
+    /* transfer has finished - grab any remaining stuff in FIFO */
+    while (remaining && (bcm283x_peri_read_nb(status) & BCM283X_BSC_S_RXD))
+    {
+        /* Read from FIFO, no barrier */
+        buf[i] = bcm283x_peri_read_nb(fifo);
+        i++;
+        remaining--;
+    }
+
+    /* Received a NACK */
+    if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+
+    /* Received Clock Stretch Timeout */
+    else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+
+    /* Not all data is received */
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+
+    bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
+
+    return reason;
+}
+
+int bcm283x_i2c_begin(int no)
+{
+    if (0 == no)
+    {
+        bcm283x_gpio_fsel(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_ALT0); /* SDA */
+        bcm283x_gpio_fsel(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_ALT0); /* SCL */
+    }
+    else
+    {
+        bcm283x_gpio_fsel(BCM_GPIO_PIN_2, BCM283X_GPIO_FSEL_ALT0); /* SDA */
+        bcm283x_gpio_fsel(BCM_GPIO_PIN_3, BCM283X_GPIO_FSEL_ALT0); /* SCL */
+    }
+    return 0;
+}
+
+void bcm283x_i2c_end(int no)
+{
+    if (0 == no)
+    {
+        bcm283x_gpio_fsel(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_INPT); /* SDA */
+        bcm283x_gpio_fsel(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_INPT); /* SCL */
+    }
+    else
+    {
+        bcm283x_gpio_fsel(BCM_GPIO_PIN_2, BCM283X_GPIO_FSEL_INPT); /* SDA */
+        bcm283x_gpio_fsel(BCM_GPIO_PIN_3, BCM283X_GPIO_FSEL_INPT); /* SCL */
+    }
+}
+
+void bcm283x_i2c_setSlaveAddress(int no, rt_uint8_t saddr)
+{
+    volatile rt_uint32_t addr;
+    if (0 == no)
+        addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_A;
+    else
+        addr = PER_BASE + BCM283X_BSC1_BASE + BCM283X_BSC_A;
+
+    bcm283x_peri_write(addr, saddr);
+}
+
+void bcm283x_i2c_setClockDivider(int no, rt_uint16_t divider)
+{
+    volatile rt_uint32_t addr;
+    if (0 == no)
+        addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DIV;
+    else
+        addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DIV;
+    bcm283x_peri_write(addr, divider);
+}
+
+void bcm283x_i2c_set_baudrate(int no, rt_uint32_t baudrate)
+{
+    rt_uint32_t divider;
+    divider = (BCM283X_CORE_CLK_HZ / baudrate) & 0xFFFE;
+    bcm283x_i2c_setClockDivider(no, (rt_uint16_t)divider);
+}
+
+/* Writes an number of bytes to I2C */
+rt_uint8_t bcm283x_i2c_write(rt_uint32_t base, const rt_uint8_t * buf, rt_uint32_t len)
+{
+    volatile rt_uint32_t dlen    = base + BCM283X_BSC_DLEN;
+    volatile rt_uint32_t fifo    = base + BCM283X_BSC_FIFO;
+    volatile rt_uint32_t status  = base + BCM283X_BSC_S;
+    volatile rt_uint32_t control = base + BCM283X_BSC_C;
+
+    rt_uint32_t remaining = len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
+    /* Clear Status */
+    bcm283x_peri_write(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
+    /* Set Data Length */
+    bcm283x_peri_write(dlen, len);
+    /* pre populate FIFO with max buffer */
+    while(remaining && (i < BCM283X_BSC_FIFO_SIZE))
+    {
+        bcm283x_peri_write_nb(fifo, buf[i]);
+        i++;
+        remaining--;
+    }
+
+    /* Enable device and start transfer */
+    bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST);
+
+    /* Transfer is over when BCM2835_BSC_S_DONE */
+    while(!(bcm283x_peri_read(status) & BCM283X_BSC_S_DONE))
+    {
+        while (remaining && (bcm283x_peri_read(status) & BCM283X_BSC_S_TXD))
+        {
+        /* Write to FIFO */
+            bcm283x_peri_write(fifo, buf[i]);
+            i++;
+            remaining--;
+        }
+    }
+
+    /* Received a NACK */
+    if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+
+    /* Received Clock Stretch Timeout */
+    else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+
+    /* Not all data is sent */
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+
+    bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
+
+    return reason;
+}
+
+rt_uint8_t bcm283x_i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len)
+{
+    volatile rt_uint32_t dlen    = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DLEN;
+    volatile rt_uint32_t fifo    = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_FIFO;
+    volatile rt_uint32_t status  = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_S;
+    volatile rt_uint32_t control = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_C;
+
+    rt_uint32_t remaining = cmds_len;
+    rt_uint32_t i = 0;
+    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
+
+    /* Clear FIFO */
+    bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
+
+    /* Clear Status */
+    bcm283x_peri_write(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
+
+    /* Set Data Length */
+    bcm283x_peri_write(dlen, cmds_len);
+
+    /* pre populate FIFO with max buffer */
+    while(remaining && (i < BCM283X_BSC_FIFO_SIZE))
+    {
+        bcm283x_peri_write_nb(fifo, cmds[i]);
+        i++;
+        remaining--;
+    }
+
+    /* Enable device and start transfer */
+    bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST);
+
+    /* poll for transfer has started (way to do repeated start, from BCM2835 datasheet) */
+    while (!(bcm283x_peri_read(status) & BCM283X_BSC_S_TA))
+    {
+        /* Linux may cause us to miss entire transfer stage */
+        if (bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE)
+            break;
+    }
+
+    remaining = buf_len;
+    i = 0;
+
+    /* Send a repeated start with read bit set in address */
+    bcm283x_peri_write(dlen, buf_len);
+    bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST  | BCM283X_BSC_C_READ);
+
+    /* Wait for write to complete and first byte back. */
+    bcm283x_clo_delayMicros(100);
+
+    /* wait for transfer to complete */
+    while (!(bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE))
+    {
+        /* we must empty the FIFO as it is populated and not use any delay */
+        while (remaining && bcm283x_peri_read(status) & BCM283X_BSC_S_RXD)
+        {
+            /* Read from FIFO, no barrier */
+            buf[i] = bcm283x_peri_read_nb(fifo);
+            i++;
+            remaining--;
+        }
+    }
+
+    /* transfer has finished - grab any remaining stuff in FIFO */
+    while (remaining && (bcm283x_peri_read(status) & BCM283X_BSC_S_RXD))
+    {
+        /* Read from FIFO */
+        buf[i] = bcm283x_peri_read(fifo);
+        i++;
+        remaining--;
+    }
+
+    /* Received a NACK */
+    if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_NACK;
+    }
+
+    /* Received Clock Stretch Timeout */
+    else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_CLKT;
+    }
+
+    /* Not all data is sent */
+    else if (remaining)
+    {
+        reason = BCM283X_I2C_REASON_ERROR_DATA;
+    }
+
+    bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
+
+    return reason;
+}
diff --git a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
new file mode 100644
index 0000000000..fc9ed1feab
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
@@ -0,0 +1,641 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-15     RT-Thread    the first version
+ * 2019-07-29     zdzn         add macro definition
+ */
+
+#ifndef __BCM283X_H__
+#define __BCM283X_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#define PER_BASE    		(0x3F000000)
+#define PER_BASE_40000000 	(0x40000000)
+
+
+#define HIGH 0x1
+#define LOW  0x0
+
+#define BCM283X_CORE_CLK_HZ		250000000	/* 50 MHz */
+
+/*! Offsets for the bases of various peripherals within the peripherals block
+ *   Base Address of the System Timer registers
+ */
+/*! Base Address of the Pads registers */
+#define BCM283X_GPIO_PADS               0x100000
+/*! Base Address of the Clock/timer registers */
+#define BCM283X_CLOCK_BASE              0x101000
+/*! Base Address of the GPIO registers */
+//#define BCM283X_GPIO_BASE               0x200000
+/*! Base Address of the SPI0 registers */
+#define BCM283X_SPI0_BASE               0x204000
+/*! Base Address of the PWM registers */
+#define BCM283X_GPIO_PWM                0x20C000
+/*! Base Address of the AUX registers */
+#define BCM283X_AUX_BASE				0x215000
+/*! Base Address of the AUX_SPI1 registers */
+#define BCM283X_SPI1_BASE				0x215080
+/*! Base Address of the AUX_SPI2 registers */
+#define BCM283X_SPI2_BASE				0x2150C0
+
+/*! Base Address of the BSC0 registers */
+#define BCM283X_BSC0_BASE 				0x205000    //for i2c0
+/*! Base Address of the BSC1 registers */
+#define BCM283X_BSC1_BASE				0x804000    //for i2c1
+/*! Base Address of the BSC1 registers */
+#define BCM283X_BSC2_BASE				0x805000    //for hdmi i2c not use 
+
+/*
+ *  GPIO
+ */
+#define GPIO_BASE       (PER_BASE + 0x200000)
+#define GPIO_GPFSEL0    HWREG32(GPIO_BASE + 0x0000)  /* GPIO Function Select 0 32bit R/W */
+#define GPIO_GPFSEL1    HWREG32(GPIO_BASE + 0x0004)  /* GPIO Function Select 1 32bit R/W */
+#define GPIO_GPFSEL2    HWREG32(GPIO_BASE + 0x0008)  /* GPIO Function Select 2 32bit R/W */
+#define GPIO_GPFSEL4    HWREG32(GPIO_BASE + 0x0010)  /* GPIO Function Select 4 32bit R/W */
+#define GPIO_GPFSEL5    HWREG32(GPIO_BASE + 0x0014)  /* GPIO Function Select 5 32bit R/W */
+#define GPIO_GPSET0     HWREG32(GPIO_BASE + 0x001C)
+#define GPIO_GPSET1     HWREG32(GPIO_BASE + 0x0020)
+#define GPIO_GPCLR0     HWREG32(GPIO_BASE + 0x0028)
+#define GPIO_GPCLR1     HWREG32(GPIO_BASE + 0x002C)
+#define GPIO_GPEDS0     HWREG32(GPIO_BASE + 0x0040)  /* GPIO Pin Event Detect Status */
+#define GPIO_GPEDS1     HWREG32(GPIO_BASE + 0x0044)
+#define GPIO_GPREN0     HWREG32(GPIO_BASE + 0x004c)  /* GPIO Pin Rising Edge Detect Enable */
+#define GPIO_GPREN1     HWREG32(GPIO_BASE + 0x0050)
+#define GPIO_GPFEN0     HWREG32(GPIO_BASE + 0x0058) /* GPIO Pin Falling Edge Detect Enable */
+#define GPIO_GPFEN1     HWREG32(GPIO_BASE + 0x005C) 
+#define GPIO_GPHEN0     HWREG32(GPIO_BASE + 0x0064) /* GPIO Pin High Detect Enable  */
+#define GPIO_GPHEN1     HWREG32(GPIO_BASE + 0x0068)
+#define GPIO_GPLEN0     HWREG32(GPIO_BASE + 0x0070) /* GPIO Pin Low Detect Enable 0 */
+#define GPIO_GPLEN1     HWREG32(GPIO_BASE + 0x0074)
+#define GPIO_GPAREN0    HWREG32(GPIO_BASE + 0x007C) /* GPIO Pin Async. Rising Edge Detect */
+#define GPIO_GPAREN1    HWREG32(GPIO_BASE + 0x0080)
+#define GPIO_GPAFEN0    HWREG32(GPIO_BASE + 0x0088) /* GPIO Pin Async. Falling Edge Detect */
+#define GPIO_GPAFEN1    HWREG32(GPIO_BASE + 0x008C)
+#define GPIO_GPPUD      HWREG32(GPIO_BASE + 0x0094)  /* GPIO Pin Pull-up/down Enable */
+#define GPIO_GPPUDCLK0  HWREG32(GPIO_BASE + 0x0098)  /* GPIO Pin Pull-up/down Enable Clock 0 */
+#define GPIO_GPPUDCLK1  HWREG32(GPIO_BASE + 0x009C)  /* GPIO Pin Pull-up/down Enable Clock 1 */
+
+#define BCM283X_GPIO_BASE       (PER_BASE + 0x200000)
+#define BCM283X_GPIO_GPFSEL0    (0x0000)  /* GPIO Function Select 0 32bit R/W */
+#define BCM283X_GPIO_GPFSEL1    (0x0004)  /* GPIO Function Select 1 32bit R/W */
+#define BCM283X_GPIO_GPFSEL2    (0x0008)  /* GPIO Function Select 2 32bit R/W */
+#define BCM283X_GPIO_GPFSEL4    (0x0010)  /* GPIO Function Select 4 32bit R/W */
+#define BCM283X_GPIO_GPFSEL5    (0x0014)  /* GPIO Function Select 5 32bit R/W */
+#define BCM283X_GPIO_GPSET0     (0x001C)
+#define BCM283X_GPIO_GPSET1     (0x0020)
+#define BCM283X_GPIO_GPCLR0     (0x0028)
+#define BCM283X_GPIO_GPCLR1     (0x002C)
+#define BCM2835_GPIO_GPLEV0     (0x0034)  /*!< GPIO Pin Level 0 */
+#define BCM2835_GPIO_GPLEV1     (0x0038)  /*!< GPIO Pin Level 1 */
+#define BCM283X_GPIO_GPEDS0     (0x0040)  /* GPIO Pin Event Detect Status */
+#define BCM283X_GPIO_GPEDS1     (0x0044)
+#define BCM283X_GPIO_GPREN0     (0x004c)  /* GPIO Pin Rising Edge Detect Enable */
+#define BCM283X_GPIO_GPREN1     (0x0050)
+#define BCM283X_GPIO_GPFEN0     (0x0058) /* GPIO Pin Falling Edge Detect Enable */
+#define BCM283X_GPIO_GPFEN1     (0x005C)
+#define BCM283X_GPIO_GPHEN0     (0x0064) /* GPIO Pin High Detect Enable  */
+#define BCM283X_GPIO_GPHEN1     (0x0068)
+#define BCM283X_GPIO_GPLEN0     (0x0070) /* GPIO Pin Low Detect Enable 0 */
+#define BCM283X_GPIO_GPLEN1     (0x0074)
+#define BCM283X_GPIO_GPAREN0    (0x007C) /* GPIO Pin Async. Rising Edge Detect */
+#define BCM283X_GPIO_GPAREN1    (0x0080)
+#define BCM283X_GPIO_GPAFEN0    (0x0088) /* GPIO Pin Async. Falling Edge Detect */
+#define BCM283X_GPIO_GPAFEN1    (0x008C)
+#define BCM283X_GPIO_GPPUD      (0x0094)  /* GPIO Pin Pull-up/down Enable */
+#define BCM283X_GPIO_GPPUDCLK0  (0x0098)  /* GPIO Pin Pull-up/down Enable Clock 0 */
+#define BCM283X_GPIO_GPPUDCLK1  (0x009C)  /* GPIO Pin Pull-up/down Enable Clock 1 */
+
+enum gpio_function_select
+{
+    BCM283X_GPIO_FSEL_INPT  = 0x00,   /*!< Input 0b000 */
+    BCM283X_GPIO_FSEL_OUTP  = 0x01,   /*!< Output 0b001 */
+    BCM283X_GPIO_FSEL_ALT0  = 0x04,   /*!< Alternate function 0 0b100 */
+    BCM283X_GPIO_FSEL_ALT1  = 0x05,   /*!< Alternate function 1 0b101 */
+    BCM283X_GPIO_FSEL_ALT2  = 0x06,   /*!< Alternate function 2 0b110, */
+    BCM283X_GPIO_FSEL_ALT3  = 0x07,   /*!< Alternate function 3 0b111 */
+    BCM283X_GPIO_FSEL_ALT4  = 0x03,   /*!< Alternate function 4 0b011 */
+    BCM283X_GPIO_FSEL_ALT5  = 0x02,   /*!< Alternate function 5 0b010 */
+    BCM283X_GPIO_FSEL_MASK  = 0x07    /*!< Function select bits mask 0b111 */
+};
+
+enum gpio_pud_mode
+{
+    BCM283X_GPIO_PUD_OFF     = 0x00,   /*!< Off ? disable pull-up/down 0b00 */
+    BCM283X_GPIO_PUD_DOWN    = 0x01,   /*!< Enable Pull Down control 0b01 */
+    BCM283X_GPIO_PUD_UP      = 0x02    /*!< Enable Pull Up control 0b10  */
+};
+
+/* Defines for BSC I2C
+ * GPIO register offsets from BCM283X_BSC*_BASE.
+ * Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map
+ */
+/* I2C Address Map offset address */
+#define BCM283X_BSC_C 			0x0000 /*!< BSC Master Control */
+#define BCM283X_BSC_S 			0x0004 /*!< BSC Master Status */
+#define BCM283X_BSC_DLEN		0x0008 /*!< BSC Master Data Length */
+#define BCM283X_BSC_A 			0x000c /*!< BSC Master Slave Address */
+#define BCM283X_BSC_FIFO		0x0010 /*!< BSC Master Data FIFO */
+#define BCM283X_BSC_DIV			0x0014 /*!< BSC Master Clock Divider */
+#define BCM283X_BSC_DEL			0x0018 /*!< BSC Master Data Delay */
+#define BCM283X_BSC_CLKT		0x001c /*!< BSC Master Clock Stretch Timeout */
+
+/* Register masks for C Register */
+#define BCM283X_BSC_C_I2CEN 		0x00008000 /*!< I2C Enable, 0 = disabled, 1 = enabled */
+#define BCM283X_BSC_C_INTR 		0x00000400 /*!< Interrupt on RX */
+#define BCM283X_BSC_C_INTT 		0x00000200 /*!< Interrupt on TX */
+#define BCM283X_BSC_C_INTD 		0x00000100 /*!< Interrupt on DONE */
+#define BCM283X_BSC_C_ST 		0x00000080 /*!< Start transfer, 1 = Start a new transfer */
+#define BCM283X_BSC_C_CLEAR_1 		0x00000020 /*!< Clear FIFO Clear */
+#define BCM283X_BSC_C_CLEAR_2 		0x00000010 /*!< Clear FIFO Clear */
+#define BCM283X_BSC_C_READ 		0x00000001 /*!<	Read transfer */
+
+/* Register masks for S Register */
+#define BCM283X_BSC_S_CLKT 		0x00000200 /*!< Clock stretch timeout */
+#define BCM283X_BSC_S_ERR 		0x00000100 /*!< ACK error */
+#define BCM283X_BSC_S_RXF 		0x00000080 /*!< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
+#define BCM283X_BSC_S_TXE 		0x00000040 /*!< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
+#define BCM283X_BSC_S_RXD 		0x00000020 /*!< RXD FIFO contains data */
+#define BCM283X_BSC_S_TXD 		0x00000010 /*!< TXD FIFO can accept data */
+#define BCM283X_BSC_S_RXR 		0x00000008 /*!< RXR FIFO needs reading (full) */
+#define BCM283X_BSC_S_TXW 		0x00000004 /*!< TXW FIFO needs writing (full) */
+#define BCM283X_BSC_S_DONE 		0x00000002 /*!< Transfer DONE */
+#define BCM283X_BSC_S_TA 		0x00000001 /*!< Transfer Active */
+
+#define BCM283X_BSC_FIFO_SIZE   	16  /*!< BSC FIFO size */
+
+enum  i2c_clock_divider
+{
+    BCM283X_I2C_CLOCK_DIVIDER_2500   = 2500,      /*!< 2500 = 10us = 100 kHz */
+    BCM283X_I2C_CLOCK_DIVIDER_626    = 626,       /*!< 622 = 2.504us = 399.3610 kHz */
+    BCM283X_I2C_CLOCK_DIVIDER_150    = 150,       /*!< 150 = 60ns = 1.666 MHz (default at reset) */
+    BCM283X_I2C_CLOCK_DIVIDER_148    = 148        /*!< 148 = 59ns = 1.689 MHz */
+};
+
+enum i2c_reason_codes
+{
+    BCM283X_I2C_REASON_OK   	     = 0x00,      /*!< Success */
+    BCM283X_I2C_REASON_ERROR_NACK    = 0x01,      /*!< Received a NACK */
+    BCM283X_I2C_REASON_ERROR_CLKT    = 0x02,      /*!< Received Clock Stretch Timeout */
+    BCM283X_I2C_REASON_ERROR_DATA    = 0x04       /*!< Not all data is sent / received */
+};
+
+/*
+ *  Interrupt Controler
+ */
+#define IRQ_BASE            (PER_BASE + 0xB200)
+#define IRQ_PEND_BASIC      HWREG32(IRQ_BASE + 0x00)
+#define IRQ_PEND1           HWREG32(IRQ_BASE + 0x04)
+#define IRQ_PEND2           HWREG32(IRQ_BASE + 0x08)
+#define IRQ_FIQ_CONTROL     HWREG32(IRQ_BASE + 0x0C)
+#define IRQ_ENABLE1         HWREG32(IRQ_BASE + 0x10)
+#define IRQ_ENABLE2         HWREG32(IRQ_BASE + 0x14)
+#define IRQ_ENABLE_BASIC    HWREG32(IRQ_BASE + 0x18)
+#define IRQ_DISABLE1        HWREG32(IRQ_BASE + 0x1C)
+#define IRQ_DISABLE2        HWREG32(IRQ_BASE + 0x20)
+#define IRQ_DISABLE_BASIC   HWREG32(IRQ_BASE + 0x24)
+
+/*
+ *  System Timer
+ */
+#define STIMER_BASE         (PER_BASE  + 0x3000)
+#define STIMER_CS           HWREG32(STIMER_BASE + 0x00)
+#define STIMER_CLO          HWREG32(STIMER_BASE + 0x04)
+#define STIMER_CHI          HWREG32(STIMER_BASE + 0x08)
+#define STIMER_C0           HWREG32(STIMER_BASE + 0x0C)
+#define STIMER_C1           HWREG32(STIMER_BASE + 0x10)
+#define STIMER_C2           HWREG32(STIMER_BASE + 0x14)
+#define STIMER_C3           HWREG32(STIMER_BASE + 0x18)
+
+/* Defines for ST */
+#define BCM283X_ST_BASE 		(PER_BASE  + 0x3000)
+#define BCM283X_ST_CS 			0x0000 /*!< System Timer Control/Status */
+#define BCM283X_ST_CLO 			0x0004 /*!< System Timer Counter Lower 32 bits */
+#define BCM283X_ST_CHI 			0x0008 /*!< System Timer Counter Upper 32 bits */
+#define BCM283X_ST_C0 			0x000C
+#define BCM283X_ST_C1 			0x0010
+#define BCM283X_ST_C2 			0x0014
+#define BCM283X_ST_C3 			0x0018
+
+/*
+ * ARM Timer
+ */
+#define ARM_TIMER_BASE		(PER_BASE + 0xB000)
+#define ARM_TIMER_LOAD		HWREG32(ARM_TIMER_BASE + 0x400)
+#define ARM_TIMER_VALUE		HWREG32(ARM_TIMER_BASE + 0x404)
+#define ARM_TIMER_CTRL		HWREG32(ARM_TIMER_BASE + 0x408)
+#define ARM_TIMER_IRQCLR	HWREG32(ARM_TIMER_BASE + 0x40C)
+#define ARM_TIMER_RAWIRQ	HWREG32(ARM_TIMER_BASE + 0x410)
+#define ARM_TIMER_MASKIRQ	HWREG32(ARM_TIMER_BASE + 0x414)
+#define ARM_TIMER_RELOAD	HWREG32(ARM_TIMER_BASE + 0x418)
+#define ARM_TIMER_PREDIV	HWREG32(ARM_TIMER_BASE + 0x41C)
+#define ARM_TIMER_CNTR		HWREG32(ARM_TIMER_BASE + 0x420)
+
+/*
+ *  Core Timer
+ */
+#define CTIMER_CTL          HWREG32(PER_BASE_40000000 + 0x00)  /* Control register */
+#define CTIMER_PRE          HWREG32(PER_BASE_40000000 + 0x08)  /* Core timer prescaler */
+#define CTIMER_LS32B        HWREG32(PER_BASE_40000000 + 0x1C)  /* Core timer access LS 32 bits */
+#define CTIMER_MS32B        HWREG32(PER_BASE_40000000 + 0x20)  /* Core timer access MS 32 bits */
+
+/*
+ *  ARM Core Timer
+ */
+#define C0TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x40)  /* Core0 timers Interrupt control */
+#define C1TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x44)  /* Core1 timers Interrupt control */
+#define C2TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x48)  /* Core2 timers Interrupt control */
+#define C3TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x4C)  /* Core3 timers Interrupt control */
+#define CORETIMER_INTCTL(n)      HWREG32(PER_BASE_40000000 + 0x40 + n*4)  /* Core3 timers Interrupt control */
+/*
+ *  ARM Core Mailbox interrupt
+ */
+#define C0MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x50)  /* Core0 Mailboxes Interrupt control */
+#define C1MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x54)  /* Core1 Mailboxes Interrupt control */
+#define C2MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x58)  /* Core2 Mailboxes Interrupt control */
+#define C3MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x5C)  /* Core3 Mailboxes Interrupt control */
+#define COREMB_INTCTL(n)    HWREG32(PER_BASE_40000000 + 0x50 + 4*n)  /* Core3 Mailboxes Interrupt control */
+/*
+ *  ARM Core IRQ/FIQ status
+ */
+#define C0_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x60)  /* Core0 IRQ Source */
+#define C1_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x64)  /* Core1 IRQ Source */
+#define C2_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x68)  /* Core2 IRQ Source */
+#define C3_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x6C)  /* Core3 IRQ Source */
+#define C0_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x70)  /* Core0 FIQ Source */
+#define C1_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x74)  /* Core1 FIQ Source */
+#define C2_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x78)  /* Core2 FIQ Source */
+#define C3_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x7C)  /* Core3 FIQ Source */
+#define CORE_IRQSOURCE(n)        HWREG32(PER_BASE_40000000 + 0x60+ n*0x4)
+#define CORE_FIQSOURCE(n)        HWREG32(PER_BASE_40000000 + 0x70+ n*0x4)
+
+#define CORE_MAILBOX3_SET(n)        HWREG32(PER_BASE_40000000 + 0x8C + n*0x10)
+#define CORE_MAILBOX3_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xCC + n*0x10)
+#define CORE_MAILBOX2_SET(n)        HWREG32(PER_BASE_40000000 + 0x88 + n*0x10)
+#define CORE_MAILBOX2_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC8 + n*0x10)
+#define CORE_MAILBOX1_SET(n)        HWREG32(PER_BASE_40000000 + 0x84 + n*0x10)
+#define CORE_MAILBOX1_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC4 + n*0x10)
+#define CORE_MAILBOX0_SET(n)        HWREG32(PER_BASE_40000000 + 0x80 + n*0x10)
+#define CORE_MAILBOX0_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC0 + n*0x10)
+
+/* for smp ipi using mailbox0 */
+#define IPI_MAILBOX_SET   CORE_MAILBOX0_SET
+
+#define IPI_MAILBOX_CLEAR CORE_MAILBOX0_CLEAR
+#define IPI_MAILBOX_INT_MASK     (0x01)
+
+#define IRQ_ARM_TIMER           64
+#define IRQ_ARM_MAILBOX         65
+#define IRQ_ARM_DB0             66
+#define IRQ_ARM_DB1             67
+#define IRQ_ARM_GPU0_HALT       68
+#define IRQ_ARM_GPU1_HALT       69
+#define IRQ_ARM_ILLEGAL_ACC1    70
+#define IRQ_ARM_ILLEGAL_ACC0    71
+
+#define IRQ_SYSTIMER_MATCH_1    1
+#define IRQ_SYSTIMER_MATCH_3    3
+
+#define IRQ_AUX                 29
+#define IRQ_IIC_SPI_SLV         43
+#define IRQ_PWA0                45
+#define IRQ_PWA1                46
+#define IRQ_SMI                 48
+#define IRQ_GPIO0               49
+#define IRQ_GPIO1               50
+#define IRQ_GPIO2               51
+#define IRQ_GPIO3               52
+#define IRQ_IIC                 53
+#define IRQ_SPI                 54
+#define IRQ_PCM                 55
+#define IRQ_UART                57
+
+/* CLOCK */
+#define BCM283X_PLLA			0
+#define BCM283X_PLLB			1
+#define BCM283X_PLLC			2
+#define BCM283X_PLLD			3
+#define BCM283X_PLLH			4
+
+#define BCM283X_PLLA_CORE		5
+#define BCM283X_PLLA_PER		6
+#define BCM283X_PLLB_ARM		7
+#define BCM283X_PLLC_CORE0		8
+#define BCM283X_PLLC_CORE1		9
+#define BCM283X_PLLC_CORE2		10
+#define BCM283X_PLLC_PER		11
+#define BCM283X_PLLD_CORE		12
+#define BCM283X_PLLD_PER		13
+#define BCM283X_PLLH_RCAL		14
+#define BCM283X_PLLH_AUX		15
+#define BCM283X_PLLH_PIX		16
+
+#define BCM283X_CLOCK_TIMER		17
+#define BCM283X_CLOCK_OTP		18
+#define BCM283X_CLOCK_UART		19
+#define BCM283X_CLOCK_VPU		20
+#define BCM283X_CLOCK_V3D		21
+#define BCM283X_CLOCK_ISP		22
+#define BCM283X_CLOCK_H264		23
+#define BCM283X_CLOCK_VEC		24
+#define BCM283X_CLOCK_HSM		25
+#define BCM283X_CLOCK_SDRAM		26
+#define BCM283X_CLOCK_TSENS		27
+#define BCM283X_CLOCK_EMMC		28
+#define BCM283X_CLOCK_PERI_IMAGE	29
+#define BCM283X_CLOCK_COUNT		30
+
+#define CM_PASSWORD		0x5a000000
+
+#define CM_GNRICCTL		0x000
+#define CM_GNRICDIV		0x004
+#define CM_VPUCTL		0x008
+#define CM_VPUDIV		0x00c
+#define CM_SYSCTL		0x010
+#define CM_SYSDIV		0x014
+#define CM_PERIACTL		0x018
+#define CM_PERIADIV		0x01c
+#define CM_PERIICTL		0x020
+#define CM_PERIIDIV		0x024
+#define CM_H264CTL		0x028
+#define CM_H264DIV		0x02c
+#define CM_ISPCTL		0x030
+#define CM_ISPDIV		0x034
+#define CM_V3DCTL		0x038
+#define CM_V3DDIV		0x03c
+#define CM_CAM0CTL		0x040
+#define CM_CAM0DIV		0x044
+#define CM_CAM1CTL		0x048
+#define CM_CAM1DIV		0x04c
+#define CM_CCP2CTL		0x050
+#define CM_CCP2DIV		0x054
+#define CM_DSI0ECTL		0x058
+#define CM_DSI0EDIV		0x05c
+#define CM_DSI0PCTL		0x060
+#define CM_DSI0PDIV		0x064
+#define CM_DPICTL		0x068
+#define CM_DPIDIV		0x06c
+#define CM_GP0CTL		0x070
+#define CM_GP0DIV		0x074
+#define CM_GP1CTL		0x078
+#define CM_GP1DIV		0x07c
+#define CM_GP2CTL		0x080
+#define CM_GP2DIV		0x084
+#define CM_HSMCTL		0x088
+#define CM_HSMDIV		0x08c
+#define CM_OTPCTL		0x090
+#define CM_OTPDIV		0x094
+#define CM_PWMCTL		0x0a0
+#define CM_PWMDIV		0x0a4
+#define CM_SMICTL		0x0b0
+#define CM_SMIDIV		0x0b4
+#define CM_TSENSCTL		0x0e0
+#define CM_TSENSDIV		0x0e4
+#define CM_TIMERCTL		0x0e8
+#define CM_TIMERDIV		0x0ec
+#define CM_UARTCTL		0x0f0
+#define CM_UARTDIV		0x0f4
+#define CM_VECCTL		0x0f8
+#define CM_VECDIV		0x0fc
+#define CM_PULSECTL		0x190
+#define CM_PULSEDIV		0x194
+#define CM_SDCCTL		0x1a8
+#define CM_SDCDIV		0x1ac
+#define CM_ARMCTL		0x1b0
+#define CM_EMMCCTL		0x1c0
+#define CM_EMMCDIV		0x1c4
+
+#define BCM283X_AUX_IRQ			0x0000  /*!< xxx */
+#define BCM283X_AUX_ENABLE		0x0004  /*!< */
+#define BCM283X_AUX_ENABLE_UART1	0x01    /*!<  */
+#define BCM283X_AUX_ENABLE_SPI0		0x02	/*!< SPI0 (SPI1 in the device) */
+#define BCM283X_AUX_ENABLE_SPI1		0x04	/*!< SPI1 (SPI2 in the device) */
+#define BCM283X_AUX_SPI_CNTL0		0x0000  /*!< */
+#define BCM283X_AUX_SPI_CNTL1 		0x0004  /*!< */
+#define BCM283X_AUX_SPI_STAT 		0x0008  /*!< */
+#define BCM283X_AUX_SPI_PEEK		0x000C  /*!< Read but do not take from FF */
+#define BCM283X_AUX_SPI_IO		0x0020  /*!< Write = TX, read=RX */
+#define BCM283X_AUX_SPI_TXHOLD		0x0030  /*!< Write = TX keep CS, read=RX */
+#define BCM283X_AUX_SPI_CLOCK_MIN	30500		/*!< 30,5kHz */
+#define BCM283X_AUX_SPI_CLOCK_MAX	125000000 	/*!< 125Mhz */
+#define BCM283X_AUX_SPI_CNTL0_SPEED	0xFFF00000  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_SPEED_MAX	0xFFF      /*!< */
+#define BCM283X_AUX_SPI_CNTL0_SPEED_SHIFT 20        /*!< */
+#define BCM283X_AUX_SPI_CNTL0_CS0_N     0x000C0000 /*!< CS 0 low */
+#define BCM283X_AUX_SPI_CNTL0_CS1_N     0x000A0000 /*!< CS 1 low */
+#define BCM283X_AUX_SPI_CNTL0_CS2_N 	0x00060000 /*!< CS 2 low */
+#define BCM283X_AUX_SPI_CNTL0_POSTINPUT	0x00010000  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_VAR_CS	0x00008000  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_VAR_WIDTH	0x00004000  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_DOUTHOLD	0x00003000  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_ENABLE	0x00000800  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_CPHA_IN	0x00000400  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_CLEARFIFO	0x00000200  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_CPHA_OUT	0x00000100  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_CPOL	0x00000080  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_MSBF_OUT	0x00000040  /*!< */
+#define BCM283X_AUX_SPI_CNTL0_SHIFTLEN	0x0000003F  /*!< */
+#define BCM283X_AUX_SPI_CNTL1_CSHIGH	0x00000700  /*!< */
+#define BCM283X_AUX_SPI_CNTL1_IDLE	0x00000080  /*!< */
+#define BCM283X_AUX_SPI_CNTL1_TXEMPTY	0x00000040  /*!< */
+#define BCM283X_AUX_SPI_CNTL1_MSBF_IN	0x00000002  /*!< */
+#define BCM283X_AUX_SPI_CNTL1_KEEP_IN	0x00000001  /*!< */
+#define BCM283X_AUX_SPI_STAT_TX_LVL	0xFF000000  /*!< */
+#define BCM283X_AUX_SPI_STAT_RX_LVL	0x00FF0000  /*!< */
+#define BCM283X_AUX_SPI_STAT_TX_FULL	0x00000400  /*!< */
+#define BCM283X_AUX_SPI_STAT_TX_EMPTY	0x00000200  /*!< */
+#define BCM283X_AUX_SPI_STAT_RX_FULL	0x00000100  /*!< */
+#define BCM283X_AUX_SPI_STAT_RX_EMPTY	0x00000080  /*!< */
+#define BCM283X_AUX_SPI_STAT_BUSY	0x00000040  /*!< */
+#define BCM283X_AUX_SPI_STAT_BITCOUNT	0x0000003F  /*!< */
+
+/* Defines for SPI */
+#define BCM283X_SPI0_CS                      0x0000 /*!< SPI Master Control and Status */
+#define BCM283X_SPI0_FIFO                    0x0004 /*!< SPI Master TX and RX FIFOs */
+#define BCM283X_SPI0_CLK                     0x0008 /*!< SPI Master Clock Divider */
+#define BCM283X_SPI0_DLEN                    0x000c /*!< SPI Master Data Length */
+#define BCM283X_SPI0_LTOH                    0x0010 /*!< SPI LOSSI mode TOH */
+#define BCM283X_SPI0_DC                      0x0014 /*!< SPI DMA DREQ Controls */
+
+/* Register masks for SPI0_CS */
+#define BCM283X_SPI0_CS_LEN_LONG             0x02000000 /*!< Enable Long data word in Lossi mode if DMA_LEN is set */
+#define BCM283X_SPI0_CS_DMA_LEN              0x01000000 /*!< Enable DMA mode in Lossi mode */
+#define BCM283X_SPI0_CS_CSPOL2               0x00800000 /*!< Chip Select 2 Polarity */
+#define BCM283X_SPI0_CS_CSPOL1               0x00400000 /*!< Chip Select 1 Polarity */
+#define BCM283X_SPI0_CS_CSPOL0               0x00200000 /*!< Chip Select 0 Polarity */
+#define BCM283X_SPI0_CS_RXF                  0x00100000 /*!< RXF - RX FIFO Full */
+#define BCM283X_SPI0_CS_RXR                  0x00080000 /*!< RXR RX FIFO needs Reading (full) */
+#define BCM283X_SPI0_CS_TXD                  0x00040000 /*!< TXD TX FIFO can accept Data */
+#define BCM283X_SPI0_CS_RXD                  0x00020000 /*!< RXD RX FIFO contains Data */
+#define BCM283X_SPI0_CS_DONE                 0x00010000 /*!< Done transfer Done */
+#define BCM283X_SPI0_CS_TE_EN                0x00008000 /*!< Unused */
+#define BCM283X_SPI0_CS_LMONO                0x00004000 /*!< Unused */
+#define BCM283X_SPI0_CS_LEN                  0x00002000 /*!< LEN LoSSI enable */
+#define BCM283X_SPI0_CS_REN                  0x00001000 /*!< REN Read Enable */
+#define BCM283X_SPI0_CS_ADCS                 0x00000800 /*!< ADCS Automatically Deassert Chip Select */
+#define BCM283X_SPI0_CS_INTR                 0x00000400 /*!< INTR Interrupt on RXR */
+#define BCM283X_SPI0_CS_INTD                 0x00000200 /*!< INTD Interrupt on Done */
+#define BCM283X_SPI0_CS_DMAEN                0x00000100 /*!< DMAEN DMA Enable */
+#define BCM283X_SPI0_CS_TA                   0x00000080 /*!< Transfer Active */
+#define BCM283X_SPI0_CS_CSPOL                0x00000040 /*!< Chip Select Polarity */
+#define BCM283X_SPI0_CS_CLEAR                0x00000030 /*!< Clear FIFO Clear RX and TX */
+#define BCM283X_SPI0_CS_CLEAR_RX             0x00000020 /*!< Clear FIFO Clear RX  */
+#define BCM283X_SPI0_CS_CLEAR_TX             0x00000010 /*!< Clear FIFO Clear TX  */
+#define BCM283X_SPI0_CS_CPOL                 0x00000008 /*!< Clock Polarity */
+#define BCM283X_SPI0_CS_CPHA                 0x00000004 /*!< Clock Phase */
+#define BCM283X_SPI0_CS_CS                   0x00000003 /*!< Chip Select */
+
+enum spi_bit_order
+{
+    BCM283X_SPI_BIT_ORDER_LSBFIRST = 0,  /*!< LSB First */
+    BCM283X_SPI_BIT_ORDER_MSBFIRST = 1   /*!< MSB First */
+};
+
+enum spi_mode
+{
+    BCM283X_SPI_MODE0 = 0,  /*!< CPOL = 0, CPHA = 0 */
+    BCM283X_SPI_MODE1 = 1,  /*!< CPOL = 0, CPHA = 1 */
+    BCM283X_SPI_MODE2 = 2,  /*!< CPOL = 1, CPHA = 0 */
+    BCM283X_SPI_MODE3 = 3   /*!< CPOL = 1, CPHA = 1 */
+};
+
+enum spi_chip_select
+{
+    BCM283X_SPI_CS0 = 0,     /*!< Chip Select 0 */
+    BCM283X_SPI_CS1 = 1,     /*!< Chip Select 1 */
+    BCM283X_SPI_CS2 = 2,     /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
+    BCM283X_SPI_CS_NONE = 3  /*!< No CS, control it yourself */
+};
+
+enum spi_clock_divider
+{
+    BCM283X_SPI_CLOCK_DIVIDER_65536 = 0,       /*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_32768 = 32768,   /*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_16384 = 16384,   /*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_8192  = 8192,    /*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_4096  = 4096,    /*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_2048  = 2048,    /*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_1024  = 1024,    /*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_512   = 512,     /*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_256   = 256,     /*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_128   = 128,     /*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_64    = 64,      /*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_32    = 32,      /*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_16    = 16,      /*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_8     = 8,       /*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_4     = 4,       /*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */
+    BCM283X_SPI_CLOCK_DIVIDER_2     = 2,       /*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/
+    BCM283X_SPI_CLOCK_DIVIDER_1     = 1        /*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */
+};
+
+/* BCM IO pin */
+enum bcm_gpio_pin
+{
+    BCM_GPIO_PIN_0 = 0,
+    BCM_GPIO_PIN_1,
+    BCM_GPIO_PIN_2,
+    BCM_GPIO_PIN_3,
+    BCM_GPIO_PIN_4,
+    BCM_GPIO_PIN_5,
+    BCM_GPIO_PIN_6,
+    BCM_GPIO_PIN_7,
+    BCM_GPIO_PIN_8,
+    BCM_GPIO_PIN_9,
+    BCM_GPIO_PIN_10,
+    BCM_GPIO_PIN_11,
+    BCM_GPIO_PIN_12,
+    BCM_GPIO_PIN_13,
+    BCM_GPIO_PIN_14,
+    BCM_GPIO_PIN_15,
+    BCM_GPIO_PIN_16,
+    BCM_GPIO_PIN_17,
+    BCM_GPIO_PIN_18,
+    BCM_GPIO_PIN_19,
+    BCM_GPIO_PIN_20,
+    BCM_GPIO_PIN_21,
+    BCM_GPIO_PIN_22,
+    BCM_GPIO_PIN_23,
+    BCM_GPIO_PIN_24,
+    BCM_GPIO_PIN_25,
+    BCM_GPIO_PIN_26,
+    BCM_GPIO_PIN_27,
+    BCM_GPIO_PIN_28,
+    BCM_GPIO_PIN_29,
+    BCM_GPIO_PIN_30,
+    BCM_GPIO_PIN_31,
+    BCM_GPIO_PIN_32,
+    BCM_GPIO_PIN_33,
+    BCM_GPIO_PIN_34,
+    BCM_GPIO_PIN_35,
+    BCM_GPIO_PIN_36,
+    BCM_GPIO_PIN_37,
+    BCM_GPIO_PIN_38,
+    BCM_GPIO_PIN_39,
+    BCM_GPIO_PIN_40,
+    BCM_GPIO_PIN_41,
+    BCM_GPIO_PIN_42,
+    BCM_GPIO_PIN_43,
+    BCM_GPIO_PIN_44,
+    BCM_GPIO_PIN_45,
+    BCM_GPIO_PIN_46,
+    BCM_GPIO_PIN_47,
+    BCM_GPIO_PIN_48,
+    BCM_GPIO_PIN_49,
+    BCM_GPIO_PIN_50,
+    BCM_GPIO_PIN_51,
+    BCM_GPIO_PIN_52,
+    BCM_GPIO_PIN_53,
+    BCM_GPIO_PIN_NUM,
+};
+
+rt_uint32_t bcm283x_peri_read(volatile rt_ubase_t addr);
+rt_uint32_t bcm283x_peri_read_nb(volatile rt_ubase_t addr);
+void bcm283x_peri_write(volatile rt_ubase_t addr, rt_uint32_t value);
+void bcm283x_peri_write_nb(volatile rt_ubase_t addr, rt_uint32_t value);
+void bcm283x_peri_set_bits(volatile rt_ubase_t addr, rt_uint32_t value, rt_uint32_t mask);
+
+void bcm283x_gpio_fsel(rt_uint8_t pin, rt_uint8_t mode);
+void bcm283x_gpio_set(rt_uint8_t pin);
+void bcm283x_gpio_clr(rt_uint8_t pin);
+
+rt_uint8_t bcm283x_gpio_lev(rt_uint8_t pin);
+rt_uint8_t bcm283x_gpio_eds(rt_uint8_t pin);
+void bcm283x_gpio_set_eds(rt_uint8_t pin);
+void bcm283x_gpio_ren(rt_uint8_t pin);
+void bcm283x_gpio_clr_ren(rt_uint8_t pin);
+void bcm283x_gpio_fen(rt_uint8_t pin);
+void bcm283x_gpio_clr_fen(rt_uint8_t pin);
+void bcm283x_gpio_hen(rt_uint8_t pin);
+void bcm283x_gpio_clr_hen(rt_uint8_t pin);
+void bcm283x_gpio_len(rt_uint8_t pin);
+void bcm283x_gpio_clr_len(rt_uint8_t pin);
+void bcm283x_gpio_aren(rt_uint8_t pin);
+void bcm283x_gpio_clr_aren(rt_uint8_t pin);
+void bcm283x_gpio_afen(rt_uint8_t pin);
+void bcm283x_gpio_clr_afen(rt_uint8_t pin);
+void bcm283x_gpio_pud(rt_uint8_t pud);
+void bcm283x_gpio_pudclk(rt_uint8_t pin, rt_uint8_t on);
+void bcm283x_gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud);
+void bcm283x_gpio_write(rt_uint8_t pin, rt_uint8_t val);
+void bcm283x_st_delay(rt_uint64_t offset_micros, rt_uint64_t micros);
+rt_uint64_t bcm283x_st_read(void);
+void bcm283x_delayMicroseconds(rt_uint64_t micros);
+void bcm283x_clo_delayMicros(rt_uint32_t micros);
+
+int bcm283x_i2c_begin(int no);
+void bcm283x_i2c_end(int no);
+void bcm283x_i2c_setSlaveAddress(int no, rt_uint8_t saddr);
+void bcm283x_i2c_setClockDivider(int no, rt_uint16_t divider);
+void bcm283x_i2c_set_baudrate(int no, rt_uint32_t baudrate);
+rt_uint8_t bcm283x_i2c_read(rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len);
+rt_uint8_t bcm283x_i2c_write(rt_uint32_t base, const rt_uint8_t * buf, rt_uint32_t len);
+rt_uint8_t bcm283x_i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len);
+
+#endif
+
diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c
new file mode 100644
index 0000000000..3c218d09a7
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_timer.h"
+
+#include "cp15.h"
+
+#ifdef RT_USING_SMP
+extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
+
+void ipi_handler(){
+    rt_scheduler_ipi_handler(0,RT_NULL);
+}
+#endif
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    ARM_TIMER_IRQCLR = 0;
+    rt_tick_increase();
+}
+
+int rt_hw_timer_init()
+{
+    __DSB();
+    rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IRQ_ARM_TIMER);
+    /* timer_clock = apb_clock/(pre_divider + 1) */
+    ARM_TIMER_PREDIV = (250 - 1);
+
+    ARM_TIMER_RELOAD = 0;
+    ARM_TIMER_LOAD   = 0;
+    ARM_TIMER_IRQCLR = 0;
+    ARM_TIMER_CTRL   = 0;
+
+    ARM_TIMER_RELOAD = 10000;
+    ARM_TIMER_LOAD   = 10000;
+
+    /* 23-bit counter, enable interrupt, enable timer */
+    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
+    return 0;
+}
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+#define MMU_LEVEL_MASK 0x1ffUL
+#define MMU_MAP_ERROR_VANOTALIGN  -1
+#define MMU_MAP_ERROR_PANOTALIGN  -2
+#define MMU_MAP_ERROR_NOPAGE      -3
+#define MMU_MAP_ERROR_CONFLICT    -4
+
+unsigned char main_tbl[4096] __attribute__((aligned (4096)));
+unsigned char __page_start[4096*100] __attribute__((aligned (4096)));
+unsigned long __page_off = 0;
+unsigned long get_free_page(void) {
+    __page_off += 4096;
+    return (unsigned long)(__page_start + __page_off - 4096);
+}
+
+#define MEM_ATTR_MEM ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
+#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
+
+static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) {
+    int level;
+    unsigned long* cur_lv_tbl = lv0_tbl;
+    unsigned long page;
+    unsigned long off;
+    int level_shift = 39;
+
+    if (va & (0x200000UL - 1)) {
+        return MMU_MAP_ERROR_VANOTALIGN;
+    }
+    if (pa & (0x200000UL - 1)) {
+        return MMU_MAP_ERROR_PANOTALIGN;
+    }
+    for (level = 0; level < 2; level++) {
+        off = (va >> level_shift);
+        off &= MMU_LEVEL_MASK;
+        if ((cur_lv_tbl[off] & 1) == 0) {
+            page = get_free_page();
+            if (!page) {
+                return MMU_MAP_ERROR_NOPAGE;
+            }
+            rt_memset((void *)page, 0, 4096);
+            cur_lv_tbl[off] = page | 0x3UL;
+        }
+        page = cur_lv_tbl[off];
+        if (!(page & 0x2)) {
+            //is block! error!
+            return MMU_MAP_ERROR_CONFLICT;
+        }
+        cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
+        level_shift -= 9;
+    }
+    attr &= 0xfff0000000000ffcUL;
+    pa |= (attr | 0x1UL); //block
+    off = (va >> 21);
+    off &= MMU_LEVEL_MASK;
+    cur_lv_tbl[off] = pa;
+    return 0;
+}
+
+int armv8_map_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, int count, unsigned long attr)
+{
+	int i;
+    int ret;
+
+	if (va & (0x200000 - 1))
+	{
+		return -1;
+	}
+	if (pa & (0x200000 - 1))
+	{
+		return -1;
+	}
+	for (i = 0; i < count; i++)
+	{
+		ret = map_single_page_2M(lv0_tbl, va, pa, attr);
+		va += 0x200000;
+		pa += 0x200000;
+        if (ret != 0)
+        {
+            return ret;
+        }
+	}
+    return 0;
+}
+
+/**
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  after interrupt disabled.
+ */
+void rt_hw_board_init(void)
+{
+    /* mmu set */
+    unsigned long val64;
+    unsigned long val32; //val32不是uint32_t,val32只是表示相关的那个寄存器是32位的
+    int ret;
+
+    val64 = 0x007f6eUL;
+    asm volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
+    asm volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
+
+    //TCR_EL1
+    val32 = (16UL << 0)
+        | (0x0UL << 6)
+        | (0x0UL << 7)
+        | (0x3UL << 8)
+        | (0x3UL << 10)
+        | (0x2UL << 12)
+        | (0x0UL << 14)
+        | (0x0UL << 16)
+        | (0x0UL << 22)
+        | (0x1UL << 23)
+        | (0x2UL << 30)
+        | (0x1UL << 32)
+        | (0x0UL << 35)
+        | (0x0UL << 36)
+        | (0x0UL << 37)
+        | (0x0UL << 38);
+    asm volatile("msr TCR_EL1, %0\n"::"r"(val32));
+    asm volatile("mrs %0, TCR_EL1\n":"=r"(val32));
+
+    asm volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
+    asm volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
+
+    rt_memset(main_tbl, 0, 4096);
+
+	ret = armv8_map_2M((unsigned long *)main_tbl, 0x0, 0x0, 32, MEM_ATTR_MEM); //32*2M = 64M
+    if (ret)
+    {
+        goto skip_mmu;
+    }
+	ret = armv8_map_2M((unsigned long *)main_tbl, 0x3f000000, 0x3f000000, 8, MEM_ATTR_IO); //8*2M = 16M
+    if (ret)
+    {
+        goto skip_mmu;
+    }
+
+	//关闭指令cache
+	__asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
+	val64 &= ~0x1000; //disable I
+	__asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
+
+	//清除指令cache
+	__asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
+	//清除tlb
+	__asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
+
+	//SCTLR_EL1, turn on mmu
+	asm volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
+	val32 |= 0x1005; //enable mmu, I C M
+	asm volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
+
+skip_mmu:
+
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
+    rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
+
+    /* initialize uart */
+    rt_hw_uart_init();      // driver/drv_uart.c
+    /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
+
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+	rt_kprintf("__page_off = %x\n", __page_off);
+}
+
+#ifdef RT_USING_SMP
+void _reset(void);
+void secondary_cpu_start(void);
+
+void rt_hw_secondary_cpu_up(void)
+{
+    int i;
+    int retry,val;
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+    /*TODO maybe, there is some bug */
+    for(i=RT_CPUS_NR-1; i>0; i-- )
+    {
+        rt_kprintf("boot cpu:%d\n", i);
+        setup_bootstrap_addr(i, (int)_reset);
+        __SEV();
+        __DSB();
+        __ISB();
+        retry = 10;
+        rt_thread_delay(RT_TICK_PER_SECOND/1000);
+        do
+        {
+            val = CORE_MAILBOX3_CLEAR(i);
+            if (val == 0)
+            {
+                rt_kprintf("start OK: CPU %d \n",i);
+                break;
+            }
+            rt_thread_delay(RT_TICK_PER_SECOND);
+
+            retry --;
+            if (retry <= 0)
+            {
+                rt_kprintf("can't start for CPU %d \n",i);
+                break;
+            }
+        }while (1);
+    }
+    __DSB();
+    __SEV();
+}
+
+void secondary_cpu_c_start(void)
+{
+    uint32_t id;
+    id = rt_hw_cpu_id();
+    rt_kprintf("cpu = 0x%08x\n",id);
+    rt_hw_timer_init();
+    rt_kprintf("cpu %d startup.\n",id);
+    rt_hw_vector_init();
+    enable_cpu_ipi_intr(id);
+    rt_hw_spin_lock(&_cpus_lock);
+    rt_system_scheduler_start();
+}
+
+void rt_hw_secondary_cpu_idle_exec(void)
+{
+    __WFE();
+}
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.h b/bsp/raspberry-pi/raspi3-64/driver/board.h
new file mode 100644
index 0000000000..40fbfd9d84
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+
+#include <rthw.h>
+#include <bcm283x.h>
+
+#define __REG32 HWREG32
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 4 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
+
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
new file mode 100644
index 0000000000..485f7b587b
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
@@ -0,0 +1,523 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "mbox.h"
+#include "drv_fb.h"
+#include "mmu.h"
+
+#define CHAR_W          8
+#define CHAR_H          12
+
+#define COLOR_DELTA     0.05
+static struct rt_hdmi_fb_device _hdmi;
+
+// https://github.com/xinu-os/xinu/blob/1789b7a50b5b73c2ea76ebd764c54a034097d04d/device/framebuffer_rpi/font.c
+unsigned char FONT[] = {
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/
+0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'!'*/
+0x00, 0x14, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'"'*/
+0x00, 0x00, 0x14, 0x14, 0x3e, 0x14, 0x3e, 0x14, 0x14, 0x00, 0x00, 0x00, /*'#'*/
+0x00, 0x00, 0x08, 0x3c, 0x0a, 0x1c, 0x28, 0x1e, 0x08, 0x00, 0x00, 0x00, /*'$'*/
+0x00, 0x00, 0x06, 0x26, 0x10, 0x08, 0x04, 0x32, 0x30, 0x00, 0x00, 0x00, /*'%'*/
+0x00, 0x00, 0x1c, 0x02, 0x02, 0x04, 0x2a, 0x12, 0x2c, 0x00, 0x00, 0x00, /*'&'*/
+0x00, 0x18, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'''*/
+0x20, 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x00, /*'('*/
+0x02, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x02, 0x00, /*')'*/
+0x00, 0x00, 0x00, 0x08, 0x2a, 0x1c, 0x2a, 0x08, 0x00, 0x00, 0x00, 0x00, /*'*'*/
+0x00, 0x00, 0x00, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /*'+'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*','*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'-'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*'.'*/
+0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x04, 0x04, 0x02, 0x02, 0x00, 0x00, /*'/'*/
+0x00, 0x1c, 0x22, 0x32, 0x2a, 0x26, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'0'*/
+0x00, 0x08, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'1'*/
+0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'2'*/
+0x00, 0x1c, 0x22, 0x20, 0x18, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'3'*/
+0x00, 0x10, 0x18, 0x18, 0x14, 0x14, 0x3e, 0x10, 0x38, 0x00, 0x00, 0x00, /*'4'*/
+0x00, 0x3e, 0x02, 0x02, 0x1e, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'5'*/
+0x00, 0x18, 0x04, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'6'*/
+0x00, 0x3e, 0x22, 0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x00, 0x00, 0x00, /*'7'*/
+0x00, 0x1c, 0x22, 0x22, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'8'*/
+0x00, 0x1c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x10, 0x0c, 0x00, 0x00, 0x00, /*'9'*/
+0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*':'*/
+0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*';'*/
+0x00, 0x00, 0x00, 0x30, 0x0c, 0x03, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, /*'<'*/
+0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, /*'='*/
+0x00, 0x00, 0x00, 0x03, 0x0c, 0x30, 0x0c, 0x03, 0x00, 0x00, 0x00, 0x00, /*'>'*/
+0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'?'*/
+0x00, 0x00, 0x1c, 0x22, 0x3a, 0x3a, 0x1a, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'@'*/
+0x00, 0x00, 0x08, 0x14, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x00, 0x00, 0x00, /*'A'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'B'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x02, 0x02, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'C'*/
+0x00, 0x00, 0x0e, 0x12, 0x22, 0x22, 0x22, 0x12, 0x0e, 0x00, 0x00, 0x00, /*'D'*/
+0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'E'*/
+0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'F'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x32, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'G'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'H'*/
+0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x3e, 0x00, 0x00, 0x00, /*'I'*/
+0x00, 0x00, 0x38, 0x20, 0x20, 0x20, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'J'*/
+0x00, 0x00, 0x22, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'K'*/
+0x00, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'L'*/
+0x00, 0x00, 0x22, 0x36, 0x2a, 0x2a, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'M'*/
+0x00, 0x00, 0x22, 0x26, 0x26, 0x2a, 0x32, 0x32, 0x22, 0x00, 0x00, 0x00, /*'N'*/
+0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'O'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'P'*/
+0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x30, 0x00, 0x00, /*'Q'*/
+0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'R'*/
+0x00, 0x00, 0x1c, 0x22, 0x02, 0x1c, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'S'*/
+0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'T'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'U'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'V'*/
+0x00, 0x00, 0x22, 0x22, 0x22, 0x2a, 0x2a, 0x36, 0x22, 0x00, 0x00, 0x00, /*'W'*/
+0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x14, 0x22, 0x22, 0x00, 0x00, 0x00, /*'X'*/
+0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'Y'*/
+0x00, 0x00, 0x3e, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'Z'*/
+0x38, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x38, 0x00, /*'['*/
+0x02, 0x02, 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x00, 0x00, /*'\'*/
+0x0e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x0e, 0x00, /*']'*/
+0x00, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'^'*/
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, /*'_'*/
+0x00, 0x0c, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'`'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'a'*/
+0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'b'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x02, 0x02, 0x3c, 0x00, 0x00, 0x00, /*'c'*/
+0x00, 0x20, 0x20, 0x20, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'d'*/
+0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x3e, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'e'*/
+0x00, 0x38, 0x04, 0x04, 0x1e, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, /*'f'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'g'*/
+0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'h'*/
+0x00, 0x08, 0x08, 0x00, 0x0c, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'i'*/
+0x00, 0x10, 0x10, 0x00, 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0e, /*'j'*/
+0x00, 0x02, 0x02, 0x02, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x00, 0x00, 0x00, /*'k'*/
+0x00, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'l'*/
+0x00, 0x00, 0x00, 0x00, 0x16, 0x2a, 0x2a, 0x2a, 0x22, 0x00, 0x00, 0x00, /*'m'*/
+0x00, 0x00, 0x00, 0x00, 0x1a, 0x26, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'n'*/
+0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'o'*/
+0x00, 0x00, 0x00, 0x00, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, /*'p'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x20, /*'q'*/
+0x00, 0x00, 0x00, 0x00, 0x1a, 0x06, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'r'*/
+0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x1c, 0x20, 0x1e, 0x00, 0x00, 0x00, /*'s'*/
+0x00, 0x08, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x08, 0x30, 0x00, 0x00, 0x00, /*'t'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'u'*/
+0x00, 0x00, 0x00, 0x00, 0x36, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'v'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x2a, 0x2a, 0x2a, 0x14, 0x00, 0x00, 0x00, /*'w'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x14, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, /*'x'*/
+0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'y'*/
+0x00, 0x00, 0x00, 0x00, 0x3e, 0x10, 0x08, 0x04, 0x3e, 0x00, 0x00, 0x00, /*'z'*/
+0x20, 0x10, 0x10, 0x10, 0x10, 0x08, 0x10, 0x10, 0x10, 0x10, 0x20, 0x00, /*'{'*/
+0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, /*'|'*/
+0x02, 0x04, 0x04, 0x04, 0x04, 0x08, 0x04, 0x04, 0x04, 0x04, 0x02, 0x00, /*'}'*/
+0x00, 0x04, 0x2a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'~'*/
+0x00, 0x00, 0x00, 0x08, 0x08, 0x14, 0x14, 0x22, 0x3e, 0x00, 0x00, 0x00, /*DEL*/
+};
+
+void newline(fb_t* fb)
+{
+    uint8_t* to;
+    uint8_t* from;
+    int i;
+    fb->y++;
+    fb->x = 0;
+
+    if (fb->y == (fb->height / CHAR_H))
+    {
+
+        to = (uint8_t*) fb->addr;
+        from = to + (CHAR_H * fb->pitch);
+
+        for (i = 0; i < ((fb->height - CHAR_H) * fb->pitch); i++)
+        {
+            *to++ = *from++;
+        }
+
+        uint32_t *addr = (uint32_t*) (fb->addr) + (fb->height - CHAR_H) * fb->width;
+
+        for (i = 0; i < (CHAR_H * fb->width); i++)
+        {
+            *addr++ = fb->back;
+        }
+
+        fb->y--;
+    }
+}
+
+void clear_line(fb_t *fb, const int line)
+{
+    int i;
+    uint32_t* addr;
+    if (line > fb->height / CHAR_H)
+    {
+        fb->y = 0;
+    }
+    else
+    {
+        fb->y = line;
+    }
+
+    fb->x = 0;
+
+    addr = (uint32_t*) (fb->addr + (line * CHAR_H * fb->depth * fb->width));
+    for (i = 0; i < (CHAR_H * fb->width); i++)
+    {
+        *addr++ = fb->back;
+    }
+
+}
+
+void clear(fb_t *fb, const uint32_t color)
+{
+
+    uint32_t *addr = (uint32_t*) fb->addr;
+    uint32_t i;
+    for (i = 0; i < (fb->height * fb->width); i++)
+    {
+        *addr++ = color;
+    }
+    fb->x = 0;
+    fb->y = 0;
+
+}
+
+void fb_draw_char(fb_t *fb, char s)
+{
+    unsigned char* addr = (unsigned char*) fb->addr;
+    unsigned char *glyph = (unsigned char*) FONT + (s) * 12;
+    // calculate the offset on screen
+    int offs = (fb->y * CHAR_H * fb->pitch) + (fb->x * (CHAR_W + 1) * 4);
+    // variables
+    int i, j, line, mask, bytesperline = (CHAR_W + 7) / 8;
+    // display a character
+    for (j = 0; j < CHAR_H; j++)
+    {
+        // display one row
+        line = offs;
+        mask = 1;
+        for (i = 0; i < CHAR_W; i++)
+        {
+            // if bit set, we use white color, otherwise black
+            *((unsigned int*) (addr + line)) = ((int) *glyph) & mask ? fb->fore : fb->back;
+            mask <<= 1;
+            line += 4;
+        }
+        // adjust to next line
+        glyph += bytesperline;
+        offs += fb->pitch;
+    }
+}
+
+void fb_print(fb_t *fb, char *s)
+{
+
+    // draw next character if it's not zero
+    while (*s)
+    {
+        // handle carrige return
+        if (*s == '\r')
+        {
+            fb->x = 0;
+        }
+        else if (*s == '\n')
+        {
+            newline(fb);
+        }
+        else if (*s == '\t')
+        {
+            fb->x = ((fb->x + 4) >> 2) << 2;
+        }
+        else if (*s == '\b')
+        {
+            if (fb->x)
+            {
+                fb->x--;
+                fb_draw_char(fb, ' ');
+            }
+        }
+        else
+        {
+            fb_draw_char(fb, *s);
+            fb->x++;
+        }
+        // next character
+        if (fb->x == fb->width / CHAR_W)
+        {
+            newline(fb);
+        }
+        s++;
+    }
+}
+
+rt_err_t hdmi_fb_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+rt_err_t hdmi_fb_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size)
+{
+#ifdef BSP_USING_USPI
+    char* buffer = (char *) buf;
+    if(keyboard_available())
+    {
+        int i = 0;
+        int j = 0;
+        while (i != size)
+        {
+            int ch = keyboard_getchar();
+            if(ch != -1)
+            buffer[j++] = ch;
+            i++;
+        }
+        return j;
+
+    }
+#endif
+    return 0;
+}
+
+rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    fb_print(&_hdmi.fb, (char *) buffer);
+#ifdef BSP_USING_HDMI_DISPLAY
+    rt_device_t uart = rt_device_find("uart1");
+    int old_flag = uart->open_flag;
+    uart->open_flag |= RT_DEVICE_FLAG_STREAM;
+    rt_device_write(uart, 0, buffer, size);
+    uart->open_flag = old_flag;
+#endif
+    return size;
+
+}
+
+rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)
+{
+    return RT_EOK;
+}
+
+const static struct rt_device_ops hdmi_fb_ops = {
+    RT_NULL,
+    hdmi_fb_open,
+    hdmi_fb_close,
+    hdmi_fb_read,
+    hdmi_fb_write,
+    hdmi_fb_control
+};
+
+static struct rt_device_graphic_info _hdmi_info;
+
+static void hdmi_draw_rect(const char* pixel, int x1, int y1, int x2, int y2)
+{
+    int i, j;
+    int line;
+    for (j = y1; j <= y2; j++)
+    {
+        line = (j * _hdmi.fb.pitch) + (x1 * 4);
+        for (i = x1; i <= x2; i++)
+        {
+            // if bit set, we use white color, otherwise black
+            *((unsigned int*) (_hdmi_info.framebuffer + line)) = *(unsigned int*) pixel;
+            line += 4;
+        }
+    }
+
+}
+
+static void hdmi_set_pixel(const char* pixel, int x, int y)
+{
+    *(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) = *(uint32_t *) pixel;
+}
+
+static void hdmi_get_pixel(char* pixel, int x, int y)
+{
+    uint32_t ret = 0;
+    ret = (*(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) & 0x00FFFFFF);
+    *pixel = ret;
+}
+
+static void hdmi_draw_hline(const char* pixel, int x1, int x2, int y)
+{
+    hdmi_draw_rect(pixel, x1, y, x2, y);
+}
+
+static void hdmi_draw_vline(const char* pixel, int x, int y1, int y2)
+{
+    hdmi_draw_rect(pixel, x, y1, x, y2);
+}
+
+static void hdmi_blit_line(const char* pixels, int x, int y, rt_size_t size)
+{
+    int i = 0;
+    uint32_t *pixel_base = (uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4));
+    uint32_t *colors = (uint32_t *) pixels;
+    for (i = 0; i < size; i++)
+    {
+        pixel_base[i] = colors[i];
+    }
+}
+
+static struct rt_device_graphic_ops hdmi_ops = {
+    hdmi_set_pixel,
+    hdmi_get_pixel,
+    hdmi_draw_hline,
+    hdmi_draw_vline,
+    hdmi_blit_line
+};
+
+rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *name)
+{
+    struct rt_device *device;
+    RT_ASSERT(hdmi_fb != RT_NULL);
+
+    device = &hdmi_fb->parent;
+    device->user_data = &hdmi_ops;
+
+    /* set device type */
+    device->type = RT_Device_Class_Graphic;
+    /* initialize device interface */
+#ifdef RT_USING_DEVICE_OPS
+    device->ops = &hdmi_fb_ops;
+#else
+    device->init = RT_NULL;
+    device->open = hdmi_fb_open;
+    device->close = hdmi_fb_close;
+    device->read = hdmi_fb_read;
+    device->write = hdmi_fb_write;
+    device->control = hdmi_fb_control;
+#endif
+
+    /* register to device manager */
+    rt_device_register(device, name, RT_DEVICE_FLAG_RDWR);
+
+    return RT_EOK;
+}
+
+/**
+ * Show a picture
+ */
+void print_fb_info()
+{
+    rt_kprintf("FrameBuffer Info: \n \t width %x\t height %x\t depth %x\t addr %x\t size %x\t \n", fb_info.width,
+            fb_info.height, fb_info.depth, fb_info.addr, fb_info.size);
+    rt_kprintf("call mbox:%x,%x,%x,%x,%x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4]);
+}
+
+void hdmi_fb_init()
+{
+    unsigned int *mbox = (unsigned int*) MBOX_ADDR;
+    mbox[0] = 35 * 4;
+    mbox[1] = MBOX_REQUEST;
+
+    mbox[2] = 0x48003;  //set phy wh
+    mbox[3] = 8;
+    mbox[4] = 8;
+    mbox[5] = 640;         //FrameBufferInfo.width
+    mbox[6] = 480;          //FrameBufferInfo.height
+
+    mbox[7] = 0x48004;  //set virt wh
+    mbox[8] = 8;
+    mbox[9] = 8;
+    mbox[10] = 640;        //FrameBufferInfo.virtual_width
+    mbox[11] = 480;         //FrameBufferInfo.virtual_height
+
+    mbox[12] = 0x48009; //set virt offset
+    mbox[13] = 8;
+    mbox[14] = 8;
+    mbox[15] = 0;           //FrameBufferInfo.x_offset
+    mbox[16] = 0;           //FrameBufferInfo.y.offset
+
+    mbox[17] = 0x48005; //set depth
+    mbox[18] = 4;
+    mbox[19] = 4;
+    mbox[20] = 32;          //FrameBufferInfo.depth
+
+    mbox[21] = 0x48006; //set pixel order
+    mbox[22] = 4;
+    mbox[23] = 4;
+    mbox[24] = 1;           //RGB, not BGR preferably
+
+    mbox[25] = 0x40001; //get framebuffer, gets alignment on request
+    mbox[26] = 8;
+    mbox[27] = 8;
+    mbox[28] = 4096;        //FrameBufferInfo.pointer
+    mbox[29] = 0;           //FrameBufferInfo.size
+
+    mbox[30] = 0x40008; //get pitch
+    mbox[31] = 4;
+    mbox[32] = 4;
+    mbox[33] = 0;           //FrameBufferInfo.pitch
+
+    mbox[34] = MBOX_TAG_LAST;
+    if (mbox_call(MBOX_CH_PROP, MMU_DISABLE) && mbox[20] == 32 && mbox[28] != 0)
+    {
+        mbox[28] &= 0x3FFFFFFF;
+        _hdmi.fb.width = mbox[5];
+        _hdmi.fb.height = mbox[6];
+        _hdmi.fb.pitch = mbox[33];
+        //_hdmi.fb.addr = (void*)((unsigned long)mbox[28]);
+        _hdmi.fb.addr = (rt_uint32_t) mbox[28];
+        _hdmi.fb.size = mbox[29];
+        _hdmi.fb.depth = 32;
+        _hdmi.fb.x = 0;
+        _hdmi.fb.y = 0;
+        _hdmi.fb.fore = CONSOLE_WHITE;
+        _hdmi.fb.back = CONSOLE_BLACK;
+        rt_hdmi_fb_device_init(&_hdmi, "hdmi");
+        rt_hw_change_mmu_table(_hdmi.fb.addr, _hdmi.fb.size, _hdmi.fb.addr, DEVICE_MEM);
+        fb_info.width = _hdmi.fb.width;
+        fb_info.height = _hdmi.fb.height;
+        fb_info.addr = _hdmi.fb.addr;
+        fb_info.size = _hdmi.fb.size;
+        fb_info.pitch = _hdmi.fb.pitch;
+        fb_info.depth = _hdmi.fb.depth;
+        _hdmi_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888;
+        _hdmi_info.bits_per_pixel = _hdmi.fb.depth;
+        _hdmi_info.width = _hdmi.fb.width;
+        _hdmi_info.height = _hdmi.fb.height;
+        _hdmi_info.framebuffer = (rt_uint8_t *) _hdmi.fb.addr;
+    }
+}
+
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
new file mode 100644
index 0000000000..1b733f8d0f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+#ifndef __DRV_FB_H__
+#define __DRV_FB_H__
+
+#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
+
+#define COLOR_BLACK RGB(0, 0, 0)
+
+#define COLOR_GREEN RGB(0, 255, 0)  
+ 
+#define COLOR_CYAN RGB(0, 255, 255) 
+
+#define COLOR_RED RGB(255, 0, 0)  
+
+#define COLOR_YELLOW RGB(255, 255, 0) 
+
+#define COLOR_WHITE RGB(255, 255, 255)   
+
+#define CONSOLE_WHITE COLOR_WHITE
+#define CONSOLE_BLACK COLOR_BLACK
+#define CONSOLE_GREEN COLOR_GREEN
+#define CONSOLE_CYAN COLOR_CYAN
+#define CONSOLE_RED COLOR_RED
+#define CONSOLE_YELLOW COLOR_YELLOW
+
+typedef struct
+{
+    rt_uint32_t width;
+    rt_uint32_t height;
+    rt_uint32_t vwidth;
+    rt_uint32_t vheight;
+    rt_uint32_t pitch;
+    rt_uint32_t depth;
+    rt_uint32_t fore;
+    rt_uint32_t back;
+    rt_uint32_t x;
+    rt_uint32_t y;
+    rt_uint32_t addr;
+    rt_uint32_t size;
+}fb_t;
+
+struct rt_hdmi_fb_device
+{
+    struct rt_device parent;
+    fb_t fb;
+};
+
+fb_t fb_info;
+void print_fb_info();
+void hdmi_fb_init();
+
+#endif/* __DRV_FB_H__ */
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
new file mode 100644
index 0000000000..ce1883cce7
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
@@ -0,0 +1,473 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+#include "raspi.h"
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_PIN
+
+struct rpi_pin_index
+{
+    rt_uint8_t phy_id;
+    rt_uint8_t bcm_id;
+    rt_uint8_t signal_name;
+    rt_uint8_t magic;
+};
+
+//raspi phy id and bcm id
+static struct rpi_pin_index phypin_index[] =
+{
+    {0, 0, 0, 0},
+    {1, 0, 0, 0},
+    {2, 0, 0, 0},
+    {3, BCM_GPIO_PIN_2, RPI_SDA1, PIN_MAGIC},
+    {4, 0, 0, 0},
+    {5, BCM_GPIO_PIN_3, RPI_SCL1, PIN_MAGIC},
+    {6, 0, 0, 0},
+    {7, BCM_GPIO_PIN_4, RPI_GPIO_GCLK,  PIN_MAGIC},
+    {8, BCM_GPIO_PIN_14, RPI_TXD0, PIN_MAGIC},
+    {9, 0, 0, 0},
+    {10, BCM_GPIO_PIN_15, RPI_RXD0, PIN_MAGIC},
+    {11, BCM_GPIO_PIN_17, RPI_GPIO_GEN0,  PIN_MAGIC},
+    {12, BCM_GPIO_PIN_18, RPI_GPIO_GEN1,  PIN_MAGIC},
+    {13, BCM_GPIO_PIN_27, RPI_GPIO_GEN2,  PIN_MAGIC},
+    {14, 0, 0, 0},
+    {15, BCM_GPIO_PIN_22, RPI_GPIO_GEN3,  PIN_MAGIC},
+    {16, BCM_GPIO_PIN_23, RPI_GPIO_GEN4, PIN_MAGIC},
+    {17, 0, 0, 0},
+    {18, BCM_GPIO_PIN_24, RPI_GPIO_GEN5, PIN_MAGIC},
+    {19, BCM_GPIO_PIN_10, RPI_SPI_MOSI, PIN_MAGIC},
+    {20, 0, 0, 0},
+    {21, BCM_GPIO_PIN_9, RPI_SPI_MISO, PIN_MAGIC},
+    {22, BCM_GPIO_PIN_25, RPI_GPIO_GEN6, PIN_MAGIC},
+    {23, BCM_GPIO_PIN_11, RPI_SPI_SCLK, PIN_MAGIC},
+    {24, BCM_GPIO_PIN_8, RPI_SPI_CE0_N, PIN_MAGIC},
+    {25, 0, 0, 0},
+    {26, BCM_GPIO_PIN_7, RPI_SPI_CE1_N, PIN_MAGIC},
+    {27, BCM_GPIO_PIN_0, RPI_SDA0, PIN_MAGIC},
+    {28, BCM_GPIO_PIN_1, RPI_SCL0, PIN_MAGIC},
+    {29, BCM_GPIO_PIN_5, RPI_CAM_CLK, PIN_MAGIC},
+    {30, 0, 0, 0},
+    {31, BCM_GPIO_PIN_6, RPI_LAN_RUN, PIN_MAGIC},
+    {32, BCM_GPIO_PIN_12, 0, PIN_MAGIC},
+    {33, BCM_GPIO_PIN_13, 0, PIN_MAGIC},
+    {34, 0, 0, 0},
+    {35, BCM_GPIO_PIN_19, 0, PIN_MAGIC},
+    {36, BCM_GPIO_PIN_16, RPI_STATUS_LED_N, PIN_MAGIC},
+    {37, BCM_GPIO_PIN_26, 0, PIN_MAGIC},
+    {38, BCM_GPIO_PIN_20, 0, PIN_MAGIC},
+    {39, 0, 0, 0},
+    {40, BCM_GPIO_PIN_21, RPI_CAM_GPIO,  PIN_MAGIC},
+};
+
+/*
+ * gpio_int[0] for BANK0 (pins 0-27)
+ * gpio_int[1] for BANK1 (pins 28-45)
+ * gpio_int[2] for BANK2 (pins 46-53)
+ */
+static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM];
+
+int gpio_set_func(enum gpio_code code, enum bcm_gpio_pin pin, rt_uint8_t func)
+{
+    RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+
+    if (func & 0x8)
+    {
+        rt_kprintf("[line]:%d There is a warning with parameter input", __LINE__);
+        return RT_EINVAL;
+    }
+
+    switch(func)
+    {
+    case 0x00:
+        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_OUTP);
+        break;
+    case 0x01:
+        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case 0x02:
+        bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
+        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case 0x03:
+        bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_DOWN);
+        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
+        break;
+    case 0x04:
+        bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_OFF);
+        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_OUTP);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+int gpio_set_value(enum gpio_code code, enum bcm_gpio_pin pin, rt_uint8_t value)
+{
+
+    RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+
+    if (value & 0xE)
+    {
+        rt_kprintf("[line]:%d There is a warning with parameter input", __LINE__);
+        return RT_EINVAL;
+    }
+
+    bcm283x_gpio_write(pin, value);
+    return RT_EOK;
+}
+
+int gpio_get_value(enum gpio_code code, enum bcm_gpio_pin pin)
+{
+    rt_uint8_t data;
+
+    RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+
+    data = bcm283x_gpio_lev(pin);
+    return data;
+}
+
+void gpio_set_irq_callback(enum gpio_code port, enum bcm_gpio_pin pin, void (*irq_cb)(void *), void *irq_arg)
+{
+    RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+
+    rt_uint8_t index;
+    if (pin <= 27)
+    {
+        index = 0;
+    }
+    else if (pin <= 45)
+    {
+        index = 1;
+    }
+    else{
+        index = 2;
+    }
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = irq_cb;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = irq_arg;
+}
+
+void gpio_set_irq_type(enum gpio_code port,  enum bcm_gpio_pin pin, rt_uint8_t irq_type)
+{
+
+    RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+
+    rt_uint8_t index;
+    if (pin <= 27)
+    {
+        index = 0;
+    }
+    else if (pin <= 45)
+    {
+        index = 1;
+    }
+    else{
+        index = 2;
+    }
+    _g_gpio_irq_tbl[index].irq_type[pin] = irq_type;
+
+    switch(irq_type)
+    {
+    case 0x00:
+        bcm283x_gpio_ren(pin);
+        break;
+    case 0x01:
+        bcm283x_gpio_fen(pin);
+        break;
+    case 0x02:
+        bcm283x_gpio_aren(pin);
+        bcm283x_gpio_afen(pin);
+        break;
+    case 0x03:
+        bcm283x_gpio_hen(pin);
+        break;
+    case 0x04:
+        bcm283x_gpio_len(pin);
+        break;
+    }
+}
+
+static void gpio_ack_irq(int irq,  enum bcm_gpio_pin pin)
+{
+    rt_uint32_t data;
+    data = IRQ_PEND2;
+    data &= (0x0 << (irq - 32));
+    IRQ_PEND2 = data;
+
+    data = IRQ_DISABLE2;
+    data |= (0x1 << (irq - 32));
+    IRQ_DISABLE2 = data;
+}
+
+void gpio_irq_disable(enum gpio_code port,  enum bcm_gpio_pin pin)
+{
+    rt_uint8_t index;
+    int irq = 0;
+    RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+
+    if (pin <= 27)
+    {
+        index = 0;
+        irq = IRQ_GPIO0;
+    }else if (pin <= 45){
+        index = 1;
+        irq = IRQ_GPIO1;
+    }else{
+        index = 2;
+        irq = IRQ_GPIO2;
+    }
+
+    gpio_ack_irq(irq, pin);
+
+    rt_uint8_t irq_type = _g_gpio_irq_tbl[index].irq_type[pin];
+
+    switch(irq_type)
+    {
+    case 0x00:
+        bcm283x_gpio_clr_ren(pin);
+        break;
+    case 0x01:
+        bcm283x_gpio_clr_fen(pin);
+        break;
+    case 0x02:
+        bcm283x_gpio_clr_aren(pin);
+        bcm283x_gpio_clr_afen(pin);
+        break;
+    case 0x03:
+        bcm283x_gpio_clr_hen(pin);
+        break;
+    case 0x04:
+        bcm283x_gpio_clr_len(pin);
+        break;
+    }
+}
+
+void gpio_clear_irq_callback(enum gpio_code port, enum bcm_gpio_pin pin)
+{
+    rt_uint8_t index;
+    gpio_irq_disable(port, pin);
+
+    if (pin <= 27)
+    {
+        index = 0;
+    }
+    else if (pin <= 45)
+    {
+        index = 1;
+    }
+    else
+    {
+        index = 2;
+    }
+
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = RT_NULL;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = RT_NULL;
+    _g_gpio_irq_tbl[index].irq_type[pin]  = RT_NULL;
+
+}
+
+
+void gpio_irq_enable(enum gpio_code port,  enum bcm_gpio_pin pin)
+{
+
+    rt_uint32_t offset;
+    rt_uint32_t data;
+
+    RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+
+    offset = pin;
+    if (pin <= 27)
+    {
+        offset = IRQ_GPIO0 - 32;
+    }
+    else if (pin <= 45)
+    {
+        offset = IRQ_GPIO1 - 32;
+    }
+    else
+    {
+        offset = IRQ_GPIO2 - 32;
+    }
+
+    data = IRQ_ENABLE2;
+    data |= 0x1 << offset;
+    IRQ_ENABLE2 = data;
+
+}
+
+//gpio_int[0] for BANK0 (pins 0-27)
+//gpio_int[1] for BANK1 (pins 28-45)
+//gpio_int[2] for BANK2 (pins 46-53)
+static void gpio_irq_handler(int irq, void *param)
+{
+    struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param;
+    rt_uint32_t pin;
+    rt_uint32_t addr;
+    rt_uint32_t value;
+    rt_uint32_t tmpvalue;
+
+    if (irq == IRQ_GPIO0)
+    {
+        /* 0~27 */
+        addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0; // 0~31
+        value = bcm283x_peri_read(addr);
+        value &= 0x0fffffff;
+        pin = 0;
+    }
+    else if (irq == IRQ_GPIO1)
+    {
+        /* 28-45 */
+        addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0;
+        tmpvalue = bcm283x_peri_read(addr);
+        tmpvalue &= (~0x0fffffff);
+
+        addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS1;
+        value = bcm283x_peri_read(addr);
+        value &= 0x3fff;
+        value = (value<<4) | tmpvalue;
+
+        pin = 28;
+    }
+    else if (irq == IRQ_GPIO2)
+    {
+        /* 46-53 */
+        addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS1;
+        value = bcm283x_peri_read(addr);
+        value &= (~0x3fff);
+        value &= 0xff600000;
+        pin = 46;
+    }
+
+    bcm283x_peri_write(addr,0);
+
+    while (value)
+    {
+        if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL))
+        {
+            irq_def->irq_cb[pin](irq_def->irq_arg[pin]);
+            gpio_ack_irq(irq,pin);
+        }
+        pin++;
+        value = value >> 1;
+    }
+}
+
+static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+{
+    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
+    {
+        rt_kprintf("pin:%d value wrongful", pin);
+        return;
+    }
+
+    gpio_set_func(GPIO_CODE_BCM, phypin_index[pin].bcm_id, mode);
+}
+
+static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+{
+    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
+    {
+        rt_kprintf("pin:%d value wrongful", pin);
+        return;
+    }
+
+    gpio_set_value(GPIO_CODE_BCM, phypin_index[pin].bcm_id, value);
+}
+
+static int pin_read(struct rt_device *device, rt_base_t pin)
+{
+    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
+    {
+        rt_kprintf("pin:%d value wrongful", pin);
+        return 0;
+    }
+
+    return gpio_get_value(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
+}
+
+static rt_err_t pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
+    {
+        rt_kprintf("pin:%d value wrongful", pin);
+        return RT_ERROR;
+    }
+
+    gpio_set_irq_callback(GPIO_CODE_BCM , phypin_index[pin].bcm_id, hdr, args);
+    gpio_set_irq_type(GPIO_CODE_BCM, phypin_index[pin].bcm_id, mode);
+
+    return RT_EOK;
+}
+
+static rt_err_t pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
+    {
+        rt_kprintf("pin:%d value wrongful", pin);
+        return RT_ERROR;
+    }
+
+    gpio_clear_irq_callback(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
+
+    return RT_EOK;
+}
+
+rt_err_t pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
+    {
+        rt_kprintf("pin:%d value wrongful", pin);
+        return RT_ERROR;
+    }
+
+    if (enabled)
+        gpio_irq_enable(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
+    else
+        gpio_irq_disable(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
+
+    return RT_EOK;
+}
+
+static const struct rt_pin_ops ops =
+{
+    pin_mode,
+    pin_write,
+    pin_read,
+    pin_attach_irq,
+    pin_detach_irq,
+    pin_irq_enable,
+};
+#endif
+
+int rt_hw_gpio_init(void)
+{
+#ifdef BSP_USING_PIN
+    rt_device_pin_register("gpio", &ops, RT_NULL);
+#endif
+
+    /* install ISR */
+    rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO0);
+
+    rt_hw_interrupt_install(IRQ_GPIO1, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO1);
+
+    rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq");
+    rt_hw_interrupt_umask(IRQ_GPIO2);
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gpio_init);
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
new file mode 100644
index 0000000000..b0a67870ab
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rtdebug.h>
+#include <rtdbg.h>
+
+#include "interrupt.h"
+#include "bcm283x.h"
+#include "raspi.h"
+#include "board.h"
+
+#define GPIO_IRQ_NUM 3
+
+struct gpio_irq_def
+{
+    void  *irq_arg[32];
+    void (*irq_cb[32])(void *param);
+    rt_uint8_t irq_type[32];
+};
+
+enum gpio_irq_clock
+{
+    GPIO_IRQ_LOSC_32KHZ = 0,
+    GPIO_IRQ_HOSC_24MHZ
+};
+
+int rt_hw_gpio_init(void);
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c
new file mode 100644
index 0000000000..5163af60ee
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_i2c.h"
+
+#if defined (BSP_USING_I2C0)
+#define I2C1BUS_NAME  "i2c0"
+#endif /*BSP_USING_I2C0*/
+
+#if defined (BSP_USING_I2C1)
+#define I2C2BUS_NAME  "i2c1"
+#endif /*BSP_USING_I2C1*/
+
+static int i2c_byte_wait_us = 0;
+
+#ifdef BSP_USING_I2C0
+
+static struct raspi_i2c_bus raspi_i2c0 =
+{
+    .device_name = I2C1BUS_NAME,
+};
+
+static struct raspi_master_config_t raspi_i2c0_cfg =
+{
+    .sdl_pin = BCM_GPIO_PIN_0,
+    .scl_pin = BCM_GPIO_PIN_1,
+    .sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
+    .scl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
+    .slave_address = 8,
+    .bsc_base = (PER_BASE + BCM283X_BSC0_BASE),
+    .clk_div = BCM283X_I2C_CLOCK_DIVIDER_148,
+};
+
+#endif /* RT_USING_HW_I2C1 */
+
+#ifdef BSP_USING_I2C1
+static struct raspi_i2c_bus raspi_i2c1 =
+{
+    .device_name = I2C2BUS_NAME,
+};
+
+static struct raspi_master_config_t raspi_i2c1_cfg =
+{
+    .sdl_pin = BCM_GPIO_PIN_2,
+    .scl_pin = BCM_GPIO_PIN_3,
+    .sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
+    .scl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
+    .slave_address = 9,
+    .bsc_base = (PER_BASE + BCM283X_BSC1_BASE),
+    .clk_div = BCM283X_I2C_CLOCK_DIVIDER_148,
+};
+#endif /* RT_USING_HW_I2C2 */
+
+#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1))
+
+static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                      rt_uint32_t,
+                                      rt_uint32_t);
+
+void i2c_master_init(struct raspi_master_config_t *cfg)
+{
+    volatile rt_uint32_t addr;
+    rt_uint32_t data;
+
+    bcm283x_gpio_fsel(cfg->sdl_pin, cfg->sdl_pin_mode); /* SDA */
+    bcm283x_gpio_fsel(cfg->scl_pin, cfg->scl_pin_mode); /* SCL */
+
+    addr = cfg->bsc_base + BCM283X_BSC_DIV;
+    data = bcm283x_peri_read(addr);
+    i2c_byte_wait_us = ( data * 1000000 / BCM283X_CORE_CLK_HZ) * 9;
+
+    addr = cfg->bsc_base + BCM283X_BSC_DIV;
+    bcm283x_peri_write(addr, cfg->clk_div);
+
+    //update
+    i2c_byte_wait_us = (cfg->clk_div * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
+}
+
+static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    volatile rt_uint32_t addr;
+    struct raspi_i2c_bus *raspi_i2c;
+    rt_size_t i;
+    RT_ASSERT(bus != RT_NULL);
+    raspi_i2c = (struct raspi_i2c_bus *) bus;
+    raspi_i2c->msg = msgs;
+    raspi_i2c->msg_ptr = 0;
+    raspi_i2c->msg_cnt = num;
+    raspi_i2c->dptr = 0;
+
+    addr = raspi_i2c->cfg->bsc_base + BCM283X_BSC_A;
+    bcm283x_peri_write(addr, msgs->addr);
+
+    for (i = 0; i < num; i++)
+    {
+        if ( raspi_i2c->msg[i].flags & RT_I2C_RD )
+        {
+            bcm283x_i2c_read(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num);
+        }
+        else
+        {
+            bcm283x_i2c_write(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num);
+        }
+    }
+    raspi_i2c->msg = RT_NULL;
+    raspi_i2c->msg_ptr = 0;
+    raspi_i2c->msg_cnt = 0;
+    raspi_i2c->dptr = 0;
+    return i;
+}
+
+static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    return 0;
+}
+static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                      rt_uint32_t cmd,
+                                      rt_uint32_t arg)
+{
+    return RT_ERROR;
+}
+
+static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
+{
+    .master_xfer = raspi_i2c_mst_xfer,
+    .slave_xfer = raspi_i2c_slv_xfer,
+    .i2c_bus_control = raspi_i2c_bus_control,
+};
+
+static rt_err_t raspi_i2c_configure(struct raspi_i2c_bus *bus, struct raspi_master_config_t *cfg)
+{
+    RT_ASSERT(bus != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    bus->device.ops = &raspi_i2c_ops;
+    bus->cfg = cfg;
+
+    i2c_master_init(cfg);
+    return RT_EOK;
+}
+#endif
+
+int rt_hw_i2c_init(void)
+{
+
+#if defined(BSP_USING_I2C0)
+    raspi_i2c_configure(&raspi_i2c0 , &raspi_i2c0_cfg);
+    rt_i2c_bus_device_register(&raspi_i2c0.device, raspi_i2c0.device_name);
+#endif  /* BSP_USING_I2C1 */
+
+#if defined(BSP_USING_I2C1)
+
+    raspi_i2c_configure(&raspi_i2c1 , &raspi_i2c1_cfg);
+    rt_i2c_bus_device_register(&raspi_i2c1.device, raspi_i2c1.device_name);
+
+#endif  /* BSP_USING_I2C2 */
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h
new file mode 100644
index 0000000000..041d6b00db
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_I2C_H__
+#define __DRV_I2C_H__
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include <rtthread.h>
+#include "bcm283x.h"
+
+struct raspi_master_config_t
+{
+    rt_uint8_t sdl_pin;
+    rt_uint8_t scl_pin;
+    rt_uint8_t sdl_pin_mode;
+    rt_uint8_t scl_pin_mode;
+    rt_uint8_t slave_address;
+    rt_uint32_t bsc_base;
+    rt_uint16_t clk_div;
+};
+
+struct raspi_i2c_bus
+{
+    struct rt_i2c_bus_device device;
+    struct rt_i2c_msg *msg;
+    rt_uint32_t msg_cnt;
+    volatile rt_uint32_t msg_ptr;
+    volatile rt_uint32_t dptr;
+    char *device_name;
+    struct raspi_master_config_t *cfg;
+};
+
+int rt_hw_i2c_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c
new file mode 100644
index 0000000000..e38393bbd0
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+
+#include "drv_rtc.h"
+
+#ifdef BSP_USING_RTC
+
+static struct rt_rtc_device rtc_device;
+
+rt_uint8_t buf[]=
+{
+    0x00, 0x00, 0x43, 0x15, 0x05, 0x01, 0x03, 0x19
+};
+
+static time_t raspi_get_timestamp(void)
+{
+    struct tm tm_new = {0};
+    buf[0] = 0;
+    bcm283x_i2c_write_read_rs((char*)buf, 1, (char*)buf, 7);
+
+    tm_new.tm_year = ((buf[6] / 16) + 0x30) * 10 + (buf[6] % 16) + 0x30;
+    tm_new.tm_mon  = ((buf[5] & 0x1F) / 16 + 0x30) + (buf[5] & 0x1F) % 16+ 0x30;
+    tm_new.tm_mday = ((buf[4] & 0x3F) / 16 + 0x30) + (buf[4] & 0x3F) % 16+ 0x30;
+    tm_new.tm_hour = ((buf[2] & 0x3F) / 16 + 0x30) + (buf[2] & 0x3F) % 16+ 0x30;
+    tm_new.tm_min  = ((buf[1] & 0x7F) / 16 + 0x30) + (buf[1] & 0x7F) % 16+ 0x30;
+    tm_new.tm_sec  = ((buf[0] & 0x7F) / 16 + 0x30) + (buf[0] & 0x7F) % 16+ 0x30;
+
+    return mktime(&tm_new);
+}
+
+static int raspi_set_timestamp(time_t timestamp)
+{
+    struct tm *tblock;
+    tblock = localtime(&timestamp);
+    buf[0] = 0;
+    buf[1] = tblock->tm_sec;
+    buf[2] = tblock->tm_min;
+    buf[3] = tblock->tm_hour;
+    buf[4] = tblock->tm_wday;
+    buf[5] = tblock->tm_mday;
+    buf[6] = tblock->tm_mon;
+    buf[7] = tblock->tm_year;
+    bcm283x_i2c_write((PER_BASE + BCM283X_BSC0_BASE) ,buf, 8);
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_init(rt_device_t dev)
+{
+    bcm283x_i2c_setSlaveAddress(0, 0x68);
+    bcm283x_i2c_set_baudrate(0, 10000);
+    raspi_set_timestamp(0);
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    bcm283x_i2c_begin(0);
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_close(rt_device_t dev)
+{
+    bcm283x_i2c_end(0);
+    return RT_EOK;
+}
+
+static rt_err_t raspi_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+
+    RT_ASSERT(dev != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+        *(rt_uint32_t *)args = raspi_get_timestamp();
+        break;
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+        raspi_set_timestamp(*(time_t *)args);
+        break;
+    default:
+        return RT_EINVAL;
+    }
+    return RT_EOK;
+}
+
+static rt_size_t raspi_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer);
+    return size;
+}
+
+static rt_size_t raspi_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer);
+    return size;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops raspi_rtc_ops =
+{
+    .init = raspi_rtc_init,
+    .open = raspi_rtc_open,
+    .close = raspi_rtc_close,
+    .read = raspi_rtc_read,
+    .write = raspi_rtc_write,
+    .control = raspi_rtc_control
+};
+#endif
+
+int rt_hw_rtc_init(void)
+{
+    rt_memset(&rtc_device, 0, sizeof(rtc_device));
+
+    rtc_device.device.type        = RT_Device_Class_RTC;
+    rtc_device.device.rx_indicate = RT_NULL;
+    rtc_device.device.tx_complete = RT_NULL;
+    rtc_device.device.ops         = &raspi_rtc_ops;
+    rtc_device.device.user_data   = RT_NULL;
+
+    /* register a rtc device */
+    rt_device_register(&rtc_device.device, "rtc", RT_DEVICE_FLAG_RDWR);
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+#endif /* BSP_USING_RTC */
+
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h
new file mode 100644
index 0000000000..82306068ca
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_RTC_H__
+#define __DRV_RTC_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <time.h>
+#include "bcm283x.h"
+
+struct rt_rtc_device
+{
+    struct rt_device device;
+};
+
+int rt_hw_rtc_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c
new file mode 100644
index 0000000000..4f3018c0ef
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c
@@ -0,0 +1,532 @@
+/*
+ * File      : drv_sdio.c
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <string.h>
+
+#include "drv_sdio.h"
+#include "interrupt.h"
+#include "drv_gpio.h"
+
+#include "bcm283x.h"
+#include <drivers/mmcsd_core.h>
+#include "bcm283x.h"
+
+
+#include <rtdbg.h>
+
+#ifdef RT_USING_SDIO
+#define CONFIG_MMC_USE_DMA
+#define DMA_ALIGN       (32U)
+
+typedef struct EMMCCommand
+{
+    const char* name;
+    unsigned int code;
+    unsigned char resp;
+    unsigned char rca;
+    int delay;
+} EMMCCommand;
+
+static EMMCCommand sdCommandTable[] =
+{
+    {"GO_IDLE_STATE", 0x00000000 | CMD_RSPNS_NO                             , RESP_NO , RCA_NO  ,0},
+    {"ALL_SEND_CID" , 0x02000000 | CMD_RSPNS_136                            , RESP_R2I, RCA_NO  ,0},
+    {"SEND_REL_ADDR", 0x03000000 | CMD_RSPNS_48                             , RESP_R6 , RCA_NO  ,0},
+    {"SET_DSR"      , 0x04000000 | CMD_RSPNS_NO                             , RESP_NO , RCA_NO  ,0},
+    {"SWITCH_FUNC"  , 0x06000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"CARD_SELECT"  , 0x07000000 | CMD_RSPNS_48B                            , RESP_R1b, RCA_YES ,0},
+    {"SEND_IF_COND" , 0x08000000 | CMD_RSPNS_48                             , RESP_R7 , RCA_NO  ,100},
+    {"SEND_CSD"     , 0x09000000 | CMD_RSPNS_136                            , RESP_R2S, RCA_YES ,0},
+    {"SEND_CID"     , 0x0A000000 | CMD_RSPNS_136                            , RESP_R2I, RCA_YES ,0},
+    {"VOLT_SWITCH"  , 0x0B000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"STOP_TRANS"   , 0x0C000000 | CMD_RSPNS_48B                            , RESP_R1b, RCA_NO  ,0},
+    {"SEND_STATUS"  , 0x0D000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_YES ,0},
+    {"GO_INACTIVE"  , 0x0F000000 | CMD_RSPNS_NO                             , RESP_NO , RCA_YES ,0},
+    {"SET_BLOCKLEN" , 0x10000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"READ_SINGLE"  , 0x11000000 | CMD_RSPNS_48 | CMD_IS_DATA   | TM_DAT_DIR_CH, RESP_R1 , RCA_NO  ,0},
+    {"READ_MULTI"   , 0x12000000 | CMD_RSPNS_48 | TM_MULTI_DATA | TM_DAT_DIR_CH, RESP_R1 , RCA_NO  ,0},
+    {"SEND_TUNING"  , 0x13000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"SPEED_CLASS"  , 0x14000000 | CMD_RSPNS_48B                            , RESP_R1b, RCA_NO  ,0},
+    {"SET_BLOCKCNT" , 0x17000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"WRITE_SINGLE" , 0x18000000 | CMD_RSPNS_48 | CMD_IS_DATA   | TM_DAT_DIR_HC, RESP_R1 , RCA_NO  ,0},
+    {"WRITE_MULTI"  , 0x19000000 | CMD_RSPNS_48 | TM_MULTI_DATA | TM_DAT_DIR_HC, RESP_R1 , RCA_NO  ,0},
+    {"PROGRAM_CSD"  , 0x1B000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"SET_WRITE_PR" , 0x1C000000 | CMD_RSPNS_48B                            , RESP_R1b, RCA_NO  ,0},
+    {"CLR_WRITE_PR" , 0x1D000000 | CMD_RSPNS_48B                            , RESP_R1b, RCA_NO  ,0},
+    {"SND_WRITE_PR" , 0x1E000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"ERASE_WR_ST"  , 0x20000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"ERASE_WR_END" , 0x21000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"ERASE"        , 0x26000000 | CMD_RSPNS_48B                            , RESP_R1b, RCA_NO  ,0},
+    {"LOCK_UNLOCK"  , 0x2A000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"APP_CMD"      , 0x37000000 | CMD_RSPNS_NO                             , RESP_NO , RCA_NO  ,100},
+    {"APP_CMD"      , 0x37000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_YES ,0},
+    {"GEN_CMD"      , 0x38000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+
+  // APP commands must be prefixed by an APP_CMD.
+    {"SET_BUS_WIDTH", 0x06000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"SD_STATUS"    , 0x0D000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_YES ,0}, // RCA???
+    {"SEND_NUM_WRBL", 0x16000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"SEND_NUM_ERS" , 0x17000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"SD_SENDOPCOND", 0x29000000 | CMD_RSPNS_48                             , RESP_R3 , RCA_NO  ,1000},
+    {"SET_CLR_DET"  , 0x2A000000 | CMD_RSPNS_48                             , RESP_R1 , RCA_NO  ,0},
+    {"SEND_SCR"     , 0x33000000 | CMD_RSPNS_48 | CMD_IS_DATA | TM_DAT_DIR_CH   , RESP_R1 , RCA_NO  ,0},
+};
+
+static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width);
+static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock);
+static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat);
+
+static inline rt_uint32_t read32(rt_uint32_t addr)
+{
+    return( *((volatile rt_uint32_t *)(addr)) );
+}
+
+static inline void write32(rt_uint32_t addr, rt_uint32_t value)
+{
+    *((volatile rt_uint32_t *)(addr)) = value;
+}
+
+static rt_err_t raspi_transfer_command(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd)
+{
+    rt_uint32_t cmdidx;
+    rt_uint32_t status;
+    rt_err_t ret = RT_EOK;
+
+    if(read32(pdat->virt + EMMC_STATUS) & SR_CMD_INHIBIT)
+        write32(pdat->virt + EMMC_CMDTM, 0x0);
+
+    EMMCCommand* cmdtab = &sdCommandTable[cmd->cmdidx];
+
+    cmdidx = cmdtab->code;
+
+    write32(pdat->virt + EMMC_ARG1, cmd->cmdarg);
+    write32(pdat->virt + EMMC_CMDTM, cmdidx);
+
+    do {
+        status = read32(pdat->virt + EMMC_STATUS);
+    } while(!(status & SR_CMD_INHIBIT));
+
+    if(cmd->resptype & RESP_MASK)
+    {
+        cmd->response[0] = read32(pdat->virt + EMMC_RESP0);
+        if(cmd->resptype & RESP_R2)
+        {
+            cmd->response[1] = read32(pdat->virt + EMMC_RESP1);
+            cmd->response[2] = read32(pdat->virt + EMMC_RESP2);
+            cmd->response[3] = read32(pdat->virt + EMMC_RESP3);
+        }
+    }
+
+    return ret;
+}
+
+static rt_err_t read_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
+{
+    rt_uint32_t * tmp = buf;
+    rt_uint32_t count = blkcount * blksize;
+    rt_uint32_t status, err;
+
+//    status = read32(pdat->virt + PL180_STATUS);
+//    err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_RX_OVERRUN);
+//    while((!err) && (count >= sizeof(rt_uint32_t)))
+//    {
+//        if(status & PL180_STAT_RX_FIFO_AVL)
+//        {
+//            *(tmp) = read32(pdat->virt + PL180_FIFO);
+//            tmp++;
+//            count -= sizeof(rt_uint32_t);
+//        }
+//        status = read32(pdat->virt + PL180_STATUS);
+//        err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_RX_OVERRUN);
+//    }
+//
+//    err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END | PL180_STAT_RX_OVERRUN);
+//    while(!err)
+//    {
+//        status = read32(pdat->virt + PL180_STATUS);
+//        err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END | PL180_STAT_RX_OVERRUN);
+//    }
+//
+//    if(status & PL180_STAT_DAT_TIME_OUT)
+//        return -RT_ERROR;
+//    else if (status & PL180_STAT_DAT_CRC_FAIL)
+//        return -RT_ERROR;
+//    else if (status & PL180_STAT_RX_OVERRUN)
+//        return -RT_ERROR;
+//    write32(pdat->virt + PL180_CLEAR, 0x1DC007FF);
+//
+//    if(count)
+//        return -RT_ERROR;
+
+    return RT_EOK;
+}
+
+static rt_err_t write_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
+{
+    rt_uint32_t * tmp = buf;
+    rt_uint32_t count = blkcount * blksize;
+    rt_uint32_t status, err;
+    int i;
+
+//    status = read32(pdat->virt + PL180_STATUS);
+//    err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT);
+//    while(!err && count)
+//    {
+//        if(status & PL180_STAT_TX_FIFO_HALF)
+//        {
+//            if(count >= 8 * sizeof(rt_uint32_t))
+//            {
+//                for(i = 0; i < 8; i++)
+//                    write32(pdat->virt + PL180_FIFO, *(tmp + i));
+//                tmp += 8;
+//                count -= 8 * sizeof(rt_uint32_t);
+//            }
+//            else
+//            {
+//                while(count >= sizeof(rt_uint32_t))
+//                {
+//                    write32(pdat->virt + PL180_FIFO, *tmp);
+//                    tmp++;
+//                    count -= sizeof(rt_uint32_t);
+//                }
+//            }
+//        }
+//        status = read32(pdat->virt + PL180_STATUS);
+//        err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT);
+//    }
+//
+//    err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END);
+//    while(!err)
+//    {
+//        status = read32(pdat->virt + PL180_STATUS);
+//        err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END);
+//    }
+//
+//    if(status & PL180_STAT_DAT_TIME_OUT)
+//        return -RT_ERROR;
+//    else if (status & PL180_STAT_DAT_CRC_FAIL)
+//        return -RT_ERROR;
+//    write32(pdat->virt + PL180_CLEAR, 0x1DC007FF);
+//
+//    if(count)
+//        return -RT_ERROR;
+    return RT_EOK;
+}
+
+static rt_err_t raspi_transfer_data(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
+{
+    rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz);
+    rt_uint32_t blksz_bits = dat->blksz - 1;
+    rt_err_t ret = -RT_ERROR;
+
+    write32(pdat->virt + EMMC_BLKSIZECNT, dlen);
+
+    if(dat->flag & DATA_DIR_READ)
+    {
+        write32(pdat->virt + EMMC_STATUS, SR_READ_TRANSFER);
+        ret = raspi_transfer_command(pdat, cmd);
+        if (ret < 0) return ret;
+        ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
+    }
+    else if(dat->flag & DATA_DIR_WRITE)
+    {
+        ret = raspi_transfer_command(pdat, cmd);
+        if (ret < 0) return ret;
+        write32(pdat->virt + EMMC_STATUS, SR_WRITE_TRANSFER);
+        ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
+    }
+
+    return ret;
+}
+
+static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data;
+    struct sdhci_cmd_t cmd;
+    struct sdhci_cmd_t stop;
+    struct sdhci_data_t dat;
+
+    rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t));
+    rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t));
+    rt_memset(&dat, 0, sizeof(struct sdhci_data_t));
+
+    cmd.cmdidx = req->cmd->cmd_code;
+    EMMCCommand* cmdtab = &sdCommandTable[cmd.cmdidx];
+    cmd.cmdarg = req->cmd->arg;
+    cmd.resptype = cmdtab->resp;
+
+    if(req->data)
+    {
+        dat.buf = (rt_uint8_t *)req->data->buf;
+        dat.flag = req->data->flags;
+        dat.blksz = req->data->blksize;
+        dat.blkcnt = req->data->blks;
+
+        req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat);
+    }
+    else
+    {
+        req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL);
+    }
+
+    req->cmd->resp[3] = cmd.response[3];
+    req->cmd->resp[2] = cmd.response[2];
+    req->cmd->resp[1] = cmd.response[1];
+    req->cmd->resp[0] = cmd.response[0];
+
+    if (req->stop)
+    {
+        stop.cmdidx = req->stop->cmd_code;
+        cmdtab = &sdCommandTable[cmd.cmdidx];
+        stop.cmdarg = req->stop->arg;
+        cmd.resptype = cmdtab->resp;
+
+        req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL);
+    }
+
+    mmcsd_req_complete(host);
+}
+
+
+static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
+{
+    struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
+
+    if(!dat)
+        return raspi_transfer_command(pdat, cmd);
+
+    return raspi_transfer_data(pdat, cmd, dat);
+}
+
+
+//#ifdef CONFIG_MMC_USE_DMA
+//#ifdef BSP_USING_SDIO0
+////ALIGN(32) static rt_uint8_t dma_buffer[64 * 1024];
+//static rt_uint8_t dma_buffer[64 * 1024];
+//#endif
+//#endif
+
+
+static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+    struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data;
+    sdhci_setclock(sdhci, io_cfg->clock);
+    sdhci_setwidth(sdhci, io_cfg->bus_width);
+}
+
+rt_int32_t mmc_card_status(struct rt_mmcsd_host *host)
+{
+    return 0;
+}
+
+void mmc_enable_irq(struct rt_mmcsd_host *host, rt_int32_t en)
+{
+
+}
+
+static rt_err_t sdhci_detect(struct sdhci_t * sdhci)
+{
+    return RT_EOK;
+}
+
+static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width)
+{
+    rt_uint32_t temp = 0;
+    struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
+    temp = read32((pdat->virt + EMMC_CONTROL0));
+    temp |= C0_HCTL_HS_EN;
+    temp |= C0_HCTL_DWITDH;   // always use 4 data lines:
+    write32((pdat->virt + EMMC_CONTROL0), temp);
+
+    return RT_EOK;
+}
+
+static rt_uint32_t sdhci_getdivider( rt_uint32_t sdHostVer, rt_uint32_t freq )
+{
+    rt_uint32_t divisor;
+    rt_uint32_t closest = 41666666 / freq;
+    rt_uint32_t shiftcount = __rt_fls(closest - 1);
+
+
+    if (shiftcount > 0) shiftcount--;
+    if (shiftcount > 7) shiftcount = 7;
+    if (sdHostVer > HOST_SPEC_V2)
+        divisor = closest;
+    else
+        divisor = (1 << shiftcount);
+
+    if (divisor <= 2) {
+        divisor = 2;
+        shiftcount = 0;
+    }
+
+    rt_uint32_t hi = 0;
+    if (sdHostVer > HOST_SPEC_V2)
+        hi = (divisor & 0x300) >> 2;
+    rt_uint32_t lo = (divisor & 0x0ff);
+    rt_uint32_t cdiv = (lo << 8) + hi;
+    return cdiv;
+}
+
+static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
+{
+    rt_uint32_t temp = 0;
+    rt_uint32_t sdHostVer = 0;
+    int count = 100000;
+    struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv;
+
+    temp = read32(pdat->virt + EMMC_STATUS);
+    while((temp & (SR_CMD_INHIBIT | SR_DAT_INHIBIT))&&(--count))
+        bcm283x_clo_delayMicros(1);
+
+    if( count <= 0 )
+    {
+        rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n", temp);
+        return RT_ERROR;
+    }
+
+    // Switch clock off.
+    temp = read32((pdat->virt + EMMC_CONTROL1));
+    temp |= ~C1_CLK_EN;
+    write32((pdat->virt + EMMC_CONTROL1),temp);
+
+    bcm283x_clo_delayMicros(10);
+
+    // Request the new clock setting and enable the clock
+    temp = read32(pdat->virt + EMMC_SLOTISR_VER);
+    sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT;
+
+    int cdiv = sdhci_getdivider(sdHostVer, clock);
+    temp = read32((pdat->virt + EMMC_CONTROL1));
+    temp = (temp & 0xffff003f) | cdiv;
+    write32((pdat->virt + EMMC_CONTROL1),temp);
+    bcm283x_clo_delayMicros(10);
+
+    // Enable the clock.
+    temp = read32(pdat->virt + EMMC_CONTROL1);
+    temp |= C1_CLK_EN;
+    write32((pdat->virt + EMMC_CONTROL1),temp);
+    bcm283x_clo_delayMicros(10);
+
+    // Wait for clock to be stable.
+    count = 10000;
+    temp = read32(pdat->virt + EMMC_CONTROL1);
+    while( !(temp & C1_CLK_STABLE) && count-- )
+        bcm283x_clo_delayMicros(10);
+
+    if( count <= 0 )
+    {
+        rt_kprintf("EMMC: ERROR: failed to get stable clock.\n");
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static const struct rt_mmcsd_host_ops ops =
+{
+    mmc_request_send,
+    mmc_set_iocfg,
+    RT_NULL,
+    RT_NULL,
+};
+
+static void sdmmc_gpio_init()
+{
+    int pin;
+
+    for (pin = BCM_GPIO_PIN_48; pin <= BCM_GPIO_PIN_53; pin++)
+    {
+        bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
+        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_ALT3);
+    }
+    bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
+    bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
+}
+
+int raspi_sdmmc_init(void)
+{
+    rt_uint32_t virt;
+    rt_uint32_t id;
+    struct rt_mmcsd_host * host = RT_NULL;
+    struct sdhci_pdata_t * pdat = RT_NULL;
+    struct sdhci_t * sdhci = RT_NULL;
+
+    rt_kprintf("raspi_sdmmc_init start\n");
+
+#ifdef BSP_USING_SDIO0
+    host = mmcsd_alloc_host();
+    if (!host)
+    {
+        rt_kprintf("alloc host failed");
+        goto err;
+    }
+
+    sdhci = rt_malloc(sizeof(struct sdhci_t));
+    if (!sdhci)
+    {
+        rt_kprintf("alloc sdhci failed");
+        goto err;
+    }
+    rt_memset(sdhci, 0, sizeof(struct sdhci_t));
+
+    rt_kprintf(">> sdmmc_gpio_init\n");
+    sdmmc_gpio_init();
+    rt_kprintf("<< sdmmc_gpio_init\n");
+
+    virt = MMC0_BASE_ADDR;
+
+    pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t));
+    RT_ASSERT(pdat != RT_NULL);
+
+    pdat->virt = (rt_uint32_t)virt;
+
+    sdhci->name = "sd0";
+    sdhci->voltages = VDD_33_34;
+    sdhci->width = MMCSD_BUSWIDTH_4;
+    sdhci->clock = 26 * 1000 * 1000;
+    sdhci->removeable = RT_TRUE;
+
+    sdhci->detect = sdhci_detect;
+    sdhci->setwidth = sdhci_setwidth;
+    sdhci->setclock = sdhci_setclock;
+    sdhci->transfer = sdhci_transfer;
+    sdhci->priv = pdat;
+    //write32(pdat->virt + PL180_POWER, 0xbf);
+
+    host->ops = &ops;
+    host->freq_min = 400000;
+    host->freq_max = 50000000;
+    host->valid_ocr = VDD_32_33 | VDD_33_34;
+    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
+    host->max_seg_size = 2048;
+    host->max_dma_segs = 10;
+    host->max_blk_size = 512;
+    host->max_blk_count = 4096;
+
+    host->private_data = sdhci;
+
+    mmcsd_change(host);
+
+    return RT_EOK;
+
+err:
+    if(host)  rt_free(host);
+    if(sdhci) rt_free(sdhci);
+
+    return -RT_EIO;
+#endif
+}
+INIT_APP_EXPORT(raspi_sdmmc_init);
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h
new file mode 100644
index 0000000000..8ab10aebb6
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h
@@ -0,0 +1,345 @@
+/*
+ * File      : drv_sdio.h
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+#include <rtthread.h>
+
+#define MMC0_BASE_ADDR     0x20300000
+
+struct raspi_mmc
+{
+    volatile rt_uint32_t arg2_reg;            /* (0x000) */
+    volatile rt_uint32_t blksizecnt_reg;      /* (0x004) */
+    volatile rt_uint32_t arg1_reg;            /* (0x008) */
+    volatile rt_uint32_t cmdtm_reg;           /* (0x00C) */
+    volatile rt_uint32_t resp0_reg;            /* (0x010) */
+    volatile rt_uint32_t resp1_reg;            /* (0x014) */
+    volatile rt_uint32_t resp2_reg;            /* (0x018) */
+    volatile rt_uint32_t resp3_reg;            /* (0x01C) */
+    volatile rt_uint32_t data_reg;           /* (0x020) */
+    volatile rt_uint32_t status_reg;           /* (0x024) */
+    volatile rt_uint32_t control0_reg;           /* (0x028) */
+    volatile rt_uint32_t control1_reg;           /* (0x02C) */
+    volatile rt_uint32_t interrupt_reg;            /* (0x030) */
+    volatile rt_uint32_t irpt_mask_reg;            /* (0x034) */
+    volatile rt_uint32_t irpt_en_reg;            /* (0x038) */
+    volatile rt_uint32_t control2_reg;            /* (0x03C) */
+    volatile rt_uint32_t reserved1[4];            /* (0x040) */
+    volatile rt_uint32_t force_irpt_reg;            /* (0x050) */
+    volatile rt_uint32_t reserved2[7];            /* (0x054) */
+    volatile rt_uint32_t boot_timeout_reg;            /* (0x070) */
+    volatile rt_uint32_t deg_sel_reg;            /* (0x074) */
+    volatile rt_uint32_t reserved3[2];            /* (0x078) */
+    volatile rt_uint32_t exrdfifo_cfg_reg;      /* (0x080) */
+    volatile rt_uint32_t exrdfifo_cn_reg;       /* (0x084) */
+    volatile rt_uint32_t tune_step_reg;        /* (0x088) */
+    volatile rt_uint32_t tune_step_std_reg;    /* (0x08C) */
+    volatile rt_uint32_t tune_step_ddr_reg;       /* (0x090) */
+    volatile rt_uint32_t reserved4[23];            /* (0x094) */
+    volatile rt_uint32_t spi_int_reg;            /* (0x0f0) */
+    volatile rt_uint32_t reserved5[2];            /* (0x0f4) */
+    volatile rt_uint32_t slotisr_ver_reg;            /* (0x0fC) */
+};
+
+typedef struct raspi_mmc *raspi_mmc_t;
+
+#define MMC0    ((tina_mmc_t)MMC0_BASE_ADDR)
+
+
+#define BIT(x)              (1<<(x))
+
+/* Struct for Intrrrupt Information */
+#define SDXC_CmdDone       BIT(0)
+#define SDXC_DataDone      BIT(1)
+#define SDXC_BlockGap      BIT(2)
+#define SDXC_WriteRdy      BIT(4)
+#define SDXC_ReadRdy       BIT(5)
+#define SDXC_Card          BIT(8)
+#define SDXC_Retune        BIT(12)
+#define SDXC_BootAck       BIT(13)
+#define SDXC_EndBoot       BIT(14)
+#define SDXC_Err              BIT(15)
+#define SDXC_CTOErr        BIT(16)
+#define SDXC_CCRCErr       BIT(17)
+#define SDXC_CENDErr       BIT(18)
+#define SDXC_CBADErr       BIT(19)
+#define SDXC_DTOErr        BIT(20)
+#define SDXC_DCRCErr       BIT(21)
+#define SDXC_DENDErr       BIT(22)
+#define SDXC_ACMDErr       BIT(24)
+
+
+/*
+    SD CMD reg
+REG[0-5] : Cmd ID
+REG[6]   : Has response
+REG[7]   : Long response
+REG[8]   : Check response CRC
+REG[9]   : Has data
+REG[10]  : Write
+REG[11]  : Steam mode
+REG[12]  : Auto stop
+REG[13]  : Wait previous over
+REG[14]  : About cmd
+REG[15]  : Send initialization
+REG[21]  : Update clock
+REG[31]  : Load cmd
+*/
+
+
+#define SDXC_BLKCNT_EN          BIT(1)
+#define SDXC_AUTO_CMD12_EN      BIT(2)
+#define SDXC_AUTO_CMD23_EN      BIT(3)
+#define SDXC_DAT_DIR              BIT(4)   //from card to host
+#define SDXC_MULTI_BLOCK        BIT(5)
+#define SDXC_CMD_RSPNS_136         BIT(16)
+#define SDXC_CMD_RSPNS_48         BIT(17)
+#define SDXC_CMD_RSPNS_48busy   BIT(16)|BIT(17)
+#define SDXC_CHECK_CRC_CMD      BIT(19)
+#define SDXC_CMD_IXCHK_EN       BIT(20)
+#define SDXC_CMD_ISDATA         BIT(21)
+#define SDXC_CMD_SUSPEND        BIT(22)
+#define SDXC_CMD_RESUME         BIT(23)
+#define SDXC_CMD_ABORT          BIT(23)|BIT(22)
+
+//#define SDXC_CHECK_CRC_CMD      BIT(19)
+//
+//#define SDXC_RESPONSE_CMD        BIT(6)
+//#define SDXC_LONG_RESPONSE_CMD   BIT(7)
+//#define SDXC_CHECK_CRC_CMD       BIT(8)
+//#define SDXC_HAS_DATA_CMD        BIT(9)
+//#define SDXC_WRITE_CMD           BIT(10)
+//#define SDXC_STEAM_CMD           BIT(11)
+//#define SDXC_AUTO_STOP_CMD       BIT(12)
+//#define SDXC_WAIT_OVER_CMD       BIT(13)
+//#define SDXC_ABOUT_CMD           BIT(14)
+//#define SDXC_SEND_INIT_CMD       BIT(15)
+//#define SDXC_UPDATE_CLOCK_CMD    BIT(21)
+//#define SDXC_LOAD_CMD            BIT(31)
+
+/* 
+    SD status reg 
+REG[0]   : FIFO_RX_LEVEL
+REG[1]   : FIFO_TX_LEVEL
+REG[2]   : FIFO_EMPTY
+REG[3]   : FIFO_FULL
+REG[4-7] : FSM_STA
+REG[8]   : CARD_PRESENT
+REG[9]   : CARD_BUSY
+REG[10]  : FSM_BUSY
+REG[11-16]: RESP_IDX 
+REG[17-21]: FIFO_LEVEL
+REG[31]   : DMA_REQ
+*/
+
+#define SDXC_CMD_INHIBIT    BIT(0)
+#define SDXC_DAT_INHIBIT    BIT(1)
+#define SDXC_DAT_ACTIVE     BIT(2)
+#define SDXC_WRITE_TRANSFER     BIT(8)
+#define SDXC_READ_TRANSFER     BIT(9)
+
+//
+//
+//#define SDXC_FIFO_RX_LEVEL    BIT(0)
+//#define SDXC_FIFO_TX_LEVEL    BIT(1)
+//#define SDXC_FIFO_EMPTY       BIT(2)
+//#define SDXC_FIFO_FULL        BIT(3)
+//#define SDXC_CARD_PRESENT     BIT(8)
+//#define SDXC_CARD_BUSY        BIT(9)
+//#define SDXC_FSM_BUSY         BIT(10)
+//#define SDXC_DMA_REQ          BIT(31)
+
+struct mmc_des_v4p1
+{
+    rt_uint32_t                         : 1,
+                    dic                 : 1, /* disable interrupt on completion                                    */
+                    last_des            : 1, /* 1-this data buffer is the last buffer                              */
+                    first_des           : 1, /* 1-data buffer is the first buffer,0-data buffer contained in the next descriptor is 1st buffer        */
+                    des_chain           : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */
+                    end_of_ring         : 1, /* 1-last descriptor flag when using dual data buffer in descriptor   */
+                                        : 24,
+                    card_err_sum        : 1, /* transfer error flag                                                */
+                    own                 : 1; /* des owner:1-idma owns it, 0-host owns it                           */
+
+#define SDXC_DES_NUM_SHIFT 12  /* smhc2!! */
+#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
+    rt_uint32_t data_buf1_sz     : 16,
+                data_buf2_sz     : 16;
+    rt_uint32_t buf_addr_ptr1;
+    rt_uint32_t buf_addr_ptr2;
+};
+
+struct sdhci_cmd_t
+{
+    rt_uint32_t cmdidx;
+    rt_uint32_t cmdarg;
+    //const char* name;
+   // rt_uint32_t code;
+    rt_uint32_t resptype;
+  //  rt_uint8_t rca;
+  //  rt_uint32_t delay;
+    rt_uint32_t response[4];
+};
+
+struct sdhci_data_t
+{
+    rt_uint8_t * buf;
+    rt_uint32_t flag;
+    rt_uint32_t blksz;
+    rt_uint32_t blkcnt;
+};
+
+struct sdhci_t
+{
+    char * name;
+    rt_uint32_t voltages;
+    rt_uint32_t width;
+    rt_uint32_t clock;
+    rt_err_t removeable;
+    void * sdcard;
+
+    rt_err_t (*detect)(struct sdhci_t * sdhci);
+    rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width);
+    rt_err_t (*setclock)(struct sdhci_t * sdhci, rt_uint32_t clock);
+    rt_err_t (*transfer)(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat);
+    void * priv;
+};
+
+struct sdhci_pdata_t
+{
+    rt_uint32_t virt;
+};
+
+// EMMC command flags
+#define CMD_TYPE_NORMAL  0x00000000
+#define CMD_TYPE_SUSPEND 0x00400000
+#define CMD_TYPE_RESUME  0x00800000
+#define CMD_TYPE_ABORT   0x00c00000
+#define CMD_IS_DATA      0x00200000
+#define CMD_IXCHK_EN     0x00100000
+#define CMD_CRCCHK_EN    0x00080000
+#define CMD_RSPNS_NO     0x00000000
+#define CMD_RSPNS_136    0x00010000
+#define CMD_RSPNS_48     0x00020000
+#define CMD_RSPNS_48B    0x00030000
+#define TM_MULTI_BLOCK   0x00000020
+#define TM_DAT_DIR_HC    0x00000000
+#define TM_DAT_DIR_CH    0x00000010
+#define TM_AUTO_CMD23    0x00000008
+#define TM_AUTO_CMD12    0x00000004
+#define TM_BLKCNT_EN     0x00000002
+#define TM_MULTI_DATA    (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN)
+
+// Response types.
+// Note that on the PI, the index and CRC are dropped, leaving 32 bits in RESP0.
+#define RESP_NO    0     // No response
+//#define RESP_R1    1     // 48  RESP0    contains card status
+#define RESP_R1b  11     // 48  RESP0    contains card status, data line indicates busy
+#define RESP_R2I   2     // 136 RESP0..3 contains 128 bit CID shifted down by 8 bits as no CRC
+#define RESP_R2S  12     // 136 RESP0..3 contains 128 bit CSD shifted down by 8 bits as no CRC
+//#define RESP_R3    3     // 48  RESP0    contains OCR register
+//#define RESP_R6    6     // 48  RESP0    contains RCA and status bits 23,22,19,12:0
+//#define RESP_R7    7     // 48  RESP0    contains voltage acceptance and check pattern
+
+#define RCA_NO     1
+#define RCA_YES    2
+
+// INTERRUPT register settings
+#define INT_AUTO_ERROR   0x01000000
+#define INT_DATA_END_ERR 0x00400000
+#define INT_DATA_CRC_ERR 0x00200000
+#define INT_DATA_TIMEOUT 0x00100000
+#define INT_INDEX_ERROR  0x00080000
+#define INT_END_ERROR    0x00040000
+#define INT_CRC_ERROR    0x00020000
+#define INT_CMD_TIMEOUT  0x00010000
+#define INT_ERR          0x00008000
+#define INT_ENDBOOT      0x00004000
+#define INT_BOOTACK      0x00002000
+#define INT_RETUNE       0x00001000
+#define INT_CARD         0x00000100
+#define INT_READ_RDY     0x00000020
+#define INT_WRITE_RDY    0x00000010
+#define INT_BLOCK_GAP    0x00000004
+#define INT_DATA_DONE    0x00000002
+#define INT_CMD_DONE     0x00000001
+#define INT_ERROR_MASK   (INT_CRC_ERROR|INT_END_ERROR|INT_INDEX_ERROR| \
+                          INT_DATA_TIMEOUT|INT_DATA_CRC_ERR|INT_DATA_END_ERR| \
+                          INT_ERR|INT_AUTO_ERROR)
+#define INT_ALL_MASK     (INT_CMD_DONE|INT_DATA_DONE|INT_READ_RDY|INT_WRITE_RDY|INT_ERROR_MASK)
+
+#define EMMC_ARG2         (0x00)
+#define EMMC_BLKSIZECNT   (0x04)
+#define EMMC_ARG1         (0x08)
+#define EMMC_CMDTM        (0x0c)
+#define EMMC_RESP0        (0x10)
+#define EMMC_RESP1        (0x14)
+#define EMMC_RESP2        (0x18)
+#define EMMC_RESP3        (0x1c)
+#define EMMC_DATA         (0x20)
+#define EMMC_STATUS       (0x24)
+#define EMMC_CONTROL0     (0x28)
+#define EMMC_CONTROL1     (0x2c)
+#define EMMC_INTERRUPT    (0x30)
+#define EMMC_IRPT_MASK    (0x34)
+#define EMMC_IRPT_EN      (0x38)
+#define EMMC_CONTROL2     (0x3c)
+#define EMMC_BOOT_TIMEOUT (0x70)
+#define EMMC_EXRDFIFO_EN  (0x84)
+#define EMMC_SPI_INT_SPT  (0xf0)
+#define EMMC_SLOTISR_VER  (0xfc)
+
+// CONTROL register settings
+#define C0_SPI_MODE_EN   0x00100000
+#define C0_HCTL_HS_EN    0x00000004
+#define C0_HCTL_DWITDH   0x00000002
+
+#define C1_SRST_DATA     0x04000000
+#define C1_SRST_CMD      0x02000000
+#define C1_SRST_HC       0x01000000
+#define C1_TOUNIT_DIS    0x000f0000
+#define C1_TOUNIT_MAX    0x000e0000
+#define C1_CLK_GENSEL    0x00000020
+#define C1_CLK_EN        0x00000004
+#define C1_CLK_STABLE    0x00000002
+#define C1_CLK_INTLEN    0x00000001
+
+#define FREQ_SETUP           400000  // 400 Khz
+#define FREQ_NORMAL        25000000  // 25 Mhz
+
+// SLOTISR_VER values
+#define HOST_SPEC_NUM              0x00ff0000
+#define HOST_SPEC_NUM_SHIFT        16
+#define HOST_SPEC_V3               2
+#define HOST_SPEC_V2               1
+#define HOST_SPEC_V1               0
+
+// STATUS register settings
+#define SR_DAT_LEVEL1        0x1e000000
+#define SR_CMD_LEVEL         0x01000000
+#define SR_DAT_LEVEL0        0x00f00000
+#define SR_DAT3              0x00800000
+#define SR_DAT2              0x00400000
+#define SR_DAT1              0x00200000
+#define SR_DAT0              0x00100000
+#define SR_WRITE_PROT        0x00080000  // From SDHC spec v2, BCM says reserved
+#define SR_READ_AVAILABLE    0x00000800  // ???? undocumented
+#define SR_WRITE_AVAILABLE   0x00000400  // ???? undocumented
+#define SR_READ_TRANSFER     0x00000200
+#define SR_WRITE_TRANSFER    0x00000100
+#define SR_DAT_ACTIVE        0x00000004
+#define SR_DAT_INHIBIT       0x00000002
+#define SR_CMD_INHIBIT       0x00000001
+
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
new file mode 100644
index 0000000000..041a97b510
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include "drv_spi.h"
+
+#if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1)
+#ifdef RT_USING_SPI
+#undef RT_USING_SPI
+#endif
+#endif
+
+#ifdef RT_USING_SPI
+
+
+static rt_uint8_t bcm2835_spi_bit_order = BCM283X_SPI_BIT_ORDER_MSBFIRST;
+static rt_uint8_t bcm2835_byte_reverse_table[] =
+{
+    0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+    0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+    0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+    0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+    0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+    0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+    0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+    0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+    0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+    0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+    0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+    0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+    0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+    0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+    0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+    0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+    0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+    0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+    0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+    0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+    0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+    0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+    0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+    0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+    0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+    0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+    0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+    0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+    0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+    0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+    0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+    0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
+};
+
+#define BSP_SPI_MAX_HZ (30* 1000 *1000)
+#define SPITIMEOUT 0x0FFF
+
+struct rt_spi_hw_config
+{
+    rt_int8_t sclk_pin;
+    rt_int8_t sclk_mode;
+    rt_int8_t mosi_pin;
+    rt_int8_t mosi_mode;
+    rt_int8_t miso_pin;
+    rt_int8_t miso_mode;
+    rt_int8_t cs_pin;
+    rt_int8_t cs_mode;
+    rt_uint32_t spi_base;
+    rt_uint32_t clk_div;
+};
+
+struct rt_sw_spi_cs
+{
+    rt_uint32_t pin;
+};
+
+struct rt_spi
+{
+    char *device_name;
+    struct rt_spi_bus *spi_bus;
+    struct rt_spi_hw_config *hwcfg;
+    struct rt_spi_configuration *cfg;
+};
+
+static rt_err_t raspi_hostspi_init(struct rt_spi_configuration *cfg)
+{
+
+    volatile rt_uint32_t addr = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_CS;
+    //volatile rt_uint32_t fifo = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_FIFO;
+
+    // spi clear fifo
+    bcm283x_peri_set_bits(addr, BCM283X_SPI0_CS_CLEAR, BCM283X_SPI0_CS_CLEAR);
+
+    //    /* Set TA = 1 */
+    //    bcm2835_peri_set_bits(addr, BCM283X_SPI0_CS_TA, BCM283X_SPI0_CS_TA);
+
+    /* Mask in the CPO and CPHA bits of CS */
+
+    bcm283x_peri_set_bits(addr,  (rt_uint32_t)(cfg->mode << 2), BCM283X_SPI0_CS_CPOL | BCM283X_SPI0_CS_CPHA);
+
+    //chipSelect
+    bcm283x_peri_set_bits(addr, BCM283X_SPI_CS0, BCM283X_SPI0_CS_CS);
+
+    rt_uint8_t shift = 21 + BCM283X_SPI_CS0;
+    /* Mask in the appropriate CSPOLn bit */
+    bcm283x_peri_set_bits(addr, LOW << shift, 1 << shift);
+
+
+    if(cfg->max_hz > BSP_SPI_MAX_HZ)
+    {
+        cfg->max_hz = BSP_SPI_MAX_HZ;
+    }
+
+    volatile rt_uint32_t clk_addr = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_CLK;
+    bcm283x_peri_write(clk_addr, cfg->max_hz);
+
+    return RT_EOK;
+}
+
+static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
+{
+    RT_ASSERT(cfg != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
+
+    struct rt_spi *hspi = (struct rt_spi *)&device->bus->parent;
+    hspi->cfg = cfg;
+
+    raspi_hostspi_init(cfg);
+
+    return RT_EOK;
+}
+
+
+rt_uint8_t correct_order(rt_uint8_t b)
+{
+    if (bcm2835_spi_bit_order == BCM283X_SPI_BIT_ORDER_LSBFIRST)
+        return bcm2835_byte_reverse_table[b];
+    else
+        return b;
+}
+
+static rt_err_t  spi_transfernb(rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len)
+{
+    volatile rt_uint32_t paddr = SPI0_BASE_ADDR + BCM283X_SPI0_CS;
+    volatile rt_uint32_t fifo = SPI0_BASE_ADDR + BCM283X_SPI0_FIFO;
+    rt_uint32_t TXCnt=0;
+    rt_uint32_t RXCnt=0;
+
+    /* Clear TX and RX fifos */
+    bcm283x_peri_set_bits(paddr, BCM283X_SPI0_CS_CLEAR, BCM283X_SPI0_CS_CLEAR);
+
+    /* Set TA = 1 */
+    bcm283x_peri_set_bits(paddr, BCM283X_SPI0_CS_TA, BCM283X_SPI0_CS_TA);
+
+    /* Use the FIFO's to reduce the interbyte times */
+    while ((TXCnt < len) || (RXCnt < len))
+    {
+        /* TX fifo not full, so add some more bytes */
+        while (((bcm283x_peri_read(paddr) & BCM283X_SPI0_CS_TXD)) && (TXCnt < len))
+        {
+            bcm283x_peri_write_nb(fifo, correct_order(tbuf[TXCnt]));
+            TXCnt++;
+        }
+        /* Rx fifo not empty, so get the next received bytes */
+        while (((bcm283x_peri_read(paddr) & BCM283X_SPI0_CS_RXD)) && (RXCnt < len))
+        {
+            rbuf[RXCnt] = correct_order(bcm283x_peri_read_nb(fifo));
+            RXCnt++;
+        }
+    }
+    /* Wait for DONE to be set */
+    while (!(bcm283x_peri_read_nb(paddr) & BCM283X_SPI0_CS_DONE));
+
+    /* Set TA = 0, and also set the barrier */
+    bcm283x_peri_set_bits(paddr, 0, BCM283X_SPI0_CS_TA);
+    return RT_EOK;
+
+}
+
+static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    rt_err_t res;
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->bus->parent.user_data != RT_NULL);
+    RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
+
+    struct rt_spi *hspi = (struct rt_spi *)&device->bus->parent;
+    /* only send data */
+    if (message->recv_buf == RT_NULL)
+    {
+        if (message->cs_take)
+        {
+            bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0);
+        }
+        res = spi_transfernb((rt_uint8_t *)message->send_buf, RT_NULL,(rt_int32_t)message->length);
+        if (message->cs_release)
+        {
+            bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1);
+
+        }
+        if (res != RT_EOK)
+            return RT_ERROR;
+    }
+
+    /* only receive data */
+    if (message->send_buf == RT_NULL)
+    {
+        if (message->cs_take)
+        {
+            bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0);
+        }
+        res = spi_transfernb(RT_NULL,(rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length);
+        if (message->cs_release)
+        {
+            bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1);
+        }
+        if (res != RT_EOK)
+            return RT_ERROR;
+    }
+    /* send & receive */
+    else
+    {
+        if (message->cs_take)
+        {
+            bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0);
+        }
+        res = spi_transfernb((rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
+                (rt_int32_t)message->length);
+        if (message->cs_release)
+        {
+            bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1);
+        }
+        if (res != RT_EOK)
+            return RT_ERROR;
+    }
+
+    return message->length;
+}
+
+rt_err_t raspi_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
+{
+    rt_err_t ret;
+    rt_int16_t gpio_pin;
+    struct rt_spi_device *spi_device;
+    struct rt_sw_spi_cs *cs_pin;
+
+    gpio_pin = phypin_index[pin].bcm_id;
+
+    spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+
+    cs_pin = (struct rt_sw_spi_cs *)rt_malloc(sizeof(struct rt_sw_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
+
+    cs_pin->pin = gpio_pin;
+
+    ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+
+    return ret;
+}
+
+#define DIV_ROUND_UP(n,d)    (((n) + (d) - 1) / (d))
+rt_uint16_t spi_clockdivider(rt_uint32_t speed_hz)
+{
+    rt_uint16_t divider;
+
+    if (speed_hz < (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MIN)
+    {
+        speed_hz = (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MIN;
+    }
+    else if (speed_hz > (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MAX)
+    {
+        speed_hz = (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MAX;
+    }
+
+    divider = (rt_uint16_t) DIV_ROUND_UP(BCM283X_CORE_CLK_HZ, 2 * speed_hz) - 1;
+
+    if (divider > (rt_uint16_t) BCM283X_AUX_SPI_CNTL0_SPEED_MAX)
+    {
+        return (rt_uint16_t) BCM283X_AUX_SPI_CNTL0_SPEED_MAX;
+    }
+
+    return divider;
+}
+
+rt_err_t raspi_spi_hw_init(struct rt_spi_hw_config *hwcfg)
+{
+    volatile rt_uint32_t enable = PER_BASE + BCM283X_AUX_BASE + BCM283X_AUX_ENABLE;
+    volatile rt_uint32_t cntl0 = PER_BASE + BCM283X_SPI1_BASE + BCM283X_AUX_SPI_CNTL0;
+    volatile rt_uint32_t cntl1 = PER_BASE + BCM283X_SPI1_BASE + BCM283X_AUX_SPI_CNTL1;
+
+    bcm283x_gpio_fsel(hwcfg->sclk_pin, hwcfg->sclk_mode);
+    bcm283x_gpio_fsel(hwcfg->miso_pin, hwcfg->miso_mode);
+    bcm283x_gpio_fsel(hwcfg->mosi_pin, hwcfg->mosi_mode);
+    bcm283x_gpio_fsel(hwcfg->cs_pin, hwcfg->cs_mode);
+
+    hwcfg->clk_div = spi_clockdivider(1000000);     // Default 1MHz SPI
+
+    bcm283x_peri_write(enable, BCM283X_AUX_ENABLE_SPI0);
+    bcm283x_peri_write(cntl1, 0);
+    bcm283x_peri_write(cntl0, BCM283X_AUX_SPI_CNTL0_CLEARFIFO);
+
+    return RT_EOK;
+}
+
+const static struct rt_spi_ops raspi_spi_ops =
+{
+    .configure = raspi_spi_configure,
+    .xfer = raspi_spi_xfer
+};
+
+#if defined (BSP_USING_SPI0)
+#define SPI0BUS_NAME  "spi0.0"
+
+struct rt_spi_bus raspi_spi0_bus =
+{
+    .ops = &raspi_spi_ops,
+    .parent.user_data = spi0
+};
+
+struct rt_spi_hw_config raspi_spi0_hw =
+{
+    .sclk_pin = BCM_GPIO_PIN_11,
+    .sclk_mode = BCM283X_GPIO_FSEL_ALT0,
+    .mosi_pin = BCM_GPIO_PIN_10,
+    .mosi_mode = BCM283X_GPIO_FSEL_ALT0,
+    .miso_pin = BCM_GPIO_PIN_9,
+    .miso_mode = BCM283X_GPIO_FSEL_ALT0,
+    .cs_pin = BCM_GPIO_PIN_8,
+    .cs_mode = BCM283X_GPIO_FSEL_ALT0,
+    .spi_base = (PER_BASE + BCM283X_SPI0_BASE),
+    .clk_div = 0,
+};
+
+struct rt_spi spi0 =
+{
+    .device_name = SPI0BUS_NAME,
+    .spi_bus = &raspi_spi0_bus,
+    .hwcfg = &raspi_spi0_hw,
+};
+
+#endif
+
+#if defined (BSP_USING_SPI1)
+#define SPI1BUS_NAME  "spi0.1"
+
+struct rt_spi_bus raspi_spi1_bus =
+{
+    .ops = &raspi_spi_ops,
+    .parent.user_data = spi1
+};
+
+struct rt_spi_hw_config raspi_spi1_hw =
+{
+    .sclk_pin = BCM_GPIO_PIN_11,
+    .sclk_mode = BCM283X_GPIO_FSEL_ALT0,
+    .mosi_pin = BCM_GPIO_PIN_10,
+    .mosi_mode = BCM283X_GPIO_FSEL_ALT0,
+    .miso_pin = BCM_GPIO_PIN_9,
+    .miso_mode = BCM283X_GPIO_FSEL_ALT0,
+    .cs_pin = BCM_GPIO_PIN_7,
+    .cs_mode = BCM283X_GPIO_FSEL_ALT0,
+    .spi_base = (PER_BASE + BCM283X_SPI0_BASE),
+    .clk_div = 0,
+};
+
+struct rt_spi spi1 =
+{
+    .device_name = SPI1BUS_NAME,
+    .spi_bus = &raspi_spi1_bus,
+    .hwcfg = &raspi_spi1_hw,
+};
+#endif
+
+int rt_hw_spi_bus_init(void)
+{
+#if defined (BSP_USING_SPI0)
+    raspi_spi_hw_init(spi0.hwcfg);
+    rt_spi_bus_register(spi0.spi_bus, spi0.device_name, spi0.spi_bus->ops);
+#endif
+
+#if defined (BSP_USING_SPI1)
+    raspi_spi_hw_init(spi1.hwcfg);
+    rt_spi_bus_register(spi1.spi_bus, spi1.device_name, spi1.spi_bus->ops);
+#endif
+
+    return RT_EOK;
+}
+INIT_PREV_EXPORT(rt_hw_spi_bus_init);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
new file mode 100644
index 0000000000..c4883758e5
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "bcm283x.h"
+#include <rtdevice.h>
+#include <drivers/spi.h>
+#include "raspi.h"
+
+#define SPI0_BASE_ADDR     (PER_BASE + BCM283X_SPI0_BASE)
+
+#define	SPI_CORE_CLK	250000000U
+#define	SPI_CS		0x00
+#define	SPI_CS_LEN_LONG		(1 << 25)
+#define	SPI_CS_DMA_LEN		(1 << 24)
+#define	SPI_CS_CSPOL2		(1 << 23)
+#define	SPI_CS_CSPOL1		(1 << 22)
+#define	SPI_CS_CSPOL0		(1 << 21)
+#define	SPI_CS_RXF		(1 << 20)
+#define	SPI_CS_RXR		(1 << 19)
+#define	SPI_CS_TXD		(1 << 18)
+#define	SPI_CS_RXD		(1 << 17)
+#define	SPI_CS_DONE		(1 << 16)
+#define	SPI_CS_LEN		(1 << 13)
+#define	SPI_CS_REN		(1 << 12)
+#define	SPI_CS_ADCS		(1 << 11)
+#define	SPI_CS_INTR		(1 << 10)
+#define	SPI_CS_INTD		(1 << 9)
+#define	SPI_CS_DMAEN		(1 << 8)
+#define	SPI_CS_TA		(1 << 7)
+#define	SPI_CS_CSPOL		(1 << 6)
+#define	SPI_CS_CLEAR_RXFIFO	(1 << 5)
+#define	SPI_CS_CLEAR_TXFIFO	(1 << 4)
+#define	SPI_CS_CPOL		(1 << 3)
+#define	SPI_CS_CPHA		(1 << 2)
+#define	SPI_CS_MASK		0x3
+#define	SPI_FIFO	0x04
+#define	SPI_CLK		0x08
+#define	SPI_CLK_MASK		0xffff
+#define	SPI_DLEN	0x0c
+#define	SPI_DLEN_MASK		0xffff
+#define	SPI_LTOH	0x10
+#define	SPI_LTOH_MASK		0xf
+#define	SPI_DC		0x14
+#define	SPI_DC_RPANIC_SHIFT	24
+#define	SPI_DC_RPANIC_MASK	(0xff << SPI_DC_RPANIC_SHIFT)
+#define	SPI_DC_RDREQ_SHIFT	16
+#define	SPI_DC_RDREQ_MASK	(0xff << SPI_DC_RDREQ_SHIFT)
+#define	SPI_DC_TPANIC_SHIFT	8
+#define	SPI_DC_TPANIC_MASK	(0xff << SPI_DC_TPANIC_SHIFT)
+#define	SPI_DC_TDREQ_SHIFT	0
+#define	SPI_DC_TDREQ_MASK	0xff
+
+int rt_hw_spi_bus_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
new file mode 100644
index 0000000000..0ead0fdf74
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "bcm283x.h"
+#include "drv_timer.h"
+#include <drivers/hwtimer.h>
+#include "cp15.h"
+
+static void rt_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state)
+{
+    if (state == 0)
+        hwtimer->ops->stop(hwtimer);
+}
+
+static rt_err_t rt_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
+{
+    rt_err_t result = RT_EOK;
+    rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
+    int timer_id = timer->timer_id;
+    if (mode == HWTIMER_MODE_PERIOD)
+        timer->cnt = cnt;
+    else
+        timer->cnt = 0; 
+    __DSB();
+    if (timer_id == 1)
+    {
+        rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_1);   
+        STIMER_C1 = STIMER_CLO + cnt;
+    } 
+    else if (timer_id == 3)
+    {
+        rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_3);   
+        STIMER_C3 = STIMER_CLO + cnt;
+    }
+    else    
+        result = -RT_ERROR;
+    __DSB();
+         
+    return result;
+}
+
+static void rt_systimer_stop(rt_hwtimer_t *hwtimer)
+{
+    rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
+    int timer_id = timer->timer_id;
+    if (timer_id == 1)
+        rt_hw_interrupt_mask(IRQ_SYSTIMER_MATCH_1);      
+    else if (timer_id == 3)
+        rt_hw_interrupt_mask(IRQ_SYSTIMER_MATCH_3); 
+ 
+}
+
+static rt_err_t rt_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+    /* The frequency value is an immutable value. */
+    if (cmd == HWTIMER_CTRL_FREQ_SET)
+    {
+        return RT_EOK;
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+}
+
+const static struct rt_hwtimer_ops systimer_ops = 
+{
+    rt_systimer_init,
+    rt_systimer_start,
+    rt_systimer_stop,
+    RT_NULL,
+    rt_systimer_ctrl
+};
+
+void rt_device_systimer_isr(int vector, void *param)
+{
+    rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param;
+    rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
+    RT_ASSERT(timer != RT_NULL);
+    int timer_id = timer->timer_id;
+
+    __DSB();
+    if (timer_id == 1)
+    {
+        STIMER_CS = 0x2;
+        STIMER_C1 = STIMER_CLO + timer->cnt;               
+    }   
+    else if (timer_id == 3)
+    {
+        STIMER_CS = 0x8;
+        STIMER_C3 = STIMER_CLO + timer->cnt;                 
+    }
+    
+    __DSB();
+    rt_device_hwtimer_isr(hwtimer);
+}
+    
+static struct rt_hwtimer_device _hwtimer1;
+static struct rt_hwtimer_device _hwtimer3;
+static struct rt_systimer_device _systimer1;
+static struct rt_systimer_device _systimer3;
+
+static const struct rt_hwtimer_info _info =
+{
+    1000000,            /* the maxinum count frequency can be set */
+    1000000,            /* the maxinum count frequency can be set */
+    0xFFFFFFFF,         /* the maximum counter value */
+    HWTIMER_CNTMODE_UP  /* count mode (inc/dec) */
+};
+
+int rt_hw_systimer_init(void)
+{
+#ifdef RT_USING_SYSTIMER1
+    _systimer1.timer_id =1;
+    _hwtimer1.ops = &systimer_ops;
+    _hwtimer1.info = &_info;
+    rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1);
+    rt_hw_interrupt_install(IRQ_SYSTIMER_MATCH_1, rt_device_systimer_isr, &_hwtimer1, "systimer1");
+    rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_1);
+#endif
+
+#ifdef RT_USING_SYSTIMER3
+    _systimer3.timer_id =3;
+    _hwtimer3.ops = &systimer_ops;
+    _hwtimer3.info = &_info;
+    rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3);
+    rt_hw_interrupt_install(IRQ_SYSTIMER_MATCH_3, rt_device_systimer_isr, &_hwtimer3, "systimer3");
+    
+#endif
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h
new file mode 100644
index 0000000000..c18e3d893c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+#ifndef __DRV_TIMER_H__
+#define __DRV_TIMER_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+typedef struct rt_systimer_device
+{
+    int  timer_id;
+    rt_uint32_t cnt;
+} rt_systimer_t;
+
+int rt_hw_systimer_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
new file mode 100644
index 0000000000..fd8ec66af9
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/5/5       Bernard      The first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include <rtdevice.h>
+
+#define AUX_BASE            (0x3F000000 + 0x215000)
+
+struct hw_uart_device
+{
+    rt_ubase_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if (uart->hw_base == AUX_BASE)
+    {
+    	rt_uint32_t value;
+
+        /* GPIO function set */
+        value = GPIO_GPFSEL1;
+        value &= ~(7<<12); /* GPIO14 */
+        value |=    2<<12 ; /* ALT5 */
+        value &= ~(7<<15); /* GPIO15 */
+        value |=    2<<15 ; /* ALT5 */
+        GPIO_GPFSEL1 = value;
+
+        /* PullUD disable */
+        GPIO_GPPUD = 0;
+        GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15);
+        GPIO_GPPUDCLK0 = 0;
+
+        AUX_ENABLES(uart->hw_base)      = 1;    /* Enable UART1 */
+        AUX_MU_IER_REG(uart->hw_base)   = 0;    /* Disable interrupt */
+        AUX_MU_CNTL_REG(uart->hw_base)  = 0;    /* Disable Transmitter and Receiver */
+        AUX_MU_LCR_REG(uart->hw_base)   = 3;    /* Works in 8-bit mode */
+        AUX_MU_MCR_REG(uart->hw_base)   = 0;    /* Disable RTS */
+        AUX_MU_IIR_REG(uart->hw_base)   = 0xC6; /* Enable FIFO, Clear FIFO */
+        AUX_MU_BAUD_REG(uart->hw_base)  = 270;  /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
+        AUX_MU_CNTL_REG(uart->hw_base)  = 3;    /* Enable Transmitter and Receiver */
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        AUX_MU_IER_REG(uart->hw_base) = 0x0;
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        AUX_MU_IER_REG(uart->hw_base) = 0x1;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
+    AUX_MU_IO_REG(uart->hw_base) = c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
+    {
+        ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+#ifdef RT_USING_UART0
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    RPI_UART0_BASE,
+    IRQ_PBA8_UART0,
+};
+static struct rt_serial_device _serial0;
+#endif
+
+#ifdef RT_USING_UART1
+/* UART1 device driver structure */
+static struct hw_uart_device _uart1_device =
+{
+    AUX_BASE,
+    IRQ_AUX,
+};
+static struct rt_serial_device _serial1;
+#endif
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART0
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
+#endif
+
+#ifdef RT_USING_UART1
+    uart = &_uart1_device;
+    _serial1.ops = &_uart_ops;
+    _serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+    /* enable Rx and Tx of UART */
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1");
+#endif
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h
new file mode 100644
index 0000000000..894c6098db
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      Bernard      the first version
+ */
+
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+/*
+ *  Auxiliary
+ */
+#define AUX_IRQ(BASE)             HWREG32(BASE + 0x00)   /* Auxiliary Interrupt status 3 */
+#define AUX_ENABLES(BASE)         HWREG32(BASE + 0x04)   /* Auxiliary enables 3bit */
+#define AUX_MU_IO_REG(BASE)       HWREG32(BASE + 0x40)   /* Mini Uart I/O Data 8bit */
+#define AUX_MU_IER_REG(BASE)      HWREG32(BASE + 0x44)   /* Mini Uart Interrupt Enable 8bit */
+#define AUX_MU_IIR_REG(BASE)      HWREG32(BASE + 0x48)   /* Mini Uart Interrupt Identify 8bit */
+#define AUX_MU_LCR_REG(BASE)      HWREG32(BASE + 0x4C)   /* Mini Uart Line Control 8bit */
+#define AUX_MU_MCR_REG(BASE)      HWREG32(BASE + 0x50)   /* Mini Uart Modem Control 8bit */
+#define AUX_MU_LSR_REG(BASE)      HWREG32(BASE + 0x54)   /* Mini Uart Line Status 8bit */
+#define AUX_MU_MSR_REG(BASE)      HWREG32(BASE + 0x58)   /* Mini Uart Modem Status 8bit */
+#define AUX_MU_SCRATCH(BASE)      HWREG32(BASE + 0x5C)   /* Mini Uart Scratch 8bit */
+#define AUX_MU_CNTL_REG(BASE)     HWREG32(BASE + 0x60)   /* Mini Uart Extra Control 8bit */
+#define AUX_MU_STAT_REG(BASE)     HWREG32(BASE + 0x64)   /* Mini Uart Extra Status 32bit */
+#define AUX_MU_BAUD_REG(BASE)     HWREG32(BASE + 0x68)   /* Mini Uart Baudrate 16bit */
+#define AUX_SPI0_CNTL0_REG(BASE)  HWREG32(BASE + 0x80)   /* SPI 1 Control register 0 32bit */
+#define AUX_SPI0_CNTL1_REG(BASE)  HWREG32(BASE + 0x84)   /* SPI 1 Control register 1 8bit */
+#define AUX_SPI0_STAT_REG(BASE)   HWREG32(BASE + 0x88)   /* SPI 1 Status 32bit */
+#define AUX_SPI0_IO_REG(BASE)     HWREG32(BASE + 0x90)   /* SPI 1 Data 32bit */
+#define AUX_SPI0_PEEK_REG(BASE)   HWREG32(BASE + 0x94)   /* SPI 1 Peek 16bit */
+#define AUX_SPI1_CNTL0_REG(BASE)  HWREG32(BASE + 0xC0)   /* SPI 2 Control register 0 32bit */
+#define AUX_SPI1_CNTL1_REG(BASE)  HWREG32(BASE + 0xC4)   /* SPI 2 Control register 1 8bit */
+
+int rt_hw_uart_init(void);
+
+#endif /* DRV_UART_H__ */
+
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
new file mode 100644
index 0000000000..a1baee96aa
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+#include "drv_wdt.h"
+
+#ifdef BSP_USING_WDT
+
+#define PM_RSTC				0x1c
+#define PM_RSTS				0x20
+#define PM_WDOG				0x24
+
+#define PM_PASSWORD			0x5a000000
+
+#define PM_WDOG_TIME_SET		0x000fffff
+#define PM_RSTC_WRCFG_CLR		0xffffffcf
+#define PM_RSTS_HADWRH_SET		0x00000040
+#define PM_RSTC_WRCFG_SET		0x00000030
+#define PM_RSTC_WRCFG_FULL_RESET	0x00000020
+#define PM_RSTC_RESET			0x00000102
+#define PM_RSTS_PARTITION_CLR          0xfffffaaa
+
+#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
+#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
+
+static struct raspi_wdt_driver bcm_wdt =
+{
+    .base = PER_BASE,
+};
+
+void raspi_watchdog_init(rt_uint32_t time_init)
+{
+    bcm_wdt.timeout = time_init;
+}
+
+void raspi_watchdog_start()
+{
+    volatile rt_uint32_t cur;
+    bcm283x_peri_write(bcm_wdt.base + PM_WDOG, PM_PASSWORD
+            | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET));
+    bcm283x_peri_write(bcm_wdt.base + PM_WDOG, PM_PASSWORD
+            | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET));
+
+    cur = bcm283x_peri_read(bcm_wdt.base + PM_RSTC);
+
+    bcm283x_peri_write(bcm_wdt.base + PM_RSTC, PM_PASSWORD
+            | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET);
+
+}
+
+void raspi_watchdog_stop()
+{
+    bcm283x_peri_write(bcm_wdt.base + PM_RSTC, PM_PASSWORD | PM_RSTC_RESET);
+}
+
+void raspi_watchdog_clr()
+{
+    bcm_wdt.timeout = 0;
+}
+
+void raspi_watchdog_set_timeout( rt_uint32_t timeout_us)
+{
+    bcm_wdt.timeout = timeout_us;
+}
+
+rt_uint64_t raspi_watchdog_get_timeout()
+{
+    return bcm_wdt.timeout;
+}
+
+rt_uint64_t raspi_watchdog_get_timeleft()
+{
+    rt_uint32_t ret = bcm283x_peri_read(bcm_wdt.base + PM_WDOG);
+    return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
+}
+
+static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt)
+{
+    /*init for 10S*/
+    raspi_watchdog_init(1000000);
+    raspi_watchdog_start();
+    raspi_watchdog_stop();
+    return RT_EOK;
+}
+
+static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    rt_uint64_t  timeout_us = 0;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        timeout_us = *((rt_uint32_t *)arg) * 1000000;
+        if (timeout_us >= 0xFFFFFFFF)
+            timeout_us = 0xFFFFFFFF;
+        raspi_watchdog_set_timeout((rt_uint32_t)timeout_us);
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        timeout_us = raspi_watchdog_get_timeout();
+        *((rt_uint32_t *)arg) = timeout_us / 1000000;
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
+        timeout_us = raspi_watchdog_get_timeleft();
+        *((rt_uint32_t *)arg) = timeout_us / 1000000;
+        break;
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        raspi_watchdog_clr();
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        raspi_watchdog_start();
+        break;
+    case RT_DEVICE_CTRL_WDT_STOP:
+        raspi_watchdog_stop();
+        break;
+    default:
+        return RT_EIO;
+    }
+    return RT_EOK;
+}
+
+static const struct rt_watchdog_ops raspi_wdg_pos =
+{
+    raspi_wdg_init,
+    raspi_wdg_control,
+};
+
+static rt_watchdog_t raspi_wdg;
+
+int rt_hw_wdt_init(void)
+{
+    raspi_wdg.ops = &raspi_wdg_pos;
+    rt_hw_watchdog_register(&raspi_wdg, "wdg", 0, RT_NULL);
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_wdt_init);
+#endif /*BSP_USING_WDT */
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
new file mode 100644
index 0000000000..a690becfd1
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __DRV_WDT_H__
+#define __DRV_WDT_H__
+
+#include <rtdef.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drivers/watchdog.h>
+
+#include "bcm283x.h"
+
+struct raspi_wdt_driver
+{
+    volatile rt_uint32_t base;
+    rt_uint32_t timeout;
+};
+
+int rt_hw_wdt_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.c b/bsp/raspberry-pi/raspi3-64/driver/mbox.c
new file mode 100644
index 0000000000..36ed95b429
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.c
@@ -0,0 +1,53 @@
+/*
+ * File      : mbox.c
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+
+/* mailbox message buffer */
+#include "mbox.h"
+#include "mmu.h"
+//volatile unsigned int  __attribute__((aligned(16))) mbox[36];
+volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR;
+/**
+ * Make a mailbox call. Returns 0 on failure, non-zero on success
+ */
+void init_mbox_mmu_map(){
+	rt_hw_change_mmu_table(MBOX_ADDR, 96, MBOX_ADDR, STRONG_ORDER_MEM);
+}
+
+int mbox_call(unsigned char ch, int mmu_enable)
+{
+    unsigned int r = (((MBOX_ADDR)&~0xF) | (ch&0xF));
+    if(mmu_enable)
+        r = BUS_ADDRESS(r);
+    /* wait until we can write to the mailbox */
+    do
+    {
+        asm volatile("nop");
+    } while (*MBOX_STATUS & MBOX_FULL);
+    /* write the address of our message to the mailbox with channel identifier */
+    *MBOX_WRITE = r;
+    /* now wait for the response */
+   // rt_kprintf("mailbox request %x\n",r);
+    while(1)
+    {
+        /* is there a response? */
+        do
+        {
+            asm volatile("nop");
+        } while (*MBOX_STATUS & MBOX_EMPTY);
+        /* is it a response to our message? */
+        if (r == *MBOX_READ){
+            /* is it a valid successful response? */
+        //	rt_kprintf("mbox: %x, %x, %x, %x, %x, %x, %x, %x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4], mbox[5], mbox[6], mbox[7]);
+            return mbox[1] == MBOX_RESPONSE;
+        }
+    }
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.h b/bsp/raspberry-pi/raspi3-64/driver/mbox.h
new file mode 100644
index 0000000000..eb7eb0318c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.h
@@ -0,0 +1,62 @@
+/*
+ * File      : mbox.h
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ */
+
+#ifndef __MBOX_H__
+#define __MBOX_H__
+
+
+/* a properly aligned buffer */
+extern volatile unsigned int* mbox;
+
+#define MBOX_REQUEST    0
+
+/* channels */
+#define MBOX_CH_POWER   0
+#define MBOX_CH_FB      1
+#define MBOX_CH_VUART   2
+#define MBOX_CH_VCHIQ   3
+#define MBOX_CH_LEDS    4
+#define MBOX_CH_BTNS    5
+#define MBOX_CH_TOUCH   6
+#define MBOX_CH_COUNT   7
+#define MBOX_CH_PROP    8
+
+/* tags */
+#define MBOX_TAG_SETPOWER       0x28001
+#define MBOX_TAG_SETCLKRATE     0x38002
+#define MBOX_GET_MAC_ADDRESS	0x10003
+#define MBOX_TAG_LAST           0
+
+#define MMIO_BASE       0x3F000000
+#define VIDEOCORE_MBOX  (MMIO_BASE+0x0000B880)
+#define MBOX_READ       ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0))
+#define MBOX_POLL       ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10))
+#define MBOX_SENDER     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14))
+#define MBOX_STATUS     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18))
+#define MBOX_CONFIG     ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C))
+#define MBOX_WRITE      ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20))
+#define MBOX_RESPONSE   0x80000000
+#define MBOX_FULL       0x80000000
+#define MBOX_EMPTY      0x40000000
+
+#define DEVICE_ID_SD_CARD	0
+#define DEVICE_ID_USB_HCD	3
+#define POWER_STATE_OFF		(0 << 0)
+#define POWER_STATE_ON		(1 << 0)
+#define POWER_STATE_WAIT	(1 << 1)
+#define POWER_STATE_NO_DEVICE	(1 << 1)	// in response
+#define MMU_ENABLE 1
+#define MMU_DISABLE 0
+
+#define MBOX_ADDR 0xc00000
+
+int mbox_call(unsigned char ch, int mmu_enable);
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/driver/raspi.h b/bsp/raspberry-pi/raspi3-64/driver/raspi.h
new file mode 100644
index 0000000000..0d55df2a11
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/driver/raspi.h
@@ -0,0 +1,70 @@
+/*
+ * File      : rsapi.h
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-07-29     zdzn           first version
+ */
+
+#ifndef __RASPI_H__
+#define __RASPI_H__
+
+#include "bcm283x.h"
+
+#define PIN_MAGIC       (0x5A)
+#define PIN_NUM(_N)     (sizeof(_N) / sizeof(_N[0]))
+
+enum gpio_code
+{
+    GPIO_CODE_PHY = 0,
+    GPIO_CODE_BCM,
+    GPIO_CODE_WIRING,
+    GPIO_CODE_NUM,
+};
+
+enum rpi_pin_name
+{
+    RPI_SDA0 = 0,
+    RPI_SCL0,
+    RPI_SDA1,
+    RPI_SCL1,
+    RPI_GPIO_GCLK,
+    RPI_CAM_CLK,
+    RPI_LAN_RUN,
+    RPI_SPI_CE1_N,
+    RPI_SPI_CE0_N,
+    RPI_SPI_MISO,
+    RPI_SPI_MOSI,
+    RPI_SPI_SCLK,
+    RPI_TXD0,
+    RPI_RXD0,
+    RPI_STATUS_LED_N,
+    RPI_GPIO_GEN0,
+    RPI_GPIO_GEN1,
+    RPI_CAM_GPIO,
+    RPI_GPIO_GEN3,
+    RPI_GPIO_GEN4,
+    RPI_GPIO_GEN5,
+    RPI_GPIO_GEN6,
+    RPI_GPIO_GEN2,
+    RPI_GPIO_GEN7,
+    RPI_GPIO_GEN8,
+    RPI_GPIO_GEN9,
+    RPI_GPIO_GEN10,
+    RPI_PWM0_OUT,
+    RPI_PWM1_OUT,
+    RPI_HDMI_HPD_P,
+    RPI_SD_CARD_DET,
+    RPI_SD_CLK_R,
+    RPI_SD_CMD_R,
+    RPI_SD_DATA0_R,
+    RPI_SD_DATA1_R,
+    RPI_SD_DATA2_R,
+    RPI_SD_DATA3_R,
+    RPI_GPIO_PIN_NUM,
+};
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/figures/raspi_uart.png b/bsp/raspberry-pi/raspi3-64/figures/raspi_uart.png
new file mode 100644
index 0000000000..c6ae382182
Binary files /dev/null and b/bsp/raspberry-pi/raspi3-64/figures/raspi_uart.png differ
diff --git a/bsp/raspberry-pi/raspi3-64/kernel8.img b/bsp/raspberry-pi/raspi3-64/kernel8.img
new file mode 100755
index 0000000000..d1e9d50822
Binary files /dev/null and b/bsp/raspberry-pi/raspi3-64/kernel8.img differ
diff --git a/bsp/raspberry-pi/raspi3-64/link.lds b/bsp/raspberry-pi/raspi3-64/link.lds
new file mode 100644
index 0000000000..604a45c110
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/link.lds
@@ -0,0 +1,151 @@
+/*
+ * File      : link.lds
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
+
+SECTIONS
+{
+    . = 0x80000;
+    . = ALIGN(4096);
+    .text :
+    {
+        KEEP(*(.text.entrypoint))       /* The entry point */
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(16);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(16);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(16);
+
+        /* section information for initial. */
+        . = ALIGN(16);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(16);
+
+        . = ALIGN(16);
+        _etext = .;
+    }
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(16);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(16);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(16);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+        PROVIDE(__bss_end = .);
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
+__bss_size = (__bss_end - __bss_start)>>3;
diff --git a/bsp/raspberry-pi/raspi3-64/qemu-64.bat b/bsp/raspberry-pi/raspi3-64/qemu-64.bat
new file mode 100644
index 0000000000..c009905e23
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/qemu-64.bat
@@ -0,0 +1 @@
+qemu-system-aarch64 -M raspi3 -kernel kernel8.img -serial null -serial stdio
\ No newline at end of file
diff --git a/bsp/raspberry-pi/raspi3-64/rtconfig.h b/bsp/raspberry-pi/raspi3-64/rtconfig.h
new file mode 100644
index 0000000000..4a8d8c42bc
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/rtconfig.h
@@ -0,0 +1,382 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+/* RT_USING_ARCH_DATA_TYPE is not set */
+/* RT_USING_SMP is not set */
+#define RT_ALIGN_SIZE 4
+/* RT_THREAD_PRIORITY_8 is not set */
+#define RT_THREAD_PRIORITY_32
+/* RT_THREAD_PRIORITY_256 is not set */
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 2048
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+/* RT_DEBUG_INIT_CONFIG is not set */
+/* RT_DEBUG_THREAD_CONFIG is not set */
+/* RT_DEBUG_SCHEDULER_CONFIG is not set */
+/* RT_DEBUG_IPC_CONFIG is not set */
+/* RT_DEBUG_TIMER_CONFIG is not set */
+/* RT_DEBUG_IRQ_CONFIG is not set */
+/* RT_DEBUG_MEM_CONFIG is not set */
+/* RT_DEBUG_SLAB_CONFIG is not set */
+/* RT_DEBUG_MEMHEAP_CONFIG is not set */
+/* RT_DEBUG_MODULE_CONFIG is not set */
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* RT_USING_SIGNALS is not set */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_MEMHEAP
+/* RT_USING_NOHEAP is not set */
+#define RT_USING_SMALL_MEM
+/* RT_USING_SLAB is not set */
+/* RT_USING_MEMHEAP_AS_HEAP is not set */
+#define RT_USING_MEMTRACE
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
+/* RT_USING_INTERRUPT_INFO is not set */
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40002
+#define ARCH_CPU_64BIT
+#define ARCH_ARM
+/* RT_USING_CPU_FFS is not set */
+#define ARCH_ARM_CORTEX_AARCH64
+#define ARCH_ARM_CORTEX_A53
+/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+/* RT_USING_CPLUSPLUS is not set */
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+/* FINSH_ECHO_DISABLE_DEFAULT is not set */
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+/* FINSH_USING_AUTH is not set */
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+/* RT_USING_DFS_MNTTABLE is not set */
+/* RT_USING_DFS_ELMFAT is not set */
+#define RT_USING_DFS_DEVFS
+/* RT_USING_DFS_ROMFS is not set */
+/* RT_USING_DFS_RAMFS is not set */
+/* RT_USING_DFS_UFFS is not set */
+/* RT_USING_DFS_JFFS2 is not set */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+/* RT_USING_SYSTEM_WORKQUEUE is not set */
+#define RT_USING_SERIAL
+/* RT_SERIAL_USING_DMA is not set */
+#define RT_SERIAL_RB_BUFSZ 64
+/* RT_USING_CAN is not set */
+/* RT_USING_HWTIMER is not set */
+/* RT_USING_CPUTIME is not set */
+/* RT_USING_I2C is not set */
+#define RT_USING_PIN
+/* RT_USING_ADC is not set */
+/* RT_USING_PWM is not set */
+/* RT_USING_MTD_NOR is not set */
+/* RT_USING_MTD_NAND is not set */
+/* RT_USING_PM is not set */
+/* RT_USING_RTC is not set */
+/* RT_USING_SDIO is not set */
+/* RT_USING_SPI is not set */
+/* RT_USING_WDT is not set */
+/* RT_USING_AUDIO is not set */
+/* RT_USING_SENSOR is not set */
+/* RT_USING_TOUCH is not set */
+/* RT_USING_HWCRYPTO is not set */
+/* RT_USING_WIFI is not set */
+
+/* Using USB */
+
+/* RT_USING_USB_HOST is not set */
+/* RT_USING_USB_DEVICE is not set */
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+/* RT_USING_PTHREADS is not set */
+#define RT_USING_POSIX
+/* RT_USING_POSIX_MMAP is not set */
+/* RT_USING_POSIX_TERMIOS is not set */
+/* RT_USING_POSIX_AIO is not set */
+/* RT_USING_MODULE is not set */
+
+/* Network */
+
+/* Socket abstraction layer */
+
+/* RT_USING_SAL is not set */
+
+/* Network interface device */
+
+/* RT_USING_NETDEV is not set */
+
+/* light weight TCP/IP stack */
+
+/* RT_USING_LWIP is not set */
+
+/* AT commands */
+
+/* RT_USING_AT is not set */
+
+/* VBUS(Virtual Software BUS) */
+
+/* RT_USING_VBUS is not set */
+
+/* Utilities */
+
+/* RT_USING_RYM is not set */
+/* RT_USING_ULOG is not set */
+/* RT_USING_UTEST is not set */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+/* PKG_USING_PAHOMQTT is not set */
+/* PKG_USING_WEBCLIENT is not set */
+/* PKG_USING_WEBNET is not set */
+/* PKG_USING_MONGOOSE is not set */
+/* PKG_USING_WEBTERMINAL is not set */
+/* PKG_USING_CJSON is not set */
+/* PKG_USING_JSMN is not set */
+/* PKG_USING_LIBMODBUS is not set */
+/* PKG_USING_FREEMODBUS is not set */
+/* PKG_USING_LJSON is not set */
+/* PKG_USING_EZXML is not set */
+/* PKG_USING_NANOPB is not set */
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* PKG_USING_WLANMARVELL is not set */
+
+/* Wiced WiFi */
+
+/* PKG_USING_WLAN_WICED is not set */
+/* PKG_USING_RW007 is not set */
+/* PKG_USING_COAP is not set */
+/* PKG_USING_NOPOLL is not set */
+/* PKG_USING_NETUTILS is not set */
+/* PKG_USING_PPP_DEVICE is not set */
+/* PKG_USING_AT_DEVICE is not set */
+/* PKG_USING_ATSRV_SOCKET is not set */
+/* PKG_USING_WIZNET is not set */
+
+/* IoT Cloud */
+
+/* PKG_USING_ONENET is not set */
+/* PKG_USING_GAGENT_CLOUD is not set */
+/* PKG_USING_ALI_IOTKIT is not set */
+/* PKG_USING_AZURE is not set */
+/* PKG_USING_TENCENT_IOTHUB is not set */
+/* PKG_USING_JIOT-C-SDK is not set */
+/* PKG_USING_NIMBLE is not set */
+/* PKG_USING_OTA_DOWNLOADER is not set */
+/* PKG_USING_IPMSG is not set */
+/* PKG_USING_LSSDP is not set */
+/* PKG_USING_AIRKISS_OPEN is not set */
+/* PKG_USING_LIBRWS is not set */
+/* PKG_USING_TCPSERVER is not set */
+/* PKG_USING_PROTOBUF_C is not set */
+/* PKG_USING_ONNX_PARSER is not set */
+/* PKG_USING_ONNX_BACKEND is not set */
+/* PKG_USING_DLT645 is not set */
+/* PKG_USING_QXWZ is not set */
+/* PKG_USING_SMTP_CLIENT is not set */
+
+/* security packages */
+
+/* PKG_USING_MBEDTLS is not set */
+/* PKG_USING_libsodium is not set */
+/* PKG_USING_TINYCRYPT is not set */
+
+/* language packages */
+
+/* PKG_USING_LUA is not set */
+/* PKG_USING_JERRYSCRIPT is not set */
+/* PKG_USING_MICROPYTHON is not set */
+
+/* multimedia packages */
+
+/* PKG_USING_OPENMV is not set */
+/* PKG_USING_MUPDF is not set */
+/* PKG_USING_STEMWIN is not set */
+/* PKG_USING_WAVPLAYER is not set */
+/* PKG_USING_TJPGD is not set */
+
+/* tools packages */
+
+/* PKG_USING_CMBACKTRACE is not set */
+/* PKG_USING_EASYFLASH is not set */
+/* PKG_USING_EASYLOGGER is not set */
+/* PKG_USING_SYSTEMVIEW is not set */
+/* PKG_USING_RDB is not set */
+/* PKG_USING_QRCODE is not set */
+/* PKG_USING_ULOG_EASYFLASH is not set */
+/* PKG_USING_ADBD is not set */
+/* PKG_USING_COREMARK is not set */
+/* PKG_USING_DHRYSTONE is not set */
+
+/* system packages */
+
+/* PKG_USING_GUIENGINE is not set */
+/* PKG_USING_CAIRO is not set */
+/* PKG_USING_PIXMAN is not set */
+/* PKG_USING_LWEXT4 is not set */
+/* PKG_USING_PARTITION is not set */
+/* PKG_USING_FAL is not set */
+/* PKG_USING_SQLITE is not set */
+/* PKG_USING_RTI is not set */
+/* PKG_USING_LITTLEVGL2RTT is not set */
+/* PKG_USING_CMSIS is not set */
+/* PKG_USING_DFS_YAFFS is not set */
+/* PKG_USING_LITTLEFS is not set */
+/* PKG_USING_THREAD_POOL is not set */
+/* PKG_USING_ROBOTS is not set */
+
+/* peripheral libraries and drivers */
+
+/* PKG_USING_SENSORS_DRIVERS is not set */
+/* PKG_USING_REALTEK_AMEBA is not set */
+/* PKG_USING_SHT2X is not set */
+/* PKG_USING_STM32_SDIO is not set */
+/* PKG_USING_ICM20608 is not set */
+/* PKG_USING_U8G2 is not set */
+/* PKG_USING_BUTTON is not set */
+/* PKG_USING_PCF8574 is not set */
+/* PKG_USING_SX12XX is not set */
+/* PKG_USING_SIGNAL_LED is not set */
+/* PKG_USING_LEDBLINK is not set */
+/* PKG_USING_WM_LIBRARIES is not set */
+/* PKG_USING_KENDRYTE_SDK is not set */
+/* PKG_USING_INFRARED is not set */
+/* PKG_USING_ROSSERIAL is not set */
+/* PKG_USING_AGILE_BUTTON is not set */
+/* PKG_USING_AGILE_LED is not set */
+/* PKG_USING_AT24CXX is not set */
+/* PKG_USING_MOTIONDRIVER2RTT is not set */
+/* PKG_USING_AD7746 is not set */
+/* PKG_USING_PCA9685 is not set */
+/* PKG_USING_I2C_TOOLS is not set */
+/* PKG_USING_NRF24L01 is not set */
+/* PKG_USING_TOUCH_DRIVERS is not set */
+/* PKG_USING_LCD_DRIVERS is not set */
+/* PKG_USING_MAX17048 is not set */
+/* PKG_USING_RPLIDAR is not set */
+
+/* miscellaneous packages */
+
+/* PKG_USING_LIBCSV is not set */
+/* PKG_USING_OPTPARSE is not set */
+/* PKG_USING_FASTLZ is not set */
+/* PKG_USING_MINILZO is not set */
+/* PKG_USING_QUICKLZ is not set */
+/* PKG_USING_MULTIBUTTON is not set */
+/* PKG_USING_FLEXIBLE_BUTTON is not set */
+/* PKG_USING_CANFESTIVAL is not set */
+/* PKG_USING_ZLIB is not set */
+/* PKG_USING_DSTR is not set */
+/* PKG_USING_TINYFRAME is not set */
+/* PKG_USING_KENDRYTE_DEMO is not set */
+/* PKG_USING_DIGITALCTRL is not set */
+/* PKG_USING_UPACKER is not set */
+/* PKG_USING_UPARAM is not set */
+
+/* samples: kernel and components samples */
+
+/* PKG_USING_KERNEL_SAMPLES is not set */
+/* PKG_USING_FILESYSTEM_SAMPLES is not set */
+/* PKG_USING_NETWORK_SAMPLES is not set */
+/* PKG_USING_PERIPHERAL_SAMPLES is not set */
+/* PKG_USING_HELLO is not set */
+/* PKG_USING_VI is not set */
+/* PKG_USING_NNOM is not set */
+/* PKG_USING_LIBANN is not set */
+/* PKG_USING_ELAPACK is not set */
+/* PKG_USING_ARMv7M_DWT is not set */
+/* PKG_USING_VT100 is not set */
+/* PKG_USING_ULAPACK is not set */
+/* PKG_USING_UKAL is not set */
+#define BCM2836_SOC
+/* BSP_SUPPORT_FPU is not set */
+
+/* Hardware Drivers Config */
+
+/* BCM Peripheral Drivers */
+
+#define BSP_USING_UART
+/* RT_USING_UART0 is not set */
+#define RT_USING_UART1
+#define BSP_USING_PIN
+/* BSP_USING_SYSTIMER is not set */
+/* BSP_USING_I2C is not set */
+/* BSP_USING_SPI is not set */
+/* BSP_USING_WDT is not set */
+/* BSP_USING_RTC is not set */
+/* BSP_USING_SDIO is not set */
+
+/* Board Peripheral Drivers */
+
+/* BSP_USING_HDMI is not set */
+
+#endif
diff --git a/bsp/raspberry-pi/raspi3-64/rtconfig.py b/bsp/raspberry-pi/raspi3-64/rtconfig.py
new file mode 100644
index 0000000000..54d5988b64
--- /dev/null
+++ b/bsp/raspberry-pi/raspi3-64/rtconfig.py
@@ -0,0 +1,54 @@
+import os
+
+# toolchains options
+ARCH        ='aarch64'
+CPU         ='cortex-a53'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    # PREFIX = 'arm-none-eabi-'
+    PREFIX = 'aarch64-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv8-a -mtune=cortex-a53'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET kernel8.img\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/raspi2/.config b/bsp/raspi2/.config
deleted file mode 100644
index e7ce89e6c8..0000000000
--- a/bsp/raspi2/.config
+++ /dev/null
@@ -1,292 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Project Configuration
-#
-
-#
-# RT-Thread Kernel
-#
-CONFIG_RT_NAME_MAX=8
-CONFIG_RT_ALIGN_SIZE=4
-# CONFIG_RT_THREAD_PRIORITY_8 is not set
-CONFIG_RT_THREAD_PRIORITY_32=y
-# CONFIG_RT_THREAD_PRIORITY_256 is not set
-CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=100
-CONFIG_RT_USING_OVERFLOW_CHECK=y
-CONFIG_RT_USING_HOOK=y
-CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=256
-# CONFIG_RT_USING_TIMER_SOFT is not set
-CONFIG_RT_DEBUG=y
-CONFIG_RT_DEBUG_COLOR=y
-# CONFIG_RT_DEBUG_INIT_CONFIG is not set
-# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
-# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
-# CONFIG_RT_DEBUG_IPC_CONFIG is not set
-# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
-# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
-# CONFIG_RT_DEBUG_MEM_CONFIG is not set
-# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
-# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
-# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
-
-#
-# Inter-Thread communication
-#
-CONFIG_RT_USING_SEMAPHORE=y
-CONFIG_RT_USING_MUTEX=y
-CONFIG_RT_USING_EVENT=y
-CONFIG_RT_USING_MAILBOX=y
-CONFIG_RT_USING_MESSAGEQUEUE=y
-# CONFIG_RT_USING_SIGNALS is not set
-
-#
-# Memory Management
-#
-CONFIG_RT_USING_MEMPOOL=y
-# CONFIG_RT_USING_MEMHEAP is not set
-# CONFIG_RT_USING_NOHEAP is not set
-CONFIG_RT_USING_SMALL_MEM=y
-# CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMTRACE is not set
-CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
-CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_INTERRUPT_INFO is not set
-CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-# CONFIG_RT_USING_MODULE is not set
-CONFIG_ARCH_ARM=y
-CONFIG_ARCH_ARM_CORTEX_A=y
-CONFIG_ARCH_ARM_CORTEX_A7=y
-
-#
-# RT-Thread Components
-#
-CONFIG_RT_USING_COMPONENTS_INIT=y
-CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
-CONFIG_RT_MAIN_THREAD_PRIORITY=10
-
-#
-# C++ features
-#
-# CONFIG_RT_USING_CPLUSPLUS is not set
-
-#
-# Command shell
-#
-CONFIG_RT_USING_FINSH=y
-CONFIG_FINSH_THREAD_NAME="tshell"
-CONFIG_FINSH_USING_HISTORY=y
-CONFIG_FINSH_HISTORY_LINES=5
-CONFIG_FINSH_USING_SYMTAB=y
-CONFIG_FINSH_USING_DESCRIPTION=y
-# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
-# CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-CONFIG_FINSH_USING_MSH_ONLY=y
-CONFIG_FINSH_ARG_MAX=10
-
-#
-# Device virtual file system
-#
-# CONFIG_RT_USING_DFS is not set
-
-#
-# Device Drivers
-#
-CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_PIPE_BUFSZ=512
-CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
-# CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
-# CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
-# CONFIG_RT_USING_PIN is not set
-# CONFIG_RT_USING_PWM is not set
-# CONFIG_RT_USING_MTD_NOR is not set
-# CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
-# CONFIG_RT_USING_WDT is not set
-# CONFIG_RT_USING_WIFI is not set
-# CONFIG_RT_USING_AUDIO is not set
-
-#
-# Using USB
-#
-# CONFIG_RT_USING_USB_HOST is not set
-# CONFIG_RT_USING_USB_DEVICE is not set
-
-#
-# POSIX layer and C standard library
-#
-# CONFIG_RT_USING_LIBC is not set
-# CONFIG_RT_USING_PTHREADS is not set
-
-#
-# Network
-#
-
-#
-# Socket abstraction layer
-#
-# CONFIG_RT_USING_SAL is not set
-
-#
-# light weight TCP/IP stack
-#
-# CONFIG_RT_USING_LWIP is not set
-
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
-
-#
-# AT commands
-#
-# CONFIG_RT_USING_AT is not set
-
-#
-# VBUS(Virtual Software BUS)
-#
-# CONFIG_RT_USING_VBUS is not set
-
-#
-# Utilities
-#
-# CONFIG_RT_USING_LOGTRACE is not set
-# CONFIG_RT_USING_RYM is not set
-
-#
-# RT-Thread online packages
-#
-
-#
-# IoT - internet of things
-#
-# CONFIG_PKG_USING_PAHOMQTT is not set
-# CONFIG_PKG_USING_WEBCLIENT is not set
-# CONFIG_PKG_USING_MONGOOSE is not set
-# CONFIG_PKG_USING_WEBTERMINAL is not set
-# CONFIG_PKG_USING_CJSON is not set
-# CONFIG_PKG_USING_JSMN is not set
-# CONFIG_PKG_USING_LJSON is not set
-# CONFIG_PKG_USING_EZXML is not set
-# CONFIG_PKG_USING_NANOPB is not set
-
-#
-# Wi-Fi
-#
-
-#
-# Marvell WiFi
-#
-# CONFIG_PKG_USING_WLANMARVELL is not set
-
-#
-# Wiced WiFi
-#
-# CONFIG_PKG_USING_WLAN_WICED is not set
-# CONFIG_PKG_USING_COAP is not set
-# CONFIG_PKG_USING_NOPOLL is not set
-# CONFIG_PKG_USING_NETUTILS is not set
-# CONFIG_PKG_USING_AT_DEVICE is not set
-
-#
-# IoT Cloud
-#
-# CONFIG_PKG_USING_ONENET is not set
-# CONFIG_PKG_USING_GAGENT_CLOUD is not set
-# CONFIG_PKG_USING_ALI_IOTKIT is not set
-# CONFIG_PKG_USING_AZURE is not set
-
-#
-# security packages
-#
-# CONFIG_PKG_USING_MBEDTLS is not set
-# CONFIG_PKG_USING_libsodium is not set
-# CONFIG_PKG_USING_TINYCRYPT is not set
-
-#
-# language packages
-#
-# CONFIG_PKG_USING_LUA is not set
-# CONFIG_PKG_USING_JERRYSCRIPT is not set
-# CONFIG_PKG_USING_MICROPYTHON is not set
-
-#
-# multimedia packages
-#
-# CONFIG_PKG_USING_OPENMV is not set
-# CONFIG_PKG_USING_MUPDF is not set
-
-#
-# tools packages
-#
-# CONFIG_PKG_USING_CMBACKTRACE is not set
-# CONFIG_PKG_USING_EASYFLASH is not set
-# CONFIG_PKG_USING_EASYLOGGER is not set
-# CONFIG_PKG_USING_SYSTEMVIEW is not set
-
-#
-# system packages
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_PERSIMMON is not set
-# CONFIG_PKG_USING_CAIRO is not set
-# CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_FAL is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-
-#
-# peripheral libraries and drivers
-#
-# CONFIG_PKG_USING_STM32F4_HAL is not set
-# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
-# CONFIG_PKG_USING_SHT2X is not set
-# CONFIG_PKG_USING_AHT10 is not set
-
-#
-# miscellaneous packages
-#
-# CONFIG_PKG_USING_LIBCSV is not set
-# CONFIG_PKG_USING_OPTPARSE is not set
-# CONFIG_PKG_USING_FASTLZ is not set
-# CONFIG_PKG_USING_MINILZO is not set
-# CONFIG_PKG_USING_QUICKLZ is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
-# CONFIG_PKG_USING_CANFESTIVAL is not set
-# CONFIG_PKG_USING_ZLIB is not set
-# CONFIG_PKG_USING_DSTR is not set
-
-#
-# sample package
-#
-# CONFIG_PKG_USING_SAMPLES is not set
-
-#
-# example package: hello
-#
-# CONFIG_PKG_USING_HELLO is not set
-CONFIG_BCM2836_SOC=y
-CONFIG_RT_USING_UART1=y
diff --git a/bsp/raspi2/Kconfig b/bsp/raspi2/Kconfig
deleted file mode 100644
index 06cbe1128f..0000000000
--- a/bsp/raspi2/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-mainmenu "RT-Thread Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config RTT_DIR
-    string
-    option env="RTT_ROOT"
-    default "../.."
-
-config PKGS_DIR
-    string
-    option env="PKGS_ROOT"
-    default "packages"
-
-source "$RTT_DIR/Kconfig"
-source "$PKGS_DIR/Kconfig"
-
-config BCM2836_SOC
-    bool
-    select ARCH_ARM_CORTEX_A7
-    select RT_USING_COMPONENTS_INIT
-    select RT_USING_USER_MAIN
-    default y
-
-source "driver/Kconfig"
diff --git a/bsp/raspi2/README.md b/bsp/raspi2/README.md
deleted file mode 100644
index d65a954728..0000000000
--- a/bsp/raspi2/README.md
+++ /dev/null
@@ -1,106 +0,0 @@
-# Raspberry PI 2B板级支持包说明
-
-## 1. 简介
-
-树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派2采用4核Broadcom BCM2836 (ARMv7-A)芯片、双核VideoCore IV GPU和1GB内存。
-
-这份RT-Thread BSP是针对 Raspberry Pi 2B 的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
-
-![raspi2](figures/raspi2.png)
-
-当前Raspberry Pi 2B对应的硬件特性：
-
-| 硬件   | 描述 |
-|------- | ------------------------------- |
-|  CPU   | ARM Cortex-A7（4核心） |
-|  主频  | 900M |
-| Memory | 1GB  (0x0000000 - 0x40000000) |
-| | 其中0x3f000000 - 0x40000000为peripheral |
-
-## 2. 编译说明
-
-Windows环境下推荐使用[env工具][1]进行编译。
-
-Linux下推荐使用gcc工具 [gcc-arm-none-eabi-4_8-2014q1_linux][2]，如果还没有编译工具，下载后，解开文件。
-
-```
-tar vxf gcc-arm-none-eabi-4_8-2014q1_linux.tar.bz2
-```
-
-Linux环境下需要修改编译器目录设置，修改`bsp/raspi2/rtconfig.py`中的
-
-```
-EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
-```
-
-为编译工具的实际所在目录，这里注意要加上后缀 `/bin`
-
-进入到`rt-thread/bsp/raspi2`目录中，运行以下命令：
-
-```
-scons
-```
-
-来编译这个板级支持包。如果编译正确无误，会产生kernel.elf、kernel.img文件。
-kernel.img即是要cp到raspberry SD卡中根目录的文件
-
-## 3. 执行
-
-### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
-
-Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
-
-解开下载的镜像文件, linux下使用如下的命令
-
-```
-unzip 2018-06-27-raspbian-stretch-lite.zip
-```
-
-准备一张空SD卡，linux环境下，插入电脑并执行
-
-```
-sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
-```
-
-**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
-
-Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
-
-最后把kernel7.img放入SD boot分区，覆盖原来的文件。
-
-### 3.2 准备好串口线
-
-目前版本是使用raspi2的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
-
-![raspi2](figures/raspi_uart.png)
-
-串口参数： 115200 8N1 ，硬件和软件流控为关。
-
-按上面的方法做好SD卡后，插入树莓派2B，通电可以在串口上看到如下所示的输出信息：
-
-```text
- heap: 0x00020b20 - 0x00400000
-
- \ | /
-- RT -     Thread Operating System
- / | \     3.1.0 build Aug 23 2018
- 2006 - 2018 Copyright by rt-thread team
-Hello RT-Thread!
-msh >
-```
-
-## 4. 支持情况
-
-| 驱动 | 支持情况  |  备注  |
-| ------ | ----  | :------:  |
-| UART | 支持 | UART0|
-
-## 5. 联系人信息
-
-维护人：[bernard][5]
-
-  [1]: https://www.rt-thread.org/page/download.html
-  [2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2
-  [3]: https://downloads.raspberrypi.org/raspbian_lite_latest
-  [4]: https://etcher.io
-  [5]: https://github.com/BernardXiong
diff --git a/bsp/raspi2/SConscript b/bsp/raspi2/SConscript
deleted file mode 100644
index c7ef7659ec..0000000000
--- a/bsp/raspi2/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# for module compiling
-import os
-from building import *
-
-cwd = GetCurrentDir()
-objs = []
-list = os.listdir(cwd)
-
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')
diff --git a/bsp/raspi2/SConstruct b/bsp/raspi2/SConstruct
deleted file mode 100644
index e5acdb2554..0000000000
--- a/bsp/raspi2/SConstruct
+++ /dev/null
@@ -1,28 +0,0 @@
-import os
-import sys
-import rtconfig
-
-from rtconfig import RTT_ROOT
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread.' + rtconfig.TARGET_EXT
-
-DefaultEnvironment(tools=[])
-env = Environment(tools = ['mingw'],
-    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
-    AR = rtconfig.AR, ARFLAGS = '-rc',
-    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
-
-# make a building
-DoBuilding(TARGET, objs)
diff --git a/bsp/raspi2/applications/SConscript b/bsp/raspi2/applications/SConscript
deleted file mode 100644
index 533df8ac31..0000000000
--- a/bsp/raspi2/applications/SConscript
+++ /dev/null
@@ -1,9 +0,0 @@
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/raspi2/applications/main.c b/bsp/raspi2/applications/main.c
deleted file mode 100644
index 101386fdfd..0000000000
--- a/bsp/raspi2/applications/main.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-5-30      Bernard      the first version
- */
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <rtthread.h>
-
-int main(int argc, char** argv)
-{
-    rt_kprintf("Hello RT-Thread!\n");
-
-    return 0;
-}
-
diff --git a/bsp/raspi2/applications/mnt.c b/bsp/raspi2/applications/mnt.c
deleted file mode 100644
index 8da1dc1ece..0000000000
--- a/bsp/raspi2/applications/mnt.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * File      : mnt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-#include <rtthread.h>
-
-int mnt_init(void)
-{
-    return 0;
-}
diff --git a/bsp/raspi2/cpu/SConscript b/bsp/raspi2/cpu/SConscript
deleted file mode 100644
index eb4ee7a585..0000000000
--- a/bsp/raspi2/cpu/SConscript
+++ /dev/null
@@ -1,9 +0,0 @@
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/raspi2/cpu/armv7.h b/bsp/raspi2/cpu/armv7.h
deleted file mode 100644
index a07d9de2a9..0000000000
--- a/bsp/raspi2/cpu/armv7.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef __ARMV7_H__
-#define __ARMV7_H__
-
-/* the exception stack without VFP registers */
-struct rt_hw_exp_stack
-{
-    unsigned long r0;
-    unsigned long r1;
-    unsigned long r2;
-    unsigned long r3;
-    unsigned long r4;
-    unsigned long r5;
-    unsigned long r6;
-    unsigned long r7;
-    unsigned long r8;
-    unsigned long r9;
-    unsigned long r10;
-    unsigned long fp;
-    unsigned long ip;
-    unsigned long sp;
-    unsigned long lr;
-    unsigned long pc;
-    unsigned long cpsr;
-};
-
-struct rt_hw_stack
-{
-    unsigned long cpsr;
-    unsigned long r0;
-    unsigned long r1;
-    unsigned long r2;
-    unsigned long r3;
-    unsigned long r4;
-    unsigned long r5;
-    unsigned long r6;
-    unsigned long r7;
-    unsigned long r8;
-    unsigned long r9;
-    unsigned long r10;
-    unsigned long fp;
-    unsigned long ip;
-    unsigned long lr;
-    unsigned long pc;
-};
-
-#define USERMODE    0x10
-#define FIQMODE     0x11
-#define IRQMODE     0x12
-#define SVCMODE     0x13
-#define MONITORMODE 0x16
-#define ABORTMODE   0x17
-#define HYPMODE     0x1b
-#define UNDEFMODE   0x1b
-#define MODEMASK    0x1f
-#define NOINT       0xc0
-
-#define T_Bit       (1<<5)
-#define F_Bit       (1<<6)
-#define I_Bit       (1<<7)
-#define A_Bit       (1<<8)
-#define E_Bit       (1<<9)
-#define J_Bit       (1<<24)
-
-#endif
diff --git a/bsp/raspi2/cpu/context_gcc.S b/bsp/raspi2/cpu/context_gcc.S
deleted file mode 100644
index 48402739f9..0000000000
--- a/bsp/raspi2/cpu/context_gcc.S
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * File      : context.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.section .text, "ax"
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mrs r0, cpsr
-    cpsid i
-    bx  lr
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    msr cpsr_c, r0
-    bx  lr
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
- */
-.globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    ldr sp, [r0]            @ get new task stack pointer
-
-    ldmfd sp!, {r4}         @ pop new task spsr
-    msr spsr_cxsf, r4
-
-    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
-
-.section .bss.share.isr
-_guest_switch_lvl:
-    .word 0
-
-.globl vmm_virq_update
-
-.section .text.isr, "ax"
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r0 --> from
- * r1 --> to
- */
-.globl rt_hw_context_switch
-rt_hw_context_switch:
-    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
-    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
-
-    mrs r4, cpsr
-    tst lr, #0x01
-    orrne r4, r4, #0x20     @ it's thumb code
-
-    stmfd sp!, {r4}         @ push cpsr
-
-    str sp, [r0]            @ store sp in preempted tasks TCB
-    ldr sp, [r1]            @ get new task stack pointer
-
-    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
-    msr spsr_cxsf, r4
-    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
- */
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    ldr r2, =rt_thread_switch_interrupt_flag
-    ldr r3, [r2]
-    cmp r3, #1
-    beq _reswitch
-    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
-    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
-    str r0, [ip]
-    str r3, [r2]
-_reswitch:
-    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
-    str r1, [r2]
-    bx  lr
diff --git a/bsp/raspi2/cpu/cp15.h b/bsp/raspi2/cpu/cp15.h
deleted file mode 100644
index ebea3f0fe3..0000000000
--- a/bsp/raspi2/cpu/cp15.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __CP15_H__
-#define __CP15_H__
-
-unsigned long rt_cpu_get_smp_id(void);
-
-void rt_cpu_mmu_disable(void);
-void rt_cpu_mmu_enable(void);
-void rt_cpu_tlb_set(volatile unsigned long*);
-
-void rt_cpu_vector_set_base(unsigned int addr);
-
-#endif
diff --git a/bsp/raspi2/cpu/cp15_gcc.S b/bsp/raspi2/cpu/cp15_gcc.S
deleted file mode 100644
index f1ed6492aa..0000000000
--- a/bsp/raspi2/cpu/cp15_gcc.S
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * File      : cp15_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- * http://www.rt-thread.org
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.globl rt_cpu_get_smp_id
-rt_cpu_get_smp_id:
-    mrc     p15, #0, r0, c0, c0, #5
-    bx      lr
-
-.globl rt_cpu_vector_set_base
-rt_cpu_vector_set_base:
-    mcr     p15, #0, r0, c12, c0, #0
-    dsb
-    bx      lr
-
-.globl rt_hw_cpu_dcache_enable
-rt_hw_cpu_dcache_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0,  r0, #0x00000004
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-.globl rt_hw_cpu_icache_enable
-rt_hw_cpu_icache_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0,  r0, #0x00001000
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-_FLD_MAX_WAY:
-   .word  0x3ff
-_FLD_MAX_IDX:
-   .word  0x7ff
-
-.globl rt_cpu_dcache_clean_flush
-rt_cpu_dcache_clean_flush:
-    push    {r4-r11}
-    dmb
-    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
-    ands    r3, r0, #0x7000000       @ get level of coherency
-    mov     r3, r3, lsr #23
-    beq     finished
-    mov     r10, #0
-loop1:
-    add     r2, r10, r10, lsr #1
-    mov     r1, r0, lsr r2
-    and     r1, r1, #7
-    cmp     r1, #2
-    blt     skip
-    mcr     p15, #2, r10, c0, c0, #0
-    isb
-    mrc     p15, #1, r1, c0, c0, #0
-    and     r2, r1, #7
-    add     r2, r2, #4
-    ldr     r4, _FLD_MAX_WAY
-    ands    r4, r4, r1, lsr #3
-    clz     r5, r4
-    ldr     r7, _FLD_MAX_IDX
-    ands    r7, r7, r1, lsr #13
-loop2:
-    mov     r9, r4
-loop3:
-    orr     r11, r10, r9, lsl r5
-    orr     r11, r11, r7, lsl r2
-    mcr     p15, #0, r11, c7, c14, #2
-    subs    r9, r9, #1
-    bge     loop3
-    subs    r7, r7, #1
-    bge     loop2
-skip:
-    add     r10, r10, #2
-    cmp     r3, r10
-    bgt     loop1
-
-finished:
-    dsb
-    isb
-    pop     {r4-r11}
-    bx      lr
-
-.globl rt_hw_cpu_dcache_disable
-rt_hw_cpu_dcache_disable:
-    push    {r4-r11, lr}
-    bl      rt_cpu_dcache_clean_flush
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0,  r0, #0x00000004
-    mcr     p15, #0, r0, c1, c0, #0
-    pop     {r4-r11, lr}
-    bx      lr
-
-.globl rt_hw_cpu_icache_disable
-rt_hw_cpu_icache_disable:
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0,  r0, #0x00001000
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-.globl rt_cpu_mmu_disable
-rt_cpu_mmu_disable:
-    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0, r0, #1
-    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
-    dsb
-    bx      lr
-
-.globl rt_cpu_mmu_enable
-rt_cpu_mmu_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0, r0, #0x001
-    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
-    dsb
-    bx      lr
-
-.globl rt_cpu_tlb_set
-rt_cpu_tlb_set:
-    mcr     p15, #0, r0, c2, c0, #0
-    dmb
-    bx      lr
diff --git a/bsp/raspi2/cpu/cpu.c b/bsp/raspi2/cpu/cpu.c
deleted file mode 100644
index 8bf16d19e8..0000000000
--- a/bsp/raspi2/cpu/cpu.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <board.h>
-
-/**
- * @addtogroup AM33xx
- */
-/*@{*/
-
-/** shutdown CPU */
-void rt_hw_cpu_shutdown()
-{
-    rt_uint32_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}
-
-/*@}*/
diff --git a/bsp/raspi2/cpu/interrupt.c b/bsp/raspi2/cpu/interrupt.c
deleted file mode 100644
index d502977c3e..0000000000
--- a/bsp/raspi2/cpu/interrupt.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018/5/3       Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "cp15.h"
-#include <board.h>
-
-#define MAX_HANDLERS                64
-
-extern volatile rt_uint8_t rt_interrupt_nest;
-
-/* exception and interrupt handler table */
-struct rt_irq_desc isr_table[MAX_HANDLERS];
-
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-extern int system_vectors;
-
-static void default_isr_handler(int vector, void *param)
-{
-    rt_kprintf("unhandled irq: %d\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    uint32_t index;
-
-    /* mask all of interrupts */
-    IRQ_DISABLE_BASIC = 0x000000ff;
-    IRQ_DISABLE1      = 0xffffffff;
-    IRQ_DISABLE2      = 0xffffffff;
-
-    for (index = 0; index < MAX_HANDLERS; index ++)
-    {
-        isr_table[index].handler = default_isr_handler;
-        isr_table[index].param = NULL;
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
-        isr_table[index].counter = 0;
-#endif
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-    if (vector < 8)
-    {
-        IRQ_DISABLE_BASIC = (1 << vector);
-    }
-    else if (vector < 32)
-    {
-        IRQ_DISABLE1 = (1 << vector);
-    }
-    else
-    {
-        vector = vector % 32;
-        IRQ_DISABLE2 = (1 << vector);
-    }
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    if (vector < 8)
-    {
-        IRQ_ENABLE_BASIC = (1 << vector);
-    }
-    else if (vector < 32)
-    {
-        IRQ_ENABLE1 = (1 << vector);
-    }
-    else
-    {
-        vector = vector % 32;
-        IRQ_ENABLE2 = (1 << vector);
-    }
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector < MAX_HANDLERS)
-    {
-        old_handler = isr_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-            isr_table[vector].handler = handler;
-            isr_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
diff --git a/bsp/raspi2/cpu/mmu.c b/bsp/raspi2/cpu/mmu.c
deleted file mode 100644
index b2503e4260..0000000000
--- a/bsp/raspi2/cpu/mmu.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * File      : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2012-01-10     bernard      porting to AM1808
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <board.h>
-
-#include "cp15.h"
-
-#define DESC_SEC       (0x2)
-#define CB             (3<<2)  //cache_on, write_back
-#define CNB            (2<<2)  //cache_on, write_through
-#define NCB            (1<<2)  //cache_off,WR_BUF on
-#define NCNB           (0<<2)  //cache_off,WR_BUF off
-#define AP_RW          (3<<10) //supervisor=RW, user=RW
-#define AP_RO          (2<<10) //supervisor=RW, user=RO
-#define XN             (1<<4)  // eXecute Never
-
-#define DOMAIN_FAULT   (0x0)
-#define DOMAIN_CHK     (0x1)
-#define DOMAIN_NOTCHK  (0x3)
-#define DOMAIN0        (0x0<<5)
-#define DOMAIN1        (0x1<<5)
-
-#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
-
-/* Read/Write, cache, write back */
-#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
-/* Read/Write, cache, write through */
-#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
-/* Read/Write without cache and write buffer */
-#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
-/* Read/Write without cache and write buffer, no execute */
-#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
-/* Read/Write without cache and write buffer */
-#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
-
-/* dump 2nd level page table */
-void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    for (i = 0; i < 256; i++)
-    {
-        rt_uint32_t pte2 = ptb[i];
-        if ((pte2 & 0x3) == 0)
-        {
-            if (fcnt == 0)
-                rt_kprintf("    ");
-            rt_kprintf("%04x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("    %04x: %x: ", i, pte2);
-        if ((pte2 & 0x3) == 0x1)
-        {
-            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
-                       (pte2 >> 15) & 0x1,
-                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
-                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
-        }
-    }
-}
-
-void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    rt_kprintf("page table@%p\n", ptb);
-    for (i = 0; i < 1024*4; i++)
-    {
-        rt_uint32_t pte1 = ptb[i];
-        if ((pte1 & 0x3) == 0)
-        {
-            rt_kprintf("%03x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("%03x: %08x: ", i, pte1);
-        if ((pte1 & 0x3) == 0x3)
-        {
-            rt_kprintf("LPAE\n");
-        }
-        else if ((pte1 & 0x3) == 0x1)
-        {
-            rt_kprintf("pte,ns:%d,domain:%d\n",
-                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
-            /*
-             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
-             *                               - 0x80000000 + 0xC0000000));
-             */
-        }
-        else if (pte1 & (1 << 18))
-        {
-            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("section,ns:%d,ap:%x,"
-                       "xn:%d,texcb:%02x,domain:%d\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       (((pte1 & (0x7 << 12)) >> 10) |
-                        ((pte1 &        0x0c) >>  2)) & 0x1f,
-                       (pte1 >> 5) & 0xf);
-        }
-    }
-}
-
-/* level1 page table, each entry for 1MB memory. */
-volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
-void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
-                      rt_uint32_t vaddrEnd,
-                      rt_uint32_t paddrStart,
-                      rt_uint32_t attr)
-{
-    volatile rt_uint32_t *pTT;
-    volatile int i, nSec;
-    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
-    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
-    for(i = 0; i <= nSec; i++)
-    {
-        *pTT = attr | (((paddrStart >> 20) + i) << 20);
-        pTT++;
-    }
-}
-
-unsigned long rt_hw_set_domain_register(unsigned long domain_val)
-{
-    unsigned long old_domain;
-
-    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
-    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
-
-    return old_domain;
-}
-
-void rt_hw_mmu_init(void)
-{
-    rt_hw_cpu_dcache_disable();
-    rt_hw_cpu_icache_disable();
-    rt_cpu_mmu_disable();
-
-    /* set page table */
-    /* 4G 1:1 memory */
-    rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
-    /* IO memory region */
-    rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
-
-    /*rt_hw_cpu_dump_page_table(MMUTable);*/
-    rt_hw_set_domain_register(0x55555555);
-
-    rt_cpu_tlb_set(MMUTable);
-
-    rt_cpu_mmu_enable();
-
-    rt_hw_cpu_icache_enable();
-    rt_hw_cpu_dcache_enable();
-}
-
diff --git a/bsp/raspi2/cpu/stack.c b/bsp/raspi2/cpu/stack.c
deleted file mode 100644
index e60e8c7170..0000000000
--- a/bsp/raspi2/cpu/stack.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-23     Bernard      the first version
- * 2011-10-05     Bernard      add thumb mode
- */
-#include <rtthread.h>
-#include <board.h>
-#include <armv7.h>
-
-/**
- * @addtogroup AM33xx
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-                             rt_uint8_t *stack_addr, void *texit)
-{
-    rt_uint32_t *stk;
-
-    stack_addr += sizeof(rt_uint32_t);
-    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
-    stk      = (rt_uint32_t *)stack_addr;
-    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
-    *(--stk) = (rt_uint32_t)texit;          /* lr */
-    *(--stk) = 0xdeadbeef;                  /* r12 */
-    *(--stk) = 0xdeadbeef;                  /* r11 */
-    *(--stk) = 0xdeadbeef;                  /* r10 */
-    *(--stk) = 0xdeadbeef;                  /* r9 */
-    *(--stk) = 0xdeadbeef;                  /* r8 */
-    *(--stk) = 0xdeadbeef;                  /* r7 */
-    *(--stk) = 0xdeadbeef;                  /* r6 */
-    *(--stk) = 0xdeadbeef;                  /* r5 */
-    *(--stk) = 0xdeadbeef;                  /* r4 */
-    *(--stk) = 0xdeadbeef;                  /* r3 */
-    *(--stk) = 0xdeadbeef;                  /* r2 */
-    *(--stk) = 0xdeadbeef;                  /* r1 */
-    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
-
-    /* cpsr */
-    if ((rt_uint32_t)tentry & 0x01)
-        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
-    else
-        *(--stk) = SVCMODE;                 /* arm mode   */
-
-    /* return task's current stack address */
-    return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/bsp/raspi2/cpu/start_gcc.S b/bsp/raspi2/cpu/start_gcc.S
deleted file mode 100644
index b60ad6a38f..0000000000
--- a/bsp/raspi2/cpu/start_gcc.S
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.equ Mode_USR,        0x10
-.equ Mode_FIQ,        0x11
-.equ Mode_IRQ,        0x12
-.equ Mode_SVC,        0x13
-.equ Mode_ABT,        0x17
-.equ Mode_UND,        0x1B
-.equ Mode_SYS,        0x1F
-
-.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
-.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
-
-.equ UND_Stack_Size,     0x00000000
-.equ SVC_Stack_Size,     0x00000100
-.equ ABT_Stack_Size,     0x00000000
-.equ RT_FIQ_STACK_PGSZ,  0x00000000
-.equ RT_IRQ_STACK_PGSZ,  0x00000100
-.equ USR_Stack_Size,     0x00000100
-
-#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
-                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
-
-.section .data.share.isr
-/* stack */
-.globl stack_start
-.globl stack_top
-
-.align 3
-stack_start:
-.rept ISR_Stack_Size
-.byte 0
-.endr
-stack_top:
-
-.text
-/* reset entry */
-.globl _reset
-_reset:
-	/* Disable IRQ & FIQ */
-	cpsid if
-
-	/* Check for HYP mode */
-	mrs r0, cpsr_all
-	and r0, r0, #0x1F
-	mov r8, #0x1A
-	cmp r0, r8
-	beq overHyped
-	b continue
-
-overHyped: /* Get out of HYP mode */
-	ldr r1, =continue
-	msr ELR_hyp, r1
-	mrs r1, cpsr_all
-	and r1, r1, #0x1f	;@ CPSR_MODE_MASK
-	orr r1, r1, #0x13	;@ CPSR_MODE_SUPERVISOR
-	msr SPSR_hyp, r1
-	eret
-
-continue:
-
-    /* disable smp */
-    bl      arm_smp_disable
-
-    /* disable mmu */
-    bl      rt_cpu_mmu_disable
-    /* set the cpu to SVC32 mode and disable interrupt */
-    mrs     r0, cpsr
-    bic     r0, r0, #0x1f
-    orr     r0, r0, #0x13
-    msr     cpsr_c, r0
-
-    /* setup stack */
-    bl      stack_setup
-
-    /* clear .bss */
-    mov     r0,#0                   /* get a zero                       */
-    ldr     r1,=__bss_start         /* bss start                        */
-    ldr     r2,=__bss_end           /* bss end                          */
-
-bss_loop:
-    cmp     r1,r2                   /* check if data to clear           */
-    strlo   r0,[r1],#4              /* clear 4 bytes                    */
-    blo     bss_loop                /* loop until done                  */
-
-    /* start RT-Thread Kernel */
-    ldr     pc, _rtthread_startup
-_rtthread_startup:
-    .word rtthread_startup
-
-stack_setup:
-    ldr     r0, =stack_top
-
-    @  Set the startup stack for svc
-    mov     sp, r0
-	sub     r0, r0, #SVC_Stack_Size
-
-    @  Enter Undefined Instruction Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #UND_Stack_Size
-
-    @  Enter Abort Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #ABT_Stack_Size
-
-    @  Enter FIQ Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #RT_FIQ_STACK_PGSZ
-
-    @  Enter IRQ Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #RT_IRQ_STACK_PGSZ
-
-    /* come back to SVC mode */
-    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
-    bx      lr
-
-.text
-;@ void arm_smp_enable(void);
-.globl arm_smp_enable
-arm_smp_enable:
-    mrc p15, 0, r0, c1, c0, 1   ;@ set SMP bit in ACTLR
-    orr r0, r0, #0x40
-    mcr p15, 0, r0, c1, c0, 1
-    bx lr
-
-.text
-;@ void arm_smp_disable(void);
-.globl arm_smp_disable
-arm_smp_disable:
-    mrc p15, 0, r0, c1, c0, 1   ;@ clear SMP bit in ACTLR
-    bic r0, r0, #0x40
-    mcr p15, 0, r0, c1, c0, 1
-    bx lr
-
-/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
-.section .text.isr, "ax"
-    .align  5
-.globl vector_fiq
-vector_fiq:
-    stmfd   sp!,{r0-r7,lr}
-    bl      rt_hw_trap_fiq
-    ldmfd   sp!,{r0-r7,lr}
-    subs    pc, lr, #4
-
-.globl      rt_interrupt_enter
-.globl      rt_interrupt_leave
-.globl      rt_thread_switch_interrupt_flag
-.globl      rt_interrupt_from_thread
-.globl      rt_interrupt_to_thread
-
-.globl      rt_current_thread
-.globl      vmm_thread
-.globl      vmm_virq_check
-
-    .align  5
-.globl vector_irq
-vector_irq:
-    stmfd   sp!, {r0-r12,lr}
-
-    bl      rt_interrupt_enter
-    bl      rt_hw_trap_irq
-    bl      rt_interrupt_leave
-
-    @ if rt_thread_switch_interrupt_flag set, jump to
-    @ rt_hw_context_switch_interrupt_do and don't return
-    ldr     r0, =rt_thread_switch_interrupt_flag
-    ldr     r1, [r0]
-    cmp     r1, #1
-    beq     rt_hw_context_switch_interrupt_do
-
-    ldmfd   sp!, {r0-r12,lr}
-    subs    pc,  lr, #4
-
-rt_hw_context_switch_interrupt_do:
-    mov     r1,  #0         @ clear flag
-    str     r1,  [r0]
-
-    mov     r1, sp          @ r1 point to {r0-r3} in stack
-    add     sp, sp, #4*4
-    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
-    mrs     r0,  spsr       @ get cpsr of interrupt thread
-    sub     r2,  lr, #4     @ save old task's pc to r2
-
-    @ Switch to SVC mode with no interrupt. If the usr mode guest is
-    @ interrupted, this will just switch to the stack of kernel space.
-    @ save the registers in kernel space won't trigger data abort.
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
-    stmfd   sp!, {r2}       @ push old task's pc
-    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
-    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
-    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
-    stmfd   sp!, {r0}       @ push old task's cpsr
-
-    ldr     r4,  =rt_interrupt_from_thread
-    ldr     r5,  [r4]
-    str     sp,  [r5]       @ store sp in preempted tasks's TCB
-
-    ldr     r6,  =rt_interrupt_to_thread
-    ldr     r6,  [r6]
-    ldr     sp,  [r6]       @ get new task's stack pointer
-
-    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
-    msr     spsr_cxsf, r4
-
-    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
-
-.macro push_svc_reg
-    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
-    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
-    mov     r0, sp
-    mrs     r6, spsr                @/* Save CPSR                       */
-    str     lr, [r0, #15*4]         @/* Push PC                         */
-    str     r6, [r0, #16*4]         @/* Push CPSR                       */
-    cps     #Mode_SVC
-    str     sp, [r0, #13*4]         @/* Save calling SP                 */
-    str     lr, [r0, #14*4]         @/* Save calling PC                 */
-.endm
-
-    .align  5
-    .globl  vector_swi
-vector_swi:
-    push_svc_reg
-    bl      rt_hw_trap_swi
-    b       .
-
-    .align  5
-    .globl  vector_undef
-vector_undef:
-    push_svc_reg
-    bl      rt_hw_trap_undef
-    b       .
-
-    .align  5
-    .globl  vector_pabt
-vector_pabt:
-    push_svc_reg
-    bl      rt_hw_trap_pabt
-    b       .
-
-    .align  5
-    .globl  vector_dabt
-vector_dabt:
-    push_svc_reg
-    bl      rt_hw_trap_dabt
-    b       .
-
-    .align  5
-    .globl  vector_resv
-vector_resv:
-    push_svc_reg
-    bl      rt_hw_trap_resv
-    b       .
diff --git a/bsp/raspi2/cpu/trap.c b/bsp/raspi2/cpu/trap.c
deleted file mode 100644
index 3012c26e2c..0000000000
--- a/bsp/raspi2/cpu/trap.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-20     Bernard      first version
- */
-
-#include <rthw.h>
-#include <board.h>
-#include <rtthread.h>
-
-#include "armv7.h"
-
-extern struct rt_thread *rt_current_thread;
-#ifdef RT_USING_FINSH
-extern long list_thread(void);
-#endif
-
-/**
- * this function will show registers of CPU
- *
- * @param regs the registers point
- */
-void rt_hw_show_register(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("Execption:\n");
-    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
-}
-
-/**
- * When comes across an instruction which it cannot handle,
- * it takes the undefined instruction trap.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("undefined instruction:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * The software interrupt instruction (SWI) is used for entering
- * Supervisor mode, usually to request a particular supervisor
- * function.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("software interrupt:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * An abort indicates that the current memory access cannot be completed,
- * which occurs during an instruction prefetch.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("prefetch abort:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * An abort indicates that the current memory access cannot be completed,
- * which occurs during a data access.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("data abort:");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * Normally, system will never reach here
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("reserved trap:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-void rt_hw_trap_irq(void)
-{
-    void *param;
-    rt_isr_handler_t isr_func;
-    extern struct rt_irq_desc isr_table[];
-
-    uint32_t value = 0;
-
-    // rt_kprintf("pend basic: 0x%08x\n", IRQ_PEND_BASIC);
-    // rt_kprintf("     pend1: 0x%08x\n", IRQ_PEND1);
-    // rt_kprintf("     pend2: 0x%08x\n", IRQ_PEND2);
-
-    value = IRQ_PEND_BASIC & 0x3ff;
-    if (value)
-    {
-        uint32_t irq;
-
-        if (value & (1 << 8))
-        {
-            value = IRQ_PEND1;
-            irq = __rt_ffs(value) - 1;
-        }
-        else if (value & (1 << 9))
-        {
-            value = IRQ_PEND2;
-            irq = __rt_ffs(value) + 31;
-        }
-        else
-        {
-            value &= 0x0f;
-            irq = __rt_ffs(value) - 1;
-        }
-
-        /* get interrupt service routine */
-        isr_func = isr_table[irq].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-        isr_table[irq].counter++;
-#endif
-        if (isr_func)
-        {
-            /* Interrupt for myself. */
-            param = isr_table[irq].param;
-            /* turn to interrupt service routine */
-            isr_func(irq, param);
-        }
-    }
-}
-
-void rt_hw_trap_fiq(void)
-{
-    /* TODO */
-}
diff --git a/bsp/raspi2/cpu/vector_gcc.S b/bsp/raspi2/cpu/vector_gcc.S
deleted file mode 100644
index 17c2d69c30..0000000000
--- a/bsp/raspi2/cpu/vector_gcc.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * File      : vector_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.section .vectors, "ax"
-.code 32
-
-.globl system_vectors
-system_vectors:
-    ldr pc, _vector_reset
-    ldr pc, _vector_undef
-    ldr pc, _vector_swi
-    ldr pc, _vector_pabt
-    ldr pc, _vector_dabt
-    ldr pc, _vector_resv
-    ldr pc, _vector_irq
-    ldr pc, _vector_fiq
-
-.globl _reset
-.globl vector_undef
-.globl vector_swi
-.globl vector_pabt
-.globl vector_dabt
-.globl vector_resv
-.globl vector_irq
-.globl vector_fiq
-
-_vector_reset:
-    .word _reset
-_vector_undef:
-    .word vector_undef
-_vector_swi:
-    .word vector_swi
-_vector_pabt:
-    .word vector_pabt
-_vector_dabt:
-    .word vector_dabt
-_vector_resv:
-    .word vector_resv
-_vector_irq:
-    .word vector_irq
-_vector_fiq:
-    .word vector_fiq
-
-.balignl    16,0xdeadbeef
diff --git a/bsp/raspi2/driver/Kconfig b/bsp/raspi2/driver/Kconfig
deleted file mode 100644
index 95c536178d..0000000000
--- a/bsp/raspi2/driver/Kconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-config RT_USING_UART1
-    bool "Enable UART1"
-    default y
diff --git a/bsp/raspi2/driver/SConscript b/bsp/raspi2/driver/SConscript
deleted file mode 100644
index 25e7ef2e55..0000000000
--- a/bsp/raspi2/driver/SConscript
+++ /dev/null
@@ -1,17 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Split('''
-board.c
-drv_uart.c
-''')
-CPPPATH = [cwd]
-
-if GetDepend('RT_USING_PIN'):
-    src += ['drv_gpio.c']
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/raspi2/driver/bcm283x.h b/bsp/raspi2/driver/bcm283x.h
deleted file mode 100644
index 85422e2a22..0000000000
--- a/bsp/raspi2/driver/bcm283x.h
+++ /dev/null
@@ -1,125 +0,0 @@
-#ifndef BCM283X_H__
-#define BCM283X_H__
-
-#include <rthw.h>
-
-#define PER_BASE    		(0x3F000000)
-#define PER_BASE_40000000 	(0x40000000)
-
-/*
- *  GPIO
- */
-#define GPIO_BASE       (PER_BASE + 0x200000)
-#define GPIO_GPFSEL0    HWREG32(GPIO_BASE + 0x00)  /* GPIO Function Select 0 32bit R/W */
-#define GPIO_GPFSEL1    HWREG32(GPIO_BASE + 0x04)  /* GPIO Function Select 1 32bit R/W */
-#define GPIO_GPFSEL2    HWREG32(GPIO_BASE + 0x08)  /* GPIO Function Select 2 32bit R/W */
-#define GPIO_GPFSEL4    HWREG32(GPIO_BASE + 0x10)  /* GPIO Function Select 4 32bit R/W */
-#define GPIO_GPSET0     HWREG32(GPIO_BASE + 0x1C)
-#define GPIO_GPCLR0     HWREG32(GPIO_BASE + 0x28)
-#define GPIO_GPPUD      HWREG32(GPIO_BASE + 0x94)  /* GPIO Pin Pull-up/down Enable */
-#define GPIO_GPPUDCLK0  HWREG32(GPIO_BASE + 0x98)  /* GPIO Pin Pull-up/down Enable Clock 0 */
-#define GPIO_GPPUDCLK1  HWREG32(GPIO_BASE + 0x9C)  /* GPIO Pin Pull-up/down Enable Clock 1 */
-
-/*
- *  Interrupt Controler
- */
-#define IRQ_BASE            (PER_BASE + 0xB200)
-#define IRQ_PEND_BASIC      HWREG32(IRQ_BASE + 0x00)
-#define IRQ_PEND1           HWREG32(IRQ_BASE + 0x04)
-#define IRQ_PEND2           HWREG32(IRQ_BASE + 0x08)
-#define IRQ_FIQ_CONTROL     HWREG32(IRQ_BASE + 0x0C)
-#define IRQ_ENABLE1         HWREG32(IRQ_BASE + 0x10)
-#define IRQ_ENABLE2         HWREG32(IRQ_BASE + 0x14)
-#define IRQ_ENABLE_BASIC    HWREG32(IRQ_BASE + 0x18)
-#define IRQ_DISABLE1        HWREG32(IRQ_BASE + 0x1C)
-#define IRQ_DISABLE2        HWREG32(IRQ_BASE + 0x20)
-#define IRQ_DISABLE_BASIC   HWREG32(IRQ_BASE + 0x24)
-
-/*
- *  System Timer
- */
-#define STIMER_BASE         (PER_BASE  + 0x3000)
-#define STIMER_CS           HWREG32(STIMER_BASE + 0x00)
-#define STIMER_CLO          HWREG32(STIMER_BASE + 0x04)
-#define STIMER_CHI          HWREG32(STIMER_BASE + 0x08)
-#define STIMER_C0           HWREG32(STIMER_BASE + 0x0C)
-#define STIMER_C1           HWREG32(STIMER_BASE + 0x10)
-#define STIMER_C2           HWREG32(STIMER_BASE + 0x14)
-#define STIMER_C3           HWREG32(STIMER_BASE + 0x18)
-
-/*
- * ARM Timer
- */
-#define ARM_TIMER_BASE		(PER_BASE + 0xB000)
-
-#define ARM_TIMER_LOAD		HWREG32(ARM_TIMER_BASE + 0x400)
-#define ARM_TIMER_VALUE		HWREG32(ARM_TIMER_BASE + 0x404)
-#define ARM_TIMER_CTRL		HWREG32(ARM_TIMER_BASE + 0x408)
-#define ARM_TIMER_IRQCLR	HWREG32(ARM_TIMER_BASE + 0x40C)
-#define ARM_TIMER_RAWIRQ	HWREG32(ARM_TIMER_BASE + 0x410)
-#define ARM_TIMER_MASKIRQ	HWREG32(ARM_TIMER_BASE + 0x414)
-#define ARM_TIMER_RELOAD	HWREG32(ARM_TIMER_BASE + 0x418)
-#define ARM_TIMER_PREDIV	HWREG32(ARM_TIMER_BASE + 0x41C)
-#define ARM_TIMER_CNTR		HWREG32(ARM_TIMER_BASE + 0x420)
-
-/*
- *  Core Timer
- */
-#define CTIMER_CTL          HWREG32(PER_BASE_40000000 + 0x00)  /* Control register */
-#define CTIMER_PRE          HWREG32(PER_BASE_40000000 + 0x08)  /* Core timer prescaler */
-#define CTIMER_LS32B        HWREG32(PER_BASE_40000000 + 0x1C)  /* Core timer access LS 32 bits */
-#define CTIMER_MS32B        HWREG32(PER_BASE_40000000 + 0x20)  /* Core timer access MS 32 bits */
-
-/*
- *  ARM Core Timer
- */
-#define C0TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x40)  /* Core0 timers Interrupt control */
-#define C1TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x44)  /* Core1 timers Interrupt control */
-#define C2TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x48)  /* Core2 timers Interrupt control */
-#define C3TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x4C)  /* Core3 timers Interrupt control */
-
-/*
- *  ARM Core Mailbox interrupt
- */
-#define C0MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x50)  /* Core0 Mailboxes Interrupt control */
-#define C1MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x54)  /* Core1 Mailboxes Interrupt control */
-#define C2MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x58)  /* Core2 Mailboxes Interrupt control */
-#define C3MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x5C)  /* Core3 Mailboxes Interrupt control */
-
-/*
- *  ARM Core IRQ/FIQ status
- */
-#define C0_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x60)  /* Core0 IRQ Source */
-#define C1_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x64)  /* Core1 IRQ Source */
-#define C2_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x68)  /* Core2 IRQ Source */
-#define C3_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x6C)  /* Core3 IRQ Source */
-#define C0_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x70)  /* Core0 FIQ Source */
-#define C1_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x74)  /* Core1 FIQ Source */
-#define C2_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x78)  /* Core2 FIQ Source */
-#define C3_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x7C)  /* Core3 FIQ Source */
-
-#define IRQ_ARM_TIMER           0
-#define IRQ_ARM_MAILBOX         1
-#define IRQ_ARM_DB0             2
-#define IRQ_ARM_DB1             3
-#define IRQ_ARM_GPU0_HALT       4
-#define IRQ_ARM_GPU1_HALT       5
-#define IRQ_ARM_ILLEGAL_ACC1    6
-#define IRQ_ARM_ILLEGAL_ACC0    7
-
-#define IRQ_AUX                 29
-#define IRQ_IIC_SPI_SLV         43
-#define IRQ_PWA0                45
-#define IRQ_PWA1                46
-#define IRQ_SMI                 48
-#define IRQ_GPIO0               49
-#define IRQ_GPIO1               50
-#define IRQ_GPIO2               51
-#define IRQ_GPIO3               52
-#define IRQ_IIC                 53
-#define IRQ_SPI                 54
-#define IRQ_PCM                 55
-#define IRQ_UART                57
-
-#endif
-
diff --git a/bsp/raspi2/driver/board.c b/bsp/raspi2/driver/board.c
deleted file mode 100644
index 30f8cd93a1..0000000000
--- a/bsp/raspi2/driver/board.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#include "drv_uart.h"
-
-void rt_hw_timer_isr(int vector, void *parameter)
-{
-    ARM_TIMER_IRQCLR = 0;
-
-    rt_tick_increase();
-}
-
-int rt_hw_timer_init(void)
-{
-    /* timer_clock = apb_clock/(pre_divider + 1) */
-    ARM_TIMER_PREDIV = (250 - 1);
-
-    ARM_TIMER_RELOAD = 0;
-    ARM_TIMER_LOAD   = 0;
-    ARM_TIMER_IRQCLR = 0;
-    ARM_TIMER_CTRL   = 0;
-
-    ARM_TIMER_RELOAD = 10000;
-    ARM_TIMER_LOAD   = 10000;
-
-    /* 23-bit counter, enable interrupt, enable timer */
-    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
-
-    rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
-    rt_hw_interrupt_umask(IRQ_ARM_TIMER);
-
-    return 0;
-}
-
-void vector_copy(void)
-{
-    rt_memcpy((void*)0x0, (void*)0x8000, 64);
-}
-
-void rt_hw_board_init(void)
-{
-    /* initialize hardware interrupt */
-    rt_hw_interrupt_init();
-    vector_copy();
-
-    /* initialize uart */
-    rt_hw_uart_init();
-
-#ifdef RT_USING_CONSOLE
-    /* set console device */
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif /* RT_USING_CONSOLE */
-
-#ifdef RT_USING_HEAP
-    /* initialize memory system */
-    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-#endif
-
-    /* initialize timer for os tick */
-    // rt_hw_timer_init();
-
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
-#endif
-}
diff --git a/bsp/raspi2/driver/board.h b/bsp/raspi2/driver/board.h
deleted file mode 100644
index 92ef5de76c..0000000000
--- a/bsp/raspi2/driver/board.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-5-30      Bernard      the first version
- */
-
-#ifndef BOARD_H__
-#define BOARD_H__
-
-#include <stdint.h>
-
-#include <rthw.h>
-#include <bcm283x.h>
-
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-
-#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
-#define RT_HW_HEAP_END      (void*)(0x0 + 4 * 1024 * 1024)
-
-void rt_hw_board_init(void);
-
-#endif
-
diff --git a/bsp/raspi2/driver/drv_uart.c b/bsp/raspi2/driver/drv_uart.c
deleted file mode 100644
index de7b987c2a..0000000000
--- a/bsp/raspi2/driver/drv_uart.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * File      : drv_uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018/5/5       Bernard      The first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <rtdevice.h>
-
-#include "board.h"
-#include "drv_uart.h"
-
-#include <rtdevice.h>
-
-#define AUX_BASE            (0x3F000000 + 0x215000)
-
-struct hw_uart_device
-{
-    rt_uint32_t hw_base;
-    rt_uint32_t irqno;
-};
-
-static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    struct hw_uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct hw_uart_device *)serial->parent.user_data;
-
-    if (uart->hw_base == AUX_BASE)
-    {
-        uint32_t value;
-
-        /* GPIO function set */
-        value = GPIO_GPFSEL1;
-        value &= ~(7<<12); /* GPIO14 */
-        value |=    2<<12 ; /* ALT5 */
-        value &= ~(7<<15); /* GPIO15 */
-        value |=    2<<15 ; /* ALT5 */
-        GPIO_GPFSEL1 = value;
-
-        /* PullUD disable */
-        GPIO_GPPUD = 0;
-        GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15);
-        GPIO_GPPUDCLK0 = 0;
-
-        AUX_ENABLES(uart->hw_base)      = 1;    /* Enable UART1 */
-        AUX_MU_IER_REG(uart->hw_base)   = 0;    /* Disable interrupt */
-        AUX_MU_CNTL_REG(uart->hw_base)  = 0;    /* Disable Transmitter and Receiver */
-        AUX_MU_LCR_REG(uart->hw_base)   = 3;    /* Works in 8-bit mode */
-        AUX_MU_MCR_REG(uart->hw_base)   = 0;    /* Disable RTS */
-        AUX_MU_IIR_REG(uart->hw_base)   = 0xC6; /* Enable FIFO, Clear FIFO */
-        AUX_MU_BAUD_REG(uart->hw_base)  = 270;  /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
-        AUX_MU_CNTL_REG(uart->hw_base)  = 3;    /* Enable Transmitter and Receiver */
-    }
-
-    return RT_EOK;
-}
-
-static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    struct hw_uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct hw_uart_device *)serial->parent.user_data;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT:
-        /* disable rx irq */
-        AUX_MU_IER_REG(uart->hw_base) = 0x0;
-        rt_hw_interrupt_mask(uart->irqno);
-        break;
-
-    case RT_DEVICE_CTRL_SET_INT:
-        /* enable rx irq */
-        AUX_MU_IER_REG(uart->hw_base) = 0x1;
-        rt_hw_interrupt_umask(uart->irqno);
-        break;
-    }
-
-    return RT_EOK;
-}
-
-static int uart_putc(struct rt_serial_device *serial, char c)
-{
-    struct hw_uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct hw_uart_device *)serial->parent.user_data;
-
-    while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
-    AUX_MU_IO_REG(uart->hw_base) = c;
-
-    return 1;
-}
-
-static int uart_getc(struct rt_serial_device *serial)
-{
-    int ch = -1;
-    struct hw_uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct hw_uart_device *)serial->parent.user_data;
-
-    if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
-    {
-        ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
-    }
-
-    return ch;
-}
-
-static const struct rt_uart_ops _uart_ops =
-{
-    uart_configure,
-    uart_control,
-    uart_putc,
-    uart_getc,
-};
-
-static void rt_hw_uart_isr(int irqno, void *param)
-{
-    struct rt_serial_device *serial = (struct rt_serial_device*)param;
-
-    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-}
-
-#ifdef RT_USING_UART0
-/* UART device driver structure */
-static struct hw_uart_device _uart0_device =
-{
-    RPI_UART0_BASE,
-    IRQ_PBA8_UART0,
-};
-static struct rt_serial_device _serial0;
-#endif
-
-#ifdef RT_USING_UART1
-/* UART1 device driver structure */
-static struct hw_uart_device _uart1_device =
-{
-    AUX_BASE,
-    IRQ_AUX,
-};
-static struct rt_serial_device _serial1;
-#endif
-
-int rt_hw_uart_init(void)
-{
-    struct hw_uart_device *uart;
-    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
-
-#ifdef RT_USING_UART0
-    uart = &_uart0_device;
-
-    _serial0.ops    = &_uart_ops;
-    _serial0.config = config;
-
-    /* register UART1 device */
-    rt_hw_serial_register(&_serial0, "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-                          uart);
-    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
-#endif
-
-#ifdef RT_USING_UART1
-    uart = &_uart1_device;
-    _serial1.ops = &_uart_ops;
-    _serial1.config = config;
-
-    /* register UART1 device */
-    rt_hw_serial_register(&_serial1, "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
-    /* enable Rx and Tx of UART */
-    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1");
-#endif
-
-    return 0;
-}
diff --git a/bsp/raspi2/driver/drv_uart.h b/bsp/raspi2/driver/drv_uart.h
deleted file mode 100644
index e489eaae65..0000000000
--- a/bsp/raspi2/driver/drv_uart.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * File      : drv_uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-5-30      Bernard      the first version
- */
-
-
-#ifndef DRV_UART_H__
-#define DRV_UART_H__
-
-/*
- *  Auxiliary
- */
-#define AUX_IRQ(BASE)             HWREG32(BASE + 0x00)   /* Auxiliary Interrupt status 3 */
-#define AUX_ENABLES(BASE)         HWREG32(BASE + 0x04)   /* Auxiliary enables 3bit */
-#define AUX_MU_IO_REG(BASE)       HWREG32(BASE + 0x40)   /* Mini Uart I/O Data 8bit */
-#define AUX_MU_IER_REG(BASE)      HWREG32(BASE + 0x44)   /* Mini Uart Interrupt Enable 8bit */
-#define AUX_MU_IIR_REG(BASE)      HWREG32(BASE + 0x48)   /* Mini Uart Interrupt Identify 8bit */
-#define AUX_MU_LCR_REG(BASE)      HWREG32(BASE + 0x4C)   /* Mini Uart Line Control 8bit */
-#define AUX_MU_MCR_REG(BASE)      HWREG32(BASE + 0x50)   /* Mini Uart Modem Control 8bit */
-#define AUX_MU_LSR_REG(BASE)      HWREG32(BASE + 0x54)   /* Mini Uart Line Status 8bit */
-#define AUX_MU_MSR_REG(BASE)      HWREG32(BASE + 0x58)   /* Mini Uart Modem Status 8bit */
-#define AUX_MU_SCRATCH(BASE)      HWREG32(BASE + 0x5C)   /* Mini Uart Scratch 8bit */
-#define AUX_MU_CNTL_REG(BASE)     HWREG32(BASE + 0x60)   /* Mini Uart Extra Control 8bit */
-#define AUX_MU_STAT_REG(BASE)     HWREG32(BASE + 0x64)   /* Mini Uart Extra Status 32bit */
-#define AUX_MU_BAUD_REG(BASE)     HWREG32(BASE + 0x68)   /* Mini Uart Baudrate 16bit */
-#define AUX_SPI0_CNTL0_REG(BASE)  HWREG32(BASE + 0x80)   /* SPI 1 Control register 0 32bit */
-#define AUX_SPI0_CNTL1_REG(BASE)  HWREG32(BASE + 0x84)   /* SPI 1 Control register 1 8bit */
-#define AUX_SPI0_STAT_REG(BASE)   HWREG32(BASE + 0x88)   /* SPI 1 Status 32bit */
-#define AUX_SPI0_IO_REG(BASE)     HWREG32(BASE + 0x90)   /* SPI 1 Data 32bit */
-#define AUX_SPI0_PEEK_REG(BASE)   HWREG32(BASE + 0x94)   /* SPI 1 Peek 16bit */
-#define AUX_SPI1_CNTL0_REG(BASE)  HWREG32(BASE + 0xC0)   /* SPI 2 Control register 0 32bit */
-#define AUX_SPI1_CNTL1_REG(BASE)  HWREG32(BASE + 0xC4)   /* SPI 2 Control register 1 8bit */
-
-int rt_hw_uart_init(void);
-
-#endif /* DRV_UART_H__ */
-
diff --git a/bsp/raspi2/figures/raspi2.png b/bsp/raspi2/figures/raspi2.png
deleted file mode 100644
index 2f2e25d9cb..0000000000
Binary files a/bsp/raspi2/figures/raspi2.png and /dev/null differ
diff --git a/bsp/raspi2/figures/raspi_uart.png b/bsp/raspi2/figures/raspi_uart.png
deleted file mode 100644
index c6ae382182..0000000000
Binary files a/bsp/raspi2/figures/raspi_uart.png and /dev/null differ
diff --git a/bsp/raspi2/link.lds b/bsp/raspi2/link.lds
deleted file mode 100644
index 75e0845943..0000000000
--- a/bsp/raspi2/link.lds
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * File      : link.lds
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * 2017-5-30     bernard       first version
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-
-SECTIONS
-{
-    . = 0x00008000;
-    . = ALIGN(4);
-    .text :
-    {
-        *(.vectors)
-        *(.text)                        /* remaining code */
-        *(.text.*)                      /* remaining code */
-
-        *(.rodata)                      /* read-only data (constants) */
-        *(.rodata*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.gnu.linkonce.t*)
-
-        /* section information for finsh shell */
-        . = ALIGN(4);
-        __fsymtab_start = .;
-        KEEP(*(FSymTab))
-        __fsymtab_end = .;
-        . = ALIGN(4);
-        __vsymtab_start = .;
-        KEEP(*(VSymTab))
-        __vsymtab_end = .;
-        . = ALIGN(4);
-
-        /* section information for initial. */
-        . = ALIGN(4);
-        __rt_init_start = .;
-        KEEP(*(SORT(.rti_fn*)))
-        __rt_init_end = .;
-        . = ALIGN(4);
-
-        . = ALIGN(4);
-        _etext = .;
-    }
-
-    .eh_frame_hdr :
-    {
-         *(.eh_frame_hdr)
-         *(.eh_frame_entry)
-    }
-    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
-
-    . = ALIGN(4);
-    .data :
-    {
-     *(.data)
-     *(.data.*)
-
-     *(.data1)
-     *(.data1.*)
-
-     . = ALIGN(8);
-     _gp = ABSOLUTE(.);     /* Base of small data */
-
-     *(.sdata)
-     *(.sdata.*)
-    }
-
-    . = ALIGN(4);
-    .ctors :
-    {
-        PROVIDE(__ctors_start__ = .);
-        KEEP(*(SORT(.ctors.*)))
-        KEEP(*(.ctors))
-        PROVIDE(__ctors_end__ = .);
-    }
-
-    .dtors :
-    {
-        PROVIDE(__dtors_start__ = .);
-        KEEP(*(SORT(.dtors.*)))
-        KEEP(*(.dtors))
-        PROVIDE(__dtors_end__ = .);
-    }
-
-    . = ALIGN(4);
-    .bss :
-    {
-        PROVIDE(__bss_start = .);
-        *(.bss)
-        *(.bss.*)
-        *(.dynbss)
-        *(COMMON)
-        PROVIDE(__bss_end = .);
-    }
-    _end = .;
-
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-     * Symbols in the DWARF debugging sections are relative to the beginning
-     * of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-}
diff --git a/bsp/raspi2/rtconfig.h b/bsp/raspi2/rtconfig.h
deleted file mode 100644
index a144bc0550..0000000000
--- a/bsp/raspi2/rtconfig.h
+++ /dev/null
@@ -1,259 +0,0 @@
-#ifndef RT_CONFIG_H__
-#define RT_CONFIG_H__
-
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Project Configuration */
-
-/* RT-Thread Kernel */
-
-#define RT_NAME_MAX 8
-#define RT_ALIGN_SIZE 4
-/* RT_THREAD_PRIORITY_8 is not set */
-#define RT_THREAD_PRIORITY_32
-/* RT_THREAD_PRIORITY_256 is not set */
-#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 100
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_HOOK
-#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 256
-/* RT_USING_TIMER_SOFT is not set */
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-/* RT_DEBUG_INIT_CONFIG is not set */
-/* RT_DEBUG_THREAD_CONFIG is not set */
-/* RT_DEBUG_SCHEDULER_CONFIG is not set */
-/* RT_DEBUG_IPC_CONFIG is not set */
-/* RT_DEBUG_TIMER_CONFIG is not set */
-/* RT_DEBUG_IRQ_CONFIG is not set */
-/* RT_DEBUG_MEM_CONFIG is not set */
-/* RT_DEBUG_SLAB_CONFIG is not set */
-/* RT_DEBUG_MEMHEAP_CONFIG is not set */
-/* RT_DEBUG_MODULE_CONFIG is not set */
-
-/* Inter-Thread communication */
-
-#define RT_USING_SEMAPHORE
-#define RT_USING_MUTEX
-#define RT_USING_EVENT
-#define RT_USING_MAILBOX
-#define RT_USING_MESSAGEQUEUE
-/* RT_USING_SIGNALS is not set */
-
-/* Memory Management */
-
-#define RT_USING_MEMPOOL
-/* RT_USING_MEMHEAP is not set */
-/* RT_USING_NOHEAP is not set */
-#define RT_USING_SMALL_MEM
-/* RT_USING_SLAB is not set */
-/* RT_USING_MEMTRACE is not set */
-#define RT_USING_HEAP
-
-/* Kernel Device Object */
-
-#define RT_USING_DEVICE
-/* RT_USING_DEVICE_OPS is not set */
-/* RT_USING_INTERRUPT_INFO is not set */
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart1"
-/* RT_USING_MODULE is not set */
-#define ARCH_ARM
-#define ARCH_ARM_CORTEX_A
-#define ARCH_ARM_CORTEX_A7
-
-/* RT-Thread Components */
-
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
-
-/* C++ features */
-
-/* RT_USING_CPLUSPLUS is not set */
-
-/* Command shell */
-
-#define RT_USING_FINSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-/* FINSH_ECHO_DISABLE_DEFAULT is not set */
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
-#define FINSH_CMD_SIZE 80
-/* FINSH_USING_AUTH is not set */
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
-#define FINSH_USING_MSH_ONLY
-#define FINSH_ARG_MAX 10
-
-/* Device virtual file system */
-
-/* RT_USING_DFS is not set */
-
-/* Device Drivers */
-
-#define RT_USING_DEVICE_IPC
-#define RT_PIPE_BUFSZ 512
-#define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
-/* RT_USING_CAN is not set */
-/* RT_USING_HWTIMER is not set */
-/* RT_USING_CPUTIME is not set */
-/* RT_USING_I2C is not set */
-/* RT_USING_PIN is not set */
-/* RT_USING_PWM is not set */
-/* RT_USING_MTD_NOR is not set */
-/* RT_USING_MTD_NAND is not set */
-/* RT_USING_RTC is not set */
-/* RT_USING_SDIO is not set */
-/* RT_USING_SPI is not set */
-/* RT_USING_WDT is not set */
-/* RT_USING_WIFI is not set */
-/* RT_USING_AUDIO is not set */
-
-/* Using USB */
-
-/* RT_USING_USB_HOST is not set */
-/* RT_USING_USB_DEVICE is not set */
-
-/* POSIX layer and C standard library */
-
-/* RT_USING_LIBC is not set */
-/* RT_USING_PTHREADS is not set */
-
-/* Network */
-
-/* Socket abstraction layer */
-
-/* RT_USING_SAL is not set */
-
-/* light weight TCP/IP stack */
-
-/* RT_USING_LWIP is not set */
-
-/* Modbus master and slave stack */
-
-/* RT_USING_MODBUS is not set */
-
-/* AT commands */
-
-/* RT_USING_AT is not set */
-
-/* VBUS(Virtual Software BUS) */
-
-/* RT_USING_VBUS is not set */
-
-/* Utilities */
-
-/* RT_USING_LOGTRACE is not set */
-/* RT_USING_RYM is not set */
-
-/* RT-Thread online packages */
-
-/* IoT - internet of things */
-
-/* PKG_USING_PAHOMQTT is not set */
-/* PKG_USING_WEBCLIENT is not set */
-/* PKG_USING_MONGOOSE is not set */
-/* PKG_USING_WEBTERMINAL is not set */
-/* PKG_USING_CJSON is not set */
-/* PKG_USING_JSMN is not set */
-/* PKG_USING_LJSON is not set */
-/* PKG_USING_EZXML is not set */
-/* PKG_USING_NANOPB is not set */
-
-/* Wi-Fi */
-
-/* Marvell WiFi */
-
-/* PKG_USING_WLANMARVELL is not set */
-
-/* Wiced WiFi */
-
-/* PKG_USING_WLAN_WICED is not set */
-/* PKG_USING_COAP is not set */
-/* PKG_USING_NOPOLL is not set */
-/* PKG_USING_NETUTILS is not set */
-/* PKG_USING_AT_DEVICE is not set */
-
-/* IoT Cloud */
-
-/* PKG_USING_ONENET is not set */
-/* PKG_USING_GAGENT_CLOUD is not set */
-/* PKG_USING_ALI_IOTKIT is not set */
-/* PKG_USING_AZURE is not set */
-
-/* security packages */
-
-/* PKG_USING_MBEDTLS is not set */
-/* PKG_USING_libsodium is not set */
-/* PKG_USING_TINYCRYPT is not set */
-
-/* language packages */
-
-/* PKG_USING_LUA is not set */
-/* PKG_USING_JERRYSCRIPT is not set */
-/* PKG_USING_MICROPYTHON is not set */
-
-/* multimedia packages */
-
-/* PKG_USING_OPENMV is not set */
-/* PKG_USING_MUPDF is not set */
-
-/* tools packages */
-
-/* PKG_USING_CMBACKTRACE is not set */
-/* PKG_USING_EASYFLASH is not set */
-/* PKG_USING_EASYLOGGER is not set */
-/* PKG_USING_SYSTEMVIEW is not set */
-
-/* system packages */
-
-/* PKG_USING_GUIENGINE is not set */
-/* PKG_USING_PERSIMMON is not set */
-/* PKG_USING_CAIRO is not set */
-/* PKG_USING_PIXMAN is not set */
-/* PKG_USING_LWEXT4 is not set */
-/* PKG_USING_PARTITION is not set */
-/* PKG_USING_FAL is not set */
-/* PKG_USING_SQLITE is not set */
-/* PKG_USING_RTI is not set */
-/* PKG_USING_LITTLEVGL2RTT is not set */
-
-/* peripheral libraries and drivers */
-
-/* PKG_USING_STM32F4_HAL is not set */
-/* PKG_USING_STM32F4_DRIVERS is not set */
-/* PKG_USING_REALTEK_AMEBA is not set */
-/* PKG_USING_SHT2X is not set */
-/* PKG_USING_AHT10 is not set */
-
-/* miscellaneous packages */
-
-/* PKG_USING_LIBCSV is not set */
-/* PKG_USING_OPTPARSE is not set */
-/* PKG_USING_FASTLZ is not set */
-/* PKG_USING_MINILZO is not set */
-/* PKG_USING_QUICKLZ is not set */
-/* PKG_USING_MULTIBUTTON is not set */
-/* PKG_USING_CANFESTIVAL is not set */
-/* PKG_USING_ZLIB is not set */
-/* PKG_USING_DSTR is not set */
-
-/* sample package */
-
-/* PKG_USING_SAMPLES is not set */
-
-/* example package: hello */
-
-/* PKG_USING_HELLO is not set */
-#define BCM2836_SOC
-#define RT_USING_UART1
-
-#endif
diff --git a/bsp/raspi2/rtconfig.py b/bsp/raspi2/rtconfig.py
deleted file mode 100644
index 37475595a2..0000000000
--- a/bsp/raspi2/rtconfig.py
+++ /dev/null
@@ -1,53 +0,0 @@
-import os
-
-# toolchains options
-ARCH        ='arm'
-CPU         ='cortex-a7'
-CROSS_TOOL  ='gcc'
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = r'../..'
-
-if os.getenv('RTT_CC'):
-    CROSS_TOOL = os.getenv('RTT_CC')
-
-PLATFORM    = 'gcc'
-EXEC_PATH   = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
-
-if os.getenv('RTT_EXEC_PATH'):
-    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
-BUILD = 'debug'
-
-if PLATFORM == 'gcc':
-    # toolchains
-    PREFIX = 'arm-none-eabi-'
-    CC      = PREFIX + 'gcc'
-    CXX     = PREFIX + 'g++'
-    AS      = PREFIX + 'gcc'
-    AR      = PREFIX + 'ar'
-    LINK    = PREFIX + 'gcc'
-    TARGET_EXT = 'elf'
-    SIZE    = PREFIX + 'size'
-    OBJDUMP = PREFIX + 'objdump'
-    OBJCPY  = PREFIX + 'objcopy'
-
-    DEVICE = ' -mfpu=neon-vfpv4 -mfloat-abi=softfp -march=armv7-a -mtune=cortex-a7 -ftree-vectorize -ffast-math'
-    CFLAGS = DEVICE + ' -Wall'
-    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
-    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
-    CPATH   = ''
-    LPATH   = ''
-
-    if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
-    else:
-        CFLAGS += ' -O2'
-
-    CXXFLAGS = CFLAGS
-
-DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n'
diff --git a/libcpu/aarch64/SConscript b/libcpu/aarch64/SConscript
new file mode 100644
index 0000000000..453afe4b3e
--- /dev/null
+++ b/libcpu/aarch64/SConscript
@@ -0,0 +1,16 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# cpu porting code files
+if rtconfig.CPU != 'common':
+    group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript
new file mode 100644
index 0000000000..57a5accc5c
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/SConscript
@@ -0,0 +1,15 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+asm_src = Split('''
+context_gcc.S
+vector_gcc.S
+entry_point.S
+cpu_gcc.S
+''')
+CPPPATH = [cwd]
+
+group = DefineGroup('cpu', src + asm_src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/cortex-a53/armv8.h b/libcpu/aarch64/cortex-a53/armv8.h
new file mode 100644
index 0000000000..28ed50e1ac
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/armv8.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long long pc;
+	unsigned long long spsr;
+	unsigned long long x30;
+	unsigned long long xz;
+	unsigned long long x28;
+	unsigned long long x29;
+	unsigned long long x26;
+	unsigned long long x27;
+	unsigned long long x24;
+	unsigned long long x25;
+	unsigned long long x22;
+	unsigned long long x23;
+	unsigned long long x20;
+	unsigned long long x21;
+	unsigned long long x18;	
+	unsigned long long x19;
+	unsigned long long x16;
+	unsigned long long x17;
+	unsigned long long x14;
+	unsigned long long x15;
+	unsigned long long x12;
+	unsigned long long x13;
+	unsigned long long x10;
+	unsigned long long x11;
+	unsigned long long x8;
+	unsigned long long x9;
+	unsigned long long x6;
+	unsigned long long x7;
+	unsigned long long x4;
+	unsigned long long x5;
+	unsigned long long x2;
+	unsigned long long x3;
+	unsigned long long x0;
+	unsigned long long x1;
+};
+
+#define SP_ELx						( ( unsigned long long ) 0x01 )
+#define SP_EL0						( ( unsigned long long ) 0x00 )
+#define PSTATE_EL1					( ( unsigned long long ) 0x04 )
+#define PSTATE_EL2					( ( unsigned long long ) 0x08 )
+#define PSTATE_EL3					( ( unsigned long long ) 0x0c )
+
+rt_ubase_t rt_hw_get_current_el(void);
+void rt_hw_set_elx_env(void);
+void rt_hw_set_current_vbar(rt_ubase_t addr);
+
+#endif
diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S
new file mode 100644
index 0000000000..3812eb4b1a
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/context_gcc.S
@@ -0,0 +1,307 @@
+/*
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+.macro SAVE_CONTEXT
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Save the entire context. */
+    STP 	X0, X1, [SP, #-0x10]!
+    STP 	X2, X3, [SP, #-0x10]!
+    STP 	X4, X5, [SP, #-0x10]!
+    STP 	X6, X7, [SP, #-0x10]!
+    STP 	X8, X9, [SP, #-0x10]!
+    STP 	X10, X11, [SP, #-0x10]!
+    STP 	X12, X13, [SP, #-0x10]!
+    STP 	X14, X15, [SP, #-0x10]!
+    STP 	X16, X17, [SP, #-0x10]!
+    STP 	X18, X19, [SP, #-0x10]!
+    STP 	X20, X21, [SP, #-0x10]!
+    STP 	X22, X23, [SP, #-0x10]!
+    STP 	X24, X25, [SP, #-0x10]!
+    STP 	X26, X27, [SP, #-0x10]!
+    STP 	X28, X29, [SP, #-0x10]!
+    STP 	X30, XZR, [SP, #-0x10]!
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MRS		X3, SPSR_EL3
+    /* Save the ELR. */
+    MRS		X2, ELR_EL3
+    B		0f
+2:
+    MRS		X3, SPSR_EL2
+    /* Save the ELR. */
+    MRS		X2, ELR_EL2
+    B		0f
+1:
+    MRS		X3, SPSR_EL1
+    MRS		X2, ELR_EL1
+    B		0f
+0:
+
+    STP 	X2, X3, [SP, #-0x10]!
+
+    MOV 	X0, SP   /* Move SP into X0 for saving. */
+
+    /* Switch to use the ELx stack pointer. */
+    MSR 	SPSEL, #1
+
+    .endm
+
+.macro SAVE_CONTEXT_T
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Save the entire context. */
+    STP 	X0, X1, [SP, #-0x10]!
+    STP 	X2, X3, [SP, #-0x10]!
+    STP 	X4, X5, [SP, #-0x10]!
+    STP 	X6, X7, [SP, #-0x10]!
+    STP 	X8, X9, [SP, #-0x10]!
+    STP 	X10, X11, [SP, #-0x10]!
+    STP 	X12, X13, [SP, #-0x10]!
+    STP 	X14, X15, [SP, #-0x10]!
+    STP 	X16, X17, [SP, #-0x10]!
+    STP 	X18, X19, [SP, #-0x10]!
+    STP 	X20, X21, [SP, #-0x10]!
+    STP 	X22, X23, [SP, #-0x10]!
+    STP 	X24, X25, [SP, #-0x10]!
+    STP 	X26, X27, [SP, #-0x10]!
+    STP 	X28, X29, [SP, #-0x10]!
+    STP 	X30, XZR, [SP, #-0x10]!
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MRS		X3, SPSR_EL3
+    MOV		X2, X30
+    B		0f
+2:
+    MRS		X3, SPSR_EL2
+    MOV		X2, X30
+    B		0f
+1:
+    MRS		X3, SPSR_EL1
+    MOV		X2, X30
+    B		0f
+0:
+
+    STP 	X2, X3, [SP, #-0x10]!
+
+    MOV 	X0, SP   /* Move SP into X0 for saving. */
+
+    /* Switch to use the ELx stack pointer. */
+    MSR 	SPSEL, #1
+
+    .endm
+
+.macro RESTORE_CONTEXT
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Set the SP to point to the stack of the task being restored. */
+    MOV		SP, X0
+
+    LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MSR		SPSR_EL3, X3
+    MSR		ELR_EL3, X2
+    B		0f
+2:
+    MSR		SPSR_EL2, X3
+    MSR		ELR_EL2, X2
+    B		0f
+1:
+    MSR		SPSR_EL1, X3
+    MSR		ELR_EL1, X2
+    B		0f
+0:
+
+    LDP 	X30, XZR, [SP], #0x10
+    LDP 	X28, X29, [SP], #0x10
+    LDP 	X26, X27, [SP], #0x10
+    LDP 	X24, X25, [SP], #0x10
+    LDP 	X22, X23, [SP], #0x10
+    LDP 	X20, X21, [SP], #0x10
+    LDP 	X18, X19, [SP], #0x10
+    LDP 	X16, X17, [SP], #0x10
+    LDP 	X14, X15, [SP], #0x10
+    LDP 	X12, X13, [SP], #0x10
+    LDP 	X10, X11, [SP], #0x10
+    LDP 	X8, X9, [SP], #0x10
+    LDP 	X6, X7, [SP], #0x10
+    LDP 	X4, X5, [SP], #0x10
+    LDP 	X2, X3, [SP], #0x10
+    LDP 	X0, X1, [SP], #0x10
+
+    /* Switch to use the ELx stack pointer.  _RB_ Might not be required. */
+    MSR 	SPSEL, #1
+
+    ERET
+
+    .endm
+
+.text
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    MRS      X0, DAIF
+    MSR      DAIFSet, #3
+    DSB      SY
+    RET
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    DSB     SY
+    MOV     X1, #0xC0
+    ANDS    X0, X0, X1
+    B.NE    rt_hw_interrupt_enable_exit
+    MSR     DAIFClr, #3
+rt_hw_interrupt_enable_exit:
+    RET
+
+/*
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    LDR		X0, [X0]
+    RESTORE_CONTEXT
+
+.text
+/*
+ * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+
+    MOV		X8,X0
+    MOV		X9,X1
+
+    SAVE_CONTEXT_T
+    
+    STR		X0, [X8]            // store sp in preempted tasks TCB
+    LDR		X0, [X9]            // get new task stack pointer
+    
+    RESTORE_CONTEXT
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ADR 	X2, rt_thread_switch_interrupt_flag
+    LDR 	X3, [X2]
+    CMP 	X3, #1
+    B.EQ 	_reswitch
+    ADR 	X4, rt_interrupt_from_thread   // set rt_interrupt_from_thread
+    MOV 	X3, #1              // set rt_thread_switch_interrupt_flag to 1
+    STR 	X0, [X4]
+    STR 	X3, [X2]
+_reswitch:
+    ADR 	X2, rt_interrupt_to_thread     // set rt_interrupt_to_thread
+    STR 	X1, [X2]
+    RET
+
+.text
+
+// -- Exception handlers ----------------------------------
+
+    .align  8
+.globl vector_fiq
+vector_fiq:
+    SAVE_CONTEXT
+    STP 	X0, X1, [SP, #-0x10]!
+    BL      rt_hw_trap_fiq
+    LDP 	X0, X1, [SP], #0x10
+    RESTORE_CONTEXT
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+
+// -------------------------------------------------------------------
+
+    .align  8
+.globl vector_irq
+vector_irq:
+    SAVE_CONTEXT
+    STP 	X0, X1, [SP, #-0x10]!
+
+    BL      rt_interrupt_enter
+    BL      rt_hw_trap_irq
+    BL      rt_interrupt_leave
+    
+    LDP 	X0, X1, [SP], #0x10
+
+    // if rt_thread_switch_interrupt_flag set, jump to
+    // rt_hw_context_switch_interrupt_do and don't return
+    ADR 	X1, rt_thread_switch_interrupt_flag
+    LDR     X2, [X1]
+    CMP     X2, #1
+    B.NE     vector_irq_exit
+
+    MOV     X2,  #0         // clear flag
+    STR     X2,  [X1]
+
+    ADR     X3,  rt_interrupt_from_thread
+    LDR     X4,  [X3]
+    STR     x0,  [X4]       // store sp in preempted tasks's TCB
+
+    ADR     x3,  rt_interrupt_to_thread
+    LDR     X4,  [X3]
+    LDR     x0,  [X4]       // get new task's stack pointer
+    
+vector_irq_exit:	
+    RESTORE_CONTEXT
+
+// -------------------------------------------------
+
+    .align  8
+    .globl  vector_error
+vector_error:
+    SAVE_CONTEXT
+    BL      rt_hw_trap_error
+    B       .
diff --git a/libcpu/aarch64/cortex-a53/cp15.h b/libcpu/aarch64/cortex-a53/cp15.h
new file mode 100644
index 0000000000..26f6ef1a31
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/cp15.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __CP15_H__
+#define __CP15_H__
+
+#include "bcm283x.h"
+#ifndef   __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
+#endif
+
+#define __WFI()    __asm__ volatile ("wfi":::"memory")
+
+#define __WFE()    __asm__ volatile ("wfe":::"memory")
+
+#define __SEV()    __asm__ volatile ("sev")
+
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+    __asm__ volatile ("isb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+    __asm__ volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+    __asm__ volatile ("dmb 0xF":::"memory");
+}
+
+#ifdef RT_USING_SMP
+static inline void send_ipi_msg(int cpu, int ipi_vector)
+{
+    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
+}
+
+static inline void setup_bootstrap_addr(int cpu, int addr)
+{
+	CORE_MAILBOX3_SET(cpu) = addr;
+}
+
+static inline void enable_cpu_ipi_intr(int cpu)
+{
+    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
+}
+
+static inline void enable_cpu_timer_intr(int cpu)
+{
+	CORETIMER_INTCTL(cpu) = 0x8;
+}
+
+static inline void enable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline void disable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 0;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline  void mask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 2;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline void unmask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline rt_uint64_t read_cntvct(void)
+{
+    rt_uint32_t val,val1;
+    asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
+    return (val);
+}
+
+static inline rt_uint64_t read_cntvoff(void)
+{
+
+    rt_uint64_t val;
+    asm volatile("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
+    return (val);
+}
+
+static inline rt_uint32_t read_cntv_tval(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val) );
+    return val;
+}
+
+
+static inline  void write_cntv_tval(rt_uint32_t val)
+{
+    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val) );
+    return;
+}
+
+static inline rt_uint32_t read_cntfrq(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val) );
+    return val;
+}
+
+
+static inline  rt_uint32_t read_cntctrl(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val) );
+    return val;
+}
+
+static inline uint32_t write_cntctrl(uint32_t val)
+{
+
+    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val) );
+    return val;
+}
+#endif
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_dcache_clean_flush(void);
+void rt_cpu_icache_flush(void);
+
+void rt_cpu_vector_set_base(rt_ubase_t addr);
+void rt_hw_mmu_init(void);
+void rt_hw_vector_init(void);
+
+void set_timer_counter(unsigned int counter);
+void set_timer_control(unsigned int control);
+#endif
diff --git a/libcpu/aarch64/cortex-a53/cpu.c b/libcpu/aarch64/cortex-a53/cpu.c
new file mode 100644
index 0000000000..962a53a071
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/cpu.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+#include "cp15.h"
+
+int rt_hw_cpu_id(void)
+{
+    int cpu_id;
+    rt_base_t value;
+
+    __asm__ volatile (
+            "mrs %0, mpidr_el1"
+            :"=r"(value)
+            );
+    cpu_id = value & 0xf;
+    return cpu_id;
+};
+
+#ifdef RT_USING_SMP
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    lock->slock = 0;
+}
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    unsigned long tmp;
+    unsigned long newval;
+    rt_hw_spinlock_t lockval;
+    __asm__ __volatile__(
+            "pld [%0]"
+            ::"r"(&lock->slock)
+            );
+
+    __asm__ __volatile__(
+            "1: ldrex   %0, [%3]\n"
+            "   add %1, %0, %4\n"
+            "   strex   %2, %1, [%3]\n"
+            "   teq %2, #0\n"
+            "   bne 1b"
+            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+            : "r" (&lock->slock), "I" (1 << 16)
+            : "cc");
+
+    while (lockval.tickets.next != lockval.tickets.owner) {
+        __WFE();
+        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
+    }
+
+    __DMB();
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    __DMB();
+    lock->tickets.owner++;
+    __DSB();
+    __SEV();
+}
+#endif /*RT_USING_SMP*/
+
+/**
+ * @addtogroup ARM CPU
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/*@}*/
diff --git a/libcpu/aarch64/cortex-a53/cpu_gcc.S b/libcpu/aarch64/cortex-a53/cpu_gcc.S
new file mode 100644
index 0000000000..ab9a5706ae
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/cpu_gcc.S
@@ -0,0 +1,78 @@
+/*
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+ 
+.text
+.globl rt_hw_get_current_el
+rt_hw_get_current_el:
+	MRS		X0, CurrentEL
+	CMP		X0, 0xc
+	B.EQ	3f
+	CMP		X0, 0x8
+	B.EQ	2f
+	CMP		X0, 0x4
+	B.EQ	1f
+	
+	LDR		X0, =0
+	B		0f
+3:
+	LDR		X0, =3
+	B		0f
+2:
+	LDR		X0, =2
+	B		0f
+1:
+	LDR		X0, =1
+	B		0f
+0:
+	RET
+
+
+.globl rt_hw_set_current_vbar
+rt_hw_set_current_vbar:
+	MRS		X1, CurrentEL
+	CMP		X1, 0xc
+	B.EQ	3f
+	CMP		X1, 0x8
+	B.EQ	2f
+	CMP		X1, 0x4
+	B.EQ	1f
+	B		0f
+3:
+	MSR		VBAR_EL3,X0
+	B		0f
+2:
+	MSR		VBAR_EL2,X0
+	B		0f
+1:
+	MSR		VBAR_EL1,X0
+	B		0f
+0:
+	RET
+
+    
+.globl rt_hw_set_elx_env
+rt_hw_set_elx_env:
+	MRS		X1, CurrentEL
+	CMP		X1, 0xc
+	B.EQ	3f
+	CMP		X1, 0x8
+	B.EQ	2f
+	CMP		X1, 0x4
+	B.EQ	1f
+	B		0f
+3:
+	MRS		X0, SCR_EL3
+	ORR		X0, X0, #0xF			/* SCR_EL3.NS|IRQ|FIQ|EA */
+	MSR		SCR_EL3, X0
+	B		0f
+2:
+	MRS	X0, HCR_EL2
+	ORR	X0, X0, #0x38
+	MSR	HCR_EL2, X0
+	B		0f
+1:
+	B		0f
+0:
+	RET
diff --git a/libcpu/aarch64/cortex-a53/entry_point.S b/libcpu/aarch64/cortex-a53/entry_point.S
new file mode 100644
index 0000000000..098cd9a840
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/entry_point.S
@@ -0,0 +1,102 @@
+.section ".text.entrypoint"
+
+.set EL1_stack,         __el1_stack
+
+.global _start
+
+// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
+// loads 'kernel8.img' file in.
+_start:
+    // read cpu id, stop slave cores
+    mrs     x1, mpidr_el1            // MPIDR_EL1: Multi-Processor Affinity Register
+    and     x1, x1, #3
+    cbz     x1, .L__cpu_0             // .L prefix is the local label in ELF 
+
+    // cpu id > 0, stop
+    // cpu id == 0 will also goto here after returned from entry() if possible
+.L__current_cpu_idle:
+    wfe
+    b       .L__current_cpu_idle
+
+.L__cpu_0:  // cpu id == 0
+
+    // set stack before our code
+
+	/* Define stack pointer for current exception level */
+	// ldr	x2, =EL1_stack
+	// mov	sp, x2
+
+    ldr     x1, =_start
+
+    // set up EL1
+    mrs     x0, CurrentEL           // CurrentEL Register. bit 2, 3. Others reserved
+    and     x0, x0, #12             // clear reserved bits
+
+    // running at EL3?
+    cmp     x0, #12                // 1100b. So, EL3
+    bne     .L__not_in_el3         // 11?  !EL3 -> 5:
+
+    // should never be executed, just for completeness. (EL3)
+    mov     x2, #0x5b1
+    msr     scr_el3, x2            // SCR_ELn  Secure Configuration Register
+    mov     x2, #0x3c9
+    msr     spsr_el3, x2           // SPSR_ELn. Saved Program Status Register. 1111001001
+    adr     x2, .L__not_in_el3   
+    msr     elr_el3, x2
+    eret                           // Exception Return: from EL3, continue from .L__not_in_el3
+
+    // running at EL2 or EL1
+.L__not_in_el3:    
+    cmp     x0, #4                 // 0x04  0100 EL1
+    beq     .L__in_el1             // EL1 -> 5:
+
+    // in EL2
+    msr     sp_el1, x1             // Set sp of EL1 to _start
+
+    // enable CNTP for EL1
+    mrs     x0, cnthctl_el2         // Counter-timer Hypervisor Control register
+    orr     x0, x0, #3
+    msr     cnthctl_el2, x0
+    msr     cntvoff_el2, xzr
+
+    // enable AArch64 in EL1
+    mov     x0, #(1 << 31)          // AArch64
+    orr     x0, x0, #(1 << 1)       // SWIO hardwired on Pi3
+    msr     hcr_el2, x0
+    mrs     x0, hcr_el2
+
+    // change execution level to EL1
+    mov     x2, #0x3c4
+    msr     spsr_el2, x2        // 1111000100
+    adr     x2, .L__in_el1
+    msr     elr_el2, x2
+    eret                        // exception return. from EL2. continue from .L__in_el1
+
+.L__in_el1:
+    mov     sp, x1             // in EL1. Set sp to _start
+
+    // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
+    mov     x1, #0x00300000       // Don't trap any SIMD/FP instructions in both EL0 and EL1
+    msr     cpacr_el1, x1
+
+    mrs x1, sctlr_el1
+    orr x1, x1, #(1 << 12)
+    bic x1, x1, #(3 << 3)
+    bic x1, x1, #(1 << 1)
+    msr sctlr_el1, x1
+
+    // clear bss
+    ldr     x1, =__bss_start
+    ldr     w2, =__bss_size
+
+.L__clean_bss_loop:
+    cbz     w2, .L__jump_to_entry
+    str     xzr, [x1], #8
+    sub     w2, w2, #1
+    cbnz    w2, .L__clean_bss_loop
+
+    // jump to C code, should not return
+.L__jump_to_entry:
+    bl      entry
+    // for failsafe, halt this core too
+    b       .L__current_cpu_idle
diff --git a/libcpu/aarch64/cortex-a53/interrupt.c b/libcpu/aarch64/cortex-a53/interrupt.c
new file mode 100644
index 0000000000..8ad60c6de2
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/interrupt.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/5/3       Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "cp15.h"
+#include "armv8.h"
+
+#include <board.h>
+
+#define MAX_HANDLERS                72
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+extern int system_vectors;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_ubase_t rt_interrupt_from_thread;
+rt_ubase_t rt_interrupt_to_thread;
+rt_ubase_t rt_thread_switch_interrupt_flag;
+
+void rt_hw_vector_init(void)
+{
+    rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);  // cpu_gcc.S
+}
+
+static void default_isr_handler(int vector, void *param)
+{
+#ifdef RT_USING_SMP
+    rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
+#else
+    rt_kprintf("unhandled irq: %d\n",vector);
+#endif
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_uint32_t index;
+
+    /* mask all of interrupts */
+    IRQ_DISABLE_BASIC = 0x000000ff;
+    IRQ_DISABLE1      = 0xffffffff;
+    IRQ_DISABLE2      = 0xffffffff;
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        isr_table[index].handler = default_isr_handler;
+        isr_table[index].param = NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
+        isr_table[index].counter = 0;
+#endif
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    if (vector < 32)
+    {
+        IRQ_DISABLE1 = (1 << vector);
+    }
+    else if (vector<64)
+    {
+        vector = vector % 32;
+        IRQ_DISABLE2 = (1 << vector);
+    }
+    else
+    {
+        vector = vector - 64;
+        IRQ_DISABLE_BASIC = (1 << vector);
+    }
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    if (vector < 32)
+    {
+        IRQ_ENABLE1 = (1 << vector);
+    }
+    else if (vector < 64)
+    {
+        vector = vector % 32;
+        IRQ_ENABLE2 = (1 << vector);
+    }
+    else
+    {
+        vector = vector - 64;
+        IRQ_ENABLE_BASIC = (1 << vector);
+    }
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+{
+    __DSB();
+    if(cpu_mask & 0x1)
+    {
+        send_ipi_msg(0, ipi_vector);
+    }
+    if(cpu_mask & 0x2)
+    {
+    	send_ipi_msg(1, ipi_vector);
+    }
+    if(cpu_mask & 0x4)
+    {
+    	send_ipi_msg(2, ipi_vector);
+    }
+    if(cpu_mask & 0x8)
+    {
+    	send_ipi_msg(3, ipi_vector);
+    }
+    __DSB();
+}
+#endif
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
+{
+    /* note: ipi_vector maybe different with irq_vector */
+    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
+}
+#endif
diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h
new file mode 100644
index 0000000000..6e86516045
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/interrupt.h
@@ -0,0 +1,20 @@
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+//void rt_hw_vector_init(void);
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
new file mode 100644
index 0000000000..17b40c3b47
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/mmu.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "mmu.h"
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+#if 0
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+#else
+    return 0;
+#endif
+}
+
+void rt_hw_init_mmu_table()
+{
+    /* set page table */
+    /* 4G 1:1 memory */
+    rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
+    /* IO memory region */
+    rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
+}
+
+void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
+                      rt_uint32_t size,
+                      rt_uint32_t paddrStart, rt_uint32_t attr)
+{
+    rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
+}
+
+void rt_hw_mmu_init(void)
+{
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
new file mode 100644
index 0000000000..022d200f96
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/mmu.h
@@ -0,0 +1,51 @@
+#ifndef MMU_H__
+#define MMU_H__
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3<<2)  //cache_on, write_back
+#define CNB            (2<<2)  //cache_on, write_through
+#define NCB            (1<<2)  //cache_off,WR_BUF on
+#define NCNB           (0<<2)  //cache_off,WR_BUF off
+#define AP_RW          (3<<10) //supervisor=RW, user=RW
+#define AP_RO          (2<<10) //supervisor=RW, user=RO
+#define XN             (1<<4)  // eXecute Never
+#define SHARED         (1<<16) /* shareable */
+#define SHAREDEVICE    (1<<2)  /* shared device */
+#define STRONGORDER    (0<<2)  /* strong ordered */
+#define MEMWBWA        ((1<<12)|(3<<2))     /* write back, write allocate */
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
+/* Read/Write without cache and write buffer */
+#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+
+/* device mapping type */
+#define DEVICE_MEM     (SHARED|SHAREDEVICE|RW_NCNBXN)
+/* normal memory mapping type */
+#define NORMAL_MEM     (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)
+#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC)
+#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000) | 0xC0000000)
+
+void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
+                      rt_uint32_t size,
+                      rt_uint32_t paddrStart, rt_uint32_t attr);
+#endif
diff --git a/libcpu/aarch64/cortex-a53/stack.c b/libcpu/aarch64/cortex-a53/stack.c
new file mode 100644
index 0000000000..68222c2c67
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/stack.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+
+#include <armv8.h>
+
+#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
+#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
+#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_ubase_t *stk;
+	rt_ubase_t current_el;
+
+	stk 	 = (rt_ubase_t*)stack_addr;
+
+	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
+	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
+	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
+	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
+	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
+	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
+	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
+	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
+	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
+	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
+	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
+	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
+	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
+	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
+	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
+	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
+	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
+	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
+	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
+	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
+	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
+	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
+	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
+	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
+	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
+	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
+	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
+	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
+	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
+	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+
+	current_el = rt_hw_get_current_el();
+
+	if(current_el == 3)
+	{
+		*(--stk) = INITIAL_SPSR_EL3;
+	}
+	else if(current_el == 2)
+	{
+		*(--stk) = INITIAL_SPSR_EL2;
+	}
+	else
+	{
+		*(--stk) = INITIAL_SPSR_EL1;
+	}
+
+	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/aarch64/cortex-a53/startup_gcc.S b/libcpu/aarch64/cortex-a53/startup_gcc.S
new file mode 100644
index 0000000000..ea4268148c
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/startup_gcc.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+    .global	Reset_Handler
+    .section ".start", "ax"
+Reset_Handler:
+    nop
diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c
new file mode 100644
index 0000000000..aa639ea596
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/trap.c
@@ -0,0 +1,221 @@
+/*
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "interrupt.h"
+#include "armv8.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%16.16llx r01:0x%16.16llx r02:0x%16.16llx r03:0x%16.16llx\n", regs->x0, regs->x1, regs->x2, regs->x3);
+    rt_kprintf("r04:0x%16.16llx r05:0x%16.16llx r06:0x%16.16llx r07:0x%16.16llx\n", regs->x4, regs->x5, regs->x6, regs->x7);
+	rt_kprintf("r08:0x%16.16llx r09:0x%16.16llx r10:0x%16.16llx r11:0x%16.16llx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+	rt_kprintf("r12:0x%16.16llx r13:0x%16.16llx r14:0x%16.16llx r15:0x%16.16llx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+	rt_kprintf("r16:0x%16.16llx r17:0x%16.16llx r18:0x%16.16llx r19:0x%16.16llx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+	rt_kprintf("r20:0x%16.16llx r21:0x%16.16llx r22:0x%16.16llx r23:0x%16.16llx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r24:0x%16.16llx r25:0x%16.16llx r26:0x%16.16llx r27:0x%16.16llx\n", regs->x24, regs->x25, regs->x26, regs->x27);
+	rt_kprintf("r28:0x%16.16llx r29:0x%16.16llx r30:0x%16.16llx", regs->x28, regs->x29, regs->x30);
+	rt_kprintf("spsr:0x%16.16llx", regs->spsr);
+	rt_kprintf("return pc:0x%16.16llx", regs->pc);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("error exception:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    uint32_t irq;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+    uint32_t value = 0;
+    value = IRQ_PEND_BASIC & 0x3ff;
+#ifdef RT_USING_SMP
+    uint32_t mailbox_data;
+    uint32_t cpu_id = rt_hw_cpu_id();
+    uint32_t int_source = CORE_IRQSOURCE(cpu_id);
+    mailbox_data = IPI_MAILBOX_CLEAR(cpu_id);
+    if (int_source & 0x0f)
+    {
+        if (int_source & 0x08){
+            isr_func = isr_table[IRQ_ARM_TIMER].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_TIMER].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_TIMER].param;
+                isr_func(IRQ_ARM_TIMER, param);
+            }
+        }
+    }
+    if (int_source & 0xf0)
+    {
+        /*it's a ipi interrupt*/
+        if (mailbox_data & 0x1){
+            /* clear mailbox */
+            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;    
+            isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_MAILBOX].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_MAILBOX].param;
+                isr_func(IRQ_ARM_MAILBOX, param);
+            }
+        }
+        else 
+            CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
+    }
+#endif
+    /* local interrupt*/
+    if (value)
+    {
+        if (value & (1 << 8))
+        {
+            value = IRQ_PEND1;
+            irq = __rt_ffs(value) - 1;
+        }
+        else if (value & (1 << 9))
+        {
+            value = IRQ_PEND2;
+            irq = __rt_ffs(value) + 31;
+        }
+        else
+        {
+            value &= 0x0f;
+            irq = __rt_ffs(value) + 63;
+        }
+
+        /* get interrupt service routine */
+        isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif
+        if (isr_func)
+        {
+            /* Interrupt for myself. */
+            param = isr_table[irq].param;
+            /* turn to interrupt service routine */
+            isr_func(irq, param);
+        }
+    }
+}
+
+void rt_hw_trap_fiq(void)
+{
+    void *param;
+    uint32_t irq;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+    uint32_t value = 0;
+    value = IRQ_PEND_BASIC & 0x3ff;
+#ifdef RT_USING_SMP
+    uint32_t mailbox_data;
+    uint32_t cpu_id = rt_hw_cpu_id();
+    uint32_t int_source = CORE_IRQSOURCE(cpu_id);
+    mailbox_data = IPI_MAILBOX_CLEAR(cpu_id);
+    if (int_source & 0x0f)
+    {
+        if (int_source & 0x08)
+        {
+            isr_func = isr_table[IRQ_ARM_TIMER].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_TIMER].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_TIMER].param;
+                isr_func(IRQ_ARM_TIMER, param);
+            }
+        }
+    }
+    if (int_source & 0xf0)
+    {
+        /*it's a ipi interrupt*/
+        if (mailbox_data & 0x1)
+        {
+            /* clear mailbox */
+            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;
+            isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_MAILBOX].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_MAILBOX].param;
+                isr_func(IRQ_ARM_MAILBOX, param);
+            }
+        }
+        else
+            CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
+    }
+#endif
+    /* local interrupt*/
+    if (value)
+    {
+        if (value & (1 << 8))
+        {
+            value = IRQ_PEND1;
+            irq = __rt_ffs(value) - 1;
+        }
+        else if (value & (1 << 9))
+        {
+            value = IRQ_PEND2;
+            irq = __rt_ffs(value) + 31;
+        }
+        else
+        {
+            value &= 0x0f;
+            irq = __rt_ffs(value) + 63;
+        }
+
+        /* get interrupt service routine */
+        isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif
+        if (irq > 1)
+            rt_kprintf("interrupt fiq %d\n", irq);
+        if (isr_func)
+        {
+            /* Interrupt for myself. */
+            param = isr_table[irq].param;
+            /* turn to interrupt service routine */
+            isr_func(irq, param);
+        }
+    }
+}
diff --git a/libcpu/aarch64/cortex-a53/vector_gcc.S b/libcpu/aarch64/cortex-a53/vector_gcc.S
new file mode 100644
index 0000000000..0efbf4e540
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/vector_gcc.S
@@ -0,0 +1,57 @@
+/*
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+ 
+.text
+
+.globl system_vectors
+.globl vector_error
+.globl vector_irq
+.globl vector_fiq
+
+system_vectors:
+.align 11
+    .set    VBAR, system_vectors
+    .org    VBAR
+    // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1)
+    .org (VBAR + 0x00 + 0)
+    B vector_error      // 			Synchronous
+    .org (VBAR + 0x80 + 0)
+    B vector_irq        //          IRQ/vIRQ
+    .org (VBAR + 0x100 + 0)
+    B vector_fiq        //          FIQ/vFIQ
+    .org (VBAR + 0x180 + 0)
+    B vector_error      //          Error/vError
+
+    // Exception from CurrentEL (EL1) with SP_ELn
+    .org (VBAR + 0x200 + 0)
+    B vector_error      // 			Synchronous
+    .org (VBAR + 0x280 + 0)
+    B vector_irq    	// 			IRQ/vIRQ
+    .org (VBAR + 0x300 + 0)
+    B vector_fiq        //          FIQ/vFIQ
+    .org (VBAR + 0x380 + 0)
+    B vector_error
+
+    // Exception from lower EL, aarch64
+    .org (VBAR + 0x400 + 0)
+    B vector_error
+    .org (VBAR + 0x480 + 0)
+    B vector_error
+    .org (VBAR + 0x500 + 0)
+    B vector_error
+    .org (VBAR + 0x580 + 0)
+    B vector_error
+
+    // Exception from lower EL, aarch32
+    .org (VBAR + 0x600 + 0)
+    B vector_error
+    .org (VBAR + 0x680 + 0)
+    B vector_error
+    .org (VBAR + 0x700 + 0)
+    B vector_error
+    .org (VBAR + 0x780 + 0)
+    B vector_error
+    .org (VBAR + 0x800 + 0)
+    B vector_error
diff --git a/libcpu/arm/cortex-a53/SConscript b/libcpu/arm/cortex-a53/SConscript
new file mode 100644
index 0000000000..eb4ee7a585
--- /dev/null
+++ b/libcpu/arm/cortex-a53/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-a53/armv7.h b/libcpu/arm/cortex-a53/armv7.h
new file mode 100644
index 0000000000..859b0371b7
--- /dev/null
+++ b/libcpu/arm/cortex-a53/armv7.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+};
+
+struct rt_hw_stack
+{
+    unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long lr;
+    unsigned long pc;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+#endif
diff --git a/libcpu/arm/cortex-a53/context_gcc.S b/libcpu/arm/cortex-a53/context_gcc.S
new file mode 100644
index 0000000000..cb95558f7a
--- /dev/null
+++ b/libcpu/arm/cortex-a53/context_gcc.S
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "../rtconfig.h"
+.section .text, "ax"
+
+#ifdef RT_USING_SMP
+#define rt_hw_interrupt_disable rt_hw_local_irq_disable
+#define rt_hw_interrupt_enable  rt_hw_local_irq_enable
+#endif
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    cpsid i
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread);
+ * r0 --> to (thread stack)
+ * r1 --> to_thread
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+#ifdef RT_USING_SMP
+    mov     r0, r1
+    bl      rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+    b       rt_hw_context_switch_exit
+
+.section .bss.share.isr
+_guest_switch_lvl:
+    .word 0
+
+.globl vmm_virq_update
+
+.section .text.isr, "ax"
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread);
+ * r0 --> from (from_thread stack)
+ * r1 --> to (to_thread stack)
+ * r2 --> to_thread
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    orrne r4, r4, #0x20     @ it's thumb code
+
+    stmfd sp!, {r4}         @ push cpsr
+
+#ifdef RT_USING_LWP
+    stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
+    sub sp, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+#ifdef RT_USING_SMP
+    mov     r0, r2
+    bl      rt_cpus_lock_status_restore
+#endif /*RT_USING_SMP*/
+    b       rt_hw_context_switch_exit
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+#ifdef RT_USING_SMP
+    /* r0 :svc_mod context
+     * r1 :addr of from_thread's sp
+     * r2 :addr of to_thread's sp
+     * r3 :to_thread's tcb
+     */
+
+    str     r0, [r1]
+
+    ldr     sp, [r2]
+    mov     r0, r3
+    bl      rt_cpus_lock_status_restore
+
+    b       rt_hw_context_switch_exit
+
+#else /*RT_USING_SMP*/
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r0, [ip]
+    str r3, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
+#endif /*RT_USING_SMP*/
+
+.global rt_hw_context_switch_exit
+rt_hw_context_switch_exit:
+
+#ifdef RT_USING_SMP
+#ifdef RT_USING_SIGNALS
+    mov     r0, sp
+    cps #Mode_IRQ
+    bl      rt_signal_check
+    cps #Mode_SVC
+    mov     sp, r0
+#endif
+#endif
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+
+#endif
+
+#ifdef RT_USING_LWP
+    ldmfd   sp, {r13, r14}^ /* usr_sp, usr_lr */
+    add     sp, #8
+#endif
+    ldmfd   sp!, {r4}
+    msr     spsr_cxsf, r4        /* original mode */
+    ldmfd   sp!, {r0-r12,lr,pc}^ /* irq return */
+
diff --git a/libcpu/arm/cortex-a53/cp15.h b/libcpu/arm/cortex-a53/cp15.h
new file mode 100644
index 0000000000..14b85b7e64
--- /dev/null
+++ b/libcpu/arm/cortex-a53/cp15.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+#include "raspi.h"
+#ifndef __CP15_H__
+#define __CP15_H__
+
+#ifndef   __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
+#endif
+
+#define __WFI()    __asm__ volatile ("wfi":::"memory")
+
+#define __WFE()    __asm__ volatile ("wfe":::"memory")
+
+#define __SEV()    __asm__ volatile ("sev")
+
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+    __asm__ volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+    __asm__ volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+    __asm__ volatile ("dmb 0xF":::"memory");
+}
+
+
+#ifdef RT_USING_SMP
+static inline void send_ipi_msg(int cpu, int ipi_vector)
+{
+    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
+}
+
+static inline void setup_bootstrap_addr(int cpu, int addr)
+{
+	CORE_MAILBOX3_SET(cpu) = addr;
+}
+
+static inline void enable_cpu_ipi_intr(int cpu)
+{
+    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
+}
+
+static inline void enable_cpu_timer_intr(int cpu)
+{
+	CORETIMER_INTCTL(cpu) = 0x8;
+}
+
+static inline void enable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline void disable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 0;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline  void mask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 2;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline void unmask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
+}
+
+static inline rt_uint64_t read_cntvct(void)
+{
+    rt_uint32_t val,val1;
+    asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
+    return (val);
+}
+
+static inline rt_uint64_t read_cntvoff(void)
+{
+
+    rt_uint64_t val;
+    asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
+    return (val);
+}
+
+static inline rt_uint32_t read_cntv_tval(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
+    return val;
+}
+
+
+static inline  void write_cntv_tval(rt_uint32_t val)
+{
+    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
+    return;
+}
+
+static inline rt_uint32_t read_cntfrq(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
+    return val;
+}
+
+
+static inline  rt_uint32_t read_cntctrl(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
+    return val;
+}
+
+static inline uint32_t write_cntctrl(uint32_t val)
+{
+
+    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
+    return val;
+}
+#endif
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_dcache_clean_flush(void);
+void rt_cpu_icache_flush(void);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+void rt_hw_mmu_init(void);
+void rt_hw_vector_init(void);
+
+void set_timer_counter(unsigned int counter);
+void set_timer_control(unsigned int control);
+#endif
diff --git a/libcpu/arm/cortex-a53/cp15_gcc.S b/libcpu/arm/cortex-a53/cp15_gcc.S
new file mode 100644
index 0000000000..db2e6143ae
--- /dev/null
+++ b/libcpu/arm/cortex-a53/cp15_gcc.S
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    /* clear SCTRL.V to customize the vector address */
+    mrc     p15, #0, r1, c1, c0, #0
+    bic     r1, #(1 << 13)
+    mcr     p15, #0, r1, c1, c0, #0
+    /* set up the vector address */
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl set_timer_counter
+set_timer_counter:
+    mcr     p15, #0, r0, c14, c3, #0  @ write virtual timer timerval register
+    bx      lr
+.globl set_timer_control
+set_timer_control:
+    mcr     p15, #0, r0, c14, c3, #1  @ write virtual timer control register
+    bx      lr
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_cpu_icache_flush
+rt_cpu_icache_flush:
+    mov r0, #0
+    mcr p15, 0, r0, c7, c5, 0       @ I+BTB cache invalidate
+    dsb
+    isb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr
diff --git a/libcpu/arm/cortex-a53/cpu.c b/libcpu/arm/cortex-a53/cpu.c
new file mode 100644
index 0000000000..4d02ca35e1
--- /dev/null
+++ b/libcpu/arm/cortex-a53/cpu.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+#include "cp15.h"
+
+int rt_hw_cpu_id(void)
+{
+    int cpu_id;
+    __asm__ volatile (
+            "mrc p15, 0, %0, c0, c0, 5"
+            :"=r"(cpu_id)
+            );
+    cpu_id &= 0xf;
+    return cpu_id;
+};
+
+
+#ifdef RT_USING_SMP
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    lock->slock = 0;
+}
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    unsigned long tmp;
+    unsigned long newval;
+    rt_hw_spinlock_t lockval;
+    __asm__ __volatile__(
+            "pld [%0]"
+            ::"r"(&lock->slock)
+            );
+
+    __asm__ __volatile__(
+            "1: ldrex   %0, [%3]\n"
+            "   add %1, %0, %4\n"
+            "   strex   %2, %1, [%3]\n"
+            "   teq %2, #0\n"
+            "   bne 1b"
+            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+            : "r" (&lock->slock), "I" (1 << 16)
+            : "cc");
+
+    while (lockval.tickets.next != lockval.tickets.owner) 
+    {
+        __WFE();
+        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
+    }
+
+    __DMB();
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    __DMB();
+    lock->tickets.owner++;
+    __DSB();
+    __SEV();
+}
+#endif /*RT_USING_SMP*/
+
+/**
+ * @addtogroup ARM CPU
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/*@}*/
diff --git a/libcpu/arm/cortex-a53/interrupt.c b/libcpu/arm/cortex-a53/interrupt.c
new file mode 100644
index 0000000000..c9e7c17f8f
--- /dev/null
+++ b/libcpu/arm/cortex-a53/interrupt.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/5/3       Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "cp15.h"
+#include <board.h>
+
+#define MAX_HANDLERS                72
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+const unsigned int VECTOR_BASE = 0x00;
+extern void rt_cpu_vector_set_base(unsigned int addr);
+extern int system_vectors;
+
+void rt_hw_vector_init(void)
+{
+    rt_cpu_vector_set_base((unsigned int)&system_vectors);
+}
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+extern int system_vectors;
+
+static void default_isr_handler(int vector, void *param)
+{
+#ifdef RT_USING_SMP
+    rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
+#else
+    rt_kprintf("unhandled irq: %d\n",vector);
+#endif
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_uint32_t index;
+
+    /* mask all of interrupts */
+    IRQ_DISABLE_BASIC = 0x000000ff;
+    IRQ_DISABLE1      = 0xffffffff;
+    IRQ_DISABLE2      = 0xffffffff;
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        isr_table[index].handler = default_isr_handler;
+        isr_table[index].param = NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
+        isr_table[index].counter = 0;
+#endif
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+
+    if (vector < 32)
+    {
+        IRQ_DISABLE1 = (1 << vector);
+    }
+    else if (vector < 64)
+    {
+        vector = vector % 32;
+        IRQ_DISABLE2 = (1 << vector);
+    }
+    else
+    {
+        vector = vector - 64;
+        IRQ_DISABLE_BASIC = (1 << vector);
+    }
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    if (vector < 32)
+    {
+        IRQ_ENABLE1 = (1 << vector);
+    }
+    else if (vector < 64)
+    {
+        vector = vector % 32;
+        IRQ_ENABLE2 = (1 << vector);
+    }
+    else
+    {
+        vector = vector - 64;
+        IRQ_ENABLE_BASIC = (1 << vector);
+    }
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+{
+    __DSB();
+    if (cpu_mask & 0x1)
+    {
+        send_ipi_msg(0, ipi_vector);
+    }
+    if (cpu_mask & 0x2)
+    {
+    	send_ipi_msg(1, ipi_vector);
+    }
+    if (cpu_mask & 0x4)
+    {
+    	send_ipi_msg(2, ipi_vector);
+    }
+    if (cpu_mask & 0x8)
+    {
+    	send_ipi_msg(3, ipi_vector);
+    }
+    __DSB();
+}
+#endif
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
+{
+    /* note: ipi_vector maybe different with irq_vector */
+    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
+}
+#endif
diff --git a/libcpu/arm/cortex-a53/interrupt.h b/libcpu/arm/cortex-a53/interrupt.h
new file mode 100644
index 0000000000..9aae0f556a
--- /dev/null
+++ b/libcpu/arm/cortex-a53/interrupt.h
@@ -0,0 +1,18 @@
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/libcpu/arm/cortex-a53/mmu.c b/libcpu/arm/cortex-a53/mmu.c
new file mode 100644
index 0000000000..b3541d2ad4
--- /dev/null
+++ b/libcpu/arm/cortex-a53/mmu.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "mmu.h"
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for (i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_init_mmu_table()
+{
+    /* set page table */
+    /* 4G 1:1 memory */
+    rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
+    /* IO memory region */
+    rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
+}
+
+void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
+                      rt_uint32_t size,
+                      rt_uint32_t paddrStart, rt_uint32_t attr)
+{
+    rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
+#ifndef RT_USING_SMP
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+#endif
+}
+
+
+void rt_hw_mmu_init(void)
+{
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+
diff --git a/libcpu/arm/cortex-a53/mmu.h b/libcpu/arm/cortex-a53/mmu.h
new file mode 100644
index 0000000000..6b0c25e990
--- /dev/null
+++ b/libcpu/arm/cortex-a53/mmu.h
@@ -0,0 +1,51 @@
+#ifndef MMU_H__
+#define MMU_H__
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3 << 2)  //cache_on, write_back
+#define CNB            (2 << 2)  //cache_on, write_through
+#define NCB            (1 << 2)  //cache_off,WR_BUF on
+#define NCNB           (0 << 2)  //cache_off,WR_BUF off
+#define AP_RW          (3 << 10) //supervisor=RW, user=RW
+#define AP_RO          (2 << 10) //supervisor=RW, user=RO
+#define XN             (1 << 4)  // eXecute Never
+#define SHARED         (1 << 16) /* shareable */
+#define SHAREDEVICE    (1 << 2)  /* shared device */
+#define STRONGORDER    (0 << 2)  /* strong ordered */
+#define MEMWBWA        ((1 << 12) | (3 << 2))     /* write back, write allocate */
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0 << 5)
+#define DOMAIN1        (0x1 << 5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK << 0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT << 2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW | DOMAIN0 | CB | DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW | DOMAIN0 | CNB | DESC_SEC)
+/* Read/Write without cache and write buffer */
+#define RW_NCNB        (AP_RW | DOMAIN0 | NCNB | DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW | DOMAIN0 | NCNB | DESC_SEC | XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW | DOMAIN1 | NCNB | DESC_SEC)
+
+/* device mapping type */
+#define DEVICE_MEM     (SHARED | SHAREDEVICE | RW_NCNBXN)
+/* normal memory mapping type */
+#define NORMAL_MEM     (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)
+#define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC)
+#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+
+void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
+                      rt_uint32_t size,
+                      rt_uint32_t paddrStart, rt_uint32_t attr);
+#endif
diff --git a/libcpu/arm/cortex-a53/stack.c b/libcpu/arm/cortex-a53/stack.c
new file mode 100644
index 0000000000..c2c60fbf49
--- /dev/null
+++ b/libcpu/arm/cortex-a53/stack.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+#include <armv7.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk      = (rt_uint32_t *)stack_addr;
+    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0xdeadbeef;                  /* r12 */
+    *(--stk) = 0xdeadbeef;                  /* r11 */
+    *(--stk) = 0xdeadbeef;                  /* r10 */
+    *(--stk) = 0xdeadbeef;                  /* r9 */
+    *(--stk) = 0xdeadbeef;                  /* r8 */
+    *(--stk) = 0xdeadbeef;                  /* r7 */
+    *(--stk) = 0xdeadbeef;                  /* r6 */
+    *(--stk) = 0xdeadbeef;                  /* r5 */
+    *(--stk) = 0xdeadbeef;                  /* r4 */
+    *(--stk) = 0xdeadbeef;                  /* r3 */
+    *(--stk) = 0xdeadbeef;                  /* r2 */
+    *(--stk) = 0xdeadbeef;                  /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+#ifdef RT_USING_LWP
+    *(--stk) = 0;       /* user lr */
+    *(--stk) = 0;       /* user sp*/
+#endif
+#ifdef RT_USING_FPU
+    *(--stk) = 0;       /* not use fpu*/
+#endif
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/libcpu/arm/cortex-a53/start_gcc.S b/libcpu/arm/cortex-a53/start_gcc.S
new file mode 100644
index 0000000000..ec74213f07
--- /dev/null
+++ b/libcpu/arm/cortex-a53/start_gcc.S
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include "../rtconfig.h"
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+#ifdef RT_USING_FPU
+.equ UND_Stack_Size,     0x00000400
+#else
+.equ UND_Stack_Size,     0x00000000
+#endif
+.equ SVC_Stack_Size,     0x00000400
+.equ ABT_Stack_Size,     0x00000000
+.equ RT_FIQ_STACK_PGSZ,  0x00000000
+.equ RT_IRQ_STACK_PGSZ,  0x00000800
+.equ USR_Stack_Size,     0x00000400
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
+
+.section .data.share.isr
+/* stack */
+
+#ifdef RT_USING_SMP
+.globl stack_start0
+.globl stack_top0
+.globl stack_start1
+.globl stack_top1
+.globl stack_start2
+.globl stack_top2
+.globl stack_start3
+.globl stack_top3
+stack_start0:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top0:
+
+stack_start1:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top1:
+
+stack_start2:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top2:
+
+stack_start3:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top3:
+
+.globl boot_indicate
+boot_indicate:
+.rept 16
+.byte 0
+.endr
+
+#else
+.globl stack_start
+.globl stack_top
+stack_start:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top:
+#endif
+
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+
+    /* Disable IRQ & FIQ */
+    cpsid if
+
+    /* Check for HYP mode */
+    mrs r0, cpsr_all
+    and r0, r0, #0x1F
+    mov r8, #0x1A
+    cmp r0, r8
+    beq overHyped
+    b continue
+
+overHyped: /* Get out of HYP mode */
+    ldr r1, =continue
+    msr ELR_hyp, r1
+    mrs r1, cpsr_all
+    and r1, r1, #0x1f    ;@ CPSR_MODE_MASK
+    orr r1, r1, #0x13    ;@ CPSR_MODE_SUPERVISOR
+    msr SPSR_hyp, r1
+    eret
+
+continue:
+
+    /* disable mmu */
+    bl      rt_cpu_mmu_disable
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+#ifdef RT_USING_SMP
+    mrc     p15, 0, r0, c0, c0, 5
+    ubfx    r0, r0, #0, #2
+    cmp     r0, #0
+    beq     1f
+    /* write boot indicate */
+    ldr     r5, = boot_indicate
+    str     r0, [r5, r0, lsl #2]
+    bl secondary_cpu_start
+    b .
+1:
+#endif
+    /* setup stack */
+#ifdef RT_USING_SMP
+    ldr     r0, =stack_top0
+#else
+    ldr     r0, =stack_top
+#endif
+    bl      stack_setup
+      
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+    bl rt_hw_init_mmu_table
+    bl init_mbox_mmu_map
+    bl rt_hw_mmu_init
+
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_FIQ_STACK_PGSZ
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_IRQ_STACK_PGSZ
+
+    /* come back to SVC mode */
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+    bx      lr
+
+.text
+
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+.section .text.isr, "ax"
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+.globl      rt_current_thread
+.globl      vmm_thread
+.globl      vmm_virq_check
+
+    .align  5
+.globl vector_irq
+vector_irq:
+#ifdef RT_USING_SMP
+    clrex
+      
+    stmfd   sp!, {r0, r1}
+    cps     #Mode_SVC
+    mov     r0, sp          /* svc_sp */
+    mov     r1, lr          /* svc_lr */
+
+    cps     #Mode_IRQ
+    sub     lr, lr, #4
+    stmfd   r0!, {r1, lr}       /* svc_lr, svc_pc */
+    stmfd   r0!, {r2 - r12}
+    ldmfd   sp!, {r1, r2}     /* original r0, r1 */
+    stmfd   r0!, {r1 - r2}
+    mrs     r1,  spsr         /* original mode */
+    stmfd   r0!, {r1}
+
+#ifdef RT_USING_LWP
+    stmfd   r0, {r13, r14}^ /* usr_sp, usr_lr */
+    sub   r0, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb r0!, {d0-d15}
+    vstmdb r0!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd r0!, {r5}
+1:
+    stmfd r0!, {r6}
+#endif
+    mov     r8, r0
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+    
+    cps     #Mode_SVC
+    mov     sp, r8
+    mov     r0, r8
+    
+    bl      rt_scheduler_do_irq_switch
+
+    b       rt_hw_context_switch_exit
+
+#else
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt. If the usr mode guest is
+    @ interrupted, this will just switch to the stack of kernel space.
+    @ save the registers in kernel space won't trigger data abort.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+#ifdef RT_USING_LWP
+    stmfd sp, {r13, r14}^  @push usr_sp, usr_lr
+    sub sp, #8
+#endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       @ get new task's stack pointer
+
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+1:
+#endif
+
+#ifdef RT_USING_LWP
+    ldmfd sp, {r13, r14}^  @pop usr_sp, usr_lr
+    add sp, #8
+#endif
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+#endif
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl  vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl  vector_undef
+vector_undef:
+    push_svc_reg
+    cps #Mode_UND
+    bl      rt_hw_trap_undef
+#ifdef RT_USING_FPU
+    ldr     lr, [sp, #15*4]
+    ldmia   sp, {r0 - r12}
+    add     sp, sp, #17 * 4
+    movs    pc, lr
+#endif
+    b       .
+
+    .align  5
+    .globl  vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl  vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl  vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .
+
+#ifdef RT_USING_SMP
+
+.global secondary_cpu_start
+secondary_cpu_start:
+    /* set vector base */
+    mrc p15, 0, r0, c1, c0, 0        
+    bic r0, #(1<<13)
+    mcr p15, 0, r0, c1, c0, 0
+    
+    /* setup stack */
+    mrc p15, 0, r0, c0, c0, 5
+    ubfx    r0, r0, #0, #2
+    ldr r1, =stack_top0
+    ldr r2, =ISR_Stack_Size
+    mul r3, r2, r0
+    add r0, r1, r3
+    bl  stack_setup
+    /* initialize the mmu table and enable mmu */
+    bl  rt_hw_mmu_init
+    b   secondary_cpu_c_start
+
+#endif
+
+;@ void arm_smp_enable(void);
+.globl arm_smp_enable
+arm_smp_enable:
+    mrc p15, 0, r0, c1, c0, 1   ;@ set SMP bit in ACTLR
+    orr r0, r0, #0x40
+    mcr p15, 0, r0, c1, c0, 1
+    bx lr
+/*
+    mrrc p15, 1, r0, r1, c15
+    orr r0, r0, #0x40
+    mcrr p15, 1, r0, r1, c15
+    dsb
+    isb
+    bx lr
+*/
+.text
+;@ void arm_smp_disable(void);
+.globl arm_smp_disable
+
+arm_smp_disable:
+    mrc p15, 0, r0, c1, c0, 1   ;@ clear SMP bit in ACTLR
+    bic r0, r0, #0x40
+    mcr p15, 0, r0, c1, c0, 1
+    bx lr
+/*
+    mrrc p15, 1, r0, r1, c15
+    bic r0, r0, #0x40
+    mcrr p15, 1, r0, r1, c15
+    bx lr
+*/
+
diff --git a/libcpu/arm/cortex-a53/trap.c b/libcpu/arm/cortex-a53/trap.c
new file mode 100644
index 0000000000..f83f183695
--- /dev/null
+++ b/libcpu/arm/cortex-a53/trap.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
+ */
+
+#include <rthw.h>
+#include <board.h>
+#include <rtthread.h>
+
+#include "armv7.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    uint32_t irq;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+    uint32_t value = 0;
+    value = IRQ_PEND_BASIC & 0x3ff;
+#ifdef RT_USING_SMP
+    uint32_t mailbox_data;
+    uint32_t cpu_id = rt_hw_cpu_id();
+    uint32_t int_source = CORE_IRQSOURCE(cpu_id);
+    mailbox_data = IPI_MAILBOX_CLEAR(cpu_id);
+    if (int_source & 0x0f)
+    {
+        if (int_source & 0x08)
+        {
+            isr_func = isr_table[IRQ_ARM_TIMER].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_TIMER].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_TIMER].param;
+                isr_func(IRQ_ARM_TIMER, param);
+            }
+        }
+    }
+    if (int_source & 0xf0)
+    {
+        /*it's a ipi interrupt*/
+        if (mailbox_data & 0x1)
+        {
+            /* clear mailbox */
+            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;    
+            isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+            isr_table[IRQ_ARM_MAILBOX].counter++;
+#endif
+            if (isr_func)
+            {
+                param = isr_table[IRQ_ARM_MAILBOX].param;
+                isr_func(IRQ_ARM_MAILBOX, param);
+            }
+        }
+        else 
+            CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
+    }
+#endif
+    /* local interrupt*/
+    if (value)
+    {
+        if (value & (1 << 8))
+        {
+            value = IRQ_PEND1;
+            irq = __rt_ffs(value) - 1;
+        }
+        else if (value & (1 << 9))
+        {
+            value = IRQ_PEND2;
+            irq = __rt_ffs(value) + 31;
+        }
+        else
+        {
+            value &= 0x0f;
+            irq = __rt_ffs(value) + 63;
+        }
+
+        /* get interrupt service routine */
+        isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif
+        if (isr_func)
+        {
+            /* Interrupt for myself. */
+            param = isr_table[irq].param;
+            /* turn to interrupt service routine */
+            isr_func(irq, param);
+        }
+    }
+}
+
+void rt_hw_trap_fiq(void)
+{
+
+}
diff --git a/libcpu/arm/cortex-a53/vector_gcc.S b/libcpu/arm/cortex-a53/vector_gcc.S
new file mode 100644
index 0000000000..eebfe9c13b
--- /dev/null
+++ b/libcpu/arm/cortex-a53/vector_gcc.S
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl    16,0xdeadbeef
diff --git a/libcpu/arm/cortex-a7/SConscript b/libcpu/arm/cortex-a7/SConscript
new file mode 100644
index 0000000000..eb4ee7a585
--- /dev/null
+++ b/libcpu/arm/cortex-a7/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/cortex-a7/armv7.h b/libcpu/arm/cortex-a7/armv7.h
new file mode 100644
index 0000000000..a07d9de2a9
--- /dev/null
+++ b/libcpu/arm/cortex-a7/armv7.h
@@ -0,0 +1,64 @@
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+};
+
+struct rt_hw_stack
+{
+    unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long lr;
+    unsigned long pc;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+#endif
diff --git a/libcpu/arm/cortex-a7/context_gcc.S b/libcpu/arm/cortex-a7/context_gcc.S
new file mode 100644
index 0000000000..48402739f9
--- /dev/null
+++ b/libcpu/arm/cortex-a7/context_gcc.S
@@ -0,0 +1,105 @@
+/*
+ * File      : context.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .text, "ax"
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    cpsid i
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr_c, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task spsr
+    msr spsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+
+.section .bss.share.isr
+_guest_switch_lvl:
+    .word 0
+
+.globl vmm_virq_update
+
+.section .text.isr, "ax"
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    orrne r4, r4, #0x20     @ it's thumb code
+
+    stmfd sp!, {r4}         @ push cpsr
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
+    msr spsr_cxsf, r4
+    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r0, [ip]
+    str r3, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
diff --git a/libcpu/arm/cortex-a7/cp15.h b/libcpu/arm/cortex-a7/cp15.h
new file mode 100644
index 0000000000..ebea3f0fe3
--- /dev/null
+++ b/libcpu/arm/cortex-a7/cp15.h
@@ -0,0 +1,12 @@
+#ifndef __CP15_H__
+#define __CP15_H__
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+
+#endif
diff --git a/libcpu/arm/cortex-a7/cp15_gcc.S b/libcpu/arm/cortex-a7/cp15_gcc.S
new file mode 100644
index 0000000000..f1ed6492aa
--- /dev/null
+++ b/libcpu/arm/cortex-a7/cp15_gcc.S
@@ -0,0 +1,140 @@
+/*
+ * File      : cp15_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * http://www.rt-thread.org
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr
diff --git a/libcpu/arm/cortex-a7/cpu.c b/libcpu/arm/cortex-a7/cpu.c
new file mode 100644
index 0000000000..8bf16d19e8
--- /dev/null
+++ b/libcpu/arm/cortex-a7/cpu.c
@@ -0,0 +1,37 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/*@}*/
diff --git a/libcpu/arm/cortex-a7/interrupt.c b/libcpu/arm/cortex-a7/interrupt.c
new file mode 100644
index 0000000000..d502977c3e
--- /dev/null
+++ b/libcpu/arm/cortex-a7/interrupt.c
@@ -0,0 +1,136 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018/5/3       Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "cp15.h"
+#include <board.h>
+
+#define MAX_HANDLERS                64
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+extern int system_vectors;
+
+static void default_isr_handler(int vector, void *param)
+{
+    rt_kprintf("unhandled irq: %d\n", vector);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    uint32_t index;
+
+    /* mask all of interrupts */
+    IRQ_DISABLE_BASIC = 0x000000ff;
+    IRQ_DISABLE1      = 0xffffffff;
+    IRQ_DISABLE2      = 0xffffffff;
+
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        isr_table[index].handler = default_isr_handler;
+        isr_table[index].param = NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
+        isr_table[index].counter = 0;
+#endif
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    if (vector < 8)
+    {
+        IRQ_DISABLE_BASIC = (1 << vector);
+    }
+    else if (vector < 32)
+    {
+        IRQ_DISABLE1 = (1 << vector);
+    }
+    else
+    {
+        vector = vector % 32;
+        IRQ_DISABLE2 = (1 << vector);
+    }
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    if (vector < 8)
+    {
+        IRQ_ENABLE_BASIC = (1 << vector);
+    }
+    else if (vector < 32)
+    {
+        IRQ_ENABLE1 = (1 << vector);
+    }
+    else
+    {
+        vector = vector % 32;
+        IRQ_ENABLE2 = (1 << vector);
+    }
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
diff --git a/libcpu/arm/cortex-a7/mmu.c b/libcpu/arm/cortex-a7/mmu.c
new file mode 100644
index 0000000000..b2503e4260
--- /dev/null
+++ b/libcpu/arm/cortex-a7/mmu.c
@@ -0,0 +1,207 @@
+/*
+ * File      : mmu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3<<2)  //cache_on, write_back
+#define CNB            (2<<2)  //cache_on, write_through
+#define NCB            (1<<2)  //cache_off,WR_BUF on
+#define NCNB           (0<<2)  //cache_off,WR_BUF off
+#define AP_RW          (3<<10) //supervisor=RW, user=RW
+#define AP_RO          (2<<10) //supervisor=RW, user=RO
+#define XN             (1<<4)  // eXecute Never
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
+/* Read/Write without cache and write buffer */
+#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_mmu_init(void)
+{
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /* set page table */
+    /* 4G 1:1 memory */
+    rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
+    /* IO memory region */
+    rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+
diff --git a/libcpu/arm/cortex-a7/stack.c b/libcpu/arm/cortex-a7/stack.c
new file mode 100644
index 0000000000..e60e8c7170
--- /dev/null
+++ b/libcpu/arm/cortex-a7/stack.c
@@ -0,0 +1,68 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+#include <armv7.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk      = (rt_uint32_t *)stack_addr;
+    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0xdeadbeef;                  /* r12 */
+    *(--stk) = 0xdeadbeef;                  /* r11 */
+    *(--stk) = 0xdeadbeef;                  /* r10 */
+    *(--stk) = 0xdeadbeef;                  /* r9 */
+    *(--stk) = 0xdeadbeef;                  /* r8 */
+    *(--stk) = 0xdeadbeef;                  /* r7 */
+    *(--stk) = 0xdeadbeef;                  /* r6 */
+    *(--stk) = 0xdeadbeef;                  /* r5 */
+    *(--stk) = 0xdeadbeef;                  /* r4 */
+    *(--stk) = 0xdeadbeef;                  /* r3 */
+    *(--stk) = 0xdeadbeef;                  /* r2 */
+    *(--stk) = 0xdeadbeef;                  /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/libcpu/arm/cortex-a7/start_gcc.S b/libcpu/arm/cortex-a7/start_gcc.S
new file mode 100644
index 0000000000..b60ad6a38f
--- /dev/null
+++ b/libcpu/arm/cortex-a7/start_gcc.S
@@ -0,0 +1,280 @@
+/*
+ * File      : start_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.equ UND_Stack_Size,     0x00000000
+.equ SVC_Stack_Size,     0x00000100
+.equ ABT_Stack_Size,     0x00000000
+.equ RT_FIQ_STACK_PGSZ,  0x00000000
+.equ RT_IRQ_STACK_PGSZ,  0x00000100
+.equ USR_Stack_Size,     0x00000100
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
+
+.section .data.share.isr
+/* stack */
+.globl stack_start
+.globl stack_top
+
+.align 3
+stack_start:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top:
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+	/* Disable IRQ & FIQ */
+	cpsid if
+
+	/* Check for HYP mode */
+	mrs r0, cpsr_all
+	and r0, r0, #0x1F
+	mov r8, #0x1A
+	cmp r0, r8
+	beq overHyped
+	b continue
+
+overHyped: /* Get out of HYP mode */
+	ldr r1, =continue
+	msr ELR_hyp, r1
+	mrs r1, cpsr_all
+	and r1, r1, #0x1f	;@ CPSR_MODE_MASK
+	orr r1, r1, #0x13	;@ CPSR_MODE_SUPERVISOR
+	msr SPSR_hyp, r1
+	eret
+
+continue:
+
+    /* disable smp */
+    bl      arm_smp_disable
+
+    /* disable mmu */
+    bl      rt_cpu_mmu_disable
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+
+    /* setup stack */
+    bl      stack_setup
+
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+    ldr     r0, =stack_top
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+	sub     r0, r0, #SVC_Stack_Size
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_FIQ_STACK_PGSZ
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_IRQ_STACK_PGSZ
+
+    /* come back to SVC mode */
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+    bx      lr
+
+.text
+;@ void arm_smp_enable(void);
+.globl arm_smp_enable
+arm_smp_enable:
+    mrc p15, 0, r0, c1, c0, 1   ;@ set SMP bit in ACTLR
+    orr r0, r0, #0x40
+    mcr p15, 0, r0, c1, c0, 1
+    bx lr
+
+.text
+;@ void arm_smp_disable(void);
+.globl arm_smp_disable
+arm_smp_disable:
+    mrc p15, 0, r0, c1, c0, 1   ;@ clear SMP bit in ACTLR
+    bic r0, r0, #0x40
+    mcr p15, 0, r0, c1, c0, 1
+    bx lr
+
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+.section .text.isr, "ax"
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+.globl      rt_current_thread
+.globl      vmm_thread
+.globl      vmm_virq_check
+
+    .align  5
+.globl vector_irq
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt. If the usr mode guest is
+    @ interrupted, this will just switch to the stack of kernel space.
+    @ save the registers in kernel space won't trigger data abort.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       @ get new task's stack pointer
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl  vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl  vector_undef
+vector_undef:
+    push_svc_reg
+    bl      rt_hw_trap_undef
+    b       .
+
+    .align  5
+    .globl  vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl  vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl  vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .
diff --git a/libcpu/arm/cortex-a7/trap.c b/libcpu/arm/cortex-a7/trap.c
new file mode 100644
index 0000000000..3012c26e2c
--- /dev/null
+++ b/libcpu/arm/cortex-a7/trap.c
@@ -0,0 +1,183 @@
+/*
+ * File      : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <board.h>
+#include <rtthread.h>
+
+#include "armv7.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    uint32_t value = 0;
+
+    // rt_kprintf("pend basic: 0x%08x\n", IRQ_PEND_BASIC);
+    // rt_kprintf("     pend1: 0x%08x\n", IRQ_PEND1);
+    // rt_kprintf("     pend2: 0x%08x\n", IRQ_PEND2);
+
+    value = IRQ_PEND_BASIC & 0x3ff;
+    if (value)
+    {
+        uint32_t irq;
+
+        if (value & (1 << 8))
+        {
+            value = IRQ_PEND1;
+            irq = __rt_ffs(value) - 1;
+        }
+        else if (value & (1 << 9))
+        {
+            value = IRQ_PEND2;
+            irq = __rt_ffs(value) + 31;
+        }
+        else
+        {
+            value &= 0x0f;
+            irq = __rt_ffs(value) - 1;
+        }
+
+        /* get interrupt service routine */
+        isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif
+        if (isr_func)
+        {
+            /* Interrupt for myself. */
+            param = isr_table[irq].param;
+            /* turn to interrupt service routine */
+            isr_func(irq, param);
+        }
+    }
+}
+
+void rt_hw_trap_fiq(void)
+{
+    /* TODO */
+}
diff --git a/libcpu/arm/cortex-a7/vector_gcc.S b/libcpu/arm/cortex-a7/vector_gcc.S
new file mode 100644
index 0000000000..17c2d69c30
--- /dev/null
+++ b/libcpu/arm/cortex-a7/vector_gcc.S
@@ -0,0 +1,65 @@
+/*
+ * File      : vector_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl    16,0xdeadbeef
-- 
cgit v1.3.1


From 08f55d9fdaf4b680c2ef4956e894187a2608af79 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Wed, 15 Jan 2020 16:38:22 +0800
Subject: add raspi3-32 in bsp

---
 bsp/raspberry-pi/raspi3-32/Kconfig  |   2 +-
 libcpu/arm/cortex-a53/SConscript    |   9 -
 libcpu/arm/cortex-a53/armv7.h       |  74 ------
 libcpu/arm/cortex-a53/context_gcc.S | 183 --------------
 libcpu/arm/cortex-a53/cp15_gcc.S    | 147 ------------
 libcpu/arm/cortex-a53/mmu.h         |  51 ----
 libcpu/arm/cortex-a53/stack.c       |  72 ------
 libcpu/arm/cortex-a53/start_gcc.S   | 459 ------------------------------------
 libcpu/arm/cortex-a53/trap.c        | 219 -----------------
 libcpu/arm/cortex-a53/vector_gcc.S  |  51 ----
 libcpu/arm/cortex-a7/SConscript     |   9 -
 libcpu/arm/cortex-a7/armv7.h        |  64 -----
 libcpu/arm/cortex-a7/context_gcc.S  | 105 ---------
 libcpu/arm/cortex-a7/cp15.h         |  12 -
 libcpu/arm/cortex-a7/cp15_gcc.S     | 140 -----------
 libcpu/arm/cortex-a7/cpu.c          |  37 ---
 libcpu/arm/cortex-a7/interrupt.c    | 136 -----------
 libcpu/arm/cortex-a7/mmu.c          | 207 ----------------
 libcpu/arm/cortex-a7/stack.c        |  68 ------
 libcpu/arm/cortex-a7/start_gcc.S    | 280 ----------------------
 libcpu/arm/cortex-a7/trap.c         | 183 --------------
 libcpu/arm/cortex-a7/vector_gcc.S   |  65 -----
 22 files changed, 1 insertion(+), 2572 deletions(-)
 delete mode 100644 libcpu/arm/cortex-a53/SConscript
 delete mode 100644 libcpu/arm/cortex-a53/armv7.h
 delete mode 100644 libcpu/arm/cortex-a53/context_gcc.S
 delete mode 100644 libcpu/arm/cortex-a53/cp15_gcc.S
 delete mode 100644 libcpu/arm/cortex-a53/mmu.h
 delete mode 100644 libcpu/arm/cortex-a53/stack.c
 delete mode 100644 libcpu/arm/cortex-a53/start_gcc.S
 delete mode 100644 libcpu/arm/cortex-a53/trap.c
 delete mode 100644 libcpu/arm/cortex-a53/vector_gcc.S
 delete mode 100644 libcpu/arm/cortex-a7/SConscript
 delete mode 100644 libcpu/arm/cortex-a7/armv7.h
 delete mode 100644 libcpu/arm/cortex-a7/context_gcc.S
 delete mode 100644 libcpu/arm/cortex-a7/cp15.h
 delete mode 100644 libcpu/arm/cortex-a7/cp15_gcc.S
 delete mode 100644 libcpu/arm/cortex-a7/cpu.c
 delete mode 100644 libcpu/arm/cortex-a7/interrupt.c
 delete mode 100644 libcpu/arm/cortex-a7/mmu.c
 delete mode 100644 libcpu/arm/cortex-a7/stack.c
 delete mode 100644 libcpu/arm/cortex-a7/start_gcc.S
 delete mode 100644 libcpu/arm/cortex-a7/trap.c
 delete mode 100644 libcpu/arm/cortex-a7/vector_gcc.S

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi3-32/Kconfig b/bsp/raspberry-pi/raspi3-32/Kconfig
index 06cbe1128f..f7693c8378 100644
--- a/bsp/raspberry-pi/raspi3-32/Kconfig
+++ b/bsp/raspberry-pi/raspi3-32/Kconfig
@@ -8,7 +8,7 @@ config BSP_DIR
 config RTT_DIR
     string
     option env="RTT_ROOT"
-    default "../.."
+    default "../../.."
 
 config PKGS_DIR
     string
diff --git a/libcpu/arm/cortex-a53/SConscript b/libcpu/arm/cortex-a53/SConscript
deleted file mode 100644
index eb4ee7a585..0000000000
--- a/libcpu/arm/cortex-a53/SConscript
+++ /dev/null
@@ -1,9 +0,0 @@
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/libcpu/arm/cortex-a53/armv7.h b/libcpu/arm/cortex-a53/armv7.h
deleted file mode 100644
index 859b0371b7..0000000000
--- a/libcpu/arm/cortex-a53/armv7.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-
-#ifndef __ARMV7_H__
-#define __ARMV7_H__
-
-/* the exception stack without VFP registers */
-struct rt_hw_exp_stack
-{
-    unsigned long r0;
-    unsigned long r1;
-    unsigned long r2;
-    unsigned long r3;
-    unsigned long r4;
-    unsigned long r5;
-    unsigned long r6;
-    unsigned long r7;
-    unsigned long r8;
-    unsigned long r9;
-    unsigned long r10;
-    unsigned long fp;
-    unsigned long ip;
-    unsigned long sp;
-    unsigned long lr;
-    unsigned long pc;
-    unsigned long cpsr;
-};
-
-struct rt_hw_stack
-{
-    unsigned long cpsr;
-    unsigned long r0;
-    unsigned long r1;
-    unsigned long r2;
-    unsigned long r3;
-    unsigned long r4;
-    unsigned long r5;
-    unsigned long r6;
-    unsigned long r7;
-    unsigned long r8;
-    unsigned long r9;
-    unsigned long r10;
-    unsigned long fp;
-    unsigned long ip;
-    unsigned long lr;
-    unsigned long pc;
-};
-
-#define USERMODE    0x10
-#define FIQMODE     0x11
-#define IRQMODE     0x12
-#define SVCMODE     0x13
-#define MONITORMODE 0x16
-#define ABORTMODE   0x17
-#define HYPMODE     0x1b
-#define UNDEFMODE   0x1b
-#define MODEMASK    0x1f
-#define NOINT       0xc0
-
-#define T_Bit       (1<<5)
-#define F_Bit       (1<<6)
-#define I_Bit       (1<<7)
-#define A_Bit       (1<<8)
-#define E_Bit       (1<<9)
-#define J_Bit       (1<<24)
-
-#endif
diff --git a/libcpu/arm/cortex-a53/context_gcc.S b/libcpu/arm/cortex-a53/context_gcc.S
deleted file mode 100644
index cb95558f7a..0000000000
--- a/libcpu/arm/cortex-a53/context_gcc.S
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- * 2019-07-28     zdzn         add smp support
- */
-
-#include "../rtconfig.h"
-.section .text, "ax"
-
-#ifdef RT_USING_SMP
-#define rt_hw_interrupt_disable rt_hw_local_irq_disable
-#define rt_hw_interrupt_enable  rt_hw_local_irq_enable
-#endif
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mrs r0, cpsr
-    cpsid i
-    bx  lr
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    msr cpsr, r0
-    bx  lr
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread);
- * r0 --> to (thread stack)
- * r1 --> to_thread
- */
-.globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    ldr sp, [r0]            @ get new task stack pointer
-
-#ifdef RT_USING_SMP
-    mov     r0, r1
-    bl      rt_cpus_lock_status_restore
-#endif /*RT_USING_SMP*/
-    b       rt_hw_context_switch_exit
-
-.section .bss.share.isr
-_guest_switch_lvl:
-    .word 0
-
-.globl vmm_virq_update
-
-.section .text.isr, "ax"
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread);
- * r0 --> from (from_thread stack)
- * r1 --> to (to_thread stack)
- * r2 --> to_thread
- */
-.globl rt_hw_context_switch
-rt_hw_context_switch:
-    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
-    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
-
-    mrs r4, cpsr
-    tst lr, #0x01
-    orrne r4, r4, #0x20     @ it's thumb code
-
-    stmfd sp!, {r4}         @ push cpsr
-
-#ifdef RT_USING_LWP
-    stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
-    sub sp, #8
-#endif
-#ifdef RT_USING_FPU
-    /* fpu context */
-    vmrs r6, fpexc
-    tst  r6, #(1<<30)
-    beq 1f
-    vstmdb sp!, {d0-d15}
-    vstmdb sp!, {d16-d31}
-    vmrs r5, fpscr
-    stmfd sp!, {r5}
-1:
-    stmfd sp!, {r6}
-#endif
-
-    str sp, [r0]            @ store sp in preempted tasks TCB
-    ldr sp, [r1]            @ get new task stack pointer
-
-#ifdef RT_USING_SMP
-    mov     r0, r2
-    bl      rt_cpus_lock_status_restore
-#endif /*RT_USING_SMP*/
-    b       rt_hw_context_switch_exit
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
- */
-.equ Mode_USR,        0x10
-.equ Mode_FIQ,        0x11
-.equ Mode_IRQ,        0x12
-.equ Mode_SVC,        0x13
-.equ Mode_ABT,        0x17
-.equ Mode_UND,        0x1B
-.equ Mode_SYS,        0x1F
-
-.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
-.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
-
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-#ifdef RT_USING_SMP
-    /* r0 :svc_mod context
-     * r1 :addr of from_thread's sp
-     * r2 :addr of to_thread's sp
-     * r3 :to_thread's tcb
-     */
-
-    str     r0, [r1]
-
-    ldr     sp, [r2]
-    mov     r0, r3
-    bl      rt_cpus_lock_status_restore
-
-    b       rt_hw_context_switch_exit
-
-#else /*RT_USING_SMP*/
-    ldr r2, =rt_thread_switch_interrupt_flag
-    ldr r3, [r2]
-    cmp r3, #1
-    beq _reswitch
-    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
-    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
-    str r0, [ip]
-    str r3, [r2]
-_reswitch:
-    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
-    str r1, [r2]
-    bx  lr
-#endif /*RT_USING_SMP*/
-
-.global rt_hw_context_switch_exit
-rt_hw_context_switch_exit:
-
-#ifdef RT_USING_SMP
-#ifdef RT_USING_SIGNALS
-    mov     r0, sp
-    cps #Mode_IRQ
-    bl      rt_signal_check
-    cps #Mode_SVC
-    mov     sp, r0
-#endif
-#endif
-#ifdef RT_USING_FPU
-/* fpu context */
-    ldmfd sp!, {r6}
-    vmsr fpexc, r6
-    tst  r6, #(1<<30)
-    beq 1f
-    ldmfd sp!, {r5}
-    vmsr fpscr, r5
-    vldmia sp!, {d16-d31}
-    vldmia sp!, {d0-d15}
-
-#endif
-
-#ifdef RT_USING_LWP
-    ldmfd   sp, {r13, r14}^ /* usr_sp, usr_lr */
-    add     sp, #8
-#endif
-    ldmfd   sp!, {r4}
-    msr     spsr_cxsf, r4        /* original mode */
-    ldmfd   sp!, {r0-r12,lr,pc}^ /* irq return */
-
diff --git a/libcpu/arm/cortex-a53/cp15_gcc.S b/libcpu/arm/cortex-a53/cp15_gcc.S
deleted file mode 100644
index db2e6143ae..0000000000
--- a/libcpu/arm/cortex-a53/cp15_gcc.S
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.globl rt_cpu_get_smp_id
-rt_cpu_get_smp_id:
-    mrc     p15, #0, r0, c0, c0, #5
-    bx      lr
-
-.globl rt_cpu_vector_set_base
-rt_cpu_vector_set_base:
-    /* clear SCTRL.V to customize the vector address */
-    mrc     p15, #0, r1, c1, c0, #0
-    bic     r1, #(1 << 13)
-    mcr     p15, #0, r1, c1, c0, #0
-    /* set up the vector address */
-    mcr     p15, #0, r0, c12, c0, #0
-    dsb
-    bx      lr
-
-.globl rt_hw_cpu_dcache_enable
-rt_hw_cpu_dcache_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0,  r0, #0x00000004
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-.globl rt_hw_cpu_icache_enable
-rt_hw_cpu_icache_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0,  r0, #0x00001000
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-_FLD_MAX_WAY:
-   .word  0x3ff
-_FLD_MAX_IDX:
-   .word  0x7ff
-
-.globl set_timer_counter
-set_timer_counter:
-    mcr     p15, #0, r0, c14, c3, #0  @ write virtual timer timerval register
-    bx      lr
-.globl set_timer_control
-set_timer_control:
-    mcr     p15, #0, r0, c14, c3, #1  @ write virtual timer control register
-    bx      lr
-
-.globl rt_cpu_dcache_clean_flush
-rt_cpu_dcache_clean_flush:
-    push    {r4-r11}
-    dmb
-    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
-    ands    r3, r0, #0x7000000       @ get level of coherency
-    mov     r3, r3, lsr #23
-    beq     finished
-    mov     r10, #0
-loop1:
-    add     r2, r10, r10, lsr #1
-    mov     r1, r0, lsr r2
-    and     r1, r1, #7
-    cmp     r1, #2
-    blt     skip
-    mcr     p15, #2, r10, c0, c0, #0
-    isb
-    mrc     p15, #1, r1, c0, c0, #0
-    and     r2, r1, #7
-    add     r2, r2, #4
-    ldr     r4, _FLD_MAX_WAY
-    ands    r4, r4, r1, lsr #3
-    clz     r5, r4
-    ldr     r7, _FLD_MAX_IDX
-    ands    r7, r7, r1, lsr #13
-loop2:
-    mov     r9, r4
-loop3:
-    orr     r11, r10, r9, lsl r5
-    orr     r11, r11, r7, lsl r2
-    mcr     p15, #0, r11, c7, c14, #2
-    subs    r9, r9, #1
-    bge     loop3
-    subs    r7, r7, #1
-    bge     loop2
-skip:
-    add     r10, r10, #2
-    cmp     r3, r10
-    bgt     loop1
-
-finished:
-    dsb
-    isb
-    pop     {r4-r11}
-    bx      lr
-
-.globl rt_cpu_icache_flush
-rt_cpu_icache_flush:
-    mov r0, #0
-    mcr p15, 0, r0, c7, c5, 0       @ I+BTB cache invalidate
-    dsb
-    isb
-    bx      lr
-
-.globl rt_hw_cpu_dcache_disable
-rt_hw_cpu_dcache_disable:
-    push    {r4-r11, lr}
-    bl      rt_cpu_dcache_clean_flush
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0,  r0, #0x00000004
-    mcr     p15, #0, r0, c1, c0, #0
-    pop     {r4-r11, lr}
-    bx      lr
-
-.globl rt_hw_cpu_icache_disable
-rt_hw_cpu_icache_disable:
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0,  r0, #0x00001000
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-.globl rt_cpu_mmu_disable
-rt_cpu_mmu_disable:
-    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0, r0, #1
-    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
-    dsb
-    bx      lr
-
-.globl rt_cpu_mmu_enable
-rt_cpu_mmu_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0, r0, #0x001
-    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
-    dsb
-    bx      lr
-
-.globl rt_cpu_tlb_set
-rt_cpu_tlb_set:
-    mcr     p15, #0, r0, c2, c0, #0
-    dmb
-    bx      lr
diff --git a/libcpu/arm/cortex-a53/mmu.h b/libcpu/arm/cortex-a53/mmu.h
deleted file mode 100644
index 6b0c25e990..0000000000
--- a/libcpu/arm/cortex-a53/mmu.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef MMU_H__
-#define MMU_H__
-#include <rtthread.h>
-#include <rthw.h>
-#include <board.h>
-#include "cp15.h"
-
-#define DESC_SEC       (0x2)
-#define CB             (3 << 2)  //cache_on, write_back
-#define CNB            (2 << 2)  //cache_on, write_through
-#define NCB            (1 << 2)  //cache_off,WR_BUF on
-#define NCNB           (0 << 2)  //cache_off,WR_BUF off
-#define AP_RW          (3 << 10) //supervisor=RW, user=RW
-#define AP_RO          (2 << 10) //supervisor=RW, user=RO
-#define XN             (1 << 4)  // eXecute Never
-#define SHARED         (1 << 16) /* shareable */
-#define SHAREDEVICE    (1 << 2)  /* shared device */
-#define STRONGORDER    (0 << 2)  /* strong ordered */
-#define MEMWBWA        ((1 << 12) | (3 << 2))     /* write back, write allocate */
-
-#define DOMAIN_FAULT   (0x0)
-#define DOMAIN_CHK     (0x1)
-#define DOMAIN_NOTCHK  (0x3)
-#define DOMAIN0        (0x0 << 5)
-#define DOMAIN1        (0x1 << 5)
-
-#define DOMAIN0_ATTR   (DOMAIN_CHK << 0)
-#define DOMAIN1_ATTR   (DOMAIN_FAULT << 2)
-
-/* Read/Write, cache, write back */
-#define RW_CB          (AP_RW | DOMAIN0 | CB | DESC_SEC)
-/* Read/Write, cache, write through */
-#define RW_CNB         (AP_RW | DOMAIN0 | CNB | DESC_SEC)
-/* Read/Write without cache and write buffer */
-#define RW_NCNB        (AP_RW | DOMAIN0 | NCNB | DESC_SEC)
-/* Read/Write without cache and write buffer, no execute */
-#define RW_NCNBXN      (AP_RW | DOMAIN0 | NCNB | DESC_SEC | XN)
-/* Read/Write without cache and write buffer */
-#define RW_FAULT       (AP_RW | DOMAIN1 | NCNB | DESC_SEC)
-
-/* device mapping type */
-#define DEVICE_MEM     (SHARED | SHAREDEVICE | RW_NCNBXN)
-/* normal memory mapping type */
-#define NORMAL_MEM     (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)
-#define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC)
-#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
-
-void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
-                      rt_uint32_t size,
-                      rt_uint32_t paddrStart, rt_uint32_t attr);
-#endif
diff --git a/libcpu/arm/cortex-a53/stack.c b/libcpu/arm/cortex-a53/stack.c
deleted file mode 100644
index c2c60fbf49..0000000000
--- a/libcpu/arm/cortex-a53/stack.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-23     Bernard      the first version
- * 2011-10-05     Bernard      add thumb mode
- */
-#include <rtthread.h>
-#include <board.h>
-#include <armv7.h>
-
-/**
- * @addtogroup AM33xx
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-                             rt_uint8_t *stack_addr, void *texit)
-{
-    rt_uint32_t *stk;
-
-    stack_addr += sizeof(rt_uint32_t);
-    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
-    stk      = (rt_uint32_t *)stack_addr;
-    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
-    *(--stk) = (rt_uint32_t)texit;          /* lr */
-    *(--stk) = 0xdeadbeef;                  /* r12 */
-    *(--stk) = 0xdeadbeef;                  /* r11 */
-    *(--stk) = 0xdeadbeef;                  /* r10 */
-    *(--stk) = 0xdeadbeef;                  /* r9 */
-    *(--stk) = 0xdeadbeef;                  /* r8 */
-    *(--stk) = 0xdeadbeef;                  /* r7 */
-    *(--stk) = 0xdeadbeef;                  /* r6 */
-    *(--stk) = 0xdeadbeef;                  /* r5 */
-    *(--stk) = 0xdeadbeef;                  /* r4 */
-    *(--stk) = 0xdeadbeef;                  /* r3 */
-    *(--stk) = 0xdeadbeef;                  /* r2 */
-    *(--stk) = 0xdeadbeef;                  /* r1 */
-    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
-
-    /* cpsr */
-    if ((rt_uint32_t)tentry & 0x01)
-        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
-    else
-        *(--stk) = SVCMODE;                 /* arm mode   */
-
-#ifdef RT_USING_LWP
-    *(--stk) = 0;       /* user lr */
-    *(--stk) = 0;       /* user sp*/
-#endif
-#ifdef RT_USING_FPU
-    *(--stk) = 0;       /* not use fpu*/
-#endif
-
-    /* return task's current stack address */
-    return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/libcpu/arm/cortex-a53/start_gcc.S b/libcpu/arm/cortex-a53/start_gcc.S
deleted file mode 100644
index ec74213f07..0000000000
--- a/libcpu/arm/cortex-a53/start_gcc.S
+++ /dev/null
@@ -1,459 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- * 2019-07-28     zdzn         add smp support
- */
-
-#include "../rtconfig.h"
-.equ Mode_USR,        0x10
-.equ Mode_FIQ,        0x11
-.equ Mode_IRQ,        0x12
-.equ Mode_SVC,        0x13
-.equ Mode_ABT,        0x17
-.equ Mode_UND,        0x1B
-.equ Mode_SYS,        0x1F
-
-.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
-.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
-
-#ifdef RT_USING_FPU
-.equ UND_Stack_Size,     0x00000400
-#else
-.equ UND_Stack_Size,     0x00000000
-#endif
-.equ SVC_Stack_Size,     0x00000400
-.equ ABT_Stack_Size,     0x00000000
-.equ RT_FIQ_STACK_PGSZ,  0x00000000
-.equ RT_IRQ_STACK_PGSZ,  0x00000800
-.equ USR_Stack_Size,     0x00000400
-
-#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
-                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
-
-.section .data.share.isr
-/* stack */
-
-#ifdef RT_USING_SMP
-.globl stack_start0
-.globl stack_top0
-.globl stack_start1
-.globl stack_top1
-.globl stack_start2
-.globl stack_top2
-.globl stack_start3
-.globl stack_top3
-stack_start0:
-.rept ISR_Stack_Size
-.byte 0
-.endr
-stack_top0:
-
-stack_start1:
-.rept ISR_Stack_Size
-.byte 0
-.endr
-stack_top1:
-
-stack_start2:
-.rept ISR_Stack_Size
-.byte 0
-.endr
-stack_top2:
-
-stack_start3:
-.rept ISR_Stack_Size
-.byte 0
-.endr
-stack_top3:
-
-.globl boot_indicate
-boot_indicate:
-.rept 16
-.byte 0
-.endr
-
-#else
-.globl stack_start
-.globl stack_top
-stack_start:
-.rept ISR_Stack_Size
-.byte 0
-.endr
-stack_top:
-#endif
-
-
-.text
-/* reset entry */
-.globl _reset
-_reset:
-
-    /* Disable IRQ & FIQ */
-    cpsid if
-
-    /* Check for HYP mode */
-    mrs r0, cpsr_all
-    and r0, r0, #0x1F
-    mov r8, #0x1A
-    cmp r0, r8
-    beq overHyped
-    b continue
-
-overHyped: /* Get out of HYP mode */
-    ldr r1, =continue
-    msr ELR_hyp, r1
-    mrs r1, cpsr_all
-    and r1, r1, #0x1f    ;@ CPSR_MODE_MASK
-    orr r1, r1, #0x13    ;@ CPSR_MODE_SUPERVISOR
-    msr SPSR_hyp, r1
-    eret
-
-continue:
-
-    /* disable mmu */
-    bl      rt_cpu_mmu_disable
-    /* set the cpu to SVC32 mode and disable interrupt */
-    mrs     r0, cpsr
-    bic     r0, r0, #0x1f
-    orr     r0, r0, #0x13
-    msr     cpsr_c, r0
-#ifdef RT_USING_SMP
-    mrc     p15, 0, r0, c0, c0, 5
-    ubfx    r0, r0, #0, #2
-    cmp     r0, #0
-    beq     1f
-    /* write boot indicate */
-    ldr     r5, = boot_indicate
-    str     r0, [r5, r0, lsl #2]
-    bl secondary_cpu_start
-    b .
-1:
-#endif
-    /* setup stack */
-#ifdef RT_USING_SMP
-    ldr     r0, =stack_top0
-#else
-    ldr     r0, =stack_top
-#endif
-    bl      stack_setup
-      
-    /* clear .bss */
-    mov     r0,#0                   /* get a zero                       */
-    ldr     r1,=__bss_start         /* bss start                        */
-    ldr     r2,=__bss_end           /* bss end                          */
-
-bss_loop:
-    cmp     r1,r2                   /* check if data to clear           */
-    strlo   r0,[r1],#4              /* clear 4 bytes                    */
-    blo     bss_loop                /* loop until done                  */
-    bl rt_hw_init_mmu_table
-    bl init_mbox_mmu_map
-    bl rt_hw_mmu_init
-
-    /* start RT-Thread Kernel */
-    ldr     pc, _rtthread_startup
-_rtthread_startup:
-    .word rtthread_startup
-
-stack_setup:
-
-    @  Set the startup stack for svc
-    mov     sp, r0
-
-    @  Enter Undefined Instruction Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #UND_Stack_Size
-
-    @  Enter Abort Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #ABT_Stack_Size
-
-    @  Enter FIQ Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #RT_FIQ_STACK_PGSZ
-
-    @  Enter IRQ Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #RT_IRQ_STACK_PGSZ
-
-    /* come back to SVC mode */
-    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
-    bx      lr
-
-.text
-
-/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
-.section .text.isr, "ax"
-    .align  5
-.globl vector_fiq
-vector_fiq:
-    stmfd   sp!,{r0-r7,lr}
-    bl      rt_hw_trap_fiq
-    ldmfd   sp!,{r0-r7,lr}
-    subs    pc, lr, #4
-
-.globl      rt_interrupt_enter
-.globl      rt_interrupt_leave
-.globl      rt_thread_switch_interrupt_flag
-.globl      rt_interrupt_from_thread
-.globl      rt_interrupt_to_thread
-
-.globl      rt_current_thread
-.globl      vmm_thread
-.globl      vmm_virq_check
-
-    .align  5
-.globl vector_irq
-vector_irq:
-#ifdef RT_USING_SMP
-    clrex
-      
-    stmfd   sp!, {r0, r1}
-    cps     #Mode_SVC
-    mov     r0, sp          /* svc_sp */
-    mov     r1, lr          /* svc_lr */
-
-    cps     #Mode_IRQ
-    sub     lr, lr, #4
-    stmfd   r0!, {r1, lr}       /* svc_lr, svc_pc */
-    stmfd   r0!, {r2 - r12}
-    ldmfd   sp!, {r1, r2}     /* original r0, r1 */
-    stmfd   r0!, {r1 - r2}
-    mrs     r1,  spsr         /* original mode */
-    stmfd   r0!, {r1}
-
-#ifdef RT_USING_LWP
-    stmfd   r0, {r13, r14}^ /* usr_sp, usr_lr */
-    sub   r0, #8
-#endif
-#ifdef RT_USING_FPU
-    /* fpu context */
-    vmrs r6, fpexc
-    tst  r6, #(1<<30)
-    beq 1f
-    vstmdb r0!, {d0-d15}
-    vstmdb r0!, {d16-d31}
-    vmrs r5, fpscr
-    stmfd r0!, {r5}
-1:
-    stmfd r0!, {r6}
-#endif
-    mov     r8, r0
-
-    bl      rt_interrupt_enter
-    bl      rt_hw_trap_irq
-    bl      rt_interrupt_leave
-    
-    cps     #Mode_SVC
-    mov     sp, r8
-    mov     r0, r8
-    
-    bl      rt_scheduler_do_irq_switch
-
-    b       rt_hw_context_switch_exit
-
-#else
-    stmfd   sp!, {r0-r12,lr}
-
-    bl      rt_interrupt_enter
-    bl      rt_hw_trap_irq
-    bl      rt_interrupt_leave
-
-    @ if rt_thread_switch_interrupt_flag set, jump to
-    @ rt_hw_context_switch_interrupt_do and don't return
-    ldr     r0, =rt_thread_switch_interrupt_flag
-    ldr     r1, [r0]
-    cmp     r1, #1
-    beq     rt_hw_context_switch_interrupt_do
-
-    ldmfd   sp!, {r0-r12,lr}
-    subs    pc,  lr, #4
-
-rt_hw_context_switch_interrupt_do:
-    mov     r1,  #0         @ clear flag
-    str     r1,  [r0]
-
-    mov     r1, sp          @ r1 point to {r0-r3} in stack
-    add     sp, sp, #4*4
-    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
-    mrs     r0,  spsr       @ get cpsr of interrupt thread
-    sub     r2,  lr, #4     @ save old task's pc to r2
-
-    @ Switch to SVC mode with no interrupt. If the usr mode guest is
-    @ interrupted, this will just switch to the stack of kernel space.
-    @ save the registers in kernel space won't trigger data abort.
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
-    stmfd   sp!, {r2}       @ push old task's pc
-    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
-    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
-    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
-    stmfd   sp!, {r0}       @ push old task's cpsr
-
-#ifdef RT_USING_LWP
-    stmfd sp, {r13, r14}^  @push usr_sp, usr_lr
-    sub sp, #8
-#endif
-#ifdef RT_USING_FPU
-    /* fpu context */
-    vmrs r6, fpexc
-    tst  r6, #(1<<30)
-    beq 1f
-    vstmdb sp!, {d0-d15}
-    vstmdb sp!, {d16-d31}
-    vmrs r5, fpscr
-    stmfd sp!, {r5}
-1:
-    stmfd sp!, {r6}
-#endif
-
-    ldr     r4,  =rt_interrupt_from_thread
-    ldr     r5,  [r4]
-    str     sp,  [r5]       @ store sp in preempted tasks's TCB
-
-    ldr     r6,  =rt_interrupt_to_thread
-    ldr     r6,  [r6]
-    ldr     sp,  [r6]       @ get new task's stack pointer
-
-#ifdef RT_USING_FPU
-/* fpu context */
-    ldmfd sp!, {r6}
-    vmsr fpexc, r6
-    tst  r6, #(1<<30)
-    beq 1f
-    ldmfd sp!, {r5}
-    vmsr fpscr, r5
-    vldmia sp!, {d16-d31}
-    vldmia sp!, {d0-d15}
-1:
-#endif
-
-#ifdef RT_USING_LWP
-    ldmfd sp, {r13, r14}^  @pop usr_sp, usr_lr
-    add sp, #8
-#endif
-
-    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
-    msr     spsr_cxsf, r4
-
-    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
-
-#endif
-
-.macro push_svc_reg
-    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
-    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
-    mov     r0, sp
-    mrs     r6, spsr                @/* Save CPSR                       */
-    str     lr, [r0, #15*4]         @/* Push PC                         */
-    str     r6, [r0, #16*4]         @/* Push CPSR                       */
-    cps     #Mode_SVC
-    str     sp, [r0, #13*4]         @/* Save calling SP                 */
-    str     lr, [r0, #14*4]         @/* Save calling PC                 */
-.endm
-
-    .align  5
-    .globl  vector_swi
-vector_swi:
-    push_svc_reg
-    bl      rt_hw_trap_swi
-    b       .
-
-    .align  5
-    .globl  vector_undef
-vector_undef:
-    push_svc_reg
-    cps #Mode_UND
-    bl      rt_hw_trap_undef
-#ifdef RT_USING_FPU
-    ldr     lr, [sp, #15*4]
-    ldmia   sp, {r0 - r12}
-    add     sp, sp, #17 * 4
-    movs    pc, lr
-#endif
-    b       .
-
-    .align  5
-    .globl  vector_pabt
-vector_pabt:
-    push_svc_reg
-    bl      rt_hw_trap_pabt
-    b       .
-
-    .align  5
-    .globl  vector_dabt
-vector_dabt:
-    push_svc_reg
-    bl      rt_hw_trap_dabt
-    b       .
-
-    .align  5
-    .globl  vector_resv
-vector_resv:
-    push_svc_reg
-    bl      rt_hw_trap_resv
-    b       .
-
-#ifdef RT_USING_SMP
-
-.global secondary_cpu_start
-secondary_cpu_start:
-    /* set vector base */
-    mrc p15, 0, r0, c1, c0, 0        
-    bic r0, #(1<<13)
-    mcr p15, 0, r0, c1, c0, 0
-    
-    /* setup stack */
-    mrc p15, 0, r0, c0, c0, 5
-    ubfx    r0, r0, #0, #2
-    ldr r1, =stack_top0
-    ldr r2, =ISR_Stack_Size
-    mul r3, r2, r0
-    add r0, r1, r3
-    bl  stack_setup
-    /* initialize the mmu table and enable mmu */
-    bl  rt_hw_mmu_init
-    b   secondary_cpu_c_start
-
-#endif
-
-;@ void arm_smp_enable(void);
-.globl arm_smp_enable
-arm_smp_enable:
-    mrc p15, 0, r0, c1, c0, 1   ;@ set SMP bit in ACTLR
-    orr r0, r0, #0x40
-    mcr p15, 0, r0, c1, c0, 1
-    bx lr
-/*
-    mrrc p15, 1, r0, r1, c15
-    orr r0, r0, #0x40
-    mcrr p15, 1, r0, r1, c15
-    dsb
-    isb
-    bx lr
-*/
-.text
-;@ void arm_smp_disable(void);
-.globl arm_smp_disable
-
-arm_smp_disable:
-    mrc p15, 0, r0, c1, c0, 1   ;@ clear SMP bit in ACTLR
-    bic r0, r0, #0x40
-    mcr p15, 0, r0, c1, c0, 1
-    bx lr
-/*
-    mrrc p15, 1, r0, r1, c15
-    bic r0, r0, #0x40
-    mcrr p15, 1, r0, r1, c15
-    bx lr
-*/
-
diff --git a/libcpu/arm/cortex-a53/trap.c b/libcpu/arm/cortex-a53/trap.c
deleted file mode 100644
index f83f183695..0000000000
--- a/libcpu/arm/cortex-a53/trap.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-20     Bernard      first version
- * 2019-07-28     zdzn         add smp support
- * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
- *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
- */
-
-#include <rthw.h>
-#include <board.h>
-#include <rtthread.h>
-
-#include "armv7.h"
-
-extern struct rt_thread *rt_current_thread;
-#ifdef RT_USING_FINSH
-extern long list_thread(void);
-#endif
-
-
-/**
- * this function will show registers of CPU
- *
- * @param regs the registers point
- */
-void rt_hw_show_register(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("Execption:\n");
-    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
-}
-
-
-/**
- * When comes across an instruction which it cannot handle,
- * it takes the undefined instruction trap.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("undefined instruction:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * The software interrupt instruction (SWI) is used for entering
- * Supervisor mode, usually to request a particular supervisor
- * function.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("software interrupt:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * An abort indicates that the current memory access cannot be completed,
- * which occurs during an instruction prefetch.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("prefetch abort:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * An abort indicates that the current memory access cannot be completed,
- * which occurs during a data access.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("data abort:");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * Normally, system will never reach here
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("reserved trap:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-void rt_hw_trap_irq(void)
-{
-    void *param;
-    uint32_t irq;
-    rt_isr_handler_t isr_func;
-    extern struct rt_irq_desc isr_table[];
-    uint32_t value = 0;
-    value = IRQ_PEND_BASIC & 0x3ff;
-#ifdef RT_USING_SMP
-    uint32_t mailbox_data;
-    uint32_t cpu_id = rt_hw_cpu_id();
-    uint32_t int_source = CORE_IRQSOURCE(cpu_id);
-    mailbox_data = IPI_MAILBOX_CLEAR(cpu_id);
-    if (int_source & 0x0f)
-    {
-        if (int_source & 0x08)
-        {
-            isr_func = isr_table[IRQ_ARM_TIMER].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-            isr_table[IRQ_ARM_TIMER].counter++;
-#endif
-            if (isr_func)
-            {
-                param = isr_table[IRQ_ARM_TIMER].param;
-                isr_func(IRQ_ARM_TIMER, param);
-            }
-        }
-    }
-    if (int_source & 0xf0)
-    {
-        /*it's a ipi interrupt*/
-        if (mailbox_data & 0x1)
-        {
-            /* clear mailbox */
-            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;    
-            isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-            isr_table[IRQ_ARM_MAILBOX].counter++;
-#endif
-            if (isr_func)
-            {
-                param = isr_table[IRQ_ARM_MAILBOX].param;
-                isr_func(IRQ_ARM_MAILBOX, param);
-            }
-        }
-        else 
-            CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
-    }
-#endif
-    /* local interrupt*/
-    if (value)
-    {
-        if (value & (1 << 8))
-        {
-            value = IRQ_PEND1;
-            irq = __rt_ffs(value) - 1;
-        }
-        else if (value & (1 << 9))
-        {
-            value = IRQ_PEND2;
-            irq = __rt_ffs(value) + 31;
-        }
-        else
-        {
-            value &= 0x0f;
-            irq = __rt_ffs(value) + 63;
-        }
-
-        /* get interrupt service routine */
-        isr_func = isr_table[irq].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-        isr_table[irq].counter++;
-#endif
-        if (isr_func)
-        {
-            /* Interrupt for myself. */
-            param = isr_table[irq].param;
-            /* turn to interrupt service routine */
-            isr_func(irq, param);
-        }
-    }
-}
-
-void rt_hw_trap_fiq(void)
-{
-
-}
diff --git a/libcpu/arm/cortex-a53/vector_gcc.S b/libcpu/arm/cortex-a53/vector_gcc.S
deleted file mode 100644
index eebfe9c13b..0000000000
--- a/libcpu/arm/cortex-a53/vector_gcc.S
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.section .vectors, "ax"
-.code 32
-
-.globl system_vectors
-system_vectors:
-    ldr pc, _vector_reset
-    ldr pc, _vector_undef
-    ldr pc, _vector_swi
-    ldr pc, _vector_pabt
-    ldr pc, _vector_dabt
-    ldr pc, _vector_resv
-    ldr pc, _vector_irq
-    ldr pc, _vector_fiq
-
-.globl _reset
-.globl vector_undef
-.globl vector_swi
-.globl vector_pabt
-.globl vector_dabt
-.globl vector_resv
-.globl vector_irq
-.globl vector_fiq
-
-_vector_reset:
-    .word _reset
-_vector_undef:
-    .word vector_undef
-_vector_swi:
-    .word vector_swi
-_vector_pabt:
-    .word vector_pabt
-_vector_dabt:
-    .word vector_dabt
-_vector_resv:
-    .word vector_resv
-_vector_irq:
-    .word vector_irq
-_vector_fiq:
-    .word vector_fiq
-
-.balignl    16,0xdeadbeef
diff --git a/libcpu/arm/cortex-a7/SConscript b/libcpu/arm/cortex-a7/SConscript
deleted file mode 100644
index eb4ee7a585..0000000000
--- a/libcpu/arm/cortex-a7/SConscript
+++ /dev/null
@@ -1,9 +0,0 @@
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/libcpu/arm/cortex-a7/armv7.h b/libcpu/arm/cortex-a7/armv7.h
deleted file mode 100644
index a07d9de2a9..0000000000
--- a/libcpu/arm/cortex-a7/armv7.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef __ARMV7_H__
-#define __ARMV7_H__
-
-/* the exception stack without VFP registers */
-struct rt_hw_exp_stack
-{
-    unsigned long r0;
-    unsigned long r1;
-    unsigned long r2;
-    unsigned long r3;
-    unsigned long r4;
-    unsigned long r5;
-    unsigned long r6;
-    unsigned long r7;
-    unsigned long r8;
-    unsigned long r9;
-    unsigned long r10;
-    unsigned long fp;
-    unsigned long ip;
-    unsigned long sp;
-    unsigned long lr;
-    unsigned long pc;
-    unsigned long cpsr;
-};
-
-struct rt_hw_stack
-{
-    unsigned long cpsr;
-    unsigned long r0;
-    unsigned long r1;
-    unsigned long r2;
-    unsigned long r3;
-    unsigned long r4;
-    unsigned long r5;
-    unsigned long r6;
-    unsigned long r7;
-    unsigned long r8;
-    unsigned long r9;
-    unsigned long r10;
-    unsigned long fp;
-    unsigned long ip;
-    unsigned long lr;
-    unsigned long pc;
-};
-
-#define USERMODE    0x10
-#define FIQMODE     0x11
-#define IRQMODE     0x12
-#define SVCMODE     0x13
-#define MONITORMODE 0x16
-#define ABORTMODE   0x17
-#define HYPMODE     0x1b
-#define UNDEFMODE   0x1b
-#define MODEMASK    0x1f
-#define NOINT       0xc0
-
-#define T_Bit       (1<<5)
-#define F_Bit       (1<<6)
-#define I_Bit       (1<<7)
-#define A_Bit       (1<<8)
-#define E_Bit       (1<<9)
-#define J_Bit       (1<<24)
-
-#endif
diff --git a/libcpu/arm/cortex-a7/context_gcc.S b/libcpu/arm/cortex-a7/context_gcc.S
deleted file mode 100644
index 48402739f9..0000000000
--- a/libcpu/arm/cortex-a7/context_gcc.S
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * File      : context.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.section .text, "ax"
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mrs r0, cpsr
-    cpsid i
-    bx  lr
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    msr cpsr_c, r0
-    bx  lr
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
- */
-.globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    ldr sp, [r0]            @ get new task stack pointer
-
-    ldmfd sp!, {r4}         @ pop new task spsr
-    msr spsr_cxsf, r4
-
-    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
-
-.section .bss.share.isr
-_guest_switch_lvl:
-    .word 0
-
-.globl vmm_virq_update
-
-.section .text.isr, "ax"
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r0 --> from
- * r1 --> to
- */
-.globl rt_hw_context_switch
-rt_hw_context_switch:
-    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
-    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
-
-    mrs r4, cpsr
-    tst lr, #0x01
-    orrne r4, r4, #0x20     @ it's thumb code
-
-    stmfd sp!, {r4}         @ push cpsr
-
-    str sp, [r0]            @ store sp in preempted tasks TCB
-    ldr sp, [r1]            @ get new task stack pointer
-
-    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
-    msr spsr_cxsf, r4
-    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
- */
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    ldr r2, =rt_thread_switch_interrupt_flag
-    ldr r3, [r2]
-    cmp r3, #1
-    beq _reswitch
-    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
-    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
-    str r0, [ip]
-    str r3, [r2]
-_reswitch:
-    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
-    str r1, [r2]
-    bx  lr
diff --git a/libcpu/arm/cortex-a7/cp15.h b/libcpu/arm/cortex-a7/cp15.h
deleted file mode 100644
index ebea3f0fe3..0000000000
--- a/libcpu/arm/cortex-a7/cp15.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __CP15_H__
-#define __CP15_H__
-
-unsigned long rt_cpu_get_smp_id(void);
-
-void rt_cpu_mmu_disable(void);
-void rt_cpu_mmu_enable(void);
-void rt_cpu_tlb_set(volatile unsigned long*);
-
-void rt_cpu_vector_set_base(unsigned int addr);
-
-#endif
diff --git a/libcpu/arm/cortex-a7/cp15_gcc.S b/libcpu/arm/cortex-a7/cp15_gcc.S
deleted file mode 100644
index f1ed6492aa..0000000000
--- a/libcpu/arm/cortex-a7/cp15_gcc.S
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * File      : cp15_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- * http://www.rt-thread.org
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.globl rt_cpu_get_smp_id
-rt_cpu_get_smp_id:
-    mrc     p15, #0, r0, c0, c0, #5
-    bx      lr
-
-.globl rt_cpu_vector_set_base
-rt_cpu_vector_set_base:
-    mcr     p15, #0, r0, c12, c0, #0
-    dsb
-    bx      lr
-
-.globl rt_hw_cpu_dcache_enable
-rt_hw_cpu_dcache_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0,  r0, #0x00000004
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-.globl rt_hw_cpu_icache_enable
-rt_hw_cpu_icache_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0,  r0, #0x00001000
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-_FLD_MAX_WAY:
-   .word  0x3ff
-_FLD_MAX_IDX:
-   .word  0x7ff
-
-.globl rt_cpu_dcache_clean_flush
-rt_cpu_dcache_clean_flush:
-    push    {r4-r11}
-    dmb
-    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
-    ands    r3, r0, #0x7000000       @ get level of coherency
-    mov     r3, r3, lsr #23
-    beq     finished
-    mov     r10, #0
-loop1:
-    add     r2, r10, r10, lsr #1
-    mov     r1, r0, lsr r2
-    and     r1, r1, #7
-    cmp     r1, #2
-    blt     skip
-    mcr     p15, #2, r10, c0, c0, #0
-    isb
-    mrc     p15, #1, r1, c0, c0, #0
-    and     r2, r1, #7
-    add     r2, r2, #4
-    ldr     r4, _FLD_MAX_WAY
-    ands    r4, r4, r1, lsr #3
-    clz     r5, r4
-    ldr     r7, _FLD_MAX_IDX
-    ands    r7, r7, r1, lsr #13
-loop2:
-    mov     r9, r4
-loop3:
-    orr     r11, r10, r9, lsl r5
-    orr     r11, r11, r7, lsl r2
-    mcr     p15, #0, r11, c7, c14, #2
-    subs    r9, r9, #1
-    bge     loop3
-    subs    r7, r7, #1
-    bge     loop2
-skip:
-    add     r10, r10, #2
-    cmp     r3, r10
-    bgt     loop1
-
-finished:
-    dsb
-    isb
-    pop     {r4-r11}
-    bx      lr
-
-.globl rt_hw_cpu_dcache_disable
-rt_hw_cpu_dcache_disable:
-    push    {r4-r11, lr}
-    bl      rt_cpu_dcache_clean_flush
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0,  r0, #0x00000004
-    mcr     p15, #0, r0, c1, c0, #0
-    pop     {r4-r11, lr}
-    bx      lr
-
-.globl rt_hw_cpu_icache_disable
-rt_hw_cpu_icache_disable:
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0,  r0, #0x00001000
-    mcr     p15, #0, r0, c1, c0, #0
-    bx      lr
-
-.globl rt_cpu_mmu_disable
-rt_cpu_mmu_disable:
-    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
-    mrc     p15, #0, r0, c1, c0, #0
-    bic     r0, r0, #1
-    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
-    dsb
-    bx      lr
-
-.globl rt_cpu_mmu_enable
-rt_cpu_mmu_enable:
-    mrc     p15, #0, r0, c1, c0, #0
-    orr     r0, r0, #0x001
-    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
-    dsb
-    bx      lr
-
-.globl rt_cpu_tlb_set
-rt_cpu_tlb_set:
-    mcr     p15, #0, r0, c2, c0, #0
-    dmb
-    bx      lr
diff --git a/libcpu/arm/cortex-a7/cpu.c b/libcpu/arm/cortex-a7/cpu.c
deleted file mode 100644
index 8bf16d19e8..0000000000
--- a/libcpu/arm/cortex-a7/cpu.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <board.h>
-
-/**
- * @addtogroup AM33xx
- */
-/*@{*/
-
-/** shutdown CPU */
-void rt_hw_cpu_shutdown()
-{
-    rt_uint32_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/arm/cortex-a7/interrupt.c b/libcpu/arm/cortex-a7/interrupt.c
deleted file mode 100644
index d502977c3e..0000000000
--- a/libcpu/arm/cortex-a7/interrupt.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018/5/3       Bernard      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "cp15.h"
-#include <board.h>
-
-#define MAX_HANDLERS                64
-
-extern volatile rt_uint8_t rt_interrupt_nest;
-
-/* exception and interrupt handler table */
-struct rt_irq_desc isr_table[MAX_HANDLERS];
-
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-extern int system_vectors;
-
-static void default_isr_handler(int vector, void *param)
-{
-    rt_kprintf("unhandled irq: %d\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    uint32_t index;
-
-    /* mask all of interrupts */
-    IRQ_DISABLE_BASIC = 0x000000ff;
-    IRQ_DISABLE1      = 0xffffffff;
-    IRQ_DISABLE2      = 0xffffffff;
-
-    for (index = 0; index < MAX_HANDLERS; index ++)
-    {
-        isr_table[index].handler = default_isr_handler;
-        isr_table[index].param = NULL;
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
-        isr_table[index].counter = 0;
-#endif
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-    if (vector < 8)
-    {
-        IRQ_DISABLE_BASIC = (1 << vector);
-    }
-    else if (vector < 32)
-    {
-        IRQ_DISABLE1 = (1 << vector);
-    }
-    else
-    {
-        vector = vector % 32;
-        IRQ_DISABLE2 = (1 << vector);
-    }
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    if (vector < 8)
-    {
-        IRQ_ENABLE_BASIC = (1 << vector);
-    }
-    else if (vector < 32)
-    {
-        IRQ_ENABLE1 = (1 << vector);
-    }
-    else
-    {
-        vector = vector % 32;
-        IRQ_ENABLE2 = (1 << vector);
-    }
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector < MAX_HANDLERS)
-    {
-        old_handler = isr_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-            isr_table[vector].handler = handler;
-            isr_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
diff --git a/libcpu/arm/cortex-a7/mmu.c b/libcpu/arm/cortex-a7/mmu.c
deleted file mode 100644
index b2503e4260..0000000000
--- a/libcpu/arm/cortex-a7/mmu.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * File      : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2012-01-10     bernard      porting to AM1808
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include <board.h>
-
-#include "cp15.h"
-
-#define DESC_SEC       (0x2)
-#define CB             (3<<2)  //cache_on, write_back
-#define CNB            (2<<2)  //cache_on, write_through
-#define NCB            (1<<2)  //cache_off,WR_BUF on
-#define NCNB           (0<<2)  //cache_off,WR_BUF off
-#define AP_RW          (3<<10) //supervisor=RW, user=RW
-#define AP_RO          (2<<10) //supervisor=RW, user=RO
-#define XN             (1<<4)  // eXecute Never
-
-#define DOMAIN_FAULT   (0x0)
-#define DOMAIN_CHK     (0x1)
-#define DOMAIN_NOTCHK  (0x3)
-#define DOMAIN0        (0x0<<5)
-#define DOMAIN1        (0x1<<5)
-
-#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
-
-/* Read/Write, cache, write back */
-#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
-/* Read/Write, cache, write through */
-#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
-/* Read/Write without cache and write buffer */
-#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
-/* Read/Write without cache and write buffer, no execute */
-#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
-/* Read/Write without cache and write buffer */
-#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
-
-/* dump 2nd level page table */
-void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    for (i = 0; i < 256; i++)
-    {
-        rt_uint32_t pte2 = ptb[i];
-        if ((pte2 & 0x3) == 0)
-        {
-            if (fcnt == 0)
-                rt_kprintf("    ");
-            rt_kprintf("%04x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("    %04x: %x: ", i, pte2);
-        if ((pte2 & 0x3) == 0x1)
-        {
-            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
-                       (pte2 >> 15) & 0x1,
-                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
-                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
-        }
-    }
-}
-
-void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    rt_kprintf("page table@%p\n", ptb);
-    for (i = 0; i < 1024*4; i++)
-    {
-        rt_uint32_t pte1 = ptb[i];
-        if ((pte1 & 0x3) == 0)
-        {
-            rt_kprintf("%03x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("%03x: %08x: ", i, pte1);
-        if ((pte1 & 0x3) == 0x3)
-        {
-            rt_kprintf("LPAE\n");
-        }
-        else if ((pte1 & 0x3) == 0x1)
-        {
-            rt_kprintf("pte,ns:%d,domain:%d\n",
-                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
-            /*
-             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
-             *                               - 0x80000000 + 0xC0000000));
-             */
-        }
-        else if (pte1 & (1 << 18))
-        {
-            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("section,ns:%d,ap:%x,"
-                       "xn:%d,texcb:%02x,domain:%d\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       (((pte1 & (0x7 << 12)) >> 10) |
-                        ((pte1 &        0x0c) >>  2)) & 0x1f,
-                       (pte1 >> 5) & 0xf);
-        }
-    }
-}
-
-/* level1 page table, each entry for 1MB memory. */
-volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
-void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
-                      rt_uint32_t vaddrEnd,
-                      rt_uint32_t paddrStart,
-                      rt_uint32_t attr)
-{
-    volatile rt_uint32_t *pTT;
-    volatile int i, nSec;
-    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
-    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
-    for(i = 0; i <= nSec; i++)
-    {
-        *pTT = attr | (((paddrStart >> 20) + i) << 20);
-        pTT++;
-    }
-}
-
-unsigned long rt_hw_set_domain_register(unsigned long domain_val)
-{
-    unsigned long old_domain;
-
-    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
-    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
-
-    return old_domain;
-}
-
-void rt_hw_mmu_init(void)
-{
-    rt_hw_cpu_dcache_disable();
-    rt_hw_cpu_icache_disable();
-    rt_cpu_mmu_disable();
-
-    /* set page table */
-    /* 4G 1:1 memory */
-    rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
-    /* IO memory region */
-    rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
-
-    /*rt_hw_cpu_dump_page_table(MMUTable);*/
-    rt_hw_set_domain_register(0x55555555);
-
-    rt_cpu_tlb_set(MMUTable);
-
-    rt_cpu_mmu_enable();
-
-    rt_hw_cpu_icache_enable();
-    rt_hw_cpu_dcache_enable();
-}
-
diff --git a/libcpu/arm/cortex-a7/stack.c b/libcpu/arm/cortex-a7/stack.c
deleted file mode 100644
index e60e8c7170..0000000000
--- a/libcpu/arm/cortex-a7/stack.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-23     Bernard      the first version
- * 2011-10-05     Bernard      add thumb mode
- */
-#include <rtthread.h>
-#include <board.h>
-#include <armv7.h>
-
-/**
- * @addtogroup AM33xx
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-                             rt_uint8_t *stack_addr, void *texit)
-{
-    rt_uint32_t *stk;
-
-    stack_addr += sizeof(rt_uint32_t);
-    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
-    stk      = (rt_uint32_t *)stack_addr;
-    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
-    *(--stk) = (rt_uint32_t)texit;          /* lr */
-    *(--stk) = 0xdeadbeef;                  /* r12 */
-    *(--stk) = 0xdeadbeef;                  /* r11 */
-    *(--stk) = 0xdeadbeef;                  /* r10 */
-    *(--stk) = 0xdeadbeef;                  /* r9 */
-    *(--stk) = 0xdeadbeef;                  /* r8 */
-    *(--stk) = 0xdeadbeef;                  /* r7 */
-    *(--stk) = 0xdeadbeef;                  /* r6 */
-    *(--stk) = 0xdeadbeef;                  /* r5 */
-    *(--stk) = 0xdeadbeef;                  /* r4 */
-    *(--stk) = 0xdeadbeef;                  /* r3 */
-    *(--stk) = 0xdeadbeef;                  /* r2 */
-    *(--stk) = 0xdeadbeef;                  /* r1 */
-    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
-
-    /* cpsr */
-    if ((rt_uint32_t)tentry & 0x01)
-        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
-    else
-        *(--stk) = SVCMODE;                 /* arm mode   */
-
-    /* return task's current stack address */
-    return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/libcpu/arm/cortex-a7/start_gcc.S b/libcpu/arm/cortex-a7/start_gcc.S
deleted file mode 100644
index b60ad6a38f..0000000000
--- a/libcpu/arm/cortex-a7/start_gcc.S
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.equ Mode_USR,        0x10
-.equ Mode_FIQ,        0x11
-.equ Mode_IRQ,        0x12
-.equ Mode_SVC,        0x13
-.equ Mode_ABT,        0x17
-.equ Mode_UND,        0x1B
-.equ Mode_SYS,        0x1F
-
-.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
-.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
-
-.equ UND_Stack_Size,     0x00000000
-.equ SVC_Stack_Size,     0x00000100
-.equ ABT_Stack_Size,     0x00000000
-.equ RT_FIQ_STACK_PGSZ,  0x00000000
-.equ RT_IRQ_STACK_PGSZ,  0x00000100
-.equ USR_Stack_Size,     0x00000100
-
-#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
-                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
-
-.section .data.share.isr
-/* stack */
-.globl stack_start
-.globl stack_top
-
-.align 3
-stack_start:
-.rept ISR_Stack_Size
-.byte 0
-.endr
-stack_top:
-
-.text
-/* reset entry */
-.globl _reset
-_reset:
-	/* Disable IRQ & FIQ */
-	cpsid if
-
-	/* Check for HYP mode */
-	mrs r0, cpsr_all
-	and r0, r0, #0x1F
-	mov r8, #0x1A
-	cmp r0, r8
-	beq overHyped
-	b continue
-
-overHyped: /* Get out of HYP mode */
-	ldr r1, =continue
-	msr ELR_hyp, r1
-	mrs r1, cpsr_all
-	and r1, r1, #0x1f	;@ CPSR_MODE_MASK
-	orr r1, r1, #0x13	;@ CPSR_MODE_SUPERVISOR
-	msr SPSR_hyp, r1
-	eret
-
-continue:
-
-    /* disable smp */
-    bl      arm_smp_disable
-
-    /* disable mmu */
-    bl      rt_cpu_mmu_disable
-    /* set the cpu to SVC32 mode and disable interrupt */
-    mrs     r0, cpsr
-    bic     r0, r0, #0x1f
-    orr     r0, r0, #0x13
-    msr     cpsr_c, r0
-
-    /* setup stack */
-    bl      stack_setup
-
-    /* clear .bss */
-    mov     r0,#0                   /* get a zero                       */
-    ldr     r1,=__bss_start         /* bss start                        */
-    ldr     r2,=__bss_end           /* bss end                          */
-
-bss_loop:
-    cmp     r1,r2                   /* check if data to clear           */
-    strlo   r0,[r1],#4              /* clear 4 bytes                    */
-    blo     bss_loop                /* loop until done                  */
-
-    /* start RT-Thread Kernel */
-    ldr     pc, _rtthread_startup
-_rtthread_startup:
-    .word rtthread_startup
-
-stack_setup:
-    ldr     r0, =stack_top
-
-    @  Set the startup stack for svc
-    mov     sp, r0
-	sub     r0, r0, #SVC_Stack_Size
-
-    @  Enter Undefined Instruction Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #UND_Stack_Size
-
-    @  Enter Abort Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #ABT_Stack_Size
-
-    @  Enter FIQ Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #RT_FIQ_STACK_PGSZ
-
-    @  Enter IRQ Mode and set its Stack Pointer
-    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
-    mov     sp, r0
-    sub     r0, r0, #RT_IRQ_STACK_PGSZ
-
-    /* come back to SVC mode */
-    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
-    bx      lr
-
-.text
-;@ void arm_smp_enable(void);
-.globl arm_smp_enable
-arm_smp_enable:
-    mrc p15, 0, r0, c1, c0, 1   ;@ set SMP bit in ACTLR
-    orr r0, r0, #0x40
-    mcr p15, 0, r0, c1, c0, 1
-    bx lr
-
-.text
-;@ void arm_smp_disable(void);
-.globl arm_smp_disable
-arm_smp_disable:
-    mrc p15, 0, r0, c1, c0, 1   ;@ clear SMP bit in ACTLR
-    bic r0, r0, #0x40
-    mcr p15, 0, r0, c1, c0, 1
-    bx lr
-
-/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
-.section .text.isr, "ax"
-    .align  5
-.globl vector_fiq
-vector_fiq:
-    stmfd   sp!,{r0-r7,lr}
-    bl      rt_hw_trap_fiq
-    ldmfd   sp!,{r0-r7,lr}
-    subs    pc, lr, #4
-
-.globl      rt_interrupt_enter
-.globl      rt_interrupt_leave
-.globl      rt_thread_switch_interrupt_flag
-.globl      rt_interrupt_from_thread
-.globl      rt_interrupt_to_thread
-
-.globl      rt_current_thread
-.globl      vmm_thread
-.globl      vmm_virq_check
-
-    .align  5
-.globl vector_irq
-vector_irq:
-    stmfd   sp!, {r0-r12,lr}
-
-    bl      rt_interrupt_enter
-    bl      rt_hw_trap_irq
-    bl      rt_interrupt_leave
-
-    @ if rt_thread_switch_interrupt_flag set, jump to
-    @ rt_hw_context_switch_interrupt_do and don't return
-    ldr     r0, =rt_thread_switch_interrupt_flag
-    ldr     r1, [r0]
-    cmp     r1, #1
-    beq     rt_hw_context_switch_interrupt_do
-
-    ldmfd   sp!, {r0-r12,lr}
-    subs    pc,  lr, #4
-
-rt_hw_context_switch_interrupt_do:
-    mov     r1,  #0         @ clear flag
-    str     r1,  [r0]
-
-    mov     r1, sp          @ r1 point to {r0-r3} in stack
-    add     sp, sp, #4*4
-    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
-    mrs     r0,  spsr       @ get cpsr of interrupt thread
-    sub     r2,  lr, #4     @ save old task's pc to r2
-
-    @ Switch to SVC mode with no interrupt. If the usr mode guest is
-    @ interrupted, this will just switch to the stack of kernel space.
-    @ save the registers in kernel space won't trigger data abort.
-    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
-    stmfd   sp!, {r2}       @ push old task's pc
-    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
-    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
-    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
-    stmfd   sp!, {r0}       @ push old task's cpsr
-
-    ldr     r4,  =rt_interrupt_from_thread
-    ldr     r5,  [r4]
-    str     sp,  [r5]       @ store sp in preempted tasks's TCB
-
-    ldr     r6,  =rt_interrupt_to_thread
-    ldr     r6,  [r6]
-    ldr     sp,  [r6]       @ get new task's stack pointer
-
-    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
-    msr     spsr_cxsf, r4
-
-    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
-
-.macro push_svc_reg
-    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
-    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
-    mov     r0, sp
-    mrs     r6, spsr                @/* Save CPSR                       */
-    str     lr, [r0, #15*4]         @/* Push PC                         */
-    str     r6, [r0, #16*4]         @/* Push CPSR                       */
-    cps     #Mode_SVC
-    str     sp, [r0, #13*4]         @/* Save calling SP                 */
-    str     lr, [r0, #14*4]         @/* Save calling PC                 */
-.endm
-
-    .align  5
-    .globl  vector_swi
-vector_swi:
-    push_svc_reg
-    bl      rt_hw_trap_swi
-    b       .
-
-    .align  5
-    .globl  vector_undef
-vector_undef:
-    push_svc_reg
-    bl      rt_hw_trap_undef
-    b       .
-
-    .align  5
-    .globl  vector_pabt
-vector_pabt:
-    push_svc_reg
-    bl      rt_hw_trap_pabt
-    b       .
-
-    .align  5
-    .globl  vector_dabt
-vector_dabt:
-    push_svc_reg
-    bl      rt_hw_trap_dabt
-    b       .
-
-    .align  5
-    .globl  vector_resv
-vector_resv:
-    push_svc_reg
-    bl      rt_hw_trap_resv
-    b       .
diff --git a/libcpu/arm/cortex-a7/trap.c b/libcpu/arm/cortex-a7/trap.c
deleted file mode 100644
index 3012c26e2c..0000000000
--- a/libcpu/arm/cortex-a7/trap.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-20     Bernard      first version
- */
-
-#include <rthw.h>
-#include <board.h>
-#include <rtthread.h>
-
-#include "armv7.h"
-
-extern struct rt_thread *rt_current_thread;
-#ifdef RT_USING_FINSH
-extern long list_thread(void);
-#endif
-
-/**
- * this function will show registers of CPU
- *
- * @param regs the registers point
- */
-void rt_hw_show_register(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("Execption:\n");
-    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
-}
-
-/**
- * When comes across an instruction which it cannot handle,
- * it takes the undefined instruction trap.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("undefined instruction:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * The software interrupt instruction (SWI) is used for entering
- * Supervisor mode, usually to request a particular supervisor
- * function.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("software interrupt:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * An abort indicates that the current memory access cannot be completed,
- * which occurs during an instruction prefetch.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("prefetch abort:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * An abort indicates that the current memory access cannot be completed,
- * which occurs during a data access.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("data abort:");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-/**
- * Normally, system will never reach here
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("reserved trap:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-void rt_hw_trap_irq(void)
-{
-    void *param;
-    rt_isr_handler_t isr_func;
-    extern struct rt_irq_desc isr_table[];
-
-    uint32_t value = 0;
-
-    // rt_kprintf("pend basic: 0x%08x\n", IRQ_PEND_BASIC);
-    // rt_kprintf("     pend1: 0x%08x\n", IRQ_PEND1);
-    // rt_kprintf("     pend2: 0x%08x\n", IRQ_PEND2);
-
-    value = IRQ_PEND_BASIC & 0x3ff;
-    if (value)
-    {
-        uint32_t irq;
-
-        if (value & (1 << 8))
-        {
-            value = IRQ_PEND1;
-            irq = __rt_ffs(value) - 1;
-        }
-        else if (value & (1 << 9))
-        {
-            value = IRQ_PEND2;
-            irq = __rt_ffs(value) + 31;
-        }
-        else
-        {
-            value &= 0x0f;
-            irq = __rt_ffs(value) - 1;
-        }
-
-        /* get interrupt service routine */
-        isr_func = isr_table[irq].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-        isr_table[irq].counter++;
-#endif
-        if (isr_func)
-        {
-            /* Interrupt for myself. */
-            param = isr_table[irq].param;
-            /* turn to interrupt service routine */
-            isr_func(irq, param);
-        }
-    }
-}
-
-void rt_hw_trap_fiq(void)
-{
-    /* TODO */
-}
diff --git a/libcpu/arm/cortex-a7/vector_gcc.S b/libcpu/arm/cortex-a7/vector_gcc.S
deleted file mode 100644
index 17c2d69c30..0000000000
--- a/libcpu/arm/cortex-a7/vector_gcc.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * File      : vector_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-.section .vectors, "ax"
-.code 32
-
-.globl system_vectors
-system_vectors:
-    ldr pc, _vector_reset
-    ldr pc, _vector_undef
-    ldr pc, _vector_swi
-    ldr pc, _vector_pabt
-    ldr pc, _vector_dabt
-    ldr pc, _vector_resv
-    ldr pc, _vector_irq
-    ldr pc, _vector_fiq
-
-.globl _reset
-.globl vector_undef
-.globl vector_swi
-.globl vector_pabt
-.globl vector_dabt
-.globl vector_resv
-.globl vector_irq
-.globl vector_fiq
-
-_vector_reset:
-    .word _reset
-_vector_undef:
-    .word vector_undef
-_vector_swi:
-    .word vector_swi
-_vector_pabt:
-    .word vector_pabt
-_vector_dabt:
-    .word vector_dabt
-_vector_resv:
-    .word vector_resv
-_vector_irq:
-    .word vector_irq
-_vector_fiq:
-    .word vector_fiq
-
-.balignl    16,0xdeadbeef
-- 
cgit v1.3.1


From f922bf2e31193768822f68d1e3c1d82ea578ed27 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Wed, 15 Jan 2020 16:46:19 +0800
Subject: Add comment information

---
 libcpu/aarch64/cortex-a53/armv8.h       | 6 +++---
 libcpu/aarch64/cortex-a53/context_gcc.S | 5 +++++
 libcpu/aarch64/cortex-a53/cp15.h        | 2 +-
 libcpu/aarch64/cortex-a53/cpu_gcc.S     | 4 ++++
 libcpu/aarch64/cortex-a53/entry_point.S | 9 +++++++++
 libcpu/aarch64/cortex-a53/interrupt.h   | 9 +++++++++
 libcpu/aarch64/cortex-a53/mmu.c         | 2 +-
 libcpu/aarch64/cortex-a53/mmu.h         | 9 +++++++++
 libcpu/aarch64/cortex-a53/trap.c        | 4 ++++
 libcpu/aarch64/cortex-a53/vector_gcc.S  | 4 ++++
 10 files changed, 49 insertions(+), 5 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/aarch64/cortex-a53/armv8.h b/libcpu/aarch64/cortex-a53/armv8.h
index 28ed50e1ac..4350890544 100644
--- a/libcpu/aarch64/cortex-a53/armv8.h
+++ b/libcpu/aarch64/cortex-a53/armv8.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,8 +8,8 @@
  * 2011-09-15     Bernard      first version
  */
 
-#ifndef __ARMV7_H__
-#define __ARMV7_H__
+#ifndef __ARMV8_H__
+#define __ARMV8_H__
 
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S
index 3812eb4b1a..f58ea1b15d 100644
--- a/libcpu/aarch64/cortex-a53/context_gcc.S
+++ b/libcpu/aarch64/cortex-a53/context_gcc.S
@@ -1,4 +1,9 @@
 /*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
  * Date           Author       Notes
  * 2018-10-06     ZhaoXiaowei    the first version
  */
diff --git a/libcpu/aarch64/cortex-a53/cp15.h b/libcpu/aarch64/cortex-a53/cp15.h
index 26f6ef1a31..91c37d679f 100644
--- a/libcpu/aarch64/cortex-a53/cp15.h
+++ b/libcpu/aarch64/cortex-a53/cp15.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/cortex-a53/cpu_gcc.S b/libcpu/aarch64/cortex-a53/cpu_gcc.S
index ab9a5706ae..b8c8b8768c 100644
--- a/libcpu/aarch64/cortex-a53/cpu_gcc.S
+++ b/libcpu/aarch64/cortex-a53/cpu_gcc.S
@@ -1,4 +1,8 @@
 /*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Date           Author       Notes
  * 2018-10-06     ZhaoXiaowei    the first version
  */
diff --git a/libcpu/aarch64/cortex-a53/entry_point.S b/libcpu/aarch64/cortex-a53/entry_point.S
index 098cd9a840..6d2c69226b 100644
--- a/libcpu/aarch64/cortex-a53/entry_point.S
+++ b/libcpu/aarch64/cortex-a53/entry_point.S
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2020-01-15     bigmagic    the first version
+ */
+
 .section ".text.entrypoint"
 
 .set EL1_stack,         __el1_stack
diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h
index 6e86516045..0c20f79bcc 100644
--- a/libcpu/aarch64/cortex-a53/interrupt.h
+++ b/libcpu/aarch64/cortex-a53/interrupt.h
@@ -1,4 +1,13 @@
 
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __INTERRUPT_H__
 #define __INTERRUPT_H__
 
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
index 17b40c3b47..29934b26a4 100644
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ b/libcpu/aarch64/cortex-a53/mmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
index 022d200f96..5bef609486 100644
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ b/libcpu/aarch64/cortex-a53/mmu.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-01-15     bigmagic     the first version
+ */
 #ifndef MMU_H__
 #define MMU_H__
 #include <rtthread.h>
diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c
index aa639ea596..13ae6d1b9e 100644
--- a/libcpu/aarch64/cortex-a53/trap.c
+++ b/libcpu/aarch64/cortex-a53/trap.c
@@ -1,4 +1,8 @@
 /*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
  * Date           Author       Notes
  * 2018-10-06     ZhaoXiaowei    the first version
  */
diff --git a/libcpu/aarch64/cortex-a53/vector_gcc.S b/libcpu/aarch64/cortex-a53/vector_gcc.S
index 0efbf4e540..fc88cce7f8 100644
--- a/libcpu/aarch64/cortex-a53/vector_gcc.S
+++ b/libcpu/aarch64/cortex-a53/vector_gcc.S
@@ -1,4 +1,8 @@
 /*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Date           Author       Notes
  * 2018-10-06     ZhaoXiaowei    the first version
  */
-- 
cgit v1.3.1


From fe24ae7ca422a735f22fedb6ac03150ba49401a7 Mon Sep 17 00:00:00 2001
From: Watson Zeng <zhiwei@synopsys.com>
Date: Thu, 16 Jan 2020 16:00:13 +0800
Subject: [bsp][synopsys] add basic new embarc bsp support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* the initial support of synopsys designware ARC processor
  using embARC_BSP, all synopsys ARC-based boards are
  supported:
  -ARC Software Development Platform
  -ARC EM Starter Kit
  -ARC EM Software Development Platform
  -ARC HS Development Kit
  -ARC IoT Development Kit

* The embARC BSP is a new generation embARC software development
  package.  ​It is designed to be the inter-layer between hardware and
  operating system. ​ BSP could hide the difference of hardware/boards,
  provide a unified interface to upper-layer.

* the initial support of synopsys MWDT toolchain.
  The DesignWare® ARC® MetaWare Development Toolkit builds upon
  a 25-year legacy of industry-leading compiler and debugger products.
  It is a complete solution that contains all the components needed to
  support the development, debugging and tuning of embedded applications
  for the DesignWare ARC processors.

* for detailed board information, pls go embarc.org.

Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
---
 bsp/synopsys/boards/.config                        |  397 +++++
 bsp/synopsys/boards/Kconfig                        |   29 +
 bsp/synopsys/boards/README.md                      |  128 ++
 bsp/synopsys/boards/SConscript                     |   17 +
 bsp/synopsys/boards/SConstruct                     |  325 ++++
 bsp/synopsys/boards/applications/SConscript        |   11 +
 bsp/synopsys/boards/applications/application.c     |   29 +
 bsp/synopsys/boards/applications/startup.c         |   76 +
 bsp/synopsys/boards/drivers/Kconfig                |   10 +
 bsp/synopsys/boards/drivers/SConscript             |   15 +
 bsp/synopsys/boards/drivers/rt_board.c             |  324 ++++
 bsp/synopsys/boards/drivers/rt_board.h             |   16 +
 bsp/synopsys/boards/linker_template_gnu.ld         |  169 +++
 bsp/synopsys/boards/linker_template_mw.ld          |  154 ++
 bsp/synopsys/boards/rtconfig.h                     |  157 ++
 bsp/synopsys/boards/rtconfig.py                    |   58 +
 bsp/synopsys/embarc/SConscript                     |   28 -
 bsp/synopsys/embarc/arc/arc_cache.c                |  420 ------
 bsp/synopsys/embarc/arc/arc_exc_asm.S              |  201 ---
 bsp/synopsys/embarc/arc/arc_exception.c            |  501 -------
 bsp/synopsys/embarc/arc/arc_timer.c                |  211 ---
 bsp/synopsys/embarc/arc/startup/arc_cxx_support.c  |  168 ---
 bsp/synopsys/embarc/arc/startup/arc_startup.S      |  262 ----
 .../embarc/device/designware/gpio/dw_gpio.c        |  481 ------
 .../embarc/device/designware/gpio/dw_gpio.h        |  145 --
 bsp/synopsys/embarc/device/designware/iic/dw_iic.c | 1584 --------------------
 bsp/synopsys/embarc/device/designware/iic/dw_iic.h |  242 ---
 .../embarc/device/designware/iic/dw_iic_hal.h      |  186 ---
 .../embarc/device/designware/iic/dw_iic_hal_cfg.h  |   82 -
 bsp/synopsys/embarc/device/designware/spi/dw_spi.c | 1337 -----------------
 bsp/synopsys/embarc/device/designware/spi/dw_spi.h |  190 ---
 .../embarc/device/designware/spi/dw_spi_hal.h      |  141 --
 .../embarc/device/designware/spi/dw_spi_hal_cfg.h  |   58 -
 .../embarc/device/designware/uart/dw_uart.c        |  956 ------------
 .../embarc/device/designware/uart/dw_uart.h        |  141 --
 .../embarc/device/designware/uart/dw_uart_hal.h    |  253 ----
 .../embarc/device/device_hal/inc/dev_common.h      |  173 ---
 .../embarc/device/device_hal/inc/dev_gpio.h        |  424 ------
 .../embarc/device/device_hal/inc/dev_iic.h         |  526 -------
 .../embarc/device/device_hal/inc/dev_spi.h         |  577 -------
 .../embarc/device/device_hal/inc/dev_uart.h        |  475 ------
 bsp/synopsys/embarc/inc/arc/arc.h                  |  436 ------
 bsp/synopsys/embarc/inc/arc/arc_asm_common.h       |  541 -------
 bsp/synopsys/embarc/inc/arc/arc_builtin.h          |  301 ----
 bsp/synopsys/embarc/inc/arc/arc_cache.h            |  321 ----
 bsp/synopsys/embarc/inc/arc/arc_em.h               |  133 --
 bsp/synopsys/embarc/inc/arc/arc_exception.h        |  461 ------
 bsp/synopsys/embarc/inc/arc/arc_feature_config.h   |  397 -----
 bsp/synopsys/embarc/inc/arc/arc_timer.h            |   99 --
 bsp/synopsys/embarc/inc/embARC_debug.h             |   94 --
 bsp/synopsys/embarc/inc/embARC_error.h             |  156 --
 bsp/synopsys/embarc/inc/embARC_toolchain.h         |  121 --
 bsp/synopsys/emsk_em9d/.config                     |  403 -----
 bsp/synopsys/emsk_em9d/Kconfig                     |   28 -
 bsp/synopsys/emsk_em9d/README.md                   |   77 -
 bsp/synopsys/emsk_em9d/SConscript                  |   18 -
 bsp/synopsys/emsk_em9d/SConstruct                  |   53 -
 bsp/synopsys/emsk_em9d/applications/SConscript     |   11 -
 bsp/synopsys/emsk_em9d/applications/application.c  |   29 -
 bsp/synopsys/emsk_em9d/applications/startup.c      |   71 -
 bsp/synopsys/emsk_em9d/drivers/Kconfig             |   10 -
 bsp/synopsys/emsk_em9d/drivers/SConscript          |   15 -
 bsp/synopsys/emsk_em9d/drivers/arc_core_config.h   |  229 ---
 bsp/synopsys/emsk_em9d/drivers/board.c             |  283 ----
 bsp/synopsys/emsk_em9d/drivers/board.h             |   28 -
 bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c       |  324 ----
 bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h       |   51 -
 bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c       |  210 ---
 bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h       |   52 -
 bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h |   39 -
 bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h     |   85 --
 bsp/synopsys/emsk_em9d/drivers/mux.c               |   67 -
 bsp/synopsys/emsk_em9d/drivers/mux.h               |  147 --
 bsp/synopsys/emsk_em9d/drivers/mux_hal.h           |   29 -
 bsp/synopsys/emsk_em9d/emsk_em9d.ld                |  114 --
 bsp/synopsys/emsk_em9d/figures/emsk_board.jpg      |  Bin 483486 -> 0 bytes
 bsp/synopsys/emsk_em9d/openocd.log                 |    9 -
 bsp/synopsys/emsk_em9d/rtconfig.h                  |  143 --
 bsp/synopsys/emsk_em9d/rtconfig.py                 |   60 -
 libcpu/arc/em/SConscript                           |    4 +-
 libcpu/arc/em/contex_gcc.S                         |  266 ----
 libcpu/arc/em/contex_gcc_mw.S                      |  364 +++++
 libcpu/arc/em/cpuport.c                            |   28 +-
 83 files changed, 2303 insertions(+), 15681 deletions(-)
 create mode 100644 bsp/synopsys/boards/.config
 create mode 100644 bsp/synopsys/boards/Kconfig
 create mode 100644 bsp/synopsys/boards/README.md
 create mode 100644 bsp/synopsys/boards/SConscript
 create mode 100644 bsp/synopsys/boards/SConstruct
 create mode 100644 bsp/synopsys/boards/applications/SConscript
 create mode 100644 bsp/synopsys/boards/applications/application.c
 create mode 100644 bsp/synopsys/boards/applications/startup.c
 create mode 100644 bsp/synopsys/boards/drivers/Kconfig
 create mode 100644 bsp/synopsys/boards/drivers/SConscript
 create mode 100644 bsp/synopsys/boards/drivers/rt_board.c
 create mode 100644 bsp/synopsys/boards/drivers/rt_board.h
 create mode 100644 bsp/synopsys/boards/linker_template_gnu.ld
 create mode 100644 bsp/synopsys/boards/linker_template_mw.ld
 create mode 100644 bsp/synopsys/boards/rtconfig.h
 create mode 100644 bsp/synopsys/boards/rtconfig.py
 delete mode 100644 bsp/synopsys/embarc/SConscript
 delete mode 100644 bsp/synopsys/embarc/arc/arc_cache.c
 delete mode 100644 bsp/synopsys/embarc/arc/arc_exc_asm.S
 delete mode 100644 bsp/synopsys/embarc/arc/arc_exception.c
 delete mode 100644 bsp/synopsys/embarc/arc/arc_timer.c
 delete mode 100644 bsp/synopsys/embarc/arc/startup/arc_cxx_support.c
 delete mode 100644 bsp/synopsys/embarc/arc/startup/arc_startup.S
 delete mode 100644 bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c
 delete mode 100644 bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h
 delete mode 100644 bsp/synopsys/embarc/device/designware/iic/dw_iic.c
 delete mode 100644 bsp/synopsys/embarc/device/designware/iic/dw_iic.h
 delete mode 100644 bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h
 delete mode 100644 bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h
 delete mode 100644 bsp/synopsys/embarc/device/designware/spi/dw_spi.c
 delete mode 100644 bsp/synopsys/embarc/device/designware/spi/dw_spi.h
 delete mode 100644 bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h
 delete mode 100644 bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h
 delete mode 100644 bsp/synopsys/embarc/device/designware/uart/dw_uart.c
 delete mode 100644 bsp/synopsys/embarc/device/designware/uart/dw_uart.h
 delete mode 100644 bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h
 delete mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_common.h
 delete mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h
 delete mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h
 delete mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h
 delete mode 100644 bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h
 delete mode 100644 bsp/synopsys/embarc/inc/arc/arc.h
 delete mode 100644 bsp/synopsys/embarc/inc/arc/arc_asm_common.h
 delete mode 100644 bsp/synopsys/embarc/inc/arc/arc_builtin.h
 delete mode 100644 bsp/synopsys/embarc/inc/arc/arc_cache.h
 delete mode 100644 bsp/synopsys/embarc/inc/arc/arc_em.h
 delete mode 100644 bsp/synopsys/embarc/inc/arc/arc_exception.h
 delete mode 100644 bsp/synopsys/embarc/inc/arc/arc_feature_config.h
 delete mode 100644 bsp/synopsys/embarc/inc/arc/arc_timer.h
 delete mode 100644 bsp/synopsys/embarc/inc/embARC_debug.h
 delete mode 100644 bsp/synopsys/embarc/inc/embARC_error.h
 delete mode 100644 bsp/synopsys/embarc/inc/embARC_toolchain.h
 delete mode 100644 bsp/synopsys/emsk_em9d/.config
 delete mode 100644 bsp/synopsys/emsk_em9d/Kconfig
 delete mode 100644 bsp/synopsys/emsk_em9d/README.md
 delete mode 100644 bsp/synopsys/emsk_em9d/SConscript
 delete mode 100644 bsp/synopsys/emsk_em9d/SConstruct
 delete mode 100644 bsp/synopsys/emsk_em9d/applications/SConscript
 delete mode 100644 bsp/synopsys/emsk_em9d/applications/application.c
 delete mode 100644 bsp/synopsys/emsk_em9d/applications/startup.c
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/Kconfig
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/SConscript
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/arc_core_config.h
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/board.c
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/board.h
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/mux.c
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/mux.h
 delete mode 100644 bsp/synopsys/emsk_em9d/drivers/mux_hal.h
 delete mode 100644 bsp/synopsys/emsk_em9d/emsk_em9d.ld
 delete mode 100644 bsp/synopsys/emsk_em9d/figures/emsk_board.jpg
 delete mode 100644 bsp/synopsys/emsk_em9d/openocd.log
 delete mode 100644 bsp/synopsys/emsk_em9d/rtconfig.h
 delete mode 100644 bsp/synopsys/emsk_em9d/rtconfig.py
 delete mode 100644 libcpu/arc/em/contex_gcc.S
 create mode 100644 libcpu/arc/em/contex_gcc_mw.S

(limited to 'libcpu')

diff --git a/bsp/synopsys/boards/.config b/bsp/synopsys/boards/.config
new file mode 100644
index 0000000000..6ae650f8cc
--- /dev/null
+++ b/bsp/synopsys/boards/.config
@@ -0,0 +1,397 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+CONFIG_RT_DEBUG_INIT_CONFIG=y
+CONFIG_RT_DEBUG_INIT=1
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40002
+CONFIG_RT_USING_CPU_FFS=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+# CONFIG_RT_USING_USER_MAIN is not set
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=1024
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=8
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=1024
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+CONFIG_PKG_USING_EMBARC_BSP=y
+CONFIG_PKG_EMBARC_BSP_PATH="/packages/system/embARC_bsp"
+CONFIG_PKG_USING_EMBARC_BSP_UPSTREAM_VERSION=y
+# CONFIG_PKG_USING_EMBARC_BSP_MASTER_VERSION is not set
+CONFIG_PKG_EMBARC_BSP_VER="upstream"
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_SOC_EMSK=y
+CONFIG_EMSK_USING_UART0=y
+CONFIG_EMSK_USING_UART1=y
diff --git a/bsp/synopsys/boards/Kconfig b/bsp/synopsys/boards/Kconfig
new file mode 100644
index 0000000000..cfab678244
--- /dev/null
+++ b/bsp/synopsys/boards/Kconfig
@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_EMSK
+    bool
+    select ARCH_ARC_EM
+    select RT_USING_COMPONENTS_INIT
+    # select RT_USING_USER_MAIN
+    select RT_USING_CPU_FFS
+    default y
+
+source "$BSP_DIR/drivers/Kconfig"
diff --git a/bsp/synopsys/boards/README.md b/bsp/synopsys/boards/README.md
new file mode 100644
index 0000000000..aee6059cfc
--- /dev/null
+++ b/bsp/synopsys/boards/README.md
@@ -0,0 +1,128 @@
+# Synopsys ARC Boards support with embARC_BSP
+
+## embARC_BSP
+
+The embARC Board support Package (BSP) is a software distributions aimed at facilitating
+the development and evaluation of embedded systems based on ARCv2 processors, which is
+designed to provide a minimal board support package for ARC users by defining
+consistent and simple software interfaces to the processors and onboard devices.
+
+The embARC BSP is a new generation embARC software development package. ​
+It is designed to be the inter-layer between hardware and operating system. ​
+BSP could hide the difference of hardware/boards, provide a unified interface to upper-layer. ​
+In the scenarios that no OS is required, embARC BSP can also standalone and work in baremetal.
+
+embARC_BSP features:
+
+* Support MetaWare & GNU toolchains​
+* Support all development boards and tcf​
+* Support various build systems and compiling environments,
+  such as ARC MetaWare & GNU IDE, makefile​
+* Designware and Subsystem drivers, including UART and GPIO, I2C, SPI, etc. ​
+* No middleware, no OS​
+* Easy to port to different platform / OS​
+* One example (UART, GPIO, timer)​
+* Code coverage reach 100% in test. ​
+* MISRA-C compliance​
+* C & C++ support, assembly support
+
+## Supported Boards
+
+* [ARC Software Development Platform](https://www.synopsys.com/dw/ipdir.php?ds=arc-software-development-platform)
+* [ARC EM Starter Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit)
+* [ARC EM Software Development Platform](https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform)
+* [ARC HS Development Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit)
+* [ARC IoT Development Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit)
+
+
+## Software Requirement
+
+### embarc_bsp
+
+There are two ways to get embarc_bsp:
+
+#### use RT-Thread ENV tool:
+
+embARC_BSP has been configured as package module, you can just run the command `pkgs --update` in <RTT_ROOT>/bsp/synopsys/boards
+folder using ENV tool.
+
+#### without RT-Thread ENV tool:
+
+We can get it from github: [embarc_bsp](https://github.com/foss-for-synopsys-dwc-arc-processors)
+
+The default path for embarc_bsp is <RTT_ROOT>/bsp/synopsys/boards/packages/embARC_bsp-upstream,
+when you use other path, please set the environment variable `EMBARC_BSP_ROOT`.
+
+### Toolchain
+
+Now both GNU and MetaWare Toolchain are supported, set the System environment variable RTT_CC select the toolchain.
+
+GNU:
+
+    set RTT_CC=gnu
+
+MetaWare:
+
+    set RTT_CC=mw
+
+#### GNU
+
+The ARC GNU Toolchain offers all of the benefits of open source tools, including complete source code and a large install base. The ARC GNU IDE Installer consists of Eclipse IDE with [ARC GNU plugin for Eclipse](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/releases), [ARC GNU prebuilt toolchain](https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases) and [OpenOCD for ARC](https://github.com/foss-for-synopsys-dwc-arc-processors/openocd>)
+
+Here, the ARC GNU toolchain is installed to `c:\arc_gnu`. If not, please change the path configuration in rtconfig.py.
+
+When you use GNU Toolchain, you need to install [Zadig](http://zadig.akeo.ie) to replace the default FTDI driver with WinUSB driver. See [How to Use OpenOCD on Windows](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/wiki/How-to-Use-OpenOCD-on-Windows>) for more information.
+
+#### MetaWare
+The [DesignWare ARC MetaWare Development Toolkit](https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware) builds on a long legacy of industry-leading compiler and debugger products for embedded applications. It is a complete solution that contains all the components needed to support the development, debugging, and tuning of embedded applications for the DesignWare® ARC® processors.
+
+Here, the ARC MetaWare toolchain is installed to `C:\ARC\MetaWare`. If not, please change the path configuration in rtconfig.py.
+
+
+
+
+
+## Build & Debug
+
+### Build embarc_lib
+
+please run the following cmds to build embarc_lib
+
+    cd <rt-thread-root>/bsp/synopsys/boards
+    scons --embarc_build
+
+### Build
+
+please run the following cmds to build
+
+    cd <rt-thread-root>/bsp/synopsys/boards
+    scons
+
+### Debug
+
+After compile, please use the following cmds to debug
+
+    scons --gdb #use gdb debugger
+    scons --mdb #use mdb debugger
+
+
+### How to choose different boards
+
+There are some parameters we can use in scons, for example:
+
+    scons --BOARD=emsk --BD_VER=23 --CUR_CORE=arcem9d --TOOLCHAIN=mw --OLEVEL=O2
+
+ * BOARD: choose the board, we can set: `emsk, iotdk, emsdp, hsdk, axs`.
+ * BD_VER: choose the board version, some boards have different versions, for example,
+   we can set: `10, 22, 23` for emsk board.
+ * CUR_CORE: choose the arc cores, some boards have different cores, for example,
+   we can set: `arcem7d, arcem9d, arcem11d` for emsk board.
+ * TOOLCHAIN: choose the toolchain to build embarc_lib, we can set: `mw, gnu`.
+ * OLEVEL: choose the build optimize level, we can set: `O0, O2, Os`.
+
+For more information, you can run the command `scons -h`.
+
+
+## Maintainer
+- [vonhust](https://github.com/vonhust)
+- [IRISZZW](https://github.com/IRISZZW)
diff --git a/bsp/synopsys/boards/SConscript b/bsp/synopsys/boards/SConscript
new file mode 100644
index 0000000000..2e95f4716c
--- /dev/null
+++ b/bsp/synopsys/boards/SConscript
@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/synopsys/boards/SConstruct b/bsp/synopsys/boards/SConstruct
new file mode 100644
index 0000000000..a66e7ec76a
--- /dev/null
+++ b/bsp/synopsys/boards/SConstruct
@@ -0,0 +1,325 @@
+import os
+import sys
+
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+
+
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+if os.getenv('EMBARC_BSP_ROOT'):
+    EMBARC_BSP_ROOT = os.getenv('EMBARC_BSP_ROOT')
+else:
+    EMBARC_BSP_ROOT = RTT_ROOT + '/bsp/synopsys/boards/packages/embARC_bsp-upstream'
+
+if not os.path.isdir(EMBARC_BSP_ROOT):
+    print('Cannot found embarc_bsp root directory, please check EMBARC_BSP_ROOT')
+    print(EMBARC_BSP_ROOT)
+    exit(-1)
+
+SUPPORTED_BOARD_DIR = EMBARC_BSP_ROOT + '/board'
+SUPPORTED_BOARD = [d for d in os.listdir(SUPPORTED_BOARD_DIR) if os.path.isdir(os.path.join(SUPPORTED_BOARD_DIR,d))]
+print 'supported BOARD = ' + str(SUPPORTED_BOARD)
+
+AddOption('--BOARD',
+        dest = 'BOARD',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = 'emsk',
+        help = 'select board')
+
+AddOption('--BD_VER',
+        dest = 'BD_VER',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = '23',
+        help = 'select bd_ver')
+
+AddOption('--CUR_CORE',
+        dest = 'CUR_CORE',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = 'arcem9d',
+        help = 'select cur_core')
+
+AddOption('--TOOLCHAIN',
+        dest = 'TOOLCHAIN',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = 'gnu',
+        help = 'select toolchain')
+
+AddOption('--OLEVEL',
+        dest = 'OLEVEL',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = 'O2',
+        help = 'select optimize level')
+
+AddOption('--mdb',
+        dest = 'mdb',
+        action = 'store_true',
+        default = False,
+        help = 'use mdb to debug the elf')
+
+AddOption('--gdb',
+        dest = 'gdb',
+        action = 'store_true',
+        default = False,
+        help = 'use gdb to debug the elf')
+
+AddOption('--embarc_build',
+        dest = 'embarc_build',
+        action = 'store_true',
+        default = False,
+        help = 'to generate embarc_lib')
+
+AddOption('--embarc_clean',
+        dest = 'embarc_clean',
+        action = 'store_true',
+        default = False,
+        help = 'to clean embarc_lib')
+
+if GetOption('BOARD'):
+    board = GetOption('BOARD')
+    if board not in SUPPORTED_BOARD:
+        print 'board %s not supported, available boards:' % board
+        print SUPPORTED_BOARD
+        exit(0)
+    else:
+        BOARD = board
+        print 'get BOARD = [%s]' % board
+
+if BOARD == 'emsdp':
+    SUPPORTED_BD_VER = ['rev2']
+else:
+    SUPPORTED_BD_VER_DIR = SUPPORTED_BOARD_DIR + '/' + BOARD + '/configs'
+    SUPPORTED_BD_VER = [d for d in os.listdir(SUPPORTED_BD_VER_DIR) if os.path.isdir(os.path.join(SUPPORTED_BD_VER_DIR,d))]
+print 'supported BD_VER = ' + str(SUPPORTED_BD_VER)
+
+if GetOption('BD_VER'):
+    bd_ver = GetOption('BD_VER')
+    if bd_ver not in SUPPORTED_BD_VER:
+        print 'bd_ver %s not supported, available bd_ver:' % bd_ver
+        print SUPPORTED_BD_VER
+        exit(0)
+    else:
+        BD_VER = bd_ver
+        print 'get BD_VER = [%s]' % BD_VER
+
+if BOARD == 'emsdp':
+    SUPPORTED_CORE_DIR = SUPPORTED_BOARD_DIR + '/' + BOARD + '/rev2/configs'
+    SUPPORTED_CORE = [d for d in os.listdir(SUPPORTED_CORE_DIR) if os.path.isdir(os.path.join(SUPPORTED_CORE_DIR,d))]
+else:
+    SUPPORTED_CORE_DIR = SUPPORTED_BD_VER_DIR + '/' + BD_VER + '/tcf'
+    SUPPORTED_CORE = [os.path.splitext(d)[0] for d in os.listdir(SUPPORTED_CORE_DIR)]
+
+print 'supported CUR_CORE = ' + str(SUPPORTED_CORE)
+
+if GetOption('CUR_CORE'):
+    cur_core = GetOption('CUR_CORE')
+    if cur_core not in SUPPORTED_CORE:
+        print 'cur_core %s not supported, available cur_core:' % cur_core
+        print SUPPORTED_CORE
+        exit(0)
+    else:
+        CUR_CORE = cur_core
+        print 'get CUR_CORE = [%s]' % CUR_CORE
+
+SUPPORTED_TOOLCHAIN = ['mw', 'gnu']
+
+print 'supported TOOLCHAIN = ' + str(SUPPORTED_TOOLCHAIN)
+
+if GetOption('TOOLCHAIN'):
+    toolchain = GetOption('TOOLCHAIN')
+    if toolchain not in SUPPORTED_TOOLCHAIN:
+        print 'toolchain %s not supported, available toolchain:' % toolchain
+        print SUPPORTED_TOOLCHAIN
+        exit(0)
+    else:
+        TOOLCHAIN = toolchain
+        print 'get TOOLCHAIN = [%s]' % TOOLCHAIN
+
+SUPPORTED_OLEVEL = ['O0', 'O2', 'Os']
+
+print 'supported OLEVEL = ' + str(SUPPORTED_OLEVEL)
+
+if GetOption('OLEVEL'):
+    olevel = GetOption('OLEVEL')
+    if olevel not in SUPPORTED_OLEVEL:
+        print 'olevel %s not supported, available olevel:' % toolchain
+        print SUPPORTED_OLEVEL
+        exit(0)
+    else:
+        OLEVEL = olevel
+        print 'get OLEVEL = [%s]' % olevel
+
+
+
+EMBARC_LIB_PATH = EMBARC_BSP_ROOT + '/obj_%s_%s/%s_%s'%(BOARD, BD_VER, TOOLCHAIN, CUR_CORE)
+# print 'EMBARC_LIB_PATH = %s'%EMBARC_LIB_PATH
+
+TARGET = 'rtthread_snps_embarc.elf'
+# print 'TARGET = %s'%TARGET
+
+# ip_ph_dir = EMBARC_BSP_ROOT + '/device/peripheral'
+# ip_ph_path = [os.path.join(ip_ph_dir,d) for d in os.listdir(ip_ph_dir) if os.path.isdir(os.path.join(ip_ph_dir,d))]
+
+if BOARD == 'emsdp':
+    board_inc_path = [SUPPORTED_CORE_DIR, SUPPORTED_CORE_DIR + '/%s/include'%CUR_CORE]
+else:
+    board_inc_path = [EMBARC_BSP_ROOT + '/board/%s/configs/%s'%(BOARD, BD_VER)]
+
+# print 'board_inc_path = %s' % board_inc_path
+# print 'ip_dw_path = %s' % ip_dw_path
+# print 'ip_ss_path = %s' % ip_ss_path
+# print 'ip_ph_path = %s' % ip_ph_path
+
+EMBARC_CPPPATH = [  EMBARC_BSP_ROOT,
+                    EMBARC_BSP_ROOT + '/include',
+                    EMBARC_BSP_ROOT + '/board',
+                    EMBARC_LIB_PATH + '/embARC_generated',
+                 ] + board_inc_path
+#print "EMBARC_CPPPATH: %s"%EMBARC_CPPPATH
+
+if TOOLCHAIN == 'mw':
+    EXEC_PATH 	= 'C:/ARC/MetaWare/arc/bin'
+    MAKE = 'gmake'
+    PREFIX = ''
+    CC = 'ccac'
+    CXX = 'ccac'
+    AS = 'ccac'
+    AR = 'arac'
+    LINK = 'ccac'
+    TARGET_EXT = 'elf'
+    SIZE = 'sizeac'
+    OBJDUMP = 'elfdumpac'
+    OBJCPY = 'elf2bin'
+    DBG = 'mdb'
+
+    OPT_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/ccac.arg '
+    MDB_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/mdb.arg '
+    COMMON_COMPILE_OPT = ' -Hnoccm -Hnosdata -Wincompatible-pointer-types -Hnocopyr -Hpurge -fdata-sections -g -%s '%(OLEVEL)
+    COMMON_DEFINES = ' -DBOARD_%s -D__MW__ -DEMBARC_TCF_GENERATED ' % BOARD.upper()
+
+    CFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -Hnocplus '
+    CXXFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES
+    AFLAGS = ' -c' + OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -Hasmcpp -I%s -I%s/embARC_generated -I%s/include '%(EMBARC_BSP_ROOT, EMBARC_LIB_PATH, EMBARC_BSP_ROOT)
+
+    LINKER_SCRIPT_FILE = RTT_ROOT + '/bsp/synopsys/boards/linker_template_mw.ld'
+    LINK_SCRIPT = EMBARC_LIB_PATH + '/linker_mw.ldf'
+
+    LFLAGS = ' -Hhostlink ' + OPT_ARG_FILE + ' -Hnocopyr -Hnosdata -Hnocrt -Hldopt=-Coutput=rtthread_snps_embarc.map -Hldopt=-Csections -Hldopt=-Ccrossfunc -Hldopt=-Csize -zstdout %s' % LINK_SCRIPT
+
+elif TOOLCHAIN == 'gnu':
+    EXEC_PATH 	= 'C:/arc_gnu/bin'
+    MAKE = 'make'
+    PREFIX = 'arc-elf32-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    DBG = PREFIX + 'gdb'
+
+    OPT_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/gcc.arg '
+    MDB_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/mdb.arg '
+    COMMON_COMPILE_OPT = ' -ffunction-sections -fdata-sections -mno-sdata -g -%s '%(OLEVEL)
+    COMMON_DEFINES = ' -DBOARD_%s -D__GNU__ -DEMBARC_TCF_GENERATED ' % BOARD.upper()
+
+    CFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -std=gnu99 '
+    CXXFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES
+    AFLAGS = ' -c ' + OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -x assembler-with-cpp -I%s -I%s/embARC_generated -I%s/include '%(EMBARC_BSP_ROOT, EMBARC_LIB_PATH, EMBARC_BSP_ROOT)
+
+    LINKER_SCRIPT_FILE = RTT_ROOT + '/bsp/synopsys/boards/linker_template_gnu.ld'
+    LINK_SCRIPT = EMBARC_LIB_PATH + '/linker_gnu.ldf'
+
+    LFLAGS = ' --specs=nsim.specs ' + OPT_ARG_FILE + ' -mno-sdata -nostartfiles -Wl,--gc-sections,-Map=rtthread_snps_embarc.map,-cref,-u,system_vectors -T %s ' % LINK_SCRIPT
+
+    OPENOCD_SCRIPT_ROOT = EXEC_PATH + '/../share/openocd/scripts'
+    OPENOCD_CFG_FILE = OPENOCD_SCRIPT_ROOT + '/board/snps_em_sk_v2.2.cfg'
+
+    OPENOCD_OPTIONS  = '-s %s -f %s' % (OPENOCD_SCRIPT_ROOT, OPENOCD_CFG_FILE)
+
+    DBG_HW_FLAGS = ''' -ex "target remote | openocd --pipe %s" -ex "load" ''' % OPENOCD_OPTIONS
+
+else :
+    print 'TOOLCHAIN %s is not supported, available toolchain:' % TOOLCHAIN
+    print SUPPORTED_TOOLCHAIN
+    exit(-1)
+
+env = Environment(ENV = os.environ, tools = ['mingw'],
+        AS = AS, ASFLAGS = AFLAGS,
+        CC = CC, CCFLAGS = CFLAGS,
+        AR = AR, ARFLAGS = '-rc',
+        LINK = LINK, LINKFLAGS = LFLAGS,
+        LIBS = ['embarc'], LIBPATH = EMBARC_LIB_PATH,
+        CPPPATH = EMBARC_CPPPATH
+        )
+env.PrependENVPath('PATH', EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+embarc_cd_cmd = ' cd %s '%EMBARC_BSP_ROOT
+embarc_make_cmd = ' %s -f options/options.mk BOARD=%s BD_VER=%s CUR_CORE=%s TOOLCHAIN=%s V=1 OLEVEL=%s LINKER_SCRIPT_FILE=%s embarc_lib '%(MAKE,BOARD, BD_VER, CUR_CORE, TOOLCHAIN, OLEVEL, LINKER_SCRIPT_FILE)
+embarc_clean_cmd = ' %s -f options/options.mk distclean '%MAKE
+
+if GetOption('embarc_build'):
+    print 'os.system: ' + embarc_cd_cmd + ' && ' + embarc_make_cmd
+    os.system(embarc_cd_cmd + ' && ' + embarc_make_cmd)
+    exit(0)
+
+if GetOption('embarc_clean'):
+    os.system(embarc_cd_cmd + ' && ' + embarc_clean_cmd)
+    exit(0)
+
+if GetOption('gdb'):
+    if os.path.isfile(TARGET):
+        os.system(DBG + DBG_HW_FLAGS + TARGET)
+    else:
+        print TARGET + 'not exist, please build first!!'
+    exit(0)
+
+if GetOption('mdb'):
+    if os.path.isfile(TARGET):
+        startup_path = EMBARC_BSP_ROOT + '/arc/startup'
+        if BOARD == 'nsim':
+            os.system('mdb -source_path=%s -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim -off=binary_stdin -off=binary_stdout \
+            -on=load_at_paddr -on=reset_upon_restart -off=flush_pipe -off=cr_for_more -OKN %s '%(startup_path, MDB_ARG_FILE) + rtconfig.TARGET)
+        else:
+            os.system('mdb -source_path=%s -nooptions -nogoifmain -toggle=include_local_symbols=1 -hard -digilent '%startup_path + rtconfig.TARGET)
+    else:
+        print TARGET + 'not exist, please build first!!'
+    exit(0)
+
+# os.system(embarc_cd_cmd + ' && ' + embarc_make_cmd)
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# if the linker script changed, relink the target
+Depends(TARGET, LINK_SCRIPT)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/synopsys/boards/applications/SConscript b/bsp/synopsys/boards/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/synopsys/boards/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/synopsys/boards/applications/application.c b/bsp/synopsys/boards/applications/application.c
new file mode 100644
index 0000000000..3e12c0ba76
--- /dev/null
+++ b/bsp/synopsys/boards/applications/application.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rtthread.h>
+
+/* thread phase init */
+static void rt_init_thread_entry(void *parameter)
+{
+    /* do component initialization */
+    rt_components_init();
+
+    /* add your initialization here */
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048,
+                            RT_THREAD_PRIORITY_MAX/3, 20);
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+
+    return 0;
+}
+
diff --git a/bsp/synopsys/boards/applications/startup.c b/bsp/synopsys/boards/applications/startup.c
new file mode 100644
index 0000000000..817bf74c9a
--- /dev/null
+++ b/bsp/synopsys/boards/applications/startup.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <rt_board.h>
+
+#ifdef RT_USING_HEAP
+#define rt_system_heap_size 1024*64
+static rt_uint32_t rt_system_heap[rt_system_heap_size/4] = {0};
+#endif
+
+extern int rt_application_init(void);
+
+void rt_hw_interrupt_init(void)
+{
+    /* rt-thread specific interrupt and exception init */
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
+
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show RT-Thread version */
+    rt_show_version();
+
+    /* initialize memory system */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)rt_system_heap, (void *)(rt_system_heap+rt_system_heap_size));
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize system timer */
+    rt_system_timer_init();
+
+    /* initialize soft timer thread */
+    rt_system_timer_thread_init();
+
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* invoke rtthread_startup */
+    rtthread_startup();
+
+    return 0;
+}
+
diff --git a/bsp/synopsys/boards/drivers/Kconfig b/bsp/synopsys/boards/drivers/Kconfig
new file mode 100644
index 0000000000..3cc4d3470d
--- /dev/null
+++ b/bsp/synopsys/boards/drivers/Kconfig
@@ -0,0 +1,10 @@
+
+config EMSK_USING_UART0
+    bool "Using UART0"
+    select RT_USING_SERIAL
+    default y
+
+config EMSK_USING_UART1
+    bool "Using UART1"
+    select RT_USING_SERIAL
+    default y
\ No newline at end of file
diff --git a/bsp/synopsys/boards/drivers/SConscript b/bsp/synopsys/boards/drivers/SConscript
new file mode 100644
index 0000000000..29272aa88e
--- /dev/null
+++ b/bsp/synopsys/boards/drivers/SConscript
@@ -0,0 +1,15 @@
+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+ASFLAGS = ' -I' + cwd
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/bsp/synopsys/boards/drivers/rt_board.c b/bsp/synopsys/boards/drivers/rt_board.c
new file mode 100644
index 0000000000..1e1b7e494b
--- /dev/null
+++ b/bsp/synopsys/boards/drivers/rt_board.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <rtdevice.h>
+#include <drivers/serial.h>
+
+#include "rt_board.h"
+#include "arc/arc_timer.h"
+#include "arc/arc_exception.h"
+
+#include "embARC_error.h"
+
+static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    DEV_UART_PTR uart;
+    unsigned int id;
+    int ret;
+
+    id = (unsigned int)(serial->parent.user_data);
+
+    uart = uart_get_dev(id);
+
+    ret = uart->uart_control(UART_CMD_SET_BAUD, (void *)(cfg->baud_rate));
+
+    if (ret != E_OK) {
+        return RT_ERROR;
+    }
+
+
+    return RT_EOK;
+}
+
+static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    DEV_UART_PTR uart;
+    unsigned int id;
+
+    id = (unsigned int)(serial->parent.user_data);
+    uart = uart_get_dev(id);
+
+    switch (cmd) {
+        case RT_DEVICE_CTRL_CLR_INT:
+            uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
+            break;
+        case RT_DEVICE_CTRL_SET_INT:
+            uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
+            break;
+        case RT_DEVICE_CTRL_SUSPEND:
+            uart->uart_control(UART_CMD_DIS_DEV, (void *)0);
+            break;
+        case RT_DEVICE_CTRL_RESUME:
+            uart->uart_control(UART_CMD_ENA_DEV, (void *)0);
+            break;
+
+        default:
+            return  RT_ERROR;
+            break;
+    }
+
+    return RT_EOK;
+}
+
+static int _putc(struct rt_serial_device *serial, char c)
+{
+    DEV_UART_PTR uart;
+    unsigned int id;
+    int ret;
+
+    id = (unsigned int)(serial->parent.user_data);
+
+    uart = uart_get_dev(id);
+
+    ret = uart->uart_write(&c, 1);
+
+    if (ret < 0) {
+        return -1;
+    } else {
+        return 1;
+    }
+}
+
+static int _getc(struct rt_serial_device *serial)
+{
+    DEV_UART_PTR uart;
+    unsigned int id;
+    unsigned int data;
+    int ret;
+    int rd_avail = 0;
+
+    id = (unsigned int)(serial->parent.user_data);
+    uart = uart_get_dev(id);
+
+    uart->uart_control(UART_CMD_GET_RXAVAIL, (void *)(&rd_avail));
+
+    if (rd_avail > 0) {
+        ret = uart->uart_read(&data, 1);
+    } else {
+        return -1;
+    }
+
+    if (ret < 0) {
+        return -1;
+    } else {
+        return data;
+    }
+
+}
+
+static const struct rt_uart_ops uart_ops =
+{
+    _configure,
+    _control,
+    _putc,
+    _getc,
+};
+
+static struct rt_serial_device uart0;
+static struct rt_serial_device uart1;
+static struct rt_serial_device uart2;
+static struct rt_serial_device uart3;
+
+static void uart0_isr(void *ptr)
+{
+    rt_hw_serial_isr((struct rt_serial_device*)&uart0, RT_SERIAL_EVENT_RX_IND);
+}
+
+static void uart1_isr(void *ptr)
+{
+    rt_hw_serial_isr((struct rt_serial_device*)&uart1, RT_SERIAL_EVENT_RX_IND);
+}
+
+static void uart2_isr(void *ptr)
+{
+    rt_hw_serial_isr((struct rt_serial_device*)&uart2, RT_SERIAL_EVENT_RX_IND);
+}
+
+static void uart3_isr(void *ptr)
+{
+    rt_hw_serial_isr((struct rt_serial_device*)&uart3, RT_SERIAL_EVENT_RX_IND);
+}
+
+
+int rt_hw_uart_init(void)
+{
+    DEV_UART_PTR uart;
+    struct serial_configure config;
+    int ret;
+
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
+
+    uart0.ops    = &uart_ops;
+    uart0.config = config;
+
+    uart1.ops    = &uart_ops;
+    uart1.config = config;
+
+    uart2.ops    = &uart_ops;
+    uart2.config = config;
+
+    uart3.ops    = &uart_ops;
+    uart3.config = config;
+
+    /* uart0 init */
+    uart = uart_get_dev(0);
+
+    if (uart != NULL) {
+        /* default format: 8bits, no parity, 1 stop bits */
+        ret = uart->uart_open(config.baud_rate);
+
+        if (ret != E_OPNED && ret != E_OK) {
+            return RT_ERROR;
+        }
+
+        /* enable rx int */
+        uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
+        /* use customized int isr */
+        uart->uart_control(UART_CMD_SET_RXCB, uart0_isr);
+        uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
+
+        rt_hw_serial_register(&uart0, "uart0",
+                            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                            (void *)0);
+    }
+
+    /* uart1 init */
+    uart = uart_get_dev(1);
+
+    if (uart != NULL) {
+        /* default format: 8bits, no parity, 1 stop bits */
+        ret = uart->uart_open(config.baud_rate);
+
+        if (ret != E_OPNED && ret != E_OK) {
+            return RT_ERROR;
+        }
+
+        /* enable rx int */
+        uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
+        /* use customized int isr */
+        uart->uart_control(UART_CMD_SET_RXCB, uart1_isr);
+        uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
+
+        rt_hw_serial_register(&uart1, "uart1",
+                            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                            (void *)1);
+    }
+
+    /* uart2 init */
+    uart = uart_get_dev(2);
+
+    if (uart != NULL) {
+        /* default format: 8bits, no parity, 1 stop bits */
+        ret = uart->uart_open(config.baud_rate);
+
+        if (ret != E_OPNED && ret != E_OK) {
+            return RT_ERROR;
+        }
+
+        /* enable rx int */
+        uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
+        /* use customized int isr */
+        uart->uart_control(UART_CMD_SET_RXCB, uart2_isr);
+        uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
+
+        rt_hw_serial_register(&uart2, "uart2",
+                            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                            (void *)2);
+    }
+
+    /* uart3 init */
+    uart = uart_get_dev(3);
+
+    if (uart != NULL) {
+        /* default format: 8bits, no parity, 1 stop bits */
+        ret = uart->uart_open(config.baud_rate);
+
+        if (ret != E_OPNED && ret != E_OK) {
+            return RT_ERROR;
+        }
+
+        /* enable rx int */
+        uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
+        /* use customized int isr */
+        uart->uart_control(UART_CMD_SET_RXCB, uart3_isr);
+        uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
+
+        rt_hw_serial_register(&uart3, "uart3",
+                            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                            (void *)3);
+    }
+
+    return RT_EOK;
+}
+
+#if defined BOARD_EMSK
+#define CONSOLE_UART "uart1"
+struct rt_serial_device *console_uart = &uart1;
+#elif defined BOARD_IOTDK || defined BOARD_EMSDP || defined BOARD_NSIM
+#define CONSOLE_UART "uart0"
+struct rt_serial_device *console_uart = &uart0;
+#elif defined BOARD_AXS
+#define CONSOLE_UART "uart2"
+struct rt_serial_device *console_uart = &uart2;
+#elif defined BOARD_HSDK
+#define CONSOLE_UART "uart3"
+struct rt_serial_device *console_uart = &uart3;
+#else
+#error "no supported board selected!"
+#endif
+
+void rt_hw_console_output(const char *str)
+{
+    while(*str != '\0')
+    {
+        if (*str == '\n') {
+            _putc(console_uart,'\r');
+        }
+        _putc(console_uart,*str);
+        str++;
+    }
+}
+
+void rt_hw_board_init()
+{
+    rt_hw_uart_init();
+    rt_components_board_init();
+    rt_console_set_device(CONSOLE_UART);
+}
+
+
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    timer_int_clear(BOARD_OS_TIMER_ID);
+    rt_tick_increase();
+}
+
+int rt_hw_timer_init(void)
+{
+
+    unsigned int cyc = BOARD_CPU_CLOCK / RT_TICK_PER_SECOND;
+
+    int_disable(BOARD_OS_TIMER_INTNO); /* disable os timer interrupt */
+    timer_stop(BOARD_OS_TIMER_ID);
+    timer_start(BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc);
+
+    int_handler_install(BOARD_OS_TIMER_INTNO, (INT_HANDLER_T)rt_hw_timer_isr);
+    int_pri_set(BOARD_OS_TIMER_INTNO, INT_PRI_MIN + 1); /* currently, firq(INT_PRI_MIN) not supported*/
+    int_enable(BOARD_OS_TIMER_INTNO);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
diff --git a/bsp/synopsys/boards/drivers/rt_board.h b/bsp/synopsys/boards/drivers/rt_board.h
new file mode 100644
index 0000000000..734ffc8aa5
--- /dev/null
+++ b/bsp/synopsys/boards/drivers/rt_board.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RT_BOARD_H__
+#define __RT_BOARD_H__
+
+#include "board.h"
+
+void rt_hw_board_init();
+
+int rt_hw_uart_init(void);
+
+#endif
diff --git a/bsp/synopsys/boards/linker_template_gnu.ld b/bsp/synopsys/boards/linker_template_gnu.ld
new file mode 100644
index 0000000000..e253bc635c
--- /dev/null
+++ b/bsp/synopsys/boards/linker_template_gnu.ld
@@ -0,0 +1,169 @@
+#define __ASSEMBLY__
+#include <target_mem_config.h>
+
+MEMORY
+{
+#if (REGION_ICCM_SIZE != 0)
+	REGION_ICCM :		ORIGIN = REGION_ICCM_START,	LENGTH = REGION_ICCM_SIZE
+#endif
+#if (REGION_DCCM_SIZE !=0)
+	REGION_DCCM :		ORIGIN = REGION_DCCM_START,	LENGTH = REGION_DCCM_SIZE
+#endif
+#if (REGION_XCCM_SIZE != 0)
+	REGION_XCCM :		ORIGIN = REGION_XCCM_START,	LENGTH = REGION_XCCM_SIZE
+#endif
+#if (REGION_YCCM_SIZE != 0)
+	REGION_YCCM :		ORIGIN = REGION_YCCM_START,	LENGTH = REGION_YCCM_SIZE
+#endif
+#if (REGION_EXT_ROM_SIZE != 0)
+	REGION_EXT_ROM :	ORIGIN = REGION_EXT_ROM_START,	LENGTH = REGION_EXT_ROM_SIZE
+#endif
+#if (REGION_EXT_RAM_SIZE != 0)
+	REGION_EXT_RAM :	ORIGIN = REGION_EXT_RAM_START,	LENGTH = REGION_EXT_RAM_SIZE
+#endif
+}
+
+ENTRY(_start)
+
+SECTIONS
+{
+	.init :
+	{
+		. = . + IMAGE_HEAD_SIZE;
+		_f_init = .;
+		KEEP (*(.init_vector .init_vector.*))
+		KEEP (*(.init_bootstrap .init_bootstrap.*))
+		_e_init = .;
+	} > REGION_ROM
+
+	.vector : ALIGN(1024)
+	{
+		_f_vector = .;
+		*(.vector .vector.*)
+		_e_vector = .;
+	} > REGION_ROM
+
+#if (REGION_XCCM_SIZE != 0)
+	.x_ccm (NOLOAD) : ALIGN(8)
+	{
+		_f_x_ccm = .;
+		*(.x_ccm .x_cmm.*)
+		_e_x_ccm = .;
+	} > REGION_XCCM
+#endif
+
+#if (REGION_YCCM_SIZE != 0)
+	.y_ccm (NOLOAD) : ALIGN(8)
+	{
+		_f_y_ccm = .;
+		*(.y_ccm .y_ccm.*)
+		_e_y_ccm = .;
+	} > REGION_YCCM
+#endif
+	.text : ALIGN(4)
+	{
+		_f_text = .;
+		*(.text .text.* .gnu.linkonce.t.*)
+		_e_text = .;
+	} > REGION_ROM
+
+	.rodata : ALIGN(4)
+	{
+		_f_rodata = .;
+
+		/* section information for finsh shell */
+		. = ALIGN(4);
+		__fsymtab_start = .;
+		KEEP(*(FSymTab))
+		__fsymtab_end = .;
+		. = ALIGN(4);
+		__vsymtab_start = .;
+		KEEP(*(VSymTab))
+		__vsymtab_end = .;
+
+		. = ALIGN(4);
+		__rt_init_start = .;
+		KEEP(*(SORT(.rti_fn*)))
+		__rt_init_end = .;
+		. = ALIGN(4);
+
+		. = ALIGN(4);
+		__CTOR_LIST__ = .;
+		LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+		KEEP(*(SORT_BY_NAME(".ctors*")))
+		LONG(0)
+		__CTOR_END__ = .;
+
+		. = ALIGN(4);
+		__init_array_start = .;
+		KEEP(*(SORT_BY_NAME(".init_array*")))
+		__init_array_end = .;
+
+		. = ALIGN(4);
+		__DTOR_LIST__ = .;
+		LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+		KEEP(*(SORT_BY_NAME(".dtors*")))
+		LONG(0)
+		__DTOR_END__ = .;
+
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		_e_rodata = .;
+	} > REGION_ROM
+
+	.data : ALIGN(4)
+	{
+		_f_data = .;
+		*(.data .data.* .gnu.linkonce.d.*)
+		_f_sdata = .;
+		__SDATA_BEGIN__ = .;
+		*(.sdata .sdata.* .gnu.linkonce.s.*)
+		PROVIDE (__sbss_start = .);
+		PROVIDE (___sbss_start = .);
+		_f_sbss = .;
+		*(.dynsbss)
+		*(.sbss .sbss.* .gnu.linkonce.sb.*)
+		*(.scommon)
+		_e_sbss = .;
+		PROVIDE (__sbss_end = .);
+		PROVIDE (___sbss_end = .);
+#if defined(EMBARC_UNIT_TEST)
+		. = ALIGN(8);
+		_f_embarc_unittest = .;
+		KEEP(*(.embarc_unittest))
+		_e_embarc_unittest = .;
+#endif
+		_e_sdata = .;
+		_e_data = .;
+	} > REGION_RAM AT > REGION_ROM
+
+	.bss (NOLOAD) : ALIGN(8)
+	{
+		_f_bss = .;
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		_e_bss = .;
+	} > REGION_RAM
+
+	.stack (NOLOAD) :
+	{
+		. = ALIGN(4);
+		_f_stack = .;
+		. = . + _STACKSIZE;
+		_e_stack = .;
+	} > REGION_RAM
+
+	.heap (NOLOAD) :
+	{
+		. = ALIGN(4);
+		__start_heap = . ;
+		_f_heap = .;
+		. = . + _HEAPSIZE;
+		_e_heap = .;
+		__end_heap = . ;
+	} > REGION_RAM
+
+	_load_addr_text = LOADADDR(.text);
+	_load_addr_rodata = LOADADDR(.rodata);
+	_load_addr_data = LOADADDR(.data);
+}
diff --git a/bsp/synopsys/boards/linker_template_mw.ld b/bsp/synopsys/boards/linker_template_mw.ld
new file mode 100644
index 0000000000..248dc5ac4c
--- /dev/null
+++ b/bsp/synopsys/boards/linker_template_mw.ld
@@ -0,0 +1,154 @@
+#define __ASSEMBLY__
+#include <target_mem_config.h>
+
+MEMORY {
+#if (REGION_ICCM_SIZE != 0)
+	REGION_ICCM :		ORIGIN = REGION_ICCM_START,	LENGTH = REGION_ICCM_SIZE
+#endif
+#if (REGION_DCCM_SIZE !=0)
+	REGION_DCCM :		ORIGIN = REGION_DCCM_START,	LENGTH = REGION_DCCM_SIZE
+#endif
+#if (REGION_XCCM_SIZE != 0)
+	REGION_XCCM :		ORIGIN = REGION_XCCM_START,	LENGTH = REGION_XCCM_SIZE
+#endif
+#if (REGION_YCCM_SIZE != 0)
+	REGION_YCCM :		ORIGIN = REGION_YCCM_START,	LENGTH = REGION_YCCM_SIZE
+#endif
+#if (REGION_EXT_ROM_SIZE != 0)
+	REGION_EXT_ROM :	ORIGIN = REGION_EXT_ROM_START,	LENGTH = REGION_EXT_ROM_SIZE
+#endif
+#if (REGION_EXT_RAM_SIZE != 0)
+	REGION_EXT_RAM :	ORIGIN = REGION_EXT_RAM_START,	LENGTH = REGION_EXT_RAM_SIZE
+#endif
+}
+
+ENTRY(_start)
+
+SECTIONS {
+
+	GROUP : {
+		.image_head: {
+			. = . + IMAGE_HEAD_SIZE;
+		}
+		.init_bootstrap:{
+			_f_init = .;
+			*(.init_vector .init_vector.*)
+			*(.init_bootstrap .init_bootstrap.*)
+			_e_init = .;
+		}
+		.vector ALIGN(1024): {
+			_f_vector = .;
+			*(.vector .vector.*)
+			_e_vector = .;
+		}
+	} > REGION_ROM
+
+#if (REGION_XCCM_SIZE != 0)
+	GROUP (NOLOAD): {
+		.x_ccm ALIGN(8): {
+			_f_x_ccm = .;
+			*(.x_ccm)
+			*(.x_ccm.*)
+			_e_x_ccm = .;
+		}
+	} > REGION_XCCM
+#endif
+
+#if (REGION_YCCM_SIZE != 0)
+	GROUP (NOLOAD): {
+		.y_ccm ALIGN(8): {
+			_f_y_ccm = .;
+			*(.y_ccm)
+			*(.y_ccm.*)
+			_e_y_ccm = .;
+		}
+	} > REGION_YCCM
+#endif
+
+	GROUP : {
+
+		.text ALIGN(4): {
+			_f_text = .;
+			*(TYPE text)
+			*(.text*)
+			_e_text = .;
+		}
+
+		.rodata  ALIGN(4): {
+			_f_rodata = .;
+
+			_fctors = .;
+			*(.ctors*)
+			_ectors = .;
+			_fdtors = .;
+			*(.dtors*)
+			_edtors = .;
+			_feh_frame = .;
+			*(.eh_frame*)
+			_eeh_frame = .;
+
+			*(TYPE lit)
+
+			/* section information for finsh shell */
+			. = ALIGN(4);
+			__fsymtab_start = .;
+			*(FSymTab*)
+			__fsymtab_end = .;
+			. = ALIGN(4);
+			__vsymtab_start = .;
+			*(VSymTab*)
+			__vsymtab_end = .;
+
+			. = ALIGN(4);
+			__rt_init_start = .;
+			*(.rti_fn*)
+			__rt_init_end = .;
+			. = ALIGN(4);
+
+			_e_rodata = .;
+		}
+
+	} > REGION_ROM
+
+
+	GROUP : {
+		.data ALIGN(8): {
+			_f_data = .;
+			_f_sdata = .;
+			*(.sdata)
+			*(.sbss)
+			_e_sdata = .;
+			*(TYPE data)
+		}
+#if defined(EMBARC_UNIT_TEST)
+		.unit_test ALIGN(8): {
+			_f_embarc_unittest = .;
+			KEEP(*(".embarc_unittest"))
+			_e_embarc_unittest = .;
+		}
+#endif
+		.tls ALIGN(8): {
+			*(.tls*)
+			_e_data = .;
+		}
+	} > REGION_RAM AT > REGION_ROM
+
+	GROUP (NOLOAD) : {
+		.bss ALIGN(8): {
+			_f_bss = .;
+			*(TYPE bss)
+			_e_bss = .;
+		}
+		.stack ALIGN(4) SIZE(_STACKSIZE): {}
+		.heap? ALIGN(4) SIZE(_HEAPSIZE): {}
+	} > REGION_RAM
+
+	_f_stack = ADDR(.stack);
+	_e_stack = ADDR(.stack) + SIZEOF(.stack);
+	_f_heap = ADDR(.heap);
+	_e_heap = ADDR(.heap) + SIZEOF(.heap);
+
+	_load_addr_text = LOADADDR(.text);
+	_load_addr_rodata = LOADADDR(.rodata);
+	_load_addr_data = LOADADDR(.data);
+}
diff --git a/bsp/synopsys/boards/rtconfig.h b/bsp/synopsys/boards/rtconfig.h
new file mode 100644
index 0000000000..6df6176c16
--- /dev/null
+++ b/bsp/synopsys/boards/rtconfig.h
@@ -0,0 +1,157 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+#define RT_DEBUG_INIT_CONFIG
+#define RT_DEBUG_INIT 1
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_MEMHEAP
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40002
+#define RT_USING_CPU_FFS
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 1024
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 8
+#define RT_USING_SERIAL
+#define RT_SERIAL_RB_BUFSZ 1024
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+#define PKG_USING_EMBARC_BSP
+#define PKG_USING_EMBARC_BSP_UPSTREAM_VERSION
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define SOC_EMSK
+#define EMSK_USING_UART0
+#define EMSK_USING_UART1
+
+#endif
diff --git a/bsp/synopsys/boards/rtconfig.py b/bsp/synopsys/boards/rtconfig.py
new file mode 100644
index 0000000000..0bafd172b5
--- /dev/null
+++ b/bsp/synopsys/boards/rtconfig.py
@@ -0,0 +1,58 @@
+import os
+
+# toolchains options
+ARCH='arc'
+CPU='em'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if CROSS_TOOL == 'gcc':
+    PLATFORM 	= 'gcc'
+    EXEC_PATH 	= 'C:/arc_gnu/bin'
+elif CROSS_TOOL =='mw':
+    PLATFORM 	= 'mw'
+    EXEC_PATH 	= 'C:/ARC/MetaWare/arc/bin'
+
+# if os.getenv('RTT_EXEC_PATH'):
+#     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arc-elf32-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    DBG = PREFIX + 'gdb'
+
+    TARGET = 'rtthread_snps_embarc.elf'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_snps_embarc.bin\n' +\
+            SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'mw':
+    # toolchains
+    CC = 'ccac'
+    CXX = 'ccac'
+    AS = 'ccac'
+    AR = 'arac'
+    LINK = 'ccac'
+    TARGET_EXT = 'elf'
+    SIZE = 'sizeac'
+    OBJDUMP = 'elfdumpac'
+    OBJCPY = 'elf2bin'
+    DBG = 'mdb'
+
+    TARGET = 'rtthread_snps_embarc.elf'
+
+    POST_ACTION = OBJCPY + ' $TARGET rtthread_snps_embarc.bin\n' +\
+            SIZE + ' $TARGET \n'
diff --git a/bsp/synopsys/embarc/SConscript b/bsp/synopsys/embarc/SConscript
deleted file mode 100644
index 9e086739af..0000000000
--- a/bsp/synopsys/embarc/SConscript
+++ /dev/null
@@ -1,28 +0,0 @@
-from building import *
-
-cwd = GetCurrentDir()
-
-embarc_arc_hal_SRCS = Split("""
-arc/arc_cache.c
-arc/arc_exc_asm.S
-arc/arc_exception.c
-arc/arc_timer.c
-arc/startup/arc_cxx_support.c
-arc/startup/arc_startup.S
-device/designware/uart/dw_uart.c
-device/designware/gpio/dw_gpio.c
-""")
-
-
-ASFLAGS = ' -I' + cwd
-
-src = embarc_arc_hal_SRCS
-
-path = [cwd,
-	cwd + '/arc',
-	cwd + '/arc/startup'
-	]
-
-group = DefineGroup('embarc', src, depend = [], CPPPATH = path, ASFLAGS = ASFLAGS)
-
-Return('group')
diff --git a/bsp/synopsys/embarc/arc/arc_cache.c b/bsp/synopsys/embarc/arc/arc_cache.c
deleted file mode 100644
index 632a3e3291..0000000000
--- a/bsp/synopsys/embarc/arc/arc_cache.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_MISC_CACHE
- * \brief implementation of cache related functions
- */
-
-#include "inc/arc/arc_cache.h"
-
-#define DIV_ROUND_UP(x, y)  (((x) + (y) - 1) / (y))
-
-
-struct cache_config {
-	uint8_t ver;			/* version */
-	uint8_t assoc;			/* Cache Associativity */
-	uint16_t line; 			/* cache line/block size */
-	uint32_t capacity;		/* capacity */
-};
-
-
-static struct cache_config icache_config, dcache_config;
-
-/**
- * \brief invalidate multi instruction cache lines
- *
- * \param[in] start_addr start address in instruction cache
- * \param[in] size  the bytes to be invalidated
- * \return 0, succeeded, -1, failed
- */
-int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size)
-{
-	if (!icache_available()) return -1;
-
-	if ((size == 0) || (size > icache_config.capacity)) {
-		return -1;
-	}
-
-	uint32_t end_addr;
-	uint32_t line_size;
-	uint32_t status;
-
-	line_size = (uint32_t)(icache_config.line);
-	end_addr = start_addr + size - 1;
-	start_addr &= (uint32_t)(~(line_size - 1));
-
-	status = cpu_lock_save();
-	do {
-		_arc_aux_write(AUX_IC_IVIL, start_addr);
-		Asm("nop_s");
-		Asm("nop_s");
-		Asm("nop_s");
-		start_addr += line_size;
-	} while (start_addr <= end_addr);
-	cpu_unlock_restore(status);
-
-	return 0;
-}
-
-/**
- * \brief lock multi lines in instruction cache
- *
- * \param[in] start_addr start address in instruction cache
- * \param[in] size  the bytes to be locked
- * \return 0, succeeded, -1, failed (cache already locked or other reasons)
- */
-int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size)
-{
-	if (!icache_available()) return -1;
-
-	if ((size == 0) || (size > icache_config.capacity)) {
-		return -1;
-	}
-
-	uint32_t end_addr;
-	uint32_t line_size;
-	uint32_t status;
-	int32_t ercd = 0;
-
-	line_size = (uint32_t)(icache_config.line);
-	end_addr = start_addr + size - 1;
-	start_addr &= (uint32_t)(~(line_size - 1));
-
-	status = cpu_lock_save();
-	do {
-		_arc_aux_write(AUX_IC_LIL, start_addr);
-		if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
-			start_addr += line_size;
-		} else {
-			ercd = -1;	/* the operation failed */
-			break;
-		}
-	} while (start_addr <= end_addr);
-	cpu_unlock_restore(status);
-
-	return ercd;
-}
-
-/**
- * \brief directly write icache internal ram
- *
- * \param[in] cache_addr, icache internal address(way+index+offset)
- * \param[in] tag	cache tag to write (tag+lock bit+valid bit)
- * \param[in] data	cache data to write
- * \return 0, succeeded, -1, failed
- */
-int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data)
-{
-	if (!icache_available()) return -1;
-
-	if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) {
-		return -1;
-	}
-	_arc_aux_write(AUX_IC_RAM_ADDR, cache_addr);
-	_arc_aux_write(AUX_IC_TAG, tag );
-	_arc_aux_write(AUX_IC_DATA, data);
-
-	return 0;
-}
-
-/**
- * \brief directly read icache internal ram
- *
- * \param[in] cache_addr, icache internal address(way+index+offset)
- * \param[out] tag	cache tag to read (tag+index+lock bit+valid bit)
- * \param[out] data	cache data to read
- * \return 0, succeeded, -1, failed
- */
-int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data)
-{
-	if (!icache_available()) return -1;
-
-	if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) {
-		return -1;
-	}
-	_arc_aux_write(AUX_IC_RAM_ADDR, cache_addr);
-	*tag = _arc_aux_read(AUX_IC_TAG);
-	*data = _arc_aux_read(AUX_IC_DATA);
-
-	return 0;
-}
-
-/**
- * \brief indirectly read icache internal ram
- *
- * \param[in] mem_addr, memory address
- * \param[out] tag	cache tag to read
- * \param[out] data	cache data to read
- * \return 0, succeeded, -1, failed
- */
-int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data)
-{
-	if (!icache_available()) return -1;
-
-	if (!(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS)) {
-		return -1;
-	}
-	_arc_aux_write(AUX_IC_RAM_ADDR, mem_addr);
-	if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
-		*tag = _arc_aux_read(AUX_IC_TAG);
-		*data = _arc_aux_read(AUX_IC_DATA);
-	} else {
-		return -1;	/* the specified memory is not in icache */
-	}
-	return 0;
- }
-
-/**
- * \brief invalidate multi data cache lines
- *
- * \param[in] start_addr start address in data cache
- * \param[in] size  the bytes to be invalidated
- * \return 0, succeeded, -1, failed
- */
-int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size)
-{
-	if (!dcache_available()) return -1;
-
-	uint32_t end_addr;
-	uint32_t line_size;
-	uint32_t status;
-
-	if ((size == 0) || (size > dcache_config.capacity)) {
-		return -1;
-	}
-
-	line_size = (uint32_t)(dcache_config.line);
-	end_addr = start_addr + size - 1;
-	start_addr &= (uint32_t)(~(line_size - 1));
-
-	status = cpu_lock_save();
-	do {
-		_arc_aux_write(AUX_DC_IVDL, start_addr);
-		Asm("nop_s");
-		Asm("nop_s");
-		Asm("nop_s");
-		/* wait for flush completion */
-		while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
-		start_addr += line_size;
-	} while (start_addr <= end_addr);
-	cpu_unlock_restore(status);
-
-	return 0;
-
-}
-
-/**
- * \brief flush multi lines in data cache
- *
- * \param[in] start_addr start address
- * \param[in] size	the bytes to be flushed
- * \return 0, succeeded, -1, failed
- */
-int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size)
-{
-	if (!dcache_available()) return -1;
-
-	if ((size == 0) || (size > dcache_config.capacity)) {
-		return -1;
-	}
-
-	uint32_t end_addr;
-	uint32_t line_size;
-	uint32_t status;
-
-	line_size = (uint32_t)(dcache_config.line);
-	end_addr = start_addr + size - 1;
-	start_addr &= (uint32_t)(~(line_size - 1));
-
-	status = cpu_lock_save();
-	do {
-		_arc_aux_write(AUX_DC_FLDL, start_addr);
-		Asm("nop_s");
-		Asm("nop_s");
-		Asm("nop_s");
-		/* wait for flush completion */
-		while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
-		start_addr += line_size;
-	} while (start_addr <= end_addr);
-	cpu_unlock_restore(status);
-
-	return 0;
-}
-
-/**
- * \brief lock multi lines in data cache
- *
- * \param[in] start_addr start address in data cache
- * \param[in] size  the bytes to be locked
- * \return 0, succeeded, -1, failed
- */
-int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size)
-{
-	if (!dcache_available()) return -1;
-
-	if ((size == 0) || (size > dcache_config.capacity)) {
-		return -1;
-	}
-
-	uint32_t end_addr;
-	uint32_t line_size;
-	uint32_t status;
-	int32_t ercd = 0;
-
-	line_size = (uint32_t)(dcache_config.line);
-	end_addr = start_addr + size - 1;
-	start_addr &= (uint32_t)(~(line_size - 1));
-
-	status = cpu_lock_save();
-	do {
-		_arc_aux_write(AUX_DC_LDL, start_addr);
-		Asm("nop_s");
-		if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
-			start_addr += line_size;
-		} else {
-			ercd = -1;	/* the operation failed */
-			break;
-		}
-	} while (start_addr <= end_addr);
-	cpu_unlock_restore(status);
-
-	return ercd;
-}
-
-/**
- * \brief directly write dcache internal ram
- *
- * \param[in] cache_addr, dcache internal address(way+index+offset)
- * \param[in] tag	cache tag to write
- * \param[in] data	cache data to write
- * \return 0, succeeded, -1, failed
- */
-int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data)
-{
-	if (!dcache_available()) return -1;
-
-	if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) {
-		return -1;
-	}
-	_arc_aux_write(AUX_DC_RAM_ADDR, cache_addr);
-	_arc_aux_write(AUX_DC_TAG, tag);
-	_arc_aux_write(AUX_DC_DATA, data);
-
-	return 0;
-}
-
-/**
- * \brief directly read dcache internal ram
- *
- * \param[in] cache_addr, dcache internal address(way+index+offset)
- * \param[out] tag	cache tag to read
- * \param[out] data	cache data to read
- * \return 0, succeeded, -1, failed
- */
-int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data)
-{
-	if (!dcache_available()) return -1;
-
-	if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) {
-		return -1;
-	}
-	_arc_aux_write(AUX_DC_RAM_ADDR, cache_addr);
-	*tag = _arc_aux_read(AUX_DC_TAG);
-	*data = _arc_aux_read(AUX_DC_DATA);
-
-	return 0;
-}
-
-/**
- * \brief indirectly read dcache internal ram
- *
- * \param[in] mem_addr, memory address(tag+index+offset)
- * \param[out] tag	cache tag to read
- * \param[out] data	cache data to read
- * \return 0, succeeded, -1, failed
- */
-int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data)
-{
-	if (!dcache_available()) return -1;
-
-	if (!(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS)) {
-		return -1;
-	}
-	_arc_aux_write(AUX_DC_RAM_ADDR, mem_addr);
-	if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
-		*tag = _arc_aux_read(AUX_DC_TAG);
-		*data = _arc_aux_read(AUX_DC_DATA);
-	} else {
-		return -1;	/* the specified memory is not in dcache */
-	}
-	return 0;
- }
-
-/**
- * \brief  initialize cache
- * 1. invalidate icache and dcache
- * 2. Only support ARCv2 cache
- */
-void arc_cache_init(void)
-{
-	uint32_t build_cfg;
-
-	build_cfg = _arc_aux_read(AUX_BCR_D_CACHE);
-
-	dcache_config.ver = build_cfg & 0xff;
-
-	if (dcache_config.ver >= 0x04) { /* ARCv2 */
-		dcache_enable(DC_CTRL_DISABLE_FLUSH_LOCKED |
-			DC_CTRL_INDIRECT_ACCESS | DC_CTRL_INVALID_FLUSH);
-		dcache_invalidate();
-		dcache_config.assoc = 1 << ((build_cfg >> 8) & 0xf);
-		dcache_config.capacity = 512 << ((build_cfg >> 12) & 0xf);
-		dcache_config.line = 16 << ((build_cfg >> 16) & 0xf);
-	}
-
-	build_cfg = _arc_aux_read(AUX_BCR_I_CACHE);
-
-	icache_config.ver = build_cfg & 0xff;
-
-	if (icache_config.ver >= 0x04) { /* ARCv2 */
-		icache_config.assoc = 1 << ((build_cfg >> 8) & 0xf);
-		icache_config.capacity = 512 << ((build_cfg >> 12) & 0xf);
-		icache_config.line = 8 << ((build_cfg >> 16) & 0xf);
-
-		icache_enable(IC_CTRL_IC_ENABLE);
-		icache_invalidate();
-	}
-
-}
diff --git a/bsp/synopsys/embarc/arc/arc_exc_asm.S b/bsp/synopsys/embarc/arc/arc_exc_asm.S
deleted file mode 100644
index 7410db3154..0000000000
--- a/bsp/synopsys/embarc/arc/arc_exc_asm.S
+++ /dev/null
@@ -1,201 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_EXCEPTION_CPU
- * \brief  assembly part of exception and interrupt processing
- */
-
-/**
- * \addtogroup ARC_HAL_EXCEPTION_CPU
- * @{
- */
-
-/* function documentation */
-/**
- * \fn void exc_entry_cpu(void)
- * \brief default entry of CPU exceptions, such as TLB miss and swap.
- *
- * \fn void exc_entry_int(void)
- * \brief normal interrupt exception entry.
- * 	In default, all interrupt exceptions are installed with normal entry.
- * 	If FIRQ is required, exc_entry_firq should be the entry.
- *
- * \fn void exc_entry_firq(void)
- * \brief firq exception entry
- */
-/** }@ */
-
-/** @cond EXCEPTION_ASM */
-
-#define __ASSEMBLY__
-#include "inc/arc/arc.h"
-#include "inc/arc/arc_asm_common.h"
-
-	.file "arc_exc_asm.S"
-
-/* entry for cpu exception handling */
-	.text
-	.global exc_entry_cpu
-	.weak exc_entry_cpu
-	.align 4
-exc_entry_cpu:
-
-	EXCEPTION_PROLOGUE
-
-	mov	r3, sp					/* as exception handler's para(exc_frame) */
-
-/* exc_nest_count +1 */
-	ld	r0, [exc_nest_count]
-	add	r0, r0, 1
-	st	r0, [exc_nest_count]
-
-/* find the exception cause */
-	lr	r0, [AUX_ECR]
-	lsr	r0, r0, 16
-	bmsk	r0, r0, 7
-	mov	r1, exc_int_handler_table
-	ld.as	r2, [r1, r0]
-
-	mov	r0, r3
-	jl	[r2]					/* jump to exception handler where interrupts are not allowed! */
-
-/* interrupts are not allowed */
-exc_return:
-
-/* exc_nest_count -1 */
-	ld	r0, [exc_nest_count]
-	sub	r0, r0, 1
-	st	r0, [exc_nest_count]
-
-	EXCEPTION_EPILOGUE
-	rtie
-
-
-/****** entry for normal interrupt exception handling ******/
-	.global exc_entry_int
-	.weak exc_entry_int
-	.align 4
-exc_entry_int:
-	clri						/* disable interrupt */
-
-#if ARC_FEATURE_FIRQ == 1
-#if ARC_FEATURE_RGF_NUM_BANKS > 1
-	lr	r0, [AUX_IRQ_ACT]			/*  check whether it is P0 interrupt */
-	btst	r0, 0
-	bnz	exc_entry_firq
-#else
-	PUSH	r10
-	lr	r10, [AUX_IRQ_ACT]
-	btst	r10, 0
-	POP	r10
-	bnz	exc_entry_firq
-#endif
-#endif
-	INTERRUPT_PROLOGUE			/* save scratch regs, this will be affected  */
-
-
-/* exc_nest_count +1 */
-	ld	r0, [exc_nest_count]
-	add	r0, r0, 1
-	st	r0, [exc_nest_count]
-
-
-	lr	r0, [AUX_IRQ_CAUSE]
-	mov	r1, exc_int_handler_table
-	ld.as	r2, [r1, r0]				/* r2 = _kernel_exc_tbl + irqno *4 */
-
-/* for the case of software triggered interrupt */
-	lr	r3, [AUX_IRQ_HINT]
-	cmp	r3, r0
-	bne.d	irq_hint_handled
-	xor	r3, r3, r3
-	sr	r3, [AUX_IRQ_HINT]
-irq_hint_handled:
-	seti						/* enable higher priority interrupt */
-
-	mov	r0, sp
-	jl	[r2]					/* jump to interrupt handler */
-
-/* no interrupts are allowed from here */
-int_return:
-	clri						/* disable interrupt */
-
-/* exc_nest_count -1 */
-	ld	r0, [exc_nest_count]
-	sub	r0, r0, 1
-	st	r0, [exc_nest_count]
-
-	INTERRUPT_EPILOGUE
-	rtie
-
-/****** entry for fast irq exception handling ******/
-	.global exc_entry_firq
-	.weak exc_entry_firq
-	.align 4
-exc_entry_firq:
-	clri						/* disable interrupt */
-	SAVE_FIQ_EXC_REGS
-
-/* exc_nest_count +1 */
-	ld	r0, [exc_nest_count]
-	add	r0, r0, 1
-	st	r0, [exc_nest_count]
-
-	lr	r0, [AUX_IRQ_CAUSE]
-	mov	r1, exc_int_handler_table
-	ld.as	r2, [r1, r0]				/* r2 = _kernel_exc_tbl + irqno *4 */
-
-/* for the case of software triggered interrupt */
-	lr	r3, [AUX_IRQ_HINT]
-	cmp	r3, r0
-	bne.d	firq_hint_handled
-	xor	r3, r3, r3
-	sr	r3, [AUX_IRQ_HINT]
-firq_hint_handled:
-
-	jl	[r2]					/* jump to interrupt handler */
-
-/* no interrupts are allowed from here */
-firq_return:
-
-/* exc_nest_count -1 */
-	ld	r0, [exc_nest_count]
-	sub	r0, r0, 1
-	st	r0, [exc_nest_count]
-
-	RESTORE_FIQ_EXC_REGS
-	rtie
-
-/** @endcond */
diff --git a/bsp/synopsys/embarc/arc/arc_exception.c b/bsp/synopsys/embarc/arc/arc_exception.c
deleted file mode 100644
index a256b0b394..0000000000
--- a/bsp/synopsys/embarc/arc/arc_exception.c
+++ /dev/null
@@ -1,501 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
- * \brief C Implementation of exception and interrupt management
- */
-#include "inc/arc/arc_exception.h"
-#include "inc/arc/arc_cache.h"
-
-//#define	 DBG_LESS
-//#include "embARC_debug.h"
-
-/**
- * \addtogroup ARC_HAL_EXCEPTION_CPU
- * @{
- * \var exc_entry_table
- * \brief exception entry table
- *
- * install exception entry table to ARC_AUX_INT_VECT_BASE in startup.
- * According to ARCv2 ISA, vectors are fetched in instruction space and thus
- * may be present in ICCM, Instruction Cache, or
- * main memory accessed by instruction fetch logic.
- * So it is put into a specific section .vector.
- *
- * Please note that the exc_entry_table maybe cached in ARC. Some functions is
- * defined in .s files.
- *
- */
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_CPU
- * \brief  default cpu exception handler
- * \param p_excinf pointer to the exception frame
- */
-static void exc_handler_default(void *p_excinf)
-{
-	// uint32_t excpt_cause_reg = 0;
-	// uint32_t excpt_ret_reg = 0;
-	// uint32_t exc_no = 0;
-
-	// excpt_cause_reg = _arc_aux_read(AUX_ECR);
-	// excpt_ret_reg = _arc_aux_read(AUX_ERRET);
-	// exc_no = (excpt_cause_reg >> 16) & 0xff;
-
-	Asm("kflag 1");
-}
-
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_INTERRUPT
- * \brief  default interrupt handler
- * \param[in] p_excinf	information for interrupt handler
- */
-static void int_handler_default(void *p_excinf)
-{
-	// uint32_t int_cause_reg = 0;
-
-	// int_cause_reg = _arc_aux_read(AUX_IRQ_CAUSE);
-	Asm("kflag 1");
-}
-
-__attribute__ ((aligned(1024), section(".vector")))
-EXC_ENTRY exc_entry_table[NUM_EXC_ALL] = {
- 	[0] = _arc_reset,
- 	[1 ... NUM_EXC_CPU-1] = exc_entry_cpu,
-	[NUM_EXC_CPU ... NUM_EXC_ALL-1] = exc_entry_int
- };
-/**
- * \var exc_int_handler_table
- * \brief the cpu exception and interrupt exception handler table
- * called in exc_entry_default and exc_entry_int
- */
-EXC_HANDLER exc_int_handler_table[NUM_EXC_ALL] = {
-	 [0 ... NUM_EXC_CPU-1] = exc_handler_default,
-	 [NUM_EXC_CPU ... NUM_EXC_ALL-1] = int_handler_default
-};
-
-/**
- * \var exc_nest_count
- * \brief the counter for exc/int processing, =0 no int/exc
- * >1 in int/exc processing
- * @}
- */
-uint32_t exc_nest_count;
-
-typedef struct aux_irq_ctrl_field {
-	/* note: little endian */
-	uint32_t save_nr_gpr_pairs: 5;	/** Indicates number of general-purpose register pairs saved, from 0 to 8/16 */
-	uint32_t res: 4;		/** Reserved */
-	uint32_t save_blink: 1;		/** Indicates whether to save and restore BLINK */
-	uint32_t save_lp_regs: 1;	/** Indicates whether to save and restore loop registers (LP_COUNT, LP_START, LP_END) */
-	uint32_t save_u_to_u: 1;	/** Indicates if user context is saved to user stack */
-	uint32_t res2: 1;		/** Reserved */
-	uint32_t save_idx_regs: 1;	/** Indicates whether to save and restore code-density registers (EI_BASE, JLI_BASE, LDI_BASE) */
-	uint32_t res3: 18;		/** Reserved */
-} aux_irq_ctrl_field_t;
-
-typedef union {
-	aux_irq_ctrl_field_t bits;
-	uint32_t value;
-} aux_irq_ctrl_t;
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
- * \brief  intialize the exception and interrupt handling
- */
-void exc_int_init(void)
-{
-	uint32_t i;
-	uint32_t status;
-	aux_irq_ctrl_t ictrl;
-
-	ictrl.value = 0;
-
-#ifndef ARC_FEATURE_RF16
-	ictrl.bits.save_nr_gpr_pairs = 6;	/* r0 to r11 (r12 saved manually) */
-#else
-	ictrl.bits.save_nr_gpr_pairs = 3;	/* r0 to r3, r10, r11  */
-#endif
-	ictrl.bits.save_blink = 1;
-	ictrl.bits.save_lp_regs = 1;		/* LP_COUNT, LP_START, LP_END */
-	ictrl.bits.save_u_to_u = 0;		/* user ctxt saved on kernel stack */
-	ictrl.bits.save_idx_regs = 1;		/* JLI, LDI, EI */
-
-	status = arc_lock_save();
-	for (i = NUM_EXC_CPU; i < NUM_EXC_ALL; i++) {
-		/* interrupt level triggered, disabled, priority is the lowest */
-		_arc_aux_write(AUX_IRQ_SELECT, i);
-		_arc_aux_write(AUX_IRQ_ENABLE, 0);
-		_arc_aux_write(AUX_IRQ_TRIGGER, 0);
-#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2)
-		_arc_aux_write(AUX_IRQ_PRIORITY, (1 << AUX_IRQ_PRIORITY_BIT_S)|(INT_PRI_MAX - INT_PRI_MIN));
-#else
-		_arc_aux_write(AUX_IRQ_PRIORITY, INT_PRI_MAX - INT_PRI_MIN);
-#endif
-	}
-	_arc_aux_write(AUX_IRQ_CTRL, ictrl.value);
-
-	arc_unlock_restore(status);
-
-	/** ipm should be set after cpu unlock restore to avoid reset of the status32 value */
-	arc_int_ipm_set((INT_PRI_MAX - INT_PRI_MIN));
-}
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_CPU
- * \brief  install a CPU exception entry
- * \param[in] excno exception number
- * \param[in] entry the entry of exception to install
- */
-int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY entry)
-{
-	uint32_t status;
-
-	EXC_ENTRY *table = (EXC_ENTRY *)_arc_aux_read(AUX_INT_VECT_BASE);
-
-	if (excno < NUM_EXC_ALL && entry != NULL
-		&& table[excno] != entry) {
-		status = cpu_lock_save();
-		/* directly write to mem, as arc gets exception handler from mem not from cache */
-		/* FIXME, here maybe icache is dirty, need to be invalidated */
-		table[excno] = entry;
-
-		if (_arc_aux_read(AUX_BCR_D_CACHE) > 0x2) {
-		/* dcache is available */
-			dcache_flush_line((uint32_t)&table[excno]);
-		}
-
-		if (_arc_aux_read(AUX_BCR_D_CACHE) > 0x2) {
-		/* icache is available */
-			icache_invalidate_line((uint32_t)&table[excno]);
-		}
-		cpu_unlock_restore(status);
-		return 0;
-	}
-	return -1;
-}
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_CPU
- * \brief  get the installed CPU exception entry
- * \param[in] excno exception number
- * \return the installed CPU exception entry
- */
-EXC_ENTRY exc_entry_get(const uint32_t excno)
-{
-	if (excno < NUM_EXC_ALL) {
-		return exc_entry_table[excno];
-	}
-	return NULL;
-}
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_CPU
- * \brief  install an exception handler
- * \param[in] excno	exception number
- * \param[in] handler the handler of exception to install
- */
-int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER handler)
-{
-	if (excno < NUM_EXC_ALL && handler != NULL) {
-		exc_int_handler_table[excno] = handler;
-		return 0;
-	}
-
-	return -1;
-}
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_CPU
- * \brief  get the installed exception handler
- * \param[in] excno	exception number
- * \return the installed exception handler or NULL
- */
-EXC_HANDLER exc_handler_get(const uint32_t excno)
-{
-	if (excno < NUM_EXC_ALL) {
-		return exc_int_handler_table[excno];
-	}
-
-	return NULL;
-}
-
-
-#ifndef EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT
-/**
- * \brief disable the specific interrupt
- *
- * \param[in] intno interrupt number
- */
-int32_t int_disable(const uint32_t intno)
-{
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		arc_int_disable(intno);
-		return 0;
-	}
-
-	return -1;
-}
-
-/**
- * \brief  enable the specific int
- *
- * \param[in] intno interrupt number
- */
-int32_t int_enable(const uint32_t intno)
-{
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		arc_int_enable(intno);
-		return 0;
-	}
-
-	return -1;
-}
-
-/**
- * \brief  check whether the specific int is enabled
- *
- * \param[in] intno interrupt number
- * \return 0 disabled, 1 enabled, < 0 error
- */
-int32_t int_enabled(const uint32_t intno)
-{
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		_arc_aux_write(AUX_IRQ_SELECT, intno);
-		return _arc_aux_read(AUX_IRQ_ENABLE);
-	}
-
-	return -1;
-}
-
-/**
- * \brief  get the interrupt priority mask
- *
- * \returns interrupt priority mask, negative num
- */
-int32_t int_ipm_get(void)
-{
-	return ((int32_t)arc_int_ipm_get() + INT_PRI_MIN);
-}
-
-
-/**
- * \brief  set the interrupt priority mask
- *
- * \param[in] intpri interrupt priority
- */
-int32_t int_ipm_set(int32_t intpri)
-{
-	if (intpri >= INT_PRI_MIN && intpri <= INT_PRI_MAX) {
-		intpri = intpri - INT_PRI_MIN;
-		arc_int_ipm_set(intpri);
-		return 0;
-	}
-
-	return  -1;
-}
-
-
-/**
- * \brief  get current interrupt priority mask
- *
- * \param[in] intno interrupt number
- * \return  <0 interrupt priority, 0 error
- */
-int32_t int_pri_get(const uint32_t intno)
-{
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		return (int32_t)arc_int_pri_get(intno) + INT_PRI_MIN;
-	}
-
-	return 0;
-}
-
-
-/**
- * \brief set interrupt priority
- *
- * \param[in] intno interrupt number
- * \param[in] intpri interrupt priority
- * \return  <0 error, 0 ok
- */
-int32_t int_pri_set(const uint32_t intno, int32_t intpri)
-{
-	uint32_t status;
-
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		status = cpu_lock_save();
-		intpri = intpri - INT_PRI_MIN;
-		arc_int_pri_set(intno,(uint32_t)intpri);
-		cpu_unlock_restore(status);
-		return 0;
-	}
-	return -1;
-}
-
-/**
- * \brief set interrupt secure or not secure
- * This function is valid in secureshield v2
- * \param[in] intno interrupt number
- * \param[in] secure, 0 for normal, >0 for secure
- * \return <0 error, 0 ok
- */
-int32_t int_secure_set(const uint32_t intno, uint32_t secure)
-{
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		arc_int_secure_set(intno, secure);
-		return 0;
-	}
-	return -1;
-
-}
-
-
-/**
- * \brief  probe the pending status of interrupt
- *
- * \param[in] intno interrupt number
- *
- * \returns 1 pending, 0 no pending, -1 error
- */
-int32_t int_probe(const uint32_t intno)
-{
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		return arc_int_probe(intno);
-	}
-	return -1;
-}
-
-
-/**
- * \brief  trigger the interrupt in software
- *
- * \param[in] intno interrupt number
- * \return 0 ok, -1 error
- */
-int32_t int_sw_trigger(const uint32_t intno)
-{
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		arc_int_sw_trigger(intno);
-		return 0;
-	}
-	return -1;
-}
-
-/**
- * \brief  config the interrupt level triggered or pulse triggered
- *
- * \param[in] intno interrupt number
- * \param[in] level, 0-level trigger, 1-pulse triggered
- * \return 0 ok, -1 error
- */
-int32_t int_level_config(const uint32_t intno, const uint32_t level)
-{
-	if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
-		arc_int_level_config(intno, level);
-		return 0;
-	}
-	return -1;
-}
-
-
-/**
- * \brief  lock cpu, disable interrupts
- */
-void cpu_lock(void)
-{
-	arc_lock();
-}
-
-/**
- * \brief  unlock cpu, enable interrupts to happen
- */
-void cpu_unlock(void)
-{
-	arc_unlock();
-}
-
-/**
- * \brief  lock cpu and return status
- *
- * \returns cpu status
- */
-uint32_t cpu_lock_save(void)
-{
-	return arc_lock_save();
-}
-
-/**
- * \brief  unlock cpu with the specific status
- *
- * \param[in] status  cpu status saved by cpu_lock_save
- */
-void cpu_unlock_restore(const uint32_t status)
-{
-	arc_unlock_restore(status);
-}
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_INTERRUPT
- * \brief  install an interrupt handler
- * \param[in] intno	interrupt number
- * \param[in] handler interrupt handler to install
- */
-int32_t int_handler_install(const uint32_t intno, INT_HANDLER handler)
-{
-	/*!< \todo parameter check ? */
-	if (intno >= NUM_EXC_CPU) {
-		return exc_handler_install(intno, handler);
-	}
-
-	return -1;
-}
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_INTERRUPT
- * \brief  get the installed an interrupt handler
- * \param[in] intno interrupt number
- * \return the installed interrupt handler or NULL
- */
-INT_HANDLER int_handler_get(const uint32_t intno)
-{
-	if (intno >= NUM_EXC_CPU) {
-		return exc_handler_get(intno);
-	}
-
-	return NULL;
-}
-#endif /* EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT */
diff --git a/bsp/synopsys/embarc/arc/arc_timer.c b/bsp/synopsys/embarc/arc/arc_timer.c
deleted file mode 100644
index 3d0c4b4f83..0000000000
--- a/bsp/synopsys/embarc/arc/arc_timer.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	ARC_HAL_MISC_TIMER
- * \brief  implementation of internal timer related functions
- * \todo RTC support should be improved if RTC is enabled
- */
-#include "inc/arc/arc_timer.h"
-#include "inc/arc/arc.h"
-#include "inc/arc/arc_builtin.h"
-
-/**
- * \brief  check whether the specific timer present
- * \param[in] no timer number
- * \retval 1 present
- * \retval 0 not present
- */
-int32_t arc_timer_present(const uint32_t no)
-{
-	uint32_t bcr = _arc_aux_read(AUX_BCR_TIMERS);
-	switch (no) {
-		case TIMER_0:
-			bcr = (bcr >> 8) & 1;
-			break;
-		case TIMER_1:
-			bcr = (bcr >> 9) & 1;
-			break;
-		case TIMER_RTC:
-			bcr = (bcr >> 10) & 1;
-			break;
-		default:
-			bcr = 0;
-			/* illegal argument so return false */
-			break;
-		}
-
-	return (int)bcr;
-}
-
-/**
- * \brief  start the specific timer
- * \param[in] no	timer number
- * \param[in] mode	timer mode
- * \param[in] val	timer limit value (not for RTC)
- * \return 0 success, -1 failure
- */
-int32_t arc_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val)
-{
-	if (arc_timer_present(no) == 0) {
-		return -1;
-	}
-
-	switch (no) {
-		case TIMER_0:
-			_arc_aux_write(AUX_TIMER0_CTRL, 0);
-			_arc_aux_write(AUX_TIMER0_LIMIT, val);
-			_arc_aux_write(AUX_TIMER0_CTRL, mode);
-			_arc_aux_write(AUX_TIMER0_CNT, 0);
-			break;
-		case TIMER_1:
-			_arc_aux_write(AUX_TIMER1_CTRL, 0);
-			_arc_aux_write(AUX_TIMER1_LIMIT, val);
-			_arc_aux_write(AUX_TIMER1_CTRL, mode);
-			_arc_aux_write(AUX_TIMER1_CNT, 0);
-			break;
-		case TIMER_RTC:
-			_arc_aux_write(AUX_RTC_CTRL, mode);
-			break;
-		default:
-			return -1;
-	}
-
-	return 0;
-}
-
-/**
- * \brief  stop and clear the specific timer
- *
- * \param[in] no timer number
- * \return 0 success, -1 failure
- */
-int32_t arc_timer_stop(const uint32_t no)
-{
-	if (arc_timer_present(no) == 0) {
-		return -1;
-	}
-
-	switch (no) {
-		case TIMER_0 :
-			_arc_aux_write(AUX_TIMER0_CTRL, 0);
-			_arc_aux_write(AUX_TIMER0_LIMIT,0);
-			_arc_aux_write(AUX_TIMER0_CNT, 0);
-			break;
-		case TIMER_1:
-			_arc_aux_write(AUX_TIMER1_CTRL, 0);
-			_arc_aux_write(AUX_TIMER1_LIMIT,0);
-			_arc_aux_write(AUX_TIMER1_CNT, 0);
-			break;
-		case TIMER_RTC:
-			_arc_aux_write(AUX_RTC_CTRL, TIMER_RTC_CLEAR);
-			break;
-		default:
-			return -1;
-	}
-
-	return 0;
-}
-
-/**
- * \brief  get timer current tick
- *
- * \param[in] no timer number
- * \param[out] val, timer value
- * \return 0 success, -1 failure
- */
-int32_t arc_timer_current(const uint32_t no, void *val)
-{
-	if (arc_timer_present(no) == 0) {
-		return -1;
-	}
-
-	switch (no) {
-		case TIMER_0 :
-			*((uint32_t *)val) = _arc_aux_read(AUX_TIMER0_CNT);
-			break;
-		case TIMER_1 :
-			*((uint32_t *)val) = _arc_aux_read(AUX_TIMER1_CNT);
-			break;
-		case TIMER_RTC:
-			*((uint64_t *)val) = _arc_aux_read(AUX_RTC_LOW);
-			break;
-		default :
-			return -1;
-	}
-
-	return 0;
-}
-
-/**
- * \brief  clear the interrupt pending bit of timer
- *
- * \param[in] no timer number
- * \return 0 success, -1 failure
- */
-int32_t arc_timer_int_clear(const uint32_t no)
-{
-	uint32_t val;
-
-	if (arc_timer_present(no) == 0) {
-		return -1;
-	}
-
-	switch (no) {
-		case TIMER_0 :
-			val = _arc_aux_read(AUX_TIMER0_CTRL);
-			val &= ~TIMER_CTRL_IP;
-			_arc_aux_write(AUX_TIMER0_CTRL, val);
-			break;
-		case TIMER_1 :
-			val = _arc_aux_read(AUX_TIMER1_CTRL);
-			val &= ~TIMER_CTRL_IP;
-			_arc_aux_write(AUX_TIMER1_CTRL, val);
-			break;
-		default :
-			return -1;
-	}
-
-	return 0;
-}
-
-/**
- * \brief  init internal timer
- */
-void arc_timer_init(void)
-{
-	arc_timer_stop(TIMER_0);
-	arc_timer_stop(TIMER_1);
-	arc_timer_stop(TIMER_RTC);
-}
diff --git a/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c b/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c
deleted file mode 100644
index af842fddc6..0000000000
--- a/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2012-2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* ------------------------------------------
- * Copyright (c) 2015, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2016-03-02
- * \author Wayne Ren(wei.ren@synopsys.com)
---------------------------------------------- */
-#include "embARC_BSP_config.h"
-#if defined(__GNU__)
-/* embARC's GNU C++ support takes reference from Zephyr (cpp_xxx.c) */
-
-/**
- * @file - Constructor module
- * @brief
- * The ctors section contains a list of function pointers that execute the
- * C++ constructors of static global objects. These must be executed before
- * the application's main() routine.
- *
- * NOTE: Not all compilers put those function pointers into the ctors section;
- * some put them into the init_array section instead.
- */
-
-/* What a constructor function pointer looks like */
-
-typedef void (*CtorFuncPtr)(void);
-
-/* Constructor function pointer list is generated by the linker script. */
-
-extern CtorFuncPtr __CTOR_LIST__[];
-extern CtorFuncPtr __CTOR_END__[];
-
-/**
- *
- * @brief Invoke all C++ style global object constructors
- *
- * This routine is invoked before the execution of the
- * application's main().
- */
-void __do_global_ctors_aux(void)
-{
-	unsigned int nCtors;
-
-	nCtors = (unsigned int)__CTOR_LIST__[0];
-
-	while (nCtors >= 1) {
-		__CTOR_LIST__[nCtors--]();
-	}
-}
-
-typedef void (*DtorFuncPtr)(void);
-
-extern DtorFuncPtr __DTOR_LIST__[];
-extern DtorFuncPtr __DTOR_END__[];
-
-/**
- *
- * @brief Invoke all C++ style global object destructors
- *
- * This routine is invoked after the execution of the
- * application's main().
- */
-void __do_global_dtors_aux(void)
-{
-	unsigned int nDtors;
-	unsigned int i;
-
-	nDtors = (unsigned int)__DTOR_LIST__[0];
-	i = 0;
-
-	while (i <= nDtors) {
-		__DTOR_LIST__[i++]();
-	}
-}
-
-void *__dso_handle = 0;
-
-/**
- * @brief Register destructor for a global object
- *
- * @param destructor the global object destructor function
- * @param objptr global object pointer
- * @param dso Dynamic Shared Object handle for shared libraries
- *
- * Function does nothing at the moment, assuming the global objects
- * do not need to be deleted
- *
- * @return N/A
- */
-int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso)
-{
-	return 0;
-}
-
-typedef void (*func_ptr)(void);
-
-extern func_ptr __init_array_start[0];
-extern func_ptr __init_array_end[0];
-
-/**
- * @brief Execute initialization routines referenced in .init_array section
- *
- * @return N/A
- */
-void __do_init_array_aux(void)
-{
-	for (func_ptr *func = __init_array_start;
-		func < __init_array_end;
-		func++) {
-		(*func)();
-	}
-}
-
-/**
- * @brief Stub for pure virtual functions
- *
- * This routine is needed for linking C++ code that uses pure virtual
- * functions.
- *
- * @return N/A
- */
-void __cxa_pure_virtual(void)
-{
-	while (1) {
-		;
-	}
-}
-#endif
diff --git a/bsp/synopsys/embarc/arc/startup/arc_startup.S b/bsp/synopsys/embarc/arc/startup/arc_startup.S
deleted file mode 100644
index 26a6fdb519..0000000000
--- a/bsp/synopsys/embarc/arc/startup/arc_startup.S
+++ /dev/null
@@ -1,262 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_STARTUP
- * \brief assembly part of startup process
- */
-
-/**
- * \addtogroup ARC_HAL_STARTUP
- * @{
- */
-/** @cond STARTUP_ASM */
-
-#define __ASSEMBLY__
-#include "embARC_BSP_config.h"
-#include "inc/arc/arc.h"
-
-	.file "arc_startup.S"
-
-.weak	_f_sdata		/* start of small data, defined in link script */
-.weak	init_hardware_hook	/* app hardware init hook */
-.weak	init_software_hook	/* app software init hook */
-
-.extern	board_main
-.extern exc_entry_table
-
-/* initial vector table */
-	.section .init_vector, "a"
-	.long _arc_reset
-	.section .init_bootstrap, "ax"
-	.global _arc_reset
-	.global _start
-	.align 4
-_start:
-_arc_reset:
-_arc_reset_stage1:
-	kflag	STATUS32_RESET_VALUE
-
-/* STAGE 1 */
-
-/* necessary hardware should be done first to speed up initialization
-	1. system clk
-	2. mem controller must be initialized before any access to external
-	mem.
-	3. others
-*/
-_arc_cache_init_start:
-	lr	r0, [AUX_BCR_D_CACHE]
-	cmp	r0, 2
-	/* invalidate dcache */
-	jle	_arc_icache_init
-	mov	r0, 1
-	sr	r0, [AUX_DC_IVDC]
-	sr	r0, [AUX_DC_CTRL]
-_arc_icache_init:
-	lr	r0, [AUX_BCR_I_CACHE]
-	cmp	r0, 2
-	jle	_arc_cache_init_end
-	/* invalidate icache */
-	mov	r0, 1
-	sr	r0, [AUX_IC_IVIC]
-	nop_s
-	nop_s
-	nop_s
-	sr	r0, [AUX_IC_CTRL]
-
-_arc_cache_init_end:
-	mov	r0, init_hardware_hook
-	cmp	r0, 0
-	jlne	[r0]
-
-/* STAGE 2: init necessary registers */
-
-_arc_reset_stage2:
-	mov	r0, 0
-
-/* interrupt related init */
-	sr	r0, [AUX_IRQ_ACT]
-	sr	r0, [AUX_IRQ_CTRL]
-	sr	r0, [AUX_IRQ_HINT]
-
-/* use the new vector table to replace the old one */
-#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2)
-	sr	exc_entry_table, [AUX_INT_VECT_BASE_S]
-#else
-	sr	exc_entry_table, [AUX_INT_VECT_BASE]
-#endif
-
-/* init stack */
-#if ARC_FEATURE_RGF_BANKED_REGS >= 16 && ARC_FEATURE_RGF_BANKED_REGS > 1 && ARC_FEATURE_FIRQ == 1
-#if _STACKSIZE < 512
-#error "not enough stack size for irq and firq"
-#endif
-
-/* switch to register bank1 */
-	lr      r0, [AUX_STATUS32]
-	bic     r0, r0, 0x70000
-	or      r0, r0, 0x10000
-	kflag   r0
-/* set sp, gp, fp in bank1 */
-	mov     sp, _e_stack
-	mov     gp, _f_sdata
-	mov     fp, 0
-/* come back to bank0 */
-	lr      r0, [AUX_STATUS32]
-	bic     r0, r0, 0x70000
-	kflag   r0
-	mov	sp, _e_stack-256
-#else
-	mov	sp, _e_stack	/* init stack pointer */
-#endif
-	mov	gp, _f_sdata	/* init small-data base register */
-	mov	fp, 0		/* init fp register */
-
-_arc_reset_stage3:
-_s3_copy_text:
-	mov	r0, _f_text
-	mov	r1, _load_addr_text
-	cmp	r0, r1
-
-/* if load addr == run addr, no need to copy */
-	jeq	_s3_copy_rodata
-	mov	r3, _e_text
-_s3_copy_text_loop:
-	ld.ab	r2, [r1, 4]
-	st.ab	r2, [r0, 4]
-	cmp	r0, r3
-	jlt	_s3_copy_text_loop
-_s3_copy_rodata:
-	mov	r0, _f_rodata
-	mov	r1, _load_addr_rodata
-	cmp	r0, r1
-
-/* if load addr == run addr, no need to copy */
-	jeq	_s3_copy_data
-	mov	r3, _e_rodata
-_s3_copy_rodata_loop:
-	ld.ab	r2, [r1, 4]
-	st.ab	r2, [r0, 4]
-	cmp	r0, r3
-	jlt	_s3_copy_rodata_loop
-_s3_copy_data:
-	mov	r0, _f_data
-	mov	r1, _load_addr_data
-	cmp	r0, r1
-	jeq	_s3_clear_bss
-
-/* if load addr == run addr, no need to copy */
-	mov	r3, _e_data
-_s3_copy_data_loop:
-	ld.ab	r2, [r1, 4]
-	st.ab	r2, [r0, 4]
-	cmp	r0, r3
-	jlt	_s3_copy_data_loop
-_s3_clear_bss:
-	mov	r0, _f_bss
-	mov	r1, _e_bss
-	cmp	r0, r1
-	jge	_arc_reset_call_main
-	mov	r2, 0
-_s3_clear_bss_loop:
-	st.ab	r2, [r0, 4]
-	cmp	r0, r1
-	jlt	_s3_clear_bss_loop
-
-/* STAGE 3: go to main */
-
-_arc_reset_call_main:
-
-/* \todo add cpp init here */
-	mov	r0, init_software_hook
-	cmp	r0, 0
-	jlne	[r0]
-/* board level library init */
-/* early init of interrupt and exception */
-	jl	exc_int_init
-/* init cache */
-	jl	arc_cache_init
-#if defined(__MW__)
-	jl	_init
-#elif defined(__GNU__)
-	jl	__do_global_ctors_aux
-	jl	__do_init_array_aux
-#endif
-	jl	board_main	/* board-level main */
-#if defined(__MW__)
-	jl	_fini
-#elif defined(__GNU__)
-	jl	__do_global_dtors_aux
-#endif
-	.global _exit_loop
-	.global _exit_halt
-	.align 4
-_exit_halt:
-_exit_loop:
-	flag	0x1
-	nop
-	nop
-	nop
-	b	_exit_loop
-
-#if defined(__MW__)
-	.global _init, _fini
-	.section ".init",text
-_init:
-	.cfa_bf	_init
-	push	%blink
-	.cfa_push	{%blink}
-
-	.section ".init$999999", text, 1, 2, check_text_align=0
-	pop	%blink
-	.cfa_pop	{%blink}
-	j	[%blink]
-	.cfa_ef
-
-	.section ".fini", text
-_fini:
-	.cfa_bf	_fini
-	push	%blink
-	.cfa_push	{%blink}
-
-	.section ".fini$999999", text, 1, 2, check_text_align=0
-	pop	%blink
-	.cfa_pop	{%blink}
-	j	[%blink]
-	.cfa_ef
-#endif
-/** @endcond */
-
-/** }@*/
diff --git a/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c b/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c
deleted file mode 100644
index ce79414fc6..0000000000
--- a/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c
+++ /dev/null
@@ -1,481 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-22
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_DW_GPIO	Designware GPIO Driver
- * \ingroup	DEVICE_DW
- * \brief	Designware GPIO Driver Implementation
- */
-
-/**
- * \file
- * \brief	designware gpio driver
- * \ingroup	DEVICE_DW_GPIO
- * \brief	Designware GPIO driver
- */
-#include "inc/embARC_toolchain.h"
-#include "inc/embARC_error.h"
-#include "inc/arc/arc_exception.h"
-
-#include "device/designware/gpio/dw_gpio.h"
-
-/** check expressions used in DesignWare GPIO driver implementation */
-#define DW_GPIO_CHECK_EXP(EXPR, ERROR_CODE)		CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
-
-#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
-/** valid check of uart info object */
-#define VALID_CHK_GPIO_INFO_OBJECT(gpioinfo_obj_ptr)		{				\
-			DW_GPIO_CHECK_EXP((gpioinfo_obj_ptr)!=NULL, E_OBJ);			\
-			DW_GPIO_CHECK_EXP(((gpioinfo_obj_ptr)->gpio_ctrl)!=NULL, E_OBJ);	\
- 		}
-#endif
-
-/**
- * \defgroup	DEVICE_DW_GPIO_STATIC	DesignWare GPIO Driver Static Functions
- * \ingroup	DEVICE_DW_GPIO
- * \brief	Static or inline functions, variables for DesignWare GPIO handle gpio operations,
- * 	only used in this file
- * @{
- */
-Inline uint32_t dw_gpio_read_ext(DW_GPIO_PORT_PTR port)
-{
-	return  port->regs->EXT_PORTS[port->no];
-}
-
-Inline uint32_t dw_gpio_read_dir(DW_GPIO_PORT_PTR port)
-{
-	return port->regs->SWPORTS[port->no].DDR;
-}
-
-Inline uint32_t dw_gpio_read_dr(DW_GPIO_PORT_PTR port)
-{
-	return port->regs->SWPORTS[port->no].DR;
-}
-
-Inline uint32_t dw_gpio_read_mthd(DW_GPIO_PORT_PTR port)
-{
-	return port->regs->INTEN;
-}
-
-Inline void dw_gpio_int_enable(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
-{
-	port->regs->INTEN |= bit_mask;
-}
-
-Inline void dw_gpio_int_disable(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
-{
-	port->regs->INTEN &= (~bit_mask);
-}
-
-Inline void dw_gpio_int_mask(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
-{
-	port->regs->INTMASK |= bit_mask;
-}
-
-Inline void dw_gpio_int_unmask(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
-{
-	port->regs->INTMASK &= (~bit_mask);
-}
-
-Inline uint32_t dw_gpio_int_read_level(DW_GPIO_PORT_PTR port)
-{
-	return port->regs->INTTYPE_LEVEL;
-}
-
-Inline uint32_t dw_gpio_int_read_polarity(DW_GPIO_PORT_PTR port)
-{
-	return port->regs->INT_POLARITY;
-}
-
-Inline uint32_t dw_gpio_int_read_debounce(DW_GPIO_PORT_PTR port)
-{
-	return port->regs->DEBOUNCE;
-}
-
-Inline uint32_t dw_gpio_int_read_status(DW_GPIO_PORT_PTR port)
-{
-	return port->regs->INTSTATUS;
-}
-
-Inline void dw_gpio_int_clear(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
-{
-	port->regs->PORTA_EOI = bit_mask;
-}
-
-static void dw_gpio_int_write_level(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_level)
-{
-	uint32_t reg_val;
-
-	reg_val = port->regs->INTTYPE_LEVEL;
-	reg_val &= (~bit_mask);
-	bit_level &= bit_mask;
-	reg_val |= bit_level;
-
-	port->regs->INTTYPE_LEVEL = reg_val;
-}
-
-static void dw_gpio_int_write_polarity(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_polarity)
-{
-	uint32_t reg_val;
-
-	reg_val = port->regs->INT_POLARITY;
-
-	reg_val &= (~bit_mask);
-	bit_polarity &= bit_mask;
-	reg_val |= bit_polarity;
-
-	port->regs->INT_POLARITY = reg_val;
-}
-
-static void dw_gpio_int_write_debounce(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_debounce)
-{
-	uint32_t reg_val;
-
-	reg_val = port->regs->DEBOUNCE;
-
-	reg_val &= (~bit_mask);
-	bit_debounce &= bit_mask;
-	reg_val |= bit_debounce;
-
-	port->regs->DEBOUNCE = reg_val;
-}
-
-static void dw_gpio_set_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg)
-{
-	dw_gpio_int_write_level(port, int_cfg->int_bit_mask, int_cfg->int_bit_type);
-	dw_gpio_int_write_polarity(port, int_cfg->int_bit_mask, int_cfg->int_bit_polarity);
-	dw_gpio_int_write_debounce(port, int_cfg->int_bit_mask, int_cfg->int_bit_debounce);
-}
-
-static void dw_gpio_get_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg)
-{
-	int_cfg->int_bit_type = dw_gpio_int_read_level(port) & int_cfg->int_bit_mask;
-	int_cfg->int_bit_polarity = dw_gpio_int_read_polarity(port) & int_cfg->int_bit_mask;
-	int_cfg->int_bit_debounce = dw_gpio_int_read_debounce(port) & int_cfg->int_bit_mask;
-}
-
-static void dw_gpio_write_dr(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val)
-{
-	uint32_t temp_reg;
-
-	temp_reg = port->regs->SWPORTS[port->no].DR;
-	temp_reg &= ~bit_mask;
-	val &= bit_mask;
-	temp_reg |= val;
-
-	port->regs->SWPORTS[port->no].DR = temp_reg;
-}
-
-static void dw_gpio_write_dir(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val)
-{
-	uint32_t temp_reg;
-
-	temp_reg = port->regs->SWPORTS[port->no].DDR;
-	temp_reg &= ~bit_mask;
-	val &= bit_mask;
-	temp_reg |= val;
-
-	port->regs->SWPORTS[port->no].DDR = temp_reg;
-}
-
-static uint32_t dw_gpio_read_val(DW_GPIO_PORT_PTR port)
-{
-	uint32_t val;
-
-	val = dw_gpio_read_ext(port) & (~dw_gpio_read_dir(port));
-	val |= dw_gpio_read_dr(port) & dw_gpio_read_dir(port);
-
-	return val;
-}
-
-/** @} end of group DEVICE_DW_GPIO_STATIC */
-
-/* interface for DEV_GPIO */
-/** Open designware gpio device with specified io direction configuration */
-int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir)
-{
-	int32_t ercd = E_OK;
-	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
-	/* END OF ERROR CHECK */
-
-	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
-	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
-
-	port_info_ptr->opn_cnt ++;
-	if (port_info_ptr->opn_cnt > 1) { /* opened before */
-		if (dir == port_info_ptr->direction) { /* direction is the same */
-			return E_OK;
-		} else { /* open with different direction */
-			return E_OPNED;
-		}
-	}
-
-	dw_gpio_write_dir(port, port->valid_bit_mask, dir);
-
-	if (port->no == DW_GPIO_PORT_A) {
-		dw_gpio_int_clear(port, DW_GPIO_MASK_ALL);
-		dw_gpio_int_disable(port, DW_GPIO_MASK_ALL);
-		dw_gpio_int_unmask(port, DW_GPIO_MASK_ALL);
-		/* install gpio interrupt handler */
-		int_handler_install(port->intno, port->int_handler);
-		int_disable(port->intno);
-		/** Set int type, int polarity and debounce configuration to default settings of device gpio */
-		dw_gpio_set_int_cfg(port, (DEV_GPIO_INT_CFG *)(&gpio_int_cfg_default));
-		port_info_ptr->method = dw_gpio_read_mthd(port);
-	} else {
-		port_info_ptr->method = DEV_GPIO_BITS_MTHD_DEFAULT;
-	}
-
-	dw_gpio_write_dr(port, port->valid_bit_mask, 0);
-
-	port_info_ptr->direction = dir;
-	port_info_ptr->extra = NULL;
-
-error_exit:
-	return ercd;
-}
-
-/** Close designware gpio device */
-int32_t dw_gpio_close(DEV_GPIO *gpio_obj)
-{
-	int32_t ercd = E_OK;
-	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
-	/* END OF ERROR CHECK */
-
-	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
-	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
-
-	DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_OK);
-
-	port_info_ptr->opn_cnt --;
-	if (port_info_ptr->opn_cnt == 0) {
-		dw_gpio_write_dr(port, port->valid_bit_mask, 0);
-		dw_gpio_write_dir(port, port->valid_bit_mask, 0);
-		if (port->no == DW_GPIO_PORT_A) {
-			dw_gpio_int_clear(port, DW_GPIO_MASK_ALL);
-			dw_gpio_int_disable(port, DW_GPIO_MASK_ALL);
-			int_disable(port->intno);
-		}
-
-		port_info_ptr->direction = 0;
-		port_info_ptr->method = 0;
-		port_info_ptr->extra = NULL;
-	} else {
-		ercd = E_OPNED;
-	}
-
-error_exit:
-	return ercd;
-}
-
-/** Read designware gpio device value */
-int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask)
-{
-	int32_t ercd = E_OK;
-	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
-	/* END OF ERROR CHECK */
-
-	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
-	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
-	DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
-
-	DW_GPIO_CHECK_EXP(val!=NULL, E_PAR);
-
-	//*val = dw_gpio_read_ext(port) & mask;
-	*val = dw_gpio_read_val(port) & mask;
-
-error_exit:
-	return ercd;
-}
-
-/** Write designware gpio device value */
-int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask)
-{
-	int32_t ercd = E_OK;
-	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
-	/* END OF ERROR CHECK */
-
-	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
-	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
-	DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
-
-	dw_gpio_write_dr(port, mask, val);
-
-error_exit:
-	return ercd;
-}
-
-/** Control designware gpio device */
-int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param)
-{
-	int32_t ercd = E_OK;
-	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
-	/* END OF ERROR CHECK */
-
-	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
-	DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
-	DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
-
-	uint32_t val32;	/** to receive unsigned int value */
-
-	if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_INPUT) {
-		val32 = (uint32_t)param;
-		dw_gpio_write_dir(port, val32, DW_GPIO_INPUT_ALL);
-		port_info_ptr->direction = dw_gpio_read_dir(port);
-	} else if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_OUTPUT) {
-		val32 = (uint32_t)param;
-		dw_gpio_write_dir(port, val32, DW_GPIO_OUTPUT_ALL);
-		port_info_ptr->direction = dw_gpio_read_dir(port);
-	} else if (ctrl_cmd == GPIO_CMD_GET_BIT_DIR) {
-		DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-		port_info_ptr->direction = dw_gpio_read_dir(port);
-		*((int32_t *)param) = port_info_ptr->direction;
-	} else {
-		DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT);
-		/* output pin cannot be used as interrupt */
-		DEV_GPIO_INT_CFG *gpio_int_cfg;
-		DEV_GPIO_BIT_ISR *port_bit_isr;
-
-		switch (ctrl_cmd) {
-			case GPIO_CMD_SET_BIT_INT_CFG:
-				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-				gpio_int_cfg = (DEV_GPIO_INT_CFG *)param;
-				dw_gpio_set_int_cfg(port, gpio_int_cfg);
-				break;
-			case GPIO_CMD_GET_BIT_INT_CFG:
-				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-				gpio_int_cfg = (DEV_GPIO_INT_CFG *)param;
-				/** read configuration, each bit stands for different configuration */
-				dw_gpio_get_int_cfg(port, gpio_int_cfg);
-				break;
-			case GPIO_CMD_SET_BIT_ISR:
-				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-				port_bit_isr = (DEV_GPIO_BIT_ISR *)param;
-				if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) {
-					port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs] = port_bit_isr->int_bit_handler;
-				} else {
-					ercd = E_PAR;
-				}
-				break;
-			case GPIO_CMD_GET_BIT_ISR:
-				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-				port_bit_isr = (DEV_GPIO_BIT_ISR *)param;
-				if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) {
-					port_bit_isr->int_bit_handler = port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs];
-				} else {
-					ercd = E_PAR;
-				}
-				break;
-			case GPIO_CMD_ENA_BIT_INT:
-				val32 = (uint32_t)param;
-				dw_gpio_int_enable(port, val32);
-				port_info_ptr->method = dw_gpio_read_mthd(port);
-				if (port_info_ptr->method) {
-					int_enable(port->intno);
-				}
-				break;
-			case GPIO_CMD_DIS_BIT_INT:
-				val32 = (uint32_t)param;
-				dw_gpio_int_disable(port, val32);
-				port_info_ptr->method = dw_gpio_read_mthd(port);
-				if (port_info_ptr->method == 0) {
-					int_disable(port->intno);
-				}
-				break;
-			case GPIO_CMD_GET_BIT_MTHD:
-				DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-				port_info_ptr->method = dw_gpio_read_mthd(port);
-				*((int32_t *)param) = port_info_ptr->method;
-				break;
-			default:
-				ercd = E_NOSPT;
-				break;
-		}
-	}
-error_exit:
-	return ercd;
-}
-
-/** designware gpio interrupt process */
-int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr)
-{
-	int32_t ercd = E_OK;
-	DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
-	/* END OF ERROR CHECK */
-
-	DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
-	DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT);
-
-	uint32_t i, gpio_bit_isr_state;
-	uint32_t max_int_bit_count = 0;
-
-	/** read interrupt status */
-	gpio_bit_isr_state = dw_gpio_int_read_status(port);
-
-	if (port->gpio_bit_isr) {
-		max_int_bit_count = (port->gpio_bit_isr->int_bit_max_cnt);
-	} else {
-		dw_gpio_int_clear(port, gpio_bit_isr_state);
-	}
-
-	for (i=0; i<max_int_bit_count; i++) {
-		if (gpio_bit_isr_state & (1<<i)) {
-			/* this bit interrupt enabled */
-			if (port->gpio_bit_isr->int_bit_handler_ptr[i]) {
-				port->gpio_bit_isr->int_bit_handler_ptr[i](gpio_obj);
-			}
-			dw_gpio_int_clear(port, (1<<i)); /** clear this bit interrupt */
-		}
-	}
-
-error_exit:
-	return ercd;
-}
diff --git a/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h b/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h
deleted file mode 100644
index c087975f82..0000000000
--- a/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-22
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \brief	designware gpio driver
- * \ingroup	DEVICE_DW_GPIO
- * \brief	Designware GPIO driver header file
- */
-
-#ifndef _DW_GPIO_H_
-#define _DW_GPIO_H_
-
-#include "device/device_hal/inc/dev_gpio.h"
-
-#include "inc/arc/arc_exception.h"
-
-#define DW_GPIO_PORT_A	(0x00)
-#define DW_GPIO_PORT_B	(0x01)
-#define DW_GPIO_PORT_C	(0x02)
-#define DW_GPIO_PORT_D	(0x03)
-
-#define DW_GPIO_INT_ACT_LOW			GPIO_INT_ACTIVE_LOW
-#define DW_GPIO_INT_ACT_HIGH			GPIO_INT_ACTIVE_HIGH
-
-#define DW_GPIO_INT_LEVEL_TRIG			GPIO_INT_LEVEL_TRIG
-#define DW_GPIO_INT_EDGE_TRIG			GPIO_INT_EDGE_TRIG
-
-#define DW_GPIO_INT_NO_DEBOUNCE			GPIO_INT_NO_DEBOUNCE
-#define DW_GPIO_INT_DEBOUNCE			GPIO_INT_DEBOUNCE
-
-#define DW_GPIO_ALL_ZERO			(0x0)
-#define DW_GPIO_ALL_ONE				(0xffffffff)
-#define DW_GPIO_MASK_ALL			(0xffffffff)
-#define DW_GPIO_INPUT_ALL			(0x0)
-#define DW_GPIO_OUTPUT_ALL			(0xffffffff)
-
-/**
- * \name	DesignWare GPIO Register Structure
- * \brief	contains definitions of DesignWare GPIO register structure.
- * @{
- */
-typedef struct port_ctrl {
-	uint32_t DR;
-	uint32_t DDR;
-	uint32_t CTRL;
-} PORT_CTRL;
-
-/* DW GPIO PORTS Registers */
-typedef volatile struct dw_gpio_reg {
-	PORT_CTRL SWPORTS[4];
-	uint32_t INTEN;		/*!< (0x30) */
-	uint32_t INTMASK;	/*!< (0x34) */
-	uint32_t INTTYPE_LEVEL;	/*!< (0x38) */
-	uint32_t INT_POLARITY;	/*!< (0x3c) */
-	uint32_t INTSTATUS;	/*!< (0x40) */
-	uint32_t RAW_INTSTATUS;	/*!< (0x44) */
-	uint32_t DEBOUNCE;	/*!< (0x48) */
-	uint32_t PORTA_EOI;	/*!< (0x4c) */
-	uint32_t EXT_PORTS[4];	/*!< (0x50) -A
-				     (0x54) -B
-				     (0x58) -C
-				     (0x5c) -D */
-	uint32_t LS_SYNC;	/*!< (0x60) */
-	uint32_t ID_CODE;	/*!< (0x64) */
-	uint32_t RESERVED_3;	/*!< (0x68) */
-	uint32_t VER_ID_CODE;	/*!< (0x6c) */
-	uint32_t CONFIG_REG2;	/*!< (0x70) */
-	uint32_t CONFIG_REG1;	/*!< (0x74) */
-} DW_GPIO_REG, *DW_GPIO_REG_PTR;
-/** @} */
-
-/** interrupt handler for each port bit */
-typedef struct dw_gpio_bit_isr {
-	uint32_t int_bit_max_cnt;		/*!< max bit count for each port */
-	DEV_GPIO_HANDLER *int_bit_handler_ptr;	/*!< interrupt handler pointer */
-} DW_GPIO_BIT_ISR, * DW_GPIO_BIT_ISR_PTR;
-
-/**
- * \brief	DesignWare GPIO control structure definition
- * \details	implement of dev_gpio_info::gpio_ctrl
- */
-typedef struct dw_gpio_port {
-	uint32_t no;				/*!< gpio port number */
-	DW_GPIO_REG_PTR	regs;			/*!< gpio port register */
-	uint32_t intno;				/*!< gpio interrupt vector number */
-	uint32_t valid_bit_mask;		/*!< valid bit mask of gpio port */
-	INT_HANDLER int_handler;		/*!< gpio interrupt handler */
-	DW_GPIO_BIT_ISR_PTR gpio_bit_isr;	/*!< gpio bit handler struct */
-} DW_GPIO_PORT, *DW_GPIO_PORT_PTR;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name	DesignWare GPIO Function Declaration
- * \brief	contains declarations of designware gpio functions.
- * \details	This are only used in gpio object implementation source file
- * @{
- */
-extern int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir);
-extern int32_t dw_gpio_close(DEV_GPIO *gpio_obj);
-extern int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask);
-extern int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask);
-extern int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param);
-extern int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-#endif /* _DW_GPIO_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic.c b/bsp/synopsys/embarc/device/designware/iic/dw_iic.c
deleted file mode 100644
index abef37ace2..0000000000
--- a/bsp/synopsys/embarc/device/designware/iic/dw_iic.c
+++ /dev/null
@@ -1,1584 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-06-30
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_DW_IIC	Designware IIC Driver
- * \ingroup	DEVICE_DW
- * \brief	Designware IIC Driver Implementation
- */
-
-/**
- * \file
- * \brief	Designware iic driver
- * \ingroup	DEVICE_DW_IIC
- */
-#include <string.h>
-
-#include "inc/embARC_toolchain.h"
-#include "inc/embARC_error.h"
-
-#include "inc/arc/arc_exception.h"
-
-#include "device/designware/iic/dw_iic_hal.h"
-#include "device/designware/iic/dw_iic.h"
-
-/** check expressions used in DesignWare IIC driver implementation */
-#define DW_IIC_CHECK_EXP(EXPR, ERROR_CODE)		CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
-
-#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
-/** valid check of iic info object */
-#define VALID_CHK_IIC_INFO_OBJECT(iicinfo_obj_ptr)		{			\
-			DW_IIC_CHECK_EXP((iicinfo_obj_ptr)!=NULL, E_OBJ);		\
-			DW_IIC_CHECK_EXP(((iicinfo_obj_ptr)->iic_ctrl)!=NULL, E_OBJ);	\
- 		}
-#endif
-
-/**
- * \name	DesignWare IIC Interrupt Callback Routine Select Marcos
- * \brief	DesignWare IIC interrupt callback routines select macros definitions
- * @{
- */
-#define DW_IIC_RDY_SND					(1U)	/*!< ready to send callback */
-#define DW_IIC_RDY_RCV					(2U)	/*!< ready to receive callback */
-/** @} */
-
-/**
- * \defgroup	DEVICE_DW_IIC_STATIC	DesignWare IIC Driver Static Functions
- * \ingroup	DEVICE_DW_IIC
- * \brief	Static or inline functions, variables for DesignWare IIC handle iic operations,
- * 	only used in this file.
- * @{
- */
-/** Disable designware iic device */
-Inline void dw_iic_disable(DW_IIC_REG *iic_reg_ptr)
-{
-	iic_reg_ptr->IC_ENABLE = DW_IIC_DISABLE;
-}
-/** Enable designware iic device */
-Inline void dw_iic_enable(DW_IIC_REG *iic_reg_ptr)
-{
-	iic_reg_ptr->IC_ENABLE = DW_IIC_ENABLE;
-}
-
-/** Clear all designware iic interrupt */
-Inline void dw_iic_clear_interrupt_all(DW_IIC_REG *iic_reg_ptr)
-{
-	(void)iic_reg_ptr->IC_CLR_INTR;
-}
-
-/** test whether iic is ready to write, 1 ready, 0 not ready */
-Inline int32_t dw_iic_putready(DW_IIC_REG *iic_reg_ptr)
-{
-	return ((iic_reg_ptr->IC_STATUS & IC_STATUS_TFNF) != 0);
-}
-/** test whether iic is ready to receive, 1 ready, 0 not ready */
-Inline int32_t dw_iic_getready(DW_IIC_REG *iic_reg_ptr)
-{
-	return ((iic_reg_ptr->IC_STATUS & IC_STATUS_RFNE) != 0);
-}
-/** Write data into IIC TX FIFO with STOP/RESTART Condition, and R/W bit */
-Inline void dw_iic_putdata(DW_IIC_REG *iic_reg_ptr, uint32_t data)
-{
-	iic_reg_ptr->IC_DATA_CMD = data;
-}
-
-/** Read Data from IIC RX FIFO */
-Inline uint32_t dw_iic_getdata(DW_IIC_REG *iic_reg_ptr)
-{
-	return (iic_reg_ptr->IC_DATA_CMD) & 0xff;
-}
-
-/** Enable designware iic bit interrupt with mask */
-Inline void dw_iic_unmask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask)
-{
-	iic_reg_ptr->IC_INTR_MASK |= mask;
-}
-
-/** Disable designware iic bit interrupt with mask */
-Inline void dw_iic_mask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask)
-{
-	iic_reg_ptr->IC_INTR_MASK &= ~mask;
-}
-
-/** Get TX FIFO Length */
-Inline uint32_t dw_iic_get_txfifo_len(DW_IIC_REG *iic_reg_ptr)
-{
-	uint32_t txfifolen;
-
-	txfifolen = ((iic_reg_ptr->IC_COMP_PARAM_1 >> 16) & 0xff) + 1;
-
-	return txfifolen;
-}
-
-/** Get RX FIFO Length */
-Inline uint32_t dw_iic_get_rxfifo_len(DW_IIC_REG *iic_reg_ptr)
-{
-	uint32_t rxfifolen;
-
-	rxfifolen = ((iic_reg_ptr->IC_COMP_PARAM_1 >> 8) & 0xff) + 1;
-
-	return rxfifolen;
-}
-
-/** Set designware iic transfer in 7bit of 10bit addressing mode as a master */
-Inline void dw_iic_set_mstaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode)
-{
-#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
-	if (mode == IIC_7BIT_ADDRESS) {
-		iic_reg_ptr->IC_TAR &= ~IC_10BITADDR_MASTER;
-	} else {
-		iic_reg_ptr->IC_TAR |= IC_10BITADDR_MASTER;
-	}
-#else
-	dw_iic_disable(iic_reg_ptr);
-	if (mode == IIC_7BIT_ADDRESS) {
-		iic_reg_ptr->IC_CON &= ~MST_10_BIT_ADDR_MODE;
-	} else {
-		iic_reg_ptr->IC_CON |= MST_10_BIT_ADDR_MODE;
-	}
-	dw_iic_enable(iic_reg_ptr);
-#endif
-}
-
-/** Set designware iic transfer in 7bit of 10bit addressing mode as a slave */
-Inline void dw_iic_set_slvaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode)
-{
-	dw_iic_disable(iic_reg_ptr);
-	if (mode == IIC_7BIT_ADDRESS) {
-		iic_reg_ptr->IC_CON &= ~SLV_10_BIT_ADDR_MODE;
-	} else {
-		iic_reg_ptr->IC_CON |= SLV_10_BIT_ADDR_MODE;
-	}
-	dw_iic_enable(iic_reg_ptr);
-}
-
-/** Set designware iic transfer target address for addressing any iic slave device as a master */
-Inline void dw_iic_set_taraddr(DW_IIC_REG *iic_reg_ptr, uint32_t address)
-{
-#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
-	iic_reg_ptr->IC_TAR &= ~(IC_TAR_10BIT_ADDR_MASK);
-	iic_reg_ptr->IC_TAR |= (IC_TAR_10BIT_ADDR_MASK & address);
-#else
-	dw_iic_disable(iic_reg_ptr);
-	iic_reg_ptr->IC_TAR &= ~(IC_TAR_10BIT_ADDR_MASK);
-	iic_reg_ptr->IC_TAR |= (IC_TAR_10BIT_ADDR_MASK & address);
-	dw_iic_enable(iic_reg_ptr);
-#endif
-}
-
-/** Set designware iic slave address as a slave */
-Inline void dw_iic_set_slvaddr(DW_IIC_REG *iic_reg_ptr, uint32_t address)
-{
-	dw_iic_disable(iic_reg_ptr);
-	iic_reg_ptr->IC_SAR &= ~(IC_SAR_10BIT_ADDR_MASK);
-	iic_reg_ptr->IC_SAR |= (IC_SAR_10BIT_ADDR_MASK & address);
-	dw_iic_enable(iic_reg_ptr);
-}
-
-/** Select speed mode, and return proper speed mode configuration */
-Inline uint32_t dw_iic_select_speedmode(uint32_t speedmode)
-{
-	uint32_t speedcfg;
-
-	if (speedmode == IIC_SPEED_STANDARD) {
-		speedcfg = IC_CON_SPEED_STANDARD;
-	} else if (speedmode == IIC_SPEED_FAST) {
-		speedcfg = IC_CON_SPEED_FAST;
-	} else if (speedmode == IIC_SPEED_FASTPLUS) {
-		speedcfg = IC_CON_SPEED_FAST;
-	} else if (speedmode == IIC_SPEED_HIGH) {
-		speedcfg = IC_CON_SPEED_HIGH;
-	} else {
-		speedcfg = IC_CON_SPEED_HIGH;
-	}
-	return speedcfg;
-}
-/** Set designware iic speed mode */
-Inline void dw_iic_set_speedmode(DW_IIC_REG *iic_reg_ptr, uint32_t speedmode)
-{
-	uint32_t ic_con_val;
-
-	dw_iic_disable(iic_reg_ptr);
-	ic_con_val = iic_reg_ptr->IC_CON & (~IC_CON_SPEED_MASK);
-	ic_con_val |= dw_iic_select_speedmode(speedmode);
-	iic_reg_ptr->IC_CON = ic_con_val;
-	dw_iic_enable(iic_reg_ptr);
-}
-
-/** Set designware working mode as master or slave */
-Inline void dw_iic_set_working_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode)
-{
-	uint32_t ic_con_val;
-	dw_iic_disable(iic_reg_ptr);
-	ic_con_val = iic_reg_ptr->IC_CON & (~IC_CON_MST_SLV_MODE_MASK);
-	if (mode == DEV_MASTER_MODE) {
-		ic_con_val |= IC_CON_ENA_MASTER_MODE;
-	} else {
-		ic_con_val |= IC_CON_ENA_SLAVE_MODE;
-	}
-	dw_iic_enable(iic_reg_ptr);
-}
-
-/** Set IC_CLK frequency by configuration the *CNT registers for different speed modes */
-Inline void dw_iic_set_scl_cnt(DW_IIC_REG *iic_reg_ptr, DW_IIC_SCL_CNT *scl_cnt)
-{
-	dw_iic_disable(iic_reg_ptr);
-	iic_reg_ptr->IC_SS_SCL_HCNT = scl_cnt->ss_scl_hcnt;
-	iic_reg_ptr->IC_SS_SCL_LCNT = scl_cnt->ss_scl_lcnt;
-	iic_reg_ptr->IC_FS_SCL_HCNT = scl_cnt->fs_scl_hcnt;
-	iic_reg_ptr->IC_FS_SCL_LCNT = scl_cnt->fs_scl_lcnt;
-	iic_reg_ptr->IC_HS_SCL_HCNT = scl_cnt->hs_scl_hcnt;
-	iic_reg_ptr->IC_HS_SCL_LCNT = scl_cnt->hs_scl_lcnt;
-	dw_iic_enable(iic_reg_ptr);
-}
-
-/** Set spike suppression configuration */
-Inline void dw_iic_set_spike_len(DW_IIC_REG *iic_reg_ptr, DW_IIC_SPKLEN *spklen)
-{
-	dw_iic_disable(iic_reg_ptr);
-	iic_reg_ptr->IC_FS_SPKLEN = spklen->fs_spklen;
-	iic_reg_ptr->IC_HS_SPKLEN = spklen->hs_spklen;
-	dw_iic_enable(iic_reg_ptr);
-}
-
-Inline void dw_iic_flush_tx(DW_IIC_REG *iic_reg_ptr)
-{
-	(void)iic_reg_ptr->IC_CLR_INTR;
-}
-
-Inline void dw_iic_flush_rx(DW_IIC_REG *iic_reg_ptr)
-{
-}
-
-static uint32_t dw_iic_get_slv_state(DW_IIC_REG *iic_reg_ptr)
-{
-	uint32_t status;
-	uint32_t slv_state = IIC_SLAVE_STATE_FREE;
-
-	status = iic_reg_ptr->IC_RAW_INTR_STAT;
-	if (status & IC_INTR_STAT_GEN_CALL) {
-	/* General Call address is received and it is acknowledged */
-		slv_state |= IIC_SLAVE_STATE_GC_REQ;
-	}
-	if (status & IC_INTR_STAT_RX_FULL) {
-	/* master is attempting to write data to this slave */
-		slv_state |= IIC_SLAVE_STATE_WR_REQ;
-	}
-	if (status & IC_INTR_STAT_RD_REQ) {
-	/* master is attempting to read data from this slave */
-		slv_state |= IIC_SLAVE_STATE_RD_REQ;
-	}
-	if (status & IC_INTR_STAT_RX_DONE) {
-	/* master does not acknowledge a transmitted byte, and transmission is done */
-		slv_state |= IIC_SLAVE_STATE_RD_DONE;
-		status = iic_reg_ptr->IC_CLR_RX_DONE;
-	}
-	if (status & IC_INTR_STAT_START_DET) {
-	/* a START or RESTART condition has occurred */
-		slv_state |= IIC_SLAVE_STATE_START;
-		status = iic_reg_ptr->IC_CLR_START_DET; /* Clear it when read */
-	}
-	if (status & IC_INTR_STAT_STOP_DET) {
-	/* a STOP condition has occurred */
-		slv_state |= IIC_SLAVE_STATE_STOP;
-		status = iic_reg_ptr->IC_CLR_STOP_DET;  /* Clear it when read */
-	}
-	if (status & (IC_INTR_STAT_TX_ABRT|IC_INTR_STAT_TX_OVER\
-		|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
-	/* error case */
-		slv_state |= IIC_SLAVE_STATE_ERROR;
-		status = iic_reg_ptr->IC_CLR_TX_ABRT;  /* Clear it when read */
-		status = iic_reg_ptr->IC_CLR_TX_OVER;
-		status = iic_reg_ptr->IC_CLR_RX_OVER;
-		status = iic_reg_ptr->IC_CLR_RX_UNDER;
-	}
-
-	return slv_state;
-}
-
-/** Init Designware IIC Device into Master mode */
-static void dw_iic_master_init(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t speed_mode, uint32_t addr_mode, uint32_t tar_addr)
-{
-	uint32_t ic_con_val = 0;
-	DW_IIC_REG *iic_reg_ptr = iic_ctrl_ptr->dw_iic_regs;
-
-	dw_iic_disable(iic_reg_ptr);
-
-	/* disable all iic interrupt */
-	iic_reg_ptr->IC_INTR_MASK = IC_INT_DISABLE_ALL;
-
-	/* Set to 7bit addressing and update target address */
-	iic_reg_ptr->IC_TAR = (tar_addr & IC_TAR_10BIT_ADDR_MASK) | IC_TAR_SPECIAL | IC_TAR_GC_OR_START;
-	/* master mode, restart enabled */
-	ic_con_val = dw_iic_select_speedmode(speed_mode) | IC_CON_ENA_MASTER_MODE | IC_CON_RESTART_EN;
-
-#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
-	if (addr_mode == IIC_10BIT_ADDRESS) {
-		iic_reg_ptr->IC_TAR |= MST_10_BIT_ADDR_MODE;
-	}
-#else
-	if (addr_mode == IIC_10BIT_ADDRESS) {
-		ic_con_val |= MST_10_BIT_ADDR_MODE;
-	}
-#endif
-	/* Set final IC_CON value */
-	iic_reg_ptr->IC_CON = ic_con_val;
-	/* FIFO threshold settings */
-	iic_reg_ptr->IC_TX_TL = IIC_TX_THRESHOLD;
-	iic_reg_ptr->IC_RX_TL = IIC_RX_THRESHOLD;
-	/* Master code settings */
-	iic_reg_ptr->IC_HS_MADDR = iic_ctrl_ptr->iic_master_code;
-	dw_iic_enable(iic_reg_ptr);
-
-	/* Clock Settings */
-	dw_iic_set_scl_cnt(iic_reg_ptr, &(iic_ctrl_ptr->iic_scl_cnt));
-	dw_iic_set_spike_len(iic_reg_ptr, &(iic_ctrl_ptr->iic_spklen));
-}
-
-/** Init Designware IIC Device into Slave mode */
-static void dw_iic_slave_init(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t addr_mode, uint32_t slv_addr)
-{
-	uint32_t ic_con_val = 0;
-	DW_IIC_REG *iic_reg_ptr = iic_ctrl_ptr->dw_iic_regs;
-
-	dw_iic_disable(iic_reg_ptr);
-
-	/* disable all iic interrupt */
-	iic_reg_ptr->IC_INTR_MASK = IC_INT_DISABLE_ALL;
-
-	/* Set slave device address as a slave */
-	iic_reg_ptr->IC_SAR = slv_addr & IC_SAR_10BIT_ADDR_MASK;
-	/* slave mode, 7 bit slave address */
-	ic_con_val = IC_CON_ENA_SLAVE_MODE;
-	/* If addr mode select to be 10 bit address mode */
-	if (addr_mode == IIC_10BIT_ADDRESS) {
-		ic_con_val |= SLV_10_BIT_ADDR_MODE;
-	}
-
-	/* Set final IC_CON value */
-	iic_reg_ptr->IC_CON = ic_con_val;
-	/* FIFO threshold settings */
-	iic_reg_ptr->IC_TX_TL = IIC_TX_THRESHOLD;
-	iic_reg_ptr->IC_RX_TL = IIC_RX_THRESHOLD;
-
-	dw_iic_enable(iic_reg_ptr);
-}
-
-/** Check error for IIC master device */
-static int32_t dw_iic_mst_chkerr(DW_IIC_CTRL *iic_ctrl_ptr)
-{
-	uint32_t status;
-	int32_t ercd = IIC_ERR_NONE;
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	status = iic_reg_ptr->IC_RAW_INTR_STAT;
-	if (status & IC_INTR_STAT_TX_ABRT) {
-		status = iic_reg_ptr->IC_TX_ABRT_SOURCE;
-		if (status & IIC_MST_ABRT_LOST_BUS) {
-			ercd = IIC_ERR_LOST_BUS;
-		} else if (status & IIC_MST_ABRT_ADDR_NOACK) {
-			ercd = IIC_ERR_ADDR_NOACK;
-		} else if (status & IIC_MST_ABRT_DATA_NOACK) {
-			ercd = IIC_ERR_DATA_NOACK;
-		} else {
-			ercd = IIC_ERR_UNDEF;
-		}
-		status = iic_reg_ptr->IC_CLR_TX_ABRT;
-	} else {
-		if (status & IC_INTR_STAT_TX_OVER) {
-			iic_ctrl_ptr->iic_tx_over ++;
-			status = iic_reg_ptr->IC_CLR_TX_OVER;
-		}
-		if (status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
-			iic_ctrl_ptr->iic_rx_over ++;
-			status = iic_reg_ptr->IC_CLR_RX_OVER;
-			status = iic_reg_ptr->IC_CLR_RX_UNDER;
-		}
-	}
-	return ercd;
-}
-
-/** Check error for IIC slave device */
-static int32_t dw_iic_slv_chkerr(DW_IIC_CTRL *iic_ctrl_ptr)
-{
-	uint32_t status;
-	int32_t ercd = IIC_ERR_NONE;
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	status = iic_reg_ptr->IC_RAW_INTR_STAT;
-	if (status & IC_INTR_STAT_TX_ABRT) {
-		status = iic_reg_ptr->IC_TX_ABRT_SOURCE;
-		if (status & IIC_SLV_ABRT_LOST_BUS) {
-			ercd = IIC_ERR_LOST_BUS;
-		} else if (status & IC_TX_ABRT_SLVFLUSH_TXFIFO) {
-			/* Flush tx fifo */
-			status = iic_reg_ptr->IC_TX_ABRT_SOURCE;
-		} else {
-			ercd = IIC_ERR_UNDEF;
-		}
-		status = iic_reg_ptr->IC_CLR_TX_ABRT;
-	} else {
-		if (status & IC_INTR_STAT_TX_OVER) {
-			iic_ctrl_ptr->iic_tx_over ++;
-			status = iic_reg_ptr->IC_CLR_TX_OVER;
-		}
-		if (status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
-			iic_ctrl_ptr->iic_rx_over ++;
-			status = iic_reg_ptr->IC_CLR_RX_OVER;
-			status = iic_reg_ptr->IC_CLR_RX_UNDER;
-		}
-	}
-	return ercd;
-}
-
-/** enable designware iic */
-static void dw_iic_enable_device(DEV_IIC_INFO *iic_info_ptr)
-{
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	if ((iic_info_ptr->status & DEV_ENABLED) == 0) {
-		dw_iic_enable(iic_reg_ptr);
-		iic_info_ptr->status |= DEV_ENABLED;
-	}
-}
-
-/** disable designware iic */
-static void dw_iic_disable_device(DEV_IIC_INFO *iic_info_ptr)
-{
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-	uint32_t i;
-
-	for (i=0; i<DW_IIC_DISABLE_MAX_T_POLL_CNT; i++) {
-		dw_iic_disable(iic_reg_ptr);
-		if ((iic_reg_ptr->IC_ENABLE_STATUS & IC_ENABLE_STATUS_IC_EN) == 0) {
-			break;
-		}
-	}
-	iic_info_ptr->status &= ~DEV_ENABLED;
-}
-
-static void dw_iic_reset_device(DEV_IIC_INFO *iic_info_ptr)
-{
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	dw_iic_disable_device(iic_info_ptr);
-	dw_iic_clear_interrupt_all(iic_reg_ptr);
-	iic_info_ptr->next_cond = IIC_MODE_STOP;
-	iic_info_ptr->cur_state = IIC_FREE;
-	iic_info_ptr->err_state = IIC_ERR_NONE;
-	iic_ctrl_ptr->iic_tx_over = 0;
-	iic_ctrl_ptr->iic_rx_over = 0;
-	dw_iic_enable_device(iic_info_ptr);
-}
-
-/** Disable iic master interrupt for transmit or receive */
-static void dw_iic_mst_dis_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn)
-{
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	switch (cbrtn) {
-		case DW_IIC_RDY_SND:
-			dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_MST_TX_ENABLE);
-			iic_ctrl_ptr->int_status &= ~DW_IIC_TXINT_ENABLE;
-			break;
-		case DW_IIC_RDY_RCV:
-			dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_MST_RX_ENABLE);
-			iic_ctrl_ptr->int_status &= ~DW_IIC_RXINT_ENABLE;
-			break;
-		default:
-			break;
-	}
-}
-
-/** Disable iic slave interrupt for transmit or receive */
-static void dw_iic_slv_dis_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn)
-{
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	switch (cbrtn) {
-		case DW_IIC_RDY_SND:
-			dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_SLV_TX_ENABLE);
-			iic_ctrl_ptr->int_status &= ~DW_IIC_TXINT_ENABLE;
-			break;
-		case DW_IIC_RDY_RCV:
-			dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_SLV_RX_ENABLE);
-			iic_ctrl_ptr->int_status &= ~DW_IIC_RXINT_ENABLE;
-			break;
-		default:
-			break;
-	}
-}
-
-/** Enable iic master interrupt for transmit or receive */
-static void dw_iic_mst_ena_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn)
-{
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	switch (cbrtn) {
-		case DW_IIC_RDY_SND:
-			iic_ctrl_ptr->int_status |= DW_IIC_TXINT_ENABLE;
-			dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_MST_TX_ENABLE);
-			break;
-		case DW_IIC_RDY_RCV:
-			iic_ctrl_ptr->int_status |= DW_IIC_RXINT_ENABLE;
-			dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_MST_RX_ENABLE);
-			break;
-		default:
-			break;
-	}
-}
-
-/** Enable iic slave interrupt for transmit or receive */
-static void dw_iic_slv_ena_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn)
-{
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	switch (cbrtn) {
-		case DW_IIC_RDY_SND:
-			iic_ctrl_ptr->int_status |= DW_IIC_TXINT_ENABLE;
-			dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_SLV_TX_ENABLE);
-			break;
-		case DW_IIC_RDY_RCV:
-			iic_ctrl_ptr->int_status |= DW_IIC_RXINT_ENABLE;
-			dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_SLV_RX_ENABLE);
-			break;
-		default:
-			break;
-	}
-}
-
-/**
- * \brief	disable designware iic send or receive interrupt
- * \param[in]	DEV_IIC_INFO 	*iic_info_ptr
- * \param[in]	cbrtn		control code of callback routine of send or receive
- */
-static void dw_iic_dis_cbr(DEV_IIC_INFO *iic_info_ptr, uint32_t cbrtn)
-{
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-
-	if (iic_info_ptr->mode == DEV_MASTER_MODE) {
-		dw_iic_mst_dis_cbr(iic_ctrl_ptr, cbrtn);
-	} else {
-		dw_iic_slv_dis_cbr(iic_ctrl_ptr, cbrtn);
-	}
-
-	if (iic_ctrl_ptr->int_status & DW_IIC_GINT_ENABLE) {
-		if ((iic_ctrl_ptr->int_status & (DW_IIC_RXINT_ENABLE|DW_IIC_TXINT_ENABLE)) == 0) {
-			int_disable(iic_ctrl_ptr->intno);
-			iic_ctrl_ptr->int_status &= ~DW_IIC_GINT_ENABLE;
-		}
-	}
-}
-
-/**
- * \brief	enable DesignWare IIC send or receive interrupt
- * \param[in]	DEV_IIC_INFO 	*iic_info_ptr
- * \param[in]	cbrtn		control code of callback routine of send or receive
- */
-static void dw_iic_ena_cbr(DEV_IIC_INFO *iic_info_ptr, uint32_t cbrtn)
-{
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-
-	if (iic_info_ptr->mode == DEV_MASTER_MODE) {
-		dw_iic_mst_ena_cbr(iic_ctrl_ptr, cbrtn);
-	} else {
-		dw_iic_slv_ena_cbr(iic_ctrl_ptr, cbrtn);
-	}
-
-	if ((iic_ctrl_ptr->int_status & DW_IIC_GINT_ENABLE) == 0) {
-		if (iic_ctrl_ptr->int_status & (DW_IIC_RXINT_ENABLE|DW_IIC_TXINT_ENABLE)) {
-			iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE;
-			int_enable(iic_ctrl_ptr->intno);
-		}
-	}
-}
-
-/**
- * \brief	enable designware iic interrupt
- * \param	iic_info_ptr	iic information structure pointer
- */
-static void dw_iic_enable_interrupt(DEV_IIC_INFO *iic_info_ptr)
-{
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-
-	int_handler_install(iic_ctrl_ptr->intno, iic_ctrl_ptr->dw_iic_int_handler);
-	iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE;
-	int_enable(iic_ctrl_ptr->intno);	/** enable iic interrupt */
-}
-/**
- * \brief	disable designware iic interrupt
- * \param	iic_info_ptr	iic information structure pointer
- */
-static void dw_iic_disable_interrupt(DEV_IIC_INFO *iic_info_ptr)
-{
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-
-	/** disable iic send&receive interrupt after disable iic interrupt */
-	dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
-	dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
-	/* disable iic interrupt */
-	int_disable(iic_ctrl_ptr->intno);
-	iic_ctrl_ptr->int_status &= ~(DW_IIC_GINT_ENABLE|DW_IIC_TXINT_ENABLE|DW_IIC_RXINT_ENABLE);
-}
-
-/** abort current interrupt transmit transfer */
-static void dw_iic_abort_tx(DEV_IIC *iic_obj)
-{
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-
-	if (iic_ctrl_ptr->int_status & DW_IIC_TXINT_ENABLE) {
-		dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
-		iic_info_ptr->status |= DEV_IN_TX_ABRT;
-		if (iic_info_ptr->iic_cbs.tx_cb != NULL) {
-			iic_info_ptr->iic_cbs.tx_cb(iic_obj);
-		}
-		iic_info_ptr->status &= ~(DEV_IN_TX_ABRT);
-	}
-}
-
-/** abort current interrupt receive transfer */
-static void dw_iic_abort_rx(DEV_IIC *iic_obj)
-{
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-
-	if (iic_ctrl_ptr->int_status & DW_IIC_RXINT_ENABLE) {
-		dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
-		iic_info_ptr->status |= DEV_IN_RX_ABRT;
-		if (iic_info_ptr->iic_cbs.rx_cb != NULL) {
-			iic_info_ptr->iic_cbs.rx_cb(iic_obj);
-		}
-		iic_info_ptr->status &= ~(DEV_IN_RX_ABRT);
-	}
-}
-
-/** Get available transmit fifo count */
-static int32_t dw_iic_get_txavail(DW_IIC_CTRL *iic_ctrl_ptr)
-{
-	int32_t tx_avail = 0;
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	if (iic_ctrl_ptr->tx_fifo_len <= 1) {
-		if (dw_iic_putready(iic_reg_ptr) == 1) {
-			tx_avail = 1;
-		} else {
-			tx_avail = 0;
-		}
-	} else {
-		tx_avail = iic_ctrl_ptr->tx_fifo_len - iic_reg_ptr->IC_TXFLR;
-	}
-	return tx_avail;
-}
-
-/** Get available receive fifo count */
-static int32_t dw_iic_get_rxavail(DW_IIC_CTRL *iic_ctrl_ptr)
-{
-	int32_t rx_avail = 0;
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	if (iic_ctrl_ptr->rx_fifo_len <= 1) {
-		if (dw_iic_getready(iic_reg_ptr) == 1) {
-			rx_avail = 1;
-		} else {
-			rx_avail = 0;
-		}
-	} else {
-		rx_avail = iic_reg_ptr->IC_RXFLR;
-	}
-	return rx_avail;
-}
-
-/**
- * IIC Master device transmit 1 data,
- * next_cond can be \ref IC_DATA_CMD_STOP,
- * \ref IC_DATA_CMD_RESTART and ref IC_DATA_CMD_NONE
- */
-static int32_t dw_iic_mst_write_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t data, uint32_t next_cond)
-{
-	uint32_t i = 0;
-	int32_t ercd = IIC_ERR_NONE;
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	while (dw_iic_putready(iic_reg_ptr) == 0) {
-		if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT;
-		ercd = dw_iic_mst_chkerr(iic_ctrl_ptr);
-		if (ercd != IIC_ERR_NONE) return ercd;
-	}
-	dw_iic_putdata(iic_reg_ptr, data|IC_DATA_CMD_WRITE_REQ|next_cond);
-
-	return ercd;
-}
-
-/** IIC Slave device transmit 1 data */
-static int32_t dw_iic_slv_write_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t data)
-{
-	uint32_t i = 0;
-	int32_t ercd = IIC_ERR_NONE;
-	uint32_t slv_state, temp;
-	uint32_t ready2send = 0;
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	for (i = 0; i < iic_ctrl_ptr->retry_cnt; i++) {
-		ercd = dw_iic_slv_chkerr(iic_ctrl_ptr);
-		if (ercd != IIC_ERR_NONE) return ercd;
-		slv_state = iic_reg_ptr->IC_RAW_INTR_STAT;
-		if (slv_state & IC_INTR_STAT_RD_REQ) {
-			if (dw_iic_putready(iic_reg_ptr)) {
-				temp = iic_reg_ptr->IC_CLR_RD_REQ;
-				ready2send = 1;
-				break;
-			}
-		} else if (slv_state & IC_INTR_STAT_RX_DONE) { /* Put RX Done before STOP */
-			temp = iic_reg_ptr->IC_CLR_RX_DONE;
-			return IIC_ERR_MSTSTOP;
-		} else if (slv_state & IC_INTR_STAT_STOP_DET) {
-			temp = iic_reg_ptr->IC_CLR_STOP_DET;
-			return IIC_ERR_MSTSTOP;
-		}
-	}
-	if (ready2send) {
-		dw_iic_putdata(iic_reg_ptr, data|IC_DATA_CMD_WRITE_REQ);
-	} else {
-		ercd = IIC_ERR_TIMEOUT;
-	}
-
-	return ercd;
-}
-
-/**
- * IIC Master device receive 1 data,
- * next_cond can be \ref IC_DATA_CMD_STOP,
- * \ref IC_DATA_CMD_RESTART and ref IC_DATA_CMD_NONE
- */
-static int32_t dw_iic_mst_read_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t *data, uint32_t next_cond)
-{
-	uint32_t i = 0;
-	int32_t ercd = IIC_ERR_NONE;
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	/* Issue a read request */
-	while (dw_iic_putready(iic_reg_ptr) == 0) {
-		if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT;
-		ercd = dw_iic_mst_chkerr(iic_ctrl_ptr);
-		if (ercd != IIC_ERR_NONE) return ercd;
-	}
-	dw_iic_putdata(iic_reg_ptr, next_cond|IC_DATA_CMD_READ_REQ);
-	/* Wait to read data */
-	i = 0;
-	while (dw_iic_getready(iic_reg_ptr) == 0) {
-		if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT;
-		ercd = dw_iic_mst_chkerr(iic_ctrl_ptr);
-		if (ercd != IIC_ERR_NONE) return ercd;
-	}
-	*data = dw_iic_getdata(iic_reg_ptr);
-	return ercd;
-}
-
-/** IIC Slave device receive 1 data */
-static int32_t dw_iic_slv_read_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t *data)
-{
-	uint32_t i = 0;
-	int32_t ercd = IIC_ERR_NONE;
-	uint32_t slv_state, temp;
-	uint32_t ready2read = 0;
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	for (i = 0; i < iic_ctrl_ptr->retry_cnt; i++) {
-		ercd = dw_iic_slv_chkerr(iic_ctrl_ptr);
-		if (ercd != IIC_ERR_NONE) return ercd;
-		slv_state = iic_reg_ptr->IC_RAW_INTR_STAT;
-		if (slv_state & IC_INTR_STAT_START_DET) {
-			temp = iic_reg_ptr->IC_CLR_START_DET;
-		}
-		if (slv_state & IC_INTR_STAT_RX_FULL) {
-			if (dw_iic_getready(iic_reg_ptr)) {
-				ready2read = 1;
-				break;
-			}
-		} else if (slv_state & IC_INTR_STAT_STOP_DET) {
-			temp = iic_reg_ptr->IC_CLR_STOP_DET;
-			return IIC_ERR_MSTSTOP;
-		}
-	}
-	if (ready2read) {
-		*data = dw_iic_getdata(iic_reg_ptr);
-	} else {
-		ercd = IIC_ERR_TIMEOUT;
-	}
-
-	return ercd;
-}
-
-/** IIC Master transmit called in interrupt */
-static void dw_iic_mst_int_write(DEV_IIC *iic_obj)
-{
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs);
-	uint32_t iic_int_status; /** iic interrupt status */
-	uint32_t last_cond, xmit_data, xmit_end = 0;
-	DEV_BUFFER *buf_ptr;
-	uint8_t *p_charbuf;
-
-	if (iic_info_ptr->next_cond == IIC_MODE_STOP) {
-		last_cond = IC_DATA_CMD_STOP;
-	} else {
-		last_cond = IC_DATA_CMD_RESTART;
-	}
-	iic_int_status = (iic_reg_ptr->IC_INTR_STAT);
-	buf_ptr = &(iic_info_ptr->tx_buf);
-	p_charbuf = (uint8_t *)buf_ptr->buf;
-	if (p_charbuf) {
-		if (iic_int_status & IC_INTR_STAT_TX_EMPTY) {
-			xmit_end = 0;
-			while (dw_iic_putready(iic_reg_ptr)) {
-				xmit_data = (uint32_t)(p_charbuf[buf_ptr->ofs])|IC_DATA_CMD_WRITE_REQ;
-				if (buf_ptr->ofs == (buf_ptr->len-1)) {
-					xmit_end = 1;
-					xmit_data |= last_cond;
-				} else {
-					xmit_data |= IC_DATA_CMD_NONE;
-				}
-				buf_ptr->ofs ++;
-				dw_iic_putdata(iic_reg_ptr, xmit_data);
-				if (xmit_end) {
-					dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
-					iic_info_ptr->cur_state = IIC_FREE;
-					if (iic_info_ptr->iic_cbs.tx_cb) {
-						iic_info_ptr->iic_cbs.tx_cb(iic_obj);
-					}
-					/* clear the send buffer pointer */
-					memset(buf_ptr, 0, sizeof(DEV_BUFFER));
-					break;
-				}
-			}
-		}
-		if (iic_int_status & IC_INTR_STAT_TX_OVER) {
-			iic_ctrl_ptr->iic_tx_over ++;
-		}
-		if (iic_int_status & IC_INTR_STAT_TX_ABRT) {
-			iic_info_ptr->err_state = dw_iic_mst_chkerr(iic_ctrl_ptr);
-			if (iic_info_ptr->err_state != IIC_ERR_NONE) {
-				dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
-				iic_info_ptr->cur_state = IIC_FREE;
-				if (iic_info_ptr->iic_cbs.err_cb) {
-					iic_info_ptr->iic_cbs.err_cb(iic_obj);
-				}
-				/* clear the send buffer pointer */
-				memset(buf_ptr, 0, sizeof(DEV_BUFFER));
-			}
-		}
-	} else {
-		dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
-		iic_info_ptr->cur_state = IIC_FREE;
-	}
-	/* Clear Interrupt */
-	iic_int_status = iic_reg_ptr->IC_CLR_INTR;
-}
-
-/** IIC Master receive called in interrupt */
-static void dw_iic_mst_int_read(DEV_IIC *iic_obj)
-{
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs);
-	uint32_t iic_int_status; /** iic interrupt status */
-	uint32_t last_cond, xmit_data;
-	DEV_BUFFER *buf_ptr;
-	DW_IIC_BUFFER *dw_iic_rxbuf_ptr;
-	uint8_t *p_charbuf;
-
-	if (iic_info_ptr->next_cond == IIC_MODE_STOP) {
-		last_cond = IC_DATA_CMD_STOP;
-	} else {
-		last_cond = IC_DATA_CMD_RESTART;
-	}
-	iic_int_status = (iic_reg_ptr->IC_INTR_STAT);
-	buf_ptr = &(iic_info_ptr->rx_buf);
-	p_charbuf = (uint8_t *)buf_ptr->buf;
-	if (p_charbuf) {
-		dw_iic_rxbuf_ptr = &(iic_ctrl_ptr->dw_iic_rxbuf);
-		if (iic_int_status & IC_INTR_STAT_TX_EMPTY) {
-			while (dw_iic_putready(iic_reg_ptr)) {
-				if (dw_iic_rxbuf_ptr->ofs >= dw_iic_rxbuf_ptr->len) {
-					dw_iic_mask_interrupt(iic_reg_ptr, IC_INTR_STAT_TX_EMPTY);
-					break;
-				}
-				xmit_data = IC_DATA_CMD_READ_REQ;
-				if (dw_iic_rxbuf_ptr->ofs == (dw_iic_rxbuf_ptr->len-1)) {
-					xmit_data |= last_cond;
-				} else {
-					xmit_data |= IC_DATA_CMD_NONE;
-				}
-				dw_iic_rxbuf_ptr->ofs ++;
-				dw_iic_putdata(iic_reg_ptr, xmit_data);
-			}
-		}
-		if (iic_int_status & IC_INTR_STAT_RX_FULL) {
-			while (dw_iic_getready(iic_reg_ptr)) {
-				p_charbuf[buf_ptr->ofs] = dw_iic_getdata(iic_reg_ptr);
-				buf_ptr->ofs ++;
-				if (buf_ptr->ofs >= buf_ptr->len) {
-					dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
-					iic_info_ptr->cur_state = IIC_FREE;
-					if (iic_info_ptr->iic_cbs.rx_cb) {
-						iic_info_ptr->iic_cbs.rx_cb(iic_obj);
-					}
-					/* clear the send buffer pointer */
-					memset(buf_ptr, 0, sizeof(DEV_BUFFER));
-					dw_iic_rxbuf_ptr->ofs = 0;
-					dw_iic_rxbuf_ptr->len = 0;
-					break;
-				}
-			}
-		}
-		if (iic_int_status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
-			iic_ctrl_ptr->iic_rx_over ++;
-		}
-		if (iic_int_status & IC_INTR_STAT_TX_ABRT) {
-			iic_info_ptr->err_state = dw_iic_mst_chkerr(iic_ctrl_ptr);
-			if (iic_info_ptr->err_state != IIC_ERR_NONE) {
-				dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
-				iic_info_ptr->cur_state = IIC_FREE;
-				if (iic_info_ptr->iic_cbs.err_cb) {
-					iic_info_ptr->iic_cbs.err_cb(iic_obj);
-				}
-				/* clear the send buffer pointer */
-				memset(buf_ptr, 0, sizeof(DEV_BUFFER));
-				dw_iic_rxbuf_ptr->ofs = 0;
-				dw_iic_rxbuf_ptr->len = 0;
-			}
-		}
-	} else {
-		dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
-		iic_info_ptr->cur_state = IIC_FREE;
-	}
-	/* Clear Interrupt */
-	iic_int_status = iic_reg_ptr->IC_CLR_INTR;
-}
-
-/** IIC Slave transmit called in interrupt */
-static void dw_iic_slv_int_process(DEV_IIC *iic_obj)
-{
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs);
-	uint32_t iic_int_status; /** iic interrupt status */
-
-	iic_int_status = (iic_reg_ptr->IC_INTR_STAT);
-	if (iic_int_status & IC_INTR_STAT_RD_REQ) { /* Read request from master */
-		if (iic_info_ptr->iic_cbs.tx_cb) {
-			iic_info_ptr->iic_cbs.tx_cb(iic_obj);
-		} else { /* When tx callback function is not set disable this tx int for slave */
-			dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
-		}
-	}
-	if (iic_int_status & IC_INTR_STAT_RX_FULL) { /* Write request from master */
-		if (iic_info_ptr->iic_cbs.rx_cb) {
-			iic_info_ptr->iic_cbs.rx_cb(iic_obj);
-		} else { /* When rx callback function is not set disable this rx int for slave */
-			dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
-		}
-	}
-	if (iic_int_status & IC_INTR_STAT_TX_OVER) {
-		iic_ctrl_ptr->iic_tx_over ++;
-	}
-	if (iic_int_status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) {
-		iic_ctrl_ptr->iic_rx_over ++;
-	}
-	if (iic_int_status & IC_INTR_STAT_TX_ABRT) {
-		iic_info_ptr->err_state = dw_iic_slv_chkerr(iic_ctrl_ptr);
-		if (iic_info_ptr->err_state != IIC_ERR_NONE) {
-			if (iic_info_ptr->iic_cbs.err_cb) {
-				iic_info_ptr->iic_cbs.err_cb(iic_obj);
-			}
-		}
-	}
-	/* Clear Interrupt */
-	iic_int_status = iic_reg_ptr->IC_CLR_INTR;
-}
-
-/** @} end of group DEVICE_DW_IIC_STATIC */
-
-/**
- * \defgroup	DEVICE_DW_IIC_IMPLEMENT	DesignWare IIC Driver Function API Implement
- * \ingroup	DEVICE_DW_IIC
- * \brief	implement device hal iic api with DesignWare IIC
- * @{
- */
-
-/**
- * \brief	open a designware iic device
- * \param[in]	iic_obj	iic device object pointer
- * \param[in]	mode	iic working mode (master or slave)
- * \param[in]	param	When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_iic_info::speed_mode "speed mode",
- *			when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_iic_info::slv_addr "slave device 7bit address"
- * \retval	E_OK	Open successfully without any issues
- * \retval	E_OPNED	If device was opened before with different parameters,
- *			then just increase the \ref dev_iic_info::opn_cnt "opn_cnt" and return \ref E_OPNED
- * \retval	E_OBJ	Device object is not valid
- * \retval	E_SYS	Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first.
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_NOSPT	Open settings are not supported
- */
-int32_t dw_iic_open (DEV_IIC *iic_obj, uint32_t mode, uint32_t param)
-{
-	int32_t ercd = E_OK;
-	uint32_t support_modes;
-	uint32_t param2check;
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
-	DW_IIC_CHECK_EXP((mode==DEV_MASTER_MODE)||(mode==DEV_SLAVE_MODE), E_PAR);
-	if (mode == DEV_MASTER_MODE) {
-		DW_IIC_CHECK_EXP((param>=IIC_SPEED_STANDARD) && (param<=IIC_SPEED_ULTRA), E_PAR);
-	}
-	/* END OF ERROR CHECK */
-
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-
-	/* Check supported modes, master or slave */
-	support_modes = iic_ctrl_ptr->support_modes;
-	DW_IIC_CHECK_EXP( (((support_modes)&DW_IIC_MASTER_SUPPORTED)&&(mode == DEV_MASTER_MODE)) || \
-				(((support_modes)&DW_IIC_SLAVE_SUPPORTED)&&(mode == DEV_SLAVE_MODE)), E_NOSPT);
-
-	/** Check opened before use case */
-	if (iic_info_ptr->opn_cnt > 0) {
-		if (mode != iic_info_ptr->mode) {
-			/* current working mode is different from passing mode */
-			return E_SYS;
-		}
-		if (mode == DEV_MASTER_MODE) { /* param is speed_mode when as master */
-			param2check = iic_info_ptr->speed_mode;
-		} else { /* param is slv_addr when as slave */
-			param2check = iic_info_ptr->slv_addr;
-		}
-		iic_info_ptr->opn_cnt ++;
-		if (param != param2check) { /* open with different speed mode */
-			return E_OPNED;
-		} else {
-			return E_OK;
-		}
-	}
-	/* auto increase open count */
-	iic_info_ptr->opn_cnt ++;
-
-	iic_info_ptr->mode = mode;
-	if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) {
-		iic_info_ptr->tar_addr &= IIC_7BIT_ADDRESS_MASK;
-		iic_info_ptr->slv_addr &= IIC_7BIT_ADDRESS_MASK;
-	} else {
-		iic_info_ptr->addr_mode = IIC_10BIT_ADDRESS;
-		iic_info_ptr->tar_addr &= IIC_10BIT_ADDRESS_MASK;
-		iic_info_ptr->slv_addr &= IIC_10BIT_ADDRESS_MASK;
-	}
-
-/* Do FIFO Length get before init */
-#if DW_IIC_CALC_FIFO_LEN_ENABLE
-	iic_ctrl_ptr->tx_fifo_len = dw_iic_get_txfifo_len(iic_ctrl_ptr->dw_iic_regs);
-	iic_ctrl_ptr->rx_fifo_len = dw_iic_get_rxfifo_len(iic_ctrl_ptr->dw_iic_regs);
-#endif
-
-	/* Disable device before init it */
-	dw_iic_disable_device(iic_info_ptr);
-
-	if (mode == DEV_MASTER_MODE) {
-		iic_info_ptr->speed_mode = param;
-		dw_iic_master_init(iic_ctrl_ptr, param, iic_info_ptr->addr_mode, iic_info_ptr->tar_addr);
-	} else {
-		iic_info_ptr->slv_addr = param;
-		dw_iic_slave_init(iic_ctrl_ptr, iic_info_ptr->addr_mode, param);
-	}
-	iic_info_ptr->status = DEV_ENABLED;
-	iic_info_ptr->cur_state = IIC_FREE;
-	iic_info_ptr->err_state = IIC_ERR_NONE;
-	iic_info_ptr->next_cond = IIC_MODE_STOP;
-	iic_info_ptr->extra = NULL;
-
-	iic_ctrl_ptr->iic_tx_over = 0;
-	iic_ctrl_ptr->iic_rx_over = 0;
-	iic_ctrl_ptr->int_status = 0;
-	memset(&(iic_ctrl_ptr->dw_iic_rxbuf), 0, sizeof(DW_IIC_BUFFER));
-	iic_ctrl_ptr->dw_iic_rxbuf.buf = &(iic_info_ptr->rx_buf);
-	/** install iic interrupt into system */
-	dw_iic_disable_interrupt(iic_info_ptr);
-	int_handler_install(iic_ctrl_ptr->intno, iic_ctrl_ptr->dw_iic_int_handler);
-	memset(&(iic_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER));
-	memset(&(iic_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER));
-	memset(&(iic_info_ptr->iic_cbs), 0, sizeof(DEV_IIC_CBS));
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	Close a DesignWare IIC device
- * \param[in]	iic_obj	iic device object pointer
- * \retval	E_OK	Close successfully without any issues(including secenary that device is already closed)
- * \retval	E_OPNED	Device is still opened, the device \ref dev_iic_info::opn_cnt "opn_cnt" decreased by 1
- * \retval	E_OBJ	Device object is not valid
- */
-int32_t dw_iic_close (DEV_IIC *iic_obj)
-{
-	int32_t ercd = E_OK;
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
-	DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_OK);
-	/* END OF ERROR CHECK */
-
-	iic_info_ptr->opn_cnt --;
-	if (iic_info_ptr->opn_cnt == 0) {
-		dw_iic_disable_interrupt(iic_info_ptr);
-		dw_iic_abort_tx(iic_obj);
-		dw_iic_abort_rx(iic_obj);
-		memset(&(iic_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER));
-		memset(&(iic_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER));
-		memset(&(iic_info_ptr->iic_cbs), 0, sizeof(DEV_IIC_CBS));
-		dw_iic_disable_device(iic_info_ptr);
-		iic_info_ptr->status = DEV_DISABLED;
-		iic_info_ptr->next_cond = IIC_MODE_STOP;
-		iic_info_ptr->extra = NULL;
-	} else {
-		ercd = E_OPNED;
-	}
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	Control iic by ctrl command
- * \param[in]	iic_obj	iic device object pointer
- * \param[in]		ctrl_cmd	\ref DEVICE_HAL_IIC_CTRLCMD "control command", to change or get some thing related to iic
- * \param[in,out]	param		parameters that maybe argument of the command,
- * 					or return values of the command, must not be NULL
- * \retval	E_OK	Control device successfully
- * \retval	E_CLSED	Device is not opened
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
- * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
- * \retval	E_NOSPT	Control command is not supported or not valid
- */
-int32_t dw_iic_control (DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param)
-{
-	int32_t ercd = E_OK;
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
-	DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED);
-	/* END OF ERROR CHECK */
-
-	uint32_t val32; /** to receive unsigned int value */
-	DEV_BUFFER *devbuf;
-
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl);
-	DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs);
-
-	/* check whether current device is disabled */
-	if ((iic_info_ptr->status & DEV_ENABLED) == 0) {
-		/** When device is disabled,
-		 * only IIC_CMD_ENA_DEV, IIC_CMD_DIS_DEV, IIC_CMD_GET_STATUS, IIC_CMD_RESET
-		 * are available, other commands will return E_SYS
-		 */
-		if ((ctrl_cmd != IIC_CMD_ENA_DEV) && \
-			(ctrl_cmd != IIC_CMD_DIS_DEV) && \
-			(ctrl_cmd != IIC_CMD_GET_STATUS) && \
-			(ctrl_cmd != IIC_CMD_RESET) ) {
-			return E_SYS;
-		}
-	}
-
-	switch (ctrl_cmd) {
-		/* Commmon commands for both master and slave mode */
-		case IIC_CMD_GET_STATUS:
-			DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = iic_info_ptr->status;
-			break;
-		case IIC_CMD_ENA_DEV:
-			dw_iic_enable_device(iic_info_ptr);
-			break;
-		case IIC_CMD_DIS_DEV:
-			dw_iic_disable_device(iic_info_ptr);
-			break;
-		case IIC_CMD_RESET:
-			dw_iic_reset_device(iic_info_ptr);
-			break;
-		case IIC_CMD_FLUSH_TX:
-			dw_iic_flush_tx(iic_reg_ptr);
-			break;
-		case IIC_CMD_FLUSH_RX:
-			dw_iic_flush_rx(iic_reg_ptr);
-			break;
-		case IIC_CMD_SET_ADDR_MODE:
-			val32 = (uint32_t)param;
-			DW_IIC_CHECK_EXP((val32==IIC_7BIT_ADDRESS) || (val32==IIC_10BIT_ADDRESS), E_PAR);
-			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
-				dw_iic_set_mstaddr_mode(iic_reg_ptr, val32);
-			} else {
-				dw_iic_set_slvaddr_mode(iic_reg_ptr, val32);
-			}
-			iic_info_ptr->addr_mode = val32;
-			break;
-		case IIC_CMD_GET_RXAVAIL:
-			DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = dw_iic_get_rxavail(iic_ctrl_ptr);
-			break;
-		case IIC_CMD_GET_TXAVAIL:
-			DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = dw_iic_get_txavail(iic_ctrl_ptr);
-			break;
-		case IIC_CMD_SET_TXCB:
-			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			iic_info_ptr->iic_cbs.tx_cb = param;
-			break;
-		case IIC_CMD_SET_RXCB:
-			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			iic_info_ptr->iic_cbs.rx_cb = param;
-			break;
-		case IIC_CMD_SET_ERRCB:
-			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			iic_info_ptr->iic_cbs.err_cb = param;
-			break;
-		case IIC_CMD_ABORT_TX:
-			dw_iic_abort_tx(iic_obj);
-			if ((iic_info_ptr->mode == DEV_MASTER_MODE) \
-				&& (iic_info_ptr->cur_state == IIC_IN_TX)) {
-				iic_info_ptr->cur_state = IIC_FREE;
-			}
-			break;
-		case IIC_CMD_ABORT_RX:
-			dw_iic_abort_rx(iic_obj);
-			if ((iic_info_ptr->mode == DEV_MASTER_MODE) \
-				&& (iic_info_ptr->cur_state == IIC_IN_RX)) {
-				iic_info_ptr->cur_state = IIC_FREE;
-			}
-			break;
-		case IIC_CMD_SET_TXINT:
-			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
-				DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_RX, E_CTX);
-			}
-			val32 = (uint32_t)param;
-			if (val32 == 0) {
-				dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND);
-				iic_info_ptr->cur_state = IIC_FREE;
-			} else {
-				iic_info_ptr->cur_state = IIC_IN_TX;
-				dw_iic_ena_cbr(iic_info_ptr, DW_IIC_RDY_SND);
-			}
-			break;
-		case IIC_CMD_SET_RXINT:
-			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
-				DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_TX, E_CTX);
-			}
-			val32 = (uint32_t)param;
-			if (val32 == 0) {
-				iic_info_ptr->cur_state = IIC_FREE;
-				dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
-			} else {
-				iic_info_ptr->cur_state = IIC_IN_RX;
-				dw_iic_ena_cbr(iic_info_ptr, DW_IIC_RDY_RCV);
-			}
-			break;
-		case IIC_CMD_SET_TXINT_BUF:
-			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
-				DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_TX, E_CTX);
-			}
-			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			if (param != NULL) {
-				devbuf = (DEV_BUFFER *)param;
-				iic_info_ptr->tx_buf = *devbuf;
-				iic_info_ptr->tx_buf.ofs = 0;
-			} else {
-				iic_info_ptr->tx_buf.buf = NULL;
-				iic_info_ptr->tx_buf.len = 0;
-				iic_info_ptr->tx_buf.ofs = 0;
-			}
-			break;
-		case IIC_CMD_SET_RXINT_BUF:
-			if (iic_info_ptr->mode == DEV_MASTER_MODE) {
-				DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_RX, E_CTX);
-			}
-			DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			if (param != NULL) {
-				devbuf = (DEV_BUFFER *)param;
-				iic_info_ptr->rx_buf = *devbuf;
-				iic_info_ptr->rx_buf.ofs = 0;
-				iic_ctrl_ptr->dw_iic_rxbuf.ofs = 0;
-				iic_ctrl_ptr->dw_iic_rxbuf.len = devbuf->len;
-			} else {
-				iic_info_ptr->rx_buf.buf = NULL;
-				iic_info_ptr->rx_buf.len = 0;
-				iic_info_ptr->rx_buf.ofs = 0;
-				iic_ctrl_ptr->dw_iic_rxbuf.ofs = 0;
-				iic_ctrl_ptr->dw_iic_rxbuf.len = 0;
-			}
-			break;
-
-		/* Master mode only commands */
-		case IIC_CMD_MST_SET_SPEED_MODE:
-			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
-			val32 = (uint32_t)param;
-			DW_IIC_CHECK_EXP((val32>=IIC_SPEED_STANDARD) && (val32<=IIC_SPEED_ULTRA), E_PAR);
-			dw_iic_set_speedmode(iic_reg_ptr, val32);
-			iic_info_ptr->speed_mode = val32;
-			break;
-		case IIC_CMD_MST_SET_TAR_ADDR:
-			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
-			if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) {
-				val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK;
-			} else {
-				val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK;
-			}
-			if (val32 != iic_info_ptr->tar_addr) {
-				dw_iic_set_taraddr(iic_reg_ptr, val32);
-				iic_info_ptr->tar_addr = val32;
-			}
-			break;
-		case IIC_CMD_MST_SET_NEXT_COND:
-			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
-			val32 = (uint32_t)param;
-			DW_IIC_CHECK_EXP((val32==IIC_MODE_STOP) || (val32==IIC_MODE_RESTART), E_PAR);
-			iic_info_ptr->next_cond = (uint32_t)param;
-			break;
-
-		/* Slave mode only commands */
-		case IIC_CMD_SLV_SET_SLV_ADDR:
-			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_SLAVE_MODE, E_NOSPT);
-			if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) {
-				val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK;
-			} else {
-				val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK;
-			}
-			dw_iic_set_slvaddr(iic_reg_ptr, val32);
-			iic_info_ptr->slv_addr = val32;
-			break;
-		case IIC_CMD_SLV_GET_SLV_STATE:
-			DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_SLAVE_MODE, E_NOSPT);
-			DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((uint32_t *)param) = dw_iic_get_slv_state(iic_reg_ptr);
-			break;
-
-		default:
-			ercd = E_NOSPT;
-			break;
-	}
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	poll transmit data through DesignWare IIC as master or slave
- * \param[in]	iic_obj	iic device object pointer
- * \param[in]	data	data that need to send (data must be uint8_t type)
- * \param[in]	len	data length need to send
- * \retval	>0	Byte count that was successfully sent for poll method,
- * 			it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state".
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_CTX	Device is still in transfer state
- * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
- */
-int32_t dw_iic_write (DEV_IIC *iic_obj, const void *data, uint32_t len)
-{
-	int32_t ercd = E_OK;
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
-	DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED);
-	DW_IIC_CHECK_EXP(iic_info_ptr->status & DEV_ENABLED, E_SYS);
-	DW_IIC_CHECK_EXP(data!=NULL, E_PAR);
-	DW_IIC_CHECK_EXP(len>0, E_PAR);
-	/* END OF ERROR CHECK */
-
-	int32_t i = 0;
-	uint32_t last_cond = 0; /* Last data for transmit, STOP or RESTART */
-	int32_t error_state = IIC_ERR_NONE;
-	const uint8_t *p_charbuf = (const uint8_t *)data;
-
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
-
-	if (iic_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode transmit data */
-		if (iic_info_ptr->next_cond == IIC_MODE_STOP) {
-			last_cond = IC_DATA_CMD_STOP;
-		} else {
-			last_cond = IC_DATA_CMD_RESTART;
-		}
-
-		/* Try to transmit 0 -> (len-1) data */
-		len = len - 1; /* Last data write differently */
-		while (i < len) {
-			error_state = dw_iic_mst_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[i]), IC_DATA_CMD_NONE);
-			if (error_state != IIC_ERR_NONE) {
-				break;
-			}
-			i ++;
-		}
-		/* Try to transmit the last data with STOP or RESTART condition */
-		if (error_state == IIC_ERR_NONE) {
-			error_state = dw_iic_mst_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[len]), last_cond);
-			if (error_state == IIC_ERR_NONE) {
-				i = i + 1; /* Add last data into send count */
-			}
-		}
-	} else { /* Slave mode transmit data */
-		while (i < len) {
-			error_state = dw_iic_slv_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[i]));
-			if (error_state != IIC_ERR_NONE) {
-				break;
-			}
-			i ++;
-		}
-	}
-	iic_info_ptr->err_state = error_state;
-	ercd = i;
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	read data through DesignWare IIC
- * \param[in]	iic_obj	iic device object pointer
- * \param[out]	data	data that need to read (data must be uint8_t type)
- * \param[in]	len	data count need to read
- * \retval	>0	Byte count that was successfully received for poll method,
- * 			it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state".
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_CTX	Device is still in transfer state
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
- */
-int32_t dw_iic_read (DEV_IIC *iic_obj, void *data, uint32_t len)
-{
-	int32_t ercd = E_OK;
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
-	DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED);
-	DW_IIC_CHECK_EXP(iic_info_ptr->status & DEV_ENABLED, E_SYS);
-	DW_IIC_CHECK_EXP(data!=NULL, E_PAR);
-	DW_IIC_CHECK_EXP(len>0, E_PAR);
-	/* END OF ERROR CHECK */
-
-	int32_t i = 0;
-	uint32_t last_cond = 0; /* Last data for receive, STOP or RESTART */
-	uint32_t val32 = 0;
-	int32_t error_state = IIC_ERR_NONE;
-	uint8_t *p_charbuf = (uint8_t *)data;
-
-	DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl);
-
-	if (iic_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode receive data */
-		if (iic_info_ptr->next_cond == IIC_MODE_STOP) {
-			last_cond = IC_DATA_CMD_STOP;
-		} else {
-			last_cond = IC_DATA_CMD_RESTART;
-		}
-
-		/* Try to receive 0 -> (len-1) data */
-		len = len - 1; /* Last data write differently */
-		while (i < len) {
-			error_state = dw_iic_mst_read_data(iic_ctrl_ptr, &val32, IC_DATA_CMD_NONE);
-			if (error_state != IIC_ERR_NONE) {
-				break;
-			} else {
-				p_charbuf[i] = (uint8_t)val32;
-			}
-			i ++;
-		}
-		/* Try to receive the last data with STOP or RESTART condition */
-		if (error_state == IIC_ERR_NONE) {
-			error_state = dw_iic_mst_read_data(iic_ctrl_ptr, &val32, last_cond);
-			if (error_state == IIC_ERR_NONE) {
-				p_charbuf[len] = (uint8_t)val32;
-				i = i + 1; /* Add last data into send count */
-			}
-		}
-	} else { /* Slave mode receive data */
-		while (i < len) {
-			error_state = dw_iic_slv_read_data(iic_ctrl_ptr, &val32);
-			if (error_state != IIC_ERR_NONE) {
-				break;
-			} else {
-				p_charbuf[i] = (uint8_t)val32;
-			}
-			i ++;
-		}
-	}
-	iic_info_ptr->err_state = error_state;
-	ercd = i;
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	DesignWare IIC interrupt processing routine
- * \param[in]	iic_info_ptr	DEV_IIC *iic_obj
- * \param[in]	ptr		extra information
- */
-void dw_iic_isr(DEV_IIC *iic_obj, void *ptr)
-{
-	int32_t ercd = E_OK;
-	DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr);
-	/* END OF ERROR CHECK */
-
-	if (iic_info_ptr->mode == DEV_MASTER_MODE) {
-		if (iic_info_ptr->cur_state == IIC_IN_TX) {
-			dw_iic_mst_int_write(iic_obj);
-		} else {
-			dw_iic_mst_int_read(iic_obj);
-		}
-	} else {
-		dw_iic_slv_int_process(iic_obj);
-	}
-
-error_exit:
-	return;
-}
-/** @} end of group DEVICE_DW_IIC_IMPLEMENT */
diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic.h
deleted file mode 100644
index 55c551a67e..0000000000
--- a/bsp/synopsys/embarc/device/designware/iic/dw_iic.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-06-30
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \brief	designware iic driver header file
- * \ingroup	DEVICE_DW_IIC
- */
-
-#ifndef _DW_IIC_H_
-#define _DW_IIC_H_
-
-#include "device/device_hal/inc/dev_iic.h"
-
-#include "inc/arc/arc_exception.h"
-
-
-/**
- * If this header file is included,
- * will indicate that this designware iic device
- * is used
- */
-#define DEVICE_USE_DESIGNWARE_IIC
-
-/**
- * \defgroup	DEVICE_DW_IIC_INFO	DesignWare IIC Related Information
- * \ingroup	DEVICE_DW_IIC
- * \brief	Defines some macros of DesignWare IIC need.
- * \details	macros like, iic number
- * @{
- */
-#define DW_IIC_MASTER_SUPPORTED		(0x1)	/*!< Support Designware IIC Master Mode */
-#define DW_IIC_SLAVE_SUPPORTED		(0x2)	/*!< Support Designware IIC Slave Mode */
-/*!< Support Designware IIC Both Master and Slave Mode */
-#define DW_IIC_BOTH_SUPPORTED		(DW_IIC_MASTER_SUPPORTED|DW_IIC_SLAVE_SUPPORTED)
-/** @} */
-
-/**
- * \defgroup	DEVICE_DW_IIC_REGSTRUCT		DesignWare IIC Register Structure
- * \ingroup	DEVICE_DW_IIC
- * \brief	contains definitions of DesignWare IIC register structure.
- * \details	detailed description of DesignWare IIC register information
- * @{
- */
-/**
- * \brief	DesignWare IIC register structure
- * \details	Detailed struct description of DesignWare IIC
- *	block register information, implementation of dev_iic_info::iic_regs
- */
-typedef volatile struct dw_iic_reg {
-	uint32_t IC_CON;		/*!< (0x00) : IIC control */
-	uint32_t IC_TAR;		/*!< (0x04) : IIC target address */
-	uint32_t IC_SAR;		/*!< (0x08) : IIC slave address */
-	uint32_t IC_HS_MADDR;		/*!< (0x0c) : IIC HS Master Mode Code address */
-	uint32_t IC_DATA_CMD;		/*!< (0x10) : IIC Rx/Tx Data Buffer and Command */
-	uint32_t IC_SS_SCL_HCNT;	/*!< (0x14) : Standard Speed IIC clock SCL High Count */
-	uint32_t IC_SS_SCL_LCNT;	/*!< (0x18) : Standard Speed IIC clock SCL Low Count */
-	uint32_t IC_FS_SCL_HCNT;	/*!< (0x1c) : Fast Speed IIC clock SCL Low Count */
-	uint32_t IC_FS_SCL_LCNT;	/*!< (0x20) : Fast Speed IIC clock SCL Low Count */
-	uint32_t IC_HS_SCL_HCNT;	/*!< (0x24) : High Speed IIC clock SCL Low Count */
-	uint32_t IC_HS_SCL_LCNT;	/*!< (0x28) : High Speed IIC clock SCL Low Count */
-	uint32_t IC_INTR_STAT;		/*!< (0x2c) : IIC Interrupt Status */
-	uint32_t IC_INTR_MASK;		/*!< (0x30) : IIC Interrupt Mask */
-	uint32_t IC_RAW_INTR_STAT;	/*!< (0x34) : IIC Raw Interrupt Status */
-	uint32_t IC_RX_TL;		/*!< (0x38) : IIC Receive FIFO Threshold */
-	uint32_t IC_TX_TL;		/*!< (0x3c) : IIC Transmit FIFO Threshold */
-	uint32_t IC_CLR_INTR;		/*!< (0x40) : Clear combined and Individual Interrupts */
-	uint32_t IC_CLR_RX_UNDER;	/*!< (0x44) : Clear RX_UNDER Interrupt */
-	uint32_t IC_CLR_RX_OVER;	/*!< (0x48) : Clear RX_OVER Interrupt */
-	uint32_t IC_CLR_TX_OVER;	/*!< (0x4c) : Clear TX_OVER Interrupt */
-	uint32_t IC_CLR_RD_REQ;		/*!< (0x50) : Clear RQ_REQ Interrupt */
-	uint32_t IC_CLR_TX_ABRT;	/*!< (0x54) : Clear TX_ABRT Interrupt */
-	uint32_t IC_CLR_RX_DONE;	/*!< (0x58) : Clear RX_DONE Interrupt */
-	uint32_t IC_CLR_ACTIVITY;	/*!< (0x5c) : Clear ACTIVITY Interrupt */
-	uint32_t IC_CLR_STOP_DET;	/*!< (0x60) : Clear STOP_DET Interrupt */
-	uint32_t IC_CLR_START_DET;	/*!< (0x64) : Clear START_DET Interrupt */
-	uint32_t IC_CLR_GEN_CALL;	/*!< (0x68) : Clear GEN_CALL Interrupt */
-	uint32_t IC_ENABLE;		/*!< (0x6c) : IIC Enable */
-	uint32_t IC_STATUS;		/*!< (0x70) : IIC Status */
-	uint32_t IC_TXFLR;		/*!< (0x74) : Transmit FIFO Level Register */
-	uint32_t IC_RXFLR;		/*!< (0x78) : Receive FIFO Level Register */
-	uint32_t IC_SDA_HOLD;		/*!< (0x7c) : SDA Hold Time Length Reg */
-	uint32_t IC_TX_ABRT_SOURCE;	/*!< (0x80) : IIC Transmit Abort Status Reg */
-	uint32_t IC_SLV_DATA_NACK_ONLY;	/*!< (0x84) : Generate SLV_DATA_NACK Register */
-	uint32_t IC_DMA_CR;		/*!< (0x88) : DMA Control Register */
-	uint32_t IC_DMA_TDLR;		/*!< (0x8c) : DMA Transmit Data Level */
-	uint32_t IC_DMA_RDLR;		/*!< (0x90) : DMA Receive Data Level */
-	uint32_t IC_SDA_SETUP;		/*!< (0x94) : SDA Setup Register */
-	uint32_t IC_ACK_GENERAL_CALL;	/*!< (0x98) : ACK General Call Register */
-	uint32_t IC_ENABLE_STATUS;	/*!< (0x9c) : Enable Status Register */
-	uint32_t IC_FS_SPKLEN;		/*!< (0xa0) : ISS and FS spike suppression limit */
-	uint32_t IC_HS_SPKLEN;		/*!< (0xa4) : HS spike suppression limit */
-	uint32_t RESERVED[19];		/*!< (0xa8) : Reserved */
-	uint32_t IC_COMP_PARAM_1;	/*!< (0xf4) : Component Parameter Register */
-	uint32_t IC_COMP_VERSION;	/*!< (0xf8) : Component Version ID Reg */
-	uint32_t IC_COMP_TYPE;		/*!< (0xfc) : Component Type Reg */
-} DW_IIC_REG, *DW_IIC_REG_PTR;
-/** @} */
-
-/** Spike Suppression Limit Configurations */
-typedef struct dw_iic_spklen {
-	uint32_t fs_spklen;	/*!< value for IC_FS_SPKLEN, Tsp for fast mode is 50ns */
-	uint32_t hs_spklen;	/*!< value for IC_HS_SPKLEN, Tsp for high-speed mode is 10ns */
-} DW_IIC_SPKLEN, *DW_IIC_SPKLEN_PTR;
-
-/** IIC Clock SCL High and Low Count Configurations for Different Speed */
-typedef struct dw_iic_scl_cnt {
-	uint32_t ss_scl_hcnt;	/*!< value for IC_SS_SCL_HCNT */
-	uint32_t ss_scl_lcnt;	/*!< value for IC_SS_SCL_LCNT */
-	uint32_t fs_scl_hcnt;	/*!< value for IC_FS_SCL_HCNT */
-	uint32_t fs_scl_lcnt;	/*!< value for IC_FS_SCL_LCNT */
-	uint32_t hs_scl_hcnt;	/*!< value for IC_HS_SCL_HCNT */
-	uint32_t hs_scl_lcnt;	/*!< value for IC_HS_SCL_LCNT */
-} DW_IIC_SCL_CNT, *DW_IIC_SCL_CNT_PTR;
-
-#define DW_IIC_GINT_DISABLED		(0)		/*!< designware interrupt disabled for control iic irq/fiq */
-#define DW_IIC_GINT_ENABLE		(1<<0)		/*!< designware interrupt enabled for control iic irq/fiq */
-#define DW_IIC_TXINT_ENABLE		(1<<1)		/*!< designware interrupt enabled for control transmit process */
-#define DW_IIC_RXINT_ENABLE		(1<<2)		/*!< designware interrupt enabled for control transmit process */
-
-typedef struct dw_iic_buffer {
-	DEV_BUFFER *buf;
-	uint32_t ofs;
-	uint32_t len;
-} DW_IIC_BUFFER, *DW_IIC_BUFFER_PTR;
-
-/**
- * \brief	DesignWare IIC control structure definition
- * \details	implement of dev_iic_info::iic_ctrl
- */
-typedef struct dw_iic_ctrl {
-	DW_IIC_REG *dw_iic_regs;	/*!< iic device registers */
-	/* Variables which should be set during object implementation */
-	uint32_t support_modes;		/*!< supported iic modes */
-	uint32_t tx_fifo_len;		/*!< transmit fifo length */
-	uint32_t rx_fifo_len;		/*!< receive fifo length */
-	uint32_t iic_master_code;	/*!< value for IC_HS_MADDR */
-	uint32_t retry_cnt;		/*!< retry count for TX or RX */
-	uint32_t intno;			/*!< iic interrupt vector number */
-	INT_HANDLER dw_iic_int_handler;	/*!< iic interrupt handler */
-	DW_IIC_SPKLEN iic_spklen;	/*!< iic spike suppression length settings */
-	DW_IIC_SCL_CNT iic_scl_cnt;	/*!< iic scl count settings */
-	/* Variables which always change during iic operation */
-	uint32_t int_status;		/*!< iic interrupt status */
-	uint32_t iic_tx_over;		/*!< iic tx overflow count */
-	uint32_t iic_rx_over;		/*!< iic rx overflow count */
-	DW_IIC_BUFFER dw_iic_rxbuf;	/*!< iic read buffer for receive data */
-} DW_IIC_CTRL, *DW_IIC_CTRL_PTR;
-
-/*!< One possible value for \ref dw_iic_ctrl::retry_cnt */
-#define DW_IIC_MAX_RETRY_COUNT		(100000)
-
-#if DW_IIC_USE_IC_CLK_MHZ == 100 /*!< 100MHz */
-/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
-static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
-
-/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
-#if DW_IIC_USE_HS_BUS_LOADING_100PF
-static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10};
-#else
-static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20};
-#endif
-
-#elif DW_IIC_USE_IC_CLK_MHZ == 50 /* 50MHz */
-/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
-static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
-
-/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
-#if DW_IIC_USE_HS_BUS_LOADING_100PF
-static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x8};
-#else
-static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x10};
-#endif
-
-#else /* Default 100MHz */
-/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
-static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
-
-/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
-#if DW_IIC_USE_HS_BUS_LOADING_100PF
-static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10};
-#else
-static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20};
-#endif
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup	DEVICE_DW_IIC_FUNCDLR	DesignWare IIC Function Declaration
- * \ingroup	DEVICE_DW_IIC
- * \brief	Contains declarations of designware iic functions.
- * \details	This are only used in iic object implementation source file
- * @{
- */
-extern int32_t dw_iic_open (DEV_IIC *iic_obj, uint32_t mode, uint32_t param);
-extern int32_t dw_iic_close (DEV_IIC *iic_obj);
-extern int32_t dw_iic_control (DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param);
-extern int32_t dw_iic_write (DEV_IIC *iic_obj, const void *data, uint32_t len);
-extern int32_t dw_iic_read (DEV_IIC *iic_obj, void *data, uint32_t len);
-extern void dw_iic_isr(DEV_IIC *iic_obj, void *ptr);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-#endif /* _DW_IIC_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h
deleted file mode 100644
index f7ec0d27a2..0000000000
--- a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-06-30
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	DEVICE_DW_IIC
- * \brief	DesignWare IIC driver hardware description related header file
- * \details	detailed hardware related definitions of DesignWare IIC driver
- */
-
-#ifndef _DEVICE_DW_IIC_HAL_H_
-#define _DEVICE_DW_IIC_HAL_H_
-
-#include "device/designware/iic/dw_iic_hal_cfg.h"
-
-/** Enable Designware IIC */
-#define DW_IIC_ENABLE			(1)
-/** Disable Designware IIC */
-#define DW_IIC_DISABLE			(0)
-
-/** Stop Condition issue after this byte */
-#define IC_DATA_CMD_STOP		(1 << 9)
-/** Restart Condition issue after this byte */
-#define IC_DATA_CMD_RESTART		(1 << 10)
-/** No Restart or stop condition after this byte */
-#define IC_DATA_CMD_NONE		(0)
-
-/** Perform a write request */
-#define IC_DATA_CMD_WRITE_REQ		(0)
-/** Perform a read request */
-#define IC_DATA_CMD_READ_REQ		(1 << 8)
-
-/** Fields of IC_CON register */
-/* DW_APB I2C IP Config Dependencies. */
-#if DW_IIC_ALLOW_RESTART
-#define IC_CON_RESTART_EN		(1 << 5)
-#else
-#define IC_CON_RESTART_EN		(0x00)
-#endif
-
-/* Master Addressing Mode Config */
-#if DW_IIC_MST_10_BIT_ADDR_SUPPORT
-#define MST_10_BIT_ADDR_MODE		(1 << 4)
-#define IC_10BITADDR_MASTER		(1 << 12)
-#else
-#define MST_10_BIT_ADDR_MODE		(0x00)
-#define IC_10BITADDR_MASTER		(0x00)
-#endif
-
-/* Slave Addressing Mode Config */
-#if DW_IIC_SLV_10_BIT_ADDR_SUPPORT
-#define SLV_10_BIT_ADDR_MODE		(1 << 3)
-#else
-#define SLV_10_BIT_ADDR_MODE		(0x00)
-#endif
-
-#if DW_IIC_SPECIAL_START_BYTE
-#define IC_TAR_SPECIAL			(1 << 11)
-#define IC_TAR_GC_OR_START		(1 << 10)
-#else
-#define IC_TAR_SPECIAL			(0x00)
-#define IC_TAR_GC_OR_START		(0x00)
-#endif
-
-/** 7bit IIC address mask for target address register */
-#define IC_TAR_7BIT_ADDR_MASK		(0x7F)
-/** 7bit IIC address mask for slave address register */
-#define IC_SAR_7BIT_ADDR_MASK		(0x7F)
-/** 10bit IIC address mask for target address register */
-#define IC_TAR_10BIT_ADDR_MASK		(0x3FF)
-/** 10bit IIC address mask for slave address register */
-#define IC_SAR_10BIT_ADDR_MASK		(0x3FF)
-
-/** Speed modes of IC_CON */
-#define IC_CON_SPEED_MASK		(0x6)
-#define IC_CON_SPEED_STANDARD		(0x2)
-#define IC_CON_SPEED_FAST		(0x4)
-#define IC_CON_SPEED_HIGH		(0x6)
-/** Working mode of IC_CON */
-#define IC_CON_MST_SLV_MODE_MASK	(0x41)
-#define IC_CON_ENA_MASTER_MODE		(0x41)
-#define IC_CON_ENA_SLAVE_MODE		(0)
-
-/* IIC interrupt control */
-#define IC_INT_DISABLE_ALL		(0x0)
-#define IC_INT_ENABLE_ALL		(0x7FF)
-/* Interrupt Register Fields */
-#define IC_INTR_STAT_GEN_CALL		(1 << 11)
-#define IC_INTR_STAT_START_DET		(1 << 10)
-#define IC_INTR_STAT_STOP_DET		(1 << 9)
-#define IC_INTR_STAT_ACTIVITY		(1 << 8)
-#define IC_INTR_STAT_RX_DONE		(1 << 7)
-#define IC_INTR_STAT_TX_ABRT		(1 << 6)
-#define IC_INTR_STAT_RD_REQ		(1 << 5)
-#define IC_INTR_STAT_TX_EMPTY		(1 << 4)
-#define IC_INTR_STAT_TX_OVER		(1 << 3)
-#define IC_INTR_STAT_RX_FULL		(1 << 2)
-#define IC_INTR_STAT_RX_OVER		(1 << 1)
-#define IC_INTR_STAT_RX_UNDER		(1 << 0)
-
-/* Interrupt enable mask as master */
-#define IC_INT_MST_TX_ENABLE		(IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_TX_OVER|IC_INTR_STAT_TX_ABRT)
-#define IC_INT_MST_RX_ENABLE		(IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER|IC_INTR_STAT_TX_ABRT)
-
-/* Interrupt enable mask as master */
-#define IC_INT_SLV_COMMON_ENABLE	(IC_INTR_STAT_START_DET|IC_INTR_STAT_STOP_DET)
-#define IC_INT_SLV_TX_ENABLE		(IC_INTR_STAT_RD_REQ|IC_INTR_STAT_TX_ABRT)
-#define IC_INT_SLV_RX_ENABLE		(IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)
-
-/* IC_ENABLE_STATUS Bits */
-#define IC_ENABLE_STATUS_IC_EN		(1 << 0)
-#define IC_ENABLE_STATUS_SLV_DIS	(1 << 1)
-#define IC_ENABLE_STATUS_SLV_RX_LOST	(1 << 2)
-
-/* IIC TX & RX threshold settings */
-#define IIC_TX_THRESHOLD		(0)
-#define IIC_RX_THRESHOLD		(0)
-
-/* DW_APB IIC (DW_IC_STATUS) Status Register Fields. */
-#define IC_STATUS_ACTIVITY		(0x01)
-#define IC_STATUS_TFNF			(0x02) /* (1 << 1) */
-#define IC_STATUS_TFE			(0x04) /* (1 << 2) */
-#define IC_STATUS_RFNE			(0x08) /* (1 << 3) */
-#define IC_STATUS_RFF			(0x10) /* (1 << 4) */
-#define IC_STATUS_MASTER_ACT		(0x20) /* (1 << 5) */
-#define IC_STATUS_SLAVE_ACT		(0x40) /* (1 << 6) */
-
-/* IC_TX_ABRT_SOURCE Register Bit Fields */
-#define IC_TX_ABRT_7B_ADDR_NOACK	(1 << 0)
-#define IC_TX_ABRT_10ADDR1_NOACK	(1 << 1)
-#define IC_TX_ABRT_10ADDR2_NOACK	(1 << 2)
-#define IC_TX_ABRT_TXDATA_NOACK		(1 << 3)
-#define IC_TX_ABRT_GCALL_NOACK		(1 << 4)
-#define IC_TX_ABRT_GCALL_READ		(1 << 5)
-#define IC_TX_ABRT_HS_ACKDET		(1 << 6)
-#define IC_TX_ABRT_SBYTE_ACKDET		(1 << 7)
-#define IC_TX_ABRT_HS_NORSTRT		(1 << 8)
-#define IC_TX_ABRT_SBYTE_NORSTRT	(1 << 9)
-#define IC_TX_ABRT_10B_RD_NORSTRT	(1 << 10)
-#define IC_TX_ABRT_MASTER_DIS		(1 << 11)
-#define IC_TX_ABRT_ARB_LOST		(1 << 12)
-#define IC_TX_ABRT_SLVFLUSH_TXFIFO	(1 << 13)
-#define IC_TX_ABRT_SLV_ARBLOST		(1 << 14)
-#define IC_TX_ABRT_SLVRD_INTX		(1 << 15)
-
-/* Combined bits for iic abort source as master */
-#define IIC_MST_ABRT_ADDR_NOACK		(IC_TX_ABRT_7B_ADDR_NOACK|IC_TX_ABRT_10ADDR1_NOACK|IC_TX_ABRT_10ADDR1_NOACK)
-#define IIC_MST_ABRT_LOST_BUS		(IC_TX_ABRT_ARB_LOST)
-#define IIC_MST_ABRT_DATA_NOACK		(IC_TX_ABRT_TXDATA_NOACK)
-
-/* Combined bits for iic abort source as slave */
-#define IIC_SLV_ABRT_LOST_BUS		(IC_TX_ABRT_ARB_LOST|IC_TX_ABRT_SLV_ARBLOST)
-
-/** @} */
-
-#endif /* _DEVICE_DW_IIC_HAL_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h
deleted file mode 100644
index 1073162176..0000000000
--- a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-07-01
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	DEVICE_DW_IIC
- * \brief	DesignWare IIC driver hardware description
- * 	related header file configuration file
- * \details	configuration file to enable or disable some function of iic
- */
-
-#ifndef _DEVICE_DW_IIC_HAL_CFG_H_
-#define _DEVICE_DW_IIC_HAL_CFG_H_
-
-#ifndef DW_IIC_ALLOW_RESTART
-#define DW_IIC_ALLOW_RESTART			(1)	/*!< allow restart configuration */
-#endif
-
-#ifdef DW_IIC_SPECIAL_START_BYTE
-#define DW_IIC_SPECIAL_START_BYTE		(0)	/*!< SPECIAL bit enable in IC_TAR */
-#endif
-
-#ifndef DW_IIC_MST_10_BIT_ADDR_SUPPORT
-#define DW_IIC_MST_10_BIT_ADDR_SUPPORT		(1)	/*!< enable 10-bit address mode */
-#endif
-
-#ifdef DW_IIC_SLV_10_BIT_ADDR_SUPPORT
-#define DW_IIC_SLV_10_BIT_ADDR_SUPPORT		(1)	/*!< slave 10-bit addressing mode */
-#endif
-
-#ifndef DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
-#define DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT	(0)	/*!< Dynamic target address update support */
-#endif
-
-#ifndef DW_IIC_DISABLE_MAX_T_POLL_CNT
-#define DW_IIC_DISABLE_MAX_T_POLL_CNT		(1250)	/*!< Timeout count, approximate to be 25us in 50MHz CPU @ Standard mode */
-#endif
-
-#ifndef DW_IIC_CALC_FIFO_LEN_ENABLE
-#define DW_IIC_CALC_FIFO_LEN_ENABLE		(1)	/*!< Default enable calculate fifo length */
-#endif
-
-#ifndef DW_IIC_USE_IC_CLK_MHZ
-#define DW_IIC_USE_IC_CLK_MHZ			(50)	/*!< Default use 50MHz IC_CLK */
-#endif
-
-#ifndef DW_IIC_USE_HS_BUS_LOADING_100PF
-#define DW_IIC_USE_HS_BUS_LOADING_100PF		(1)	/*!< Use bus loading 100pf */
-#endif
-
-#endif /* _DEVICE_DW_IIC_HAL_CFG_H_ */
-
diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi.c b/bsp/synopsys/embarc/device/designware/spi/dw_spi.c
deleted file mode 100644
index bea413b411..0000000000
--- a/bsp/synopsys/embarc/device/designware/spi/dw_spi.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-06-25
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_DW_SPI	Designware SPI Driver
- * \ingroup	DEVICE_DW
- * \brief	Designware SPI Driver Implementation
- */
-
-/**
- * \file
- * \brief	DesignWare SPI driver implementation based on device hal layer definition (\ref dev_spi.h)
- * \ingroup	DEVICE_DW_SPI
- */
-#include <string.h>
-
-#include "inc/embARC_toolchain.h"
-#include "inc/embARC_error.h"
-
-#include "inc/arc/arc_exception.h"
-
-#include "device/designware/spi/dw_spi_hal.h"
-#include "device/designware/spi/dw_spi.h"
-
-/**
- * \defgroup	DEVICE_DW_SPI_DEFINES	DesignWare SPI Driver Macros
- * \ingroup	DEVICE_DW_SPI
- * \brief	DesignWare SPI driver macros used in spi driver
- * @{
- */
-/** check expressions used in DesignWare SPI driver implementation */
-#define DW_SPI_CHECK_EXP(EXPR, ERROR_CODE)		CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
-
-/** convert DesignWare frequence to divisor */
-#define DW_SPI_FREQ2DV(perifreq, spifreq)		((perifreq) / (spifreq))
-
-#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
-/** valid check of spi info object */
-#define VALID_CHK_SPI_INFO_OBJECT(spiinfo_obj_ptr)		{			\
-			DW_SPI_CHECK_EXP((spiinfo_obj_ptr)!=NULL, E_OBJ);		\
-			DW_SPI_CHECK_EXP(((spiinfo_obj_ptr)->spi_ctrl)!=NULL, E_OBJ);	\
- 		}
-#endif
-
-/**
- * \defgroup	DEVICE_DW_SPI_DEF_CBR	DesignWare SPI Interrupt Callback Routine Select Marcos
- * \ingroup	DEVICE_DW_SPI_DEFINES
- * \brief	DesignWare SPI interrupt callback routines select macros definitions
- * @{
- */
-#define DW_SPI_RDY_SND					(1U)	/*!< ready to send callback */
-#define DW_SPI_RDY_RCV					(2U)	/*!< ready to receive callback */
-#define DW_SPI_RDY_XFER					(3U)	/*!< ready to transfer callback */
-/** @} */
-
-/** @} */
-
-/**
- * \defgroup	DEVICE_DW_SPI_STATIC	DesignWare SPI Driver Static Functions
- * \ingroup	DEVICE_DW_SPI
- * \brief	Static or inline functions, variables for DesignWare SPI handle spi operations,
- * 	only used in this file.
- * @{
- */
-
-/** Disable designware spi device */
-Inline void dw_spi_disable(DW_SPI_REG *spi_reg_ptr)
-{
-/** disable spi operations, then program spi control regs is possible */
-	spi_reg_ptr->SSIENR = DW_SPI_SSI_DISABLE;
-}
-/** Enable designware spi device */
-Inline void dw_spi_enable(DW_SPI_REG *spi_reg_ptr)
-{
-	spi_reg_ptr->SSIENR = DW_SPI_SSI_ENABLE;
-}
-
-/** Clear all designware spi interrupt */
-Inline void dw_spi_clear_interrupt_all(DW_SPI_REG *spi_reg_ptr)
-{
-	(void)spi_reg_ptr->ICR;
-}
-
-/** test whether spi is busy, busy return 1, else 0 */
-Inline int32_t dw_spi_busy(DW_SPI_REG *spi_reg_ptr)
-{
-	return ((spi_reg_ptr->SR & DW_SPI_SR_BUSY) != 0);
-}
-/** test whether spi is ready to send, 1 ready, 0 not ready */
-Inline int32_t dw_spi_putready(DW_SPI_REG *spi_reg_ptr)
-{
-	return ((spi_reg_ptr->SR & DW_SPI_SR_TFNF) != 0);
-}
-/** test whether spi is read to receive, 1 ready, 0 not ready */
-Inline int32_t dw_spi_getready(DW_SPI_REG *spi_reg_ptr)
-{
-	return ((spi_reg_ptr->SR & DW_SPI_SR_RFNE) != 0);
-}
-/** write data to spi send fifo */
-Inline void dw_spi_putdata(DW_SPI_REG *spi_reg_ptr, int32_t data)
-{
-	spi_reg_ptr->DATAREG = (uint32_t)data;
-}
-/** read data from spi receive fifo, return data received */
-Inline int32_t dw_spi_getdata(DW_SPI_REG *spi_reg_ptr)
-{
-	return (int32_t)spi_reg_ptr->DATAREG;
-}
-/**
- * \brief	send data by spi when available,
- * 	mostly used in interrupt method, non-blocked function
- * \param[in]	spi_reg_ptr	spi register structure pointer
- * \param[in]	data		data to be sent
- * \retval	E_OK		send successfully
- * \retval	E_OBJ		not ready to send data
- */
-Inline int32_t dw_spi_snd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data)
-{
-	if (dw_spi_putready(spi_reg_ptr)) {
-		dw_spi_putdata(spi_reg_ptr, data);
-		return E_OK;
-	}
-	return E_OBJ;
-}
-/**
- * \brief	receive one char from spi,
- * 	mostly used in interrupt routine, non-blocked function
- * \param[in]	spi_reg_ptr	spi register structure pointer
- * \return	data received by the spi
- */
-Inline int32_t dw_spi_rcv_dat(DW_SPI_REG *spi_reg_ptr)
-{
-	return dw_spi_getdata(spi_reg_ptr);
-}
-/**
- * \brief	send char by spi in poll method, blocked function
- * \param[in]	spi_reg_ptr	spi register structure pointer
- * \param[in]	data		data to be sent
- */
-Inline void dw_spi_psnd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data)
-{
-	/** wait until spi is ready to send */
-	while (!dw_spi_putready(spi_reg_ptr)); /* blocked */
-	/** send char */
-	dw_spi_putdata(spi_reg_ptr, data);
-}
-/**
- * \brief	receive one char from spi in poll method, blocked function
- * \param[in]	spi_reg_ptr	spi register structure pointer
- * \return	data received by the spi
- */
-Inline int32_t dw_spi_prcv_dat(DW_SPI_REG *spi_reg_ptr)
-{
-	/** wait until spi is ready to receive */
-	while (!dw_spi_getready(spi_reg_ptr)); /* blocked */
-	/** receive data */
-	return dw_spi_getdata(spi_reg_ptr);
-}
-
-/** Reset designware FIFO by disable spi device, then enable device */
-Inline void dw_spi_reset_fifo(DW_SPI_REG *spi_reg_ptr)
-{
-	dw_spi_disable(spi_reg_ptr);
-	dw_spi_enable(spi_reg_ptr);
-}
-
-/** Enable designware spi bit interrupt with mask */
-Inline void dw_spi_unmask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask)
-{
-	spi_reg_ptr->IMR |= mask;
-}
-
-/** Disable designware spi bit interrupt with mask */
-Inline void dw_spi_mask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask)
-{
-	spi_reg_ptr->IMR &= ~mask;
-}
-
-/** Set designware spi device frequency */
-Inline void dw_spi_set_freq(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t freq)
-{
-	uint32_t sck_divisor;
-	DW_SPI_REG *spi_reg_ptr = spi_ctrl_ptr->dw_spi_regs;
-
-	dw_spi_disable(spi_reg_ptr);
-
-	sck_divisor = DW_SPI_FREQ2DV(spi_ctrl_ptr->dw_apb_bus_freq, freq);
-	spi_reg_ptr->BAUDR = sck_divisor;
-	dw_spi_enable(spi_reg_ptr);
-}
-
-/** Set designware spi device data frame size */
-static int32_t dw_spi_set_dfs(DW_SPI_REG *spi_reg_ptr, uint32_t dfs)
-{
-	uint32_t ctrl0_reg;
-	if ((dfs <= 3) || (dfs > 16)) return -1;
-
-	dw_spi_disable(spi_reg_ptr);
-	ctrl0_reg = spi_reg_ptr->CTRLR0;
-	ctrl0_reg &= ~(DW_SPI_CTRLR0_DFS_MASK);
-	spi_reg_ptr->CTRLR0 = ctrl0_reg | (dfs-1);
-	dw_spi_enable(spi_reg_ptr);
-
-	return 0;
-}
-
-/** Choose proper designware spi clock mode setting value */
-Inline uint32_t dw_spi_select_clockmode(uint32_t clk_mode)
-{
-	return (clk_mode << DW_SPI_CTRLR0_SC_OFS);
-}
-
-/** Set designware spi clock mode */
-Inline int32_t dw_spi_set_clockmode(DW_SPI_REG *spi_reg_ptr, uint32_t clk_mode)
-{
-	if (clk_mode > SPI_CPOL_1_CPHA_1) {
-		return -1;
-	}
-	dw_spi_disable(spi_reg_ptr);
-	spi_reg_ptr->CTRLR0 &= ~(DW_SPI_CTRLR0_SC_MASK);
-	spi_reg_ptr->CTRLR0 |= dw_spi_select_clockmode(clk_mode);
-	dw_spi_enable(spi_reg_ptr);
-	return 0;
-}
-
-/** Select a spi slave with slv_line */
-Inline int32_t dw_spi_select_slave(DW_SPI_REG *spi_reg_ptr, uint32_t slv_line)
-{
-	/* check if spi busy */
-	if (dw_spi_busy(spi_reg_ptr)) return -1;
-
-	spi_reg_ptr->SER = 1<<slv_line;
-	return 0;
-}
-
-/** Deselect a spi device */
-Inline int32_t dw_spi_deselect_slave(DW_SPI_REG *spi_reg_ptr, uint32_t slv_line)
-{
-	/* check if spi busy */
-	if (dw_spi_busy(spi_reg_ptr)) return -1;
-
-	spi_reg_ptr->SER = 0;
-	return 0;
-}
-
-Inline void dw_spi_flush_tx(DW_SPI_REG *spi_reg_ptr)
-{
-	dw_spi_reset_fifo(spi_reg_ptr);
-}
-
-Inline void dw_spi_flush_rx(DW_SPI_REG *spi_reg_ptr)
-{
-	dw_spi_reset_fifo(spi_reg_ptr);
-}
-
-/** Get TX FIFO Length.
- *    calculate spi fifo length using fifo threshold method
- *  If you attempt to set bits [7:0] of this register to
- *  a value greater than or equal to the depth of the FIFO,
- *  this field is not written and retains its current value.
- */
-static uint32_t dw_spi_get_txfifo_len(DW_SPI_REG *spi_reg_ptr)
-{
-	uint32_t fifo_thr_lev_tmp, left, right, i;
-
-	fifo_thr_lev_tmp = spi_reg_ptr->TXFTLR;
-
-	if (fifo_thr_lev_tmp != 0) {
-		left = fifo_thr_lev_tmp;
-	} else {
-		left = DW_SPI_MIN_FIFO_LENGTH;
-	}
-	right = DW_SPI_MAX_FIFO_LENGTH + 1;
-
-	for (i = left; i <= right; i++) {
-		spi_reg_ptr->TXFTLR = i;
-		if (spi_reg_ptr->TXFTLR != i) {
-			break;
-		}
-	}
-	spi_reg_ptr->TXFTLR = fifo_thr_lev_tmp; /* restore old fifo threshold */
-
-	return (i);
-}
-
-/** Get RX FIFO Length */
-static uint32_t dw_spi_get_rxfifo_len(DW_SPI_REG *spi_reg_ptr)
-{
-	uint32_t fifo_thr_lev_tmp, left, right, i;
-
-	fifo_thr_lev_tmp = spi_reg_ptr->RXFTLR;
-
-	if (fifo_thr_lev_tmp != 0) {
-		left = fifo_thr_lev_tmp;
-	} else {
-		left = DW_SPI_MIN_FIFO_LENGTH;
-	}
-	right = DW_SPI_MAX_FIFO_LENGTH + 1;
-
-	for (i = left; i <= right; i++) {
-		spi_reg_ptr->RXFTLR = i;
-		if (spi_reg_ptr->RXFTLR != i) {
-			break;
-		}
-	}
-	spi_reg_ptr->RXFTLR = fifo_thr_lev_tmp; /* restore old fifo threshold */
-
-	return (i);
-}
-
-/** Init Designware SPI Hardware */
-static void dw_spi_hw_init(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t clk_mode, uint32_t dfs)
-{
-	uint32_t ctrl0_reg = 0;
-	DW_SPI_REG *spi_reg_ptr = spi_ctrl_ptr->dw_spi_regs;
-
-	dw_spi_disable(spi_reg_ptr);
-
-	/* Clear interrupts */
-	ctrl0_reg = spi_reg_ptr->ICR;
-	/* Mask all interrupts */
-	spi_reg_ptr->IMR = 0;
-
-	ctrl0_reg = DW_SPI_CTRLR0_FRF_MOTOROLA | DW_SPI_TMOD_TRANSMIT_RECEIVE \
-			| dw_spi_select_clockmode(clk_mode) | (dfs - 1) | DW_SPI_CTRLR0_SLV_OE_ENABLE;
-	spi_reg_ptr->CTRLR0 = ctrl0_reg;
-	spi_reg_ptr->CTRLR1 = 0;
-
-	/* deselect slaves */
-	spi_reg_ptr->SER = 0;
-
-	/* Set threshold values for both tx and rx */
-	spi_reg_ptr->TXFTLR = 0;
-	spi_reg_ptr->RXFTLR = 0;
-
-	dw_spi_enable(spi_reg_ptr);
-}
-
-/** enable designware spi */
-static void dw_spi_enable_device(DEV_SPI_INFO *spi_info_ptr)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-
-	if ((spi_info_ptr->status & DEV_ENABLED) == 0) {
-		dw_spi_enable(spi_reg_ptr);
-		spi_info_ptr->status |= DEV_ENABLED;
-	}
-}
-
-/** disable designware spi */
-static void dw_spi_disable_device(DEV_SPI_INFO *spi_info_ptr)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-
-	dw_spi_disable(spi_reg_ptr);
-	spi_info_ptr->status &= ~DEV_ENABLED;
-}
-
-
-/**
- * \brief	disable designware spi send or receive interrupt
- * \param[in]	DEV_SPI_INFO 	*spi_info_ptr
- * \param[in]	cbrtn		control code of callback routine of send or receive
- */
-static int32_t dw_spi_dis_cbr(DEV_SPI_INFO *spi_info_ptr, uint32_t cbrtn)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-	int32_t ercd = E_OK;
-
-	if ((spi_info_ptr->status & DW_SPI_IN_XFER) != 0) { /* only in transfer need do check */
-		switch (cbrtn) {
-			case DW_SPI_RDY_SND:
-				DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX, E_CTX);
-				spi_info_ptr->status &= ~(DW_SPI_IN_TX);
-				break;
-			case DW_SPI_RDY_RCV:
-				DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX, E_CTX);
-				spi_info_ptr->status &= ~(DW_SPI_IN_RX);
-				break;
-			case DW_SPI_RDY_XFER:
-				DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER, E_CTX);
-				spi_info_ptr->status &= ~(DW_SPI_IN_XFER);
-				break;
-			default:
-				break;
-		}
-	}
-
-	dw_spi_mask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER);
-
-	if (spi_ctrl_ptr->int_status & DW_SPI_GINT_ENABLE) {
-		int_disable(spi_ctrl_ptr->intno);
-		spi_ctrl_ptr->int_status &= ~DW_SPI_GINT_ENABLE;
-	}
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	enable DesignWare SPI send or receive interrupt
- * \param[in]	DEV_SPI_INFO 	*spi_info_ptr
- * \param[in]	cbrtn		control code of callback routine of send or receive
- */
-static int32_t dw_spi_ena_cbr(DEV_SPI_INFO *spi_info_ptr, uint32_t cbrtn)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-	int32_t ercd = E_OK;
-
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == 0, E_CTX);
-	switch (cbrtn) {
-		case DW_SPI_RDY_SND:
-			spi_info_ptr->status |= DW_SPI_IN_TX;
-			break;
-		case DW_SPI_RDY_RCV:
-			spi_info_ptr->status |= DW_SPI_IN_RX;
-			break;
-		case DW_SPI_RDY_XFER:
-			spi_info_ptr->status |= DW_SPI_IN_XFER;
-			break;
-		default:
-			break;
-	}
-	dw_spi_unmask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER);
-
-	if ((spi_ctrl_ptr->int_status & DW_SPI_GINT_ENABLE) == 0) {
-		spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE;
-		int_enable(spi_ctrl_ptr->intno);
-	}
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	enable designware spi interrupt
- * \param	spi_info_ptr	spi information structure pointer
- */
-static void dw_spi_enable_interrupt(DEV_SPI_INFO *spi_info_ptr)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-
-	int_handler_install(spi_ctrl_ptr->intno, spi_ctrl_ptr->dw_spi_int_handler);
-	spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE;
-	int_enable(spi_ctrl_ptr->intno);	/** enable spi interrupt */
-}
-/**
- * \brief	disable designware spi interrupt
- * \param	spi_info_ptr	spi information structure pointer
- */
-static void dw_spi_disable_interrupt(DEV_SPI_INFO *spi_info_ptr)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-
-	/** disable spi send&receive interrupt after disable spi interrupt */
-	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND);
-	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
-	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
-	/* disable spi interrupt */
-	dw_spi_mask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER);
-	spi_info_ptr->status &= ~DW_SPI_IN_XFER;
-	int_disable(spi_ctrl_ptr->intno);
-	spi_ctrl_ptr->int_status &= ~(DW_SPI_GINT_ENABLE);
-}
-
-static void dw_spi_reset_device(DEV_SPI_INFO *spi_info_ptr)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-
-	dw_spi_disable_device(spi_info_ptr);
-	dw_spi_disable_interrupt(spi_info_ptr);
-	dw_spi_clear_interrupt_all(spi_reg_ptr);
-	dw_spi_enable_device(spi_info_ptr);
-}
-
-/** abort current interrupt transmit transfer */
-static int32_t dw_spi_abort_tx(DEV_SPI *spi_obj)
-{
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-	int32_t ercd = E_OK;
-
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK);
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX, E_CTX);
-
-	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND);
-	spi_info_ptr->status |= DEV_IN_TX_ABRT;
-	if (spi_info_ptr->spi_cbs.tx_cb != NULL) {
-		spi_info_ptr->spi_cbs.tx_cb(spi_obj);
-	}
-	spi_info_ptr->status &= ~(DEV_IN_TX_ABRT);
-
-error_exit:
-	return ercd;
-}
-
-/** abort current interrupt receive transfer */
-static int32_t dw_spi_abort_rx(DEV_SPI *spi_obj)
-{
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-	int32_t ercd = E_OK;
-
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK);
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX, E_CTX);
-
-	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
-	spi_info_ptr->status |= DEV_IN_RX_ABRT;
-	if (spi_info_ptr->spi_cbs.rx_cb != NULL) {
-		spi_info_ptr->spi_cbs.rx_cb(spi_obj);
-	}
-	spi_info_ptr->status &= ~(DEV_IN_RX_ABRT);
-
-error_exit:
-	return ercd;
-}
-
-/** abort current interrupt transfer */
-static int32_t dw_spi_abort_xfer(DEV_SPI *spi_obj)
-{
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-	int32_t ercd = E_OK;
-
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK);
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER, E_CTX);
-
-	dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
-	spi_info_ptr->status |= DEV_IN_XFER_ABRT;
-	if (spi_info_ptr->spi_cbs.xfer_cb != NULL) {
-		spi_info_ptr->spi_cbs.xfer_cb(spi_obj);
-	}
-	spi_info_ptr->status &= ~(DEV_IN_XFER_ABRT);
-
-error_exit:
-	return ercd;
-}
-
-/** Get available transmit fifo count */
-static int32_t dw_spi_get_txavail(DW_SPI_CTRL *spi_ctrl_ptr)
-{
-	int32_t tx_avail = 0;
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-
-#if DW_SPI_CALC_FIFO_LEN_ENABLE
-	if (spi_ctrl_ptr->tx_fifo_len <= 1) {
-		if (dw_spi_putready(spi_reg_ptr) == 1) {
-			tx_avail = 1;
-		} else {
-			tx_avail = 0;
-		}
-	} else
-#endif
-	{
-		tx_avail = spi_ctrl_ptr->tx_fifo_len - spi_reg_ptr->TXFLR;
-	}
-	return tx_avail;
-}
-
-/** Get available receive fifo count */
-static int32_t dw_spi_get_rxavail(DW_SPI_CTRL *spi_ctrl_ptr)
-{
-	int32_t rx_avail = 0;
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-
-#if DW_SPI_CALC_FIFO_LEN_ENABLE
-	if (spi_ctrl_ptr->rx_fifo_len <= 1) {
-		if (dw_spi_getready(spi_reg_ptr) == 1) {
-			rx_avail = 1;
-		} else {
-			rx_avail = 0;
-		}
-	} else
-#endif
-	{
-		rx_avail = spi_reg_ptr->RXFLR;
-	}
-	return rx_avail;
-}
-
-static uint32_t dw_spi_tx_max(DW_SPI_CTRL *spi_ctrl_ptr)
-{
-	uint32_t tx_left, tx_room;
-	DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer);
-
-	tx_left = (xfer->xfer_len - xfer->tx_idx) / xfer->nbytes;
-	tx_room = dw_spi_get_txavail(spi_ctrl_ptr);
-
-	return (tx_left < tx_room) ? tx_left : tx_room;
-}
-
-static uint32_t dw_spi_rx_max(DW_SPI_CTRL *spi_ctrl_ptr)
-{
-	uint32_t rx_left, rx_room;
-	DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer);
-
-	rx_left = (xfer->xfer_len - xfer->rx_idx) / xfer->nbytes;
-	rx_room = dw_spi_get_rxavail(spi_ctrl_ptr);
-
-	return (rx_left < rx_room) ? rx_left : rx_room;
-}
-
-Inline int32_t dw_spi_rx_end(DW_SPI_CTRL *spi_ctrl_ptr)
-{
-	DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer);
-
-	return (xfer->rx_idx >= xfer->xfer_len);
-}
-
-Inline int32_t dw_spi_tx_end(DW_SPI_CTRL *spi_ctrl_ptr)
-{
-	DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer);
-
-	return (xfer->tx_idx >= xfer->xfer_len);
-}
-
-/** 1 for end, 0 for not end */
-Inline int32_t dw_spi_xfer_end(DW_SPI_CTRL *spi_ctrl_ptr)
-{
-	return (dw_spi_tx_end(spi_ctrl_ptr) && dw_spi_rx_end(spi_ctrl_ptr));
-}
-
-static int32_t dw_spi_writer(DEV_SPI_INFO *spi_info_ptr)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
-	DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer);
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-	uint32_t tx_max = dw_spi_tx_max(spi_ctrl_ptr);
-	int32_t tx_w;
-	uint32_t tx_cnt = tx_max;
-
-	if (dw_xfer->tx_xfer == NULL) {
-		return 0;
-	}
-	while (tx_max) {
-		if (dw_xfer->tx_xfer->tx_idx >= dw_xfer->tx_xfer->tot_len) {
-			dw_xfer->tx_xfer = dw_xfer->tx_xfer->next;
-			if (dw_xfer->tx_xfer == NULL) {
-				break;
-			}
-		}
-		if ( (dw_xfer->tx_xfer->tx_idx >= dw_xfer->tx_xfer->tx_ofs) \
-			&& (dw_xfer->tx_xfer->tx_idx < dw_xfer->tx_xfer->tx_totlen)) {
-			if (dw_xfer->nbytes == 1) {
-				tx_w = (int32_t)(*(int8_t *)(dw_xfer->tx_xfer->tx_buf));
-			} else {
-				tx_w = (int32_t)(*(int16_t *)(dw_xfer->tx_xfer->tx_buf));
-			}
-			dw_xfer->tx_xfer->tx_buf += dw_xfer->nbytes;
-		} else {
-			tx_w = spi_info_ptr->dummy;
-		}
-		dw_spi_putdata(spi_reg_ptr, tx_w);
-		dw_xfer->tx_xfer->tx_idx += dw_xfer->nbytes;
-		dw_xfer->tx_idx += dw_xfer->nbytes;
-		tx_max --;
-	}
-	return ((tx_cnt-tx_max) * dw_xfer->nbytes);
-}
-
-static int32_t dw_spi_reader(DEV_SPI_INFO *spi_info_ptr)
-{
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
-	DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer);
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-	uint32_t rx_max = dw_spi_rx_max(spi_ctrl_ptr);
-	int32_t rx_w;
-	uint32_t rx_cnt = rx_max;
-
-	if (dw_xfer->rx_xfer == NULL) {
-		return 0;
-	}
-	while (rx_max) {
-		if (dw_xfer->rx_xfer->rx_idx >= dw_xfer->rx_xfer->tot_len) {
-			dw_xfer->rx_xfer = dw_xfer->rx_xfer->next;
-			if (dw_xfer->rx_xfer == NULL) {
-				break;
-			}
-		}
-		rx_w = dw_spi_getdata(spi_reg_ptr);
-		if ( (dw_xfer->rx_xfer->rx_idx >= dw_xfer->rx_xfer->rx_ofs) \
-			&& (dw_xfer->rx_xfer->rx_idx < dw_xfer->rx_xfer->rx_totlen) ) {
-			if (dw_xfer->nbytes == 1) {
-				*(int8_t *)(dw_xfer->rx_xfer->rx_buf) = rx_w;
-			} else {
-				*(int16_t *)(dw_xfer->rx_xfer->rx_buf) = rx_w;
-			}
-			dw_xfer->rx_xfer->rx_buf += dw_xfer->nbytes;
-		}
-		dw_xfer->rx_xfer->rx_idx += dw_xfer->nbytes;
-		dw_xfer->rx_idx += dw_xfer->nbytes;
-		rx_max --;
-	}
-	return ((rx_cnt-rx_max) * dw_xfer->nbytes);
-}
-
-Inline uint32_t dw_spi_nbytes(uint32_t dfs)
-{
-	uint32_t nbytes = 1;
-
-	if (dfs > 8) nbytes = 2;
-	return nbytes;
-}
-
-static void dw_spi_init_transfer(DW_SPI_CTRL *spi_ctrl_ptr, DEV_SPI_TRANSFER *xfer, uint32_t dfs)
-{
-	DW_SPI_TRANSFER *dw_xfer= &(spi_ctrl_ptr->dw_xfer);
-	uint32_t tot_len = 0;
-
-	dw_xfer->tx_xfer = xfer;
-	dw_xfer->rx_xfer = xfer;
-	dw_xfer->tx_idx = 0;
-	dw_xfer->rx_idx = 0;
-	dw_xfer->nbytes = dw_spi_nbytes(dfs);
-
-	/** Calculate all transfer length */
-	while (xfer) {
-		DEV_SPI_XFER_INIT(xfer);
-		tot_len += xfer->tot_len;
-		xfer = xfer->next;
-	}
-	dw_xfer->xfer_len = tot_len;
-}
-
-/* Check buffer align status, 0 for aligned, -1 for not-aligned */
-static int32_t dw_spi_chk_xfer_aligned(DEV_SPI_TRANSFER *xfer, uint32_t dfs)
-{
-	uint32_t align_bytes = 1;
-	if (xfer == NULL) return -1;
-
-	if (dfs > 8) {
-		align_bytes = 2;
-	} else {
-		return 0;
-	}
-
-	while (xfer) {
-		/* check tx buffer align status */
-		if (xfer->tx_len != 0) {
-			if (xfer->tx_len % align_bytes) return -1;
-			if (xfer->tx_ofs % align_bytes) return -1;
-			if (!CHECK_ALIGN_BYTES(xfer->tx_buf, align_bytes)) return -1;
-		}
-		/* check tx buffer align status */
-		if (xfer->rx_len != 0) {
-			if (xfer->rx_len % align_bytes) return -1;
-			if (xfer->rx_ofs % align_bytes) return -1;
-			if (!CHECK_ALIGN_BYTES(xfer->rx_buf, align_bytes)) return -1;
-		}
-		xfer = xfer->next;
-	}
-	return 0;
-}
-
-static uint32_t dw_spi_poll_transfer(DEV_SPI_INFO *spi_info_ptr)
-{
-	uint32_t len = 0;
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
-
-	spi_info_ptr->status |= DEV_IN_XFER;
-	while (!dw_spi_xfer_end(spi_ctrl_ptr)) {
-		len += dw_spi_writer(spi_info_ptr);
-		len += dw_spi_reader(spi_info_ptr);
-	}
-	spi_info_ptr->status &= ~DEV_IN_XFER;
-
-	return len>>1;
-}
-
-/** @} */
-
-/**
- * \brief	open a designware spi device
- * \param[in]	spi_obj	spi object pointer
- * \param[in]	mode	spi working mode (master or slave)
- * \param[in]	param	parameter, for master, param is the freq, for slave, param is dfs
- * \retval	E_OK	Open successfully without any issues
- * \retval	E_OPNED	If device was opened before with different parameters,
- *			then just increase the \ref dev_spi_info::opn_cnt "opn_cnt" and return \ref E_OPNED
- * \retval	E_OBJ	Device object is not valid
- * \retval	E_SYS	Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first.
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_NOSPT	Open settings are not supported
- */
-int32_t dw_spi_open (DEV_SPI *spi_obj, uint32_t mode, uint32_t param)
-{
-	int32_t ercd = E_OK;
-	uint32_t param2check;
-	uint32_t clk_mode, dfs_val;
-	uint32_t support_modes;
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
-	DW_SPI_CHECK_EXP((mode==DEV_MASTER_MODE)||(mode==DEV_SLAVE_MODE), E_PAR);
-	if (mode == DEV_SLAVE_MODE) { /* clock mode should be in the enum structure */
-		DW_SPI_CHECK_EXP((param>=SPI_CPOL_0_CPHA_0) && (param<=SPI_CPOL_1_CPHA_1), E_PAR);
-	} else { /* frequence should > 0 */
-		DW_SPI_CHECK_EXP(param>0, E_PAR);
-	}
-	/* END OF ERROR CHECK */
-
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
-
-	/* Check supported modes, master or slave */
-	support_modes = spi_ctrl_ptr->support_modes;
-	DW_SPI_CHECK_EXP( (((support_modes)&DW_SPI_MASTER_SUPPORTED)&&(mode == DEV_MASTER_MODE)) || \
-				(((support_modes)&DW_SPI_SLAVE_SUPPORTED)&&(mode == DEV_SLAVE_MODE)), E_NOSPT);
-
-	/** Check opened before use case */
-	if (spi_info_ptr->opn_cnt > 0) {
-		if (mode != spi_info_ptr->mode) {
-			/* current working mode is different from passing mode */
-			return E_SYS;
-		}
-		if (mode == DEV_MASTER_MODE) { /* param is freq when as master */
-			param2check = spi_info_ptr->freq;
-		} else { /* param is clk_mode when as slave */
-			param2check = spi_info_ptr->clk_mode;
-		}
-		spi_info_ptr->opn_cnt ++;
-		if (param != param2check) { /* open with different speed mode */
-			return E_OPNED;
-		} else {
-			return E_OK;
-		}
-	}
-	/* auto increase open count */
-	spi_info_ptr->opn_cnt ++;
-
-	/* Do FIFO Length get before init */
-#if DW_SPI_CALC_FIFO_LEN_ENABLE
-	spi_ctrl_ptr->tx_fifo_len = dw_spi_get_txfifo_len(spi_ctrl_ptr->dw_spi_regs);
-	spi_ctrl_ptr->rx_fifo_len = dw_spi_get_rxfifo_len(spi_ctrl_ptr->dw_spi_regs);
-#endif
-	/* hardware init */
-	spi_info_ptr->mode = mode;
-	clk_mode = SPI_CLK_MODE_DEFAULT;
-	dfs_val = SPI_DFS_DEFAULT;
-	if (mode == DEV_SLAVE_MODE) {
-		clk_mode = param;
-	}
-	spi_info_ptr->dfs = dfs_val;
-	spi_info_ptr->clk_mode = clk_mode;
-	dw_spi_hw_init(spi_ctrl_ptr, clk_mode, dfs_val);
-	if (mode == DEV_MASTER_MODE) { /* Deselect all slaves, and set frequence */
-		dw_spi_deselect_slave(spi_ctrl_ptr->dw_spi_regs, 0);
-		dw_spi_set_freq(spi_ctrl_ptr, param);
-		spi_info_ptr->freq = param;
-	}
-
-	spi_info_ptr->status = DEV_ENABLED;
-	spi_info_ptr->extra = NULL;
-	spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED;
-	spi_info_ptr->dummy = 0xff;
-
-	spi_ctrl_ptr->int_status = 0;
-	dw_spi_init_transfer(spi_ctrl_ptr, NULL, dfs_val);
-
-	/** install spi interrupt into system */
-	dw_spi_disable_interrupt(spi_info_ptr);
-	int_handler_install(spi_ctrl_ptr->intno, spi_ctrl_ptr->dw_spi_int_handler);
-	memset(&(spi_info_ptr->xfer), 0, sizeof(DEV_SPI_TRANSFER));
-	memset(&(spi_info_ptr->spi_cbs), 0, sizeof(DEV_SPI_CBS));
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	close a DesignWare SPI device
- * \param[in]	spi_obj	spi object pointer
- * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
- * \retval	E_OPNED	Device is still opened, the device \ref dev_spi_info::opn_cnt "opn_cnt" decreased by 1
- * \retval	E_OBJ	Device object is not valid
- */
-int32_t dw_spi_close (DEV_SPI *spi_obj)
-{
-	int32_t ercd = E_OK;
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
-	DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_OK);
-	/* END OF ERROR CHECK */
-
-	spi_info_ptr->opn_cnt --;
-	if (spi_info_ptr->opn_cnt == 0) {
-		DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-
-		dw_spi_disable_interrupt(spi_info_ptr);
-		dw_spi_abort_tx(spi_obj);
-		dw_spi_abort_rx(spi_obj);
-		memset(&(spi_info_ptr->xfer), 0, sizeof(DEV_SPI_TRANSFER));
-		memset(&(spi_info_ptr->spi_cbs), 0, sizeof(DEV_SPI_CBS));
-		memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER));
-		dw_spi_disable_device(spi_info_ptr);
-		spi_info_ptr->status = DEV_DISABLED;
-		spi_info_ptr->extra = NULL;
-	} else {
-		ercd = E_OPNED;
-	}
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	control spi by ctrl command
- * \param[in]		spi_obj		spi object pointer
- * \param[in]		ctrl_cmd	control command code to do specific spi work
- * \param[in,out]	param		parameters used to control spi or return something
- * \retval	E_OK	Control device successfully
- * \retval	E_CLSED	Device is not opened
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
- * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
- * \retval	E_NOSPT	Control command is not supported or not valid
- */
-int32_t dw_spi_control (DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param)
-{
-	int32_t ercd = E_OK;
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
-	DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED);
-	/* END OF ERROR CHECK */
-
-	uint32_t val32; /** to receive unsigned int value */
-	DEV_BUFFER *devbuf;
-
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl);
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-	DEV_SPI_TRANSFER *spi_xfer = &(spi_info_ptr->xfer);
-
-	/* check whether current device is disabled */
-	if ((spi_info_ptr->status & DEV_ENABLED) == 0) {
-		/** When device is disabled,
-		 * only SPI_CMD_ENA_DEV, SPI_CMD_DIS_DEV, SPI_CMD_GET_STATUS, SPI_CMD_RESET
-		 * are available, other commands will return E_SYS
-		 */
-		if ((ctrl_cmd != SPI_CMD_ENA_DEV) && \
-			(ctrl_cmd != SPI_CMD_DIS_DEV) && \
-			(ctrl_cmd != SPI_CMD_GET_STATUS) && \
-			(ctrl_cmd != SPI_CMD_RESET) ) {
-			return E_SYS;
-		}
-	}
-
-	switch (ctrl_cmd) {
-		/* Commmon commands for both master and slave mode */
-		case SPI_CMD_GET_STATUS:
-			DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = spi_info_ptr->status;
-			break;
-		case SPI_CMD_SET_CLK_MODE:
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			val32 = (uint32_t)param;
-			DW_SPI_CHECK_EXP((val32>=SPI_CPOL_0_CPHA_0) && (val32<=SPI_CPOL_1_CPHA_1), E_PAR);
-			if (dw_spi_set_clockmode(spi_reg_ptr, val32) == 0) {
-				spi_info_ptr->clk_mode = val32;
-			} else {
-				ercd = E_SYS;
-			}
-			break;
-		case SPI_CMD_ENA_DEV:
-			dw_spi_enable_device(spi_info_ptr);
-			break;
-		case SPI_CMD_DIS_DEV:
-			dw_spi_disable_device(spi_info_ptr);
-			break;
-		case SPI_CMD_RESET:
-			dw_spi_reset_device(spi_info_ptr);
-			break;
-		case SPI_CMD_FLUSH_TX:
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			dw_spi_flush_tx(spi_reg_ptr);
-			break;
-		case SPI_CMD_FLUSH_RX:
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			dw_spi_flush_rx(spi_reg_ptr);
-			break;
-		case SPI_CMD_SET_DFS:
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			val32 = (uint32_t)param;
-			DW_SPI_CHECK_EXP(val32>0, E_PAR);
-			if (dw_spi_set_dfs(spi_reg_ptr, val32) == 0) {
-				spi_info_ptr->dfs = val32;
-			} else {
-				ercd = E_SYS;
-			}
-			break;
-		case SPI_CMD_SET_DUMMY_DATA:
-			val32 = (uint32_t)param;
-			spi_info_ptr->dummy = val32;
-			break;
-		case SPI_CMD_GET_RXAVAIL: /* Notice in bytes unit */
-			DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = dw_spi_get_rxavail(spi_ctrl_ptr) * dw_spi_nbytes(spi_info_ptr->dfs);
-			break;
-		case SPI_CMD_GET_TXAVAIL: /* Notice in bytes unit */
-			DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = dw_spi_get_txavail(spi_ctrl_ptr) * dw_spi_nbytes(spi_info_ptr->dfs);
-			break;
-		case SPI_CMD_SET_TXCB:
-			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			spi_info_ptr->spi_cbs.tx_cb = param;
-			break;
-		case SPI_CMD_SET_RXCB:
-			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			spi_info_ptr->spi_cbs.rx_cb = param;
-			break;
-		case SPI_CMD_SET_XFERCB:
-			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			spi_info_ptr->spi_cbs.xfer_cb = param;
-			break;
-		case SPI_CMD_SET_ERRCB:
-			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			spi_info_ptr->spi_cbs.err_cb = param;
-			break;
-		case SPI_CMD_ABORT_TX:
-			ercd = dw_spi_abort_tx(spi_obj);
-			break;
-		case SPI_CMD_ABORT_RX:
-			ercd = dw_spi_abort_rx(spi_obj);
-			break;
-		case SPI_CMD_ABORT_XFER:
-			ercd = dw_spi_abort_xfer(spi_obj);
-			break;
-		case SPI_CMD_SET_TXINT:
-			val32 = (uint32_t)param;
-			if (val32 == 0) {
-				ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND);
-			} else {
-				ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_SND);
-			}
-			break;
-		case SPI_CMD_SET_RXINT:
-			val32 = (uint32_t)param;
-			if (val32 == 0) {
-				ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
-			} else {
-				ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
-			}
-			break;
-		case SPI_CMD_SET_TXINT_BUF:
-			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			if (param != NULL) {
-				devbuf = (DEV_BUFFER *)param;
-				DEV_SPI_XFER_SET_TXBUF(spi_xfer, devbuf->buf, 0, devbuf->len);
-				DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, devbuf->len, 0);
-				DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL);
-				DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(spi_xfer, spi_info_ptr->dfs) == 0, E_PAR);
-				dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs);
-			} else {
-				DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, 0, 0);
-				DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, 0, 0);
-				DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL);
-				dw_spi_init_transfer(spi_ctrl_ptr, NULL, spi_info_ptr->dfs);
-			}
-			break;
-		case SPI_CMD_SET_RXINT_BUF:
-			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			if (param != NULL) {
-				devbuf = (DEV_BUFFER *)param;
-				DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, devbuf->len, 0);
-				DEV_SPI_XFER_SET_RXBUF(spi_xfer, devbuf->buf, 0, devbuf->len);
-				DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL);
-				/* Check transfer align */
-				DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(spi_xfer, spi_info_ptr->dfs) == 0, E_PAR);
-				dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs);
-			} else {
-				DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, 0, 0);
-				DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, 0, 0);
-				DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL);
-				dw_spi_init_transfer(spi_ctrl_ptr, NULL, spi_info_ptr->dfs);
-			}
-			break;
-		case SPI_CMD_TRANSFER_POLLING:
-			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			if (param != NULL) {
-				/* Check transfer align */
-				DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned((DEV_SPI_TRANSFER *)param, spi_info_ptr->dfs) == 0, E_PAR);
-				*spi_xfer = *((DEV_SPI_TRANSFER *)param);
-				dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs);
-				/* Transfer data by poll */
-				dw_spi_poll_transfer(spi_info_ptr);
-			} else {
-				ercd = E_PAR;
-			}
-			break;
-		case SPI_CMD_TRANSFER_INT:
-			DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			if (param != NULL) {
-				DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-				/* Check transfer align */
-				DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned((DEV_SPI_TRANSFER *)param, spi_info_ptr->dfs) == 0, E_PAR);
-				*spi_xfer = *((DEV_SPI_TRANSFER *)param);
-				dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs);
-				/* Transfer data by interrupt */
-				ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
-			} else {
-				ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
-			}
-			break;
-
-		/* Master mode only commands */
-		case SPI_CMD_MST_SET_FREQ:
-			DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			val32 = (uint32_t)param;
-			DW_SPI_CHECK_EXP(val32>0, E_PAR);
-			dw_spi_set_freq(spi_ctrl_ptr, val32);
-			spi_info_ptr->freq = val32;
-			break;
-		case SPI_CMD_MST_SEL_DEV:
-			DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			val32 = (uint32_t)param;
-			if (dw_spi_select_slave(spi_reg_ptr, val32) == 0) {
-				spi_info_ptr->slave = val32;
-			} else {
-				ercd = E_SYS;
-			}
-			break;
-		case SPI_CMD_MST_DSEL_DEV:
-			DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT);
-			DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-			val32 = (uint32_t)param;
-			if (dw_spi_deselect_slave(spi_reg_ptr, val32) == 0) {
-				spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED;
-			} else {
-				ercd = E_SYS;
-			}
-			break;
-
-		/* Slave mode only commands */
-
-
-		default:
-			ercd = E_NOSPT;
-			break;
-	}
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	send data through DesignWare SPI
- * \param[in]	spi_obj	spi object pointer
- * \param[in]	data	pointer to data need to send by spi
- * \param[in]	len	length of data to be sent
- * \retval	>0	Byte count that was successfully sent for poll method
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_CTX	Device is still in transfer state
- * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
- */
-int32_t dw_spi_write (DEV_SPI *spi_obj, const void *data, uint32_t len)
-{
-	int32_t ercd = E_OK;
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
-	DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED);
-	DW_SPI_CHECK_EXP(spi_info_ptr->status & DEV_ENABLED, E_SYS);
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-	DW_SPI_CHECK_EXP(data!=NULL, E_PAR);
-	DW_SPI_CHECK_EXP(len>0, E_PAR);
-	/* END OF ERROR CHECK */
-
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
-	DEV_SPI_TRANSFER spi_xfer;
-
-	/* Master and Slave transmit */
-	DEV_SPI_XFER_SET_TXBUF(&spi_xfer, data, 0, len);
-	DEV_SPI_XFER_SET_RXBUF(&spi_xfer, NULL, len, 0);
-	DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL);
-
-	/* Check transfer align */
-	DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(&spi_xfer, spi_info_ptr->dfs) == 0, E_PAR);
-
-	dw_spi_init_transfer(spi_ctrl_ptr, &spi_xfer, spi_info_ptr->dfs);
-
-	ercd = dw_spi_poll_transfer(spi_info_ptr);
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	read data through DesignWare SPI
- * \param[in]	spi_info_ptr	spi information structure pointer
- * \param[out]	data		data that need to read (data must be char type)
- * \param[in]	len		data count need to read
- * \retval	>=0		data have been read
- * \retval	E_PAR		arguments passed was wrong
- * \retval	E_OBJ		spi has something error, nothing can be done
- * \retval	E_CLSED		spi was closed, not available for control
- * \retval	<0		other error code not defined here
- */
-int32_t dw_spi_read (DEV_SPI *spi_obj, void *data, uint32_t len)
-{
-	int32_t ercd = E_OK;
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
-	DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED);
-	DW_SPI_CHECK_EXP(spi_info_ptr->status & DEV_ENABLED, E_SYS);
-	DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX);
-	DW_SPI_CHECK_EXP(data!=NULL, E_PAR);
-	DW_SPI_CHECK_EXP(len>0, E_PAR);
-	/* END OF ERROR CHECK */
-
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
-	DEV_SPI_TRANSFER spi_xfer;
-
-	/* Master and Slave transmit */
-	DEV_SPI_XFER_SET_TXBUF(&spi_xfer, NULL, len, 0);
-	DEV_SPI_XFER_SET_RXBUF(&spi_xfer, data, 0, len);
-	DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL);
-
-	/* Check transfer align */
-	DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(&spi_xfer, spi_info_ptr->dfs) == 0, E_PAR);
-
-	dw_spi_init_transfer(spi_ctrl_ptr, &spi_xfer, spi_info_ptr->dfs);
-
-	ercd = dw_spi_poll_transfer(spi_info_ptr);
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	DesignWare SPI interrupt processing routine
- * \param[in]	spi_info_ptr	DEV_SPI_INFO *spi_info_ptr
- * \param[in]	ptr		extra information
- */
-void dw_spi_isr(DEV_SPI *spi_obj, void *ptr)
-{
-	int32_t ercd = E_OK;
-	DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr);
-	/* END OF ERROR CHECK */
-
-	DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl);
-	DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs);
-
-	uint32_t isr_status;
-
-	isr_status = spi_reg_ptr->ISR;
-
-	if (!isr_status) return;
-	if (spi_ctrl_ptr->dw_xfer.xfer_len == 0) {
-		dw_spi_disable_interrupt(spi_info_ptr);
-	} else {
-		if (isr_status & (DW_SPI_IMR_TXOIM|DW_SPI_IMR_RXOIM|DW_SPI_IMR_RXUIM)) {
-			dw_spi_clear_interrupt_all(spi_reg_ptr);
-			dw_spi_disable_interrupt(spi_info_ptr);
-			if (spi_info_ptr->spi_cbs.err_cb) {
-				spi_info_ptr->spi_cbs.err_cb(spi_obj);
-			}
-			memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER));
-		}
-		dw_spi_reader(spi_info_ptr);
-		if (isr_status & DW_SPI_IMR_TXEIM) {
-			dw_spi_writer(spi_info_ptr);
-		}
-		if (dw_spi_xfer_end(spi_ctrl_ptr)) {
-			if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX) {
-				dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND);
-				if (spi_info_ptr->spi_cbs.tx_cb) {
-					spi_info_ptr->spi_cbs.tx_cb(spi_obj);
-				}
-			} else if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX) {
-				dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV);
-				if (spi_info_ptr->spi_cbs.rx_cb) {
-					spi_info_ptr->spi_cbs.rx_cb(spi_obj);
-				}
-			} else if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER) {
-				dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER);
-				if (spi_info_ptr->spi_cbs.xfer_cb) {
-					spi_info_ptr->spi_cbs.xfer_cb(spi_obj);
-				}
-			} else {
-				dw_spi_disable_interrupt(spi_info_ptr);
-			}
-			memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER));
-		}
-	}
-
-error_exit:
-	return;
-}
-/** @} */ /* DEVICE_DW_SPI_IMPLEMENT */
-
-/** @} */ /* DEVICE_DW_SPI */
diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi.h
deleted file mode 100644
index ef2faa90e6..0000000000
--- a/bsp/synopsys/embarc/device/designware/spi/dw_spi.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-06-25
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \brief	DesignWare SPI driver header file
- * \ingroup	DEVICE_DW_SPI
- */
-
-#ifndef _DEVICE_DW_SPI_H_
-#define _DEVICE_DW_SPI_H_
-
-#include "device/device_hal/inc/dev_spi.h"
-
-/**
- * if this header file is included,
- * will indicate that this designware spi device
- * is used
- */
-#define DEVICE_USE_DESIGNWARE_SPI
-
-#define DW_SPI_IN_FREE			(0)					/*!< Currently not in spi transfer */
-#define DW_SPI_IN_XFER			(DEV_IN_TX|DEV_IN_RX|DEV_IN_XFER)	/*!< Currently in spi transfer */
-#define DW_SPI_IN_TX			(DEV_IN_TX|DEV_IN_XFER)			/*!< Currently in spi tx */
-#define DW_SPI_IN_RX			(DEV_IN_RX|DEV_IN_XFER)			/*!< Currently in spi rx */
-
-#define DW_SPI_GINT_DISABLED		(0)		/*!< designware interrupt disabled for control iic irq/fiq */
-#define DW_SPI_GINT_ENABLE		(1<<0)		/*!< designware interrupt enabled for control iic irq/fiq */
-
-#define DW_SPI_MASTER_SUPPORTED		(0x1)	/*!< Support Designware SPI Master Mode */
-#define DW_SPI_SLAVE_SUPPORTED		(0x2)	/*!< Support Designware SPI Slave Mode */
-/*!< Support Designware SPI Both Master and Slave Mode */
-#define DW_SPI_BOTH_SUPPORTED		(DW_SPI_MASTER_SUPPORTED|DW_SPI_SLAVE_SUPPORTED)
-
-/**
- * \defgroup	DEVICE_DW_SPI_REGSTRUCT		DesignWare SPI Register Structure
- * \ingroup	DEVICE_DW_SPI
- * \brief	contains definitions of DesignWare SPI register structure.
- * \details	detailed description of DesignWare SPI register information
- * @{
- */
-/**
- * \brief	DesignWare SPI register structure
- * \details	Detailed struct description of DesignWare SPI
- * 	block register information, implementation of dev_spi_info::spi_regs
- */
-typedef volatile struct dw_spi_reg
-{
-	/*!< Control Register */
-	/*!< SPI Control Register 0  (0x0) */
-	uint32_t CTRLR0;
-	/*!< SPI Control Register 1  (0x4) */
-	uint32_t CTRLR1;
-	/*!< Enable Register */
-	/*!< SPI Enable Register  (0x8) */
-	uint32_t SSIENR;
-	/*!< SPI Microwire Control Register  (0xC) */
-	uint32_t MWCR;
-	/*!< SPI Slave Enable Register  (0x10) */
-	uint32_t SER;
-	/*!< SPI Baud Rate Select Register  (0x14) */
-	uint32_t BAUDR;
-	/*!< TX and RX FIFO Control Register */
-	/*!< SPI Transmit FIFO Threshold Level Register  (0x18) */
-	uint32_t TXFTLR;
-	/*!< SPI Receive  FIFO Threshold Level Register  (0x1C) */
-	uint32_t RXFTLR;
-	/*!< SPI Transmit FIFO Level Register  (0x20) */
-	uint32_t TXFLR;
-	/*!< SPI Receive  FIFO Level Register  (0x24) */
-	uint32_t RXFLR;
-	/*!< SPI Status   Register  (0x28) */
-	uint32_t SR;
-	/*!< Interrupt Enable/Disable/Control Registers */
-	/*!< SPI Interrupt Mask Register  (0x2C) */
-	uint32_t IMR;
-	/*!< SPI Interrupt Status Register  (0x30) */
-	uint32_t ISR;
-	/*!< SPI Raw Interrupt Status Register (0x34) */
-	uint32_t RISR;
-	/*!< SPI Transmit FIFO Overflow Interrupt Clear Register  (0x38) */
-	uint32_t TXOICR;
-	/*!< SPI Receive  FIFO Overflow Interrupt Clear Register  (0x3C) */
-	uint32_t RXOICR;
-	/*!< SPI Receive FIFO Underflow Interrupt Clear Register  (0x40) */
-	uint32_t RXUICR;
-	/*!< SPI Multi-Master Interrupt Clear Register  (0x44) */
-	uint32_t MSTICR;
-	/*!< SPI Interrupt Clear Register  (0x48) */
-	uint32_t ICR;
-	/*!< DMA Control Register  (0x4C) */
-	uint32_t DMACR;
-	/*!< DMA Transmit Data Level  (0x50) */
-	uint32_t DMATDLR;
-	/*!< DMA Receive Data Level  (0x54) */
-	uint32_t DMARDLR;
-	/*!< SPI Identification Register  (0x58) */
-	uint32_t IDR;
-	/*!< SPI CoreKit ID Register (Value after Reset : 0x3332322A)  (0x5C) */
-	uint32_t SSI_VER_ID;
-	/*!< Data Register */
-	/*!< SPI DATA Register for both Read and Write  (0x60) */
-	uint32_t DATAREG;
-} DW_SPI_REG, *DW_SPI_REG_PTR;
-/** @} */
-
-/** Designware SPI Message Transfer */
-typedef struct dw_spi_transfer {
-	uint32_t xfer_len;
-	uint32_t tx_idx;
-	uint32_t rx_idx;
-	uint32_t nbytes;
-	DEV_SPI_TRANSFER *tx_xfer;
-	DEV_SPI_TRANSFER *rx_xfer;
-} DW_SPI_TRANSFER, *DW_SPI_TRANSFER_PTR;
-
-/**
- * \brief	DesignWare SPI control structure definition
- * \details	implement of dev_spi_info::dev_spi_info
- */
-typedef struct dw_spi_ctrl {
-	DW_SPI_REG *dw_spi_regs;	/*!< spi register */
-	/* Variables which should be set during object implementation */
-	uint32_t support_modes;		/*!< supported spi modes */
-	uint32_t intno;			/*!< interrupt no */
-	uint32_t dw_apb_bus_freq;	/*!< spi ip apb bus frequency */
-	uint32_t tx_fifo_len;		/*!< transmit fifo length */
-	uint32_t rx_fifo_len;		/*!< receive fifo length */
-	INT_HANDLER dw_spi_int_handler;	/*!< spi interrupt handler */
-	/* Variables which always change during iic operation */
-	uint32_t int_status;		/*!< iic interrupt status */
-	DW_SPI_TRANSFER dw_xfer;	/*!< designware spi transfer */
-} DW_SPI_CTRL, *DW_SPI_CTRL_PTR;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup	DEVICE_DW_SPI_FUNCDLR		DesignWare SPI Function Declaration
- * \ingroup	DEVICE_DW_SPI
- * \brief	contains declarations of designware spi functions.
- * \details	This are only used in \ref dw_spi_obj.c
- * @{
- */
-extern int32_t dw_spi_open (DEV_SPI *spi_obj, uint32_t mode, uint32_t param);
-extern int32_t dw_spi_close (DEV_SPI *spi_obj);
-extern int32_t dw_spi_control (DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param);
-extern int32_t dw_spi_write (DEV_SPI *spi_obj, const void *data, uint32_t len);
-extern int32_t dw_spi_read (DEV_SPI *spi_obj, void *data, uint32_t len);
-extern void dw_spi_isr(DEV_SPI *spi_obj, void *ptr);
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-
-#endif /* _DEVICE_DW_SPI_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h
deleted file mode 100644
index b1a233c699..0000000000
--- a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-06-25
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	DEVICE_DW_SPI
- * \brief	DesignWare SPI driver hardware description related header file
- * \details	detailed hardware related definitions of DesignWare SPI driver
- */
-
-#ifndef _DEVICE_DW_SPI_HAL_H_
-#define _DEVICE_DW_SPI_HAL_H_
-
-#include "device/designware/spi/dw_spi_hal_cfg.h"
-
-/* DW APB SPI bit definitions */
-
-/**
- * \name	DesignWare SPI HAL CTRL0 Macros
- * \brief	DesignWare SPI hal ctrl0 macros,
- * 	include dfs, scph, scppl, tmod, etc
- * @{
- */
-#define DW_SPI_CTRLR0_DFS_MASK			(0xf)
-
-#define DW_SPI_CTRLR0_SC_OFS			(6)
-#define DW_SPI_CTRLR0_SC_MASK			(0xC0)
-#define DW_SPI_CTRLR0_SCPH_HIGH			(0x40)
-#define DW_SPI_CTRLR0_SCPH_LOW			(0)
-#define DW_SPI_CTRLR0_SCPOL_HIGH		(0x80)
-#define DW_SPI_CTRLR0_SCPOL_LOW			(0)
-
-#define DW_SPI_CTRLR0_TMOD_MASK			(0x300)
-#define DW_SPI_TMOD_TRANSMIT_RECEIVE		(0)
-#define DW_SPI_TMOD_TRANSMIT_ONLY		(0x100)
-#define DW_SPI_TMOD_RECEIVE_ONLY		(0x200)
-#define DW_SPI_TMOD_EEPROM_READ_ONLY		(0x300)
-
-#define DW_SPI_CTRLR0_FRF_MOTOROLA		(0x0)
-#define DW_SPI_CTRLR0_FRF_TI			(0x10)
-#define DW_SPI_CTRLR0_FRF_MICROWIRE		(0x20)
-
-#define DW_SPI_CTRLR0_SLV_OE_DISABLE		(1<<10)
-#define DW_SPI_CTRLR0_SLV_OE_ENABLE		(0)
-
-
-/** @} */
-
-/**
- * \name	DesignWare SPI HAL ISR Flags
- * \brief	DesignWare SPI hal Interrupt Status Flags
- * @{
- */
-#define DW_SPI_TX_OVERFLOW_ERROR		(0x2)
-#define DW_SPI_RX_UNDERFLOW_ERROR		(0x4)
-#define DW_SPI_RX_OVERFLOW_ERROR		(0x8)
-
-#define DW_SPI_ISR_RX_FIFO_INT_MASK		(0x10)
-#define DW_SPI_ISR_TX_FIFO_INT_MASK		(0x1)
-#define DW_SPI_ISR_TX_OVERFLOW_INT_MASK		(0x2)
-#define DW_SPI_ISR_RX_UNDERFLOW_INT_MASK	(0x4)
-#define DW_SPI_ISR_RX_OVERFLOW_INT_MASK		(0x8)
-/** @} */
-
-/**
- * \name	DesignWare SPI HAL SR Flags
- * \brief	DesignWare SPI hal Status Flags
- * @{
- */
-#define DW_SPI_SR_DCOL				(0x40)
-#define DW_SPI_SR_TXE				(0x20)
-#define DW_SPI_SR_RFF				(0x10)
-#define DW_SPI_SR_RFNE				(0x8)
-#define DW_SPI_SR_TFE				(0x4)
-#define DW_SPI_SR_TFNF				(0x2)
-#define DW_SPI_SR_BUSY				(0x1)
-/** @} */
-
-/**
- * \name	DesignWare SPI HAL SSI Enable Macros
- * \brief	DesignWare SPI hal ssi enable macros
- * @{
- */
-/* Macros */
-#define DW_SPI_SSI_ENABLE			(1)	/*!< SSI Enable */
-#define DW_SPI_SSI_DISABLE			(0)	/*!< SSI Disable */
-/** @} */
-
-/**
- * \name	DesignWare SPI HAL IMR Macros
- * \brief	DesignWare SPI hal interrupt mask macros
- * @{
- */
-#define DW_SPI_IMR_MSTIM			(0x20)	/*!< Multi-Master Contention Interrupt Mask */
-#define DW_SPI_IMR_RXFIM			(0x10)	/*!< Receive FIFO Full Interrupt Mask */
-#define DW_SPI_IMR_RXOIM			(0x08)	/*!< Receive FIFO Overflow Interrupt Mask */
-#define DW_SPI_IMR_RXUIM			(0x04)	/*!< Receive FIFO Underflow Interrupt Mask */
-#define DW_SPI_IMR_TXOIM			(0x02)	/*!< Transmit FIFO Overflow Interrupt Mask */
-#define DW_SPI_IMR_TXEIM			(0x01)	/*!< Transmit FIFO Empty Interrupt Mask */
-
-#define DW_SPI_IMR_XFER				(DW_SPI_IMR_TXEIM|DW_SPI_IMR_RXFIM|DW_SPI_IMR_TXOIM|DW_SPI_IMR_RXOIM|DW_SPI_IMR_RXUIM)
-/** @} */
-
-#define DW_SPI_SSI_IDLE				(1)
-#define DW_SPI_SPI_TRANSMIT			(1)
-#define DW_SPI_SPI_RECEIVE			(2)
-#define DW_SPI_SSI_MASTER			(1)
-#define DW_SPI_SSI_SLAVE			(0)
-
-
-#endif /* _DEVICE_DW_SPI_HAL_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h
deleted file mode 100644
index d6caf71466..0000000000
--- a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2015-09-09
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	DEVICE_DW_SPI
- * \brief	DesignWare SPI driver hardware description
- * 	related header file configuration file
- * \details	configuration file to enable or disable some function of spi
- */
-
-#ifndef _DEVICE_DW_SPI_HAL_CFG_H_
-#define _DEVICE_DW_SPI_HAL_CFG_H_
-
-#ifndef DW_SPI_CALC_FIFO_LEN_ENABLE
-#define DW_SPI_CALC_FIFO_LEN_ENABLE		(1)	/*!< Defaultly enable calculate fifo length */
-#endif
-
-#ifndef DW_SPI_MAX_FIFO_LENGTH
-#define DW_SPI_MAX_FIFO_LENGTH			(256)	/*!< Max FIFO depth for designware SPI device */
-#endif
-
-#ifndef DW_SPI_MIN_FIFO_LENGTH
-#define DW_SPI_MIN_FIFO_LENGTH			(2)	/*!< Min FIFO depth for designware SPI device */
-#endif
-
-#endif /* _DEVICE_DW_SPI_HAL_CFG_H_ */
-
diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart.c b/bsp/synopsys/embarc/device/designware/uart/dw_uart.c
deleted file mode 100644
index 999ee751e0..0000000000
--- a/bsp/synopsys/embarc/device/designware/uart/dw_uart.c
+++ /dev/null
@@ -1,956 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-20
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_DW_UART	Designware UART Driver
- * \ingroup	DEVICE_DW
- * \brief	Designware UART Driver Implementation
- */
-
-/**
- * \file
- * \ingroup	DEVICE_DW_UART
- * \brief	DesignWare UART driver implementation based on device hal layer definition (\ref dev_uart.h)
- */
-#include <string.h>
-
-#include "inc/embARC_toolchain.h"
-#include "inc/embARC_error.h"
-
-#include "inc/arc/arc_exception.h"
-
-#include "device/designware/uart/dw_uart_hal.h"
-#include "device/designware/uart/dw_uart.h"
-
-
-/**
- * \name	DesignWare UART Driver Macros
- * \brief	DesignWare UART driver macros used in uart driver
- * @{
- */
-/** check expressions used in DesignWare UART driver implementation */
-#define DW_UART_CHECK_EXP(EXPR, ERROR_CODE)		CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
-
-#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
-/** valid check of uart info object */
-#define VALID_CHK_UART_INFO_OBJECT(uartinfo_obj_ptr)		{				\
-			DW_UART_CHECK_EXP((uartinfo_obj_ptr)!=NULL, E_OBJ);			\
-			DW_UART_CHECK_EXP(((uartinfo_obj_ptr)->uart_ctrl)!=NULL, E_OBJ);	\
- 		}
-#endif
-
-/** convert DesignWare baudrate to divisor */
-#define DW_UART_BAUD2DIV(perifreq, baud)		((perifreq) / ((baud)*16))
-
-/**
- * \name	DesignWare UART Interrupt Callback Routine Select Marcos
- * \brief	DesignWare UART interrupt callback routines select macros definitions
- * @{
- */
-#define DW_UART_RDY_SND					(1U)	/*!< ready to send callback */
-#define DW_UART_RDY_RCV					(2U)	/*!< ready to receive callback */
-/** @} */
-
-/** @} */
-
-/**
- * \defgroup	DEVICE_DW_UART_STATIC	DesignWare UART Driver Static Functions
- * \ingroup	DEVICE_DW_UART
- * \brief	Static or inline functions, variables for DesignWare UART handle uart operations,
- * 	only used in this file
- * @{
- */
-const uint8_t dw_uart_databits[] = { \
-	DW_UART_LCR_WORD_LEN5, DW_UART_LCR_WORD_LEN6, \
-	DW_UART_LCR_WORD_LEN7, DW_UART_LCR_WORD_LEN8};
-const uint8_t dw_uart_parity[] = {
-	DW_UART_LCR_PARITY_NONE, DW_UART_LCR_PARITY_ODD,
-	DW_UART_LCR_PARITY_EVEN, DW_UART_LCR_PARITY_MASK,
-	DW_UART_LCR_PARITY_SPACE
-};
-const uint8_t dw_uart_stopbits[] = {
-	DW_UART_LCR_1_STOP_BIT, DW_UART_LCR_1D5_STOP_BIT,
-	DW_UART_LCR_2_STOP_BIT
-};
-
-/** test whether uart is ready to send, 1 ready, 0 not ready */
-Inline int32_t dw_uart_putready(DW_UART_REG *uart_reg_ptr)
-{
-	return ((uart_reg_ptr->USR & DW_UART_USR_TFNF) != 0);
-}
-/** test whether uart is ready to receive, 1 ready, 0 not ready */
-Inline int32_t dw_uart_getready(DW_UART_REG *uart_reg_ptr)
-{
-	return ((uart_reg_ptr->USR & DW_UART_USR_RFNE) != 0);
-}
-/** write char to uart send fifo */
-Inline void dw_uart_putchar(DW_UART_REG *uart_reg_ptr, char chr)
-{
-	uart_reg_ptr->DATA = chr;
-}
-/** read data from uart receive fifo, return data received */
-Inline int32_t dw_uart_getchar(DW_UART_REG *uart_reg_ptr)
-{
-	return (int32_t)uart_reg_ptr->DATA;
-}
-/**
- * \brief	send char by uart when available,
- * 	mostly used in interrupt method, non-blocked function
- * \param[in]	uart_reg_ptr	uart register structure pointer
- * \param[in]	chr		char to be sent
- * \retval	0		send successfully
- * \retval	-1		not ready to send data
- */
-Inline int32_t dw_uart_snd_chr(DW_UART_REG *uart_reg_ptr, char chr)
-{
-	if (dw_uart_putready(uart_reg_ptr)) {
-		dw_uart_putchar(uart_reg_ptr, chr);
-		return 0;
-	}
-	return -1;
-}
-/**
- * \brief	receive one char from uart,
- * 	mostly used in interrupt routine, non-blocked function
- * \param[in]	uart_reg_ptr	uart register structure pointer
- * \return	data received by the uart
- */
-Inline int32_t dw_uart_rcv_chr(DW_UART_REG *uart_reg_ptr)
-{
-	return dw_uart_getchar(uart_reg_ptr);
-}
-/**
- * \brief	send char by uart in poll method, blocked function
- * \param[in]	uart_reg_ptr	uart register structure pointer
- * \param[in]	chr		char to be sent
- */
-Inline void dw_uart_psnd_chr(DW_UART_REG *uart_reg_ptr, char chr)
-{
-	/** wait until uart is ready to send */
-	while (!dw_uart_putready(uart_reg_ptr)); /* blocked */
-	/** send char */
-	dw_uart_putchar(uart_reg_ptr, chr);
-}
-/**
- * \brief	receive one char from uart in poll method, blocked function
- * \param[in]	uart_reg_ptr	uart register structure pointer
- * \return	data received by the uart
- */
-Inline int32_t dw_uart_prcv_chr(DW_UART_REG *uart_reg_ptr)
-{
-	/** wait until uart is ready to receive */
-	while (!dw_uart_getready(uart_reg_ptr)); /* blocked */
-	/** receive data */
-	return dw_uart_getchar(uart_reg_ptr);
-}
-
-/** Get TX FIFO Length */
-Inline uint32_t dw_uart_get_txfifo_len(DW_UART_REG *uart_reg_ptr)
-{
-	uint32_t txfifolen;
-	uint32_t uart_cpr;
-
-	uart_cpr = uart_reg_ptr->CPR;
-	if (uart_cpr & DW_UART_CPR_FIFO_STAT) {
-		txfifolen = ((uart_cpr & DW_UART_CPR_FIFO_MODE) >> DW_UART_CPR_FIFO_MODE_OFS) << 4;
-	} else {
-		txfifolen = 0;
-	}
-
-	return txfifolen;
-}
-
-/** Get RX FIFO Length */
-Inline uint32_t dw_uart_get_rxfifo_len(DW_UART_REG *uart_reg_ptr)
-{
-	uint32_t rxfifolen;
-	uint32_t uart_cpr;
-
-	uart_cpr = uart_reg_ptr->CPR;
-	if (uart_cpr & DW_UART_CPR_FIFO_STAT) {
-		rxfifolen = ((uart_cpr & DW_UART_CPR_FIFO_MODE) >> DW_UART_CPR_FIFO_MODE_OFS) << 4;
-	} else {
-		rxfifolen = 0;
-	}
-
-	return rxfifolen;
-}
-
-/**
- * \brief	set designware uart DPS value
- * \param	uart_reg_ptr	uart register structure
- * \param	dps		data bits/parity bit/stop bits parameter
- * \retval	0	Set ok
- * \retval	!0	Set failed
- */
-static int32_t dw_uart_set_dps(DW_UART_REG *uart_reg_ptr, UART_DPS_FORMAT *dps)
-{
-	uint32_t dps_value = 0;
-
-	if (dps == NULL) return -1;
-	/* data bits check */
-	if ((dps->databits < 5) || (dps->databits > 8)) return -1;
-	/* stop bits check */
-	if (dps->stopbits > UART_STPBITS_TWO) return -1;
-	/* parity bit type check */
-	if (dps->parity > UART_PARITY_SPACE) return -1;
-
-	dps_value |= (uint32_t)dw_uart_databits[dps->databits-5];
-	dps_value |= (uint32_t)dw_uart_stopbits[dps->stopbits];
-	dps_value |= (uint32_t)dw_uart_parity[dps->parity];
-
-	/* clear dps bits */
-	uart_reg_ptr->LCR &= (~DW_UART_LCR_DPS_MASK);
-	/* set dps bits */
-	uart_reg_ptr->LCR |= dps_value;
-
-	return 0;
-}
-
-/**
- * \brief	set designware uart baudrate
- * \param	uart_reg_ptr	uart register structure
- * \param	baud_divisor	uart baudrate divisor
- */
-static void dw_uart_set_baud(DW_UART_REG *uart_reg_ptr, uint32_t baud_divisor)
-{
-	/* enable uart baudrate update */
-	uart_reg_ptr->LCR |= DW_UART_LCR_DLAB;
-	/**
-	 * setting uart baudrate registers
-	 */
-	uart_reg_ptr->DATA = baud_divisor & 0xff;	/*!< DLL */
-	uart_reg_ptr->IER = (baud_divisor>>8) & 0xff;	/*!< DLH */
-	/** disable DLAB */
-	uart_reg_ptr->LCR &= ~(DW_UART_LCR_DLAB);
-}
-
-/**
- * \brief	Do uart software reset
- * \param	uart_reg_ptr	uart register structure
- */
-Inline void dw_uart_software_reset(DW_UART_REG *uart_reg_ptr)
-{
-	uart_reg_ptr->SRR = DW_UART_SRR_UR|DW_UART_SRR_RFR|DW_UART_SRR_XFR;
-	while(uart_reg_ptr->USR & DW_UART_USR_BUSY); /* wait until software reset completed */
-}
-
-/**
- * \brief	set designware uart baudrate
- * \param	uart_reg_ptr	uart register structure
- * \param	hwfc		uart hardware flow control type
- * \note	Need to set corresponding pin functions
- */
-static void dw_uart_set_hwfc(DW_UART_REG *uart_reg_ptr, UART_HW_FLOW_CONTROL hwfc)
-{
-	if (hwfc == UART_FC_NONE) {
-		uart_reg_ptr->MCR &= ~(DW_UART_MCR_AFCE|DW_UART_MCR_RTS);
-	}
-	if ((hwfc == UART_FC_RTS) || (hwfc == UART_FC_BOTH)) {
-		uart_reg_ptr->MCR |= (DW_UART_MCR_AFCE|DW_UART_MCR_RTS);
-	}
-	if ((hwfc == UART_FC_CTS) || (hwfc == UART_FC_BOTH)) {
-		uart_reg_ptr->MCR |= (DW_UART_MCR_AFCE);
-	}
-}
-
-Inline void dw_uart_set_break(DW_UART_REG *uart_reg_ptr)
-{
-	uart_reg_ptr->LCR |= DW_UART_LCR_BREAK;
-}
-
-Inline void dw_uart_clr_break(DW_UART_REG *uart_reg_ptr)
-{
-	uart_reg_ptr->LCR &= ~DW_UART_LCR_BREAK;
-}
-
-/**
- * \brief	init designware uart with selected baud
- * \param[in]	uart_reg_ptr	uart register structure pointer
- * \param[in]	baud_divisor	baudrate divisor
- */
-static void dw_uart_init(DW_UART_REG *uart_reg_ptr, uint32_t baud_divisor, UART_DPS_FORMAT *dps, UART_HW_FLOW_CONTROL hwfc)
-{
-	dw_uart_software_reset(uart_reg_ptr);
-
-	dw_uart_set_hwfc(uart_reg_ptr, hwfc);
-	dw_uart_set_dps(uart_reg_ptr, dps);
-	dw_uart_set_baud(uart_reg_ptr, baud_divisor);
-
-	uart_reg_ptr->IIR = 0x1;	/** enable uart fifo (FCR IIR is the same) */
-	uart_reg_ptr->IER = 0x0;	/** disable all uart interrupt */
-}
-
-/**
- * \brief	set designware uart baudrate
- * \param	uart_info_ptr	uart information structure pointer
- */
-static void dw_uart_flush_output(DEV_UART_INFO *uart_info_ptr)
-{
-	uint32_t i;
-	char *p_charbuf;
-
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	if (uart_info_ptr->tx_buf.buf != NULL) {
-		p_charbuf = (char *)(uart_info_ptr->tx_buf.buf);
-		for (i = uart_info_ptr->tx_buf.ofs; i < uart_info_ptr->tx_buf.len; i ++) {
-			dw_uart_psnd_chr(uart_reg_ptr, p_charbuf[i]);
-		}
-		/* clear transmit buffer */
-		uart_info_ptr->tx_buf.buf = NULL;
-		uart_info_ptr->tx_buf.len = 0;
-		uart_info_ptr->tx_buf.ofs = 0;
-	}
-	/* wait until transmit fifo is empty */
-	while ((uart_reg_ptr->USR & DW_UART_USR_TFE) == 0);
-	while (uart_reg_ptr->USR & DW_UART_USR_BUSY);
-}
-
-/**
- * \brief	disable designware uart send or receive interrupt
- * \param[in]	DEV_UART_INFO 	*uart_info_ptr
- * \param[in]	cbrtn		control code of callback routine of send or receive
- */
-static void dw_uart_dis_cbr(DEV_UART_INFO *uart_info_ptr, uint32_t cbrtn)
-{
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	switch (cbrtn) {
-		case DW_UART_RDY_SND:
-			uart_reg_ptr->IER &= ~DW_UART_IER_XMIT_EMPTY;
-			uart_ctrl_ptr->int_status &= ~DW_UART_TXINT_ENABLE;
-			break;
-		case DW_UART_RDY_RCV:
-			uart_reg_ptr->IER &= ~DW_UART_IER_DATA_AVAIL;
-			uart_ctrl_ptr->int_status &= ~DW_UART_RXINT_ENABLE;
-			break;
-		default:
-			break;
-	}
-	if (uart_ctrl_ptr->int_status & DW_UART_GINT_ENABLE) {
-		if ((uart_ctrl_ptr->int_status & (DW_UART_RXINT_ENABLE|DW_UART_TXINT_ENABLE)) == 0) {
-			int_disable(uart_ctrl_ptr->intno);
-			uart_ctrl_ptr->int_status &= ~DW_UART_GINT_ENABLE;
-		}
-	}
-}
-
-/**
- * \brief	enable DesignWare UART send or receive interrupt
- * \param[in]	DEV_UART_INFO 	*uart_info_ptr
- * \param[in]	cbrtn		control code of callback routine of send or receive
- */
-static void dw_uart_ena_cbr(DEV_UART_INFO *uart_info_ptr, uint32_t cbrtn)
-{
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	switch (cbrtn) {
-		case DW_UART_RDY_SND:
-			uart_ctrl_ptr->int_status |= DW_UART_TXINT_ENABLE;
-			uart_reg_ptr->IER |= DW_UART_IER_XMIT_EMPTY;
-			break;
-		case DW_UART_RDY_RCV:
-			uart_ctrl_ptr->int_status |= DW_UART_RXINT_ENABLE;
-			uart_reg_ptr->IER |= DW_UART_IER_DATA_AVAIL;
-			break;
-		default:
-			break;
-	}
-	if ((uart_ctrl_ptr->int_status & DW_UART_GINT_ENABLE) == 0) {
-		if (uart_ctrl_ptr->int_status & (DW_UART_RXINT_ENABLE|DW_UART_TXINT_ENABLE)) {
-			uart_ctrl_ptr->int_status |= DW_UART_GINT_ENABLE;
-			int_enable(uart_ctrl_ptr->intno);
-		}
-	}
-}
-
-/**
- * \brief	enable designware uart interrupt
- * \param	uart_info_ptr	uart information structure pointer
- */
-static void dw_uart_enable_interrupt(DEV_UART_INFO *uart_info_ptr)
-{
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-
-	int_handler_install(uart_ctrl_ptr->intno, uart_ctrl_ptr->dw_uart_int_handler);
-	uart_ctrl_ptr->int_status |= DW_UART_GINT_ENABLE;
-	int_enable(uart_ctrl_ptr->intno);	/** enable uart interrupt */
-}
-/**
- * \brief	disable designware uart interrupt
- * \param	uart_info_ptr	uart information structure pointer
- */
-static void dw_uart_disable_interrupt(DEV_UART_INFO *uart_info_ptr)
-{
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-
-	/** disable uart send&receive interrupt after disable uart interrupt */
-	dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND);
-	dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV);
-	/* disable uart interrupt */
-	int_disable(uart_ctrl_ptr->intno);
-	uart_ctrl_ptr->int_status &= ~(DW_UART_GINT_ENABLE|DW_UART_TXINT_ENABLE|DW_UART_RXINT_ENABLE);
-}
-
-/** enable designware uart */
-static void dw_uart_enable_device(DEV_UART_INFO *uart_info_ptr)
-{
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	if ((uart_info_ptr->status & DEV_ENABLED) == 0) {
-		dw_uart_set_baud(uart_reg_ptr, uart_info_ptr->baudrate);
-		uart_info_ptr->status |= DEV_ENABLED;
-	}
-}
-
-/** disable designware uart */
-static void dw_uart_disable_device(DEV_UART_INFO *uart_info_ptr)
-{
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	if ((uart_info_ptr->status & DEV_ENABLED) == DEV_ENABLED) {
-		dw_uart_set_baud(uart_reg_ptr, 0);
-		uart_info_ptr->status &= ~DEV_ENABLED;
-	}
-}
-
-/** abort current interrupt transmit transfer */
-static void dw_uart_abort_tx(DEV_UART *uart_obj)
-{
-	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-
-	if (uart_ctrl_ptr->int_status & DW_UART_TXINT_ENABLE) {
-		dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND);
-		uart_info_ptr->status |= DEV_IN_TX_ABRT;
-		if (uart_info_ptr->uart_cbs.tx_cb != NULL) {
-			uart_info_ptr->uart_cbs.tx_cb(uart_obj);
-		}
-		uart_info_ptr->status &= ~(DEV_IN_TX_ABRT);
-	}
-}
-
-/** abort current interrupt receive transfer */
-static void dw_uart_abort_rx(DEV_UART *uart_obj)
-{
-	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-
-	if (uart_ctrl_ptr->int_status & DW_UART_RXINT_ENABLE) {
-		dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV);
-		uart_info_ptr->status |= DEV_IN_RX_ABRT;
-		if (uart_info_ptr->uart_cbs.rx_cb != NULL) {
-			uart_info_ptr->uart_cbs.rx_cb(uart_obj);
-		}
-		uart_info_ptr->status &= ~(DEV_IN_RX_ABRT);
-	}
-}
-
-/** Get available transmit fifo count */
-static int32_t dw_uart_get_txavail(DW_UART_CTRL *uart_ctrl_ptr)
-{
-	int32_t tx_avail = 0;
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG *)(uart_ctrl_ptr->dw_uart_regbase);
-
-	if (uart_ctrl_ptr->tx_fifo_len <= 1) {
-		if (dw_uart_putready(uart_reg_ptr) == 1) {
-			tx_avail = 1;
-		} else {
-			tx_avail = 0;
-		}
-	} else {
-		tx_avail = uart_ctrl_ptr->tx_fifo_len - uart_reg_ptr->TFL;
-	}
-	return tx_avail;
-}
-
-/** Get available receive fifo count */
-static int32_t dw_uart_get_rxavail(DW_UART_CTRL *uart_ctrl_ptr)
-{
-	int32_t rx_avail = 0;
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG *)(uart_ctrl_ptr->dw_uart_regbase);
-
-	if (uart_ctrl_ptr->rx_fifo_len <= 1) {
-		if (dw_uart_getready(uart_reg_ptr) == 1) {
-			rx_avail = 1;
-		} else {
-			rx_avail = 0;
-		}
-	} else {
-		rx_avail = uart_reg_ptr->RFL;
-	}
-	return rx_avail;
-}
-
-
-/** @} end of group DEVICE_DW_UART_STATIC */
-
-/**
- * \brief	open a designware uart device
- * \param[in]	uart_obj	uart object structure pointer
- * \param[in]	baud		baudrate to initialized
- * \retval	E_OK	Open successfully without any issues
- * \retval	E_OPNED	If device was opened before with different baudrate, then return E_OPNED
- * \retval	E_OBJ	Device object is not valid
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_NOSPT	Open settings are not supported
- */
-int32_t dw_uart_open (DEV_UART *uart_obj, uint32_t baud)
-{
-	int32_t ercd = E_OK;
-	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
-	DW_UART_CHECK_EXP(baud>0, E_PAR);
-	/* END OF ERROR CHECK */
-
-	uart_info_ptr->opn_cnt ++;
-	if (uart_info_ptr->opn_cnt > 1) { /* opened before */
-		if (baud == uart_info_ptr->baudrate) { /* baudrate is the same */
-			return E_OK;
-		} else { /* open with different baudrate */
-			return E_OPNED;
-		}
-	}
-
-	int32_t baud_divisor = 0;
-
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	/* Get FIFO Length */
-	uart_ctrl_ptr->tx_fifo_len = dw_uart_get_txfifo_len(uart_reg_ptr);
-	uart_ctrl_ptr->rx_fifo_len = dw_uart_get_rxfifo_len(uart_reg_ptr);
-
-	/** init uart */
-	uart_info_ptr->baudrate = baud;
-	baud_divisor = DW_UART_BAUD2DIV(uart_ctrl_ptr->dw_apb_bus_freq, baud);
-	uart_info_ptr->dps_format = dps_format_default;
-	uart_info_ptr->hwfc = hwfc_default;
-	dw_uart_init(uart_reg_ptr, baud_divisor, &(uart_info_ptr->dps_format), uart_info_ptr->hwfc);
-
-	uart_info_ptr->status = DEV_ENABLED;
-	uart_info_ptr->extra = NULL;
-
-	/**
-	 * uart interrupt related init
-	 */
-	dw_uart_disable_interrupt(uart_info_ptr);
-	/** install uart interrupt into system */
-	int_handler_install(uart_ctrl_ptr->intno, uart_ctrl_ptr->dw_uart_int_handler);
-
-	memset(&(uart_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER));
-	memset(&(uart_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER));
-	memset(&(uart_info_ptr->uart_cbs), 0, sizeof(DEV_UART_CBS));
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	close a DesignWare UART device
- * \param[in]	uart_obj	uart object structure pointer
- * \retval	E_OK	Open successfully without any issues
- * \retval	E_OPNED	Device is still opened, the device opn_cnt decreased by 1
- * \retval	E_OBJ	Device object is not valid
- */
-int32_t dw_uart_close (DEV_UART *uart_obj)
-{
-	int32_t ercd = E_OK;
-	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
-	DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_OK);
-	/* END OF ERROR CHECK */
-
-	uart_info_ptr->opn_cnt --;
-	if (uart_info_ptr->opn_cnt == 0) {
-		dw_uart_disable_interrupt(uart_info_ptr);
-		dw_uart_abort_tx(uart_obj);
-		dw_uart_abort_rx(uart_obj);
-		dw_uart_flush_output(uart_info_ptr);
-		memset(&(uart_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER));
-		memset(&(uart_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER));
-		memset(&(uart_info_ptr->uart_cbs), 0, sizeof(DEV_UART_CBS));
-		dw_uart_disable_device(uart_info_ptr);
-		uart_info_ptr->status = 0;
-		uart_info_ptr->extra = NULL;
-	} else {
-		ercd = E_OPNED;
-	}
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	control uart by ctrl command
- * \param[in]	uart_obj	uart object structure pointer
- * \param[in]	ctrl_cmd	control command code to do specific uart work
- * \param[in,out]	param	parameters used to control uart or return something
- * \retval	E_OK	Control device successfully
- * \retval	E_CLSED	Device is not opened
- * \retval	E_DIS	Device is disabled
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Control device failed, due to hardware issues
- * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
- * \retval	E_NOSPT	Control command is not supported or not valid
- */
-int32_t dw_uart_control (DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param)
-{
-	int32_t ercd = E_OK;
-	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
-	DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED);
-	/* END OF ERROR CHECK */
-
-	uint32_t val32; /** to receive unsigned int value */
-	int32_t baud_divisor = 0;
-	DEV_BUFFER *devbuf;
-	UART_DPS_FORMAT *dps_ptr;
-	UART_HW_FLOW_CONTROL hwfc_local;
-
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	/* check whether current device is disabled */
-	if ((uart_info_ptr->status & DEV_ENABLED) == 0) {
-		/** When device is disabled,
-		 * only UART_CMD_ENA_DEV, UART_CMD_DIS_DEV, UART_CMD_GET_STATUS
-		 * are available, other commands will return E_SYS
-		 */
-		if ((ctrl_cmd != UART_CMD_ENA_DEV) && \
-			(ctrl_cmd != UART_CMD_DIS_DEV) && \
-			(ctrl_cmd != UART_CMD_GET_STATUS) ) {
-			return E_SYS;
-		}
-	}
-
-	switch (ctrl_cmd) {
-		case UART_CMD_SET_BAUD:
-			val32 = (uint32_t)param;
-			DW_UART_CHECK_EXP(val32>0, E_PAR);
-			if (val32 != uart_info_ptr->baudrate) {
-				baud_divisor = DW_UART_BAUD2DIV(uart_ctrl_ptr->dw_apb_bus_freq, val32);
-				dw_uart_set_baud(uart_reg_ptr, baud_divisor);
-				uart_info_ptr->baudrate = val32;
-			}
-			break;
-		case UART_CMD_GET_STATUS:
-			DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = uart_info_ptr->status;
-			break;
-		case UART_CMD_ENA_DEV:
-			dw_uart_enable_device(uart_info_ptr);
-			break;
-		case UART_CMD_DIS_DEV:
-			dw_uart_disable_device(uart_info_ptr);
-			break;
-		case UART_CMD_FLUSH_OUTPUT:
-			dw_uart_flush_output(uart_info_ptr);
-			break;
-		case UART_CMD_GET_RXAVAIL:
-			DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = dw_uart_get_rxavail(uart_ctrl_ptr);
-			break;
-		case UART_CMD_GET_TXAVAIL:
-			DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
-			*((int32_t *)param) = dw_uart_get_txavail(uart_ctrl_ptr);
-			break;
-		case UART_CMD_BREAK_SET:
-			dw_uart_set_break(uart_reg_ptr);
-			break;
-		case UART_CMD_BREAK_CLR:
-			dw_uart_clr_break(uart_reg_ptr);
-			break;
-		case UART_CMD_SET_DPS_FORMAT:
-			DW_UART_CHECK_EXP(param!=NULL, E_PAR);
-			dps_ptr = (UART_DPS_FORMAT *)param;
-			if (dw_uart_set_dps(uart_reg_ptr, dps_ptr) == 0) {
-				uart_info_ptr->dps_format = *dps_ptr;
-			} else {
-				ercd = E_PAR;
-			}
-			break;
-		case UART_CMD_SET_HWFC:
-			hwfc_local = (UART_HW_FLOW_CONTROL)param;
-			DW_UART_CHECK_EXP(((hwfc_local>=UART_FC_NONE) && (hwfc_local<=UART_FC_BOTH)), E_PAR);
-			dw_uart_set_hwfc(uart_reg_ptr, hwfc_local);
-			uart_info_ptr->hwfc = hwfc_local;
-			break;
-		case UART_CMD_SET_TXCB:
-			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			uart_info_ptr->uart_cbs.tx_cb = param;
-			break;
-		case UART_CMD_SET_RXCB:
-			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			uart_info_ptr->uart_cbs.rx_cb = param;
-			break;
-		case UART_CMD_SET_ERRCB:
-			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			uart_info_ptr->uart_cbs.err_cb = param;
-			break;
-		case UART_CMD_ABORT_TX:
-			dw_uart_abort_tx(uart_obj);
-			break;
-		case UART_CMD_ABORT_RX:
-			dw_uart_abort_rx(uart_obj);
-			break;
-		case UART_CMD_SET_TXINT:
-			val32 = (uint32_t)param;
-			if (val32 == 0) {
-				dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND);
-			} else {
-				dw_uart_ena_cbr(uart_info_ptr, DW_UART_RDY_SND);
-			}
-			break;
-		case UART_CMD_SET_RXINT:
-			val32 = (uint32_t)param;
-			if (val32 == 0) {
-				dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV);
-			} else {
-				dw_uart_ena_cbr(uart_info_ptr, DW_UART_RDY_RCV);
-			}
-			break;
-		case UART_CMD_SET_TXINT_BUF:
-			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			if (param != NULL) {
-				devbuf = (DEV_BUFFER *)param;
-				uart_info_ptr->tx_buf = *devbuf;
-				uart_info_ptr->tx_buf.ofs = 0;
-			} else {
-				uart_info_ptr->tx_buf.buf = NULL;
-				uart_info_ptr->tx_buf.len = 0;
-				uart_info_ptr->tx_buf.ofs = 0;
-			}
-			break;
-		case UART_CMD_SET_RXINT_BUF:
-			DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR);
-			if (param != NULL) {
-				devbuf = (DEV_BUFFER *)param;
-				uart_info_ptr->rx_buf = *devbuf;
-				uart_info_ptr->rx_buf.ofs = 0;
-			} else {
-				uart_info_ptr->rx_buf.buf = NULL;
-				uart_info_ptr->rx_buf.len = 0;
-				uart_info_ptr->rx_buf.ofs = 0;
-			}
-			break;
-		default:
-			ercd = E_NOSPT;
-			break;
-	}
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	send data through DesignWare UART
- * \param[in]	uart_obj	uart object structure pointer
- * \param[in]	data		data that need to send (data must be char type)
- * \param[in]	len		data length need to send
- * \retval	>0	Byte count that was successfully sent for poll method
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Can't write data to hardware due to hardware issues
- */
-int32_t dw_uart_write (DEV_UART *uart_obj, const void *data, uint32_t len)
-{
-	int32_t ercd = E_OK;
-	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
-	DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED);
-	DW_UART_CHECK_EXP(uart_info_ptr->status & DEV_ENABLED, E_SYS);
-	DW_UART_CHECK_EXP(data!=NULL, E_PAR);
-	DW_UART_CHECK_EXP(len>0, E_PAR);
-	/* END OF ERROR CHECK */
-
-	int32_t i = 0;
-	const char *p_charbuf = (const char *)data;
-
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	while (i < len) {
-		dw_uart_psnd_chr(uart_reg_ptr, p_charbuf[i++]);
-	}
-	ercd = i;
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	read data through DesignWare UART
- * \param[in]	uart_obj	uart object structure pointer
- * \param[out]	data		data that need to read (data must be char type)
- * \param[in]	len		data count need to read
- * \retval	>0	Byte count that was successfully sent for poll method
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
- */
-int32_t dw_uart_read (DEV_UART *uart_obj, void *data, uint32_t len)
-{
-	int32_t ercd = E_OK;
-	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
-	DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED);
-	DW_UART_CHECK_EXP(uart_info_ptr->status & DEV_ENABLED, E_SYS);
-	DW_UART_CHECK_EXP(data!=NULL, E_PAR);
-	DW_UART_CHECK_EXP(len>0, E_PAR);
-	/* END OF ERROR CHECK */
-
-	int32_t i = 0;
-	char *p_charbuf = (char *)data;
-
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	while (i < len) {
-		p_charbuf[i++] = dw_uart_prcv_chr(uart_reg_ptr);
-	}
-	ercd = i;
-
-error_exit:
-	return ercd;
-}
-
-/**
- * \brief	DesignWare UART interrupt processing routine
- * \param[in]	uart_obj	uart object structure pointer
- * \param[in]	ptr		extra information
- */
-void dw_uart_isr (DEV_UART *uart_obj, void *ptr)
-{
-	int32_t ercd = E_OK;
-	DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info);
-
-	/* START ERROR CHECK */
-	VALID_CHK_UART_INFO_OBJECT(uart_info_ptr);
-	/* END OF ERROR CHECK */
-
-	uint32_t uart_int_status; /** uart interrupt status */
-	volatile uint32_t temp; /** read error status to clear interrupt */
-	DEV_BUFFER *buf_ptr;
-	char *p_charbuf;
-
-	DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl);
-	DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase);
-
-	/** get uart interrupt status */
-	uart_int_status = (uart_reg_ptr->IIR) & DW_UART_IIR_INT_ID_MASK;
-
-	switch (uart_int_status) {
-		case DW_UART_IIR_MDM_STATUS:
-			temp = (volatile uint32_t)(uart_reg_ptr->MSR);
-			break;
-		case DW_UART_IIR_LINE_STATUS:
-			if (uart_info_ptr->uart_cbs.err_cb) {
-				uart_info_ptr->uart_cbs.err_cb(uart_info_ptr);
-			}
-			temp = (volatile uint32_t)(uart_reg_ptr->LSR);
-			break;
-		case DW_UART_IIR_XMIT_EMPTY:
-			buf_ptr = &(uart_info_ptr->tx_buf);
-			p_charbuf = (char *)buf_ptr->buf;
-			if (p_charbuf != NULL) {
-				while (dw_uart_putready(uart_reg_ptr)) {
-					dw_uart_putchar(uart_reg_ptr, p_charbuf[buf_ptr->ofs]);
-					buf_ptr->ofs ++;
-					if (buf_ptr->ofs >= buf_ptr->len) {
-						dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND);
-						if (uart_info_ptr->uart_cbs.tx_cb) {
-							uart_info_ptr->uart_cbs.tx_cb(uart_obj);
-						}
-						/* clear the send buffer pointer */
-						memset(buf_ptr, 0, sizeof(DEV_BUFFER));
-						break;
-					}
-				}
-			} else {
-				if (uart_info_ptr->uart_cbs.tx_cb) {
-					uart_info_ptr->uart_cbs.tx_cb(uart_obj);
-				}
-			}
-			break;
-		case DW_UART_IIR_RX_TIMEOUT:
-			temp = dw_uart_getchar(uart_reg_ptr);
-			break;
-		case DW_UART_IIR_DATA_AVAIL:
-			buf_ptr = &(uart_info_ptr->rx_buf);
-			p_charbuf = (char *)buf_ptr->buf;
-			if (p_charbuf != NULL) {
-				while (dw_uart_getready(uart_reg_ptr)) {
-					p_charbuf[buf_ptr->ofs] = (char)dw_uart_getchar(uart_reg_ptr);
-					buf_ptr->ofs ++;
-					if (buf_ptr->ofs >= buf_ptr->len) {
-						dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV);
-						if (uart_info_ptr->uart_cbs.rx_cb) {
-							uart_info_ptr->uart_cbs.rx_cb(uart_obj);
-						}
-						/* clear the send buffer pointer */
-						memset(buf_ptr, 0, sizeof(DEV_BUFFER));
-						break;
-					}
-				}
-			} else {
-				if (uart_info_ptr->uart_cbs.rx_cb) {
-					uart_info_ptr->uart_cbs.rx_cb(uart_obj);
-				}
-			}
-			break;
-		default:
-			temp = (volatile uint32_t)(uart_reg_ptr->USR);
-			break;
-	}
-
-error_exit:
-	return;
-}
diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart.h b/bsp/synopsys/embarc/device/designware/uart/dw_uart.h
deleted file mode 100644
index 366c4fccc2..0000000000
--- a/bsp/synopsys/embarc/device/designware/uart/dw_uart.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-20
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	DEVICE_DW_UART
- * \brief	DesignWare UART driver header file
- * \details     detailed definitions of designware uart driver
- */
-
-#ifndef _DW_UART_H_
-#define _DW_UART_H_
-
-#include "device/device_hal/inc/dev_uart.h"
-
-#include "inc/arc/arc_exception.h"
-
-/**
- * if this header file is included,
- * will indicate that this designware uart device
- * is used
- */
-#define DEVICE_USE_DESIGNWARE_UART
-
-/**
- * \name	DesignWare UART Register Structure
- * \brief	contains definitions of DesignWare UART register structure.
- * @{
- */
-/**
- * \brief	DesignWare UART register structure
- * \details	Detailed struct description of DesignWare UART
- * 	block register information, implementation of dev_uart_info::uart_regs
- */
-typedef volatile struct dw_uart_reg {
-	uint32_t DATA;		/*!< data in/out and DLL */
-	uint32_t IER;		/*!< Interrupt enable register and DLH */
-	uint32_t IIR;		/*!< Interrupt Id register and FCR */
-	uint32_t LCR;		/*!< Line control Register */
-	uint32_t MCR;		/*!< Modem control register */
-	uint32_t LSR;		/*!< Line Status Register */
-	uint32_t MSR;		/*!< Modem status Register */
-	uint32_t SCRATCHPAD;	/*!< Uart scratch pad register */
-	uint32_t LPDLL;		/*!< Low Power Divisor Latch (Low) Reg */
-	uint32_t LPDLH;		/*!< Low Power Divisor Latch (High) Reg */
-	uint32_t RES1[2];	/*!< Reserved */
-	uint32_t SHR[16];	/*!< Shadow data register(SRBR and STHR) */
-	uint32_t FAR;		/*!< FIFO Access register */
-	uint32_t TFR;		/*!< Transmit FIFO Read */
-	uint32_t RFW;		/*!< Receive FIFO write */
-	uint32_t USR;		/*!< UART status register */
-	uint32_t TFL;		/*!< Transmit FIFO level */
-	uint32_t RFL;		/*!< Receive FIFO level */
-	uint32_t SRR;		/*!< Software reset register */
-	uint32_t SRTS;		/*!< Shadow request to send */
-	uint32_t SBCR;		/*!< Shadow break control */
-	uint32_t SDMAM;		/*!< Shadow DMA mode */
-	uint32_t SFE;		/*!< Shadow FIFO enable */
-	uint32_t SRT;		/*!< Shadow RCVR Trigger */
-	uint32_t STET;		/*!< Shadow TX empty register */
-	uint32_t HTX;		/*!< Halt TX */
-	uint32_t DMASA;		/*!< DMA Software ACK */
-	uint32_t RES2[18];	/*!< Reserved */
-	uint32_t CPR;		/*!< Camponent parameter register */
-	uint32_t UCV;		/*!< UART Component Version */
-	uint32_t CTR;		/*!< Component typw register */
-} DW_UART_REG, *DW_UART_REG_PTR;
-/** @} */
-
-#define DW_UART_GINT_DISABLED	(0)		/*!< designware interrupt disabled for control uart irq/fiq */
-#define DW_UART_GINT_ENABLE	(1<<0)		/*!< designware interrupt enabled for control uart irq/fiq */
-#define DW_UART_TXINT_ENABLE	(1<<1)		/*!< designware interrupt enabled for control transmit process */
-#define DW_UART_RXINT_ENABLE	(1<<2)		/*!< designware interrupt enabled for control transmit process */
-
-/**
- * \brief	DesignWare UART control structure definition
- * \details	implement of dev_uart_info::uart_ctrl
- */
-typedef struct dw_uart_ctrl {
-	uint32_t dw_uart_regbase;		/*!< uart ip register base */
-	uint32_t dw_apb_bus_freq;		/*!< uart ip apb bus frequency */
-	uint32_t intno;				/*!< uart interrupt vector number */
-	INT_HANDLER dw_uart_int_handler;	/*!< uart interrupt handler */
-	uint32_t tx_fifo_len;			/*!< transmit fifo length, set by user in object implementation */
-	uint32_t rx_fifo_len;			/*!< receive fifo length, set by user in object implementation */
-	uint32_t int_status;			/*!< interrupt status for designware uart */
-} DW_UART_CTRL, *DW_UART_CTRL_PTR;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name	DesignWare UART Function Declaration
- * \brief	contains declarations of designware uart functions.
- * \details	This are only used in uart object implementation source file
- * @{
- */
-extern int32_t dw_uart_open (DEV_UART *uart_obj, uint32_t baud);
-extern int32_t dw_uart_close (DEV_UART *uart_obj);
-extern int32_t dw_uart_control (DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param);
-extern int32_t dw_uart_write (DEV_UART *uart_obj, const void *data, uint32_t len);
-extern int32_t dw_uart_read (DEV_UART *uart_obj, void *data, uint32_t len);
-extern void dw_uart_isr(DEV_UART *uart_obj, void *ptr);
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DW_UART_H_ */
diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h b/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h
deleted file mode 100644
index 367894df99..0000000000
--- a/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-20
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	DEVICE_DW_IIC
- * \brief	DesignWare UART driver hardware description related header file
- * \details	detailed hardware related definitions of DesignWare UART driver
- */
-
-#ifndef _DEVICE_DW_UART_HAL_H_
-#define _DEVICE_DW_UART_HAL_H_
-
-/* DW APB UART bit definitions */
-
-/**
- * \name	DesignWare UART HAL IER Marcos
- * \brief	DesignWare UART hal IER related macros
- * @{
- */
-/* IER */
-#define DW_UART_IER_DATA_AVAIL			(0x01)
-#define DW_UART_IER_XMIT_EMPTY			(0x02)
-#define DW_UART_IER_LINE_STATUS			(0x04)
-#define DW_UART_IER_MDM_STATUS			(0x08)
-#define DW_UART_IER_PTIME			(0x80)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL IIR Marcos
- * \brief	DesignWare UART hal IIR related macros
- * @{
- */
-/* IIR */
-/* IIR READ */
-#define DW_UART_IIR_IP				(0x01)
-#define DW_UART_IIR_MASK			(0x0E)
-#define DW_UART_IIR_READ_FIFO_ENABLE		(0xC0)
-
-/* Possible interrupt IIR_MASK values */
-#define DW_UART_IIR_MDM_STATUS			(0x00)
-#define DW_UART_IIR_XMIT_EMPTY			(0x02)
-#define DW_UART_IIR_DATA_AVAIL			(0x04)
-#define DW_UART_IIR_LINE_STATUS			(0x06)
-#define DW_UART_IIR_RX_TIMEOUT			(0x0C)
-#define DW_UART_IIR_INT_ID_MASK			(0x0f)
-
-/* IIR WRITE */
-#define DW_UART_IIR_FIFO_ENABLE			(0x01)
-#define DW_UART_IIR_RCVR_FIFO_RESET		(0x02)
-#define DW_UART_IIR_XMIT_FIFO_RESET		(0x04)
-#define DW_UART_IIR_DMA_MODE_SELECT		(0x08)
-#define DW_UART_IIR_RCV_TRIGGER_MASK		(0xC0)
-
-/* Values for IIR receive trigger */
-#define DW_UART_IIR_TRIGGER_LEVEL_1_CHAR	(0x00)
-#define DW_UART_IIR_TRIGGER_LEVEL_1_4_FULL	(0x40)
-#define DW_UART_IIR_TRIGGER_LEVEL_1_2_FULL	(0x80)
-#define DW_UART_IIR_TRIGGER_LEVEL_2_LESS_FULL	(0xC0)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL LCR Marcos
- * \brief	DesignWare UART hal LCR related macros
- * @{
- */
-/* LCR */
-#define DW_UART_LCR_WORD_LEN_MASK		(0x03)
-#define DW_UART_LCR_STOP_BIT_MASK		(0x04)
-#define DW_UART_LCR_PARITY_MASK			(0x38)
-#define DW_UART_LCR_DPS_MASK			(0x3F)
-#define DW_UART_LCR_STICK_PARITY		(0x20)
-#define DW_UART_LCR_BREAK			(0x40)
-#define DW_UART_LCR_DLAB			(0x80)
-
-/* Word length values */
-#define DW_UART_LCR_WORD_LEN5			(0x00)
-#define DW_UART_LCR_WORD_LEN6			(0x01)
-#define DW_UART_LCR_WORD_LEN7			(0x02)
-#define DW_UART_LCR_WORD_LEN8			(0x03)
-
-/* stop bit values */
-#define DW_UART_LCR_1_STOP_BIT			(0x00)
-#define DW_UART_LCR_1D5_STOP_BIT		(0x04)
-#define DW_UART_LCR_2_STOP_BIT			(0x04)
-
-/* Parity bit values */
-#define DW_UART_LCR_PARITY_NONE			(0x00)
-#define DW_UART_LCR_PARITY_ODD			(0x08)
-#define DW_UART_LCR_PARITY_EVEN			(0x18)
-#define DW_UART_LCR_PARITY_MARK			(0x28)
-#define DW_UART_LCR_PARITY_SPACE		(0x38)
-
-/** @} */
-
-/**
- * \name	DesignWare UART HAL MCR Marcos
- * \brief	DesignWare UART hal MCR related macros
- * @{
- */
-/* MCR */
-#define DW_UART_MCR_DTR				(0x01)
-#define DW_UART_MCR_RTS				(0x02)
-#define DW_UART_MCR_LOOPBACK			(0x10)
-#define DW_UART_MCR_AFCE			(0x20)
-#define DW_UART_MCR_SIRE			(0x40)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL LSR Marcos
- * \brief	DesignWare UART hal LSR related macros
- * @{
- */
-/* LSR */
-#define DW_UART_LSR_DR				(0x01)
-#define DW_UART_LSR_OVERRUN			(0x02)
-#define DW_UART_LSR_PARITYERR			(0x04)
-#define DW_UART_LSR_FRAMEERR			(0x08)
-#define DW_UART_LSR_BREAKRCVD			(0x10)
-#define DW_UART_LSR_TXD_EMPTY			(0x20)
-#define DW_UART_LSR_TX_STATUS			(0x40)
-#define DW_UART_LSR_RX_FIFOERR			(0x80)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL MSR Marcos
- * \brief	DesignWare UART hal MSR related macros
- * @{
- */
-/* MSR */
-#define DW_UART_MSR_DCTS			(0x01)
-#define DW_UART_MSR_DDSR			(0x02)
-#define DW_UART_MSR_TERI			(0x04)
-#define DW_UART_MSR_DDCD			(0x08)
-#define DW_UART_MSR_CTS				(0x10)
-#define DW_UART_MSR_DSR				(0x20)
-#define DW_UART_MSR_RIC				(0x40)
-#define DW_UART_MSR_DCD				(0x80)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL FCR Marcos
- * \brief	DesignWare UART hal FCR related macros
- * @{
- */
-/* FCR */
-#define DW_UART_FCR_FEN				(0x01)
-#define DW_UART_FCR_RFR				(0x02)
-#define DW_UART_FCR_TFR				(0x04)
-#define DW_UART_FCR_DMS				(0x08)
-#define DW_UART_FCR_RTL				(0xC0)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL USR Marcos
- * \brief	DesignWare UART hal USR related macros
- * @{
- */
-/* USR */
-#define DW_UART_USR_BUSY			(0x01)
-#define DW_UART_USR_TFNF			(0x02)
-#define DW_UART_USR_TFE				(0x04)
-#define DW_UART_USR_RFNE			(0x08)
-#define DW_UART_USR_RFF				(0x10)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL SFE Marcos
- * \brief	DesignWare UART hal SFE related macros
- * @{
- */
-/* SFE */
-#define DW_UART_SFE_SHADOW_FIFO_ENABLE		(0x01)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL SRR Marcos
- * \brief	DesignWare UART hal SRR related macros
- * @{
- */
-/* SRR */
-#define DW_UART_SRR_UR				(0x01)
-#define DW_UART_SRR_RFR				(0x02)
-#define DW_UART_SRR_XFR				(0x04)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL SRT Marcos
- * \brief	DesignWare UART hal SRT related macros
- * @{
- */
-/* SRT */
-#define DW_UART_SRT_TRIGGER_LEVEL_1_CHAR	(0x00)
-#define DW_UART_SRT_TRIGGER_LEVEL_1_4_FULL	(0x01)
-#define DW_UART_SRT_TRIGGER_LEVEL_1_2_FULL	(0x02)
-#define DW_UART_SRT_TRIGGER_LEVEL_2_LESS_FULL	(0x03)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL STET Marcos
- * \brief	DesignWare UART hal STET related macros
- * @{
- */
-/* STET*/
-#define DW_UART_STET_FIFO_EMPTY			(0x00)
-#define DW_UART_STET_2_CHARS_IN_FIFO		(0x01)
-#define DW_UART_STET_1_4_FULL			(0x02)
-#define DW_UART_STET_1_2_FULL			(0x03)
-/** @} */
-
-/**
- * \name	DesignWare UART HAL CPR Marcos
- * \brief	DesignWare UART hal CPR related macros
- * @{
- */
-/* CPR*/
-#define DW_UART_CPR_FIFO_STAT			(1<<10)
-#define DW_UART_CPR_FIFO_MODE_OFS		(16)
-#define DW_UART_CPR_FIFO_MODE_MASK		(0xFF)
-#define DW_UART_CPR_FIFO_MODE			(0xFF0000)
-/** @} */
-
-#endif /* _DEVICE_DW_UART_HAL_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h
deleted file mode 100644
index 623d54a611..0000000000
--- a/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-16
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_HAL_COMMON	Common Device Layer Definitions
- * \ingroup	DEVICE_HAL_DEF
- * \brief	common definitions for device layer (\ref dev_common.h)
- *
- * @{
- *
- * \file
- * \brief	header file to define common definitions for device layer
- * \details	Here in this file provide definitions that need by other
- * 	devices in device layer
- */
-
-#ifndef _DEVICE_HAL_COMMON_H_
-#define _DEVICE_HAL_COMMON_H_
-
-#include <stdint.h>
-
-/**
- * \defgroup	DEVICE_HAL_COMMON_DEVSTATE	Common Device State
- * \ingroup	DEVICE_HAL_COMMON
- * \brief	definitions for device state
- * \details	here defines macros for device open/close,
- * 	device working good/error, used in
- * 	\ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
- * 	\ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO
- * @{
- */
-/*
- * macros for device open and close state
- */
-#define DEV_CLOSED				(0)	/*!< Indicate that device was closed */
-#define DEV_OPENED				(1)	/*!< Indicate that the device was opened */
-
-/*
- * macros for device good and error state
- */
-#define DEV_GOOD				(0)	/*!< Indicate device is good */
-#define DEV_ERROR				(1)	/*!< Indicate device error */
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_COMMON_DEVMTHD	Common Device Working Method
- * \ingroup	DEVICE_HAL_COMMON
- * \brief	definitions for device working method(interrupt or poll)
- * \details	here defines macros for working method,
- * 	interrupt or poll method,used in
- * 	\ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
- * 	\ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO
- * @{
- */
-/*
- * macros for device working method
- */
-#define DEV_POLL_METHOD				(0)	/*!< Indicate that the device running in poll method */
-#define DEV_INTERRUPT_METHOD			(1)	/*!< Indicate that the device running in interrupt method */
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_COMMON_DEVMODE	Common Device Working Mode
- * \ingroup	DEVICE_HAL_COMMON
- * \brief	definitions for device working mode(master or slave)
- * \details	here defines macros for working mode,
- * 	Master or Slave mode,used in
- * 	\ref DEV_HAL_IIC, \ref DEV_HAL_SPI.
- * @{
- */
-/*
- * macros for device working mode
- */
-#define DEV_MASTER_MODE				(0)	/*!< Indicate that the device working as master */
-#define DEV_SLAVE_MODE				(1)	/*!< Indicate that the device working as slave */
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_COMMON_DEVSTATUS	Common Device Status
- * \ingroup	DEVICE_HAL_COMMON
- * \brief	definitions for device status, 1 bit for 1 function
- * @{
- */
-#define DEV_DISABLED				(0)	/*!< Bit 0 for device enabled state, disabled */
-#define DEV_ENABLED				(1<<0)	/*!< Bit 0 for device enabled state, enabled */
-#define DEV_IN_TX				(1<<1)	/*!< Bit 1 for device in transmit state */
-#define DEV_IN_RX				(1<<2)	/*!< Bit 2 for device in receive state */
-#define DEV_IN_XFER				(1<<3)	/*!< Bit 3 for device in transfer state */
-#define DEV_IN_TX_ABRT				(1<<4)	/*!< Bit 4 for device in transmit abort state */
-#define DEV_IN_RX_ABRT				(1<<5)	/*!< Bit 5 for device in receive abort state */
-#define DEV_IN_XFER_ABRT			(1<<6)	/*!< Bit 6 for device in transfer abort state */
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_COMMON_DEFCMD	Common Device Defining Command
- * \ingroup	DEVICE_HAL_COMMON
- * \brief	definitions for defining command code
- * \details	here defines macros to define command code,
- * 	in system code, use \ref DEV_SET_SYSCMD to define command code.
- * 	in user code, use \ref DEV_SET_USRCMD to define command code.
- * 	So that there will be no conflicts in system and user defined command code.
- * 	this used used in
- * 	\ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
- * 	\ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO,
- *     	and in user code
- * @{
- */
-/*
- * macros for control command base
- */
-#define DEV_SYS_CMDBSE				(0x00000000)		/*!< default system device control command base(defined by embARC) */
-#define DEV_USR_CMDBSE				(0x80000000)		/*!< default user device control command base(defined by user) in user implementing */
-#define DEV_SET_SYSCMD(cmd)			(DEV_SYS_CMDBSE|(cmd))	/*!< set device system control command */
-#define DEV_SET_USRCMD(cmd)			(DEV_USR_CMDBSE|(cmd))	/*!< set device user control command */
-
-#define CONV2VOID(param)			((void *)(param))	/*!< convert param into void * type */
-/** @} */
-
-/**
- * Common Device Buffer Structure
- */
-typedef struct dev_buffer {
-	void *buf;	/*!< buffer pointer */
-	uint32_t len;	/*!< buffer length in bytes */
-	uint32_t ofs;	/*!< current offset in buffer */
-} DEV_BUFFER;
-
-/** Init device buffer */
-#define DEV_BUFFER_INIT(devbuf, buffer, size)	{		\
-					(devbuf)->buf = (void *)(buffer);	\
-					(devbuf)->len = (uint32_t)(size);	\
-					(devbuf)->ofs = (uint32_t)(0);		\
-				}
-
-/**
- *   Device callback function typedef.
- * This is usually used in device callback settings,
- * and \ptr should be the device object pointer,
- * such as DEV_IIC * */
-typedef void (*DEV_CALLBACK) (void *ptr);
-
-/** @} */
-#endif /* _DEVICE_HAL_COMMON_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h
deleted file mode 100644
index 290fd313a2..0000000000
--- a/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-17
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_HAL_GPIO		GPIO Device HAL Interface
- * \ingroup	DEVICE_HAL_DEF
- * \brief	definitions for gpio device hardware layer (\ref dev_gpio.h)
- * \details	provide interfaces for gpio driver to implement
- *  Here is a diagram for the gpio interface.
- *
- *  \htmlonly
- *  <div class="imagebox">
- *      <div style="width: 600px">
- *          <img src="pic/dev_gpio_hal.jpg" alt="GPIO Device HAL Interface Diagram"/>
- *          <p>GPIO Device HAL Interface Diagram</p>
- *      </div>
- *  </div>
- *  \endhtmlonly
- *
- * @{
- *
- * \file
- * \brief	gpio device hardware layer definitions
- * \details	Provide common definitions for gpio device,
- * 	then the software developer can develop gpio driver
- * 	following these definitions, and the applications
- * 	can directly call this definition to realize functions
- *
- */
-
-#ifndef _DEVICE_HAL_GPIO_H_
-#define _DEVICE_HAL_GPIO_H_
-
-#include "device/device_hal/inc/dev_common.h"
-
-/**
- * \defgroup	DEVICE_HAL_GPIO_DEFDIR	GPIO Port Direction Definition
- * \ingroup	DEVICE_HAL_GPIO
- * \brief	Define macros to indicate gpio directions
- * @{
- */
-/*
- * defines for gpio directions
- */
-#define GPIO_DIR_INPUT				(0)		/*!< gpio works as input */
-#define GPIO_DIR_OUTPUT				(1)		/*!< gpio works as output */
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_GPIO_CTRLCMD		GPIO Device Control Commands
- * \ingroup	DEVICE_HAL_GPIO
- * \brief	Definitions for gpio control command, used in \ref dev_gpio::gpio_control "GPIO IO Control"
- * \details	These commands defined here can be used in user code directly.
- * - Parameters Usage
- *   - For passing parameters like integer, just use uint32_t/int32_t to directly pass values
- *   - For passing parameters for a structure, please use pointer to pass values
- *   - For getting some data, please use pointer to store the return data
- * - Common Return Values
- *   - \ref E_OK,	Control device successfully
- *   - \ref E_CLSED,	Device is not opened
- *   - \ref E_OBJ,	Device object is not valid or not exists
- *   - \ref E_PAR,	Parameter is not valid for current control command
- *   - \ref E_SYS,	Control device failed, due to hardware issues such as device is disabled
- *   - \ref E_NOSPT,	Control command is not supported or not valid
- * @{
- */
-/**
- * Set the \ref dev_gpio_info::direction "direction" of masked bits of gpio port into \ref GPIO_DIR_INPUT "input"
- * - Param type : uint32_t
- * - Param usage : 1 in each bit will be masked.
- * - Return value explanation :
- */
-#define GPIO_CMD_SET_BIT_DIR_INPUT			DEV_SET_SYSCMD(0)
-/**
- * Set the \ref dev_gpio_info::direction "direction" of masked bits of gpio port into \ref GPIO_DIR_OUTPUT "output"
- * - Param type : uint32_t
- * - Param usage : 1 in each bit will be masked.
- * - Return value explanation :
- */
-#define GPIO_CMD_SET_BIT_DIR_OUTPUT			DEV_SET_SYSCMD(1)
-/**
- * Get \ref dev_gpio_info::direction "gpio port direction".
- * - Param type : uint32_t
- * - Param usage : 1 bit for 1 bit of gpio port, 0 for input, 1 for output
- * - Return value explanation :
- */
-#define GPIO_CMD_GET_BIT_DIR				DEV_SET_SYSCMD(2)
-/**
- * Set gpio interrupt configuration for each bit.
- * - Param type : \ref DEV_GPIO_INT_CFG *
- * - Param usage : store gpio interrupt configuration for each bit.
- * - Return value explanation :
- */
-#define GPIO_CMD_SET_BIT_INT_CFG			DEV_SET_SYSCMD(3)
-/**
- * Get gpio interrupt configuration for each bit.
- * - Param type : \ref DEV_GPIO_INT_CFG *
- * - Param usage : First set int_bit_mask in DEV_GPIO_INT_CFG structure to
- * the mask of which bit of GPIO you want to get. And the interrupt configuration
- * will be stored in the structure DEV_GPIO_INT_CFG, each bit stand for each bit of port.
- * - Return value explanation :
- */
-#define GPIO_CMD_GET_BIT_INT_CFG			DEV_SET_SYSCMD(4)
-/**
- * Set gpio service routine for each bit.
- * - Param type : \ref DEV_GPIO_BIT_ISR *
- * - Param usage : store gpio handler information for each bit, int handler's param will be DEV_GPIO *.
- * - Return value explanation :
- */
-#define GPIO_CMD_SET_BIT_ISR				DEV_SET_SYSCMD(5)
-/**
- * Get gpio service routine for each bit.
- * - Param type : \ref DEV_GPIO_BIT_ISR *
- * - Param usage : By passing int_bit_ofs in DEV_GPIO_BIT_ISR,
- * it will return interrupt handler for this bit and store it in int_bit_handler.
- * - Return value explanation :
- */
-#define GPIO_CMD_GET_BIT_ISR				DEV_SET_SYSCMD(6)
-/**
- * Enable gpio interrupt of the masked bits.
- * - Param type : uint32_t
- * - Param usage : 1 in each bit will be masked.
- * - Return value explanation :
- */
-#define GPIO_CMD_ENA_BIT_INT				DEV_SET_SYSCMD(7)
-/**
- * Disable gpio interrupt of the masked bits.
- * - Param type : uint32_t
- * - Param usage : 1 in each bit will be masked.
- * - Return value explanation :
- */
-#define GPIO_CMD_DIS_BIT_INT				DEV_SET_SYSCMD(8)
-/**
- * Get \ref dev_gpio_info::method "gpio interrupt enable status".
- * - Param type : uint32_t *
- * - Param usage : 1 bit for 1 bit of gpio port, 0 for poll, 1 for interrupt
- * - Return value explanation :
- */
-#define GPIO_CMD_GET_BIT_MTHD				DEV_SET_SYSCMD(9)
-/* @} */
-
-/**
- * \defgroup	DEVICE_HAL_GPIO_INT_CFG_SET	GPIO Device Int Configuration Settings
- * \ingroup	DEVICE_HAL_GPIO
- * \brief	definition of gpio interrupt type
- * @{
- */
-
-/* GPIO Mask Defintions */
-/** Mask none bits of the max 32bits */
-#define GPIO_BITS_MASK_NONE			(0)
-/** Mask all bits of the max 32bits */
-#define GPIO_BITS_MASK_ALL			(0XFFFFFFFF)
-
-/* GPIO Interrupt Type Related Definitions */
-
-/** Level sensitive interrupt type for 1 bit */
-#define GPIO_INT_LEVEL_TRIG			(0)
-/** Edge sensitive interrupt type for 1 bit */
-#define GPIO_INT_EDGE_TRIG			(1)
-/** Level sensitive interrupt type for all 32 bits */
-#define GPIO_INT_LEVEL_TRIG_ALL			(0)
-/** Edge sensitive interrupt type for all 32 bits */
-#define GPIO_INT_EDGE_TRIG_ALL			(0XFFFFFFFF)
-
-/* For bit settings */
-/** Set bit interrupt type of gpio into level sensitive */
-#define GPIO_INT_BIT_LEVEL_TRIG(bit_ofs)	(GPIO_INT_LEVEL_TRIG<<(bit_ofs))
-/** Set bit interrupt type of gpio into edge sensitive */
-#define GPIO_INT_BIT_EDGE_TRIG(bit_ofs)		(GPIO_INT_EDGE_TRIG<<(bit_ofs))
-/* For bits settings */
-/** Set interrupt type of masked bits of gpio into level sensitive */
-#define GPIO_INT_BITS_LEVEL_TRIG(bit_mask)	(GPIO_INT_LEVEL_TRIG_ALL&(bit_mask))
-/** Set bit interrupt type of gpio into edge sensitive */
-#define GPIO_INT_BITS_EDGE_TRIG(bit_mask)	(GPIO_INT_EDGE_TRIG_ALL&(bit_mask))
-
-/* GPIO Interrupt Polarity Related Definitions */
-
-/** GPIO Interrupt polarity type enum */
-typedef enum gpio_int_polarity {
-	/* Polarity for 1 bit */
-	GPIO_INT_ACTIVE_LOW   = 0, /*!< Active low for level-sensitive interrupt for 1 bit */
-	GPIO_INT_FALLING_EDGE = 0, /*!< Falling-edge for edge-sensitive interrupt for 1 bit */
-	GPIO_INT_ACTIVE_HIGH =  1, /*!< Active high for level-sensitive interrupt for 1 bit */
-	GPIO_INI_RISING_EDGE = 1, /*!< Rising-edge for edge-sensitive interrupt for 1 bit */
-	/* Polartiy for all 32 bits */
-	GPIO_INT_ACTIVE_LOW_ALL   = 0, /*!< Active low for level-sensitive interrupt for all bits */
-	GPIO_INT_FALLING_EDGE_ALL = 0, /*!< Falling-edge for edge-sensitive interrupt for all bits */
-	GPIO_INT_ACTIVE_HIGH_ALL =  0XFFFFFFFF, /*!< Active high for level-sensitive interrupt for all bits */
-	GPIO_INI_RISING_EDGE_ALL = 0XFFFFFFFF /*!< Rising-edge for edge-sensitive interrupt for all bits */
-} GPIO_INT_POLARITY;
-
-/* For bit settings */
-/** Set bit polarity of gpio into active low */
-#define GPIO_INT_BIT_POL_ACT_LOW(bit_ofs)	(GPIO_INT_ACTIVE_LOW<<(bit_ofs))
-/** Set bit polarity of gpio into active high */
-#define GPIO_INT_BIT_POL_ACT_HIGH(bit_ofs)	(GPIO_INT_ACTIVE_HIGH<<(bit_ofs))
-/** Set bit polarity of gpio into falling edge */
-#define GPIO_INT_BIT_POL_FALL_EDGE(bit_ofs)	(GPIO_INT_FALLING_EDGE<<(bit_ofs))
-/** Set bit polarity of gpio into rising edge */
-#define GPIO_INT_BIT_POL_RISE_EDGE(bit_ofs)	(GPIO_INI_RISING_EDGE<<(bit_ofs))
-
-/* For bits settings */
-/** Set polarity of masked bits of gpio into active low */
-#define GPIO_INT_BITS_POL_ACT_LOW(bit_mask)	(GPIO_INT_ACTIVE_LOW_ALL&(bit_mask))
-/** Set polarity of masked bits of gpio into active high */
-#define GPIO_INT_BITS_POL_ACT_HIGH(bit_mask)	(GPIO_INT_ACTIVE_HIGH_ALL&(bit_mask))
-/** Set polarity of masked bits of gpio into falling edge */
-#define GPIO_INT_BITS_POL_FALL_EDGE(bit_mask)	(GPIO_INT_FALLING_EDGE_ALL&(bit_mask))
-/** Set polarity of masked bits of gpio into rising edge */
-#define GPIO_INT_BITS_POL_RISE_EDGE(bit_mask)	(GPIO_INI_RISING_EDGE_ALL&(bit_mask))
-
-/* GPIO Interrupt Debounce Related Definitions */
-
-/* For bit settings */
-/** Disable debounce circuitry for 1 bit */
-#define GPIO_INT_NO_DEBOUNCE			(0)
-/** Enable debounce circuitry for 1 bit */
-#define GPIO_INT_DEBOUNCE			(1)
-
-/* For bits settings */
-/** Disable debounce circuitry for all bits */
-#define GPIO_INT_NO_DEBOUNCE_ALL		(0)
-/** Enable debounce circuitry for all bits */
-#define GPIO_INT_DEBOUNCE_ALL			(0XFFFFFFFF)
-
-/* For bit settings */
-/** Set bit interrupt debounce of gpio into enabled */
-#define GPIO_INT_BIT_ENA_DEBOUNCE(bit_ofs)	(GPIO_INT_DEBOUNCE<<(bit_ofs))
-/** Set bit interrupt debounce of gpio into disabled */
-#define GPIO_INT_BIT_DIS_DEBOUNCE(bit_ofs)	(GPIO_INT_NO_DEBOUNCE<<(bit_ofs))
-/* For bits settings */
-/** Set bit interrupt debounce of gpio into enabled */
-#define GPIO_INT_BITS_ENA_DEBOUNCE(bit_mask)	(GPIO_INT_DEBOUNCE_ALL&(bit_mask))
-/** Set bit interrupt debounce of gpio into disabled */
-#define GPIO_INT_BITS_DIS_DEBOUNCE(bit_mask)	(GPIO_INT_NO_DEBOUNCE_ALL&(bit_mask))
-
-/** GPIO interrupt configuration */
-typedef struct dev_gpio_int_cfg {
-	uint32_t int_bit_mask;		/*!< interrupt bit mask for gpio */
-	uint32_t int_bit_type;		/*!< \ref GPIO_INT_LEVEL_TRIG "level sensitive" or \ref GPIO_INT_EDGE_TRIG "edge sensitive" for each gpio bit */
-	uint32_t int_bit_polarity;	/*!< active high or low, refer to \ref GPIO_INT_POLARITY for each gpio bit */
-	uint32_t int_bit_debounce;	/*!< \ref GPIO_INT_DEBOUNCE "enable" or \ref GPIO_INT_NO_DEBOUNCE "disable" debounce logic for each gpio bit */
-} DEV_GPIO_INT_CFG, * DEV_GPIO_INT_CFG_PTR;
-
-/** Default interrupt configuration for all gpio bits */
-static const DEV_GPIO_INT_CFG gpio_int_cfg_default = \
-	{GPIO_BITS_MASK_ALL, GPIO_INT_LEVEL_TRIG_ALL, \
-		GPIO_INT_ACTIVE_LOW_ALL, GPIO_INT_NO_DEBOUNCE_ALL};
-
-/** GPIO interrupt handler or Interrupt Service Routine(ISR) */
-typedef void (*DEV_GPIO_HANDLER) (void *ptr);
-
-/** interrupt handler for each port bit */
-typedef struct dev_gpio_bit_isr {
-	uint32_t int_bit_ofs;			/*!< int bit offset */
-	DEV_GPIO_HANDLER int_bit_handler;	/*!< interrupt handler */
-} DEV_GPIO_BIT_ISR, * DEV_GPIO_BIT_ISR_PTR;
-/* @} */
-
-/**
- * \defgroup	DEVICE_HAL_GPIO_DEVSTRUCT	GPIO Device Interface Definition
- * \ingroup	DEVICE_HAL_GPIO
- * \brief	contains definitions of gpio device structure.
- * \details	This structure will be used in user implemented code, which was called
- *     \ref DEVICE_IMPL "Device Driver Implement Layer" for gpio to use in implementation code.
- *     Application developer should use the GPIO API provided here to access to GPIO devices.
- *     BSP developer should follow the API definition to implement GPIO device drivers.
- * @{
- */
-/**
- * \brief	gpio information struct definition
- * \details	informations about gpio open count, working status
- * 	gpio registers and control block, gpio io direction and interrupt/poll for each bit of gpio
- * \note	Only available for gpio with max 32bits
- */
-typedef struct dev_gpio_info {
-	void *gpio_ctrl;	/*!< gpio control related pointer, implemented by bsp developer, and this should be set during gpio object implementation */
-	uint32_t opn_cnt;	/*!< gpio open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */
-	uint32_t direction;	/*!< each bit direction of this GPIO, default all \ref GPIO_DIR_INPUT "input" for first open */
-	uint32_t method;	/*!< int/poll method for each bit of GPIO, 0 for poll, 1 for interrupt, default all \ref DEV_POLL_METHOD "poll" for first open */
-	void * extra;		/*!< a extra pointer to get hook to applications which should not used by bsp developer,
-					this should be NULL for first open and you can \ref DEV_GPIO_INFO_SET_EXTRA_OBJECT "set"
-					or \ref DEV_GPIO_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */
-} DEV_GPIO_INFO, * DEV_GPIO_INFO_PTR;
-/** Set extra information pointer of gpio info */
-#define DEV_GPIO_INFO_SET_EXTRA_OBJECT(gpio_info_ptr, extra_info)	(gpio_info_ptr)->extra = (void *)(extra_info)
-/** Get extra information pointer of gpio info */
-#define DEV_GPIO_INFO_GET_EXTRA_OBJECT(gpio_info_ptr)			((gpio_info_ptr)->extra)
-
-/** Method of all gpio bits set to poll */
-#define DEV_GPIO_BITS_MTHD_POLL			(0)
-/** Method of all gpio bits set to interrupt */
-#define DEV_GPIO_BITS_MTHD_INTERRUPT		(0xFFFFFFFF)
-/** Default method of all gpio bits should be poll for first open */
-#define DEV_GPIO_BITS_MTHD_DEFAULT		(DEV_GPIO_BITS_MTHD_POLL)
-
-/**
- * \brief	gpio device interface definition
- * \details	define gpio device interface, like gpio information structure,
- * 	fuctions to open/close/control gpio, write or read data via gpio
- * \note	all this details are implemented by user in user porting code
- */
-typedef struct dev_gpio {
-	DEV_GPIO_INFO gpio_info;		/*!< gpio device information */
-	int32_t (*gpio_open) (uint32_t dir);	/*!< open gpio device with pre-defined gpio direction */
-	int32_t (*gpio_close) (void);		/*!< close gpio device */
-	int32_t (*gpio_control) (uint32_t ctrl_cmd, void *param);	/*!< control gpio device */
-	int32_t (*gpio_write) (uint32_t val, uint32_t mask);	/*!< write gpio device with val, only write the masked bits */
-	int32_t (*gpio_read) (uint32_t *val, uint32_t mask);	/*!< read gpio device val, only read the masked bits */
-} DEV_GPIO, * DEV_GPIO_PTR;
-
-/**
- * \fn		int32_t (* dev_gpio::gpio_open) (uint32_t dir)
- * \details	Open a gpio device with pre-defined io direction.
- * \param[in]	dir	gpio direction for each bit
- * \retval	E_OK	Open successfully without any issues
- * \retval	E_OPNED	If device was opened before with different parameters,
- *			then just increase the \ref dev_gpio_info::opn_cnt "opn_cnt" and return \ref E_OPNED
- * \retval	E_OBJ	Device object is not valid
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_NOSPT	Open settings are not supported
- */
-
-/**
- * \fn		int32_t (* dev_gpio::gpio_close) (void)
- * \details	Close an gpio device, just decrease the \ref dev_gpio_info::opn_cnt "opn_cnt",
- *      if \ref dev_gpio_info::opn_cnt "opn_cnt" equals 0, then close the device
- * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
- * \retval	E_OPNED	Device is still opened, the device \ref dev_gpio_info::opn_cnt "opn_cnt" decreased by 1
- * \retval	E_OBJ	Device object is not valid
- */
-
-/**
- * \fn		int32_t (* dev_gpio::gpio_control) (uint32_t ctrl_cmd, void *param)
- * \details	Control an gpio device by \ref ctrl_cmd, with passed \ref param.
- * 	you can control gpio device using predefined gpio control commands defined using \ref DEV_SET_SYSCMD
- * 	(which must be implemented by bsp developer), such as \ref GPIO_CMD_SET_BIT_DIR_INPUT
- * 	"change masked gpio direction to input", and \ref DEVICE_HAL_GPIO_CTRLCMD "more".
- * 	And you can also control gpio device using your own specified commands defined using \ref DEV_SET_USRCMD,
- * 	but these specified commands should be defined in your own gpio device driver implementation.
- * \param[in]		ctrl_cmd	\ref DEVICE_HAL_GPIO_CTRLCMD "control command", to change or get some thing related to gpio
- * \param[in,out]	param		parameters that maybe argument of the command, or return values of the command
- * \retval	E_OK	Control device successfully
- * \retval	E_CLSED	Device is not opened
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Control device failed, due to hardware issues
- * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
- * \retval	E_NOSPT	Control command is not supported or not valid, such as interrupt is not supported
- */
-
-/**
- * \fn		int32_t (* dev_gpio::gpio_write) (uint32_t val, uint32_t mask)
- * \details	Write gpio with \ref val, and only change the masked bits of gpio.
- * \param[in]	val	the data that need to write to gpio
- * \param[in]	mask	gpio bit mask
- * \retval	E_OK	Write gpio with specified value successfully
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid
- */
-
-/**
- * \fn		int32_t (* dev_gpio::gpio_read) (uint32_t *val, uint32_t mask)
- * \details	Read the masked gpio value
- * \param[out]	val	pointer to data need to read from gpio
- * \param[in]	mask	gpio bit mask
- * \retval	E_OK	Read gpio data successfully
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid
- */
-
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief	get an \ref dev_gpio "gpio device" by gpio device id.
- * 	For how to use gpio device hal refer to \ref dev_gpio "Functions in gpio device structure"
- * \param[in]	gpio_id	id of gpio, defined by user
- * \retval	!NULL	pointer to an \ref dev_gpio "gpio device structure"
- * \retval	NULL	failed to find the gpio device by \ref gpio_id
- * \note	need to implemented by user in user code
- */
-extern DEV_GPIO_PTR gpio_get_dev(int32_t gpio_id);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-#endif /* _DEVICE_HAL_GPIO_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h
deleted file mode 100644
index 14106671ff..0000000000
--- a/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h
+++ /dev/null
@@ -1,526 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-06-16
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_HAL_IIC	IIC Device HAL Interface
- * \ingroup	DEVICE_HAL_DEF
- * \brief	definitions for iic device hardware layer (\ref dev_iic.h)
- * \details	provide interfaces for iic driver to implement
- *  Here is a diagram for the iic interface.
- *
- *  \htmlonly
- *  <div class="imagebox">
- *      <div style="width: 600px">
- *          <img src="pic/dev_iic_hal.jpg" alt="IIC Device HAL Interface Diagram"/>
- *          <p>IIC Device HAL Interface Diagram</p>
- *      </div>
- *  </div>
- *  \endhtmlonly
- *
- * @{
- *
- * \file
- * \brief	iic device hardware layer definitions
- * \details	provide common definitions for iic device,
- * 	then software developer can develop iic driver
- * 	following this definitions, and the applications
- * 	can directly call this definition to realize functions
- */
-
-#ifndef _DEVICE_HAL_IIC_H_
-#define _DEVICE_HAL_IIC_H_
-
-#include "device/device_hal/inc/dev_common.h"
-
-/**
- * \defgroup	DEVICE_HAL_IIC_CFG	IIC Related Configurations
- * \ingroup	DEVICE_HAL_IIC
- * \brief	Macros for IIC device related configurations.
- * @{
- */
-/** IIC Bus possible speed modes */
-typedef enum iic_speed_mode {
-	IIC_SPEED_STANDARD = 0,	/*!< Bidirectional, Standard-mode (Sm), with a bit rate up to 100 kbit/s */
-	IIC_SPEED_FAST     = 1,	/*!< Bidirectional, Fast-mode (Fm), with a bit rate up to 400 kbit/s */
-	IIC_SPEED_FASTPLUS = 2,	/*!< Bidirectional, Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s */
-	IIC_SPEED_HIGH     = 3,	/*!< Bidirectional, High-speed mode (Hs-mode), with a bit rate up to 3.4 Mbit/s */
-	IIC_SPEED_ULTRA    = 4	/*!< Unidirectional(Write only), Ultra Fast-mode (UFm), with a bit rate up to 5 Mbit/s */
-} IIC_SPEED_MODE;
-
-/** IIC next Condition */
-typedef enum iic_next_condtion {
-	IIC_MODE_STOP    = 0,	/*!< Send a STOP condition after write/read operation */
-	IIC_MODE_RESTART = 1	/*!< Send a RESTART condition after write/read operation */
-} IIC_NEXT_CONDTION;
-
-/** IIC Error State */
-typedef enum iic_error_state {
-	IIC_ERR_NONE       = 0,	/*!< Currently in iic device free state */
-	IIC_ERR_LOST_BUS   = 1,	/*!< Master or slave lost bus during operation */
-	IIC_ERR_ADDR_NOACK = 2,	/*!< Slave address is sent but not addressed by any slave devices */
-	IIC_ERR_DATA_NOACK = 3,	/*!< Data in transfer is not acked when it should be acked */
-	IIC_ERR_TIMEOUT    = 4,	/*!< Transfer timeout, no more data is received or sent */
-	IIC_ERR_MSTSTOP    = 5,	/*!< Slave received a STOP condition from master device */
-	IIC_ERR_UNDEF      = 6	/*!< Undefined error cases */
-} IIC_ERROR_STATE;
-
-/** IIC Working State */
-typedef enum iic_working_state {
-	IIC_FREE  = 0,	/*!< Currently in iic device free state */
-	IIC_IN_TX = 1,	/*!< Currently in iic master transmit state */
-	IIC_IN_RX = 2	/*!< Currently in iic master receive state */
-} IIC_WORKING_STATE;
-
-/** IIC Addressing Mode */
-typedef enum iic_address_mode {
-	IIC_7BIT_ADDRESS  = 0,	/*!< Use 7bit address mode */
-	IIC_10BIT_ADDRESS = 1	/*!< Use 10bit address mode */
-} IIC_ADDRESS_MODE;
-
-/** IIC Slave State */
-typedef enum iic_slave_state {
-	IIC_SLAVE_STATE_FREE     = 0,		/*!< None state, in free */
-	IIC_SLAVE_STATE_START    = (1<<1),	/*!< Start or Restart condition, clear it when read */
-	IIC_SLAVE_STATE_STOP     = (1<<2),	/*!< Stop condition, clear it when read */
-	IIC_SLAVE_STATE_RD_REQ   = (1<<3),	/*!< Read request from master, this will trigger the slave transmit callback */
-	IIC_SLAVE_STATE_RD_DONE  = (1<<4),	/*!< Read request done from master, clear it when read */
-	IIC_SLAVE_STATE_WR_REQ   = (1<<5),	/*!< Write request from master, this will trigger the slave receive callback */
-	IIC_SLAVE_STATE_GC_REQ   = (1<<6),	/*!< General call request from master */
-	IIC_SLAVE_STATE_ERROR    = (1<<7)	/*!< Error, clear it when read */
-} IIC_SLAVE_STATE;
-
-/** 7bit IIC address mask */
-#define IIC_7BIT_ADDRESS_MASK		(0x7F)
-/** 10bit IIC address mask */
-#define IIC_10BIT_ADDRESS_MASK		(0x3FF)
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_IIC_CTRLCMD		IIC Device Control Commands
- * \ingroup	DEVICE_HAL_IIC
- * \brief	Definitions for iic control command, used in \ref dev_iic::iic_control "IIC IO Control"
- * \details	These commands defined here can be used in user code directly.
- * - Parameters Usage
- *   - For passing parameters like integer, just use uint32_t/int32_t to directly pass values
- *   - For passing parameters for a structure, please use pointer to pass values
- *   - For getting some data, please use pointer to store the return data
- * - Common Return Values
- *   - \ref E_OK,	Control device successfully
- *   - \ref E_CLSED,	Device is not opened
- *   - \ref E_OBJ,	Device object is not valid or not exists
- *   - \ref E_PAR,	Parameter is not valid for current control command
- *   - \ref E_SYS,	Control device failed, due to hardware issues such as device is disabled
- *   - \ref E_CTX,	Control device failed, due to different reasons like in transfer state
- *   - \ref E_NOSPT,	Control command is not supported or not valid
- * @{
- */
-
-/** Define IIC control commands for common usage */
-#define DEV_SET_IIC_SYSCMD(cmd)		DEV_SET_SYSCMD((cmd))
-/** Define IIC control commands for master usage */
-#define DEV_SET_IIC_MST_SYSCMD(cmd)	DEV_SET_SYSCMD(0x00004000|(cmd))
-/** Define IIC control commands for slave usage */
-#define DEV_SET_IIC_SLV_SYSCMD(cmd)	DEV_SET_SYSCMD(0x00008000|(cmd))
-
-/* ++++ Common commands for IIC Device ++++ */
-/**
- * Get \ref dev_iic_info::status "current device status"
- * - Param type : uint32_t *
- * - Param usage : store result of current status
- * - Return value explanation :
- */
-#define IIC_CMD_GET_STATUS			DEV_SET_IIC_SYSCMD(0)
-/**
- * Set \ref dev_iic_info::addr_mode "iic addressing mode".
- * - Param type : uint32_t
- * - Param usage : iic addressing mode, possible values can be found \ref IIC_ADDRESS_MODE "here"
- * - Return value explanation :
- */
-#define IIC_CMD_SET_ADDR_MODE			DEV_SET_IIC_SYSCMD(1)
-/**
- * Set \ref dev_iic_cbs::tx_cb "iic transmit success callback" function
- * when all required bytes are transmitted for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : transmit success callback function for iic
- * - Return value explanation :
- */
-#define IIC_CMD_SET_TXCB			DEV_SET_IIC_SYSCMD(2)
-/**
- * Set \ref dev_iic_cbs::rx_cb "iic receive success callback" function
- * when all required bytes are received for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : receive success callback function for iic
- * - Return value explanation :
- */
-#define IIC_CMD_SET_RXCB			DEV_SET_IIC_SYSCMD(3)
-/**
- * Set \ref dev_iic_cbs::err_cb "iic transfer error callback" function
- * when something error happened for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : transfer error callback function for iic
- * - Return value explanation :
- */
-#define IIC_CMD_SET_ERRCB			DEV_SET_IIC_SYSCMD(4)
-/**
- * Set buffer for interrupt transmit, and it will set \ref dev_iic_info::tx_buf "tx_buf".
- * - IIC master mode use case  \n
- *    For master mode, if you set tx buffer to NULL, when tx interrupt is enabled and entered into tx interrupt,
- * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the
- * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt
- * and call tx callback function if available.
- * - IIC slave mode use case   \n
- *    For slave mode, the tx buffer is not used, only tx callback function is used, and if tx callback is not set,
- * then it will automatically disable the tx interrupt, if tx callback is set, it will call the tx callback function
- * and you need to write or read in the tx callback function, to avoid meaningless waiting, you can use control command
- * \ref IIC_CMD_GET_TXAVAIL to get how many bytes space existing in transmit fifo, and use iic_write to send the available
- * bytes.
- * - Param type : DEV_BUFFER * or NULL
- * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL
- * - Return value explanation :
- */
-#define IIC_CMD_SET_TXINT_BUF			DEV_SET_IIC_SYSCMD(5)
-/**
- * Set buffer for interrupt receive, and it will set \ref dev_iic_info::rx_buf "rx_buf"
- * - IIC master mode use case  \n
- *   Similar to \ref IIC_CMD_SET_TXINT_BUF
- * - IIC slave mode use case   \n
- *   Similiar to \ref IIC_CMD_SET_TXINT_BUF
- * - Param type : DEV_BUFFER * or NULL
- * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL
- * - Return value explanation :
- */
-#define IIC_CMD_SET_RXINT_BUF			DEV_SET_IIC_SYSCMD(6)
-/**
- * Enable or disable transmit interrupt,
- * for master mode, only one of tx and rx interrupt can be enabled,
- * if tx interrupt is enabled, then rx interrupt can't be changed.
- * - Param type : uint32_t
- * - Param usage : enable(none-zero) or disable(zero) flag
- * - Return value explanation :
- */
-#define IIC_CMD_SET_TXINT			DEV_SET_IIC_SYSCMD(7)
-/**
- * Enable or disable receive interrupt,
- * for master mode, only one of tx and rx interrupt can be enabled,
- * if rx interrupt is enabled, then tx interrupt can't be changed.
- * - Param type : uint32_t
- * - Param usage : enable(none-zero) or disable(zero) flag
- * - Return value explanation :
- */
-#define IIC_CMD_SET_RXINT			DEV_SET_IIC_SYSCMD(8)
-/**
- * Abort current interrupt transmit operation if tx interrupt enabled,
- * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT
- * in \ref dev_iic_info::status "status" variable,
- * and call the transmit callback function, when tx callback is finished,
- * it will clear \ref DEV_IN_TX_ABRT and return
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define IIC_CMD_ABORT_TX			DEV_SET_IIC_SYSCMD(9)
-/**
- * Abort current interrupt receive operation if rx interrupt enabled,
- * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT
- * in \ref dev_iic_info::status "status" variable,
- * and call the receive callback function, when rx callback is finished,
- * it will clear \ref DEV_IN_TX_ABRT and return
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define IIC_CMD_ABORT_RX			DEV_SET_IIC_SYSCMD(10)
-/**
- * Do a software reset for IIC device, it will stop current transfer,
- * and clear error state and bring device to normal state, set next condition to STOP
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define IIC_CMD_RESET				DEV_SET_IIC_SYSCMD(11)
-/**
- * Flush iic device transmit buffer or fifo
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define IIC_CMD_FLUSH_TX			DEV_SET_IIC_SYSCMD(12)
-/**
- * Flush iic device receive buffer or fifo
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define IIC_CMD_FLUSH_RX			DEV_SET_IIC_SYSCMD(13)
-/**
- * Enable iic device
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define IIC_CMD_ENA_DEV				DEV_SET_IIC_SYSCMD(14)
-/**
- * Disable iic device, when device is disabled,
- * only \ref IIC_CMD_ENA_DEV, \ref IIC_CMD_DIS_DEV,
- * \ref IIC_CMD_GET_STATUS and \ref IIC_CMD_RESET
- * commands can be executed, other commands will return \ref E_SYS
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define IIC_CMD_DIS_DEV				DEV_SET_IIC_SYSCMD(15)
-/**
- * Get how many bytes space in iic are available to transmit,
- * this can be used in interrupt callback functions,
- * cooperate with \ref dev_iic::iic_write "iic_write" API to realize non-blocked write
- * - Param type : int32_t *
- * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available
- * - Return value explaination :
- */
-#define IIC_CMD_GET_TXAVAIL			DEV_SET_IIC_SYSCMD(16)
-/**
- * Get how many bytes in iic are available to receive,
- * this can be used in interrupt callback functions,
- * cooperate with \ref dev_iic::iic_read "iic_read" API to realize non-blocked read
- * - Param type : int32_t *
- * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available
- * - Return value explanation :
- */
-#define IIC_CMD_GET_RXAVAIL			DEV_SET_IIC_SYSCMD(17)
-
-/* ++++ Master only commands for IIC Device ++++ */
-/**
- * Set \ref dev_iic_info::speed_mode "iic speed mode".
- * - Param type : uint32_t
- * - Param usage : iic speed mode, possible values can be found \ref IIC_SPEED_MODE "here",
- * and if passing mode is not supported, it will choose a lower supported speed mode
- * - Return value explanation :
- */
-#define IIC_CMD_MST_SET_SPEED_MODE		DEV_SET_IIC_MST_SYSCMD(0)
-/**
- * Set next condition for following transmit or receive operation.
- * For example, you can change next condition before iic_read or iic_write,
- * then in iic_read/iic_write operation, it will send a STOP/RESTART condition
- * after the last byte of this operation. For interrupt, this is similar.
- * - Param type : uint32_t
- * - Param usage : next condition can be \ref IIC_NEXT_CONDTION
- * - Return value explanation :
- */
-#define IIC_CMD_MST_SET_NEXT_COND		DEV_SET_IIC_MST_SYSCMD(1)
-/**
- * Set target slave device address for selecting slave device
- * - Param type : uint32_t
- * - Param usage : target slave address value
- * - Return value explanation :
- */
-#define IIC_CMD_MST_SET_TAR_ADDR		DEV_SET_IIC_MST_SYSCMD(2)
-
-
-/* ++++ Slave only commands for IIC Device ++++ */
-/**
- * Set slave address when working as slave iic device
- * - Param type : uint32_t
- * - Param usage : slave address value
- * - Return value explanation :
- */
-#define IIC_CMD_SLV_SET_SLV_ADDR		DEV_SET_IIC_SLV_SYSCMD(0)
-/**
- * Get \ref iic_slave_state "slave state" when working as slave iic device
- * - Param type : uint32_t *
- * - Param usage : slave state
- * - Return value explanation :
- */
-#define IIC_CMD_SLV_GET_SLV_STATE		DEV_SET_IIC_SLV_SYSCMD(1)
-
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_IIC_CALLBACK	IIC Interrupt callback functions
- * \ingroup	DEVICE_HAL_IIC
- * \brief	callback function structure for IIC device
- * @{
- */
-typedef struct dev_iic_cbs {
-	DEV_CALLBACK tx_cb;	/*!< iic data transmit success required bytes callback */
-	DEV_CALLBACK rx_cb;	/*!< iic data receive success required bytes callback */
-	DEV_CALLBACK err_cb;	/*!< iic error callback */
-} DEV_IIC_CBS, *DEV_IIC_CBS_PTR;
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_IIC_DEVSTRUCT	IIC Device Structure
- * \ingroup	DEVICE_HAL_IIC
- * \brief	contains definitions of iic device structure.
- * \details	this structure will be used in user implemented code, which was called
- *     Device Driver Implement Layer for iic to realize in user code.
- * @{
- */
-/**
- * \brief	iic information struct definition
- * \details	informations about iic open state, working state,
- * 	baurate, iic registers, working method, interrupt number
- */
-typedef struct dev_iic_info {
-	void *iic_ctrl;		/*!< iic control related pointer, implemented by bsp developer, and this should be set during iic object implementation */
-	uint32_t opn_cnt;	/*!< iic open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */
-	uint32_t status;	/*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */
-	uint32_t mode;		/*!< current working mode, which can be \ref DEV_MASTER_MODE "master mode" or \ref DEV_SLAVE_MODE "slave mode" */
-	uint32_t speed_mode;	/*!< current working \ref IIC_SPEED_MODE "iic speed mode" */
-	uint32_t cur_state;	/*!< \ref IIC_WORKING_STATE "current working state for iic device", this should be \ref IIC_FREE for first open */
-	uint32_t err_state;	/*!< \ref IIC_ERROR_STATE "current error state for iic device", this should be \ref IIC_ERR_NONE for first open */
-	uint32_t addr_mode;	/*!< \ref IIC_ADDRESS_MODE "current addressing mode", this should be \ref IIC_7BIT_ADDRESS for first open */
-	uint32_t slv_addr;	/*!< slave address when working as slave iic device, this should be 0 for first open */
-	uint32_t tar_addr;	/*!< target slave device address when addressing that slave device, this should be 0 for first open */
-	uint32_t next_cond;	/*!< \ref IIC_NEXT_CONDTION "next condition for master transmit or receive", \
-					possible values are STOP or RESTART, it should be STOP for first open */
-	DEV_BUFFER tx_buf;	/*!< transmit buffer via interrupt, this should be all zero for first open */
-	DEV_BUFFER rx_buf;	/*!< receive buffer via interrupt, this should be all zero for first open */
-	DEV_IIC_CBS iic_cbs;	/*!< iic callbacks, for both master and slave mode, this should be all NULL for first open */
-	void *extra;		/*!< a extra pointer to get hook to applications which should not used by bsp developer,
-					this should be NULL for first open and you can \ref DEV_IIC_INFO_SET_EXTRA_OBJECT "set"
-					or \ref DEV_IIC_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */
-} DEV_IIC_INFO, * DEV_IIC_INFO_PTR;
-
-/** Set extra information pointer of iic info */
-#define DEV_IIC_INFO_SET_EXTRA_OBJECT(iic_info_ptr, extra_info)		(iic_info_ptr)->extra = (void *)(extra_info)
-/** Get extra information pointer of iic info */
-#define DEV_IIC_INFO_GET_EXTRA_OBJECT(iic_info_ptr)			((iic_info_ptr)->extra)
-
-/**
- * \brief	iic device interface definition
- * \details	define iic device interface, like iic information structure,
- * 	fuctions to get iic info, open/close/control iic, send/receive data by iic
- * \note	all this details are implemented by user in user porting code
- */
-typedef struct dev_iic {
-	DEV_IIC_INFO iic_info;					/*!< iic device information */
-	int32_t (*iic_open) (uint32_t mode, uint32_t param);	/*!< open iic device in master/slave mode, \
-									when in master mode, param stands for speed mode, \
-									when in slave mode, param stands for slave address */
-	int32_t (*iic_close) (void);				/*!< close iic device */
-	int32_t (*iic_control) (uint32_t ctrl_cmd, void *param);/*!< control iic device */
-	int32_t (*iic_write) (const void *data, uint32_t len);	/*!< send data by iic device (blocking method) */
-	int32_t (*iic_read) (void *data, uint32_t len);		/*!< read data from iic device (blocking method) */
-} DEV_IIC, * DEV_IIC_PTR;
-
-/**
- * \fn		int32_t (* dev_iic::iic_open) (uint32_t mode, uint32_t param)
- * \details	open an iic device with selected mode (master or slave) with defined \ref param
- * \param[in]	mode	working mode (\ref DEV_MASTER_MODE "master" or \ref DEV_SLAVE_MODE "slave")
- * \param[in]	param	When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_iic_info::speed_mode "speed mode",
- * 			when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_iic_info::slv_addr "slave device 7bit address"
- * \retval	E_OK	Open successfully without any issues
- * \retval	E_OPNED	If device was opened before with different parameters,
- *			then just increase the \ref dev_iic_info::opn_cnt "opn_cnt" and return \ref E_OPNED
- * \retval	E_OBJ	Device object is not valid
- * \retval	E_SYS	Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first.
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_NOSPT	Open settings are not supported
- */
-
-/**
- * \fn		int32_t (* dev_iic::iic_close) (void)
- * \details	close an iic device, just decrease the \ref dev_iic_info::opn_cnt "opn_cnt",
- *      if \ref dev_iic_info::opn_cnt "opn_cnt" equals 0, then close the device
- * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
- * \retval	E_OPNED	Device is still opened, the device \ref dev_iic_info::opn_cnt "opn_cnt" decreased by 1
- * \retval	E_OBJ	Device object is not valid
- */
-
-/**
- * \fn		int32_t (* dev_iic::iic_control) (uint32_t ctrl_cmd, void *param)
- * \details	control an iic device by \ref ctrl_cmd, with passed \ref param.
- * 	you can control iic device using predefined iic control commands defined using \ref DEV_SET_SYSCMD
- * 	(which must be implemented by bsp developer), such as \ref IIC_CMD_SET_SPEED "set iic speed mode",
- * 	\ref IIC_CMD_FLUSH_TX "flush tx" and \ref DEVICE_HAL_IIC_CTRLCMD "more".
- * 	And you can also control iic device using your own specified commands defined using \ref DEV_SET_USRCMD,
- * 	but these specified commands should be defined in your own iic device driver implementation.
- * \param[in]		ctrl_cmd	\ref DEVICE_HAL_IIC_CTRLCMD "control command", to change or get some thing related to iic
- * \param[in,out]	param		parameters that maybe argument of the command,
- * 					or return values of the command, must not be NULL
- * \retval	E_OK	Control device successfully
- * \retval	E_CLSED	Device is not opened
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
- * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
- * \retval	E_NOSPT	Control command is not supported or not valid
- */
-
-/**
- * \fn		int32_t (* dev_iic::iic_write) (const void *data, uint32_t len)
- * \details	send \ref data through iic with defined \ref len to slave device which slave address is \ref slv_addr.
- * \param[in]	data	pointer to data need to send by iic
- * \param[in]	len	length of data to be sent
- * \retval	>0	Byte count that was successfully sent for poll method,
- * 			it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state".
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_CTX	Device is still in transfer state
- * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
- */
-
-/**
- * \fn		int32_t (* dev_iic::iic_read) (void *data, uint32_t len)
- * \details	receive \ref data of defined \ref len through iic from slave device which slave address is \ref slv_addr.
- * \param[out]	data	pointer to data need to received by iic
- * \param[in]	len	length of data to be received
- * \retval	>0	Byte count that was successfully received for poll method,
- * 			it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state".
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_CTX	Device is still in transfer state
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
- */
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief	get an \ref dev_iic "iic device" by iic device id.
- * 	For how to use iic device hal refer to \ref DEVICE_HAL_IIC_DEVSTRUCT "Functions in iic device structure"
- * \param[in]	iic_id	id of iic, defined by user
- * \retval	!NULL	pointer to an \ref dev_iic "iic device structure"
- * \retval	NULL	failed to find the iic device by \ref iic_id
- * \note	need to implemented by user in user code
- */
-extern DEV_IIC_PTR iic_get_dev(int32_t iic_id);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-#endif /* _DEVICE_HAL_IIC_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h
deleted file mode 100644
index 4469654e54..0000000000
--- a/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h
+++ /dev/null
@@ -1,577 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-06-16
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_HAL_SPI	SPI Device HAL Interface
- * \ingroup	DEVICE_HAL_DEF
- * \brief	definitions for spi device hardware layer (\ref dev_spi.h)
- * \details	provide interfaces for spi driver to implement
- *  Here is a diagram for the spi interface.
- *
- *  \htmlonly
- *  <div class="imagebox">
- *      <div style="width: 600px">
- *          <img src="pic/dev_spi_hal.jpg" alt="SPI Device HAL Interface Diagram"/>
- *          <p>SPI Device HAL Interface Diagram</p>
- *      </div>
- *  </div>
- *  \endhtmlonly
- *
- * @{
- *
- * \file
- * \brief	spi device hardware layer definitions
- * \details	provide common definitions for spi device,
- * 	then software developer can develop spi driver
- * 	following this definitions, and the applications
- * 	can directly call this definition to realize functions
- */
-
-#ifndef _DEVICE_HAL_SPI_H_
-#define _DEVICE_HAL_SPI_H_
-
-#include "device/device_hal/inc/dev_common.h"
-
-
-/**
- * \defgroup	DEVICE_HAL_SPI_CTRLCMD		SPI Device Control Commands
- * \ingroup	DEVICE_HAL_SPI
- * \brief	Definitions for spi control command, used in \ref dev_spi::spi_control "SPI IO Control"
- * \details	These commands defined here can be used in user code directly.
- * - Parameters Usage
- *   - For passing parameters like integer, just use uint32_t/int32_t to directly pass values
- *   - For passing parameters for a structure, please use pointer to pass values
- *   - For getting some data, please use pointer to store the return data
- * - Common Return Values
- *   - \ref E_OK,	Control device successfully
- *   - \ref E_CLSED,	Device is not opened
- *   - \ref E_OBJ,	Device object is not valid or not exists
- *   - \ref E_PAR,	Parameter is not valid for current control command
- *   - \ref E_SYS,	Control device failed, due to hardware issues such as device is disabled
- *   - \ref E_CTX,	Control device failed, due to different reasons like in transfer state
- *   - \ref E_NOSPT,	Control command is not supported or not valid
- * - Usage Comment
- *   - For SPI poll or interrupt read/write/transfer operations, only 1 operation can be triggered.
- *     If there is a operation is running, any other operation will return \ref E_CTX
- *   - If SPI is in transfer, then the following operations may return \ref E_CTX. Like
- *     \ref SPI_CMD_SET_CLK_MODE, \ref SPI_CMD_SET_TXINT_BUF, \ref SPI_CMD_SET_RXINT_BUF,
- *     \ref SPI_CMD_SET_TXINT, \ref SPI_CMD_SET_RXINT, \ref SPI_CMD_ABORT_TX, \ref SPI_CMD_ABORT_RX,
- *     \ref SPI_CMD_FLUSH_TX, \ref SPI_CMD_FLUSH_RX, \ref SPI_CMD_SET_DFS, \ref SPI_CMD_TRANSFER_POLLING,
- *     \ref SPI_CMD_TRANSFER_INT, \ref SPI_CMD_ABORT_XFER, \ref SPI_CMD_MST_SEL_DEV, \ref SPI_CMD_MST_DSEL_DEV,
- *     \ref SPI_CMD_MST_SET_FREQ and \ref dev_spi::spi_write "SPI Poll Write" or \ref dev_spi::spi_read "SPI Poll Read".
- * @{
- */
-
-/** Define SPI control commands for common usage */
-#define DEV_SET_SPI_SYSCMD(cmd)		DEV_SET_SYSCMD((cmd))
-/** Define SPI control commands for master usage */
-#define DEV_SET_SPI_MST_SYSCMD(cmd)	DEV_SET_SYSCMD(0x00001000|(cmd))
-/** Define SPI control commands for slave usage */
-#define DEV_SET_SPI_SLV_SYSCMD(cmd)	DEV_SET_SYSCMD(0x00002000|(cmd))
-
-
-/* ++++ Common commands for SPI Device ++++ */
-/**
- * Get \ref dev_spi_info::status "current device status"
- * - Param type : uint32_t *
- * - Param usage : store result of current status
- * - Return value explanation :
- */
-#define SPI_CMD_GET_STATUS			DEV_SET_SPI_SYSCMD(0)
-/**
- * set the \ref dev_spi_info::clk_mode "clock mode" of spi transfer
- * - Param type : uint32_t
- * - Param usage : spi clock mode to choose clock phase and clock polarity
- * - Return value explanation :
- */
-#define SPI_CMD_SET_CLK_MODE			DEV_SET_SPI_SYSCMD(1)
-/**
- * set spi \ref dev_spi_info::dfs "data frame size"
- * - Param type : uint32_t
- * - Param usage : should > 0
- * - Return value explanation : If dfs is not supported, then return \ref E_SYS
- */
-#define SPI_CMD_SET_DFS				DEV_SET_SPI_SYSCMD(2)
-/**
- * set the \ref dev_spi_info::dummy "dummy data" during spi transfer
- * - Param type : uint32_t
- * - Param usage : dummy data to transfer
- * - Return value explanation :
- */
-#define SPI_CMD_SET_DUMMY_DATA			DEV_SET_SPI_SYSCMD(3)
-/**
- * Set \ref dev_spi_cbs::tx_cb "spi transmit success callback" function
- * when all required bytes are transmitted for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : transmit success callback function for spi
- * - Return value explanation :
- */
-#define SPI_CMD_SET_TXCB			DEV_SET_SPI_SYSCMD(4)
-/**
- * Set \ref dev_spi_cbs::rx_cb "spi receive success callback" function
- * when all required bytes are received for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : receive success callback function for spi
- * - Return value explanation :
- */
-#define SPI_CMD_SET_RXCB			DEV_SET_SPI_SYSCMD(5)
-/**
- * Set \ref dev_spi_cbs::xfer_cb "spi transfer success callback" function
- * when all required transfer are done for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : transfer success callback function for spi
- * - Return value explanation :
- */
-#define SPI_CMD_SET_XFERCB			DEV_SET_SPI_SYSCMD(6)
-/**
- * Set \ref dev_spi_cbs::err_cb "spi transfer error callback" function
- * when something error happened for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : transfer error callback function for spi
- * - Return value explanation :
- */
-#define SPI_CMD_SET_ERRCB			DEV_SET_SPI_SYSCMD(7)
-/**
- * Set buffer in interrupt transmit, and it will set \ref dev_spi_info::xfer "spi tranfer".
- * - SPI master and slave mode use case  \n
- *    For both master and slave mode, if you set tx buffer to NULL, when tx interrupt is enabled and entered into tx interrupt,
- * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the
- * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt
- * and call tx callback function if available.
- * - Param type : DEV_BUFFER * or NULL
- * - Param usage : buffer structure pointer, if param is NULL, then it will set xfer to empty
- * - Return value explanation :
- */
-#define SPI_CMD_SET_TXINT_BUF			DEV_SET_SPI_SYSCMD(8)
-/**
- * Set buffer in interrupt receive, and it will set \ref dev_spi_info::xfer "spi tranfer".
- * - SPI master mode use case  \n
- *   Similar to \ref SPI_CMD_SET_TXINT_BUF
- * - SPI slave mode use case   \n
- *   Similiar to \ref SPI_CMD_SET_TXINT_BUF
- * - Param type : DEV_BUFFER * or NULL
- * - Param usage : buffer structure pointer, if param is NULL, then it will set xfer to empty
- * - Return value explanation :
- */
-#define SPI_CMD_SET_RXINT_BUF			DEV_SET_SPI_SYSCMD(9)
-/**
- * Enable or disable transmit interrupt,
- * for master mode, only one of tx and rx interrupt can be enabled,
- * if tx interrupt is enabled, then rx interrupt can't be enabled.
- * - Param type : uint32_t
- * - Param usage : enable(none-zero) or disable(zero) flag
- * - Return value explanation :
- */
-#define SPI_CMD_SET_TXINT			DEV_SET_SPI_SYSCMD(10)
-/**
- * Enable or disable receive interrupt,
- * for master mode, only one of tx and rx interrupt can be enabled,
- * if rx interrupt is enabled, then tx interrupt can't be enabled.
- * - Param type : uint32_t
- * - Param usage : enable(none-zero) or disable(zero) flag
- * - Return value explanation :
- */
-#define SPI_CMD_SET_RXINT			DEV_SET_SPI_SYSCMD(11)
-/**
- * start the transfer by polling
- * - Param type : \ref DEV_SPI_TRANSFER *
- * - Param usage :
- * - Return value explanation :
- */
-#define SPI_CMD_TRANSFER_POLLING		DEV_SET_SPI_SYSCMD(12)
-/**
- * start the transfer by interrupt
- * - Param type : \ref DEV_SPI_TRANSFER * or NULL
- * - Param usage : If NULL, it will disable transfer interrupt, if not NULL, it will enable transfer interrupt
- * - Return value explanation :
- */
-#define SPI_CMD_TRANSFER_INT			DEV_SET_SPI_SYSCMD(13)
-/**
- * Abort current interrupt transmit operation if tx interrupt enabled,
- * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT
- * in \ref dev_spi_info::status "status" variable,
- * and call the transmit callback function, when tx callback is finished,
- * it will clear \ref DEV_IN_TX_ABRT and return
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define SPI_CMD_ABORT_TX			DEV_SET_SPI_SYSCMD(14)
-/**
- * Abort current interrupt receive operation if rx interrupt enabled,
- * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT
- * in \ref dev_spi_info::status "status" variable,
- * and call the receive callback function, when rx callback is finished,
- * it will clear \ref DEV_IN_TX_ABRT and return
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define SPI_CMD_ABORT_RX			DEV_SET_SPI_SYSCMD(15)
-/**
- * Abort current interrupt transfer operation if transfer is issued,
- * it will disable transfer interrupt, and set \ref DEV_IN_XFER_ABRT
- * in \ref dev_spi_info::status "status" variable,
- * and call the transfer callback function, when xfer callback is finished,
- * it will clear \ref DEV_IN_XFER_ABRT and return
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define SPI_CMD_ABORT_XFER			DEV_SET_SPI_SYSCMD(16)
-/**
- * Do a software reset for SPI device, it will stop current transfer,
- * and clear error state and bring device to normal state, set next condition to STOP
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define SPI_CMD_RESET				DEV_SET_SPI_SYSCMD(17)
-/**
- * Flush spi tx fifo, this will clear the data in tx fifo
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define SPI_CMD_FLUSH_TX			DEV_SET_SPI_SYSCMD(18)
-/**
- * Flush spi rx fifo, this will clear the data in rx fifo
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define SPI_CMD_FLUSH_RX			DEV_SET_SPI_SYSCMD(19)
-/**
- * Enable spi device
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define SPI_CMD_ENA_DEV				DEV_SET_SPI_SYSCMD(20)
-/**
- * Disable spi device, when device is disabled,
- * only \ref SPI_CMD_ENA_DEV, \ref SPI_CMD_DIS_DEV,
- * \ref SPI_CMD_GET_STATUS and \ref SPI_CMD_RESET
- * commands can be executed, other commands will return \ref E_SYS
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define SPI_CMD_DIS_DEV				DEV_SET_SPI_SYSCMD(21)
-/**
- * Get how many bytes space in spi are available to transmit,
- * this can be used in interrupt callback functions,
- * cooperate with \ref dev_spi::spi_write "spi_write" API to realize non-blocked write
- * - Param type : int32_t *
- * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available
- * - Return value explanation :
- */
-#define SPI_CMD_GET_TXAVAIL			DEV_SET_SPI_SYSCMD(22)
-/**
- * Get how many bytes in spi are available to receive,
- * this can be used in interrupt callback functions,
- * cooperate with \ref dev_spi::spi_read "spi_read" API to realize non-blocked read
- * - Param type : int32_t *
- * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available
- * - Return value explanation :
- */
-#define SPI_CMD_GET_RXAVAIL			DEV_SET_SPI_SYSCMD(23)
-
-
-/* ++++ Master only commands for SPI Device ++++ */
-/**
- *  select spi slave device
- * - Param type : uint32_t
- * - Param usage : the number of spi slave device to select
- * - Return value explanation : return \ref E_SYS when selection can't be done, return \ref E_CTX during transfer
- */
-#define SPI_CMD_MST_SEL_DEV			DEV_SET_SPI_MST_SYSCMD(0)
-/**
- *  de-select spi slave device
- * - Param type : uint32_t
- * - Param usage : the number of spi slave device to de-select
- * - Return value explanation : return \ref E_SYS when selection can't be done, return \ref E_CTX during transfer
- */
-#define SPI_CMD_MST_DSEL_DEV			DEV_SET_SPI_MST_SYSCMD(1)
- /**
- * Set \ref dev_spi_info::freq "spi frequency".
- * - Param type : uint32_t
- * - Param usage : spi freq
- * - Return value explanation : no return
- */
-#define SPI_CMD_MST_SET_FREQ			DEV_SET_SPI_MST_SYSCMD(2)
-
-
-/* ++++ Slave only commands for SPI Device ++++ */
-
-/* \todo add spi slave related CMDs */
-
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_SPI_CALLBACK	SPI Interrupt callback functions
- * \ingroup	DEVICE_HAL_SPI
- * \brief	callback function structure for SPI device
- * @{
- */
-typedef struct dev_spi_cbs {
-	DEV_CALLBACK tx_cb;	/*!< spi data transmit success required bytes callback */
-	DEV_CALLBACK rx_cb;	/*!< spi data receive success required bytes callback */
-	DEV_CALLBACK err_cb;	/*!< spi error callback */
-	DEV_CALLBACK xfer_cb;	/*!< transfer callback */
-} DEV_SPI_CBS, *DEV_SPI_CBS_PTR;
-/** @} */
-
-/** SPI Clock Mode */
-typedef enum spi_clk_mode {
-	SPI_CPOL_0_CPHA_0 = 0,	/*!< Inactive state of serial clock is low, serial clock toggles in middle of first data bit */
-	SPI_CPOL_0_CPHA_1 = 1,	/*!< Inactive state of serial clock is low, serial clock toggles at start of first data bit  */
-	SPI_CPOL_1_CPHA_0 = 2,	/*!< Inactive state of serial clock is high, serial clock toggles in middle of first data bit */
-	SPI_CPOL_1_CPHA_1 = 3,	/*!< Inactive state of serial clock is high, serial clock toggles at start of first data bit */
-
-	SPI_CLK_MODE_0    = SPI_CPOL_0_CPHA_0,	/*!< Equal to \ref SPI_CPOL_0_CPHA_0 */
-	SPI_CLK_MODE_1    = SPI_CPOL_0_CPHA_1,	/*!< Equal to \ref SPI_CPOL_0_CPHA_1 */
-	SPI_CLK_MODE_2    = SPI_CPOL_1_CPHA_0,	/*!< Equal to \ref SPI_CPOL_1_CPHA_0 */
-	SPI_CLK_MODE_3    = SPI_CPOL_1_CPHA_1	/*!< Equal to \ref SPI_CPOL_1_CPHA_1 */
-} SPI_CLK_MODE;
-
-#define SPI_CLK_MODE_DEFAULT	SPI_CPOL_0_CPHA_0	/*!< Default SPI device clock mode */
-
-/**
- * \defgroup	DEVICE_HAL_SPI_DEVSTRUCT	SPI Device Structure
- * \ingroup	DEVICE_HAL_SPI
- * \brief	contains definitions of spi device structure.
- * \details	this structure will be used in user implemented code, which was called
- * 	Device Driver Implement Layer for spi to realize in user code.
- * @{
- */
-typedef struct dev_spi_transfer DEV_SPI_TRANSFER, *DEV_SPI_TRANSFER_PTR;
-/**
- * \brief	spi read and write data structure used by \ref SPI_CMD_TRANSFER
- * 	spi write then read data
- *
- */
-struct dev_spi_transfer {
-	DEV_SPI_TRANSFER *next;
-	/* Calc by software */
-	/** tot_len = (tx_totlen>rx_totlen)?tx_totlen:rx_totlen */
-	uint32_t tot_len;
-	/* Set by user */
-	uint8_t *tx_buf;
-	uint32_t tx_ofs;
-	uint32_t tx_len;
-	uint8_t *rx_buf;
-	uint32_t rx_ofs;
-	uint32_t rx_len;
-	/* Should auto set to proper value during set buffer value */
-	uint32_t tx_idx;
-	uint32_t tx_totlen;	/** tx_totlen = tx_len + tx_ofs */
-	uint32_t rx_idx;
-	uint32_t rx_totlen;	/** rx_totlen = rx_len + rx_ofs */
-};
-
-/** Set tx buffer of device spi transfer */
-#define DEV_SPI_XFER_SET_TXBUF(xfer, buf, ofs, len)		{		\
-					(xfer)->tx_buf = (uint8_t *)(buf);	\
-					(xfer)->tx_len = (uint32_t)(len);	\
-					(xfer)->tx_ofs = (uint32_t)(ofs);	\
-					(xfer)->tx_idx = 0;			\
-					(xfer)->tx_totlen = ( (uint32_t)(len) 	\
-							+ (uint32_t)(ofs) ) ;	\
-				}
-
-/** Set rx buffer of device spi transfer */
-#define DEV_SPI_XFER_SET_RXBUF(xfer, buf, ofs, len)		{		\
-					(xfer)->rx_buf = (uint8_t *)(buf);	\
-					(xfer)->rx_len = (uint32_t)(len);	\
-					(xfer)->rx_ofs = (uint32_t)(ofs);	\
-					(xfer)->rx_idx = 0;			\
-					(xfer)->rx_totlen = ( (uint32_t)(len) 	\
-							+ (uint32_t)(ofs) ) ;	\
-				}
-
-/** Calculate total length of current transfer without next transfer */
-#define DEV_SPI_XFER_CALC_TOTLEN(xfer)		(xfer)->tot_len =	\
-				((xfer)->tx_totlen > (xfer)->rx_totlen) ? (xfer)->tx_totlen : (xfer)->rx_totlen ;
-
-/** Set next SPI transfer */
-#define DEV_SPI_XFER_SET_NEXT(xfer, next_xfer)	(xfer)->next = (next_xfer);
-
-/** Init spi transfer */
-#define DEV_SPI_XFER_INIT(xfer)					{		\
-					(xfer)->tx_idx = 0;			\
-					(xfer)->rx_idx = 0;			\
-					(xfer)->tx_totlen = ((xfer)->tx_len  	\
-							+ (xfer)->tx_ofs) ;	\
-					(xfer)->rx_totlen = ((xfer)->rx_len  	\
-							+ (xfer)->rx_ofs) ;	\
-					DEV_SPI_XFER_CALC_TOTLEN(xfer);		\
-				}
-/**
- * \brief	spi information struct definition
- * \details	informations about spi open state, working state,
- * 	frequency, spi registers, working method, interrupt number
- */
-typedef struct dev_spi_info {
-	void *spi_ctrl;		/*!< spi control related */
-	uint32_t status;	/*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */
-	uint32_t freq;		/*!< spi working baudrate */
-	uint8_t mode;		/*!< spi working mode (master/slave) */
-	uint8_t clk_mode;	/*!< spi clock phase and polarity, this should be \ref SPI_CLK_MODE_DEFAULT for first open */
-	uint8_t opn_cnt;	/*!< spi open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */
-	uint8_t slave;		/*!< current selected slave device no, start from 0, this should be \ref SPI_SLAVE_NOT_SELECTED for first open */
-	uint8_t dfs;		/*!< data frame size, this should be \ref SPI_DFS_DEFAULT for first open */
-
-	DEV_SPI_TRANSFER xfer;	/*!< spi transfer, this should be set to all zero for first open */
-	DEV_SPI_CBS spi_cbs;	/*!< spi callbacks, for both master and slave mode, this should be all NULL for first open */
-	void *extra;		/*!< a extra pointer to get hook to applications which should not used by bsp developer,
-					this should be NULL for first open and you can \ref DEV_SPI_INFO_SET_EXTRA_OBJECT "set"
-					or \ref DEV_SPI_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */
-	uint32_t dummy;		/*!< dummy write data when send and receive, this should be \ref SPI_DUMMY_DEFAULT for first open */
-} DEV_SPI_INFO, * DEV_SPI_INFO_PTR;
-
-/** Set extra information pointer of spi info */
-#define DEV_SPI_INFO_SET_EXTRA_OBJECT(spi_info_ptr, extra_info)		(spi_info_ptr)->extra = (void *)(extra_info)
-/** Get extra information pointer of spi info */
-#define DEV_SPI_INFO_GET_EXTRA_OBJECT(spi_info_ptr)			((spi_info_ptr)->extra)
-
-#define SPI_DFS_DEFAULT				8		/*!< Default spi data frame size */
-#define SPI_SLAVE_NOT_SELECTED			(0xFF)		/*!< Slave is not selected */
-#define SPI_DUMMY_DEFAULT			(0xFF)		/*!< default dummy value for first open */
-
-/**
- * \brief	spi device interface definition
- * \details	define spi device interface, like spi information structure,
- * 	fuctions to get spi info, open/close/control spi, send/receive data by spi
- * \note	all this details are implemented by user in user porting code
- */
-typedef struct dev_spi {
-	DEV_SPI_INFO spi_info;						/*!< spi device information */
-	int32_t (*spi_open) (uint32_t mode, uint32_t param);		/*!< open spi device in master/slave mode, \
-									when in master mode, param stands for frequency, \
-									when in slave mode, param stands for clock mode */
-	int32_t (*spi_close) (void);					/*!< close spi device */
-	int32_t (*spi_control) (uint32_t ctrl_cmd, void *param);	/*!< control spi device */
-	int32_t (*spi_write) (const void *data, uint32_t len);		/*!< send data to spi device (blocking method) */
-	int32_t (*spi_read) (void *data, uint32_t len);			/*!< read data from spi device (blocking method) */
-} DEV_SPI, * DEV_SPI_PTR;
-
-/**
- * \fn		int32_t (* dev_spi::spi_open) (uint32_t mode, uint32_t param)
- * \details	open an spi device with selected mode (master or slave) with defined \ref param
- * \param[in]	mode	working mode (\ref DEV_MASTER_MODE "master" or \ref DEV_SLAVE_MODE "slave")
- * \param[in]	param	When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_spi_info::freq "frequency",
- * 			when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_spi_info::clk_mode "slave clock mode"
- * \retval	E_OK	Open successfully without any issues
- * \retval	E_OPNED	If device was opened before with different parameters,
- *			then just increase the \ref dev_spi_info::opn_cnt "opn_cnt" and return \ref E_OPNED
- * \retval	E_OBJ	Device object is not valid
- * \retval	E_SYS	Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first.
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_NOSPT	Open settings are not supported
- */
-
-/**
- * \fn		int32_t (* dev_spi::spi_close) (void)
- * \details	close an spi device, just decrease the \ref dev_spi_info::opn_cnt "opn_cnt",
- *      if \ref dev_spi_info::opn_cnt "opn_cnt" equals 0, then close the device
- * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
- * \retval	E_OPNED	Device is still opened, the device \ref dev_spi_info::opn_cnt "opn_cnt" decreased by 1
- * \retval	E_OBJ	Device object is not valid
- */
-
-/**
- * \fn		int32_t (* dev_spi::spi_control) (uint32_t ctrl_cmd, void *param)
- * \details	control an spi device by \ref ctrl_cmd, with passed \ref param.
- * 	you can control spi device using predefined spi control commands defined using \ref DEV_SET_SYSCMD
- * 	(which must be implemented by bsp developer), such as \ref SPI_CMD_MST_SET_FREQ "set spi master frequency",
- * 	\ref SPI_CMD_FLUSH_TX "flush tx" and \ref DEVICE_HAL_SPI_CTRLCMD "more".
- * 	And you can also control spi device using your own specified commands defined using \ref DEV_SET_USRCMD,
- * 	but these specified commands should be defined in your own spi device driver implementation.
- * \param[in]		ctrl_cmd	\ref DEVICE_HAL_SPI_CTRLCMD "control command", to change or get some thing related to spi
- * \param[in,out]	param		parameters that maybe argument of the command,
- * 					or return values of the command, must not be NULL
- * \retval	E_OK	Control device successfully
- * \retval	E_CLSED	Device is not opened
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
- * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
- * \retval	E_NOSPT	Control command is not supported or not valid
- */
-
-/**
- * \fn		int32_t (* dev_spi::spi_write) (const void *data, uint32_t len)
- * \details	send \ref data through spi with defined \ref len to slave device .
- * \param[in]	data	pointer to data need to send by spi
- * \param[in]	len	length of data to be sent
- * \retval	>0	Byte count that was successfully sent for poll method
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_CTX	Device is still in transfer state
- * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
- */
-
-/**
- * \fn		int32_t (* dev_spi::spi_read) (void *data, uint32_t len)
- * \details	receive \ref data of defined \ref len through spi from slave device .
- * \param[out]	data	pointer to data need to received by spi
- * \param[in]	len	length of data to be received
- * \retval	>0	Byte count that was successfully received for poll method
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_CTX	Device is still in transfer state
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
- */
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief	get an \ref dev_spi "spi device" by spi device id.
- * 	For how to use spi device hal refer to \ref dev_spi "Functions in spi device structure"
- * \param[in]	spi_id	id of spi, defined by user
- * \retval	!NULL	pointer to an \ref dev_spi "spi device structure"
- * \retval	NULL	failed to find the spi device by \ref spi_id
- * \note	need to implemented by user in user code
- */
-extern DEV_SPI_PTR spi_get_dev(int32_t spi_id);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-#endif /* _DEVICE_HAL_SPI_H_ */
diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h
deleted file mode 100644
index c8e17d6421..0000000000
--- a/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h
+++ /dev/null
@@ -1,475 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-16
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \defgroup	DEVICE_HAL_UART		UART Device HAL Interface
- * \ingroup	DEVICE_HAL_DEF
- * \brief	Definitions for uart device hardware layer (\ref dev_uart.h)
- * \details	Provide unified APIs for uart driver to implement.
- *  Here is a diagram for the uart interface.
- *
- *  \htmlonly
- *  <div class="imagebox">
- *      <div style="width: 600px">
- *          <img src="pic/dev_uart_hal.jpg" alt="UART Device HAL Interface Diagram"/>
- *          <p>UART Device HAL Interface Diagram</p>
- *      </div>
- *  </div>
- *  \endhtmlonly
- *
- * ### Reference Links
- *     * [Serial Port](https://en.wikipedia.org/wiki/Serial_port)
- *
- * @{6
- *
- * \file
- * \brief	uart device hardware layer definitions
- * \details	Provide common definitions for uart device,
- * 	then software developer can develop uart driver
- * 	following this definitions, and the applications
- * 	can directly call this definition to realize functions
- *
- */
-
-#ifndef _DEVICE_HAL_UART_H_
-#define _DEVICE_HAL_UART_H_
-
-#include "device/device_hal/inc/dev_common.h"
-
-/**
- * \defgroup	DEVICE_HAL_UART_BAUD	UART Device Baudrate Definitions
- * \ingroup	DEVICE_HAL_UART
- * \brief	Macros for uart baudrate.
- * \details	Definitions for baudrate from 4800 to 115200bps.
- * @{
- */
-/*
- * defines for uart baudrates
- */
-#define UART_BAUDRATE_110			(110)		/*!< uart baudrate 110bps */
-#define UART_BAUDRATE_300			(300)		/*!< uart baudrate 300bps */
-#define UART_BAUDRATE_600			(600)		/*!< uart baudrate 600bps */
-#define UART_BAUDRATE_1200			(1200)		/*!< uart baudrate 1200bps */
-#define UART_BAUDRATE_2400			(2400)		/*!< uart baudrate 2400bps */
-#define UART_BAUDRATE_4800			(4800)		/*!< uart baudrate 4800bps */
-#define UART_BAUDRATE_9600			(9600)		/*!< uart baudrate 9600bps */
-#define UART_BAUDRATE_14400			(14400)		/*!< uart baudrate 14400bps */
-#define UART_BAUDRATE_19200			(19200)		/*!< uart baudrate 19200bps */
-#define UART_BAUDRATE_38400			(38400)		/*!< uart baudrate 38400bps */
-#define UART_BAUDRATE_57600			(57600)		/*!< uart baudrate 57600bps */
-#define UART_BAUDRATE_115200			(115200)	/*!< uart baudrate 115200bps */
-#define UART_BAUDRATE_230400			(230400)	/*!< uart baudrate 230400bps */
-#define UART_BAUDRATE_460800			(460800)	/*!< uart baudrate 460800bps */
-#define UART_BAUDRATE_921600			(921600)	/*!< uart baudrate 921600bps */
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_UART_FORMAT	UART Device Format Definitions
- * \ingroup	DEVICE_HAL_UART
- * \brief	Macros for uart format.
- * \details	Definitions for uart format like databits, parity, stopbits.
- * @{
- */
-/**
- * UART Device Parity Types Enum
- */
-typedef enum {
-	UART_PARITY_NONE  = 0,	/*!< no parity bit */
-	UART_PARITY_ODD   = 1,	/*!< odd parity bit */
-	UART_PARITY_EVEN  = 2,	/*!< even parity bit */
-	UART_PARITY_MARK  = 3,	/*!< mark parity bit, always logical 1 */
-	UART_PARITY_SPACE = 4	/*!< space parity bit, always logical 0 */
-} UART_PARITY;
-
-/**
- * UART Device Stop Bits Enum
- */
-typedef enum {
-	UART_STPBITS_ONE     = 0,	/*!< 1 stop bit */
-	UART_STPBITS_ONEHALF = 1,	/*!< 1.5 stop bits */
-	UART_STPBITS_TWO     = 2	/*!< 2 stop bits */
-} UART_STOPBITS;
-
-/**
- * UART DPS Format: databits/parity/stopbits
- */
-typedef struct uart_dps_format {
-	uint32_t databits;	/*!< data bits */
-	UART_PARITY parity;	/*!< parity bit type */
-	UART_STOPBITS stopbits;	/*!< stop bits */
-} UART_DPS_FORMAT;
-
-#define UART_DATABITS_DEFAULT	8	/*!< default data bits */
-
-/** Default UART DPS format */
-static const UART_DPS_FORMAT dps_format_default = {UART_DATABITS_DEFAULT, UART_PARITY_NONE, UART_STPBITS_ONE};
-/** @} */
-
-/**
- * UART Device Hardware Flow Control Types Enum
- */
-typedef enum {
-	UART_FC_NONE = 0,	/*!< Non hardware flow control */
-	UART_FC_RTS  = 1,	/*!< Request To Send */
-	UART_FC_CTS  = 2,	/*!< Clear To Send */
-	UART_FC_BOTH = 3	/*!< Both hardware flow control methods */
-} UART_HW_FLOW_CONTROL;
-/** Default hardware flow control method */
-static const UART_HW_FLOW_CONTROL hwfc_default = UART_FC_NONE;
-
-/**
- * \defgroup	DEVICE_HAL_UART_CTRLCMD		UART Device Control Commands
- * \ingroup	DEVICE_HAL_UART
- * \brief	Definitions for uart control command, used in \ref dev_uart::uart_control "UART IO Control"
- * \details	These commands defined here can be used in user code directly.
- * - Parameters Usage
- *   - For passing parameters like integer, just use uint32_t/int32_t to directly pass values
- *   - For passing parameters for a structure, please use pointer to pass values
- *   - For getting some data, please use pointer to store the return data
- * - Common Return Values
- *   - \ref E_OK,	Control device successfully
- *   - \ref E_CLSED,	Device is not opened
- *   - \ref E_OBJ,	Device object is not valid or not exists
- *   - \ref E_PAR,	Parameter is not valid for current control command
- *   - \ref E_SYS,	Control device failed, due to hardware issues such as device is disabled
- *   - \ref E_CTX,	Control device failed, due to different reasons like in transfer state
- *   - \ref E_NOSPT,	Control command is not supported or not valid
- * @{
- */
-/**
- * Set \ref dev_uart_info::baudrate "uart baudrate".
- * - Param type : uint32_t
- * - Param usage : uart baudrate, must above zero. Here is a list of \ref DEVICE_HAL_UART_BAUD "possible baudrates"
- * - Return value explanation :
- */
-#define UART_CMD_SET_BAUD			DEV_SET_SYSCMD(0)
-/**
- * Get \ref dev_uart_info::status "current device status"
- * - Param type : uint32_t *
- * - Param usage : store result of current status
- * - Return value explanation :
- */
-#define UART_CMD_GET_STATUS			DEV_SET_SYSCMD(1)
-/**
- * Enable uart device
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define UART_CMD_ENA_DEV			DEV_SET_SYSCMD(2)
-/**
- * Disable uart device, when device is disabled,
- * only \ref UART_CMD_ENA_DEV, \ref UART_CMD_DIS_DEV and
- * \ref UART_CMD_GET_STATUS commands can be executed,
- * other commands will return \ref E_SYS
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define UART_CMD_DIS_DEV			DEV_SET_SYSCMD(3)
-/**
- * Flush uart device output
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define UART_CMD_FLUSH_OUTPUT			DEV_SET_SYSCMD(4)
-/**
- * Get how many bytes space in uart are available to transmit,
- * this can be used in interrupt callback functions,
- * cooperate with \ref dev_uart::uart_write "uart_write" API to realize non-blocked write
- * - Param type : int32_t *
- * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available
- * - Return value explanation :
- */
-#define UART_CMD_GET_TXAVAIL			DEV_SET_SYSCMD(5)
-/**
- * Get how many bytes in uart are available to receive,
- * this can be used in interrupt callback functions,
- * cooperate with \ref dev_uart::uart_read "uart_read" API to realize non-blocked read
- * - Param type : int32_t *
- * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available
- * - Return value explanation :
- */
-#define UART_CMD_GET_RXAVAIL			DEV_SET_SYSCMD(6)
-/**
- * Cause a break condition to be transmitted to the receiving device
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define UART_CMD_BREAK_SET			DEV_SET_SYSCMD(7)
-/**
- * Clear break condition and return to normal
- * - Param type : NULL
- * - Param usage : param is not required
- * - Return value explanation :
- */
-#define UART_CMD_BREAK_CLR			DEV_SET_SYSCMD(8)
-/**
- * Change uart \ref dev_uart_info::dps_format "D/P/S(Data/Parity/Stop) format"
- * - Param type : \ref UART_DPS_FORMAT *
- * - Param usage : uart dps format including databits, parity and stopbits
- * - Return value explanation :
- */
-#define UART_CMD_SET_DPS_FORMAT			DEV_SET_SYSCMD(9)
-/**
- * Set uart device \ref dev_uart_info::hwfc "hardware flow control"
- * - Param type : \ref UART_HW_FLOW_CONTROL
- * - Param usage : uart dps format including databits, parity and stopbits
- * - Return value explanation :
- */
-#define UART_CMD_SET_HWFC			DEV_SET_SYSCMD(10)
-/**
- * Set \ref dev_uart_cbs::tx_cb "uart transmit success callback" function
- * when all required bytes are transmitted for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : transmit success callback function for uart
- * - Return value explanation :
- */
-#define UART_CMD_SET_TXCB			DEV_SET_SYSCMD(11)
-/**
- * Set \ref dev_uart_cbs::rx_cb "uart receive success callback" function
- * when all required bytes are received for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : receive success callback function for uart
- * - Return value explanation :
- */
-#define UART_CMD_SET_RXCB			DEV_SET_SYSCMD(12)
-/**
- * Set \ref dev_uart_cbs::err_cb "uart transfer error callback" function
- * when something error happened for interrupt method
- * - Param type : \ref DEV_CALLBACK * or NULL
- * - Param usage : transfer error callback function for uart
- * - Return value explanation :
- */
-#define UART_CMD_SET_ERRCB			DEV_SET_SYSCMD(13)
-/**
- * Set transmit buffer via interrupt, and it will set \ref dev_uart_info::tx_buf "tx_buf"
- * - Param type : DEV_BUFFER * or NULL
- * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL
- * - Return value explanation :
- */
-#define UART_CMD_SET_TXINT_BUF			DEV_SET_SYSCMD(14)
-/**
- * Set receive buffer via interrupt, and it will set \ref dev_uart_info::rx_buf "rx_buf"
- * - Param type : DEV_BUFFER * or NULL
- * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL
- * - Return value explanation :
- */
-#define UART_CMD_SET_RXINT_BUF			DEV_SET_SYSCMD(15)
-/**
- * Enable or disable transmit interrupt
- * - Param type : uint32_t
- * - Param usage : enable(none-zero) or disable(zero) flag
- * - Return value explanation :
- */
-#define UART_CMD_SET_TXINT			DEV_SET_SYSCMD(16)
-/**
- * Enable or disable receive interrupt
- * - Param type : uint32_t
- * - Param usage : enable(none-zero) or disable(zero) flag
- * - Return value explanation :
- */
-#define UART_CMD_SET_RXINT			DEV_SET_SYSCMD(17)
-/**
- * Abort current interrupt transmit operation if tx interrupt enabled,
- * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT
- * in \ref dev_uart_info::status "status" variable,
- * and call the transmit callback function, when tx callback is finished,
- * it will clear \ref DEV_IN_TX_ABRT and return
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define UART_CMD_ABORT_TX			DEV_SET_SYSCMD(18)
-/**
- * Abort current interrupt receive operation if rx interrupt enabled,
- * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT
- * in \ref dev_uart_info::status "status" variable,
- * and call the receive callback function, when rx callback is finished,
- * it will clear \ref DEV_IN_TX_ABRT and return
- * - Param type : NULL
- * - Param usage :
- * - Return value explanation :
- */
-#define UART_CMD_ABORT_RX			DEV_SET_SYSCMD(19)
-
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_UART_CALLBACK	UART Interrupt callback functions
- * \ingroup	DEVICE_HAL_UART
- * \brief	callback function structure for UART device
- * @{
- */
-typedef struct dev_uart_cbs {
-	DEV_CALLBACK tx_cb;	/*!< uart data transmit success required bytes callback */
-	DEV_CALLBACK rx_cb;	/*!< uart data receive success required bytes callback */
-	DEV_CALLBACK err_cb;	/*!< uart error callback */
-} DEV_UART_CBS, *DEV_UART_CBS_PTR;
-/** @} */
-
-/**
- * \defgroup	DEVICE_HAL_UART_DEVSTRUCT	UART Device Interface Definition
- * \ingroup	DEVICE_HAL_UART
- * \brief	Contains definitions of uart device interface structure.
- * \details	This structure will be used in user implemented code, which was called
- *     \ref DEVICE_IMPL "Device Driver Implement Layer" for uart to use in implementation code.
- *     Application developer should use the UART API provided here to access to UART devices.
- *     BSP developer should follow the API definition to implement UART device drivers.
- * @{
- */
-/**
- * \brief	UART information struct definition
- * \details	informations about uart open count, working status,
- *     baudrate, uart registers and ctrl structure, uart dps format
- */
-typedef struct dev_uart_info {
-	void *uart_ctrl;	/*!< uart control related pointer, implemented by bsp developer, and this should be set during uart object implementation */
-	uint32_t opn_cnt;	/*!< uart open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */
-	uint32_t status;	/*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */
-	uint32_t baudrate;	/*!< uart baud rate, this should be the value of baud passing by uart_open if first successfully opened */
-	UART_DPS_FORMAT dps_format;	/*!< D/P/S format settings for uart device, here is \ref dps_format_default "default settings for first open" */
-	UART_HW_FLOW_CONTROL hwfc;	/*!< UART hardware flow control, here is \ref hwfc_default "default hardware flow control settings for first open" */
-	DEV_BUFFER tx_buf;	/*!< transmit buffer via interrupt, this should be all zero for first open */
-	DEV_BUFFER rx_buf;	/*!< receive buffer via interrupt, this should be all zero for first open */
-	DEV_UART_CBS uart_cbs;	/*!< uart callbacks, callback arguments should be \ref DEV_UART * or NULL, this should be all NULL for first open */
-	void *extra;		/*!< a extra pointer to get hook to applications which should not used by bsp developer,
-					this should be NULL for first open and you can \ref DEV_UART_INFO_SET_EXTRA_OBJECT "set"
-					or \ref DEV_UART_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */
-} DEV_UART_INFO, * DEV_UART_INFO_PTR;
-
-/** Set extra information pointer of uart info */
-#define DEV_UART_INFO_SET_EXTRA_OBJECT(uart_info_ptr, extra_info)	(uart_info_ptr)->extra = (void *)(extra_info)
-/** Get extra information pointer of uart info */
-#define DEV_UART_INFO_GET_EXTRA_OBJECT(uart_info_ptr)			((uart_info_ptr)->extra)
-
-/**
- * \brief	UART device interface definition
- * \details	Define uart device interface, like uart information structure,
- * 	provide functions to open/close/control uart, send/receive data by uart
- * \note	All this details are implemented by user in user porting code
- */
-typedef struct dev_uart {
-	DEV_UART_INFO uart_info;				/*!< UART device information */
-	int32_t (*uart_open) (uint32_t baud);			/*!< Open uart device */
-	int32_t (*uart_close) (void);				/*!< Close uart device */
-	int32_t (*uart_control) (uint32_t ctrl_cmd, void *param);	/*!< Control uart device */
-	int32_t (*uart_write) (const void *data, uint32_t len);	/*!< Send data by uart device(blocked) */
-	int32_t (*uart_read) (void *data, uint32_t len);	/*!< Read data from uart device(blocked) */
-} DEV_UART, * DEV_UART_PTR;
-
-/**
- * \fn		int32_t (* dev_uart::uart_open) (uint32_t baud)
- * \details	open an uart device with defined baudrate
- * \param[in]	baud	\ref DEVICE_HAL_UART_BAUD "initial baudrate of uart", must > 0
- * \retval	E_OK	Open successfully without any issues
- * \retval	E_OPNED	If device was opened before with different parameters,
- *			then just increase the \ref dev_uart_info::opn_cnt "opn_cnt" and return \ref E_OPNED
- * \retval	E_OBJ	Device object is not valid
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_NOSPT	Open settings are not supported
- */
-
-/**
- * \fn		int32_t (* dev_uart::uart_close) (void)
- * \details	close an uart device, just decrease the \ref dev_uart_info::opn_cnt "opn_cnt",
- *      if \ref dev_uart_info::opn_cnt "opn_cnt" equals 0, then close the device
- * \retval	E_OK	Close successfully without any issues(including scenario that device is already closed)
- * \retval	E_OPNED	Device is still opened, the device \ref dev_uart_info::opn_cnt "opn_cnt" decreased by 1
- * \retval	E_OBJ	Device object is not valid
- */
-
-/**
- * \fn		int32_t (* dev_uart::uart_control) (uint32_t ctrl_cmd, void *param)
- * \details	control an uart device by \ref ctrl_cmd, with passed \ref param.
- * 	you can control uart device using predefined uart control commands defined using \ref DEV_SET_SYSCMD
- * 	(which must be implemented by bsp developer), such as \ref UART_CMD_SET_BAUD "change baudrate",
- * 	\ref UART_CMD_FLUSH_OUTPUT "flush output" and \ref DEVICE_HAL_UART_CTRLCMD "more".
- * 	And you can also control uart device using your own specified commands defined using \ref DEV_SET_USRCMD,
- * 	but these specified commands should be defined in your own uart device driver implementation.
- * \param[in]		ctrl_cmd	\ref DEVICE_HAL_UART_CTRLCMD "control command", to change or get some thing related to uart
- * \param[in,out]	param		parameters that maybe argument of the command, or return values of the command
- * \retval	E_OK	Control device successfully
- * \retval	E_CLSED	Device is not opened
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid for current control command
- * \retval	E_SYS	Control device failed, due to hardware issues, such as device is disabled
- * \retval	E_CTX	Control device failed, due to different reasons like in transfer state
- * \retval	E_NOSPT	Control command is not supported or not valid
- */
-
-/**
- * \fn		int32_t (* dev_uart::uart_write) (const void *data, uint32_t len)
- * \details	send \ref data through uart with defined \ref len(blocked).
- * \param[in]	data	pointer to data need to send by uart, must not be NULL
- * \param[in]	len	length of data to be sent, must > 0
- * \retval	>0	Byte count that was successfully sent for poll method
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_SYS	Can't write data to hardware due to hardware issues, such as device is disabled
- */
-
-/**
- * \fn		int32_t (* dev_uart::uart_read) (void *data, uint32_t len)
- * \details	receive \ref data of defined \ref len through uart(blocked).
- * \param[out]	data	pointer to data need to received by uart, must not be NULL
- * \param[in]	len	length of data to be received, must > 0
- * \retval	>0	Byte count that was successfully received for poll method
- * \retval	E_OBJ	Device object is not valid or not exists
- * \retval	E_PAR	Parameter is not valid
- * \retval	E_SYS	Can't receive data from hardware due to hardware issues, such as device is disabled
- */
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief	get an \ref dev_uart "uart device" by uart device id.
- * 	For how to use uart device hal refer to \ref DEVICE_HAL_UART_DEVSTRUCT "Functions in uart device structure"
- * \param[in]	uart_id	id of uart, defined by user
- * \retval	!NULL	pointer to an \ref dev_uart "uart device structure"
- * \retval	NULL	failed to find the uart device by \ref uart_id
- * \note	need to implemented by user in user code
- */
-extern DEV_UART_PTR uart_get_dev(int32_t uart_id);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-#endif /* _DEVICE_HAL_UART_H_ */
diff --git a/bsp/synopsys/embarc/inc/arc/arc.h b/bsp/synopsys/embarc/inc/arc/arc.h
deleted file mode 100644
index 91c0a3850e..0000000000
--- a/bsp/synopsys/embarc/inc/arc/arc.h
+++ /dev/null
@@ -1,436 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-20
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_CORE_COMM
- * \brief  header file including common core definitions
- */
-
- /**
-  * \addtogroup ARC_HAL_CORE_COMM
-  * @{
-  */
-
-
-#ifndef _ARC_HAL_CORE_H_
-#define _ARC_HAL_CORE_H_
-
-#include "inc/arc/arc_feature_config.h"
-
-/**
- * \name exception number definitions
- * @{
- */
-
-/* ARC exception number */
-#define EXC_NO_RESET			(0)	/*!< reset vector, the entry of power up and reset */
-#define EXC_NO_MEM_ERR			(1)	/*!< external memory bus error */
-#define EXC_NO_INS_ERR			(2)	/*!< illegal instruction or illegal instruction sequence */
-#define EXC_NO_MAC_CHK			(3)	/*!< machine check error */
-#define EXC_NO_TLB_MISS_I		(4)	/*!< instruction TLB missing exception, useless without MMU */
-#define EXC_NO_TLB_MISS_D		(5)	/*!< data TLB missing exception, useless without MMU */
-#define EXC_NO_PRO_VIO			(6)	/*!< protection violation */
-#define EXC_NO_PRI_VIO			(7)	/*!< privilege violation */
-#define EXC_NO_SWI			(8)	/*!< software interrupt */
-#define EXC_NO_TRAP			(9)	/*!< trap */
-#define EXC_NO_EXT			(10)	/*!< extension exception */
-#define EXC_NO_DIV_ZER0			(11)	/*!< divide by zero */
-#define EXC_NO_DC_ERR			(12)	/*!< data cache consistency error */
-#define EXC_NO_MAL_ALIGN		(13)	/*!< misaligned data access */
-#define EXC_NO_RESERVE0			(14)	/*!< reserved */
-#define EXC_NO_RESERVE1			(15)	/*!< reserved */
-
-/* extension interrupts */
-#define EXC_NO_16			(16)	/*!< interrupt vector 16 */
-#define EXC_NO_17			(17)	/*!< interrupt vector 17 */
-#define EXC_NO_18			(18)	/*!< interrupt vector 18 */
-#define EXC_NO_19			(19)	/*!< interrupt vector 19 */
-#define EXC_NO_20			(20)	/*!< interrupt vector 20 */
-#define EXC_NO_21			(21)	/*!< interrupt vector 21 */
-#define EXC_NO_22			(22)	/*!< interrupt vector 22 */
-#define EXC_NO_23			(23)	/*!< interrupt vector 23 */
-#define EXC_NO_24			(24)	/*!< interrupt vector 24 */
-#define EXC_NO_25			(25)	/*!< interrupt vector 25 */
-#define EXC_NO_26			(26)	/*!< interrupt vector 26 */
-#define EXC_NO_27			(27)	/*!< interrupt vector 27 */
-#define EXC_NO_28			(28)	/*!< interrupt vector 28 */
-#define EXC_NO_29			(29)	/*!< interrupt vector 29 */
-#define EXC_NO_30			(30)	/*!< interrupt vector 30 */
-#define EXC_NO_31			(31)	/*!< interrupt vector 31 */
-/* ... ARC supports 255 interrupt vectors at most */
-#define EXC_NO_255			(255)	/*!< interrupt vector 255 */
-
-/** @} */
-
-/**
- * \name exception vector offset
- * @{
- */
-#define EXC_NO_TO_OFFSET(no)	(no << 2)
-
-/* ARC exception vector offset */
-#define EXC_VECTOR_RESET		(0x00)	/*!< EXC_NO_RESET offset */
-#define EXC_VECTOR_MEM_ERR		(0x04)	/*!< EXC_NO_MEM_ERR offset */
-#define EXC_VECTOR_INS_ERR		(0x08)	/*!< EXC_NO_INS_ERR offset */
-#define EXC_VECTOR_MAC_CHK		(0x0c)	/*!< EXC_NO_MAC_CHK offset */
-#define EXC_VECTOR_TLB_MISS_I		(0x10)	/*!< EXC_NO_TLB_MISS_I offset */
-#define EXC_VECTOR_TLB_MISS_D		(0x14)	/*!< EXC_NO_TLB_MISS_D offset */
-#define EXC_VECTOR_PRO_VIO		(0x18)	/*!< EXC_NO_PRO_VIO offset */
-#define EXC_VECTOR_PRI_VIO		(0x1c)	/*!< EXC_NO_PRI_VIO offset */
-#define EXC_VECTOR_SWI			(0x20)	/*!< EXC_NO_SWI offset */
-#define EXC_VECTOR_TRAP			(0x24)	/*!< EXC_NO_TRAP offset */
-#define EXC_VECTOR_EXT			(0x28)	/*!< EXC_NO_EXT offset */
-#define EXC_VECTOR_DIV_ZER0		(0x2c)	/*!< EXC_NO_DIV_ZER0 offset */
-#define EXC_VECTOR_DC_ERR		(0x30)	/*!< EXC_NO_DC_ERR offset */
-#define EXC_VECTOR_MAL_ALIGN		(0x34)	/*!< EXC_NO_MAL_ALIGN offset */
-#define EXC_VECTOR_RESERVE0		(0x38)	/*!< EXC_NO_RESERVE0 offset */
-#define EXC_VECTOR_RESERVE1		(0x3c)	/*!< EXC_NO_RESERVE1 offset */
-/** @} */
-
-/**
- * \name build configuration register
- * @{
- */
-#define AUX_BCR_VER			(0x60)	/*!< build configuration register version */
-#define AUX_BCR_BTA			(0x63)	/*!< build configuration for BTA LINK */
-#define AUX_BCR_VECBASE			(0x68)	/*!< build configuration for interrupt vector base */
-#define AUX_BCR_MPU			(0x6d)	/*!< build configuration for memory protection unit */
-#define AUX_BCR_RF			(0x6e)	/*!< build configuration for core registers */
-#define AUX_BCR_D_CACHE			(0x72)	/*!< build configuration for data cache */
-#define AUX_BCR_DCCM			(0x74)	/*!< build configuration for DCCM */
-#define AUX_BCR_TIMERS			(0x75)	/*!< build configuration for processor timers */
-#define AUX_BCR_AP 			(0x76)	/*!< build configuration for actionpoints */
-#define AUX_BCR_I_CACHE			(0x77)	/*!< build configuration for instruction cache */
-#define AUX_BCR_ICCM			(0x78)	/*!< build configuration for ICCM */
-#define AUX_BCR_DSP			(0x7a)	/*!< build configuration for DSP */
-#define AUX_BCR_MUL			(0x7b)	/*!< build configuration for multiply */
-#define AUX_BCR_SWAP			(0x7c)	/*!< build configuration for swap */
-#define AUX_BCR_NORM			(0x7d)	/*!< build configuration for normalize */
-#define AUX_BCR_MIXMAX			(0x7e)	/*!< build configuration for MIN/MAX */
-#define AUX_BCR_BARREL			(0x7f)	/*!< build configuration for barrel shift */
-#define AUX_BCR_ISA			(0xc1)	/*!< build configuration for ISA configuration */
-#define AUX_BCR_STACK			(0xc5)	/*!< build configuration for stack region */
-#define AUX_BCR_ERP			(0xc7)	/*!< build configuration for error protection */
-#define AUX_BCR_FPU			(0xc8)	/*!< build configuration for floating-point unit */
-#define AUX_BCR_CPORT			(0xc9)	/*!< build configuration for code protection */
-#define AUX_BCR_BS			(0xcb)	/*!< build configuration for bitstream */
-#define AUX_BCR_AGU			(0xcc)	/*!< build configuration for address generate unit */
-#define AUX_BCR_DMAC			(0xcd)	/*!< build configuration for DMA */
-#define AUX_BCR_CONNECT_SYSTEM		(0xd0)	/*!< build configuration for arc connect */
-#define AUX_BCR_CONNECT_SEMA		(0xd1)	/*!< build configuration for inter-core semaphore */
-#define AUX_BCR_CONNECT_MESSAGE		(0xd2)	/*!< build configuration for inter-code message */
-#define AUX_BCR_CONNECT_PMU		(0xd3)	/*!< build configuration for power management unit */
-#define AUX_BCR_CONNECT_GFRC		(0xd6)	/*!< build configuration for global free running counter */
-#define AUX_BCR_CAL_STORE		(0xd9)	/*!< build configuration for calibration parameter storage */
-#define AUX_BCR_CONNECT_ICI		(0xe0)	/*!< build configuration for inter-core interrupt unit */
-#define AUX_BCR_CONNECT_ICD		(0xe1)	/*!< build configuration for inter-core debug unit */
-#define AUX_BCR_CONNECT_PDM		(0xe3)	/*!< build configuration for power domain management unit*/
-#define AUX_BCR_RTT			(0xf2)	/*!< build configuration for real-time trace */
-#define AUX_BCR_IRQ			(0xf3)	/*!< build configuration for interrupt */
-#define AUX_BCR_PCT			(0xf5)	/*!< build configuration for performance counters */
-#define AUX_BCR_CC			(0xf6)	/*!< build configuration for performance counters */
-#define AUX_BCR_PDM_DVFS		(0xf7)	/*!< build configuration for PDM and DVFS */
-
-#define AUX_BCR_SEC_BUILD		(0xdb)
-
-/* from 0xF5 and 0xF6 */
-
-#define AUX_BCR_IFQUEUE			(0xfe)	/*!< build configuration for instruction fetch queue */
-#define AUX_BCR_SMART			(0xff)   /*!< build configuration for SmaRT debug feature */
-/** @} */
-
-
-#define	AUX_SEC_STAT			(0x9)
-#define AUX_SEC_STAT_BIT_SSC		(0)
-#define AUX_SEC_STAT_BIT_NSRT		(1)
-#define AUX_SEC_STAT_BIT_NSRU		(2)
-#define AUX_SEC_STAT_BIT_IRM		(3)
-#define AUX_SEC_STAT_BIT_SUE		(4)
-#define AUX_SEC_STAT_BIT_NIC		(5)
-
-/**
- * \name status register STATUS32
- * @{
- */
-#define AUX_STATUS32			(0xa)
-#define AUX_STATUS32_P0			(0xb)
-
-/* STATUS32 bit-field definition */
-#define AUX_STATUS_BIT_AE		(5)	/*!< processor is in an exception */
-#define AUX_STATUS_BIT_DE		(6)	/*!< delayed branch is pending */
-#define AUX_STATUS_BIT_U		(7)	/*!< user mode */
-#define AUX_STATUS_BIT_L		(12)	/*!< zero-overhead loop enable */
-#define AUX_STATUS_BIT_IE		(31)	/*!< interrupt enable */
-
-/* masks correspond to STATUS32 bit-field */
-#define AUX_STATUS_MASK_AE		(1<<AUX_STATUS_BIT_AE)	/*!< mask of AUX_STATUS_BIT_AE */
-#define AUX_STATUS_MASK_DE		(1<<AUX_STATUS_BIT_DE)	/*!< mask of AUX_STATUS_BIT_DE */
-#define AUX_STATUS_MASK_U		(1<<AUX_STATUS_BIT_U)	/*!< mask of AUX_STATUS_BIT_U */
-#define AUX_STATUS_MASK_L		(1<<AUX_STATUS_BIT_L)	/*!< mask of AUX_STATUS_BIT_L */
-#define AUX_STATUS_MASK_IE		(1<<AUX_STATUS_BIT_IE)	/*!< mask of AUX_STATUS_BIT_IE */
-/** @} */
-
-/**
- * \name zero overhead loop auxiliary register
- * @{
- */
-#define AUX_LP_START			(0x2) 	/*!< loop start address (32-bit) */
-#define AUX_LP_END			(0x3) 	/*!< loop end address (32-bit) */
-/** @} */
-
-#define AUX_USER_SP			(0xd)	/*!< user-mode stack pointer */
-/* added in silverstone */
-#define AUX_KERNEL_SP			(0x38)	/*!< kernel-mode stack pointer */
-#define AUX_SEC_U_SP			(0x39)	/*!< secure user-mode stack pointer */
-#define AUX_SEC_K_SP			(0x3a)	/*!< secure kernel-mode stack pointer */
-
-/* additional stack checkingh registers for secure mode */
-#define AUX_S_USTACK_BASE		(0x263)
-#define AUX_S_USTACK_TOP		(0x262)
-
-#define AUX_S_KSTACK_BASE		(0x267)
-#define AUX_S_KSTACK_TOP		(0x266)
-
-/**
- * \name auxiliary register for hardware counter 0 and 1
- * @{
- */
-#define AUX_TIMER0_LIMIT		(0x23)	/*!< timer 0 limit value */
-#define AUX_TIMER0_CTRL			(0x22)	/*!< timer 0 control value */
-#define AUX_TIMER0_CNT			(0x21)	/*!< timer 0 count value */
-#define AUX_TIMER1_LIMIT		(0x102)	/*!< timer 1 limit value */
-#define AUX_TIMER1_CTRL			(0x101)	/*!< timer 1 control value */
-#define AUX_TIMER1_CNT			(0x100)	/*!< timer 1 count value */
-/** @} */
-
-#define AUX_SECURE_TIMER0_CNT		(0x106) /*!< secure timer 0 count value */
-#define AUX_SECURE_TIMER0_CTRL		(0x107) /*!< secure timer 0 control value */
-#define AUX_SECURE_TIMER0_LIMIT		(0x108) /*!< secure timer 0 limit value */
-#define AUX_SECURE_TIMER1_CNT		(0x109) /*!< secure timer 1 count value */
-#define AUX_SECURE_TIMER1_CTRL		(0x10a) /*!< secure timer 1 control value */
-#define AUX_SECURE_TIMER1_LIMIT		(0x10b) /*!< secure timer 1 limit value */
-
-
-/**
- * \name auxiliary register for real-time counter
- * @{
- */
-#define AUX_RTC_CTRL			(0x103)	/*!< real-time counter control register */
-#define AUX_RTC_LOW			(0x104)	/*!< real-time counter count low register */
-#define AUX_RTC_HIGH			(0x105)	/*!< real-time counter count high register */
-/** @} */
-
-/**
- * \name indexed table auxiliary register
- * @{
- */
-#define AUX_JLI_BASE			(0x290)	/*!< jump and link indexed base address */
-#define AUX_LDI_BASE			(0x291)	/*!< load indexed base address */
-#define AUX_EI_BASE			(0x292)	/*!< execute indexed base address */
-/** @} */
-
-/**
- * \name baseline auxiliary register set
- * @{
- */
-/* to be added */
-#define AUX_ERRET			(0x400)	/*!< exception return address */
-#define AUX_ERBTA			(0x401)	/*!< BTA saved on exception entry */
-#define AUX_ERSTATUS			(0x402)	/*!< STATUS32 saved on exception */
-#define AUX_ECR				(0x403)	/*!< exception cause register */
-#define AUX_EFA				(0x404) /*!< exception fault address */
-#define AUX_BTA				(0x412)	/*!< branch target address */
-/** @} */
-
-/* New register to control which exceptions can be handled in NS mode */
-#define AUX_ERSEC_STAT			(0x406)
-#define AUX_ERSEC_STAT_BIT_ERM		31
-#define AUX_SEC_EXCEPT			(0x407)
-
-/**
- * \name MPU register set
- * @{
- */
-#define AUX_MPU_EN      		(0x409)	/*!< MPU enable register  */
-#define AUX_MPU_ECR			(0x420)	/*!< MPU exception cause */
-#define AUX_MPU_RDB0    		(0x422)	/*!< MPU region descriptor base 0 */
-#define AUX_MPU_RDP0    		(0x423)	/*!< MPU region descriptor permission 0 */
-
-/* MPU register set in silverstone */
-#define AUX_MPU_INDEX			(0x448)
-#define AUX_MPU_INDEX_BIT_D		(31)
-#define AUX_MPU_RSTART			(0x449)
-#define AUX_MPU_REND			(0x44a)
-#define AUX_MPU_RPER			(0x44b)
-#define AUX_MPU_RPER_BIT_S		(15)
-#define AUX_MPU_PROBE			(0x44c)
-#define AUX_MPU_ECR			(0x420)
-
-#define AUX_NSC_TABLE_BASE		(0x269)
-#define AUX_NSC_TABLE_TOP		(0x268)
-
-/** @} */
-
-/**
- * \name exception cause register (ECR) bit-field definition
- * @{
- */
-#define AUX_ECR_VEC_MASK		(0xff0000)	/*!< [23:16] = exception vector */
-#define AUX_ECR_CODE_MASK		(0x00ff00)	/*!< [15: 8] = exception cause code */
-#define AUX_ECR_PARAM_MASK		(0x0000ff)	/*!< [ 7: 0] = exception parameters */
-/** @} */
-
-/**
- * \name exception vector number and cause code
- * @{
- */
-#define AUX_ECR_V_INSN_ERR		(0x02)	/*!< vector number of illegal instruction */
-#define AUX_ECR_V_MACH_CHK		(0x03)	/*!< vector number of machine check */
-#define AUX_ECR_V_ITLB_MISS		(0x04)	/*!< vector number of instruction TLB missing exception */
-#define AUX_ECR_V_DTLB_MISS		(0x05)	/*!< vector number of data TLB missing exception */
-#define AUX_ECR_V_PROTV			(0x06)	/*!< vector number of protection violation */
-#define AUX_ECR_V_TRAP			(0x09)	/*!< vector number of trap */
-#define AUX_ECR_V_MISALIG_DATA 		(0x0d)	/*!< vector number of misaligned data access */
-
-#define AUX_ECR_C_PROTV_INST_FETCH	(0x00)	/*!< cause code of instruction fetch (protection violation) */
-#define AUX_ECR_C_PROTV_LOAD		(0x01)	/*!< cause code related memory read (protection violation) */
-#define AUX_ECR_C_PROTV_STORE		(0x02)	/*!< cause code related memory write (protection violation) */
-#define AUX_ECR_C_PROTV_XCHG		(0x03)	/*!< cause code related read-modify-write (protection violation) */
-
-#define AUX_ECR_C_MCHK_DUP_TLB		(0x01)	/*!< \todo definition is to be added. */
-
-#define AUX_ECR_C_BIT_DTLB_LD_MISS	(8)	/*!< \todo definition is to be added. */
-#define AUX_ECR_C_BIT_DTLB_ST_MISS	(9)	/*!< \todo definition is to be added. */
-/** @} */
-
-/**
- * \name interrupt related auxiliary register
- * @{
- */
-#define AUX_IRQ_CTRL			(0xe)	/*!< interrupt context saving control register */
-#define AUX_INT_VECT_BASE		(0x25)	/*!< interrupt vector base register */
-#define AUX_INT_VECT_BASE_S		(0x26)	/*!< secure interrupt vector based register */
-#define AUX_IRQ_ACT			(0x43)	/*!< active interrupts register */
-#define AUX_IRQ_CAUSE			(0x40a)	/*!< interrupt cause register */
-#define AUX_IRQ_SELECT			(0x40b)	/*!< interrupt select register */
-#define AUX_IRQ_PRIORITY		(0x206)	/*!< interrupt priority register */
-#define AUX_IRQ_PRIORITY_BIT_S		(0x8)	/*!< S bit offset in interrupt priority register */
-#define AUX_IRQ_ENABLE			(0x40c)	/*!< interrupt enable register */
-#define AUX_IRQ_TRIGGER			(0x40d)	/*!< interrupt trigger: level or pulse */
-#define AUX_IRQ_PENDING			(0x416)	/*!< interrupt pending register */
-#define AUX_IRQ_PLUSE_CLR		(0x415)	/*!< interrupt pulse cancel register */
-#define AUX_IRQ_STATUS			(0x40f)	/*!< interrupt status register */
-#define AUX_IRQ_PRI_PENDING		(0x200)	/*!< interrupt priority pending register */
-#define AUX_IRQ_HINT			(0x201)	/*!< software interrupt trigger */
-/** @} */
-
-/**
- * \name cache related auxiliary register
- * @{
- */
-#define AUX_IC_IVIC			(0x10)	/*!< invalidate instruction cache */
-#define AUX_IC_CTRL			(0x11)	/*!< instruction cache control register */
-#define AUX_IC_LIL			(0x13)	/*!< lock instruction cache line */
-#define AUX_IC_IVIL			(0x19)	/*!< invalidate instruction cache line */
-#define AUX_IC_RAM_ADDR			(0x1a)	/*!< instruction cache external access address */
-#define AUX_IC_TAG			(0x1b)	/*!< instruction cache tag access */
-#define AUX_IC_DATA			(0x1d)	/*!< instruction cache data access */
-#define AUX_DC_IVDC			(0x47)	/*!< invalidate data cache */
-#define AUX_DC_CTRL			(0x48)	/*!< data cache control register */
-#define AUX_DC_LDL			(0x49)	/*!< lock data cache line */
-#define AUX_DC_IVDL			(0x4a)	/*!< invalidate data cache line */
-#define AUX_DC_FLSH			(0x4b)	/*!< flush data cache */
-#define AUX_DC_FLDL			(0x4c)	/*!< flush data line */
-#define AUX_DC_RAM_ADDR			(0x58)	/*!< data cache external access address */
-#define AUX_DC_TAG			(0x59)	/*!< data cache tag access */
-#define AUX_DC_DATA			(0x5b)	/*!< data cache data access */
-/** @} */
-
-/**
- * \name dmac related auxiliary register
- * @{
- */
-#define AUX_DMACTRL			(0x680)	/*!< DMA control register */
-#define AUX_DMACENB			(0x681)	/*!< DMA channel enable register */
-#define AUX_DMACDSB			(0x682)	/*!< DMA channel disable register */
-#define AUX_DMACHPRI			(0x683)	/*!< DMA channel high priority level register */
-#define AUX_DMACNPRI			(0x684)	/*!< DMA channel normal priority level register */
-#define AUX_DMACREQ			(0x685)	/*!< DMA channel transfer request register */
-#define AUX_DMACSTAT0			(0x686)	/*!< DMA channel status register 0 */
-#define AUX_DMACSTAT1			(0x687)	/*!< DMA channel status register 1 */
-#define AUX_DMACIRQ			(0x688)	/*!< DMA channel interrupt request status/clear register */
-#define AUX_DMACBASE			(0x689)	/*!< DMA channel structure register base address */
-#define AUX_DMACRST			(0x68A)	/*!< DMA channel reset register base address */
-
-#define AUX_DMACTRL0			(0x690)	/*!< DMA channel 0 control register when mapped in aux */
-#define AUX_DMASAR0			(0x691)	/*!< DMA channel 0 source address register when mapped in aux */
-#define AUX_DMADAR0			(0x692)	/*!< DMA channel 0 destination register when mapped in aux */
-#define AUX_DMACTRLx			(AUX_DMACTRL0)	/*!< DMA channel 0 control register when mapped in aux */
-#define AUX_DMASARx			(AUX_DMASAR0)	/*!< DMA channel 0 source address register when mapped in aux */
-#define AUX_DMADARx			(AUX_DMADAR0)	/*!< DMA channel 0 destination register when mapped in aux */
-/** @} */
-
-
-
-/**
- * \name other auxiliary register
- * @{
- */
-#define AUX_IDENTITY			(0x4) 	/*!< identity register */
-#define AUX_DMP_PERIPHERAL		(0x20a) /*!< peripheral memory region */
-#define AUX_XFLAGS			(0x44f) /*!< user extension flags register */
-#define AUX_MCIP_CMD			(0x600) /*!< \todo definition is to be added. */
-#define AUX_MCIP_WDATA			(0x601) /*!< \todo definition is to be added. */
-#define AUX_MCIP_READBACK		(0x602) /*!< \todo definition is to be added. */
-#define AUX_SMART_CONTROL		(0x700) /*!< \todo definition is to be added. */
-#define AUX_SMART_DATA			(0x701) /*!< \todo definition is to be added. */
-
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __ASSEMBLY__
-/* add type definition and function declaration here */
-#endif	/* assembly */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif	/* _ARC_HAL_CORE_H_ */
-
- /**  @} */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_asm_common.h b/bsp/synopsys/embarc/inc/arc/arc_asm_common.h
deleted file mode 100644
index 68d9ca4e67..0000000000
--- a/bsp/synopsys/embarc/inc/arc/arc_asm_common.h
+++ /dev/null
@@ -1,541 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_MISC
- * \brief common macro definitions for assembly file
- */
-/** @cond ARC_HAL_ASM_COMMON */
-
-#ifndef _ARC_HAL_ASM_COMMON_H_
-#define _ARC_HAL_ASM_COMMON_H_
-
-#include "embARC_BSP_config.h"
-#include "arc_feature_config.h"
-
-/* Note on the LD/ST addr modes with addr reg wback
- *
- * LD.a same as LD.aw
- *
- * LD.a    reg1, [reg2, x]  => Pre Incr
- *      Eff Addr for load = [reg2 + x]
- *
- * LD.ab   reg1, [reg2, x]  => Post Incr
- *      Eff Addr for load = [reg2]
- */
-#if defined(__GNU__)
-.macro PUSH reg
-	st.a	\reg, [sp, -4]
-.endm
-
-.macro PUSHAX aux
-	lr	r10, [\aux]
-	PUSH	r10
-.endm
-
-.macro POP reg
-	ld.ab	\reg, [sp, 4]
-.endm
-
-.macro POPAX aux
-	POP	r10
-	sr	r10, [\aux]
-.endm
-#else
-.macro PUSH, reg
-	st.a	reg, [sp, -4]
-.endm
-
-.macro PUSHAX, aux
-	lr	r10, [aux]
-	PUSH	r10
-.endm
-
-.macro POP, reg
-    ld.ab   reg, [sp, 4]
-.endm
-
-.macro POPAX, aux
-	POP	r10
-	sr	r10, [aux]
-.endm
-#endif
-
-/*--------------------------------------------------------------
- * Helpers to save/restore callee-saved regs:
- * used by several macros below
- *-------------------------------------------------------------*/
-.macro SAVE_CALLEE_REGS
-	PUSH	r13
-	PUSH	r14
-	PUSH	r15
-#ifndef ARC_FEATURE_RF16
-	PUSH	r16
-	PUSH	r17
-	PUSH	r18
-	PUSH	r19
-	PUSH	r20
-	PUSH	r21
-	PUSH	r22
-	PUSH	r23
-	PUSH	r24
-	PUSH	r25
-#endif
-.endm
-
-.macro RESTORE_CALLEE_REGS
-#ifndef ARC_FEATURE_RF16
-	POP	r25
-	POP	r24
-	POP	r23
-	POP	r22
-	POP	r21
-	POP	r20
-	POP	r19
-	POP	r18
-	POP	r17
-	POP	r16
-#endif
-	POP	r15
-	POP	r14
-	POP	r13
-.endm
-
-.macro CLEAR_CALLEE_REGS
-#ifndef ARC_FEATURE_RF16
-	mov	r25, 0
-	mov	r24, 0
-	mov	r23, 0
-	mov	r22, 0
-	mov	r21, 0
-	mov	r20, 0
-	mov	r19, 0
-	mov	r18, 0
-	mov	r17, 0
-	mov	r16, 0
-#endif
-	mov	r15, 0
-	mov	r14, 0
-	mov	r13, 0
-.endm
-
-.macro CLEAR_SCRATCH_REGS
-	mov	r1, 0
-	mov 	r2, 0
-	mov	r3, 0
-	mov	r4, 0
-	mov	r5, 0
-	mov	r6, 0
-	mov	r7, 0
-	mov	r8, 0
-	mov 	r9, 0
-	mov	r10, 0
-	mov	r11, 0
-	mov	r12, 0
-
-	mov 	fp, 0
-	mov 	r29, 0
-	mov 	r30, 0
-.endm
-
-
-.macro SAVE_LP_REGS
-	PUSH	r60
-	PUSHAX	AUX_LP_START
-	PUSHAX	AUX_LP_END
-.endm
-
-.macro RESTORE_LP_REGS
-	POPAX	AUX_LP_END
-	POPAX	AUX_LP_START
-	POP	r10
-/* must not use the LP_COUNT register(r60) as the destination of multi-cycle instruction */
-	mov	r60, r10
-
-.endm
-
-.macro SAVE_R0_TO_R12
-	PUSH    r0
-	PUSH    r1
-	PUSH    r2
-	PUSH    r3
-#ifndef ARC_FEATURE_RF16
- 	PUSH    r4
- 	PUSH    r5
- 	PUSH    r6
- 	PUSH    r7
- 	PUSH    r8
- 	PUSH    r9
-#endif
-	PUSH    r10
-	PUSH    r11
-	PUSH    r12
-.endm
-
-.macro RESTORE_R0_TO_R12
-	POP	r12
-	POP	r11
-	POP	r10
-#ifndef ARC_FEATURE_RF16
-	POP	r9
-	POP	r8
-	POP	r7
-	POP	r6
-	POP	r5
-	POP	r4
-#endif
-	POP	r3
-	POP	r2
-	POP	r1
-	POP	r0
-.endm
-
-.macro SAVE_CODE_DENSITY
-	PUSHAX	AUX_JLI_BASE
-	PUSHAX	AUX_LDI_BASE
-	PUSHAX	AUX_EI_BASE
-.endm
-
-.macro RESTORE_CODE_DENSITY
-	POPAX	AUX_EI_BASE
-	POPAX	AUX_LDI_BASE
-	POPAX	AUX_JLI_BASE
-.endm
-
-/* todo: check the contents of NON_SCRATCH_REGS in debug */
-.macro SAVE_NONSCRATCH_REGS
-/* r0-r12 are saved by caller function */
-	PUSH	gp
-	PUSH	fp
-	PUSH	blink
-	SAVE_CALLEE_REGS
-.endm
-
-.macro RESTORE_NONSCRATCH_REGS
-	RESTORE_CALLEE_REGS
-	POP	blink
-	POP	fp
-	POP	gp
-.endm
-
-
-.macro SAVE_FIQ_EXC_REGS
-#ifndef ARC_FEATURE_RGF_BANKED_REGS
-	SAVE_R0_TO_R12
-
-	PUSH	gp
-	PUSH	fp
-	PUSH	r30		/* general purpose */
-	PUSH	blink
-
-#else
-#if ARC_FEATURE_RGF_BANKED_REGS != 4 && ARC_FEATURE_RGF_BANKED_REGS != 8 && \
-	ARC_FEATURE_RGF_BANKED_REGS != 16  && ARC_FEATURE_RGF_BANKED_REGS != 32
-#error	"unsupported ARC_FEATURE_RGF_BANKED_REGS"
-#endif
-
-#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 || \
-	ARC_FEATURE_RGF_BANKED_REGS == 16
-	PUSH	r4
-	PUSH	r5
-	PUSH	r6
-	PUSH	r7
-	PUSH	r8
-	PUSH	r9
-#endif
-
-#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8
-	PUSH	r10
-	PUSH	r11
-#endif
-
-#if ARC_FEATURE_RGF_BANKED_REGS == 4
-	PUSH	r12
-#endif
-
-#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8
-	PUSH	gp
-	PUSH	fp
-	PUSH	r30		/* general purpose */
-	PUSH	blink
-#endif
-
-#endif /* #ifndef ARC_FEATURE_RGF_BANKED_REGS */
-
-#ifdef ARC_FEATURE_CODE_DENSITY
-	SAVE_CODE_DENSITY
-#endif
-	SAVE_LP_REGS
-.endm
-
-.macro RESTORE_FIQ_EXC_REGS
-	RESTORE_LP_REGS
-#ifdef	ARC_FEATURE_CODE_DENSITY
-	RESTORE_CODE_DENSITY
-#endif
-
-#ifndef ARC_FEATURE_RGF_BANKED_REGS
-	POP	blink
-	POP	r30
-	POP	fp
-	POP	gp
-
-	RESTORE_R0_TO_R12
-#else
-
-#if ARC_FEATURE_RGF_BANKED_REGS != 4 && ARC_FEATURE_RGF_BANKED_REGS != 8 && \
-	ARC_FEATURE_RGF_BANKED_REGS != 16 && ARC_FEATURE_RGF_BANKED_REGS != 32
-#error	"unsupported ARC_FEATURE_RGF_BANKED_REGS"
-#endif
-
-#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8
-	POP	blink
-	POP	r30
-	POP	fp
-	POP	gp
-#endif
-
-#if ARC_FEATURE_RGF_BANKED_REGS == 4
-	POP	r12
-#endif
-
-#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8
-	POP		r11
-	POP		r10
-#endif
-
-#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 || \
-	ARC_FEATURE_RGF_BANKED_REGS == 16
-	POP		r9
-	POP		r8
-	POP		r7
-	POP		r6
-	POP		r5
-	POP		r4
-#endif
-
-#endif  /* #ifndef ARC_FEATURE_RGF_BANKED_REGS */
-.endm
-
-/* normal interrupt prologue, pc, status and r0-r11 are saved by hardware */
-.macro INTERRUPT_PROLOGUE
-	PUSH	r12
-	PUSH	gp
-	PUSH	fp
-	PUSH	ilink
-	PUSH	r30
-
-	sub	sp, sp, 4 /* skip bta */
-.endm
-
-
-/* normal interrupt epilogue, pc, status and r0-r11 are restored by hardware */
-.macro INTERRUPT_EPILOGUE
-	add	sp, sp, 4 /* skip bta */
-
-	POP	r30
-	POP	ilink
-	POP	fp
-	POP	gp
-	POP	r12
-.endm
-
-#if SECURESHIELD_VERSION == 2
-/* exception prologue, create the same frame of interrupt manually */
-.macro EXCEPTION_PROLOGUE
-	st.as	r10, [sp, -6]	/* save r10 first, free up a register*/
-
-	PUSHAX	AUX_ERSTATUS
-	sub 	sp, sp, 4 /* slot for SEC_STAT */
-	PUSHAX	AUX_ERRET
-
-	PUSH	blink
-
-	PUSH	r11
-	sub	sp, sp, 4 /* r10 is  pushed before */
-#ifndef ARC_FEATURE_RF16
-	PUSH	r9
-	PUSH	r8
-	PUSH	r7
-	PUSH	r6
-	PUSH	r5
-	PUSH	r4
-#endif
-	PUSH	r3
-	PUSH	r2
-	PUSH	r1
-	PUSH	r0
-
-#ifdef ARC_FEATURE_CODE_DENSITY
-	SAVE_CODE_DENSITY
-#endif
-	SAVE_LP_REGS
-
-	PUSH	r12
-	PUSH	gp
-	PUSH	fp
-	PUSH	ilink
-	PUSH	r30
-
-	PUSHAX	AUX_ERBTA
-.endm
-
-/* exception epilogue, restore the same frame of interrupt manually */
-.macro EXCEPTION_EPILOGUE
-	POPAX	AUX_ERBTA
-
-	POP	r30
-	POP	ilink
-	POP	fp
-	POP	gp
-	POP	r12
-
-	RESTORE_LP_REGS
-
-#ifdef ARC_FEATURE_CODE_DENSITY
-	RESTORE_CODE_DENSITY
-#endif
-	POP	r0
-	POP	r1
-	POP	r2
-	POP	r3
-#ifndef ARC_FEATURE_RF16
-	POP	r4
-	POP	r5
-	POP	r6
-	POP	r7
-	POP	r8
-	POP	r9
-#endif
-	add	sp, sp, 4 /* r10 will be popped finally */
-	POP	r11
-
-	POP	blink
-
-
-	POPAX	AUX_ERRET
-	add 	sp, sp, 4  /* slot for SEC_STAT */
-	POPAX	AUX_ERSTATUS
-
-	ld.as	r10, [sp, -6]	/* restore r10 */
-.endm
-#else /* normal version */
-/* exception prologue, create the same frame of interrupt manually */
-.macro EXCEPTION_PROLOGUE
-#ifdef	ARC_FEATURE_CODE_DENSITY
-	st.as	r10, [sp, -11]	/* save r10 first, free up a register*/
-#else
-	st.as	r10, [sp, -8]
-#endif
-	PUSHAX	AUX_ERSTATUS
-	PUSHAX	AUX_ERRET
-
-#ifdef ARC_FEATURE_CODE_DENSITY
-	SAVE_CODE_DENSITY
-#endif
-	SAVE_LP_REGS
-
-	PUSH	blink
-
-	PUSH	r11
-	sub	sp, sp, 4 /* r10 is  pushed before */
-#ifndef ARC_FEATURE_RF16
-	PUSH	r9
-	PUSH	r8
-	PUSH	r7
-	PUSH	r6
-	PUSH	r5
-	PUSH	r4
-#endif
-	PUSH	r3
-	PUSH	r2
-	PUSH	r1
-	PUSH	r0
-
-	PUSH	r12
-	PUSH	gp
-	PUSH	fp
-	PUSH	ilink
-	PUSH	r30
-
-	PUSHAX	AUX_ERBTA
-.endm
-
-/* exception epilogue, restore the same frame of interrupt manually */
-.macro EXCEPTION_EPILOGUE
-	POPAX	AUX_ERBTA
-
-	POP	r30
-	POP	ilink
-	POP	fp
-	POP	gp
-	POP	r12
-
-	POP	r0
-	POP	r1
-	POP	r2
-	POP	r3
-#ifndef ARC_FEATURE_RF16
-	POP	r4
-	POP	r5
-	POP	r6
-	POP	r7
-	POP	r8
-	POP	r9
-#endif
-	add	sp, sp, 4 /* r10 will be popped finally */
-	POP	r11
-
-	POP	blink
-
-	RESTORE_LP_REGS
-
-#ifdef ARC_FEATURE_CODE_DENSITY
-	RESTORE_CODE_DENSITY
-#endif
-
-	POPAX	AUX_ERRET
-	POPAX	AUX_ERSTATUS
-
-#ifdef	ARC_FEATURE_CODE_DENSITY
-	ld.as	r10, [sp, -11]	/* restore r10 */
-#else
-	ld.as	r10, [sp, -8]
-#endif
-.endm
-
-#endif /* SECURESHIELD_VERSION == 2 */
-
-#endif	/* _ARC_HAL_ASM_COMMON_H */
-/** @endcond */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_builtin.h b/bsp/synopsys/embarc/inc/arc/arc_builtin.h
deleted file mode 100644
index d9b76124ff..0000000000
--- a/bsp/synopsys/embarc/inc/arc/arc_builtin.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-12
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_BUILTIN
- * \brief header file of builtin and helper functions
- *
- * The Metaware toolchain and the GNU toolchain are supported. The details please go to see the file.
- */
-
-/**
- * \addtogroup	ARC_HAL_BUILTIN
- * @{
- */
-
-#ifndef _ARC_HAL_BUILTIN_H_
-#define _ARC_HAL_BUILTIN_H_
-
-#include "inc/embARC_toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined (__MW__)	/* Metaware toolchain */
-
-#define _arc_nop			_nop 	/*!< no operation, generate a nop instruction produces a single NOP instruction in the compiled code */
-
-#define _arc_brk			_brk 	/*!< generate a brk instruction */
-
-#define _arc_clri			_clri  	/*!< generate a clri instruction */
-
-#define _arc_seti(c)			_seti(c) /*!< generate a seti instruction */
-
-#define	_arc_core_write(regno, val)	_core_write(val, regno)	/*!< write core register */
-
-#define _arc_core_read(regno)		_core_read(regno)	/*!< read core register */
-
-#define _arc_lr_reg(aux)		_lr(aux)	/*!< read auxiliary register */
-
-#define _arc_sr_reg(aux, val)		_sr(val, aux)	/*!< write auxiliary register */
-
-#define _arc_sleep(a)			_sleep(a)	/*!< generate a sleep instruction */
-
-#define _arc_flag(a)			_flag(a)	/*!< generate a flag instruction */
-
-#define _arc_kflag(a)
-
-#define _arc_sync			_sync 		/*!< generate a sync instruction */
-
-/*
- * !< _arc_usually (expr) evaluates expression expr and
- * informs the compiler that the value is usually true.
- */
-#define _arc_usually(a)			_Usually((a))
-
-/*
- * !< _arc_rarely (expr) evaluates expression expr and
- * informs the compiler that the value is rarely true.
- */
-#define _arc_rarely(a)			_Rarely((a))
-
-#if 0
-/**
- * \brief 	Reverses the byte order of the 16-bit operand,
- *  		reversing the endianness of the value.
- *    		Not for ARC HS family
- */
-#define _arc_swap16(a)			_swap16(a)
-/**
- * \brief 	Reverses the byte order of the 32-bit operand,
- *  		reversing the endianness of the value.
- *    		Not for ARC HS family
- */
-#define _arc_swap32(a)			_swap32(a)
-#else
-Inline uint32_t _arc_swap32(uint32_t val) {
-	register uint32_t v;
-	__asm__ volatile ("swape %0, %1" :"=r"(v): "r"(val));
-	return v;
-}
-
-Inline uint16_t _arc_swap16(uint32_t val) {
-	register uint32_t temp;
-	register uint32_t v;
-	__asm__ volatile ("swape %0, %1" :"=r"(temp): "r"(val));
-	__asm__ volatile ("lsr16 %0, %1" :"=r"(v): "r"(temp));
-	return (unsigned short)v;
-}
-#endif
-
-/**
- * \brief 	Each call to _swi() generates one
- * 			software interrupt instruction (SWI) for processors
- * 			to support the SWI instruction.
- */
-#define _arc_swi				_swi
-
-/* \todo add more builtin functions of metaware tool */
-
-#elif defined (__GNU__) /* GNU toolchain */
-
-#define _arc_nop				__builtin_arc_nop
-#define _arc_brk				__builtin_arc_brk
-#define _arc_seti(c)				__builtin_arc_seti(c)
-#define _arc_core_write(regno, val)		__builtin_arc_core_write(regno,val)
-#define _arc_core_read(regno)			__builtin_arc_core_read(regno)
-#define _arc_flag(a)				__builtin_arc_flag(a)
-#define _arc_kflag(a)				__builtin_arc_kflag(a)
-#define _arc_lr_reg(aux)			__builtin_arc_lr(aux)
-/* don't uncomment this now */
-//#define _arc_sr_reg(aux, val)			__builtin_arc_sr(aux, val)
-#define _arc_sleep(a)				__builtin_arc_sleep(a)
-//#define _arc_sync				__builtin_arc_sync
-
-/**
- * \brief _arc_usually (expr) evaluates expression expr and
- * 		  informs the compiler that the value is usually true.
- */
-#define _arc_usually(a)				__builtin_expect((int)(a), 1)
-
-/**
- * \brief _arc_rarely (expr) evaluates expression expr and
- *	informs the compiler that the value is rarely true.
- */
-#define _arc_rarely(a)				__builtin_expect((int)(a), 0)
-
-/**
- * \brief 	Each call to _swi() generates one
- * 			software interrupt instruction (SWI) for processors
- * 			to support the SWI instruction.
- */
-#define _arc_swi 				__builtin_arc_swi
-
-Inline uint32_t _arc_clri(void) {
-	register uint32_t v;
-	__asm__ volatile ("clri %0" :"=r"(v));
-	return v;
-
-}
-/* \todo add more builtin functions of gnu tool */
-
-Inline uint32_t _arc_swap32(uint32_t val) {
-	register uint32_t v;
-	__asm__ volatile ("swape %0, %1" :"=r"(v): "r"(val));
-	return v;
-}
-
-Inline uint16_t _arc_swap16(uint32_t val) {
-	register uint32_t temp;
-	register uint32_t v;
-	__asm__ volatile ("swape %0, %1" :"=r"(temp): "r"(val));
-	__asm__ volatile ("lsr16 %0, %1" :"=r"(v): "r"(temp));
-	return (unsigned short)v;
-}
-
-Inline void _arc_sync(void) {
-	__asm__ volatile ("sync");
-}
-
-/**
- * \note Following is a workaround for arc gcc
- *       built-in function __builtin_arc_sr.
- *       But it is wrong in GCC arc-4.8-R3-rc3 and shouldn't be used.
- */
-
-/*
- * The auxiliary register address is specified as a long immediate operand by caller.
- * e.g.
- *    write_aux_reg(0x69, some_val);
- * This generates the tightest code.
- */
-#define write_aux_reg(reg_imm, val)	\
-({					\
-	Asm(		\
-	"	sr   %0, [%1]	\n"	\
-	:				\
-	: "ir"(val), "r"(reg_imm));	\
-})
-
-#define _arc_sr_reg(aux, val)			write_aux_reg(aux, val)
-
-#endif
-
-/* \todo add more helper functions here, such as memory operation */
-
-#define _arc_aux_read(aux)			_arc_lr_reg(aux)
-#define _arc_aux_write(aux, val)		_arc_sr_reg(aux, val)
-
-/**
- * \name cache related helper function
- * @{
- */
-
-/**
- * \brief  read memory and bypass the cache
- * \param[in] ptr memory address
- * \return value in the memory
- */
-Inline uint32_t _arc_read_uncached_32(void *ptr)
-{
-	uint32_t __ret;
-	Asm("ld.di %0, [%1]":"=r"(__ret):"r"(ptr));
-	return __ret;
-}
-
-/**
- * \brief  write memory and bypass the cache
- * \param[in] ptr memory address
- * \param[in] data  vaule to be written
- */
-Inline void _arc_write_uncached_32(void *ptr, uint32_t data)
-{
-	Asm("st.di %0, [%1]":: "r"(data), "r"(ptr));
-}
-
-/**
- * \brief  read memory with cache
- * \param[in] ptr memory address
- * \returns value in the memory
- */
-Inline uint32_t _arc_read_cached_32(void *ptr)
-{
-	uint32_t __ret;
-	Asm("ld %0, [%1]":"=r"(__ret):"r"(ptr));
-	return __ret;
-}
-
-/**
- * \brief  read memory with cache
- * \param[in] ptr memory address
- * \param[in] data vaule to be written
- * \return description
- */
-Inline void _arc_write_cached_32(void *ptr, uint32_t data)
-{
-	Asm("st %0, [%1]":: "r"(data), "r"(ptr));
-}
-
-/**
- * \brief go to main function with proper arguments
- * \param  argc argument count
- * \param  argv argument content array
- * \retval return value of main function
- */
-Inline int32_t _arc_goto_main(int argc, char **argv) {
-	int __ret;
-	__asm__ volatile(
-		"mov %%r0, %1\n"
-		"mov %%r1, %2\n"
-		"push_s %%blink\n"
-		"jl main\n"
-		"pop_s %%blink\n"
-		"mov %0, %%r0"
-		:"=r"(__ret): "r"(argc), "r"(argv));
-	return (int)__ret;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#if defined(LIB_SECURESHIELD) && defined(LIB_SECURESHIELD_OVERRIDES) && (SECURESHIELD_VERSION == 1)
-#define OVERRIDE_ARC_HAL_BUILTIN_H
-#include "secureshield_overrides.h"
-#endif
-
-/** @} */
-#endif /* _ARC_HAL_BUILTIN_H_ */
-/** @} */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_cache.h b/bsp/synopsys/embarc/inc/arc/arc_cache.h
deleted file mode 100644
index dfbc7df9a5..0000000000
--- a/bsp/synopsys/embarc/inc/arc/arc_cache.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	ARC_HAL_MISC_CACHE
- * \brief header file of cache module
- */
-
-#ifndef _ARC_HAL_CACHE_H_
-#define _ARC_HAL_CACHE_H_
-
-#include "inc/embARC_toolchain.h"
-#include "inc/arc/arc.h"
-#include "inc/arc/arc_builtin.h"
-#include "inc/arc/arc_exception.h"
-
-/**
- * \name instruction cache control register related definition
- * \todo this definitions will be reviewed.
- * @{
- */
-#define IC_CTRL_IC_ENABLE			0x0	/*!< enable instruction cache */
-#define IC_CTRL_IC_DISABLE			0x1	/*!< disable instruction cache */
-#define IC_CTRL_DIRECT_ACCESS			0x0	/*!< direct access mode */
-#define IC_CTRL_INDIRECT_ACCESS			0x20	/*!< indirect access mode */
-#define IC_CTRL_OP_SUCCEEDED			0x8	/*!< instruction cache operation succeeded */
-/** @} */
-
-/**
- * \name data cache control register related definition
- * \todo this definition will be reviewed.
- * @{
- */
-#define IC_CTRL_I
-#define DC_CTRL_DC_ENABLE			0x0	/*!< enable data cache */
-#define DC_CTRL_DC_DISABLE			0x1	/*!< disable data cache */
-#define DC_CTRL_INVALID_ONLY			0x0	/*!< invalid data cache only */
-#define DC_CTRL_INVALID_FLUSH			0x40	/*!< invalid and flush data cache */
-#define DC_CTRL_ENABLE_FLUSH_LOCKED		0x80	/*!< the locked data cache can be flushed */
-#define DC_CTRL_DISABLE_FLUSH_LOCKED		0x0	/*!< the locked data cache cannot be flushed */
-#define DC_CTRL_FLUSH_STATUS			0x100	/*!< flush status */
-#define DC_CTRL_DIRECT_ACCESS			0x0	/*!< direct access mode  */
-#define DC_CTRL_INDIRECT_ACCESS			0x20	/*!< indirect access mode */
-#define DC_CTRL_OP_SUCCEEDED			0x4	/*!< data cache operation succeeded */
-/** @} */
-
-/**
- * \name instruction cache related inline function
- * @{
- */
-
-/**
- * \brief  check whether instruction cache is available,
- * 0 for not available, >0 for available
- */
-Inline uint8_t icache_available(void)
-{
-	return (_arc_aux_read(AUX_BCR_I_CACHE) & 0xF);
-}
-
-/**
- * \brief  enable instruction cache
- * \param[in] icache_en_mask operation mask
- */
-Inline void icache_enable(uint32_t icache_en_mask)
-{
-	if (!icache_available()) return;
-	_arc_aux_write(AUX_IC_CTRL, icache_en_mask);
-}
-
-/**
- * \brief  disable instruction cache
- */
-Inline void icache_disable(void)
-{
-	if (!icache_available()) return;
-	_arc_aux_write(AUX_IC_CTRL, IC_CTRL_IC_DISABLE);
-}
-
-/**
- * \brief  invalidate the entire instruction cache
- */
-Inline void icache_invalidate(void)
-{
-	if (!icache_available()) return;
-	/* invalidate the entire icache */
-	_arc_aux_write(AUX_IC_IVIC, 0);
-	Asm("nop_s");
-	Asm("nop_s");
-	Asm("nop_s");
-}
-
-/**
- * \brief  invalidate specific cache line
- * \param[in] address memory address
- */
-Inline void icache_invalidate_line(uint32_t address)
-{
-	if (!icache_available()) return;
-	_arc_aux_write(AUX_IC_IVIL, address);
-	/* the 3 nops are required by ARCv2 ISA */
-	Asm("nop_s");
-	Asm("nop_s");
-	Asm("nop_s");
-}
-
-/**
- * \brief  lock specific cache line
- * \param[in] address memory address
- * \return 0, succeeded, -1, failed
- */
-Inline int32_t icache_lock_line(uint32_t address)
-{
-	if (!icache_available()) return -1;
-	_arc_aux_write(AUX_IC_LIL, address);
-	if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
-		return 0;
-	} else {
-		return -1;
-	}
-}
-
-/**
- * \brief  set icache access mode
- * \param[in] mode, access mode, 1: indirect access 0:direct access
- */
-Inline void icache_access_mode(uint32_t mode)
-{
-	if (!icache_available()) return;
-	if (mode) {
-		_arc_aux_write(AUX_IC_CTRL, _arc_aux_read(AUX_IC_CTRL) | IC_CTRL_INDIRECT_ACCESS);
-	} else {
-		_arc_aux_write(AUX_IC_CTRL, _arc_aux_read(AUX_IC_CTRL) & (~IC_CTRL_INDIRECT_ACCESS));
-	}
-}
-
-
-/** @} */
-
-/**
- * \name data cache related inline functions
- * @{
- */
-
-/**
- * \brief  check whether data cache is available,
- * 0 for not available, >0 for available
- */
-Inline uint8_t dcache_available(void)
-{
-	return (_arc_aux_read(AUX_BCR_D_CACHE) & 0xF);
-}
-
-/**
- * \brief 	invalidate the entire data cache
- */
-Inline void dcache_invalidate(void)
-{
-	if (!dcache_available()) return;
-	uint32_t status;
-
-	status = cpu_lock_save();
-	_arc_aux_write(AUX_DC_IVDC, 1);
-	/* wait for flush completion */
-	while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
-	cpu_unlock_restore(status);
-}
-
-/**
- * \brief invalidate the specific cache line
- * \param[in] address memory address
- */
-Inline void dcache_invalidate_line(uint32_t address)
-{
-	if (!dcache_available()) return;
-	_arc_aux_write(AUX_DC_IVDL, address);
-	Asm("nop_s");
-	Asm("nop_s");
-	Asm("nop_s");
-}
-
-/**
- * \brief enable data cache
- * \param[in] dcache_en_mask operation mask
- */
-Inline void dcache_enable(uint32_t dcache_en_mask)
-{
-	if (!dcache_available()) return;
-	_arc_aux_write(AUX_DC_CTRL, dcache_en_mask);
-}
-
-/**
- * \brief disable data cache
- */
-Inline void dcache_disable(void)
-{
-	if (!dcache_available()) return;
-	_arc_aux_write(AUX_DC_CTRL, DC_CTRL_DC_DISABLE);
-}
-
-/**
- * \brief flush data cache
- */
-Inline void dcache_flush(void)
-{
-	if (!dcache_available()) return;
-	uint32_t status;
-
-	status = cpu_lock_save();
-	_arc_aux_write(AUX_DC_FLSH, 1);
-	/* wait for flush completion */
-	while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
-	cpu_unlock_restore(status);
-}
-
-/**
- * \brief  flush the specific data cache line
- * \param[in] address memory address
- */
-Inline void dcache_flush_line(uint32_t address)
-{
-	if (!dcache_available()) return;
-
-	uint32_t status;
-
-	status = cpu_lock_save();
-	_arc_aux_write(AUX_DC_FLDL, address);
-	while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
-	cpu_unlock_restore(status);
-}
-
-/**
- * \brief  lock the specific data cache line
- * \param[in] address memory address
- * \return 0, succeeded, -1, failed
- */
-Inline int dcache_lock_line(uint32_t address)
-{
-	if (!dcache_available()) return -1;
-	_arc_aux_write(AUX_DC_LDL, address);
-	if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
-		return 0;
-	} else {
-		return -1;
-	}
-}
-
-/**
- * \brief  set dcache access mode
- * \param[in] mode, access mode, 1: indirect access 0:direct access
- */
-Inline void dcache_access_mode(uint32_t mode)
-{
-	if (!dcache_available()) return;
-	if (mode) {
-		_arc_aux_write(AUX_DC_CTRL, _arc_aux_read(AUX_DC_CTRL) | DC_CTRL_INDIRECT_ACCESS);
-	} else {
-		_arc_aux_write(AUX_DC_CTRL, _arc_aux_read(AUX_DC_CTRL) & (~DC_CTRL_INDIRECT_ACCESS));
-	}
-}
-
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name declarations of cache related functions
- * @{
- */
-extern int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size);
-extern int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size);
-extern int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data);
-extern int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data);
-extern int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data);
-extern int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size);
-extern int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size);
-extern int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size);
-extern int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data);
-extern int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data);
-extern int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data);
-extern void arc_cache_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @} */
-#endif	/* _ARC_HAL_CACHE_H_ */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_em.h b/bsp/synopsys/embarc/inc/arc/arc_em.h
deleted file mode 100644
index cfb9636449..0000000000
--- a/bsp/synopsys/embarc/inc/arc/arc_em.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-06-12
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_CORE_EM
- * \brief header file of EM series
- */
-
-/**
- * \addtogroup ARC_HAL_CORE_EM
- * @{
- */
-
-#ifndef _ARC_HAL_EM_H_
-#define _ARC_HAL_EM_H_
-
-#include "inc/arc/arc.h"
-
-#define AUX_ACC0_LO		(0x580)
-#define AUX_ACC0_GLO		(0x581)
-#define AUX_ACC0_HI		(0x582)
-#define AUX_ACC0_GHI		(0x583)
-#define AUX_DSP_BFLY0		(0x598)
-#define AUX_DSP_FFT_CTRL	(0x59e)
-#define AUX_DSP_CTRL		(0x59f)
-
-#define AUX_AGU_AUX_AP0		(0x5c0)
-#define AUX_AGU_AUX_AP1		(0x5c1)
-#define AUX_AGU_AUX_AP2		(0x5c2)
-#define AUX_AGU_AUX_AP3		(0x5c3)
-#define AUX_AGU_AUX_AP4		(0x5c4)
-#define AUX_AGU_AUX_AP5		(0x5c5)
-#define AUX_AGU_AUX_AP6		(0x5c6)
-#define AUX_AGU_AUX_AP7		(0x5c7)
-#define AUX_AGU_AUX_AP8		(0x5c8)
-#define AUX_AGU_AUX_AP9		(0x5c9)
-#define AUX_AGU_AUX_AP10	(0x5ca)
-#define AUX_AGU_AUX_AP11	(0x5cb)
-#define AUX_AGU_AUX_AP12	(0x5cc)
-#define AUX_AGU_AUX_AP13	(0x5cd)
-#define AUX_AGU_AUX_AP14	(0x5ce)
-#define AUX_AGU_AUX_AP15	(0x5cf)
-
-#define AUX_AGU_AXU_OS0		(0x5d0)
-#define AUX_AGU_AXU_OS1		(0x5d1)
-#define AUX_AGU_AXU_OS2		(0x5d2)
-#define AUX_AGU_AXU_OS3		(0x5d3)
-#define AUX_AGU_AXU_OS4		(0x5d4)
-#define AUX_AGU_AXU_OS5		(0x5d5)
-#define AUX_AGU_AXU_OS6		(0x5d6)
-#define AUX_AGU_AXU_OS7		(0x5d7)
-#define AUX_AGU_AXU_OS8		(0x5d8)
-#define AUX_AGU_AXU_OS9		(0x5d9)
-#define AUX_AGU_AXU_OS10	(0x5da)
-#define AUX_AGU_AXU_OS11	(0x5db)
-#define AUX_AGU_AXU_OS12	(0x5dc)
-#define AUX_AGU_AXU_OS13	(0x5dd)
-#define AUX_AGU_AXU_OS14	(0x5de)
-#define AUX_AGU_AXU_OS15	(0x5df)
-
-#define	AUX_AGU_AUX_MOD0	(0x5e0)
-#define	AUX_AGU_AUX_MOD1	(0x5e1)
-#define	AUX_AGU_AUX_MOD2	(0x5e2)
-#define	AUX_AGU_AUX_MOD3	(0x5e3)
-#define	AUX_AGU_AUX_MOD4	(0x5e4)
-#define	AUX_AGU_AUX_MOD5	(0x5e5)
-#define	AUX_AGU_AUX_MOD6	(0x5e6)
-#define	AUX_AGU_AUX_MOD7	(0x5e7)
-#define	AUX_AGU_AUX_MOD8	(0x5e8)
-#define	AUX_AGU_AUX_MOD9	(0x5e9)
-#define	AUX_AGU_AUX_MOD10	(0x5ea)
-#define	AUX_AGU_AUX_MOD11	(0x5eb)
-#define	AUX_AGU_AUX_MOD12	(0x5ec)
-#define	AUX_AGU_AUX_MOD13	(0x5ed)
-#define	AUX_AGU_AUX_MOD14	(0x5ee)
-#define	AUX_AGU_AUX_MOD15	(0x5ef)
-#define	AUX_AGU_AUX_MOD16	(0x5f0)
-#define	AUX_AGU_AUX_MOD17	(0x5f1)
-#define	AUX_AGU_AUX_MOD18	(0x5f2)
-#define	AUX_AGU_AUX_MOD19	(0x5f3)
-#define	AUX_AGU_AUX_MOD20	(0x5f4)
-#define	AUX_AGU_AUX_MOD21	(0x5f5)
-#define	AUX_AGU_AUX_MOD22	(0x5f6)
-#define	AUX_AGU_AUX_MOD23	(0x5f7)
-
-#define AUX_XCCM_BASE		(0x5f8)
-#define AUX_YCCM_BASE		(0x5f9)
-
-
-/** \todo add em series specific definitions here */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ARC_HAL_EM_H_ */
-
-/** @} */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_exception.h b/bsp/synopsys/embarc/inc/arc/arc_exception.h
deleted file mode 100644
index e485b159c3..0000000000
--- a/bsp/synopsys/embarc/inc/arc/arc_exception.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
- * \brief header file of exception and interrupt management module
- */
-
-#ifndef _ARC_HAL_EXCEPTION_H_
-#define _ARC_HAL_EXCEPTION_H_
-
-#include "inc/embARC_toolchain.h"
-#include "inc/arc/arc.h"
-#include "inc/arc/arc_builtin.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \addtogroup ARC_HAL_EXCEPTION_CPU
- * @{
- * \todo need a conf.h from application or board to define the
- * features of processor, such as number of exception, code
- * density and FIQ.
- */
-#ifndef NUM_EXC_CPU
-#define NUM_EXC_CPU	16	/*!< number of CPU exceptions */
-#endif
-
-#ifndef NUM_EXC_INT
-#define NUM_EXC_INT	9	/*!< number of interrupt exceptions, defined by users*/
-#endif
-
-#define NUM_EXC_ALL	(NUM_EXC_CPU + NUM_EXC_INT) /*!< total number of exceptions */
-
-
-
-#ifdef ARC_FEATURE_SEC_PRESENT
-typedef struct int_exc_frame {
-	uint32_t erbta;
-
-	uint32_t r30;	/* r30 is useless, skipped? */
-	uint32_t ilink;	/* r29 is useless, skipped?*/
-	/* r28 is sp, saved other place */
-	uint32_t fp;	/* r27 */
-	uint32_t gp;	/* r26 */
-
-	uint32_t r12;
-
-	uint32_t lp_end, lp_start, lp_count;
-
-#ifdef ARC_FEATURE_CODE_DENSITY
-	uint32_t ei, ldi, jli;
-#endif
-
-	uint32_t r0, r1, r2, r3;
-#ifndef ARC_FEATURE_RF16
-	uint32_t r4, r5, r6, r7, r8, r9;
-#endif
-	uint32_t r10, r11;
-
-	uint32_t blink;	/* r31 */
-	uint32_t ret;
-	uint32_t sec_stat;
-	uint32_t status32;
-} EMBARC_PACKED INT_EXC_FRAME;
-#else
-typedef struct int_exc_frame {
-	uint32_t erbta;
-
-	uint32_t r30;	/* r30 is useless, skipped? */
-	uint32_t ilink;	/* r29 is useless, skipped?*/
-	/* r28 is sp, saved other place */
-	uint32_t fp;	/* r27 */
-	uint32_t gp;	/* r26 */
-
-	uint32_t r12;
-
-	uint32_t r0, r1, r2, r3;
-#ifndef ARC_FEATURE_RF16
-	uint32_t r4, r5, r6, r7, r8, r9;
-#endif
-	uint32_t r10, r11;
-
-	uint32_t blink;	/* r31 */
-
-	uint32_t lp_end, lp_start, lp_count;
-
-#ifdef ARC_FEATURE_CODE_DENSITY
-	uint32_t ei, ldi, jli;
-#endif
-
-	uint32_t ret;
-	uint32_t status32;
-} EMBARC_PACKED INT_EXC_FRAME;
-#endif
-
-typedef struct callee_frame {
-#ifndef ARC_FEATURE_RF16
-	uint32_t r25;
-	uint32_t r24;
-	uint32_t r23;
-	uint32_t r22;
-	uint32_t r21;
-	uint32_t r20;
-	uint32_t r19;
-	uint32_t r18;
-	uint32_t r17;
-	uint32_t r16;
-#endif
-	uint32_t r15;
-	uint32_t r14;
-	uint32_t r13;
-} EMBARC_PACKED CALLEE_FRAME;
-
-typedef struct processor_frame {
-	CALLEE_FRAME callee_regs;
-	INT_EXC_FRAME exc_frame;
-} EMBARC_PACKED PROCESSOR_FRAME;
-
-#define ARC_PROCESSOR_FRAME_SIZE	(sizeof(PROCESSOR_FRAME) / sizeof(uint32_t))
-#define ARC_EXC_FRAME_SIZE		(sizeof(INT_EXC_FRAME) / sizeof(uint32_t))
-#define ARC_CALLEE_FRAME_SIZE		(sizeof(CALLEE_FRAME) / sizeof(uint32_t))
-
-
-extern uint32_t exc_nest_count;
-
-/**
- * \brief write the exception vector base
- *
- * \param[in] vec_base the target vector base
- */
-Inline void arc_vector_base_write(const void * vec_base)
-{
-	_arc_aux_write(AUX_INT_VECT_BASE, (uint32_t)vec_base);
-}
-
-/**
- * \brief read current exception vector base
- *
- * \returns exception vector base (uint32_t)
- */
-Inline uint32_t arc_vector_base_read(void)
-{
-	return _arc_aux_read(AUX_INT_VECT_BASE);
-}
-
-/**
- * \brief  sense whether in exc/interrupt processing
- *
- * \retval 0	not in exc/interrupt processing
- * \retval 1	in exc/interrupt processing
- */
-Inline uint32_t exc_sense(void)
-{
-	return (exc_nest_count > 0U);
-}
-
-/** @}*/
-
-/**
- * \addtogroup ARC_HAL_EXCEPTION_INTERRUPT
- * @{
- */
-#ifndef INT_PRI_MIN
-#define INT_PRI_MIN	(-2)		/*!< the minimum interrupt priority */
-#endif
-
-#define INT_PRI_MAX (-1)		/*!< the maximum interrupt priority */
-/**
- * \brief disable the specific interrupt
- *
- * \param[in] intno interrupt number
- */
-Inline void arc_int_disable(const uint32_t intno)
-{
-	_arc_aux_write(AUX_IRQ_SELECT, intno);
-	_arc_aux_write(AUX_IRQ_ENABLE, 0);
-}
-
-/**
- * \brief  enable the specific int
- *
- * \param[in] intno interrupt number
- */
-Inline void arc_int_enable(const uint32_t intno)
-{
-	_arc_aux_write(AUX_IRQ_SELECT, intno);
-	_arc_aux_write(AUX_IRQ_ENABLE, 1);
-}
-
-/**
- * \brief  check whether the specific int is enabled
- *
- * \param[in] intno interrupt number
- * \return 0 disabled, 1 enabled
- */
-Inline uint32_t arc_int_enabled(const uint32_t intno)
-{
-	_arc_aux_write(AUX_IRQ_SELECT, intno);
-	return _arc_aux_read(AUX_IRQ_ENABLE);
-}
-
-/**
- * \brief  get the interrupt priority mask
- *
- * \returns interrupt priority mask, negative num
- */
-Inline uint32_t arc_int_ipm_get(void)
-{
-	return ((_arc_aux_read(AUX_STATUS32) >> 1) & 0x0f);
-}
-
-/**
- * \brief  set the interrupt priority mask
- *
- * \param[in] intpri interrupt priority
- */
-Inline void arc_int_ipm_set(uint32_t intpri)
-{
-	volatile uint32_t status;
-	status = _arc_aux_read(AUX_STATUS32) & ~0x1e;
-
-	status = status | ((intpri << 1) & 0x1e);
-	/* sr cannot write AUX_STATUS32 */
-	Asm("kflag %0"::"ir"(status));
-}
-
-/**
- * \brief  get current interrupt priority mask
- *
- * \param[in] intno interrupt number
- */
-Inline uint32_t arc_int_pri_get(const uint32_t intno)
-{
-	_arc_aux_write(AUX_IRQ_SELECT, intno);
-	return _arc_aux_read(AUX_IRQ_PRIORITY);
-}
-
-/**
- * \brief set interrupt priority
- *
- * \param[in] intno interrupt number
- * \param[in] intpri interrupt priority
- */
-Inline void arc_int_pri_set(const uint32_t intno, uint32_t intpri)
-{
-	_arc_aux_write(AUX_IRQ_SELECT, intno);
-	_arc_aux_write(AUX_IRQ_PRIORITY, intpri | (_arc_aux_read(AUX_IRQ_PRIORITY) & 0xfffffff0));
-}
-
-/**
- * \brief set interrupt secure or not secure
- *
- * \param[in] intno interrupt number
- * \param[in] secure, 0 for normal, >0 for secure
- */
-Inline void arc_int_secure_set(const uint32_t intno, uint32_t secure)
-{
-
-	_arc_aux_write(AUX_IRQ_SELECT, intno);
-
-	if (secure) {
-		_arc_aux_write(AUX_IRQ_PRIORITY, _arc_aux_read(AUX_IRQ_PRIORITY) |
-			(1 << AUX_IRQ_PRIORITY_BIT_S));
-	} else {
-		_arc_aux_write(AUX_IRQ_PRIORITY, _arc_aux_read(AUX_IRQ_PRIORITY) & 0xf);
-	}
-
-}
-
-/**
- * \brief  probe the pending status of interrupt
- *
- * \param[in] intno interrupt number
- *
- * \returns 1 pending, 0 no pending
- */
-Inline uint32_t arc_int_probe(const uint32_t intno)
-{
-	_arc_aux_write(AUX_IRQ_SELECT, intno);
-	return _arc_aux_read(AUX_IRQ_PENDING);
-}
-
-/**
- * \brief  trigger the interrupt in software
- *
- * \param[in] intno interrupt number
- */
-Inline void arc_int_sw_trigger(const uint32_t intno)
-{
-	_arc_aux_write(AUX_IRQ_HINT, intno);
-}
-
-/**
- * \brief  config the interrupt level triggered or pulse triggered
- *
- * \param[in] intno interrupt number
- * \param[in] level, 0-level trigger, 1-pluse triggered
- */
-Inline void arc_int_level_config(const uint32_t intno, const uint32_t level)
-{
-	_arc_aux_write(AUX_IRQ_SELECT, intno);
-	_arc_aux_write(AUX_IRQ_TRIGGER, level);
-}
-
-/**
- * \brief  lock cpu, disable interrupts
- */
-Inline void arc_lock(void)
-{
-	Asm("clri");
-	Asm("":::"memory");
-}
-
-/**
- * \brief  unlock cpu, enable interrupts to happen
- */
-Inline void arc_unlock(void)
-{
-	Asm("":::"memory");
-	Asm("seti");
-}
-
-/**
- * \brief  lock cpu and staus
- *
- * \returns cpu status
- */
-Inline uint32_t arc_lock_save(void)
-{
-	return _arc_clri();
-}
-
-/**
- * \brief  unlock cpu with the specific status
- *
- * \param[in] status  cpu status saved by cpu_lock_save
- */
-Inline void arc_unlock_restore(const uint32_t status)
-{
-	_arc_seti(status);
-}
-/** @}*/
-
-/**
- * \addtogroup ARC_HAL_EXCEPTION_CPU
- * @{
- */
-/**
- * \typedef EXC_ENTRY
- * \brief  the data type for exception entry
- */
-typedef void (*EXC_ENTRY) (void);
-/**
- * \typedef EXC_HANDLER
- * \brief  the data type for exception handler
- */
-typedef	void (*EXC_HANDLER) (void *exc_frame);
-/** @}*/
-
-
-/**
- * \ingroup ARC_HAL_EXCEPTION_INTERRUPT
- * \typedef INT_HANDLER
- * \brief  the data type for interrupt handler
- */
-typedef void (*INT_HANDLER) (void *ptr);
-
-extern EXC_ENTRY exc_entry_table[NUM_EXC_ALL];
-extern EXC_HANDLER exc_int_handler_table[NUM_EXC_ALL];
-
-/** \ingroup ARC_HAL_EXCEPTION_CPU
- * @{
- */
-/**
- * \fn _arc_reset
- * \brief the reset entry
- */
-extern void _arc_reset(void);
-/**
- * \fn exc_entry_cpu
- * \brief the default CPU exception entry
- */
-extern void exc_entry_cpu(void);
-
-/**
- * \fn exc_entry_firq
- * \brief the fast interrupt exception entry
- */
-extern void exc_entry_firq(void);
-/**
- * \fn exc_entry_int
- * \brief the interrupt exception entry
- */
-extern void exc_entry_int(void);
-/** @}*/
-
-/* excetpion related apis */
-extern void exc_int_init(void);
-extern int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY entry);
-extern EXC_ENTRY exc_entry_get(const uint32_t excno);
-extern int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER handler);
-extern EXC_HANDLER exc_handler_get(const uint32_t excno);
-
-/* interrupt related apis */
-extern int32_t int_disable(const uint32_t intno);
-extern int32_t int_enable(const uint32_t intno);
-extern int32_t int_enabled(const uint32_t intno);
-extern int32_t int_ipm_get(void);
-extern int32_t int_ipm_set(int32_t intpri);
-extern int32_t int_pri_get(const uint32_t intno);
-extern int32_t int_pri_set(const uint32_t intno, int32_t intpri);
-extern int32_t int_probe(const uint32_t intno);
-extern int32_t int_sw_trigger(const uint32_t intno);
-extern int32_t int_level_config(const uint32_t intno, const uint32_t level);
-extern void cpu_lock(void);
-extern void cpu_unlock(void);
-extern uint32_t cpu_lock_save(void);
-extern void cpu_unlock_restore(const uint32_t status);
-extern int32_t int_handler_install(const uint32_t intno, INT_HANDLER handler);
-extern INT_HANDLER int_handler_get(const uint32_t intno);
-extern int32_t int_secure_set(const uint32_t intno, uint32_t secure);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ARC_HAL_EXCEPTION_H_*/
diff --git a/bsp/synopsys/embarc/inc/arc/arc_feature_config.h b/bsp/synopsys/embarc/inc/arc/arc_feature_config.h
deleted file mode 100644
index 87b1913df5..0000000000
--- a/bsp/synopsys/embarc/inc/arc/arc_feature_config.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2016-09-08
- * \author Huaqi Fang(Huaqi.Fang@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_MISC
- * \brief header file for arc feature configuration
- */
-
-/**
- * \addtogroup ARC_HAL_MISC
- * @{
- */
-
-#ifndef _ARC_FEATURE_CONFIG_H_
-#define _ARC_FEATURE_CONFIG_H_
-
-// Enable core_config.h in EMSK OSP
-//#ifdef EMBARC_TCF_GENERATED
-#include "arc_core_config.h"
-//#endif
-
-/** ARC baseline instruction set version number */
-#if !defined(_ARCVER)
-#if defined(core_config_cir_identity_arcver)
-#define _ARCVER				core_config_cir_identity_arcver
-#else
-#define _ARCVER				0x42
-#endif
-#endif
-
-/** ARC CPU Clock Frequency in Hz unit */
-#if !defined(ARC_FEATURE_CPU_CLOCK_FREQ)
-#if defined(core_config_clock_speed)
-#define ARC_FEATURE_CPU_CLOCK_FREQ	(core_config_clock_speed*1000000)
-#endif
-#endif
-
-/** ARC PC size */
-#if !defined(ARC_FEATURE_PC_SIZE)
-#if defined(core_config_pc_size)
-#define ARC_FEATURE_PC_SIZE		core_config_pc_size
-#else
-#define ARC_FEATURE_PC_SIZE		32
-#endif
-#endif
-
-/** ARC LPC size */
-#if !defined(ARC_FEATURE_LPC_SIZE)
-#if defined(core_config_lpc_size)
-#define ARC_FEATURE_LPC_SIZE		core_config_lpc_size
-#else
-#define ARC_FEATURE_LPC_SIZE		32
-#endif
-#endif
-
-/** ARC Addr size */
-#if !defined(ARC_FEATURE_ADDR_SIZE)
-#if defined(core_config_addr_size)
-#define ARC_FEATURE_ADDR_SIZE		core_config_addr_size
-#else
-#define ARC_FEATURE_ADDR_SIZE		32
-#endif
-#endif
-
-/** ARC Endian/Byte Order */
-#define ARC_FEATURE_LITTLE_ENDIAN	1234
-#define ARC_FEATURE_BIG_ENDIAN		4321
-
-#if !defined(ARC_FEATURE_BYTE_ORDER)
-#if defined(core_config_bcr_isa_config_b)
-#if core_config_bcr_isa_config_b == 0
-#define ARC_FEATURE_BYTE_ORDER		ARC_FEATURE_LITTLE_ENDIAN
-#else
-#define ARC_FEATURE_BYTE_ORDER		ARC_FEATURE_BIG_ENDIAN
-#endif
-#else
-#define ARC_FEATURE_BYTE_ORDER		ARC_FEATURE_LITTLE_ENDIAN
-#endif
-#endif
-
-/** Reduced register option, if enabled, ARC_FEATURE_RF16 will be defined */
-#if !defined(ARC_FEATURE_RF16)
-#if defined(core_config_bcr_rf_build_e) && core_config_bcr_rf_build_e == 1
-#define ARC_FEATURE_RF16
-#endif
-#endif
-
-/** Unaligned access option, if enabled, ARC_FEATURE_UNALIGNED will be defined */
-#if !defined(ARC_FEATURE_UNALIGNED)
-#if defined(core_config_unaligned) && core_config_unaligned == 1
-#define ARC_FEATURE_UNALIGNED
-#endif
-#endif
-
-
-/** Code density option, if enabled, ARC_FEATURE_CODE_DENSITY will be defined */
-#if !defined(ARC_FEATURE_CODE_DENSITY)
-#if defined(core_config_code_density) && core_config_code_density == 1
-#define ARC_FEATURE_CODE_DENSITY
-#endif
-#endif
-
-/** The number of register file banks */
-#if !defined(ARC_FEATURE_RGF_NUM_BANKS)
-#if defined(core_config_rgf_num_banks)
-#define ARC_FEATURE_RGF_NUM_BANKS	core_config_rgf_num_banks
-#else
-#define ARC_FEATURE_RGF_NUM_BANKS	1
-#endif
-#endif
-
-/** The number of registers replicated per register bank */
-#if !defined(ARC_FEATURE_RGF_BANKED_REGS)
-#if defined(core_config_rgf_banked_regs)
-#define ARC_FEATURE_RGF_BANKED_REGS	core_config_rgf_banked_regs
-#endif
-#endif
-
-/** Interrupt unit presence */
-#if !defined(ARC_FEATURE_INTERRUPTS_PRESENT)
-#if defined(core_config_interrupts_present)
-#define ARC_FEATURE_INTERRUPTS_PRESENT	core_config_interrupts_present
-#endif
-#endif
-
-/** FIRQ_OPTION configuration option, 1 for enabled, 0 for disabled */
-#if !defined(ARC_FEATURE_FIRQ)
-#if defined(core_config_bcr_irq_build_f)
-#define ARC_FEATURE_FIRQ		core_config_bcr_irq_build_f
-#else
-#define ARC_FEATURE_FIRQ		0
-#endif
-#endif
-
-/** The number of interrupts */
-#if !defined(NUM_EXC_INT)
-#if defined(core_config_interrupts_number)
-#define NUM_EXC_INT			core_config_interrupts_number
-#endif
-#endif
-
-/** The number of external interrupts */
-#if !defined(NUM_EXC_EXT_INT)
-#if defined(core_config_interrupts_externals)
-#define NUM_EXC_EXT_INT			core_config_interrupts_externals
-#endif
-#endif
-
-/** The interrupt priority levels */
-#if !defined(INT_PRI_MIN)
-#if defined(core_config_interrupts_priorities)
-#define INT_PRI_MIN			(-core_config_interrupts_priorities)
-#endif
-#endif
-
-// ARC TIMER_BUILD
-/** Timer0 present or not */
-#if !defined(ARC_FEATURE_TIMER0_PRESENT)
-#if defined(core_config_timer0)
-#define ARC_FEATURE_TIMER0_PRESENT	core_config_timer0
-#define ARC_FEATURE_TIMER0_LEVEL	(core_config_timer0_level-core_config_interrupts_priorities)
-#define ARC_FEATURE_TIMER0_VECTOR	core_config_timer0_vector
-#endif
-#endif
-
-/** Timer1 present or not */
-#if !defined(ARC_FEATURE_TIMER1_PRESENT)
-#if defined(core_config_timer1)
-#define ARC_FEATURE_TIMER1_PRESENT	core_config_timer1
-#define ARC_FEATURE_TIMER1_LEVEL	(core_config_timer1_level-core_config_interrupts_priorities)
-#define ARC_FEATURE_TIMER1_VECTOR	core_config_timer1_vector
-#endif
-#endif
-
-/** Secure Timer0 present or not */
-#if !defined(ARC_FEATURE_SEC_TIMER0_PRESENT)
-#if defined(core_config_sec_timer0)
-#define ARC_FEATURE_SEC_TIMER0_PRESENT	core_config_sec_timer0
-#define ARC_FEATURE_SEC_TIMER0_LEVEL	(core_config_sec_timer0_level-core_config_interrupts_priorities)
-#define ARC_FEATURE_SEC_TIMER0_VECTOR	20
-#endif
-#endif
-
-/** Secure Timer1 present or not */
-#if !defined(ARC_FEATURE_SEC_TIMER1_PRESENT)
-#if defined(core_config_sec_timer1)
-#define ARC_FEATURE_SEC_TIMER1_PRESENT	core_config_sec_timer1
-#define ARC_FEATURE_SEC_TIMER1_LEVEL	(core_config_sec_timer1_level-core_config_interrupts_priorities)
-#define ARC_FEATURE_SEC_TIMER1_VECTOR	21
-#endif
-#endif
-
-
-/** 64bit RTC present or not */
-#if !defined(ARC_FEATURE_RTC_PRESENT)
-#if defined(core_config_rtc)
-#define ARC_FEATURE_RTC_PRESENT		core_config_rtc
-#endif
-#endif
-
-// Memory related definitions
-/** ICCM Presence, base address and size */
-#if !defined(ARC_FEATURE_ICCM_PRESENT)
-#if defined(core_config_iccm_present) && core_config_iccm_present == 1
-#define ARC_FEATURE_ICCM_PRESENT	1
-#define ARC_FEATURE_ICCM_BASE		core_config_iccm_base
-#define ARC_FEATURE_ICCM_SIZE		core_config_iccm_size
-#endif
-#endif
-
-/** ICCM0 Presence, base address and size */
-#if !defined(ARC_FEATURE_ICCM0_PRESENT)
-#if defined(core_config_iccm0_present) && core_config_iccm0_present == 1
-#define ARC_FEATURE_ICCM0_PRESENT	1
-#define ARC_FEATURE_ICCM0_BASE		core_config_iccm0_base
-#define ARC_FEATURE_ICCM0_SIZE		core_config_iccm0_size
-#endif
-#endif
-
-/** ICCM1 Presence, base address and size */
-#if !defined(ARC_FEATURE_ICCM1_PRESENT)
-#if defined(core_config_iccm1_present) && core_config_iccm1_present == 1
-#define ARC_FEATURE_ICCM1_PRESENT	1
-#define ARC_FEATURE_ICCM1_BASE		core_config_iccm1_base
-#define ARC_FEATURE_ICCM1_SIZE		core_config_iccm1_size
-#endif
-#endif
-
-/** DCCM Presence, base address and size */
-#if !defined(ARC_FEATURE_DCCM_PRESENT)
-#if defined(core_config_dccm_present) && core_config_dccm_present == 1
-#define ARC_FEATURE_DCCM_PRESENT	1
-#define ARC_FEATURE_DCCM_BASE		core_config_dccm_base
-#define ARC_FEATURE_DCCM_SIZE		core_config_dccm_size
-#ifdef core_config_dccm_interleave
-#define ARC_FEATURE_DCCM_INTERLEAVE	core_config_dccm_interleave
-#endif
-#endif
-#endif
-
-/** Peripheral memory region(DMP) base address, if dmp configured, this macro will be defined as base address */
-#if !defined(ARC_FEATURE_DMP_PERIPHERAL)
-#if defined(core_config_cir_dmp_peripheral)
-#define ARC_FEATURE_DMP_PERIPHERAL	core_config_cir_dmp_peripheral
-#endif
-#endif
-
-/** MPU options */
-#if !defined(ARC_FEATURE_MPU_PRESENT)
-#if defined(core_config_mpu_present) && core_config_mpu_present == 1
-#define ARC_FEATURE_MPU_PRESENT		1
-#define ARC_FEATURE_MPU_VERSION		core_config_bcr_mpu_build_version
-#define ARC_FEATURE_MPU_REGIONS		core_config_mpu_regions
-#ifdef core_config_bcr_mpu_build_i
-#define ARC_FEATURE_MPU_BUILD_I		core_config_bcr_mpu_build_i
-#endif
-#ifdef core_config_bcr_mpu_build_s
-#define ARC_FEATURE_MPU_BUILD_S		core_config_bcr_mpu_build_s
-#endif
-#endif
-#endif
-
-/** Secure BCR SEC_BUILD BCR */
-#if !defined(ARC_FEATURE_SEC_PRESENT)
-#if defined(core_config_bcr_sec_build)
-#define ARC_FEATURE_SEC_PRESENT		1
-#define ARC_FEATURE_SEC_VERSION		core_config_bcr_sec_build_version
-#define	ARC_FEATURE_SEC_BUILD_DSM	core_config_bcr_sec_build_dsm
-#define	ARC_FEATURE_SEC_BUILD_NSM	core_config_bcr_sec_build_nsm
-#define	ARC_FEATURE_SEC_BUILD_I1SM	core_config_bcr_sec_build_i1sm
-#define	ARC_FEATURE_SEC_BUILD_I0SM	core_config_bcr_sec_build_i0sm
-#define	ARC_FEATURE_SEC_BUILD_S		core_config_bcr_sec_build_s
-#define	ARC_FEATURE_SEC_BUILD_EI	core_config_bcr_sec_build_ei
-#define	ARC_FEATURE_SEC_BUILD_ED	core_config_bcr_sec_build_ed
-#endif
-#endif
-
-#if !defined(ARC_FEATURE_SEC_MODES)
-#if defined(core_config_sec_modes)
-#define ARC_FEATURE_SEC_MODES		core_config_sec_modes
-#endif
-#endif
-
-/** Data Cache options */
-#if !defined(ARC_FEATURE_DCACHE_PRESENT)
-#if defined(core_config_dcache_present) && core_config_dcache_present == 1
-#define ARC_FEATURE_DCACHE_PRESENT		1
-#define ARC_FEATURE_DCACHE_BUILD		core_config_bcr_d_cache_build
-#define ARC_FEATURE_DCACHE_BUILD_VERSION	core_config_bcr_d_cache_build_version
-#define ARC_FEATURE_DCACHE_BUILD_ASSOC		core_config_bcr_d_cache_build_assoc
-#define ARC_FEATURE_DCACHE_BUILD_CAPACITY	core_config_bcr_d_cache_build_capacity
-#define ARC_FEATURE_DCACHE_BUILD_BSIZE		core_config_bcr_d_cache_build_bsize
-#define ARC_FEATURE_DCACHE_BUILD_FL		core_config_bcr_d_cache_build_fl
-#define ARC_FEATURE_DCACHE_BUILD_U		core_config_bcr_d_cache_build_u
-#define ARC_FEATURE_DCACHE_SIZE			core_config_dcache_size
-#define ARC_FEATURE_DCACHE_LINE_SIZE		core_config_dcache_line_size
-#define ARC_FEATURE_DCACHE_WAYS			core_config_dcache_ways
-#define ARC_FEATURE_DCACHE_FEATURE		core_config_dcache_feature
-#endif
-#endif
-
-/** Instruction Cache options */
-#if !defined(ARC_FEATURE_ICACHE_PRESENT)
-#if defined(core_config_icache_present) && core_config_icache_present == 1
-#define ARC_FEATURE_ICACHE_PRESENT		1
-#define ARC_FEATURE_ICACHE_BUILD		core_config_bcr_i_cache_build
-#define ARC_FEATURE_ICACHE_BUILD_VERSION	core_config_bcr_i_cache_build_version
-#define ARC_FEATURE_ICACHE_BUILD_ASSOC		core_config_bcr_i_cache_build_assoc
-#define ARC_FEATURE_ICACHE_BUILD_CAPACITY	core_config_bcr_i_cache_build_capacity
-#define ARC_FEATURE_ICACHE_BUILD_BSIZE		core_config_bcr_i_cache_build_bsize
-#define ARC_FEATURE_ICACHE_BUILD_FL		core_config_bcr_i_cache_build_fl
-#define ARC_FEATURE_ICACHE_BUILD_D		core_config_bcr_i_cache_build_d
-#define ARC_FEATURE_ICACHE_SIZE			core_config_icache_size
-#define ARC_FEATURE_ICACHE_LINE_SIZE		core_config_icache_line_size
-#define ARC_FEATURE_ICACHE_WAYS			core_config_icache_ways
-#define ARC_FEATURE_ICACHE_FEATURE		core_config_icache_feature
-#endif
-#endif
-
-/** ARC uDMA options */
-#if !defined(ARC_FEATURE_DMAC)
-#if defined(core_config_dmac)
-#define ARC_FEATURE_DMAC		core_config_dmac
-#define CORE_DMAC_CHANNELS		core_config_dmac_channels
-#define CORE_DMAC_REGISTERS		core_config_dmac_registers
-#if core_config_bcr_dmac_build_int_cfg == 2 && core_config_bcr_dmac_build_int_cfg == 4
-#define DMA_MULTI_IRQ			1
-#else
-#define DMA_MULTI_IRQ			0
-#endif
-#define ARC_FEATURE_DMAC_PRESENT	core_config_dmac
-#define ARC_FEATURE_DMAC_VERSION	core_config_bcr_dmac_build_version
-#define ARC_FEATURE_DMAC_CHANNELS	core_config_dmac_channels
-#define ARC_FEATURE_DMAC_REGISTERS	core_config_dmac_registers
-#define ARC_FEATURE_DMAC_INT_CFG	core_config_bcr_dmac_build_int_cfg
-#define ARC_FEATURE_DMAC_FIFO_DEPTH	core_config_dmac_fifo_depth
-
-#ifdef ARC_FEATURE_SEC_TIMER0_PRESENT
-#define DMA_IRQ_NUM_START		22
-#define ARC_FEATURE_DMAC_VECTOR_START	22
-#else
-#define DMA_IRQ_NUM_START		20
-#define ARC_FEATURE_DMAC_VECTOR_START	20
-#endif
-
-#endif
-#endif
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef ARC_FEATURE_UNALIGNED
-#define STATUS32_RESET_VALUE		(1<<19)
-#else
-#define STATUS32_RESET_VALUE		(0)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ARC_FEATURE_CONFIG_H_ */
-
-/** @} */
diff --git a/bsp/synopsys/embarc/inc/arc/arc_timer.h b/bsp/synopsys/embarc/inc/arc/arc_timer.h
deleted file mode 100644
index b5237f31a9..0000000000
--- a/bsp/synopsys/embarc/inc/arc/arc_timer.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-07-15
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup ARC_HAL_MISC_TIMER
- * \brief header file of ARC internal timer
- */
-
-/**
- * \addtogroup ARC_HAL_MISC_TIMER
- * @{
- */
-
-#ifndef _ARC_HAL_TIMER_H_
-#define _ARC_HAL_TIMER_H_
-#include "inc/arc/arc.h"
-#include "inc/embARC_toolchain.h"
-
-/**
- * \name arc internal timers names
- * @{
- */
-#define TIMER_0		0 	/*!< macro name for arc internal timer 0 */
-#define TIMER_1		1 	/*!< macro name for arc internal timer 1 */
-#define TIMER_RTC	2 	/*!< macro name for arc internal RTC */
-
-/** @} */
-
-/**
- * \name bit definition of RTC CTRL reg
- * @{
- */
-
-#define TIMER_RTC_ENABLE	0x01	   /*!< enable RTC */
-#define TIMER_RTC_CLEAR		0x02	   /* clears the AUX_RTC_LOW and AUX_RTC_HIGH */
-#define TIMER_RTC_STATUS_A0	0x40000000 /*!< track bit of atomicity of reads of RTC */
-#define TIMER_RTC_STATUS_A1	0x80000000 /*!< track bit of atomicity of reads of RTC */
-
-/** @} */
-
-/**
- * \name bit definition of timer CTRL reg
- * @{
- */
-#define TIMER_CTRL_IE		(1 << 0)	/*!< Interrupt when count reaches limit */
-#define TIMER_CTRL_NH		(1 << 1)	/*!< Count only when CPU NOT halted */
-#define TIMER_CTRL_W		(1 << 2)	/*!< watchdog enable */
-#define TIMER_CTRL_IP		(1 << 3)	/*!< interrupt pending */
-
-/** @} */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern int32_t arc_timer_present(const uint32_t no);
-extern int32_t arc_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val);
-extern int32_t arc_timer_stop(const uint32_t no);
-extern int32_t arc_timer_current(const uint32_t no, void* val);
-extern int32_t arc_timer_int_clear(const uint32_t no);
-extern void arc_timer_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* _ARC_HAL_TIMER_H_ */
-/** }@*/
diff --git a/bsp/synopsys/embarc/inc/embARC_debug.h b/bsp/synopsys/embarc/inc/embARC_debug.h
deleted file mode 100644
index 092374622d..0000000000
--- a/bsp/synopsys/embarc/inc/embARC_debug.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2017, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2017.03
- * \date 2014-12-26
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup EMBARC_DEBUG
- * \brief necessary definitions of debug
- */
-
-#ifndef _EMBARC_DEBUG_H_
-#define _EMBARC_DEBUG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef EMBARC_PRINTF
-	#include "common/xprintf.h"
-	#define EMBARC_PRINTF xprintf
-#endif
-
-/*
- * if you want to use DBG or dbg_printf,
- * please define DEBUG or DBG_LESS or DBG_MORE before include embARC_debug.h
- * DEBUG: enable debug print
- * DBG_LESS: enable less debug msg
- * DBG_MORE: enable more debug msg
- **/
-
-#if defined(DEBUG)
-#if defined(DEBUG_HOSTLINK)
-#include <stdio.h>
-#define DBG(fmt, ...)	printf(fmt, ##__VA_ARGS__)
-#else
-#define DBG(fmt, ...)	EMBARC_PRINTF(fmt, ##__VA_ARGS__)
-#endif
-#else
-#define DBG(fmt, ...)
-#endif
-
-#define DBG_LESS_INFO	0x01    /* less debug  messages */
-#define DBG_MORE_INFO	0x02    /* more debug  messages */
-
-
-#if defined (DBG_LESS)
-#define DBG_TYPE		(DBG_LESS_INFO)
-#elif defined (DBG_MORE)
-#define DBG_TYPE		((DBG_LESS_INFO) | (DBG_MORE_INFO))
-#else
-#define DBG_TYPE 		0
-#endif
-
-#if DBG_TYPE > 0
-#define dbg_printf(type, fmt, ...) \
-		if (((type) & DBG_TYPE))  { EMBARC_PRINTF(fmt, ##__VA_ARGS__); }
-#else
-#define dbg_printf(type, fmt, ...)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* DEBUG_H_ */
diff --git a/bsp/synopsys/embarc/inc/embARC_error.h b/bsp/synopsys/embarc/inc/embARC_error.h
deleted file mode 100644
index 9bd9c318aa..0000000000
--- a/bsp/synopsys/embarc/inc/embARC_error.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-12-25
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	EMBARC_ERROR
- * \brief	header file to define common definitions error management
- */
-
-/**
- * \addtogroup	EMBARC_ERROR
- * @{
- */
-
-#ifndef _EMBARC_ERROR_H_
-#define _EMBARC_ERROR_H_
-
-#include <stdint.h>
-#include "inc/arc/arc_builtin.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**
- * \name	Main Error Code Definitions
- * @{
- */
-#define E_OK		(0)		/*!< ok */
-#define E_SYS		(-5)		/*!< system error */
-#define E_NOSPT		(-9)		/*!< unsupported features */
-#define E_RSFN		(-10)		/*!< reserved function code */
-#define E_RSATR		(-11)		/*!< reserved attribute */
-#define E_PAR		(-17)		/*!< parameter error */
-#define E_ID		(-18)		/*!< invalid ID number */
-#define E_CTX		(-25)		/*!< context error */
-#define E_MACV		(-26)		/*!< memory access violation */
-#define E_OACV		(-27)		/*!< object access violation */
-#define E_ILUSE		(-28)		/*!< illegal service call use */
-#define E_NOMEM		(-33)		/*!< insufficient memory */
-#define E_NOID		(-34)		/*!< no ID number available */
-#define E_NORES		(-35)		/*!< no resource available */
-#define E_OBJ		(-41)		/*!< object state error */
-#define E_NOEXS		(-42)		/*!< non-existent object */
-#define E_QOVR		(-43)		/*!< queue overflow */
-#define E_RLWAI		(-49)		/*!< forced release from waiting */
-#define E_TMOUT		(-50)		/*!< polling failure or timeout */
-#define E_DLT		(-51)		/*!< waiting object deleted */
-#define E_CLS		(-52)		/*!< waiting object state changed */
-#define E_WBLK		(-57)		/*!< non-blocking accepted */
-#define E_BOVR		(-58)		/*!< buffer overflow */
-#define E_OPNED		(-6)		/*!< device is opened */
-#define E_CLSED		(-7)		/*!< device is closed */
-/** @} end of name */
-
-/**
- * \name	Generate And Decompose Error Code
- * @{
- */
-#ifndef ERCD
-/** generate error code using main error code and sub error code */
-#define ERCD(mercd, sercd) \
-		((uint32_t)((((uint32_t) sercd) << 8) | (((uint32_t) mercd) & 0xffU)))
-#endif /* ERCD */
-
-#ifndef MERCD
-#ifdef INT8_MAX
-/** get main error code from error code */
-#define MERCD(ercd)		((uint32_t)((int8_t)(ercd)))
-#else /* INT8_MAX */
-/** get main error code from error code */
-#define MERCD(ercd)		((uint32_t)(((uint32_t) ercd) | ~0xffU))
-#endif /* INT8_MAX */
-#endif /* MERCD */
-
-#ifndef SERCD
-/** get sub error code from error code */
-#define SERCD(ercd)		((uint32_t)((ercd) >> 8))
-#endif /* SERCD */
-/** @} end of name */
-
-/**
- * \name	Check Error
- * @{
- */
-/**
- * \brief   check an expression to see if it is right, and when error
- * 	set the ercd, and goto exit_label
- * \param   EXPR	the expression that need to be checked (==0 failed)
- * \param   ERCD	MUST pass a variable to here to get the error code
- * \param   ERROR_CODE error code that pass to ERCD
- * \param   EXIT_LABEL a label to go when error happens
- */
-#define CHECK_EXP(EXPR, ERCD, ERROR_CODE, EXIT_LABEL) 	{	\
-		if (_arc_rarely(!(EXPR))) { 			\
-			ERCD = (ERROR_CODE);			\
-			goto EXIT_LABEL;			\
-		}						\
-	}
-/**
- * \brief   check an expression to see if it is right, and when error
- * 			directly goto exit_label
- * \param   EXPR       the expression that need to be checked (==0 failed)
- * \param   EXIT_LABEL a label to go when error happens
- * \retval
- */
-#define CHECK_EXP_NOERCD(EXPR, EXIT_LABEL) {			\
-		if (_arc_rarely(!(EXPR))) { 			\
-			goto EXIT_LABEL;			\
-		}						\
-	}
-/** check cnt bytes align, 1 for aligned, 0 for not-aligned */
-#define CHECK_ALIGN_BYTES(pointer, cnt)		((((uint32_t)(pointer)) & (cnt-1)) == 0)
-/** check 2 bytes align, 1 for aligned, 0 for not-aligned */
-#define CHECK_ALIGN_2BYTES(pointer)		((((uint32_t)(pointer)) & 0x1) == 0)
-/** check 4 bytes align, 1 for aligned, 0 for not-aligned */
-#define CHECK_ALIGN_4BYTES(pointer)		((((uint32_t)(pointer)) & 0x3) == 0)
-/** check 8 bytes align, 1 for aligned, 0 for not-aligned */
-#define CHECK_ALIGN_8BYTES(pointer)		((((uint32_t)(pointer)) & 0x7) == 0)
-/** @} end of name */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _EMBARC_ERROR_H_ */
-/** @} end of group EMBARC_ERROR */
diff --git a/bsp/synopsys/embarc/inc/embARC_toolchain.h b/bsp/synopsys/embarc/inc/embARC_toolchain.h
deleted file mode 100644
index 37aef66064..0000000000
--- a/bsp/synopsys/embarc/inc/embARC_toolchain.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * \version 2016.05
- * \date 2014-12-25
- * \author Wayne Ren(Wei.Ren@synopsys.com)
---------------------------------------------- */
-
-/**
- * \file
- * \ingroup	TOOLCHAIN
- * \brief toolchain dependent definitions
- */
-
-#include <stdint.h>	/* C99 standard lib */
-#include <limits.h>	/* C99 standard lib */
-#include <stddef.h>	/* C99 standard lib */
-#include <stdbool.h> 	/* C99 standard lib */
-
-#include "embARC_BSP_config.h"
-
-/**
- * \addtogroup TOOLCHAIN
- * @{
- */
-
-#ifndef _EMBARC_TOOLCHAIN_H_
-#define _EMBARC_TOOLCHAIN_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- *  macro definitions of compiler extend function
- */
-#ifndef __cplusplus				/* C++ supports inline */
-#if __STDC_VERSION__ < 199901L			/* C99 supports inline */
-#ifndef inline
-#define inline	__inline__			/* inline function */
-#endif
-#endif /* __STDC_VERSION__ < 199901L */
-#endif /* __cplusplus */
-
-#ifndef Inline
-#define Inline	static __inline__		/* inline function */
-#endif
-
-#ifndef __cplusplus				/* C++ supports asm */
-#ifndef asm
-#define asm	__asm__				/* inline asm */
-#endif
-#endif /* __cplusplus */
-
-#ifndef Asm
-#define Asm	__asm__ volatile		/* inline asm (no optimization) */
-#endif
-
-/* compiler attributes */
-#define EMBARC_FORCEINLINE	__attribute__((always_inline))
-#define EMBARC_NOINLINE		__attribute__((noinline))
-#define EMBARC_PACKED		__attribute__((packed))
-#define EMBARC_WEAK		__attribute__((weak))
-#define EMBARC_ALIAS(f)		__attribute__((weak, alias (#f)))
-#define EMBARC_LINKTO(f)	__attribute__((alias (#f)))
-#define EMBARC_NORETURN		__attribute__((noreturn))
-#define EMBARC_NAKED		__attribute__((naked))	/* function without return */
-#define EMBARC_ALIGNED(x)	__attribute__((aligned(x)))
-
-
-/* array count macro */
-#define EMBARC_ARRAY_COUNT(x) (sizeof(x)/sizeof(x[0]))
-
-/* convert macro argument to string */
-/* note: this needs one level of indirection, accomplished with the helper macro
- *       __EMBARC_TO_STRING */
-#define __EMBARC_TO_STRING(x) #x
-#define EMBARC_TO_STRING(x)   __EMBARC_TO_STRING(x)
-
-#if defined(__GNU__)
-/* GNU tool specific definitions */
-
-#elif defined(__MW__)
-/* Metaware tool specific definitions */
-/* Metaware toolchain related definitions */
-
-#else
-#error "unsupported toolchain"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _EMBARC_TOOLCHAIN_H_ */
-/** }@ */
diff --git a/bsp/synopsys/emsk_em9d/.config b/bsp/synopsys/emsk_em9d/.config
deleted file mode 100644
index 8451f5d956..0000000000
--- a/bsp/synopsys/emsk_em9d/.config
+++ /dev/null
@@ -1,403 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Configuration
-#
-
-#
-# RT-Thread Kernel
-#
-CONFIG_RT_NAME_MAX=8
-# CONFIG_RT_USING_SMP is not set
-CONFIG_RT_ALIGN_SIZE=4
-# CONFIG_RT_THREAD_PRIORITY_8 is not set
-CONFIG_RT_THREAD_PRIORITY_32=y
-# CONFIG_RT_THREAD_PRIORITY_256 is not set
-CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=100
-CONFIG_RT_USING_OVERFLOW_CHECK=y
-CONFIG_RT_USING_HOOK=y
-CONFIG_RT_USING_IDLE_HOOK=y
-CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=256
-# CONFIG_RT_USING_TIMER_SOFT is not set
-CONFIG_RT_DEBUG=y
-CONFIG_RT_DEBUG_COLOR=y
-# CONFIG_RT_DEBUG_INIT_CONFIG is not set
-# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
-# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
-# CONFIG_RT_DEBUG_IPC_CONFIG is not set
-# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
-# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
-# CONFIG_RT_DEBUG_MEM_CONFIG is not set
-# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
-# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
-# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
-
-#
-# Inter-Thread communication
-#
-CONFIG_RT_USING_SEMAPHORE=y
-CONFIG_RT_USING_MUTEX=y
-CONFIG_RT_USING_EVENT=y
-CONFIG_RT_USING_MAILBOX=y
-CONFIG_RT_USING_MESSAGEQUEUE=y
-# CONFIG_RT_USING_SIGNALS is not set
-
-#
-# Memory Management
-#
-CONFIG_RT_USING_MEMPOOL=y
-# CONFIG_RT_USING_MEMHEAP is not set
-# CONFIG_RT_USING_NOHEAP is not set
-CONFIG_RT_USING_SMALL_MEM=y
-# CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMTRACE is not set
-CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
-CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_INTERRUPT_INFO is not set
-CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40000
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
-
-#
-# RT-Thread Components
-#
-CONFIG_RT_USING_COMPONENTS_INIT=y
-# CONFIG_RT_USING_USER_MAIN is not set
-
-#
-# C++ features
-#
-# CONFIG_RT_USING_CPLUSPLUS is not set
-
-#
-# Command shell
-#
-CONFIG_RT_USING_FINSH=y
-CONFIG_FINSH_THREAD_NAME="tshell"
-CONFIG_FINSH_USING_HISTORY=y
-CONFIG_FINSH_HISTORY_LINES=5
-CONFIG_FINSH_USING_SYMTAB=y
-CONFIG_FINSH_USING_DESCRIPTION=y
-# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
-# CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
-CONFIG_FINSH_ARG_MAX=10
-
-#
-# Device virtual file system
-#
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
-# CONFIG_RT_USING_DFS_NFS is not set
-
-#
-# Device Drivers
-#
-CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_PIPE_BUFSZ=512
-CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
-# CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
-# CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
-CONFIG_RT_USING_PIN=y
-# CONFIG_RT_USING_ADC is not set
-# CONFIG_RT_USING_PWM is not set
-# CONFIG_RT_USING_MTD_NOR is not set
-# CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_MTD is not set
-# CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
-# CONFIG_RT_USING_WDT is not set
-# CONFIG_RT_USING_AUDIO is not set
-
-#
-# Using WiFi
-#
-# CONFIG_RT_USING_WIFI is not set
-
-#
-# Using USB
-#
-# CONFIG_RT_USING_USB_HOST is not set
-# CONFIG_RT_USING_USB_DEVICE is not set
-
-#
-# POSIX layer and C standard library
-#
-CONFIG_RT_USING_LIBC=y
-# CONFIG_RT_USING_PTHREADS is not set
-# CONFIG_RT_USING_POSIX is not set
-# CONFIG_RT_USING_MODULE is not set
-
-#
-# Network
-#
-
-#
-# Socket abstraction layer
-#
-CONFIG_RT_USING_SAL=y
-
-#
-# protocol stack implement
-#
-CONFIG_SAL_USING_LWIP=y
-CONFIG_SAL_USING_AT=y
-# CONFIG_SAL_USING_POSIX is not set
-CONFIG_SAL_SOCKETS_NUM=16
-CONFIG_SAL_PROTO_FAMILIES_NUM=4
-
-#
-# light weight TCP/IP stack
-#
-CONFIG_RT_USING_LWIP=y
-# CONFIG_RT_USING_LWIP141 is not set
-CONFIG_RT_USING_LWIP202=y
-# CONFIG_RT_USING_LWIP210 is not set
-# CONFIG_RT_USING_LWIP_IPV6 is not set
-CONFIG_RT_LWIP_IGMP=y
-CONFIG_RT_LWIP_ICMP=y
-# CONFIG_RT_LWIP_SNMP is not set
-CONFIG_RT_LWIP_DNS=y
-CONFIG_RT_LWIP_DHCP=y
-CONFIG_IP_SOF_BROADCAST=1
-CONFIG_IP_SOF_BROADCAST_RECV=1
-
-#
-# Static IPv4 Address
-#
-CONFIG_RT_LWIP_IPADDR="192.168.1.30"
-CONFIG_RT_LWIP_GWADDR="192.168.1.1"
-CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
-CONFIG_RT_LWIP_UDP=y
-CONFIG_RT_LWIP_TCP=y
-# CONFIG_RT_LWIP_RAW is not set
-# CONFIG_RT_LWIP_PPP is not set
-CONFIG_RT_MEMP_NUM_NETCONN=8
-CONFIG_RT_LWIP_PBUF_NUM=16
-CONFIG_RT_LWIP_RAW_PCB_NUM=4
-CONFIG_RT_LWIP_UDP_PCB_NUM=4
-CONFIG_RT_LWIP_TCP_PCB_NUM=4
-CONFIG_RT_LWIP_TCP_SEG_NUM=40
-CONFIG_RT_LWIP_TCP_SND_BUF=8196
-CONFIG_RT_LWIP_TCP_WND=8196
-CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
-CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
-CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
-# CONFIG_LWIP_NO_RX_THREAD is not set
-# CONFIG_LWIP_NO_TX_THREAD is not set
-CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
-CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
-CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
-# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
-CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
-CONFIG_SO_REUSE=1
-CONFIG_LWIP_SO_RCVTIMEO=1
-CONFIG_LWIP_SO_SNDTIMEO=1
-CONFIG_LWIP_SO_RCVBUF=1
-# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
-CONFIG_LWIP_NETIF_LOOPBACK=0
-# CONFIG_RT_LWIP_STATS is not set
-# CONFIG_RT_LWIP_DEBUG is not set
-
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
-
-#
-# AT commands
-#
-CONFIG_RT_USING_AT=y
-# CONFIG_AT_DEBUG is not set
-# CONFIG_AT_USING_SERVER is not set
-CONFIG_AT_USING_CLIENT=y
-CONFIG_AT_CLIENT_NUM_MAX=1
-CONFIG_AT_USING_SOCKET=y
-CONFIG_AT_USING_CLI=y
-# CONFIG_AT_PRINT_RAW_CMD is not set
-CONFIG_AT_SW_VERSION_NUM=0x10200
-# CONFIG_LWIP_USING_DHCPD is not set
-
-#
-# VBUS(Virtual Software BUS)
-#
-# CONFIG_RT_USING_VBUS is not set
-
-#
-# Utilities
-#
-# CONFIG_RT_USING_LOGTRACE is not set
-# CONFIG_RT_USING_RYM is not set
-# CONFIG_RT_USING_ULOG is not set
-# CONFIG_RT_USING_UTEST is not set
-
-#
-# RT-Thread online packages
-#
-
-#
-# IoT - internet of things
-#
-# CONFIG_PKG_USING_PAHOMQTT is not set
-# CONFIG_PKG_USING_WEBCLIENT is not set
-# CONFIG_PKG_USING_MONGOOSE is not set
-# CONFIG_PKG_USING_WEBTERMINAL is not set
-# CONFIG_PKG_USING_CJSON is not set
-# CONFIG_PKG_USING_JSMN is not set
-# CONFIG_PKG_USING_LJSON is not set
-# CONFIG_PKG_USING_EZXML is not set
-# CONFIG_PKG_USING_NANOPB is not set
-
-#
-# Wi-Fi
-#
-
-#
-# Marvell WiFi
-#
-# CONFIG_PKG_USING_WLANMARVELL is not set
-
-#
-# Wiced WiFi
-#
-# CONFIG_PKG_USING_WLAN_WICED is not set
-# CONFIG_PKG_USING_COAP is not set
-# CONFIG_PKG_USING_NOPOLL is not set
-# CONFIG_PKG_USING_NETUTILS is not set
-CONFIG_PKG_USING_AT_DEVICE=y
-CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device"
-CONFIG_PKG_AT_INIT_BY_THREAD=y
-# CONFIG_AT_DEVICE_M26 is not set
-# CONFIG_AT_DEVICE_EC20 is not set
-CONFIG_AT_DEVICE_ESP8266=y
-# CONFIG_AT_DEVICE_NOT_SELECTED is not set
-CONFIG_AT_DEVICE_SOCKETS_NUM=5
-CONFIG_AT_DEVICE_NAME="uart0"
-CONFIG_AT_DEVICE_RECV_BUFF_LEN=512
-CONFIG_AT_DEVICE_WIFI_SSID="embarc"
-CONFIG_AT_DEVICE_WIFI_PASSWORD="qazwsxedc"
-CONFIG_PKG_USING_AT_DEVICE_LATEST_VERSION=y
-# CONFIG_PKG_USING_AT_DEVICE_V100 is not set
-# CONFIG_PKG_USING_AT_DEVICE_V110 is not set
-CONFIG_PKG_AT_DEVICE_VER="latest"
-
-#
-# IoT Cloud
-#
-# CONFIG_PKG_USING_ONENET is not set
-# CONFIG_PKG_USING_GAGENT_CLOUD is not set
-# CONFIG_PKG_USING_ALI_IOTKIT is not set
-# CONFIG_PKG_USING_AZURE is not set
-
-#
-# security packages
-#
-# CONFIG_PKG_USING_MBEDTLS is not set
-# CONFIG_PKG_USING_libsodium is not set
-# CONFIG_PKG_USING_TINYCRYPT is not set
-
-#
-# language packages
-#
-# CONFIG_PKG_USING_LUA is not set
-# CONFIG_PKG_USING_JERRYSCRIPT is not set
-# CONFIG_PKG_USING_MICROPYTHON is not set
-
-#
-# multimedia packages
-#
-# CONFIG_PKG_USING_OPENMV is not set
-# CONFIG_PKG_USING_MUPDF is not set
-
-#
-# tools packages
-#
-# CONFIG_PKG_USING_CMBACKTRACE is not set
-# CONFIG_PKG_USING_EASYFLASH is not set
-# CONFIG_PKG_USING_EASYLOGGER is not set
-# CONFIG_PKG_USING_SYSTEMVIEW is not set
-
-#
-# system packages
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_CAIRO is not set
-# CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_FAL is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-
-#
-# peripheral libraries and drivers
-#
-# CONFIG_PKG_USING_STM32F4_HAL is not set
-# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
-# CONFIG_PKG_USING_SHT2X is not set
-# CONFIG_PKG_USING_AHT10 is not set
-# CONFIG_PKG_USING_AP3216C is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-
-#
-# miscellaneous packages
-#
-# CONFIG_PKG_USING_LIBCSV is not set
-# CONFIG_PKG_USING_OPTPARSE is not set
-# CONFIG_PKG_USING_FASTLZ is not set
-# CONFIG_PKG_USING_MINILZO is not set
-# CONFIG_PKG_USING_QUICKLZ is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
-# CONFIG_PKG_USING_CANFESTIVAL is not set
-# CONFIG_PKG_USING_ZLIB is not set
-# CONFIG_PKG_USING_DSTR is not set
-
-#
-# sample package
-#
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
-# CONFIG_PKG_USING_HELLO is not set
-CONFIG_SOC_EMSK=y
-CONFIG_EMSK_USING_UART0=y
-CONFIG_EMSK_USING_UART1=y
diff --git a/bsp/synopsys/emsk_em9d/Kconfig b/bsp/synopsys/emsk_em9d/Kconfig
deleted file mode 100644
index 1bdec3c71f..0000000000
--- a/bsp/synopsys/emsk_em9d/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-mainmenu "RT-Thread Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config RTT_DIR
-    string
-    option env="RTT_ROOT"
-    default "../../.."
-
-config PKGS_DIR
-    string
-    option env="PKGS_ROOT"
-    default "packages"
-
-source "$RTT_DIR/Kconfig"
-source "$PKGS_DIR/Kconfig"
-
-config SOC_EMSK
-    bool
-    select ARCH_ARC_EM
-    select RT_USING_COMPONENTS_INIT
-    # select RT_USING_USER_MAIN
-    default y
-
-source "$BSP_DIR/drivers/Kconfig"
diff --git a/bsp/synopsys/emsk_em9d/README.md b/bsp/synopsys/emsk_em9d/README.md
deleted file mode 100644
index d5cc11fe88..0000000000
--- a/bsp/synopsys/emsk_em9d/README.md
+++ /dev/null
@@ -1,77 +0,0 @@
-# Synopsys DesignWare ARC EM Starter Kit
-
-## Overview
-
-The DesignWare™ ARC™ EM Starter Kit(EMSK, emsk) is a low-cost, versatile
-solution enabling rapid software development and software debugging, and
-profiling for the ARC EM Family of processors. The EM Family includes the EM4,
-EM6, EM5D, EM7D, EM9D, and EM11D cores.
-
-![EM Starter Kit](figures/emsk_board.jpg)
-
-The EMSK consists of a hardware platform and a software package, including
-pre-installed FPGA images of different configurations of the ARC EM Processor
-with peripherals.
-
-The development board is based on a Xilinx Spartan-6 LX45 FPGA. It supports
-hardware extensions using six 2x6 connectors supporting a total of 48 user I/O
-pins (plus power and ground pins) that can be used to connect components such
-as sensors, actuators, memories, displays, buttons, switches, and
-communication devices. A Digilent Pmod™ compatible extension board containing
-a four-channel 12-bit A/D converter with an IIC interface and an AC power
-adapter are included in the package.
-
-## Board Resources
-
-| Hardware | Description |
-| -- | -- |
-| SOC | EMSK |
-| Core | EM9D                                   |
-| Arch       |  32-bit ARC EM                                         |
-| Frequency  |  20/25 Mhz                                            |
-| RAM | 128 MB DDR RAM + 256 KB Instruction CCM + 256 KB Data CCM |
-|Flash | 16 MB SPI Flash for FPGA configuration with 128 KB reserved for application |
-
-## Usage
-
-### FPGA Configuration
-
-Current, only em9d configuration is supported and tested for RT-Thread. However,
-it's can be easily applied to other configurations because all emsk configurations almost share the same memory map and periphreals.
-
-Please refer [EMSK configuration](https://embarc.org/embarc_osp/doc/build/html/board/emsk.html) for details.
-
-### Toolchain
-
-The ARC GNU Toolchain offers all of the benefits of open source tools, including complete source code and a large install base. The ARC GNU IDE Installer consists of Eclipse IDE with [ARC GNU plugin for Eclipse](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/releases), [ARC GNU prebuilt toolchain](https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases) and [OpenOCD for ARC](https://github.com/foss-for-synopsys-dwc-arc-processors/openocd>)
-
-Here, the ARC GNU toolchain is installed to `c:\arc\gnu`. If not, please change the path configuration in rtconfig.py.
-
-### Compile
-
-please run the following cmds to compile
-
-    cd <rt-thread-root>/bsp/synopsys/emsk_em9d
-    scons
-
-## Debug
-
-You need to  install [Zadig](http://zadig.akeo.ie) to replace the default FTDI driver with WinUSB driver. See [How to Use OpenOCD on Windows](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/wiki/How-to-Use-OpenOCD-on-Windows>) for more information.
-
-After compile, please use the following cmds to debug
-
-    scons  --gdb
-
-
-## Supported Drivers
-
-| Driver | Supported | Comment  |
-| ------ | ----  | :------:  |
-| UART1 |  yes |  USB-UART for shell & log |
-| UART0 | yes | PMOD A UART for UART modules, e.g. esp8266 |
-
-## Maintainer
-- [vonhust](https://github.com/vonhust)
-
-## Notes
-
diff --git a/bsp/synopsys/emsk_em9d/SConscript b/bsp/synopsys/emsk_em9d/SConscript
deleted file mode 100644
index 86b6c891cd..0000000000
--- a/bsp/synopsys/emsk_em9d/SConscript
+++ /dev/null
@@ -1,18 +0,0 @@
-# for module compiling
-import os
-Import('RTT_ROOT')
-
-cwd = str(Dir('#'))
-objs = []
-list = os.listdir(cwd)
-
-ASFLAGS = ' -I' + cwd
-
-objs = objs + SConscript(os.path.join(cwd, '../embarc/SConscript'))
-
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')
diff --git a/bsp/synopsys/emsk_em9d/SConstruct b/bsp/synopsys/emsk_em9d/SConstruct
deleted file mode 100644
index d8e88ebeea..0000000000
--- a/bsp/synopsys/emsk_em9d/SConstruct
+++ /dev/null
@@ -1,53 +0,0 @@
-import os
-import sys
-import rtconfig
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-
-try:
-    from building import *
-except:
-    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
-    print(RTT_ROOT)
-    exit(-1)
-
-TARGET = 'rtthread_snps_emsk_em9d.' + rtconfig.TARGET_EXT
-
-# use scons --gdb to debug emsk
-AddOption('--gdb',
-        dest = 'gdb',
-        action = 'store_true',
-        default = False,
-        help = 'use gdb to debug the elf')
-
-if GetOption('gdb'):
-        if os.path.isfile(rtconfig.TARGET):
-            os.system(rtconfig.DBG + rtconfig.DBG_HW_FLAGS + rtconfig.TARGET)
-        else:
-            print rtconfig.TARGET + 'not exist, please build first!!'
-        exit(0)
-
-DefaultEnvironment(tools=[])
-env = Environment(tools = ['mingw'],
-        AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-        CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-        AR = rtconfig.AR, ARFLAGS = '-rc',
-        LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT)
-
-# if the linker script changed, relink the target
-Depends(TARGET, rtconfig.LINK_SCRIPT)
-
-# make a building
-DoBuilding(TARGET, objs)
diff --git a/bsp/synopsys/emsk_em9d/applications/SConscript b/bsp/synopsys/emsk_em9d/applications/SConscript
deleted file mode 100644
index 01eb940dfb..0000000000
--- a/bsp/synopsys/emsk_em9d/applications/SConscript
+++ /dev/null
@@ -1,11 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = os.path.join(str(Dir('#')), 'applications')
-src	= Glob('*.c')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/synopsys/emsk_em9d/applications/application.c b/bsp/synopsys/emsk_em9d/applications/application.c
deleted file mode 100644
index 3e12c0ba76..0000000000
--- a/bsp/synopsys/emsk_em9d/applications/application.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <rtthread.h>
-
-/* thread phase init */
-static void rt_init_thread_entry(void *parameter)
-{
-    /* do component initialization */
-    rt_components_init();
-
-    /* add your initialization here */
-}
-
-int rt_application_init()
-{
-    rt_thread_t tid;
-
-    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048,
-                            RT_THREAD_PRIORITY_MAX/3, 20);
-    if (tid != RT_NULL)
-        rt_thread_startup(tid);
-
-    return 0;
-}
-
diff --git a/bsp/synopsys/emsk_em9d/applications/startup.c b/bsp/synopsys/emsk_em9d/applications/startup.c
deleted file mode 100644
index f561436272..0000000000
--- a/bsp/synopsys/emsk_em9d/applications/startup.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <board.h>
-
-extern int rt_application_init(void);
-
-void rt_hw_interrupt_init(void)
-{
-    /* rt-thread specific interrupt and exception init */
-}
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-
-    /* initialize hardware interrupt */
-    rt_hw_interrupt_init();
-
-    /* initialize board */
-    rt_hw_board_init();
-
-    /* show RT-Thread version */
-    rt_show_version();
-
-    /* initialize memory system */
-#ifdef RT_USING_HEAP
-    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
-#endif
-
-    /* initialize scheduler system */
-    rt_system_scheduler_init();
-
-    /* initialize system timer */
-    rt_system_timer_init();
-
-    /* initialize soft timer thread */
-    rt_system_timer_thread_init();
-
-    /* initialize application */
-    rt_application_init();
-
-    /* initialize idle thread */
-    rt_thread_idle_init();
-
-    /* start scheduler */
-    rt_system_scheduler_start();
-
-    /* never reach here */
-    return ;
-}
-
-int board_main(void)
-{
-    /* disable interrupt first */
-    rt_hw_interrupt_disable();
-
-    /* invoke rtthread_startup */
-    rtthread_startup();
-
-    return 0;
-}
-
diff --git a/bsp/synopsys/emsk_em9d/drivers/Kconfig b/bsp/synopsys/emsk_em9d/drivers/Kconfig
deleted file mode 100644
index 3cc4d3470d..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-
-config EMSK_USING_UART0
-    bool "Using UART0"
-    select RT_USING_SERIAL
-    default y
-
-config EMSK_USING_UART1
-    bool "Using UART1"
-    select RT_USING_SERIAL
-    default y
\ No newline at end of file
diff --git a/bsp/synopsys/emsk_em9d/drivers/SConscript b/bsp/synopsys/emsk_em9d/drivers/SConscript
deleted file mode 100644
index 29272aa88e..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/SConscript
+++ /dev/null
@@ -1,15 +0,0 @@
-import copy
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = GetCurrentDir()
-src	= Glob('*.c')
-
-ASFLAGS = ' -I' + cwd
-
-CPPPATH = [cwd]
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')
diff --git a/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h b/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h
deleted file mode 100644
index 8340e94091..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* This file is automatically generated from tcf file. DO NOT EDIT */
-#ifndef __core_config_h
-	#define __core_config_h  1
-	#define	core_config_cir_identity	0x00000042
-	#define	core_config_cir_identity_chipid	0
-	#define	core_config_cir_identity_arcnum	0
-	#define	core_config_cir_identity_arcver	66
-	#define	core_config_cir_identity_family	4
-	#define	core_config_cir_identity_corever	2
-	#define	core_config_cir_aux_dccm	0x80000000
-	#define	core_config_bcr_bcr_ver	0x00000002
-	#define	core_config_bcr_bcr_ver_version	2
-	#define	core_config_bcr_vecbase_ac_build	0x00000010
-	#define	core_config_bcr_rf_build	0x0000c902
-	#define	core_config_bcr_rf_build_version	2
-	#define	core_config_bcr_rf_build_p	1
-	#define	core_config_bcr_rf_build_e	0
-	#define	core_config_bcr_rf_build_r	0
-	#define	core_config_bcr_rf_build_b	1
-	#define	core_config_bcr_rf_build_d	3
-	#define	core_config_bcr_dccm_build	0x00010904
-	#define	core_config_bcr_dccm_build_cycles	0
-	#define	core_config_bcr_dccm_build_interleave	1
-	#define	core_config_bcr_dccm_build_size1	0
-	#define	core_config_bcr_dccm_build_size0	9
-	#define	core_config_bcr_dccm_build_version	4
-	#define	core_config_bcr_timer_build	0x00010304
-	#define	core_config_bcr_timer_build_sp1	0
-	#define	core_config_bcr_timer_build_sp0	0
-	#define	core_config_bcr_timer_build_p1	0
-	#define	core_config_bcr_timer_build_p0	1
-	#define	core_config_bcr_timer_build_st1	0
-	#define	core_config_bcr_timer_build_st0	0
-	#define	core_config_bcr_timer_build_rtc	0
-	#define	core_config_bcr_timer_build_rtsc_ver	1
-	#define	core_config_bcr_timer_build_rtsc	0
-	#define	core_config_bcr_timer_build_t0	1
-	#define	core_config_bcr_timer_build_t1	1
-	#define	core_config_bcr_timer_build_version	4
-	#define	core_config_bcr_ap_build	0x00000405
-	#define	core_config_bcr_ap_build_version	5
-	#define	core_config_bcr_ap_build_type	4
-	#define	core_config_bcr_iccm_build	0x00000a04
-	#define	core_config_bcr_iccm_build_iccm1_size1	0
-	#define	core_config_bcr_iccm_build_iccm0_size1	0
-	#define	core_config_bcr_iccm_build_iccm1_size0	0
-	#define	core_config_bcr_iccm_build_iccm0_size0	10
-	#define	core_config_bcr_iccm_build_version	4
-	#define	core_config_bcr_xy_build	0x00001620
-	#define	core_config_bcr_xy_build_memsize	1
-	#define	core_config_bcr_xy_build_interleaved	1
-	#define	core_config_bcr_xy_build_config	2
-	#define	core_config_bcr_xy_build_version	32
-	#define	core_config_bcr_dsp_build	0x00003521
-	#define	core_config_bcr_dsp_build_wide	0
-	#define	core_config_bcr_dsp_build_itu_pa	1
-	#define	core_config_bcr_dsp_build_acc_shift	2
-	#define	core_config_bcr_dsp_build_comp	1
-	#define	core_config_bcr_dsp_build_divsqrt	1
-	#define	core_config_bcr_dsp_build_version	33
-	#define	core_config_bcr_multiply_build	0x00022a06
-	#define	core_config_bcr_multiply_build_version16x16	2
-	#define	core_config_bcr_multiply_build_dsp	2
-	#define	core_config_bcr_multiply_build_cyc	2
-	#define	core_config_bcr_multiply_build_type	2
-	#define	core_config_bcr_multiply_build_version32x32	6
-	#define	core_config_bcr_swap_build	0x00000003
-	#define	core_config_bcr_swap_build_version	3
-	#define	core_config_bcr_norm_build	0x00000003
-	#define	core_config_bcr_norm_build_version	3
-	#define	core_config_bcr_minmax_build	0x00000002
-	#define	core_config_bcr_minmax_build_version	2
-	#define	core_config_bcr_barrel_build	0x00000303
-	#define	core_config_bcr_barrel_build_version	3
-	#define	core_config_bcr_barrel_build_shift_option	3
-	#define	core_config_bcr_isa_config	0x12447402
-	#define	core_config_bcr_isa_config_d	1
-	#define	core_config_bcr_isa_config_c	2
-	#define	core_config_bcr_isa_config_l	0
-	#define	core_config_bcr_isa_config_n	1
-	#define	core_config_bcr_isa_config_a	0
-	#define	core_config_bcr_isa_config_b	0
-	#define	core_config_bcr_isa_config_addr_size	4
-	#define	core_config_bcr_isa_config_lpc_size	7
-	#define	core_config_bcr_isa_config_pc_size	4
-	#define	core_config_bcr_isa_config_version	2
-	#define	core_config_bcr_stack_region_build	0x00000002
-	#define	core_config_bcr_fpu_build	0x00000f02
-	#define	core_config_bcr_fpu_build_da	0
-	#define	core_config_bcr_fpu_build_dd	0
-	#define	core_config_bcr_fpu_build_dc	0
-	#define	core_config_bcr_fpu_build_df	0
-	#define	core_config_bcr_fpu_build_dp	0
-	#define	core_config_bcr_fpu_build_fd	0
-	#define	core_config_bcr_fpu_build_fm	0
-	#define	core_config_bcr_fpu_build_sd	1
-	#define	core_config_bcr_fpu_build_sc	1
-	#define	core_config_bcr_fpu_build_sf	1
-	#define	core_config_bcr_fpu_build_sp	1
-	#define	core_config_bcr_fpu_build_version	2
-	#define	core_config_bcr_bs_build	0x00000001
-	#define	core_config_bcr_bs_build_version	1
-	#define	core_config_bcr_agu_build	0x01988c01
-	#define	core_config_bcr_agu_build_accordian	1
-	#define	core_config_bcr_agu_build_wb_size	4
-	#define	core_config_bcr_agu_build_num_modifier	24
-	#define	core_config_bcr_agu_build_num_offset	8
-	#define	core_config_bcr_agu_build_num_addr	12
-	#define	core_config_bcr_agu_build_version	1
-	#define	core_config_bcr_dmac_build	0x000a0101
-	#define	core_config_bcr_dmac_build_int_cfg	1
-	#define	core_config_bcr_dmac_build_fifo	1
-	#define	core_config_bcr_dmac_build_chan_mem	0
-	#define	core_config_bcr_dmac_build_channels	1
-	#define	core_config_bcr_dmac_build_version	1
-	#define	core_config_bcr_core_config	0x00000101
-	#define	core_config_bcr_core_config_turbo_boost	1
-	#define	core_config_bcr_core_config_version	1
-	#define	core_config_bcr_irq_build	0x13101401
-	#define	core_config_bcr_irq_build_raz	0
-	#define	core_config_bcr_irq_build_f	1
-	#define	core_config_bcr_irq_build_p	3
-	#define	core_config_bcr_irq_build_exts	16
-	#define	core_config_bcr_irq_build_irqs	20
-	#define	core_config_bcr_irq_build_version	1
-	#define	core_config_bcr_pct_build	0x08080102
-	#define	core_config_bcr_pct_build_version	2
-	#define	core_config_bcr_pct_build_s	1
-	#define	core_config_bcr_pct_build_i	0
-	#define	core_config_bcr_pct_build_c	8
-	#define	core_config_bcr_cc_build	0x006f0004
-	#define	core_config_bcr_cc_build_version	4
-	#define	core_config_bcr_cc_build_cc	111
-	#define	core_config_bcr_ifqueue_build	0x00000002
-	#define	core_config_bcr_ifqueue_build_bd	0
-	#define	core_config_bcr_ifqueue_build_version	2
-	#define	core_config_bcr_smart_build	0x00002003
-	#define	core_config_bcr_smart_build_version	3
-	#define	core_config_bcr_smart_build_stack_size	8
-	#define	core_config_cir_aux_iccm	0x00000000
-	#define	core_config_cir_dmp_peripheral	0xf0000000
-	#define	core_config_cir_xccm_base	0xc0000000
-	#define	core_config_cir_yccm_base	0xe0000000
-	#define	core_config_family	4
-	#define	core_config_core_version	2
-	#define	core_config_family_name	"arcv2em"
-	#define	core_config_rgf_num_banks	2
-	#define	core_config_rgf_banked_regs	32
-	#define	core_config_rgf_num_wr_ports	2
-	#define	core_config_endian	"little"
-	#define	core_config_endian_little	1
-	#define	core_config_endian_big	0
-	#define	core_config_lpc_size	32
-	#define	core_config_pc_size	32
-	#define	core_config_addr_size	32
-	#define	core_config_unaligned	1
-	#define	core_config_code_density	1
-	#define	core_config_div_rem	"radix2"
-	#define	core_config_div_rem_radix2	1
-	#define	core_config_turbo_boost	1
-	#define	core_config_swap	1
-	#define	core_config_bitscan	1
-	#define	core_config_mpy_option	"mpyd"
-	#define	core_config_mpy_option_num	8
-	#define	core_config_shift_assist	1
-	#define	core_config_barrel_shifter	1
-	#define	core_config_dsp	1
-	#define	core_config_dsp2	1
-	#define	core_config_dsp_complex	1
-	#define	core_config_dsp_divsqrt	"radix2"
-	#define	core_config_dsp_divsqrt_radix2	1
-	#define	core_config_dsp_itu	1
-	#define	core_config_dsp_accshift	"full"
-	#define	core_config_dsp_accshift_full	1
-	#define	core_config_agu_large	1
-	#define	core_config_agu_wb_depth	4
-	#define	core_config_agu_accord	1
-	#define	core_config_xy	1
-	#define	core_config_xy_config	"dccm_x_y"
-	#define	core_config_xy_config_dccm_x_y	1
-	#define	core_config_xy_size	8192
-	#define	core_config_xy_size_KM	"8K"
-	#define	core_config_xy_interleave	1
-	#define	core_config_xy_x_base	0xc0000000
-	#define	core_config_xy_y_base	0xe0000000
-	#define	core_config_bitstream	1
-	#define	core_config_fpus_div	1
-	#define	core_config_fpu_mac	1
-	#define	core_config_fpus_mpy_slow	1
-	#define	core_config_fpus_div_slow	1
-	#define	core_config_timer0	1
-	#define	core_config_timer0_level	1
-	#define	core_config_timer0_vector	16
-	#define	core_config_timer1	1
-	#define	core_config_timer1_level	0
-	#define	core_config_timer1_vector	17
-	#define	core_config_action_points	2
-	#define	core_config_stack_check	1
-	#define	core_config_smart_stack_entries	8
-	#define	core_config_ifq_present	1
-	#define	core_config_ifq_entries	1
-	#define	core_config_interrupts_present	1
-	#define	core_config_interrupts_number	20
-	#define	core_config_interrupts_priorities	4
-	#define	core_config_interrupts_externals	16
-	#define	core_config_interrupts	20
-	#define	core_config_interrupt_priorities	4
-	#define	core_config_ext_interrupts	16
-	#define	core_config_interrupts_firq	1
-	#define	core_config_interrupts_base	0x0
-	#define	core_config_dccm_present	1
-	#define	core_config_dccm_size	0x20000
-	#define	core_config_dccm_base	0x80000000
-	#define	core_config_dccm_interleave	1
-	#define	core_config_iccm_present	1
-	#define	core_config_iccm0_present	1
-	#define	core_config_iccm_size	0x40000
-	#define	core_config_iccm0_size	0x40000
-	#define	core_config_iccm_base	0x00000000
-	#define	core_config_iccm0_base	0x00000000
-	#define	core_config_pct_counters	8
-	#define	core_config_dmac	1
-	#define	core_config_dmac_channels	2
-	#define	core_config_dmac_registers	0
-	#define	core_config_dmac_fifo_depth	2
-	#define	core_config_dmac_int_config	"single_internal"
-	#define	core_config_clock_speed	20
-#endif /* __core_config_h */
-
diff --git a/bsp/synopsys/emsk_em9d/drivers/board.c b/bsp/synopsys/emsk_em9d/drivers/board.c
deleted file mode 100644
index 449360f3a5..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/board.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <rtdevice.h>
-#include <drivers/serial.h>
-
-#include "board.h"
-#include "inc/arc/arc_timer.h"
-#include "inc/arc/arc_exception.h"
-
-#include "inc/embARC_error.h"
-#include "mux.h"
-#include "dw_uart_obj.h"
-
-
-static void rt_hw_timer_isr(int vector, void *param)
-{
-    arc_timer_int_clear(BOARD_OS_TIMER_ID);
-    rt_tick_increase();
-}
-
-static void emsk_mux_init(void)
-{
-    MUX_REG *mux_regs;
-
-    mux_regs = (MUX_REG *)(PERIPHERAL_BASE|REL_REGBASE_PINMUX);
-    mux_init(mux_regs);
-
-    /**
-     * + Please refer to corresponding EMSK User Guide for detailed information
-     *   -> Appendix: A  Hardware Functional Description
-     *      -> Pmods Configuration summary
-     * + Set up pin-multiplexer of all PMOD connections
-     *   - PM1 J1: Upper row as UART 0, lower row as SPI Slave
-     *   - PM2 J2: IIC 0 and run/halt signals
-     *   - PM3 J3: GPIO Port A and Port C
-     *   - PM4 J4: IIC 1 and Port D
-     *   - PM5 J5: Upper row as SPI Master, lower row as Port A
-     *   - PM6 J6: Upper row as SPI Master, lower row as Port A
-     */
-    set_pmod_mux(mux_regs, PM1_UR_UART_0 | PM1_LR_SPI_S \
-                | PM2_I2C_HRI           \
-                | PM3_GPIO_AC           \
-                | PM4_I2C_GPIO_D        \
-                | PM5_UR_SPI_M1 | PM5_LR_GPIO_A \
-                | PM6_UR_SPI_M0 | PM6_LR_GPIO_A );
-
-    /**
-     * PM1 upper row as UART
-     * UM4:RXD, UM3:TXD
-     * UM2:RTS_N, UM1:CTS_N
-     */
-    set_uart_map(mux_regs, 0xe4);
-}
-
-static struct rt_serial_device _emsk_uart0;  //abstracted serial for RTT
-static struct rt_serial_device _emsk_uart1;
-
-static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    DEV_UART_PTR uart;
-    unsigned int id;
-    int ret;
-
-    id = (unsigned int)(serial->parent.user_data);
-
-    uart = uart_get_dev(id);
-
-    ret = uart->uart_control(UART_CMD_SET_BAUD, (void *)(cfg->baud_rate));
-
-    if (ret != E_OK) {
-        return RT_ERROR;
-    }
-
-
-    return RT_EOK;
-}
-
-static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    DEV_UART_PTR uart;
-    unsigned int id;
-
-    id = (unsigned int)(serial->parent.user_data);
-    uart = uart_get_dev(id);
-
-    switch (cmd) {
-        case RT_DEVICE_CTRL_CLR_INT:
-            uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
-            break;
-        case RT_DEVICE_CTRL_SET_INT:
-            uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
-            break;
-        case RT_DEVICE_CTRL_SUSPEND:
-            uart->uart_control(UART_CMD_DIS_DEV, (void *)0);
-            break;
-        case RT_DEVICE_CTRL_RESUME:
-            uart->uart_control(UART_CMD_ENA_DEV, (void *)0);
-            break;
-
-        default:
-            return  RT_ERROR;
-            break;
-    }
-
-    return RT_EOK;
-}
-
-static int _putc(struct rt_serial_device *serial, char c)
-{
-    DEV_UART_PTR uart;
-    unsigned int id;
-    int ret;
-
-    id = (unsigned int)(serial->parent.user_data);
-
-    uart = uart_get_dev(id);
-
-    ret = uart->uart_write(&c, 1);
-
-    if (ret < 0) {
-        return -1;
-    } else {
-        return 1;
-    }
-}
-
-static int _getc(struct rt_serial_device *serial)
-{
-    DEV_UART_PTR uart;
-    unsigned int id;
-    unsigned int data;
-    int ret;
-    int rd_avail = 0;
-
-    id = (unsigned int)(serial->parent.user_data);
-    uart = uart_get_dev(id);
-
-    uart->uart_control(UART_CMD_GET_RXAVAIL, (void *)(&rd_avail));
-
-    if (rd_avail > 0) {
-        ret = uart->uart_read(&data, 1);
-    } else {
-        return -1;
-    }
-
-    if (ret < 0) {
-        return -1;
-    } else {
-        return data;
-    }
-
-}
-
-static void _emsk_uart0_isr(void *ptr)
-{
-    rt_hw_serial_isr((struct rt_serial_device*)&_emsk_uart0, RT_SERIAL_EVENT_RX_IND);
-}
-
-static const struct rt_uart_ops _emsk_uart0_ops =
-{
-    _configure,
-    _control,
-    _putc,
-    _getc,
-};
-
-static void _emsk_uart1_isr(void *ptr)
-{
-    rt_hw_serial_isr((struct rt_serial_device*)&_emsk_uart1, RT_SERIAL_EVENT_RX_IND);
-}
-
-static const struct rt_uart_ops _emsk_uart1_ops =
-{
-    _configure,
-    _control,
-    _putc,
-    _getc,
-};
-
-int rt_hw_uart_init(void)
-{
-    DEV_UART_PTR uart;
-    struct serial_configure config;
-    int ret;
-
-    config.baud_rate = BAUD_RATE_115200;
-    config.bit_order = BIT_ORDER_LSB;
-    config.data_bits = DATA_BITS_8;
-    config.parity    = PARITY_NONE;
-    config.stop_bits = STOP_BITS_1;
-    config.invert    = NRZ_NORMAL;
-    config.bufsz     = RT_SERIAL_RB_BUFSZ;
-
-    _emsk_uart0.ops    = &_emsk_uart0_ops;
-    _emsk_uart0.config = config;
-
-    _emsk_uart1.ops    = &_emsk_uart1_ops;
-    _emsk_uart1.config = config;
-
-    /* open UART1 for USB-UART interface */
-    uart = uart_get_dev(DW_UART_1_ID);
-    /* default format: 8bits, no parity, 1 stop bits */
-    ret = uart->uart_open(config.baud_rate);
-
-    if (ret != E_OPNED && ret != E_OK) {
-        return RT_ERROR;
-    }
-
-    /* enable rx int */
-    uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
-    /* use customized int isr */
-    uart->uart_control(UART_CMD_SET_RXCB, _emsk_uart1_isr);
-    uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
-
-    rt_hw_serial_register(&_emsk_uart1, "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-                          (void *)DW_UART_1_ID);
-
-     /* open UART0 in PMOD A*/
-    uart = uart_get_dev(DW_UART_0_ID);
-    /* default format: 8bits, no parity, 1 stop bits */
-    ret = uart->uart_open(config.baud_rate);
-
-    if (ret != E_OPNED && ret != E_OK) {
-        return RT_ERROR;
-    }
-
-    /* enable rx int */
-    uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
-    /* use customized int isr */
-    uart->uart_control(UART_CMD_SET_RXCB, _emsk_uart0_isr);
-    uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
-
-    rt_hw_serial_register(&_emsk_uart0, "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-                          (void *)DW_UART_0_ID);
-
-    return RT_EOK;
-}
-
-void rt_hw_console_output(const char *str)
-{
-    while(*str != '\0')
-    {
-        if (*str == '\n') {
-            _putc(&_emsk_uart1,'\r');
-        }
-        _putc(&_emsk_uart1,*str);
-        str++;
-    }
-}
-
-int rt_hw_timer_init(void)
-{
-
-    unsigned int cyc = BOARD_CPU_CLOCK / RT_TICK_PER_SECOND;
-
-    int_disable(BOARD_OS_TIMER_INTNO); /* disable os timer interrupt */
-    arc_timer_stop(BOARD_OS_TIMER_ID);
-    arc_timer_start(BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc);
-
-    int_handler_install(BOARD_OS_TIMER_INTNO, (INT_HANDLER)rt_hw_timer_isr);
-    int_enable(BOARD_OS_TIMER_INTNO);
-
-    return 0;
-}
-INIT_BOARD_EXPORT(rt_hw_timer_init);
-
-void rt_hw_board_init()
-{
-    emsk_mux_init();
-
-    rt_hw_uart_init();
-    rt_components_board_init();
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-}
diff --git a/bsp/synopsys/emsk_em9d/drivers/board.h b/bsp/synopsys/emsk_em9d/drivers/board.h
deleted file mode 100644
index aebf88bd42..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/board.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-#include "emsk_hardware.h"
-
-#define BOARD_OS_TIMER_ID       0
-#define BOARD_OS_TIMER_INTNO    16
-#define BOARD_CPU_CLOCK         25000000
-
-#if defined(__GNUC__)
-extern int __start_heap;
-#define HEAP_BEGIN      ((void*)&__start_heap)
-#endif
-
-extern int __end_heap;
-#define HEAP_END        (void*)(&__end_heap)
-
-void rt_hw_board_init();
-
-int rt_hw_uart_init(void);
-
-#endif
diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c b/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c
deleted file mode 100644
index 8701a0e9c7..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include "inc/arc/arc.h"
-#include "inc/arc/arc_builtin.h"
-
-#include "dw_gpio_obj.h"
-
-#include "emsk_hardware.h"
-/*
- * Uncomment this to enable default
- * gpio bit handler output message
- * by uart
- */
-
-#ifdef ARC_FEATURE_DMP_PERIPHERAL
-#define PERIPHERAL_BASE     ARC_FEATURE_DMP_PERIPHERAL
-#else
-#define PERIPHERAL_BASE     _arc_aux_read(AUX_DMP_PERIPHERAL)
-#endif
-
-#if (USE_DW_GPIO_PORT_A)
-static DEV_GPIO     port_a;
-static DW_GPIO_PORT dw_gpio_port_a;
-static DEV_GPIO_HANDLER dw_gpio_bit_handler_a[EMSK_GPIO_A_INT_MAX_COUNT];
-static DW_GPIO_BIT_ISR dw_gpio_bit_isr_a = {
-    EMSK_GPIO_A_INT_MAX_COUNT, dw_gpio_bit_handler_a
-};
-
-static int32_t porta_open(uint32_t dir)
-{
-    return dw_gpio_open(&port_a, dir);
-}
-
-static int32_t porta_close(void)
-{
-    return dw_gpio_close(&port_a);
-}
-
-static int32_t porta_control(uint32_t ctrl_cmd, void *param)
-{
-    return dw_gpio_control(&port_a, ctrl_cmd, param);
-}
-
-static int32_t porta_write(uint32_t val, uint32_t mask)
-{
-    return dw_gpio_write(&port_a, val, mask);
-}
-
-static int32_t porta_read(uint32_t *val, uint32_t mask)
-{
-    return dw_gpio_read(&port_a, val, mask);
-}
-
-static void porta_isr(void *ptr)
-{
-    dw_gpio_isr_handler(&port_a, ptr);
-}
-
-static void porta_install(void)
-{
-    uint32_t i;
-    DEV_GPIO_PTR port_ptr = &port_a;
-    DEV_GPIO_INFO_PTR info_ptr = &(port_a.gpio_info);
-    DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_a);
-
-    info_ptr->gpio_ctrl = (void *)dw_port_ptr;
-    info_ptr->opn_cnt = 0;
-    info_ptr->method = 0;
-    info_ptr->direction = 0;
-    info_ptr->extra = 0;
-
-    dw_port_ptr->no = DW_GPIO_PORT_A;
-    dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0);
-    dw_port_ptr->valid_bit_mask = EMSK_GPIO_A_VALID_MASK;
-    dw_port_ptr->intno = INTNO_GPIO;
-    dw_port_ptr->int_handler = porta_isr;
-
-    for (i=0; i<dw_gpio_bit_isr_a.int_bit_max_cnt; i++) {
-        dw_gpio_bit_isr_a.int_bit_handler_ptr[i] = NULL;
-    }
-    dw_port_ptr->gpio_bit_isr = &dw_gpio_bit_isr_a;
-
-    port_ptr->gpio_open = porta_open;
-    port_ptr->gpio_close = porta_close;
-    port_ptr->gpio_control = porta_control;
-    port_ptr->gpio_write = porta_write;
-    port_ptr->gpio_read = porta_read;
-}
-#endif
-
-#if (USE_DW_GPIO_PORT_B)
-static DEV_GPIO     port_b;
-static DW_GPIO_PORT dw_gpio_port_b;
-
-static int32_t portb_open(uint32_t dir)
-{
-    return dw_gpio_open(&port_b, dir);
-}
-
-static int32_t portb_close(void)
-{
-    return dw_gpio_close(&port_b);
-}
-
-static int32_t portb_control(uint32_t ctrl_cmd, void *param)
-{
-    return dw_gpio_control(&port_b, ctrl_cmd, param);
-}
-
-static int32_t portb_write(uint32_t val, uint32_t mask)
-{
-    return dw_gpio_write(&port_b, val, mask);
-}
-
-static int32_t portb_read(uint32_t *val, uint32_t mask)
-{
-    return dw_gpio_read(&port_b, val, mask);
-}
-
-static void portb_isr(void *ptr)
-{
-    dw_gpio_isr_handler(&port_b, ptr);
-}
-
-static void portb_install(void)
-{
-    DEV_GPIO_PTR port_ptr = &port_b;
-    DEV_GPIO_INFO_PTR info_ptr = &(port_b.gpio_info);
-    DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_b);
-
-    info_ptr->gpio_ctrl = (void *)dw_port_ptr;
-    info_ptr->opn_cnt = 0;
-    info_ptr->method = 0;
-    info_ptr->direction = 0;
-    info_ptr->extra = 0;
-
-    dw_port_ptr->no = DW_GPIO_PORT_B;
-    dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0);
-    dw_port_ptr->valid_bit_mask = EMSK_GPIO_B_VALID_MASK;
-
-    dw_port_ptr->intno = INTNO_GPIO;
-    dw_port_ptr->int_handler = portb_isr;
-    dw_port_ptr->gpio_bit_isr = NULL;
-
-    port_ptr->gpio_open = portb_open;
-    port_ptr->gpio_close = portb_close;
-    port_ptr->gpio_control = portb_control;
-    port_ptr->gpio_write = portb_write;
-    port_ptr->gpio_read = portb_read;
-}
-#endif
-
-
-#if (USE_DW_GPIO_PORT_C)
-static DEV_GPIO     port_c;
-static DW_GPIO_PORT dw_gpio_port_c;
-
-static int32_t portc_open(uint32_t dir)
-{
-    return dw_gpio_open(&port_c, dir);
-}
-
-static int32_t portc_close(void)
-{
-    return dw_gpio_close(&port_c);
-}
-
-static int32_t portc_control(uint32_t ctrl_cmd, void *param)
-{
-    return dw_gpio_control(&port_c, ctrl_cmd, param);
-}
-
-static int32_t portc_write(uint32_t val, uint32_t mask)
-{
-    return dw_gpio_write(&port_c, val, mask);
-}
-
-static int32_t portc_read(uint32_t *val, uint32_t mask)
-{
-    return dw_gpio_read(&port_c, val, mask);
-}
-
-static void portc_isr(void *ptr)
-{
-    dw_gpio_isr_handler(&port_c, ptr);
-}
-
-static void portc_install(void)
-{
-    DEV_GPIO_PTR port_ptr = &port_c;
-    DEV_GPIO_INFO_PTR info_ptr = &(port_c.gpio_info);
-    DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_c);
-
-    info_ptr->gpio_ctrl = (void *)dw_port_ptr;
-    info_ptr->opn_cnt = 0;
-    info_ptr->method = 0;
-    info_ptr->direction = 0;
-    info_ptr->extra = 0;
-
-    dw_port_ptr->no = DW_GPIO_PORT_C;
-    dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0);
-    dw_port_ptr->valid_bit_mask = EMSK_GPIO_C_VALID_MASK;
-
-    dw_port_ptr->intno = INTNO_GPIO;
-    dw_port_ptr->int_handler = portc_isr;
-    dw_port_ptr->gpio_bit_isr = NULL;
-
-    port_ptr->gpio_open = portc_open;
-    port_ptr->gpio_close = portc_close;
-    port_ptr->gpio_control = portc_control;
-    port_ptr->gpio_write = portc_write;
-    port_ptr->gpio_read = portc_read;
-}
-#endif
-
-#if (USE_DW_GPIO_PORT_D)
-static DEV_GPIO     port_d;
-static DW_GPIO_PORT dw_gpio_port_d;
-
-static int32_t portd_open(uint32_t dir)
-{
-    return dw_gpio_open(&port_d, dir);
-}
-
-static int32_t portd_close(void)
-{
-    return dw_gpio_close(&port_d);
-}
-
-static int32_t portd_control(uint32_t ctrl_cmd, void *param)
-{
-    return dw_gpio_control(&port_d, ctrl_cmd, param);
-}
-
-static int32_t portd_write(uint32_t val, uint32_t mask)
-{
-    return dw_gpio_write(&port_d, val, mask);
-}
-
-static int32_t portd_read(uint32_t *val, uint32_t mask)
-{
-    return dw_gpio_read(&port_d, val, mask);
-}
-
-static void portd_isr(void *ptr)
-{
-    dw_gpio_isr_handler(&port_d, ptr);
-}
-
-static void portd_install(void)
-{
-    DEV_GPIO_PTR port_ptr = &port_d;
-    DEV_GPIO_INFO_PTR info_ptr = &(port_d.gpio_info);
-    DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_d);
-
-    info_ptr->gpio_ctrl = (void *)dw_port_ptr;
-    info_ptr->opn_cnt = 0;
-    info_ptr->method = 0;
-    info_ptr->direction = 0;
-    info_ptr->extra = 0;
-
-    dw_port_ptr->no = DW_GPIO_PORT_D;
-    dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0);
-    dw_port_ptr->valid_bit_mask = EMSK_GPIO_D_VALID_MASK;
-
-    dw_port_ptr->intno = INTNO_GPIO;
-    dw_port_ptr->int_handler = portd_isr;
-    dw_port_ptr->gpio_bit_isr = NULL;
-
-    port_ptr->gpio_open = portd_open;
-    port_ptr->gpio_close = portd_close;
-    port_ptr->gpio_control = portd_control;
-    port_ptr->gpio_write = portd_write;
-    port_ptr->gpio_read = portd_read;
-}
-#endif
-
-DEV_GPIO_PTR gpio_get_dev(int32_t gpio_id)
-{
-    static uint32_t install_flag = 0;
-
-    /* intall device objects */
-    if (install_flag == 0) {
-        install_flag = 1;
-        dw_gpio_all_install();
-    }
-
-    switch (gpio_id) {
-#if (USE_DW_GPIO_PORT_A)
-        case DW_GPIO_PORT_A: return &port_a;
-#endif
-#if (USE_DW_GPIO_PORT_B)
-        case DW_GPIO_PORT_B: return &port_b;
-#endif
-#if (USE_DW_GPIO_PORT_C)
-        case DW_GPIO_PORT_C: return &port_c;
-#endif
-#if (USE_DW_GPIO_PORT_D)
-        case DW_GPIO_PORT_D: return &port_d;
-#endif
-        default:
-            break;
-    }
-    return NULL;
-}
-
-void dw_gpio_all_install(void)
-{
-#if (USE_DW_GPIO_PORT_A)
-    porta_install();
-#endif
-#if (USE_DW_GPIO_PORT_B)
-    portb_install();
-#endif
-#if (USE_DW_GPIO_PORT_C)
-    portc_install();
-#endif
-#if (USE_DW_GPIO_PORT_D)
-    portd_install();
-#endif
-}
diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h b/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h
deleted file mode 100644
index d39a09159d..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _DW_GPIO_OBJ_H_
-#define _DW_GPIO_OBJ_H_
-
-#include "device/designware/gpio/dw_gpio.h"
-
-/**
- * \name    Designware GPIO Port Bank Control Macros
- * @{
- */
-#define USE_DW_GPIO_PORT_A      1
-#define USE_DW_GPIO_PORT_B      1
-#define USE_DW_GPIO_PORT_C      1
-#define USE_DW_GPIO_PORT_D      1
-/** @} end of name */
-
-/**
- * \name    Designware GPIO Port Interrupt Available Number Macros
- * @{
- */
-#define EMSK_GPIO_A_INT_MAX_COUNT   32
-#define EMSK_GPIO_B_INT_MAX_COUNT   0
-#define EMSK_GPIO_C_INT_MAX_COUNT   0
-#define EMSK_GPIO_D_INT_MAX_COUNT   0
-/** @} end of name */
-
-/**
- * \name    Designware GPIO Port Available Bits Macros
- * @{
- */
-#define EMSK_GPIO_A_VALID_MASK      DW_GPIO_MASK_ALL
-#define EMSK_GPIO_B_VALID_MASK      DW_GPIO_MASK_ALL
-#define EMSK_GPIO_C_VALID_MASK      DW_GPIO_MASK_ALL
-#define EMSK_GPIO_D_VALID_MASK      DW_GPIO_MASK_ALL
-/** @} end of name */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern void dw_gpio_all_install(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DW_GPIO_OBJ_H_*/
diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c b/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c
deleted file mode 100644
index 9e3ebd3db9..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include "inc/arc/arc.h"
-#include "inc/arc/arc_builtin.h"
-#include "inc/embARC_toolchain.h"
-#include "inc/embARC_error.h"
-
-#include "inc/arc/arc_exception.h"
-#include "device/designware/uart/dw_uart.h"
-#include "dw_uart_obj.h"
-
-#include "emsk_hardware.h"
-
-#define DW_UART_FIFO_LEN    32
-
-/**
- * \name    EMSK DesignWare UART 0 Object Instantiation
- * @{
- */
-#if (USE_DW_UART_0)
-static void dw_uart_0_isr(void *ptr);
-#define DW_UART_0_RELBASE   (REL_REGBASE_UART0) /*!< designware uart 0 relative baseaddr */
-#define DW_UART_0_INTNO     (INTNO_UART0)       /*!< designware uart 0 interrupt number  */
-
-DEV_UART        dw_uart_0;          /*!< designware uart object */
-DW_UART_CTRL    dw_uart_0_ctrl = {          /*!< designware uart 0 ctrl */
-    0, CLK_BUS_APB, DW_UART_0_INTNO, (INT_HANDLER)dw_uart_0_isr,
-    DW_UART_FIFO_LEN, DW_UART_FIFO_LEN, 0
-};
-
-/** designware uart 0 open */
-static int32_t dw_uart_0_open (uint32_t baud)
-{
-    return dw_uart_open(&dw_uart_0, baud);
-}
-/** designware uart 0 close */
-static int32_t dw_uart_0_close (void)
-{
-    return dw_uart_close(&dw_uart_0);
-}
-/** designware uart 0 control */
-static int32_t dw_uart_0_control (uint32_t ctrl_cmd, void *param)
-{
-    return dw_uart_control(&dw_uart_0, ctrl_cmd, param);
-}
-/** designware uart 0 write */
-static int32_t dw_uart_0_write (const void *data, uint32_t len)
-{
-    return dw_uart_write(&dw_uart_0, data, len);
-}
-/** designware uart 0 close */
-static int32_t dw_uart_0_read (void *data, uint32_t len)
-{
-    return dw_uart_read(&dw_uart_0, data, len);
-}
-/** designware uart 0 interrupt rountine */
-static void dw_uart_0_isr(void *ptr)
-{
-    dw_uart_isr(&dw_uart_0, ptr);
-}
-/** install designware uart 0 to system */
-static void dw_uart_0_install(void)
-{
-    uint32_t uart_abs_base = 0;
-    DEV_UART *dw_uart_ptr = &dw_uart_0;
-    DEV_UART_INFO *dw_uart_info_ptr = &(dw_uart_0.uart_info);
-    DW_UART_CTRL *dw_uart_ctrl_ptr = &dw_uart_0_ctrl;
-
-    /**
-     * get absolute designware base address
-     */
-    uart_abs_base = (uint32_t)PERIPHERAL_BASE + DW_UART_0_RELBASE;
-    dw_uart_ctrl_ptr->dw_uart_regbase = uart_abs_base;
-
-    /** uart info init */
-    dw_uart_info_ptr->uart_ctrl = (void *)dw_uart_ctrl_ptr;
-    dw_uart_info_ptr->opn_cnt = 0;
-    dw_uart_info_ptr->status = 0;
-    dw_uart_info_ptr->baudrate = UART_BAUDRATE_115200;  /* default 115200bps */
-
-    /** uart dev init */
-    dw_uart_ptr->uart_open = dw_uart_0_open;
-    dw_uart_ptr->uart_close = dw_uart_0_close;
-    dw_uart_ptr->uart_control = dw_uart_0_control;
-    dw_uart_ptr->uart_write = dw_uart_0_write;
-    dw_uart_ptr->uart_read = dw_uart_0_read;
-
-}
-#endif /* USE_DW_UART_0 */
-/** @} end of name */
-
-/**
- * \name    EMSK DesignWare UART 1 Object Instantiation
- * @{
- */
-#if (USE_DW_UART_1)
-static void dw_uart_1_isr(void *ptr);
-#define DW_UART_1_RELBASE   (REL_REGBASE_UART1) /*!< designware uart 1 relative baseaddr */
-#define DW_UART_1_INTNO     (INTNO_UART1)       /*!< designware uart 1 interrupt number  */
-
-DEV_UART        dw_uart_1;          /*!< designware uart 1 object */
-DW_UART_CTRL    dw_uart_1_ctrl = {          /*!< designware uart 1 ctrl */
-    0, CLK_BUS_APB, DW_UART_1_INTNO, (INT_HANDLER)dw_uart_1_isr,
-    DW_UART_FIFO_LEN, DW_UART_FIFO_LEN, 0
-};
-
-/** designware uart 1 open */
-static int32_t dw_uart_1_open (uint32_t baud)
-{
-    return dw_uart_open(&dw_uart_1, baud);
-}
-/** designware uart 1 close */
-static int32_t dw_uart_1_close (void)
-{
-    return dw_uart_close(&dw_uart_1);
-}
-/** designware uart 1 control */
-static int32_t dw_uart_1_control (uint32_t ctrl_cmd, void *param)
-{
-    return dw_uart_control(&dw_uart_1, ctrl_cmd, param);
-}
-/** designware uart 1 write */
-static int32_t dw_uart_1_write (const void *data, uint32_t len)
-{
-    return dw_uart_write(&dw_uart_1, data, len);
-}
-/** designware uart 1 close */
-static int32_t dw_uart_1_read (void *data, uint32_t len)
-{
-    return dw_uart_read(&dw_uart_1, data, len);
-}
-/** designware uart 1 interrupt routine */
-static void dw_uart_1_isr(void *ptr)
-{
-    dw_uart_isr(&dw_uart_1, ptr);
-}
-/** install designware uart 1 to system */
-static void dw_uart_1_install(void)
-{
-    uint32_t uart_abs_base = 0;
-    DEV_UART *dw_uart_ptr = &dw_uart_1;
-    DEV_UART_INFO *dw_uart_info_ptr = &(dw_uart_1.uart_info);
-    DW_UART_CTRL *dw_uart_ctrl_ptr = &dw_uart_1_ctrl;
-
-    /**
-     * get absolute designware base address
-     */
-    uart_abs_base = (uint32_t)PERIPHERAL_BASE + DW_UART_1_RELBASE;
-    dw_uart_ctrl_ptr->dw_uart_regbase = uart_abs_base;
-
-    /** uart info init */
-    dw_uart_info_ptr->uart_ctrl = (void *)dw_uart_ctrl_ptr;
-    dw_uart_info_ptr->opn_cnt = 0;
-    dw_uart_info_ptr->status = 0;
-    dw_uart_info_ptr->baudrate = UART_BAUDRATE_115200;  /* default 115200bps */
-
-    /** uart dev init */
-    dw_uart_ptr->uart_open = dw_uart_1_open;
-    dw_uart_ptr->uart_close = dw_uart_1_close;
-    dw_uart_ptr->uart_control = dw_uart_1_control;
-    dw_uart_ptr->uart_write = dw_uart_1_write;
-    dw_uart_ptr->uart_read = dw_uart_1_read;
-}
-#endif /* USE_DW_UART_1 */
-/** @} end of name */
-
-/** get one designware device structure */
-DEV_UART_PTR uart_get_dev(int32_t uart_id)
-{
-    static uint32_t install_flag = 0;
-
-    /* intall device objects */
-    if (install_flag == 0) {
-        install_flag = 1;
-        dw_uart_all_install();
-    }
-
-    switch (uart_id) {
-#if (USE_DW_UART_0)
-        case DW_UART_0_ID:
-            return &dw_uart_0;
-            break;
-#endif
-#if (USE_DW_UART_1)
-        case DW_UART_1_ID:
-            return &dw_uart_1;
-            break;
-#endif
-        default:
-            break;
-    }
-    return NULL;
-}
-
-/**
- * \brief   install all uart objects
- * \note    \b MUST be called during system init
- */
-void dw_uart_all_install(void)
-{
-#if (USE_DW_UART_0)
-    dw_uart_0_install();
-#endif
-#if (USE_DW_UART_1)
-    dw_uart_1_install();
-#endif
-}
diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h b/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h
deleted file mode 100644
index 7a63880fab..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _DW_UART_OBJ_H_
-#define _DW_UART_OBJ_H_
-
-#include "device/device_hal/inc/dev_uart.h"
-
-/**
- * \name    DesignWare UART Object Number
- * @{
- */
-#define DW_UART_NUM (2) /*!< DesignWare UART valid number */
-/** @} end of name */
-
-/**
- * \name    Designware UART Object ID Macros
- * @{
- */
-#define DW_UART_0_ID    0   /*!< uart 0 id macro */
-#define DW_UART_1_ID    1   /*!< uart 1 id macro */
-/** @} end of name */
-
-/**
- * \name    Designware UART Object Control Macros
- * @{
- */
-#define USE_DW_UART_0   1   /*!< enable use designware uart 0 */
-#define USE_DW_UART_1   1   /*!< enable use designware uart 1 */
-/** @} end of name */
-
-/**
- * \name    Designware UART Ringbuffer Size Control Macros
- * @{
- */
-#define MAX_SNDBUF_SIZE 256 /*!< max size of uart send buffer */
-#define MAX_RCVBUF_SIZE 10  /*!< max size of uart recv buffer */
-/** @} end of name */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern void dw_uart_all_install(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DW_UART_OBJ_H_ */
diff --git a/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h b/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h
deleted file mode 100644
index 706aac94c4..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _EMBARC_BSP_CONFIG_H_
-#define _EMBARC_BSP_CONFIG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define BOARD_EMSK
-/****************************************************************************
- * BSP Definitions
- ****************************************************************************/
-/**
- *  Toolchain Definition for MetaWare or GNU
- */
-//#define __MW__
-#define __GNU__
-
-/**
- *  Must be set.
- *  If changed, modify .lcf file for
- *  .stack ALIGN(4) SIZE(524288): {}
- *  .heap? ALIGN(4) SIZE(524288): {}
- */
-#define _STACKSIZE      (4 * 1024)
-#define _HEAPSZ         (32 * 1024)
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _EMBARC_CONFIG_BSP_H_ */
diff --git a/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h b/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h
deleted file mode 100644
index d60e314389..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _EMSK_HARDWARE_H_
-#define _EMSK_HARDWARE_H_
-
-#include "inc/arc/arc_feature_config.h"
-
-/** CPU Clock Frequency definition */
-#if defined(BOARD_CPU_FREQ)
-        /*!< Get cpu clock frequency definition from build system */
-        #define CLK_CPU                 (BOARD_CPU_FREQ)
-#elif defined(ARC_FEATURE_CPU_CLOCK_FREQ)
-        /*!< Get cpu clock frequency definition from tcf file */
-        #define CLK_CPU                 (ARC_FEATURE_CPU_CLOCK_FREQ)
-#else
-        /*!< Default cpu clock frequency */
-        #define CLK_CPU                 (20000000)
-#endif
-
-/** Peripheral Bus Reference Clock definition */
-#ifdef BOARD_DEV_FREQ
-        /*!< Get peripheral bus reference clock defintion from build system */
-        #define CLK_BUS_APB             (BOARD_DEV_FREQ)
-#else
-        /*!< Default peripheral bus reference clock defintion */
-        #define CLK_BUS_APB             (50000000U)
-#endif
-
-#ifdef ARC_FEATURE_DMP_PERIPHERAL
-#define PERIPHERAL_BASE         ARC_FEATURE_DMP_PERIPHERAL
-#else
-#define PERIPHERAL_BASE         _arc_aux_read(AUX_DMP_PERIPHERAL)
-#endif
-
-/* Device Register Base Address */
-#define REL_REGBASE_PINMUX              (0x00000000U)           /*!< PINMUX */
-#define REL_REGBASE_SPI_MST_CS_CTRL     (0x00000014U)           /*!< SPI Master Select Ctrl */
-#define REL_REGBASE_GPIO0               (0x00002000U)           /*!< GPIO 0 Onboard */
-#define REL_REGBASE_TIMERS              (0x00003000U)           /*!< DW TIMER */
-#define REL_REGBASE_I2C0                (0x00004000U)           /*!< I2C 0 */
-#define REL_REGBASE_I2C1                (0x00005000U)           /*!< I2C 1 */
-#define REL_REGBASE_SPI0                (0x00006000U)           /*!< SPI Master  */
-#define REL_REGBASE_SPI1                (0x00007000U)           /*!< SPI Slave   */
-#define REL_REGBASE_UART0               (0x00008000U)           /*!< UART0 is connected to PMOD */
-#define REL_REGBASE_UART1               (0x00009000U)           /*!< UART1 is USB-UART�� use UART1 as default */
-#define REL_REGBASE_UART2               (0x0000A000U)           /*!< UART2 */
-#define REL_REGBASE_WDT                 (0x0000B000U)           /*!< WDT  */
-// #define REL_REGBASE_I2S_MASTER_IN    (0x0000C000U)           /*!< I2S Master In  */
-// #define REL_REGBASE_I2S_MASTER_OUT   (0x0000D000U)           /*!< I2S Master Out  */
-// #define REL_REGBASE_GMAC             (0x0000E000U)           /*!< GMAC  */
-
-/* Interrupt Connection */
-#define INTNO_TIMER0                    16                      /*!< ARC Timer0 */
-#define INTNO_TIMER1                    17                      /*!< ARC Timer1 */
-#define INTNO_SECURE_TIMER0             20                      /*!< Core Secure Timer 0 */
-#define INTNO_DMA_START                 22                      /*!< Core DMA Controller */
-#define INTNO_DMA_COMPLETE              22                      /*!< Core DMA Controller Complete */
-#define INTNO_DMA_ERROR                 23                      /*!< Core DMA Controller Error */
-#define INTNO_GPIO                      24                      /*!< GPIO controller */
-#define INTNO_I2C0                      25                      /*!< I2C_0 controller */
-#define INTNO_I2C1                      26                      /*!< I2C_1 controller */
-#define INTNO_SPI_MASTER                27                      /*!< SPI Master controller */
-#define INTNO_SPI_SLAVE                 28                      /*!< SPI Slave controller */
-#define INTNO_UART0                     29                      /*!< UART0 */
-#define INTNO_UART1                     30                      /*!< UART1 */
-#define INTNO_UART2                     31                      /*!< UART2 */
-#define INTNO_DW_WDT                    32                      /*!< WDT */
-#define INTNO_DW_TMR0                   33                      /*!< DW Timer 0 */
-#define INTNO_DW_TMR1                   34                      /*!< DW Timer 1 */
-// #define INTNO_I2S_Master_In          33                      /*!< I2S Master In */
-// #define INTNO_I2S_Master_Out         34                      /*!< I2S Master Out */
-// #define INTNO_GMAC                   35                      /*!< GMAC */
-
-/* SPI Mater Signals Usage */
-#define EMSK_SPI_LINE_0                 0                       /*!< CS0 -- Pmod 6 pin1 */
-#define EMSK_SPI_LINE_1                 1                       /*!< CS1 -- Pmod 5 pin1 or Pmod 6 pin 7 */
-#define EMSK_SPI_LINE_2                 2                       /*!< CS2 -- Pmod 6 pin8 */
-#define EMSK_SPI_LINE_SDCARD            3                       /*!< CS3 -- On-board SD card  */
-#define EMSK_SPI_LINE_SPISLAVE          4                       /*!< CS4 -- Internal SPI slave */
-#define EMSK_SPI_LINE_SFLASH            5                       /*!< CS5 -- On-board SPI Flash memory */
-
-#endif  /* _EMSK_HARDWARE_H_ */
diff --git a/bsp/synopsys/emsk_em9d/drivers/mux.c b/bsp/synopsys/emsk_em9d/drivers/mux.c
deleted file mode 100644
index a56cb15212..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/mux.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include "mux_hal.h"
-#include "mux.h"
-
-static MUX_REG *mux_ctrl_regs = (MUX_REG *)0;
-
-/** initialize i2c controller and set slave device address */
-void mux_init(MUX_REG *mux_regs)
-{
-    // Initialize Mux controller registers by default values
-    mux_regs[PMOD_MUX_CTRL] = PMOD_MUX_CTRL_DEFAULT;
-    mux_regs[SPI_MAP_CTRL] =  SPI_MAP_CTRL_DEFAULT;
-    mux_regs[UART_MAP_CTRL] = UART_MAP_CTRL_DEFAULT;
-    mux_ctrl_regs = mux_regs;
-}
-
-/** Get mux ctrl register pointer, only valid after mux_init */
-MUX_REG *get_mux_regs(void)
-{
-    return mux_ctrl_regs;
-}
-
-/** set PMOD muxer scheme */
-void set_pmod_mux(MUX_REG *mux_regs, uint32_t val)
-{
-    mux_regs[PMOD_MUX_CTRL] = val;
-}
-
-/** get PMOD muxer scheme */
-uint32_t get_pmod_mux(MUX_REG *mux_regs)
-{
-    return (uint32_t) mux_regs[PMOD_MUX_CTRL];
-}
-
-/** set PMOD muxer scheme */
-void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits)
-{
-    mux_regs[PMOD_MUX_CTRL] = ((mux_regs[PMOD_MUX_CTRL] & ~change_bits) | val);
-}
-
-/** set SPI connection scheme */
-void set_spi_map(MUX_REG *mux_regs, uint32_t val)
-{
-    mux_regs[SPI_MAP_CTRL] = val;
-}
-
-/** get SPI connection scheme */
-uint32_t get_spi_map(MUX_REG *mux_regs)
-{
-    return (uint32_t) mux_regs[SPI_MAP_CTRL];
-}
-
-/** set UART connection scheme */
-void set_uart_map(MUX_REG *mux_regs, uint32_t val)
-{
-    mux_regs[UART_MAP_CTRL] = val;
-}
-
-/** get UART connection scheme */
-uint32_t get_uart_map(MUX_REG *mux_regs)
-{
-    return (uint32_t) mux_regs[UART_MAP_CTRL];
-}
diff --git a/bsp/synopsys/emsk_em9d/drivers/mux.h b/bsp/synopsys/emsk_em9d/drivers/mux.h
deleted file mode 100644
index 47f796bebe..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/mux.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _MUX_H_
-#define _MUX_H_
-
-#include "inc/embARC_toolchain.h"
-
-#define BIT0			(0)
-#define BIT1			(1)
-#define BIT2			(2)
-#define BIT3			(3)
-#define PM1_OFFSET		(0)
-#define PM2_OFFSET		(4)
-#define PM3_OFFSET		(8)
-#define PM4_OFFSET		(12)
-#define PM5_OFFSET		(16)
-#define PM6_OFFSET		(20)
-#define PM7_OFFSET		(24)
-
-#define PM1_MASK		(0xf << PM1_OFFSET)
-#define PM2_MASK		(0xf << PM2_OFFSET)
-#define PM3_MASK		(0xf << PM3_OFFSET)
-#define PM4_MASK		(0xf << PM4_OFFSET)
-#define PM5_MASK		(0xf << PM5_OFFSET)
-#define PM6_MASK		(0xf << PM6_OFFSET)
-#define PM7_MASK		(0xf << PM7_OFFSET)
-
-
-#define SPI_MAP_NORMAL		(0)
-#define SPI_MAP_LOOPBACK	(1)
-
-#define UART_MAP_TYPE4		(0xE4)
-#define UART_MAP_TYPE3		(0x6C)
-
-/**
- * \name	Default pin muxer settings
- * @{
- */
-#define PMOD_MUX_CTRL_DEFAULT	(0)			/*!< all pins are configured as GPIO inputs */
-#define SPI_MAP_CTRL_DEFAULT	(SPI_MAP_NORMAL)	/*!< normal SPI mode */
-#define UART_MAP_CTRL_DEFAULT	(UART_MAP_TYPE4)	/*!< TYPE4 PMOD compatible */
-/** @} end of name */
-
-/**
- * \name	PMOD 1 Multiplexor
- * @{
- */
-#define PM1_UR_GPIO_C		((0 << BIT0) << PM1_OFFSET)	/*!< Pmod1[4:1] are connected to DW GPIO Port C[11:8] */
-#define PM1_UR_UART_0		((1 << BIT0) << PM1_OFFSET)	/*!< Pmod1[4:1] are connected to DW UART0 signals */
-
-#define PM1_LR_GPIO_A		((0 << BIT2) << PM1_OFFSET)	/*!< Pmod1[10:7] are connected to DW GPIO Port A[11:8] */
-#define PM1_LR_SPI_S		((1 << BIT2) << PM1_OFFSET)	/*!< Pmod1[10:7] are connected to DW SPI Slave signals */
-/** @} end of name */
-
-
-/**
- * \name	PMOD 2 Multiplexor
- * @{
- */
-#define PM2_GPIO_AC		((0 << BIT0) << PM2_OFFSET)	/*!< Pmod2[4:1]	 are connected to DW GPIO Port C[15:12],
-									Pmod2[10:7] are connected to DW GPIO Port A[15:12]  */
-
-#define PM2_I2C_HRI		((1 << BIT0) << PM2_OFFSET)	/*!< connect I2C to Pmod2[4:1] and halt/run interface to Pmod2[10:7] */
-/** @} end of name */
-
-
-/**
- * \name	PMOD 3 Multiplexor
- * @{
- */
-#define PM3_GPIO_AC		((0 << BIT0) << PM3_OFFSET)	/*!< Pmod3[4:1]  are connected to DW GPIO Port C[19:16],
-									Pmod3[10:7] are connected to DW GPIO Port A[19:16]  */
-
-#define PM3_I2C_GPIO_D		((1 << BIT0) << PM3_OFFSET)	/*!< Pmod3[4:3]  are connected to DW I2C signals,
-									Pmod3[2:1]  are connected to DW GPIO Port D[1:0],
-									Pmod3[10:7] are connected to DW GPIO Port D[3:2] */
-/** @} end of name */
-
-
-/**
- * \name	PMOD 4 Multiplexor
- * @{
- */
-#define PM4_GPIO_AC		((0 << BIT0) << PM4_OFFSET)	/*!< Pmod4[4:1]  are connected to DW GPIO Port C[23:20],
-									Pmod4[10:7] are connected to DW GPIO Port A[23:20] */
-
-#define PM4_I2C_GPIO_D		((1 << BIT0) << PM4_OFFSET)	/*!< Pmod4[4:3]  are connected to DW I2C signals,
-									Pmod4[2:1]  are connected to DW GPIO Port D[5:4],
-									Pmod4[10:7] are connected to DW GPIO Port D[7:6] */
-/** @} end of name */
-
-/**
- * \name	PMOD 5 Multiplexor
- * @{
- */
-#define PM5_UR_GPIO_C		((0 << BIT0) << PM5_OFFSET)	/*!< Pmod5[4:1] are connected to DW GPIO Port C[27:24] */
-#define PM5_UR_SPI_M1		((1 << BIT0) << PM5_OFFSET)	/*!< Pmod5[4:1] are connected to DW SPI Master signals using CS1_N */
-
-#define PM5_LR_GPIO_A		((0 << BIT2) << PM5_OFFSET)	/*!< Pmod5[10:7] are connected to DW GPIO Port A[27:24] */
-#define PM5_LR_SPI_M2		((1 << BIT2) << PM5_OFFSET)	/*!< Pmod5[10:7] are connected to DW SPI Master signals using CS2_N */
-/** @} end of name */
-
-
-/**
- * \name	PMOD 6 Multiplexor
- * @{
- */
-#define PM6_UR_GPIO_C		((0 << BIT0) << PM6_OFFSET)	/*!< Pmod6[4:1] are connected to DW GPIO Port C[31:28] */
-#define PM6_UR_SPI_M0		((1 << BIT0) << PM6_OFFSET)	/*!< Pmod6[4:1] are connected to DW SPI Master signals using CS0_N */
-
-#define PM6_LR_GPIO_A		((0 << BIT2) << PM6_OFFSET)	/*!< Pmod6[10:7] are connected to DW GPIO Port A[31:28] */
-
-#define PM6_LR_CSS_STAT 	((1 << BIT2) << PM6_OFFSET)	/*!< Pmod6[8:7] are connected to the DW SPI Master chip select signals CS1_N and CS2_N,
-									Pmod6[6:5] are connected to the ARC EM halt and sleep status signals */
-/** @} end of name */
-
-/**
- * \name	PMOD 7 Multiplexor
- * @{
- */
-#define PM7_GPIO_D		((0 << BIT0) << PM7_OFFSET)	/*!< Pmod7[4:1] are connected to DW GPIO Port D[11:8] */
-#define PM7_STAT		((1 << BIT0) << PM7_OFFSET)	/*!< Pmod7[4:1] are connected to the ARC EM sleep status signals */
-/** @} end of name */
-typedef volatile uint32_t MUX_REG;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern void mux_init(MUX_REG *mux_regs);
-extern MUX_REG *get_mux_regs(void);
-extern void set_pmod_mux(MUX_REG *mux_regs, uint32_t val);
-extern uint32_t get_pmod_mux(MUX_REG *mux_regs);
-extern void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits);
-extern void set_spi_map(MUX_REG *mux_regs, uint32_t val);
-extern uint32_t get_spi_map(MUX_REG *mux_regs);
-extern void set_uart_map(MUX_REG *mux_regs, uint32_t val);
-extern uint32_t get_uart_map(MUX_REG *mux_regs);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _MUX_H_ */
diff --git a/bsp/synopsys/emsk_em9d/drivers/mux_hal.h b/bsp/synopsys/emsk_em9d/drivers/mux_hal.h
deleted file mode 100644
index 9a5c8c14b9..0000000000
--- a/bsp/synopsys/emsk_em9d/drivers/mux_hal.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _MUX_HAL_H_
-#define _MUX_HAL_H_
-
-/**
- * \name	Mux Control Register Index
- * @{
- */
-#define PMOD_MUX_CTRL	0	/*!< 32-bits, offset 0x0,
-					This register controls mapping of the peripheral device signals on Pmod connectors */
-
-#define I2C_MAP_CTRL	1	/*!< 32-bits, offset 0x4 */
-
-#define SPI_MAP_CTRL	2	/*!< 32-bits, offset 0x8,
-					SPI_MAP_CTRL[0] selects the mode of operation of the SPI Slave:
-					- Normal operation, SPI_MAP_CTRL[0]=0: SPI Slave is connected to Pmod1 at connector J1.
-					- Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to the SPI Master inside the FPGA using CS4.
-							 */
-
-#define UART_MAP_CTRL	3	/*!< 32-bits, offset 0x8,
-					This register controls the mapping of the UART signals on the Pmod1 connector. */
-/** @} end of name */
-
-
-#endif	/* _MUX_HAL_H_ */
diff --git a/bsp/synopsys/emsk_em9d/emsk_em9d.ld b/bsp/synopsys/emsk_em9d/emsk_em9d.ld
deleted file mode 100644
index 849ecf6329..0000000000
--- a/bsp/synopsys/emsk_em9d/emsk_em9d.ld
+++ /dev/null
@@ -1,114 +0,0 @@
-MEMORY
-{
- ICCM : ORIGIN = 0x00000000, LENGTH = 0x40000
- DCCM : ORIGIN = 0x80000000, LENGTH = 0x20000
- EXT_RAM : ORIGIN = 0x10000000, LENGTH = 0x8000000
-}
-ENTRY(_start)
-SECTIONS
-{
- .init :
- {
-  _f_init = .;
-  KEEP (*(.init_vector))
-  KEEP (*(.init_bootstrap))
-  _e_init = .;
- } > EXT_RAM
- .vector : ALIGN(1024)
- {
-  _f_vector = .;
-  *(.vector)
-  _e_vector = .;
- } > EXT_RAM
- .text : ALIGN(4)
- {
-  _f_text = .;
-  *(.text .text.* .gnu.linkonce.t.*)
-  _e_text = .;
- } > EXT_RAM
- .rodata : ALIGN(4)
- {
-  _f_rodata = .;
-
-  /* section information for finsh shell */
-  . = ALIGN(4);
-  __fsymtab_start = .;
-  KEEP(*(FSymTab))
-  __fsymtab_end = .;
-  . = ALIGN(4);
-  __vsymtab_start = .;
-  KEEP(*(VSymTab))
-  __vsymtab_end = .;
-
-  . = ALIGN(4);
-  __rt_init_start = .;
-  KEEP(*(SORT(.rti_fn*)))
-   __rt_init_end = .;
-  . = ALIGN(4);
-
-
-  __CTOR_LIST__ = .;
-  LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
-  KEEP(*(SORT_BY_NAME(".ctors*")))
-  LONG(0)
-  __CTOR_END__ = .;
-  . = ALIGN(4);
-  __init_array_start = .;
-  KEEP(*(SORT_BY_NAME(".init_array*")))
-  __init_array_end = .;
-  . = ALIGN(4);
-  __DTOR_LIST__ = .;
-  LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
-  KEEP(*(SORT_BY_NAME(".dtors*")))
-  LONG(0)
-  __DTOR_END__ = .;
-  *(.rodata .rodata.* .gnu.linkonce.r.*)
-  _e_rodata = .;
- } > EXT_RAM
- .data : ALIGN(4)
- {
-  _f_data = .;
-  *(.data .data.* .gnu.linkonce.d.*)
-  _f_sdata = .;
-  __SDATA_BEGIN__ = .;
-  *(.sdata .sdata.* .gnu.linkonce.s.*)
-  _e_sdata = .;
-  _e_data = .;
- } > EXT_RAM
- .bss (NOLOAD) : ALIGN(8)
- {
-  PROVIDE (__sbss_start = .);
-  PROVIDE (___sbss_start = .);
-  _f_bss = .;
-  _f_sbss = .;
-  *(.dynsbss)
-  *(.sbss .sbss.* .gnu.linkonce.sb.*)
-  *(.scommon)
-  _e_sbss = .;
-  PROVIDE (__sbss_end = .);
-  PROVIDE (___sbss_end = .);
-  *(.dynbss)
-  *(.bss .bss.* .gnu.linkonce.b.*)
-  *(COMMON)
-  _e_bss = .;
- } > EXT_RAM
- .stack (NOLOAD) :
- {
-  . = ALIGN(4);
-  _f_stack = .;
-  . = . + 4096;
-  _e_stack = .;
- } > EXT_RAM
- .heap (NOLOAD) :
- {
-  . = ALIGN(4);
-  __start_heap = . ;
-  _f_heap = .;
-  . = . + 0x8000;
-  _e_heap = .;
-  __end_heap = . ;
- } > EXT_RAM
- _load_addr_text = LOADADDR(.text);
- _load_addr_rodata = LOADADDR(.rodata);
- _load_addr_data = LOADADDR(.data);
-}
diff --git a/bsp/synopsys/emsk_em9d/figures/emsk_board.jpg b/bsp/synopsys/emsk_em9d/figures/emsk_board.jpg
deleted file mode 100644
index c96c3d6b6e..0000000000
Binary files a/bsp/synopsys/emsk_em9d/figures/emsk_board.jpg and /dev/null differ
diff --git a/bsp/synopsys/emsk_em9d/openocd.log b/bsp/synopsys/emsk_em9d/openocd.log
deleted file mode 100644
index 4ef893515e..0000000000
--- a/bsp/synopsys/emsk_em9d/openocd.log
+++ /dev/null
@@ -1,9 +0,0 @@
-Warn : deprecated option: -p/--pipe. Use '-c "gdb_port pipe; log_output openocd.log"' instead.
-adapter speed: 5000 kHz
-Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
-Info : clock speed 5000 kHz
-Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2)
-Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2)
-target state: halted
-Info : accepting 'gdb' connection from pipe
-Info : dropped 'gdb' connection
diff --git a/bsp/synopsys/emsk_em9d/rtconfig.h b/bsp/synopsys/emsk_em9d/rtconfig.h
deleted file mode 100644
index d2fab1109a..0000000000
--- a/bsp/synopsys/emsk_em9d/rtconfig.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
-
-// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
-#define RT_NAME_MAX	6
-// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
-#define RT_ALIGN_SIZE	4
-// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
-// <item description="8">8</item>
-// <item description="32">32</item>
-// <item description="256">256</item>
-// </integer>
-#define RT_THREAD_PRIORITY_MAX	32
-// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="1000" />
-#define RT_TICK_PER_SECOND	1000
-// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
-#define IDLE_THREAD_STACK_SIZE	512
-// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
-// #define RT_THREAD_DEBUG
-// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
-#define RT_USING_OVERFLOW_CHECK
-// </section>
-
-// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
-#define RT_USING_HOOK
-// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
-// #define RT_USING_TIMER_SOFT
-// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
-#define RT_TIMER_THREAD_PRIO	4
-// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
-#define RT_TIMER_THREAD_STACK_SIZE	512
-// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
-#define RT_TIMER_TICK_PER_SECOND	10
-// </section>
-
-// <section name="IPC" description="Inter-Thread communication" default="always" >
-// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
-#define RT_USING_SEMAPHORE
-// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
-#define RT_USING_MUTEX
-// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
-#define RT_USING_EVENT
-// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
-#define RT_USING_MAILBOX
-// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
-#define RT_USING_MESSAGEQUEUE
-// </section>
-
-// <section name="MM" description="Memory Management" default="always" >
-// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
-#define RT_USING_MEMPOOL
-// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
-// #define RT_USING_MEMHEAP
-// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
-#define RT_USING_HEAP
-// <bool name="RT_USING_MEMHEAP_AS_HEAP" description="Using Memory Heap Object as system heap" default="true" />
-// #define RT_USING_MEMHEAP_AS_HEAP
-// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
-#define RT_USING_SMALL_MEM
-// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
-// #define RT_USING_SLAB
-// </section>
-
-// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
-#define RT_USING_DEVICE
-// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
-#define RT_USING_DEVICE_IPC
-// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
-#define RT_USING_SERIAL
-// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
-#define RT_UART_RX_BUFFER_SIZE    64
-// <bool name=RT_USING_INTERRUPT_INFO description="Using interrupt information description" default="true" />
-#define RT_USING_INTERRUPT_INFO
-// </section>
-
-// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
-#define RT_USING_CONSOLE
-// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
-#define RT_CONSOLEBUF_SIZE	128
-// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
-#define RT_CONSOLE_DEVICE_NAME	"uart1"
-// </section>
-
-// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
-#define RT_USING_COMPONENTS_INIT
-// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
-#define RT_USING_FINSH
-// <bool name="FINSH_USING_MSH" description="Using module shell" default="true" />
-#define FINSH_USING_MSH
-// <bool name="FINSH_USING_MSH_DEFAULT" description="The default shell is msh" default="true" />
-#define FINSH_USING_MSH_DEFAULT
-// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
-#define FINSH_USING_SYMTAB
-// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
-#define FINSH_USING_DESCRIPTION
-// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
-#define FINSH_THREAD_STACK_SIZE	4096
-// </section>
-
-// <section name="LIBC" description="C Runtime library setting" default="always" >
-// <bool name="RT_USING_LIBC" description="Using C library" default="true" />
-// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
-#define RT_USING_PTHREADS
-// </section>
-
-// <section name="RT_USING_DFS" description="Device file system" default="true" >
-// #define RT_USING_DFS
-// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
-// #define DFS_USING_WORKDIR
-// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
-#define DFS_FILESYSTEMS_MAX	2
-// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
-#define DFS_FD_MAX	4
-// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
-#define RT_USING_DFS_ELMFAT
-// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
-// <item description="LFN1">1</item>
-// <item description="LFN1">2</item>
-// </integer>
-#define RT_DFS_ELM_USE_LFN	1
-// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
-#define RT_DFS_ELM_MAX_LFN	64
-// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
-// #define RT_USING_DFS_YAFFS2
-// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
-// #define RT_USING_DFS_UFFS
-// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
-// #define RT_USING_DFS_DEVFS
-// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
-// #define RT_USING_DFS_NFS
-// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
-// </section>
-// </RDTConfigurator>
-
-
-#endif
diff --git a/bsp/synopsys/emsk_em9d/rtconfig.py b/bsp/synopsys/emsk_em9d/rtconfig.py
deleted file mode 100644
index 7ba12867fd..0000000000
--- a/bsp/synopsys/emsk_em9d/rtconfig.py
+++ /dev/null
@@ -1,60 +0,0 @@
-import os
-
-# toolchains options
-ARCH='arc'
-CPU='em'
-CROSS_TOOL='gcc'
-
-if os.getenv('RTT_CC'):
-    CROSS_TOOL = os.getenv('RTT_CC')
-
-# only support GNU GCC compiler
-PLATFORM 	= 'gcc'
-EXEC_PATH 	= 'C:/arc/gnu/bin'
-
-if os.getenv('RTT_EXEC_PATH'):
-    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
-BUILD = 'debug'
-
-if PLATFORM == 'gcc':
-    # toolchains
-    PREFIX = 'arc-elf32-'
-    CC = PREFIX + 'gcc'
-    CXX = PREFIX + 'g++'
-    AS = PREFIX + 'gcc'
-    AR = PREFIX + 'ar'
-    LINK = PREFIX + 'gcc'
-    TARGET_EXT = 'elf'
-    SIZE = PREFIX + 'size'
-    OBJDUMP = PREFIX + 'objdump'
-    OBJCPY = PREFIX + 'objcopy'
-    DBG = PREFIX + 'gdb'
-    DEVICE = ' -mno-sdata -Wall -mcpu=em4_fpus -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter -mfpu=fpus_all'
-    CFLAGS = DEVICE
-    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LINK_SCRIPT = 'emsk_em9d.ld'
-    LFLAGS = DEVICE + ' -mno-sdata -nostartfiles -Wl,--gc-sections,-Map=emsk_em9d.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT
-
-    OPENOCD_SCRIPT_ROOT = 'C:/arc/gnu/share/openocd/scripts'
-    OPENOCD_CFG_FILE = OPENOCD_SCRIPT_ROOT + '/board/snps_em_sk_v2.2.cfg'
-
-    OPENOCD_OPTIONS  = '-s %s -f %s' % (OPENOCD_SCRIPT_ROOT, OPENOCD_CFG_FILE)
-
-    DBG_HW_FLAGS = ''' -ex "target remote | openocd --pipe %s" -ex "load" ''' % OPENOCD_OPTIONS
-
-
-    TARGET = 'rtthread_snps_emsk_em9d.' + TARGET_EXT
-
-    CPATH = ''
-    LPATH = ''
-
-    if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
-            SIZE + ' $TARGET \n'
-    #POST_ACTION = DBG + DBG_HW_FLAGS + TARGET
diff --git a/libcpu/arc/em/SConscript b/libcpu/arc/em/SConscript
index 49c32b689d..ff1d8c134d 100644
--- a/libcpu/arc/em/SConscript
+++ b/libcpu/arc/em/SConscript
@@ -8,9 +8,7 @@ cwd     = GetCurrentDir()
 src     = Glob('*.c')
 CPPPATH = [cwd]
 
-
-if rtconfig.PLATFORM == 'gcc':
-    src += Glob('*_gcc.S')
+src += Glob('*.S')
 
 group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
 
diff --git a/libcpu/arc/em/contex_gcc.S b/libcpu/arc/em/contex_gcc.S
deleted file mode 100644
index a8abe089bf..0000000000
--- a/libcpu/arc/em/contex_gcc.S
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * Copyright (c) 2018, Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#define __ASSEMBLY__
-#include "inc/arc/arc.h"
-#include "inc/arc/arc_asm_common.h"
-
-.global rt_interrupt_enter; .type rt_interrupt_enter, %function
-.global rt_interrupt_leave; .type rt_interrupt_leave, %function
-.global context_switch_reqflg; .type context_switch_reqflg, %object
-.global rt_interrupt_from_thread; .type rt_interrupt_from_thread, %object
-.global rt_interrupt_to_thread; .type rt_interrupt_to_thread, %object
-
-	.text
-	.align 4
-dispatcher:
-	st sp, [r0]
-	ld sp, [r1]
-	pop r0
-	j [r0]
-
-/* return routine when task dispatch happened in task context */
-dispatch_r:
-	RESTORE_NONSCRATCH_REGS
-	j	[blink]
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.global rt_hw_interrupt_disable
-.type rt_hw_interrupt_disable, %function
-rt_hw_interrupt_disable:
- 	clri r0
- 	j [blink]
-
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.global rt_hw_interrupt_enable
-.type rt_hw_interrupt_enable, %function
-rt_hw_interrupt_enable:
-	seti r0
-	j [blink]
-
-
-.global rt_hw_context_switch_interrupt
-.type rt_hw_context_switch_interrupt, %function
-rt_hw_context_switch_interrupt:
-	st r0, [rt_interrupt_from_thread]
-	st r1, [rt_interrupt_to_thread]
-	mov r0, 1
-	st r0, [context_switch_reqflg]
-	j [blink]
-
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r0 --> from
- * r1 --> to
- */
-.global rt_hw_context_switch
-.type rt_hw_context_switch, %function
-rt_hw_context_switch:
-	SAVE_NONSCRATCH_REGS
-	mov r2, dispatch_r
-	push r2
-	b dispatcher
-
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
- */
-.global rt_hw_context_switch_to
-.type rt_hw_context_switch_to, %function
-rt_hw_context_switch_to:
-	ld sp, [r0]
-	pop r0
-	j [r0]
-
-.global start_r
-.type start_r, %function
-start_r:
-	pop blink;
-	pop r1
-	pop r2
-	pop r0
-
-	j_s.d [r1]
-	kflag r2
-
-/****** exceptions and interrupts handing ******/
-/****** entry for exception handling ******/
-	.global exc_entry_cpu
-	.align 4
-exc_entry_cpu:
-
-	EXCEPTION_PROLOGUE
-
-	mov	blink,	sp
-	mov	r3, sp		/* as exception handler's para(p_excinfo) */
-
-	ld	r0, [exc_nest_count]
-	add	r1, r0, 1
-	st	r1, [exc_nest_count]
-	cmp	r0, 0
-	bne	exc_handler_1
-/* change to exception stack if interrupt happened in task context */
-	mov	sp, _e_stack
-exc_handler_1:
-	PUSH	blink
-
-	lr	r0, [AUX_ECR]
-	lsr	r0, r0, 16
-	mov	r1, exc_int_handler_table
-	ld.as	r2, [r1, r0]
-
-	mov	r0, r3
-	jl	[r2]
-
-/* interrupts are not allowed */
-ret_exc:
-	POP	sp
-	mov	r1, exc_nest_count
-	ld	r0, [r1]
-	sub	r0, r0, 1
-	cmp	r0, 0
-	bne.d	ret_exc_1
-	st	r0, [r1]
-
-	ld	r0, [context_switch_reqflg]
-	cmp	r0, 0
-	bne	ret_exc_2
-ret_exc_1:	/* return from non-task context, interrupts or exceptions are nested */
-	EXCEPTION_EPILOGUE
-	rtie
-
-/* there is a dispatch request */
-ret_exc_2:
-	/* clear dispatch request */
-	mov	r0, 0
-	st	r0, [context_switch_reqflg]
-
-	SAVE_CALLEE_REGS	/* save callee save registers */
-
-	/* clear exception bit to do exception exit by SW */
-	lr	r0, [AUX_STATUS32]
-	bclr	r0, r0, AUX_STATUS_BIT_AE
-	kflag	r0
-
-	mov	r1, ret_exc_r	/* save return address */
-	PUSH	r1
-
-	ld 	r0, [rt_interrupt_from_thread]
-	ld 	r1, [rt_interrupt_to_thread]
-	b	dispatcher
-
-ret_exc_r:
-	/* recover exception status */
-	lr	r0, [AUX_STATUS32]
-	bset	r0, r0, AUX_STATUS_BIT_AE
-	kflag	r0
-
-	RESTORE_CALLEE_REGS
-	EXCEPTION_EPILOGUE
-	rtie
-
-/****** entry for normal interrupt exception handling ******/
-	.global exc_entry_int	/* entry for interrupt handling */
-	.align 4
-exc_entry_int:
-#if ARC_FEATURE_FIRQ == 1
-/*  check whether it is P0 interrupt */
-#if ARC_FEATURE_RGF_NUM_BANKS > 1
-	lr	r0, [AUX_IRQ_ACT]
-	btst	r0, 0
-	jnz	exc_entry_firq
-#else
-	PUSH	r10
-	lr	r10, [AUX_IRQ_ACT]
-	btst	r10, 0
-	POP	r10
-	jnz	exc_entry_firq
-#endif
-#endif
-	INTERRUPT_PROLOGUE
-
-	mov	blink, sp
-
-	clri	/* disable interrupt */
-	ld	r3, [exc_nest_count]
-	add	r2, r3, 1
-	st	r2, [exc_nest_count]
-	seti	/* enable higher priority interrupt */
-
-	cmp	r3, 0
-	bne	irq_handler_1
-/* change to exception stack if interrupt happened in task context */
-	mov	sp, _e_stack
-irq_handler_1:
-	PUSH	blink
-
-	jl 	rt_interrupt_enter
-
-	lr	r0, [AUX_IRQ_CAUSE]
-	sr	r0, [AUX_IRQ_SELECT]
-	mov	r1, exc_int_handler_table
-	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
-/* handle software triggered interrupt */
-	lr	r3, [AUX_IRQ_HINT]
-	cmp	r3, r0
-	bne.d irq_hint_handled
-	xor	r3, r3, r3
-	sr	r3, [AUX_IRQ_HINT]
-irq_hint_handled:
-	lr	r3, [AUX_IRQ_PRIORITY]
-	PUSH	r3		/* save irq priority */
-
-	jl	[r2]		/* jump to interrupt handler */
-	jl	rt_interrupt_leave
-ret_int:
-	clri			/* disable interrupt */
-	POP	r3		/* irq priority */
-	POP	sp
-	mov	r1, exc_nest_count
-	ld	r0, [r1]
-	sub	r0, r0, 1
-	cmp	r0, 0
-	bne.d	ret_int_1
-	st	r0, [r1]
-
-	ld	r0, [context_switch_reqflg]
-	cmp	r0, 0
-	bne	ret_int_2
-ret_int_1:	/* return from non-task context */
-	INTERRUPT_EPILOGUE
-	rtie
-/* there is a dispatch request */
-ret_int_2:
-	/* clear dispatch request */
-	mov	r0, 0
-	st	r0, [context_switch_reqflg]
-
-	/* interrupt return by SW */
-	lr	r10, [AUX_IRQ_ACT]
-	PUSH	r10
-	bclr	r10, r10, r3	/* clear related bits in IRQ_ACT */
-	sr	r10, [AUX_IRQ_ACT]
-
-	SAVE_CALLEE_REGS	/* save callee save registers */
-	mov	r1, ret_int_r	/* save return address */
-	PUSH	r1
-
-	ld 	r0, [rt_interrupt_from_thread]
-	ld 	r1, [rt_interrupt_to_thread]
-	b	dispatcher
-
-ret_int_r:
-	RESTORE_CALLEE_REGS
-	/* recover AUX_IRQ_ACT to restore the interrup status */
-	POPAX	AUX_IRQ_ACT
-	INTERRUPT_EPILOGUE
-	rtie
\ No newline at end of file
diff --git a/libcpu/arc/em/contex_gcc_mw.S b/libcpu/arc/em/contex_gcc_mw.S
new file mode 100644
index 0000000000..81b291c1c8
--- /dev/null
+++ b/libcpu/arc/em/contex_gcc_mw.S
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2018, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define __ASSEMBLY__
+#include "include/arc/arc.h"
+#include "include/arc/arc_asm_common.h"
+
+.global rt_interrupt_enter;
+.global rt_interrupt_leave;
+.global context_switch_reqflg;
+.global rt_interrupt_from_thread;
+.global rt_interrupt_to_thread;
+.global exc_nest_count;
+.global set_hw_stack_check;
+
+	.text
+	.align 4
+dispatcher:
+	st sp, [r0]
+	ld sp, [r1]
+#if ARC_FEATURE_STACK_CHECK
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+	jl	set_hw_stack_check
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bset r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bset r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+	pop r0
+	j [r0]
+
+/* return routine when task dispatch happened in task context */
+dispatch_r:
+	RESTORE_NONSCRATCH_REGS
+	j	[blink]
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+	.global rt_hw_interrupt_disable
+	.align 4
+rt_hw_interrupt_disable:
+ 	clri r0
+ 	j [blink]
+
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+	.global rt_hw_interrupt_enable
+	.align 4
+rt_hw_interrupt_enable:
+	seti r0
+	j [blink]
+
+
+	.global rt_hw_context_switch_interrupt
+	.align 4
+rt_hw_context_switch_interrupt:
+	st r0, [rt_interrupt_from_thread]
+	st r1, [rt_interrupt_to_thread]
+	mov r0, 1
+	st r0, [context_switch_reqflg]
+	j [blink]
+
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+	.global rt_hw_context_switch
+	.align 4
+rt_hw_context_switch:
+	SAVE_NONSCRATCH_REGS
+	mov r2, dispatch_r
+	push r2
+	b dispatcher
+
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+	.global rt_hw_context_switch_to
+	.align 4
+rt_hw_context_switch_to:
+	ld sp, [r0]
+#if ARC_FEATURE_STACK_CHECK
+	mov r1, r0
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+	jl	set_hw_stack_check
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bset r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bset r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+	pop r0
+	j [r0]
+
+	.global start_r
+	.align 4
+start_r:
+	pop blink;
+	pop r1
+	pop r2
+	pop r0
+
+	j_s.d [r1]
+	kflag r2
+
+/*
+ * int __rt_ffs(int value);
+ * r0 --> value
+ */
+	.global __rt_ffs
+	.align 4
+__rt_ffs:
+	breq r0, 0, __rt_ffs_return
+	ffs r1, r0
+	add r0, r1, 1
+__rt_ffs_return:
+	j [blink]
+
+/****** exceptions and interrupts handing ******/
+/****** entry for exception handling ******/
+	.global exc_entry_cpu
+	.align 4
+exc_entry_cpu:
+
+	EXCEPTION_PROLOGUE
+
+	mov	blink,	sp
+	mov	r3, sp		/* as exception handler's para(p_excinfo) */
+
+	ld	r0, [exc_nest_count]
+	add	r1, r0, 1
+	st	r1, [exc_nest_count]
+	brne	r0, 0, exc_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+exc_handler_1:
+	PUSH	blink
+
+	lr	r0, [AUX_ECR]
+	lsr	r0, r0, 16
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]
+
+	mov	r0, r3
+	jl	[r2]
+
+/* interrupts are not allowed */
+ret_exc:
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st	r0, [r1]
+	brne	r0, 0, ret_exc_1 /* nest exception case */
+	lr	r1, [AUX_IRQ_ACT] /* nest interrupt case */
+	brne	r1, 0, ret_exc_1
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_exc_2
+ret_exc_1:	/* return from non-task context, interrupts or exceptions are nested */
+	EXCEPTION_EPILOGUE
+	rtie
+
+/* there is a dispatch request */
+ret_exc_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+
+	/* clear exception bit to do exception exit by SW */
+	lr	r0, [AUX_STATUS32]
+	bclr	r0, r0, AUX_STATUS_BIT_AE
+	kflag	r0
+
+	mov	r1, ret_exc_r	/* save return address */
+	PUSH	r1
+
+	ld 	r0, [rt_interrupt_from_thread]
+	ld 	r1, [rt_interrupt_to_thread]
+	b	dispatcher
+
+ret_exc_r:
+	/* recover exception status */
+	lr	r0, [AUX_STATUS32]
+	bset	r0, r0, AUX_STATUS_BIT_AE
+	kflag	r0
+
+	RESTORE_CALLEE_REGS
+	EXCEPTION_EPILOGUE
+	rtie
+
+/****** entry for normal interrupt exception handling ******/
+	.global exc_entry_int	/* entry for interrupt handling */
+	.align 4
+exc_entry_int:
+#if ARC_FEATURE_FIRQ == 1
+/*  check whether it is P0 interrupt */
+#if ARC_FEATURE_RGF_NUM_BANKS > 1
+	lr	r0, [AUX_IRQ_ACT]
+	btst	r0, 0
+	jnz	exc_entry_firq
+#else
+	PUSH	r10
+	lr	r10, [AUX_IRQ_ACT]
+	btst	r10, 0
+	POP	r10
+	jnz	exc_entry_firq
+#endif
+#endif
+	INTERRUPT_PROLOGUE
+
+	mov	blink, sp
+
+	clri	/* disable interrupt */
+	ld	r3, [exc_nest_count]
+	add	r2, r3, 1
+	st	r2, [exc_nest_count]
+	seti	/* enable higher priority interrupt */
+
+	brne	r3, 0, irq_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+#if ARC_FEATURE_STACK_CHECK
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+irq_handler_1:
+	PUSH	blink
+
+	jl 	rt_interrupt_enter
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	sr	r0, [AUX_IRQ_SELECT]
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
+/* handle software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d irq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+irq_hint_handled:
+	lr	r3, [AUX_IRQ_PRIORITY]
+	PUSH	r3		/* save irq priority */
+
+	jl	[r2]		/* jump to interrupt handler */
+	jl	rt_interrupt_leave
+ret_int:
+	clri			/* disable interrupt */
+	POP	r3		/* irq priority */
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st	r0, [r1]
+/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */
+	lr	r0, [AUX_IRQ_CAUSE]
+	sr	r0, [AUX_IRQ_SELECT]
+	lr 	r3, [AUX_IRQ_PRIORITY]
+	lr	r1, [AUX_IRQ_ACT]
+	bclr	r2, r1, r3
+	brne	r2, 0, ret_int_1
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_int_2
+ret_int_1:	/* return from non-task context */
+	INTERRUPT_EPILOGUE
+	rtie
+/* there is a dispatch request */
+ret_int_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	/* interrupt return by SW */
+	lr	r10, [AUX_IRQ_ACT]
+	PUSH	r10
+	bclr	r10, r10, r3	/* clear related bits in IRQ_ACT */
+	sr	r10, [AUX_IRQ_ACT]
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+	mov	r1, ret_int_r	/* save return address */
+	PUSH	r1
+
+	ld 	r0, [rt_interrupt_from_thread]
+	ld 	r1, [rt_interrupt_to_thread]
+	b	dispatcher
+
+ret_int_r:
+	RESTORE_CALLEE_REGS
+	/* recover AUX_IRQ_ACT to restore the interrup status */
+	POPAX	AUX_IRQ_ACT
+	INTERRUPT_EPILOGUE
+	rtie
+
+/****** entry for fast irq exception handling ******/
+	.global exc_entry_firq
+	.weak exc_entry_firq
+	.align 4
+exc_entry_firq:
+	SAVE_FIQ_EXC_REGS
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	mov	r1, exc_int_handler_table
+/* r2 = _kernel_exc_tbl + irqno *4 */
+	ld.as	r2, [r1, r0]
+
+/* for the case of software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d	firq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+firq_hint_handled:
+/* jump to interrupt handler */
+	mov	r0, sp
+	jl	[r2]
+
+firq_return:
+	RESTORE_FIQ_EXC_REGS
+	rtie
diff --git a/libcpu/arc/em/cpuport.c b/libcpu/arc/em/cpuport.c
index 88c2e12f9b..34f538881f 100644
--- a/libcpu/arc/em/cpuport.c
+++ b/libcpu/arc/em/cpuport.c
@@ -5,11 +5,13 @@
  */
 #include <rtthread.h>
 
-#include "inc/arc/arc_exception.h"
-
-/* enable interrupt and set interrupt priority mask */
-#define ARC_INIT_STATUS (AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1))
+#include "arc/arc_exception.h"
 
+#if ARC_FEATURE_STACK_CHECK
+#define ARC_INIT_STATUS ((1 << AUX_STATUS_BIT_SC) | AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE)
+#else
+#define ARC_INIT_STATUS (AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE)
+#endif
 
 extern void start_r(void);
 
@@ -17,6 +19,7 @@ extern void start_r(void);
 rt_uint32_t context_switch_reqflg;
 rt_uint32_t rt_interrupt_from_thread;
 rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t exc_nest_count;
 
 struct init_stack_frame {
 	rt_uint32_t pc;
@@ -66,4 +69,19 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
 void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
 {
     exception_handle = exception_handle;
-}
\ No newline at end of file
+}
+
+void set_hw_stack_check(rt_uint32_t *from, rt_uint32_t *to)
+{
+    struct rt_thread *rt_thread_to;
+	if (to != NULL) {
+        rt_thread_to = rt_container_of(to, struct rt_thread, sp);
+#if ARC_FEATURE_SEC_PRESENT
+		arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr));
+		arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size);
+#else
+		arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr));
+		arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size);
+#endif
+	}
+}
-- 
cgit v1.3.1


From 607ed935134baba572671d79561f3ae3624610b2 Mon Sep 17 00:00:00 2001
From: nongxiaoming <nongxiaoming@qq.com>
Date: Tue, 11 Feb 2020 21:39:35 +0800
Subject: [libcpu]context-m33:fix label error in context_gcc.S.

---
 libcpu/arm/cortex-m33/context_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S
index 3c7dcfa3d7..18e97c631e 100644
--- a/libcpu/arm/cortex-m33/context_gcc.S
+++ b/libcpu/arm/cortex-m33/context_gcc.S
@@ -98,7 +98,7 @@ PendSV_Handler:
     MSR     PRIMASK, r2                             /* if r1 == 0x00, do msr PRIMASK, r2 */
     BX      lr                                      /* if r1 == 0x00, do bx lr */
 
-schedule
+schedule:
     PUSH    {r2}                                    /* store interrupt state */
 
     /* clear rt_thread_switch_interrupt_flag to 0 */
-- 
cgit v1.3.1


From 7ef85206dd82f9654ffe4bbf8b3e670da752031c Mon Sep 17 00:00:00 2001
From: David Lin <linpeng1577@gmail.com>
Date: Sun, 16 Feb 2020 20:39:50 +0800
Subject: Fixed function spelling mistakes in context_iar.S

swtich_to_thread -> switch_to_thread
---
 libcpu/rx/context_iar.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/rx/context_iar.S b/libcpu/rx/context_iar.S
index 143ae00315..db02ce4d1f 100644
--- a/libcpu/rx/context_iar.S
+++ b/libcpu/rx/context_iar.S
@@ -73,12 +73,12 @@ ___interrupt_27:
     MOV.L    #_rt_interrupt_from_thread, R15
     MOV.L    [ R15 ], R15
     MOV.L    R0, [ R15 ]
-    BRA      swtich_to_thread
+    BRA      switch_to_thread
 need_modify_isp:
     MVFC     ISP, R15                
     ADD      #12, R15
     MVTC     R15, ISP
-swtich_to_thread:
+switch_to_thread:
     SETPSW   U
     MOV.L    #_rt_interrupt_to_thread, R15
     MOV.L    [ R15 ], R15
-- 
cgit v1.3.1


From 36d2652f0d560f7ceffdf9f2660b59c486b1f175 Mon Sep 17 00:00:00 2001
From: David Lin <linpeng1577@gmail.com>
Date: Mon, 17 Feb 2020 09:13:17 +0800
Subject: Fixed typo 'threah' and 'swithc' in cpuport.c

Fixed typo:
    threah -> thread
    swithc -> switch
---
 libcpu/rx/cpuport.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c
index e8a75c629e..681c0e8e6e 100644
--- a/libcpu/rx/cpuport.c
+++ b/libcpu/rx/cpuport.c
@@ -58,7 +58,7 @@ struct stack_frame
 };
 
 /**
- * Initilial the threah stack.
+ * Initilial the thread stack.
  * 
  * @author LXZ (2014/11/8)
  * 
@@ -158,7 +158,7 @@ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to)
     ENTER_INTERRUPT();
 }
 /**
- * swithc thread out the interrupt
+ * switch thread out the interrupt
  * 
  * @author LXZ (2014/11/8)
  * 
-- 
cgit v1.3.1


From 0471b6d344edff643609f12c680a37336c52c8b4 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 20 Feb 2020 15:42:10 +0800
Subject: [bsp/raspi3] raspi3 mmu

---
 bsp/raspberry-pi/raspi3-64/driver/SConscript |   1 -
 bsp/raspberry-pi/raspi3-64/driver/board.c    | 152 +----------
 libcpu/aarch64/cortex-a53/mmu.c              | 373 +++++++++++++++++----------
 libcpu/aarch64/cortex-a53/mmu.h              |  79 ++----
 4 files changed, 264 insertions(+), 341 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi3-64/driver/SConscript b/bsp/raspberry-pi/raspi3-64/driver/SConscript
index 2c19b9436d..b11a0ba371 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/SConscript
+++ b/bsp/raspberry-pi/raspi3-64/driver/SConscript
@@ -7,7 +7,6 @@ src     = Split('''
 board.c
 bcm283x.c
 drv_uart.c
-mbox.c
 ''')
 CPPPATH = [cwd]
 
diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c
index 3c218d09a7..564725b9c5 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/board.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.c
@@ -16,6 +16,7 @@
 #include "drv_timer.h"
 
 #include "cp15.h"
+#include "mmu.h"
 
 #ifdef RT_USING_SMP
 extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
@@ -57,156 +58,17 @@ void idle_wfi(void)
     asm volatile ("wfi");
 }
 
-#define MMU_LEVEL_MASK 0x1ffUL
-#define MMU_MAP_ERROR_VANOTALIGN  -1
-#define MMU_MAP_ERROR_PANOTALIGN  -2
-#define MMU_MAP_ERROR_NOPAGE      -3
-#define MMU_MAP_ERROR_CONFLICT    -4
-
-unsigned char main_tbl[4096] __attribute__((aligned (4096)));
-unsigned char __page_start[4096*100] __attribute__((aligned (4096)));
-unsigned long __page_off = 0;
-unsigned long get_free_page(void) {
-    __page_off += 4096;
-    return (unsigned long)(__page_start + __page_off - 4096);
-}
-
-#define MEM_ATTR_MEM ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
-#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
-
-static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) {
-    int level;
-    unsigned long* cur_lv_tbl = lv0_tbl;
-    unsigned long page;
-    unsigned long off;
-    int level_shift = 39;
-
-    if (va & (0x200000UL - 1)) {
-        return MMU_MAP_ERROR_VANOTALIGN;
-    }
-    if (pa & (0x200000UL - 1)) {
-        return MMU_MAP_ERROR_PANOTALIGN;
-    }
-    for (level = 0; level < 2; level++) {
-        off = (va >> level_shift);
-        off &= MMU_LEVEL_MASK;
-        if ((cur_lv_tbl[off] & 1) == 0) {
-            page = get_free_page();
-            if (!page) {
-                return MMU_MAP_ERROR_NOPAGE;
-            }
-            rt_memset((void *)page, 0, 4096);
-            cur_lv_tbl[off] = page | 0x3UL;
-        }
-        page = cur_lv_tbl[off];
-        if (!(page & 0x2)) {
-            //is block! error!
-            return MMU_MAP_ERROR_CONFLICT;
-        }
-        cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
-        level_shift -= 9;
-    }
-    attr &= 0xfff0000000000ffcUL;
-    pa |= (attr | 0x1UL); //block
-    off = (va >> 21);
-    off &= MMU_LEVEL_MASK;
-    cur_lv_tbl[off] = pa;
-    return 0;
-}
-
-int armv8_map_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, int count, unsigned long attr)
-{
-	int i;
-    int ret;
-
-	if (va & (0x200000 - 1))
-	{
-		return -1;
-	}
-	if (pa & (0x200000 - 1))
-	{
-		return -1;
-	}
-	for (i = 0; i < count; i++)
-	{
-		ret = map_single_page_2M(lv0_tbl, va, pa, attr);
-		va += 0x200000;
-		pa += 0x200000;
-        if (ret != 0)
-        {
-            return ret;
-        }
-	}
-    return 0;
-}
-
 /**
  *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
  *  after interrupt disabled.
  */
 void rt_hw_board_init(void)
 {
-    /* mmu set */
-    unsigned long val64;
-    unsigned long val32; //val32不是uint32_t,val32只是表示相关的那个寄存器是32位的
-    int ret;
-
-    val64 = 0x007f6eUL;
-    asm volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
-    asm volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
-
-    //TCR_EL1
-    val32 = (16UL << 0)
-        | (0x0UL << 6)
-        | (0x0UL << 7)
-        | (0x3UL << 8)
-        | (0x3UL << 10)
-        | (0x2UL << 12)
-        | (0x0UL << 14)
-        | (0x0UL << 16)
-        | (0x0UL << 22)
-        | (0x1UL << 23)
-        | (0x2UL << 30)
-        | (0x1UL << 32)
-        | (0x0UL << 35)
-        | (0x0UL << 36)
-        | (0x0UL << 37)
-        | (0x0UL << 38);
-    asm volatile("msr TCR_EL1, %0\n"::"r"(val32));
-    asm volatile("mrs %0, TCR_EL1\n":"=r"(val32));
-
-    asm volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
-    asm volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
-
-    rt_memset(main_tbl, 0, 4096);
-
-	ret = armv8_map_2M((unsigned long *)main_tbl, 0x0, 0x0, 32, MEM_ATTR_MEM); //32*2M = 64M
-    if (ret)
-    {
-        goto skip_mmu;
-    }
-	ret = armv8_map_2M((unsigned long *)main_tbl, 0x3f000000, 0x3f000000, 8, MEM_ATTR_IO); //8*2M = 16M
-    if (ret)
-    {
-        goto skip_mmu;
-    }
-
-	//关闭指令cache
-	__asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
-	val64 &= ~0x1000; //disable I
-	__asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
-
-	//清除指令cache
-	__asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
-	//清除tlb
-	__asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
-
-	//SCTLR_EL1, turn on mmu
-	asm volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
-	val32 |= 0x1005; //enable mmu, I C M
-	asm volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
-
-skip_mmu:
+    mmu_init();//初始化mmu
+    armv8_map(0, 0, 0x800000, MEM_ATTR_MEMORY);
+    armv8_map(0x3f00B000, 0x3f00B000, 0x1000, MEM_ATTR_IO);//timer
+    armv8_map(0x3f200000, 0x3f200000, 0x16000, MEM_ATTR_IO);//uart
+    mmu_enable();
 
     /* initialize hardware interrupt */
     rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
@@ -232,7 +94,7 @@ skip_mmu:
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
-	rt_kprintf("__page_off = %x\n", __page_off);
+
 }
 
 #ifdef RT_USING_SMP
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
index 29934b26a4..0a1a5b36ad 100644
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ b/libcpu/aarch64/cortex-a53/mmu.c
@@ -1,186 +1,277 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       Notes
- * 2012-01-10     bernard      porting to AM1808
- * 2019-07-28     zdzn         add smp support
+ * Date           Author             Notes
+ * 2020-02-20     bigmagic           first version
  */
 
-#include "mmu.h"
+#include <mmu.h>
+#include <stddef.h>
 
-/* dump 2nd level page table */
-void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
+#define TTBR_CNP    1
+
+typedef unsigned long int	uint64_t;
+
+static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
+
+#define IS_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
+
+//映射方式
+#define PMD_TYPE_SECT		(1 << 0)
+
+#define PMD_TYPE_TABLE		(3 << 0)
+
+#define PTE_TYPE_PAGE		(3 << 0)
+
+#define BITS_PER_VA                39
+
+/* Granule size of 4KB is being used */
+#define GRANULE_SIZE_SHIFT         12
+#define GRANULE_SIZE               (1 << GRANULE_SIZE_SHIFT)
+#define XLAT_ADDR_MASK             ((1UL << BITS_PER_VA) - GRANULE_SIZE)
 
-    for (i = 0; i < 256; i++)
+#define PMD_TYPE_MASK		(3 << 0)
+
+int free_idx = 1;
+
+void mmu_memset(char *dst, char v,  size_t len)
+{
+    while (len--)
     {
-        rt_uint32_t pte2 = ptb[i];
-        if ((pte2 & 0x3) == 0)
-        {
-            if (fcnt == 0)
-                rt_kprintf("    ");
-            rt_kprintf("%04x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
+        *dst++ = v;
+    }
+}
 
-        rt_kprintf("    %04x: %x: ", i, pte2);
-        if ((pte2 & 0x3) == 0x1)
-        {
-            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
-                       (pte2 >> 15) & 0x1,
-                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+static unsigned long __page_off = 0;
+static unsigned long get_free_page(void) {
+    __page_off += 512;
+    return (unsigned long)(main_tbl + __page_off);
+}
+
+void mmu_init(void)
+{
+    unsigned long val64;
+    unsigned long val32; //val32不是uint32_t,val32只是表示相关的那个寄存器是32位的
+
+    val64 = 0x007f6eUL;
+    __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
+    __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
+
+    //TCR_EL1
+    val32 = (16UL << 0)//48 位
+        | (0x0UL << 6)//没有用到
+        | (0x0UL << 7)//使能enable lower half
+        | (0x3UL << 8)//写回模式，没有cahce访问
+        | (0x3UL << 10)//Inner Shareable
+        | (0x2UL << 12)
+        | (0x0UL << 14)//4K
+        | (0x0UL << 16)
+        | (0x0UL << 22)
+        | (0x1UL << 23)
+        | (0x2UL << 30)
+        | (0x1UL << 32)
+        | (0x0UL << 35)
+        | (0x0UL << 36)
+        | (0x0UL << 37)
+        | (0x0UL << 38);
+    __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32));
+    __asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32));
+
+    __asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
+    __asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
+
+    mmu_memset((char *)main_tbl, 0, 4096);
+}
+
+void mmu_enable(void)
+{
+    unsigned long val64;
+    unsigned long val32;
+
+    //关闭指令cache
+    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
+    val64 &= ~0x1000; //disable I
+    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
+
+    //清除指令cache
+    __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
+    //清除tlb
+    __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
+
+    //SCTLR_EL1, turn on mmu
+    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
+    val32 |= 0x1005; //enable mmu, I C M
+    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
+}
+
+static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) {
+    int level;
+    unsigned long* cur_lv_tbl = lv0_tbl;
+    unsigned long page;
+    unsigned long off;
+    int level_shift = 39;
+
+    if (va & (0x200000UL - 1)) {
+        return MMU_MAP_ERROR_VANOTALIGN;
+    }
+    if (pa & (0x200000UL - 1)) {
+        return MMU_MAP_ERROR_PANOTALIGN;
+    }
+    for (level = 0; level < 2; level++) {
+        off = (va >> level_shift);
+        off &= MMU_LEVEL_MASK;
+        if ((cur_lv_tbl[off] & 1) == 0) {
+            page = get_free_page();
+            if (!page) {
+                return MMU_MAP_ERROR_NOPAGE;
+            }
+            mmu_memset((char *)page, 0, 4096);
+            cur_lv_tbl[off] = page | 0x3UL;
         }
-        else
-        {
-            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
-                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        page = cur_lv_tbl[off];
+        if (!(page & 0x2)) {
+            //is block! error!
+            return MMU_MAP_ERROR_CONFLICT;
         }
+        cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
+        level_shift -= 9;
     }
+    attr &= 0xfff0000000000ffcUL;
+    pa |= (attr | 0x1UL); //block
+    off = (va >> 21);
+    off &= MMU_LEVEL_MASK;
+    cur_lv_tbl[off] = pa;
+    return 0;
 }
 
-void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr)
 {
     int i;
-    int fcnt = 0;
+    int ret;
 
-    rt_kprintf("page table@%p\n", ptb);
-    for (i = 0; i < 1024*4; i++)
+    if (va & (0x200000 - 1))
     {
-        rt_uint32_t pte1 = ptb[i];
-        if ((pte1 & 0x3) == 0)
-        {
-            rt_kprintf("%03x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("%03x: %08x: ", i, pte1);
-        if ((pte1 & 0x3) == 0x3)
-        {
-            rt_kprintf("LPAE\n");
-        }
-        else if ((pte1 & 0x3) == 0x1)
-        {
-            rt_kprintf("pte,ns:%d,domain:%d\n",
-                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
-            /*
-             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
-             *                               - 0x80000000 + 0xC0000000));
-             */
-        }
-        else if (pte1 & (1 << 18))
-        {
-            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
-        }
-        else
+        return -1;
+    }
+    if (pa & (0x200000 - 1))
+    {
+        return -1;
+    }
+    for (i = 0; i < count; i++)
+    {
+        ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr);
+        va += 0x200000;
+        pa += 0x200000;
+        if (ret != 0)
         {
-            rt_kprintf("section,ns:%d,ap:%x,"
-                       "xn:%d,texcb:%02x,domain:%d\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       (((pte1 & (0x7 << 12)) >> 10) |
-                        ((pte1 &        0x0c) >>  2)) & 0x1f,
-                       (pte1 >> 5) & 0xf);
+            return ret;
         }
     }
+    return 0;
+}
+
+//将表的地址映射到其他的地方去
+static void set_table(uint64_t *pt, uint64_t *table_addr)
+{
+	uint64_t val;
+    //0x607
+
+	val = (0x3UL | (uint64_t)table_addr);//(0x3UL | (uint64_t)table_addr);
+	*pt = val;
 }
 
-/* level1 page table, each entry for 1MB memory. */
-volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
-void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
-                      rt_uint32_t vaddrEnd,
-                      rt_uint32_t paddrStart,
-                      rt_uint32_t attr)
+void mmu_memset2(unsigned char *dst, char v,  int len)
 {
-    volatile rt_uint32_t *pTT;
-    volatile int i, nSec;
-    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
-    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
-    for(i = 0; i <= nSec; i++)
+    while (len--)
     {
-        *pTT = attr | (((paddrStart >> 20) + i) << 20);
-        pTT++;
+        *dst++ = v;
     }
 }
 
-unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+static uint64_t *create_table(void)
 {
-#if 0
-    unsigned long old_domain;
-
-    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
-    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
-
-    return old_domain;
-#else
-    return 0;
-#endif
+	uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE;
+	/* Mark all entries as invalid */
+	mmu_memset2((unsigned char *)new_table, 0, 4096);
+	free_idx++;
+	return new_table;
 }
 
-void rt_hw_init_mmu_table()
+static int pte_type(uint64_t *pte)
 {
-    /* set page table */
-    /* 4G 1:1 memory */
-    rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
-    /* IO memory region */
-    rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
+	return *pte & PMD_TYPE_MASK;
 }
 
-void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
-                      rt_uint32_t size,
-                      rt_uint32_t paddrStart, rt_uint32_t attr)
+static int level2shift(int level)
 {
-    rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
+	/* Page is 12 bits wide, every level translates 9 bits */
+    //
+	return (12 + 9 * (3 - level));
 }
 
-void rt_hw_mmu_init(void)
+
+uint64_t *test_table = 0;
+
+
+
+//根据表映射
+static uint64_t *get_level_table(uint64_t *pte)
 {
-    rt_cpu_dcache_clean_flush();
-    rt_cpu_icache_flush();
-    rt_hw_cpu_dcache_disable();
-    rt_hw_cpu_icache_disable();
-    rt_cpu_mmu_disable();
+	uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
+	
+	if (pte_type(pte) != PMD_TYPE_TABLE) {
+		table = create_table();
+		set_table(pte, table);
+	}
+	return table;
+}
 
-    /*rt_hw_cpu_dump_page_table(MMUTable);*/
-    rt_hw_set_domain_register(0x55555555);
 
-    rt_cpu_tlb_set(MMUTable);
+static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
+{
+	uint64_t block_size = 0;
+	uint64_t block_shift = 0;
+	uint64_t *pte;
+	uint64_t idx = 0;
+	uint64_t addr = 0;
+	uint64_t *table = 0;
+	int level = 0;
 
-    rt_cpu_mmu_enable();
+	addr = virt;
+	while (size) {
+		table = &main_tbl[0];//将一级页表的地址赋值
+		for (level = 0; level < 4; level++) {
+			block_shift = level2shift(level);
+            idx = addr >> block_shift;
+			idx = idx%512;
+            block_size = (uint64_t)(1L << block_shift);
+			pte = table + idx;
 
-    rt_hw_cpu_icache_enable();
-    rt_hw_cpu_dcache_enable();
+			if (size >= block_size && IS_ALIGNED(addr, block_size)) {
+                attr &= 0xfff0000000000ffcUL;
+                if(level != 3)
+                {
+                    *pte = phys | (attr | 0x1UL);
+                }
+                else
+                {
+                    *pte = phys | (attr | 0x3UL);
+                }
+				addr += block_size;
+				phys += block_size;
+				size -= block_size;
+				break;
+			}
+			table = get_level_table(pte);
+		}
+	}
 }
+
+void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr)
+{
+    map_region(va, pa, size, attr);
+}
+
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
index 5bef609486..6b68922e5a 100644
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ b/libcpu/aarch64/cortex-a53/mmu.h
@@ -1,60 +1,31 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       Notes
- * 2020-01-15     bigmagic     the first version
+ * Date           Author             Notes
+ * 2020-02-20     bigmagic           first version
  */
-#ifndef MMU_H__
-#define MMU_H__
-#include <rtthread.h>
-#include <rthw.h>
-#include <board.h>
-#include "cp15.h"
-
-#define DESC_SEC       (0x2)
-#define CB             (3<<2)  //cache_on, write_back
-#define CNB            (2<<2)  //cache_on, write_through
-#define NCB            (1<<2)  //cache_off,WR_BUF on
-#define NCNB           (0<<2)  //cache_off,WR_BUF off
-#define AP_RW          (3<<10) //supervisor=RW, user=RW
-#define AP_RO          (2<<10) //supervisor=RW, user=RO
-#define XN             (1<<4)  // eXecute Never
-#define SHARED         (1<<16) /* shareable */
-#define SHAREDEVICE    (1<<2)  /* shared device */
-#define STRONGORDER    (0<<2)  /* strong ordered */
-#define MEMWBWA        ((1<<12)|(3<<2))     /* write back, write allocate */
-
-#define DOMAIN_FAULT   (0x0)
-#define DOMAIN_CHK     (0x1)
-#define DOMAIN_NOTCHK  (0x3)
-#define DOMAIN0        (0x0<<5)
-#define DOMAIN1        (0x1<<5)
-
-#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
-
-/* Read/Write, cache, write back */
-#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
-/* Read/Write, cache, write through */
-#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
-/* Read/Write without cache and write buffer */
-#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
-/* Read/Write without cache and write buffer, no execute */
-#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
-/* Read/Write without cache and write buffer */
-#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
-
-/* device mapping type */
-#define DEVICE_MEM     (SHARED|SHAREDEVICE|RW_NCNBXN)
-/* normal memory mapping type */
-#define NORMAL_MEM     (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)
-#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC)
-#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000) | 0xC0000000)
-
-void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
-                      rt_uint32_t size,
-                      rt_uint32_t paddrStart, rt_uint32_t attr);
-#endif
+
+#ifndef  __MMU_H__
+#define  __MMU_H__
+
+#define MMU_LEVEL_MASK 0x1ffUL
+#define MMU_MAP_ERROR_VANOTALIGN  -1
+#define MMU_MAP_ERROR_PANOTALIGN  -2
+#define MMU_MAP_ERROR_NOPAGE      -3
+#define MMU_MAP_ERROR_CONFLICT    -4
+
+#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
+#define MEM_ATTR_IO     ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
+
+void mmu_init(void);
+
+void mmu_enable(void);
+
+int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr);
+
+void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
+
+#endif  /*__MMU_H__*/
-- 
cgit v1.3.1


From 0458f0b79804489759c078b5a601fa078b195f35 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 20 Feb 2020 22:57:07 +0800
Subject: remove comments in Chinese and keep the code style

---
 bsp/raspberry-pi/raspi3-64/driver/board.c |  2 +-
 libcpu/aarch64/cortex-a53/mmu.c           | 72 +++++++++++++++----------------
 libcpu/aarch64/cortex-a53/mmu.h           |  2 +-
 3 files changed, 36 insertions(+), 40 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c
index 564725b9c5..00f27e0cc8 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/board.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.c
@@ -64,7 +64,7 @@ void idle_wfi(void)
  */
 void rt_hw_board_init(void)
 {
-    mmu_init();//初始化mmu
+    mmu_init();
     armv8_map(0, 0, 0x800000, MEM_ATTR_MEMORY);
     armv8_map(0x3f00B000, 0x3f00B000, 0x1000, MEM_ATTR_IO);//timer
     armv8_map(0x3f200000, 0x3f200000, 0x16000, MEM_ATTR_IO);//uart
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
index 0a1a5b36ad..d9e49c9cf8 100644
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ b/libcpu/aarch64/cortex-a53/mmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,6 @@
  * Date           Author             Notes
  * 2020-02-20     bigmagic           first version
  */
-
 #include <mmu.h>
 #include <stddef.h>
 
@@ -19,21 +18,20 @@ static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
 
 #define IS_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
 
-//映射方式
 #define PMD_TYPE_SECT		(1 << 0)
 
 #define PMD_TYPE_TABLE		(3 << 0)
 
 #define PTE_TYPE_PAGE		(3 << 0)
 
-#define BITS_PER_VA                39
+#define BITS_PER_VA          39
 
 /* Granule size of 4KB is being used */
 #define GRANULE_SIZE_SHIFT         12
 #define GRANULE_SIZE               (1 << GRANULE_SIZE_SHIFT)
 #define XLAT_ADDR_MASK             ((1UL << BITS_PER_VA) - GRANULE_SIZE)
 
-#define PMD_TYPE_MASK		(3 << 0)
+#define PMD_TYPE_MASK		       (3 << 0)
 
 int free_idx = 1;
 
@@ -46,7 +44,8 @@ void mmu_memset(char *dst, char v,  size_t len)
 }
 
 static unsigned long __page_off = 0;
-static unsigned long get_free_page(void) {
+static unsigned long get_free_page(void) 
+{
     __page_off += 512;
     return (unsigned long)(main_tbl + __page_off);
 }
@@ -54,17 +53,17 @@ static unsigned long get_free_page(void) {
 void mmu_init(void)
 {
     unsigned long val64;
-    unsigned long val32; //val32不是uint32_t,val32只是表示相关的那个寄存器是32位的
+    unsigned long val32;
 
     val64 = 0x007f6eUL;
     __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
     __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
 
     //TCR_EL1
-    val32 = (16UL << 0)//48 位
-        | (0x0UL << 6)//没有用到
-        | (0x0UL << 7)//使能enable lower half
-        | (0x3UL << 8)//写回模式，没有cahce访问
+    val32 = (16UL << 0)//48bit
+        | (0x0UL << 6)
+        | (0x0UL << 7)
+        | (0x3UL << 8)
         | (0x3UL << 10)//Inner Shareable
         | (0x2UL << 12)
         | (0x0UL << 14)//4K
@@ -91,14 +90,11 @@ void mmu_enable(void)
     unsigned long val64;
     unsigned long val32;
 
-    //关闭指令cache
     __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
     val64 &= ~0x1000; //disable I
     __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
 
-    //清除指令cache
     __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
-    //清除tlb
     __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
 
     //SCTLR_EL1, turn on mmu
@@ -107,32 +103,39 @@ void mmu_enable(void)
     __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
 }
 
-static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) {
+static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
+{
     int level;
     unsigned long* cur_lv_tbl = lv0_tbl;
     unsigned long page;
     unsigned long off;
     int level_shift = 39;
 
-    if (va & (0x200000UL - 1)) {
+    if (va & (0x200000UL - 1)) 
+    {
         return MMU_MAP_ERROR_VANOTALIGN;
     }
-    if (pa & (0x200000UL - 1)) {
+    if (pa & (0x200000UL - 1)) 
+    {
         return MMU_MAP_ERROR_PANOTALIGN;
     }
-    for (level = 0; level < 2; level++) {
+    for (level = 0; level < 2; level++) 
+    {
         off = (va >> level_shift);
         off &= MMU_LEVEL_MASK;
-        if ((cur_lv_tbl[off] & 1) == 0) {
+        if ((cur_lv_tbl[off] & 1) == 0) 
+        {
             page = get_free_page();
-            if (!page) {
+            if (!page) 
+            {
                 return MMU_MAP_ERROR_NOPAGE;
             }
             mmu_memset((char *)page, 0, 4096);
             cur_lv_tbl[off] = page | 0x3UL;
         }
         page = cur_lv_tbl[off];
-        if (!(page & 0x2)) {
+        if (!(page & 0x2)) 
+        {
             //is block! error!
             return MMU_MAP_ERROR_CONFLICT;
         }
@@ -173,13 +176,10 @@ int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long at
     return 0;
 }
 
-//将表的地址映射到其他的地方去
 static void set_table(uint64_t *pt, uint64_t *table_addr)
 {
 	uint64_t val;
-    //0x607
-
-	val = (0x3UL | (uint64_t)table_addr);//(0x3UL | (uint64_t)table_addr);
+	val = (0x3UL | (uint64_t)table_addr);
 	*pt = val;
 }
 
@@ -208,28 +208,21 @@ static int pte_type(uint64_t *pte)
 static int level2shift(int level)
 {
 	/* Page is 12 bits wide, every level translates 9 bits */
-    //
 	return (12 + 9 * (3 - level));
 }
 
-
-uint64_t *test_table = 0;
-
-
-
-//根据表映射
 static uint64_t *get_level_table(uint64_t *pte)
 {
 	uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
 	
-	if (pte_type(pte) != PMD_TYPE_TABLE) {
+	if (pte_type(pte) != PMD_TYPE_TABLE) 
+    {
 		table = create_table();
 		set_table(pte, table);
 	}
 	return table;
 }
 
-
 static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
 {
 	uint64_t block_size = 0;
@@ -241,16 +234,19 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
 	int level = 0;
 
 	addr = virt;
-	while (size) {
-		table = &main_tbl[0];//将一级页表的地址赋值
-		for (level = 0; level < 4; level++) {
+	while (size) 
+    {
+		table = &main_tbl[0];
+		for (level = 0; level < 4; level++) 
+        {
 			block_shift = level2shift(level);
             idx = addr >> block_shift;
 			idx = idx%512;
             block_size = (uint64_t)(1L << block_shift);
 			pte = table + idx;
 
-			if (size >= block_size && IS_ALIGNED(addr, block_size)) {
+			if (size >= block_size && IS_ALIGNED(addr, block_size)) 
+            {
                 attr &= 0xfff0000000000ffcUL;
                 if(level != 3)
                 {
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
index 6b68922e5a..15e014deb6 100644
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ b/libcpu/aarch64/cortex-a53/mmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
-- 
cgit v1.3.1


From 2d3ae92075737d555ea5b83f31fece121c7c5a9a Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Fri, 21 Feb 2020 21:29:06 +0800
Subject: space instead of table keep the code style

---
 libcpu/aarch64/cortex-a53/mmu.c | 96 ++++++++++++++++++++---------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
index d9e49c9cf8..aab6bf9ebe 100644
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ b/libcpu/aarch64/cortex-a53/mmu.c
@@ -12,17 +12,17 @@
 
 #define TTBR_CNP    1
 
-typedef unsigned long int	uint64_t;
+typedef unsigned long int    uint64_t;
 
 static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
 
-#define IS_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
+#define IS_ALIGNED(x, a)        (((x) & ((typeof(x))(a) - 1)) == 0)
 
-#define PMD_TYPE_SECT		(1 << 0)
+#define PMD_TYPE_SECT        (1 << 0)
 
-#define PMD_TYPE_TABLE		(3 << 0)
+#define PMD_TYPE_TABLE        (3 << 0)
 
-#define PTE_TYPE_PAGE		(3 << 0)
+#define PTE_TYPE_PAGE        (3 << 0)
 
 #define BITS_PER_VA          39
 
@@ -31,7 +31,7 @@ static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
 #define GRANULE_SIZE               (1 << GRANULE_SIZE_SHIFT)
 #define XLAT_ADDR_MASK             ((1UL << BITS_PER_VA) - GRANULE_SIZE)
 
-#define PMD_TYPE_MASK		       (3 << 0)
+#define PMD_TYPE_MASK               (3 << 0)
 
 int free_idx = 1;
 
@@ -178,9 +178,9 @@ int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long at
 
 static void set_table(uint64_t *pt, uint64_t *table_addr)
 {
-	uint64_t val;
-	val = (0x3UL | (uint64_t)table_addr);
-	*pt = val;
+    uint64_t val;
+    val = (0x3UL | (uint64_t)table_addr);
+    *pt = val;
 }
 
 void mmu_memset2(unsigned char *dst, char v,  int len)
@@ -193,59 +193,59 @@ void mmu_memset2(unsigned char *dst, char v,  int len)
 
 static uint64_t *create_table(void)
 {
-	uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE;
-	/* Mark all entries as invalid */
-	mmu_memset2((unsigned char *)new_table, 0, 4096);
-	free_idx++;
-	return new_table;
+    uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE;
+    /* Mark all entries as invalid */
+    mmu_memset2((unsigned char *)new_table, 0, 4096);
+    free_idx++;
+    return new_table;
 }
 
 static int pte_type(uint64_t *pte)
 {
-	return *pte & PMD_TYPE_MASK;
+    return *pte & PMD_TYPE_MASK;
 }
 
 static int level2shift(int level)
 {
-	/* Page is 12 bits wide, every level translates 9 bits */
-	return (12 + 9 * (3 - level));
+    /* Page is 12 bits wide, every level translates 9 bits */
+    return (12 + 9 * (3 - level));
 }
 
 static uint64_t *get_level_table(uint64_t *pte)
 {
-	uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
-	
-	if (pte_type(pte) != PMD_TYPE_TABLE) 
+    uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
+    
+    if (pte_type(pte) != PMD_TYPE_TABLE) 
     {
-		table = create_table();
-		set_table(pte, table);
-	}
-	return table;
+        table = create_table();
+        set_table(pte, table);
+    }
+    return table;
 }
 
 static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
 {
-	uint64_t block_size = 0;
-	uint64_t block_shift = 0;
-	uint64_t *pte;
-	uint64_t idx = 0;
-	uint64_t addr = 0;
-	uint64_t *table = 0;
-	int level = 0;
-
-	addr = virt;
-	while (size) 
+    uint64_t block_size = 0;
+    uint64_t block_shift = 0;
+    uint64_t *pte;
+    uint64_t idx = 0;
+    uint64_t addr = 0;
+    uint64_t *table = 0;
+    int level = 0;
+
+    addr = virt;
+    while (size) 
     {
-		table = &main_tbl[0];
-		for (level = 0; level < 4; level++) 
+        table = &main_tbl[0];
+        for (level = 0; level < 4; level++) 
         {
-			block_shift = level2shift(level);
+            block_shift = level2shift(level);
             idx = addr >> block_shift;
-			idx = idx%512;
+            idx = idx%512;
             block_size = (uint64_t)(1L << block_shift);
-			pte = table + idx;
+            pte = table + idx;
 
-			if (size >= block_size && IS_ALIGNED(addr, block_size)) 
+            if (size >= block_size && IS_ALIGNED(addr, block_size)) 
             {
                 attr &= 0xfff0000000000ffcUL;
                 if(level != 3)
@@ -256,14 +256,14 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
                 {
                     *pte = phys | (attr | 0x3UL);
                 }
-				addr += block_size;
-				phys += block_size;
-				size -= block_size;
-				break;
-			}
-			table = get_level_table(pte);
-		}
-	}
+                addr += block_size;
+                phys += block_size;
+                size -= block_size;
+                break;
+            }
+            table = get_level_table(pte);
+        }
+    }
 }
 
 void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr)
-- 
cgit v1.3.1


From b6031497b9c6cb0b0b6aec8dd465e92dea1ee430 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Wed, 26 Feb 2020 14:17:21 +0800
Subject: fix execption printf err

---
 libcpu/aarch64/cortex-a53/trap.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c
index 13ae6d1b9e..1c99970d8f 100644
--- a/libcpu/aarch64/cortex-a53/trap.c
+++ b/libcpu/aarch64/cortex-a53/trap.c
@@ -26,16 +26,16 @@ extern long list_thread(void);
 void rt_hw_show_register(struct rt_hw_exp_stack *regs)
 {
     rt_kprintf("Execption:\n");
-    rt_kprintf("r00:0x%16.16llx r01:0x%16.16llx r02:0x%16.16llx r03:0x%16.16llx\n", regs->x0, regs->x1, regs->x2, regs->x3);
-    rt_kprintf("r04:0x%16.16llx r05:0x%16.16llx r06:0x%16.16llx r07:0x%16.16llx\n", regs->x4, regs->x5, regs->x6, regs->x7);
-	rt_kprintf("r08:0x%16.16llx r09:0x%16.16llx r10:0x%16.16llx r11:0x%16.16llx\n", regs->x8, regs->x9, regs->x10, regs->x11);
-	rt_kprintf("r12:0x%16.16llx r13:0x%16.16llx r14:0x%16.16llx r15:0x%16.16llx\n", regs->x12, regs->x13, regs->x14, regs->x15);
-	rt_kprintf("r16:0x%16.16llx r17:0x%16.16llx r18:0x%16.16llx r19:0x%16.16llx\n", regs->x16, regs->x17, regs->x18, regs->x19);
-	rt_kprintf("r20:0x%16.16llx r21:0x%16.16llx r22:0x%16.16llx r23:0x%16.16llx\n", regs->x20, regs->x21, regs->x22, regs->x23);
-    rt_kprintf("r24:0x%16.16llx r25:0x%16.16llx r26:0x%16.16llx r27:0x%16.16llx\n", regs->x24, regs->x25, regs->x26, regs->x27);
-	rt_kprintf("r28:0x%16.16llx r29:0x%16.16llx r30:0x%16.16llx", regs->x28, regs->x29, regs->x30);
-	rt_kprintf("spsr:0x%16.16llx", regs->spsr);
-	rt_kprintf("return pc:0x%16.16llx", regs->pc);
+    rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
+    rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
+	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
+	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
 }
 
 /**
-- 
cgit v1.3.1


From 773f7cdf52f3ca8c778186699560bcfe7fffc9e3 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Wed, 26 Feb 2020 15:32:44 +0800
Subject: [bsp/raspi3-64]add core timer driver

---
 bsp/raspberry-pi/raspi3-64/.config          |  48 +++++-
 bsp/raspberry-pi/raspi3-64/driver/Kconfig   |  21 ++-
 bsp/raspberry-pi/raspi3-64/driver/bcm283x.h |  10 ++
 bsp/raspberry-pi/raspi3-64/driver/board.c   |  39 ++++-
 bsp/raspberry-pi/raspi3-64/rtconfig.h       | 217 +---------------------------
 libcpu/aarch64/cortex-a53/context_gcc.S     |  25 ++++
 libcpu/aarch64/cortex-a53/trap.c            |  49 ++-----
 7 files changed, 146 insertions(+), 263 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi3-64/.config b/bsp/raspberry-pi/raspi3-64/.config
index d51c923bf9..8ef205d539 100644
--- a/bsp/raspberry-pi/raspi3-64/.config
+++ b/bsp/raspberry-pi/raspi3-64/.config
@@ -67,12 +67,9 @@ CONFIG_RT_USING_DEVICE_OPS=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40002
+CONFIG_RT_VER_NUM=0x40003
 CONFIG_ARCH_CPU_64BIT=y
-CONFIG_ARCH_ARM=y
 # CONFIG_RT_USING_CPU_FFS is not set
-CONFIG_ARCH_ARM_CORTEX_AARCH64=y
-CONFIG_ARCH_ARM_CORTEX_A53=y
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
@@ -150,6 +147,8 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_WIFI is not set
 
 #
@@ -216,6 +215,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -269,6 +269,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_DLT645 is not set
 # CONFIG_PKG_USING_QXWZ is not set
 # CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
 
 #
 # security packages
@@ -306,6 +307,10 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
 
 #
 # system packages
@@ -324,6 +329,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LITTLEFS is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
 
 #
 # peripheral libraries and drivers
@@ -331,6 +337,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_SENSORS_DRIVERS is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -352,9 +359,9 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
 # CONFIG_PKG_USING_TOUCH_DRIVERS is not set
-# CONFIG_PKG_USING_LCD_DRIVERS is not set
 # CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
 
 #
 # miscellaneous packages
@@ -391,6 +398,36 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_MPLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+# CONFIG_PKG_USING_JS_PERSIMMON is not set
+# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RDBD_SRC is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_RTX is not set
+# CONFIG_RT_USING_TESTCASE is not set
+# CONFIG_PKG_USING_NGHTTP2 is not set
+# CONFIG_PKG_USING_AVS is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_STS is not set
+# CONFIG_PKG_USING_DLMS is not set
+# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
+# CONFIG_PKG_USING_ZBAR is not set
 CONFIG_BCM2836_SOC=y
 # CONFIG_BSP_SUPPORT_FPU is not set
 
@@ -405,6 +442,7 @@ CONFIG_BSP_USING_UART=y
 # CONFIG_RT_USING_UART0 is not set
 CONFIG_RT_USING_UART1=y
 CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_CORETIMER=y
 # CONFIG_BSP_USING_SYSTIMER is not set
 # CONFIG_BSP_USING_I2C is not set
 # CONFIG_BSP_USING_SPI is not set
diff --git a/bsp/raspberry-pi/raspi3-64/driver/Kconfig b/bsp/raspberry-pi/raspi3-64/driver/Kconfig
index e45d0a3ca2..963567f19f 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/Kconfig
+++ b/bsp/raspberry-pi/raspi3-64/driver/Kconfig
@@ -25,18 +25,23 @@ menu "Hardware Drivers Config"
             select RT_USING_PIN
             default y
 
+        config BSP_USING_CORETIMER
+            bool "Using core timer"
+            select RT_USING_CORETIMER
+            default y
+
         menuconfig BSP_USING_SYSTIMER
             bool "Enable SYSTIMER"
-            select RT_USING_SYSTIMER
+            select BSP_USING_SYSTIMER
             default n
 
-            if  RT_USING_SYSTIMER
-                config RT_USING_SYSTIMER1
-                    bool "Enable sys timer1"
-                    default n
-                config RT_USING_SYSTIMER3
-                    bool "Enable sys timer3"
-                    default n
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
         endif
 
         menuconfig BSP_USING_I2C
diff --git a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
index fc9ed1feab..c8b178ec85 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
@@ -201,6 +201,16 @@ enum i2c_reason_codes
 #define IRQ_DISABLE2        HWREG32(IRQ_BASE + 0x20)
 #define IRQ_DISABLE_BASIC   HWREG32(IRQ_BASE + 0x24)
 
+/*
+ *  Gtimer IRQ flag
+ */
+#define SYSTEM_TIMER_IRQ_0    (1 << 0)
+#define SYSTEM_TIMER_IRQ_1    (1 << 1)
+#define SYSTEM_TIMER_IRQ_2    (1 << 2)
+#define SYSTEM_TIMER_IRQ_3    (1 << 3)
+
+#define NON_SECURE_TIMER_IRQ    (1 << 1)
+
 /*
  *  System Timer
  */
diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c
index 00f27e0cc8..a12755657b 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/board.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.c
@@ -18,6 +18,20 @@
 #include "cp15.h"
 #include "mmu.h"
 
+#ifdef BSP_USING_CORETIMER
+static rt_uint64_t timerStep;
+#define CORE0_TIMER_IRQ_CTRL    HWREG32(0x40000040)
+
+int rt_hw_get_gtimer_frq(void);
+void rt_hw_set_gtimer_val(rt_uint64_t value);
+void rt_hw_gtimer_enable(void);
+
+void core0_timer_enable_interrupt_controller()
+{
+    CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
+}
+#endif
+
 #ifdef RT_USING_SMP
 extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
 
@@ -28,15 +42,29 @@ void ipi_handler(){
 
 void rt_hw_timer_isr(int vector, void *parameter)
 {
+#ifdef BSP_USING_CORETIMER
+    rt_hw_set_gtimer_val(timerStep);
+#else
     ARM_TIMER_IRQCLR = 0;
+#endif
     rt_tick_increase();
 }
 
-int rt_hw_timer_init()
+void rt_hw_timer_init(void)
 {
-    __DSB();
     rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
     rt_hw_interrupt_umask(IRQ_ARM_TIMER);
+#ifdef BSP_USING_CORETIMER
+    __ISB();
+    timerStep = rt_hw_get_gtimer_frq();
+    __DSB();
+    timerStep /= RT_TICK_PER_SECOND;
+    
+    rt_hw_gtimer_enable();
+    rt_hw_set_gtimer_val(timerStep);
+    core0_timer_enable_interrupt_controller();
+#else
+    __DSB();
     /* timer_clock = apb_clock/(pre_divider + 1) */
     ARM_TIMER_PREDIV = (250 - 1);
 
@@ -50,7 +78,7 @@ int rt_hw_timer_init()
 
     /* 23-bit counter, enable interrupt, enable timer */
     ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
-    return 0;
+#endif
 }
 
 void idle_wfi(void)
@@ -68,8 +96,9 @@ void rt_hw_board_init(void)
     armv8_map(0, 0, 0x800000, MEM_ATTR_MEMORY);
     armv8_map(0x3f00B000, 0x3f00B000, 0x1000, MEM_ATTR_IO);//timer
     armv8_map(0x3f200000, 0x3f200000, 0x16000, MEM_ATTR_IO);//uart
+    armv8_map(0x40000000, 0x40000000, 0x1000, MEM_ATTR_IO);//core timer
     mmu_enable();
-
+    
     /* initialize hardware interrupt */
     rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
     rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
@@ -80,7 +109,7 @@ void rt_hw_board_init(void)
     rt_hw_timer_init();
     rt_thread_idle_sethook(idle_wfi);
 
-#ifdef RT_USING_CONSOLE
+    #ifdef RT_USING_CONSOLE
     /* set console device */
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif /* RT_USING_CONSOLE */
diff --git a/bsp/raspberry-pi/raspi3-64/rtconfig.h b/bsp/raspberry-pi/raspi3-64/rtconfig.h
index 4a8d8c42bc..18210fc276 100644
--- a/bsp/raspberry-pi/raspi3-64/rtconfig.h
+++ b/bsp/raspberry-pi/raspi3-64/rtconfig.h
@@ -7,12 +7,8 @@
 /* RT-Thread Kernel */
 
 #define RT_NAME_MAX 8
-/* RT_USING_ARCH_DATA_TYPE is not set */
-/* RT_USING_SMP is not set */
 #define RT_ALIGN_SIZE 4
-/* RT_THREAD_PRIORITY_8 is not set */
 #define RT_THREAD_PRIORITY_32
-/* RT_THREAD_PRIORITY_256 is not set */
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
@@ -25,16 +21,6 @@
 #define RT_TIMER_THREAD_STACK_SIZE 2048
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
-/* RT_DEBUG_INIT_CONFIG is not set */
-/* RT_DEBUG_THREAD_CONFIG is not set */
-/* RT_DEBUG_SCHEDULER_CONFIG is not set */
-/* RT_DEBUG_IPC_CONFIG is not set */
-/* RT_DEBUG_TIMER_CONFIG is not set */
-/* RT_DEBUG_IRQ_CONFIG is not set */
-/* RT_DEBUG_MEM_CONFIG is not set */
-/* RT_DEBUG_SLAB_CONFIG is not set */
-/* RT_DEBUG_MEMHEAP_CONFIG is not set */
-/* RT_DEBUG_MODULE_CONFIG is not set */
 
 /* Inter-Thread communication */
 
@@ -43,16 +29,12 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
-/* RT_USING_SIGNALS is not set */
 
 /* Memory Management */
 
 #define RT_USING_MEMPOOL
 #define RT_USING_MEMHEAP
-/* RT_USING_NOHEAP is not set */
 #define RT_USING_SMALL_MEM
-/* RT_USING_SLAB is not set */
-/* RT_USING_MEMHEAP_AS_HEAP is not set */
 #define RT_USING_MEMTRACE
 #define RT_USING_HEAP
 
@@ -60,17 +42,11 @@
 
 #define RT_USING_DEVICE
 #define RT_USING_DEVICE_OPS
-/* RT_USING_INTERRUPT_INFO is not set */
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x40002
+#define RT_VER_NUM 0x40003
 #define ARCH_CPU_64BIT
-#define ARCH_ARM
-/* RT_USING_CPU_FFS is not set */
-#define ARCH_ARM_CORTEX_AARCH64
-#define ARCH_ARM_CORTEX_A53
-/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
 
 /* RT-Thread Components */
 
@@ -81,7 +57,6 @@
 
 /* C++ features */
 
-/* RT_USING_CPLUSPLUS is not set */
 
 /* Command shell */
 
@@ -91,11 +66,9 @@
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
-/* FINSH_ECHO_DISABLE_DEFAULT is not set */
 #define FINSH_THREAD_PRIORITY 20
 #define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-/* FINSH_USING_AUTH is not set */
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
 #define FINSH_USING_MSH_ONLY
@@ -108,275 +81,101 @@
 #define DFS_FILESYSTEMS_MAX 2
 #define DFS_FILESYSTEM_TYPES_MAX 2
 #define DFS_FD_MAX 16
-/* RT_USING_DFS_MNTTABLE is not set */
-/* RT_USING_DFS_ELMFAT is not set */
 #define RT_USING_DFS_DEVFS
-/* RT_USING_DFS_ROMFS is not set */
-/* RT_USING_DFS_RAMFS is not set */
-/* RT_USING_DFS_UFFS is not set */
-/* RT_USING_DFS_JFFS2 is not set */
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
-/* RT_USING_SYSTEM_WORKQUEUE is not set */
 #define RT_USING_SERIAL
-/* RT_SERIAL_USING_DMA is not set */
 #define RT_SERIAL_RB_BUFSZ 64
-/* RT_USING_CAN is not set */
-/* RT_USING_HWTIMER is not set */
-/* RT_USING_CPUTIME is not set */
-/* RT_USING_I2C is not set */
 #define RT_USING_PIN
-/* RT_USING_ADC is not set */
-/* RT_USING_PWM is not set */
-/* RT_USING_MTD_NOR is not set */
-/* RT_USING_MTD_NAND is not set */
-/* RT_USING_PM is not set */
-/* RT_USING_RTC is not set */
-/* RT_USING_SDIO is not set */
-/* RT_USING_SPI is not set */
-/* RT_USING_WDT is not set */
-/* RT_USING_AUDIO is not set */
-/* RT_USING_SENSOR is not set */
-/* RT_USING_TOUCH is not set */
-/* RT_USING_HWCRYPTO is not set */
-/* RT_USING_WIFI is not set */
 
 /* Using USB */
 
-/* RT_USING_USB_HOST is not set */
-/* RT_USING_USB_DEVICE is not set */
 
 /* POSIX layer and C standard library */
 
 #define RT_USING_LIBC
-/* RT_USING_PTHREADS is not set */
 #define RT_USING_POSIX
-/* RT_USING_POSIX_MMAP is not set */
-/* RT_USING_POSIX_TERMIOS is not set */
-/* RT_USING_POSIX_AIO is not set */
-/* RT_USING_MODULE is not set */
 
 /* Network */
 
 /* Socket abstraction layer */
 
-/* RT_USING_SAL is not set */
 
 /* Network interface device */
 
-/* RT_USING_NETDEV is not set */
 
 /* light weight TCP/IP stack */
 
-/* RT_USING_LWIP is not set */
 
 /* AT commands */
 
-/* RT_USING_AT is not set */
 
 /* VBUS(Virtual Software BUS) */
 
-/* RT_USING_VBUS is not set */
 
 /* Utilities */
 
-/* RT_USING_RYM is not set */
-/* RT_USING_ULOG is not set */
-/* RT_USING_UTEST is not set */
 
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
 
-/* PKG_USING_PAHOMQTT is not set */
-/* PKG_USING_WEBCLIENT is not set */
-/* PKG_USING_WEBNET is not set */
-/* PKG_USING_MONGOOSE is not set */
-/* PKG_USING_WEBTERMINAL is not set */
-/* PKG_USING_CJSON is not set */
-/* PKG_USING_JSMN is not set */
-/* PKG_USING_LIBMODBUS is not set */
-/* PKG_USING_FREEMODBUS is not set */
-/* PKG_USING_LJSON is not set */
-/* PKG_USING_EZXML is not set */
-/* PKG_USING_NANOPB is not set */
 
 /* Wi-Fi */
 
 /* Marvell WiFi */
 
-/* PKG_USING_WLANMARVELL is not set */
 
 /* Wiced WiFi */
 
-/* PKG_USING_WLAN_WICED is not set */
-/* PKG_USING_RW007 is not set */
-/* PKG_USING_COAP is not set */
-/* PKG_USING_NOPOLL is not set */
-/* PKG_USING_NETUTILS is not set */
-/* PKG_USING_PPP_DEVICE is not set */
-/* PKG_USING_AT_DEVICE is not set */
-/* PKG_USING_ATSRV_SOCKET is not set */
-/* PKG_USING_WIZNET is not set */
 
 /* IoT Cloud */
 
-/* PKG_USING_ONENET is not set */
-/* PKG_USING_GAGENT_CLOUD is not set */
-/* PKG_USING_ALI_IOTKIT is not set */
-/* PKG_USING_AZURE is not set */
-/* PKG_USING_TENCENT_IOTHUB is not set */
-/* PKG_USING_JIOT-C-SDK is not set */
-/* PKG_USING_NIMBLE is not set */
-/* PKG_USING_OTA_DOWNLOADER is not set */
-/* PKG_USING_IPMSG is not set */
-/* PKG_USING_LSSDP is not set */
-/* PKG_USING_AIRKISS_OPEN is not set */
-/* PKG_USING_LIBRWS is not set */
-/* PKG_USING_TCPSERVER is not set */
-/* PKG_USING_PROTOBUF_C is not set */
-/* PKG_USING_ONNX_PARSER is not set */
-/* PKG_USING_ONNX_BACKEND is not set */
-/* PKG_USING_DLT645 is not set */
-/* PKG_USING_QXWZ is not set */
-/* PKG_USING_SMTP_CLIENT is not set */
 
 /* security packages */
 
-/* PKG_USING_MBEDTLS is not set */
-/* PKG_USING_libsodium is not set */
-/* PKG_USING_TINYCRYPT is not set */
 
 /* language packages */
 
-/* PKG_USING_LUA is not set */
-/* PKG_USING_JERRYSCRIPT is not set */
-/* PKG_USING_MICROPYTHON is not set */
 
 /* multimedia packages */
 
-/* PKG_USING_OPENMV is not set */
-/* PKG_USING_MUPDF is not set */
-/* PKG_USING_STEMWIN is not set */
-/* PKG_USING_WAVPLAYER is not set */
-/* PKG_USING_TJPGD is not set */
 
 /* tools packages */
 
-/* PKG_USING_CMBACKTRACE is not set */
-/* PKG_USING_EASYFLASH is not set */
-/* PKG_USING_EASYLOGGER is not set */
-/* PKG_USING_SYSTEMVIEW is not set */
-/* PKG_USING_RDB is not set */
-/* PKG_USING_QRCODE is not set */
-/* PKG_USING_ULOG_EASYFLASH is not set */
-/* PKG_USING_ADBD is not set */
-/* PKG_USING_COREMARK is not set */
-/* PKG_USING_DHRYSTONE is not set */
 
 /* system packages */
 
-/* PKG_USING_GUIENGINE is not set */
-/* PKG_USING_CAIRO is not set */
-/* PKG_USING_PIXMAN is not set */
-/* PKG_USING_LWEXT4 is not set */
-/* PKG_USING_PARTITION is not set */
-/* PKG_USING_FAL is not set */
-/* PKG_USING_SQLITE is not set */
-/* PKG_USING_RTI is not set */
-/* PKG_USING_LITTLEVGL2RTT is not set */
-/* PKG_USING_CMSIS is not set */
-/* PKG_USING_DFS_YAFFS is not set */
-/* PKG_USING_LITTLEFS is not set */
-/* PKG_USING_THREAD_POOL is not set */
-/* PKG_USING_ROBOTS is not set */
 
 /* peripheral libraries and drivers */
 
-/* PKG_USING_SENSORS_DRIVERS is not set */
-/* PKG_USING_REALTEK_AMEBA is not set */
-/* PKG_USING_SHT2X is not set */
-/* PKG_USING_STM32_SDIO is not set */
-/* PKG_USING_ICM20608 is not set */
-/* PKG_USING_U8G2 is not set */
-/* PKG_USING_BUTTON is not set */
-/* PKG_USING_PCF8574 is not set */
-/* PKG_USING_SX12XX is not set */
-/* PKG_USING_SIGNAL_LED is not set */
-/* PKG_USING_LEDBLINK is not set */
-/* PKG_USING_WM_LIBRARIES is not set */
-/* PKG_USING_KENDRYTE_SDK is not set */
-/* PKG_USING_INFRARED is not set */
-/* PKG_USING_ROSSERIAL is not set */
-/* PKG_USING_AGILE_BUTTON is not set */
-/* PKG_USING_AGILE_LED is not set */
-/* PKG_USING_AT24CXX is not set */
-/* PKG_USING_MOTIONDRIVER2RTT is not set */
-/* PKG_USING_AD7746 is not set */
-/* PKG_USING_PCA9685 is not set */
-/* PKG_USING_I2C_TOOLS is not set */
-/* PKG_USING_NRF24L01 is not set */
-/* PKG_USING_TOUCH_DRIVERS is not set */
-/* PKG_USING_LCD_DRIVERS is not set */
-/* PKG_USING_MAX17048 is not set */
-/* PKG_USING_RPLIDAR is not set */
 
 /* miscellaneous packages */
 
-/* PKG_USING_LIBCSV is not set */
-/* PKG_USING_OPTPARSE is not set */
-/* PKG_USING_FASTLZ is not set */
-/* PKG_USING_MINILZO is not set */
-/* PKG_USING_QUICKLZ is not set */
-/* PKG_USING_MULTIBUTTON is not set */
-/* PKG_USING_FLEXIBLE_BUTTON is not set */
-/* PKG_USING_CANFESTIVAL is not set */
-/* PKG_USING_ZLIB is not set */
-/* PKG_USING_DSTR is not set */
-/* PKG_USING_TINYFRAME is not set */
-/* PKG_USING_KENDRYTE_DEMO is not set */
-/* PKG_USING_DIGITALCTRL is not set */
-/* PKG_USING_UPACKER is not set */
-/* PKG_USING_UPARAM is not set */
 
 /* samples: kernel and components samples */
 
-/* PKG_USING_KERNEL_SAMPLES is not set */
-/* PKG_USING_FILESYSTEM_SAMPLES is not set */
-/* PKG_USING_NETWORK_SAMPLES is not set */
-/* PKG_USING_PERIPHERAL_SAMPLES is not set */
-/* PKG_USING_HELLO is not set */
-/* PKG_USING_VI is not set */
-/* PKG_USING_NNOM is not set */
-/* PKG_USING_LIBANN is not set */
-/* PKG_USING_ELAPACK is not set */
-/* PKG_USING_ARMv7M_DWT is not set */
-/* PKG_USING_VT100 is not set */
-/* PKG_USING_ULAPACK is not set */
-/* PKG_USING_UKAL is not set */
+
+/* Privated Packages of RealThread */
+
+
+/* Network Utilities */
+
 #define BCM2836_SOC
-/* BSP_SUPPORT_FPU is not set */
 
 /* Hardware Drivers Config */
 
 /* BCM Peripheral Drivers */
 
 #define BSP_USING_UART
-/* RT_USING_UART0 is not set */
 #define RT_USING_UART1
 #define BSP_USING_PIN
-/* BSP_USING_SYSTIMER is not set */
-/* BSP_USING_I2C is not set */
-/* BSP_USING_SPI is not set */
-/* BSP_USING_WDT is not set */
-/* BSP_USING_RTC is not set */
-/* BSP_USING_SDIO is not set */
+#define BSP_USING_CORETIMER
 
 /* Board Peripheral Drivers */
 
-/* BSP_USING_HDMI is not set */
 
 #endif
diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S
index f58ea1b15d..f9052d2201 100644
--- a/libcpu/aarch64/cortex-a53/context_gcc.S
+++ b/libcpu/aarch64/cortex-a53/context_gcc.S
@@ -8,6 +8,31 @@
  * 2018-10-06     ZhaoXiaowei    the first version
  */
 
+  /*
+ *enable gtimer
+ */
+.globl rt_hw_gtimer_enable
+rt_hw_gtimer_enable:
+    MOV X0,#1
+	MSR CNTP_CTL_EL0,X0
+	RET
+
+/*
+ *set gtimer CNTP_TVAL_EL0 value
+ */
+.globl rt_hw_set_gtimer_val
+rt_hw_set_gtimer_val:
+	MSR CNTP_TVAL_EL0,X0
+	RET
+
+/*
+ *get gtimer frq value
+ */
+.globl rt_hw_get_gtimer_frq
+rt_hw_get_gtimer_frq:
+	MRS X0,CNTFRQ_EL0
+	RET
+
 .macro SAVE_CONTEXT
 
     /* Switch to use the EL0 stack pointer. */
diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c
index 1c99970d8f..41d4d620f6 100644
--- a/libcpu/aarch64/cortex-a53/trap.c
+++ b/libcpu/aarch64/cortex-a53/trap.c
@@ -56,7 +56,8 @@ void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
     rt_hw_cpu_shutdown();
 }
 
-#define GIC_ACK_INTID_MASK              0x000003ff
+#define GIC_ACK_INTID_MASK              (0x000003ff)
+#define CORE0_IRQ_SOURCE	            (0x40000060)
 
 void rt_hw_trap_irq(void)
 {
@@ -66,43 +67,19 @@ void rt_hw_trap_irq(void)
     extern struct rt_irq_desc isr_table[];
     uint32_t value = 0;
     value = IRQ_PEND_BASIC & 0x3ff;
-#ifdef RT_USING_SMP
-    uint32_t mailbox_data;
-    uint32_t cpu_id = rt_hw_cpu_id();
-    uint32_t int_source = CORE_IRQSOURCE(cpu_id);
-    mailbox_data = IPI_MAILBOX_CLEAR(cpu_id);
-    if (int_source & 0x0f)
+#ifdef BSP_USING_CORETIMER
+    uint32_t int_source = HWREG32(CORE0_IRQ_SOURCE)  & 0x3ff;
+    if (int_source & 0x02)
     {
-        if (int_source & 0x08){
-            isr_func = isr_table[IRQ_ARM_TIMER].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-            isr_table[IRQ_ARM_TIMER].counter++;
-#endif
-            if (isr_func)
-            {
-                param = isr_table[IRQ_ARM_TIMER].param;
-                isr_func(IRQ_ARM_TIMER, param);
-            }
-        }
-    }
-    if (int_source & 0xf0)
-    {
-        /*it's a ipi interrupt*/
-        if (mailbox_data & 0x1){
-            /* clear mailbox */
-            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;    
-            isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-            isr_table[IRQ_ARM_MAILBOX].counter++;
-#endif
-            if (isr_func)
-            {
-                param = isr_table[IRQ_ARM_MAILBOX].param;
-                isr_func(IRQ_ARM_MAILBOX, param);
-            }
+        isr_func = isr_table[IRQ_ARM_TIMER].handler;
+        #ifdef RT_USING_INTERRUPT_INFO
+                    isr_table[IRQ_ARM_TIMER].counter++;
+        #endif
+        if (isr_func)
+        {
+            param = isr_table[IRQ_ARM_TIMER].param;
+            isr_func(IRQ_ARM_TIMER, param);
         }
-        else 
-            CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
     }
 #endif
     /* local interrupt*/
-- 
cgit v1.3.1


From 53211b3c6eeb868d975d33a02a49b8babc21f65d Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Wed, 26 Feb 2020 15:43:23 +0800
Subject: replace space to tab

---
 libcpu/aarch64/cortex-a53/context_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S
index f9052d2201..d5c241036e 100644
--- a/libcpu/aarch64/cortex-a53/context_gcc.S
+++ b/libcpu/aarch64/cortex-a53/context_gcc.S
@@ -13,7 +13,7 @@
  */
 .globl rt_hw_gtimer_enable
 rt_hw_gtimer_enable:
-    MOV X0,#1
+	MOV X0,#1
 	MSR CNTP_CTL_EL0,X0
 	RET
 
-- 
cgit v1.3.1


From ff10eaed9c4df15a4ce89ef94fe0a22e65411cb0 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Fri, 28 Feb 2020 17:49:50 +0800
Subject: [bsp/raspi3-64]fix gpio drvier

---
 bsp/raspberry-pi/raspi3-64/.config            |   6 +-
 bsp/raspberry-pi/raspi3-64/driver/SConscript  |   1 -
 bsp/raspberry-pi/raspi3-64/driver/bcm283x.c   | 575 -----------------------
 bsp/raspberry-pi/raspi3-64/driver/bcm283x.h   | 651 --------------------------
 bsp/raspberry-pi/raspi3-64/driver/board.c     |   1 +
 bsp/raspberry-pi/raspi3-64/driver/board.h     |   4 -
 bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c  | 474 +++++++------------
 bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h  |  13 +-
 bsp/raspberry-pi/raspi3-64/driver/drv_timer.c |  84 ++--
 bsp/raspberry-pi/raspi3-64/driver/drv_uart.c  |  26 +-
 bsp/raspberry-pi/raspi3-64/driver/raspi.h     | 467 ++++++++++++++++--
 bsp/raspberry-pi/raspi3-64/rtconfig.h         |   3 +
 libcpu/aarch64/cortex-a53/cp15.h              |   1 -
 libcpu/aarch64/cortex-a53/interrupt.c         |   4 +-
 libcpu/aarch64/cortex-a53/interrupt.h         |   2 +
 15 files changed, 660 insertions(+), 1652 deletions(-)
 delete mode 100644 bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
 delete mode 100644 bsp/raspberry-pi/raspi3-64/driver/bcm283x.h

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi3-64/.config b/bsp/raspberry-pi/raspi3-64/.config
index 28e075c64a..1587f978ca 100644
--- a/bsp/raspberry-pi/raspi3-64/.config
+++ b/bsp/raspberry-pi/raspi3-64/.config
@@ -146,7 +146,7 @@ CONFIG_RT_USING_SERIAL=y
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
+CONFIG_RT_USING_HWTIMER=y
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 CONFIG_RT_USING_PIN=y
@@ -465,7 +465,9 @@ CONFIG_BSP_USING_UART=y
 CONFIG_RT_USING_UART1=y
 CONFIG_BSP_USING_PIN=y
 CONFIG_BSP_USING_CORETIMER=y
-# CONFIG_BSP_USING_SYSTIMER is not set
+CONFIG_BSP_USING_SYSTIMER=y
+CONFIG_RT_USING_SYSTIMER1=y
+# CONFIG_RT_USING_SYSTIMER3 is not set
 # CONFIG_BSP_USING_I2C is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_WDT is not set
diff --git a/bsp/raspberry-pi/raspi3-64/driver/SConscript b/bsp/raspberry-pi/raspi3-64/driver/SConscript
index b11a0ba371..484e20faff 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/SConscript
+++ b/bsp/raspberry-pi/raspi3-64/driver/SConscript
@@ -5,7 +5,6 @@ from building import *
 cwd     = GetCurrentDir()
 src     = Split('''
 board.c
-bcm283x.c
 drv_uart.c
 ''')
 CPPPATH = [cwd]
diff --git a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
deleted file mode 100644
index ea92c33a0f..0000000000
--- a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2019-07-29     zdzn           first version
- */
-
-#include "bcm283x.h"
-
-rt_uint32_t bcm283x_peri_read(volatile rt_ubase_t addr)
-{
-    rt_uint32_t ret;
-    __sync_synchronize();
-    ret = HWREG32(addr);
-    __sync_synchronize();
-    return ret;
-}
-
-rt_uint32_t bcm283x_peri_read_nb(volatile rt_ubase_t addr)
-{
-    return HWREG32(addr);
-}
-
-void bcm283x_peri_write(volatile rt_ubase_t addr, rt_uint32_t value)
-{
-    __sync_synchronize();
-    HWREG32(addr) = value;
-    __sync_synchronize();
-}
-
-void bcm283x_peri_write_nb(volatile rt_ubase_t addr, rt_uint32_t value)
-{
-    HWREG32(addr) = value;
-}
-
-void bcm283x_peri_set_bits(volatile rt_ubase_t addr, rt_uint32_t value, rt_uint32_t mask)
-{
-    rt_uint32_t v = bcm283x_peri_read(addr);
-    v = (v & ~mask) | (value & mask);
-    bcm283x_peri_write(addr, v);
-}
-
-void bcm283x_gpio_fsel(rt_uint8_t pin, rt_uint8_t mode)
-{
-    volatile rt_ubase_t addr = (BCM283X_GPIO_BASE + BCM283X_GPIO_GPFSEL0 + (pin / 10) * 4);
-    rt_uint8_t   shift = (pin % 10) * 3;
-    rt_uint32_t  mask = BCM283X_GPIO_FSEL_MASK << shift;
-    rt_uint32_t  value = mode << shift;
-
-    bcm283x_peri_set_bits(addr, value, mask);
-}
-
-void bcm283x_gpio_set(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPSET0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    bcm283x_peri_write(addr, 1 << shift);
-}
-
-void bcm283x_gpio_clr(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPCLR0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    bcm283x_peri_write(addr, 1 << shift);
-}
-
-rt_uint8_t bcm283x_gpio_lev(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM2835_GPIO_GPLEV0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = bcm283x_peri_read(addr);
-    return (value & (1 << shift)) ? HIGH : LOW;
-}
-
-rt_uint8_t bcm283x_gpio_eds(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = bcm283x_peri_read(addr);
-    return (value & (1 << shift)) ? HIGH : LOW;
-}
-
-/* Write a 1 to clear the bit in EDS */
-void bcm283x_gpio_set_eds(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_write(addr, value);
-}
-
-/* Rising edge detect enable */
-void bcm283x_gpio_ren(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPREN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, value, value);
-}
-
-void bcm283x_gpio_clr_ren(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPREN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, 0, value);
-}
-
-/* Falling edge detect enable */
-void bcm283x_gpio_fen(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPFEN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, value, value);
-}
-void bcm283x_gpio_clr_fen(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPFEN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, 0, value);
-}
-
-/* High detect enable */
-void bcm283x_gpio_hen(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, value, value);
-}
-
-void bcm283x_gpio_clr_hen(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, 0, value);
-}
-
-/* Low detect enable */
-void bcm283x_gpio_len(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPLEN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, value, value);
-}
-
-void bcm283x_gpio_clr_len(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPLEN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, 0, value);
-}
-
-/* Async rising edge detect enable */
-void bcm283x_gpio_aren(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAREN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, value, value);
-}
-void bcm283x_gpio_clr_aren(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAREN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, 0, value);
-}
-
-/* Async falling edge detect enable */
-void bcm283x_gpio_afen(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAFEN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, value, value);
-}
-void bcm283x_gpio_clr_afen(rt_uint8_t pin)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAFEN0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    rt_uint32_t value = 1 << shift;
-    bcm283x_peri_set_bits(addr, 0, value);
-}
-
-/* Set pullup/down */
-void bcm283x_gpio_pud(rt_uint8_t pud)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPPUD;
-    bcm283x_peri_write(addr, pud);
-}
-
-/* Pullup/down clock
-// Clocks the value of pud into the GPIO pin
-*/
-void bcm283x_gpio_pudclk(rt_uint8_t pin, rt_uint8_t on)
-{
-    volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPPUDCLK0 + (pin / 32) * 4;
-    rt_uint8_t shift = pin % 32;
-    bcm283x_peri_write(addr, (on? 1 : 0) << shift);
-}
-
-void bcm283x_gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud)
-{
-    bcm283x_gpio_pud(pud);
-    bcm283x_clo_delayMicros(10);
-
-    bcm283x_gpio_pudclk(pin, 1);
-    bcm283x_clo_delayMicros(10);
-
-    bcm283x_gpio_pud(BCM283X_GPIO_PUD_OFF);
-    bcm283x_gpio_pudclk(pin, 0);
-}
-
-
-void bcm283x_gpio_write(rt_uint8_t pin, rt_uint8_t val)
-{
-    if (val)
-        bcm283x_gpio_set(pin);
-    else
-        bcm283x_gpio_clr(pin);
-}
-
-rt_uint64_t bcm283x_st_read(void)
-{
-    volatile rt_ubase_t addr;
-    rt_uint32_t hi, lo;
-    rt_uint64_t st;
-
-    addr = BCM283X_ST_BASE + BCM283X_ST_CHI;
-    hi = bcm283x_peri_read(addr);
-
-    addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
-    lo = bcm283x_peri_read(addr);
-
-    addr = BCM283X_ST_BASE + BCM283X_ST_CHI;
-    st = bcm283x_peri_read(addr);
-
-    /* Test for overflow */
-    if (st == hi)
-    {
-        rt_kprintf(">> 1crash???\n");
-        st <<= 32;
-        st += lo;
-        rt_kprintf(">> 2crash!!!\n");
-    }
-    else
-    {
-        st <<= 32;
-        addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
-        st += bcm283x_peri_read(addr);
-    }
-    return st;
-}
-
-/* microseconds */
-void bcm283x_delayMicroseconds(rt_uint64_t micros)
-{
-    rt_uint64_t start;
-
-    start =  bcm283x_st_read();
-    rt_kprintf("bcm283x_st_read result: %d\n", start);
-
-    /* Not allowed to access timer registers (result is not as precise)*/
-    if (start==0)
-        return;
-
-    bcm283x_st_delay(start, micros);
-}
-
-void bcm283x_clo_delayMicros(rt_uint32_t micros)
-{
-    volatile rt_uint32_t addr;
-    rt_uint32_t compare;
-
-    addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
-    compare = bcm283x_peri_read(addr) + micros;
-    while(bcm283x_peri_read(addr) < compare);
-}
-
-void bcm283x_st_delay(rt_uint64_t offset_micros, rt_uint64_t micros)
-{
-    rt_uint64_t compare = offset_micros + micros;
-    while(bcm283x_st_read() < compare);
-}
-
-
-/* Read an number of bytes from I2C */
-rt_uint8_t bcm283x_i2c_read(rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len)
-{
-    volatile rt_uint32_t  dlen    = base + BCM283X_BSC_DLEN;
-    volatile rt_uint32_t  fifo    = base + BCM283X_BSC_FIFO;
-    volatile rt_uint32_t  status  = base + BCM283X_BSC_S;
-    volatile rt_uint32_t  control = base + BCM283X_BSC_C;
-
-    rt_uint32_t remaining = len;
-    rt_uint32_t i = 0;
-    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
-
-    /* Clear FIFO */
-    bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
-    /* Clear Status */
-    bcm283x_peri_write_nb(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
-    /* Set Data Length */
-    bcm283x_peri_write_nb(dlen, len);
-    /* Start read */
-    bcm283x_peri_write_nb(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST | BCM283X_BSC_C_READ);
-
-    /* wait for transfer to complete */
-    while (!(bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE))
-    {
-        /* we must empty the FIFO as it is populated and not use any delay */
-        while (remaining && bcm283x_peri_read_nb(status) & BCM283X_BSC_S_RXD)
-        {
-            /* Read from FIFO, no barrier */
-            buf[i] = bcm283x_peri_read_nb(fifo);
-            i++;
-            remaining--;
-        }
-    }
-
-    /* transfer has finished - grab any remaining stuff in FIFO */
-    while (remaining && (bcm283x_peri_read_nb(status) & BCM283X_BSC_S_RXD))
-    {
-        /* Read from FIFO, no barrier */
-        buf[i] = bcm283x_peri_read_nb(fifo);
-        i++;
-        remaining--;
-    }
-
-    /* Received a NACK */
-    if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_NACK;
-    }
-
-    /* Received Clock Stretch Timeout */
-    else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_CLKT;
-    }
-
-    /* Not all data is received */
-    else if (remaining)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_DATA;
-    }
-
-    bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
-
-    return reason;
-}
-
-int bcm283x_i2c_begin(int no)
-{
-    if (0 == no)
-    {
-        bcm283x_gpio_fsel(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_ALT0); /* SDA */
-        bcm283x_gpio_fsel(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_ALT0); /* SCL */
-    }
-    else
-    {
-        bcm283x_gpio_fsel(BCM_GPIO_PIN_2, BCM283X_GPIO_FSEL_ALT0); /* SDA */
-        bcm283x_gpio_fsel(BCM_GPIO_PIN_3, BCM283X_GPIO_FSEL_ALT0); /* SCL */
-    }
-    return 0;
-}
-
-void bcm283x_i2c_end(int no)
-{
-    if (0 == no)
-    {
-        bcm283x_gpio_fsel(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_INPT); /* SDA */
-        bcm283x_gpio_fsel(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_INPT); /* SCL */
-    }
-    else
-    {
-        bcm283x_gpio_fsel(BCM_GPIO_PIN_2, BCM283X_GPIO_FSEL_INPT); /* SDA */
-        bcm283x_gpio_fsel(BCM_GPIO_PIN_3, BCM283X_GPIO_FSEL_INPT); /* SCL */
-    }
-}
-
-void bcm283x_i2c_setSlaveAddress(int no, rt_uint8_t saddr)
-{
-    volatile rt_uint32_t addr;
-    if (0 == no)
-        addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_A;
-    else
-        addr = PER_BASE + BCM283X_BSC1_BASE + BCM283X_BSC_A;
-
-    bcm283x_peri_write(addr, saddr);
-}
-
-void bcm283x_i2c_setClockDivider(int no, rt_uint16_t divider)
-{
-    volatile rt_uint32_t addr;
-    if (0 == no)
-        addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DIV;
-    else
-        addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DIV;
-    bcm283x_peri_write(addr, divider);
-}
-
-void bcm283x_i2c_set_baudrate(int no, rt_uint32_t baudrate)
-{
-    rt_uint32_t divider;
-    divider = (BCM283X_CORE_CLK_HZ / baudrate) & 0xFFFE;
-    bcm283x_i2c_setClockDivider(no, (rt_uint16_t)divider);
-}
-
-/* Writes an number of bytes to I2C */
-rt_uint8_t bcm283x_i2c_write(rt_uint32_t base, const rt_uint8_t * buf, rt_uint32_t len)
-{
-    volatile rt_uint32_t dlen    = base + BCM283X_BSC_DLEN;
-    volatile rt_uint32_t fifo    = base + BCM283X_BSC_FIFO;
-    volatile rt_uint32_t status  = base + BCM283X_BSC_S;
-    volatile rt_uint32_t control = base + BCM283X_BSC_C;
-
-    rt_uint32_t remaining = len;
-    rt_uint32_t i = 0;
-    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
-
-    /* Clear FIFO */
-    bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
-    /* Clear Status */
-    bcm283x_peri_write(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
-    /* Set Data Length */
-    bcm283x_peri_write(dlen, len);
-    /* pre populate FIFO with max buffer */
-    while(remaining && (i < BCM283X_BSC_FIFO_SIZE))
-    {
-        bcm283x_peri_write_nb(fifo, buf[i]);
-        i++;
-        remaining--;
-    }
-
-    /* Enable device and start transfer */
-    bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST);
-
-    /* Transfer is over when BCM2835_BSC_S_DONE */
-    while(!(bcm283x_peri_read(status) & BCM283X_BSC_S_DONE))
-    {
-        while (remaining && (bcm283x_peri_read(status) & BCM283X_BSC_S_TXD))
-        {
-        /* Write to FIFO */
-            bcm283x_peri_write(fifo, buf[i]);
-            i++;
-            remaining--;
-        }
-    }
-
-    /* Received a NACK */
-    if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_NACK;
-    }
-
-    /* Received Clock Stretch Timeout */
-    else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_CLKT;
-    }
-
-    /* Not all data is sent */
-    else if (remaining)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_DATA;
-    }
-
-    bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
-
-    return reason;
-}
-
-rt_uint8_t bcm283x_i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len)
-{
-    volatile rt_uint32_t dlen    = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DLEN;
-    volatile rt_uint32_t fifo    = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_FIFO;
-    volatile rt_uint32_t status  = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_S;
-    volatile rt_uint32_t control = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_C;
-
-    rt_uint32_t remaining = cmds_len;
-    rt_uint32_t i = 0;
-    rt_uint8_t reason = BCM283X_I2C_REASON_OK;
-
-    /* Clear FIFO */
-    bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
-
-    /* Clear Status */
-    bcm283x_peri_write(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
-
-    /* Set Data Length */
-    bcm283x_peri_write(dlen, cmds_len);
-
-    /* pre populate FIFO with max buffer */
-    while(remaining && (i < BCM283X_BSC_FIFO_SIZE))
-    {
-        bcm283x_peri_write_nb(fifo, cmds[i]);
-        i++;
-        remaining--;
-    }
-
-    /* Enable device and start transfer */
-    bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST);
-
-    /* poll for transfer has started (way to do repeated start, from BCM2835 datasheet) */
-    while (!(bcm283x_peri_read(status) & BCM283X_BSC_S_TA))
-    {
-        /* Linux may cause us to miss entire transfer stage */
-        if (bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE)
-            break;
-    }
-
-    remaining = buf_len;
-    i = 0;
-
-    /* Send a repeated start with read bit set in address */
-    bcm283x_peri_write(dlen, buf_len);
-    bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST  | BCM283X_BSC_C_READ);
-
-    /* Wait for write to complete and first byte back. */
-    bcm283x_clo_delayMicros(100);
-
-    /* wait for transfer to complete */
-    while (!(bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE))
-    {
-        /* we must empty the FIFO as it is populated and not use any delay */
-        while (remaining && bcm283x_peri_read(status) & BCM283X_BSC_S_RXD)
-        {
-            /* Read from FIFO, no barrier */
-            buf[i] = bcm283x_peri_read_nb(fifo);
-            i++;
-            remaining--;
-        }
-    }
-
-    /* transfer has finished - grab any remaining stuff in FIFO */
-    while (remaining && (bcm283x_peri_read(status) & BCM283X_BSC_S_RXD))
-    {
-        /* Read from FIFO */
-        buf[i] = bcm283x_peri_read(fifo);
-        i++;
-        remaining--;
-    }
-
-    /* Received a NACK */
-    if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_NACK;
-    }
-
-    /* Received Clock Stretch Timeout */
-    else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_CLKT;
-    }
-
-    /* Not all data is sent */
-    else if (remaining)
-    {
-        reason = BCM283X_I2C_REASON_ERROR_DATA;
-    }
-
-    bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
-
-    return reason;
-}
diff --git a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
deleted file mode 100644
index c8b178ec85..0000000000
--- a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h
+++ /dev/null
@@ -1,651 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2019-07-15     RT-Thread    the first version
- * 2019-07-29     zdzn         add macro definition
- */
-
-#ifndef __BCM283X_H__
-#define __BCM283X_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#define PER_BASE    		(0x3F000000)
-#define PER_BASE_40000000 	(0x40000000)
-
-
-#define HIGH 0x1
-#define LOW  0x0
-
-#define BCM283X_CORE_CLK_HZ		250000000	/* 50 MHz */
-
-/*! Offsets for the bases of various peripherals within the peripherals block
- *   Base Address of the System Timer registers
- */
-/*! Base Address of the Pads registers */
-#define BCM283X_GPIO_PADS               0x100000
-/*! Base Address of the Clock/timer registers */
-#define BCM283X_CLOCK_BASE              0x101000
-/*! Base Address of the GPIO registers */
-//#define BCM283X_GPIO_BASE               0x200000
-/*! Base Address of the SPI0 registers */
-#define BCM283X_SPI0_BASE               0x204000
-/*! Base Address of the PWM registers */
-#define BCM283X_GPIO_PWM                0x20C000
-/*! Base Address of the AUX registers */
-#define BCM283X_AUX_BASE				0x215000
-/*! Base Address of the AUX_SPI1 registers */
-#define BCM283X_SPI1_BASE				0x215080
-/*! Base Address of the AUX_SPI2 registers */
-#define BCM283X_SPI2_BASE				0x2150C0
-
-/*! Base Address of the BSC0 registers */
-#define BCM283X_BSC0_BASE 				0x205000    //for i2c0
-/*! Base Address of the BSC1 registers */
-#define BCM283X_BSC1_BASE				0x804000    //for i2c1
-/*! Base Address of the BSC1 registers */
-#define BCM283X_BSC2_BASE				0x805000    //for hdmi i2c not use 
-
-/*
- *  GPIO
- */
-#define GPIO_BASE       (PER_BASE + 0x200000)
-#define GPIO_GPFSEL0    HWREG32(GPIO_BASE + 0x0000)  /* GPIO Function Select 0 32bit R/W */
-#define GPIO_GPFSEL1    HWREG32(GPIO_BASE + 0x0004)  /* GPIO Function Select 1 32bit R/W */
-#define GPIO_GPFSEL2    HWREG32(GPIO_BASE + 0x0008)  /* GPIO Function Select 2 32bit R/W */
-#define GPIO_GPFSEL4    HWREG32(GPIO_BASE + 0x0010)  /* GPIO Function Select 4 32bit R/W */
-#define GPIO_GPFSEL5    HWREG32(GPIO_BASE + 0x0014)  /* GPIO Function Select 5 32bit R/W */
-#define GPIO_GPSET0     HWREG32(GPIO_BASE + 0x001C)
-#define GPIO_GPSET1     HWREG32(GPIO_BASE + 0x0020)
-#define GPIO_GPCLR0     HWREG32(GPIO_BASE + 0x0028)
-#define GPIO_GPCLR1     HWREG32(GPIO_BASE + 0x002C)
-#define GPIO_GPEDS0     HWREG32(GPIO_BASE + 0x0040)  /* GPIO Pin Event Detect Status */
-#define GPIO_GPEDS1     HWREG32(GPIO_BASE + 0x0044)
-#define GPIO_GPREN0     HWREG32(GPIO_BASE + 0x004c)  /* GPIO Pin Rising Edge Detect Enable */
-#define GPIO_GPREN1     HWREG32(GPIO_BASE + 0x0050)
-#define GPIO_GPFEN0     HWREG32(GPIO_BASE + 0x0058) /* GPIO Pin Falling Edge Detect Enable */
-#define GPIO_GPFEN1     HWREG32(GPIO_BASE + 0x005C) 
-#define GPIO_GPHEN0     HWREG32(GPIO_BASE + 0x0064) /* GPIO Pin High Detect Enable  */
-#define GPIO_GPHEN1     HWREG32(GPIO_BASE + 0x0068)
-#define GPIO_GPLEN0     HWREG32(GPIO_BASE + 0x0070) /* GPIO Pin Low Detect Enable 0 */
-#define GPIO_GPLEN1     HWREG32(GPIO_BASE + 0x0074)
-#define GPIO_GPAREN0    HWREG32(GPIO_BASE + 0x007C) /* GPIO Pin Async. Rising Edge Detect */
-#define GPIO_GPAREN1    HWREG32(GPIO_BASE + 0x0080)
-#define GPIO_GPAFEN0    HWREG32(GPIO_BASE + 0x0088) /* GPIO Pin Async. Falling Edge Detect */
-#define GPIO_GPAFEN1    HWREG32(GPIO_BASE + 0x008C)
-#define GPIO_GPPUD      HWREG32(GPIO_BASE + 0x0094)  /* GPIO Pin Pull-up/down Enable */
-#define GPIO_GPPUDCLK0  HWREG32(GPIO_BASE + 0x0098)  /* GPIO Pin Pull-up/down Enable Clock 0 */
-#define GPIO_GPPUDCLK1  HWREG32(GPIO_BASE + 0x009C)  /* GPIO Pin Pull-up/down Enable Clock 1 */
-
-#define BCM283X_GPIO_BASE       (PER_BASE + 0x200000)
-#define BCM283X_GPIO_GPFSEL0    (0x0000)  /* GPIO Function Select 0 32bit R/W */
-#define BCM283X_GPIO_GPFSEL1    (0x0004)  /* GPIO Function Select 1 32bit R/W */
-#define BCM283X_GPIO_GPFSEL2    (0x0008)  /* GPIO Function Select 2 32bit R/W */
-#define BCM283X_GPIO_GPFSEL4    (0x0010)  /* GPIO Function Select 4 32bit R/W */
-#define BCM283X_GPIO_GPFSEL5    (0x0014)  /* GPIO Function Select 5 32bit R/W */
-#define BCM283X_GPIO_GPSET0     (0x001C)
-#define BCM283X_GPIO_GPSET1     (0x0020)
-#define BCM283X_GPIO_GPCLR0     (0x0028)
-#define BCM283X_GPIO_GPCLR1     (0x002C)
-#define BCM2835_GPIO_GPLEV0     (0x0034)  /*!< GPIO Pin Level 0 */
-#define BCM2835_GPIO_GPLEV1     (0x0038)  /*!< GPIO Pin Level 1 */
-#define BCM283X_GPIO_GPEDS0     (0x0040)  /* GPIO Pin Event Detect Status */
-#define BCM283X_GPIO_GPEDS1     (0x0044)
-#define BCM283X_GPIO_GPREN0     (0x004c)  /* GPIO Pin Rising Edge Detect Enable */
-#define BCM283X_GPIO_GPREN1     (0x0050)
-#define BCM283X_GPIO_GPFEN0     (0x0058) /* GPIO Pin Falling Edge Detect Enable */
-#define BCM283X_GPIO_GPFEN1     (0x005C)
-#define BCM283X_GPIO_GPHEN0     (0x0064) /* GPIO Pin High Detect Enable  */
-#define BCM283X_GPIO_GPHEN1     (0x0068)
-#define BCM283X_GPIO_GPLEN0     (0x0070) /* GPIO Pin Low Detect Enable 0 */
-#define BCM283X_GPIO_GPLEN1     (0x0074)
-#define BCM283X_GPIO_GPAREN0    (0x007C) /* GPIO Pin Async. Rising Edge Detect */
-#define BCM283X_GPIO_GPAREN1    (0x0080)
-#define BCM283X_GPIO_GPAFEN0    (0x0088) /* GPIO Pin Async. Falling Edge Detect */
-#define BCM283X_GPIO_GPAFEN1    (0x008C)
-#define BCM283X_GPIO_GPPUD      (0x0094)  /* GPIO Pin Pull-up/down Enable */
-#define BCM283X_GPIO_GPPUDCLK0  (0x0098)  /* GPIO Pin Pull-up/down Enable Clock 0 */
-#define BCM283X_GPIO_GPPUDCLK1  (0x009C)  /* GPIO Pin Pull-up/down Enable Clock 1 */
-
-enum gpio_function_select
-{
-    BCM283X_GPIO_FSEL_INPT  = 0x00,   /*!< Input 0b000 */
-    BCM283X_GPIO_FSEL_OUTP  = 0x01,   /*!< Output 0b001 */
-    BCM283X_GPIO_FSEL_ALT0  = 0x04,   /*!< Alternate function 0 0b100 */
-    BCM283X_GPIO_FSEL_ALT1  = 0x05,   /*!< Alternate function 1 0b101 */
-    BCM283X_GPIO_FSEL_ALT2  = 0x06,   /*!< Alternate function 2 0b110, */
-    BCM283X_GPIO_FSEL_ALT3  = 0x07,   /*!< Alternate function 3 0b111 */
-    BCM283X_GPIO_FSEL_ALT4  = 0x03,   /*!< Alternate function 4 0b011 */
-    BCM283X_GPIO_FSEL_ALT5  = 0x02,   /*!< Alternate function 5 0b010 */
-    BCM283X_GPIO_FSEL_MASK  = 0x07    /*!< Function select bits mask 0b111 */
-};
-
-enum gpio_pud_mode
-{
-    BCM283X_GPIO_PUD_OFF     = 0x00,   /*!< Off ? disable pull-up/down 0b00 */
-    BCM283X_GPIO_PUD_DOWN    = 0x01,   /*!< Enable Pull Down control 0b01 */
-    BCM283X_GPIO_PUD_UP      = 0x02    /*!< Enable Pull Up control 0b10  */
-};
-
-/* Defines for BSC I2C
- * GPIO register offsets from BCM283X_BSC*_BASE.
- * Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map
- */
-/* I2C Address Map offset address */
-#define BCM283X_BSC_C 			0x0000 /*!< BSC Master Control */
-#define BCM283X_BSC_S 			0x0004 /*!< BSC Master Status */
-#define BCM283X_BSC_DLEN		0x0008 /*!< BSC Master Data Length */
-#define BCM283X_BSC_A 			0x000c /*!< BSC Master Slave Address */
-#define BCM283X_BSC_FIFO		0x0010 /*!< BSC Master Data FIFO */
-#define BCM283X_BSC_DIV			0x0014 /*!< BSC Master Clock Divider */
-#define BCM283X_BSC_DEL			0x0018 /*!< BSC Master Data Delay */
-#define BCM283X_BSC_CLKT		0x001c /*!< BSC Master Clock Stretch Timeout */
-
-/* Register masks for C Register */
-#define BCM283X_BSC_C_I2CEN 		0x00008000 /*!< I2C Enable, 0 = disabled, 1 = enabled */
-#define BCM283X_BSC_C_INTR 		0x00000400 /*!< Interrupt on RX */
-#define BCM283X_BSC_C_INTT 		0x00000200 /*!< Interrupt on TX */
-#define BCM283X_BSC_C_INTD 		0x00000100 /*!< Interrupt on DONE */
-#define BCM283X_BSC_C_ST 		0x00000080 /*!< Start transfer, 1 = Start a new transfer */
-#define BCM283X_BSC_C_CLEAR_1 		0x00000020 /*!< Clear FIFO Clear */
-#define BCM283X_BSC_C_CLEAR_2 		0x00000010 /*!< Clear FIFO Clear */
-#define BCM283X_BSC_C_READ 		0x00000001 /*!<	Read transfer */
-
-/* Register masks for S Register */
-#define BCM283X_BSC_S_CLKT 		0x00000200 /*!< Clock stretch timeout */
-#define BCM283X_BSC_S_ERR 		0x00000100 /*!< ACK error */
-#define BCM283X_BSC_S_RXF 		0x00000080 /*!< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
-#define BCM283X_BSC_S_TXE 		0x00000040 /*!< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
-#define BCM283X_BSC_S_RXD 		0x00000020 /*!< RXD FIFO contains data */
-#define BCM283X_BSC_S_TXD 		0x00000010 /*!< TXD FIFO can accept data */
-#define BCM283X_BSC_S_RXR 		0x00000008 /*!< RXR FIFO needs reading (full) */
-#define BCM283X_BSC_S_TXW 		0x00000004 /*!< TXW FIFO needs writing (full) */
-#define BCM283X_BSC_S_DONE 		0x00000002 /*!< Transfer DONE */
-#define BCM283X_BSC_S_TA 		0x00000001 /*!< Transfer Active */
-
-#define BCM283X_BSC_FIFO_SIZE   	16  /*!< BSC FIFO size */
-
-enum  i2c_clock_divider
-{
-    BCM283X_I2C_CLOCK_DIVIDER_2500   = 2500,      /*!< 2500 = 10us = 100 kHz */
-    BCM283X_I2C_CLOCK_DIVIDER_626    = 626,       /*!< 622 = 2.504us = 399.3610 kHz */
-    BCM283X_I2C_CLOCK_DIVIDER_150    = 150,       /*!< 150 = 60ns = 1.666 MHz (default at reset) */
-    BCM283X_I2C_CLOCK_DIVIDER_148    = 148        /*!< 148 = 59ns = 1.689 MHz */
-};
-
-enum i2c_reason_codes
-{
-    BCM283X_I2C_REASON_OK   	     = 0x00,      /*!< Success */
-    BCM283X_I2C_REASON_ERROR_NACK    = 0x01,      /*!< Received a NACK */
-    BCM283X_I2C_REASON_ERROR_CLKT    = 0x02,      /*!< Received Clock Stretch Timeout */
-    BCM283X_I2C_REASON_ERROR_DATA    = 0x04       /*!< Not all data is sent / received */
-};
-
-/*
- *  Interrupt Controler
- */
-#define IRQ_BASE            (PER_BASE + 0xB200)
-#define IRQ_PEND_BASIC      HWREG32(IRQ_BASE + 0x00)
-#define IRQ_PEND1           HWREG32(IRQ_BASE + 0x04)
-#define IRQ_PEND2           HWREG32(IRQ_BASE + 0x08)
-#define IRQ_FIQ_CONTROL     HWREG32(IRQ_BASE + 0x0C)
-#define IRQ_ENABLE1         HWREG32(IRQ_BASE + 0x10)
-#define IRQ_ENABLE2         HWREG32(IRQ_BASE + 0x14)
-#define IRQ_ENABLE_BASIC    HWREG32(IRQ_BASE + 0x18)
-#define IRQ_DISABLE1        HWREG32(IRQ_BASE + 0x1C)
-#define IRQ_DISABLE2        HWREG32(IRQ_BASE + 0x20)
-#define IRQ_DISABLE_BASIC   HWREG32(IRQ_BASE + 0x24)
-
-/*
- *  Gtimer IRQ flag
- */
-#define SYSTEM_TIMER_IRQ_0    (1 << 0)
-#define SYSTEM_TIMER_IRQ_1    (1 << 1)
-#define SYSTEM_TIMER_IRQ_2    (1 << 2)
-#define SYSTEM_TIMER_IRQ_3    (1 << 3)
-
-#define NON_SECURE_TIMER_IRQ    (1 << 1)
-
-/*
- *  System Timer
- */
-#define STIMER_BASE         (PER_BASE  + 0x3000)
-#define STIMER_CS           HWREG32(STIMER_BASE + 0x00)
-#define STIMER_CLO          HWREG32(STIMER_BASE + 0x04)
-#define STIMER_CHI          HWREG32(STIMER_BASE + 0x08)
-#define STIMER_C0           HWREG32(STIMER_BASE + 0x0C)
-#define STIMER_C1           HWREG32(STIMER_BASE + 0x10)
-#define STIMER_C2           HWREG32(STIMER_BASE + 0x14)
-#define STIMER_C3           HWREG32(STIMER_BASE + 0x18)
-
-/* Defines for ST */
-#define BCM283X_ST_BASE 		(PER_BASE  + 0x3000)
-#define BCM283X_ST_CS 			0x0000 /*!< System Timer Control/Status */
-#define BCM283X_ST_CLO 			0x0004 /*!< System Timer Counter Lower 32 bits */
-#define BCM283X_ST_CHI 			0x0008 /*!< System Timer Counter Upper 32 bits */
-#define BCM283X_ST_C0 			0x000C
-#define BCM283X_ST_C1 			0x0010
-#define BCM283X_ST_C2 			0x0014
-#define BCM283X_ST_C3 			0x0018
-
-/*
- * ARM Timer
- */
-#define ARM_TIMER_BASE		(PER_BASE + 0xB000)
-#define ARM_TIMER_LOAD		HWREG32(ARM_TIMER_BASE + 0x400)
-#define ARM_TIMER_VALUE		HWREG32(ARM_TIMER_BASE + 0x404)
-#define ARM_TIMER_CTRL		HWREG32(ARM_TIMER_BASE + 0x408)
-#define ARM_TIMER_IRQCLR	HWREG32(ARM_TIMER_BASE + 0x40C)
-#define ARM_TIMER_RAWIRQ	HWREG32(ARM_TIMER_BASE + 0x410)
-#define ARM_TIMER_MASKIRQ	HWREG32(ARM_TIMER_BASE + 0x414)
-#define ARM_TIMER_RELOAD	HWREG32(ARM_TIMER_BASE + 0x418)
-#define ARM_TIMER_PREDIV	HWREG32(ARM_TIMER_BASE + 0x41C)
-#define ARM_TIMER_CNTR		HWREG32(ARM_TIMER_BASE + 0x420)
-
-/*
- *  Core Timer
- */
-#define CTIMER_CTL          HWREG32(PER_BASE_40000000 + 0x00)  /* Control register */
-#define CTIMER_PRE          HWREG32(PER_BASE_40000000 + 0x08)  /* Core timer prescaler */
-#define CTIMER_LS32B        HWREG32(PER_BASE_40000000 + 0x1C)  /* Core timer access LS 32 bits */
-#define CTIMER_MS32B        HWREG32(PER_BASE_40000000 + 0x20)  /* Core timer access MS 32 bits */
-
-/*
- *  ARM Core Timer
- */
-#define C0TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x40)  /* Core0 timers Interrupt control */
-#define C1TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x44)  /* Core1 timers Interrupt control */
-#define C2TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x48)  /* Core2 timers Interrupt control */
-#define C3TIMER_INTCTL      HWREG32(PER_BASE_40000000 + 0x4C)  /* Core3 timers Interrupt control */
-#define CORETIMER_INTCTL(n)      HWREG32(PER_BASE_40000000 + 0x40 + n*4)  /* Core3 timers Interrupt control */
-/*
- *  ARM Core Mailbox interrupt
- */
-#define C0MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x50)  /* Core0 Mailboxes Interrupt control */
-#define C1MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x54)  /* Core1 Mailboxes Interrupt control */
-#define C2MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x58)  /* Core2 Mailboxes Interrupt control */
-#define C3MB_INTCTL         HWREG32(PER_BASE_40000000 + 0x5C)  /* Core3 Mailboxes Interrupt control */
-#define COREMB_INTCTL(n)    HWREG32(PER_BASE_40000000 + 0x50 + 4*n)  /* Core3 Mailboxes Interrupt control */
-/*
- *  ARM Core IRQ/FIQ status
- */
-#define C0_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x60)  /* Core0 IRQ Source */
-#define C1_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x64)  /* Core1 IRQ Source */
-#define C2_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x68)  /* Core2 IRQ Source */
-#define C3_IRQSOURCE        HWREG32(PER_BASE_40000000 + 0x6C)  /* Core3 IRQ Source */
-#define C0_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x70)  /* Core0 FIQ Source */
-#define C1_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x74)  /* Core1 FIQ Source */
-#define C2_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x78)  /* Core2 FIQ Source */
-#define C3_FIQSOURCE        HWREG32(PER_BASE_40000000 + 0x7C)  /* Core3 FIQ Source */
-#define CORE_IRQSOURCE(n)        HWREG32(PER_BASE_40000000 + 0x60+ n*0x4)
-#define CORE_FIQSOURCE(n)        HWREG32(PER_BASE_40000000 + 0x70+ n*0x4)
-
-#define CORE_MAILBOX3_SET(n)        HWREG32(PER_BASE_40000000 + 0x8C + n*0x10)
-#define CORE_MAILBOX3_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xCC + n*0x10)
-#define CORE_MAILBOX2_SET(n)        HWREG32(PER_BASE_40000000 + 0x88 + n*0x10)
-#define CORE_MAILBOX2_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC8 + n*0x10)
-#define CORE_MAILBOX1_SET(n)        HWREG32(PER_BASE_40000000 + 0x84 + n*0x10)
-#define CORE_MAILBOX1_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC4 + n*0x10)
-#define CORE_MAILBOX0_SET(n)        HWREG32(PER_BASE_40000000 + 0x80 + n*0x10)
-#define CORE_MAILBOX0_CLEAR(n)      HWREG32(PER_BASE_40000000 + 0xC0 + n*0x10)
-
-/* for smp ipi using mailbox0 */
-#define IPI_MAILBOX_SET   CORE_MAILBOX0_SET
-
-#define IPI_MAILBOX_CLEAR CORE_MAILBOX0_CLEAR
-#define IPI_MAILBOX_INT_MASK     (0x01)
-
-#define IRQ_ARM_TIMER           64
-#define IRQ_ARM_MAILBOX         65
-#define IRQ_ARM_DB0             66
-#define IRQ_ARM_DB1             67
-#define IRQ_ARM_GPU0_HALT       68
-#define IRQ_ARM_GPU1_HALT       69
-#define IRQ_ARM_ILLEGAL_ACC1    70
-#define IRQ_ARM_ILLEGAL_ACC0    71
-
-#define IRQ_SYSTIMER_MATCH_1    1
-#define IRQ_SYSTIMER_MATCH_3    3
-
-#define IRQ_AUX                 29
-#define IRQ_IIC_SPI_SLV         43
-#define IRQ_PWA0                45
-#define IRQ_PWA1                46
-#define IRQ_SMI                 48
-#define IRQ_GPIO0               49
-#define IRQ_GPIO1               50
-#define IRQ_GPIO2               51
-#define IRQ_GPIO3               52
-#define IRQ_IIC                 53
-#define IRQ_SPI                 54
-#define IRQ_PCM                 55
-#define IRQ_UART                57
-
-/* CLOCK */
-#define BCM283X_PLLA			0
-#define BCM283X_PLLB			1
-#define BCM283X_PLLC			2
-#define BCM283X_PLLD			3
-#define BCM283X_PLLH			4
-
-#define BCM283X_PLLA_CORE		5
-#define BCM283X_PLLA_PER		6
-#define BCM283X_PLLB_ARM		7
-#define BCM283X_PLLC_CORE0		8
-#define BCM283X_PLLC_CORE1		9
-#define BCM283X_PLLC_CORE2		10
-#define BCM283X_PLLC_PER		11
-#define BCM283X_PLLD_CORE		12
-#define BCM283X_PLLD_PER		13
-#define BCM283X_PLLH_RCAL		14
-#define BCM283X_PLLH_AUX		15
-#define BCM283X_PLLH_PIX		16
-
-#define BCM283X_CLOCK_TIMER		17
-#define BCM283X_CLOCK_OTP		18
-#define BCM283X_CLOCK_UART		19
-#define BCM283X_CLOCK_VPU		20
-#define BCM283X_CLOCK_V3D		21
-#define BCM283X_CLOCK_ISP		22
-#define BCM283X_CLOCK_H264		23
-#define BCM283X_CLOCK_VEC		24
-#define BCM283X_CLOCK_HSM		25
-#define BCM283X_CLOCK_SDRAM		26
-#define BCM283X_CLOCK_TSENS		27
-#define BCM283X_CLOCK_EMMC		28
-#define BCM283X_CLOCK_PERI_IMAGE	29
-#define BCM283X_CLOCK_COUNT		30
-
-#define CM_PASSWORD		0x5a000000
-
-#define CM_GNRICCTL		0x000
-#define CM_GNRICDIV		0x004
-#define CM_VPUCTL		0x008
-#define CM_VPUDIV		0x00c
-#define CM_SYSCTL		0x010
-#define CM_SYSDIV		0x014
-#define CM_PERIACTL		0x018
-#define CM_PERIADIV		0x01c
-#define CM_PERIICTL		0x020
-#define CM_PERIIDIV		0x024
-#define CM_H264CTL		0x028
-#define CM_H264DIV		0x02c
-#define CM_ISPCTL		0x030
-#define CM_ISPDIV		0x034
-#define CM_V3DCTL		0x038
-#define CM_V3DDIV		0x03c
-#define CM_CAM0CTL		0x040
-#define CM_CAM0DIV		0x044
-#define CM_CAM1CTL		0x048
-#define CM_CAM1DIV		0x04c
-#define CM_CCP2CTL		0x050
-#define CM_CCP2DIV		0x054
-#define CM_DSI0ECTL		0x058
-#define CM_DSI0EDIV		0x05c
-#define CM_DSI0PCTL		0x060
-#define CM_DSI0PDIV		0x064
-#define CM_DPICTL		0x068
-#define CM_DPIDIV		0x06c
-#define CM_GP0CTL		0x070
-#define CM_GP0DIV		0x074
-#define CM_GP1CTL		0x078
-#define CM_GP1DIV		0x07c
-#define CM_GP2CTL		0x080
-#define CM_GP2DIV		0x084
-#define CM_HSMCTL		0x088
-#define CM_HSMDIV		0x08c
-#define CM_OTPCTL		0x090
-#define CM_OTPDIV		0x094
-#define CM_PWMCTL		0x0a0
-#define CM_PWMDIV		0x0a4
-#define CM_SMICTL		0x0b0
-#define CM_SMIDIV		0x0b4
-#define CM_TSENSCTL		0x0e0
-#define CM_TSENSDIV		0x0e4
-#define CM_TIMERCTL		0x0e8
-#define CM_TIMERDIV		0x0ec
-#define CM_UARTCTL		0x0f0
-#define CM_UARTDIV		0x0f4
-#define CM_VECCTL		0x0f8
-#define CM_VECDIV		0x0fc
-#define CM_PULSECTL		0x190
-#define CM_PULSEDIV		0x194
-#define CM_SDCCTL		0x1a8
-#define CM_SDCDIV		0x1ac
-#define CM_ARMCTL		0x1b0
-#define CM_EMMCCTL		0x1c0
-#define CM_EMMCDIV		0x1c4
-
-#define BCM283X_AUX_IRQ			0x0000  /*!< xxx */
-#define BCM283X_AUX_ENABLE		0x0004  /*!< */
-#define BCM283X_AUX_ENABLE_UART1	0x01    /*!<  */
-#define BCM283X_AUX_ENABLE_SPI0		0x02	/*!< SPI0 (SPI1 in the device) */
-#define BCM283X_AUX_ENABLE_SPI1		0x04	/*!< SPI1 (SPI2 in the device) */
-#define BCM283X_AUX_SPI_CNTL0		0x0000  /*!< */
-#define BCM283X_AUX_SPI_CNTL1 		0x0004  /*!< */
-#define BCM283X_AUX_SPI_STAT 		0x0008  /*!< */
-#define BCM283X_AUX_SPI_PEEK		0x000C  /*!< Read but do not take from FF */
-#define BCM283X_AUX_SPI_IO		0x0020  /*!< Write = TX, read=RX */
-#define BCM283X_AUX_SPI_TXHOLD		0x0030  /*!< Write = TX keep CS, read=RX */
-#define BCM283X_AUX_SPI_CLOCK_MIN	30500		/*!< 30,5kHz */
-#define BCM283X_AUX_SPI_CLOCK_MAX	125000000 	/*!< 125Mhz */
-#define BCM283X_AUX_SPI_CNTL0_SPEED	0xFFF00000  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_SPEED_MAX	0xFFF      /*!< */
-#define BCM283X_AUX_SPI_CNTL0_SPEED_SHIFT 20        /*!< */
-#define BCM283X_AUX_SPI_CNTL0_CS0_N     0x000C0000 /*!< CS 0 low */
-#define BCM283X_AUX_SPI_CNTL0_CS1_N     0x000A0000 /*!< CS 1 low */
-#define BCM283X_AUX_SPI_CNTL0_CS2_N 	0x00060000 /*!< CS 2 low */
-#define BCM283X_AUX_SPI_CNTL0_POSTINPUT	0x00010000  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_VAR_CS	0x00008000  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_VAR_WIDTH	0x00004000  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_DOUTHOLD	0x00003000  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_ENABLE	0x00000800  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_CPHA_IN	0x00000400  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_CLEARFIFO	0x00000200  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_CPHA_OUT	0x00000100  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_CPOL	0x00000080  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_MSBF_OUT	0x00000040  /*!< */
-#define BCM283X_AUX_SPI_CNTL0_SHIFTLEN	0x0000003F  /*!< */
-#define BCM283X_AUX_SPI_CNTL1_CSHIGH	0x00000700  /*!< */
-#define BCM283X_AUX_SPI_CNTL1_IDLE	0x00000080  /*!< */
-#define BCM283X_AUX_SPI_CNTL1_TXEMPTY	0x00000040  /*!< */
-#define BCM283X_AUX_SPI_CNTL1_MSBF_IN	0x00000002  /*!< */
-#define BCM283X_AUX_SPI_CNTL1_KEEP_IN	0x00000001  /*!< */
-#define BCM283X_AUX_SPI_STAT_TX_LVL	0xFF000000  /*!< */
-#define BCM283X_AUX_SPI_STAT_RX_LVL	0x00FF0000  /*!< */
-#define BCM283X_AUX_SPI_STAT_TX_FULL	0x00000400  /*!< */
-#define BCM283X_AUX_SPI_STAT_TX_EMPTY	0x00000200  /*!< */
-#define BCM283X_AUX_SPI_STAT_RX_FULL	0x00000100  /*!< */
-#define BCM283X_AUX_SPI_STAT_RX_EMPTY	0x00000080  /*!< */
-#define BCM283X_AUX_SPI_STAT_BUSY	0x00000040  /*!< */
-#define BCM283X_AUX_SPI_STAT_BITCOUNT	0x0000003F  /*!< */
-
-/* Defines for SPI */
-#define BCM283X_SPI0_CS                      0x0000 /*!< SPI Master Control and Status */
-#define BCM283X_SPI0_FIFO                    0x0004 /*!< SPI Master TX and RX FIFOs */
-#define BCM283X_SPI0_CLK                     0x0008 /*!< SPI Master Clock Divider */
-#define BCM283X_SPI0_DLEN                    0x000c /*!< SPI Master Data Length */
-#define BCM283X_SPI0_LTOH                    0x0010 /*!< SPI LOSSI mode TOH */
-#define BCM283X_SPI0_DC                      0x0014 /*!< SPI DMA DREQ Controls */
-
-/* Register masks for SPI0_CS */
-#define BCM283X_SPI0_CS_LEN_LONG             0x02000000 /*!< Enable Long data word in Lossi mode if DMA_LEN is set */
-#define BCM283X_SPI0_CS_DMA_LEN              0x01000000 /*!< Enable DMA mode in Lossi mode */
-#define BCM283X_SPI0_CS_CSPOL2               0x00800000 /*!< Chip Select 2 Polarity */
-#define BCM283X_SPI0_CS_CSPOL1               0x00400000 /*!< Chip Select 1 Polarity */
-#define BCM283X_SPI0_CS_CSPOL0               0x00200000 /*!< Chip Select 0 Polarity */
-#define BCM283X_SPI0_CS_RXF                  0x00100000 /*!< RXF - RX FIFO Full */
-#define BCM283X_SPI0_CS_RXR                  0x00080000 /*!< RXR RX FIFO needs Reading (full) */
-#define BCM283X_SPI0_CS_TXD                  0x00040000 /*!< TXD TX FIFO can accept Data */
-#define BCM283X_SPI0_CS_RXD                  0x00020000 /*!< RXD RX FIFO contains Data */
-#define BCM283X_SPI0_CS_DONE                 0x00010000 /*!< Done transfer Done */
-#define BCM283X_SPI0_CS_TE_EN                0x00008000 /*!< Unused */
-#define BCM283X_SPI0_CS_LMONO                0x00004000 /*!< Unused */
-#define BCM283X_SPI0_CS_LEN                  0x00002000 /*!< LEN LoSSI enable */
-#define BCM283X_SPI0_CS_REN                  0x00001000 /*!< REN Read Enable */
-#define BCM283X_SPI0_CS_ADCS                 0x00000800 /*!< ADCS Automatically Deassert Chip Select */
-#define BCM283X_SPI0_CS_INTR                 0x00000400 /*!< INTR Interrupt on RXR */
-#define BCM283X_SPI0_CS_INTD                 0x00000200 /*!< INTD Interrupt on Done */
-#define BCM283X_SPI0_CS_DMAEN                0x00000100 /*!< DMAEN DMA Enable */
-#define BCM283X_SPI0_CS_TA                   0x00000080 /*!< Transfer Active */
-#define BCM283X_SPI0_CS_CSPOL                0x00000040 /*!< Chip Select Polarity */
-#define BCM283X_SPI0_CS_CLEAR                0x00000030 /*!< Clear FIFO Clear RX and TX */
-#define BCM283X_SPI0_CS_CLEAR_RX             0x00000020 /*!< Clear FIFO Clear RX  */
-#define BCM283X_SPI0_CS_CLEAR_TX             0x00000010 /*!< Clear FIFO Clear TX  */
-#define BCM283X_SPI0_CS_CPOL                 0x00000008 /*!< Clock Polarity */
-#define BCM283X_SPI0_CS_CPHA                 0x00000004 /*!< Clock Phase */
-#define BCM283X_SPI0_CS_CS                   0x00000003 /*!< Chip Select */
-
-enum spi_bit_order
-{
-    BCM283X_SPI_BIT_ORDER_LSBFIRST = 0,  /*!< LSB First */
-    BCM283X_SPI_BIT_ORDER_MSBFIRST = 1   /*!< MSB First */
-};
-
-enum spi_mode
-{
-    BCM283X_SPI_MODE0 = 0,  /*!< CPOL = 0, CPHA = 0 */
-    BCM283X_SPI_MODE1 = 1,  /*!< CPOL = 0, CPHA = 1 */
-    BCM283X_SPI_MODE2 = 2,  /*!< CPOL = 1, CPHA = 0 */
-    BCM283X_SPI_MODE3 = 3   /*!< CPOL = 1, CPHA = 1 */
-};
-
-enum spi_chip_select
-{
-    BCM283X_SPI_CS0 = 0,     /*!< Chip Select 0 */
-    BCM283X_SPI_CS1 = 1,     /*!< Chip Select 1 */
-    BCM283X_SPI_CS2 = 2,     /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
-    BCM283X_SPI_CS_NONE = 3  /*!< No CS, control it yourself */
-};
-
-enum spi_clock_divider
-{
-    BCM283X_SPI_CLOCK_DIVIDER_65536 = 0,       /*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_32768 = 32768,   /*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_16384 = 16384,   /*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_8192  = 8192,    /*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_4096  = 4096,    /*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_2048  = 2048,    /*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_1024  = 1024,    /*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_512   = 512,     /*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_256   = 256,     /*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_128   = 128,     /*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_64    = 64,      /*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_32    = 32,      /*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_16    = 16,      /*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_8     = 8,       /*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */
-    BCM283X_SPI_CLOCK_DIVIDER_4     = 4,       /*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */
-    BCM283X_SPI_CLOCK_DIVIDER_2     = 2,       /*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/
-    BCM283X_SPI_CLOCK_DIVIDER_1     = 1        /*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */
-};
-
-/* BCM IO pin */
-enum bcm_gpio_pin
-{
-    BCM_GPIO_PIN_0 = 0,
-    BCM_GPIO_PIN_1,
-    BCM_GPIO_PIN_2,
-    BCM_GPIO_PIN_3,
-    BCM_GPIO_PIN_4,
-    BCM_GPIO_PIN_5,
-    BCM_GPIO_PIN_6,
-    BCM_GPIO_PIN_7,
-    BCM_GPIO_PIN_8,
-    BCM_GPIO_PIN_9,
-    BCM_GPIO_PIN_10,
-    BCM_GPIO_PIN_11,
-    BCM_GPIO_PIN_12,
-    BCM_GPIO_PIN_13,
-    BCM_GPIO_PIN_14,
-    BCM_GPIO_PIN_15,
-    BCM_GPIO_PIN_16,
-    BCM_GPIO_PIN_17,
-    BCM_GPIO_PIN_18,
-    BCM_GPIO_PIN_19,
-    BCM_GPIO_PIN_20,
-    BCM_GPIO_PIN_21,
-    BCM_GPIO_PIN_22,
-    BCM_GPIO_PIN_23,
-    BCM_GPIO_PIN_24,
-    BCM_GPIO_PIN_25,
-    BCM_GPIO_PIN_26,
-    BCM_GPIO_PIN_27,
-    BCM_GPIO_PIN_28,
-    BCM_GPIO_PIN_29,
-    BCM_GPIO_PIN_30,
-    BCM_GPIO_PIN_31,
-    BCM_GPIO_PIN_32,
-    BCM_GPIO_PIN_33,
-    BCM_GPIO_PIN_34,
-    BCM_GPIO_PIN_35,
-    BCM_GPIO_PIN_36,
-    BCM_GPIO_PIN_37,
-    BCM_GPIO_PIN_38,
-    BCM_GPIO_PIN_39,
-    BCM_GPIO_PIN_40,
-    BCM_GPIO_PIN_41,
-    BCM_GPIO_PIN_42,
-    BCM_GPIO_PIN_43,
-    BCM_GPIO_PIN_44,
-    BCM_GPIO_PIN_45,
-    BCM_GPIO_PIN_46,
-    BCM_GPIO_PIN_47,
-    BCM_GPIO_PIN_48,
-    BCM_GPIO_PIN_49,
-    BCM_GPIO_PIN_50,
-    BCM_GPIO_PIN_51,
-    BCM_GPIO_PIN_52,
-    BCM_GPIO_PIN_53,
-    BCM_GPIO_PIN_NUM,
-};
-
-rt_uint32_t bcm283x_peri_read(volatile rt_ubase_t addr);
-rt_uint32_t bcm283x_peri_read_nb(volatile rt_ubase_t addr);
-void bcm283x_peri_write(volatile rt_ubase_t addr, rt_uint32_t value);
-void bcm283x_peri_write_nb(volatile rt_ubase_t addr, rt_uint32_t value);
-void bcm283x_peri_set_bits(volatile rt_ubase_t addr, rt_uint32_t value, rt_uint32_t mask);
-
-void bcm283x_gpio_fsel(rt_uint8_t pin, rt_uint8_t mode);
-void bcm283x_gpio_set(rt_uint8_t pin);
-void bcm283x_gpio_clr(rt_uint8_t pin);
-
-rt_uint8_t bcm283x_gpio_lev(rt_uint8_t pin);
-rt_uint8_t bcm283x_gpio_eds(rt_uint8_t pin);
-void bcm283x_gpio_set_eds(rt_uint8_t pin);
-void bcm283x_gpio_ren(rt_uint8_t pin);
-void bcm283x_gpio_clr_ren(rt_uint8_t pin);
-void bcm283x_gpio_fen(rt_uint8_t pin);
-void bcm283x_gpio_clr_fen(rt_uint8_t pin);
-void bcm283x_gpio_hen(rt_uint8_t pin);
-void bcm283x_gpio_clr_hen(rt_uint8_t pin);
-void bcm283x_gpio_len(rt_uint8_t pin);
-void bcm283x_gpio_clr_len(rt_uint8_t pin);
-void bcm283x_gpio_aren(rt_uint8_t pin);
-void bcm283x_gpio_clr_aren(rt_uint8_t pin);
-void bcm283x_gpio_afen(rt_uint8_t pin);
-void bcm283x_gpio_clr_afen(rt_uint8_t pin);
-void bcm283x_gpio_pud(rt_uint8_t pud);
-void bcm283x_gpio_pudclk(rt_uint8_t pin, rt_uint8_t on);
-void bcm283x_gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud);
-void bcm283x_gpio_write(rt_uint8_t pin, rt_uint8_t val);
-void bcm283x_st_delay(rt_uint64_t offset_micros, rt_uint64_t micros);
-rt_uint64_t bcm283x_st_read(void);
-void bcm283x_delayMicroseconds(rt_uint64_t micros);
-void bcm283x_clo_delayMicros(rt_uint32_t micros);
-
-int bcm283x_i2c_begin(int no);
-void bcm283x_i2c_end(int no);
-void bcm283x_i2c_setSlaveAddress(int no, rt_uint8_t saddr);
-void bcm283x_i2c_setClockDivider(int no, rt_uint16_t divider);
-void bcm283x_i2c_set_baudrate(int no, rt_uint32_t baudrate);
-rt_uint8_t bcm283x_i2c_read(rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len);
-rt_uint8_t bcm283x_i2c_write(rt_uint32_t base, const rt_uint8_t * buf, rt_uint32_t len);
-rt_uint8_t bcm283x_i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len);
-
-#endif
-
diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c
index cfaa3c9294..35f90bf54f 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/board.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.c
@@ -17,6 +17,7 @@
 
 #include "cp15.h"
 #include "mmu.h"
+#include "raspi.h"
 
 #ifdef BSP_USING_CORETIMER
 static rt_uint64_t timerStep;
diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.h b/bsp/raspberry-pi/raspi3-64/driver/board.h
index e42c249201..b44c245a17 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/board.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.h
@@ -13,10 +13,6 @@
 
 #include <stdint.h>
 
-#include <rthw.h>
-#include <bcm283x.h>
-
-#define __REG32 HWREG32
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;
 
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
index ce1883cce7..56ef412725 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
@@ -10,62 +10,8 @@
 #include "raspi.h"
 #include "drv_gpio.h"
 
-#ifdef BSP_USING_PIN
-
-struct rpi_pin_index
-{
-    rt_uint8_t phy_id;
-    rt_uint8_t bcm_id;
-    rt_uint8_t signal_name;
-    rt_uint8_t magic;
-};
-
-//raspi phy id and bcm id
-static struct rpi_pin_index phypin_index[] =
-{
-    {0, 0, 0, 0},
-    {1, 0, 0, 0},
-    {2, 0, 0, 0},
-    {3, BCM_GPIO_PIN_2, RPI_SDA1, PIN_MAGIC},
-    {4, 0, 0, 0},
-    {5, BCM_GPIO_PIN_3, RPI_SCL1, PIN_MAGIC},
-    {6, 0, 0, 0},
-    {7, BCM_GPIO_PIN_4, RPI_GPIO_GCLK,  PIN_MAGIC},
-    {8, BCM_GPIO_PIN_14, RPI_TXD0, PIN_MAGIC},
-    {9, 0, 0, 0},
-    {10, BCM_GPIO_PIN_15, RPI_RXD0, PIN_MAGIC},
-    {11, BCM_GPIO_PIN_17, RPI_GPIO_GEN0,  PIN_MAGIC},
-    {12, BCM_GPIO_PIN_18, RPI_GPIO_GEN1,  PIN_MAGIC},
-    {13, BCM_GPIO_PIN_27, RPI_GPIO_GEN2,  PIN_MAGIC},
-    {14, 0, 0, 0},
-    {15, BCM_GPIO_PIN_22, RPI_GPIO_GEN3,  PIN_MAGIC},
-    {16, BCM_GPIO_PIN_23, RPI_GPIO_GEN4, PIN_MAGIC},
-    {17, 0, 0, 0},
-    {18, BCM_GPIO_PIN_24, RPI_GPIO_GEN5, PIN_MAGIC},
-    {19, BCM_GPIO_PIN_10, RPI_SPI_MOSI, PIN_MAGIC},
-    {20, 0, 0, 0},
-    {21, BCM_GPIO_PIN_9, RPI_SPI_MISO, PIN_MAGIC},
-    {22, BCM_GPIO_PIN_25, RPI_GPIO_GEN6, PIN_MAGIC},
-    {23, BCM_GPIO_PIN_11, RPI_SPI_SCLK, PIN_MAGIC},
-    {24, BCM_GPIO_PIN_8, RPI_SPI_CE0_N, PIN_MAGIC},
-    {25, 0, 0, 0},
-    {26, BCM_GPIO_PIN_7, RPI_SPI_CE1_N, PIN_MAGIC},
-    {27, BCM_GPIO_PIN_0, RPI_SDA0, PIN_MAGIC},
-    {28, BCM_GPIO_PIN_1, RPI_SCL0, PIN_MAGIC},
-    {29, BCM_GPIO_PIN_5, RPI_CAM_CLK, PIN_MAGIC},
-    {30, 0, 0, 0},
-    {31, BCM_GPIO_PIN_6, RPI_LAN_RUN, PIN_MAGIC},
-    {32, BCM_GPIO_PIN_12, 0, PIN_MAGIC},
-    {33, BCM_GPIO_PIN_13, 0, PIN_MAGIC},
-    {34, 0, 0, 0},
-    {35, BCM_GPIO_PIN_19, 0, PIN_MAGIC},
-    {36, BCM_GPIO_PIN_16, RPI_STATUS_LED_N, PIN_MAGIC},
-    {37, BCM_GPIO_PIN_26, 0, PIN_MAGIC},
-    {38, BCM_GPIO_PIN_20, 0, PIN_MAGIC},
-    {39, 0, 0, 0},
-    {40, BCM_GPIO_PIN_21, RPI_CAM_GPIO,  PIN_MAGIC},
-};
 
+#ifdef BSP_USING_PIN
 /*
  * gpio_int[0] for BANK0 (pins 0-27)
  * gpio_int[1] for BANK1 (pins 28-45)
@@ -73,286 +19,262 @@ static struct rpi_pin_index phypin_index[] =
  */
 static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM];
 
-int gpio_set_func(enum gpio_code code, enum bcm_gpio_pin pin, rt_uint8_t func)
+void gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud)
 {
-    RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
-    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
-
-    if (func & 0x8)
-    {
-        rt_kprintf("[line]:%d There is a warning with parameter input", __LINE__);
-        return RT_EINVAL;
-    }
+    rt_uint8_t num = pin / 32;
+    rt_uint8_t shift = pin % 32;
+    BCM283X_GPIO_GPPUD = pud;
+    DELAY_MICROS(10);
+    BCM283X_GPIO_GPPUDCLK(num) = 1 << shift;
+    DELAY_MICROS(10);
+    BCM283X_GPIO_GPPUD = BCM283X_GPIO_PUD_OFF;
+    BCM283X_GPIO_GPPUDCLK(num) = 0 << shift;
+}
 
-    switch(func)
-    {
-    case 0x00:
-        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_OUTP);
-        break;
-    case 0x01:
-        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
-        break;
-    case 0x02:
-        bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
-        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
-        break;
-    case 0x03:
-        bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_DOWN);
-        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT);
-        break;
-    case 0x04:
-        bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_OFF);
-        bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_OUTP);
-        break;
-    }
+static void gpio_ack_irq(int irq, bcm_gpio_pin pin)
+{
+    rt_uint32_t data;
+    data = IRQ_PEND2;
+    data &= (0x0 << (irq - 32));
+    IRQ_PEND2 = data;
 
-    return RT_EOK;
+    data = IRQ_DISABLE2;
+    data |= (0x1 << (irq - 32));
+    IRQ_DISABLE2 = data;
 }
 
-int gpio_set_value(enum gpio_code code, enum bcm_gpio_pin pin, rt_uint8_t value)
+void gpio_irq_disable(rt_uint8_t index, bcm_gpio_pin pin)
 {
+    int irq = 0;
+    rt_uint32_t  reg_value;
+    rt_uint8_t irq_type;
+    irq = IRQ_GPIO0 + index;
 
-    RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
-    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+    gpio_ack_irq(irq, pin);
+
+    irq_type = _g_gpio_irq_tbl[index].irq_type[pin];
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t mask = 1 << shift;
 
-    if (value & 0xE)
+    switch (irq_type)
     {
-        rt_kprintf("[line]:%d There is a warning with parameter input", __LINE__);
-        return RT_EINVAL;
+    case PIN_IRQ_MODE_RISING:
+        reg_value = BCM283X_GPIO_GPREN(pin /32);
+        BCM283X_GPIO_GPREN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_FALLING:
+        reg_value = BCM283X_GPIO_GPFEN(pin /32);
+        BCM283X_GPIO_GPFEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_RISING_FALLING:
+        reg_value = BCM283X_GPIO_GPAREN(pin /32);
+        BCM283X_GPIO_GPAREN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        reg_value = BCM283X_GPIO_GPAFEN(pin /32);
+        BCM283X_GPIO_GPAFEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_HIGH_LEVEL:
+        reg_value = BCM283X_GPIO_GPHEN(pin /32);
+        BCM283X_GPIO_GPHEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
+    case PIN_IRQ_MODE_LOW_LEVEL:
+        reg_value = BCM283X_GPIO_GPLEN(pin /32);
+        BCM283X_GPIO_GPLEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask);
+        break;
     }
-
-    bcm283x_gpio_write(pin, value);
-    return RT_EOK;
 }
 
-int gpio_get_value(enum gpio_code code, enum bcm_gpio_pin pin)
+void gpio_irq_enable(rt_uint8_t index, bcm_gpio_pin pin)
 {
-    rt_uint8_t data;
-
-    RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM));
-    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+    rt_uint32_t offset;
+    rt_uint32_t data;
 
-    data = bcm283x_gpio_lev(pin);
-    return data;
-}
+    offset = pin;
+    if (index == 0)
+        offset = IRQ_GPIO0 - 32;
+    else if (index == 1)
+        offset = IRQ_GPIO1 - 32;
+    else
+        offset = IRQ_GPIO2 - 32;
 
-void gpio_set_irq_callback(enum gpio_code port, enum bcm_gpio_pin pin, void (*irq_cb)(void *), void *irq_arg)
-{
-    RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
-    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+    data = IRQ_ENABLE2;
+    data |= 0x1 << offset;
+    IRQ_ENABLE2 = data;
 
-    rt_uint8_t index;
-    if (pin <= 27)
-    {
-        index = 0;
-    }
-    else if (pin <= 45)
-    {
-        index = 1;
-    }
-    else{
-        index = 2;
-    }
-    _g_gpio_irq_tbl[index].irq_cb[pin]    = irq_cb;
-    _g_gpio_irq_tbl[index].irq_arg[pin]   = irq_arg;
 }
 
-void gpio_set_irq_type(enum gpio_code port,  enum bcm_gpio_pin pin, rt_uint8_t irq_type)
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
 {
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    RT_ASSERT(!(mode & 0x8));
 
-    RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
-    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
-
-    rt_uint8_t index;
-    if (pin <= 27)
-    {
-        index = 0;
-    }
-    else if (pin <= 45)
+    switch (mode)
     {
-        index = 1;
-    }
-    else{
-        index = 2;
-    }
-    _g_gpio_irq_tbl[index].irq_type[pin] = irq_type;
-
-    switch(irq_type)
-    {
-    case 0x00:
-        bcm283x_gpio_ren(pin);
+    case PIN_MODE_OUTPUT:
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_OUTP);
         break;
-    case 0x01:
-        bcm283x_gpio_fen(pin);
+    case PIN_MODE_INPUT:
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
         break;
-    case 0x02:
-        bcm283x_gpio_aren(pin);
-        bcm283x_gpio_afen(pin);
+    case PIN_MODE_INPUT_PULLUP:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_UP);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
         break;
-    case 0x03:
-        bcm283x_gpio_hen(pin);
+    case PIN_MODE_INPUT_PULLDOWN:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_DOWN);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT);
         break;
-    case 0x04:
-        bcm283x_gpio_len(pin);
+    case PIN_MODE_OUTPUT_OD:
+        gpio_set_pud(pin, BCM283X_GPIO_PUD_OFF);
+        GPIO_FSEL(pin, BCM283X_GPIO_FSEL_OUTP);
         break;
     }
 }
 
-static void gpio_ack_irq(int irq,  enum bcm_gpio_pin pin)
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
 {
-    rt_uint32_t data;
-    data = IRQ_PEND2;
-    data &= (0x0 << (irq - 32));
-    IRQ_PEND2 = data;
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    RT_ASSERT(!(value & 0xE));
+
+    if (value)
+        BCM283X_GPIO_GPSET(pin / 32) |= (1 << (pin %32));
+    else
+        BCM283X_GPIO_GPCLR(pin / 32) |= (0 << (pin %32));
 
-    data = IRQ_DISABLE2;
-    data |= (0x1 << (irq - 32));
-    IRQ_DISABLE2 = data;
 }
 
-void gpio_irq_disable(enum gpio_code port,  enum bcm_gpio_pin pin)
+static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
 {
-    rt_uint8_t index;
-    int irq = 0;
-    RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
-    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
+    return (BCM2835_GPIO_GPLEV(pin / 32) & (1 << (pin % 32)))? PIN_HIGH : PIN_LOW;
+}
+
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 
+    rt_uint8_t index;
+    rt_uint32_t  reg_value;
     if (pin <= 27)
-    {
         index = 0;
-        irq = IRQ_GPIO0;
-    }else if (pin <= 45){
+    else if (pin <= 45)
         index = 1;
-        irq = IRQ_GPIO1;
-    }else{
+    else
         index = 2;
-        irq = IRQ_GPIO2;
-    }
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = hdr;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = args;
+    _g_gpio_irq_tbl[index].irq_type[pin]  = mode;
 
-    gpio_ack_irq(irq, pin);
-
-    rt_uint8_t irq_type = _g_gpio_irq_tbl[index].irq_type[pin];
+    rt_uint8_t shift = pin % 32;
+    rt_uint32_t mask = 1 << shift;
 
-    switch(irq_type)
+    switch (mode)
     {
-    case 0x00:
-        bcm283x_gpio_clr_ren(pin);
+    case PIN_IRQ_MODE_RISING:
+        reg_value = BCM283X_GPIO_GPREN(pin /32);
+        BCM283X_GPIO_GPREN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
         break;
-    case 0x01:
-        bcm283x_gpio_clr_fen(pin);
+    case PIN_IRQ_MODE_FALLING:
+        reg_value = BCM283X_GPIO_GPFEN(pin /32);
+        BCM283X_GPIO_GPFEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
         break;
-    case 0x02:
-        bcm283x_gpio_clr_aren(pin);
-        bcm283x_gpio_clr_afen(pin);
+    case PIN_IRQ_MODE_RISING_FALLING:
+        reg_value = BCM283X_GPIO_GPAREN(pin /32);
+        BCM283X_GPIO_GPAREN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
+        reg_value = BCM283X_GPIO_GPAFEN(pin /32);
+        BCM283X_GPIO_GPAFEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
         break;
-    case 0x03:
-        bcm283x_gpio_clr_hen(pin);
+    case PIN_IRQ_MODE_HIGH_LEVEL:
+        reg_value = BCM283X_GPIO_GPHEN(pin /32);
+        BCM283X_GPIO_GPHEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
         break;
-    case 0x04:
-        bcm283x_gpio_clr_len(pin);
+    case PIN_IRQ_MODE_LOW_LEVEL:
+        reg_value = BCM283X_GPIO_GPLEN(pin /32);
+        BCM283X_GPIO_GPLEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask);
         break;
     }
+    return RT_EOK;
 }
 
-void gpio_clear_irq_callback(enum gpio_code port, enum bcm_gpio_pin pin)
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 {
-    rt_uint8_t index;
-    gpio_irq_disable(port, pin);
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 
+    rt_uint8_t index;
     if (pin <= 27)
-    {
         index = 0;
-    }
     else if (pin <= 45)
-    {
         index = 1;
-    }
     else
-    {
         index = 2;
-    }
+
+    gpio_irq_disable(index, pin);
 
     _g_gpio_irq_tbl[index].irq_cb[pin]    = RT_NULL;
     _g_gpio_irq_tbl[index].irq_arg[pin]   = RT_NULL;
     _g_gpio_irq_tbl[index].irq_type[pin]  = RT_NULL;
 
+    return RT_EOK;
 }
 
-
-void gpio_irq_enable(enum gpio_code port,  enum bcm_gpio_pin pin)
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
 {
+    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 
-    rt_uint32_t offset;
-    rt_uint32_t data;
-
-    RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM));
-    RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53));
-
-    offset = pin;
+    rt_uint8_t index;
     if (pin <= 27)
-    {
-        offset = IRQ_GPIO0 - 32;
-    }
+        index = 0;
     else if (pin <= 45)
-    {
-        offset = IRQ_GPIO1 - 32;
-    }
+        index = 1;
     else
-    {
-        offset = IRQ_GPIO2 - 32;
-    }
+        index = 2;
 
-    data = IRQ_ENABLE2;
-    data |= 0x1 << offset;
-    IRQ_ENABLE2 = data;
+    if (enabled)
+        gpio_irq_enable(index, pin);
+    else
+        gpio_irq_disable(index, pin);
 
+    return RT_EOK;
 }
 
-//gpio_int[0] for BANK0 (pins 0-27)
-//gpio_int[1] for BANK1 (pins 28-45)
-//gpio_int[2] for BANK2 (pins 46-53)
 static void gpio_irq_handler(int irq, void *param)
 {
     struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param;
     rt_uint32_t pin;
-    rt_uint32_t addr;
     rt_uint32_t value;
     rt_uint32_t tmpvalue;
 
     if (irq == IRQ_GPIO0)
     {
         /* 0~27 */
-        addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0; // 0~31
-        value = bcm283x_peri_read(addr);
+
+        value = BCM283X_GPIO_GPEDS(0);
         value &= 0x0fffffff;
         pin = 0;
+        BCM283X_GPIO_GPEDS(0) = 0;
     }
     else if (irq == IRQ_GPIO1)
     {
         /* 28-45 */
-        addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0;
-        tmpvalue = bcm283x_peri_read(addr);
+        tmpvalue = BCM283X_GPIO_GPEDS(0);
         tmpvalue &= (~0x0fffffff);
 
-        addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS1;
-        value = bcm283x_peri_read(addr);
+        value = BCM283X_GPIO_GPEDS(1);
         value &= 0x3fff;
         value = (value<<4) | tmpvalue;
-
         pin = 28;
+        BCM283X_GPIO_GPEDS(0) = 0;
+        BCM283X_GPIO_GPEDS(1) = 0;
     }
     else if (irq == IRQ_GPIO2)
     {
         /* 46-53 */
-        addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS1;
-        value = bcm283x_peri_read(addr);
+        value = BCM283X_GPIO_GPEDS(1);
         value &= (~0x3fff);
         value &= 0xff600000;
         pin = 46;
+        BCM283X_GPIO_GPEDS(1) = 0;
     }
 
-    bcm283x_peri_write(addr,0);
-
     while (value)
     {
         if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL))
@@ -365,90 +287,14 @@ static void gpio_irq_handler(int irq, void *param)
     }
 }
 
-static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
-{
-    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
-    {
-        rt_kprintf("pin:%d value wrongful", pin);
-        return;
-    }
-
-    gpio_set_func(GPIO_CODE_BCM, phypin_index[pin].bcm_id, mode);
-}
-
-static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
-{
-    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
-    {
-        rt_kprintf("pin:%d value wrongful", pin);
-        return;
-    }
-
-    gpio_set_value(GPIO_CODE_BCM, phypin_index[pin].bcm_id, value);
-}
-
-static int pin_read(struct rt_device *device, rt_base_t pin)
-{
-    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
-    {
-        rt_kprintf("pin:%d value wrongful", pin);
-        return 0;
-    }
-
-    return gpio_get_value(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
-}
-
-static rt_err_t pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
-{
-    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
-    {
-        rt_kprintf("pin:%d value wrongful", pin);
-        return RT_ERROR;
-    }
-
-    gpio_set_irq_callback(GPIO_CODE_BCM , phypin_index[pin].bcm_id, hdr, args);
-    gpio_set_irq_type(GPIO_CODE_BCM, phypin_index[pin].bcm_id, mode);
-
-    return RT_EOK;
-}
-
-static rt_err_t pin_detach_irq(struct rt_device *device, rt_int32_t pin)
-{
-    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
-    {
-        rt_kprintf("pin:%d value wrongful", pin);
-        return RT_ERROR;
-    }
-
-    gpio_clear_irq_callback(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
-
-    return RT_EOK;
-}
-
-rt_err_t pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
-{
-    if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC))
-    {
-        rt_kprintf("pin:%d value wrongful", pin);
-        return RT_ERROR;
-    }
-
-    if (enabled)
-        gpio_irq_enable(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
-    else
-        gpio_irq_disable(GPIO_CODE_BCM, phypin_index[pin].bcm_id);
-
-    return RT_EOK;
-}
-
 static const struct rt_pin_ops ops =
 {
-    pin_mode,
-    pin_write,
-    pin_read,
-    pin_attach_irq,
-    pin_detach_irq,
-    pin_irq_enable,
+    raspi_pin_mode,
+    raspi_pin_write,
+    raspi_pin_read,
+    raspi_pin_attach_irq,
+    raspi_pin_detach_irq,
+    raspi_pin_irq_enable,
 };
 #endif
 
@@ -456,7 +302,6 @@ int rt_hw_gpio_init(void)
 {
 #ifdef BSP_USING_PIN
     rt_device_pin_register("gpio", &ops, RT_NULL);
-#endif
 
     /* install ISR */
     rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq");
@@ -467,6 +312,7 @@ int rt_hw_gpio_init(void)
 
     rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq");
     rt_hw_interrupt_umask(IRQ_GPIO2);
+#endif
 
     return 0;
 }
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
index b0a67870ab..f51817b035 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
@@ -11,19 +11,20 @@
 #ifndef __DRV_GPIO_H__
 #define __DRV_GPIO_H__
 
-#include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
-#include <rtdebug.h>
-#include <rtdbg.h>
 
-#include "interrupt.h"
-#include "bcm283x.h"
-#include "raspi.h"
 #include "board.h"
+#include "interrupt.h"
+
 
 #define GPIO_IRQ_NUM 3
 
+#define IRQ_GPIO0               49
+#define IRQ_GPIO1               50
+#define IRQ_GPIO2               51
+#define IRQ_GPIO3               52
+
 struct gpio_irq_def
 {
     void  *irq_arg[32];
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
index 0ead0fdf74..00b31897d8 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
@@ -8,58 +8,60 @@
  * 2019-07-29     zdzn           first version
  */
 
-#include <rtthread.h>
-#include <rtdevice.h>
-#include "bcm283x.h"
 #include "drv_timer.h"
-#include <drivers/hwtimer.h>
-#include "cp15.h"
+#include "interrupt.h"
+#include "raspi.h"
 
-static void rt_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state)
+#ifdef BSP_USING_SYSTIMER
+
+static void raspi_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state)
 {
     if (state == 0)
         hwtimer->ops->stop(hwtimer);
 }
 
-static rt_err_t rt_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
+static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
 {
     rt_err_t result = RT_EOK;
     rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
     int timer_id = timer->timer_id;
+
     if (mode == HWTIMER_MODE_PERIOD)
         timer->cnt = cnt;
     else
         timer->cnt = 0; 
-    __DSB();
+
+    __sync_synchronize();
     if (timer_id == 1)
     {
-        rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_1);   
+        rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
         STIMER_C1 = STIMER_CLO + cnt;
     } 
     else if (timer_id == 3)
     {
-        rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_3);   
+        rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
         STIMER_C3 = STIMER_CLO + cnt;
     }
     else    
         result = -RT_ERROR;
-    __DSB();
+
+    __sync_synchronize();
          
     return result;
 }
 
-static void rt_systimer_stop(rt_hwtimer_t *hwtimer)
+static void raspi_systimer_stop(rt_hwtimer_t *hwtimer)
 {
     rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
     int timer_id = timer->timer_id;
     if (timer_id == 1)
-        rt_hw_interrupt_mask(IRQ_SYSTIMER_MATCH_1);      
+        rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1);
     else if (timer_id == 3)
-        rt_hw_interrupt_mask(IRQ_SYSTIMER_MATCH_3); 
+        rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3);
  
 }
 
-static rt_err_t rt_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
 {
     /* The frequency value is an immutable value. */
     if (cmd == HWTIMER_CTRL_FREQ_SET)
@@ -72,23 +74,17 @@ static rt_err_t rt_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg
     }
 }
 
-const static struct rt_hwtimer_ops systimer_ops = 
-{
-    rt_systimer_init,
-    rt_systimer_start,
-    rt_systimer_stop,
-    RT_NULL,
-    rt_systimer_ctrl
-};
 
 void rt_device_systimer_isr(int vector, void *param)
 {
+    
     rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param;
     rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
     RT_ASSERT(timer != RT_NULL);
+
     int timer_id = timer->timer_id;
 
-    __DSB();
+    __sync_synchronize();
     if (timer_id == 1)
     {
         STIMER_CS = 0x2;
@@ -99,15 +95,29 @@ void rt_device_systimer_isr(int vector, void *param)
         STIMER_CS = 0x8;
         STIMER_C3 = STIMER_CLO + timer->cnt;                 
     }
-    
-    __DSB();
+    __sync_synchronize();
+
     rt_device_hwtimer_isr(hwtimer);
 }
-    
+
+#ifdef RT_USING_SYSTIMER1
 static struct rt_hwtimer_device _hwtimer1;
+static rt_systimer_t _systimer1;
+#endif
+
+#ifdef RT_USING_SYSTIMER3
 static struct rt_hwtimer_device _hwtimer3;
-static struct rt_systimer_device _systimer1;
-static struct rt_systimer_device _systimer3;
+static rt_systimer_t _systimer3;
+#endif
+
+const static struct rt_hwtimer_ops systimer_ops =
+{
+    raspi_systimer_init,
+    raspi_systimer_start,
+    raspi_systimer_stop,
+    RT_NULL,
+    raspi_systimer_ctrl
+};
 
 static const struct rt_hwtimer_info _info =
 {
@@ -117,15 +127,20 @@ static const struct rt_hwtimer_info _info =
     HWTIMER_CNTMODE_UP  /* count mode (inc/dec) */
 };
 
+#endif
+
 int rt_hw_systimer_init(void)
 {
+
+#ifdef BSP_USING_SYSTIMER
+
 #ifdef RT_USING_SYSTIMER1
     _systimer1.timer_id =1;
     _hwtimer1.ops = &systimer_ops;
     _hwtimer1.info = &_info;
     rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1);
-    rt_hw_interrupt_install(IRQ_SYSTIMER_MATCH_1, rt_device_systimer_isr, &_hwtimer1, "systimer1");
-    rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_1);
+    rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_hwtimer1, "systimer1");
+    rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
 #endif
 
 #ifdef RT_USING_SYSTIMER3
@@ -133,9 +148,12 @@ int rt_hw_systimer_init(void)
     _hwtimer3.ops = &systimer_ops;
     _hwtimer3.info = &_info;
     rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3);
-    rt_hw_interrupt_install(IRQ_SYSTIMER_MATCH_3, rt_device_systimer_isr, &_hwtimer3, "systimer3");
-    
+    rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_hwtimer3, "systimer3");
+    rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
+#endif
+
 #endif
 
     return 0;
 }
+INIT_DEVICE_EXPORT(rt_hw_systimer_init);
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
index fd8ec66af9..62fcb966b4 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
@@ -12,11 +12,10 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
+#include "raspi.h"
 #include "board.h"
 #include "drv_uart.h"
 
-#include <rtdevice.h>
-
 #define AUX_BASE            (0x3F000000 + 0x215000)
 
 struct hw_uart_device
@@ -34,20 +33,19 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
 
     if (uart->hw_base == AUX_BASE)
     {
-    	rt_uint32_t value;
+        rt_uint32_t value;
 
         /* GPIO function set */
-        value = GPIO_GPFSEL1;
-        value &= ~(7<<12); /* GPIO14 */
-        value |=    2<<12 ; /* ALT5 */
-        value &= ~(7<<15); /* GPIO15 */
-        value |=    2<<15 ; /* ALT5 */
-        GPIO_GPFSEL1 = value;
-
-        /* PullUD disable */
-        GPIO_GPPUD = 0;
-        GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15);
-        GPIO_GPPUDCLK0 = 0;
+        value = BCM283X_GPIO_GPFSEL(1);
+        value &= ~(7 << 12); /* GPIO14 */
+        value |= 2 << 12 ; /* ALT5 */
+        value &= ~(7 << 15); /* GPIO15 */
+        value |= 2 << 15 ; /* ALT5 */
+        BCM283X_GPIO_GPFSEL(1) = value;
+
+        BCM283X_GPIO_GPPUD = 0;
+        BCM283X_GPIO_GPPUDCLK(0) = (1 << 14) | (1 << 15);
+        BCM283X_GPIO_GPPUDCLK(0) = 0;
 
         AUX_ENABLES(uart->hw_base)      = 1;    /* Enable UART1 */
         AUX_MU_IER_REG(uart->hw_base)   = 0;    /* Disable interrupt */
diff --git a/bsp/raspberry-pi/raspi3-64/driver/raspi.h b/bsp/raspberry-pi/raspi3-64/driver/raspi.h
index 001d1b7962..9a5de2af02 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/raspi.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/raspi.h
@@ -12,60 +12,160 @@
 #ifndef __RASPI_H__
 #define __RASPI_H__
 
-#include "bcm283x.h"
+#include <rthw.h>
 
-#define PIN_MAGIC       (0x5A)
-#define PIN_NUM(_N)     (sizeof(_N) / sizeof(_N[0]))
+#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
 
-enum gpio_code
+typedef enum
 {
-    GPIO_CODE_PHY = 0,
-    GPIO_CODE_BCM,
-    GPIO_CODE_WIRING,
-    GPIO_CODE_NUM,
-};
+    BCM_GPIO_PIN_0 = 0,
+    BCM_GPIO_PIN_1,
+    BCM_GPIO_PIN_2,
+    BCM_GPIO_PIN_3,
+    BCM_GPIO_PIN_4,
+    BCM_GPIO_PIN_5,
+    BCM_GPIO_PIN_6,
+    BCM_GPIO_PIN_7,
+    BCM_GPIO_PIN_8,
+    BCM_GPIO_PIN_9,
+    BCM_GPIO_PIN_10,
+    BCM_GPIO_PIN_11,
+    BCM_GPIO_PIN_12,
+    BCM_GPIO_PIN_13,
+    BCM_GPIO_PIN_14,
+    BCM_GPIO_PIN_15,
+    BCM_GPIO_PIN_16,
+    BCM_GPIO_PIN_17,
+    BCM_GPIO_PIN_18,
+    BCM_GPIO_PIN_19,
+    BCM_GPIO_PIN_20,
+    BCM_GPIO_PIN_21,
+    BCM_GPIO_PIN_22,
+    BCM_GPIO_PIN_23,
+    BCM_GPIO_PIN_24,
+    BCM_GPIO_PIN_25,
+    BCM_GPIO_PIN_26,
+    BCM_GPIO_PIN_27,
+    BCM_GPIO_PIN_28,
+    BCM_GPIO_PIN_29,
+    BCM_GPIO_PIN_30,
+    BCM_GPIO_PIN_31,
+    BCM_GPIO_PIN_32,
+    BCM_GPIO_PIN_33,
+    BCM_GPIO_PIN_34,
+    BCM_GPIO_PIN_35,
+    BCM_GPIO_PIN_36,
+    BCM_GPIO_PIN_37,
+    BCM_GPIO_PIN_38,
+    BCM_GPIO_PIN_39,
+    BCM_GPIO_PIN_40,
+    BCM_GPIO_PIN_41,
+    BCM_GPIO_PIN_42,
+    BCM_GPIO_PIN_43,
+    BCM_GPIO_PIN_44,
+    BCM_GPIO_PIN_45,
+    BCM_GPIO_PIN_46,
+    BCM_GPIO_PIN_47,
+    BCM_GPIO_PIN_48,
+    BCM_GPIO_PIN_49,
+    BCM_GPIO_PIN_50,
+    BCM_GPIO_PIN_51,
+    BCM_GPIO_PIN_52,
+    BCM_GPIO_PIN_53,
+    BCM_GPIO_PIN_NULL,
+} bcm_gpio_pin;
 
-enum rpi_pin_name
+typedef enum
 {
-    RPI_SDA0 = 0,
-    RPI_SCL0,
-    RPI_SDA1,
-    RPI_SCL1,
-    RPI_GPIO_GCLK,
-    RPI_CAM_CLK,
-    RPI_LAN_RUN,
-    RPI_SPI_CE1_N,
-    RPI_SPI_CE0_N,
-    RPI_SPI_MISO,
-    RPI_SPI_MOSI,
-    RPI_SPI_SCLK,
-    RPI_TXD0,
-    RPI_RXD0,
-    RPI_STATUS_LED_N,
-    RPI_GPIO_GEN0,
-    RPI_GPIO_GEN1,
-    RPI_CAM_GPIO,
-    RPI_GPIO_GEN3,
-    RPI_GPIO_GEN4,
-    RPI_GPIO_GEN5,
-    RPI_GPIO_GEN6,
-    RPI_GPIO_GEN2,
-    RPI_GPIO_GEN7,
-    RPI_GPIO_GEN8,
-    RPI_GPIO_GEN9,
-    RPI_GPIO_GEN10,
-    RPI_PWM0_OUT,
-    RPI_PWM1_OUT,
-    RPI_HDMI_HPD_P,
-    RPI_SD_CARD_DET,
-    RPI_SD_CLK_R,
-    RPI_SD_CMD_R,
-    RPI_SD_DATA0_R,
-    RPI_SD_DATA1_R,
-    RPI_SD_DATA2_R,
-    RPI_SD_DATA3_R,
-    RPI_GPIO_PIN_NUM,
-};
+    BCM283X_GPIO_FSEL_INPT = 0x00,   /*!< Input 0b000 */
+    BCM283X_GPIO_FSEL_OUTP = 0x01,   /*!< Output 0b001 */
+    BCM283X_GPIO_FSEL_ALT0 = 0x04,   /*!< Alternate function 0 0b100 */
+    BCM283X_GPIO_FSEL_ALT1 = 0x05,   /*!< Alternate function 1 0b101 */
+    BCM283X_GPIO_FSEL_ALT2 = 0x06,   /*!< Alternate function 2 0b110, */
+    BCM283X_GPIO_FSEL_ALT3 = 0x07,   /*!< Alternate function 3 0b111 */
+    BCM283X_GPIO_FSEL_ALT4 = 0x03,   /*!< Alternate function 4 0b011 */
+    BCM283X_GPIO_FSEL_ALT5 = 0x02,   /*!< Alternate function 5 0b010 */
+    BCM283X_GPIO_FSEL_MASK = 0x07    /*!< Function select bits mask 0b111 */
+} gpio_function_select;
+
+typedef enum
+{
+    BCM283X_GPIO_PUD_OFF    = 0x00,   /*!< Off ? disable pull-up/down 0b00 */
+    BCM283X_GPIO_PUD_DOWN   = 0x01,   /*!< Enable Pull Down control 0b01 */
+    BCM283X_GPIO_PUD_UP     = 0x02    /*!< Enable Pull Up control 0b10  */
+} gpio_pud_mode;
+
+#define BCM283X_CORE_CLK_HZ 250000000    /* 50 MHz */
+
+/* Base Address */
+#define PER_BASE     (0x3F000000)
+#define PER_BASE_40000000    (0x40000000)
+//#define BCM283X_PERI_BASE     (0x3F000000)
+//#define BCM283X_PER_BASE_40000000    (0x40000000)
+
+/* Base Address Registers Offset */
+#define ST_BASE_OFFSET     (0x003000)
+#define GPIO_PAD_OFFSET     (0x100000)
+#define CLOCK_BASE_OFFSET (0x101000)
+#define GPIO_BASE_OFFSET (0x200000)
+#define SPI0_BASE_OFFSET (0x204000)
+#define BSC0_BASE_OFFSET (0x205000)
+#define GPIO_PWM_OFFSET     (0x20C000)
+#define AUX_BASE_OFFSET     (0x215000)
+#define SPI1_BASE_OFFSET (0x215080)
+#define SPI2_BASE_OFFSET (0x2150C0)
+#define BSC1_BASE_OFFSET (0x804000)
+#define BSC2_BASE_OFFSET (0x805000)
+
+/* IRQ */
+#define IRQ_SYSTEM_TIMER_0 0
+#define IRQ_SYSTEM_TIMER_1  1
+#define IRQ_SYSTEM_TIMER_2 2
+#define IRQ_SYSTEM_TIMER_3 3
+#define IRQ_USB      9
+#define IRQ_AUX      29
+#define IRQ_PCM      55
+#define IRQ_ARM_TIMER     64
+#define IRQ_ARM_MAILBOX     65
+
+/* Interrupt Controler */
+#define IRQ_BASE     (PER_BASE + 0xB200)
+#define IRQ_PEND_BASIC      __REG32(IRQ_BASE + 0x0000)
+#define IRQ_PEND1    __REG32(IRQ_BASE + 0x0004)
+#define IRQ_PEND2    __REG32(IRQ_BASE + 0x0008)
+#define IRQ_FIQ_CONTROL     __REG32(IRQ_BASE + 0x000C)
+#define IRQ_ENABLE1  __REG32(IRQ_BASE + 0x0010)
+#define IRQ_ENABLE2  __REG32(IRQ_BASE + 0x0014)
+#define IRQ_ENABLE_BASIC    __REG32(IRQ_BASE + 0x0018)
+#define IRQ_DISABLE1 __REG32(IRQ_BASE + 0x001C)
+#define IRQ_DISABLE2 __REG32(IRQ_BASE + 0x0020)
+#define IRQ_DISABLE_BASIC   __REG32(IRQ_BASE + 0x0024)
+
+
+/* Defines for WDT*/
+#define PM_BASE  (PER_BASE  + GPIO_PAD_OFFSET)
+#define PM_RSTC  __REG32(PM_BASE + 0x001C)
+#define PM_RSTS  __REG32(PM_BASE + 0x0020)
+#define PM_WDOG  __REG32(PM_BASE + 0x0024)
+
+#define PM_PASSWORD     0x5a000000
+#define PM_WDOG_TIME_SET    0x000fffff
+#define PM_RSTC_WRCFG_CLR    0xffffffcf
+#define PM_RSTS_HADWRH_SET    0x00000040
+#define PM_RSTC_WRCFG_SET    0x00000030
+#define PM_RSTC_WRCFG_FULL_RESET    0x00000020
+#define PM_RSTC_RESET 0x00000102
+#define PM_RSTS_PARTITION_CLR 0xfffffaaa
+
+/* Defines for System Timer */
+#define STIMER_BASE  (PER_BASE  + ST_BASE_OFFSET)
+#define STIMER_CS    __REG32(STIMER_BASE + 0x0000)
+#define STIMER_CLO   __REG32(STIMER_BASE + 0x0004)
+#define STIMER_CHI   __REG32(STIMER_BASE + 0x0008)
+#define STIMER_C0    __REG32(STIMER_BASE + 0x000C)
+#define STIMER_C1    __REG32(STIMER_BASE + 0x0010)
+#define STIMER_C2    __REG32(STIMER_BASE + 0x0014)
+#define STIMER_C3    __REG32(STIMER_BASE + 0x0018)
 
 #define DELAY_MICROS(micros) \
     do{ \
@@ -73,4 +173,273 @@ enum rpi_pin_name
  while (STIMER_CLO < compare); \
     } while (0) \
 
+/* Defines for GPIO */
+#define BCM283X_GPIO_BASE     (PER_BASE + GPIO_BASE_OFFSET)
+#define BCM283X_GPIO_GPFSEL(n) __REG32(BCM283X_GPIO_BASE + 0x0000 + 0x4 * n) /* GPIO Function Select 32bit R/W */
+#define BCM283X_GPIO_GPSET(n) __REG32(BCM283X_GPIO_BASE + 0x001C + 0x4 * n) /* GPIO Pin Output Set */
+#define BCM283X_GPIO_GPCLR(n) __REG32(BCM283X_GPIO_BASE + 0x0028 + 0x4 * n) /* GPIO Pin Output Clear */
+#define BCM2835_GPIO_GPLEV(n) __REG32(BCM283X_GPIO_BASE + 0x0034 + 0x4 * n) /* GPIO Pin Level */
+#define BCM283X_GPIO_GPEDS(n) __REG32(BCM283X_GPIO_BASE + 0x0040 + 0x4 * n) /* GPIO Pin Event Detect Status */
+#define BCM283X_GPIO_GPREN(n) __REG32(BCM283X_GPIO_BASE + 0x004c + 0x4 * n) /* GPIO Pin Rising Edge Detect Enable */
+#define BCM283X_GPIO_GPFEN(n) __REG32(BCM283X_GPIO_BASE + 0x0058 + 0x4 * n) /* GPIO Pin Falling Edge Detect Enable */
+#define BCM283X_GPIO_GPHEN(n) __REG32(BCM283X_GPIO_BASE + 0x0064 + 0x4 * n) /* GPIO Pin High Detect Enable  */
+#define BCM283X_GPIO_GPLEN(n) __REG32(BCM283X_GPIO_BASE + 0x0070 + 0x4 * n) /* GPIO Pin Low Detect Enable */
+#define BCM283X_GPIO_GPAREN(n) __REG32(BCM283X_GPIO_BASE + 0x007C + 0x4 * n) /* GPIO Pin Async. Rising Edge Detect */
+#define BCM283X_GPIO_GPAFEN(n) __REG32(BCM283X_GPIO_BASE + 0x0088 + 0x4 * n) /* GPIO Pin Async. Falling Edge Detect */
+#define BCM283X_GPIO_GPPUD     __REG32(BCM283X_GPIO_BASE + 0x0094)     /* GPIO Pin Pull-up/down Enable */
+#define BCM283X_GPIO_GPPUDCLK(n)    __REG32(BCM283X_GPIO_BASE + 0x0098 + 0x4 * n) /* GPIO Pin Pull-up/down Enable Clock */
+
+#define GPIO_FSEL_NUM(pin)  (pin/10)
+#define GPIO_FSEL_SHIFT(pin)  ((pin%10)*3)
+#define GPIO_FSEL(pin, mode) \
+    do{ \
+ __sync_synchronize(); \
+ BCM283X_GPIO_GPFSEL(GPIO_FSEL_NUM(pin)) |= ((mode & BCM283X_GPIO_FSEL_MASK) << GPIO_FSEL_SHIFT(pin)); \
+    } while (0) \
+
+/* Defines for I2C */
+#define BCM283X_BSC0_BASE     (PER_BASE + BSC0_BASE_OFFSET)    //for i2c0
+#define BCM283X_BSC1_BASE     (PER_BASE + BSC1_BASE_OFFSET)    //for i2c1
+#define BCM283X_BSC2_BASE     (PER_BASE + BSC2_BASE_OFFSET)    //for hdmi i2c not use
+
+#define BCM283X_BSC_C(BASE)  __REG32(BASE + 0x0000)    /* BSC Master Control */
+#define BCM283X_BSC_S(BASE)  __REG32(BASE + 0x0004)    /* BSC Master Status */
+#define BCM283X_BSC_DLEN(BASE)      __REG32(BASE + 0x0008)    /* BSC Master Data Length */
+#define BCM283X_BSC_A(BASE)  __REG32(BASE + 0x000c)    /* BSC Master Slave Address */
+#define BCM283X_BSC_FIFO(BASE)      __REG32(BASE + 0x0010)    /* BSC Master Data FIFO */
+#define BCM283X_BSC_DIV(BASE)       __REG32(BASE + 0x0014)    /* BSC Master Clock Divider */
+#define BCM283X_BSC_DEL(BASE)       __REG32(BASE + 0x0018)    /* BSC Master Data Delay */
+#define BCM283X_BSC_CLKT(BASE)      __REG32(BASE + 0x001c)    /* BSC Master Clock Stretch Timeout */
+
+/* Register masks for C Register */
+#define BSC_C_I2CEN      0x00008000 /* I2C Enable, 0 = disabled, 1 = enabled */
+#define BSC_C_INTR      0x00000400 /* Interrupt on RX */
+#define BSC_C_INTT      0x00000200 /* Interrupt on TX */
+#define BSC_C_INTD      0x00000100 /* Interrupt on DONE */
+#define BSC_C_ST      0x00000080 /* Start transfer, 1 = Start a new transfer */
+#define BSC_C_CLEAR_1   0x00000020 /* Clear FIFO Clear */
+#define BSC_C_CLEAR_2   0x00000010 /* Clear FIFO Clear */
+#define BSC_C_READ       0x00000001 /* Read transfer */
+
+/* Register masks for S Register */
+#define BSC_S_CLKT      0x00000200 /* Clock stretch timeout */
+#define BSC_S_ERR      0x00000100 /* ACK error */
+#define BSC_S_RXF       0x00000080 /* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
+#define BSC_S_TXE       0x00000040 /* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
+#define BSC_S_RXD       0x00000020 /* RXD FIFO contains data */
+#define BSC_S_TXD       0x00000010 /* TXD FIFO can accept data */
+#define BSC_S_RXR      0x00000008 /* RXR FIFO needs reading (full) */
+#define BSC_S_TXW      0x00000004 /* TXW FIFO needs writing (full) */
+#define BSC_S_DONE      0x00000002 /* Transfer DONE */
+#define BSC_S_TA      0x00000001 /* Transfer Active */
+
+#define BSC_FIFO_SIZE  (16)  /* BSC FIFO size */
+
+/* Defines for SPI */
+#define BCM283X_SPI0_BASE     (PER_BASE + SPI0_BASE_OFFSET)
+#define BCM283X_SPI1_BASE     (PER_BASE + SPI1_BASE_OFFSET)
+#define BCM283X_SPI2_BASE     (PER_BASE + SPI2_BASE_OFFSET)
+
+#define BCM283X_SPI0_CS(BASE) __REG32(BASE + 0x0000) /* SPI Master Control and Status */
+#define BCM283X_SPI0_FIFO(BASE) __REG32(BASE + 0x0004) /* SPI Master TX and RX FIFOs */
+#define BCM283X_SPI0_CLK(BASE) __REG32(BASE + 0x0008) /* SPI Master Clock Divider */
+#define BCM283X_SPI0_DLEN(BASE) __REG32(BASE + 0x000c) /* SPI Master Data Length */
+#define BCM283X_SPI0_LTOH(BASE) __REG32(BASE + 0x0010) /* SPI LOSSI mode TOH */
+#define BCM283X_SPI0_DC(BASE) __REG32(BASE + 0x0014) /* SPI DMA DREQ Controls */
+
+/* Register masks for SPI0_CS */
+#define BCM283X_SPI0_CS_LEN_LONG    0x02000000 /* Enable Long data word in Lossi mode if DMA_LEN is set */
+#define BCM283X_SPI0_CS_DMA_LEN 0x01000000 /* Enable DMA mode in Lossi mode */
+#define BCM283X_SPI0_CS_CSPOL2 0x00800000 /* Chip Select 2 Polarity */
+#define BCM283X_SPI0_CS_CSPOL1 0x00400000 /* Chip Select 1 Polarity */
+#define BCM283X_SPI0_CS_CSPOL0 0x00200000 /* Chip Select 0 Polarity */
+#define BCM283X_SPI0_CS_RXF     0x00100000 /* RXF - RX FIFO Full */
+#define BCM283X_SPI0_CS_RXR     0x00080000 /* RXR RX FIFO needs Reading (full) */
+#define BCM283X_SPI0_CS_TXD     0x00040000 /* TXD TX FIFO can accept Data */
+#define BCM283X_SPI0_CS_RXD     0x00020000 /* RXD RX FIFO contains Data */
+#define BCM283X_SPI0_CS_DONE 0x00010000 /* Done transfer Done */
+#define BCM283X_SPI0_CS_TE_EN 0x00008000 /* Unused */
+#define BCM283X_SPI0_CS_LMONO 0x00004000 /* Unused */
+#define BCM283X_SPI0_CS_LEN     0x00002000 /* LEN LoSSI enable */
+#define BCM283X_SPI0_CS_REN     0x00001000 /* REN Read Enable */
+#define BCM283X_SPI0_CS_ADCS 0x00000800 /* ADCS Automatically Deassert Chip Select */
+#define BCM283X_SPI0_CS_INTR 0x00000400 /* INTR Interrupt on RXR */
+#define BCM283X_SPI0_CS_INTD 0x00000200 /* INTD Interrupt on Done */
+#define BCM283X_SPI0_CS_DMAEN 0x00000100 /* DMAEN DMA Enable */
+#define BCM283X_SPI0_CS_TA     0x00000080 /* Transfer Active */
+#define BCM283X_SPI0_CS_CSPOL 0x00000040 /* Chip Select Polarity */
+#define BCM283X_SPI0_CS_CLEAR 0x00000030 /* Clear FIFO Clear RX and TX */
+#define BCM283X_SPI0_CS_CLEAR_RX    0x00000020 /* Clear FIFO Clear RX  */
+#define BCM283X_SPI0_CS_CLEAR_TX    0x00000010 /* Clear FIFO Clear TX  */
+#define BCM283X_SPI0_CS_CPOL 0x00000008 /* Clock Polarity */
+#define BCM283X_SPI0_CS_CPHA 0x00000004 /* Clock Phase */
+#define BCM283X_SPI0_CS_CS     0x00000003 /* Chip Select */
+
+/* ARM Timer */
+#define ARM_TIMER_BASE  (PER_BASE + 0xB000)
+#define ARM_TIMER_LOAD  __REG32(ARM_TIMER_BASE + 0x400)
+#define ARM_TIMER_VALUE  __REG32(ARM_TIMER_BASE + 0x404)
+#define ARM_TIMER_CTRL  __REG32(ARM_TIMER_BASE + 0x408)
+#define ARM_TIMER_IRQCLR     __REG32(ARM_TIMER_BASE + 0x40C)
+#define ARM_TIMER_RAWIRQ     __REG32(ARM_TIMER_BASE + 0x410)
+#define ARM_TIMER_MASKIRQ     __REG32(ARM_TIMER_BASE + 0x414)
+#define ARM_TIMER_RELOAD     __REG32(ARM_TIMER_BASE + 0x418)
+#define ARM_TIMER_PREDIV     __REG32(ARM_TIMER_BASE + 0x41C)
+#define ARM_TIMER_CNTR  __REG32(ARM_TIMER_BASE + 0x420)
+
+/* ARM Core Timer */
+#define C0TIMER_INTCTL   __REG32(PER_BASE_40000000 + 0x40)  /* Core0 timers Interrupt control */
+#define C1TIMER_INTCTL  __REG32(PER_BASE_40000000 + 0x44)  /* Core1 timers Interrupt control */
+#define C2TIMER_INTCTL  __REG32(PER_BASE_40000000 + 0x48)  /* Core2 timers Interrupt control */
+#define C3TIMER_INTCTL  __REG32(PER_BASE_40000000 + 0x4C)  /* Core3 timers Interrupt control */
+#define CORETIMER_INTCTL(n)     __REG32(PER_BASE_40000000 + 0x40 + n*4)  /* Coren timers Interrupt control */
+
+/*
+ *  Gtimer IRQ flag
+ */
+#define SYSTEM_TIMER_IRQ_0    (1 << 0)
+#define SYSTEM_TIMER_IRQ_1    (1 << 1)
+#define SYSTEM_TIMER_IRQ_2    (1 << 2)
+#define SYSTEM_TIMER_IRQ_3    (1 << 3)
+
+#define NON_SECURE_TIMER_IRQ    (1 << 1)
+
+/* ARM Core Mailbox interrupt */
+#define C0MB_INTCTL      __REG32(PER_BASE_40000000 + 0x50)  /* Core0 Mailboxes Interrupt control */
+#define C1MB_INTCTL      __REG32(PER_BASE_40000000 + 0x54)  /* Core1 Mailboxes Interrupt control */
+#define C2MB_INTCTL      __REG32(PER_BASE_40000000 + 0x58)  /* Core2 Mailboxes Interrupt control */
+#define C3MB_INTCTL      __REG32(PER_BASE_40000000 + 0x5C)  /* Core3 Mailboxes Interrupt control */
+#define COREMB_INTCTL(n)     __REG32(PER_BASE_40000000 + 0x50 + 4*n)  /* Coren Mailboxes Interrupt control */
+
+/* ARM Core IRQ/FIQ status */
+#define C0_IRQSOURCE  __REG32(PER_BASE_40000000 + 0x60)  /* Core0 IRQ Source */
+#define C1_IRQSOURCE  __REG32(PER_BASE_40000000 + 0x64)  /* Core1 IRQ Source */
+#define C2_IRQSOURCE  __REG32(PER_BASE_40000000 + 0x68)  /* Core2 IRQ Source */
+#define C3_IRQSOURCE  __REG32(PER_BASE_40000000 + 0x6C)  /* Core3 IRQ Source */
+#define C0_FIQSOURCE  __REG32(PER_BASE_40000000 + 0x70)  /* Core0 FIQ Source */
+#define C1_FIQSOURCE  __REG32(PER_BASE_40000000 + 0x74)  /* Core1 FIQ Source */
+#define C2_FIQSOURCE  __REG32(PER_BASE_40000000 + 0x78)  /* Core2 FIQ Source */
+#define C3_FIQSOURCE  __REG32(PER_BASE_40000000 + 0x7C)  /* Core3 FIQ Source */
+#define CORE_IRQSOURCE(n)     __REG32(PER_BASE_40000000 + 0x60+ n*0x4)
+#define CORE_FIQSOURCE(n)     __REG32(PER_BASE_40000000 + 0x70+ n*0x4)
+
+#define CORE_MAILBOX3_SET(n) __REG32(PER_BASE_40000000 + 0x8C + n*0x10)
+#define CORE_MAILBOX3_CLEAR(n)      __REG32(PER_BASE_40000000 + 0xCC + n*0x10)
+#define CORE_MAILBOX2_SET(n) __REG32(PER_BASE_40000000 + 0x88 + n*0x10)
+#define CORE_MAILBOX2_CLEAR(n)      __REG32(PER_BASE_40000000 + 0xC8 + n*0x10)
+#define CORE_MAILBOX1_SET(n) __REG32(PER_BASE_40000000 + 0x84 + n*0x10)
+#define CORE_MAILBOX1_CLEAR(n)      __REG32(PER_BASE_40000000 + 0xC4 + n*0x10)
+#define CORE_MAILBOX0_SET(n) __REG32(PER_BASE_40000000 + 0x80 + n*0x10)
+#define CORE_MAILBOX0_CLEAR(n)      __REG32(PER_BASE_40000000 + 0xC0 + n*0x10)
+
+/* For SMP IPI use MailBox0 */
+#define IPI_MAILBOX_SET  CORE_MAILBOX0_SET
+#define IPI_MAILBOX_CLEAR     CORE_MAILBOX0_CLEAR
+#define IPI_MAILBOX_INT_MASK (0x01)
+
+enum spi_bit_order
+{
+    BCM283X_SPI_BIT_ORDER_LSBFIRST = 0,  /*!< LSB First */
+    BCM283X_SPI_BIT_ORDER_MSBFIRST = 1   /*!< MSB First */
+};
+
+enum spi_mode
+{
+    BCM283X_SPI_MODE0 = 0,  /*!< CPOL = 0, CPHA = 0 */
+    BCM283X_SPI_MODE1 = 1,  /*!< CPOL = 0, CPHA = 1 */
+    BCM283X_SPI_MODE2 = 2,  /*!< CPOL = 1, CPHA = 0 */
+    BCM283X_SPI_MODE3 = 3   /*!< CPOL = 1, CPHA = 1 */
+};
+
+enum spi_chip_select
+{
+    BCM283X_SPI_CS0 = 0,     /*!< Chip Select 0 */
+    BCM283X_SPI_CS1 = 1,     /*!< Chip Select 1 */
+    BCM283X_SPI_CS2 = 2,     /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
+    BCM283X_SPI_CS_NONE = 3  /*!< No CS, control it yourself */
+};
+
+enum spi_clock_divider
+{
+    BCM283X_SPI_CLOCK_DIVIDER_65536 = 0,       /*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_32768 = 32768,   /*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_16384 = 16384,   /*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_8192 = 8192,    /*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_4096 = 4096,    /*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_2048 = 2048,    /*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_1024 = 1024,    /*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_512  = 512,     /*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_256  = 256,     /*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_128  = 128,     /*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_64   = 64,      /*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_32   = 32,      /*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_16   = 16,      /*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_8    = 8,       /*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */
+    BCM283X_SPI_CLOCK_DIVIDER_4    = 4,       /*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */
+    BCM283X_SPI_CLOCK_DIVIDER_2    = 2,       /*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/
+    BCM283X_SPI_CLOCK_DIVIDER_1    = 1 /*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */
+};
+
+/*redefine for raspi*/
+typedef gpio_function_select raspi_pin_select;
+typedef enum
+{
+    RPI_GPIO_P1_01 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_02 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_03 = BCM_GPIO_PIN_2,
+    RPI_GPIO_P1_04 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_05 = BCM_GPIO_PIN_3,
+    RPI_GPIO_P1_06 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_07 = BCM_GPIO_PIN_4,
+    RPI_GPIO_P1_08 = BCM_GPIO_PIN_14,
+    RPI_GPIO_P1_09 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_10 = BCM_GPIO_PIN_15,
+    RPI_GPIO_P1_11 = BCM_GPIO_PIN_17,
+    RPI_GPIO_P1_12 = BCM_GPIO_PIN_18,
+    RPI_GPIO_P1_13 = BCM_GPIO_PIN_27,
+    RPI_GPIO_P1_14 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_15 = BCM_GPIO_PIN_22,
+    RPI_GPIO_P1_16 = BCM_GPIO_PIN_23,
+    RPI_GPIO_P1_17 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_18 = BCM_GPIO_PIN_24,
+    RPI_GPIO_P1_19 = BCM_GPIO_PIN_10,
+    RPI_GPIO_P1_20 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_21 = BCM_GPIO_PIN_9,
+    RPI_GPIO_P1_22 = BCM_GPIO_PIN_25,
+    RPI_GPIO_P1_23 = BCM_GPIO_PIN_11,
+    RPI_GPIO_P1_24 = BCM_GPIO_PIN_8,
+    RPI_GPIO_P1_25 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_26 = BCM_GPIO_PIN_7,
+    RPI_GPIO_P1_27 = BCM_GPIO_PIN_0,
+    RPI_GPIO_P1_28 = BCM_GPIO_PIN_1,
+    RPI_GPIO_P1_29 = BCM_GPIO_PIN_5,
+    RPI_GPIO_P1_30 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_31 = BCM_GPIO_PIN_6,
+    RPI_GPIO_P1_32 = BCM_GPIO_PIN_12,
+    RPI_GPIO_P1_33 = BCM_GPIO_PIN_13,
+    RPI_GPIO_P1_34 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_35 = BCM_GPIO_PIN_19,
+    RPI_GPIO_P1_36 = BCM_GPIO_PIN_16,
+    RPI_GPIO_P1_37 = BCM_GPIO_PIN_26,
+    RPI_GPIO_P1_38 = BCM_GPIO_PIN_20,
+    RPI_GPIO_P1_39 = BCM_GPIO_PIN_NULL,
+    RPI_GPIO_P1_40 = BCM_GPIO_PIN_21,
+} raspi_gpio_pin;
+
+typedef enum
+{
+    BCM283X_I2C_CLOCK_DIVIDER_2500  = 2500,      /* 2500 = 10us = 100 kHz */
+    BCM283X_I2C_CLOCK_DIVIDER_626   = 626,       /* 622 = 2.504us = 399.3610 kHz */
+    BCM283X_I2C_CLOCK_DIVIDER_150   = 150,       /* 150 = 60ns = 1.666 MHz (default at reset) */
+    BCM283X_I2C_CLOCK_DIVIDER_148   = 148 /* 148 = 59ns = 1.689 MHz */
+} i2c_clock_divider;
+
+typedef enum
+{
+    BCM283X_I2C_REASON_OK    = 0x00,      /* Success */
+    BCM283X_I2C_REASON_ERROR_NACK   = 0x01,      /* Received a NACK */
+    BCM283X_I2C_REASON_ERROR_CLKT   = 0x02,      /* Received Clock Stretch Timeout */
+    BCM283X_I2C_REASON_ERROR_DATA   = 0x04       /* Not all data is sent / received */
+} i2c_reason_codes;
+
 #endif
diff --git a/bsp/raspberry-pi/raspi3-64/rtconfig.h b/bsp/raspberry-pi/raspi3-64/rtconfig.h
index 0e569b52ef..0dc44fcb15 100644
--- a/bsp/raspberry-pi/raspi3-64/rtconfig.h
+++ b/bsp/raspberry-pi/raspi3-64/rtconfig.h
@@ -101,6 +101,7 @@
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
 #define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_HWTIMER
 #define RT_USING_PIN
 #define RT_USING_SDIO
 #define RT_SDIO_STACK_SIZE 2048
@@ -193,6 +194,8 @@
 #define RT_USING_UART1
 #define BSP_USING_PIN
 #define BSP_USING_CORETIMER
+#define BSP_USING_SYSTIMER
+#define RT_USING_SYSTIMER1
 #define BSP_USING_SDIO
 #define BSP_USING_SDIO0
 
diff --git a/libcpu/aarch64/cortex-a53/cp15.h b/libcpu/aarch64/cortex-a53/cp15.h
index 91c37d679f..f3ffd6f857 100644
--- a/libcpu/aarch64/cortex-a53/cp15.h
+++ b/libcpu/aarch64/cortex-a53/cp15.h
@@ -11,7 +11,6 @@
 #ifndef __CP15_H__
 #define __CP15_H__
 
-#include "bcm283x.h"
 #ifndef   __STATIC_FORCEINLINE
 #define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
 #endif
diff --git a/libcpu/aarch64/cortex-a53/interrupt.c b/libcpu/aarch64/cortex-a53/interrupt.c
index 8ad60c6de2..a412ca1953 100644
--- a/libcpu/aarch64/cortex-a53/interrupt.c
+++ b/libcpu/aarch64/cortex-a53/interrupt.c
@@ -12,12 +12,12 @@
  */
 
 #include <rthw.h>
+#include <board.h>
 #include <rtthread.h>
 
 #include "cp15.h"
 #include "armv8.h"
-
-#include <board.h>
+#include "interrupt.h"
 
 #define MAX_HANDLERS                72
 
diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h
index 0c20f79bcc..3533d3818c 100644
--- a/libcpu/aarch64/cortex-a53/interrupt.h
+++ b/libcpu/aarch64/cortex-a53/interrupt.h
@@ -14,6 +14,8 @@
 #include <rthw.h>
 #include <board.h>
 
+#include "raspi.h"
+
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
-- 
cgit v1.3.1


From cc95025f052f98414ebe9e2a77334937a6ca550d Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Mon, 2 Mar 2020 20:42:01 +0800
Subject: fix build err

---
 libcpu/aarch64/cortex-a53/mmu.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'libcpu')

diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
index 15e014deb6..61d64164b1 100644
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ b/libcpu/aarch64/cortex-a53/mmu.h
@@ -20,6 +20,8 @@
 #define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
 #define MEM_ATTR_IO     ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
 
+#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+
 void mmu_init(void);
 
 void mmu_enable(void);
-- 
cgit v1.3.1


From 6416a18554c11945271e16fbb8233396a25fba24 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Tue, 17 Mar 2020 13:45:13 +0800
Subject: add cache option api

---
 libcpu/aarch64/cortex-a53/SConscript |   1 +
 libcpu/aarch64/cortex-a53/cache.S    | 151 +++++++++++++++++++++++++++++++++++
 libcpu/aarch64/cortex-a53/mmu.c      |  94 ++++++++++++++++++++++
 libcpu/aarch64/cortex-a53/mmu.h      |  47 ++++++++++-
 4 files changed, 292 insertions(+), 1 deletion(-)
 create mode 100644 libcpu/aarch64/cortex-a53/cache.S

(limited to 'libcpu')

diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript
index 57a5accc5c..75e170a0cf 100644
--- a/libcpu/aarch64/cortex-a53/SConscript
+++ b/libcpu/aarch64/cortex-a53/SConscript
@@ -7,6 +7,7 @@ context_gcc.S
 vector_gcc.S
 entry_point.S
 cpu_gcc.S
+cache.S
 ''')
 CPPPATH = [cwd]
 
diff --git a/libcpu/aarch64/cortex-a53/cache.S b/libcpu/aarch64/cortex-a53/cache.S
new file mode 100644
index 0000000000..7f295a2b02
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/cache.S
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2020-03-17     bigmagic           first version
+ */
+
+/*
+ * void __asm_dcache_level(level)
+ *
+ * flush or invalidate one level cache.
+ *
+ * x0: cache level
+ * x1: 0 clean & invalidate, 1 invalidate only
+ * x2~x9: clobbered
+ */
+.globl __asm_dcache_level
+__asm_dcache_level:
+    lsl    x12, x0, #1
+    msr    csselr_el1, x12        /* select cache level */
+    isb                /* sync change of cssidr_el1 */
+    mrs    x6, ccsidr_el1        /* read the new cssidr_el1 */
+    and    x2, x6, #7        /* x2 <- log2(cache line size)-4 */
+    add    x2, x2, #4        /* x2 <- log2(cache line size) */
+    mov    x3, #0x3ff
+    and    x3, x3, x6, lsr #3    /* x3 <- max number of #ways */
+    clz    w5, w3            /* bit position of #ways */
+    mov    x4, #0x7fff
+    and    x4, x4, x6, lsr #13    /* x4 <- max number of #sets */
+    /* x12 <- cache level << 1 */
+    /* x2 <- line length offset */
+    /* x3 <- number of cache ways - 1 */
+    /* x4 <- number of cache sets - 1 */
+    /* x5 <- bit position of #ways */
+
+loop_set:
+    mov    x6, x3            /* x6 <- working copy of #ways */
+loop_way:
+    lsl    x7, x6, x5
+    orr    x9, x12, x7        /* map way and level to cisw value */
+    lsl    x7, x4, x2
+    orr    x9, x9, x7        /* map set number to cisw value */
+    tbz    w1, #0, 1f
+    dc    isw, x9
+    b    2f
+1:    dc    cisw, x9        /* clean & invalidate by set/way */
+2:    subs    x6, x6, #1        /* decrement the way */
+    b.ge    loop_way
+    subs    x4, x4, #1        /* decrement the set */
+    b.ge    loop_set
+
+    ret
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 clean & invalidate, 1 invalidate only
+ *
+ * flush or invalidate all data cache by SET/WAY.
+ */
+.globl __asm_dcache_all
+__asm_dcache_all:
+    mov    x1, x0
+    dsb    sy
+    mrs    x10, clidr_el1        /* read clidr_el1 */
+    lsr    x11, x10, #24
+    and    x11, x11, #0x7        /* x11 <- loc */
+    cbz    x11, finished        /* if loc is 0, exit */
+    mov    x15, lr
+    mov    x0, #0            /* start flush at cache level 0 */
+    /* x0  <- cache level */
+    /* x10 <- clidr_el1 */
+    /* x11 <- loc */
+    /* x15 <- return address */
+
+loop_level:
+    lsl    x12, x0, #1
+    add    x12, x12, x0        /* x0 <- tripled cache level */
+    lsr    x12, x10, x12
+    and    x12, x12, #7        /* x12 <- cache type */
+    cmp    x12, #2
+    b.lt    skip            /* skip if no cache or icache */
+    bl    __asm_dcache_level    /* x1 = 0 flush, 1 invalidate */
+skip:
+    add    x0, x0, #1        /* increment cache level */
+    cmp    x11, x0
+    b.gt    loop_level
+
+    mov    x0, #0
+    msr    csselr_el1, x0        /* restore csselr_el1 */
+    dsb    sy
+    isb
+    mov    lr, x15
+
+finished:
+    ret
+
+.globl __asm_flush_dcache_all
+__asm_flush_dcache_all:
+    mov    x0, #0
+    b    __asm_dcache_all
+
+.globl __asm_invalidate_dcache_all
+__asm_invalidate_dcache_all:
+    mov    x0, #0x1
+    b    __asm_dcache_all
+
+/*
+ * void __asm_flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+.globl __asm_flush_dcache_range
+__asm_flush_dcache_range:
+    mrs    x3, ctr_el0
+    lsr    x3, x3, #16
+    and    x3, x3, #0xf
+    mov    x2, #4
+    lsl    x2, x2, x3        /* cache line size */
+
+    /* x2 <- minimal cache line size in cache system */
+    sub    x3, x2, #1
+    bic    x0, x0, x3
+1:    dc    civac, x0    /* clean & invalidate data or unified cache */
+    add    x0, x0, x2
+    cmp    x0, x1
+    b.lo    1b
+    dsb    sy
+    ret
+
+/*
+ * void __asm_invalidate_icache_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+.globl __asm_invalidate_icache_all
+__asm_invalidate_icache_all:
+    ic    ialluis
+    isb    sy
+    ret
+
+.globl __asm_flush_l3_cache
+__asm_flush_l3_cache:
+    mov    x0, #0            /* return status as success */
+    ret
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
index aab6bf9ebe..b799143084 100644
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ b/libcpu/aarch64/cortex-a53/mmu.c
@@ -9,6 +9,7 @@
  */
 #include <mmu.h>
 #include <stddef.h>
+#include <rthw.h>
 
 #define TTBR_CNP    1
 
@@ -35,6 +36,13 @@ static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
 
 int free_idx = 1;
 
+void __asm_invalidate_icache_all(void);
+void __asm_flush_dcache_all(void);
+int __asm_flush_l3_cache(void);
+void __asm_flush_dcache_range(unsigned long long start, unsigned long long end);
+void __asm_invalidate_dcache_all(void);
+void __asm_invalidate_icache_all(void);
+
 void mmu_memset(char *dst, char v,  size_t len)
 {
     while (len--)
@@ -50,6 +58,20 @@ static unsigned long get_free_page(void)
     return (unsigned long)(main_tbl + __page_off);
 }
 
+
+static inline unsigned int get_sctlr(void)
+{
+    unsigned int val;
+    asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+    return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+    asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+    asm volatile("isb");
+}
+
 void mmu_init(void)
 {
     unsigned long val64;
@@ -101,6 +123,9 @@ void mmu_enable(void)
     __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
     val32 |= 0x1005; //enable mmu, I C M
     __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
+    rt_hw_icache_enable();
+    rt_hw_dcache_enable();
+
 }
 
 static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
@@ -271,3 +296,72 @@ void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned
     map_region(va, pa, size, attr);
 }
 
+void rt_hw_dcache_enable(void)
+{
+    if (!(get_sctlr() & CR_M)) 
+    {
+        rt_kprintf("please init mmu!\n");
+    }
+    else
+    {
+        set_sctlr(get_sctlr() | CR_C);
+    }
+}
+
+void rt_hw_dcache_flush_all(void)
+{
+    int ret;
+
+    __asm_flush_dcache_all();
+    ret = __asm_flush_l3_cache();
+    if (ret)
+    {
+        rt_kprintf("flushing dcache returns 0x%x\n", ret);
+    }
+    else
+    {
+        rt_kprintf("flushing dcache successfully.\n");
+    }
+}
+
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
+{
+    __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
+{
+    __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+
+void rt_hw_dcache_invalidate_all(void)
+{
+    __asm_invalidate_dcache_all();
+}
+
+void rt_hw_dcache_disable(void)
+{
+    /* if cache isn't enabled no need to disable */
+    if(!(get_sctlr() & CR_C))
+    {
+        rt_kprintf("need enable cache!\n");
+        return;
+    }
+    set_sctlr(get_sctlr() & ~CR_C);
+}
+
+//icache
+void rt_hw_icache_enable(void)
+{
+    __asm_invalidate_icache_all();
+    set_sctlr(get_sctlr() | CR_I);
+}
+
+void rt_hw_icache_invalidate_all(void)
+{
+    __asm_invalidate_icache_all();
+}
+
+void rt_hw_icache_disable(void)
+{
+    set_sctlr(get_sctlr() & ~CR_I);
+}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
index 61d64164b1..6a66472c79 100644
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ b/libcpu/aarch64/cortex-a53/mmu.h
@@ -11,6 +11,37 @@
 #ifndef  __MMU_H__
 #define  __MMU_H__
 
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M    (1 << 0)    /* MMU enable                */
+#define CR_A    (1 << 1)    /* Alignment abort enable        */
+#define CR_C    (1 << 2)    /* Dcache enable            */
+#define CR_W    (1 << 3)    /* Write buffer enable            */
+#define CR_P    (1 << 4)    /* 32-bit exception handler        */
+#define CR_D    (1 << 5)    /* 32-bit data address range        */
+#define CR_L    (1 << 6)    /* Implementation defined        */
+#define CR_B    (1 << 7)    /* Big endian                */
+#define CR_S    (1 << 8)    /* System MMU protection        */
+#define CR_R    (1 << 9)    /* ROM MMU protection            */
+#define CR_F    (1 << 10)    /* Implementation defined        */
+#define CR_Z    (1 << 11)    /* Implementation defined        */
+#define CR_I    (1 << 12)    /* Icache enable            */
+#define CR_V    (1 << 13)    /* Vectors relocated to 0xffff0000    */
+#define CR_RR   (1 << 14)    /* Round Robin cache replacement    */
+#define CR_L4   (1 << 15)    /* LDR pc can set T bit            */
+#define CR_DT   (1 << 16)
+#define CR_IT   (1 << 18)
+#define CR_ST   (1 << 19)
+#define CR_FI   (1 << 21)    /* Fast interrupt (lower latency mode)    */
+#define CR_U    (1 << 22)    /* Unaligned access operation        */
+#define CR_XP   (1 << 23)    /* Extended page tables            */
+#define CR_VE   (1 << 24)    /* Vectored interrupts            */
+#define CR_EE   (1 << 25)    /* Exception (Big) Endian        */
+#define CR_TRE  (1 << 28)    /* TEX remap enable            */
+#define CR_AFE  (1 << 29)    /* Access flag enable            */
+#define CR_TE   (1 << 30)    /* Thumb exception enable        */
+
 #define MMU_LEVEL_MASK 0x1ffUL
 #define MMU_MAP_ERROR_VANOTALIGN  -1
 #define MMU_MAP_ERROR_PANOTALIGN  -2
@@ -20,7 +51,7 @@
 #define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
 #define MEM_ATTR_IO     ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
 
-#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+#define BUS_ADDRESS(phys)    (((phys) & ~0xC0000000)  |  0xC0000000)
 
 void mmu_init(void);
 
@@ -30,4 +61,18 @@ int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long at
 
 void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
 
+//dcache
+void rt_hw_dcache_enable(void);
+void rt_hw_dcache_flush_all(void);
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size);
+void rt_hw_dcache_invalidate_all(void);
+void rt_hw_dcache_disable(void);
+
+//icache
+void rt_hw_icache_enable(void);
+void rt_hw_icache_invalidate_all(void);
+void rt_hw_icache_disable(void);
+
+
 #endif  /*__MMU_H__*/
-- 
cgit v1.3.1


From e6600dbf107ae82366d9320a4af6865d689280a8 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Fri, 13 Mar 2020 11:31:15 +0800
Subject: remove cortex-a53 from libcpu/arm

---
 libcpu/arm/cortex-a53/cp15.h      | 168 ----------------------------------
 libcpu/arm/cortex-a53/cpu.c       |  91 ------------------
 libcpu/arm/cortex-a53/interrupt.c | 186 -------------------------------------
 libcpu/arm/cortex-a53/interrupt.h |  18 ----
 libcpu/arm/cortex-a53/mmu.c       | 188 --------------------------------------
 5 files changed, 651 deletions(-)
 delete mode 100644 libcpu/arm/cortex-a53/cp15.h
 delete mode 100644 libcpu/arm/cortex-a53/cpu.c
 delete mode 100644 libcpu/arm/cortex-a53/interrupt.c
 delete mode 100644 libcpu/arm/cortex-a53/interrupt.h
 delete mode 100644 libcpu/arm/cortex-a53/mmu.c

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-a53/cp15.h b/libcpu/arm/cortex-a53/cp15.h
deleted file mode 100644
index 14b85b7e64..0000000000
--- a/libcpu/arm/cortex-a53/cp15.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-#include "raspi.h"
-#ifndef __CP15_H__
-#define __CP15_H__
-
-#ifndef   __STATIC_FORCEINLINE
-#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
-#endif
-
-#define __WFI()    __asm__ volatile ("wfi":::"memory")
-
-#define __WFE()    __asm__ volatile ("wfe":::"memory")
-
-#define __SEV()    __asm__ volatile ("sev")
-
-__STATIC_FORCEINLINE  void __ISB(void)
-{
-    __asm__ volatile ("isb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE  void __DSB(void)
-{
-    __asm__ volatile ("dsb 0xF":::"memory");
-}
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-
-__STATIC_FORCEINLINE  void __DMB(void)
-{
-    __asm__ volatile ("dmb 0xF":::"memory");
-}
-
-
-#ifdef RT_USING_SMP
-static inline void send_ipi_msg(int cpu, int ipi_vector)
-{
-    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
-}
-
-static inline void setup_bootstrap_addr(int cpu, int addr)
-{
-	CORE_MAILBOX3_SET(cpu) = addr;
-}
-
-static inline void enable_cpu_ipi_intr(int cpu)
-{
-    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
-}
-
-static inline void enable_cpu_timer_intr(int cpu)
-{
-	CORETIMER_INTCTL(cpu) = 0x8;
-}
-
-static inline void enable_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 1;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
-}
-
-static inline void disable_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 0;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
-}
-
-static inline  void mask_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 2;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
-}
-
-static inline void unmask_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 1;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
-}
-
-static inline rt_uint64_t read_cntvct(void)
-{
-    rt_uint32_t val,val1;
-    asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
-    return (val);
-}
-
-static inline rt_uint64_t read_cntvoff(void)
-{
-
-    rt_uint64_t val;
-    asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
-    return (val);
-}
-
-static inline rt_uint32_t read_cntv_tval(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
-    return val;
-}
-
-
-static inline  void write_cntv_tval(rt_uint32_t val)
-{
-    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
-    return;
-}
-
-static inline rt_uint32_t read_cntfrq(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
-    return val;
-}
-
-
-static inline  rt_uint32_t read_cntctrl(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
-    return val;
-}
-
-static inline uint32_t write_cntctrl(uint32_t val)
-{
-
-    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
-    return val;
-}
-#endif
-
-unsigned long rt_cpu_get_smp_id(void);
-
-void rt_cpu_mmu_disable(void);
-void rt_cpu_mmu_enable(void);
-void rt_cpu_tlb_set(volatile unsigned long*);
-
-void rt_cpu_dcache_clean_flush(void);
-void rt_cpu_icache_flush(void);
-
-void rt_cpu_vector_set_base(unsigned int addr);
-void rt_hw_mmu_init(void);
-void rt_hw_vector_init(void);
-
-void set_timer_counter(unsigned int counter);
-void set_timer_control(unsigned int control);
-#endif
diff --git a/libcpu/arm/cortex-a53/cpu.c b/libcpu/arm/cortex-a53/cpu.c
deleted file mode 100644
index 4d02ca35e1..0000000000
--- a/libcpu/arm/cortex-a53/cpu.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- * 2019-07-28     zdzn         add smp support
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <board.h>
-#include "cp15.h"
-
-int rt_hw_cpu_id(void)
-{
-    int cpu_id;
-    __asm__ volatile (
-            "mrc p15, 0, %0, c0, c0, 5"
-            :"=r"(cpu_id)
-            );
-    cpu_id &= 0xf;
-    return cpu_id;
-};
-
-
-#ifdef RT_USING_SMP
-void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
-{
-    lock->slock = 0;
-}
-
-void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
-{
-    unsigned long tmp;
-    unsigned long newval;
-    rt_hw_spinlock_t lockval;
-    __asm__ __volatile__(
-            "pld [%0]"
-            ::"r"(&lock->slock)
-            );
-
-    __asm__ __volatile__(
-            "1: ldrex   %0, [%3]\n"
-            "   add %1, %0, %4\n"
-            "   strex   %2, %1, [%3]\n"
-            "   teq %2, #0\n"
-            "   bne 1b"
-            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
-            : "r" (&lock->slock), "I" (1 << 16)
-            : "cc");
-
-    while (lockval.tickets.next != lockval.tickets.owner) 
-    {
-        __WFE();
-        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
-    }
-
-    __DMB();
-}
-
-void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
-{
-    __DMB();
-    lock->tickets.owner++;
-    __DSB();
-    __SEV();
-}
-#endif /*RT_USING_SMP*/
-
-/**
- * @addtogroup ARM CPU
- */
-/*@{*/
-
-/** shutdown CPU */
-void rt_hw_cpu_shutdown()
-{
-    rt_uint32_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/arm/cortex-a53/interrupt.c b/libcpu/arm/cortex-a53/interrupt.c
deleted file mode 100644
index c9e7c17f8f..0000000000
--- a/libcpu/arm/cortex-a53/interrupt.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018/5/3       Bernard      first version
- * 2019-07-28     zdzn         add smp support
- * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
- *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "cp15.h"
-#include <board.h>
-
-#define MAX_HANDLERS                72
-
-#ifdef RT_USING_SMP
-#define rt_interrupt_nest rt_cpu_self()->irq_nest
-#else
-extern volatile rt_uint8_t rt_interrupt_nest;
-#endif
-
-const unsigned int VECTOR_BASE = 0x00;
-extern void rt_cpu_vector_set_base(unsigned int addr);
-extern int system_vectors;
-
-void rt_hw_vector_init(void)
-{
-    rt_cpu_vector_set_base((unsigned int)&system_vectors);
-}
-
-/* exception and interrupt handler table */
-struct rt_irq_desc isr_table[MAX_HANDLERS];
-
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-extern int system_vectors;
-
-static void default_isr_handler(int vector, void *param)
-{
-#ifdef RT_USING_SMP
-    rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
-#else
-    rt_kprintf("unhandled irq: %d\n",vector);
-#endif
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    rt_uint32_t index;
-
-    /* mask all of interrupts */
-    IRQ_DISABLE_BASIC = 0x000000ff;
-    IRQ_DISABLE1      = 0xffffffff;
-    IRQ_DISABLE2      = 0xffffffff;
-    for (index = 0; index < MAX_HANDLERS; index ++)
-    {
-        isr_table[index].handler = default_isr_handler;
-        isr_table[index].param = NULL;
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
-        isr_table[index].counter = 0;
-#endif
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-
-    if (vector < 32)
-    {
-        IRQ_DISABLE1 = (1 << vector);
-    }
-    else if (vector < 64)
-    {
-        vector = vector % 32;
-        IRQ_DISABLE2 = (1 << vector);
-    }
-    else
-    {
-        vector = vector - 64;
-        IRQ_DISABLE_BASIC = (1 << vector);
-    }
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    if (vector < 32)
-    {
-        IRQ_ENABLE1 = (1 << vector);
-    }
-    else if (vector < 64)
-    {
-        vector = vector % 32;
-        IRQ_ENABLE2 = (1 << vector);
-    }
-    else
-    {
-        vector = vector - 64;
-        IRQ_ENABLE_BASIC = (1 << vector);
-    }
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector < MAX_HANDLERS)
-    {
-        old_handler = isr_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-            isr_table[vector].handler = handler;
-            isr_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
-
-#ifdef RT_USING_SMP
-void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
-{
-    __DSB();
-    if (cpu_mask & 0x1)
-    {
-        send_ipi_msg(0, ipi_vector);
-    }
-    if (cpu_mask & 0x2)
-    {
-    	send_ipi_msg(1, ipi_vector);
-    }
-    if (cpu_mask & 0x4)
-    {
-    	send_ipi_msg(2, ipi_vector);
-    }
-    if (cpu_mask & 0x8)
-    {
-    	send_ipi_msg(3, ipi_vector);
-    }
-    __DSB();
-}
-#endif
-
-#ifdef RT_USING_SMP
-void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
-{
-    /* note: ipi_vector maybe different with irq_vector */
-    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
-}
-#endif
diff --git a/libcpu/arm/cortex-a53/interrupt.h b/libcpu/arm/cortex-a53/interrupt.h
deleted file mode 100644
index 9aae0f556a..0000000000
--- a/libcpu/arm/cortex-a53/interrupt.h
+++ /dev/null
@@ -1,18 +0,0 @@
-
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-#include <rthw.h>
-#include <board.h>
-
-#define INT_IRQ     0x00
-#define INT_FIQ     0x01
-
-void rt_hw_interrupt_init(void);
-void rt_hw_interrupt_mask(int vector);
-void rt_hw_interrupt_umask(int vector);
-
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name);
-
-#endif
diff --git a/libcpu/arm/cortex-a53/mmu.c b/libcpu/arm/cortex-a53/mmu.c
deleted file mode 100644
index b3541d2ad4..0000000000
--- a/libcpu/arm/cortex-a53/mmu.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2012-01-10     bernard      porting to AM1808
- * 2019-07-28     zdzn         add smp support
- */
-
-#include "mmu.h"
-
-/* dump 2nd level page table */
-void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    for (i = 0; i < 256; i++)
-    {
-        rt_uint32_t pte2 = ptb[i];
-        if ((pte2 & 0x3) == 0)
-        {
-            if (fcnt == 0)
-                rt_kprintf("    ");
-            rt_kprintf("%04x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("    %04x: %x: ", i, pte2);
-        if ((pte2 & 0x3) == 0x1)
-        {
-            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
-                       (pte2 >> 15) & 0x1,
-                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
-                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
-        }
-    }
-}
-
-void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    rt_kprintf("page table@%p\n", ptb);
-    for (i = 0; i < 1024*4; i++)
-    {
-        rt_uint32_t pte1 = ptb[i];
-        if ((pte1 & 0x3) == 0)
-        {
-            rt_kprintf("%03x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("%03x: %08x: ", i, pte1);
-        if ((pte1 & 0x3) == 0x3)
-        {
-            rt_kprintf("LPAE\n");
-        }
-        else if ((pte1 & 0x3) == 0x1)
-        {
-            rt_kprintf("pte,ns:%d,domain:%d\n",
-                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
-            /*
-             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
-             *                               - 0x80000000 + 0xC0000000));
-             */
-        }
-        else if (pte1 & (1 << 18))
-        {
-            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("section,ns:%d,ap:%x,"
-                       "xn:%d,texcb:%02x,domain:%d\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       (((pte1 & (0x7 << 12)) >> 10) |
-                        ((pte1 &        0x0c) >>  2)) & 0x1f,
-                       (pte1 >> 5) & 0xf);
-        }
-    }
-}
-
-/* level1 page table, each entry for 1MB memory. */
-volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
-void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
-                      rt_uint32_t vaddrEnd,
-                      rt_uint32_t paddrStart,
-                      rt_uint32_t attr)
-{
-    volatile rt_uint32_t *pTT;
-    volatile int i, nSec;
-    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
-    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
-    for (i = 0; i <= nSec; i++)
-    {
-        *pTT = attr | (((paddrStart >> 20) + i) << 20);
-        pTT++;
-    }
-}
-
-unsigned long rt_hw_set_domain_register(unsigned long domain_val)
-{
-    unsigned long old_domain;
-
-    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
-    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
-
-    return old_domain;
-}
-
-void rt_hw_init_mmu_table()
-{
-    /* set page table */
-    /* 4G 1:1 memory */
-    rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
-    /* IO memory region */
-    rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
-}
-
-void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
-                      rt_uint32_t size,
-                      rt_uint32_t paddrStart, rt_uint32_t attr)
-{
-    rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
-#ifndef RT_USING_SMP
-    rt_cpu_dcache_clean_flush();
-    rt_cpu_icache_flush();
-#endif
-}
-
-
-void rt_hw_mmu_init(void)
-{
-    rt_cpu_dcache_clean_flush();
-    rt_cpu_icache_flush();
-    rt_hw_cpu_dcache_disable();
-    rt_hw_cpu_icache_disable();
-    rt_cpu_mmu_disable();
-
-    /*rt_hw_cpu_dump_page_table(MMUTable);*/
-    rt_hw_set_domain_register(0x55555555);
-
-    rt_cpu_tlb_set(MMUTable);
-
-    rt_cpu_mmu_enable();
-
-    rt_hw_cpu_icache_enable();
-    rt_hw_cpu_dcache_enable();
-}
-
-- 
cgit v1.3.1


From efbb5490d7799caf70e5bf76a1d0a8b02fcfb9e2 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 19 Mar 2020 18:31:55 +0800
Subject: add soc timer cntpct

---
 bsp/raspberry-pi/raspi3-64/driver/board.c |  2 ++
 libcpu/aarch64/cortex-a53/context_gcc.S   | 14 ++++++++++++++
 2 files changed, 16 insertions(+)

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c
index 0305dda8d9..5d15dda987 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/board.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.c
@@ -25,6 +25,8 @@ static rt_uint64_t timerStep;
 
 int rt_hw_get_gtimer_frq(void);
 void rt_hw_set_gtimer_val(rt_uint64_t value);
+int rt_hw_get_gtimer_val(void);
+int rt_hw_get_cntpct_val(void);
 void rt_hw_gtimer_enable(void);
 
 void core0_timer_enable_interrupt_controller()
diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S
index d5c241036e..934db7ed84 100644
--- a/libcpu/aarch64/cortex-a53/context_gcc.S
+++ b/libcpu/aarch64/cortex-a53/context_gcc.S
@@ -25,6 +25,20 @@ rt_hw_set_gtimer_val:
 	MSR CNTP_TVAL_EL0,X0
 	RET
 
+/*
+ *get gtimer CNTP_TVAL_EL0 value
+ */
+.globl rt_hw_get_gtimer_val
+rt_hw_get_gtimer_val:
+	MRS X0,CNTP_TVAL_EL0
+	RET
+
+
+.globl rt_hw_get_cntpct_val
+rt_hw_get_cntpct_val:
+	MRS X0, CNTPCT_EL0
+	RET
+
 /*
  *get gtimer frq value
  */
-- 
cgit v1.3.1


From 0f26ffa7a26117396e2763fa74bf397cf907efe3 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Sun, 5 Apr 2020 13:29:29 +0800
Subject: add ls2k bsp

---
 bsp/ls2kdev/.config                 | 435 ++++++++++++++++++++++++++++++++++++
 bsp/ls2kdev/Kconfig                 |  32 +++
 bsp/ls2kdev/README.md               |   8 +
 bsp/ls2kdev/SConscript              |  12 +
 bsp/ls2kdev/SConstruct              |  39 ++++
 bsp/ls2kdev/applications/SConscript |   8 +
 bsp/ls2kdev/applications/main.c     |  17 ++
 bsp/ls2kdev/drivers/SConscript      |  10 +
 bsp/ls2kdev/drivers/board.c         |  99 ++++++++
 bsp/ls2kdev/drivers/board.h         |  24 ++
 bsp/ls2kdev/drivers/drv_uart.c      | 178 +++++++++++++++
 bsp/ls2kdev/drivers/drv_uart.h      | 114 ++++++++++
 bsp/ls2kdev/drivers/interrupt.c     |  89 ++++++++
 bsp/ls2kdev/drivers/ls2k1000.h      |  13 ++
 bsp/ls2kdev/mipssim_ram.lds         | 141 ++++++++++++
 bsp/ls2kdev/rtconfig.h              | 168 ++++++++++++++
 bsp/ls2kdev/rtconfig.py             |  60 +++++
 libcpu/Kconfig                      |   3 +
 libcpu/mips/common/asm.h            |  89 ++++++++
 libcpu/mips/common/entry_gcc.S      |  25 ++-
 libcpu/mips/common/mips_addrspace.h |  18 +-
 libcpu/mips/gs264/SConscript        |  14 ++
 libcpu/mips/gs264/cpuinit_gcc.S     |  26 +++
 23 files changed, 1606 insertions(+), 16 deletions(-)
 create mode 100644 bsp/ls2kdev/.config
 create mode 100644 bsp/ls2kdev/Kconfig
 create mode 100644 bsp/ls2kdev/README.md
 create mode 100644 bsp/ls2kdev/SConscript
 create mode 100644 bsp/ls2kdev/SConstruct
 create mode 100644 bsp/ls2kdev/applications/SConscript
 create mode 100644 bsp/ls2kdev/applications/main.c
 create mode 100644 bsp/ls2kdev/drivers/SConscript
 create mode 100644 bsp/ls2kdev/drivers/board.c
 create mode 100644 bsp/ls2kdev/drivers/board.h
 create mode 100644 bsp/ls2kdev/drivers/drv_uart.c
 create mode 100644 bsp/ls2kdev/drivers/drv_uart.h
 create mode 100644 bsp/ls2kdev/drivers/interrupt.c
 create mode 100644 bsp/ls2kdev/drivers/ls2k1000.h
 create mode 100644 bsp/ls2kdev/mipssim_ram.lds
 create mode 100644 bsp/ls2kdev/rtconfig.h
 create mode 100644 bsp/ls2kdev/rtconfig.py
 create mode 100644 libcpu/mips/gs264/SConscript
 create mode 100644 libcpu/mips/gs264/cpuinit_gcc.S

(limited to 'libcpu')

diff --git a/bsp/ls2kdev/.config b/bsp/ls2kdev/.config
new file mode 100644
index 0000000000..00b8746e4f
--- /dev/null
+++ b/bsp/ls2kdev/.config
@@ -0,0 +1,435 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_MIPS64=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread MIPS CPU
+#
+# CONFIG_RT_USING_FPU is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_MPLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+# CONFIG_PKG_USING_JS_PERSIMMON is not set
+# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RDBD_SRC is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_RTX is not set
+# CONFIG_RT_USING_TESTCASE is not set
+# CONFIG_PKG_USING_NGHTTP2 is not set
+# CONFIG_PKG_USING_AVS is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_STS is not set
+# CONFIG_PKG_USING_DLMS is not set
+# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
+# CONFIG_PKG_USING_ZBAR is not set
+CONFIG_SOC_LS2K1000=y
diff --git a/bsp/ls2kdev/Kconfig b/bsp/ls2kdev/Kconfig
new file mode 100644
index 0000000000..5cfb6892ff
--- /dev/null
+++ b/bsp/ls2kdev/Kconfig
@@ -0,0 +1,32 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$RTT_DIR/libcpu/mips/common/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_LS2K1000
+    bool
+    select ARCH_MIPS64
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select RT_USING_DEVICE
+    default y
+    
\ No newline at end of file
diff --git a/bsp/ls2kdev/README.md b/bsp/ls2kdev/README.md
new file mode 100644
index 0000000000..9e3ce3aa1e
--- /dev/null
+++ b/bsp/ls2kdev/README.md
@@ -0,0 +1,8 @@
+ls2k 板级支持包
+
+
+---
+
+## 1. 简介
+
+本bsp在龙芯派上运行
\ No newline at end of file
diff --git a/bsp/ls2kdev/SConscript b/bsp/ls2kdev/SConscript
new file mode 100644
index 0000000000..0992612410
--- /dev/null
+++ b/bsp/ls2kdev/SConscript
@@ -0,0 +1,12 @@
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/ls2kdev/SConstruct b/bsp/ls2kdev/SConstruct
new file mode 100644
index 0000000000..c605363062
--- /dev/null
+++ b/bsp/ls2kdev/SConstruct
@@ -0,0 +1,39 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+rtconfig.AFLAGS += ' -I' + str(Dir('#'))
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+rtconfig.LFLAGS += " -Ttext 0xffffffff80200000"
+env.Replace(LINKFLAGS = rtconfig.LFLAGS)
+
+if GetDepend('RT_USING_FPU'):
+    env['CCFLAGS']   = env['CCFLAGS'].replace('-msoft-float', '-mhard-float')
+    env['ASFLAGS']   = env['ASFLAGS'].replace('-msoft-float', '-mhard-float')
+    env['CXXFLAGS']  = env['CXXFLAGS'].replace('-msoft-float', '-mhard-float')
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('-msoft-float', '-mhard-float')
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/ls2kdev/applications/SConscript b/bsp/ls2kdev/applications/SConscript
new file mode 100644
index 0000000000..fb5ce2ce93
--- /dev/null
+++ b/bsp/ls2kdev/applications/SConscript
@@ -0,0 +1,8 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''])
+
+Return('group')
diff --git a/bsp/ls2kdev/applications/main.c b/bsp/ls2kdev/applications/main.c
new file mode 100644
index 0000000000..54691f0f89
--- /dev/null
+++ b/bsp/ls2kdev/applications/main.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic    first version
+ */
+
+#include <rtthread.h>
+
+int main(int argc, char** argv)
+{   
+    rt_kprintf("ls2k1000:hello rtthread!\n");
+    return 0;
+}
diff --git a/bsp/ls2kdev/drivers/SConscript b/bsp/ls2kdev/drivers/SConscript
new file mode 100644
index 0000000000..d5542b768f
--- /dev/null
+++ b/bsp/ls2kdev/drivers/SConscript
@@ -0,0 +1,10 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/ls2kdev/drivers/board.c b/bsp/ls2kdev/drivers/board.c
new file mode 100644
index 0000000000..3edbae9ee7
--- /dev/null
+++ b/bsp/ls2kdev/drivers/board.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic     Initial version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "mips_regs.h"
+#include "exception.h"
+#include "drv_uart.h"
+#include "board.h"
+/**
+ * this function will reset CPU
+ *
+ */
+void rt_hw_cpu_reset(void)
+{
+    rt_kprintf("reboot system...\n");
+    while (1);
+}
+
+/**
+ * this function will shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    while (1);
+}
+
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void rt_hw_timer_handler(void)
+{
+    unsigned int count;
+
+    count = read_c0_compare();
+    write_c0_compare(count);
+    write_c0_count(0);
+    /* increase a OS tick */
+    rt_tick_increase();
+}
+
+/**
+ * This function will initial OS timer
+ */
+void rt_hw_timer_init(void)
+{
+    write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
+    write_c0_count(0);
+    mips_unmask_cpu_irq(7);
+}
+
+/**
+ * Board level initialization
+ */
+void rt_hw_board_init(void)
+{
+    rt_hw_exception_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
+
+    #ifdef RT_USING_FPU
+    /* init hardware fpu */
+    rt_hw_fpu_init();
+    #endif
+
+#ifdef RT_USING_SERIAL
+    /* init hardware UART device */
+    rt_hw_uart_init();
+    /* set console device */
+    rt_console_set_device("uart");
+#endif
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void*)RT_HW_HEAP_BEGIN, (void*)RT_HW_HEAP_END);
+#endif
+
+    /* init operating system timer */
+    rt_hw_timer_init();
+
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+    rt_kprintf("Current SR: 0x%08x\n", read_c0_status());
+
+}
diff --git a/bsp/ls2kdev/drivers/board.h b/bsp/ls2kdev/drivers/board.h
new file mode 100644
index 0000000000..df4b40fb78
--- /dev/null
+++ b/bsp/ls2kdev/drivers/board.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic     the first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+
+extern unsigned char __bss_end;
+
+#define CPU_HZ	(100 * 1000 * 1000)
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/ls2kdev/drivers/drv_uart.c b/bsp/ls2kdev/drivers/drv_uart.c
new file mode 100644
index 0000000000..428393dcc4
--- /dev/null
+++ b/bsp/ls2kdev/drivers/drv_uart.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic     Initial version
+ */
+
+/**
+ * @addtogroup ls2k
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include "drv_uart.h"
+
+#define TRUE 1
+#define FALSE 0
+
+struct rt_uart_ls2k
+{
+    void *base;
+    rt_uint32_t IRQ;
+};
+
+static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+
+    UART_IER(uart_dev->base) = 0; /* clear interrupt */
+    UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */
+    /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+    UART_LCR(uart_dev->base) = 0x3;
+    UART_MCR(uart_dev->base) = 0x3;
+    UART_LSR(uart_dev->base) = 0x60;
+    UART_MSR(uart_dev->base) = 0xb0;
+
+    return RT_EOK;
+}
+
+static rt_err_t mipssim_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT: /* Disable RX IRQ */
+        rt_hw_interrupt_mask(uart_dev->IRQ);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT: /* Enable RX IRQ */
+        rt_hw_interrupt_umask(uart_dev->IRQ);
+        UART_IER(uart_dev->base) |= (IER_IRxE|IER_ILE);
+        break;
+
+    default:
+        break;
+    }
+
+    return RT_EOK;
+
+}
+
+static rt_bool_t uart_is_transmit_empty(struct rt_uart_ls2k *uart_dev)
+{
+    unsigned char status = UART_LSR(uart_dev->base);
+
+    if (status & (UARTLSR_TE | UARTLSR_TFE))
+    {
+        return TRUE;
+    }
+    else
+    {
+        return FALSE;
+    }
+}
+
+static int mipssim_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+
+    while (FALSE == uart_is_transmit_empty(uart_dev))
+        ;
+
+    UART_DAT(uart_dev->base) = c;
+
+    return 1;
+}
+
+static int mipssim_uart_getc(struct rt_serial_device *serial)
+{
+    struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+
+    if (LSR_RXRDY & UART_LSR(uart_dev->base))
+    {
+        return UART_DAT(uart_dev->base);
+    }
+
+    return -1;
+}
+
+/* UART interrupt handler */
+static void uart_irq_handler(int vector, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+    struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+    unsigned char iir = UART_IIR(uart_dev->base);
+
+    /* Find out interrupt reason */
+    if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
+    {
+        rt_interrupt_enter();
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        rt_interrupt_leave();
+    }
+
+}
+
+static const struct rt_uart_ops mipssim_uart_ops =
+{
+    mipssim_uart_configure,
+    mipssim_uart_control,
+    mipssim_uart_putc,
+    mipssim_uart_getc,
+};
+
+struct rt_uart_ls2k uart_dev0 =
+{
+    (void *)UART0_BASE,
+    4,
+};
+struct rt_serial_device serial;
+
+
+void rt_hw_uart_init(void)
+{
+    struct rt_uart_ls2k *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart = &uart_dev0;
+
+    serial.ops    = &mipssim_uart_ops;
+    serial.config = config;
+
+    rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART");
+
+    /* register UART device */
+    rt_hw_serial_register(&serial,
+                          "uart",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+}
+/*@}*/
diff --git a/bsp/ls2kdev/drivers/drv_uart.h b/bsp/ls2kdev/drivers/drv_uart.h
new file mode 100644
index 0000000000..95c69a0442
--- /dev/null
+++ b/bsp/ls2kdev/drivers/drv_uart.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-05     bigmagic     Initial version
+ */
+
+#ifndef _DRV_UART_H__
+#define _DRV_UART_H__
+
+#include "ls2k1000.h"
+#include <rthw.h>
+
+/* UART registers */
+#define UART_DAT(base)		HWREG8(base + 0x00)
+#define UART_IER(base)		HWREG8(base + 0x01)
+#define UART_IIR(base)		HWREG8(base + 0x02)
+#define UART_FCR(base)		HWREG8(base + 0x02)
+#define UART_LCR(base)		HWREG8(base + 0x03)
+#define UART_MCR(base)		HWREG8(base + 0x04)
+#define UART_LSR(base)		HWREG8(base + 0x05)
+#define UART_MSR(base)		HWREG8(base + 0x06)
+
+#define UART_LSB(base)		HWREG8(base + 0x00)
+#define UART_MSB(base)		HWREG8(base + 0x01)
+
+/* interrupt enable register */
+#define	IER_IRxE	0x1
+#define	IER_ITxE	0x2
+#define	IER_ILE	    0x4
+#define	IER_IME	    0x8
+
+/* interrupt identification register */
+#define	IIR_IMASK	0xf	/* mask */
+#define	IIR_RXTOUT	0xc	/* receive timeout */
+#define	IIR_RLS		0x6	/* receive line status */
+#define	IIR_RXRDY	0x4	/* receive ready */
+#define	IIR_TXRDY	0x2	/* transmit ready */
+#define	IIR_NOPEND	0x1	/* nothing */
+#define	IIR_MLSC	0x0	/* modem status */
+#define	IIR_FIFO_MASK	0xc0	/* set if FIFOs are enabled */
+
+/* fifo control register */
+#define	FIFO_ENABLE	    0x01	/* enable fifo */
+#define	FIFO_RCV_RST	0x02	/* reset receive fifo */
+#define	FIFO_XMT_RST	0x04	/* reset transmit fifo */
+#define	FIFO_DMA_MODE	0x08	/* enable dma mode */
+#define	FIFO_TRIGGER_1	0x00	/* trigger at 1 char */
+#define	FIFO_TRIGGER_4	0x40	/* trigger at 4 chars */
+#define	FIFO_TRIGGER_8	0x80	/* trigger at 8 chars */
+#define	FIFO_TRIGGER_14	0xc0	/* trigger at 14 chars */
+
+// 线路控制寄存器
+/* character format control register */
+#define	CFCR_DLAB	0x80	/* divisor latch */
+#define	CFCR_SBREAK	0x40	/* send break */
+#define	CFCR_PZERO	0x30	/* zero parity */
+#define	CFCR_PONE	0x20	/* one parity */
+#define	CFCR_PEVEN	0x10	/* even parity */
+#define	CFCR_PODD	0x00	/* odd parity */
+#define	CFCR_PENAB	0x08	/* parity enable */
+#define	CFCR_STOPB	0x04	/* 2 stop bits */
+#define	CFCR_8BITS	0x03	/* 8 data bits */
+#define	CFCR_7BITS	0x02	/* 7 data bits */
+#define	CFCR_6BITS	0x01	/* 6 data bits */
+#define	CFCR_5BITS	0x00	/* 5 data bits */
+
+/* modem control register */
+#define	MCR_LOOPBACK	0x10	/* loopback */
+#define	MCR_IENABLE	0x08	/* output 2 = int enable */
+#define	MCR_DRS		0x04	/* output 1 = xxx */
+#define	MCR_RTS		0x02	/* enable RTS */
+#define	MCR_DTR		0x01	/* enable DTR */
+
+/* line status register */
+#define	LSR_RCV_FIFO	0x80	/* error in receive fifo */
+#define	LSR_TSRE	0x40	/* transmitter empty */
+#define	LSR_TXRDY	0x20	/* transmitter ready */
+#define	LSR_BI		0x10	/* break detected */
+#define	LSR_FE		0x08	/* framing error */
+#define	LSR_PE		0x04	/* parity error */
+#define	LSR_OE		0x02	/* overrun error */
+#define	LSR_RXRDY	0x01	/* receiver ready */
+#define	LSR_RCV_MASK	0x1f
+
+
+/* UART interrupt enable register value */
+#define UARTIER_IME		(1 << 3)
+#define UARTIER_ILE		(1 << 2)
+#define UARTIER_ITXE	(1 << 1)
+#define UARTIER_IRXE	(1 << 0)
+
+/* UART line control register value */
+#define UARTLCR_DLAB	(1 << 7)
+#define UARTLCR_BCB		(1 << 6)
+#define UARTLCR_SPB		(1 << 5)
+#define UARTLCR_EPS		(1 << 4)
+#define UARTLCR_PE		(1 << 3)
+#define UARTLCR_SB		(1 << 2)
+
+/* UART line status register value */
+#define UARTLSR_ERROR	(1 << 7)
+#define UARTLSR_TE		(1 << 6)
+#define UARTLSR_TFE		(1 << 5)
+#define UARTLSR_BI		(1 << 4)
+#define UARTLSR_FE		(1 << 3)
+#define UARTLSR_PE		(1 << 2)
+#define UARTLSR_OE		(1 << 1)
+#define UARTLSR_DR		(1 << 0)
+
+#endif
diff --git a/bsp/ls2kdev/drivers/interrupt.c b/bsp/ls2kdev/drivers/interrupt.c
new file mode 100644
index 0000000000..6473e5aa94
--- /dev/null
+++ b/bsp/ls2kdev/drivers/interrupt.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic     Initial version
+ */
+
+/**
+ * @addtogroup ls2k
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <exception.h>
+
+#define MAX_INTR 32
+
+static struct rt_irq_desc irq_handle_table[MAX_INTR];
+
+static void rt_hw_interrupt_handler(int vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_uint32_t idx;
+    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
+    for (idx = 0; idx < MAX_INTR; idx ++)
+    {
+        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
+    }
+}
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                         void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector >= 0 && vector < MAX_INTR)
+    {
+        old_handler = irq_handle_table[vector].handler;
+
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+        irq_handle_table[vector].handler = handler;
+        irq_handle_table[vector].param = param;
+    }
+
+    return old_handler;
+}
+
+void rt_hw_timer_handler(void);
+
+void rt_do_mips_cpu_irq(rt_uint32_t ip)
+{
+    void *param;
+    rt_isr_handler_t irq_func;
+
+    if (ip == 7) {
+        rt_hw_timer_handler();
+    } else {
+        irq_func = irq_handle_table[ip].handler;
+                param = irq_handle_table[ip].param;
+
+                /* do interrupt */
+                irq_func(ip, param);
+    }
+}
+
+void rt_hw_interrupt_umask(int irq)
+{
+    mips_unmask_cpu_irq(irq);
+}
+
+void rt_hw_interrupt_mask(int irq)
+{
+    mips_mask_cpu_irq(irq);
+}
+/*@}*/
diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h
new file mode 100644
index 0000000000..8c2d84bfaa
--- /dev/null
+++ b/bsp/ls2kdev/drivers/ls2k1000.h
@@ -0,0 +1,13 @@
+#ifndef _LS2K1000_H__
+#define _LS2K1000_H__
+
+#include <mips.h>
+
+#define UART0_BASE_ADDR 0xbfe00000
+#define UART0_OFF   0x0
+#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
+
+void rt_hw_timer_handler(void);
+void rt_hw_uart_init(void);
+
+#endif
\ No newline at end of file
diff --git a/bsp/ls2kdev/mipssim_ram.lds b/bsp/ls2kdev/mipssim_ram.lds
new file mode 100644
index 0000000000..70385101c1
--- /dev/null
+++ b/bsp/ls2kdev/mipssim_ram.lds
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic  Initial version
+ */
+
+OUTPUT_ARCH(mips)
+GROUP(-lgcc -lc)
+
+ENTRY(_start)
+SECTIONS
+{
+    . = 0x80200000 ;
+    .text :
+    {
+        __ebase_entry = .;
+        KEEP(*(.exc_vectors))
+        __ebase_end = .;
+        start = .;
+        *(.start);
+            . = ALIGN(4);	 
+            *(.text)
+            *(.text.*)
+            *(.rodata)
+            *(.rodata.*)
+            *(.rodata1)
+            *(.rodata1.*)
+
+
+            /* section information for finsh shell */
+            . = ALIGN(4);
+            __fsymtab_start = .;
+            KEEP(*(FSymTab))
+            __fsymtab_end = .;
+            . = ALIGN(4);
+            __vsymtab_start = .;
+            KEEP(*(VSymTab))
+            __vsymtab_end = .;
+            . = ALIGN(4);
+
+            . = ALIGN(4);
+            __rt_init_start = .;
+            KEEP(*(SORT(.rti_fn*)))
+            __rt_init_end = .;
+            . = ALIGN(4);
+
+            . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+        . = ALIGN(4);
+    }
+    
+    .eh_frame_hdr : 
+    { 
+         *(.eh_frame_hdr) 
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(4);
+    .data : 
+    {
+         *(.data)
+         *(.data.*)
+        
+         *(.data1)
+         *(.data1.*)
+
+         . = ALIGN(8);
+         _gp = ABSOLUTE(.);     /* Base of small data */
+         
+         *(.sdata)
+         *(.sdata.*)
+    }
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _system_stack_start = .;
+        . = . + 0x1000;
+        _system_stack = .;
+    }
+
+    .sbss : 
+    {
+        __bss_start = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.dynsbss)
+        *(.scommon)
+    }
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+        __bss_end = .;
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/ls2kdev/rtconfig.h b/bsp/ls2kdev/rtconfig.h
new file mode 100644
index 0000000000..f53fcc66f4
--- /dev/null
+++ b/bsp/ls2kdev/rtconfig.h
@@ -0,0 +1,168 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 2048
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40003
+#define ARCH_MIPS64
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread MIPS CPU */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Privated Packages of RealThread */
+
+
+/* Network Utilities */
+
+#define SOC_LS2K1000
+
+#endif
diff --git a/bsp/ls2kdev/rtconfig.py b/bsp/ls2kdev/rtconfig.py
new file mode 100644
index 0000000000..f3e3786525
--- /dev/null
+++ b/bsp/ls2kdev/rtconfig.py
@@ -0,0 +1,60 @@
+import os
+# CPU options
+ARCH='mips'
+CPU ='gs264'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = '../..'
+
+# toolchains options
+CROSS_TOOL  = 'gcc'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM    = 'gcc'
+	EXEC_PATH   = "/opt/mips-2015.05-19-mips-sde-elf-i686-pc-linux-gnu/mips-2015.05/bin/"
+#	EXEC_PATH   = r'D:\mgc\embedded\codebench\bin'
+else:
+    print('================ERROR===========================')
+    print('Not support %s yet!' % CROSS_TOOL)
+    print('=================================================')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD       = 'debug'
+
+PREFIX = 'mips-sde-elf-'
+CC = PREFIX + 'gcc'
+AS = PREFIX + 'gcc'
+AR = PREFIX + 'ar'
+LINK = PREFIX + 'gcc'
+TARGET_EXT = 'elf'
+SIZE = PREFIX + 'size'
+OBJDUMP = PREFIX + 'objdump'
+OBJCPY = PREFIX + 'objcopy'
+READELF = PREFIX + 'readelf'
+
+DEVICE = ' -march=mips64r2 -mabi=64 -msoft-float'
+CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
+AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
+LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T mipssim_ram.lds'
+CXXFLAGS = CFLAGS
+
+CPATH = ''
+LPATH = ''
+
+if BUILD == 'debug':
+    CFLAGS += ' -O0 -gdwarf-2'
+    AFLAGS += ' -gdwarf-2'
+else:
+    CFLAGS += ' -O2'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+READELF_ACTION = READELF + ' -a $TARGET > rtt.map\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/libcpu/Kconfig b/libcpu/Kconfig
index 3c8c73636d..95d3dd5228 100644
--- a/libcpu/Kconfig
+++ b/libcpu/Kconfig
@@ -77,6 +77,9 @@ config ARCH_ARM_CORTEX_A9
 config ARCH_MIPS
     bool
 
+config ARCH_MIPS64
+    bool
+
 config ARCH_MIPS_XBURST
     bool
     select ARCH_MIPS
diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h
index ec451650d2..987a1fb2b6 100644
--- a/libcpu/mips/common/asm.h
+++ b/libcpu/mips/common/asm.h
@@ -14,6 +14,7 @@
 #ifndef __ASM_H__
 #define __ASM_H__
 
+#include <rtconfig.h>
 /*
  * LEAF - declare leaf routine
  */
@@ -117,7 +118,94 @@ symbol		=	value
 /*
  * Macros to handle different pointer/register sizes for 32/64-bit code
  */
+#if defined SOC_LS2K1000
+/*
+ * Size of a register
+ */
+#define SZREG	8
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#define REG_S		sd
+#define REG_L		ld
+#define REG_SUBU	dsubu
+#define REG_ADDU	daddu
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#define INT_ADD		dadd
+#define INT_ADDU	daddu
+#define INT_ADDI	daddi
+#define INT_ADDIU	daddiu
+#define INT_SUB		dsub
+#define INT_SUBU	dsubu
+#define INT_L		ld
+#define INT_S		sd
+#define INT_SLL		dsll
+#define INT_SLLV	dsllv
+#define INT_SRL		dsrl
+#define INT_SRLV	dsrlv
+#define INT_SRA		dsra
+#define INT_SRAV	dsrav
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#define LONG_ADD	dadd
+#define LONG_ADDU	daddu
+#define LONG_ADDI	daddi
+#define LONG_ADDIU	daddiu
+#define LONG_SUB	dsub
+#define LONG_SUBU	dsubu
+#define LONG_L		ld
+#define LONG_S		sd
+#define LONG_SP		sdp
+#define LONG_SLL	dsll
+#define LONG_SLLV	dsllv
+#define LONG_SRL	dsrl
+#define LONG_SRLV	dsrlv
+#define LONG_SRA	dsra
+#define LONG_SRAV	dsrav
+
+#define LONG		.dword
+#define LONGSIZE	8
+#define LONGMASK	7
+#define LONGLOG		3
 
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#define PTR_ADD		dadd
+#define PTR_ADDU	daddu
+#define PTR_ADDI	daddi
+#define PTR_ADDIU	daddiu
+#define PTR_SUB		dsub
+#define PTR_SUBU	dsubu
+#define PTR_L		ld
+#define PTR_S		sd
+#define PTR_LA		dla
+#define PTR_LI		dli
+#define PTR_SLL		dsll
+#define PTR_SLLV	dsllv
+#define PTR_SRL		dsrl
+#define PTR_SRLV	dsrlv
+#define PTR_SRA		dsra
+#define PTR_SRAV	dsrav
+
+#define PTR_SCALESHIFT	3
+
+#define PTR		.dword
+#define PTRSIZE		8
+#define PTRLOG		3
+
+#define MFC0		dmfc0
+#define MTC0		dmtc0
+
+#else
 /*
  * Size of a register
  */
@@ -211,6 +299,7 @@ symbol		=	value
 #define MFC0		mfc0
 #define MTC0		mtc0
 
+#endif
 
 #define SSNOP		sll zero, zero, 1
 
diff --git a/libcpu/mips/common/entry_gcc.S b/libcpu/mips/common/entry_gcc.S
index b6f758e273..757774cfd9 100644
--- a/libcpu/mips/common/entry_gcc.S
+++ b/libcpu/mips/common/entry_gcc.S
@@ -13,6 +13,9 @@
 #endif
 
 #include <mips.h>
+#include <rtconfig.h>
+
+#include "asm.h"
 #include <rtconfig.h>
 
     .section ".start", "ax"
@@ -25,27 +28,33 @@ _rtthread_entry:
     .globl  _start
 _start:
 #endif
-    la	ra, _rtthread_entry
+    PTR_LA	ra, _rtthread_entry
 
     /* disable interrupt */
     mtc0	zero, CP0_CAUSE
     mtc0	zero, CP0_STATUS	# Set CPU to disable interrupt.
     ehb
+
+#ifdef ARCH_MIPS64
+    dli		t0, ST0_KX
+    MTC0	t0, CP0_STATUS
+#endif
+
     /* setup stack pointer */
-    la	sp, _system_stack
-    la	gp, _gp
+    PTR_LA	sp, _system_stack
+    PTR_LA	gp, _gp
 
     bal	rt_cpu_early_init
     nop
 
     /* clear bss */
-    la	t0, __bss_start
-    la	t1, __bss_end
+    PTR_LA	t0, __bss_start
+    PTR_LA	t1, __bss_end
+
 _clr_bss_loop:
     sw	zero, 0(t0)
-    bne	t0, t1, _clr_bss_loop
-    addiu	t0, t0, 4
-
+    bne	t1, t0, _clr_bss_loop
+    addu	t0, 4
     /* jump to RT-Thread RTOS */
     jal	rtthread_startup
     nop
diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h
index 10fc2d6593..b057e1e917 100644
--- a/libcpu/mips/common/mips_addrspace.h
+++ b/libcpu/mips/common/mips_addrspace.h
@@ -24,7 +24,7 @@
 #define _ATYPE_		__PTRDIFF_TYPE__
 #define _ATYPE32_	int
 #define _ATYPE64_	__s64
-#ifdef CONFIG_64BIT
+#ifdef ARCH_MIPS64
 #define _CONST64_(x)	x ## L
 #else
 #define _CONST64_(x)	x ## LL
@@ -54,7 +54,7 @@
 #define XPHYSADDR(a)		((_ACAST64_(a)) &			\
 				 _CONST64_(0x000000ffffffffff))
 
-#ifdef CONFIG_64BIT
+#ifdef ARCH_MIPS64
 
 /*
  * Memory segments (64bit kernel mode addresses)
@@ -90,6 +90,14 @@
 #define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2BASE)
 #define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3BASE)
 
+#define CKUSEG			0x00000000
+#define CKSEG0			0x80000000
+#define CKSEG1			0xa0000000
+#define CKSEG2			0xc0000000
+#define CKSEG3			0xe0000000
+
+#endif
+
 /*
  * Memory segments (32bit kernel mode addresses)
  * These are the traditional names used in the 32-bit universe.
@@ -100,13 +108,7 @@
 #define KSEG2BASE			0xc0000000
 #define KSEG3BASE			0xe0000000
 
-#define CKUSEG			0x00000000
-#define CKSEG0			0x80000000
-#define CKSEG1			0xa0000000
-#define CKSEG2			0xc0000000
-#define CKSEG3			0xe0000000
 
-#endif
 
 /*
  * Cache modes for XKPHYS address conversion macros
diff --git a/libcpu/mips/gs264/SConscript b/libcpu/mips/gs264/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/gs264/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/gs264/cpuinit_gcc.S b/libcpu/mips/gs264/cpuinit_gcc.S
new file mode 100644
index 0000000000..bd84663350
--- /dev/null
+++ b/libcpu/mips/gs264/cpuinit_gcc.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic     Initial version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+
+    .section ".text", "ax"
+    .set noreorder
+
+    .globl  rt_cpu_early_init
+rt_cpu_early_init:
+     mfc0	t0, CP0_CONFIG
+     ori	t0, 3
+     mtc0	t0, CP0_CONFIG
+     ehb
+     jr	ra
\ No newline at end of file
-- 
cgit v1.3.1


From 990f731b776055390db854f9cc980799e39247e8 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Mon, 6 Apr 2020 15:46:28 +0800
Subject: fix mips64 some bug

---
 bsp/ls2kdev/.config                 |  22 +-----
 bsp/ls2kdev/drivers/board.c         |   7 +-
 bsp/ls2kdev/drivers/board.h         |   2 +-
 bsp/ls2kdev/ls2k_ram.lds            | 141 ++++++++++++++++++++++++++++++++++++
 bsp/ls2kdev/mipssim_ram.lds         | 141 ------------------------------------
 bsp/ls2kdev/rtconfig.h              |  11 +--
 bsp/ls2kdev/rtconfig.py             |   8 +-
 libcpu/mips/common/asm.h            |   4 +
 libcpu/mips/common/context_gcc.S    |  24 +++---
 libcpu/mips/common/entry_gcc.S      |   4 +-
 libcpu/mips/common/exception.c      |  17 +++--
 libcpu/mips/common/exception_gcc.S  |  13 +++-
 libcpu/mips/common/mips_addrspace.h |   9 ++-
 libcpu/mips/common/mips_regs.h      |  46 +++++++++++-
 libcpu/mips/common/ptrace.h         |  25 +++++--
 libcpu/mips/common/stack.c          |  21 +++---
 libcpu/mips/common/stackframe.h     |   4 +-
 17 files changed, 278 insertions(+), 221 deletions(-)
 create mode 100644 bsp/ls2kdev/ls2k_ram.lds
 delete mode 100644 bsp/ls2kdev/mipssim_ram.lds

(limited to 'libcpu')

diff --git a/bsp/ls2kdev/.config b/bsp/ls2kdev/.config
index 00b8746e4f..20cf03b625 100644
--- a/bsp/ls2kdev/.config
+++ b/bsp/ls2kdev/.config
@@ -21,11 +21,12 @@ CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=2048
 CONFIG_RT_USING_TIMER_SOFT=y
-CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_PRIO=20
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
 CONFIG_RT_DEBUG=y
 # CONFIG_RT_DEBUG_COLOR is not set
-# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+CONFIG_RT_DEBUG_INIT_CONFIG=y
+CONFIG_RT_DEBUG_INIT=1
 # CONFIG_RT_DEBUG_THREAD_CONFIG is not set
 # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
 # CONFIG_RT_DEBUG_IPC_CONFIG is not set
@@ -106,18 +107,7 @@ CONFIG_FINSH_ARG_MAX=10
 #
 # Device virtual file system
 #
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS is not set
 
 #
 # Device Drivers
@@ -161,10 +151,6 @@ CONFIG_RT_USING_PIN=y
 #
 CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_PTHREADS is not set
-CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
 # CONFIG_RT_USING_MODULE is not set
 
 #
diff --git a/bsp/ls2kdev/drivers/board.c b/bsp/ls2kdev/drivers/board.c
index 3edbae9ee7..20b7a84516 100644
--- a/bsp/ls2kdev/drivers/board.c
+++ b/bsp/ls2kdev/drivers/board.c
@@ -70,10 +70,10 @@ void rt_hw_board_init(void)
     /* init hardware interrupt */
     rt_hw_interrupt_init();
 
-    #ifdef RT_USING_FPU
+#ifdef RT_USING_FPU
     /* init hardware fpu */
     rt_hw_fpu_init();
-    #endif
+#endif
 
 #ifdef RT_USING_SERIAL
     /* init hardware UART device */
@@ -88,8 +88,7 @@ void rt_hw_board_init(void)
 
     /* init operating system timer */
     rt_hw_timer_init();
-
-
+    
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
diff --git a/bsp/ls2kdev/drivers/board.h b/bsp/ls2kdev/drivers/board.h
index df4b40fb78..6e2f85ec74 100644
--- a/bsp/ls2kdev/drivers/board.h
+++ b/bsp/ls2kdev/drivers/board.h
@@ -16,7 +16,7 @@
 extern unsigned char __bss_end;
 
 #define CPU_HZ	(100 * 1000 * 1000)
-#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_BEGIN    KSEG1BASE//(void*)&__bss_end
 #define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
 
 void rt_hw_board_init(void);
diff --git a/bsp/ls2kdev/ls2k_ram.lds b/bsp/ls2kdev/ls2k_ram.lds
new file mode 100644
index 0000000000..8bec1e855b
--- /dev/null
+++ b/bsp/ls2kdev/ls2k_ram.lds
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic  Initial version
+ */
+
+OUTPUT_ARCH(mips)
+GROUP(-lgcc -lc)
+
+ENTRY(_start)
+SECTIONS
+{
+    . = 0xffffffff82000000 ;
+    .text :
+    {
+        __ebase_entry = .;
+        KEEP(*(.exc_vectors))
+        __ebase_end = .;
+        start = .;
+        *(.start);
+            . = ALIGN(4);	 
+            *(.text)
+            *(.text.*)
+            *(.rodata)
+            *(.rodata.*)
+            *(.rodata1)
+            *(.rodata1.*)
+
+
+            /* section information for finsh shell */
+            . = ALIGN(4);
+            __fsymtab_start = .;
+            KEEP(*(FSymTab))
+            __fsymtab_end = .;
+            . = ALIGN(4);
+            __vsymtab_start = .;
+            KEEP(*(VSymTab))
+            __vsymtab_end = .;
+            . = ALIGN(4);
+
+            . = ALIGN(4);
+            __rt_init_start = .;
+            KEEP(*(SORT(.rti_fn*)))
+            __rt_init_end = .;
+            . = ALIGN(4);
+
+            . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+        . = ALIGN(4);
+    }
+    
+    .eh_frame_hdr : 
+    { 
+         *(.eh_frame_hdr) 
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(4);
+    .data : 
+    {
+         *(.data)
+         *(.data.*)
+        
+         *(.data1)
+         *(.data1.*)
+
+         . = ALIGN(8);
+         _gp = ABSOLUTE(.);     /* Base of small data */
+         
+         *(.sdata)
+         *(.sdata.*)
+    }
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _system_stack_start = .;
+        . = . + 0x1000;
+        _system_stack = .;
+    }
+
+    .sbss : 
+    {
+        __bss_start = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.dynsbss)
+        *(.scommon)
+    }
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+        __bss_end = .;
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/ls2kdev/mipssim_ram.lds b/bsp/ls2kdev/mipssim_ram.lds
deleted file mode 100644
index 70385101c1..0000000000
--- a/bsp/ls2kdev/mipssim_ram.lds
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-04-05     bigmagic  Initial version
- */
-
-OUTPUT_ARCH(mips)
-GROUP(-lgcc -lc)
-
-ENTRY(_start)
-SECTIONS
-{
-    . = 0x80200000 ;
-    .text :
-    {
-        __ebase_entry = .;
-        KEEP(*(.exc_vectors))
-        __ebase_end = .;
-        start = .;
-        *(.start);
-            . = ALIGN(4);	 
-            *(.text)
-            *(.text.*)
-            *(.rodata)
-            *(.rodata.*)
-            *(.rodata1)
-            *(.rodata1.*)
-
-
-            /* section information for finsh shell */
-            . = ALIGN(4);
-            __fsymtab_start = .;
-            KEEP(*(FSymTab))
-            __fsymtab_end = .;
-            . = ALIGN(4);
-            __vsymtab_start = .;
-            KEEP(*(VSymTab))
-            __vsymtab_end = .;
-            . = ALIGN(4);
-
-            . = ALIGN(4);
-            __rt_init_start = .;
-            KEEP(*(SORT(.rti_fn*)))
-            __rt_init_end = .;
-            . = ALIGN(4);
-
-            . = ALIGN(4);
-        __rt_utest_tc_tab_start = .;
-        KEEP(*(UtestTcTab))
-        __rt_utest_tc_tab_end = .;
-        . = ALIGN(4);
-    }
-    
-    .eh_frame_hdr : 
-    { 
-         *(.eh_frame_hdr) 
-         *(.eh_frame_entry)
-    }
-    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
-
-    . = ALIGN(4);
-    .data : 
-    {
-         *(.data)
-         *(.data.*)
-        
-         *(.data1)
-         *(.data1.*)
-
-         . = ALIGN(8);
-         _gp = ABSOLUTE(.);     /* Base of small data */
-         
-         *(.sdata)
-         *(.sdata.*)
-    }
-
-    .stack :
-    {
-        . = ALIGN(8);
-        _system_stack_start = .;
-        . = . + 0x1000;
-        _system_stack = .;
-    }
-
-    .sbss : 
-    {
-        __bss_start = .;
-        *(.sbss)
-        *(.sbss.*)
-        *(.dynsbss)
-        *(.scommon)
-    }
-
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.dynbss)
-        *(COMMON)
-        __bss_end = .;
-    }
-    _end = .;
-
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-     * Symbols in the DWARF debugging sections are relative to the beginning
-     * of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-}
diff --git a/bsp/ls2kdev/rtconfig.h b/bsp/ls2kdev/rtconfig.h
index f53fcc66f4..80f068c5c0 100644
--- a/bsp/ls2kdev/rtconfig.h
+++ b/bsp/ls2kdev/rtconfig.h
@@ -17,9 +17,11 @@
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 2048
 #define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_PRIO 20
 #define RT_TIMER_THREAD_STACK_SIZE 2048
 #define RT_DEBUG
+#define RT_DEBUG_INIT_CONFIG
+#define RT_DEBUG_INIT 1
 
 /* Inter-Thread communication */
 
@@ -71,12 +73,6 @@
 
 /* Device virtual file system */
 
-#define RT_USING_DFS
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
-#define DFS_FD_MAX 16
-#define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
 
@@ -93,7 +89,6 @@
 /* POSIX layer and C standard library */
 
 #define RT_USING_LIBC
-#define RT_USING_POSIX
 
 /* Network */
 
diff --git a/bsp/ls2kdev/rtconfig.py b/bsp/ls2kdev/rtconfig.py
index f3e3786525..c8490a382f 100644
--- a/bsp/ls2kdev/rtconfig.py
+++ b/bsp/ls2kdev/rtconfig.py
@@ -40,10 +40,10 @@ OBJDUMP = PREFIX + 'objdump'
 OBJCPY = PREFIX + 'objcopy'
 READELF = PREFIX + 'readelf'
 
-DEVICE = ' -march=mips64r2 -mabi=64 -msoft-float'
-CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
-AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
-LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T mipssim_ram.lds'
+DEVICE = ' -march=mips64r2 -mabi=64 -msoft-float -EL'
+CFLAGS = DEVICE + '  -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
+AFLAGS = ' -c' + DEVICE + '  -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
+LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls2k_ram.lds'
 CXXFLAGS = CFLAGS
 
 CPATH = ''
diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h
index 987a1fb2b6..a16db1868e 100644
--- a/libcpu/mips/common/asm.h
+++ b/libcpu/mips/common/asm.h
@@ -261,7 +261,11 @@ symbol		=	value
 #define LONG_SRAV	srav
 
 #define LONG		.word
+#ifdef ARCH_MIPS64
+#define LONGSIZE	8
+#else
 #define LONGSIZE	4
+#endif
 #define LONGMASK	3
 #define LONGLOG		2
 
diff --git a/libcpu/mips/common/context_gcc.S b/libcpu/mips/common/context_gcc.S
index 251fc81c3c..cdcdede39a 100644
--- a/libcpu/mips/common/context_gcc.S
+++ b/libcpu/mips/common/context_gcc.S
@@ -25,11 +25,11 @@
  */
     .globl rt_hw_context_switch
 rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
+    MTC0    ra, CP0_EPC
     SAVE_ALL
 
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
+    REG_S      sp, 0(a0)       /* store sp in preempted tasks TCB */
+    REG_L      sp, 0(a1)       /* get new task stack pointer */
 
     RESTORE_ALL_AND_RET
 
@@ -39,7 +39,7 @@ rt_hw_context_switch:
  */
     .globl rt_hw_context_switch_to
 rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
+    REG_L      sp, 0(a0)       /* get new task stack pointer */
     RESTORE_ALL_AND_RET
 
 /*
@@ -50,17 +50,17 @@ rt_hw_context_switch_to:
     .globl rt_interrupt_to_thread
     .globl rt_hw_context_switch_interrupt
 rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
+    PTR_LA      t0, rt_thread_switch_interrupt_flag
+    REG_L       t1, 0(t0)
     nop
     bnez    t1, _reswitch
     nop
     li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
     sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
+    PTR_LA      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
     sw      a0, 0(t0)
 _reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
+    PTR_LA      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
     sw      a1, 0(t0)
     jr      ra
     nop
@@ -78,7 +78,7 @@ mips_irq_handle:
     /* let k0 keep the current context sp */
     move    k0, sp
     /* switch to kernel stack */
-    la      sp, _system_stack
+    PTR_LA  sp, _system_stack
 
     jal     rt_interrupt_enter
     nop
@@ -96,7 +96,7 @@ mips_irq_handle:
     * if rt_thread_switch_interrupt_flag set, jump to
     * rt_hw_context_switch_interrupt_do and do not return
     */
-    la      k0, rt_thread_switch_interrupt_flag
+    PTR_LA  k0, rt_thread_switch_interrupt_flag
     lw      k1, 0(k0)
     beqz    k1, spurious_interrupt
     nop
@@ -106,12 +106,12 @@ mips_irq_handle:
     /*
     * switch to the new thread
     */
-    la      k0, rt_interrupt_from_thread
+    PTR_LA  k0, rt_interrupt_from_thread
     lw      k1, 0(k0)
     nop
     sw      sp, 0(k1)                       /* store sp in preempted task TCB */
 
-    la      k0, rt_interrupt_to_thread
+    PTR_LA  k0, rt_interrupt_to_thread
     lw      k1, 0(k0)
     nop
     lw      sp, 0(k1)                       /* get new task stack pointer */
diff --git a/libcpu/mips/common/entry_gcc.S b/libcpu/mips/common/entry_gcc.S
index 757774cfd9..d1a0704809 100644
--- a/libcpu/mips/common/entry_gcc.S
+++ b/libcpu/mips/common/entry_gcc.S
@@ -31,8 +31,8 @@ _start:
     PTR_LA	ra, _rtthread_entry
 
     /* disable interrupt */
-    mtc0	zero, CP0_CAUSE
-    mtc0	zero, CP0_STATUS	# Set CPU to disable interrupt.
+    MTC0	zero, CP0_CAUSE
+    MTC0	zero, CP0_STATUS	# Set CPU to disable interrupt.
     ehb
 
 #ifdef ARCH_MIPS64
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index de67e98199..11192955cf 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -19,10 +19,10 @@
 
 /*@{*/
 
-extern rt_uint32_t __ebase_entry;
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
+extern rt_ubase_t __ebase_entry;
+rt_ubase_t rt_interrupt_from_thread;
+rt_ubase_t rt_interrupt_to_thread;
+rt_ubase_t rt_thread_switch_interrupt_flag;
 
 rt_base_t rt_hw_interrupt_disable(void)
 {
@@ -101,7 +101,10 @@ static void install_default_exception_handler(void)
 
 int rt_hw_exception_init(void)
 {
-    rt_uint32_t ebase = (rt_uint32_t)&__ebase_entry;
+    rt_ubase_t ebase = (rt_ubase_t)&__ebase_entry;
+#ifdef ARCH_MIPS64
+    ebase |= 0xffffffff00000000;
+#endif
     write_c0_ebase(ebase);
     clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL);
     clear_c0_status(ST0_IM | ST0_IE);
@@ -114,12 +117,12 @@ int rt_hw_exception_init(void)
 
 void rt_general_exc_dispatch(struct pt_regs *regs)
 {
-    rt_uint32_t cause, exccode;
+    rt_ubase_t cause, exccode;
 
     exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 
     if (exccode == 0) {
-        rt_uint32_t status, pending;
+        rt_ubase_t status, pending;
         status = read_c0_status();
         pending = (cause & CAUSEF_IP) & (status & ST0_IM);
         if (pending & CAUSEF_IP0)
diff --git a/libcpu/mips/common/exception_gcc.S b/libcpu/mips/common/exception_gcc.S
index 176b60e594..9664438ac1 100644
--- a/libcpu/mips/common/exception_gcc.S
+++ b/libcpu/mips/common/exception_gcc.S
@@ -7,6 +7,11 @@
  * Date           Author       Notes
  * 2019-12-04     Jiaxun Yang  Initial version
  */
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
 
     .section ".exc_vectors", "ax"
     .extern tlb_refill_handler
@@ -45,15 +50,15 @@ irq_exception:
     /* general exception handler */
 _general_exception_handler:
     .set	noreorder
-    la	$k0, mips_irq_handle
-    jr	$k0
+    PTR_LA	k0, mips_irq_handle
+    jr	k0
     nop
     .set	reorder
 
     /* interrupt handler */
 _irq_handler:
     .set	noreorder
-    la	$k0, mips_irq_handle
-    jr	$k0
+    PTR_LA	k0, mips_irq_handle
+    jr	k0
     nop
     .set	reorder
diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h
index b057e1e917..f3bb60662e 100644
--- a/libcpu/mips/common/mips_addrspace.h
+++ b/libcpu/mips/common/mips_addrspace.h
@@ -75,6 +75,12 @@
 #define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
 #define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
 
+#define KUSEGBASE			0xffffffff00000000
+#define KSEG0BASE			0xffffffff80000000
+#define KSEG1BASE			0xffffffffa0000000
+#define KSEG2BASE			0xffffffffc0000000
+#define KSEG3BASE			0xffffffffe0000000
+
 #else
 
 #define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0BASE)
@@ -96,8 +102,6 @@
 #define CKSEG2			0xc0000000
 #define CKSEG3			0xe0000000
 
-#endif
-
 /*
  * Memory segments (32bit kernel mode addresses)
  * These are the traditional names used in the 32-bit universe.
@@ -108,6 +112,7 @@
 #define KSEG2BASE			0xc0000000
 #define KSEG3BASE			0xe0000000
 
+#endif
 
 
 /*
diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h
index 7e1359fa33..a7db15d2ad 100644
--- a/libcpu/mips/common/mips_regs.h
+++ b/libcpu/mips/common/mips_regs.h
@@ -10,13 +10,14 @@
 
 #ifndef _MIPS_REGS_H_
 #define _MIPS_REGS_H_
-
+#include <rtconfig.h>
 #define REG_A0	4
 #define REG_SP	29
 #define REG_GP	28
 #define REG_FP	30
 #define REG_RA	31
 
+#ifdef ARCH_MIPS64
 #define zero	$0	/* wired zero */
 #define AT	$1	/* assembler temp  - uppercase because of ".set at" */
 #define v0	$2	/* return value */
@@ -56,6 +57,49 @@
 #define s8	$30	/* same like fp! */
 #define ra	$31	/* return address */
 
+#else
+
+#define zero	$0	/* wired zero */
+#define AT	$at	/* assembler temp - uppercase because of ".set at" */
+#define v0	$2	/* return value - caller saved */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define a4	$8	/* arg reg 64 bit; caller saved in 32 bit */
+#define ta0	$8
+#define a5	$9
+#define ta1	$9
+#define a6	$10
+#define ta2	$10
+#define a7	$11
+#define ta3	$11
+#define t0	$12	/* caller saved */
+#define t1	$13
+#define t2	$14
+#define t3	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* caller saved */
+#define t9	$25	/* callee address for PIC/temp */
+#define jp	$25	/* PIC jump register */
+#define k0	$26	/* kernel temporary */
+#define k1	$27
+#define gp	$28	/* global pointer - caller saved for PIC */
+#define sp	$29	/* stack pointer */
+#define fp	$30	/* frame pointer */
+#define s8	$30	/* callee saved */
+#define ra	$31	/* return address */
+
+#endif
+
 #define fv0	$f0	 /* return value */
 #define fv0f	$f1
 #define fv1	$f2
diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h
index cae57cbf4c..c048959053 100644
--- a/libcpu/mips/common/ptrace.h
+++ b/libcpu/mips/common/ptrace.h
@@ -14,6 +14,8 @@
 #include "asm.h"
 #include "mips_regs.h"
 
+#define HI_LO_SIZE  4
+
 #define FP_REG_SIZE 8
 #define NUM_FPU_REGS 16
 
@@ -27,6 +29,7 @@ struct mips_fpu_struct {
 };
 
 struct pt_regs {
+#ifndef ARCH_MIPS64
     /* Only O32 Need This! */
     /* Pad bytes for argument save space on the stack. */
     rt_uint32_t pad0[8];
@@ -41,6 +44,18 @@ struct pt_regs {
     rt_uint32_t cp0_badvaddr;
     rt_uint32_t cp0_cause;
     rt_uint32_t cp0_epc;
+#else
+    /* Saved main processor registers. */
+    unsigned long regs[32];
+
+    /* Saved special registers. */
+    rt_uint32_t cp0_status;
+    rt_uint32_t hi;
+    rt_uint32_t lo;
+    unsigned long cp0_badvaddr;
+    rt_uint32_t cp0_cause;
+    unsigned long cp0_epc;
+#endif
 
 #ifdef RT_USING_FPU
     /* FPU Registers */
@@ -52,7 +67,7 @@ struct pt_regs {
 #endif
 
 /* Note: For call stack o32 ABI has 0x8 shadowsoace Here  */
-#define PT_R0		(0x8 * LONGSIZE)	/* 0 */
+#define PT_R0		(0x0 * LONGSIZE)	/* 0 */
 #define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
 #define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
 #define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
@@ -89,8 +104,8 @@ struct pt_regs {
  * Saved special registers
  */
 #define PT_STATUS	((PT_R31) + LONGSIZE)	/* 32 */
-#define PT_HI		((PT_STATUS) + LONGSIZE)	/* 33 */
-#define PT_LO		((PT_HI) + LONGSIZE)	/* 34 */
+#define PT_HI		((PT_STATUS) + HI_LO_SIZE)	/* 33 */
+#define PT_LO		((PT_HI) + HI_LO_SIZE)	/* 34 */
 #define PT_BADVADDR	((PT_LO) + LONGSIZE)	/* 35 */
 #define PT_CAUSE	((PT_BADVADDR) + LONGSIZE)	/* 36 */
 #define PT_EPC		((PT_CAUSE) + LONGSIZE)	/* 37 */
@@ -115,9 +130,9 @@ struct pt_regs {
 #define PT_FPU_R28              ((PT_FPU_R26) + FP_REG_SIZE)
 #define PT_FPU_R30              ((PT_FPU_R28) + FP_REG_SIZE)
 #define PT_FPU_FCSR31           ((PT_FPU_R30) + FP_REG_SIZE)
-#define PT_FPU_PAD0             ((PT_FPU_FCSR31) + LONGSIZE)
+#define PT_FPU_PAD0             ((PT_FPU_FCSR31) + 4)
 
-#define PT_FPU_END     	        ((PT_FPU_PAD0) + LONGSIZE)
+#define PT_FPU_END     	        ((PT_FPU_PAD0) + 4)
 #define PT_SIZE			PT_FPU_END
 #else
 #define PT_SIZE			PT_REG_END
diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c
index b0e613c7a7..b933b184e7 100644
--- a/libcpu/mips/common/stack.c
+++ b/libcpu/mips/common/stack.c
@@ -16,8 +16,8 @@ register rt_uint32_t $GP __asm__ ("$28");
 
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
 {
-    static rt_uint32_t wSR=0;
-    static rt_uint32_t wGP;
+    static rt_ubase_t wSR=0;
+    static rt_ubase_t wGP;
     rt_uint8_t *stk;
 
     struct pt_regs *pt;
@@ -25,26 +25,27 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
     rt_uint32_t i;
 
     /* Get stack aligned */
-    stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 8);
     stk -= sizeof(struct pt_regs);
     pt =  (struct pt_regs*)stk;
 
+#ifndef ARCH_MIPS64
     for (i = 0; i < 8; ++i)
     {
         pt->pad0[i] = 0xdeadbeef;
     }
-
+#endif
     /* Fill Stack register numbers */
     for (i = 0; i < 32; ++i)
     {
         pt->regs[i] = 0xdeadbeef;
     }
 
-    pt->regs[REG_SP] = (rt_uint32_t)stk;
-    pt->regs[REG_A0] = (rt_uint32_t)parameter;
-    pt->regs[REG_GP] = (rt_uint32_t)$GP;
-    pt->regs[REG_FP] = (rt_uint32_t)0x0;
-    pt->regs[REG_RA] = (rt_uint32_t)texit;
+    pt->regs[REG_SP] = (rt_ubase_t)stk;
+    pt->regs[REG_A0] = (rt_ubase_t)parameter;
+    pt->regs[REG_GP] = (rt_ubase_t)$GP;
+    pt->regs[REG_FP] = (rt_ubase_t)0x0;
+    pt->regs[REG_RA] = (rt_ubase_t)texit;
 
     pt->hi	= 0x0;
     pt->lo	= 0x0;
@@ -53,7 +54,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
     pt->cp0_status |= (ST0_CU1 | ST0_FR);
 #endif
     pt->cp0_cause	= read_c0_cause();
-    pt->cp0_epc	= (rt_uint32_t)tentry;
+    pt->cp0_epc	= (rt_ubase_t)tentry;
     pt->cp0_badvaddr	= 0x0;
 
     return stk;
diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h
index 77d55f6934..b5a038d1f6 100644
--- a/libcpu/mips/common/stackframe.h
+++ b/libcpu/mips/common/stackframe.h
@@ -159,11 +159,11 @@
     .endm
 
     .macro	RESTORE_TEMP
-    LONG_L	$24, PT_LO(sp)
+    lw	$24, PT_LO(sp)
     LONG_L	$8, PT_R8(sp)
     LONG_L	$9, PT_R9(sp)
     mtlo	$24
-    LONG_L	$24, PT_HI(sp)
+    lw	$24, PT_HI(sp)
     LONG_L	$10, PT_R10(sp)
     LONG_L	$11, PT_R11(sp)
     mthi	$24
-- 
cgit v1.3.1


From c024e2e485c813aa1c70e079f61fe50a80d8215c Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Tue, 7 Apr 2020 11:26:30 +0800
Subject: add ls2k bsp config

---
 bsp/ls2kdev/.config             | 9 +++------
 bsp/ls2kdev/applications/main.c | 2 +-
 bsp/ls2kdev/rtconfig.h          | 7 +------
 libcpu/mips/common/exception.c  | 6 +++---
 libcpu/mips/common/stackframe.h | 4 ++--
 5 files changed, 10 insertions(+), 18 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/ls2kdev/.config b/bsp/ls2kdev/.config
index 20cf03b625..d8a97b46b0 100644
--- a/bsp/ls2kdev/.config
+++ b/bsp/ls2kdev/.config
@@ -20,13 +20,10 @@ CONFIG_RT_USING_HOOK=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=2048
-CONFIG_RT_USING_TIMER_SOFT=y
-CONFIG_RT_TIMER_THREAD_PRIO=20
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+# CONFIG_RT_USING_TIMER_SOFT is not set
 CONFIG_RT_DEBUG=y
 # CONFIG_RT_DEBUG_COLOR is not set
-CONFIG_RT_DEBUG_INIT_CONFIG=y
-CONFIG_RT_DEBUG_INIT=1
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
 # CONFIG_RT_DEBUG_THREAD_CONFIG is not set
 # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
 # CONFIG_RT_DEBUG_IPC_CONFIG is not set
@@ -65,7 +62,7 @@ CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
 CONFIG_RT_VER_NUM=0x40003
 # CONFIG_RT_USING_CPU_FFS is not set
diff --git a/bsp/ls2kdev/applications/main.c b/bsp/ls2kdev/applications/main.c
index 54691f0f89..bd975f4825 100644
--- a/bsp/ls2kdev/applications/main.c
+++ b/bsp/ls2kdev/applications/main.c
@@ -12,6 +12,6 @@
 
 int main(int argc, char** argv)
 {   
-    rt_kprintf("ls2k1000:hello rtthread!\n");
+    rt_kprintf("Hi, this is RT-Thread!!\n");
     return 0;
 }
diff --git a/bsp/ls2kdev/rtconfig.h b/bsp/ls2kdev/rtconfig.h
index 80f068c5c0..aaeed71df5 100644
--- a/bsp/ls2kdev/rtconfig.h
+++ b/bsp/ls2kdev/rtconfig.h
@@ -16,12 +16,7 @@
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 2048
-#define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO 20
-#define RT_TIMER_THREAD_STACK_SIZE 2048
 #define RT_DEBUG
-#define RT_DEBUG_INIT_CONFIG
-#define RT_DEBUG_INIT 1
 
 /* Inter-Thread communication */
 
@@ -41,7 +36,7 @@
 
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart"
 #define RT_VER_NUM 0x40003
 #define ARCH_MIPS64
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index 11192955cf..cd7d97e6c0 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -117,14 +117,14 @@ int rt_hw_exception_init(void)
 
 void rt_general_exc_dispatch(struct pt_regs *regs)
 {
-    rt_ubase_t cause, exccode;
+    rt_ubase_t exccode = 0;
 
-    exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 
     if (exccode == 0) {
         rt_ubase_t status, pending;
         status = read_c0_status();
-        pending = (cause & CAUSEF_IP) & (status & ST0_IM);
+
+        pending =  (CAUSEF_IP) & (status & ST0_IM);
         if (pending & CAUSEF_IP0)
             rt_do_mips_cpu_irq(0);
         if (pending & CAUSEF_IP1)
diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h
index b5a038d1f6..258f9a994f 100644
--- a/libcpu/mips/common/stackframe.h
+++ b/libcpu/mips/common/stackframe.h
@@ -60,11 +60,11 @@
     mfhi	v1
     LONG_S	$8, PT_R8(sp)
     LONG_S	$9, PT_R9(sp)
-    LONG_S	v1, PT_HI(sp)
+    sw	v1, PT_HI(sp)
     mflo	v1
     LONG_S	$10, PT_R10(sp)
     LONG_S	$11, PT_R11(sp)
-    LONG_S	v1,  PT_LO(sp)
+    sw	v1,  PT_LO(sp)
     LONG_S	$12, PT_R12(sp)
     LONG_S	$13, PT_R13(sp)
     LONG_S	$14, PT_R14(sp)
-- 
cgit v1.3.1


From 3c5329a9b709e413bbc878e5661fa942060d41fb Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Tue, 7 Apr 2020 14:43:20 +0800
Subject: mips repair constraint

---
 libcpu/mips/common/asm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h
index a16db1868e..6a5353b803 100644
--- a/libcpu/mips/common/asm.h
+++ b/libcpu/mips/common/asm.h
@@ -118,7 +118,7 @@ symbol		=	value
 /*
  * Macros to handle different pointer/register sizes for 32/64-bit code
  */
-#if defined SOC_LS2K1000
+#if defined ARCH_MIPS64
 /*
  * Size of a register
  */
-- 
cgit v1.3.1


From dff04ffdc6e76973eef52d38090231dd2771c8d9 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Tue, 7 Apr 2020 14:49:20 +0800
Subject: fix mips stackframe point

---
 libcpu/mips/common/ptrace.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h
index c048959053..00ce58a085 100644
--- a/libcpu/mips/common/ptrace.h
+++ b/libcpu/mips/common/ptrace.h
@@ -67,7 +67,11 @@ struct pt_regs {
 #endif
 
 /* Note: For call stack o32 ABI has 0x8 shadowsoace Here  */
+#ifdef ARCH_MIPS64
 #define PT_R0		(0x0 * LONGSIZE)	/* 0 */
+#else
+#define PT_R0		(0x8 * LONGSIZE)	/* 0 */
+#endif
 #define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
 #define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
 #define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
-- 
cgit v1.3.1


From c27f13c6c9f2df5ce2fd74652d3388c3f3c5a843 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Tue, 7 Apr 2020 19:01:54 +0800
Subject: [mips]fix a bug

---
 libcpu/mips/common/mips_regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h
index a7db15d2ad..c5dd727e23 100644
--- a/libcpu/mips/common/mips_regs.h
+++ b/libcpu/mips/common/mips_regs.h
@@ -17,7 +17,7 @@
 #define REG_FP	30
 #define REG_RA	31
 
-#ifdef ARCH_MIPS64
+#ifndef ARCH_MIPS64
 #define zero	$0	/* wired zero */
 #define AT	$1	/* assembler temp  - uppercase because of ".set at" */
 #define v0	$2	/* return value */
-- 
cgit v1.3.1


From ee61d78b184040327dbe83f2941932bd15b8e9c5 Mon Sep 17 00:00:00 2001
From: duhuanpeng <548708880@qq.com>
Date: Wed, 25 Mar 2020 23:12:22 +0800
Subject: MIPS: inline routine should be static here

gcc will remove this "unused" routine and cause a linking error.
symbol not found when linking.

Signed-off-by: duhuanpeng <548708880@qq.com>
---
 libcpu/mips/common/mips_fpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h
index d6351f7655..50df3746a5 100644
--- a/libcpu/mips/common/mips_fpu.h
+++ b/libcpu/mips/common/mips_fpu.h
@@ -18,7 +18,7 @@
  * init hardware FPU
  */
 #ifdef RT_USING_FPU
-inline void rt_hw_fpu_init(void)
+rt_inline void rt_hw_fpu_init(void)
 {
     rt_uint32_t c0_status = 0;
     rt_uint32_t c1_status = 0;
@@ -38,7 +38,7 @@ inline void rt_hw_fpu_init(void)
     return ;
 }
 #else
-    inline void rt_hw_fpu_init(void){} /* Do nothing */
+    rt_inline void rt_hw_fpu_init(void){} /* Do nothing */
 #endif
 
 #endif
-- 
cgit v1.3.1


From f295149f20e2c1f29c8321929d0e56721fe91ac2 Mon Sep 17 00:00:00 2001
From: duhuanpeng <548708880@qq.com>
Date: Fri, 3 Apr 2020 20:32:07 +0800
Subject: MIPS: fix inline assembly for FPU

Signed-off-by: duhuanpeng <548708880@qq.com>
---
 libcpu/mips/common/mips_regs.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h
index c5dd727e23..a13e24b539 100644
--- a/libcpu/mips/common/mips_regs.h
+++ b/libcpu/mips/common/mips_regs.h
@@ -999,7 +999,7 @@ do {									\
 
 #define write_32bit_cp0_set1_register(register,value)           \
         __asm__ __volatile__(                                   \
-        "ctc0\t%0,"STR(register)"\n\t"				\
+        "ctc0\t%0,$"STR(register)"\n\t"				\
     "nop"							\
         : : "r" (value));
 
@@ -1037,14 +1037,14 @@ do {									\
     __asm__ __volatile__(                                   \
     ".set\tpush\n\t"					\
     ".set\treorder\n\t"					\
-        "cfc1\t%0,"STR(source)"\n\t"                            \
+        "cfc1\t%0,$"STR(source)"\n\t"                            \
     ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
 #define write_32bit_cp1_register(register,value)                \
         __asm__ __volatile__(                                   \
-        "ctc1\t%0,"STR(register)"\n\t"				\
+        "ctc1\t%0,$"STR(register)"\n\t"				\
     "nop"							\
         : : "r" (value));
 
-- 
cgit v1.3.1


From b3c7bc964bdab9a4ff04f06e9cfb85bd2f9c6107 Mon Sep 17 00:00:00 2001
From: Jonne <qzhang1535@gmail.com>
Date: Fri, 10 Apr 2020 21:40:33 +0800
Subject: 更新mini2440 bsp包: 1、加入Kconfig以支持图形化菜单配置
 2、编译脚本中添加动态模块编译参数 3、开启自动初始化机制支持
 4、重构串口驱动以解决开启posix支持后终端无响应问题 5、解决dm9000网卡驱动link
 up问题 6、添加mnt.c文件用来挂载文件系统
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 bsp/mini2440/.config                    | 513 ++++++++++++++++++++++++++++++++
 bsp/mini2440/Kconfig                    |  28 ++
 bsp/mini2440/SConstruct                 |   4 +-
 bsp/mini2440/applications/application.c | 252 ----------------
 bsp/mini2440/applications/main.c        |  28 ++
 bsp/mini2440/applications/mnt.c         |  23 ++
 bsp/mini2440/applications/startup.c     | 165 ----------
 bsp/mini2440/drivers/SConscript         |   4 +-
 bsp/mini2440/drivers/board.c            | 154 +++-------
 bsp/mini2440/drivers/board.h            |   1 -
 bsp/mini2440/drivers/console.c          | 180 -----------
 bsp/mini2440/drivers/dm9000.c           |   7 +-
 bsp/mini2440/drivers/dm9000.h           |   2 +-
 bsp/mini2440/drivers/key.c              |   2 +-
 bsp/mini2440/drivers/sdcard.c           |   9 +-
 bsp/mini2440/drivers/touch.c            |   2 +-
 bsp/mini2440/drivers/uart.c             | 183 ++++++++++++
 bsp/mini2440/rtconfig.h                 | 359 +++++++++++++---------
 bsp/mini2440/rtconfig.py                |  13 +-
 libcpu/arm/s3c24x0/serial.c             | 291 ------------------
 libcpu/arm/s3c24x0/serial.h             |  66 ----
 21 files changed, 1063 insertions(+), 1223 deletions(-)
 create mode 100644 bsp/mini2440/.config
 create mode 100644 bsp/mini2440/Kconfig
 delete mode 100644 bsp/mini2440/applications/application.c
 create mode 100644 bsp/mini2440/applications/main.c
 create mode 100644 bsp/mini2440/applications/mnt.c
 delete mode 100644 bsp/mini2440/applications/startup.c
 delete mode 100644 bsp/mini2440/drivers/console.c
 create mode 100644 bsp/mini2440/drivers/uart.c
 delete mode 100644 libcpu/arm/s3c24x0/serial.c
 delete mode 100644 libcpu/arm/s3c24x0/serial.h

(limited to 'libcpu')

diff --git a/bsp/mini2440/.config b/bsp/mini2440/.config
new file mode 100644
index 0000000000..e10689caa8
--- /dev/null
+++ b/bsp/mini2440/.config
@@ -0,0 +1,513 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+CONFIG_BOARD_MINI2440=y
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_ARM9=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+CONFIG_RT_USING_CPLUSPLUS=y
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=5
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=5
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+CONFIG_RT_USING_PTHREADS=y
+CONFIG_PTHREAD_NUM_MAX=8
+CONFIG_RT_USING_POSIX=y
+CONFIG_RT_USING_POSIX_MMAP=y
+CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_AIO=y
+CONFIG_RT_USING_MODULE=y
+CONFIG_RT_USING_CUSTOM_DLMODULE=y
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+CONFIG_RT_USING_SAL=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+CONFIG_SAL_USING_POSIX=y
+
+#
+# Network interface device
+#
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
+
+#
+# light weight TCP/IP stack
+#
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+CONFIG_RT_USING_LWIP210=y
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.0.30"
+CONFIG_RT_LWIP_GWADDR="192.168.0.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+CONFIG_RT_LWIP_RAW=y
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=8
+CONFIG_RT_LWIP_PBUF_NUM=16
+CONFIG_RT_LWIP_RAW_PCB_NUM=4
+CONFIG_RT_LWIP_UDP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_SEG_NUM=40
+CONFIG_RT_LWIP_TCP_SND_BUF=8196
+CONFIG_RT_LWIP_TCP_WND=8196
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
+# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_LWIP_NETIF_LINK_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_RT_LWIP_NETIF_LOOPBACK=y
+CONFIG_LWIP_NETIF_LOOPBACK=1
+CONFIG_RT_LWIP_STATS=y
+# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
+CONFIG_RT_LWIP_USING_PING=y
+# CONFIG_RT_LWIP_DEBUG is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+# CONFIG_LWIP_USING_DHCPD is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+CONFIG_YMODEM_USING_CRC_TABLE=y
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
diff --git a/bsp/mini2440/Kconfig b/bsp/mini2440/Kconfig
new file mode 100644
index 0000000000..44da5183eb
--- /dev/null
+++ b/bsp/mini2440/Kconfig
@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config BOARD_MINI2440
+    bool "mini2440"
+    select ARCH_ARM_ARM9
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+
diff --git a/bsp/mini2440/SConstruct b/bsp/mini2440/SConstruct
index a89673811c..93120f79ec 100644
--- a/bsp/mini2440/SConstruct
+++ b/bsp/mini2440/SConstruct
@@ -27,8 +27,8 @@ Export('rtconfig')
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT)
 
-if GetDepend('RT_USING_RTGUI'):
-    objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
+#if GetDepend('RT_USING_RTGUI'):
+#    objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
 
 # libc testsuite 
 # objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
diff --git a/bsp/mini2440/applications/application.c b/bsp/mini2440/applications/application.c
deleted file mode 100644
index 89dbfb6b19..0000000000
--- a/bsp/mini2440/applications/application.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author		Notes
- * 2007-11-20     Yi.Qiu		add rtgui application
- * 2008-6-28      Bernard		no rtgui init
- */
-
-/**
- * @addtogroup mini2440
- */
- 
-/*@{*/
-
-#include <rtthread.h>
-#include "touch.h"
-#include "lcd.h"
-#include "led.h"
-#include "dm9000.h"
-
-#ifdef RT_USING_DFS
-/* dfs filesystem:ELM FatFs filesystem init */
-#include <dfs_elm.h>
-/* dfs Filesystem APIs */
-#include <dfs_fs.h>
-#ifdef RT_USING_DFS_UFFS
-/* dfs filesystem:UFFS filesystem init */
-#include <dfs_uffs.h>
-#endif
-#endif
-
-#ifdef RT_USING_LWIP
-#include <netif/ethernetif.h>
-#endif
-
-#ifdef RT_USING_RTGUI
-#include <rtgui/rtgui.h>
-#endif
-
-#ifdef RT_USING_FTK
-#include "ftk.h"
-#endif
-
-#define RT_INIT_THREAD_STACK_SIZE (2*1024)
-
-#ifdef RT_USING_DFS_ROMFS
-#include <dfs_romfs.h>
-#endif
-
-#ifdef RT_USING_FTK
-static int argc = 1;
-static char* argv[] = {"ftk", NULL};
-
-void rt_ftk_thread_entry(void *parameter)
-{
-	int FTK_MAIN(int argc, char *argv[]);
-
-	FTK_MAIN(argc, argv);
-
-	return;
-}
-
-#endif
-
-void rt_init_thread_entry(void *parameter)
-{
-/* Filesystem Initialization */
-#ifdef RT_USING_DFS
-	{
-		/* init the device filesystem */
-		dfs_init();
-
-#if defined(RT_USING_DFS_ELMFAT)
-		/* init the elm chan FatFs filesystam*/
-		elm_init();
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-		{
-			rt_kprintf("File System initialized!\n");
-		}
-		else
-			rt_kprintf("File System initialzation failed!\n");
-#endif
-
-#if defined(RT_USING_DFS_ROMFS)
-		dfs_romfs_init();
-		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
-#endif
-
-#if defined(RT_USING_DFS_DEVFS)
-		devfs_init();
-		if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0)
-			rt_kprintf("Device File System initialized!\n");
-		else
-			rt_kprintf("Device File System initialzation failed!\n");
-
-		#ifdef RT_USING_NEWLIB
-		/* init libc */
-		libc_system_init("uart0");
-		#endif
-#endif
-
-#if defined(RT_USING_DFS) && defined(RT_USING_LWIP) && defined(RT_USING_DFS_NFS)
-		/* NFSv3 Initialization */
-		nfs_init();
-
-		if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
-			rt_kprintf("NFSv3 File System initialized!\n");
-		else
-			rt_kprintf("NFSv3 File System initialzation failed!\n");
-#endif
-
-#if defined(RT_USING_DFS_UFFS)
-		/* init the uffs filesystem */
-		dfs_uffs_init();
-
-		/* mount flash device as flash directory */
-		if (dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
-			rt_kprintf("UFFS File System initialized!\n");
-		else
-			rt_kprintf("UFFS File System initialzation failed!\n");
-#endif
-	}
-#endif
-
-#ifdef RT_USING_RTGUI
-	{
-		extern void rtgui_system_server_init(void);
-
-		rt_device_t lcd;
-		
-		/* init lcd */
-		rt_hw_lcd_init();
-			
-		/* init touch panel */
-		rtgui_touch_hw_init();	
-
-		/* init keypad */
-		rt_hw_key_init();
-
-		/* find lcd device */
-		lcd = rt_device_find("lcd");
-
-		/* set lcd device as rtgui graphic driver */		
-		rtgui_graphic_set_device(lcd);
-
-		/* initalize rtgui system server */
-		rtgui_system_server_init();
-	}
-#endif
-
-/* LwIP Initialization */
-#ifdef RT_USING_LWIP
-	{
-		extern void lwip_sys_init(void);
-		eth_system_device_init();
-
-		/* register ethernetif device */
-		rt_hw_dm9000_init();
-
-		/* init lwip system */
-		lwip_sys_init();
-		rt_kprintf("TCP/IP initialized!\n");
-	}
-#endif
-
-#ifdef RT_USING_FTK
-	{
-		rt_thread_t ftk_thread;
-
-		/* init lcd */
-		rt_hw_lcd_init();
-
-		/* init touch panel */
-		rtgui_touch_hw_init();	
-
-		/* init keypad */
-		rt_hw_key_init();
-
-		/* create ftk thread */
-		ftk_thread = rt_thread_create("ftk",
-									rt_ftk_thread_entry, RT_NULL,
-									10 * 1024, 8, 20);	
-
-		/* startup ftk thread */
-		if (ftk_thread != RT_NULL)
-			rt_thread_startup(ftk_thread);		
-	}
-#endif
-}
-
-void rt_led_thread_entry(void *parameter)
-{
-	while (1)
-	{
-		/* light on leds for one second */
-		rt_hw_led_on(LED2|LED3);
-		rt_hw_led_off(LED1|LED4);
-		rt_thread_delay(100);
-
-		/* light off leds for one second */
-		rt_hw_led_off(LED2|LED3);
-		rt_hw_led_on(LED1|LED4);
-		rt_thread_delay(100);
-	}
-}
-
-int rt_application_init(void)
-{
-	rt_thread_t init_thread;
-	rt_thread_t led_thread;
-
-#if (RT_THREAD_PRIORITY_MAX == 32)
-	init_thread = rt_thread_create("init",
-								rt_init_thread_entry, RT_NULL,
-								RT_INIT_THREAD_STACK_SIZE, 8, 20);
-
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 20, 20);
-#else
-	init_thread = rt_thread_create("init",
-								rt_init_thread_entry, RT_NULL,
-								RT_INIT_THREAD_STACK_SIZE, 80, 20);
-
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 200, 20);
-#endif
-
-	if (init_thread != RT_NULL)
-		rt_thread_startup(init_thread);
-
-	if (led_thread != RT_NULL)
-		rt_thread_startup(led_thread);
-
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/mini2440/applications/main.c b/bsp/mini2440/applications/main.c
new file mode 100644
index 0000000000..a67ff93f7a
--- /dev/null
+++ b/bsp/mini2440/applications/main.c
@@ -0,0 +1,28 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <rtthread.h>
+
+#include "led.h"
+
+int main(void)
+{
+    printf("hello rt-thread\n");
+
+    while (1)
+    {
+        /* light on leds for one second */
+        rt_hw_led_on(LED2|LED3);
+        rt_hw_led_off(LED1|LED4);
+        rt_thread_delay(100);
+    
+        /* light off leds for one second */
+        rt_hw_led_off(LED2|LED3);
+        rt_hw_led_on(LED1|LED4);
+        rt_thread_delay(100);
+    }   
+
+    return 0;
+}
+
+
diff --git a/bsp/mini2440/applications/mnt.c b/bsp/mini2440/applications/mnt.c
new file mode 100644
index 0000000000..fc9f915167
--- /dev/null
+++ b/bsp/mini2440/applications/mnt.c
@@ -0,0 +1,23 @@
+#include <rtthread.h>
+
+#ifdef RT_USING_DFS
+#include <dfs_fs.h>
+#include "dfs_ramfs.h"
+
+int mnt_init(void)
+{
+
+    if(dfs_mount(RT_NULL, "/", "ram", 0, dfs_ramfs_create(rt_malloc(1024),1024)) == 0)
+    {
+        rt_kprintf("RAM file system initializated!\n");
+    }
+    else
+    {
+        rt_kprintf("RAM file system initializate failed!\n");
+    }
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif
+
diff --git a/bsp/mini2440/applications/startup.c b/bsp/mini2440/applications/startup.c
deleted file mode 100644
index fab223d834..0000000000
--- a/bsp/mini2440/applications/startup.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-02-26     Bernard      first implementation
- * 2006-05-05     Bernard      add two test thread
- * 2006-08-10     Bernard      use rt_show_version to display version information
- * 2008-07-14     Bernard      modify the heap memory init parameter
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <s3c24x0.h>
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-#endif
-
-extern void rt_hw_interrupt_init(void);
-extern void rt_hw_board_init(void);
-extern void rt_hw_rtc_init(void);
-extern void rt_serial_init(void);
-extern void rt_system_timer_init(void);
-extern void rt_system_scheduler_init(void);
-extern void rt_thread_idle_init(void);
-extern void rt_hw_cpu_icache_enable(void);
-extern void rt_show_version(void);
-extern void rt_system_heap_init(void*, void*);
-extern void rt_hw_finsh_init(void);
-extern void rt_application_init(void);
-
-extern struct serial_device uart0;
-extern struct rt_device uart0_device;
-extern struct serial_device uart2;
-extern struct rt_device uart2_device;
-
-/**
- * @addtogroup mini2440
- */
-
-/*@{*/
-#if defined(__CC_ARM)
-	extern int Image$$ER_ZI$$ZI$$Base;
-	extern int Image$$ER_ZI$$ZI$$Length;
-	extern int Image$$ER_ZI$$ZI$$Limit;
-#elif (defined (__GNUC__))
-	rt_uint8_t _irq_stack_start[1024];
-	rt_uint8_t _fiq_stack_start[1024];
-	rt_uint8_t _undefined_stack_start[512];
-	rt_uint8_t _abort_stack_start[512];
-	rt_uint8_t _svc_stack_start[4096] SECTION(".nobss");
-	extern unsigned char __bss_start;
-	extern unsigned char __bss_end;
-#endif
-
-#ifdef RT_USING_FINSH
-extern int finsh_system_init(void);
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* enable cpu cache */
-	rt_hw_cpu_icache_enable();
-	rt_hw_cpu_dcache_enable();
-
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
-
-	/* init board */
-	rt_hw_board_init();
-
-	/* show version */
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init kernel object */
-	rt_system_object_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-	/* init heap memory system */
-#ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x33F00000);
-#else
-	rt_system_heap_init((void*)&__bss_end, (void*)0x33F00000);
-#endif
-
-#ifdef RT_USING_MODULE
-	/* init module system*/
-	rt_system_module_init();
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-#ifdef RT_USING_DEVICE
-	/* register uart0 */
-	rt_hw_serial_register(&uart0_device, "uart0",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart0);
-
-	/* register uart2, used for RTI debug */
-	rt_hw_serial_register(&uart2_device, "uart2",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart2);
-
-#ifdef RT_USING_DFS
-	rt_hw_sdcard_init();
-#ifdef RT_USING_DFS_UFFS
-	rt_hw_nand_init();
-#endif
-#endif
-
-	/* rtc init */
-	rt_hw_rtc_init();
-#endif
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-#ifdef RT_USING_DEVICE
-	finsh_set_device("uart0");
-#endif
-#endif
-
-	rt_system_timer_thread_init();
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-int main(void)
-{
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
-
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
-
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/mini2440/drivers/SConscript b/bsp/mini2440/drivers/SConscript
index 55c8b43cd5..8b36ce3aab 100644
--- a/bsp/mini2440/drivers/SConscript
+++ b/bsp/mini2440/drivers/SConscript
@@ -8,7 +8,7 @@ cwd     = os.path.join(str(Dir('#')), 'drivers')
 src = Split("""
 board.c
 led.c
-console.c
+uart.c
 """)
 
 if GetDepend('RT_USING_DFS'):
@@ -18,7 +18,7 @@ if GetDepend('RT_USING_LWIP'):
 	src += ['dm9000.c']
 
 if GetDepend('RT_USING_RTGUI'):
-    	src += ['touch.c', 'key.c', 'calibration.c']
+    	src += ['touch.c', 'key.c']
 
 if GetDepend('RT_USING_FTK'):
     	src += ['touch.c', 'key.c']
diff --git a/bsp/mini2440/drivers/board.c b/bsp/mini2440/drivers/board.c
index fc623386b4..14e2e426df 100644
--- a/bsp/mini2440/drivers/board.c
+++ b/bsp/mini2440/drivers/board.c
@@ -26,6 +26,29 @@
  */
 /*@{*/
 
+#if defined(__CC_ARM)
+    extern int Image$$ER_ZI$$ZI$$Base;
+    extern int Image$$ER_ZI$$ZI$$Length;
+    extern int Image$$ER_ZI$$ZI$$Limit;
+#elif (defined (__GNUC__))
+    rt_uint8_t _irq_stack_start[1024];
+    rt_uint8_t _fiq_stack_start[1024];
+    rt_uint8_t _undefined_stack_start[512];
+    rt_uint8_t _abort_stack_start[512];
+    rt_uint8_t _svc_stack_start[4096] SECTION(".nobss");
+#endif
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN      (((void*)&__bss_end) + 0x1000)
+#endif
+
+#define HEAP_END        (void*)(0x33F00000)
+
+
 extern rt_uint32_t PCLK, FCLK, HCLK, UCLK;
 
 extern void rt_hw_clock_init(void);
@@ -35,26 +58,6 @@ extern void rt_hw_get_clock(void);
 extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
 extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
 
-#define UART0	((struct uartport *)&U0BASE)
-struct serial_int_rx uart0_int_rx;
-struct serial_device uart0 =
-{
-	UART0,
-	&uart0_int_rx,
-	RT_NULL
-};
-struct rt_device uart0_device;
-
-#define UART2	((struct uartport *)&U2BASE)
-struct serial_int_rx uart2_int_rx;
-struct serial_device uart2 =
-{
-	UART2,
-	&uart2_int_rx,
-	RT_NULL
-};
-struct rt_device uart2_device;
-
 /**
  * This function will handle rtos timer
  */
@@ -63,92 +66,6 @@ static void rt_timer_handler(int vector, void *param)
 	rt_tick_increase();
 }
 
-/**
- * This function will handle serial
- */
-static void rt_serial0_handler(int vector, void *param)
-{
-	INTSUBMSK |= (BIT_SUB_RXD0);
-
-	rt_hw_serial_isr(&uart0_device);
-
-	SUBSRCPND |= BIT_SUB_RXD0;
-
-	/* Unmask sub interrupt (RXD0) */
-	INTSUBMSK  &=~(BIT_SUB_RXD0);
-}
-
-/**
- * This function will handle serial
- */
-static void rt_serial2_handler(int vector, void *param)
-{
-	INTSUBMSK |= (BIT_SUB_RXD2);
-
-	rt_hw_serial_isr(&uart2_device);
-
-	SUBSRCPND |= BIT_SUB_RXD2;
-
-	/* Unmask sub interrupt (RXD0) */
-	INTSUBMSK  &=~(BIT_SUB_RXD2);
-}
-
-/**
- * This function will handle init uart
- */
-static void rt_hw_uart_init(void)
-{
-	int i;
-	/* UART0 port configure */
-	GPHCON |= 0xAA;
-	/* PULLUP is disable */
-	GPHUP |= 0xF;
-
-	/* FIFO enable, Tx/Rx FIFO clear */
-	uart0.uart_device->ufcon = 0x0;
-	/* disable the flow control */
-	uart0.uart_device->umcon = 0x0;
-	/* Normal,No parity,1 stop,8 bit */
-	uart0.uart_device->ulcon = 0x3;
-	/*
-	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal,interrupt or polling
-	 */
-	uart0.uart_device->ucon = 0x245;
-	/* Set uart0 bps */
-	uart0.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1;
-	/* output PCLK to UART0/1, PWMTIMER */
-	CLKCON |= 0x0D00;
-
-	/* FIFO enable, Tx/Rx FIFO clear */
-	uart2.uart_device->ufcon = 0x0;
-	/* disable the flow control */
-	uart2.uart_device->umcon = 0x0;
-	/* Normal,No parity,1 stop,8 bit */
-	uart2.uart_device->ulcon = 0x3;
-	/*
-	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal,interrupt or polling
-	 */
-	uart2.uart_device->ucon = 0x245;
-	/* Set uart0 bps */
-	uart2.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1;
-
-	for (i = 0; i < 100; i++);
-
-	/* install uart0 isr */
-	INTSUBMSK &= ~(BIT_SUB_RXD0);
-
-	/* install uart2 isr */
-	INTSUBMSK &= ~(BIT_SUB_RXD2);
-
-	rt_hw_interrupt_install(INTUART0, rt_serial0_handler, RT_NULL, "UART0");
-	rt_hw_interrupt_umask(INTUART0);
-
-	rt_hw_interrupt_install(INTUART2, rt_serial2_handler, RT_NULL, "UART2");
-	rt_hw_interrupt_umask(INTUART2);
-}
-
 /**
  * This function will init timer4 for system ticks
  */
@@ -177,6 +94,12 @@ static  void rt_hw_timer_init(void)
  */
 void rt_hw_board_init(void)
 {
+	rt_hw_cpu_icache_enable();
+	rt_hw_cpu_dcache_enable();
+
+	/* init hardware interrupt */
+	rt_hw_interrupt_init();
+
 	/* initialize the system clock */
 	rt_hw_clock_init();
 
@@ -186,14 +109,27 @@ void rt_hw_board_init(void)
 	/* initialize led port */
 	rt_hw_led_init();
 
-	/* initialize uart */
-	rt_hw_uart_init();
-
 	/* initialize mmu */
 	rt_hw_mmu_init();
 
 	/* initialize timer4 */
 	rt_hw_timer_init();
+
+	/* initialize system heap */
+	rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+
+	rt_components_board_init();
+
+#ifdef RT_USING_CONSOLE
+	rt_console_set_device("uart0");
+#endif
+
 }
 
+#ifdef RT_USING_MODULE
+int rt_system_module_init(void)
+{
+    return 0;
+}
+#endif
 /*@}*/
diff --git a/bsp/mini2440/drivers/board.h b/bsp/mini2440/drivers/board.h
index 2635ab147a..434f725216 100644
--- a/bsp/mini2440/drivers/board.h
+++ b/bsp/mini2440/drivers/board.h
@@ -16,7 +16,6 @@
 #define __BOARD_H__
 
 #include <s3c24x0.h>
-#include <serial.h>
 
 void rt_hw_board_init(void);
 void rt_hw_sdcard_init(void);
diff --git a/bsp/mini2440/drivers/console.c b/bsp/mini2440/drivers/console.c
deleted file mode 100644
index 70a57a7370..0000000000
--- a/bsp/mini2440/drivers/console.c
+++ /dev/null
@@ -1,180 +0,0 @@
-#include <rtthread.h>
-
-#include <serial.h>
-
-#define RT_CONSOLE_WIDTH		240
-#define RT_CONSOLE_HEIGHT		320
-
-#define RT_CONSOLE_FONT_WIDTH	8
-#define RT_CONSOLE_FONT_HEIGHT	16
-
-#define RT_CONSOLE_COL			(RT_CONSOLE_WIDTH/RT_CONSOLE_FONT_WIDTH)
-#define RT_CONSOLE_ROW			(RT_CONSOLE_HEIGHT/RT_CONSOLE_FONT_HEIGHT)
-
-#define RT_CONSOLE_TAB			4
-
-#define RT_CONSOLE_FOREPIXEL	(0x001f)
-
-extern struct serial_device uart0;
-
-struct rt_console
-{
-	rt_uint8_t* video_ptr;
-	rt_uint8_t* font_ptr;
-
-	/* bpp and pixel of width */
-	rt_uint8_t bpp;
-	rt_uint32_t pitch;
-
-	/* current cursor */
-	rt_uint8_t current_col;
-	rt_uint8_t current_row;
-};
-struct rt_console console;
-
-void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp);
-void rt_hw_console_newline(void);
-void rt_hw_console_putc(char c);
-void rt_hw_console_clear(void);
-
-void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp)
-{
-	rt_memset(&console, 0, sizeof(struct rt_console));
-
-	console.video_ptr = video_ptr;
-	console.font_ptr = font_ptr;
-	console.bpp = bpp;
-	console.pitch = console.bpp * RT_CONSOLE_WIDTH;
-
-	rt_hw_console_clear();
-}
-
-void rt_hw_console_putc(char c)
-{
-	switch (c)
-	{
-        case 10:
-        case 11:
-        case 12:
-        case 13:
-			/* to next line */
-            rt_hw_console_newline();
-            console.current_col = 0;
-            break;
-
-        case 9:
-            console.current_col += RT_CONSOLE_TAB;
-            break;
-
-        default:
-			{
-				rt_uint8_t* font_ptr;
-				register rt_uint32_t cursor;
-				register rt_uint32_t i, j;
-
-				if (console.current_col == RT_CONSOLE_COL)
-				{
-					rt_hw_console_newline();
-					console.current_col = 0;
-
-					rt_hw_console_putc(c);
-					return;
-				}
-
-				font_ptr = console.font_ptr + c * RT_CONSOLE_FONT_HEIGHT;
-				cursor = (console.current_row * RT_CONSOLE_FONT_HEIGHT) * console.pitch
-					+ console.current_col * RT_CONSOLE_FONT_WIDTH * console.bpp;
-
-				for (i = 0; i < RT_CONSOLE_FONT_HEIGHT; i ++ )
-				{
-					for (j = 0; j < RT_CONSOLE_FONT_WIDTH; j ++)
-					{
-						if ( ((font_ptr[i] >> (7-j)) & 0x01) != 0 )
-						{
-							/* draw a pixel */
-							rt_uint8_t *ptr = &(console.video_ptr[cursor + i * console.pitch + j * console.bpp]);
-							switch(console.bpp)
-							{
-							case 1:
-								*ptr = RT_CONSOLE_FOREPIXEL;
-								break;
-							case 2:
-								*(rt_uint16_t*)ptr = RT_CONSOLE_FOREPIXEL;
-								break;
-							case 3:
-								ptr[0] = RT_CONSOLE_FOREPIXEL & 0xff;
-								ptr[1] = (RT_CONSOLE_FOREPIXEL >> 8) & 0xff;
-								ptr[2] = (RT_CONSOLE_FOREPIXEL >> 16) & 0xff;
-								break;
-							case 4:
-								*(rt_uint32_t*)ptr = RT_CONSOLE_FOREPIXEL;
-								break;
-							}
-						}
-					}
-				}
-
-				console.current_col ++;
-			}
-			break;
-	}
-}
-
-void rt_hw_console_newline()
-{
-	console.current_row ++;
-	if (console.current_row >= RT_CONSOLE_ROW)
-	{
-		rt_uint32_t i;
-
-		/* scroll to next line */
-		for (i = 0; i < RT_CONSOLE_ROW - 1; i ++)
-		{
-			rt_memcpy(console.video_ptr + i * RT_CONSOLE_FONT_HEIGHT * console.pitch,
-				console.video_ptr + (i + 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch,
-				RT_CONSOLE_FONT_HEIGHT * console.pitch);
-		}
-
-		/* clear last line */
-		rt_memset(console.video_ptr + (RT_CONSOLE_ROW - 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch,
-			0,
-			RT_CONSOLE_FONT_HEIGHT * console.pitch);
-
-		console.current_row = RT_CONSOLE_ROW - 1;
-	}
-}
-
-void rt_hw_console_clear()
-{
-	console.current_col = 0;
-	console.current_row = 0;
-
-	rt_memset(console.video_ptr, 0, RT_CONSOLE_HEIGHT * console.pitch);
-}
-
-/* write one character to serial, must not trigger interrupt */
-void rt_hw_serial_putc(const char c)
-{
-	/*
-		to be polite with serial console add a line feed
-		to the carriage return character
-	*/
-	if (c=='\n')rt_hw_serial_putc('\r');
-
-	while (!(uart0.uart_device->ustat & USTAT_TXB_EMPTY));
-	uart0.uart_device->utxh = (c & 0x1FF);
-}
-
-/**
- * This function is used by rt_kprintf to display a string on console.
- *
- * @param str the displayed string
- */
-void rt_hw_console_output(const char* str)
-{
-	while (*str)
-	{
-		rt_hw_serial_putc(*str++);
-	}
-}
-
diff --git a/bsp/mini2440/drivers/dm9000.c b/bsp/mini2440/drivers/dm9000.c
index e3f1f0d634..22afb322c7 100644
--- a/bsp/mini2440/drivers/dm9000.c
+++ b/bsp/mini2440/drivers/dm9000.c
@@ -287,6 +287,9 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
 		}
 	}
 
+	/* send a notify */
+	eth_device_linkchange(&dm9000_device.parent, RT_TRUE);
+
 	/* see what we've got */
 	lnk = phy_read(17) >> 12;
 	rt_kprintf("operating at ");
@@ -588,7 +591,7 @@ void INTEINT4_7_handler(int irqno, void *param)
 	EINTPEND = eint_pend;
 }
 
-void rt_hw_dm9000_init()
+int rt_hw_dm9000_init()
 {
 	/* Set GPF7 as EINT7 */
 	GPFCON = GPFCON & (~(3 << 14)) | (2 << 14);
@@ -641,6 +644,8 @@ void rt_hw_dm9000_init()
 	rt_hw_interrupt_umask(INTEINT4_7);
 }
 
+INIT_DEVICE_EXPORT(rt_hw_dm9000_init);
+
 void dm9000a(void)
 {
 	rt_kprintf("\n");
diff --git a/bsp/mini2440/drivers/dm9000.h b/bsp/mini2440/drivers/dm9000.h
index 1dda60bfd2..28499c22d8 100644
--- a/bsp/mini2440/drivers/dm9000.h
+++ b/bsp/mini2440/drivers/dm9000.h
@@ -143,6 +143,6 @@
 
 #define GPCR_GEP_CNTL       (1<<0)
 
-void rt_hw_dm9000_init(void);
+int rt_hw_dm9000_init(void);
 
 #endif
diff --git a/bsp/mini2440/drivers/key.c b/bsp/mini2440/drivers/key.c
index 3c73c7a788..d75ffd6d26 100644
--- a/bsp/mini2440/drivers/key.c
+++ b/bsp/mini2440/drivers/key.c
@@ -79,7 +79,7 @@ static void rt_hw_key_isr(void)
 /**
  * This function is only for QEMU emulation
  */
-static void rt_key_handler(int vector)
+static void rt_key_handler(int vector, void *param)
 {
 	INTSUBMSK |= (BIT_SUB_RXD1);
 
diff --git a/bsp/mini2440/drivers/sdcard.c b/bsp/mini2440/drivers/sdcard.c
index b2ab684e48..0f5b79bb25 100644
--- a/bsp/mini2440/drivers/sdcard.c
+++ b/bsp/mini2440/drivers/sdcard.c
@@ -550,7 +550,7 @@ static rt_size_t rt_sdcard_write(rt_device_t dev,
     return size;
 }
 
-void rt_hw_sdcard_init(void)
+int rt_hw_sdcard_init(void)
 {
     rt_uint8_t i, status;
     rt_uint8_t *sector;
@@ -574,7 +574,7 @@ void rt_hw_sdcard_init(void)
         {
             rt_kprintf("allocate partition sector buffer failed\n");
 
-            return;
+            return RT_ERROR;
         }
         status = sd_readblock(0, sector);
         if (status == RT_EOK)
@@ -637,12 +637,15 @@ void rt_hw_sdcard_init(void)
         /* release sector buffer */
         rt_free(sector);
 
-        return;
+        return RT_ERROR; 
     }
     else
     {
         rt_kprintf("sdcard init failed\n");
     }
+
+    return RT_EOK;
 }
 
+INIT_BOARD_EXPORT(rt_hw_sdcard_init);
 #endif
diff --git a/bsp/mini2440/drivers/touch.c b/bsp/mini2440/drivers/touch.c
index 08d41080be..e584c379e3 100644
--- a/bsp/mini2440/drivers/touch.c
+++ b/bsp/mini2440/drivers/touch.c
@@ -349,7 +349,7 @@ static void s3c2410_intc_stylus_updown(void)
 	SUBSRCPND |= BIT_SUB_TC;
 }
 
-static void rt_touch_handler(int irqno)
+static void rt_touch_handler(int irqno, void *param)
 {
 	if (SUBSRCPND & BIT_SUB_ADC)
 	{
diff --git a/bsp/mini2440/drivers/uart.c b/bsp/mini2440/drivers/uart.c
new file mode 100644
index 0000000000..f7bf1d9461
--- /dev/null
+++ b/bsp/mini2440/drivers/uart.c
@@ -0,0 +1,183 @@
+/*
+ * File      : uart.c
+ * Drivers for s3c2440 uarts.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-09     Jonne        Code refactoring for new bsp
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#define ULCON_OFS				0x00
+#define UCON_OFS				0x04
+#define UFCON_OFS				0x08
+#define UMCON_OFS				0x0c
+#define UTRSTAT_OFS				0x10
+#define UERSTAT_OFS				0x14
+#define UFSTAT_OFS				0x18
+#define UMSTAT_OFS				0x1c
+#define UTXH_OFS				0x20
+#define URXH_OFS				0x24
+#define UBRDIV_OFS				0x28
+
+#define readl(addr)             (*(volatile unsigned long *)(addr))
+#define writel(addr, value)     (*(volatile unsigned long *)(addr) = value)  
+
+#define PCLK_HZ                 50000000
+
+struct hw_uart_device
+{
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg) 
+{
+    struct hw_uart_device* uart = serial->parent.user_data;
+
+    writel(uart->hw_base + UBRDIV_OFS, PCLK_HZ / (cfg->baud_rate * 16));
+
+    writel(uart->hw_base + ULCON_OFS, 0x03);// 8bit data, 1bit stop, No parity
+    writel(uart->hw_base + UCON_OFS, 0x05);
+    writel(uart->hw_base + UFCON_OFS, 0x00);
+    writel(uart->hw_base + UMCON_OFS, 0x00);
+
+	return RT_EOK;
+}
+
+static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+	struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL); 
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        INTSUBMSK |= BIT_SUB_RXD0;
+		
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        INTSUBMSK &= ~(BIT_SUB_RXD0);
+        break;
+    }
+
+    return RT_EOK;
+}
+static int s3c2440_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device* uart = serial->parent.user_data;
+
+    while(!(readl(uart->hw_base + UTRSTAT_OFS) & (1<<2))) 
+    {
+    }
+
+    writel(uart->hw_base + UTXH_OFS, c);
+    
+    return 0;
+
+     
+}
+static int s3c2440_getc(struct rt_serial_device *serial)
+{
+    struct hw_uart_device* uart = serial->parent.user_data;
+    int ch = -1;
+
+    if(readl(uart->hw_base + UTRSTAT_OFS) & (1<<0)) 
+    {
+        ch = readl(uart->hw_base + URXH_OFS) & 0x000000FF;
+    }
+    
+    return ch;
+}
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    
+    /*clear SUBSRCPND*/ 
+    if(irqno == INTUART0) 
+    {
+        SUBSRCPND = BIT_SUB_RXD0;
+    } 
+    else if(irqno == INTUART1) 
+    {
+        SUBSRCPND = BIT_SUB_RXD1;
+    }
+    else 
+    {
+        SUBSRCPND = BIT_SUB_RXD2;
+    }
+}
+
+static struct rt_uart_ops s3c2440_uart_ops = {
+		.configure = s3c2440_serial_configure,
+		.control = s3c2440_serial_control,
+		.putc = s3c2440_putc,
+		.getc = s3c2440_getc
+};
+
+
+static struct rt_serial_device _serial0 = {
+	.ops = &s3c2440_uart_ops,
+	.config = RT_SERIAL_CONFIG_DEFAULT,
+	.serial_rx = NULL,
+	.serial_tx = NULL
+};
+static struct hw_uart_device _hwserial0 = {
+	.hw_base = 0x50000000,
+	.irqno = INTUART0
+};
+
+static struct rt_serial_device _serial1 = {
+	.ops = &s3c2440_uart_ops,
+	.config = RT_SERIAL_CONFIG_DEFAULT,
+	.serial_rx = NULL,
+	.serial_tx = NULL
+};
+static struct hw_uart_device _hwserial1 = {
+	.hw_base = 0x50004000,
+	.irqno = INTUART1
+};
+
+static struct rt_serial_device _serial2 = {
+	.ops = &s3c2440_uart_ops,
+	.config = RT_SERIAL_CONFIG_DEFAULT,
+	.serial_rx = NULL,
+	.serial_tx = NULL
+};
+static struct hw_uart_device _hwserial2 = {
+	.hw_base = 0x50008000,
+	.irqno = INTUART2
+};
+
+
+int rt_hw_uart_init(void)
+{
+    /* register UART0 device */
+    rt_hw_serial_register(&_serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial0);
+    rt_hw_interrupt_install(_hwserial0.irqno, rt_hw_uart_isr, &_serial0, "uart0");
+    rt_hw_interrupt_umask(INTUART0);
+	
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial1);
+    rt_hw_interrupt_install(_hwserial1.irqno, rt_hw_uart_isr, &_serial1, "uart1");
+    rt_hw_interrupt_umask(INTUART1);
+
+    /* register UART2 device */
+    rt_hw_serial_register(&_serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial2);
+    rt_hw_interrupt_install(_hwserial2.irqno, rt_hw_uart_isr, &_serial2, "uart2");
+    rt_hw_interrupt_umask(INTUART2);
+
+    return 0;
+}
+
+INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/mini2440/rtconfig.h b/bsp/mini2440/rtconfig.h
index 8147715c8f..5d65b46148 100644
--- a/bsp/mini2440/rtconfig.h
+++ b/bsp/mini2440/rtconfig.h
@@ -1,176 +1,243 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
-
-// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
-#define RT_NAME_MAX	32
-// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
-#define RT_ALIGN_SIZE	4
-// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
-// <item description="8">8</item>
-// <item description="32">32</item>
-// <item description="256">256</item>
-// </integer>
-#define RT_THREAD_PRIORITY_MAX	256
-// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
-#define RT_TICK_PER_SECOND	100
-// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
-// #define RT_DEBUG
-// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
-// #define RT_THREAD_DEBUG
-// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
-#define RT_USING_OVERFLOW_CHECK
-// <bool name="RT_USING_INTERRUPT_INFO" description="Show more interrupt description" default="true" />
-#define RT_USING_INTERRUPT_INFO
-// </section>
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+#define BOARD_MINI2440
 
-// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
-// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
-// #define RT_USING_TIMER_SOFT
-// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
-#define RT_TIMER_THREAD_PRIO	8
-// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
-#define RT_TIMER_THREAD_STACK_SIZE	512
-// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
-#define RT_TIMER_TICK_PER_SECOND	10
-// </section>
-
-// <section name="IPC" description="Inter-Thread communication" default="always" >
-// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
 #define RT_USING_SEMAPHORE
-// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
 #define RT_USING_MUTEX
-// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
 #define RT_USING_EVENT
-// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
 #define RT_USING_MAILBOX
-// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
 #define RT_USING_MESSAGEQUEUE
-// </section>
 
-// <section name="MM" description="Memory Management" default="always" >
-// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+/* Memory Management */
+
 #define RT_USING_MEMPOOL
-// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
-#define RT_USING_HEAP
-// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_MEMHEAP
 #define RT_USING_SMALL_MEM
-// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
-// #define RT_USING_SLAB
-// </section>
+#define RT_USING_HEAP
 
-// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
-#define RT_USING_DEVICE
-#define RT_USING_DEVICE_IPC
-// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
-#define RT_USING_UART0
-// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
-#define RT_UART_RX_BUFFER_SIZE	64
-// </section>
+/* Kernel Device Object */
 
-// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_DEVICE
 #define RT_USING_CONSOLE
-// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
-#define RT_CONSOLEBUF_SIZE	128
-// </section>
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40003
+#define ARCH_ARM
+#define ARCH_ARM_ARM9
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+#define RT_USING_CPLUSPLUS
+
+/* Command shell */
 
-// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
 #define RT_USING_FINSH
-// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
 #define FINSH_USING_DESCRIPTION
-// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
-#define FINSH_THREAD_STACK_SIZE	4096
-// </section>
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
 
-// <section name="LIBC" description="C Runtime library setting" default="always" >
-// <bool name="RT_USING_LIBC" description="Using C library" default="true" />
-#define RT_USING_LIBC
-// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
-#define RT_USING_PTHREADS
-// </section>
+/* Device virtual file system */
 
-// <section name="RT_USING_DFS" description="Device file system" default="true" >
 #define RT_USING_DFS
-// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
 #define DFS_USING_WORKDIR
-// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
-#define DFS_FILESYSTEMS_MAX	2
-// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
-#define DFS_FD_MAX	4
-// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define DFS_FILESYSTEMS_MAX 5
+#define DFS_FILESYSTEM_TYPES_MAX 5
+#define DFS_FD_MAX 16
 #define RT_USING_DFS_ELMFAT
-// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
-// <item description="LFN1">1</item>
-// <item description="LFN1">2</item>
-// </integer>
-#define RT_DFS_ELM_USE_LFN	1
-// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936">
-#define RT_DFS_ELM_CODE_PAGE	936
-// <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" />
-// #define RT_DFS_ELM_CODE_PAGE_FILE
-// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
-#define RT_DFS_ELM_MAX_LFN	255
-// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
-// #define RT_USING_DFS_YAFFS2
-// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
-// #define RT_USING_DFS_UFFS
-// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
 #define RT_USING_DFS_DEVFS
-// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
-// #define RT_USING_DFS_NFS
-// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
-// </section>
+#define RT_USING_DFS_RAMFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_PTHREADS
+#define PTHREAD_NUM_MAX 8
+#define RT_USING_POSIX
+#define RT_USING_POSIX_MMAP
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_AIO
+#define RT_USING_MODULE
+#define RT_USING_CUSTOM_DLMODULE
+
+/* Network */
+
+/* Socket abstraction layer */
+
+#define RT_USING_SAL
+
+/* protocol stack implement */
+
+#define SAL_USING_LWIP
+#define SAL_USING_POSIX
+
+/* Network interface device */
+
+#define RT_USING_NETDEV
+#define NETDEV_USING_IFCONFIG
+#define NETDEV_USING_PING
+#define NETDEV_USING_NETSTAT
+#define NETDEV_USING_AUTO_DEFAULT
+#define NETDEV_IPV4 1
+#define NETDEV_IPV6 0
+
+/* light weight TCP/IP stack */
 
-// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
 #define RT_USING_LWIP
-// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_USING_LWIP210
+#define RT_LWIP_IGMP
 #define RT_LWIP_ICMP
-// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
-// #define RT_LWIP_IGMP
-// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_DNS
+#define RT_LWIP_DHCP
+#define IP_SOF_BROADCAST 1
+#define IP_SOF_BROADCAST_RECV 1
+
+/* Static IPv4 Address */
+
+#define RT_LWIP_IPADDR "192.168.0.30"
+#define RT_LWIP_GWADDR "192.168.0.1"
+#define RT_LWIP_MSKADDR "255.255.255.0"
 #define RT_LWIP_UDP
-// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
 #define RT_LWIP_TCP
-// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
-#define RT_LWIP_DNS
-// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
-#define RT_LWIP_TCP_PCB_NUM	5
-// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
-#define RT_LWIP_TCP_SND_BUF	8192
-// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
-#define RT_LWIP_TCP_WND	8192
-// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
-// #define RT_LWIP_SNMP
-// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
-// #define RT_LWIP_DHCP
-// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="8" />
-#define RT_LWIP_TCP_SEG_NUM	40
-// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
-// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	32
-// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
-// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
-#define RT_LWIP_ETHTHREAD_PRIORITY	144
-// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	32
-// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
-// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
-#define RT_LWIP_IPADDR "192.168.1.30"
-// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
-#define RT_LWIP_GWADDR  "192.168.1.1"
-// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
-#define RT_LWIP_MSKADDR  "255.255.255.0"
-// </section>
-
-// </RDTConfigurator>
+#define RT_LWIP_RAW
+#define RT_MEMP_NUM_NETCONN 8
+#define RT_LWIP_PBUF_NUM 16
+#define RT_LWIP_RAW_PCB_NUM 4
+#define RT_LWIP_UDP_PCB_NUM 4
+#define RT_LWIP_TCP_PCB_NUM 4
+#define RT_LWIP_TCP_SEG_NUM 40
+#define RT_LWIP_TCP_SND_BUF 8196
+#define RT_LWIP_TCP_WND 8196
+#define RT_LWIP_TCPTHREAD_PRIORITY 10
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_PRIORITY 12
+#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+#define LWIP_NETIF_STATUS_CALLBACK 1
+#define LWIP_NETIF_LINK_CALLBACK 1
+#define SO_REUSE 1
+#define LWIP_SO_RCVTIMEO 1
+#define LWIP_SO_SNDTIMEO 1
+#define LWIP_SO_RCVBUF 1
+#define RT_LWIP_NETIF_LOOPBACK
+#define LWIP_NETIF_LOOPBACK 1
+#define RT_LWIP_STATS
+#define RT_LWIP_USING_PING
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_CRC_TABLE
+#define YMODEM_USING_FILE_TRANSFER
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
 
 #endif
diff --git a/bsp/mini2440/rtconfig.py b/bsp/mini2440/rtconfig.py
index dd574acb16..106597711a 100644
--- a/bsp/mini2440/rtconfig.py
+++ b/bsp/mini2440/rtconfig.py
@@ -9,14 +9,14 @@ ARCH     = 'arm'
 CPU      = 's3c24x0'
 TextBase = '0x30000000'
 
-CROSS_TOOL 	= 'keil'
+CROSS_TOOL 	= 'gcc'
 
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM 	= 'gcc'
-    EXEC_PATH 	= 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
+    EXEC_PATH 	= '/opt/gcc-arm-none-eabi-6_2-2016q4/bin'
 elif CROSS_TOOL == 'keil':
     PLATFORM 	= 'armcc'
     EXEC_PATH 	= 'C:/Keil'
@@ -43,12 +43,21 @@ if PLATFORM == 'gcc':
     SIZE = PREFIX + 'size'
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
 
     DEVICE = ' -mcpu=arm920t'
     CFLAGS = DEVICE
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + ' -DTEXT_BASE=' + TextBase
     LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_mini2440.map,-cref,-u,_start  -nostartfiles -T mini2440_ram.ld' + ' -Ttext ' + TextBase
 
+    # module setting 
+    CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
+    M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
+    M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
+                                    ' -shared -fPIC -nostartfiles -static-libgcc'
+    M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
+
     CPATH = ''
     LPATH = ''
 
diff --git a/libcpu/arm/s3c24x0/serial.c b/libcpu/arm/s3c24x0/serial.c
deleted file mode 100644
index 1eca1b1110..0000000000
--- a/libcpu/arm/s3c24x0/serial.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-03-13     Bernard      first version
- * 2009-04-20     yi.qiu      modified according bernard's stm32 version
- */
-
-#include <rtthread.h>
-
-#include "serial.h"
-
-/**
- * @addtogroup S3C24X0
- */
-/*@{*/
-
-/* RT-Thread Device Interface */
-/**
- * This function initializes serial
- */
-static rt_err_t rt_serial_init(rt_device_t dev)
-{
-    struct serial_device* uart = (struct serial_device*) dev->user_data;
-
-    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-    {
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-        {
-            rt_memset(uart->int_rx->rx_buffer, 0,
-                      sizeof(uart->int_rx->rx_buffer));
-            uart->int_rx->read_index = uart->int_rx->save_index = 0;
-        }
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-        {
-            rt_memset(uart->int_tx->tx_buffer, 0,
-                      sizeof(uart->int_tx->tx_buffer));
-            uart->int_tx->write_index = uart->int_tx->save_index = 0;
-        }
-
-        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-    }
-
-    return RT_EOK;
-}
-
-/* save a char to serial buffer */
-static void rt_serial_savechar(struct serial_device* uart, char ch)
-{
-    rt_base_t level;
-
-    /* disable interrupt */
-    level = rt_hw_interrupt_disable();
-
-    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
-    uart->int_rx->save_index ++;
-    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
-        uart->int_rx->save_index = 0;
-
-    /* if the next position is read index, discard this 'read char' */
-    if (uart->int_rx->save_index == uart->int_rx->read_index)
-    {
-        uart->int_rx->read_index ++;
-        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-            uart->int_rx->read_index = 0;
-    }
-
-    /* enable interrupt */
-    rt_hw_interrupt_enable(level);
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    return RT_EOK;
-}
-
-static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-    rt_uint8_t* ptr;
-    rt_err_t err_code;
-    struct serial_device* uart;
-
-    ptr = buffer;
-    err_code = RT_EOK;
-    uart = (struct serial_device*)dev->user_data;
-
-    if (ptr == RT_NULL)
-    {
-        err_code = -RT_ENOMEM;
-        rt_set_errno(err_code);
-        return -RT_ENOMEM;
-    }
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        rt_base_t level;
-
-        /* interrupt mode Rx */
-        while (size)
-        {
-            if (uart->int_rx->read_index != uart->int_rx->save_index)
-            {
-                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
-                size --;
-
-                /* disable interrupt */
-                level = rt_hw_interrupt_disable();
-
-                uart->int_rx->read_index ++;
-                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-                    uart->int_rx->read_index = 0;
-
-                /* enable interrupt */
-                rt_hw_interrupt_enable(level);
-            }
-            else
-            {
-                /* set error code */
-                err_code = -RT_EEMPTY;
-                break;
-            }
-        }
-    }
-    else
-    {
-        /* polling mode */
-        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-        {
-            while (uart->uart_device->ustat & USTAT_RCV_READY)
-            {
-                *ptr = uart->uart_device->urxh & 0xff;
-                ptr ++;
-            }
-        }
-    }
-
-    /* set error code */
-    rt_set_errno(err_code);
-    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-    rt_uint8_t* ptr;
-    rt_err_t err_code;
-    struct serial_device* uart;
-
-    err_code = RT_EOK;
-    ptr = (rt_uint8_t*)buffer;
-    uart = (struct serial_device*)dev->user_data;
-
-    if (ptr == RT_NULL)
-    {
-        err_code = -RT_ENOMEM;
-        rt_set_errno(err_code);
-        return -RT_ENOMEM;
-    }
-    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-    {
-        /* interrupt mode Tx */
-        while (uart->int_tx->save_index != uart->int_tx->write_index)
-        {
-            /* save on tx buffer */
-            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
-
-            -- size;
-
-            /* move to next position */
-            uart->int_tx->save_index ++;
-
-            /* wrap save index */
-            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
-                uart->int_tx->save_index = 0;
-        }
-
-        /* set error code */
-        if (size > 0)
-            err_code = -RT_EFULL;
-    }
-    else
-    {
-        /* polling mode */
-        while (size)
-        {
-            /*
-             * to be polite with serial console add a line feed
-             * to the carriage return character
-             */
-            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
-            {
-                while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
-                uart->uart_device->utxh = '\r';
-            }
-
-            while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
-            uart->uart_device->utxh = (*ptr & 0xFF);
-
-            ++ptr;
-            --size;
-        }
-    }
-
-    /* set error code */
-    rt_set_errno(err_code);
-    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_SUSPEND:
-        /* suspend device */
-        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-        break;
-
-    case RT_DEVICE_CTRL_RESUME:
-        /* resume device */
-        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-        break;
-    }
-
-    return RT_EOK;
-}
-
-/*
- * serial register
- */
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
-{
-    RT_ASSERT(device != RT_NULL);
-
-    device->type        = RT_Device_Class_Char;
-    device->rx_indicate = RT_NULL;
-    device->tx_complete = RT_NULL;
-    device->init        = rt_serial_init;
-    device->open        = rt_serial_open;
-    device->close       = rt_serial_close;
-    device->read        = rt_serial_read;
-    device->write       = rt_serial_write;
-    device->control     = rt_serial_control;
-    device->user_data   = serial;
-
-    /* register a character device */
-    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
-}
-
-/* ISR for serial interrupt */
-void rt_hw_serial_isr(rt_device_t device)
-{
-    struct serial_device* uart = (struct serial_device*) device->user_data;
-
-    /* interrupt mode receive */
-    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
-
-    /* save on rx buffer */
-    while (uart->uart_device->ustat & USTAT_RCV_READY)
-    {
-        rt_serial_savechar(uart, uart->uart_device->urxh & 0xff);
-    }
-
-    /* invoke callback */
-    if (device->rx_indicate != RT_NULL)
-    {
-        rt_size_t rx_length;
-
-        /* get rx length */
-        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
-                    UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
-                    uart->int_rx->save_index - uart->int_rx->read_index;
-
-        device->rx_indicate(device, rx_length);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/arm/s3c24x0/serial.h b/libcpu/arm/s3c24x0/serial.h
deleted file mode 100644
index 8a647ef35f..0000000000
--- a/libcpu/arm/s3c24x0/serial.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#ifndef __RT_HW_SERIAL_H__
-#define __RT_HW_SERIAL_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "s3c24x0.h"
-
-#define	USTAT_RCV_READY		0x01   	/* receive data ready */ 
-#define	USTAT_TXB_EMPTY		0x02   	/* tx buffer empty */
-#define BPS					115200	/* serial baudrate */
-
-#define UART_RX_BUFFER_SIZE		64
-#define UART_TX_BUFFER_SIZE		64
-
-struct serial_int_rx
-{
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
-};
-
-struct serial_int_tx
-{
-	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
-	rt_uint32_t write_index, save_index;
-};
-
-typedef struct uartport
-{
-	volatile rt_uint32_t ulcon;
-	volatile rt_uint32_t ucon;
-	volatile rt_uint32_t ufcon;
-	volatile rt_uint32_t umcon;
-	volatile rt_uint32_t ustat;
-	volatile rt_uint32_t urxb;
-	volatile rt_uint32_t ufstat;
-	volatile rt_uint32_t umstat;
-	volatile rt_uint32_t utxh;	
-	volatile rt_uint32_t urxh;	
-	volatile rt_uint32_t ubrd;
-}uartport;
-
-struct serial_device
-{
-	uartport* uart_device;
-	
-	/* rx structure */
-	struct serial_int_rx* int_rx;
-
-	/* tx structure */
-	struct serial_int_tx* int_tx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
-
-void rt_hw_serial_isr(rt_device_t device);
-
-#endif
-- 
cgit v1.3.1


From fb8c7829a8a861f9837912ecf926899f48349967 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 16 Apr 2020 16:10:57 +0800
Subject: add raspi4 bsp

---
 bsp/raspberry-pi/raspi4/.config                 | 455 ++++++++++++++++++++++++
 bsp/raspberry-pi/raspi4/Kconfig                 |  29 ++
 bsp/raspberry-pi/raspi4/README.md               | 100 ++++++
 bsp/raspberry-pi/raspi4/SConscript              |  14 +
 bsp/raspberry-pi/raspi4/SConstruct              |  30 ++
 bsp/raspberry-pi/raspi4/applications/SConscript |   9 +
 bsp/raspberry-pi/raspi4/applications/main.c     |  19 +
 bsp/raspberry-pi/raspi4/driver/Kconfig          |  97 +++++
 bsp/raspberry-pi/raspi4/driver/SConscript       |   9 +
 bsp/raspberry-pi/raspi4/driver/board.c          |  98 +++++
 bsp/raspberry-pi/raspi4/driver/board.h          |  25 ++
 bsp/raspberry-pi/raspi4/driver/drv_gpio.c       | 117 ++++++
 bsp/raspberry-pi/raspi4/driver/drv_gpio.h       |  79 ++++
 bsp/raspberry-pi/raspi4/driver/drv_uart.c       | 158 ++++++++
 bsp/raspberry-pi/raspi4/driver/drv_uart.h       |  84 +++++
 bsp/raspberry-pi/raspi4/driver/iomap.h          |  13 +
 bsp/raspberry-pi/raspi4/link.lds                | 153 ++++++++
 bsp/raspberry-pi/raspi4/rtconfig.h              | 179 ++++++++++
 bsp/raspberry-pi/raspi4/rtconfig.py             |  51 +++
 libcpu/aarch64/SConscript                       |   3 +
 libcpu/aarch64/common/SConscript                |  24 ++
 libcpu/aarch64/common/armv8.h                   |  63 ++++
 libcpu/aarch64/common/cache.S                   | 151 ++++++++
 libcpu/aarch64/common/context_gcc.S             | 351 ++++++++++++++++++
 libcpu/aarch64/common/cp15.h                    | 166 +++++++++
 libcpu/aarch64/common/cpu.c                     |  91 +++++
 libcpu/aarch64/common/cpu_gcc.S                 |  82 +++++
 libcpu/aarch64/common/gic/SConscript            |  24 ++
 libcpu/aarch64/common/gic/gic_pl400.c           | 368 +++++++++++++++++++
 libcpu/aarch64/common/gic/gic_pl400.h           |  35 ++
 libcpu/aarch64/common/mmu.c                     | 367 +++++++++++++++++++
 libcpu/aarch64/common/mmu.h                     |  78 ++++
 libcpu/aarch64/common/startup_gcc.S             |  13 +
 libcpu/aarch64/common/vector_gcc.S              |  61 ++++
 libcpu/aarch64/cortex-a53/SConscript            |  15 +-
 libcpu/aarch64/cortex-a53/armv8.h               |  63 ----
 libcpu/aarch64/cortex-a53/cache.S               | 151 --------
 libcpu/aarch64/cortex-a53/context_gcc.S         | 351 ------------------
 libcpu/aarch64/cortex-a53/cp15.h                | 166 ---------
 libcpu/aarch64/cortex-a53/cpu.c                 |  91 -----
 libcpu/aarch64/cortex-a53/cpu_gcc.S             |  82 -----
 libcpu/aarch64/cortex-a53/interrupt.h           |   6 +-
 libcpu/aarch64/cortex-a53/mmu.c                 | 367 -------------------
 libcpu/aarch64/cortex-a53/mmu.h                 |  78 ----
 libcpu/aarch64/cortex-a53/startup_gcc.S         |  13 -
 libcpu/aarch64/cortex-a53/vector_gcc.S          |  61 ----
 libcpu/aarch64/cortex-a57/SConscript            |  13 +
 libcpu/aarch64/cortex-a57/entry_point.S         | 111 ++++++
 libcpu/aarch64/cortex-a57/interrupt.c           |  73 ++++
 libcpu/aarch64/cortex-a57/interrupt.h           |  27 ++
 libcpu/aarch64/cortex-a57/stack.c               |  90 +++++
 libcpu/aarch64/cortex-a57/trap.c                |  98 +++++
 52 files changed, 4016 insertions(+), 1436 deletions(-)
 create mode 100644 bsp/raspberry-pi/raspi4/.config
 create mode 100644 bsp/raspberry-pi/raspi4/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi4/README.md
 create mode 100644 bsp/raspberry-pi/raspi4/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4/SConstruct
 create mode 100644 bsp/raspberry-pi/raspi4/applications/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4/applications/main.c
 create mode 100644 bsp/raspberry-pi/raspi4/driver/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi4/driver/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4/driver/board.c
 create mode 100644 bsp/raspberry-pi/raspi4/driver/board.h
 create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_gpio.c
 create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_gpio.h
 create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_uart.c
 create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_uart.h
 create mode 100644 bsp/raspberry-pi/raspi4/driver/iomap.h
 create mode 100644 bsp/raspberry-pi/raspi4/link.lds
 create mode 100644 bsp/raspberry-pi/raspi4/rtconfig.h
 create mode 100644 bsp/raspberry-pi/raspi4/rtconfig.py
 create mode 100644 libcpu/aarch64/common/SConscript
 create mode 100644 libcpu/aarch64/common/armv8.h
 create mode 100644 libcpu/aarch64/common/cache.S
 create mode 100644 libcpu/aarch64/common/context_gcc.S
 create mode 100644 libcpu/aarch64/common/cp15.h
 create mode 100644 libcpu/aarch64/common/cpu.c
 create mode 100644 libcpu/aarch64/common/cpu_gcc.S
 create mode 100644 libcpu/aarch64/common/gic/SConscript
 create mode 100644 libcpu/aarch64/common/gic/gic_pl400.c
 create mode 100644 libcpu/aarch64/common/gic/gic_pl400.h
 create mode 100644 libcpu/aarch64/common/mmu.c
 create mode 100644 libcpu/aarch64/common/mmu.h
 create mode 100644 libcpu/aarch64/common/startup_gcc.S
 create mode 100644 libcpu/aarch64/common/vector_gcc.S
 delete mode 100644 libcpu/aarch64/cortex-a53/armv8.h
 delete mode 100644 libcpu/aarch64/cortex-a53/cache.S
 delete mode 100644 libcpu/aarch64/cortex-a53/context_gcc.S
 delete mode 100644 libcpu/aarch64/cortex-a53/cp15.h
 delete mode 100644 libcpu/aarch64/cortex-a53/cpu.c
 delete mode 100644 libcpu/aarch64/cortex-a53/cpu_gcc.S
 delete mode 100644 libcpu/aarch64/cortex-a53/mmu.c
 delete mode 100644 libcpu/aarch64/cortex-a53/mmu.h
 delete mode 100644 libcpu/aarch64/cortex-a53/startup_gcc.S
 delete mode 100644 libcpu/aarch64/cortex-a53/vector_gcc.S
 create mode 100644 libcpu/aarch64/cortex-a57/SConscript
 create mode 100644 libcpu/aarch64/cortex-a57/entry_point.S
 create mode 100644 libcpu/aarch64/cortex-a57/interrupt.c
 create mode 100644 libcpu/aarch64/cortex-a57/interrupt.h
 create mode 100644 libcpu/aarch64/cortex-a57/stack.c
 create mode 100644 libcpu/aarch64/cortex-a57/trap.c

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi4/.config b/bsp/raspberry-pi/raspi4/.config
new file mode 100644
index 0000000000..e300d0217b
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/.config
@@ -0,0 +1,455 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_CPU_64BIT=y
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_MPLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+# CONFIG_PKG_USING_JS_PERSIMMON is not set
+# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RDBD_SRC is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_RTX is not set
+# CONFIG_RT_USING_TESTCASE is not set
+# CONFIG_PKG_USING_NGHTTP2 is not set
+# CONFIG_PKG_USING_AVS is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_STS is not set
+# CONFIG_PKG_USING_DLMS is not set
+# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
+# CONFIG_PKG_USING_ZBAR is not set
+CONFIG_BCM2711_SOC=y
+# CONFIG_BSP_SUPPORT_FPU is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# BCM Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART0=y
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GIC400=y
+# CONFIG_BSP_USING_GIC500 is not set
+CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_CORETIMER=y
+# CONFIG_BSP_USING_SYSTIMER is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SDIO is not set
+
+#
+# Board Peripheral Drivers
+#
+# CONFIG_BSP_USING_HDMI is not set
diff --git a/bsp/raspberry-pi/raspi4/Kconfig b/bsp/raspberry-pi/raspi4/Kconfig
new file mode 100644
index 0000000000..e71ed3d54b
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/Kconfig
@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2711_SOC
+    bool
+    select ARCH_ARM_CORTEX_A57
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_CPU_64BIT
+    default y
+
+source "driver/Kconfig"
diff --git a/bsp/raspberry-pi/raspi4/README.md b/bsp/raspberry-pi/raspi4/README.md
new file mode 100644
index 0000000000..28e00f96c0
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/README.md
@@ -0,0 +1,100 @@
+# Raspberry PI 3-64板级支持包说明
+
+## 1. 简介
+
+树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3有三个发行版本：
+
+* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz，双核VideoCore IV GPU，1GB内存，100 Base-T Ethernet
+* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM， GigaE over USB 2.0
+* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM
+
+这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+
+## 2. 编译说明
+
+### 2.1 Window上的环境搭建
+
+Windows环境下推荐使用[env工具][1]进行编译。
+
+首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
+
+将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
+
+接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py`
+
+修改路径：
+
+```
+EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
+```
+
+然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。
+
+### 2.2 Linux上的环境搭建
+
+Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
+
+直接进入`bsp\raspberry-pi\raspi3-64`，输入scons编译即可。
+
+
+## 3. 执行
+
+### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
+
+Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
+
+解开下载的镜像文件, linux下使用如下的命令
+
+```
+unzip 2018-06-27-raspbian-stretch-lite.zip
+```
+
+准备一张空SD卡，linux环境下，插入电脑并执行
+
+```
+sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
+```
+
+**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
+
+Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
+
+最后把kernel8.img放入SD boot分区，删除其它 kernel*.img。
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示(图片中的板子是pi2，GPIO引脚是一样的)：
+
+![raspi2](figures/raspi_uart.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+按上面的方法做好SD卡后，插入树莓派，通电可以在串口上看到如下所示的输出信息：
+
+```text
+ heap: 0x00020b20 - 0x00400000
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     3.1.0 build Aug 23 2019
+ 2006 - 2019 Copyright by rt-thread team
+Hello RT-Thread!
+msh >
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+[1]: https://www.rt-thread.org/page/download.html
+[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
+[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+[4]: https://etcher.io
+[5]: https://github.com/BernardXiong
diff --git a/bsp/raspberry-pi/raspi4/SConscript b/bsp/raspberry-pi/raspi4/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/raspberry-pi/raspi4/SConstruct b/bsp/raspberry-pi/raspi4/SConstruct
new file mode 100644
index 0000000000..93f349aab8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/SConstruct
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)
+
diff --git a/bsp/raspberry-pi/raspi4/applications/SConscript b/bsp/raspberry-pi/raspi4/applications/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi4/applications/main.c b/bsp/raspberry-pi/raspi4/applications/main.c
new file mode 100644
index 0000000000..9664e67d01
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hi, this is RT-Thread!!\n");
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi4/driver/Kconfig b/bsp/raspberry-pi/raspi4/driver/Kconfig
new file mode 100644
index 0000000000..208b4b4300
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/Kconfig
@@ -0,0 +1,97 @@
+
+config BSP_SUPPORT_FPU
+    bool "Using Float"
+    default n
+
+menu "Hardware Drivers Config"
+    menu "BCM Peripheral Drivers"
+        menuconfig BSP_USING_UART
+            bool "Using UART"
+            select RT_USING_SERIAL
+            default y
+
+            if BSP_USING_UART
+                config RT_USING_UART0
+                bool "Enabel UART 0"
+                default y
+            endif
+            
+        menuconfig BSP_USING_GIC
+            bool "Enable GIC"
+            select RT_USING_GIC
+            default y
+        if BSP_USING_GIC
+            config BSP_USING_GIC400
+                bool "Enable GIC400"
+                default y
+            config BSP_USING_GIC500
+                bool "Enable GIC500"
+                default n
+        endif
+
+        config BSP_USING_PIN
+            bool "Using PIN"
+            select RT_USING_PIN
+            default y
+
+        config BSP_USING_CORETIMER
+            bool "Using core timer"
+            select RT_USING_CORETIMER
+            default y
+
+        menuconfig BSP_USING_SYSTIMER
+            bool "Enable SYSTIMER"
+            select BSP_USING_SYSTIMER
+            default n
+
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
+        endif
+
+        config BSP_USING_WDT
+            bool "Enable WDT"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+
+        if BSP_USING_RTC
+            config BSP_USING_ALARM
+                bool "Enable Alarm"
+                select RT_USING_ALARM
+                default n
+        endif
+        
+        menuconfig BSP_USING_SDIO
+            bool "Enable SDIO"
+            select RT_USING_SDIO
+            default n
+
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO0
+                bool "Enable SDIO0"
+                select RT_USING_SDIO
+                default n
+        endif
+    endmenu
+
+    menu "Board Peripheral Drivers"
+        menuconfig BSP_USING_HDMI
+            bool "Enable HDMI"
+            default n
+
+        if BSP_USING_HDMI
+            config BSP_USING_HDMI_DISPLAY
+                bool "HDMI DISPLAY"
+                default n
+        endif
+    endmenu
+endmenu
diff --git a/bsp/raspberry-pi/raspi4/driver/SConscript b/bsp/raspberry-pi/raspi4/driver/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi4/driver/board.c b/bsp/raspberry-pi/raspi4/driver/board.c
new file mode 100644
index 0000000000..9716755b72
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/board.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include "cp15.h"
+#include "mmu.h"
+
+static rt_uint64_t timerStep;
+// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
+#define CORE0_TIMER_IRQ_CTRL    HWREG32(0xFF800040)
+#define TIMER_IRQ               30
+#define NON_SECURE_TIMER_IRQ    (1 << 1)
+
+int rt_hw_get_gtimer_frq(void);
+void rt_hw_set_gtimer_val(rt_uint64_t value);
+int rt_hw_get_gtimer_val(void);
+int rt_hw_get_cntpct_val(void);
+void rt_hw_gtimer_enable(void);
+
+void core0_timer_enable_interrupt_controller()
+{
+    CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
+}
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    rt_hw_set_gtimer_val(timerStep);
+    rt_tick_increase();
+}
+
+void rt_hw_timer_init(void)
+{
+    rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(TIMER_IRQ);
+    __ISB();
+    timerStep = rt_hw_get_gtimer_frq();
+    __DSB();
+    timerStep /= RT_TICK_PER_SECOND;
+    
+    rt_hw_gtimer_enable();
+    rt_hw_set_gtimer_val(timerStep);
+    core0_timer_enable_interrupt_controller();
+}
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+/**
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  after interrupt disabled.
+ */
+void rt_hw_board_init(void)
+{
+    mmu_init();
+    armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
+    armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio
+    armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer
+    mmu_enable();
+
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
+    rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
+
+    /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
+
+    /* initialize uart */
+    rt_hw_uart_init();      // driver/drv_uart.c
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
\ No newline at end of file
diff --git a/bsp/raspberry-pi/raspi4/driver/board.h b/bsp/raspberry-pi/raspi4/driver/board.h
new file mode 100644
index 0000000000..66805464f2
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/board.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
+
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4/driver/drv_gpio.c
new file mode 100644
index 0000000000..4317a358e0
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/drv_gpio.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_PIN
+
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+{
+    uint32_t fselnum = pin / 10;
+    uint32_t fselrest = pin % 10;
+
+    uint32_t gpfsel = 0;
+    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
+    gpfsel |= (uint32_t)(mode << (fselrest * 3));
+
+    switch (fselnum)
+    {
+    case 0:
+        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
+        break;
+    case 1:
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+        break;
+    case 2:
+        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
+        break;
+    case 3:
+        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
+        break;
+    case 4:
+        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
+        break;
+    case 5:
+        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
+        break;
+    default:
+        break;
+    }
+}
+
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+{
+    uint32_t num = pin / 32;
+
+    if(num == 0)
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
+        }
+    }
+    else
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        
+    }
+}
+
+static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+{
+    return 0;
+}
+
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    return RT_EOK;
+}
+
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    return RT_EOK;
+}
+
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    return RT_EOK;
+}
+
+static const struct rt_pin_ops ops =
+{
+    raspi_pin_mode,
+    raspi_pin_write,
+    raspi_pin_read,
+    raspi_pin_attach_irq,
+    raspi_pin_detach_irq,
+    raspi_pin_irq_enable,
+};
+#endif
+
+int rt_hw_gpio_init(void)
+{
+#ifdef BSP_USING_PIN
+    rt_device_pin_register("gpio", &ops, RT_NULL);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gpio_init);
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h
new file mode 100644
index 0000000000..ebc9452cec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "interrupt.h"
+
+#define GPIO_BASE (0xFE000000 + 0x00200000)
+
+#define GPIO_REG_GPFSEL0(BASE)             HWREG32(BASE + 0x00)
+#define GPIO_REG_GPFSEL1(BASE)             HWREG32(BASE + 0x04)
+#define GPIO_REG_GPFSEL2(BASE)             HWREG32(BASE + 0x08)
+#define GPIO_REG_GPFSEL3(BASE)             HWREG32(BASE + 0x0C)
+#define GPIO_REG_GPFSEL4(BASE)             HWREG32(BASE + 0x10)
+#define GPIO_REG_GPFSEL5(BASE)             HWREG32(BASE + 0x14)
+#define GPIO_REG_REV0(BASE)                HWREG32(BASE + 0x18)
+#define GPIO_REG_GPSET0(BASE)              HWREG32(BASE + 0x1C)
+#define GPIO_REG_GPSET1(BASE)              HWREG32(BASE + 0x20)
+#define GPIO_REG_REV1(BASE)                HWREG32(BASE + 0x24)
+#define GPIO_REG_GPCLR0(BASE)              HWREG32(BASE + 0x28)
+#define GPIO_REG_GPCLR1(BASE)              HWREG32(BASE + 0x2C)
+#define GPIO_REG_REV2(BASE)                HWREG32(BASE + 0x30)
+#define GPIO_REG_GPLEV0(BASE)              HWREG32(BASE + 0x34)
+#define GPIO_REG_GPLEV1(BASE)              HWREG32(BASE + 0x38)
+#define GPIO_REG_REV3(BASE)                HWREG32(BASE + 0x3C)
+#define GPIO_REG_GPEDS0(BASE)              HWREG32(BASE + 0x40)
+#define GPIO_REG_GPEDS1(BASE)              HWREG32(BASE + 0x44)
+#define GPIO_REG_REV4(BASE)                HWREG32(BASE + 0x48)
+#define GPIO_REG_GPREN0(BASE)              HWREG32(BASE + 0x4C)
+#define GPIO_REG_GPREN1(BASE)              HWREG32(BASE + 0x50)
+#define GPIO_REG_REV5(BASE)                HWREG32(BASE + 0x54)
+#define GPIO_REG_GPFEN0(BASE)              HWREG32(BASE + 0x58)
+#define GPIO_REG_GPFEN1(BASE)              HWREG32(BASE + 0x5C)
+#define GPIO_REG_REV6(BASE)                HWREG32(BASE + 0x60)
+#define GPIO_REG_GPHEN0(BASE)              HWREG32(BASE + 0x64)
+#define GPIO_REG_GPHEN1(BASE)              HWREG32(BASE + 0x68)
+#define GPIO_REG_REV7(BASE)                HWREG32(BASE + 0x6C)
+#define GPIO_REG_GPLEN0(BASE)              HWREG32(BASE + 0x70)
+#define GPIO_REG_GPLEN1(BASE)              HWREG32(BASE + 0x74)
+#define GPIO_REG_REV8(BASE)                HWREG32(BASE + 0x78)
+#define GPIO_REG_GPAREN0(BASE)             HWREG32(BASE + 0x7C)
+#define GPIO_REG_GPAREN1(BASE)             HWREG32(BASE + 0x80)
+#define GPIO_REG_REV11(BASE)               HWREG32(BASE + 0x84)
+#define GPIO_REG_GPAFEN0(BASE)             HWREG32(BASE + 0x88)
+#define GPIO_REG_GPAFEN1(BASE)             HWREG32(BASE + 0x8C)
+#define GPIO_REG_REV10(BASE)               HWREG32(BASE + 0x90)
+#define GPIO_REG_GPPUD(BASE)               HWREG32(BASE + 0x94)
+#define GPIO_REG_GPPUDCLK0(BASE)           HWREG32(BASE + 0x98)
+#define GPIO_REG_GPPUDCLK1(BASE)           HWREG32(BASE + 0x9C)
+#define GPIO_REG_REV9(BASE)                HWREG32(BASE + 0xA0)
+#define GPIO_REG_TEST(BASE)                HWREG32(BASE + 0xA4)
+
+typedef enum {
+    INPUT = 0b000,
+    OUTPUT = 0b001,
+    ALT0 = 0b100,
+    ALT1 = 0b101,
+    ALT2 = 0b110,
+    ALT3 = 0b111,
+    ALT4 = 0b011,
+    ALT5 = 0b010
+} GPIO_FUNC;
+
+
+int rt_hw_gpio_init(void);
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.c b/bsp/raspberry-pi/raspi4/driver/drv_uart.c
new file mode 100644
index 0000000000..a7ac1b5892
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/drv_uart.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+
+#define UART0_BASE            (0xFE000000 + 0x00201000)
+#define PL011_BASE            UART0_BASE
+#define IRQ_PL011             (121 + 32)
+
+#define UART_REFERENCE_CLOCK 48000000
+
+struct hw_uart_device
+{
+    rt_ubase_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+    uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16;
+    uint32_t ibrd = bauddiv / 1000;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+    if(uart->hw_base == PL011_BASE)
+    {
+        uint32_t gpfsel = 0;
+
+        gpfsel &= ~((uint32_t)(0x07 << (4 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (4 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        gpfsel &= ~((uint32_t)(0x07 << (5 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (5 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
+        PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
+        PL011_REG_IBRD(uart->hw_base) = ibrd;
+        PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
+        PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
+        PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM);
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
+    PL011_REG_DR(uart->hw_base) = (uint8_t)c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
+    {
+        ch = PL011_REG_DR(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
+}
+
+
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    PL011_BASE,
+    IRQ_PL011,
+};
+
+static struct rt_serial_device _serial0;
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart");
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.h b/bsp/raspberry-pi/raspi4/driver/drv_uart.h
new file mode 100644
index 0000000000..4f23d7b46e
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/drv_uart.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+// register's bit
+#define PL011_FR_RI          (1 << 8)
+#define PL011_FR_TXFE        (1 << 7)
+#define PL011_FR_RXFF        (1 << 6)
+#define PL011_FR_TXFF        (1 << 5)
+#define PL011_FR_RXFE        (1 << 4)
+#define PL011_FR_BUSY        (1 << 3)
+#define PL011_FR_DCD         (1 << 2)
+#define PL011_FR_DSR         (1 << 1)
+#define PL011_FR_CTS         (1 << 0)
+
+#define PL011_LCRH_SPS       (1 << 7)
+#define PL011_LCRH_WLEN_8    (3 << 5)
+#define PL011_LCRH_WLEN_7    (2 << 5)
+#define PL011_LCRH_WLEN_6    (1 << 5)
+#define PL011_LCRH_WLEN_5    (0 << 5)
+#define PL011_LCRH_FEN       (1 << 4)
+#define PL011_LCRH_STP2      (1 << 3)
+#define PL011_LCRH_EPS       (1 << 2)
+#define PL011_LCRH_PEN       (1 << 1)
+#define PL011_LCRH_BRK       (1 << 0)
+
+#define PL011_CR_CTSEN       (1 << 15)
+#define PL011_CR_RTSEN       (1 << 14)
+#define PL011_CR_RTS         (1 << 11)
+#define PL011_CR_DTR         (1 << 10)
+#define PL011_CR_RXE         (1 << 9)
+#define PL011_CR_TXE         (1 << 8)
+#define PL011_CR_LBE         (1 << 7)
+#define PL011_CR_SIRLP       (1 << 2)
+#define PL011_CR_SIREN       (1 << 1)
+#define PL011_CR_UARTEN      (1 << 0)
+
+#define PL011_IMSC_TXIM      (1 << 5)
+#define PL011_IMSC_RXIM      (1 << 4)
+
+#define PL011_INTERRUPT_OVERRUN_ERROR   (1 << 10)
+#define PL011_INTERRUPT_BREAK_ERROR     (1 << 9)
+#define PL011_INTERRUPT_PARITY_ERROR    (1 << 8)
+#define PL011_INTERRUPT_FRAMING_ERROR   (1 << 7)
+#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
+#define PL011_INTERRUPT_TRANSMIT        (1 << 5)
+#define PL011_INTERRUPT_RECEIVE         (1 << 4)
+#define PL011_INTERRUPT_nUARTCTS        (1 << 1)
+
+#define PL011_REG_DR(BASE)              HWREG32(BASE + 0x00)
+#define PL011_REG_RSRECR(BASE)          HWREG32(BASE + 0x04)
+#define PL011_REG_RESERVED0(BASE)       HWREG32(BASE + 0x08)
+#define PL011_REG_FR(BASE)              HWREG32(BASE + 0x18)
+#define PL011_REG_RESERVED1(BASE)       HWREG32(BASE + 0x1C)
+#define PL011_REG_ILPR(BASE)            HWREG32(BASE + 0x20)
+#define PL011_REG_IBRD(BASE)            HWREG32(BASE + 0x24)
+#define PL011_REG_FBRD(BASE)            HWREG32(BASE + 0x28)
+#define PL011_REG_LCRH(BASE)            HWREG32(BASE + 0x2C)
+#define PL011_REG_CR(BASE)              HWREG32(BASE + 0x30)
+#define PL011_REG_IFLS(BASE)            HWREG32(BASE + 0x34)
+#define PL011_REG_IMSC(BASE)            HWREG32(BASE + 0x38)
+#define PL011_REG_RIS(BASE)             HWREG32(BASE + 0x3C)
+#define PL011_REG_MIS(BASE)             HWREG32(BASE + 0x40)
+#define PL011_REG_ICR(BASE)             HWREG32(BASE + 0x44)
+#define PL011_REG_DMACR(BASE)           HWREG32(BASE + 0x48)
+#define PL011_REG_RESERVED2(BASE)       HWREG32(BASE + 0x4C)
+#define PL011_REG_ITCR(BASE)            HWREG32(BASE + 0x80)
+#define PL011_REG_ITIP(BASE)            HWREG32(BASE + 0x84)
+#define PL011_REG_ITOP(BASE)            HWREG32(BASE + 0x88)
+#define PL011_REG_TDR(BASE)             HWREG32(BASE + 0x8C)
+
+int rt_hw_uart_init(void);
+
+#endif /* DRV_UART_H__ */
+
diff --git a/bsp/raspberry-pi/raspi4/driver/iomap.h b/bsp/raspberry-pi/raspi4/driver/iomap.h
new file mode 100644
index 0000000000..00fc2025d9
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/iomap.h
@@ -0,0 +1,13 @@
+#ifndef __RASPI4_H__
+#define __RASPI4_H__
+
+#define INTC_BASE   0xff800000
+#define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
+#define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
+#define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
+#define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
+
+#define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
+#define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
+
+#endif
\ No newline at end of file
diff --git a/bsp/raspberry-pi/raspi4/link.lds b/bsp/raspberry-pi/raspi4/link.lds
new file mode 100644
index 0000000000..b7b2dcc32c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/link.lds
@@ -0,0 +1,153 @@
+/*
+ * File      : link.lds
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
+
+SECTIONS
+{
+    . = 0x80000;
+    . = ALIGN(4096);
+    .text :
+    {
+        KEEP(*(.text.entrypoint))       /* The entry point */
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        *(COMMON)
+        
+        /* section information for finsh shell */
+        . = ALIGN(16);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(16);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(16);
+
+        /* section information for initial. */
+        . = ALIGN(16);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(16);
+
+        . = ALIGN(16);
+        _etext = .;
+    }
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(16);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(16);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(16);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        
+        PROVIDE(__bss_end = .);
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
+__bss_size = (__bss_end - __bss_start)>>3;
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.h b/bsp/raspberry-pi/raspi4/rtconfig.h
new file mode 100644
index 0000000000..049e117559
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/rtconfig.h
@@ -0,0 +1,179 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 2048
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40003
+#define ARCH_CPU_64BIT
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Privated Packages of RealThread */
+
+
+/* Network Utilities */
+
+#define BCM2711_SOC
+
+/* Hardware Drivers Config */
+
+/* BCM Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART0
+#define BSP_USING_GIC
+#define BSP_USING_GIC400
+#define BSP_USING_PIN
+#define BSP_USING_CORETIMER
+
+/* Board Peripheral Drivers */
+
+
+#endif
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py
new file mode 100644
index 0000000000..228ec0176a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/rtconfig.py
@@ -0,0 +1,51 @@
+import os
+
+# toolchains options
+ARCH        ='aarch64'
+CPU         ='cortex-a57'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    # PREFIX = 'arm-none-eabi-'
+    PREFIX = 'aarch64-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv8-a -mtune=cortex-a57'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/libcpu/aarch64/SConscript b/libcpu/aarch64/SConscript
index 453afe4b3e..5fca2b473b 100644
--- a/libcpu/aarch64/SConscript
+++ b/libcpu/aarch64/SConscript
@@ -9,6 +9,9 @@ cwd   = GetCurrentDir()
 group = []
 list  = os.listdir(cwd)
 
+# add common code files
+group = group + SConscript(os.path.join('common', 'SConscript'))
+
 # cpu porting code files
 if rtconfig.CPU != 'common':
     group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript
new file mode 100644
index 0000000000..72fb8e26c3
--- /dev/null
+++ b/libcpu/aarch64/common/SConscript
@@ -0,0 +1,24 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
+
+# build for sub-directory
+list = os.listdir(cwd)
+objs = []
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+group = group + objs
+
+
+Return('group')
diff --git a/libcpu/aarch64/common/armv8.h b/libcpu/aarch64/common/armv8.h
new file mode 100644
index 0000000000..4350890544
--- /dev/null
+++ b/libcpu/aarch64/common/armv8.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __ARMV8_H__
+#define __ARMV8_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long long pc;
+	unsigned long long spsr;
+	unsigned long long x30;
+	unsigned long long xz;
+	unsigned long long x28;
+	unsigned long long x29;
+	unsigned long long x26;
+	unsigned long long x27;
+	unsigned long long x24;
+	unsigned long long x25;
+	unsigned long long x22;
+	unsigned long long x23;
+	unsigned long long x20;
+	unsigned long long x21;
+	unsigned long long x18;	
+	unsigned long long x19;
+	unsigned long long x16;
+	unsigned long long x17;
+	unsigned long long x14;
+	unsigned long long x15;
+	unsigned long long x12;
+	unsigned long long x13;
+	unsigned long long x10;
+	unsigned long long x11;
+	unsigned long long x8;
+	unsigned long long x9;
+	unsigned long long x6;
+	unsigned long long x7;
+	unsigned long long x4;
+	unsigned long long x5;
+	unsigned long long x2;
+	unsigned long long x3;
+	unsigned long long x0;
+	unsigned long long x1;
+};
+
+#define SP_ELx						( ( unsigned long long ) 0x01 )
+#define SP_EL0						( ( unsigned long long ) 0x00 )
+#define PSTATE_EL1					( ( unsigned long long ) 0x04 )
+#define PSTATE_EL2					( ( unsigned long long ) 0x08 )
+#define PSTATE_EL3					( ( unsigned long long ) 0x0c )
+
+rt_ubase_t rt_hw_get_current_el(void);
+void rt_hw_set_elx_env(void);
+void rt_hw_set_current_vbar(rt_ubase_t addr);
+
+#endif
diff --git a/libcpu/aarch64/common/cache.S b/libcpu/aarch64/common/cache.S
new file mode 100644
index 0000000000..7f295a2b02
--- /dev/null
+++ b/libcpu/aarch64/common/cache.S
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2020-03-17     bigmagic           first version
+ */
+
+/*
+ * void __asm_dcache_level(level)
+ *
+ * flush or invalidate one level cache.
+ *
+ * x0: cache level
+ * x1: 0 clean & invalidate, 1 invalidate only
+ * x2~x9: clobbered
+ */
+.globl __asm_dcache_level
+__asm_dcache_level:
+    lsl    x12, x0, #1
+    msr    csselr_el1, x12        /* select cache level */
+    isb                /* sync change of cssidr_el1 */
+    mrs    x6, ccsidr_el1        /* read the new cssidr_el1 */
+    and    x2, x6, #7        /* x2 <- log2(cache line size)-4 */
+    add    x2, x2, #4        /* x2 <- log2(cache line size) */
+    mov    x3, #0x3ff
+    and    x3, x3, x6, lsr #3    /* x3 <- max number of #ways */
+    clz    w5, w3            /* bit position of #ways */
+    mov    x4, #0x7fff
+    and    x4, x4, x6, lsr #13    /* x4 <- max number of #sets */
+    /* x12 <- cache level << 1 */
+    /* x2 <- line length offset */
+    /* x3 <- number of cache ways - 1 */
+    /* x4 <- number of cache sets - 1 */
+    /* x5 <- bit position of #ways */
+
+loop_set:
+    mov    x6, x3            /* x6 <- working copy of #ways */
+loop_way:
+    lsl    x7, x6, x5
+    orr    x9, x12, x7        /* map way and level to cisw value */
+    lsl    x7, x4, x2
+    orr    x9, x9, x7        /* map set number to cisw value */
+    tbz    w1, #0, 1f
+    dc    isw, x9
+    b    2f
+1:    dc    cisw, x9        /* clean & invalidate by set/way */
+2:    subs    x6, x6, #1        /* decrement the way */
+    b.ge    loop_way
+    subs    x4, x4, #1        /* decrement the set */
+    b.ge    loop_set
+
+    ret
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 clean & invalidate, 1 invalidate only
+ *
+ * flush or invalidate all data cache by SET/WAY.
+ */
+.globl __asm_dcache_all
+__asm_dcache_all:
+    mov    x1, x0
+    dsb    sy
+    mrs    x10, clidr_el1        /* read clidr_el1 */
+    lsr    x11, x10, #24
+    and    x11, x11, #0x7        /* x11 <- loc */
+    cbz    x11, finished        /* if loc is 0, exit */
+    mov    x15, lr
+    mov    x0, #0            /* start flush at cache level 0 */
+    /* x0  <- cache level */
+    /* x10 <- clidr_el1 */
+    /* x11 <- loc */
+    /* x15 <- return address */
+
+loop_level:
+    lsl    x12, x0, #1
+    add    x12, x12, x0        /* x0 <- tripled cache level */
+    lsr    x12, x10, x12
+    and    x12, x12, #7        /* x12 <- cache type */
+    cmp    x12, #2
+    b.lt    skip            /* skip if no cache or icache */
+    bl    __asm_dcache_level    /* x1 = 0 flush, 1 invalidate */
+skip:
+    add    x0, x0, #1        /* increment cache level */
+    cmp    x11, x0
+    b.gt    loop_level
+
+    mov    x0, #0
+    msr    csselr_el1, x0        /* restore csselr_el1 */
+    dsb    sy
+    isb
+    mov    lr, x15
+
+finished:
+    ret
+
+.globl __asm_flush_dcache_all
+__asm_flush_dcache_all:
+    mov    x0, #0
+    b    __asm_dcache_all
+
+.globl __asm_invalidate_dcache_all
+__asm_invalidate_dcache_all:
+    mov    x0, #0x1
+    b    __asm_dcache_all
+
+/*
+ * void __asm_flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+.globl __asm_flush_dcache_range
+__asm_flush_dcache_range:
+    mrs    x3, ctr_el0
+    lsr    x3, x3, #16
+    and    x3, x3, #0xf
+    mov    x2, #4
+    lsl    x2, x2, x3        /* cache line size */
+
+    /* x2 <- minimal cache line size in cache system */
+    sub    x3, x2, #1
+    bic    x0, x0, x3
+1:    dc    civac, x0    /* clean & invalidate data or unified cache */
+    add    x0, x0, x2
+    cmp    x0, x1
+    b.lo    1b
+    dsb    sy
+    ret
+
+/*
+ * void __asm_invalidate_icache_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+.globl __asm_invalidate_icache_all
+__asm_invalidate_icache_all:
+    ic    ialluis
+    isb    sy
+    ret
+
+.globl __asm_flush_l3_cache
+__asm_flush_l3_cache:
+    mov    x0, #0            /* return status as success */
+    ret
\ No newline at end of file
diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S
new file mode 100644
index 0000000000..934db7ed84
--- /dev/null
+++ b/libcpu/aarch64/common/context_gcc.S
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+  /*
+ *enable gtimer
+ */
+.globl rt_hw_gtimer_enable
+rt_hw_gtimer_enable:
+	MOV X0,#1
+	MSR CNTP_CTL_EL0,X0
+	RET
+
+/*
+ *set gtimer CNTP_TVAL_EL0 value
+ */
+.globl rt_hw_set_gtimer_val
+rt_hw_set_gtimer_val:
+	MSR CNTP_TVAL_EL0,X0
+	RET
+
+/*
+ *get gtimer CNTP_TVAL_EL0 value
+ */
+.globl rt_hw_get_gtimer_val
+rt_hw_get_gtimer_val:
+	MRS X0,CNTP_TVAL_EL0
+	RET
+
+
+.globl rt_hw_get_cntpct_val
+rt_hw_get_cntpct_val:
+	MRS X0, CNTPCT_EL0
+	RET
+
+/*
+ *get gtimer frq value
+ */
+.globl rt_hw_get_gtimer_frq
+rt_hw_get_gtimer_frq:
+	MRS X0,CNTFRQ_EL0
+	RET
+
+.macro SAVE_CONTEXT
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Save the entire context. */
+    STP 	X0, X1, [SP, #-0x10]!
+    STP 	X2, X3, [SP, #-0x10]!
+    STP 	X4, X5, [SP, #-0x10]!
+    STP 	X6, X7, [SP, #-0x10]!
+    STP 	X8, X9, [SP, #-0x10]!
+    STP 	X10, X11, [SP, #-0x10]!
+    STP 	X12, X13, [SP, #-0x10]!
+    STP 	X14, X15, [SP, #-0x10]!
+    STP 	X16, X17, [SP, #-0x10]!
+    STP 	X18, X19, [SP, #-0x10]!
+    STP 	X20, X21, [SP, #-0x10]!
+    STP 	X22, X23, [SP, #-0x10]!
+    STP 	X24, X25, [SP, #-0x10]!
+    STP 	X26, X27, [SP, #-0x10]!
+    STP 	X28, X29, [SP, #-0x10]!
+    STP 	X30, XZR, [SP, #-0x10]!
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MRS		X3, SPSR_EL3
+    /* Save the ELR. */
+    MRS		X2, ELR_EL3
+    B		0f
+2:
+    MRS		X3, SPSR_EL2
+    /* Save the ELR. */
+    MRS		X2, ELR_EL2
+    B		0f
+1:
+    MRS		X3, SPSR_EL1
+    MRS		X2, ELR_EL1
+    B		0f
+0:
+
+    STP 	X2, X3, [SP, #-0x10]!
+
+    MOV 	X0, SP   /* Move SP into X0 for saving. */
+
+    /* Switch to use the ELx stack pointer. */
+    MSR 	SPSEL, #1
+
+    .endm
+
+.macro SAVE_CONTEXT_T
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Save the entire context. */
+    STP 	X0, X1, [SP, #-0x10]!
+    STP 	X2, X3, [SP, #-0x10]!
+    STP 	X4, X5, [SP, #-0x10]!
+    STP 	X6, X7, [SP, #-0x10]!
+    STP 	X8, X9, [SP, #-0x10]!
+    STP 	X10, X11, [SP, #-0x10]!
+    STP 	X12, X13, [SP, #-0x10]!
+    STP 	X14, X15, [SP, #-0x10]!
+    STP 	X16, X17, [SP, #-0x10]!
+    STP 	X18, X19, [SP, #-0x10]!
+    STP 	X20, X21, [SP, #-0x10]!
+    STP 	X22, X23, [SP, #-0x10]!
+    STP 	X24, X25, [SP, #-0x10]!
+    STP 	X26, X27, [SP, #-0x10]!
+    STP 	X28, X29, [SP, #-0x10]!
+    STP 	X30, XZR, [SP, #-0x10]!
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MRS		X3, SPSR_EL3
+    MOV		X2, X30
+    B		0f
+2:
+    MRS		X3, SPSR_EL2
+    MOV		X2, X30
+    B		0f
+1:
+    MRS		X3, SPSR_EL1
+    MOV		X2, X30
+    B		0f
+0:
+
+    STP 	X2, X3, [SP, #-0x10]!
+
+    MOV 	X0, SP   /* Move SP into X0 for saving. */
+
+    /* Switch to use the ELx stack pointer. */
+    MSR 	SPSEL, #1
+
+    .endm
+
+.macro RESTORE_CONTEXT
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Set the SP to point to the stack of the task being restored. */
+    MOV		SP, X0
+
+    LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MSR		SPSR_EL3, X3
+    MSR		ELR_EL3, X2
+    B		0f
+2:
+    MSR		SPSR_EL2, X3
+    MSR		ELR_EL2, X2
+    B		0f
+1:
+    MSR		SPSR_EL1, X3
+    MSR		ELR_EL1, X2
+    B		0f
+0:
+
+    LDP 	X30, XZR, [SP], #0x10
+    LDP 	X28, X29, [SP], #0x10
+    LDP 	X26, X27, [SP], #0x10
+    LDP 	X24, X25, [SP], #0x10
+    LDP 	X22, X23, [SP], #0x10
+    LDP 	X20, X21, [SP], #0x10
+    LDP 	X18, X19, [SP], #0x10
+    LDP 	X16, X17, [SP], #0x10
+    LDP 	X14, X15, [SP], #0x10
+    LDP 	X12, X13, [SP], #0x10
+    LDP 	X10, X11, [SP], #0x10
+    LDP 	X8, X9, [SP], #0x10
+    LDP 	X6, X7, [SP], #0x10
+    LDP 	X4, X5, [SP], #0x10
+    LDP 	X2, X3, [SP], #0x10
+    LDP 	X0, X1, [SP], #0x10
+
+    /* Switch to use the ELx stack pointer.  _RB_ Might not be required. */
+    MSR 	SPSEL, #1
+
+    ERET
+
+    .endm
+
+.text
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    MRS      X0, DAIF
+    MSR      DAIFSet, #3
+    DSB      SY
+    RET
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    DSB     SY
+    MOV     X1, #0xC0
+    ANDS    X0, X0, X1
+    B.NE    rt_hw_interrupt_enable_exit
+    MSR     DAIFClr, #3
+rt_hw_interrupt_enable_exit:
+    RET
+
+/*
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    LDR		X0, [X0]
+    RESTORE_CONTEXT
+
+.text
+/*
+ * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+
+    MOV		X8,X0
+    MOV		X9,X1
+
+    SAVE_CONTEXT_T
+    
+    STR		X0, [X8]            // store sp in preempted tasks TCB
+    LDR		X0, [X9]            // get new task stack pointer
+    
+    RESTORE_CONTEXT
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ADR 	X2, rt_thread_switch_interrupt_flag
+    LDR 	X3, [X2]
+    CMP 	X3, #1
+    B.EQ 	_reswitch
+    ADR 	X4, rt_interrupt_from_thread   // set rt_interrupt_from_thread
+    MOV 	X3, #1              // set rt_thread_switch_interrupt_flag to 1
+    STR 	X0, [X4]
+    STR 	X3, [X2]
+_reswitch:
+    ADR 	X2, rt_interrupt_to_thread     // set rt_interrupt_to_thread
+    STR 	X1, [X2]
+    RET
+
+.text
+
+// -- Exception handlers ----------------------------------
+
+    .align  8
+.globl vector_fiq
+vector_fiq:
+    SAVE_CONTEXT
+    STP 	X0, X1, [SP, #-0x10]!
+    BL      rt_hw_trap_fiq
+    LDP 	X0, X1, [SP], #0x10
+    RESTORE_CONTEXT
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+
+// -------------------------------------------------------------------
+
+    .align  8
+.globl vector_irq
+vector_irq:
+    SAVE_CONTEXT
+    STP 	X0, X1, [SP, #-0x10]!
+
+    BL      rt_interrupt_enter
+    BL      rt_hw_trap_irq
+    BL      rt_interrupt_leave
+    
+    LDP 	X0, X1, [SP], #0x10
+
+    // if rt_thread_switch_interrupt_flag set, jump to
+    // rt_hw_context_switch_interrupt_do and don't return
+    ADR 	X1, rt_thread_switch_interrupt_flag
+    LDR     X2, [X1]
+    CMP     X2, #1
+    B.NE     vector_irq_exit
+
+    MOV     X2,  #0         // clear flag
+    STR     X2,  [X1]
+
+    ADR     X3,  rt_interrupt_from_thread
+    LDR     X4,  [X3]
+    STR     x0,  [X4]       // store sp in preempted tasks's TCB
+
+    ADR     x3,  rt_interrupt_to_thread
+    LDR     X4,  [X3]
+    LDR     x0,  [X4]       // get new task's stack pointer
+    
+vector_irq_exit:	
+    RESTORE_CONTEXT
+
+// -------------------------------------------------
+
+    .align  8
+    .globl  vector_error
+vector_error:
+    SAVE_CONTEXT
+    BL      rt_hw_trap_error
+    B       .
diff --git a/libcpu/aarch64/common/cp15.h b/libcpu/aarch64/common/cp15.h
new file mode 100644
index 0000000000..f3ffd6f857
--- /dev/null
+++ b/libcpu/aarch64/common/cp15.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __CP15_H__
+#define __CP15_H__
+
+#ifndef   __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
+#endif
+
+#define __WFI()    __asm__ volatile ("wfi":::"memory")
+
+#define __WFE()    __asm__ volatile ("wfe":::"memory")
+
+#define __SEV()    __asm__ volatile ("sev")
+
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+    __asm__ volatile ("isb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+    __asm__ volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+    __asm__ volatile ("dmb 0xF":::"memory");
+}
+
+#ifdef RT_USING_SMP
+static inline void send_ipi_msg(int cpu, int ipi_vector)
+{
+    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
+}
+
+static inline void setup_bootstrap_addr(int cpu, int addr)
+{
+	CORE_MAILBOX3_SET(cpu) = addr;
+}
+
+static inline void enable_cpu_ipi_intr(int cpu)
+{
+    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
+}
+
+static inline void enable_cpu_timer_intr(int cpu)
+{
+	CORETIMER_INTCTL(cpu) = 0x8;
+}
+
+static inline void enable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline void disable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 0;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline  void mask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 2;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline void unmask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline rt_uint64_t read_cntvct(void)
+{
+    rt_uint32_t val,val1;
+    asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
+    return (val);
+}
+
+static inline rt_uint64_t read_cntvoff(void)
+{
+
+    rt_uint64_t val;
+    asm volatile("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
+    return (val);
+}
+
+static inline rt_uint32_t read_cntv_tval(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val) );
+    return val;
+}
+
+
+static inline  void write_cntv_tval(rt_uint32_t val)
+{
+    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val) );
+    return;
+}
+
+static inline rt_uint32_t read_cntfrq(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val) );
+    return val;
+}
+
+
+static inline  rt_uint32_t read_cntctrl(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val) );
+    return val;
+}
+
+static inline uint32_t write_cntctrl(uint32_t val)
+{
+
+    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val) );
+    return val;
+}
+#endif
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_dcache_clean_flush(void);
+void rt_cpu_icache_flush(void);
+
+void rt_cpu_vector_set_base(rt_ubase_t addr);
+void rt_hw_mmu_init(void);
+void rt_hw_vector_init(void);
+
+void set_timer_counter(unsigned int counter);
+void set_timer_control(unsigned int control);
+#endif
diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c
new file mode 100644
index 0000000000..962a53a071
--- /dev/null
+++ b/libcpu/aarch64/common/cpu.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+#include "cp15.h"
+
+int rt_hw_cpu_id(void)
+{
+    int cpu_id;
+    rt_base_t value;
+
+    __asm__ volatile (
+            "mrs %0, mpidr_el1"
+            :"=r"(value)
+            );
+    cpu_id = value & 0xf;
+    return cpu_id;
+};
+
+#ifdef RT_USING_SMP
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    lock->slock = 0;
+}
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    unsigned long tmp;
+    unsigned long newval;
+    rt_hw_spinlock_t lockval;
+    __asm__ __volatile__(
+            "pld [%0]"
+            ::"r"(&lock->slock)
+            );
+
+    __asm__ __volatile__(
+            "1: ldrex   %0, [%3]\n"
+            "   add %1, %0, %4\n"
+            "   strex   %2, %1, [%3]\n"
+            "   teq %2, #0\n"
+            "   bne 1b"
+            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+            : "r" (&lock->slock), "I" (1 << 16)
+            : "cc");
+
+    while (lockval.tickets.next != lockval.tickets.owner) {
+        __WFE();
+        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
+    }
+
+    __DMB();
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    __DMB();
+    lock->tickets.owner++;
+    __DSB();
+    __SEV();
+}
+#endif /*RT_USING_SMP*/
+
+/**
+ * @addtogroup ARM CPU
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/*@}*/
diff --git a/libcpu/aarch64/common/cpu_gcc.S b/libcpu/aarch64/common/cpu_gcc.S
new file mode 100644
index 0000000000..b8c8b8768c
--- /dev/null
+++ b/libcpu/aarch64/common/cpu_gcc.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+ 
+.text
+.globl rt_hw_get_current_el
+rt_hw_get_current_el:
+	MRS		X0, CurrentEL
+	CMP		X0, 0xc
+	B.EQ	3f
+	CMP		X0, 0x8
+	B.EQ	2f
+	CMP		X0, 0x4
+	B.EQ	1f
+	
+	LDR		X0, =0
+	B		0f
+3:
+	LDR		X0, =3
+	B		0f
+2:
+	LDR		X0, =2
+	B		0f
+1:
+	LDR		X0, =1
+	B		0f
+0:
+	RET
+
+
+.globl rt_hw_set_current_vbar
+rt_hw_set_current_vbar:
+	MRS		X1, CurrentEL
+	CMP		X1, 0xc
+	B.EQ	3f
+	CMP		X1, 0x8
+	B.EQ	2f
+	CMP		X1, 0x4
+	B.EQ	1f
+	B		0f
+3:
+	MSR		VBAR_EL3,X0
+	B		0f
+2:
+	MSR		VBAR_EL2,X0
+	B		0f
+1:
+	MSR		VBAR_EL1,X0
+	B		0f
+0:
+	RET
+
+    
+.globl rt_hw_set_elx_env
+rt_hw_set_elx_env:
+	MRS		X1, CurrentEL
+	CMP		X1, 0xc
+	B.EQ	3f
+	CMP		X1, 0x8
+	B.EQ	2f
+	CMP		X1, 0x4
+	B.EQ	1f
+	B		0f
+3:
+	MRS		X0, SCR_EL3
+	ORR		X0, X0, #0xF			/* SCR_EL3.NS|IRQ|FIQ|EA */
+	MSR		SCR_EL3, X0
+	B		0f
+2:
+	MRS	X0, HCR_EL2
+	ORR	X0, X0, #0x38
+	MSR	HCR_EL2, X0
+	B		0f
+1:
+	B		0f
+0:
+	RET
diff --git a/libcpu/aarch64/common/gic/SConscript b/libcpu/aarch64/common/gic/SConscript
new file mode 100644
index 0000000000..b114ba7678
--- /dev/null
+++ b/libcpu/aarch64/common/gic/SConscript
@@ -0,0 +1,24 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+
+gic400_group = Split('''
+gic_pl400.c
+''')
+
+gic500_group = Split('''
+gic_pl500.c
+''')
+
+src = ()
+if GetDepend('BSP_USING_GIC400'):
+	src = gic400_group
+if GetDepend('BSP_USING_GIC500'):
+	src = gic500_group
+
+group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c
new file mode 100644
index 0000000000..eb35c5b2a4
--- /dev/null
+++ b/libcpu/aarch64/common/gic/gic_pl400.c
@@ -0,0 +1,368 @@
+/*
+ * Copyright 2014, General Dynamics C4 Systems
+ *
+ * This software may be distributed and modified according to the terms of
+ * the GNU General Public License version 2. Note that NO WARRANTY is provided.
+ * See "LICENSE_GPLv2.txt" for details.
+ *
+ * @TAG(GD_GPL)
+ */
+
+#include "gic_pl400.h"
+#include "iomap.h"
+
+#define BIT(n) (1ul<<(n))
+#define MASK(n) (BIT(n)-1ul)
+
+/* Setters/getters helpers */
+#define IRQ_REG(IRQ) ((IRQ) / 32)
+#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
+#define IRQ_MASK MASK(10)
+#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < SPECIAL_IRQ_START)
+
+#define CPU(X) (1<<(X))
+#define TARGET_CPU_ALLINT(CPU) ( \
+        ( ((CPU)&0xff)<<0  ) |\
+        ( ((CPU)&0xff)<<8  ) |\
+        ( ((CPU)&0xff)<<16 ) |\
+        ( ((CPU)&0xff)<<24 ) \
+    )
+#define TARGET_CPU0_ALLINT   TARGET_CPU_ALLINT(CPU(0))
+
+
+#define IRQ_SET_ALL 0xffffffff;
+
+/* Special IRQ's */
+#define SPECIAL_IRQ_START 1020
+#define IRQ_NONE          1023
+
+/* Memory map for GIC distributor */
+struct gic_dist_map {
+    uint32_t enable;                /* 0x000 */
+    uint32_t ic_type;               /* 0x004 */
+    uint32_t dist_ident;            /* 0x008 */
+    uint32_t res1[29];              /* [0x00C, 0x080) */
+
+    uint32_t group[32];          /* [0x080, 0x100) */
+
+    uint32_t enable_set[32];        /* [0x100, 0x180) */
+    uint32_t enable_clr[32];        /* [0x180, 0x200) */
+    uint32_t pending_set[32];       /* [0x200, 0x280) */
+    uint32_t pending_clr[32];       /* [0x280, 0x300) */
+    uint32_t active[32];            /* [0x300, 0x380) */
+    uint32_t active_clr[32];        /* [0x380, 0x400) */
+
+    uint32_t priority[255];         /* [0x400, 0x7FC) */
+    uint32_t res2;                  /* 0x7FC */
+
+    uint32_t targets[255];          /* [0x800, 0xBFC) */
+    uint32_t res3;                  /* 0xBFC */
+
+    uint32_t config[64];             /* [0xC00, 0xD00) */
+
+    uint32_t ppi_status;            /* [0xD00, 0xD04) */
+    uint32_t spi_status[15];        /* [0xD04, 0xD40) */
+    uint32_t res4[112];              /* [0xD40, 0xF00) */
+
+    uint32_t sgi_control;           /* 0xF00 */
+    uint32_t res5[3];               /* [0xF04, 0xF10) */
+    uint32_t sgi_pending_clr[4];    /* [0xF10, 0xF20) */
+    uint32_t sgi_pending_set[4];    /* [0xF20, 0xF30) */
+    uint32_t res10[40];             /* [0xF30, 0xFD0) */
+
+    uint32_t periph_id[8];         /* [0xFD0, 0xFF0) */
+    uint32_t component_id[4];       /* [0xFF0, 0xFFF] */
+};
+
+
+/* Memory map for GIC  cpu interface */
+struct gic_cpu_iface_map {
+    uint32_t icontrol;              /*  0x000         */
+    uint32_t pri_msk_c;             /*  0x004         */
+    uint32_t bp_c;                  /*  0x008         */
+    uint32_t int_ack;               /*  0x00C         */
+    uint32_t eoi;                   /*  0x010         */
+    uint32_t run_priority;          /*  0x014         */
+    uint32_t hi_pend;               /*  0x018         */
+    uint32_t ns_alias_bp_c;         /*  0x01C         */
+    uint32_t ns_alias_ack;          /*  0x020 GIC_PL400 only */
+    uint32_t ns_alias_eoi;          /*  0x024 GIC_PL400 only */
+    uint32_t ns_alias_hi_pend;      /*  0x028 GIC_PL400 only */
+
+    uint32_t res1[41];              /* [0x02C, 0x0D0) */
+    uint32_t active_priority[4];    /* [0x0D0, 0xC0] GIC_PL400 only */
+    uint32_t ns_active_priority[4]; /* [0xE0,0xF0] GIC_PL400 only */
+    uint32_t res4[3];               /* [0xF0, 0xFC] */
+
+    uint32_t cpu_if_ident;          /*  0x0FC         */
+    uint32_t deactive;              /* [0x1000] */
+};
+
+volatile struct gic_dist_map *gic_dist =
+    (volatile struct gic_dist_map*)(GIC_PL400_DISTRIBUTOR_PPTR);
+
+volatile struct gic_cpu_iface_map *gic_cpuiface =
+    (volatile struct gic_cpu_iface_map*)(GIC_PL400_CONTROLLER_PPTR);
+
+/* Helpers */
+static inline int
+is_irq_pending(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    return !!(gic_dist->pending_set[word] & BIT(bit));
+}
+
+static inline int
+is_irq_active(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    return !!(gic_dist->active[word] & BIT(bit));
+}
+
+static inline int
+is_irq_enabled(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    return !!(gic_dist->enable_set[word] & BIT(bit));
+}
+
+static inline int
+is_irq_edge_triggered(irq_t irq)
+{
+    int word = irq / 16;
+    int bit = ((irq & 0xf) * 2);
+    return !!(gic_dist->config[word] & BIT(bit + 1));
+}
+
+static inline int
+is_irq_1_N(irq_t irq)
+{
+    int word = irq / 16;
+    int bit = ((irq & 0xf) * 2);
+    return !!(gic_dist->config[word] & BIT(bit + 0));
+}
+
+static inline int
+is_irq_N_N(irq_t irq)
+{
+    return !(is_irq_1_N(irq));
+}
+
+static inline void
+dist_pending_clr(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    /* Using |= here is detrimental to your health */
+    gic_dist->pending_clr[word] = BIT(bit);
+}
+
+static inline void
+dist_pending_set(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    gic_dist->pending_set[word] = BIT(bit);
+}
+
+static inline void
+dist_enable_clr(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    /* Using |= here is detrimental to your health */
+    gic_dist->enable_clr[word] = BIT(bit);
+}
+
+static inline void
+dist_enable_set(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    gic_dist->enable_set[word] = BIT(bit);
+}
+
+/**
+   DONT_TRANSLATE
+ */
+static void dist_init(void)
+{
+    int i;
+    int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
+    gic_dist->enable = 0;
+
+#if 0
+    /* configure to group 0 for security */
+    for (i = 0; i < nirqs; i += 32) {
+        gic_dist->group[i / 32] = 0xffffffff;
+    }
+#endif
+
+    for (i = 0; i < nirqs; i += 32) {
+        /* disable */
+        gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
+        /* clear pending */
+        gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
+    }
+
+    /* reset interrupts priority */
+    for (i = 32; i < nirqs; i += 4) {
+        gic_dist->priority[i / 4] = 0x0;
+    }
+
+    /*
+     * reset int target to cpu 0
+     * (Should really query which processor we're running on and use that)
+     */
+    for (i = 0; i < nirqs; i += 4) {
+        gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
+    }
+
+    /* level-triggered, 1-N */
+    for (i = 64; i < nirqs; i += 32) {
+        gic_dist->config[i / 32] = 0;
+        //gic_dist->config[i / 32] = 0x55555555;
+    }
+    /* enable the int controller */
+    gic_dist->enable = 1;
+}
+
+/**
+   DONT_TRANSLATE
+ */
+static void cpu_iface_init(void)
+{
+    uint32_t i;
+
+    /* For non-Exynos4, the registers are banked per CPU, need to clear them */
+    gic_dist->enable_clr[0] = IRQ_SET_ALL;
+    gic_dist->pending_clr[0] = IRQ_SET_ALL;
+    gic_dist->priority[0] = 0x00;
+    /* put everything in group 0 */
+
+    /* clear any software generated interrupts */
+    for (i = 0; i < 16; i += 4) {
+        gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
+    }
+
+    gic_cpuiface->icontrol = 0;
+    gic_cpuiface->pri_msk_c = 0x000000f0;
+    gic_cpuiface->bp_c = 0x00000003;
+
+    while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != IRQ_NONE) {
+        gic_cpuiface->eoi = i;
+    }
+    gic_cpuiface->icontrol = 0x1;
+}
+
+/**
+   DONT_TRANSLATE
+ */
+void initIRQController(void)
+{
+    dist_init();
+    cpu_iface_init();
+}
+
+
+
+/*
+ * The only sane way to get an GIC IRQ number that can be properly
+ * ACKED later is through the int_ack register. Unfortunately, reading
+ * this register changes the interrupt state to pending so future
+ * reads will not return the same value For this reason, we have a
+ * global variable to store the IRQ number.
+ */
+static uint32_t active_irq = IRQ_NONE;
+
+/**
+   DONT_TRANSLATE
+ */
+interrupt_t
+getActiveIRQ(void)
+{
+    uint32_t irq;
+    if (!IS_IRQ_VALID(active_irq)) {
+        active_irq = gic_cpuiface->int_ack;
+    }
+
+    if (IS_IRQ_VALID(active_irq)) {
+        irq = active_irq & IRQ_MASK;
+    } else {
+        irq = 1023;
+    }
+
+    return irq;
+}
+
+/*
+ * GIC has 4 states: pending->active(+pending)->inactive
+ * seL4 expects two states: active->inactive.
+ * We ignore the active state in GIC to conform
+ */
+/**
+   DONT_TRANSLATE
+ */
+bool_t
+isIRQPending(void)
+{
+    return IS_IRQ_VALID(gic_cpuiface->hi_pend);
+}
+
+
+/**
+   DONT_TRANSLATE
+ */
+void
+maskInterrupt(bool_t disable, interrupt_t irq)
+{
+    if (disable) {
+        dist_enable_clr(irq);
+    } else {
+        dist_enable_set(irq);
+    }
+}
+
+/**
+   DONT_TRANSLATE
+ */
+void
+ackInterrupt(irq_t irq)
+{
+    if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq)) {
+		return;
+	}
+    if (is_irq_edge_triggered(irq)) {
+        dist_pending_clr(irq);
+    }
+    gic_cpuiface->eoi = active_irq;
+    active_irq = IRQ_NONE;
+}
+
+void
+handleSpuriousIRQ(void)
+{
+}
+
+void rt_hw_interrupt_mask(int vector)
+{
+    maskInterrupt(1, vector);
+}
+
+void rt_hw_interrupt_umask(int vector)
+{
+    maskInterrupt(0, vector);
+}
+
+int rt_hw_interrupt_get_irq(void)
+{
+    return getActiveIRQ();
+}
+
+void rt_hw_interrupt_ack(int fiq_irq)
+{
+    return ackInterrupt(fiq_irq);
+}
diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h
new file mode 100644
index 0000000000..a43583bd7c
--- /dev/null
+++ b/libcpu/aarch64/common/gic/gic_pl400.h
@@ -0,0 +1,35 @@
+
+#ifndef __ARCH_MACHINE_GIC_PL400_H
+#define __ARCH_MACHINE_GIC_PL400_H
+
+#include <stdint.h>
+
+typedef uint16_t interrupt_t;
+typedef uint16_t irq_t;
+typedef uint64_t  bool_t;
+
+/** MODIFIES: [*] */
+interrupt_t getActiveIRQ(void);
+/** MODIFIES: [*] */
+interrupt_t getPendingIRQ(void);
+/** MODIFIES: [*] */
+bool_t isIRQPending(void);
+/** MODIFIES: [*] */
+void maskInterrupt(bool_t disable, interrupt_t irq);
+/** MODIFIES: [*] */
+void ackInterrupt(irq_t irq);
+/** MODIFIES: [*] */
+static inline void setInterruptMode(irq_t irq, bool_t levelTrigger, bool_t polarityLow) { }
+
+/** MODIFIES: [*] */
+void initIRQController(void);
+
+void handleSpuriousIRQ(void);
+
+void rt_hw_interrupt_umask(int vector);
+
+int rt_hw_interrupt_get_irq(void);
+
+void rt_hw_interrupt_ack(int fiq_irq);
+#endif /* !__ARCH_MACHINE_GIC400_H */
+
diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c
new file mode 100644
index 0000000000..b799143084
--- /dev/null
+++ b/libcpu/aarch64/common/mmu.c
@@ -0,0 +1,367 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2020-02-20     bigmagic           first version
+ */
+#include <mmu.h>
+#include <stddef.h>
+#include <rthw.h>
+
+#define TTBR_CNP    1
+
+typedef unsigned long int    uint64_t;
+
+static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
+
+#define IS_ALIGNED(x, a)        (((x) & ((typeof(x))(a) - 1)) == 0)
+
+#define PMD_TYPE_SECT        (1 << 0)
+
+#define PMD_TYPE_TABLE        (3 << 0)
+
+#define PTE_TYPE_PAGE        (3 << 0)
+
+#define BITS_PER_VA          39
+
+/* Granule size of 4KB is being used */
+#define GRANULE_SIZE_SHIFT         12
+#define GRANULE_SIZE               (1 << GRANULE_SIZE_SHIFT)
+#define XLAT_ADDR_MASK             ((1UL << BITS_PER_VA) - GRANULE_SIZE)
+
+#define PMD_TYPE_MASK               (3 << 0)
+
+int free_idx = 1;
+
+void __asm_invalidate_icache_all(void);
+void __asm_flush_dcache_all(void);
+int __asm_flush_l3_cache(void);
+void __asm_flush_dcache_range(unsigned long long start, unsigned long long end);
+void __asm_invalidate_dcache_all(void);
+void __asm_invalidate_icache_all(void);
+
+void mmu_memset(char *dst, char v,  size_t len)
+{
+    while (len--)
+    {
+        *dst++ = v;
+    }
+}
+
+static unsigned long __page_off = 0;
+static unsigned long get_free_page(void) 
+{
+    __page_off += 512;
+    return (unsigned long)(main_tbl + __page_off);
+}
+
+
+static inline unsigned int get_sctlr(void)
+{
+    unsigned int val;
+    asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+    return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+    asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+    asm volatile("isb");
+}
+
+void mmu_init(void)
+{
+    unsigned long val64;
+    unsigned long val32;
+
+    val64 = 0x007f6eUL;
+    __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
+    __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
+
+    //TCR_EL1
+    val32 = (16UL << 0)//48bit
+        | (0x0UL << 6)
+        | (0x0UL << 7)
+        | (0x3UL << 8)
+        | (0x3UL << 10)//Inner Shareable
+        | (0x2UL << 12)
+        | (0x0UL << 14)//4K
+        | (0x0UL << 16)
+        | (0x0UL << 22)
+        | (0x1UL << 23)
+        | (0x2UL << 30)
+        | (0x1UL << 32)
+        | (0x0UL << 35)
+        | (0x0UL << 36)
+        | (0x0UL << 37)
+        | (0x0UL << 38);
+    __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32));
+    __asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32));
+
+    __asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
+    __asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
+
+    mmu_memset((char *)main_tbl, 0, 4096);
+}
+
+void mmu_enable(void)
+{
+    unsigned long val64;
+    unsigned long val32;
+
+    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
+    val64 &= ~0x1000; //disable I
+    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
+
+    __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
+    __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
+
+    //SCTLR_EL1, turn on mmu
+    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
+    val32 |= 0x1005; //enable mmu, I C M
+    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
+    rt_hw_icache_enable();
+    rt_hw_dcache_enable();
+
+}
+
+static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
+{
+    int level;
+    unsigned long* cur_lv_tbl = lv0_tbl;
+    unsigned long page;
+    unsigned long off;
+    int level_shift = 39;
+
+    if (va & (0x200000UL - 1)) 
+    {
+        return MMU_MAP_ERROR_VANOTALIGN;
+    }
+    if (pa & (0x200000UL - 1)) 
+    {
+        return MMU_MAP_ERROR_PANOTALIGN;
+    }
+    for (level = 0; level < 2; level++) 
+    {
+        off = (va >> level_shift);
+        off &= MMU_LEVEL_MASK;
+        if ((cur_lv_tbl[off] & 1) == 0) 
+        {
+            page = get_free_page();
+            if (!page) 
+            {
+                return MMU_MAP_ERROR_NOPAGE;
+            }
+            mmu_memset((char *)page, 0, 4096);
+            cur_lv_tbl[off] = page | 0x3UL;
+        }
+        page = cur_lv_tbl[off];
+        if (!(page & 0x2)) 
+        {
+            //is block! error!
+            return MMU_MAP_ERROR_CONFLICT;
+        }
+        cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
+        level_shift -= 9;
+    }
+    attr &= 0xfff0000000000ffcUL;
+    pa |= (attr | 0x1UL); //block
+    off = (va >> 21);
+    off &= MMU_LEVEL_MASK;
+    cur_lv_tbl[off] = pa;
+    return 0;
+}
+
+int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr)
+{
+    int i;
+    int ret;
+
+    if (va & (0x200000 - 1))
+    {
+        return -1;
+    }
+    if (pa & (0x200000 - 1))
+    {
+        return -1;
+    }
+    for (i = 0; i < count; i++)
+    {
+        ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr);
+        va += 0x200000;
+        pa += 0x200000;
+        if (ret != 0)
+        {
+            return ret;
+        }
+    }
+    return 0;
+}
+
+static void set_table(uint64_t *pt, uint64_t *table_addr)
+{
+    uint64_t val;
+    val = (0x3UL | (uint64_t)table_addr);
+    *pt = val;
+}
+
+void mmu_memset2(unsigned char *dst, char v,  int len)
+{
+    while (len--)
+    {
+        *dst++ = v;
+    }
+}
+
+static uint64_t *create_table(void)
+{
+    uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE;
+    /* Mark all entries as invalid */
+    mmu_memset2((unsigned char *)new_table, 0, 4096);
+    free_idx++;
+    return new_table;
+}
+
+static int pte_type(uint64_t *pte)
+{
+    return *pte & PMD_TYPE_MASK;
+}
+
+static int level2shift(int level)
+{
+    /* Page is 12 bits wide, every level translates 9 bits */
+    return (12 + 9 * (3 - level));
+}
+
+static uint64_t *get_level_table(uint64_t *pte)
+{
+    uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
+    
+    if (pte_type(pte) != PMD_TYPE_TABLE) 
+    {
+        table = create_table();
+        set_table(pte, table);
+    }
+    return table;
+}
+
+static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
+{
+    uint64_t block_size = 0;
+    uint64_t block_shift = 0;
+    uint64_t *pte;
+    uint64_t idx = 0;
+    uint64_t addr = 0;
+    uint64_t *table = 0;
+    int level = 0;
+
+    addr = virt;
+    while (size) 
+    {
+        table = &main_tbl[0];
+        for (level = 0; level < 4; level++) 
+        {
+            block_shift = level2shift(level);
+            idx = addr >> block_shift;
+            idx = idx%512;
+            block_size = (uint64_t)(1L << block_shift);
+            pte = table + idx;
+
+            if (size >= block_size && IS_ALIGNED(addr, block_size)) 
+            {
+                attr &= 0xfff0000000000ffcUL;
+                if(level != 3)
+                {
+                    *pte = phys | (attr | 0x1UL);
+                }
+                else
+                {
+                    *pte = phys | (attr | 0x3UL);
+                }
+                addr += block_size;
+                phys += block_size;
+                size -= block_size;
+                break;
+            }
+            table = get_level_table(pte);
+        }
+    }
+}
+
+void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr)
+{
+    map_region(va, pa, size, attr);
+}
+
+void rt_hw_dcache_enable(void)
+{
+    if (!(get_sctlr() & CR_M)) 
+    {
+        rt_kprintf("please init mmu!\n");
+    }
+    else
+    {
+        set_sctlr(get_sctlr() | CR_C);
+    }
+}
+
+void rt_hw_dcache_flush_all(void)
+{
+    int ret;
+
+    __asm_flush_dcache_all();
+    ret = __asm_flush_l3_cache();
+    if (ret)
+    {
+        rt_kprintf("flushing dcache returns 0x%x\n", ret);
+    }
+    else
+    {
+        rt_kprintf("flushing dcache successfully.\n");
+    }
+}
+
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
+{
+    __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
+{
+    __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+
+void rt_hw_dcache_invalidate_all(void)
+{
+    __asm_invalidate_dcache_all();
+}
+
+void rt_hw_dcache_disable(void)
+{
+    /* if cache isn't enabled no need to disable */
+    if(!(get_sctlr() & CR_C))
+    {
+        rt_kprintf("need enable cache!\n");
+        return;
+    }
+    set_sctlr(get_sctlr() & ~CR_C);
+}
+
+//icache
+void rt_hw_icache_enable(void)
+{
+    __asm_invalidate_icache_all();
+    set_sctlr(get_sctlr() | CR_I);
+}
+
+void rt_hw_icache_invalidate_all(void)
+{
+    __asm_invalidate_icache_all();
+}
+
+void rt_hw_icache_disable(void)
+{
+    set_sctlr(get_sctlr() & ~CR_I);
+}
\ No newline at end of file
diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h
new file mode 100644
index 0000000000..6a66472c79
--- /dev/null
+++ b/libcpu/aarch64/common/mmu.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2020-02-20     bigmagic           first version
+ */
+
+#ifndef  __MMU_H__
+#define  __MMU_H__
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M    (1 << 0)    /* MMU enable                */
+#define CR_A    (1 << 1)    /* Alignment abort enable        */
+#define CR_C    (1 << 2)    /* Dcache enable            */
+#define CR_W    (1 << 3)    /* Write buffer enable            */
+#define CR_P    (1 << 4)    /* 32-bit exception handler        */
+#define CR_D    (1 << 5)    /* 32-bit data address range        */
+#define CR_L    (1 << 6)    /* Implementation defined        */
+#define CR_B    (1 << 7)    /* Big endian                */
+#define CR_S    (1 << 8)    /* System MMU protection        */
+#define CR_R    (1 << 9)    /* ROM MMU protection            */
+#define CR_F    (1 << 10)    /* Implementation defined        */
+#define CR_Z    (1 << 11)    /* Implementation defined        */
+#define CR_I    (1 << 12)    /* Icache enable            */
+#define CR_V    (1 << 13)    /* Vectors relocated to 0xffff0000    */
+#define CR_RR   (1 << 14)    /* Round Robin cache replacement    */
+#define CR_L4   (1 << 15)    /* LDR pc can set T bit            */
+#define CR_DT   (1 << 16)
+#define CR_IT   (1 << 18)
+#define CR_ST   (1 << 19)
+#define CR_FI   (1 << 21)    /* Fast interrupt (lower latency mode)    */
+#define CR_U    (1 << 22)    /* Unaligned access operation        */
+#define CR_XP   (1 << 23)    /* Extended page tables            */
+#define CR_VE   (1 << 24)    /* Vectored interrupts            */
+#define CR_EE   (1 << 25)    /* Exception (Big) Endian        */
+#define CR_TRE  (1 << 28)    /* TEX remap enable            */
+#define CR_AFE  (1 << 29)    /* Access flag enable            */
+#define CR_TE   (1 << 30)    /* Thumb exception enable        */
+
+#define MMU_LEVEL_MASK 0x1ffUL
+#define MMU_MAP_ERROR_VANOTALIGN  -1
+#define MMU_MAP_ERROR_PANOTALIGN  -2
+#define MMU_MAP_ERROR_NOPAGE      -3
+#define MMU_MAP_ERROR_CONFLICT    -4
+
+#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
+#define MEM_ATTR_IO     ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
+
+#define BUS_ADDRESS(phys)    (((phys) & ~0xC0000000)  |  0xC0000000)
+
+void mmu_init(void);
+
+void mmu_enable(void);
+
+int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr);
+
+void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
+
+//dcache
+void rt_hw_dcache_enable(void);
+void rt_hw_dcache_flush_all(void);
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size);
+void rt_hw_dcache_invalidate_all(void);
+void rt_hw_dcache_disable(void);
+
+//icache
+void rt_hw_icache_enable(void);
+void rt_hw_icache_invalidate_all(void);
+void rt_hw_icache_disable(void);
+
+
+#endif  /*__MMU_H__*/
diff --git a/libcpu/aarch64/common/startup_gcc.S b/libcpu/aarch64/common/startup_gcc.S
new file mode 100644
index 0000000000..ea4268148c
--- /dev/null
+++ b/libcpu/aarch64/common/startup_gcc.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+    .global	Reset_Handler
+    .section ".start", "ax"
+Reset_Handler:
+    nop
diff --git a/libcpu/aarch64/common/vector_gcc.S b/libcpu/aarch64/common/vector_gcc.S
new file mode 100644
index 0000000000..fc88cce7f8
--- /dev/null
+++ b/libcpu/aarch64/common/vector_gcc.S
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+ 
+.text
+
+.globl system_vectors
+.globl vector_error
+.globl vector_irq
+.globl vector_fiq
+
+system_vectors:
+.align 11
+    .set    VBAR, system_vectors
+    .org    VBAR
+    // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1)
+    .org (VBAR + 0x00 + 0)
+    B vector_error      // 			Synchronous
+    .org (VBAR + 0x80 + 0)
+    B vector_irq        //          IRQ/vIRQ
+    .org (VBAR + 0x100 + 0)
+    B vector_fiq        //          FIQ/vFIQ
+    .org (VBAR + 0x180 + 0)
+    B vector_error      //          Error/vError
+
+    // Exception from CurrentEL (EL1) with SP_ELn
+    .org (VBAR + 0x200 + 0)
+    B vector_error      // 			Synchronous
+    .org (VBAR + 0x280 + 0)
+    B vector_irq    	// 			IRQ/vIRQ
+    .org (VBAR + 0x300 + 0)
+    B vector_fiq        //          FIQ/vFIQ
+    .org (VBAR + 0x380 + 0)
+    B vector_error
+
+    // Exception from lower EL, aarch64
+    .org (VBAR + 0x400 + 0)
+    B vector_error
+    .org (VBAR + 0x480 + 0)
+    B vector_error
+    .org (VBAR + 0x500 + 0)
+    B vector_error
+    .org (VBAR + 0x580 + 0)
+    B vector_error
+
+    // Exception from lower EL, aarch32
+    .org (VBAR + 0x600 + 0)
+    B vector_error
+    .org (VBAR + 0x680 + 0)
+    B vector_error
+    .org (VBAR + 0x700 + 0)
+    B vector_error
+    .org (VBAR + 0x780 + 0)
+    B vector_error
+    .org (VBAR + 0x800 + 0)
+    B vector_error
diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript
index 75e170a0cf..c6a4817802 100644
--- a/libcpu/aarch64/cortex-a53/SConscript
+++ b/libcpu/aarch64/cortex-a53/SConscript
@@ -1,16 +1,13 @@
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
-asm_src = Split('''
-context_gcc.S
-vector_gcc.S
-entry_point.S
-cpu_gcc.S
-cache.S
-''')
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
 CPPPATH = [cwd]
 
-group = DefineGroup('cpu', src + asm_src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/libcpu/aarch64/cortex-a53/armv8.h b/libcpu/aarch64/cortex-a53/armv8.h
deleted file mode 100644
index 4350890544..0000000000
--- a/libcpu/aarch64/cortex-a53/armv8.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-
-#ifndef __ARMV8_H__
-#define __ARMV8_H__
-
-/* the exception stack without VFP registers */
-struct rt_hw_exp_stack
-{
-	unsigned long long pc;
-	unsigned long long spsr;
-	unsigned long long x30;
-	unsigned long long xz;
-	unsigned long long x28;
-	unsigned long long x29;
-	unsigned long long x26;
-	unsigned long long x27;
-	unsigned long long x24;
-	unsigned long long x25;
-	unsigned long long x22;
-	unsigned long long x23;
-	unsigned long long x20;
-	unsigned long long x21;
-	unsigned long long x18;	
-	unsigned long long x19;
-	unsigned long long x16;
-	unsigned long long x17;
-	unsigned long long x14;
-	unsigned long long x15;
-	unsigned long long x12;
-	unsigned long long x13;
-	unsigned long long x10;
-	unsigned long long x11;
-	unsigned long long x8;
-	unsigned long long x9;
-	unsigned long long x6;
-	unsigned long long x7;
-	unsigned long long x4;
-	unsigned long long x5;
-	unsigned long long x2;
-	unsigned long long x3;
-	unsigned long long x0;
-	unsigned long long x1;
-};
-
-#define SP_ELx						( ( unsigned long long ) 0x01 )
-#define SP_EL0						( ( unsigned long long ) 0x00 )
-#define PSTATE_EL1					( ( unsigned long long ) 0x04 )
-#define PSTATE_EL2					( ( unsigned long long ) 0x08 )
-#define PSTATE_EL3					( ( unsigned long long ) 0x0c )
-
-rt_ubase_t rt_hw_get_current_el(void);
-void rt_hw_set_elx_env(void);
-void rt_hw_set_current_vbar(rt_ubase_t addr);
-
-#endif
diff --git a/libcpu/aarch64/cortex-a53/cache.S b/libcpu/aarch64/cortex-a53/cache.S
deleted file mode 100644
index 7f295a2b02..0000000000
--- a/libcpu/aarch64/cortex-a53/cache.S
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author             Notes
- * 2020-03-17     bigmagic           first version
- */
-
-/*
- * void __asm_dcache_level(level)
- *
- * flush or invalidate one level cache.
- *
- * x0: cache level
- * x1: 0 clean & invalidate, 1 invalidate only
- * x2~x9: clobbered
- */
-.globl __asm_dcache_level
-__asm_dcache_level:
-    lsl    x12, x0, #1
-    msr    csselr_el1, x12        /* select cache level */
-    isb                /* sync change of cssidr_el1 */
-    mrs    x6, ccsidr_el1        /* read the new cssidr_el1 */
-    and    x2, x6, #7        /* x2 <- log2(cache line size)-4 */
-    add    x2, x2, #4        /* x2 <- log2(cache line size) */
-    mov    x3, #0x3ff
-    and    x3, x3, x6, lsr #3    /* x3 <- max number of #ways */
-    clz    w5, w3            /* bit position of #ways */
-    mov    x4, #0x7fff
-    and    x4, x4, x6, lsr #13    /* x4 <- max number of #sets */
-    /* x12 <- cache level << 1 */
-    /* x2 <- line length offset */
-    /* x3 <- number of cache ways - 1 */
-    /* x4 <- number of cache sets - 1 */
-    /* x5 <- bit position of #ways */
-
-loop_set:
-    mov    x6, x3            /* x6 <- working copy of #ways */
-loop_way:
-    lsl    x7, x6, x5
-    orr    x9, x12, x7        /* map way and level to cisw value */
-    lsl    x7, x4, x2
-    orr    x9, x9, x7        /* map set number to cisw value */
-    tbz    w1, #0, 1f
-    dc    isw, x9
-    b    2f
-1:    dc    cisw, x9        /* clean & invalidate by set/way */
-2:    subs    x6, x6, #1        /* decrement the way */
-    b.ge    loop_way
-    subs    x4, x4, #1        /* decrement the set */
-    b.ge    loop_set
-
-    ret
-
-/*
- * void __asm_flush_dcache_all(int invalidate_only)
- *
- * x0: 0 clean & invalidate, 1 invalidate only
- *
- * flush or invalidate all data cache by SET/WAY.
- */
-.globl __asm_dcache_all
-__asm_dcache_all:
-    mov    x1, x0
-    dsb    sy
-    mrs    x10, clidr_el1        /* read clidr_el1 */
-    lsr    x11, x10, #24
-    and    x11, x11, #0x7        /* x11 <- loc */
-    cbz    x11, finished        /* if loc is 0, exit */
-    mov    x15, lr
-    mov    x0, #0            /* start flush at cache level 0 */
-    /* x0  <- cache level */
-    /* x10 <- clidr_el1 */
-    /* x11 <- loc */
-    /* x15 <- return address */
-
-loop_level:
-    lsl    x12, x0, #1
-    add    x12, x12, x0        /* x0 <- tripled cache level */
-    lsr    x12, x10, x12
-    and    x12, x12, #7        /* x12 <- cache type */
-    cmp    x12, #2
-    b.lt    skip            /* skip if no cache or icache */
-    bl    __asm_dcache_level    /* x1 = 0 flush, 1 invalidate */
-skip:
-    add    x0, x0, #1        /* increment cache level */
-    cmp    x11, x0
-    b.gt    loop_level
-
-    mov    x0, #0
-    msr    csselr_el1, x0        /* restore csselr_el1 */
-    dsb    sy
-    isb
-    mov    lr, x15
-
-finished:
-    ret
-
-.globl __asm_flush_dcache_all
-__asm_flush_dcache_all:
-    mov    x0, #0
-    b    __asm_dcache_all
-
-.globl __asm_invalidate_dcache_all
-__asm_invalidate_dcache_all:
-    mov    x0, #0x1
-    b    __asm_dcache_all
-
-/*
- * void __asm_flush_dcache_range(start, end)
- *
- * clean & invalidate data cache in the range
- *
- * x0: start address
- * x1: end address
- */
-.globl __asm_flush_dcache_range
-__asm_flush_dcache_range:
-    mrs    x3, ctr_el0
-    lsr    x3, x3, #16
-    and    x3, x3, #0xf
-    mov    x2, #4
-    lsl    x2, x2, x3        /* cache line size */
-
-    /* x2 <- minimal cache line size in cache system */
-    sub    x3, x2, #1
-    bic    x0, x0, x3
-1:    dc    civac, x0    /* clean & invalidate data or unified cache */
-    add    x0, x0, x2
-    cmp    x0, x1
-    b.lo    1b
-    dsb    sy
-    ret
-
-/*
- * void __asm_invalidate_icache_all(void)
- *
- * invalidate all tlb entries.
- */
-.globl __asm_invalidate_icache_all
-__asm_invalidate_icache_all:
-    ic    ialluis
-    isb    sy
-    ret
-
-.globl __asm_flush_l3_cache
-__asm_flush_l3_cache:
-    mov    x0, #0            /* return status as success */
-    ret
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S
deleted file mode 100644
index 934db7ed84..0000000000
--- a/libcpu/aarch64/cortex-a53/context_gcc.S
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-10-06     ZhaoXiaowei    the first version
- */
-
-  /*
- *enable gtimer
- */
-.globl rt_hw_gtimer_enable
-rt_hw_gtimer_enable:
-	MOV X0,#1
-	MSR CNTP_CTL_EL0,X0
-	RET
-
-/*
- *set gtimer CNTP_TVAL_EL0 value
- */
-.globl rt_hw_set_gtimer_val
-rt_hw_set_gtimer_val:
-	MSR CNTP_TVAL_EL0,X0
-	RET
-
-/*
- *get gtimer CNTP_TVAL_EL0 value
- */
-.globl rt_hw_get_gtimer_val
-rt_hw_get_gtimer_val:
-	MRS X0,CNTP_TVAL_EL0
-	RET
-
-
-.globl rt_hw_get_cntpct_val
-rt_hw_get_cntpct_val:
-	MRS X0, CNTPCT_EL0
-	RET
-
-/*
- *get gtimer frq value
- */
-.globl rt_hw_get_gtimer_frq
-rt_hw_get_gtimer_frq:
-	MRS X0,CNTFRQ_EL0
-	RET
-
-.macro SAVE_CONTEXT
-
-    /* Switch to use the EL0 stack pointer. */
-    MSR 	SPSEL, #0
-
-    /* Save the entire context. */
-    STP 	X0, X1, [SP, #-0x10]!
-    STP 	X2, X3, [SP, #-0x10]!
-    STP 	X4, X5, [SP, #-0x10]!
-    STP 	X6, X7, [SP, #-0x10]!
-    STP 	X8, X9, [SP, #-0x10]!
-    STP 	X10, X11, [SP, #-0x10]!
-    STP 	X12, X13, [SP, #-0x10]!
-    STP 	X14, X15, [SP, #-0x10]!
-    STP 	X16, X17, [SP, #-0x10]!
-    STP 	X18, X19, [SP, #-0x10]!
-    STP 	X20, X21, [SP, #-0x10]!
-    STP 	X22, X23, [SP, #-0x10]!
-    STP 	X24, X25, [SP, #-0x10]!
-    STP 	X26, X27, [SP, #-0x10]!
-    STP 	X28, X29, [SP, #-0x10]!
-    STP 	X30, XZR, [SP, #-0x10]!
-
-    MRS		X0, CurrentEL
-    CMP		X0, 0xc
-    B.EQ	3f
-    CMP		X0, 0x8
-    B.EQ	2f
-    CMP		X0, 0x4
-    B.EQ	1f
-    B 		.
-3:
-    MRS		X3, SPSR_EL3
-    /* Save the ELR. */
-    MRS		X2, ELR_EL3
-    B		0f
-2:
-    MRS		X3, SPSR_EL2
-    /* Save the ELR. */
-    MRS		X2, ELR_EL2
-    B		0f
-1:
-    MRS		X3, SPSR_EL1
-    MRS		X2, ELR_EL1
-    B		0f
-0:
-
-    STP 	X2, X3, [SP, #-0x10]!
-
-    MOV 	X0, SP   /* Move SP into X0 for saving. */
-
-    /* Switch to use the ELx stack pointer. */
-    MSR 	SPSEL, #1
-
-    .endm
-
-.macro SAVE_CONTEXT_T
-
-    /* Switch to use the EL0 stack pointer. */
-    MSR 	SPSEL, #0
-
-    /* Save the entire context. */
-    STP 	X0, X1, [SP, #-0x10]!
-    STP 	X2, X3, [SP, #-0x10]!
-    STP 	X4, X5, [SP, #-0x10]!
-    STP 	X6, X7, [SP, #-0x10]!
-    STP 	X8, X9, [SP, #-0x10]!
-    STP 	X10, X11, [SP, #-0x10]!
-    STP 	X12, X13, [SP, #-0x10]!
-    STP 	X14, X15, [SP, #-0x10]!
-    STP 	X16, X17, [SP, #-0x10]!
-    STP 	X18, X19, [SP, #-0x10]!
-    STP 	X20, X21, [SP, #-0x10]!
-    STP 	X22, X23, [SP, #-0x10]!
-    STP 	X24, X25, [SP, #-0x10]!
-    STP 	X26, X27, [SP, #-0x10]!
-    STP 	X28, X29, [SP, #-0x10]!
-    STP 	X30, XZR, [SP, #-0x10]!
-
-    MRS		X0, CurrentEL
-    CMP		X0, 0xc
-    B.EQ	3f
-    CMP		X0, 0x8
-    B.EQ	2f
-    CMP		X0, 0x4
-    B.EQ	1f
-    B 		.
-3:
-    MRS		X3, SPSR_EL3
-    MOV		X2, X30
-    B		0f
-2:
-    MRS		X3, SPSR_EL2
-    MOV		X2, X30
-    B		0f
-1:
-    MRS		X3, SPSR_EL1
-    MOV		X2, X30
-    B		0f
-0:
-
-    STP 	X2, X3, [SP, #-0x10]!
-
-    MOV 	X0, SP   /* Move SP into X0 for saving. */
-
-    /* Switch to use the ELx stack pointer. */
-    MSR 	SPSEL, #1
-
-    .endm
-
-.macro RESTORE_CONTEXT
-
-    /* Switch to use the EL0 stack pointer. */
-    MSR 	SPSEL, #0
-
-    /* Set the SP to point to the stack of the task being restored. */
-    MOV		SP, X0
-
-    LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
-
-    MRS		X0, CurrentEL
-    CMP		X0, 0xc
-    B.EQ	3f
-    CMP		X0, 0x8
-    B.EQ	2f
-    CMP		X0, 0x4
-    B.EQ	1f
-    B 		.
-3:
-    MSR		SPSR_EL3, X3
-    MSR		ELR_EL3, X2
-    B		0f
-2:
-    MSR		SPSR_EL2, X3
-    MSR		ELR_EL2, X2
-    B		0f
-1:
-    MSR		SPSR_EL1, X3
-    MSR		ELR_EL1, X2
-    B		0f
-0:
-
-    LDP 	X30, XZR, [SP], #0x10
-    LDP 	X28, X29, [SP], #0x10
-    LDP 	X26, X27, [SP], #0x10
-    LDP 	X24, X25, [SP], #0x10
-    LDP 	X22, X23, [SP], #0x10
-    LDP 	X20, X21, [SP], #0x10
-    LDP 	X18, X19, [SP], #0x10
-    LDP 	X16, X17, [SP], #0x10
-    LDP 	X14, X15, [SP], #0x10
-    LDP 	X12, X13, [SP], #0x10
-    LDP 	X10, X11, [SP], #0x10
-    LDP 	X8, X9, [SP], #0x10
-    LDP 	X6, X7, [SP], #0x10
-    LDP 	X4, X5, [SP], #0x10
-    LDP 	X2, X3, [SP], #0x10
-    LDP 	X0, X1, [SP], #0x10
-
-    /* Switch to use the ELx stack pointer.  _RB_ Might not be required. */
-    MSR 	SPSEL, #1
-
-    ERET
-
-    .endm
-
-.text
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    MRS      X0, DAIF
-    MSR      DAIFSet, #3
-    DSB      SY
-    RET
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    DSB     SY
-    MOV     X1, #0xC0
-    ANDS    X0, X0, X1
-    B.NE    rt_hw_interrupt_enable_exit
-    MSR     DAIFClr, #3
-rt_hw_interrupt_enable_exit:
-    RET
-
-/*
- * void rt_hw_context_switch_to(rt_ubase_t to);
- * r0 --> to
- */
-.globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    LDR		X0, [X0]
-    RESTORE_CONTEXT
-
-.text
-/*
- * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
- * r0 --> from
- * r1 --> to
- */
-.globl rt_hw_context_switch
-rt_hw_context_switch:
-
-    MOV		X8,X0
-    MOV		X9,X1
-
-    SAVE_CONTEXT_T
-    
-    STR		X0, [X8]            // store sp in preempted tasks TCB
-    LDR		X0, [X9]            // get new task stack pointer
-    
-    RESTORE_CONTEXT
-
-/*
- * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
- */
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    ADR 	X2, rt_thread_switch_interrupt_flag
-    LDR 	X3, [X2]
-    CMP 	X3, #1
-    B.EQ 	_reswitch
-    ADR 	X4, rt_interrupt_from_thread   // set rt_interrupt_from_thread
-    MOV 	X3, #1              // set rt_thread_switch_interrupt_flag to 1
-    STR 	X0, [X4]
-    STR 	X3, [X2]
-_reswitch:
-    ADR 	X2, rt_interrupt_to_thread     // set rt_interrupt_to_thread
-    STR 	X1, [X2]
-    RET
-
-.text
-
-// -- Exception handlers ----------------------------------
-
-    .align  8
-.globl vector_fiq
-vector_fiq:
-    SAVE_CONTEXT
-    STP 	X0, X1, [SP, #-0x10]!
-    BL      rt_hw_trap_fiq
-    LDP 	X0, X1, [SP], #0x10
-    RESTORE_CONTEXT
-
-.globl      rt_interrupt_enter
-.globl      rt_interrupt_leave
-.globl      rt_thread_switch_interrupt_flag
-.globl      rt_interrupt_from_thread
-.globl      rt_interrupt_to_thread
-
-
-// -------------------------------------------------------------------
-
-    .align  8
-.globl vector_irq
-vector_irq:
-    SAVE_CONTEXT
-    STP 	X0, X1, [SP, #-0x10]!
-
-    BL      rt_interrupt_enter
-    BL      rt_hw_trap_irq
-    BL      rt_interrupt_leave
-    
-    LDP 	X0, X1, [SP], #0x10
-
-    // if rt_thread_switch_interrupt_flag set, jump to
-    // rt_hw_context_switch_interrupt_do and don't return
-    ADR 	X1, rt_thread_switch_interrupt_flag
-    LDR     X2, [X1]
-    CMP     X2, #1
-    B.NE     vector_irq_exit
-
-    MOV     X2,  #0         // clear flag
-    STR     X2,  [X1]
-
-    ADR     X3,  rt_interrupt_from_thread
-    LDR     X4,  [X3]
-    STR     x0,  [X4]       // store sp in preempted tasks's TCB
-
-    ADR     x3,  rt_interrupt_to_thread
-    LDR     X4,  [X3]
-    LDR     x0,  [X4]       // get new task's stack pointer
-    
-vector_irq_exit:	
-    RESTORE_CONTEXT
-
-// -------------------------------------------------
-
-    .align  8
-    .globl  vector_error
-vector_error:
-    SAVE_CONTEXT
-    BL      rt_hw_trap_error
-    B       .
diff --git a/libcpu/aarch64/cortex-a53/cp15.h b/libcpu/aarch64/cortex-a53/cp15.h
deleted file mode 100644
index f3ffd6f857..0000000000
--- a/libcpu/aarch64/cortex-a53/cp15.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-
-#ifndef __CP15_H__
-#define __CP15_H__
-
-#ifndef   __STATIC_FORCEINLINE
-#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
-#endif
-
-#define __WFI()    __asm__ volatile ("wfi":::"memory")
-
-#define __WFE()    __asm__ volatile ("wfe":::"memory")
-
-#define __SEV()    __asm__ volatile ("sev")
-
-__STATIC_FORCEINLINE  void __ISB(void)
-{
-    __asm__ volatile ("isb 0xF":::"memory");
-}
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE  void __DSB(void)
-{
-    __asm__ volatile ("dsb 0xF":::"memory");
-}
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-
-__STATIC_FORCEINLINE  void __DMB(void)
-{
-    __asm__ volatile ("dmb 0xF":::"memory");
-}
-
-#ifdef RT_USING_SMP
-static inline void send_ipi_msg(int cpu, int ipi_vector)
-{
-    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
-}
-
-static inline void setup_bootstrap_addr(int cpu, int addr)
-{
-	CORE_MAILBOX3_SET(cpu) = addr;
-}
-
-static inline void enable_cpu_ipi_intr(int cpu)
-{
-    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
-}
-
-static inline void enable_cpu_timer_intr(int cpu)
-{
-	CORETIMER_INTCTL(cpu) = 0x8;
-}
-
-static inline void enable_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 1;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
-}
-
-static inline void disable_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 0;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
-}
-
-static inline  void mask_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 2;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
-}
-
-static inline void unmask_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 1;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
-}
-
-static inline rt_uint64_t read_cntvct(void)
-{
-    rt_uint32_t val,val1;
-    asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
-    return (val);
-}
-
-static inline rt_uint64_t read_cntvoff(void)
-{
-
-    rt_uint64_t val;
-    asm volatile("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
-    return (val);
-}
-
-static inline rt_uint32_t read_cntv_tval(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val) );
-    return val;
-}
-
-
-static inline  void write_cntv_tval(rt_uint32_t val)
-{
-    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val) );
-    return;
-}
-
-static inline rt_uint32_t read_cntfrq(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val) );
-    return val;
-}
-
-
-static inline  rt_uint32_t read_cntctrl(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val) );
-    return val;
-}
-
-static inline uint32_t write_cntctrl(uint32_t val)
-{
-
-    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val) );
-    return val;
-}
-#endif
-
-unsigned long rt_cpu_get_smp_id(void);
-
-void rt_cpu_mmu_disable(void);
-void rt_cpu_mmu_enable(void);
-void rt_cpu_tlb_set(volatile unsigned long*);
-
-void rt_cpu_dcache_clean_flush(void);
-void rt_cpu_icache_flush(void);
-
-void rt_cpu_vector_set_base(rt_ubase_t addr);
-void rt_hw_mmu_init(void);
-void rt_hw_vector_init(void);
-
-void set_timer_counter(unsigned int counter);
-void set_timer_control(unsigned int control);
-#endif
diff --git a/libcpu/aarch64/cortex-a53/cpu.c b/libcpu/aarch64/cortex-a53/cpu.c
deleted file mode 100644
index 962a53a071..0000000000
--- a/libcpu/aarch64/cortex-a53/cpu.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- * 2019-07-28     zdzn         add smp support
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <board.h>
-#include "cp15.h"
-
-int rt_hw_cpu_id(void)
-{
-    int cpu_id;
-    rt_base_t value;
-
-    __asm__ volatile (
-            "mrs %0, mpidr_el1"
-            :"=r"(value)
-            );
-    cpu_id = value & 0xf;
-    return cpu_id;
-};
-
-#ifdef RT_USING_SMP
-void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
-{
-    lock->slock = 0;
-}
-
-void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
-{
-    unsigned long tmp;
-    unsigned long newval;
-    rt_hw_spinlock_t lockval;
-    __asm__ __volatile__(
-            "pld [%0]"
-            ::"r"(&lock->slock)
-            );
-
-    __asm__ __volatile__(
-            "1: ldrex   %0, [%3]\n"
-            "   add %1, %0, %4\n"
-            "   strex   %2, %1, [%3]\n"
-            "   teq %2, #0\n"
-            "   bne 1b"
-            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
-            : "r" (&lock->slock), "I" (1 << 16)
-            : "cc");
-
-    while (lockval.tickets.next != lockval.tickets.owner) {
-        __WFE();
-        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
-    }
-
-    __DMB();
-}
-
-void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
-{
-    __DMB();
-    lock->tickets.owner++;
-    __DSB();
-    __SEV();
-}
-#endif /*RT_USING_SMP*/
-
-/**
- * @addtogroup ARM CPU
- */
-/*@{*/
-
-/** shutdown CPU */
-void rt_hw_cpu_shutdown()
-{
-    rt_uint32_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/aarch64/cortex-a53/cpu_gcc.S b/libcpu/aarch64/cortex-a53/cpu_gcc.S
deleted file mode 100644
index b8c8b8768c..0000000000
--- a/libcpu/aarch64/cortex-a53/cpu_gcc.S
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Date           Author       Notes
- * 2018-10-06     ZhaoXiaowei    the first version
- */
- 
-.text
-.globl rt_hw_get_current_el
-rt_hw_get_current_el:
-	MRS		X0, CurrentEL
-	CMP		X0, 0xc
-	B.EQ	3f
-	CMP		X0, 0x8
-	B.EQ	2f
-	CMP		X0, 0x4
-	B.EQ	1f
-	
-	LDR		X0, =0
-	B		0f
-3:
-	LDR		X0, =3
-	B		0f
-2:
-	LDR		X0, =2
-	B		0f
-1:
-	LDR		X0, =1
-	B		0f
-0:
-	RET
-
-
-.globl rt_hw_set_current_vbar
-rt_hw_set_current_vbar:
-	MRS		X1, CurrentEL
-	CMP		X1, 0xc
-	B.EQ	3f
-	CMP		X1, 0x8
-	B.EQ	2f
-	CMP		X1, 0x4
-	B.EQ	1f
-	B		0f
-3:
-	MSR		VBAR_EL3,X0
-	B		0f
-2:
-	MSR		VBAR_EL2,X0
-	B		0f
-1:
-	MSR		VBAR_EL1,X0
-	B		0f
-0:
-	RET
-
-    
-.globl rt_hw_set_elx_env
-rt_hw_set_elx_env:
-	MRS		X1, CurrentEL
-	CMP		X1, 0xc
-	B.EQ	3f
-	CMP		X1, 0x8
-	B.EQ	2f
-	CMP		X1, 0x4
-	B.EQ	1f
-	B		0f
-3:
-	MRS		X0, SCR_EL3
-	ORR		X0, X0, #0xF			/* SCR_EL3.NS|IRQ|FIQ|EA */
-	MSR		SCR_EL3, X0
-	B		0f
-2:
-	MRS	X0, HCR_EL2
-	ORR	X0, X0, #0x38
-	MSR	HCR_EL2, X0
-	B		0f
-1:
-	B		0f
-0:
-	RET
diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h
index 3533d3818c..8e741ed4e6 100644
--- a/libcpu/aarch64/cortex-a53/interrupt.h
+++ b/libcpu/aarch64/cortex-a53/interrupt.h
@@ -1,11 +1,11 @@
-
 /*
  * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       Notes
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
  */
 
 #ifndef __INTERRUPT_H__
@@ -19,8 +19,6 @@
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
-//void rt_hw_vector_init(void);
-
 void rt_hw_interrupt_init(void);
 void rt_hw_interrupt_mask(int vector);
 void rt_hw_interrupt_umask(int vector);
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
deleted file mode 100644
index b799143084..0000000000
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author             Notes
- * 2020-02-20     bigmagic           first version
- */
-#include <mmu.h>
-#include <stddef.h>
-#include <rthw.h>
-
-#define TTBR_CNP    1
-
-typedef unsigned long int    uint64_t;
-
-static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
-
-#define IS_ALIGNED(x, a)        (((x) & ((typeof(x))(a) - 1)) == 0)
-
-#define PMD_TYPE_SECT        (1 << 0)
-
-#define PMD_TYPE_TABLE        (3 << 0)
-
-#define PTE_TYPE_PAGE        (3 << 0)
-
-#define BITS_PER_VA          39
-
-/* Granule size of 4KB is being used */
-#define GRANULE_SIZE_SHIFT         12
-#define GRANULE_SIZE               (1 << GRANULE_SIZE_SHIFT)
-#define XLAT_ADDR_MASK             ((1UL << BITS_PER_VA) - GRANULE_SIZE)
-
-#define PMD_TYPE_MASK               (3 << 0)
-
-int free_idx = 1;
-
-void __asm_invalidate_icache_all(void);
-void __asm_flush_dcache_all(void);
-int __asm_flush_l3_cache(void);
-void __asm_flush_dcache_range(unsigned long long start, unsigned long long end);
-void __asm_invalidate_dcache_all(void);
-void __asm_invalidate_icache_all(void);
-
-void mmu_memset(char *dst, char v,  size_t len)
-{
-    while (len--)
-    {
-        *dst++ = v;
-    }
-}
-
-static unsigned long __page_off = 0;
-static unsigned long get_free_page(void) 
-{
-    __page_off += 512;
-    return (unsigned long)(main_tbl + __page_off);
-}
-
-
-static inline unsigned int get_sctlr(void)
-{
-    unsigned int val;
-    asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
-    return val;
-}
-
-static inline void set_sctlr(unsigned int val)
-{
-    asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
-    asm volatile("isb");
-}
-
-void mmu_init(void)
-{
-    unsigned long val64;
-    unsigned long val32;
-
-    val64 = 0x007f6eUL;
-    __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
-    __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
-
-    //TCR_EL1
-    val32 = (16UL << 0)//48bit
-        | (0x0UL << 6)
-        | (0x0UL << 7)
-        | (0x3UL << 8)
-        | (0x3UL << 10)//Inner Shareable
-        | (0x2UL << 12)
-        | (0x0UL << 14)//4K
-        | (0x0UL << 16)
-        | (0x0UL << 22)
-        | (0x1UL << 23)
-        | (0x2UL << 30)
-        | (0x1UL << 32)
-        | (0x0UL << 35)
-        | (0x0UL << 36)
-        | (0x0UL << 37)
-        | (0x0UL << 38);
-    __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32));
-    __asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32));
-
-    __asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
-    __asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
-
-    mmu_memset((char *)main_tbl, 0, 4096);
-}
-
-void mmu_enable(void)
-{
-    unsigned long val64;
-    unsigned long val32;
-
-    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
-    val64 &= ~0x1000; //disable I
-    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
-
-    __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
-    __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
-
-    //SCTLR_EL1, turn on mmu
-    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
-    val32 |= 0x1005; //enable mmu, I C M
-    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
-    rt_hw_icache_enable();
-    rt_hw_dcache_enable();
-
-}
-
-static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
-{
-    int level;
-    unsigned long* cur_lv_tbl = lv0_tbl;
-    unsigned long page;
-    unsigned long off;
-    int level_shift = 39;
-
-    if (va & (0x200000UL - 1)) 
-    {
-        return MMU_MAP_ERROR_VANOTALIGN;
-    }
-    if (pa & (0x200000UL - 1)) 
-    {
-        return MMU_MAP_ERROR_PANOTALIGN;
-    }
-    for (level = 0; level < 2; level++) 
-    {
-        off = (va >> level_shift);
-        off &= MMU_LEVEL_MASK;
-        if ((cur_lv_tbl[off] & 1) == 0) 
-        {
-            page = get_free_page();
-            if (!page) 
-            {
-                return MMU_MAP_ERROR_NOPAGE;
-            }
-            mmu_memset((char *)page, 0, 4096);
-            cur_lv_tbl[off] = page | 0x3UL;
-        }
-        page = cur_lv_tbl[off];
-        if (!(page & 0x2)) 
-        {
-            //is block! error!
-            return MMU_MAP_ERROR_CONFLICT;
-        }
-        cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
-        level_shift -= 9;
-    }
-    attr &= 0xfff0000000000ffcUL;
-    pa |= (attr | 0x1UL); //block
-    off = (va >> 21);
-    off &= MMU_LEVEL_MASK;
-    cur_lv_tbl[off] = pa;
-    return 0;
-}
-
-int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr)
-{
-    int i;
-    int ret;
-
-    if (va & (0x200000 - 1))
-    {
-        return -1;
-    }
-    if (pa & (0x200000 - 1))
-    {
-        return -1;
-    }
-    for (i = 0; i < count; i++)
-    {
-        ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr);
-        va += 0x200000;
-        pa += 0x200000;
-        if (ret != 0)
-        {
-            return ret;
-        }
-    }
-    return 0;
-}
-
-static void set_table(uint64_t *pt, uint64_t *table_addr)
-{
-    uint64_t val;
-    val = (0x3UL | (uint64_t)table_addr);
-    *pt = val;
-}
-
-void mmu_memset2(unsigned char *dst, char v,  int len)
-{
-    while (len--)
-    {
-        *dst++ = v;
-    }
-}
-
-static uint64_t *create_table(void)
-{
-    uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE;
-    /* Mark all entries as invalid */
-    mmu_memset2((unsigned char *)new_table, 0, 4096);
-    free_idx++;
-    return new_table;
-}
-
-static int pte_type(uint64_t *pte)
-{
-    return *pte & PMD_TYPE_MASK;
-}
-
-static int level2shift(int level)
-{
-    /* Page is 12 bits wide, every level translates 9 bits */
-    return (12 + 9 * (3 - level));
-}
-
-static uint64_t *get_level_table(uint64_t *pte)
-{
-    uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
-    
-    if (pte_type(pte) != PMD_TYPE_TABLE) 
-    {
-        table = create_table();
-        set_table(pte, table);
-    }
-    return table;
-}
-
-static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
-{
-    uint64_t block_size = 0;
-    uint64_t block_shift = 0;
-    uint64_t *pte;
-    uint64_t idx = 0;
-    uint64_t addr = 0;
-    uint64_t *table = 0;
-    int level = 0;
-
-    addr = virt;
-    while (size) 
-    {
-        table = &main_tbl[0];
-        for (level = 0; level < 4; level++) 
-        {
-            block_shift = level2shift(level);
-            idx = addr >> block_shift;
-            idx = idx%512;
-            block_size = (uint64_t)(1L << block_shift);
-            pte = table + idx;
-
-            if (size >= block_size && IS_ALIGNED(addr, block_size)) 
-            {
-                attr &= 0xfff0000000000ffcUL;
-                if(level != 3)
-                {
-                    *pte = phys | (attr | 0x1UL);
-                }
-                else
-                {
-                    *pte = phys | (attr | 0x3UL);
-                }
-                addr += block_size;
-                phys += block_size;
-                size -= block_size;
-                break;
-            }
-            table = get_level_table(pte);
-        }
-    }
-}
-
-void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr)
-{
-    map_region(va, pa, size, attr);
-}
-
-void rt_hw_dcache_enable(void)
-{
-    if (!(get_sctlr() & CR_M)) 
-    {
-        rt_kprintf("please init mmu!\n");
-    }
-    else
-    {
-        set_sctlr(get_sctlr() | CR_C);
-    }
-}
-
-void rt_hw_dcache_flush_all(void)
-{
-    int ret;
-
-    __asm_flush_dcache_all();
-    ret = __asm_flush_l3_cache();
-    if (ret)
-    {
-        rt_kprintf("flushing dcache returns 0x%x\n", ret);
-    }
-    else
-    {
-        rt_kprintf("flushing dcache successfully.\n");
-    }
-}
-
-void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
-{
-    __asm_flush_dcache_range(start_addr, start_addr + size);
-}
-void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
-{
-    __asm_flush_dcache_range(start_addr, start_addr + size);
-}
-
-void rt_hw_dcache_invalidate_all(void)
-{
-    __asm_invalidate_dcache_all();
-}
-
-void rt_hw_dcache_disable(void)
-{
-    /* if cache isn't enabled no need to disable */
-    if(!(get_sctlr() & CR_C))
-    {
-        rt_kprintf("need enable cache!\n");
-        return;
-    }
-    set_sctlr(get_sctlr() & ~CR_C);
-}
-
-//icache
-void rt_hw_icache_enable(void)
-{
-    __asm_invalidate_icache_all();
-    set_sctlr(get_sctlr() | CR_I);
-}
-
-void rt_hw_icache_invalidate_all(void)
-{
-    __asm_invalidate_icache_all();
-}
-
-void rt_hw_icache_disable(void)
-{
-    set_sctlr(get_sctlr() & ~CR_I);
-}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
deleted file mode 100644
index 6a66472c79..0000000000
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author             Notes
- * 2020-02-20     bigmagic           first version
- */
-
-#ifndef  __MMU_H__
-#define  __MMU_H__
-
-/*
- * CR1 bits (CP#15 CR1)
- */
-#define CR_M    (1 << 0)    /* MMU enable                */
-#define CR_A    (1 << 1)    /* Alignment abort enable        */
-#define CR_C    (1 << 2)    /* Dcache enable            */
-#define CR_W    (1 << 3)    /* Write buffer enable            */
-#define CR_P    (1 << 4)    /* 32-bit exception handler        */
-#define CR_D    (1 << 5)    /* 32-bit data address range        */
-#define CR_L    (1 << 6)    /* Implementation defined        */
-#define CR_B    (1 << 7)    /* Big endian                */
-#define CR_S    (1 << 8)    /* System MMU protection        */
-#define CR_R    (1 << 9)    /* ROM MMU protection            */
-#define CR_F    (1 << 10)    /* Implementation defined        */
-#define CR_Z    (1 << 11)    /* Implementation defined        */
-#define CR_I    (1 << 12)    /* Icache enable            */
-#define CR_V    (1 << 13)    /* Vectors relocated to 0xffff0000    */
-#define CR_RR   (1 << 14)    /* Round Robin cache replacement    */
-#define CR_L4   (1 << 15)    /* LDR pc can set T bit            */
-#define CR_DT   (1 << 16)
-#define CR_IT   (1 << 18)
-#define CR_ST   (1 << 19)
-#define CR_FI   (1 << 21)    /* Fast interrupt (lower latency mode)    */
-#define CR_U    (1 << 22)    /* Unaligned access operation        */
-#define CR_XP   (1 << 23)    /* Extended page tables            */
-#define CR_VE   (1 << 24)    /* Vectored interrupts            */
-#define CR_EE   (1 << 25)    /* Exception (Big) Endian        */
-#define CR_TRE  (1 << 28)    /* TEX remap enable            */
-#define CR_AFE  (1 << 29)    /* Access flag enable            */
-#define CR_TE   (1 << 30)    /* Thumb exception enable        */
-
-#define MMU_LEVEL_MASK 0x1ffUL
-#define MMU_MAP_ERROR_VANOTALIGN  -1
-#define MMU_MAP_ERROR_PANOTALIGN  -2
-#define MMU_MAP_ERROR_NOPAGE      -3
-#define MMU_MAP_ERROR_CONFLICT    -4
-
-#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
-#define MEM_ATTR_IO     ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
-
-#define BUS_ADDRESS(phys)    (((phys) & ~0xC0000000)  |  0xC0000000)
-
-void mmu_init(void);
-
-void mmu_enable(void);
-
-int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr);
-
-void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
-
-//dcache
-void rt_hw_dcache_enable(void);
-void rt_hw_dcache_flush_all(void);
-void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
-void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size);
-void rt_hw_dcache_invalidate_all(void);
-void rt_hw_dcache_disable(void);
-
-//icache
-void rt_hw_icache_enable(void);
-void rt_hw_icache_invalidate_all(void);
-void rt_hw_icache_disable(void);
-
-
-#endif  /*__MMU_H__*/
diff --git a/libcpu/aarch64/cortex-a53/startup_gcc.S b/libcpu/aarch64/cortex-a53/startup_gcc.S
deleted file mode 100644
index ea4268148c..0000000000
--- a/libcpu/aarch64/cortex-a53/startup_gcc.S
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-    .global	Reset_Handler
-    .section ".start", "ax"
-Reset_Handler:
-    nop
diff --git a/libcpu/aarch64/cortex-a53/vector_gcc.S b/libcpu/aarch64/cortex-a53/vector_gcc.S
deleted file mode 100644
index fc88cce7f8..0000000000
--- a/libcpu/aarch64/cortex-a53/vector_gcc.S
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Date           Author       Notes
- * 2018-10-06     ZhaoXiaowei    the first version
- */
- 
-.text
-
-.globl system_vectors
-.globl vector_error
-.globl vector_irq
-.globl vector_fiq
-
-system_vectors:
-.align 11
-    .set    VBAR, system_vectors
-    .org    VBAR
-    // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1)
-    .org (VBAR + 0x00 + 0)
-    B vector_error      // 			Synchronous
-    .org (VBAR + 0x80 + 0)
-    B vector_irq        //          IRQ/vIRQ
-    .org (VBAR + 0x100 + 0)
-    B vector_fiq        //          FIQ/vFIQ
-    .org (VBAR + 0x180 + 0)
-    B vector_error      //          Error/vError
-
-    // Exception from CurrentEL (EL1) with SP_ELn
-    .org (VBAR + 0x200 + 0)
-    B vector_error      // 			Synchronous
-    .org (VBAR + 0x280 + 0)
-    B vector_irq    	// 			IRQ/vIRQ
-    .org (VBAR + 0x300 + 0)
-    B vector_fiq        //          FIQ/vFIQ
-    .org (VBAR + 0x380 + 0)
-    B vector_error
-
-    // Exception from lower EL, aarch64
-    .org (VBAR + 0x400 + 0)
-    B vector_error
-    .org (VBAR + 0x480 + 0)
-    B vector_error
-    .org (VBAR + 0x500 + 0)
-    B vector_error
-    .org (VBAR + 0x580 + 0)
-    B vector_error
-
-    // Exception from lower EL, aarch32
-    .org (VBAR + 0x600 + 0)
-    B vector_error
-    .org (VBAR + 0x680 + 0)
-    B vector_error
-    .org (VBAR + 0x700 + 0)
-    B vector_error
-    .org (VBAR + 0x780 + 0)
-    B vector_error
-    .org (VBAR + 0x800 + 0)
-    B vector_error
diff --git a/libcpu/aarch64/cortex-a57/SConscript b/libcpu/aarch64/cortex-a57/SConscript
new file mode 100644
index 0000000000..c6a4817802
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/SConscript
@@ -0,0 +1,13 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/cortex-a57/entry_point.S b/libcpu/aarch64/cortex-a57/entry_point.S
new file mode 100644
index 0000000000..6d2c69226b
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/entry_point.S
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2020-01-15     bigmagic    the first version
+ */
+
+.section ".text.entrypoint"
+
+.set EL1_stack,         __el1_stack
+
+.global _start
+
+// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
+// loads 'kernel8.img' file in.
+_start:
+    // read cpu id, stop slave cores
+    mrs     x1, mpidr_el1            // MPIDR_EL1: Multi-Processor Affinity Register
+    and     x1, x1, #3
+    cbz     x1, .L__cpu_0             // .L prefix is the local label in ELF 
+
+    // cpu id > 0, stop
+    // cpu id == 0 will also goto here after returned from entry() if possible
+.L__current_cpu_idle:
+    wfe
+    b       .L__current_cpu_idle
+
+.L__cpu_0:  // cpu id == 0
+
+    // set stack before our code
+
+	/* Define stack pointer for current exception level */
+	// ldr	x2, =EL1_stack
+	// mov	sp, x2
+
+    ldr     x1, =_start
+
+    // set up EL1
+    mrs     x0, CurrentEL           // CurrentEL Register. bit 2, 3. Others reserved
+    and     x0, x0, #12             // clear reserved bits
+
+    // running at EL3?
+    cmp     x0, #12                // 1100b. So, EL3
+    bne     .L__not_in_el3         // 11?  !EL3 -> 5:
+
+    // should never be executed, just for completeness. (EL3)
+    mov     x2, #0x5b1
+    msr     scr_el3, x2            // SCR_ELn  Secure Configuration Register
+    mov     x2, #0x3c9
+    msr     spsr_el3, x2           // SPSR_ELn. Saved Program Status Register. 1111001001
+    adr     x2, .L__not_in_el3   
+    msr     elr_el3, x2
+    eret                           // Exception Return: from EL3, continue from .L__not_in_el3
+
+    // running at EL2 or EL1
+.L__not_in_el3:    
+    cmp     x0, #4                 // 0x04  0100 EL1
+    beq     .L__in_el1             // EL1 -> 5:
+
+    // in EL2
+    msr     sp_el1, x1             // Set sp of EL1 to _start
+
+    // enable CNTP for EL1
+    mrs     x0, cnthctl_el2         // Counter-timer Hypervisor Control register
+    orr     x0, x0, #3
+    msr     cnthctl_el2, x0
+    msr     cntvoff_el2, xzr
+
+    // enable AArch64 in EL1
+    mov     x0, #(1 << 31)          // AArch64
+    orr     x0, x0, #(1 << 1)       // SWIO hardwired on Pi3
+    msr     hcr_el2, x0
+    mrs     x0, hcr_el2
+
+    // change execution level to EL1
+    mov     x2, #0x3c4
+    msr     spsr_el2, x2        // 1111000100
+    adr     x2, .L__in_el1
+    msr     elr_el2, x2
+    eret                        // exception return. from EL2. continue from .L__in_el1
+
+.L__in_el1:
+    mov     sp, x1             // in EL1. Set sp to _start
+
+    // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
+    mov     x1, #0x00300000       // Don't trap any SIMD/FP instructions in both EL0 and EL1
+    msr     cpacr_el1, x1
+
+    mrs x1, sctlr_el1
+    orr x1, x1, #(1 << 12)
+    bic x1, x1, #(3 << 3)
+    bic x1, x1, #(1 << 1)
+    msr sctlr_el1, x1
+
+    // clear bss
+    ldr     x1, =__bss_start
+    ldr     w2, =__bss_size
+
+.L__clean_bss_loop:
+    cbz     w2, .L__jump_to_entry
+    str     xzr, [x1], #8
+    sub     w2, w2, #1
+    cbnz    w2, .L__clean_bss_loop
+
+    // jump to C code, should not return
+.L__jump_to_entry:
+    bl      entry
+    // for failsafe, halt this core too
+    b       .L__current_cpu_idle
diff --git a/libcpu/aarch64/cortex-a57/interrupt.c b/libcpu/aarch64/cortex-a57/interrupt.c
new file mode 100644
index 0000000000..d770259d61
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/interrupt.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <gic_pl400.h>
+#include <board.h>
+#include <armv8.h>
+
+#define MAX_HANDLERS                256
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+extern int system_vectors;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_ubase_t rt_interrupt_from_thread;
+rt_ubase_t rt_interrupt_to_thread;
+rt_ubase_t rt_thread_switch_interrupt_flag;
+
+void rt_hw_vector_init(void)
+{
+    rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);  // cpu_gcc.S
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    initIRQController();
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a57/interrupt.h b/libcpu/aarch64/cortex-a57/interrupt.h
new file mode 100644
index 0000000000..0d2d4867c7
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/interrupt.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/libcpu/aarch64/cortex-a57/stack.c b/libcpu/aarch64/cortex-a57/stack.c
new file mode 100644
index 0000000000..68222c2c67
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/stack.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+
+#include <armv8.h>
+
+#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
+#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
+#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_ubase_t *stk;
+	rt_ubase_t current_el;
+
+	stk 	 = (rt_ubase_t*)stack_addr;
+
+	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
+	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
+	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
+	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
+	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
+	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
+	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
+	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
+	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
+	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
+	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
+	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
+	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
+	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
+	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
+	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
+	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
+	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
+	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
+	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
+	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
+	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
+	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
+	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
+	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
+	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
+	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
+	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
+	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
+	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+
+	current_el = rt_hw_get_current_el();
+
+	if(current_el == 3)
+	{
+		*(--stk) = INITIAL_SPSR_EL3;
+	}
+	else if(current_el == 2)
+	{
+		*(--stk) = INITIAL_SPSR_EL2;
+	}
+	else
+	{
+		*(--stk) = INITIAL_SPSR_EL1;
+	}
+
+	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/aarch64/cortex-a57/trap.c b/libcpu/aarch64/cortex-a57/trap.c
new file mode 100644
index 0000000000..d93aa18fd6
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/trap.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "interrupt.h"
+#include "armv8.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
+    rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
+	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
+	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("error exception:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_ack(int fiq_irq);
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    int ir; 
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    ir = rt_hw_interrupt_get_irq();
+    if (ir == 1023)
+    {
+        /* Spurious interrupt */
+        return;
+    }
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+    isr_table[ir].counter++;
+#endif
+    if (isr_func)
+    {
+        /* Interrupt for myself. */
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
+
+}
+
+void rt_hw_trap_fiq(void)
+{
+}
-- 
cgit v1.3.1


From a120c914bb003646010d1d385be36b5260284132 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 16 Apr 2020 16:42:07 +0800
Subject: add bsp/raspi4 readme

---
 bsp/raspberry-pi/raspi3-64/README.md    |   2 +-
 bsp/raspberry-pi/raspi4/Kconfig         |   2 +-
 bsp/raspberry-pi/raspi4/README.md       |  81 +++++++++--------------
 bsp/raspberry-pi/raspi4/rtconfig.py     |   2 +-
 libcpu/aarch64/cortex-a57/SConscript    |  13 ----
 libcpu/aarch64/cortex-a57/entry_point.S | 111 --------------------------------
 libcpu/aarch64/cortex-a57/interrupt.c   |  73 ---------------------
 libcpu/aarch64/cortex-a57/interrupt.h   |  27 --------
 libcpu/aarch64/cortex-a57/stack.c       |  90 --------------------------
 libcpu/aarch64/cortex-a57/trap.c        |  98 ----------------------------
 libcpu/aarch64/cortex-a72/SConscript    |  13 ++++
 libcpu/aarch64/cortex-a72/entry_point.S | 111 ++++++++++++++++++++++++++++++++
 libcpu/aarch64/cortex-a72/interrupt.c   |  73 +++++++++++++++++++++
 libcpu/aarch64/cortex-a72/interrupt.h   |  27 ++++++++
 libcpu/aarch64/cortex-a72/stack.c       |  90 ++++++++++++++++++++++++++
 libcpu/aarch64/cortex-a72/trap.c        |  98 ++++++++++++++++++++++++++++
 16 files changed, 446 insertions(+), 465 deletions(-)
 delete mode 100644 libcpu/aarch64/cortex-a57/SConscript
 delete mode 100644 libcpu/aarch64/cortex-a57/entry_point.S
 delete mode 100644 libcpu/aarch64/cortex-a57/interrupt.c
 delete mode 100644 libcpu/aarch64/cortex-a57/interrupt.h
 delete mode 100644 libcpu/aarch64/cortex-a57/stack.c
 delete mode 100644 libcpu/aarch64/cortex-a57/trap.c
 create mode 100644 libcpu/aarch64/cortex-a72/SConscript
 create mode 100644 libcpu/aarch64/cortex-a72/entry_point.S
 create mode 100644 libcpu/aarch64/cortex-a72/interrupt.c
 create mode 100644 libcpu/aarch64/cortex-a72/interrupt.h
 create mode 100644 libcpu/aarch64/cortex-a72/stack.c
 create mode 100644 libcpu/aarch64/cortex-a72/trap.c

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi3-64/README.md b/bsp/raspberry-pi/raspi3-64/README.md
index 28e00f96c0..576b13ed0e 100644
--- a/bsp/raspberry-pi/raspi3-64/README.md
+++ b/bsp/raspberry-pi/raspi3-64/README.md
@@ -17,7 +17,7 @@
 
 Windows环境下推荐使用[env工具][1]进行编译。
 
-首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
+首先下载windows上的aarch64的gcc交叉编译工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
 
 将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
 
diff --git a/bsp/raspberry-pi/raspi4/Kconfig b/bsp/raspberry-pi/raspi4/Kconfig
index e71ed3d54b..075a5d81aa 100644
--- a/bsp/raspberry-pi/raspi4/Kconfig
+++ b/bsp/raspberry-pi/raspi4/Kconfig
@@ -20,7 +20,7 @@ source "$PKGS_DIR/Kconfig"
 
 config BCM2711_SOC
     bool
-    select ARCH_ARM_CORTEX_A57
+    select ARCH_ARM_CORTEX_A72
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     select ARCH_CPU_64BIT
diff --git a/bsp/raspberry-pi/raspi4/README.md b/bsp/raspberry-pi/raspi4/README.md
index 28e00f96c0..1e7411894e 100644
--- a/bsp/raspberry-pi/raspi4/README.md
+++ b/bsp/raspberry-pi/raspi4/README.md
@@ -1,86 +1,67 @@
-# Raspberry PI 3-64板级支持包说明
+# Raspberry PI 4板级支持包说明
 
 ## 1. 简介
 
-树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3有三个发行版本：
+树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
 
-* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz，双核VideoCore IV GPU，1GB内存，100 Base-T Ethernet
-* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM， GigaE over USB 2.0
-* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM
+外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
 
-这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
 
 
 ## 2. 编译说明
 
-### 2.1 Window上的环境搭建
-
-Windows环境下推荐使用[env工具][1]进行编译。
-
-首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
-
-将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
-
-接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py`
+Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
 
-修改路径：
+将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。
 
 ```
-EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
 ```
 
-然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。
-
-### 2.2 Linux上的环境搭建
-
-Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
-
-直接进入`bsp\raspberry-pi\raspi3-64`，输入scons编译即可。
+直接进入`bsp\raspberry-pi\raspi4`，输入scons编译即可。
 
 
 ## 3. 执行
 
-### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
-
-Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
-
-解开下载的镜像文件, linux下使用如下的命令
+### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡
 
-```
-unzip 2018-06-27-raspbian-stretch-lite.zip
-```
-
-准备一张空SD卡，linux环境下，插入电脑并执行
+首先下载镜像
 
-```
-sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
-```
+* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb)
+* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe)
+* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg)
 
-**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
+### 3.2 准备好串口线
 
-Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
+目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
 
-最后把kernel8.img放入SD boot分区，删除其它 kernel*.img。
+![raspi2](../raspi3-32/figures/raspberrypi-console.png)
 
-### 3.2 准备好串口线
+串口参数： 115200 8N1 ，硬件和软件流控为关。
 
-目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示(图片中的板子是pi2，GPIO引脚是一样的)：
+### 3.3 程序下载
 
-![raspi2](figures/raspi_uart.png)
+当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下：
 
-串口参数： 115200 8N1 ，硬件和软件流控为关。
+```
+enable_uart=1
+arm_64bit=1
+kernel=rtthread.bin
+```
 
-按上面的方法做好SD卡后，插入树莓派，通电可以在串口上看到如下所示的输出信息：
+按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
 
 ```text
- heap: 0x00020b20 - 0x00400000
+heap: 0x000c9350 - 0x040c9350
 
  \ | /
 - RT -     Thread Operating System
- / | \     3.1.0 build Aug 23 2019
- 2006 - 2019 Copyright by rt-thread team
-Hello RT-Thread!
-msh >
+ / | \     4.0.3 build Apr 16 2020
+ 2006 - 2020 Copyright by rt-thread team
+Hi, this is RT-Thread!!
+msh />
 ```
 
 ## 4. 支持情况
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py
index 228ec0176a..9265b016be 100644
--- a/bsp/raspberry-pi/raspi4/rtconfig.py
+++ b/bsp/raspberry-pi/raspi4/rtconfig.py
@@ -2,7 +2,7 @@ import os
 
 # toolchains options
 ARCH        ='aarch64'
-CPU         ='cortex-a57'
+CPU         ='cortex-a72'
 CROSS_TOOL  ='gcc'
 
 if os.getenv('RTT_ROOT'):
diff --git a/libcpu/aarch64/cortex-a57/SConscript b/libcpu/aarch64/cortex-a57/SConscript
deleted file mode 100644
index c6a4817802..0000000000
--- a/libcpu/aarch64/cortex-a57/SConscript
+++ /dev/null
@@ -1,13 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
-CPPPATH = [cwd]
-
-group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/libcpu/aarch64/cortex-a57/entry_point.S b/libcpu/aarch64/cortex-a57/entry_point.S
deleted file mode 100644
index 6d2c69226b..0000000000
--- a/libcpu/aarch64/cortex-a57/entry_point.S
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Date           Author       Notes
- * 2020-01-15     bigmagic    the first version
- */
-
-.section ".text.entrypoint"
-
-.set EL1_stack,         __el1_stack
-
-.global _start
-
-// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
-// loads 'kernel8.img' file in.
-_start:
-    // read cpu id, stop slave cores
-    mrs     x1, mpidr_el1            // MPIDR_EL1: Multi-Processor Affinity Register
-    and     x1, x1, #3
-    cbz     x1, .L__cpu_0             // .L prefix is the local label in ELF 
-
-    // cpu id > 0, stop
-    // cpu id == 0 will also goto here after returned from entry() if possible
-.L__current_cpu_idle:
-    wfe
-    b       .L__current_cpu_idle
-
-.L__cpu_0:  // cpu id == 0
-
-    // set stack before our code
-
-	/* Define stack pointer for current exception level */
-	// ldr	x2, =EL1_stack
-	// mov	sp, x2
-
-    ldr     x1, =_start
-
-    // set up EL1
-    mrs     x0, CurrentEL           // CurrentEL Register. bit 2, 3. Others reserved
-    and     x0, x0, #12             // clear reserved bits
-
-    // running at EL3?
-    cmp     x0, #12                // 1100b. So, EL3
-    bne     .L__not_in_el3         // 11?  !EL3 -> 5:
-
-    // should never be executed, just for completeness. (EL3)
-    mov     x2, #0x5b1
-    msr     scr_el3, x2            // SCR_ELn  Secure Configuration Register
-    mov     x2, #0x3c9
-    msr     spsr_el3, x2           // SPSR_ELn. Saved Program Status Register. 1111001001
-    adr     x2, .L__not_in_el3   
-    msr     elr_el3, x2
-    eret                           // Exception Return: from EL3, continue from .L__not_in_el3
-
-    // running at EL2 or EL1
-.L__not_in_el3:    
-    cmp     x0, #4                 // 0x04  0100 EL1
-    beq     .L__in_el1             // EL1 -> 5:
-
-    // in EL2
-    msr     sp_el1, x1             // Set sp of EL1 to _start
-
-    // enable CNTP for EL1
-    mrs     x0, cnthctl_el2         // Counter-timer Hypervisor Control register
-    orr     x0, x0, #3
-    msr     cnthctl_el2, x0
-    msr     cntvoff_el2, xzr
-
-    // enable AArch64 in EL1
-    mov     x0, #(1 << 31)          // AArch64
-    orr     x0, x0, #(1 << 1)       // SWIO hardwired on Pi3
-    msr     hcr_el2, x0
-    mrs     x0, hcr_el2
-
-    // change execution level to EL1
-    mov     x2, #0x3c4
-    msr     spsr_el2, x2        // 1111000100
-    adr     x2, .L__in_el1
-    msr     elr_el2, x2
-    eret                        // exception return. from EL2. continue from .L__in_el1
-
-.L__in_el1:
-    mov     sp, x1             // in EL1. Set sp to _start
-
-    // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
-    mov     x1, #0x00300000       // Don't trap any SIMD/FP instructions in both EL0 and EL1
-    msr     cpacr_el1, x1
-
-    mrs x1, sctlr_el1
-    orr x1, x1, #(1 << 12)
-    bic x1, x1, #(3 << 3)
-    bic x1, x1, #(1 << 1)
-    msr sctlr_el1, x1
-
-    // clear bss
-    ldr     x1, =__bss_start
-    ldr     w2, =__bss_size
-
-.L__clean_bss_loop:
-    cbz     w2, .L__jump_to_entry
-    str     xzr, [x1], #8
-    sub     w2, w2, #1
-    cbnz    w2, .L__clean_bss_loop
-
-    // jump to C code, should not return
-.L__jump_to_entry:
-    bl      entry
-    // for failsafe, halt this core too
-    b       .L__current_cpu_idle
diff --git a/libcpu/aarch64/cortex-a57/interrupt.c b/libcpu/aarch64/cortex-a57/interrupt.c
deleted file mode 100644
index d770259d61..0000000000
--- a/libcpu/aarch64/cortex-a57/interrupt.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <gic_pl400.h>
-#include <board.h>
-#include <armv8.h>
-
-#define MAX_HANDLERS                256
-
-#ifdef RT_USING_SMP
-#define rt_interrupt_nest rt_cpu_self()->irq_nest
-#else
-extern volatile rt_uint8_t rt_interrupt_nest;
-#endif
-
-extern int system_vectors;
-
-/* exception and interrupt handler table */
-struct rt_irq_desc isr_table[MAX_HANDLERS];
-
-rt_ubase_t rt_interrupt_from_thread;
-rt_ubase_t rt_interrupt_to_thread;
-rt_ubase_t rt_thread_switch_interrupt_flag;
-
-void rt_hw_vector_init(void)
-{
-    rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);  // cpu_gcc.S
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    initIRQController();
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector < MAX_HANDLERS)
-    {
-        old_handler = isr_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-            isr_table[vector].handler = handler;
-            isr_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a57/interrupt.h b/libcpu/aarch64/cortex-a57/interrupt.h
deleted file mode 100644
index 0d2d4867c7..0000000000
--- a/libcpu/aarch64/cortex-a57/interrupt.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-#include <rthw.h>
-#include <board.h>
-
-#define INT_IRQ     0x00
-#define INT_FIQ     0x01
-
-void rt_hw_interrupt_init(void);
-void rt_hw_interrupt_mask(int vector);
-void rt_hw_interrupt_umask(int vector);
-
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name);
-
-#endif
diff --git a/libcpu/aarch64/cortex-a57/stack.c b/libcpu/aarch64/cortex-a57/stack.c
deleted file mode 100644
index 68222c2c67..0000000000
--- a/libcpu/aarch64/cortex-a57/stack.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-23     Bernard      the first version
- * 2011-10-05     Bernard      add thumb mode
- */
-#include <rtthread.h>
-#include <board.h>
-
-#include <armv8.h>
-
-#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
-#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
-#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry 
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
-{
-	rt_ubase_t *stk;
-	rt_ubase_t current_el;
-
-	stk 	 = (rt_ubase_t*)stack_addr;
-
-	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
-	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
-	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
-	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
-	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
-	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
-	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
-	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
-	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
-	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
-	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
-	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
-	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
-	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
-	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
-	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
-	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
-	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
-	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
-	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
-	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
-	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
-	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
-	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
-	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
-	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
-	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
-	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
-	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
-	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
-
-	current_el = rt_hw_get_current_el();
-
-	if(current_el == 3)
-	{
-		*(--stk) = INITIAL_SPSR_EL3;
-	}
-	else if(current_el == 2)
-	{
-		*(--stk) = INITIAL_SPSR_EL2;
-	}
-	else
-	{
-		*(--stk) = INITIAL_SPSR_EL1;
-	}
-
-	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
diff --git a/libcpu/aarch64/cortex-a57/trap.c b/libcpu/aarch64/cortex-a57/trap.c
deleted file mode 100644
index d93aa18fd6..0000000000
--- a/libcpu/aarch64/cortex-a57/trap.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- * 
- * Date           Author       Notes
- * 2018-10-06     ZhaoXiaowei    the first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include "interrupt.h"
-#include "armv8.h"
-
-extern struct rt_thread *rt_current_thread;
-#ifdef RT_USING_FINSH
-extern long list_thread(void);
-#endif
-
-/**
- * this function will show registers of CPU
- *
- * @param regs the registers point
- */
-void rt_hw_show_register(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("Execption:\n");
-    rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
-    rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
-	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
-	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
-	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
-	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
-    rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
-	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
-	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
-	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
-}
-
-/**
- * When comes across an instruction which it cannot handle,
- * it takes the undefined instruction trap.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("error exception:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-#define GIC_ACK_INTID_MASK              0x000003ff
-
-int rt_hw_interrupt_get_irq(void);
-void rt_hw_interrupt_ack(int fiq_irq);
-
-void rt_hw_trap_irq(void)
-{
-    void *param;
-    int ir; 
-    rt_isr_handler_t isr_func;
-    extern struct rt_irq_desc isr_table[];
-
-    ir = rt_hw_interrupt_get_irq();
-    if (ir == 1023)
-    {
-        /* Spurious interrupt */
-        return;
-    }
-
-    /* get interrupt service routine */
-    isr_func = isr_table[ir].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-    isr_table[ir].counter++;
-#endif
-    if (isr_func)
-    {
-        /* Interrupt for myself. */
-        param = isr_table[ir].param;
-        /* turn to interrupt service routine */
-        isr_func(ir, param);
-    }
-
-    /* end of interrupt */
-    rt_hw_interrupt_ack(ir);
-
-}
-
-void rt_hw_trap_fiq(void)
-{
-}
diff --git a/libcpu/aarch64/cortex-a72/SConscript b/libcpu/aarch64/cortex-a72/SConscript
new file mode 100644
index 0000000000..c6a4817802
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/SConscript
@@ -0,0 +1,13 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/cortex-a72/entry_point.S b/libcpu/aarch64/cortex-a72/entry_point.S
new file mode 100644
index 0000000000..6d2c69226b
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/entry_point.S
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2020-01-15     bigmagic    the first version
+ */
+
+.section ".text.entrypoint"
+
+.set EL1_stack,         __el1_stack
+
+.global _start
+
+// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
+// loads 'kernel8.img' file in.
+_start:
+    // read cpu id, stop slave cores
+    mrs     x1, mpidr_el1            // MPIDR_EL1: Multi-Processor Affinity Register
+    and     x1, x1, #3
+    cbz     x1, .L__cpu_0             // .L prefix is the local label in ELF 
+
+    // cpu id > 0, stop
+    // cpu id == 0 will also goto here after returned from entry() if possible
+.L__current_cpu_idle:
+    wfe
+    b       .L__current_cpu_idle
+
+.L__cpu_0:  // cpu id == 0
+
+    // set stack before our code
+
+	/* Define stack pointer for current exception level */
+	// ldr	x2, =EL1_stack
+	// mov	sp, x2
+
+    ldr     x1, =_start
+
+    // set up EL1
+    mrs     x0, CurrentEL           // CurrentEL Register. bit 2, 3. Others reserved
+    and     x0, x0, #12             // clear reserved bits
+
+    // running at EL3?
+    cmp     x0, #12                // 1100b. So, EL3
+    bne     .L__not_in_el3         // 11?  !EL3 -> 5:
+
+    // should never be executed, just for completeness. (EL3)
+    mov     x2, #0x5b1
+    msr     scr_el3, x2            // SCR_ELn  Secure Configuration Register
+    mov     x2, #0x3c9
+    msr     spsr_el3, x2           // SPSR_ELn. Saved Program Status Register. 1111001001
+    adr     x2, .L__not_in_el3   
+    msr     elr_el3, x2
+    eret                           // Exception Return: from EL3, continue from .L__not_in_el3
+
+    // running at EL2 or EL1
+.L__not_in_el3:    
+    cmp     x0, #4                 // 0x04  0100 EL1
+    beq     .L__in_el1             // EL1 -> 5:
+
+    // in EL2
+    msr     sp_el1, x1             // Set sp of EL1 to _start
+
+    // enable CNTP for EL1
+    mrs     x0, cnthctl_el2         // Counter-timer Hypervisor Control register
+    orr     x0, x0, #3
+    msr     cnthctl_el2, x0
+    msr     cntvoff_el2, xzr
+
+    // enable AArch64 in EL1
+    mov     x0, #(1 << 31)          // AArch64
+    orr     x0, x0, #(1 << 1)       // SWIO hardwired on Pi3
+    msr     hcr_el2, x0
+    mrs     x0, hcr_el2
+
+    // change execution level to EL1
+    mov     x2, #0x3c4
+    msr     spsr_el2, x2        // 1111000100
+    adr     x2, .L__in_el1
+    msr     elr_el2, x2
+    eret                        // exception return. from EL2. continue from .L__in_el1
+
+.L__in_el1:
+    mov     sp, x1             // in EL1. Set sp to _start
+
+    // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
+    mov     x1, #0x00300000       // Don't trap any SIMD/FP instructions in both EL0 and EL1
+    msr     cpacr_el1, x1
+
+    mrs x1, sctlr_el1
+    orr x1, x1, #(1 << 12)
+    bic x1, x1, #(3 << 3)
+    bic x1, x1, #(1 << 1)
+    msr sctlr_el1, x1
+
+    // clear bss
+    ldr     x1, =__bss_start
+    ldr     w2, =__bss_size
+
+.L__clean_bss_loop:
+    cbz     w2, .L__jump_to_entry
+    str     xzr, [x1], #8
+    sub     w2, w2, #1
+    cbnz    w2, .L__clean_bss_loop
+
+    // jump to C code, should not return
+.L__jump_to_entry:
+    bl      entry
+    // for failsafe, halt this core too
+    b       .L__current_cpu_idle
diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c
new file mode 100644
index 0000000000..d770259d61
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/interrupt.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <gic_pl400.h>
+#include <board.h>
+#include <armv8.h>
+
+#define MAX_HANDLERS                256
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+extern int system_vectors;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_ubase_t rt_interrupt_from_thread;
+rt_ubase_t rt_interrupt_to_thread;
+rt_ubase_t rt_thread_switch_interrupt_flag;
+
+void rt_hw_vector_init(void)
+{
+    rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);  // cpu_gcc.S
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    initIRQController();
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a72/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h
new file mode 100644
index 0000000000..0d2d4867c7
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/interrupt.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/libcpu/aarch64/cortex-a72/stack.c b/libcpu/aarch64/cortex-a72/stack.c
new file mode 100644
index 0000000000..68222c2c67
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/stack.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+
+#include <armv8.h>
+
+#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
+#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
+#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_ubase_t *stk;
+	rt_ubase_t current_el;
+
+	stk 	 = (rt_ubase_t*)stack_addr;
+
+	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
+	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
+	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
+	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
+	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
+	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
+	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
+	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
+	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
+	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
+	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
+	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
+	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
+	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
+	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
+	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
+	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
+	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
+	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
+	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
+	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
+	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
+	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
+	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
+	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
+	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
+	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
+	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
+	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
+	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+
+	current_el = rt_hw_get_current_el();
+
+	if(current_el == 3)
+	{
+		*(--stk) = INITIAL_SPSR_EL3;
+	}
+	else if(current_el == 2)
+	{
+		*(--stk) = INITIAL_SPSR_EL2;
+	}
+	else
+	{
+		*(--stk) = INITIAL_SPSR_EL1;
+	}
+
+	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/aarch64/cortex-a72/trap.c b/libcpu/aarch64/cortex-a72/trap.c
new file mode 100644
index 0000000000..d93aa18fd6
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/trap.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "interrupt.h"
+#include "armv8.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
+    rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
+	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
+	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("error exception:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_ack(int fiq_irq);
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    int ir; 
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    ir = rt_hw_interrupt_get_irq();
+    if (ir == 1023)
+    {
+        /* Spurious interrupt */
+        return;
+    }
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+    isr_table[ir].counter++;
+#endif
+    if (isr_func)
+    {
+        /* Interrupt for myself. */
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
+
+}
+
+void rt_hw_trap_fiq(void)
+{
+}
-- 
cgit v1.3.1


From 709e0d5799a57e9904d856fd94a935bd1deb153d Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 16 Apr 2020 18:48:27 +0800
Subject: add bsp/raspi4 gicv2

---
 bsp/raspberry-pi/raspi4/driver/board.c |   7 +-
 bsp/raspberry-pi/raspi4/driver/iomap.h |   1 +
 bsp/raspberry-pi/raspi4/rtconfig.py    |   2 +-
 libcpu/aarch64/common/gic/gic_pl400.c  | 478 +++++++++++++--------------------
 libcpu/aarch64/common/gic/gic_pl400.h  |  94 ++++---
 libcpu/aarch64/cortex-a72/interrupt.c  |  50 +++-
 6 files changed, 299 insertions(+), 333 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi4/driver/board.c b/bsp/raspberry-pi/raspi4/driver/board.c
index 9716755b72..46d629a35d 100644
--- a/bsp/raspberry-pi/raspi4/driver/board.c
+++ b/bsp/raspberry-pi/raspi4/driver/board.c
@@ -75,10 +75,6 @@ void rt_hw_board_init(void)
     rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
     rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
 
-    /* initialize timer for os tick */
-    rt_hw_timer_init();
-    rt_thread_idle_sethook(idle_wfi);
-
     /* initialize uart */
     rt_hw_uart_init();      // driver/drv_uart.c
 #ifdef RT_USING_CONSOLE
@@ -91,6 +87,9 @@ void rt_hw_board_init(void)
     rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
     rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
 #endif
+        /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
 
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
diff --git a/bsp/raspberry-pi/raspi4/driver/iomap.h b/bsp/raspberry-pi/raspi4/driver/iomap.h
index 00fc2025d9..675cd147e3 100644
--- a/bsp/raspberry-pi/raspi4/driver/iomap.h
+++ b/bsp/raspberry-pi/raspi4/driver/iomap.h
@@ -1,6 +1,7 @@
 #ifndef __RASPI4_H__
 #define __RASPI4_H__
 
+#define ARM_GIC_NR_IRQS     512
 #define INTC_BASE   0xff800000
 #define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
 #define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py
index 9265b016be..a1dd168d3d 100644
--- a/bsp/raspberry-pi/raspi4/rtconfig.py
+++ b/bsp/raspberry-pi/raspi4/rtconfig.py
@@ -32,7 +32,7 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY  = PREFIX + 'objcopy'
 
-    DEVICE = ' -march=armv8-a -mtune=cortex-a57'
+    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
     CFLAGS = DEVICE + ' -Wall'
     AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
     LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c
index eb35c5b2a4..4d003a9dcd 100644
--- a/libcpu/aarch64/common/gic/gic_pl400.c
+++ b/libcpu/aarch64/common/gic/gic_pl400.c
@@ -1,368 +1,262 @@
 /*
- * Copyright 2014, General Dynamics C4 Systems
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- * This software may be distributed and modified according to the terms of
- * the GNU General Public License version 2. Note that NO WARRANTY is provided.
- * See "LICENSE_GPLv2.txt" for details.
+ * SPDX-License-Identifier: Apache-2.0
  *
- * @TAG(GD_GPL)
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2014-04-03     Grissiom     many enhancements
+ * 2018-11-22     Jesven       add rt_hw_ipi_send()
+ *                             add rt_hw_ipi_handler_install()
  */
+#include <rtthread.h>
 
 #include "gic_pl400.h"
+#include "cp15.h"
 #include "iomap.h"
 
-#define BIT(n) (1ul<<(n))
-#define MASK(n) (BIT(n)-1ul)
-
-/* Setters/getters helpers */
-#define IRQ_REG(IRQ) ((IRQ) / 32)
-#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
-#define IRQ_MASK MASK(10)
-#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < SPECIAL_IRQ_START)
+#define ARM_GIC_MAX_NR 1
+struct arm_gic
+{
+    rt_uint32_t offset;         /* the first interrupt index in the vector table */
 
-#define CPU(X) (1<<(X))
-#define TARGET_CPU_ALLINT(CPU) ( \
-        ( ((CPU)&0xff)<<0  ) |\
-        ( ((CPU)&0xff)<<8  ) |\
-        ( ((CPU)&0xff)<<16 ) |\
-        ( ((CPU)&0xff)<<24 ) \
-    )
-#define TARGET_CPU0_ALLINT   TARGET_CPU_ALLINT(CPU(0))
+    rt_uint32_t dist_hw_base;   /* the base address of the gic distributor */
+    rt_uint32_t cpu_hw_base;    /* the base addrees of the gic cpu interface */
+};
 
+/* 'ARM_GIC_MAX_NR' is the number of cores */
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
 
-#define IRQ_SET_ALL 0xffffffff;
+static unsigned int _gic_max_irq;
 
-/* Special IRQ's */
-#define SPECIAL_IRQ_START 1020
-#define IRQ_NONE          1023
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
 
-/* Memory map for GIC distributor */
-struct gic_dist_map {
-    uint32_t enable;                /* 0x000 */
-    uint32_t ic_type;               /* 0x004 */
-    uint32_t dist_ident;            /* 0x008 */
-    uint32_t res1[29];              /* [0x00C, 0x080) */
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-    uint32_t group[32];          /* [0x080, 0x100) */
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
 
-    uint32_t enable_set[32];        /* [0x100, 0x180) */
-    uint32_t enable_clr[32];        /* [0x180, 0x200) */
-    uint32_t pending_set[32];       /* [0x200, 0x280) */
-    uint32_t pending_clr[32];       /* [0x280, 0x300) */
-    uint32_t active[32];            /* [0x300, 0x380) */
-    uint32_t active_clr[32];        /* [0x380, 0x400) */
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
 
-    uint32_t priority[255];         /* [0x400, 0x7FC) */
-    uint32_t res2;                  /* 0x7FC */
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-    uint32_t targets[255];          /* [0x800, 0xBFC) */
-    uint32_t res3;                  /* 0xBFC */
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
 
-    uint32_t config[64];             /* [0xC00, 0xD00) */
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
 
-    uint32_t ppi_status;            /* [0xD00, 0xD04) */
-    uint32_t spi_status[15];        /* [0xD04, 0xD40) */
-    uint32_t res4[112];              /* [0xD40, 0xF00) */
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
 
-    uint32_t sgi_control;           /* 0xF00 */
-    uint32_t res5[3];               /* [0xF04, 0xF10) */
-    uint32_t sgi_pending_clr[4];    /* [0xF10, 0xF20) */
-    uint32_t sgi_pending_set[4];    /* [0xF20, 0xF30) */
-    uint32_t res10[40];             /* [0xF30, 0xFD0) */
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-    uint32_t periph_id[8];         /* [0xFD0, 0xFF0) */
-    uint32_t component_id[4];       /* [0xFF0, 0xFFF] */
-};
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
 
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
 
-/* Memory map for GIC  cpu interface */
-struct gic_cpu_iface_map {
-    uint32_t icontrol;              /*  0x000         */
-    uint32_t pri_msk_c;             /*  0x004         */
-    uint32_t bp_c;                  /*  0x008         */
-    uint32_t int_ack;               /*  0x00C         */
-    uint32_t eoi;                   /*  0x010         */
-    uint32_t run_priority;          /*  0x014         */
-    uint32_t hi_pend;               /*  0x018         */
-    uint32_t ns_alias_bp_c;         /*  0x01C         */
-    uint32_t ns_alias_ack;          /*  0x020 GIC_PL400 only */
-    uint32_t ns_alias_eoi;          /*  0x024 GIC_PL400 only */
-    uint32_t ns_alias_hi_pend;      /*  0x028 GIC_PL400 only */
-
-    uint32_t res1[41];              /* [0x02C, 0x0D0) */
-    uint32_t active_priority[4];    /* [0x0D0, 0xC0] GIC_PL400 only */
-    uint32_t ns_active_priority[4]; /* [0xE0,0xF0] GIC_PL400 only */
-    uint32_t res4[3];               /* [0xF0, 0xFC] */
-
-    uint32_t cpu_if_ident;          /*  0x0FC         */
-    uint32_t deactive;              /* [0x1000] */
-};
+void arm_gic_clear_pending(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
 
-volatile struct gic_dist_map *gic_dist =
-    (volatile struct gic_dist_map*)(GIC_PL400_DISTRIBUTOR_PPTR);
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-volatile struct gic_cpu_iface_map *gic_cpuiface =
-    (volatile struct gic_cpu_iface_map*)(GIC_PL400_CONTROLLER_PPTR);
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
 
-/* Helpers */
-static inline int
-is_irq_pending(irq_t irq)
-{
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    return !!(gic_dist->pending_set[word] & BIT(bit));
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
-static inline int
-is_irq_active(irq_t irq)
+void arm_gic_clear_active(rt_uint32_t index, int irq)
 {
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    return !!(gic_dist->active[word] & BIT(bit));
-}
+    rt_uint32_t mask = 1 << (irq % 32);
 
-static inline int
-is_irq_enabled(irq_t irq)
-{
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    return !!(gic_dist->enable_set[word] & BIT(bit));
-}
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-static inline int
-is_irq_edge_triggered(irq_t irq)
-{
-    int word = irq / 16;
-    int bit = ((irq & 0xf) * 2);
-    return !!(gic_dist->config[word] & BIT(bit + 1));
-}
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
 
-static inline int
-is_irq_1_N(irq_t irq)
-{
-    int word = irq / 16;
-    int bit = ((irq & 0xf) * 2);
-    return !!(gic_dist->config[word] & BIT(bit + 0));
+    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
-static inline int
-is_irq_N_N(irq_t irq)
+/* Set up the cpu mask for the specific interrupt */
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
 {
-    return !(is_irq_1_N(irq));
-}
+    rt_uint32_t old_tgt;
 
-static inline void
-dist_pending_clr(irq_t irq)
-{
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    /* Using |= here is detrimental to your health */
-    gic_dist->pending_clr[word] = BIT(bit);
-}
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-static inline void
-dist_pending_set(irq_t irq)
-{
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    gic_dist->pending_set[word] = BIT(bit);
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
 }
 
-static inline void
-dist_enable_clr(irq_t irq)
+void arm_gic_umask(rt_uint32_t index, int irq)
 {
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    /* Using |= here is detrimental to your health */
-    gic_dist->enable_clr[word] = BIT(bit);
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
-static inline void
-dist_enable_set(irq_t irq)
+void arm_gic_dump_type(rt_uint32_t index)
 {
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    gic_dist->enable_set[word] = BIT(bit);
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
 }
 
-/**
-   DONT_TRANSLATE
- */
-static void dist_init(void)
+void arm_gic_dump(rt_uint32_t index)
 {
-    int i;
-    int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
-    gic_dist->enable = 0;
-
-#if 0
-    /* configure to group 0 for security */
-    for (i = 0; i < nirqs; i += 32) {
-        gic_dist->group[i / 32] = 0xffffffff;
-    }
-#endif
-
-    for (i = 0; i < nirqs; i += 32) {
-        /* disable */
-        gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
-        /* clear pending */
-        gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
-    }
-
-    /* reset interrupts priority */
-    for (i = 32; i < nirqs; i += 4) {
-        gic_dist->priority[i / 4] = 0x0;
+    unsigned int i, k;
+
+    k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+    rt_kprintf("--- hw mask ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
     }
-
-    /*
-     * reset int target to cpu 0
-     * (Should really query which processor we're running on and use that)
-     */
-    for (i = 0; i < nirqs; i += 4) {
-        gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
+    rt_kprintf("\n--- hw pending ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
+                                        i * 32));
     }
-
-    /* level-triggered, 1-N */
-    for (i = 64; i < nirqs; i += 32) {
-        gic_dist->config[i / 32] = 0;
-        //gic_dist->config[i / 32] = 0x55555555;
+    rt_kprintf("\n--- hw active ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
     }
-    /* enable the int controller */
-    gic_dist->enable = 1;
+    rt_kprintf("\n");
 }
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
+#endif
 
-/**
-   DONT_TRANSLATE
- */
-static void cpu_iface_init(void)
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
 {
-    uint32_t i;
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
 
-    /* For non-Exynos4, the registers are banked per CPU, need to clear them */
-    gic_dist->enable_clr[0] = IRQ_SET_ALL;
-    gic_dist->pending_clr[0] = IRQ_SET_ALL;
-    gic_dist->priority[0] = 0x00;
-    /* put everything in group 0 */
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-    /* clear any software generated interrupts */
-    for (i = 0; i < 16; i += 4) {
-        gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
-    }
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
 
-    gic_cpuiface->icontrol = 0;
-    gic_cpuiface->pri_msk_c = 0x000000f0;
-    gic_cpuiface->bp_c = 0x00000003;
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
 
-    while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != IRQ_NONE) {
-        gic_cpuiface->eoi = i;
-    }
-    gic_cpuiface->icontrol = 0x1;
-}
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
+        _gic_max_irq = ARM_GIC_NR_IRQS;
 
-/**
-   DONT_TRANSLATE
- */
-void initIRQController(void)
-{
-    dist_init();
-    cpu_iface_init();
-}
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+    cpumask |= cpumask << 24;
 
+    GIC_DIST_CTRL(dist_base) = 0x0;
 
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
 
-/*
- * The only sane way to get an GIC IRQ number that can be properly
- * ACKED later is through the int_ack register. Unfortunately, reading
- * this register changes the interrupt state to pending so future
- * reads will not return the same value For this reason, we have a
- * global variable to store the IRQ number.
- */
-static uint32_t active_irq = IRQ_NONE;
-
-/**
-   DONT_TRANSLATE
- */
-interrupt_t
-getActiveIRQ(void)
-{
-    uint32_t irq;
-    if (!IS_IRQ_VALID(active_irq)) {
-        active_irq = gic_cpuiface->int_ack;
-    }
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
 
-    if (IS_IRQ_VALID(active_irq)) {
-        irq = active_irq & IRQ_MASK;
-    } else {
-        irq = 1023;
-    }
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
 
-    return irq;
-}
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
 
-/*
- * GIC has 4 states: pending->active(+pending)->inactive
- * seL4 expects two states: active->inactive.
- * We ignore the active state in GIC to conform
- */
-/**
-   DONT_TRANSLATE
- */
-bool_t
-isIRQPending(void)
-{
-    return IS_IRQ_VALID(gic_cpuiface->hi_pend);
-}
+#if 0
+    /* All interrupts defaults to IGROUP1(IRQ). */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
+#endif
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0;
 
+    /* Enable group0 and group1 interrupt forwarding. */
+    GIC_DIST_CTRL(dist_base) = 0x01;
 
-/**
-   DONT_TRANSLATE
- */
-void
-maskInterrupt(bool_t disable, interrupt_t irq)
-{
-    if (disable) {
-        dist_enable_clr(irq);
-    } else {
-        dist_enable_set(irq);
-    }
+    return 0;
 }
 
-/**
-   DONT_TRANSLATE
- */
-void
-ackInterrupt(irq_t irq)
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
 {
-    if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq)) {
-		return;
-	}
-    if (is_irq_edge_triggered(irq)) {
-        dist_pending_clr(irq);
-    }
-    gic_cpuiface->eoi = active_irq;
-    active_irq = IRQ_NONE;
-}
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-void
-handleSpuriousIRQ(void)
-{
-}
+    _gic_table[index].cpu_hw_base = cpu_base;
 
-void rt_hw_interrupt_mask(int vector)
-{
-    maskInterrupt(1, vector);
-}
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    GIC_CPU_BINPOINT(cpu_base) = 0x7;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
 
-void rt_hw_interrupt_umask(int vector)
-{
-    maskInterrupt(0, vector);
+    return 0;
 }
 
-int rt_hw_interrupt_get_irq(void)
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
 {
-    return getActiveIRQ();
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
 }
 
-void rt_hw_interrupt_ack(int fiq_irq)
-{
-    return ackInterrupt(fiq_irq);
-}
diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h
index a43583bd7c..fa20846ea2 100644
--- a/libcpu/aarch64/common/gic/gic_pl400.h
+++ b/libcpu/aarch64/common/gic/gic_pl400.h
@@ -1,35 +1,61 @@
-
-#ifndef __ARCH_MACHINE_GIC_PL400_H
-#define __ARCH_MACHINE_GIC_PL400_H
-
-#include <stdint.h>
-
-typedef uint16_t interrupt_t;
-typedef uint16_t irq_t;
-typedef uint64_t  bool_t;
-
-/** MODIFIES: [*] */
-interrupt_t getActiveIRQ(void);
-/** MODIFIES: [*] */
-interrupt_t getPendingIRQ(void);
-/** MODIFIES: [*] */
-bool_t isIRQPending(void);
-/** MODIFIES: [*] */
-void maskInterrupt(bool_t disable, interrupt_t irq);
-/** MODIFIES: [*] */
-void ackInterrupt(irq_t irq);
-/** MODIFIES: [*] */
-static inline void setInterruptMode(irq_t irq, bool_t levelTrigger, bool_t polarityLow) { }
-
-/** MODIFIES: [*] */
-void initIRQController(void);
-
-void handleSpuriousIRQ(void);
-
-void rt_hw_interrupt_umask(int vector);
-
-int rt_hw_interrupt_get_irq(void);
-
-void rt_hw_interrupt_ack(int fiq_irq);
-#endif /* !__ARCH_MACHINE_GIC400_H */
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#ifndef __GIC_PL400_H__
+#define __GIC_PL400_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_clear_active(rt_uint32_t index, int irq);
+void arm_gic_clear_pending(rt_uint32_t index, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+void arm_gic_dump(rt_uint32_t index);
+
+#endif
 
diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c
index d770259d61..6fec968dc2 100644
--- a/libcpu/aarch64/cortex-a72/interrupt.c
+++ b/libcpu/aarch64/cortex-a72/interrupt.c
@@ -13,8 +13,10 @@
 #include <gic_pl400.h>
 #include <board.h>
 #include <armv8.h>
+#include "iomap.h"
 
 #define MAX_HANDLERS                256
+#define GIC_ACK_INTID_MASK          0x000003ff
 
 #ifdef RT_USING_SMP
 #define rt_interrupt_nest rt_cpu_self()->irq_nest
@@ -41,7 +43,15 @@ void rt_hw_vector_init(void)
  */
 void rt_hw_interrupt_init(void)
 {
-    initIRQController();
+
+    rt_uint32_t gic_cpu_base = 0;
+    rt_uint32_t gic_dist_base = 0;
+
+    /* initialize ARM GIC */
+    gic_dist_base = GIC_PL400_DISTRIBUTOR_PPTR;
+    gic_cpu_base = GIC_PL400_CONTROLLER_PPTR;
+    arm_gic_dist_init(0, gic_dist_base, 0);
+    arm_gic_cpu_init(0, gic_cpu_base);
 }
 
 /**
@@ -70,4 +80,40 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
     }
 
     return old_handler;
-}
\ No newline at end of file
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    arm_gic_mask(0, vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    arm_gic_umask(0, vector);
+}
+
+/**
+ * This function returns the active interrupt number.
+ * @param none
+ */
+int rt_hw_interrupt_get_irq(void)
+{
+    return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK;
+}
+
+/**
+ * This function acknowledges the interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_ack(int vector)
+{
+    arm_gic_ack(0, vector);
+}
-- 
cgit v1.3.1


From 90f41ef8a2a9e7f71343be12d2f73122e17b1fc2 Mon Sep 17 00:00:00 2001
From: David Lin <linpeng1577@gmail.com>
Date: Fri, 17 Apr 2020 19:12:18 +0800
Subject: Update start_gcc.S

---
 libcpu/arm/s3c24x0/start_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/s3c24x0/start_gcc.S b/libcpu/arm/s3c24x0/start_gcc.S
index 4adc458094..cc2b2f6310 100644
--- a/libcpu/arm/s3c24x0/start_gcc.S
+++ b/libcpu/arm/s3c24x0/start_gcc.S
@@ -191,7 +191,7 @@ reset:
 copy_loop:
 	ldmia	r0!, {r3-r10}			/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}			/* copy to   target address [r1]    */
-	cmp		r0, r2					/* until source end addreee [r2]    */
+	cmp		r0, r2			/* until source end address [r2]    */
 	ble		copy_loop
 
 	/* setup stack */
-- 
cgit v1.3.1


From 5e507448ee71499aa1fbaa1f273372318f569331 Mon Sep 17 00:00:00 2001
From: David Lin <linpeng1577@gmail.com>
Date: Fri, 17 Apr 2020 19:18:52 +0800
Subject: Update start_gcc.S

---
 libcpu/arm/s3c44b0/start_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/s3c44b0/start_gcc.S b/libcpu/arm/s3c44b0/start_gcc.S
index 65b3d422dd..4c448a344f 100644
--- a/libcpu/arm/s3c44b0/start_gcc.S
+++ b/libcpu/arm/s3c44b0/start_gcc.S
@@ -107,7 +107,7 @@ reset:
 copy_loop:
 	ldmia	r0!, {r3-r10}	/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}	/* copy to   target address [r1]    */
-	cmp	r0, r2				/* until source end addreee [r2]    */
+	cmp	r0, r2		/* until source end address [r2]    */
 	ble	copy_loop
 #endif
 	
-- 
cgit v1.3.1


From ee4cabe69f90cd2bde042d7d8d114e420b09319f Mon Sep 17 00:00:00 2001
From: Huaqi Fang <578567190@qq.com>
Date: Fri, 17 Apr 2020 21:07:29 +0800
Subject: [BSP][Nuclei] Add Nuclei RISC-V Processor support

* Nuclei RISC-V Processor support is added both RV32 and RV64
* Nuclei RVSTAR BSP is added, UART driver is added
* MSH works well in RVSTAR board

---------------------------

Squashed commit of the following:

commit b7368bc2ed725c42f9adc297d0e9cf3ed706a520
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 17 14:38:54 2020 +0800

    [BSP][Nuclei] Pretty source code

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 2c42a997f7b5d8aa53bdaf19ccb30596091a112d
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 16 15:51:03 2020 +0800

    [libcpu] Remove ARCH_NUCLEI in libcpu kconfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 915ad4c076ff3d7cebda896537605e7f7939b7af
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 16 15:50:00 2020 +0800

    [BSP][Nuclei] Remove ARCH_NUCLEI in bsp KConfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit fe43869c79675a25669447d57ea5d77385e07ca5
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 15 12:43:20 2020 +0800

    [BSP][NUCLEI] Simply application main.c

    Remove previous complicated application of gd32vf103_rvstar

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 8fd31727bc7ff51c83a3c47840cff1bfb100c0ba
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 15 12:38:04 2020 +0800

    [BSP][NUCLEI] Format application and board source code

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit b432308b20cdf24dfcc1398511d1d83bce6a9df2
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 15 11:58:28 2020 +0800

    [BSP][Nuclei] Format source code of drivers of gd32vf103

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 7366173d749d8a51ed8d48eca09007d27aee8ad8
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 15 11:54:02 2020 +0800

    [LIBCPU][NUCLEI] Optimize nuclei cpu portable code

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 8c2cd4745b7279a6721946d119441bbf7fd1a9c2
Author: Huaqi Fang <578567190@qq.com>
Date:   Tue Apr 14 15:45:42 2020 +0800

    nuclei: Update README.md

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit fa8a2f24ea5e4dbce714ffda16c1ce558e5b5ddb
Author: Huaqi Fang <578567190@qq.com>
Date:   Tue Apr 14 14:06:54 2020 +0800

    nuclei: Add gpio driver not tested

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 1be40bc50be43dfcdd105291bd24355498f9fef3
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 9 14:55:22 2020 +0800

    Nuclei: Update README.md

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 4c8beb204b7ee3e38c04e1f23a1f7e4ce48aa196
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 9 10:20:25 2020 +0800

    Nuclei: Change idle stack size from 256 to 396 bytes

    If changed to 396 bytes, then debug optimization level changed
    from O2 to O0, and the application can run successfully without
    stack overflow issue of tidle0 task
    warning: tidle0 stack is close to end of stack address.

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit da2bcf5c56ef32b611405a8e591ecd3f1e598b11
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 9 10:11:40 2020 +0800

    nuclei: Remove unused kconfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 0b932c677a7934d60e70da141744790aec202ef6
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 9 09:32:22 2020 +0800

    nuclei: optimize drivers support

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 0431f6f01f6efab2900de552abede83639415431
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 8 19:28:02 2020 +0800

    tools: Update mkdist.py for nuclei bsp

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 0e1f502edfddff93a4a66c041be68560ef4828eb
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 8 18:46:58 2020 +0800

    nuclei: optimize rvstar support directory

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 1131f6e6483d8f2fbafe07f4e598fc8f802ee85d
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 8 18:37:24 2020 +0800

    nuclei: update kconfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit ad81c1d3bf9d80d2b561c94e903e7ce4ca2c68c6
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 8 15:43:00 2020 +0800

    nuclei: Rename board name

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit d780138a1abf5da5097cc89e6a428ebeae06f284
Author: Huaqi Fang <578567190@qq.com>
Date:   Tue Apr 7 09:36:19 2020 +0800

    libcpu: Add Nuclei arch option in KConfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 60320d34b1d88315efe1b566fd6bc75c69851f06
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 16:51:01 2020 +0800

    nuclei: Update nuclei sdk of rt-thread support

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit a042b806efe0ea3bc9dba80ebc7696e5941ba35f
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 11:34:09 2020 +0800

    nuclei: modify application for not print anything

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 2a9603adcb584b29886a2b93ded2473f4e8bffb1
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 11:31:01 2020 +0800

    nuclei: Add .gitignore for nuclei bsp

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 34aaf6aebae75c3ee9d38cc17e6bdb826ed9e357
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 11:28:06 2020 +0800

    nuclei_sdk: update link script of rvstar to contain rt-thread needed sections

            /* section information for finsh shell */
            . = ALIGN(4);
            __fsymtab_start = .;
            KEEP(*(FSymTab))
            __fsymtab_end = .;

            . = ALIGN(4);
            __vsymtab_start = .;
            KEEP(*(VSymTab))
            __vsymtab_end = .;

            /* section information for initial. */
            . = ALIGN(4);
            __rt_init_start = .;
            KEEP(*(SORT(.rti_fn*)))
            __rt_init_end = .;

    The above code placed in rodata section

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 3451466e9d8da3c3c8a631be69f3c7a5e6220c21
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 10:04:42 2020 +0800

    bsp: Add initial commit of nuclei rvstar board bsp

    Signed-off-by: Huaqi Fang <578567190@qq.com>

Signed-off-by: Huaqi Fang <578567190@qq.com>
---
 bsp/nuclei/.gitignore                              |  26 ++
 bsp/nuclei/gd32vf103_rvstar/.config                | 453 ++++++++++++++++++
 bsp/nuclei/gd32vf103_rvstar/Kconfig                |  28 ++
 bsp/nuclei/gd32vf103_rvstar/README.md              | 209 +++++++++
 bsp/nuclei/gd32vf103_rvstar/SConscript             |  17 +
 bsp/nuclei/gd32vf103_rvstar/SConstruct             |  85 ++++
 .../gd32vf103_rvstar/applications/SConscript       |  11 +
 bsp/nuclei/gd32vf103_rvstar/applications/main.c    |  19 +
 bsp/nuclei/gd32vf103_rvstar/board/Kconfig          |  47 ++
 bsp/nuclei/gd32vf103_rvstar/board/SConscript       |  11 +
 bsp/nuclei/gd32vf103_rvstar/board/board.c          |  67 +++
 bsp/nuclei/gd32vf103_rvstar/board/board.h          |  21 +
 bsp/nuclei/gd32vf103_rvstar/rtconfig.h             | 181 +++++++
 bsp/nuclei/gd32vf103_rvstar/rtconfig.py            |  58 +++
 .../libraries/gd32vf103/HAL_Drivers/SConscript     |  21 +
 .../libraries/gd32vf103/HAL_Drivers/drv_config.h   |  26 ++
 .../libraries/gd32vf103/HAL_Drivers/drv_gpio.c     | 520 +++++++++++++++++++++
 .../libraries/gd32vf103/HAL_Drivers/drv_gpio.h     |  51 ++
 .../libraries/gd32vf103/HAL_Drivers/drv_usart.c    | 347 ++++++++++++++
 .../libraries/gd32vf103/HAL_Drivers/drv_usart.h    |  36 ++
 libcpu/risc-v/SConscript                           |   3 +-
 libcpu/risc-v/nuclei/SConscript                    |  14 +
 libcpu/risc-v/nuclei/context_gcc.S                 | 188 ++++++++
 libcpu/risc-v/nuclei/cpuport.c                     | 259 ++++++++++
 libcpu/risc-v/nuclei/cpuport.h                     |  40 ++
 libcpu/risc-v/nuclei/interrupt_gcc.S               | 218 +++++++++
 tools/mkdist.py                                    |   7 +
 27 files changed, 2962 insertions(+), 1 deletion(-)
 create mode 100644 bsp/nuclei/.gitignore
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/.config
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/Kconfig
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/README.md
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/SConscript
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/SConstruct
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/applications/SConscript
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/applications/main.c
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/Kconfig
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/SConscript
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/board.c
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/board.h
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/rtconfig.h
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/rtconfig.py
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h
 create mode 100644 libcpu/risc-v/nuclei/SConscript
 create mode 100644 libcpu/risc-v/nuclei/context_gcc.S
 create mode 100644 libcpu/risc-v/nuclei/cpuport.c
 create mode 100644 libcpu/risc-v/nuclei/cpuport.h
 create mode 100644 libcpu/risc-v/nuclei/interrupt_gcc.S

(limited to 'libcpu')

diff --git a/bsp/nuclei/.gitignore b/bsp/nuclei/.gitignore
new file mode 100644
index 0000000000..975dcc6995
--- /dev/null
+++ b/bsp/nuclei/.gitignore
@@ -0,0 +1,26 @@
+*.i
+*.o
+*.d
+*.elf
+*.diss
+*.map
+*.bin
+*.log
+.vscode
+
+*.dump
+*.verilog
+
+*.swp
+*.swo
+
+prebuilt_tools/
+setup_config.sh
+setup_config.bat
+
+tags
+TAGS
+TAG
+CTAGS
+Makefile.local
+Makefile.global
diff --git a/bsp/nuclei/gd32vf103_rvstar/.config b/bsp/nuclei/gd32vf103_rvstar/.config
new file mode 100644
index 0000000000..c68135acc4
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/.config
@@ -0,0 +1,453 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=396
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+CONFIG_RT_DEBUG_INIT_CONFIG=y
+CONFIG_RT_DEBUG_INIT=1
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart4"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+CONFIG_PKG_USING_NUCLEI_SDK=y
+CONFIG_PKG_NUCLEI_SDK_PATH="/packages/peripherals/nuclei_sdk"
+# CONFIG_PKG_USING_NUCLEI_SDK_V023 is not set
+CONFIG_PKG_USING_NUCLEI_SDK_LATEST_VERSION=y
+CONFIG_PKG_NUCLEI_SDK_VER="latest"
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_GD32VF103V=y
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_USING_UART_CONSOLE=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART0 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+CONFIG_BSP_USING_UART4=y
+
+#
+# Board extended module Drivers
+#
+CONFIG_SOC_GD32VF103=y
diff --git a/bsp/nuclei/gd32vf103_rvstar/Kconfig b/bsp/nuclei/gd32vf103_rvstar/Kconfig
new file mode 100644
index 0000000000..fb1ab0ffd5
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/Kconfig
@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+ 
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+
+config SOC_GD32VF103
+    bool
+    select ARCH_RISCV32
+    select PKG_USING_NUCLEI_SDK
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
diff --git a/bsp/nuclei/gd32vf103_rvstar/README.md b/bsp/nuclei/gd32vf103_rvstar/README.md
new file mode 100644
index 0000000000..f9575aa2ee
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/README.md
@@ -0,0 +1,209 @@
+# 芯来科技RVSTAR开发板 #
+
+## 简介
+
+**RVSTAR开发板** 是由芯来科技公司推出的基于采用芯来科技RISC-V架构处理器芯片的GD32VF103的开发板。
+
+更多关于 **RVSTAR开发板** 开发板的详细资料请参见 [RVSTAR开发板快速入门](https://www.rvmcu.com/quickstart-quickstart-index-u-RV_STAR.html)
+
+### 板载资源
+
+| 硬件 | 描述 |
+| ---  | --- |
+| 内核 | Nuclei N205 |
+| 架构 | 32-bit RV32IMAC |
+| 主频 | 108 MHz |
+
+## 工具安装
+
+### 安装工具链
+
+请根据[安装Nuclei RISC-V GCC Toolchain和OpenOCD](https://doc.nucleisys.com/nuclei_sdk/quickstart.html#setup-tools-and-environment) 来安装依赖的工具。
+
+### 添加环境变量
+
+将Nuclei RISC-V GCC Toolchain和OpenOCD的环境变量进行设置。
+
+#### Windows
+
+假设工具安装在 **D:\Software\Nuclei**目录下, 则可以修改系统环境变量**PATH**,
+将**D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;**增加到**PATH**中。
+
+或者在ENV工具命令行中运行
+
+~~~cmd
+set PATH=D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;%PATH%
+~~~
+
+#### Linux
+
+假设工具安装在 **~/Software/Nuclei**目录下, 通过在Linux的``.bashrc``增加如下一行代码
+来添加环境变量。
+
+~~~bash
+export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
+~~~
+
+或者在ENV工具命令行中运行
+
+~~~bash
+export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
+~~~
+
+**注意**: 对应的RISC-V GCC和OPENOCD的路径请替换成自己安装的路径。
+
+## 烧写及执行
+
+### [驱动设置](https://doc.nucleisys.com/nuclei_board_labs/hw/hw.html#on-board-debugger-driver)
+
+### 编译程序
+
+下载好[RT-Thread](https://github.com/RT-Thread/rt-thread)的代码和[ENV工具](https://www.rt-thread.org/document/site/tutorial/env-video/)以后。
+
+按照ENV工具的教程, 在**rt-thread\bsp\nuclei\gd32vf103_rvstar**目录打开ENV工具命令行。
+
+**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。
+
+1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包
+2. **可选**: 运行 ``menuconfig``来进行内核配置
+3. 运行 ``scons -c``清理之前的编译结果
+4. 运行 ``scons``来进行代码的编译
+
+### 下载程序
+
+在保证程序能够正常编译后, 在相同ENV终端执行``scons --run upload``进行代码的下载。
+
+正常下载的输出如下:
+
+~~~
+scons: Reading SConscript files ...
+Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip
+Upload application rtthread.elf using openocd and gdb
+riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240"                     -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg"                     --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load"                     -ex "monitor resume" -ex "monitor shutdown" -ex "quit"
+D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory.
+
+Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43)
+Licensed under GNU GPL v2
+For bug reports, read
+        http://openocd.org/doc/doxygen/bugs.html
+rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:251
+251                 if (idle_hook_list[i] != RT_NULL)
+cleared protection for sectors 0 through 127 on flash bank 0
+
+Loading section .init, size 0x264 lma 0x8000000
+Loading section .text, size 0x140de lma 0x8000280
+Loading section .rodata, size 0x37c0 lma 0x8014360
+Loading section .data, size 0x404 lma 0x8017b20
+Start address 0x800015c, load size 98054
+Transfer rate: 8 KB/sec, 10894 bytes/write.
+shutdown command invoked
+A debugging session is active.
+
+        Inferior 1 [Remote target] will be detached.
+
+Quit anyway? (y or n) [answered Y; input not from terminal]
+Remote communication error.  Target disconnected.: Success.
+~~~
+
+下载程序之后, 连接串口(115200-N-8-1), 可以看到 RT-Thread 的输出信息：
+
+```
+initialize rti_board_start:0 done
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Apr  9 2020
+ 2006 - 2020 Copyright by rt-thread team
+do components initialization.
+initialize rti_board_end:0 done
+initialize dfs_init:0 done
+initialize libc_system_init:0 done
+initialize finsh_system_init:0 done
+msh />
+```
+
+在串口终端(我这里使用的是TeraTerm)输入``ps``即可查看当前线程工作情况:
+
+~~~
+msh />ps
+thread   pri  status      sp     stack size max used left tick  error
+-------- ---  ------- ---------- ----------  ------  ---------- ---
+thread01  19  suspend 0x00000158 0x0000018c    87%   0x00000005 000
+thread00  19  suspend 0x00000158 0x0000018c    87%   0x00000005 000
+tshell    20  running 0x00000258 0x00001000    18%   0x00000004 000
+tidle0    31  ready   0x000000a8 0x0000018c    59%   0x0000000e 000
+timer      4  suspend 0x000000f8 0x00000200    49%   0x00000009 000
+main      10  suspend 0x00000168 0x00000800    36%   0x00000006 000
+msh />
+~~~
+
+### 调试程序
+
+在保证程序编译成功后, 在相同ENV终端执行``scons --run debug``进行代码在命令行下进行GDB调试。
+
+正常的调试输出如下：
+
+~~~
+scons: Reading SConscript files ...
+Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip
+Debug application rtthread.elf using openocd and gdb
+riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240"                     -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg"
+D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory.
+GNU gdb (GDB) 8.3.0.20190516-git
+Copyright (C) 2019 Free Software Foundation, Inc.
+License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
+This is free software: you are free to change and redistribute it.
+There is NO WARRANTY, to the extent permitted by law.
+Type "show copying" and "show warranty" for details.
+This GDB was configured as "--host=i686-w64-mingw32 --target=riscv-nuclei-elf".
+Type "show configuration" for configuration details.
+For bug reporting instructions, please see:
+<http://www.gnu.org/software/gdb/bugs/>.
+Find the GDB manual and other documentation resources online at:
+    <http://www.gnu.org/software/gdb/documentation/>.
+
+For help, type "help".
+Type "apropos word" to search for commands related to "word"...
+Reading symbols from rtthread.elf...
+Remote debugging using | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43)
+Licensed under GNU GPL v2
+For bug reports, read
+        http://openocd.org/doc/doxygen/bugs.html
+rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:249
+249             for (i = 0; i < RT_IDLE_HOOK_LIST_SIZE; i++)
+(gdb)
+(gdb) b main.c:35
+Breakpoint 1 at 0x8000290: file applications\main.c, line 35.
+(gdb) c
+Continuing.
+Note: automatically using hardware breakpoints for read-only addresses.
+
+Breakpoint 1, thread_entry (parameter=0x0) at applications\main.c:35
+35              rt_thread_mdelay(500);
+(gdb)
+~~~
+
+调试例子参见如下文档:
+
+* https://doc.nucleisys.com/nuclei_sdk/quickstart.html#debug-application
+
+为了更方便的进行调试, 也可以下载**Nuclei Studio**集成开发环境, 创建一个Debug Configuration, 选择编译好的
+ELF文件, 然后配置OPENOCD和GDB即可, OPENOCD配置文件路径为**bsp\nuclei\gd32vf103_rvstar\packages\nuclei_sdk-latest\SoC\gd32vf103\Board\gd32vf103v_rvstar\openocd_gd32vf103.cfg**
+
+
+## 驱动支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | RV-STAR板载串口是UART4 |
+
+**注:**
+
+- 适配RT-Thread的驱动框架的代码在 [../libraries/gd32vf103/HAL_Drivers](../libraries/gd32vf103/HAL_Drivers)目录下。
+- 如果有开发者想适配更多的驱动, 请在对应目录下增加驱动适配支持。
+
+## 联系人信息
+
+维护人：
+- [fanghuaqi](https://github.com/fanghuaqi)
+
diff --git a/bsp/nuclei/gd32vf103_rvstar/SConscript b/bsp/nuclei/gd32vf103_rvstar/SConscript
new file mode 100644
index 0000000000..014c428d0a
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/SConscript
@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nuclei/gd32vf103_rvstar/SConstruct b/bsp/nuclei/gd32vf103_rvstar/SConstruct
new file mode 100644
index 0000000000..7adcd69070
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/SConstruct
@@ -0,0 +1,85 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+bsp_library_type = rtconfig.NUCLEI_SDK_SOC
+rtconfig.BSP_LIBRARY_TYPE = bsp_library_type
+
+openocd_cfg = rtconfig.NUCLEI_SDK_OPENOCD_CFG.replace('\\', '/')
+
+# include hal drivers
+hal_sconscript = os.path.join(libraries_path_prefix, bsp_library_type, 'HAL_Drivers', 'SConscript')
+
+if os.path.isfile(hal_sconscript):
+    objs.extend(SConscript(hal_sconscript))
+
+# make a building
+DoBuilding(TARGET, objs)
+
+# Run upload or debug if --run=upload or --upload=debug
+run_target = GetOption('run')
+SUPPORT_RUN_TARGETS = ["upload", "debug"]
+if run_target in SUPPORT_RUN_TARGETS:
+    if os.path.isfile(TARGET):
+        if run_target == "upload":
+            upload_cmd = '{} {} -ex "set remotetimeout 240" \
+                    -ex "target remote | openocd --pipe -f {}" \
+                    --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" \
+                    -ex "monitor resume" -ex "monitor shutdown" -ex "quit"'.format(GDB, TARGET, openocd_cfg)
+            print("Upload application {} using openocd and gdb".format(TARGET))
+            print(upload_cmd)
+            os.system(upload_cmd)
+        elif run_target == "debug":
+            debug_cmd = '{} {} -ex "set remotetimeout 240" \
+                    -ex "target remote | openocd --pipe -f {}"'.format(GDB, TARGET, openocd_cfg)
+            print("Debug application {} using openocd and gdb".format(TARGET))
+            print(debug_cmd)
+            os.system(debug_cmd)
+    else:
+        print(TARGET + ' not exist, please run scons first!!')
+    exit(0)
diff --git a/bsp/nuclei/gd32vf103_rvstar/applications/SConscript b/bsp/nuclei/gd32vf103_rvstar/applications/SConscript
new file mode 100644
index 0000000000..ef1c39fd83
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd, ]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuclei/gd32vf103_rvstar/applications/main.c b/bsp/nuclei/gd32vf103_rvstar/applications/main.c
new file mode 100644
index 0000000000..7da5f0da45
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-15     hqfang       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+int main(int argc, char *argv[])
+{
+    return RT_EOK;
+}
+
+/******************** end of file *******************/
\ No newline at end of file
diff --git a/bsp/nuclei/gd32vf103_rvstar/board/Kconfig b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig
new file mode 100644
index 0000000000..5165ac7629
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig
@@ -0,0 +1,47 @@
+menu "Hardware Drivers Config"
+
+config SOC_GD32VF103V
+    bool
+    select SOC_SERIES_GD32VF103V
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_UART_CONSOLE
+        bool "Enable UART CONSOLE"
+        select BSP_USING_UART
+        select BSP_USING_UART4
+        default y
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+        endif
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/nuclei/gd32vf103_rvstar/board/SConscript b/bsp/nuclei/gd32vf103_rvstar/board/SConscript
new file mode 100644
index 0000000000..148c99f42c
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/board/SConscript
@@ -0,0 +1,11 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.c b/bsp/nuclei/gd32vf103_rvstar/board/board.c
new file mode 100644
index 0000000000..7dad875006
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/board/board.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-02     hqfang       first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "cpuport.h"
+
+#ifdef RT_USING_SERIAL
+    #include <drv_usart.h>
+#endif
+
+/** _end symbol defined in linker script of Nuclei SDK */
+extern void *_end;
+
+/** _heap_end symbol defined in linker script of Nuclei SDK */
+extern void *_heap_end;
+#define HEAP_BEGIN  &_end
+#define HEAP_END    &_heap_end
+
+/*
+ * - Implemented and defined in Nuclei SDK system_<Device>.c file
+ * - Required macro NUCLEI_BANNER set to 0
+ */
+extern void _init(void);
+
+/**
+ * @brief Setup hardware board for rt-thread
+ *
+ */
+void rt_hw_board_init(void)
+{
+    /* OS Tick Configuration */
+    rt_hw_ticksetup();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
+#endif
+
+    _init(); // __libc_init_array is not used in RT-Thread
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+    /* Set the shell console output device */
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/******************** end of file *******************/
+
diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.h b/bsp/nuclei/gd32vf103_rvstar/board/board.h
new file mode 100644
index 0000000000..4e571e3ee2
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/board/board.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author          Notes
+ * 2020-04-02     hqfang          first version
+ *
+ */
+
+#ifndef __BOARD__
+#define __BOARD__
+
+#include "nuclei_sdk_hal.h"
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD__ */
+
+/******************** end of file *******************/
diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.h b/bsp/nuclei/gd32vf103_rvstar/rtconfig.h
new file mode 100644
index 0000000000..2498e39e9d
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.h
@@ -0,0 +1,181 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 396
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+#define RT_DEBUG_INIT_CONFIG
+#define RT_DEBUG_INIT 1
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart4"
+#define RT_VER_NUM 0x40003
+#define ARCH_RISCV
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_NUCLEI_SDK
+#define PKG_USING_NUCLEI_SDK_LATEST_VERSION
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_GD32VF103V
+
+/* Onboard Peripheral Drivers */
+
+#define BSP_USING_UART_CONSOLE
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART4
+
+/* Board extended module Drivers */
+
+#define SOC_GD32VF103
+
+#endif
diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.py b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py
new file mode 100644
index 0000000000..8136b392f8
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py
@@ -0,0 +1,58 @@
+import os
+
+# toolchains options
+ARCH='risc-v'
+CPU='nuclei'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if CROSS_TOOL == 'gcc':
+    PLATFORM  = 'gcc'
+    EXEC_PATH = 'D:/Software/Nuclei/gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+# if os.getenv('RTT_EXEC_PATH'):
+#     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+# Fixed configurations below
+NUCLEI_SDK_SOC = "gd32vf103"
+NUCLEI_SDK_BOARD = "gd32vf103v_rvstar"
+NUCLEI_SDK_DOWNLOAD = "flashxip"
+NUCLEI_SDK_CORE = "n205"
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv-nuclei-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    GDB     = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    CFLAGS  = ' -ffunction-sections -fdata-sections -fno-common '
+    AFLAGS  = CFLAGS
+    LFLAGS  = ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections '
+    LFLAGS += ' -Wl,-cref,-Map=rtthread.map'
+    LFLAGS  += ' -u _isatty -u _write -u _sbrk -u _read -u _close -u _fstat -u _lseek '
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -ggdb'
+        AFLAGS += ' -ggdb'
+    else:
+        CFLAGS += ' -O2 -Os'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript
new file mode 100644
index 0000000000..4761127102
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript
@@ -0,0 +1,21 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_usart.c']
+
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h
new file mode 100644
index 0000000000..bb24afa19e
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-04-08     hqfang            first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c
new file mode 100644
index 0000000000..75ab81f18e
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c
@@ -0,0 +1,520 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-04-09     hqfang            first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+static const struct pin_index pins[] =
+{
+
+    __GD32_PIN(0, A, 0),
+    __GD32_PIN(1, A, 1),
+    __GD32_PIN(2, A, 2),
+    __GD32_PIN(3, A, 3),
+    __GD32_PIN(4, A, 4),
+    __GD32_PIN(5, A, 5),
+    __GD32_PIN(6, A, 6),
+    __GD32_PIN(7, A, 7),
+    __GD32_PIN(8, A, 8),
+    __GD32_PIN(9, A, 9),
+    __GD32_PIN(10, A, 10),
+    __GD32_PIN(11, A, 11),
+    __GD32_PIN(12, A, 12),
+    __GD32_PIN(13, A, 13),
+    __GD32_PIN(14, A, 14),
+    __GD32_PIN(15, A, 15),
+
+    __GD32_PIN(16, B, 0),
+    __GD32_PIN(17, B, 1),
+    __GD32_PIN(18, B, 2),
+    __GD32_PIN(19, B, 3),
+    __GD32_PIN(20, B, 4),
+    __GD32_PIN(21, B, 5),
+    __GD32_PIN(22, B, 6),
+    __GD32_PIN(23, B, 7),
+    __GD32_PIN(24, B, 8),
+    __GD32_PIN(25, B, 9),
+    __GD32_PIN(26, B, 10),
+    __GD32_PIN(27, B, 11),
+    __GD32_PIN(28, B, 12),
+    __GD32_PIN(29, B, 13),
+    __GD32_PIN(30, B, 14),
+    __GD32_PIN(31, B, 15),
+
+    __GD32_PIN(32, C, 0),
+    __GD32_PIN(33, C, 1),
+    __GD32_PIN(34, C, 2),
+    __GD32_PIN(35, C, 3),
+    __GD32_PIN(36, C, 4),
+    __GD32_PIN(37, C, 5),
+    __GD32_PIN(38, C, 6),
+    __GD32_PIN(39, C, 7),
+    __GD32_PIN(40, C, 8),
+    __GD32_PIN(41, C, 9),
+    __GD32_PIN(42, C, 10),
+    __GD32_PIN(43, C, 11),
+    __GD32_PIN(44, C, 12),
+    __GD32_PIN(45, C, 13),
+    __GD32_PIN(46, C, 14),
+    __GD32_PIN(47, C, 15),
+
+    __GD32_PIN(48, D, 0),
+    __GD32_PIN(49, D, 1),
+    __GD32_PIN(50, D, 2),
+    __GD32_PIN(51, D, 3),
+    __GD32_PIN(52, D, 4),
+    __GD32_PIN(53, D, 5),
+    __GD32_PIN(54, D, 6),
+    __GD32_PIN(55, D, 7),
+    __GD32_PIN(56, D, 8),
+    __GD32_PIN(57, D, 9),
+    __GD32_PIN(58, D, 10),
+    __GD32_PIN(59, D, 11),
+    __GD32_PIN(60, D, 12),
+    __GD32_PIN(61, D, 13),
+    __GD32_PIN(62, D, 14),
+    __GD32_PIN(63, D, 15),
+
+    __GD32_PIN(64, E, 0),
+    __GD32_PIN(65, E, 1),
+    __GD32_PIN(66, E, 2),
+    __GD32_PIN(67, E, 3),
+    __GD32_PIN(68, E, 4),
+    __GD32_PIN(69, E, 5),
+    __GD32_PIN(70, E, 6),
+    __GD32_PIN(71, E, 7),
+    __GD32_PIN(72, E, 8),
+    __GD32_PIN(73, E, 9),
+    __GD32_PIN(74, E, 10),
+    __GD32_PIN(75, E, 11),
+    __GD32_PIN(76, E, 12),
+    __GD32_PIN(77, E, 13),
+    __GD32_PIN(78, E, 14),
+    __GD32_PIN(79, E, 15),
+};
+
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {GPIO_PIN_0, EXTI0_IRQn},
+    {GPIO_PIN_1, EXTI1_IRQn},
+    {GPIO_PIN_2, EXTI2_IRQn},
+    {GPIO_PIN_3, EXTI3_IRQn},
+    {GPIO_PIN_4, EXTI4_IRQn},
+    {GPIO_PIN_5, EXTI5_9_IRQn},
+    {GPIO_PIN_6, EXTI5_9_IRQn},
+    {GPIO_PIN_7, EXTI5_9_IRQn},
+    {GPIO_PIN_8, EXTI5_9_IRQn},
+    {GPIO_PIN_9, EXTI5_9_IRQn},
+    {GPIO_PIN_10, EXTI10_15_IRQn},
+    {GPIO_PIN_11, EXTI10_15_IRQn},
+    {GPIO_PIN_12, EXTI10_15_IRQn},
+    {GPIO_PIN_13, EXTI10_15_IRQn},
+    {GPIO_PIN_14, EXTI10_15_IRQn},
+    {GPIO_PIN_15, EXTI10_15_IRQn},
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+static const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    gpio_bit_write(index->gpio, index->pin, (bit_status)value);
+}
+
+static int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    value = gpio_input_bit_get(index->gpio, index->pin);
+
+    return value;
+}
+
+static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    rt_uint32_t pin_mode;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    pin_mode = GPIO_MODE_OUT_PP;
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        /* output setting */
+        pin_mode = GPIO_MODE_OUT_PP;
+        break;
+    case PIN_MODE_OUTPUT_OD:
+        /* output setting: od. */
+        pin_mode = GPIO_MODE_OUT_OD;
+        break;
+    case PIN_MODE_INPUT:
+        /* input setting: not pull. */
+        pin_mode = GPIO_MODE_IN_FLOATING;
+        break;
+    case PIN_MODE_INPUT_PULLUP:
+        /* input setting: pull up. */
+        pin_mode = GPIO_MODE_IPU;
+        break;
+    case PIN_MODE_INPUT_PULLDOWN:
+        /* input setting: pull down. */
+        pin_mode = GPIO_MODE_IPD;
+        break;
+    default:
+        break;
+    }
+
+    gpio_init(index->gpio, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
+}
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+    int i;
+    for (i = 0; i < 32; i++)
+    {
+        if ((0x01 << i) == bit)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
+{
+    rt_int32_t mapindex = bit2bitno(pinbit);
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+
+static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                    rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    exti_trig_type_enum trigger_mode;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        irqindex = bit2bitno(index->pin);
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        irqmap = &pin_irq_map[irqindex];
+
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            trigger_mode = EXTI_TRIG_RISING;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            trigger_mode = EXTI_TRIG_FALLING;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            trigger_mode = EXTI_TRIG_BOTH;
+            break;
+        default:
+            rt_hw_interrupt_enable(level);
+            return RT_EINVAL;
+        }
+        /* connect EXTI line to  GPIO pin */
+        gpio_exti_source_select(index->gpio, index->pin);
+
+        /* configure EXTI line */
+        exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
+        exti_interrupt_flag_clear((exti_line_enum)(index->pin));
+
+        /* enable and set interrupt priority */
+        ECLIC_SetShvIRQ(irqmap->irqno, ECLIC_NON_VECTOR_INTERRUPT);
+        ECLIC_SetLevelIRQ(irqmap->irqno, 1);
+        ECLIC_EnableIRQ(irqmap->irqno);
+        pin_irq_enable_mask |= irqmap->pinbit;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return RT_EINVAL;
+        }
+        if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
+            {
+                ECLIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
+            {
+                ECLIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else
+        {
+            ECLIC_DisableIRQ(irqmap->irqno);
+        }
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+const static struct rt_pin_ops _gd32_pin_ops =
+{
+    gd32_pin_mode,
+    gd32_pin_write,
+    gd32_pin_read,
+    gd32_pin_attach_irq,
+    gd32_pin_dettach_irq,
+    gd32_pin_irq_enable,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
+{
+    if (RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
+    {
+        pin_irq_hdr(exti_line);
+        exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
+    }
+}
+
+void EXTI0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(0);
+    rt_interrupt_leave();
+}
+void EXTI1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(1);
+    rt_interrupt_leave();
+}
+void EXTI2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(2);
+    rt_interrupt_leave();
+}
+void EXTI3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(3);
+    rt_interrupt_leave();
+}
+void EXTI4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(4);
+    rt_interrupt_leave();
+}
+void EXTI5_9_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(5);
+    GD32_GPIO_EXTI_IRQHandler(6);
+    GD32_GPIO_EXTI_IRQHandler(7);
+    GD32_GPIO_EXTI_IRQHandler(8);
+    GD32_GPIO_EXTI_IRQHandler(9);
+    rt_interrupt_leave();
+}
+void EXTI10_15_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(10);
+    GD32_GPIO_EXTI_IRQHandler(11);
+    GD32_GPIO_EXTI_IRQHandler(12);
+    GD32_GPIO_EXTI_IRQHandler(13);
+    GD32_GPIO_EXTI_IRQHandler(14);
+    GD32_GPIO_EXTI_IRQHandler(15);
+    rt_interrupt_leave();
+}
+
+int rt_hw_pin_init(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_GPIOC);
+    rcu_periph_clock_enable(RCU_GPIOD);
+    rcu_periph_clock_enable(RCU_GPIOE);
+    rcu_periph_clock_enable(RCU_AF);
+    return rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+#endif /* RT_USING_PIN */
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h
new file mode 100644
index 0000000000..93d24a8317
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2018-11-06     balanceTWK        first version
+ * 2020-04-15     hqfang            Modify for gd32vf103
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+#define __GD32_PORT(port)  GPIO##port
+
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA)/(0x0400UL) )) + PIN)
+
+#define __GD32_PIN(index, gpio, gpio_index)                                \
+    {                                                                      \
+        index, GPIO##gpio, GPIO_PIN_##gpio_index                           \
+    }
+
+#define __GD32_PIN_RESERVE                                                 \
+    {                                                                      \
+        -1, 0, 0                                                           \
+    }
+
+/* GD32 GPIO driver */
+struct pin_index
+{
+    int index;
+    uint32_t gpio;
+    uint32_t pin;
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+
+int rt_hw_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */
+
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c
new file mode 100644
index 0000000000..00fac33b3e
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-23     tyustli      first version
+ * 2020-04-02     hqfang       modified for Nuclei
+ */
+
+#include <drv_usart.h>
+
+#ifdef RT_USING_SERIAL
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
+    && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4)
+    #error "Please define at least one BSP_USING_UARTx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART0
+    GDUART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    GDUART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    GDUART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    GDUART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+    GDUART4_INDEX,
+#endif
+};
+
+static struct gd32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART0
+    {
+        "uart0",
+        USART0,
+        USART0_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART1
+    {
+        "uart1",
+        USART1,
+        USART1_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART2
+    {
+        "uart2",
+        USART2,
+        USART2_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART3
+    {
+        "uart3",
+        USART3,
+        USART3_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART4
+    {
+        "uart4",
+        UART4,
+        UART4_IRQn,
+    },
+#endif
+};
+
+static struct gd32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+static rt_err_t gd32_configure(struct rt_serial_device *serial,
+                               struct serial_configure *cfg)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    usart_deinit(usart->uart_base);
+    usart_baudrate_set(usart->uart_base, cfg->baud_rate);
+
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        usart_word_length_set(usart->uart_base, USART_WL_8BIT);
+        break;
+
+    case DATA_BITS_9:
+        usart_word_length_set(usart->uart_base, USART_WL_9BIT);
+        break;
+    default:
+        usart_word_length_set(usart->uart_base, USART_WL_8BIT);
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        usart_stop_bit_set(usart->uart_base, USART_STB_1BIT);
+        break;
+    case STOP_BITS_2:
+        usart_stop_bit_set(usart->uart_base, USART_STB_2BIT);
+        break;
+    default:
+        usart_stop_bit_set(usart->uart_base, USART_STB_1BIT);
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        usart_parity_config(usart->uart_base, USART_PM_NONE);
+        break;
+    case PARITY_ODD:
+        usart_parity_config(usart->uart_base, USART_PM_ODD);
+        break;
+    case PARITY_EVEN:
+        usart_parity_config(usart->uart_base, USART_PM_EVEN);
+        break;
+    default:
+        usart_parity_config(usart->uart_base, USART_PM_NONE);
+        break;
+    }
+    usart_hardware_flow_rts_config(usart->uart_base, USART_RTS_DISABLE);
+    usart_hardware_flow_cts_config(usart->uart_base, USART_RTS_DISABLE);
+    usart_receive_config(usart->uart_base, USART_RECEIVE_ENABLE);
+    usart_transmit_config(usart->uart_base, USART_TRANSMIT_ENABLE);
+    usart_enable(usart->uart_base);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd,
+                             void *arg)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        ECLIC_DisableIRQ(usart->irqn);
+        usart_interrupt_disable(usart->uart_base, USART_INT_RBNE);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        ECLIC_EnableIRQ(usart->irqn);
+        /* enable USART0 receive interrupt */
+        usart_interrupt_enable(usart->uart_base, USART_INT_RBNE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int gd32_putc(struct rt_serial_device *serial, char ch)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    usart_data_transmit(usart->uart_base, (uint8_t) ch);
+    while (usart_flag_get(usart->uart_base, USART_FLAG_TBE) == RESET);
+
+    return 1;
+}
+
+static int gd32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    ch = -1;
+    if (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE))
+    {
+        ch = usart_data_receive(usart->uart_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops gd32_uart_ops = { gd32_configure, gd32_control,
+           gd32_putc, gd32_getc,
+           RT_NULL
+};
+
+static void usart_isr(struct rt_serial_device *serial)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    if ((usart_interrupt_flag_get(usart->uart_base, USART_INT_FLAG_RBNE)
+            != RESET)
+            && (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE)))
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        usart_interrupt_flag_clear(usart->uart_base, USART_INT_FLAG_RBNE);
+        usart_flag_clear(usart->uart_base, USART_FLAG_RBNE);
+    }
+    else
+    {
+        if (usart_flag_get(usart->uart_base, USART_FLAG_CTSF) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_CTSF);
+        }
+
+        if (usart_flag_get(usart->uart_base, USART_FLAG_LBDF) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_LBDF);
+        }
+
+        if (usart_flag_get(usart->uart_base, USART_FLAG_TC) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_TC);
+        }
+    }
+}
+
+#ifdef BSP_USING_UART0
+
+void USART0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART0_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART1
+
+void USART1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART1_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART2
+
+void USART2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART2_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART3
+
+void UART3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART3_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART4
+
+void UART4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART4_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+int rt_hw_usart_init(void)
+{
+    rt_size_t obj_num;
+    int index;
+
+    obj_num = sizeof(uart_obj) / sizeof(struct gd32_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (index = 0; index < obj_num; index++)
+    {
+        /* init UART object */
+        uart_obj[index].config = &uart_config[index];
+        uart_obj[index].serial.ops = &gd32_uart_ops;
+        uart_obj[index].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[index].serial,
+                                       uart_obj[index].config->name,
+                                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
+                                       | RT_DEVICE_FLAG_INT_TX, &uart_obj[index]);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+
+#endif /* RT_USING_SERIAL */
+
+/******************** end of file *******************/
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h
new file mode 100644
index 0000000000..176720c4a2
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-15     hqfang       first version
+ */
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_config.h>
+
+/* gd32 config class */
+struct gd32_uart_config
+{
+    const char *name;
+    uint32_t uart_base;
+    IRQn_Type irqn;
+};
+
+/* gd32 uart dirver class */
+struct gd32_uart
+{
+    struct gd32_uart_config *config;
+    struct rt_serial_device serial;
+};
+
+int rt_hw_usart_init(void);
+
+#endif /* __DRV_USART_H__ */
+
+/******************* end of file *******************/
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 640e46a4fb..024cc5ba44 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -10,7 +10,8 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-group = group + SConscript(os.path.join('common', 'SConscript'))
+if rtconfig.CPU != "nuclei":
+    group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
 group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/risc-v/nuclei/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/nuclei/context_gcc.S b/libcpu/risc-v/nuclei/context_gcc.S
new file mode 100644
index 0000000000..fda453940d
--- /dev/null
+++ b/libcpu/risc-v/nuclei/context_gcc.S
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     Huaqi        First Nuclei RISC-V porting implementation
+ */
+
+#include "riscv_encoding.h"
+
+#ifndef __riscv_32e
+#define RT_SAVED_REGNUM         30
+#else
+#define RT_SAVED_REGNUM         14
+#endif
+
+#define RT_CONTEXT_SIZE         (RT_SAVED_REGNUM * REGBYTES)
+
+    .extern rt_interrupt_from_thread
+    .extern rt_interrupt_to_thread
+
+
+.section    .text
+
+
+/*
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * a0 --> to_thread
+ */
+    .globl rt_hw_context_switch_to
+
+/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the stack
+	for lazy saving of FPU registers. */
+.align 3
+rt_hw_context_switch_to:
+    /* Setup Interrupt Stack using
+       The stack that was used by main()
+       before the scheduler is started is
+       no longer required after the scheduler is started.
+       Interrupt stack pointer is stored in CSR_MSCRATCH */
+    la t0, _sp
+    csrw CSR_MSCRATCH, t0
+    LOAD sp, 0x0(a0)                /* Read sp from first TCB member(a0) */
+
+    /* Pop PC from stack and set MEPC */
+    LOAD t0,  0  * REGBYTES(sp)
+    csrw CSR_MEPC, t0
+    /* Pop mstatus from stack and set it */
+    LOAD t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+    csrw CSR_MSTATUS, t0
+    /* Interrupt still disable here */
+    /* Restore Registers from Stack */
+    LOAD x1,  1  * REGBYTES(sp)    /* RA */
+    LOAD x5,  2  * REGBYTES(sp)
+    LOAD x6,  3  * REGBYTES(sp)
+    LOAD x7,  4  * REGBYTES(sp)
+    LOAD x8,  5  * REGBYTES(sp)
+    LOAD x9,  6  * REGBYTES(sp)
+    LOAD x10, 7  * REGBYTES(sp)
+    LOAD x11, 8  * REGBYTES(sp)
+    LOAD x12, 9  * REGBYTES(sp)
+    LOAD x13, 10 * REGBYTES(sp)
+    LOAD x14, 11 * REGBYTES(sp)
+    LOAD x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 13 * REGBYTES(sp)
+    LOAD x17, 14 * REGBYTES(sp)
+    LOAD x18, 15 * REGBYTES(sp)
+    LOAD x19, 16 * REGBYTES(sp)
+    LOAD x20, 17 * REGBYTES(sp)
+    LOAD x21, 18 * REGBYTES(sp)
+    LOAD x22, 19 * REGBYTES(sp)
+    LOAD x23, 20 * REGBYTES(sp)
+    LOAD x24, 21 * REGBYTES(sp)
+    LOAD x25, 22 * REGBYTES(sp)
+    LOAD x26, 23 * REGBYTES(sp)
+    LOAD x27, 24 * REGBYTES(sp)
+    LOAD x28, 25 * REGBYTES(sp)
+    LOAD x29, 26 * REGBYTES(sp)
+    LOAD x30, 27 * REGBYTES(sp)
+    LOAD x31, 28 * REGBYTES(sp)
+#endif
+
+    addi sp, sp, RT_CONTEXT_SIZE
+
+    mret
+
+.align 2
+.global eclic_msip_handler
+eclic_msip_handler:
+    addi sp, sp, -RT_CONTEXT_SIZE
+    STORE x1,  1  * REGBYTES(sp)    /* RA */
+    STORE x5,  2  * REGBYTES(sp)
+    STORE x6,  3  * REGBYTES(sp)
+    STORE x7,  4  * REGBYTES(sp)
+    STORE x8,  5  * REGBYTES(sp)
+    STORE x9,  6  * REGBYTES(sp)
+    STORE x10, 7  * REGBYTES(sp)
+    STORE x11, 8  * REGBYTES(sp)
+    STORE x12, 9  * REGBYTES(sp)
+    STORE x13, 10 * REGBYTES(sp)
+    STORE x14, 11 * REGBYTES(sp)
+    STORE x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    STORE x16, 13 * REGBYTES(sp)
+    STORE x17, 14 * REGBYTES(sp)
+    STORE x18, 15 * REGBYTES(sp)
+    STORE x19, 16 * REGBYTES(sp)
+    STORE x20, 17 * REGBYTES(sp)
+    STORE x21, 18 * REGBYTES(sp)
+    STORE x22, 19 * REGBYTES(sp)
+    STORE x23, 20 * REGBYTES(sp)
+    STORE x24, 21 * REGBYTES(sp)
+    STORE x25, 22 * REGBYTES(sp)
+    STORE x26, 23 * REGBYTES(sp)
+    STORE x27, 24 * REGBYTES(sp)
+    STORE x28, 25 * REGBYTES(sp)
+    STORE x29, 26 * REGBYTES(sp)
+    STORE x30, 27 * REGBYTES(sp)
+    STORE x31, 28 * REGBYTES(sp)
+#endif
+    /* Push mstatus to stack */
+    csrr t0, CSR_MSTATUS
+    STORE t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+
+    /* Push additional registers */
+
+    /* Store sp to task stack */
+    LOAD t0, rt_interrupt_from_thread
+    STORE sp, 0(t0)
+
+    csrr t0, CSR_MEPC
+    STORE t0, 0(sp)
+
+    jal rt_hw_taskswitch
+
+    /* Switch task context */
+    LOAD t0, rt_interrupt_to_thread
+    LOAD sp, 0x0(t0)
+
+    /* Pop PC from stack and set MEPC */
+    LOAD t0,  0  * REGBYTES(sp)
+    csrw CSR_MEPC, t0
+
+    /* Pop additional registers */
+
+    /* Pop mstatus from stack and set it */
+    LOAD t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+    csrw CSR_MSTATUS, t0
+    /* Interrupt still disable here */
+    /* Restore Registers from Stack */
+    LOAD x1,  1  * REGBYTES(sp)    /* RA */
+    LOAD x5,  2  * REGBYTES(sp)
+    LOAD x6,  3  * REGBYTES(sp)
+    LOAD x7,  4  * REGBYTES(sp)
+    LOAD x8,  5  * REGBYTES(sp)
+    LOAD x9,  6  * REGBYTES(sp)
+    LOAD x10, 7  * REGBYTES(sp)
+    LOAD x11, 8  * REGBYTES(sp)
+    LOAD x12, 9  * REGBYTES(sp)
+    LOAD x13, 10 * REGBYTES(sp)
+    LOAD x14, 11 * REGBYTES(sp)
+    LOAD x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 13 * REGBYTES(sp)
+    LOAD x17, 14 * REGBYTES(sp)
+    LOAD x18, 15 * REGBYTES(sp)
+    LOAD x19, 16 * REGBYTES(sp)
+    LOAD x20, 17 * REGBYTES(sp)
+    LOAD x21, 18 * REGBYTES(sp)
+    LOAD x22, 19 * REGBYTES(sp)
+    LOAD x23, 20 * REGBYTES(sp)
+    LOAD x24, 21 * REGBYTES(sp)
+    LOAD x25, 22 * REGBYTES(sp)
+    LOAD x26, 23 * REGBYTES(sp)
+    LOAD x27, 24 * REGBYTES(sp)
+    LOAD x28, 25 * REGBYTES(sp)
+    LOAD x29, 26 * REGBYTES(sp)
+    LOAD x30, 27 * REGBYTES(sp)
+    LOAD x31, 28 * REGBYTES(sp)
+#endif
+
+    addi sp, sp, RT_CONTEXT_SIZE
+    mret
diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c
new file mode 100644
index 0000000000..fad9afdf4c
--- /dev/null
+++ b/libcpu/risc-v/nuclei/cpuport.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     Huaqi        Nuclei RISC-V Core porting code.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "cpuport.h"
+
+#define SYSTICK_TICK_CONST                      (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
+
+/* Interrupt level for kernel systimer interrupt and software timer interrupt */
+#define RT_KERNEL_INTERRUPT_LEVEL               1
+
+/* Initial CSR MSTATUS value when thread created */
+#define RT_INITIAL_MSTATUS                      (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL)
+
+/**
+ * @brief from thread used interrupt context switch
+ * 
+ */
+volatile rt_ubase_t  rt_interrupt_from_thread = 0;
+/**
+ * @brief to thread used interrupt context switch
+ * 
+ */
+volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
+/**
+ * @brief flag to indicate context switch in interrupt or not
+ * 
+ */
+volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
+
+/**
+ * @brief thread stack frame of saved context
+ * 
+ */
+struct rt_hw_stack_frame
+{
+    rt_ubase_t epc;        /*!< epc - epc    - program counter                     */
+    rt_ubase_t ra;         /*!< x1  - ra     - return address for jumps            */
+    rt_ubase_t t0;         /*!< x5  - t0     - temporary register 0                */
+    rt_ubase_t t1;         /*!< x6  - t1     - temporary register 1                */
+    rt_ubase_t t2;         /*!< x7  - t2     - temporary register 2                */
+    rt_ubase_t s0_fp;      /*!< x8  - s0/fp  - saved register 0 or frame pointer   */
+    rt_ubase_t s1;         /*!< x9  - s1     - saved register 1                    */
+    rt_ubase_t a0;         /*!< x10 - a0     - return value or function argument 0 */
+    rt_ubase_t a1;         /*!< x11 - a1     - return value or function argument 1 */
+    rt_ubase_t a2;         /*!< x12 - a2     - function argument 2                 */
+    rt_ubase_t a3;         /*!< x13 - a3     - function argument 3                 */
+    rt_ubase_t a4;         /*!< x14 - a4     - function argument 4                 */
+    rt_ubase_t a5;         /*!< x15 - a5     - function argument 5                 */
+#ifndef __riscv_32e
+    rt_ubase_t a6;         /*!< x16 - a6     - function argument 6                 */
+    rt_ubase_t a7;         /*!< x17 - s7     - function argument 7                 */
+    rt_ubase_t s2;         /*!< x18 - s2     - saved register 2                    */
+    rt_ubase_t s3;         /*!< x19 - s3     - saved register 3                    */
+    rt_ubase_t s4;         /*!< x20 - s4     - saved register 4                    */
+    rt_ubase_t s5;         /*!< x21 - s5     - saved register 5                    */
+    rt_ubase_t s6;         /*!< x22 - s6     - saved register 6                    */
+    rt_ubase_t s7;         /*!< x23 - s7     - saved register 7                    */
+    rt_ubase_t s8;         /*!< x24 - s8     - saved register 8                    */
+    rt_ubase_t s9;         /*!< x25 - s9     - saved register 9                    */
+    rt_ubase_t s10;        /*!< x26 - s10    - saved register 10                   */
+    rt_ubase_t s11;        /*!< x27 - s11    - saved register 11                   */
+    rt_ubase_t t3;         /*!< x28 - t3     - temporary register 3                */
+    rt_ubase_t t4;         /*!< x29 - t4     - temporary register 4                */
+    rt_ubase_t t5;         /*!< x30 - t5     - temporary register 5                */
+    rt_ubase_t t6;         /*!< x31 - t6     - temporary register 6                */
+#endif
+    rt_ubase_t mstatus;    /*!<              - machine status register             */
+};
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct rt_hw_stack_frame *frame;
+    rt_uint8_t         *stk;
+    int                i;
+
+    stk  = stack_addr + sizeof(rt_ubase_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
+    stk -= sizeof(struct rt_hw_stack_frame);
+
+    frame = (struct rt_hw_stack_frame *)stk;
+
+    for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
+    {
+        ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
+    }
+
+    frame->ra      = (rt_ubase_t)texit;
+    frame->a0      = (rt_ubase_t)parameter;
+    frame->epc     = (rt_ubase_t)tentry;
+
+    frame->mstatus = RT_INITIAL_MSTATUS;
+
+    return stk;
+}
+
+/**
+ * @brief Do rt-thread context switch in interrupt context
+ * 
+ * @param from thread sp of from thread
+ * @param to thread sp of to thread
+ */
+void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
+{
+    if (rt_thread_switch_interrupt_flag == 0)
+        rt_interrupt_from_thread = from;
+
+    rt_interrupt_to_thread = to;
+    rt_thread_switch_interrupt_flag = 1;
+    RT_YIELD();
+}
+
+/**
+ * @brief Do rt-thread context switch in task context
+ * 
+ * @param from thread sp of from thread
+ * @param to thread sp of to thread
+ */
+void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
+{
+    rt_interrupt_from_thread = from;
+    rt_interrupt_to_thread = to;
+    RT_YIELD();
+}
+
+/**
+ * @brief shutdown CPU
+ * 
+ */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/**
+ * @brief Do extra task switch code
+ * 
+ * @details
+ * 
+ * - Clear software timer interrupt request flag
+ * - clear rt_thread_switch_interrupt_flag to 0
+ */
+void rt_hw_taskswitch(void)
+{
+    /* Clear Software IRQ, A MUST */
+    SysTimer_ClearSWIRQ();
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * @brief Setup systimer and software timer interrupt
+ * 
+ * @details 
+ * 
+ * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level
+ * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level
+ * - Enable these two interrupts
+ */
+void rt_hw_ticksetup(void)
+{
+    uint64_t ticks = SYSTICK_TICK_CONST;
+
+    /* Make SWI and SysTick the lowest priority interrupts. */
+    /* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
+    SysTick_Config(ticks);
+    ECLIC_DisableIRQ(SysTimer_IRQn);
+    ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
+    ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
+    ECLIC_EnableIRQ(SysTimer_IRQn);
+
+    /* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
+    ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
+    ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
+    ECLIC_EnableIRQ(SysTimerSW_IRQn);
+}
+
+/**
+ * systimer interrupt handler eclic_mtip_handler
+ * is hard coded in startup_<Device>.S
+ * We define SysTick_Handler as eclic_mtip_handler
+ * for easy understanding
+ */
+#define SysTick_Handler     eclic_mtip_handler
+
+/**
+ * @brief This is the timer interrupt service routine.
+ * 
+ */
+void SysTick_Handler(void)
+{
+    /* Reload systimer */
+    SysTick_Reload(SYSTICK_TICK_CONST);
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* tick increase */
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief Disable cpu interrupt
+ * 
+ * @details
+ * 
+ * - Disable cpu interrupt by clear MIE bit in MSTATUS
+ * - Return the previous value in MSTATUS before clear MIE bit
+ * 
+ * @return the previous value in MSTATUS before clear MIE bit 
+ */
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
+}
+
+/**
+ * @brief Restore previous saved interrupt status
+ * 
+ * @param level previous saved MSTATUS value
+ */
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    __RV_CSR_WRITE(CSR_MSTATUS, level);
+}
diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h
new file mode 100644
index 0000000000..3736f0078a
--- /dev/null
+++ b/libcpu/risc-v/nuclei/cpuport.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     hqfang       Nuclei RISC-V Core porting code.
+ */
+
+#ifndef __CPUPORT_H__
+#define __CPUPORT_H__
+
+#include <rtconfig.h>
+#include <nuclei_sdk_soc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Scheduler utilities. */
+#define RT_YIELD()                                                              \
+{                                                                               \
+    /* Set a software interrupt(SWI) request to request a context switch. */    \
+    SysTimer_SetSWIRQ();                                                        \
+    /* Barriers are normally not required but do ensure the code is completely  \
+    within the specified behaviour for the architecture. */                     \
+    __RWMB();                                                                   \
+    __FENCE_I();                                                                \
+}
+
+extern void rt_hw_ticksetup(void);
+extern void rt_hw_taskswitch(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libcpu/risc-v/nuclei/interrupt_gcc.S b/libcpu/risc-v/nuclei/interrupt_gcc.S
new file mode 100644
index 0000000000..02a3e3e760
--- /dev/null
+++ b/libcpu/risc-v/nuclei/interrupt_gcc.S
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     hqfang       First Nuclei RISC-V porting implementation
+ */
+
+#include "riscv_encoding.h"
+
+.section    .text.entry
+.align 8
+
+/**
+ * \brief  Global interrupt disabled
+ * \details
+ *  This function disable global interrupt.
+ * \remarks
+ *  - All the interrupt requests will be ignored by CPU.
+ */
+.macro DISABLE_MIE
+    csrc CSR_MSTATUS, MSTATUS_MIE
+.endm
+
+/**
+ * \brief  Macro for context save
+ * \details
+ * This macro save ABI defined caller saved registers in the stack.
+ * \remarks
+ * - This Macro could use to save context when you enter to interrupt
+ * or exception
+*/
+/* Save caller registers */
+.macro SAVE_CONTEXT
+    csrrw sp, CSR_MSCRATCHCSWL, sp
+    /* Allocate stack space for context saving */
+#ifndef __riscv_32e
+    addi sp, sp, -20*REGBYTES
+#else
+    addi sp, sp, -14*REGBYTES
+#endif /* __riscv_32e */
+
+    STORE x1, 0*REGBYTES(sp)
+    STORE x4, 1*REGBYTES(sp)
+    STORE x5, 2*REGBYTES(sp)
+    STORE x6, 3*REGBYTES(sp)
+    STORE x7, 4*REGBYTES(sp)
+    STORE x10, 5*REGBYTES(sp)
+    STORE x11, 6*REGBYTES(sp)
+    STORE x12, 7*REGBYTES(sp)
+    STORE x13, 8*REGBYTES(sp)
+    STORE x14, 9*REGBYTES(sp)
+    STORE x15, 10*REGBYTES(sp)
+#ifndef __riscv_32e
+    STORE x16, 14*REGBYTES(sp)
+    STORE x17, 15*REGBYTES(sp)
+    STORE x28, 16*REGBYTES(sp)
+    STORE x29, 17*REGBYTES(sp)
+    STORE x30, 18*REGBYTES(sp)
+    STORE x31, 19*REGBYTES(sp)
+#endif /* __riscv_32e */
+.endm
+
+/**
+ * \brief  Macro for restore caller registers
+ * \details
+ * This macro restore ABI defined caller saved registers from stack.
+ * \remarks
+ * - You could use this macro to restore context before you want return
+ * from interrupt or exeception
+ */
+/* Restore caller registers */
+.macro RESTORE_CONTEXT
+    LOAD x1, 0*REGBYTES(sp)
+    LOAD x4, 1*REGBYTES(sp)
+    LOAD x5, 2*REGBYTES(sp)
+    LOAD x6, 3*REGBYTES(sp)
+    LOAD x7, 4*REGBYTES(sp)
+    LOAD x10, 5*REGBYTES(sp)
+    LOAD x11, 6*REGBYTES(sp)
+    LOAD x12, 7*REGBYTES(sp)
+    LOAD x13, 8*REGBYTES(sp)
+    LOAD x14, 9*REGBYTES(sp)
+    LOAD x15, 10*REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 14*REGBYTES(sp)
+    LOAD x17, 15*REGBYTES(sp)
+    LOAD x28, 16*REGBYTES(sp)
+    LOAD x29, 17*REGBYTES(sp)
+    LOAD x30, 18*REGBYTES(sp)
+    LOAD x31, 19*REGBYTES(sp)
+
+    /* De-allocate the stack space */
+    addi sp, sp, 20*REGBYTES
+#else
+    /* De-allocate the stack space */
+    addi sp, sp, 14*REGBYTES
+#endif /* __riscv_32e */
+    csrrw sp, CSR_MSCRATCHCSWL, sp
+.endm
+
+/**
+ * \brief  Macro for save necessary CSRs to stack
+ * \details
+ * This macro store MCAUSE, MEPC, MSUBM to stack.
+ */
+.macro SAVE_CSR_CONTEXT
+    /* Store CSR mcause to stack using pushmcause */
+    csrrwi  x0, CSR_PUSHMCAUSE, 11
+    /* Store CSR mepc to stack using pushmepc */
+    csrrwi  x0, CSR_PUSHMEPC, 12
+    /* Store CSR msub to stack using pushmsub */
+    csrrwi  x0, CSR_PUSHMSUBM, 13
+.endm
+
+/**
+ * \brief  Macro for restore necessary CSRs from stack
+ * \details
+ * This macro restore MSUBM, MEPC, MCAUSE from stack.
+ */
+.macro RESTORE_CSR_CONTEXT
+    LOAD x5,  13*REGBYTES(sp)
+    csrw CSR_MSUBM, x5
+    LOAD x5,  12*REGBYTES(sp)
+    csrw CSR_MEPC, x5
+    LOAD x5,  11*REGBYTES(sp)
+    csrw CSR_MCAUSE, x5
+.endm
+
+/**
+ * \brief  Exception/NMI Entry
+ * \details
+ * This function provide common entry functions for exception/nmi.
+ * \remarks
+ * This function provide a default exception/nmi entry.
+ * ABI defined caller save register and some CSR registers
+ * to be saved before enter interrupt handler and be restored before return.
+ */
+.section .text.trap
+/* In CLIC mode, the exeception entry must be 64bytes aligned */
+.align 6
+.global exc_entry
+exc_entry:
+    /* Save the caller saving registers (context) */
+    SAVE_CONTEXT
+    /* Save the necessary CSR registers */
+    SAVE_CSR_CONTEXT
+
+    /*
+     * Set the exception handler function arguments
+     * argument 1: mcause value
+     * argument 2: current stack point(SP) value
+     */
+    csrr a0, mcause
+    mv a1, sp
+    /*
+     * TODO: Call the exception handler function
+     * By default, the function template is provided in
+     * system_Device.c, you can adjust it as you want
+     */
+    call core_exception_handler
+
+    /* Restore the necessary CSR registers */
+    RESTORE_CSR_CONTEXT
+    /* Restore the caller saving registers (context) */
+    RESTORE_CONTEXT
+
+    /* Return to regular code */
+    mret
+
+/**
+ * \brief  Non-Vector Interrupt Entry
+ * \details
+ * This function provide common entry functions for handling
+ * non-vector interrupts
+ * \remarks
+ * This function provide a default non-vector interrupt entry.
+ * ABI defined caller save register and some CSR registers need
+ * to be saved before enter interrupt handler and be restored before return.
+ */
+.section      .text.irq
+/* In CLIC mode, the interrupt entry must be 4bytes aligned */
+.align 2
+.global irq_entry
+/* This label will be set to MTVT2 register */
+irq_entry:
+    /* Save the caller saving registers (context) */
+    SAVE_CONTEXT
+    /* Save the necessary CSR registers */
+    SAVE_CSR_CONTEXT
+
+    /* This special CSR read/write operation, which is actually
+     * claim the CLIC to find its pending highest ID, if the ID
+     * is not 0, then automatically enable the mstatus.MIE, and
+     * jump to its vector-entry-label, and update the link register
+     */
+    csrrw ra, CSR_JALMNXTI, ra
+
+    /* Critical section with interrupts disabled */
+    DISABLE_MIE
+
+    /* Restore the necessary CSR registers */
+    RESTORE_CSR_CONTEXT
+    /* Restore the caller saving registers (context) */
+    RESTORE_CONTEXT
+
+    /* Return to regular code */
+    mret
+
+/* Default Handler for Exceptions / Interrupts */
+.global default_intexc_handler
+Undef_Handler:
+default_intexc_handler:
+1:
+	j 1b
+
diff --git a/tools/mkdist.py b/tools/mkdist.py
index 7e4b9a8bbe..ec527d87e1 100644
--- a/tools/mkdist.py
+++ b/tools/mkdist.py
@@ -345,6 +345,13 @@ def MkDist(program, BSP_ROOT, RTT_ROOT, Env, rttide = None):
         bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type']))
         shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))
 
+    # copy nuclei bsp libiary files
+    if os.path.basename(os.path.dirname(BSP_ROOT)) == 'nuclei':
+        print("=> copy nuclei bsp library")
+        library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries')
+        library_dir  = os.path.join(dist_dir, 'libraries')
+        bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type']))
+
     # do bsp special dist handle
     if 'dist_handle' in Env:
         print("=> start dist handle")
-- 
cgit v1.3.1


From 38f400d50ad315ee5cadb00a680f944818812314 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Mon, 25 May 2020 17:30:05 +0800
Subject: add raspi4 32bit mode bsp

---
 bsp/raspberry-pi/raspi4-32/.config                 | 453 +++++++++++++++++++++
 bsp/raspberry-pi/raspi4-32/Kconfig                 |  28 ++
 bsp/raspberry-pi/raspi4-32/README.md               |  79 ++++
 bsp/raspberry-pi/raspi4-32/SConscript              |  14 +
 bsp/raspberry-pi/raspi4-32/SConstruct              |  30 ++
 bsp/raspberry-pi/raspi4-32/applications/SConscript |   9 +
 bsp/raspberry-pi/raspi4-32/applications/main.c     |  19 +
 bsp/raspberry-pi/raspi4-32/driver/Kconfig          |  97 +++++
 bsp/raspberry-pi/raspi4-32/driver/SConscript       |   9 +
 bsp/raspberry-pi/raspi4-32/driver/board.c          |  85 ++++
 bsp/raspberry-pi/raspi4-32/driver/board.h          |  25 ++
 bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c       | 117 ++++++
 bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h       |  77 ++++
 bsp/raspberry-pi/raspi4-32/driver/drv_uart.c       | 152 +++++++
 bsp/raspberry-pi/raspi4-32/driver/drv_uart.h       |  83 ++++
 bsp/raspberry-pi/raspi4-32/driver/raspi4.h         |  73 ++++
 bsp/raspberry-pi/raspi4-32/link.lds                | 153 +++++++
 bsp/raspberry-pi/raspi4-32/rtconfig.h              | 173 ++++++++
 bsp/raspberry-pi/raspi4-32/rtconfig.py             |  54 +++
 libcpu/arm/cortex-a/start_gcc.S                    |  20 +
 20 files changed, 1750 insertions(+)
 create mode 100644 bsp/raspberry-pi/raspi4-32/.config
 create mode 100644 bsp/raspberry-pi/raspi4-32/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi4-32/README.md
 create mode 100644 bsp/raspberry-pi/raspi4-32/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4-32/SConstruct
 create mode 100644 bsp/raspberry-pi/raspi4-32/applications/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4-32/applications/main.c
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/board.c
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/board.h
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/drv_uart.c
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/drv_uart.h
 create mode 100644 bsp/raspberry-pi/raspi4-32/driver/raspi4.h
 create mode 100644 bsp/raspberry-pi/raspi4-32/link.lds
 create mode 100644 bsp/raspberry-pi/raspi4-32/rtconfig.h
 create mode 100644 bsp/raspberry-pi/raspi4-32/rtconfig.py

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config
new file mode 100644
index 0000000000..9194a7dc7f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/.config
@@ -0,0 +1,453 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARMV8=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_BCM2711_SOC=y
+# CONFIG_BSP_SUPPORT_FPU is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# BCM Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART0=y
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GIC400=y
+# CONFIG_BSP_USING_GIC500 is not set
+CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_CORETIMER=y
+# CONFIG_BSP_USING_SYSTIMER is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SDIO is not set
+
+#
+# Board Peripheral Drivers
+#
+# CONFIG_BSP_USING_HDMI is not set
diff --git a/bsp/raspberry-pi/raspi4-32/Kconfig b/bsp/raspberry-pi/raspi4-32/Kconfig
new file mode 100644
index 0000000000..1e49c47680
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/Kconfig
@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2711_SOC
+    bool
+    select ARCH_ARMV8
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "driver/Kconfig"
diff --git a/bsp/raspberry-pi/raspi4-32/README.md b/bsp/raspberry-pi/raspi4-32/README.md
new file mode 100644
index 0000000000..52baca8047
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/README.md
@@ -0,0 +1,79 @@
+# Raspberry PI 4板级支持包说明
+
+## 1. 简介
+
+树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
+
+外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
+
+这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+
+## 2. 编译说明
+
+推荐使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到`bsp\raspberry-pi\raspi4-32`目录中，运行以下命令：
+
+```
+scons
+```
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、kernel7.img文件。
+
+
+## 3. 执行
+
+### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡
+
+首先下载镜像
+
+* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb)
+* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe)
+* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg)
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
+
+![raspi2](../raspi3-32/figures/raspberrypi-console.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+### 3.3 程序下载
+
+当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下：
+
+```
+enable_uart=1
+arm_64bit=0
+kernel_addr=0x8000
+kernel=kernel7.img
+```
+
+按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
+
+```text
+heap: 0x00044270 - 0x04044270
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build May 25 2020
+ 2006 - 2020 Copyright by rt-thread team
+Hi, this is RT-Thread!!
+msh />
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+[1]: https://www.rt-thread.org/page/download.html
+[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
+[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+[4]: https://etcher.io
+[5]: https://github.com/BernardXiong
diff --git a/bsp/raspberry-pi/raspi4-32/SConscript b/bsp/raspberry-pi/raspi4-32/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/raspberry-pi/raspi4-32/SConstruct b/bsp/raspberry-pi/raspi4-32/SConstruct
new file mode 100644
index 0000000000..93f349aab8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/SConstruct
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)
+
diff --git a/bsp/raspberry-pi/raspi4-32/applications/SConscript b/bsp/raspberry-pi/raspi4-32/applications/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi4-32/applications/main.c b/bsp/raspberry-pi/raspi4-32/applications/main.c
new file mode 100644
index 0000000000..9664e67d01
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hi, this is RT-Thread!!\n");
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi4-32/driver/Kconfig b/bsp/raspberry-pi/raspi4-32/driver/Kconfig
new file mode 100644
index 0000000000..208b4b4300
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/Kconfig
@@ -0,0 +1,97 @@
+
+config BSP_SUPPORT_FPU
+    bool "Using Float"
+    default n
+
+menu "Hardware Drivers Config"
+    menu "BCM Peripheral Drivers"
+        menuconfig BSP_USING_UART
+            bool "Using UART"
+            select RT_USING_SERIAL
+            default y
+
+            if BSP_USING_UART
+                config RT_USING_UART0
+                bool "Enabel UART 0"
+                default y
+            endif
+            
+        menuconfig BSP_USING_GIC
+            bool "Enable GIC"
+            select RT_USING_GIC
+            default y
+        if BSP_USING_GIC
+            config BSP_USING_GIC400
+                bool "Enable GIC400"
+                default y
+            config BSP_USING_GIC500
+                bool "Enable GIC500"
+                default n
+        endif
+
+        config BSP_USING_PIN
+            bool "Using PIN"
+            select RT_USING_PIN
+            default y
+
+        config BSP_USING_CORETIMER
+            bool "Using core timer"
+            select RT_USING_CORETIMER
+            default y
+
+        menuconfig BSP_USING_SYSTIMER
+            bool "Enable SYSTIMER"
+            select BSP_USING_SYSTIMER
+            default n
+
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
+        endif
+
+        config BSP_USING_WDT
+            bool "Enable WDT"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+
+        if BSP_USING_RTC
+            config BSP_USING_ALARM
+                bool "Enable Alarm"
+                select RT_USING_ALARM
+                default n
+        endif
+        
+        menuconfig BSP_USING_SDIO
+            bool "Enable SDIO"
+            select RT_USING_SDIO
+            default n
+
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO0
+                bool "Enable SDIO0"
+                select RT_USING_SDIO
+                default n
+        endif
+    endmenu
+
+    menu "Board Peripheral Drivers"
+        menuconfig BSP_USING_HDMI
+            bool "Enable HDMI"
+            default n
+
+        if BSP_USING_HDMI
+            config BSP_USING_HDMI_DISPLAY
+                bool "HDMI DISPLAY"
+                default n
+        endif
+    endmenu
+endmenu
diff --git a/bsp/raspberry-pi/raspi4-32/driver/SConscript b/bsp/raspberry-pi/raspi4-32/driver/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.c b/bsp/raspberry-pi/raspi4-32/driver/board.c
new file mode 100644
index 0000000000..7a3524126d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/board.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include "cp15.h"
+#include "mmu.h"
+
+struct mem_desc platform_mem_desc[] = {
+    {0x0, 0x6400000, 0x0, NORMAL_MEM},
+    {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM},//uart gpio
+    {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic
+};
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    ARM_TIMER_IRQCLR = 0;
+    rt_tick_increase();
+}
+
+void rt_hw_timer_init(void)
+{
+    rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(ARM_TIMER_IRQ);
+    /* timer_clock = apb_clock/(pre_divider + 1) */
+    ARM_TIMER_PREDIV = (250 - 1);
+
+    ARM_TIMER_RELOAD = 0;
+    ARM_TIMER_LOAD   = 0;
+    ARM_TIMER_IRQCLR = 0;
+    ARM_TIMER_CTRL   = 0;
+
+    ARM_TIMER_RELOAD = 10000;
+    ARM_TIMER_LOAD   = 10000;
+
+    /* 23-bit counter, enable interrupt, enable timer */
+    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
+}
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+/**
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  after interrupt disabled.
+ */
+void rt_hw_board_init(void)
+{
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
+    /* initialize uart */
+    rt_hw_uart_init();      // driver/drv_uart.c
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+        /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.h b/bsp/raspberry-pi/raspi4-32/driver/board.h
new file mode 100644
index 0000000000..d675cc658e
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/board.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+#include "raspi4.h"
+
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c
new file mode 100644
index 0000000000..4317a358e0
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_PIN
+
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+{
+    uint32_t fselnum = pin / 10;
+    uint32_t fselrest = pin % 10;
+
+    uint32_t gpfsel = 0;
+    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
+    gpfsel |= (uint32_t)(mode << (fselrest * 3));
+
+    switch (fselnum)
+    {
+    case 0:
+        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
+        break;
+    case 1:
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+        break;
+    case 2:
+        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
+        break;
+    case 3:
+        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
+        break;
+    case 4:
+        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
+        break;
+    case 5:
+        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
+        break;
+    default:
+        break;
+    }
+}
+
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+{
+    uint32_t num = pin / 32;
+
+    if(num == 0)
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
+        }
+    }
+    else
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        
+    }
+}
+
+static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+{
+    return 0;
+}
+
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    return RT_EOK;
+}
+
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    return RT_EOK;
+}
+
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    return RT_EOK;
+}
+
+static const struct rt_pin_ops ops =
+{
+    raspi_pin_mode,
+    raspi_pin_write,
+    raspi_pin_read,
+    raspi_pin_attach_irq,
+    raspi_pin_detach_irq,
+    raspi_pin_irq_enable,
+};
+#endif
+
+int rt_hw_gpio_init(void)
+{
+#ifdef BSP_USING_PIN
+    rt_device_pin_register("gpio", &ops, RT_NULL);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gpio_init);
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h
new file mode 100644
index 0000000000..c4658fcebb
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "interrupt.h"
+
+#define GPIO_REG_GPFSEL0(BASE)             HWREG32(BASE + 0x00)
+#define GPIO_REG_GPFSEL1(BASE)             HWREG32(BASE + 0x04)
+#define GPIO_REG_GPFSEL2(BASE)             HWREG32(BASE + 0x08)
+#define GPIO_REG_GPFSEL3(BASE)             HWREG32(BASE + 0x0C)
+#define GPIO_REG_GPFSEL4(BASE)             HWREG32(BASE + 0x10)
+#define GPIO_REG_GPFSEL5(BASE)             HWREG32(BASE + 0x14)
+#define GPIO_REG_REV0(BASE)                HWREG32(BASE + 0x18)
+#define GPIO_REG_GPSET0(BASE)              HWREG32(BASE + 0x1C)
+#define GPIO_REG_GPSET1(BASE)              HWREG32(BASE + 0x20)
+#define GPIO_REG_REV1(BASE)                HWREG32(BASE + 0x24)
+#define GPIO_REG_GPCLR0(BASE)              HWREG32(BASE + 0x28)
+#define GPIO_REG_GPCLR1(BASE)              HWREG32(BASE + 0x2C)
+#define GPIO_REG_REV2(BASE)                HWREG32(BASE + 0x30)
+#define GPIO_REG_GPLEV0(BASE)              HWREG32(BASE + 0x34)
+#define GPIO_REG_GPLEV1(BASE)              HWREG32(BASE + 0x38)
+#define GPIO_REG_REV3(BASE)                HWREG32(BASE + 0x3C)
+#define GPIO_REG_GPEDS0(BASE)              HWREG32(BASE + 0x40)
+#define GPIO_REG_GPEDS1(BASE)              HWREG32(BASE + 0x44)
+#define GPIO_REG_REV4(BASE)                HWREG32(BASE + 0x48)
+#define GPIO_REG_GPREN0(BASE)              HWREG32(BASE + 0x4C)
+#define GPIO_REG_GPREN1(BASE)              HWREG32(BASE + 0x50)
+#define GPIO_REG_REV5(BASE)                HWREG32(BASE + 0x54)
+#define GPIO_REG_GPFEN0(BASE)              HWREG32(BASE + 0x58)
+#define GPIO_REG_GPFEN1(BASE)              HWREG32(BASE + 0x5C)
+#define GPIO_REG_REV6(BASE)                HWREG32(BASE + 0x60)
+#define GPIO_REG_GPHEN0(BASE)              HWREG32(BASE + 0x64)
+#define GPIO_REG_GPHEN1(BASE)              HWREG32(BASE + 0x68)
+#define GPIO_REG_REV7(BASE)                HWREG32(BASE + 0x6C)
+#define GPIO_REG_GPLEN0(BASE)              HWREG32(BASE + 0x70)
+#define GPIO_REG_GPLEN1(BASE)              HWREG32(BASE + 0x74)
+#define GPIO_REG_REV8(BASE)                HWREG32(BASE + 0x78)
+#define GPIO_REG_GPAREN0(BASE)             HWREG32(BASE + 0x7C)
+#define GPIO_REG_GPAREN1(BASE)             HWREG32(BASE + 0x80)
+#define GPIO_REG_REV11(BASE)               HWREG32(BASE + 0x84)
+#define GPIO_REG_GPAFEN0(BASE)             HWREG32(BASE + 0x88)
+#define GPIO_REG_GPAFEN1(BASE)             HWREG32(BASE + 0x8C)
+#define GPIO_REG_REV10(BASE)               HWREG32(BASE + 0x90)
+#define GPIO_REG_GPPUD(BASE)               HWREG32(BASE + 0x94)
+#define GPIO_REG_GPPUDCLK0(BASE)           HWREG32(BASE + 0x98)
+#define GPIO_REG_GPPUDCLK1(BASE)           HWREG32(BASE + 0x9C)
+#define GPIO_REG_REV9(BASE)                HWREG32(BASE + 0xA0)
+#define GPIO_REG_TEST(BASE)                HWREG32(BASE + 0xA4)
+
+typedef enum {
+    INPUT = 0b000,
+    OUTPUT = 0b001,
+    ALT0 = 0b100,
+    ALT1 = 0b101,
+    ALT2 = 0b110,
+    ALT3 = 0b111,
+    ALT4 = 0b011,
+    ALT5 = 0b010
+} GPIO_FUNC;
+
+
+int rt_hw_gpio_init(void);
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c
new file mode 100644
index 0000000000..6a70cdfb3a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+
+struct hw_uart_device
+{
+    rt_ubase_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+    uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16;
+    uint32_t ibrd = bauddiv / 1000;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+    if(uart->hw_base == PL011_BASE)
+    {
+        uint32_t gpfsel = 0;
+
+        gpfsel &= ~((uint32_t)(0x07 << (4 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (4 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        gpfsel &= ~((uint32_t)(0x07 << (5 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (5 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
+        PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
+        PL011_REG_IBRD(uart->hw_base) = ibrd;
+        PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
+        PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
+        PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM);
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
+    PL011_REG_DR(uart->hw_base) = (uint8_t)c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
+    {
+        ch = PL011_REG_DR(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
+}
+
+
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    PL011_BASE,
+    IRQ_PL011,
+};
+
+static struct rt_serial_device _serial0;
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart");
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h
new file mode 100644
index 0000000000..714043efd3
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+// register's bit
+#define PL011_FR_RI          (1 << 8)
+#define PL011_FR_TXFE        (1 << 7)
+#define PL011_FR_RXFF        (1 << 6)
+#define PL011_FR_TXFF        (1 << 5)
+#define PL011_FR_RXFE        (1 << 4)
+#define PL011_FR_BUSY        (1 << 3)
+#define PL011_FR_DCD         (1 << 2)
+#define PL011_FR_DSR         (1 << 1)
+#define PL011_FR_CTS         (1 << 0)
+
+#define PL011_LCRH_SPS       (1 << 7)
+#define PL011_LCRH_WLEN_8    (3 << 5)
+#define PL011_LCRH_WLEN_7    (2 << 5)
+#define PL011_LCRH_WLEN_6    (1 << 5)
+#define PL011_LCRH_WLEN_5    (0 << 5)
+#define PL011_LCRH_FEN       (1 << 4)
+#define PL011_LCRH_STP2      (1 << 3)
+#define PL011_LCRH_EPS       (1 << 2)
+#define PL011_LCRH_PEN       (1 << 1)
+#define PL011_LCRH_BRK       (1 << 0)
+
+#define PL011_CR_CTSEN       (1 << 15)
+#define PL011_CR_RTSEN       (1 << 14)
+#define PL011_CR_RTS         (1 << 11)
+#define PL011_CR_DTR         (1 << 10)
+#define PL011_CR_RXE         (1 << 9)
+#define PL011_CR_TXE         (1 << 8)
+#define PL011_CR_LBE         (1 << 7)
+#define PL011_CR_SIRLP       (1 << 2)
+#define PL011_CR_SIREN       (1 << 1)
+#define PL011_CR_UARTEN      (1 << 0)
+
+#define PL011_IMSC_TXIM      (1 << 5)
+#define PL011_IMSC_RXIM      (1 << 4)
+
+#define PL011_INTERRUPT_OVERRUN_ERROR   (1 << 10)
+#define PL011_INTERRUPT_BREAK_ERROR     (1 << 9)
+#define PL011_INTERRUPT_PARITY_ERROR    (1 << 8)
+#define PL011_INTERRUPT_FRAMING_ERROR   (1 << 7)
+#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
+#define PL011_INTERRUPT_TRANSMIT        (1 << 5)
+#define PL011_INTERRUPT_RECEIVE         (1 << 4)
+#define PL011_INTERRUPT_nUARTCTS        (1 << 1)
+
+#define PL011_REG_DR(BASE)              HWREG32(BASE + 0x00)
+#define PL011_REG_RSRECR(BASE)          HWREG32(BASE + 0x04)
+#define PL011_REG_RESERVED0(BASE)       HWREG32(BASE + 0x08)
+#define PL011_REG_FR(BASE)              HWREG32(BASE + 0x18)
+#define PL011_REG_RESERVED1(BASE)       HWREG32(BASE + 0x1C)
+#define PL011_REG_ILPR(BASE)            HWREG32(BASE + 0x20)
+#define PL011_REG_IBRD(BASE)            HWREG32(BASE + 0x24)
+#define PL011_REG_FBRD(BASE)            HWREG32(BASE + 0x28)
+#define PL011_REG_LCRH(BASE)            HWREG32(BASE + 0x2C)
+#define PL011_REG_CR(BASE)              HWREG32(BASE + 0x30)
+#define PL011_REG_IFLS(BASE)            HWREG32(BASE + 0x34)
+#define PL011_REG_IMSC(BASE)            HWREG32(BASE + 0x38)
+#define PL011_REG_RIS(BASE)             HWREG32(BASE + 0x3C)
+#define PL011_REG_MIS(BASE)             HWREG32(BASE + 0x40)
+#define PL011_REG_ICR(BASE)             HWREG32(BASE + 0x44)
+#define PL011_REG_DMACR(BASE)           HWREG32(BASE + 0x48)
+#define PL011_REG_RESERVED2(BASE)       HWREG32(BASE + 0x4C)
+#define PL011_REG_ITCR(BASE)            HWREG32(BASE + 0x80)
+#define PL011_REG_ITIP(BASE)            HWREG32(BASE + 0x84)
+#define PL011_REG_ITOP(BASE)            HWREG32(BASE + 0x88)
+#define PL011_REG_TDR(BASE)             HWREG32(BASE + 0x8C)
+
+int rt_hw_uart_init(void);
+
+#endif /* DRV_UART_H__ */
diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h
new file mode 100644
index 0000000000..9106643e3d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h
@@ -0,0 +1,73 @@
+#ifndef __RASPI4_H__
+#define __RASPI4_H__
+//https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0.pdf
+
+#define __REG32(x)  (*((volatile unsigned int *)(x)))
+#define __REG16(x)  (*((volatile unsigned short *)(x)))
+
+/* GIC IRQ MAX */
+#define MAX_HANDLERS                (256)
+
+/* base address */
+#define PER_BASE                    (0xFE000000)
+
+/* GPIO */
+#define GPIO_BASE                   (PER_BASE + 0x00200000)
+
+/* Timer (ARM side) */
+#define ARM_TIMER_IRQ       (64)
+#define ARM_TIMER_BASE      (PER_BASE + 0xB000)
+#define ARM_TIMER_LOAD      HWREG32(ARM_TIMER_BASE + 0x400)
+#define ARM_TIMER_VALUE     HWREG32(ARM_TIMER_BASE + 0x404)
+#define ARM_TIMER_CTRL      HWREG32(ARM_TIMER_BASE + 0x408)
+#define ARM_TIMER_IRQCLR    HWREG32(ARM_TIMER_BASE + 0x40C)
+#define ARM_TIMER_RAWIRQ    HWREG32(ARM_TIMER_BASE + 0x410)
+#define ARM_TIMER_MASKIRQ   HWREG32(ARM_TIMER_BASE + 0x414)
+#define ARM_TIMER_RELOAD    HWREG32(ARM_TIMER_BASE + 0x418)
+#define ARM_TIMER_PREDIV    HWREG32(ARM_TIMER_BASE + 0x41C)
+#define ARM_TIMER_CNTR      HWREG32(ARM_TIMER_BASE + 0x420)
+
+/* UART PL011 */
+#define UART0_BASE                  (PER_BASE + 0x00201000)
+#define PL011_BASE                  UART0_BASE
+#define IRQ_PL011                   (96 + 57)
+#define UART_REFERENCE_CLOCK        (48000000)
+
+// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
+#define CORE0_TIMER_IRQ_CTRL        HWREG32(0xFF800040)
+#define TIMER_IRQ                   30
+#define NON_SECURE_TIMER_IRQ        (1 << 1)
+
+/* GIC */
+#define INTC_BASE                   (0xff800000)
+#define ARM_GIC_NR_IRQS             (512)
+#define ARM_GIC_MAX_NR              (512)
+#define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
+#define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
+#define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
+#define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
+
+#define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
+#define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
+
+#define GIC_IRQ_START   0
+
+#define GIC_ACK_INTID_MASK  0x000003ff
+
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    return GIC_PL400_DISTRIBUTOR_PPTR;
+}
+
+rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
+{
+    return GIC_PL400_CONTROLLER_PPTR;
+}
+
+static inline  void __DSB(void)
+{
+    __asm__ volatile ("dsb 0xF":::"memory");
+}
+
+#endif
diff --git a/bsp/raspberry-pi/raspi4-32/link.lds b/bsp/raspberry-pi/raspi4-32/link.lds
new file mode 100644
index 0000000000..3f2f8ca413
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/link.lds
@@ -0,0 +1,153 @@
+/*
+ * File      : link.lds
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
+
+SECTIONS
+{
+    . = 0x8000;
+    . = ALIGN(4096);
+    .text :
+    {
+        KEEP(*(.text.entrypoint))       /* The entry point */
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        *(COMMON)
+        
+        /* section information for finsh shell */
+        . = ALIGN(16);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(16);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(16);
+
+        /* section information for initial. */
+        . = ALIGN(16);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(16);
+
+        . = ALIGN(16);
+        _etext = .;
+    }
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(16);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(16);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(16);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        
+        PROVIDE(__bss_end = .);
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
+__bss_size = (__bss_end - __bss_start)>>3;
diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h
new file mode 100644
index 0000000000..479b6a0fd3
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h
@@ -0,0 +1,173 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 2048
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40003
+#define ARCH_ARMV8
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define BCM2711_SOC
+
+/* Hardware Drivers Config */
+
+/* BCM Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART0
+#define BSP_USING_GIC
+#define BSP_USING_GIC400
+#define BSP_USING_PIN
+#define BSP_USING_CORETIMER
+
+/* Board Peripheral Drivers */
+
+
+#endif
diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.py b/bsp/raspberry-pi/raspi4-32/rtconfig.py
new file mode 100644
index 0000000000..681ec91b9e
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-32/rtconfig.py
@@ -0,0 +1,54 @@
+import os
+
+# toolchains options
+ARCH        ='arm'
+CPU         ='cortex-a'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/usr/bin'  
+
+BUILD = 'debug'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+if PLATFORM == 'gcc':
+    # toolchains
+    # PREFIX = 'arm-none-eabi-'
+    PREFIX = 'arm-none-eabi-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n'
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 268cc7ef56..a8f3a36630 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -52,6 +52,26 @@ stack_top:
 /* reset entry */
 .globl _reset
 _reset:
+#ifdef ARCH_ARMV8
+    /* Check for HYP mode */
+    mrs r0, cpsr_all
+    and r0, r0, #0x1F
+    mov r8, #0x1A
+    cmp r0, r8
+    beq overHyped
+    b continue
+
+overHyped: /* Get out of HYP mode */
+    ldr r1, =continue
+    msr ELR_hyp, r1
+    mrs r1, cpsr_all
+    and r1, r1, #0x1f    ;@ CPSR_MODE_MASK
+    orr r1, r1, #0x13    ;@ CPSR_MODE_SUPERVISOR
+    msr SPSR_hyp, r1
+    eret
+
+continue:
+#endif
     /* set the cpu to SVC32 mode and disable interrupt */
     cps #Mode_SVC
 
-- 
cgit v1.3.1


From f4c71fc5bf2cce76447dcf735726a6983320eda9 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Mon, 25 May 2020 17:46:48 +0800
Subject: rename raspi4 to raspi4-64

---
 bsp/raspberry-pi/raspi4-64/.config                 | 454 ++++++++++++++++++++
 bsp/raspberry-pi/raspi4-64/Kconfig                 |  29 ++
 bsp/raspberry-pi/raspi4-64/README.md               | 113 +++++
 bsp/raspberry-pi/raspi4-64/SConscript              |  14 +
 bsp/raspberry-pi/raspi4-64/SConstruct              |  30 ++
 bsp/raspberry-pi/raspi4-64/applications/SConscript |   9 +
 bsp/raspberry-pi/raspi4-64/applications/main.c     |  19 +
 bsp/raspberry-pi/raspi4-64/driver/Kconfig          |  97 +++++
 bsp/raspberry-pi/raspi4-64/driver/SConscript       |   9 +
 bsp/raspberry-pi/raspi4-64/driver/board.c          |  93 +++++
 bsp/raspberry-pi/raspi4-64/driver/board.h          |  25 ++
 bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c       | 117 ++++++
 bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h       |  77 ++++
 bsp/raspberry-pi/raspi4-64/driver/drv_uart.c       | 152 +++++++
 bsp/raspberry-pi/raspi4-64/driver/drv_uart.h       |  83 ++++
 bsp/raspberry-pi/raspi4-64/driver/raspi4.h         |  29 ++
 bsp/raspberry-pi/raspi4-64/link.lds                | 153 +++++++
 bsp/raspberry-pi/raspi4-64/rtconfig.h              | 174 ++++++++
 bsp/raspberry-pi/raspi4-64/rtconfig.py             |  51 +++
 bsp/raspberry-pi/raspi4/.config                    | 455 ---------------------
 bsp/raspberry-pi/raspi4/Kconfig                    |  29 --
 bsp/raspberry-pi/raspi4/README.md                  |  81 ----
 bsp/raspberry-pi/raspi4/SConscript                 |  14 -
 bsp/raspberry-pi/raspi4/SConstruct                 |  30 --
 bsp/raspberry-pi/raspi4/applications/SConscript    |   9 -
 bsp/raspberry-pi/raspi4/applications/main.c        |  19 -
 bsp/raspberry-pi/raspi4/driver/Kconfig             |  97 -----
 bsp/raspberry-pi/raspi4/driver/SConscript          |   9 -
 bsp/raspberry-pi/raspi4/driver/board.c             |  93 -----
 bsp/raspberry-pi/raspi4/driver/board.h             |  25 --
 bsp/raspberry-pi/raspi4/driver/drv_gpio.c          | 117 ------
 bsp/raspberry-pi/raspi4/driver/drv_gpio.h          |  77 ----
 bsp/raspberry-pi/raspi4/driver/drv_uart.c          | 152 -------
 bsp/raspberry-pi/raspi4/driver/drv_uart.h          |  83 ----
 bsp/raspberry-pi/raspi4/driver/iomap.h             |  29 --
 bsp/raspberry-pi/raspi4/link.lds                   | 153 -------
 bsp/raspberry-pi/raspi4/rtconfig.h                 | 179 --------
 bsp/raspberry-pi/raspi4/rtconfig.py                |  51 ---
 libcpu/Kconfig                                     |   3 +
 libcpu/aarch64/common/gic/gic_pl400.c              |   1 -
 libcpu/aarch64/cortex-a72/interrupt.c              |   1 -
 41 files changed, 1731 insertions(+), 1704 deletions(-)
 create mode 100644 bsp/raspberry-pi/raspi4-64/.config
 create mode 100644 bsp/raspberry-pi/raspi4-64/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi4-64/README.md
 create mode 100644 bsp/raspberry-pi/raspi4-64/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4-64/SConstruct
 create mode 100644 bsp/raspberry-pi/raspi4-64/applications/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4-64/applications/main.c
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/board.c
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/board.h
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/drv_uart.c
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/drv_uart.h
 create mode 100644 bsp/raspberry-pi/raspi4-64/driver/raspi4.h
 create mode 100644 bsp/raspberry-pi/raspi4-64/link.lds
 create mode 100644 bsp/raspberry-pi/raspi4-64/rtconfig.h
 create mode 100644 bsp/raspberry-pi/raspi4-64/rtconfig.py
 delete mode 100644 bsp/raspberry-pi/raspi4/.config
 delete mode 100644 bsp/raspberry-pi/raspi4/Kconfig
 delete mode 100644 bsp/raspberry-pi/raspi4/README.md
 delete mode 100644 bsp/raspberry-pi/raspi4/SConscript
 delete mode 100644 bsp/raspberry-pi/raspi4/SConstruct
 delete mode 100644 bsp/raspberry-pi/raspi4/applications/SConscript
 delete mode 100644 bsp/raspberry-pi/raspi4/applications/main.c
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/Kconfig
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/SConscript
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/board.c
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/board.h
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/drv_gpio.c
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/drv_gpio.h
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/drv_uart.c
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/drv_uart.h
 delete mode 100644 bsp/raspberry-pi/raspi4/driver/iomap.h
 delete mode 100644 bsp/raspberry-pi/raspi4/link.lds
 delete mode 100644 bsp/raspberry-pi/raspi4/rtconfig.h
 delete mode 100644 bsp/raspberry-pi/raspi4/rtconfig.py

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi4-64/.config b/bsp/raspberry-pi/raspi4-64/.config
new file mode 100644
index 0000000000..0ab68e8fe3
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/.config
@@ -0,0 +1,454 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_CPU_64BIT=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARMV8=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_BCM2711_SOC=y
+# CONFIG_BSP_SUPPORT_FPU is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# BCM Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART0=y
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GIC400=y
+# CONFIG_BSP_USING_GIC500 is not set
+CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_CORETIMER=y
+# CONFIG_BSP_USING_SYSTIMER is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SDIO is not set
+
+#
+# Board Peripheral Drivers
+#
+# CONFIG_BSP_USING_HDMI is not set
diff --git a/bsp/raspberry-pi/raspi4-64/Kconfig b/bsp/raspberry-pi/raspi4-64/Kconfig
new file mode 100644
index 0000000000..c1ee600450
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/Kconfig
@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2711_SOC
+    bool
+    select ARCH_ARMV8
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_CPU_64BIT
+    default y
+
+source "driver/Kconfig"
diff --git a/bsp/raspberry-pi/raspi4-64/README.md b/bsp/raspberry-pi/raspi4-64/README.md
new file mode 100644
index 0000000000..56aa6f0ca5
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/README.md
@@ -0,0 +1,113 @@
+# Raspberry PI 4板级支持包说明
+
+## 1. 简介
+
+树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
+
+外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
+
+这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+
+## 2. 编译说明
+
+
+
+### 2.1 Window上的环境搭建
+
+Windows环境下推荐使用[env工具](https://www.rt-thread.org/page/download.html)进行编译。
+
+首先下载windows上的aarch64的gcc交叉编译工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
+
+将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
+
+接着修改`bsp\raspberry-pi\raspi4-64\rtconfig.py`
+
+修改路径：
+
+```
+EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
+```
+
+然后在`bsp\raspberry-pi\raspi4-64\`下输入scons编译即可。
+
+**window环境搭建注意**
+
+下载完成`gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf.tar.xz`交叉编译工具链后，最好采用7-zip解压工具进行两次解压。
+确保解压目录下的`/bin/aarch64-elf-ld.exe`文件的size不为0。
+否则编译会出现如下错误:
+
+```
+collect2.exe:fatal error:CreateProcess:No such file or directory
+```
+
+### 2.2 Linux上的环境搭建
+
+Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
+
+将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。
+
+```
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
+```
+
+直接进入`bsp\raspberry-pi\raspi4-64`，输入scons编译即可。
+
+
+## 3. 执行
+
+### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡
+
+首先下载镜像
+
+* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb)
+* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe)
+* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg)
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
+
+![raspi2](../raspi3-32/figures/raspberrypi-console.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+### 3.3 程序下载
+
+当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下：
+
+```
+enable_uart=1
+arm_64bit=1
+kernel=rtthread.bin
+```
+
+按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
+
+```text
+heap: 0x000c9350 - 0x040c9350
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Apr 16 2020
+ 2006 - 2020 Copyright by rt-thread team
+Hi, this is RT-Thread!!
+msh />
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+[1]: https://www.rt-thread.org/page/download.html
+[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
+[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+[4]: https://etcher.io
+[5]: https://github.com/BernardXiong
diff --git a/bsp/raspberry-pi/raspi4-64/SConscript b/bsp/raspberry-pi/raspi4-64/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/raspberry-pi/raspi4-64/SConstruct b/bsp/raspberry-pi/raspi4-64/SConstruct
new file mode 100644
index 0000000000..93f349aab8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/SConstruct
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)
+
diff --git a/bsp/raspberry-pi/raspi4-64/applications/SConscript b/bsp/raspberry-pi/raspi4-64/applications/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi4-64/applications/main.c b/bsp/raspberry-pi/raspi4-64/applications/main.c
new file mode 100644
index 0000000000..9664e67d01
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hi, this is RT-Thread!!\n");
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi4-64/driver/Kconfig b/bsp/raspberry-pi/raspi4-64/driver/Kconfig
new file mode 100644
index 0000000000..208b4b4300
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/Kconfig
@@ -0,0 +1,97 @@
+
+config BSP_SUPPORT_FPU
+    bool "Using Float"
+    default n
+
+menu "Hardware Drivers Config"
+    menu "BCM Peripheral Drivers"
+        menuconfig BSP_USING_UART
+            bool "Using UART"
+            select RT_USING_SERIAL
+            default y
+
+            if BSP_USING_UART
+                config RT_USING_UART0
+                bool "Enabel UART 0"
+                default y
+            endif
+            
+        menuconfig BSP_USING_GIC
+            bool "Enable GIC"
+            select RT_USING_GIC
+            default y
+        if BSP_USING_GIC
+            config BSP_USING_GIC400
+                bool "Enable GIC400"
+                default y
+            config BSP_USING_GIC500
+                bool "Enable GIC500"
+                default n
+        endif
+
+        config BSP_USING_PIN
+            bool "Using PIN"
+            select RT_USING_PIN
+            default y
+
+        config BSP_USING_CORETIMER
+            bool "Using core timer"
+            select RT_USING_CORETIMER
+            default y
+
+        menuconfig BSP_USING_SYSTIMER
+            bool "Enable SYSTIMER"
+            select BSP_USING_SYSTIMER
+            default n
+
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
+        endif
+
+        config BSP_USING_WDT
+            bool "Enable WDT"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+
+        if BSP_USING_RTC
+            config BSP_USING_ALARM
+                bool "Enable Alarm"
+                select RT_USING_ALARM
+                default n
+        endif
+        
+        menuconfig BSP_USING_SDIO
+            bool "Enable SDIO"
+            select RT_USING_SDIO
+            default n
+
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO0
+                bool "Enable SDIO0"
+                select RT_USING_SDIO
+                default n
+        endif
+    endmenu
+
+    menu "Board Peripheral Drivers"
+        menuconfig BSP_USING_HDMI
+            bool "Enable HDMI"
+            default n
+
+        if BSP_USING_HDMI
+            config BSP_USING_HDMI_DISPLAY
+                bool "HDMI DISPLAY"
+                default n
+        endif
+    endmenu
+endmenu
diff --git a/bsp/raspberry-pi/raspi4-64/driver/SConscript b/bsp/raspberry-pi/raspi4-64/driver/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi4-64/driver/board.c b/bsp/raspberry-pi/raspi4-64/driver/board.c
new file mode 100644
index 0000000000..79a24d184f
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/board.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include "cp15.h"
+#include "mmu.h"
+
+static rt_uint64_t timerStep;
+
+int rt_hw_get_gtimer_frq(void);
+void rt_hw_set_gtimer_val(rt_uint64_t value);
+int rt_hw_get_gtimer_val(void);
+int rt_hw_get_cntpct_val(void);
+void rt_hw_gtimer_enable(void);
+
+void core0_timer_enable_interrupt_controller(void)
+{
+    CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
+}
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    rt_hw_set_gtimer_val(timerStep);
+    rt_tick_increase();
+}
+
+void rt_hw_timer_init(void)
+{
+    rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(TIMER_IRQ);
+    __ISB();
+    timerStep = rt_hw_get_gtimer_frq();
+    __DSB();
+    timerStep /= RT_TICK_PER_SECOND;
+    
+    rt_hw_gtimer_enable();
+    rt_hw_set_gtimer_val(timerStep);
+    core0_timer_enable_interrupt_controller();
+}
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+/**
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  after interrupt disabled.
+ */
+void rt_hw_board_init(void)
+{
+    mmu_init();
+    armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
+    armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio
+    armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer
+    mmu_enable();
+
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
+    rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
+
+    /* initialize uart */
+    rt_hw_uart_init();      // driver/drv_uart.c
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+        /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
diff --git a/bsp/raspberry-pi/raspi4-64/driver/board.h b/bsp/raspberry-pi/raspi4-64/driver/board.h
new file mode 100644
index 0000000000..d675cc658e
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/board.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+#include "raspi4.h"
+
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c
new file mode 100644
index 0000000000..4317a358e0
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_PIN
+
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+{
+    uint32_t fselnum = pin / 10;
+    uint32_t fselrest = pin % 10;
+
+    uint32_t gpfsel = 0;
+    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
+    gpfsel |= (uint32_t)(mode << (fselrest * 3));
+
+    switch (fselnum)
+    {
+    case 0:
+        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
+        break;
+    case 1:
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+        break;
+    case 2:
+        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
+        break;
+    case 3:
+        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
+        break;
+    case 4:
+        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
+        break;
+    case 5:
+        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
+        break;
+    default:
+        break;
+    }
+}
+
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+{
+    uint32_t num = pin / 32;
+
+    if(num == 0)
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
+        }
+    }
+    else
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        
+    }
+}
+
+static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+{
+    return 0;
+}
+
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    return RT_EOK;
+}
+
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    return RT_EOK;
+}
+
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    return RT_EOK;
+}
+
+static const struct rt_pin_ops ops =
+{
+    raspi_pin_mode,
+    raspi_pin_write,
+    raspi_pin_read,
+    raspi_pin_attach_irq,
+    raspi_pin_detach_irq,
+    raspi_pin_irq_enable,
+};
+#endif
+
+int rt_hw_gpio_init(void)
+{
+#ifdef BSP_USING_PIN
+    rt_device_pin_register("gpio", &ops, RT_NULL);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gpio_init);
diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h
new file mode 100644
index 0000000000..c4658fcebb
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "interrupt.h"
+
+#define GPIO_REG_GPFSEL0(BASE)             HWREG32(BASE + 0x00)
+#define GPIO_REG_GPFSEL1(BASE)             HWREG32(BASE + 0x04)
+#define GPIO_REG_GPFSEL2(BASE)             HWREG32(BASE + 0x08)
+#define GPIO_REG_GPFSEL3(BASE)             HWREG32(BASE + 0x0C)
+#define GPIO_REG_GPFSEL4(BASE)             HWREG32(BASE + 0x10)
+#define GPIO_REG_GPFSEL5(BASE)             HWREG32(BASE + 0x14)
+#define GPIO_REG_REV0(BASE)                HWREG32(BASE + 0x18)
+#define GPIO_REG_GPSET0(BASE)              HWREG32(BASE + 0x1C)
+#define GPIO_REG_GPSET1(BASE)              HWREG32(BASE + 0x20)
+#define GPIO_REG_REV1(BASE)                HWREG32(BASE + 0x24)
+#define GPIO_REG_GPCLR0(BASE)              HWREG32(BASE + 0x28)
+#define GPIO_REG_GPCLR1(BASE)              HWREG32(BASE + 0x2C)
+#define GPIO_REG_REV2(BASE)                HWREG32(BASE + 0x30)
+#define GPIO_REG_GPLEV0(BASE)              HWREG32(BASE + 0x34)
+#define GPIO_REG_GPLEV1(BASE)              HWREG32(BASE + 0x38)
+#define GPIO_REG_REV3(BASE)                HWREG32(BASE + 0x3C)
+#define GPIO_REG_GPEDS0(BASE)              HWREG32(BASE + 0x40)
+#define GPIO_REG_GPEDS1(BASE)              HWREG32(BASE + 0x44)
+#define GPIO_REG_REV4(BASE)                HWREG32(BASE + 0x48)
+#define GPIO_REG_GPREN0(BASE)              HWREG32(BASE + 0x4C)
+#define GPIO_REG_GPREN1(BASE)              HWREG32(BASE + 0x50)
+#define GPIO_REG_REV5(BASE)                HWREG32(BASE + 0x54)
+#define GPIO_REG_GPFEN0(BASE)              HWREG32(BASE + 0x58)
+#define GPIO_REG_GPFEN1(BASE)              HWREG32(BASE + 0x5C)
+#define GPIO_REG_REV6(BASE)                HWREG32(BASE + 0x60)
+#define GPIO_REG_GPHEN0(BASE)              HWREG32(BASE + 0x64)
+#define GPIO_REG_GPHEN1(BASE)              HWREG32(BASE + 0x68)
+#define GPIO_REG_REV7(BASE)                HWREG32(BASE + 0x6C)
+#define GPIO_REG_GPLEN0(BASE)              HWREG32(BASE + 0x70)
+#define GPIO_REG_GPLEN1(BASE)              HWREG32(BASE + 0x74)
+#define GPIO_REG_REV8(BASE)                HWREG32(BASE + 0x78)
+#define GPIO_REG_GPAREN0(BASE)             HWREG32(BASE + 0x7C)
+#define GPIO_REG_GPAREN1(BASE)             HWREG32(BASE + 0x80)
+#define GPIO_REG_REV11(BASE)               HWREG32(BASE + 0x84)
+#define GPIO_REG_GPAFEN0(BASE)             HWREG32(BASE + 0x88)
+#define GPIO_REG_GPAFEN1(BASE)             HWREG32(BASE + 0x8C)
+#define GPIO_REG_REV10(BASE)               HWREG32(BASE + 0x90)
+#define GPIO_REG_GPPUD(BASE)               HWREG32(BASE + 0x94)
+#define GPIO_REG_GPPUDCLK0(BASE)           HWREG32(BASE + 0x98)
+#define GPIO_REG_GPPUDCLK1(BASE)           HWREG32(BASE + 0x9C)
+#define GPIO_REG_REV9(BASE)                HWREG32(BASE + 0xA0)
+#define GPIO_REG_TEST(BASE)                HWREG32(BASE + 0xA4)
+
+typedef enum {
+    INPUT = 0b000,
+    OUTPUT = 0b001,
+    ALT0 = 0b100,
+    ALT1 = 0b101,
+    ALT2 = 0b110,
+    ALT3 = 0b111,
+    ALT4 = 0b011,
+    ALT5 = 0b010
+} GPIO_FUNC;
+
+
+int rt_hw_gpio_init(void);
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c
new file mode 100644
index 0000000000..6a70cdfb3a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+
+struct hw_uart_device
+{
+    rt_ubase_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+    uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16;
+    uint32_t ibrd = bauddiv / 1000;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+    if(uart->hw_base == PL011_BASE)
+    {
+        uint32_t gpfsel = 0;
+
+        gpfsel &= ~((uint32_t)(0x07 << (4 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (4 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        gpfsel &= ~((uint32_t)(0x07 << (5 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (5 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
+        PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
+        PL011_REG_IBRD(uart->hw_base) = ibrd;
+        PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
+        PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
+        PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM);
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
+    PL011_REG_DR(uart->hw_base) = (uint8_t)c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
+    {
+        ch = PL011_REG_DR(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
+}
+
+
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    PL011_BASE,
+    IRQ_PL011,
+};
+
+static struct rt_serial_device _serial0;
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart");
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h
new file mode 100644
index 0000000000..714043efd3
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+// register's bit
+#define PL011_FR_RI          (1 << 8)
+#define PL011_FR_TXFE        (1 << 7)
+#define PL011_FR_RXFF        (1 << 6)
+#define PL011_FR_TXFF        (1 << 5)
+#define PL011_FR_RXFE        (1 << 4)
+#define PL011_FR_BUSY        (1 << 3)
+#define PL011_FR_DCD         (1 << 2)
+#define PL011_FR_DSR         (1 << 1)
+#define PL011_FR_CTS         (1 << 0)
+
+#define PL011_LCRH_SPS       (1 << 7)
+#define PL011_LCRH_WLEN_8    (3 << 5)
+#define PL011_LCRH_WLEN_7    (2 << 5)
+#define PL011_LCRH_WLEN_6    (1 << 5)
+#define PL011_LCRH_WLEN_5    (0 << 5)
+#define PL011_LCRH_FEN       (1 << 4)
+#define PL011_LCRH_STP2      (1 << 3)
+#define PL011_LCRH_EPS       (1 << 2)
+#define PL011_LCRH_PEN       (1 << 1)
+#define PL011_LCRH_BRK       (1 << 0)
+
+#define PL011_CR_CTSEN       (1 << 15)
+#define PL011_CR_RTSEN       (1 << 14)
+#define PL011_CR_RTS         (1 << 11)
+#define PL011_CR_DTR         (1 << 10)
+#define PL011_CR_RXE         (1 << 9)
+#define PL011_CR_TXE         (1 << 8)
+#define PL011_CR_LBE         (1 << 7)
+#define PL011_CR_SIRLP       (1 << 2)
+#define PL011_CR_SIREN       (1 << 1)
+#define PL011_CR_UARTEN      (1 << 0)
+
+#define PL011_IMSC_TXIM      (1 << 5)
+#define PL011_IMSC_RXIM      (1 << 4)
+
+#define PL011_INTERRUPT_OVERRUN_ERROR   (1 << 10)
+#define PL011_INTERRUPT_BREAK_ERROR     (1 << 9)
+#define PL011_INTERRUPT_PARITY_ERROR    (1 << 8)
+#define PL011_INTERRUPT_FRAMING_ERROR   (1 << 7)
+#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
+#define PL011_INTERRUPT_TRANSMIT        (1 << 5)
+#define PL011_INTERRUPT_RECEIVE         (1 << 4)
+#define PL011_INTERRUPT_nUARTCTS        (1 << 1)
+
+#define PL011_REG_DR(BASE)              HWREG32(BASE + 0x00)
+#define PL011_REG_RSRECR(BASE)          HWREG32(BASE + 0x04)
+#define PL011_REG_RESERVED0(BASE)       HWREG32(BASE + 0x08)
+#define PL011_REG_FR(BASE)              HWREG32(BASE + 0x18)
+#define PL011_REG_RESERVED1(BASE)       HWREG32(BASE + 0x1C)
+#define PL011_REG_ILPR(BASE)            HWREG32(BASE + 0x20)
+#define PL011_REG_IBRD(BASE)            HWREG32(BASE + 0x24)
+#define PL011_REG_FBRD(BASE)            HWREG32(BASE + 0x28)
+#define PL011_REG_LCRH(BASE)            HWREG32(BASE + 0x2C)
+#define PL011_REG_CR(BASE)              HWREG32(BASE + 0x30)
+#define PL011_REG_IFLS(BASE)            HWREG32(BASE + 0x34)
+#define PL011_REG_IMSC(BASE)            HWREG32(BASE + 0x38)
+#define PL011_REG_RIS(BASE)             HWREG32(BASE + 0x3C)
+#define PL011_REG_MIS(BASE)             HWREG32(BASE + 0x40)
+#define PL011_REG_ICR(BASE)             HWREG32(BASE + 0x44)
+#define PL011_REG_DMACR(BASE)           HWREG32(BASE + 0x48)
+#define PL011_REG_RESERVED2(BASE)       HWREG32(BASE + 0x4C)
+#define PL011_REG_ITCR(BASE)            HWREG32(BASE + 0x80)
+#define PL011_REG_ITIP(BASE)            HWREG32(BASE + 0x84)
+#define PL011_REG_ITOP(BASE)            HWREG32(BASE + 0x88)
+#define PL011_REG_TDR(BASE)             HWREG32(BASE + 0x8C)
+
+int rt_hw_uart_init(void);
+
+#endif /* DRV_UART_H__ */
diff --git a/bsp/raspberry-pi/raspi4-64/driver/raspi4.h b/bsp/raspberry-pi/raspi4-64/driver/raspi4.h
new file mode 100644
index 0000000000..3f18353904
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/driver/raspi4.h
@@ -0,0 +1,29 @@
+#ifndef __RASPI4_H__
+#define __RASPI4_H__
+
+//gpio
+#define GPIO_BASE (0xFE000000 + 0x00200000)
+
+//uart
+#define UART0_BASE                  (0xFE000000 + 0x00201000)
+#define PL011_BASE                  UART0_BASE
+#define IRQ_PL011                   (121 + 32)
+#define UART_REFERENCE_CLOCK        (48000000)
+
+// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
+#define CORE0_TIMER_IRQ_CTRL    HWREG32(0xFF800040)
+#define TIMER_IRQ               30
+#define NON_SECURE_TIMER_IRQ    (1 << 1)
+
+//gic max
+#define ARM_GIC_NR_IRQS             (512)
+#define INTC_BASE                   (0xff800000)
+#define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
+#define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
+#define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
+#define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
+
+#define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
+#define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
+
+#endif
diff --git a/bsp/raspberry-pi/raspi4-64/link.lds b/bsp/raspberry-pi/raspi4-64/link.lds
new file mode 100644
index 0000000000..b7b2dcc32c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/link.lds
@@ -0,0 +1,153 @@
+/*
+ * File      : link.lds
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
+
+SECTIONS
+{
+    . = 0x80000;
+    . = ALIGN(4096);
+    .text :
+    {
+        KEEP(*(.text.entrypoint))       /* The entry point */
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        *(COMMON)
+        
+        /* section information for finsh shell */
+        . = ALIGN(16);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(16);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(16);
+
+        /* section information for initial. */
+        . = ALIGN(16);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(16);
+
+        . = ALIGN(16);
+        _etext = .;
+    }
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(16);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(16);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(16);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        
+        PROVIDE(__bss_end = .);
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
+__bss_size = (__bss_end - __bss_start)>>3;
diff --git a/bsp/raspberry-pi/raspi4-64/rtconfig.h b/bsp/raspberry-pi/raspi4-64/rtconfig.h
new file mode 100644
index 0000000000..bdde9d5f4a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/rtconfig.h
@@ -0,0 +1,174 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 2048
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40003
+#define ARCH_CPU_64BIT
+#define ARCH_ARMV8
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define BCM2711_SOC
+
+/* Hardware Drivers Config */
+
+/* BCM Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART0
+#define BSP_USING_GIC
+#define BSP_USING_GIC400
+#define BSP_USING_PIN
+#define BSP_USING_CORETIMER
+
+/* Board Peripheral Drivers */
+
+
+#endif
diff --git a/bsp/raspberry-pi/raspi4-64/rtconfig.py b/bsp/raspberry-pi/raspi4-64/rtconfig.py
new file mode 100644
index 0000000000..a1dd168d3d
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4-64/rtconfig.py
@@ -0,0 +1,51 @@
+import os
+
+# toolchains options
+ARCH        ='aarch64'
+CPU         ='cortex-a72'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    # PREFIX = 'arm-none-eabi-'
+    PREFIX = 'aarch64-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/raspberry-pi/raspi4/.config b/bsp/raspberry-pi/raspi4/.config
deleted file mode 100644
index e300d0217b..0000000000
--- a/bsp/raspberry-pi/raspi4/.config
+++ /dev/null
@@ -1,455 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Project Configuration
-#
-
-#
-# RT-Thread Kernel
-#
-CONFIG_RT_NAME_MAX=8
-# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
-# CONFIG_RT_USING_SMP is not set
-CONFIG_RT_ALIGN_SIZE=4
-# CONFIG_RT_THREAD_PRIORITY_8 is not set
-CONFIG_RT_THREAD_PRIORITY_32=y
-# CONFIG_RT_THREAD_PRIORITY_256 is not set
-CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=100
-CONFIG_RT_USING_OVERFLOW_CHECK=y
-CONFIG_RT_USING_HOOK=y
-CONFIG_RT_USING_IDLE_HOOK=y
-CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=2048
-CONFIG_RT_USING_TIMER_SOFT=y
-CONFIG_RT_TIMER_THREAD_PRIO=4
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
-CONFIG_RT_DEBUG=y
-# CONFIG_RT_DEBUG_COLOR is not set
-# CONFIG_RT_DEBUG_INIT_CONFIG is not set
-# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
-# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
-# CONFIG_RT_DEBUG_IPC_CONFIG is not set
-# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
-# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
-# CONFIG_RT_DEBUG_MEM_CONFIG is not set
-# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
-# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
-# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
-
-#
-# Inter-Thread communication
-#
-CONFIG_RT_USING_SEMAPHORE=y
-CONFIG_RT_USING_MUTEX=y
-CONFIG_RT_USING_EVENT=y
-CONFIG_RT_USING_MAILBOX=y
-CONFIG_RT_USING_MESSAGEQUEUE=y
-# CONFIG_RT_USING_SIGNALS is not set
-
-#
-# Memory Management
-#
-CONFIG_RT_USING_MEMPOOL=y
-# CONFIG_RT_USING_MEMHEAP is not set
-# CONFIG_RT_USING_NOHEAP is not set
-CONFIG_RT_USING_SMALL_MEM=y
-# CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMTRACE is not set
-CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
-CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_INTERRUPT_INFO is not set
-CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
-CONFIG_RT_VER_NUM=0x40003
-CONFIG_ARCH_CPU_64BIT=y
-# CONFIG_RT_USING_CPU_FFS is not set
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
-
-#
-# RT-Thread Components
-#
-CONFIG_RT_USING_COMPONENTS_INIT=y
-CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
-CONFIG_RT_MAIN_THREAD_PRIORITY=10
-
-#
-# C++ features
-#
-# CONFIG_RT_USING_CPLUSPLUS is not set
-
-#
-# Command shell
-#
-CONFIG_RT_USING_FINSH=y
-CONFIG_FINSH_THREAD_NAME="tshell"
-CONFIG_FINSH_USING_HISTORY=y
-CONFIG_FINSH_HISTORY_LINES=5
-CONFIG_FINSH_USING_SYMTAB=y
-CONFIG_FINSH_USING_DESCRIPTION=y
-# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
-# CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
-CONFIG_FINSH_ARG_MAX=10
-
-#
-# Device virtual file system
-#
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
-
-#
-# Device Drivers
-#
-CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_PIPE_BUFSZ=512
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
-CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
-CONFIG_RT_SERIAL_RB_BUFSZ=64
-# CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
-# CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
-CONFIG_RT_USING_PIN=y
-# CONFIG_RT_USING_ADC is not set
-# CONFIG_RT_USING_PWM is not set
-# CONFIG_RT_USING_MTD_NOR is not set
-# CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
-# CONFIG_RT_USING_WDT is not set
-# CONFIG_RT_USING_AUDIO is not set
-# CONFIG_RT_USING_SENSOR is not set
-# CONFIG_RT_USING_TOUCH is not set
-# CONFIG_RT_USING_HWCRYPTO is not set
-# CONFIG_RT_USING_PULSE_ENCODER is not set
-# CONFIG_RT_USING_INPUT_CAPTURE is not set
-# CONFIG_RT_USING_WIFI is not set
-
-#
-# Using USB
-#
-# CONFIG_RT_USING_USB_HOST is not set
-# CONFIG_RT_USING_USB_DEVICE is not set
-
-#
-# POSIX layer and C standard library
-#
-CONFIG_RT_USING_LIBC=y
-# CONFIG_RT_USING_PTHREADS is not set
-CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
-# CONFIG_RT_USING_MODULE is not set
-
-#
-# Network
-#
-
-#
-# Socket abstraction layer
-#
-# CONFIG_RT_USING_SAL is not set
-
-#
-# Network interface device
-#
-# CONFIG_RT_USING_NETDEV is not set
-
-#
-# light weight TCP/IP stack
-#
-# CONFIG_RT_USING_LWIP is not set
-
-#
-# AT commands
-#
-# CONFIG_RT_USING_AT is not set
-
-#
-# VBUS(Virtual Software BUS)
-#
-# CONFIG_RT_USING_VBUS is not set
-
-#
-# Utilities
-#
-# CONFIG_RT_USING_RYM is not set
-# CONFIG_RT_USING_ULOG is not set
-# CONFIG_RT_USING_UTEST is not set
-
-#
-# RT-Thread online packages
-#
-
-#
-# IoT - internet of things
-#
-# CONFIG_PKG_USING_PAHOMQTT is not set
-# CONFIG_PKG_USING_WEBCLIENT is not set
-# CONFIG_PKG_USING_WEBNET is not set
-# CONFIG_PKG_USING_MONGOOSE is not set
-# CONFIG_PKG_USING_MYMQTT is not set
-# CONFIG_PKG_USING_WEBTERMINAL is not set
-# CONFIG_PKG_USING_CJSON is not set
-# CONFIG_PKG_USING_JSMN is not set
-# CONFIG_PKG_USING_LIBMODBUS is not set
-# CONFIG_PKG_USING_FREEMODBUS is not set
-# CONFIG_PKG_USING_LJSON is not set
-# CONFIG_PKG_USING_EZXML is not set
-# CONFIG_PKG_USING_NANOPB is not set
-
-#
-# Wi-Fi
-#
-
-#
-# Marvell WiFi
-#
-# CONFIG_PKG_USING_WLANMARVELL is not set
-
-#
-# Wiced WiFi
-#
-# CONFIG_PKG_USING_WLAN_WICED is not set
-# CONFIG_PKG_USING_RW007 is not set
-# CONFIG_PKG_USING_COAP is not set
-# CONFIG_PKG_USING_NOPOLL is not set
-# CONFIG_PKG_USING_NETUTILS is not set
-# CONFIG_PKG_USING_PPP_DEVICE is not set
-# CONFIG_PKG_USING_AT_DEVICE is not set
-# CONFIG_PKG_USING_ATSRV_SOCKET is not set
-# CONFIG_PKG_USING_WIZNET is not set
-
-#
-# IoT Cloud
-#
-# CONFIG_PKG_USING_ONENET is not set
-# CONFIG_PKG_USING_GAGENT_CLOUD is not set
-# CONFIG_PKG_USING_ALI_IOTKIT is not set
-# CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
-# CONFIG_PKG_USING_JIOT-C-SDK is not set
-# CONFIG_PKG_USING_NIMBLE is not set
-# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
-# CONFIG_PKG_USING_IPMSG is not set
-# CONFIG_PKG_USING_LSSDP is not set
-# CONFIG_PKG_USING_AIRKISS_OPEN is not set
-# CONFIG_PKG_USING_LIBRWS is not set
-# CONFIG_PKG_USING_TCPSERVER is not set
-# CONFIG_PKG_USING_PROTOBUF_C is not set
-# CONFIG_PKG_USING_ONNX_PARSER is not set
-# CONFIG_PKG_USING_ONNX_BACKEND is not set
-# CONFIG_PKG_USING_DLT645 is not set
-# CONFIG_PKG_USING_QXWZ is not set
-# CONFIG_PKG_USING_SMTP_CLIENT is not set
-# CONFIG_PKG_USING_ABUP_FOTA is not set
-
-#
-# security packages
-#
-# CONFIG_PKG_USING_MBEDTLS is not set
-# CONFIG_PKG_USING_libsodium is not set
-# CONFIG_PKG_USING_TINYCRYPT is not set
-
-#
-# language packages
-#
-# CONFIG_PKG_USING_LUA is not set
-# CONFIG_PKG_USING_JERRYSCRIPT is not set
-# CONFIG_PKG_USING_MICROPYTHON is not set
-
-#
-# multimedia packages
-#
-# CONFIG_PKG_USING_OPENMV is not set
-# CONFIG_PKG_USING_MUPDF is not set
-# CONFIG_PKG_USING_STEMWIN is not set
-# CONFIG_PKG_USING_WAVPLAYER is not set
-# CONFIG_PKG_USING_TJPGD is not set
-
-#
-# tools packages
-#
-# CONFIG_PKG_USING_CMBACKTRACE is not set
-# CONFIG_PKG_USING_EASYFLASH is not set
-# CONFIG_PKG_USING_EASYLOGGER is not set
-# CONFIG_PKG_USING_SYSTEMVIEW is not set
-# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
-# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
-# CONFIG_PKG_USING_ADBD is not set
-# CONFIG_PKG_USING_COREMARK is not set
-# CONFIG_PKG_USING_DHRYSTONE is not set
-# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
-# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
-# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
-# CONFIG_PKG_USING_BS8116A is not set
-
-#
-# system packages
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_CAIRO is not set
-# CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_FAL is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-# CONFIG_PKG_USING_CMSIS is not set
-# CONFIG_PKG_USING_DFS_YAFFS is not set
-# CONFIG_PKG_USING_LITTLEFS is not set
-# CONFIG_PKG_USING_THREAD_POOL is not set
-# CONFIG_PKG_USING_ROBOTS is not set
-# CONFIG_PKG_USING_EV is not set
-
-#
-# peripheral libraries and drivers
-#
-# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
-# CONFIG_PKG_USING_SHT2X is not set
-# CONFIG_PKG_USING_SHT3X is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_ICM20608 is not set
-# CONFIG_PKG_USING_U8G2 is not set
-# CONFIG_PKG_USING_BUTTON is not set
-# CONFIG_PKG_USING_PCF8574 is not set
-# CONFIG_PKG_USING_SX12XX is not set
-# CONFIG_PKG_USING_SIGNAL_LED is not set
-# CONFIG_PKG_USING_LEDBLINK is not set
-# CONFIG_PKG_USING_WM_LIBRARIES is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
-# CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
-# CONFIG_PKG_USING_AGILE_BUTTON is not set
-# CONFIG_PKG_USING_AGILE_LED is not set
-# CONFIG_PKG_USING_AT24CXX is not set
-# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
-# CONFIG_PKG_USING_AD7746 is not set
-# CONFIG_PKG_USING_PCA9685 is not set
-# CONFIG_PKG_USING_I2C_TOOLS is not set
-# CONFIG_PKG_USING_NRF24L01 is not set
-# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
-# CONFIG_PKG_USING_MAX17048 is not set
-# CONFIG_PKG_USING_RPLIDAR is not set
-# CONFIG_PKG_USING_AS608 is not set
-
-#
-# miscellaneous packages
-#
-# CONFIG_PKG_USING_LIBCSV is not set
-# CONFIG_PKG_USING_OPTPARSE is not set
-# CONFIG_PKG_USING_FASTLZ is not set
-# CONFIG_PKG_USING_MINILZO is not set
-# CONFIG_PKG_USING_QUICKLZ is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
-# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
-# CONFIG_PKG_USING_CANFESTIVAL is not set
-# CONFIG_PKG_USING_ZLIB is not set
-# CONFIG_PKG_USING_DSTR is not set
-# CONFIG_PKG_USING_TINYFRAME is not set
-# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
-# CONFIG_PKG_USING_DIGITALCTRL is not set
-# CONFIG_PKG_USING_UPACKER is not set
-# CONFIG_PKG_USING_UPARAM is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-# CONFIG_PKG_USING_HELLO is not set
-# CONFIG_PKG_USING_VI is not set
-# CONFIG_PKG_USING_NNOM is not set
-# CONFIG_PKG_USING_LIBANN is not set
-# CONFIG_PKG_USING_ELAPACK is not set
-# CONFIG_PKG_USING_ARMv7M_DWT is not set
-# CONFIG_PKG_USING_VT100 is not set
-# CONFIG_PKG_USING_ULAPACK is not set
-# CONFIG_PKG_USING_UKAL is not set
-
-#
-# Privated Packages of RealThread
-#
-# CONFIG_PKG_USING_CODEC is not set
-# CONFIG_PKG_USING_PLAYER is not set
-# CONFIG_PKG_USING_MPLAYER is not set
-# CONFIG_PKG_USING_PERSIMMON_SRC is not set
-# CONFIG_PKG_USING_JS_PERSIMMON is not set
-# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
-
-#
-# Network Utilities
-#
-# CONFIG_PKG_USING_WICED is not set
-# CONFIG_PKG_USING_CLOUDSDK is not set
-# CONFIG_PKG_USING_POWER_MANAGER is not set
-# CONFIG_PKG_USING_RT_OTA is not set
-# CONFIG_PKG_USING_RDBD_SRC is not set
-# CONFIG_PKG_USING_RTINSIGHT is not set
-# CONFIG_PKG_USING_SMARTCONFIG is not set
-# CONFIG_PKG_USING_RTX is not set
-# CONFIG_RT_USING_TESTCASE is not set
-# CONFIG_PKG_USING_NGHTTP2 is not set
-# CONFIG_PKG_USING_AVS is not set
-# CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_STS is not set
-# CONFIG_PKG_USING_DLMS is not set
-# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
-# CONFIG_PKG_USING_ZBAR is not set
-CONFIG_BCM2711_SOC=y
-# CONFIG_BSP_SUPPORT_FPU is not set
-
-#
-# Hardware Drivers Config
-#
-
-#
-# BCM Peripheral Drivers
-#
-CONFIG_BSP_USING_UART=y
-CONFIG_RT_USING_UART0=y
-CONFIG_BSP_USING_GIC=y
-CONFIG_BSP_USING_GIC400=y
-# CONFIG_BSP_USING_GIC500 is not set
-CONFIG_BSP_USING_PIN=y
-CONFIG_BSP_USING_CORETIMER=y
-# CONFIG_BSP_USING_SYSTIMER is not set
-# CONFIG_BSP_USING_WDT is not set
-# CONFIG_BSP_USING_RTC is not set
-# CONFIG_BSP_USING_SDIO is not set
-
-#
-# Board Peripheral Drivers
-#
-# CONFIG_BSP_USING_HDMI is not set
diff --git a/bsp/raspberry-pi/raspi4/Kconfig b/bsp/raspberry-pi/raspi4/Kconfig
deleted file mode 100644
index 075a5d81aa..0000000000
--- a/bsp/raspberry-pi/raspi4/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-mainmenu "RT-Thread Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config RTT_DIR
-    string
-    option env="RTT_ROOT"
-    default "../../.."
-
-config PKGS_DIR
-    string
-    option env="PKGS_ROOT"
-    default "packages"
-
-source "$RTT_DIR/Kconfig"
-source "$PKGS_DIR/Kconfig"
-
-config BCM2711_SOC
-    bool
-    select ARCH_ARM_CORTEX_A72
-    select RT_USING_COMPONENTS_INIT
-    select RT_USING_USER_MAIN
-    select ARCH_CPU_64BIT
-    default y
-
-source "driver/Kconfig"
diff --git a/bsp/raspberry-pi/raspi4/README.md b/bsp/raspberry-pi/raspi4/README.md
deleted file mode 100644
index 1e7411894e..0000000000
--- a/bsp/raspberry-pi/raspi4/README.md
+++ /dev/null
@@ -1,81 +0,0 @@
-# Raspberry PI 4板级支持包说明
-
-## 1. 简介
-
-树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
-
-外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
-
-这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
-
-
-## 2. 编译说明
-
-Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
-
-将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。
-
-```
-PLATFORM    = 'gcc'
-EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
-```
-
-直接进入`bsp\raspberry-pi\raspi4`，输入scons编译即可。
-
-
-## 3. 执行
-
-### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡
-
-首先下载镜像
-
-* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb)
-* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe)
-* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg)
-
-### 3.2 准备好串口线
-
-目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
-
-![raspi2](../raspi3-32/figures/raspberrypi-console.png)
-
-串口参数： 115200 8N1 ，硬件和软件流控为关。
-
-### 3.3 程序下载
-
-当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下：
-
-```
-enable_uart=1
-arm_64bit=1
-kernel=rtthread.bin
-```
-
-按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
-
-```text
-heap: 0x000c9350 - 0x040c9350
-
- \ | /
-- RT -     Thread Operating System
- / | \     4.0.3 build Apr 16 2020
- 2006 - 2020 Copyright by rt-thread team
-Hi, this is RT-Thread!!
-msh />
-```
-
-## 4. 支持情况
-
-| 驱动 | 支持情况  |  备注  |
-| ------ | ----  | :------:  |
-| UART | 支持 | UART0|
-
-## 5. 联系人信息
-
-维护人：[bernard][5]
-
-[1]: https://www.rt-thread.org/page/download.html
-[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
-[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
-[4]: https://etcher.io
-[5]: https://github.com/BernardXiong
diff --git a/bsp/raspberry-pi/raspi4/SConscript b/bsp/raspberry-pi/raspi4/SConscript
deleted file mode 100644
index c7ef7659ec..0000000000
--- a/bsp/raspberry-pi/raspi4/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# for module compiling
-import os
-from building import *
-
-cwd = GetCurrentDir()
-objs = []
-list = os.listdir(cwd)
-
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')
diff --git a/bsp/raspberry-pi/raspi4/SConstruct b/bsp/raspberry-pi/raspi4/SConstruct
deleted file mode 100644
index 93f349aab8..0000000000
--- a/bsp/raspberry-pi/raspi4/SConstruct
+++ /dev/null
@@ -1,30 +0,0 @@
-import os
-import sys
-import rtconfig
-
-from rtconfig import RTT_ROOT
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread.' + rtconfig.TARGET_EXT
-
-DefaultEnvironment(tools=[])
-env = Environment(tools = ['mingw'],
-    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
-    AR = rtconfig.AR, ARFLAGS = '-rc',
-    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-env['ASCOM'] = env['ASPPCOM']
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
-
-# make a building
-DoBuilding(TARGET, objs)
-
diff --git a/bsp/raspberry-pi/raspi4/applications/SConscript b/bsp/raspberry-pi/raspi4/applications/SConscript
deleted file mode 100644
index 533df8ac31..0000000000
--- a/bsp/raspberry-pi/raspi4/applications/SConscript
+++ /dev/null
@@ -1,9 +0,0 @@
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/raspberry-pi/raspi4/applications/main.c b/bsp/raspberry-pi/raspi4/applications/main.c
deleted file mode 100644
index 9664e67d01..0000000000
--- a/bsp/raspberry-pi/raspi4/applications/main.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#include <rtthread.h>
-#include <rtdevice.h>
-#include <board.h>
-
-int main(int argc, char** argv)
-{
-    rt_kprintf("Hi, this is RT-Thread!!\n");
-    return 0;
-}
diff --git a/bsp/raspberry-pi/raspi4/driver/Kconfig b/bsp/raspberry-pi/raspi4/driver/Kconfig
deleted file mode 100644
index 208b4b4300..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/Kconfig
+++ /dev/null
@@ -1,97 +0,0 @@
-
-config BSP_SUPPORT_FPU
-    bool "Using Float"
-    default n
-
-menu "Hardware Drivers Config"
-    menu "BCM Peripheral Drivers"
-        menuconfig BSP_USING_UART
-            bool "Using UART"
-            select RT_USING_SERIAL
-            default y
-
-            if BSP_USING_UART
-                config RT_USING_UART0
-                bool "Enabel UART 0"
-                default y
-            endif
-            
-        menuconfig BSP_USING_GIC
-            bool "Enable GIC"
-            select RT_USING_GIC
-            default y
-        if BSP_USING_GIC
-            config BSP_USING_GIC400
-                bool "Enable GIC400"
-                default y
-            config BSP_USING_GIC500
-                bool "Enable GIC500"
-                default n
-        endif
-
-        config BSP_USING_PIN
-            bool "Using PIN"
-            select RT_USING_PIN
-            default y
-
-        config BSP_USING_CORETIMER
-            bool "Using core timer"
-            select RT_USING_CORETIMER
-            default y
-
-        menuconfig BSP_USING_SYSTIMER
-            bool "Enable SYSTIMER"
-            select BSP_USING_SYSTIMER
-            default n
-
-        if  BSP_USING_SYSTIMER
-            config RT_USING_SYSTIMER1
-                bool "Enable sys timer1"
-                default n
-            config RT_USING_SYSTIMER3
-                bool "Enable sys timer3"
-                default n
-        endif
-
-        config BSP_USING_WDT
-            bool "Enable WDT"
-            select RT_USING_WDT
-            default n
-
-        menuconfig BSP_USING_RTC
-            bool "Enable RTC"
-            select RT_USING_RTC
-            default n
-
-        if BSP_USING_RTC
-            config BSP_USING_ALARM
-                bool "Enable Alarm"
-                select RT_USING_ALARM
-                default n
-        endif
-        
-        menuconfig BSP_USING_SDIO
-            bool "Enable SDIO"
-            select RT_USING_SDIO
-            default n
-
-        if BSP_USING_SDIO
-            config BSP_USING_SDIO0
-                bool "Enable SDIO0"
-                select RT_USING_SDIO
-                default n
-        endif
-    endmenu
-
-    menu "Board Peripheral Drivers"
-        menuconfig BSP_USING_HDMI
-            bool "Enable HDMI"
-            default n
-
-        if BSP_USING_HDMI
-            config BSP_USING_HDMI_DISPLAY
-                bool "HDMI DISPLAY"
-                default n
-        endif
-    endmenu
-endmenu
diff --git a/bsp/raspberry-pi/raspi4/driver/SConscript b/bsp/raspberry-pi/raspi4/driver/SConscript
deleted file mode 100644
index 533df8ac31..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/SConscript
+++ /dev/null
@@ -1,9 +0,0 @@
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/raspberry-pi/raspi4/driver/board.c b/bsp/raspberry-pi/raspi4/driver/board.c
deleted file mode 100644
index 79a24d184f..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/board.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#include "drv_uart.h"
-
-#include "cp15.h"
-#include "mmu.h"
-
-static rt_uint64_t timerStep;
-
-int rt_hw_get_gtimer_frq(void);
-void rt_hw_set_gtimer_val(rt_uint64_t value);
-int rt_hw_get_gtimer_val(void);
-int rt_hw_get_cntpct_val(void);
-void rt_hw_gtimer_enable(void);
-
-void core0_timer_enable_interrupt_controller(void)
-{
-    CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
-}
-
-void rt_hw_timer_isr(int vector, void *parameter)
-{
-    rt_hw_set_gtimer_val(timerStep);
-    rt_tick_increase();
-}
-
-void rt_hw_timer_init(void)
-{
-    rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
-    rt_hw_interrupt_umask(TIMER_IRQ);
-    __ISB();
-    timerStep = rt_hw_get_gtimer_frq();
-    __DSB();
-    timerStep /= RT_TICK_PER_SECOND;
-    
-    rt_hw_gtimer_enable();
-    rt_hw_set_gtimer_val(timerStep);
-    core0_timer_enable_interrupt_controller();
-}
-
-void idle_wfi(void)
-{
-    asm volatile ("wfi");
-}
-
-/**
- *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
- *  after interrupt disabled.
- */
-void rt_hw_board_init(void)
-{
-    mmu_init();
-    armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
-    armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio
-    armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer
-    mmu_enable();
-
-    /* initialize hardware interrupt */
-    rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
-    rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
-
-    /* initialize uart */
-    rt_hw_uart_init();      // driver/drv_uart.c
-#ifdef RT_USING_CONSOLE
-    /* set console device */
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif /* RT_USING_CONSOLE */
-
-#ifdef RT_USING_HEAP
-    /* initialize memory system */
-    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-#endif
-        /* initialize timer for os tick */
-    rt_hw_timer_init();
-    rt_thread_idle_sethook(idle_wfi);
-
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
-#endif
-}
diff --git a/bsp/raspberry-pi/raspi4/driver/board.h b/bsp/raspberry-pi/raspi4/driver/board.h
deleted file mode 100644
index a7c96b3276..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/board.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#ifndef BOARD_H__
-#define BOARD_H__
-
-#include <stdint.h>
-#include "iomap.h"
-
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-
-#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
-#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
-
-void rt_hw_board_init(void);
-
-#endif
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4/driver/drv_gpio.c
deleted file mode 100644
index 4317a358e0..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/drv_gpio.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#include "drv_gpio.h"
-
-#ifdef BSP_USING_PIN
-
-static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
-{
-    uint32_t fselnum = pin / 10;
-    uint32_t fselrest = pin % 10;
-
-    uint32_t gpfsel = 0;
-    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
-    gpfsel |= (uint32_t)(mode << (fselrest * 3));
-
-    switch (fselnum)
-    {
-    case 0:
-        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
-        break;
-    case 1:
-        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
-        break;
-    case 2:
-        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
-        break;
-    case 3:
-        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
-        break;
-    case 4:
-        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
-        break;
-    case 5:
-        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
-        break;
-    default:
-        break;
-    }
-}
-
-static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
-{
-    uint32_t num = pin / 32;
-
-    if(num == 0)
-    {
-        if(value == 0)
-        {
-            GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
-        }
-        else
-        {
-            GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
-        }
-    }
-    else
-    {
-        if(value == 0)
-        {
-            GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
-        }
-        else
-        {
-            GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
-        }
-        
-    }
-}
-
-static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
-{
-    return 0;
-}
-
-static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
-{
-    return RT_EOK;
-}
-
-static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
-{
-    return RT_EOK;
-}
-
-rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
-{
-    return RT_EOK;
-}
-
-static const struct rt_pin_ops ops =
-{
-    raspi_pin_mode,
-    raspi_pin_write,
-    raspi_pin_read,
-    raspi_pin_attach_irq,
-    raspi_pin_detach_irq,
-    raspi_pin_irq_enable,
-};
-#endif
-
-int rt_hw_gpio_init(void)
-{
-#ifdef BSP_USING_PIN
-    rt_device_pin_register("gpio", &ops, RT_NULL);
-#endif
-
-    return 0;
-}
-INIT_DEVICE_EXPORT(rt_hw_gpio_init);
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h
deleted file mode 100644
index c4658fcebb..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/drv_gpio.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#ifndef __DRV_GPIO_H__
-#define __DRV_GPIO_H__
-
-#include <rtthread.h>
-#include <rtdevice.h>
-
-#include "board.h"
-#include "interrupt.h"
-
-#define GPIO_REG_GPFSEL0(BASE)             HWREG32(BASE + 0x00)
-#define GPIO_REG_GPFSEL1(BASE)             HWREG32(BASE + 0x04)
-#define GPIO_REG_GPFSEL2(BASE)             HWREG32(BASE + 0x08)
-#define GPIO_REG_GPFSEL3(BASE)             HWREG32(BASE + 0x0C)
-#define GPIO_REG_GPFSEL4(BASE)             HWREG32(BASE + 0x10)
-#define GPIO_REG_GPFSEL5(BASE)             HWREG32(BASE + 0x14)
-#define GPIO_REG_REV0(BASE)                HWREG32(BASE + 0x18)
-#define GPIO_REG_GPSET0(BASE)              HWREG32(BASE + 0x1C)
-#define GPIO_REG_GPSET1(BASE)              HWREG32(BASE + 0x20)
-#define GPIO_REG_REV1(BASE)                HWREG32(BASE + 0x24)
-#define GPIO_REG_GPCLR0(BASE)              HWREG32(BASE + 0x28)
-#define GPIO_REG_GPCLR1(BASE)              HWREG32(BASE + 0x2C)
-#define GPIO_REG_REV2(BASE)                HWREG32(BASE + 0x30)
-#define GPIO_REG_GPLEV0(BASE)              HWREG32(BASE + 0x34)
-#define GPIO_REG_GPLEV1(BASE)              HWREG32(BASE + 0x38)
-#define GPIO_REG_REV3(BASE)                HWREG32(BASE + 0x3C)
-#define GPIO_REG_GPEDS0(BASE)              HWREG32(BASE + 0x40)
-#define GPIO_REG_GPEDS1(BASE)              HWREG32(BASE + 0x44)
-#define GPIO_REG_REV4(BASE)                HWREG32(BASE + 0x48)
-#define GPIO_REG_GPREN0(BASE)              HWREG32(BASE + 0x4C)
-#define GPIO_REG_GPREN1(BASE)              HWREG32(BASE + 0x50)
-#define GPIO_REG_REV5(BASE)                HWREG32(BASE + 0x54)
-#define GPIO_REG_GPFEN0(BASE)              HWREG32(BASE + 0x58)
-#define GPIO_REG_GPFEN1(BASE)              HWREG32(BASE + 0x5C)
-#define GPIO_REG_REV6(BASE)                HWREG32(BASE + 0x60)
-#define GPIO_REG_GPHEN0(BASE)              HWREG32(BASE + 0x64)
-#define GPIO_REG_GPHEN1(BASE)              HWREG32(BASE + 0x68)
-#define GPIO_REG_REV7(BASE)                HWREG32(BASE + 0x6C)
-#define GPIO_REG_GPLEN0(BASE)              HWREG32(BASE + 0x70)
-#define GPIO_REG_GPLEN1(BASE)              HWREG32(BASE + 0x74)
-#define GPIO_REG_REV8(BASE)                HWREG32(BASE + 0x78)
-#define GPIO_REG_GPAREN0(BASE)             HWREG32(BASE + 0x7C)
-#define GPIO_REG_GPAREN1(BASE)             HWREG32(BASE + 0x80)
-#define GPIO_REG_REV11(BASE)               HWREG32(BASE + 0x84)
-#define GPIO_REG_GPAFEN0(BASE)             HWREG32(BASE + 0x88)
-#define GPIO_REG_GPAFEN1(BASE)             HWREG32(BASE + 0x8C)
-#define GPIO_REG_REV10(BASE)               HWREG32(BASE + 0x90)
-#define GPIO_REG_GPPUD(BASE)               HWREG32(BASE + 0x94)
-#define GPIO_REG_GPPUDCLK0(BASE)           HWREG32(BASE + 0x98)
-#define GPIO_REG_GPPUDCLK1(BASE)           HWREG32(BASE + 0x9C)
-#define GPIO_REG_REV9(BASE)                HWREG32(BASE + 0xA0)
-#define GPIO_REG_TEST(BASE)                HWREG32(BASE + 0xA4)
-
-typedef enum {
-    INPUT = 0b000,
-    OUTPUT = 0b001,
-    ALT0 = 0b100,
-    ALT1 = 0b101,
-    ALT2 = 0b110,
-    ALT3 = 0b111,
-    ALT4 = 0b011,
-    ALT5 = 0b010
-} GPIO_FUNC;
-
-
-int rt_hw_gpio_init(void);
-
-#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.c b/bsp/raspberry-pi/raspi4/driver/drv_uart.c
deleted file mode 100644
index 6a70cdfb3a..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/drv_uart.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <rtdevice.h>
-
-#include "board.h"
-#include "drv_uart.h"
-#include "drv_gpio.h"
-
-struct hw_uart_device
-{
-    rt_ubase_t hw_base;
-    rt_uint32_t irqno;
-};
-
-static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    struct hw_uart_device *uart;
-    uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16;
-    uint32_t ibrd = bauddiv / 1000;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct hw_uart_device *)serial->parent.user_data;
-    if(uart->hw_base == PL011_BASE)
-    {
-        uint32_t gpfsel = 0;
-
-        gpfsel &= ~((uint32_t)(0x07 << (4 * 3)));
-        gpfsel |= (uint32_t)(ALT0 << (4 * 3));
-        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
-
-        gpfsel &= ~((uint32_t)(0x07 << (5 * 3)));
-        gpfsel |= (uint32_t)(ALT0 << (5 * 3));
-        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
-
-        PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
-        PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
-        PL011_REG_IBRD(uart->hw_base) = ibrd;
-        PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
-        PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
-        PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
-    }
-
-    return RT_EOK;
-}
-
-static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    struct hw_uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct hw_uart_device *)serial->parent.user_data;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT:
-        /* disable rx irq */
-        PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM);
-        rt_hw_interrupt_mask(uart->irqno);
-        break;
-
-    case RT_DEVICE_CTRL_SET_INT:
-        /* enable rx irq */
-        PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
-        rt_hw_interrupt_umask(uart->irqno);
-        break;
-    }
-
-    return RT_EOK;
-}
-
-static int uart_putc(struct rt_serial_device *serial, char c)
-{
-    struct hw_uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct hw_uart_device *)serial->parent.user_data;
-
-    while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
-    PL011_REG_DR(uart->hw_base) = (uint8_t)c;
-
-    return 1;
-}
-
-static int uart_getc(struct rt_serial_device *serial)
-{
-    int ch = -1;
-    struct hw_uart_device *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct hw_uart_device *)serial->parent.user_data;
-
-    if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
-    {
-        ch = PL011_REG_DR(uart->hw_base) & 0xff;
-    }
-
-    return ch;
-}
-
-static const struct rt_uart_ops _uart_ops =
-{
-    uart_configure,
-    uart_control,
-    uart_putc,
-    uart_getc,
-};
-
-static void rt_hw_uart_isr(int irqno, void *param)
-{
-    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
-    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-    PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
-}
-
-
-/* UART device driver structure */
-static struct hw_uart_device _uart0_device =
-{
-    PL011_BASE,
-    IRQ_PL011,
-};
-
-static struct rt_serial_device _serial0;
-
-int rt_hw_uart_init(void)
-{
-    struct hw_uart_device *uart;
-    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
-
-    uart = &_uart0_device;
-
-    _serial0.ops    = &_uart_ops;
-    _serial0.config = config;
-
-    /* register UART1 device */
-    rt_hw_serial_register(&_serial0, "uart",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-                          uart);
-    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart");
-
-    return 0;
-}
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.h b/bsp/raspberry-pi/raspi4/driver/drv_uart.h
deleted file mode 100644
index 714043efd3..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/drv_uart.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#ifndef DRV_UART_H__
-#define DRV_UART_H__
-
-// register's bit
-#define PL011_FR_RI          (1 << 8)
-#define PL011_FR_TXFE        (1 << 7)
-#define PL011_FR_RXFF        (1 << 6)
-#define PL011_FR_TXFF        (1 << 5)
-#define PL011_FR_RXFE        (1 << 4)
-#define PL011_FR_BUSY        (1 << 3)
-#define PL011_FR_DCD         (1 << 2)
-#define PL011_FR_DSR         (1 << 1)
-#define PL011_FR_CTS         (1 << 0)
-
-#define PL011_LCRH_SPS       (1 << 7)
-#define PL011_LCRH_WLEN_8    (3 << 5)
-#define PL011_LCRH_WLEN_7    (2 << 5)
-#define PL011_LCRH_WLEN_6    (1 << 5)
-#define PL011_LCRH_WLEN_5    (0 << 5)
-#define PL011_LCRH_FEN       (1 << 4)
-#define PL011_LCRH_STP2      (1 << 3)
-#define PL011_LCRH_EPS       (1 << 2)
-#define PL011_LCRH_PEN       (1 << 1)
-#define PL011_LCRH_BRK       (1 << 0)
-
-#define PL011_CR_CTSEN       (1 << 15)
-#define PL011_CR_RTSEN       (1 << 14)
-#define PL011_CR_RTS         (1 << 11)
-#define PL011_CR_DTR         (1 << 10)
-#define PL011_CR_RXE         (1 << 9)
-#define PL011_CR_TXE         (1 << 8)
-#define PL011_CR_LBE         (1 << 7)
-#define PL011_CR_SIRLP       (1 << 2)
-#define PL011_CR_SIREN       (1 << 1)
-#define PL011_CR_UARTEN      (1 << 0)
-
-#define PL011_IMSC_TXIM      (1 << 5)
-#define PL011_IMSC_RXIM      (1 << 4)
-
-#define PL011_INTERRUPT_OVERRUN_ERROR   (1 << 10)
-#define PL011_INTERRUPT_BREAK_ERROR     (1 << 9)
-#define PL011_INTERRUPT_PARITY_ERROR    (1 << 8)
-#define PL011_INTERRUPT_FRAMING_ERROR   (1 << 7)
-#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
-#define PL011_INTERRUPT_TRANSMIT        (1 << 5)
-#define PL011_INTERRUPT_RECEIVE         (1 << 4)
-#define PL011_INTERRUPT_nUARTCTS        (1 << 1)
-
-#define PL011_REG_DR(BASE)              HWREG32(BASE + 0x00)
-#define PL011_REG_RSRECR(BASE)          HWREG32(BASE + 0x04)
-#define PL011_REG_RESERVED0(BASE)       HWREG32(BASE + 0x08)
-#define PL011_REG_FR(BASE)              HWREG32(BASE + 0x18)
-#define PL011_REG_RESERVED1(BASE)       HWREG32(BASE + 0x1C)
-#define PL011_REG_ILPR(BASE)            HWREG32(BASE + 0x20)
-#define PL011_REG_IBRD(BASE)            HWREG32(BASE + 0x24)
-#define PL011_REG_FBRD(BASE)            HWREG32(BASE + 0x28)
-#define PL011_REG_LCRH(BASE)            HWREG32(BASE + 0x2C)
-#define PL011_REG_CR(BASE)              HWREG32(BASE + 0x30)
-#define PL011_REG_IFLS(BASE)            HWREG32(BASE + 0x34)
-#define PL011_REG_IMSC(BASE)            HWREG32(BASE + 0x38)
-#define PL011_REG_RIS(BASE)             HWREG32(BASE + 0x3C)
-#define PL011_REG_MIS(BASE)             HWREG32(BASE + 0x40)
-#define PL011_REG_ICR(BASE)             HWREG32(BASE + 0x44)
-#define PL011_REG_DMACR(BASE)           HWREG32(BASE + 0x48)
-#define PL011_REG_RESERVED2(BASE)       HWREG32(BASE + 0x4C)
-#define PL011_REG_ITCR(BASE)            HWREG32(BASE + 0x80)
-#define PL011_REG_ITIP(BASE)            HWREG32(BASE + 0x84)
-#define PL011_REG_ITOP(BASE)            HWREG32(BASE + 0x88)
-#define PL011_REG_TDR(BASE)             HWREG32(BASE + 0x8C)
-
-int rt_hw_uart_init(void);
-
-#endif /* DRV_UART_H__ */
diff --git a/bsp/raspberry-pi/raspi4/driver/iomap.h b/bsp/raspberry-pi/raspi4/driver/iomap.h
deleted file mode 100644
index 3f18353904..0000000000
--- a/bsp/raspberry-pi/raspi4/driver/iomap.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __RASPI4_H__
-#define __RASPI4_H__
-
-//gpio
-#define GPIO_BASE (0xFE000000 + 0x00200000)
-
-//uart
-#define UART0_BASE                  (0xFE000000 + 0x00201000)
-#define PL011_BASE                  UART0_BASE
-#define IRQ_PL011                   (121 + 32)
-#define UART_REFERENCE_CLOCK        (48000000)
-
-// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
-#define CORE0_TIMER_IRQ_CTRL    HWREG32(0xFF800040)
-#define TIMER_IRQ               30
-#define NON_SECURE_TIMER_IRQ    (1 << 1)
-
-//gic max
-#define ARM_GIC_NR_IRQS             (512)
-#define INTC_BASE                   (0xff800000)
-#define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
-#define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
-#define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
-#define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
-
-#define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
-#define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
-
-#endif
diff --git a/bsp/raspberry-pi/raspi4/link.lds b/bsp/raspberry-pi/raspi4/link.lds
deleted file mode 100644
index b7b2dcc32c..0000000000
--- a/bsp/raspberry-pi/raspi4/link.lds
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * File      : link.lds
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * 2017-5-30     bernard       first version
- */
-
-/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
-
-SECTIONS
-{
-    . = 0x80000;
-    . = ALIGN(4096);
-    .text :
-    {
-        KEEP(*(.text.entrypoint))       /* The entry point */
-        *(.vectors)
-        *(.text)                        /* remaining code */
-        *(.text.*)                      /* remaining code */
-
-        *(.rodata)                      /* read-only data (constants) */
-        *(.rodata*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.gnu.linkonce.t*)
-
-        *(COMMON)
-        
-        /* section information for finsh shell */
-        . = ALIGN(16);
-        __fsymtab_start = .;
-        KEEP(*(FSymTab))
-        __fsymtab_end = .;
-        . = ALIGN(16);
-        __vsymtab_start = .;
-        KEEP(*(VSymTab))
-        __vsymtab_end = .;
-        . = ALIGN(16);
-
-        /* section information for initial. */
-        . = ALIGN(16);
-        __rt_init_start = .;
-        KEEP(*(SORT(.rti_fn*)))
-        __rt_init_end = .;
-        . = ALIGN(16);
-
-        . = ALIGN(16);
-        _etext = .;
-    }
-
-    .eh_frame_hdr :
-    {
-         *(.eh_frame_hdr)
-         *(.eh_frame_entry)
-    }
-    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
-
-    . = ALIGN(16);
-    .data :
-    {
-     *(.data)
-     *(.data.*)
-
-     *(.data1)
-     *(.data1.*)
-
-     . = ALIGN(16);
-     _gp = ABSOLUTE(.);     /* Base of small data */
-
-     *(.sdata)
-     *(.sdata.*)
-    }
-
-    . = ALIGN(16);
-    .ctors :
-    {
-        PROVIDE(__ctors_start__ = .);
-        KEEP(*(SORT(.ctors.*)))
-        KEEP(*(.ctors))
-        PROVIDE(__ctors_end__ = .);
-    }
-
-    .dtors :
-    {
-        PROVIDE(__dtors_start__ = .);
-        KEEP(*(SORT(.dtors.*)))
-        KEEP(*(.dtors))
-        PROVIDE(__dtors_end__ = .);
-    }
-
-    . = ALIGN(16);
-    .bss :
-    {
-        PROVIDE(__bss_start = .);
-        *(.bss)
-        *(.bss.*)
-        *(.dynbss)
-        
-        PROVIDE(__bss_end = .);
-    }
-    _end = .;
-
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-     * Symbols in the DWARF debugging sections are relative to the beginning
-     * of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-}
-
-__bss_size = (__bss_end - __bss_start)>>3;
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.h b/bsp/raspberry-pi/raspi4/rtconfig.h
deleted file mode 100644
index 049e117559..0000000000
--- a/bsp/raspberry-pi/raspi4/rtconfig.h
+++ /dev/null
@@ -1,179 +0,0 @@
-#ifndef RT_CONFIG_H__
-#define RT_CONFIG_H__
-
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Project Configuration */
-
-/* RT-Thread Kernel */
-
-#define RT_NAME_MAX 8
-#define RT_ALIGN_SIZE 4
-#define RT_THREAD_PRIORITY_32
-#define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 100
-#define RT_USING_OVERFLOW_CHECK
-#define RT_USING_HOOK
-#define RT_USING_IDLE_HOOK
-#define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 2048
-#define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 2048
-#define RT_DEBUG
-
-/* Inter-Thread communication */
-
-#define RT_USING_SEMAPHORE
-#define RT_USING_MUTEX
-#define RT_USING_EVENT
-#define RT_USING_MAILBOX
-#define RT_USING_MESSAGEQUEUE
-
-/* Memory Management */
-
-#define RT_USING_MEMPOOL
-#define RT_USING_SMALL_MEM
-#define RT_USING_HEAP
-
-/* Kernel Device Object */
-
-#define RT_USING_DEVICE
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart"
-#define RT_VER_NUM 0x40003
-#define ARCH_CPU_64BIT
-
-/* RT-Thread Components */
-
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
-
-/* C++ features */
-
-
-/* Command shell */
-
-#define RT_USING_FINSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
-#define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
-#define FINSH_ARG_MAX 10
-
-/* Device virtual file system */
-
-#define RT_USING_DFS
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
-#define DFS_FD_MAX 16
-#define RT_USING_DFS_DEVFS
-
-/* Device Drivers */
-
-#define RT_USING_DEVICE_IPC
-#define RT_PIPE_BUFSZ 512
-#define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_PIN
-
-/* Using USB */
-
-
-/* POSIX layer and C standard library */
-
-#define RT_USING_LIBC
-#define RT_USING_POSIX
-
-/* Network */
-
-/* Socket abstraction layer */
-
-
-/* Network interface device */
-
-
-/* light weight TCP/IP stack */
-
-
-/* AT commands */
-
-
-/* VBUS(Virtual Software BUS) */
-
-
-/* Utilities */
-
-
-/* RT-Thread online packages */
-
-/* IoT - internet of things */
-
-
-/* Wi-Fi */
-
-/* Marvell WiFi */
-
-
-/* Wiced WiFi */
-
-
-/* IoT Cloud */
-
-
-/* security packages */
-
-
-/* language packages */
-
-
-/* multimedia packages */
-
-
-/* tools packages */
-
-
-/* system packages */
-
-
-/* peripheral libraries and drivers */
-
-
-/* miscellaneous packages */
-
-
-/* samples: kernel and components samples */
-
-
-/* Privated Packages of RealThread */
-
-
-/* Network Utilities */
-
-#define BCM2711_SOC
-
-/* Hardware Drivers Config */
-
-/* BCM Peripheral Drivers */
-
-#define BSP_USING_UART
-#define RT_USING_UART0
-#define BSP_USING_GIC
-#define BSP_USING_GIC400
-#define BSP_USING_PIN
-#define BSP_USING_CORETIMER
-
-/* Board Peripheral Drivers */
-
-
-#endif
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py
deleted file mode 100644
index a1dd168d3d..0000000000
--- a/bsp/raspberry-pi/raspi4/rtconfig.py
+++ /dev/null
@@ -1,51 +0,0 @@
-import os
-
-# toolchains options
-ARCH        ='aarch64'
-CPU         ='cortex-a72'
-CROSS_TOOL  ='gcc'
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = r'../../..'
-
-if os.getenv('RTT_CC'):
-    CROSS_TOOL = os.getenv('RTT_CC')
-
-PLATFORM    = 'gcc'
-EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
-
-BUILD = 'debug'
-
-if PLATFORM == 'gcc':
-    # toolchains
-    # PREFIX = 'arm-none-eabi-'
-    PREFIX = 'aarch64-elf-'
-    CC      = PREFIX + 'gcc'
-    CXX     = PREFIX + 'g++'
-    AS      = PREFIX + 'gcc'
-    AR      = PREFIX + 'ar'
-    LINK    = PREFIX + 'gcc'
-    TARGET_EXT = 'elf'
-    SIZE    = PREFIX + 'size'
-    OBJDUMP = PREFIX + 'objdump'
-    OBJCPY  = PREFIX + 'objcopy'
-
-    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
-    CFLAGS = DEVICE + ' -Wall'
-    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
-    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
-    CPATH   = ''
-    LPATH   = ''
-
-    if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
-    else:
-        CFLAGS += ' -O2'
-
-    CXXFLAGS = CFLAGS
-
-DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/libcpu/Kconfig b/libcpu/Kconfig
index 95d3dd5228..e355664de2 100644
--- a/libcpu/Kconfig
+++ b/libcpu/Kconfig
@@ -74,6 +74,9 @@ config ARCH_ARM_CORTEX_A9
     bool
     select ARCH_ARM_CORTEX_A
 
+config ARCH_ARMV8
+    bool
+
 config ARCH_MIPS
     bool
 
diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c
index 4d003a9dcd..1f4d868636 100644
--- a/libcpu/aarch64/common/gic/gic_pl400.c
+++ b/libcpu/aarch64/common/gic/gic_pl400.c
@@ -14,7 +14,6 @@
 
 #include "gic_pl400.h"
 #include "cp15.h"
-#include "iomap.h"
 
 #define ARM_GIC_MAX_NR 1
 struct arm_gic
diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c
index 6fec968dc2..3b689dceb3 100644
--- a/libcpu/aarch64/cortex-a72/interrupt.c
+++ b/libcpu/aarch64/cortex-a72/interrupt.c
@@ -13,7 +13,6 @@
 #include <gic_pl400.h>
 #include <board.h>
 #include <armv8.h>
-#include "iomap.h"
 
 #define MAX_HANDLERS                256
 #define GIC_ACK_INTID_MASK          0x000003ff
-- 
cgit v1.3.1


From c3d63e49decf74896fbf3696f181c601ee32f6f0 Mon Sep 17 00:00:00 2001
From: aozima <wuyangyong@gmail.com>
Date: Sat, 30 May 2020 15:23:25 +0800
Subject: set Systick interrupt priority to the lowest

---
 libcpu/arm/cortex-m0/context_gcc.S   | 4 ++--
 libcpu/arm/cortex-m0/context_iar.S   | 4 ++--
 libcpu/arm/cortex-m0/context_rvds.S  | 4 ++--
 libcpu/arm/cortex-m23/context_gcc.S  | 4 ++--
 libcpu/arm/cortex-m23/context_iar.S  | 4 ++--
 libcpu/arm/cortex-m23/context_rvds.S | 4 ++--
 libcpu/arm/cortex-m3/context_gcc.S   | 4 ++--
 libcpu/arm/cortex-m3/context_iar.S   | 4 ++--
 libcpu/arm/cortex-m3/context_rvds.S  | 4 ++--
 libcpu/arm/cortex-m33/context_gcc.S  | 4 ++--
 libcpu/arm/cortex-m33/context_iar.S  | 4 ++--
 libcpu/arm/cortex-m33/context_rvds.S | 4 ++--
 libcpu/arm/cortex-m4/context_gcc.S   | 4 ++--
 libcpu/arm/cortex-m4/context_iar.S   | 4 ++--
 libcpu/arm/cortex-m4/context_rvds.S  | 4 ++--
 libcpu/arm/cortex-m7/context_gcc.S   | 4 ++--
 libcpu/arm/cortex-m7/context_iar.S   | 4 ++--
 libcpu/arm/cortex-m7/context_rvds.S  | 4 ++--
 18 files changed, 36 insertions(+), 36 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S
index d9993247e2..a504ee076e 100644
--- a/libcpu/arm/cortex-m0/context_gcc.S
+++ b/libcpu/arm/cortex-m0/context_gcc.S
@@ -22,7 +22,7 @@
 	.equ 	SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
 	.equ 	NVIC_INT_CTRL, 0xE000ED04       /* interrupt control state register */
 	.equ 	NVIC_SHPR3, 0xE000ED20          /* system priority register (3) */
-	.equ 	NVIC_PENDSV_PRI, 0x00FF0000     /* PendSV priority value (lowest) */
+	.equ 	NVIC_PENDSV_PRI, 0xFFFF0000     /* PendSV and SysTick priority value (lowest) */
 	.equ 	NVIC_PENDSVSET, 0x10000000      /* value to trigger PendSV exception */
 
 /*
@@ -159,7 +159,7 @@ rt_hw_context_switch_to:
     MOVS    R0, #1
     STR     R0, [R1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR     R0, =NVIC_SHPR3
     LDR     R1, =NVIC_PENDSV_PRI
     LDR     R2, [R0,#0x00]       /* read */
diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S
index 50d3781359..6f410d1a24 100644
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -163,7 +163,7 @@ rt_hw_context_switch_to:
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S
index fb9ce9b4bf..072486587c 100644
--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -168,7 +168,7 @@ rt_hw_context_switch_to    PROC
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S
index 4fc5a3adbd..067348181d 100644
--- a/libcpu/arm/cortex-m23/context_gcc.S
+++ b/libcpu/arm/cortex-m23/context_gcc.S
@@ -23,7 +23,7 @@
 	.equ 	SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
 	.equ 	NVIC_INT_CTRL, 0xE000ED04       /* interrupt control state register */
 	.equ 	NVIC_SHPR3, 0xE000ED20          /* system priority register (3) */
-	.equ 	NVIC_PENDSV_PRI, 0x00FF0000     /* PendSV priority value (lowest) */
+	.equ 	NVIC_PENDSV_PRI, 0xFFFF0000     /* PendSV and SysTick priority value (lowest) */
 	.equ 	NVIC_PENDSVSET, 0x10000000      /* value to trigger PendSV exception */
 
 /*
@@ -160,7 +160,7 @@ rt_hw_context_switch_to:
     MOVS    R0, #1
     STR     R0, [R1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR     R0, =NVIC_SHPR3
     LDR     R1, =NVIC_PENDSV_PRI
     LDR     R2, [R0,#0x00]       /* read */
diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S
index 4f30c0bc0c..4d50d0fdec 100644
--- a/libcpu/arm/cortex-m23/context_iar.S
+++ b/libcpu/arm/cortex-m23/context_iar.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -164,7 +164,7 @@ rt_hw_context_switch_to:
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S
index f243097cc6..4486ceaf08 100644
--- a/libcpu/arm/cortex-m23/context_rvds.S
+++ b/libcpu/arm/cortex-m23/context_rvds.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -169,7 +169,7 @@ rt_hw_context_switch_to    PROC
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S
index d17a8aa12c..2878d20082 100644
--- a/libcpu/arm/cortex-m3/context_gcc.S
+++ b/libcpu/arm/cortex-m3/context_gcc.S
@@ -24,7 +24,7 @@
     .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
     
     .equ    SHPR3, 0xE000ED20               /* system priority register (3) */
-    .equ    PENDSV_PRI_LOWEST, 0x00FF0000   /* PendSV priority value (lowest) */
+    .equ    PENDSV_PRI_LOWEST, 0xFFFF0000   /* PendSV and SysTick priority value (lowest) */
 
 /*
  * rt_base_t rt_hw_interrupt_disable();
@@ -140,7 +140,7 @@ rt_hw_context_switch_to:
     MOV     R0, #1
     STR     R0, [R1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR     R0, =SHPR3
     LDR     R1, =PENDSV_PRI_LOWEST
     LDR.W   R2, [R0,#0]             /* read */
diff --git a/libcpu/arm/cortex-m3/context_iar.S b/libcpu/arm/cortex-m3/context_iar.S
index 91645c48b3..7c0e69bf59 100644
--- a/libcpu/arm/cortex-m3/context_iar.S
+++ b/libcpu/arm/cortex-m3/context_iar.S
@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -139,7 +139,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S
index a2a7f41a27..a661430499 100644
--- a/libcpu/arm/cortex-m3/context_rvds.S
+++ b/libcpu/arm/cortex-m3/context_rvds.S
@@ -18,7 +18,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -145,7 +145,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S
index 18e97c631e..27596bf787 100644
--- a/libcpu/arm/cortex-m33/context_gcc.S
+++ b/libcpu/arm/cortex-m33/context_gcc.S
@@ -25,7 +25,7 @@
 .equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
-.equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
 .equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
 
 /*
@@ -225,7 +225,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR r0, =NVIC_SYSPRI2
     LDR r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       /* read       */
diff --git a/libcpu/arm/cortex-m33/context_iar.S b/libcpu/arm/cortex-m33/context_iar.S
index 4a32c5bcef..67cf2727a2 100644
--- a/libcpu/arm/cortex-m33/context_iar.S
+++ b/libcpu/arm/cortex-m33/context_iar.S
@@ -21,7 +21,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -231,7 +231,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m33/context_rvds.S b/libcpu/arm/cortex-m33/context_rvds.S
index 7ca43933f2..dc22ead7c5 100644
--- a/libcpu/arm/cortex-m33/context_rvds.S
+++ b/libcpu/arm/cortex-m33/context_rvds.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -232,7 +232,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S
index 420f4f8ae3..f569a35863 100644
--- a/libcpu/arm/cortex-m4/context_gcc.S
+++ b/libcpu/arm/cortex-m4/context_gcc.S
@@ -25,7 +25,7 @@
 .equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
-.equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
 .equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
 
 /*
@@ -182,7 +182,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR r0, =NVIC_SYSPRI2
     LDR r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       /* read       */
diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S
index 06b8c7f884..18d6a3f784 100644
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@@ -21,7 +21,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -186,7 +186,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S
index f6d2447c5e..3f948bc349 100644
--- a/libcpu/arm/cortex-m4/context_rvds.S
+++ b/libcpu/arm/cortex-m4/context_rvds.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -186,7 +186,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m7/context_gcc.S b/libcpu/arm/cortex-m7/context_gcc.S
index 420f4f8ae3..f569a35863 100644
--- a/libcpu/arm/cortex-m7/context_gcc.S
+++ b/libcpu/arm/cortex-m7/context_gcc.S
@@ -25,7 +25,7 @@
 .equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
-.equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
 .equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
 
 /*
@@ -182,7 +182,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR r0, =NVIC_SYSPRI2
     LDR r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       /* read       */
diff --git a/libcpu/arm/cortex-m7/context_iar.S b/libcpu/arm/cortex-m7/context_iar.S
index 06b8c7f884..18d6a3f784 100644
--- a/libcpu/arm/cortex-m7/context_iar.S
+++ b/libcpu/arm/cortex-m7/context_iar.S
@@ -21,7 +21,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -186,7 +186,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
diff --git a/libcpu/arm/cortex-m7/context_rvds.S b/libcpu/arm/cortex-m7/context_rvds.S
index ea9e9cb8b3..d051f819c1 100644
--- a/libcpu/arm/cortex-m7/context_rvds.S
+++ b/libcpu/arm/cortex-m7/context_rvds.S
@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -186,7 +186,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read
-- 
cgit v1.3.1


From 92ab0fd59347d2f484e33c34802f88b4d4d71b80 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 4 Jun 2020 00:03:07 +0800
Subject: fix startup code address relative jump

---
 libcpu/arm/cortex-a/start_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index a8f3a36630..2e99db7218 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -62,7 +62,7 @@ _reset:
     b continue
 
 overHyped: /* Get out of HYP mode */
-    ldr r1, =continue
+    adr r1, continue
     msr ELR_hyp, r1
     mrs r1, cpsr_all
     and r1, r1, #0x1f    ;@ CPSR_MODE_MASK
-- 
cgit v1.3.1


From 62b2038fe6772a0021ee684947542a7649517593 Mon Sep 17 00:00:00 2001
From: David Lin <linpeng1577@gmail.com>
Date: Wed, 10 Jun 2020 10:15:06 +0800
Subject:  [libcpu]Fixed the wrong notes in context_iar.S

swith -> switch
---
 libcpu/rx/context_iar.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/rx/context_iar.S b/libcpu/rx/context_iar.S
index db02ce4d1f..97c630e797 100644
--- a/libcpu/rx/context_iar.S
+++ b/libcpu/rx/context_iar.S
@@ -28,8 +28,8 @@ _rt_hw_interrupt_enable:
      MVTIPL     #KERNEL_INTERRUPT_PRIORITY
      RTS
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
 ___interrupt_27:
 
-- 
cgit v1.3.1


From d2eaa452d652c205aef16ee7385cb1a5d188c942 Mon Sep 17 00:00:00 2001
From: xieyangrun <xieyangrun@smartcomma.com>
Date: Thu, 18 Jun 2020 09:18:48 +0800
Subject: [libcpu/arm/*/cpuport.c]fixed __rt_ffs bug on account of armclang
 LTO.

---
 libcpu/arm/cortex-m3/cpuport.c  | 4 ++--
 libcpu/arm/cortex-m33/cpuport.c | 4 ++--
 libcpu/arm/cortex-m4/cpuport.c  | 4 ++--
 libcpu/arm/cortex-m7/cpuport.c  | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c
index d17d4fdf2e..d58782e2c5 100644
--- a/libcpu/arm/cortex-m3/cpuport.c
+++ b/libcpu/arm/cortex-m3/cpuport.c
@@ -388,13 +388,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c
index 415f560911..a589ba3462 100644
--- a/libcpu/arm/cortex-m33/cpuport.c
+++ b/libcpu/arm/cortex-m33/cpuport.c
@@ -475,13 +475,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
         "BX      lr                   \n"
 
         : "=r"(value)
diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c
index f556ba0c26..dc8a9aab59 100644
--- a/libcpu/arm/cortex-m4/cpuport.c
+++ b/libcpu/arm/cortex-m4/cpuport.c
@@ -472,13 +472,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c
index c22242f140..e701a52307 100644
--- a/libcpu/arm/cortex-m7/cpuport.c
+++ b/libcpu/arm/cortex-m7/cpuport.c
@@ -472,13 +472,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
-- 
cgit v1.3.1


From 1f2a7b564cca0610b246db11a035504ce9d9d1c7 Mon Sep 17 00:00:00 2001
From: xuzhuoyi <xzy476386434@vip.qq.com>
Date: Thu, 18 Jun 2020 10:53:34 +0800
Subject: [libcpu][arm][cortex-m23] Change exception return call address to
 0xFFFFFFFD

---
 libcpu/arm/cortex-m23/context_gcc.S  | 2 +-
 libcpu/arm/cortex-m23/context_iar.S  | 2 +-
 libcpu/arm/cortex-m23/context_rvds.S | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S
index 067348181d..48f90413d9 100644
--- a/libcpu/arm/cortex-m23/context_gcc.S
+++ b/libcpu/arm/cortex-m23/context_gcc.S
@@ -137,7 +137,7 @@ pendsv_exit:
     /* restore interrupt */
     MSR     PRIMASK, R2
 
-    MOVS    R0, #0x04
+    MOVS    R0, #0x03
     RSBS    R0, R0, #0x00
     BX      R0
 /*
diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S
index 4d50d0fdec..c7d85cc5e2 100644
--- a/libcpu/arm/cortex-m23/context_iar.S
+++ b/libcpu/arm/cortex-m23/context_iar.S
@@ -139,7 +139,7 @@ pendsv_exit
     ; restore interrupt
     MSR     PRIMASK, r2
 
-    MOVS    r0, #0x04
+    MOVS    r0, #0x03
     RSBS    r0, r0, #0x00
     BX      r0
 
diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S
index 4486ceaf08..ca381d0f8f 100644
--- a/libcpu/arm/cortex-m23/context_rvds.S
+++ b/libcpu/arm/cortex-m23/context_rvds.S
@@ -143,7 +143,7 @@ pendsv_exit
     ; restore interrupt
     MSR     PRIMASK, r2
 
-    MOVS    r0, #0x04
+    MOVS    r0, #0x03
     RSBS    r0, r0, #0x00
     BX      r0
     ENDP
-- 
cgit v1.3.1


From 1ec681a55121b9b1d5fcdb274a3c3d10d408a960 Mon Sep 17 00:00:00 2001
From: bigamgic <zhaofujin@rt-thread.com>
Date: Sun, 21 Jun 2020 23:25:32 +0800
Subject: fix ls2k libc and irq

---
 bsp/ls2kdev/drivers/drv_gpio.c  | 147 +++++++++++++++++++++++++++++----
 bsp/ls2kdev/drivers/drv_gpio.h  |  20 +++++
 bsp/ls2kdev/drivers/drv_uart.c  |  24 +++---
 bsp/ls2kdev/drivers/drv_uart.h  |   2 +-
 bsp/ls2kdev/drivers/interrupt.c | 178 ++++++++++++++++++++++++++++++++++++----
 bsp/ls2kdev/drivers/interrupt.h |  85 +++++++++++++++++++
 bsp/ls2kdev/drivers/ls2k1000.h  |  13 ++-
 libcpu/mips/common/exception.c  |  39 +++++----
 8 files changed, 449 insertions(+), 59 deletions(-)
 create mode 100644 bsp/ls2kdev/drivers/interrupt.h

(limited to 'libcpu')

diff --git a/bsp/ls2kdev/drivers/drv_gpio.c b/bsp/ls2kdev/drivers/drv_gpio.c
index bcbecd9e2c..e1c5d61331 100644
--- a/bsp/ls2kdev/drivers/drv_gpio.c
+++ b/bsp/ls2kdev/drivers/drv_gpio.c
@@ -8,25 +8,14 @@
  * 2017-10-20      ZYH          add mode open drain and input pull down
  * 2020-06-01     Du Huanpeng   GPIO driver based on <components/drivers/include/drivers/pin.h>
  */
-
-
 #include <rtthread.h>
 #include <drivers/pin.h>
-#include <rthw.h>
 #include <ls2k1000.h>
-
-struct loongson_gpio {
-    rt_uint64_t GPIO0_OEN;
-    rt_uint64_t GPIO1_OEN;    /* Reserved */
-    rt_uint64_t GPIO0_O;
-    rt_uint64_t GPIO1_O;      /* Reserved */
-    rt_uint64_t GPIO0_I;
-    rt_uint64_t GPIO1_I;      /* Reserved */
-    rt_uint64_t GPIO0_INTEN;
-    rt_uint64_t GPIO1_INTEN;  /* Reserved */
-};
+#include "drv_gpio.h"
 
 #ifdef RT_USING_PIN
+#define     GPIO_IRQ_NUM                    (64)
+static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM];
 
 static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
 {
@@ -92,13 +81,36 @@ static int loongson_pin_read(struct rt_device *device, rt_base_t pin)
     return rc;
 }
 
-    /* TODO: add GPIO interrupt */
+/* TODO: add GPIO interrupt */
 static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
 {
+    rt_uint8_t index;
+    rt_uint64_t m;
     struct loongson_gpio *gpio;
 
     gpio = (void *)device->user_data;
 
+    if(pin < 4)
+    {
+        index = pin;
+    }
+    else if(pin < 32)
+    {
+        index = 5;
+    }
+    else
+    {
+        index = 6;
+    }
+    
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = hdr;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = args;
+    _g_gpio_irq_tbl[index].irq_type[pin]  = mode;
+
+    liointc_set_irq_mode(index, mode);
+    m = (rt_uint64_t)1 << pin;
+    gpio->GPIO0_INTEN |= m;
+
     return RT_EOK;
 }
 static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
@@ -107,6 +119,24 @@ static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_int32_t pin
 
     gpio = (void *)device->user_data;
 
+    rt_uint8_t index;
+    if(pin < 4)
+    {
+        index = pin;
+    }
+    else if(pin < 32)
+    {
+        index = 5;
+    }
+    else
+    {
+        index = 6;
+    }
+    _g_gpio_irq_tbl[index].irq_cb[pin]    = RT_NULL;
+    _g_gpio_irq_tbl[index].irq_arg[pin]   = RT_NULL;
+    _g_gpio_irq_tbl[index].irq_type[pin]  = RT_NULL;
+    _g_gpio_irq_tbl[index].state[pin]     = RT_NULL;
+
     return RT_EOK;
 }
 static rt_err_t loongson_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
@@ -115,9 +145,72 @@ static rt_err_t loongson_pin_irq_enable(struct rt_device *device, rt_base_t pin,
 
     gpio = (void *)device->user_data;
 
+    rt_uint8_t index;
+    if(pin < 4)
+    {
+        index = pin;
+    }
+    else if(pin < 32)
+    {
+        index = 5;
+    }
+    else
+    {
+        index = 6;
+    }
+
+    if (enabled)
+        _g_gpio_irq_tbl[index].state[pin] = 1;
+    else
+        _g_gpio_irq_tbl[index].state[pin] = 0;
     return RT_EOK;
 }
 
+static void gpio_irq_handler(int irq, void *param)
+{
+    struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param;
+    rt_uint32_t pin;
+    rt_uint32_t value;
+    rt_uint32_t tmpvalue;
+
+    if(irq == LS2K_GPIO0_INT_IRQ)
+    {
+        pin = 0;
+    }
+    else if(irq == LS2K_GPIO1_INT_IRQ)
+    {
+        pin = 1;
+    }
+    else if(irq == LS2K_GPIO2_INT_IRQ)
+    {
+        pin = 2;
+    }
+    else if(irq == LS2K_GPIO3_INT_IRQ)
+    {
+        pin = 3;
+    }
+    else if(irq == LS2K_GPIO_INTLO_IRQ)
+    {
+        pin = 4;
+    }
+    else
+    {
+        pin = 32;
+    }
+    
+    while (value)
+    {
+        if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL))
+        {
+            if(irq_def->state[pin])
+            {
+                irq_def->irq_cb[pin](irq_def->irq_arg[pin]);
+            }
+        }
+        pin++;
+        value = value >> 1;
+    }
+}
 
 static struct rt_pin_ops loongson_pin_ops = {
     .pin_mode  = loongson_pin_mode,
@@ -139,6 +232,30 @@ int loongson_pin_init(void)
     loongson_gpio_priv = (void *)GPIO_BASE;
     rc = rt_device_pin_register("pin", &loongson_pin_ops, loongson_gpio_priv);
 
+    //gpio0
+    rt_hw_interrupt_install(LS2K_GPIO0_INT_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq");
+    rt_hw_interrupt_umask(LS2K_GPIO0_INT_IRQ);
+
+    //gpio1
+    rt_hw_interrupt_install(LS2K_GPIO1_INT_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq");
+    rt_hw_interrupt_umask(LS2K_GPIO1_INT_IRQ);
+
+    //gpio2
+    rt_hw_interrupt_install(LS2K_GPIO2_INT_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq");
+    rt_hw_interrupt_umask(LS2K_GPIO2_INT_IRQ);
+
+    //gpio3
+    rt_hw_interrupt_install(LS2K_GPIO3_INT_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[3], "gpio3_irq");
+    rt_hw_interrupt_umask(LS2K_GPIO3_INT_IRQ);
+
+    //gpio4~gpio31
+    rt_hw_interrupt_install(LS2K_GPIO_INTLO_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[4], "gpio4_irq");
+    rt_hw_interrupt_umask(LS2K_GPIO_INTLO_IRQ);
+
+    //gpio32~gpio63
+    rt_hw_interrupt_install(LS2K_GPIO_INTHI_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[5], "gpio5_irq");
+    rt_hw_interrupt_umask(LS2K_GPIO_INTHI_IRQ);
+
     return rc;
 }
 INIT_BOARD_EXPORT(loongson_pin_init);
diff --git a/bsp/ls2kdev/drivers/drv_gpio.h b/bsp/ls2kdev/drivers/drv_gpio.h
index 6d505c1294..51a75c306e 100644
--- a/bsp/ls2kdev/drivers/drv_gpio.h
+++ b/bsp/ls2kdev/drivers/drv_gpio.h
@@ -13,6 +13,26 @@
 #ifndef __DRV_GPIO_H__
 #define __DRV_GPIO_H__
 
+#include <rthw.h>
+
+struct gpio_irq_def
+{
+    void  *irq_arg[32];
+    void (*irq_cb[32])(void *param);
+    rt_uint8_t irq_type[32];
+    rt_uint8_t state[32];
+};
+
+struct loongson_gpio {
+    rt_uint64_t GPIO0_OEN;
+    rt_uint64_t GPIO1_OEN;    /* Reserved */
+    rt_uint64_t GPIO0_O;
+    rt_uint64_t GPIO1_O;      /* Reserved */
+    rt_uint64_t GPIO0_I;
+    rt_uint64_t GPIO1_I;      /* Reserved */
+    rt_uint64_t GPIO0_INTEN;
+    rt_uint64_t GPIO1_INTEN;  /* Reserved */
+};
 
 int loongson_pin_init(void);
 
diff --git a/bsp/ls2kdev/drivers/drv_uart.c b/bsp/ls2kdev/drivers/drv_uart.c
index 428393dcc4..baed70b61f 100644
--- a/bsp/ls2kdev/drivers/drv_uart.c
+++ b/bsp/ls2kdev/drivers/drv_uart.c
@@ -28,7 +28,7 @@ struct rt_uart_ls2k
     rt_uint32_t IRQ;
 };
 
-static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
     struct rt_uart_ls2k *uart_dev = RT_NULL;
 
@@ -48,7 +48,7 @@ static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct s
     return RT_EOK;
 }
 
-static rt_err_t mipssim_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+static rt_err_t ls2k_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
     struct rt_uart_ls2k *uart_dev = RT_NULL;
 
@@ -88,7 +88,7 @@ static rt_bool_t uart_is_transmit_empty(struct rt_uart_ls2k *uart_dev)
     }
 }
 
-static int mipssim_uart_putc(struct rt_serial_device *serial, char c)
+static int ls2k_uart_putc(struct rt_serial_device *serial, char c)
 {
     struct rt_uart_ls2k *uart_dev = RT_NULL;
 
@@ -104,7 +104,7 @@ static int mipssim_uart_putc(struct rt_serial_device *serial, char c)
     return 1;
 }
 
-static int mipssim_uart_getc(struct rt_serial_device *serial)
+static int ls2k_uart_getc(struct rt_serial_device *serial)
 {
     struct rt_uart_ls2k *uart_dev = RT_NULL;
 
@@ -141,18 +141,18 @@ static void uart_irq_handler(int vector, void *param)
 
 }
 
-static const struct rt_uart_ops mipssim_uart_ops =
+static const struct rt_uart_ops ls2k_uart_ops =
 {
-    mipssim_uart_configure,
-    mipssim_uart_control,
-    mipssim_uart_putc,
-    mipssim_uart_getc,
+    ls2k_uart_configure,
+    ls2k_uart_control,
+    ls2k_uart_putc,
+    ls2k_uart_getc,
 };
 
 struct rt_uart_ls2k uart_dev0 =
 {
-    (void *)UART0_BASE,
-    4,
+    (void *)UARTx_BASE(0),
+    LS2K_UART_0_1_2_3_IRQ,
 };
 struct rt_serial_device serial;
 
@@ -164,7 +164,7 @@ void rt_hw_uart_init(void)
 
     uart = &uart_dev0;
 
-    serial.ops    = &mipssim_uart_ops;
+    serial.ops    = &ls2k_uart_ops;
     serial.config = config;
 
     rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART");
diff --git a/bsp/ls2kdev/drivers/drv_uart.h b/bsp/ls2kdev/drivers/drv_uart.h
index 95c69a0442..4d17b99b35 100644
--- a/bsp/ls2kdev/drivers/drv_uart.h
+++ b/bsp/ls2kdev/drivers/drv_uart.h
@@ -5,7 +5,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2019-04-05     bigmagic     Initial version
+ * 2020-04-05     bigmagic     Initial version
  */
 
 #ifndef _DRV_UART_H__
diff --git a/bsp/ls2kdev/drivers/interrupt.c b/bsp/ls2kdev/drivers/interrupt.c
index 6473e5aa94..97f5994ec7 100644
--- a/bsp/ls2kdev/drivers/interrupt.c
+++ b/bsp/ls2kdev/drivers/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,8 +17,9 @@
 #include <rtthread.h>
 #include <rthw.h>
 #include <exception.h>
-
-#define MAX_INTR 32
+#include <drivers/pin.h>
+#include "ls2k1000.h"
+#include "interrupt.h"
 
 static struct rt_irq_desc irq_handle_table[MAX_INTR];
 
@@ -27,17 +28,141 @@ static void rt_hw_interrupt_handler(int vector, void *param)
     rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
+static void liointc_init(void)
+{
+    int i;
+    /* Router for LIOINTC0, to Core 0, INT0 (CPU IP2) */
+    for (i = 0; i < 32; i ++)
+    {
+        HWREG8(LIOINTC0_BASE + i) = LIOINTC_COREx_INTy(0, 0);
+    }
+
+    /* Router for LIOINTC1, to Core 0, INT1 (CPU IP3) */
+    for (i = 0; i < 32; i ++)
+    {
+        HWREG8(LIOINTC1_BASE + i) = LIOINTC_COREx_INTy(0, 1);
+    }
+
+    /* Disable all IRQs */
+    HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_DISABLE) = 0xffffffff;
+    HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_DISABLE) = 0xffffffff;
+
+    /* Set all IRQs to low level triggered (Default?) */
+    HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) = 0x0;
+    HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) = 0x0;
+
+    HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) = 0x0;
+    HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) = 0x0;
+}
+
+//set irq mode
+void liointc_set_irq_mode(int irq, int mode)
+{
+    if(irq < 32)
+    {
+        if(mode == PIN_IRQ_MODE_RISING)
+        {
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL)  |= (0x0 << (irq));
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq));
+        }
+        else if(mode == PIN_IRQ_MODE_FALLING)
+        {
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL)  |= (0x1 << (irq));
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq));
+        }
+        else if(mode == PIN_IRQ_MODE_HIGH_LEVEL)
+        {
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL)  |= (0x1 << (irq));
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq));
+        }
+        else if(mode == PIN_IRQ_MODE_LOW_LEVEL)
+        {
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL)  |= (0x0 << (irq));
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq));
+        }
+        else
+        {
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL)  |= (0x1 << (irq));
+            HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq));
+        }
+    }
+    else
+    {
+        if(mode == PIN_IRQ_MODE_RISING)
+        {
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL)  |= (0x0 << (irq - 32));
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32));
+        }
+        else if(mode == PIN_IRQ_MODE_FALLING)
+        {
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL)  |= (0x1 << (irq - 32));
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32));
+        }
+        else if(mode == PIN_IRQ_MODE_HIGH_LEVEL)
+        {
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL)  |= (0x1 << (irq - 32));
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq - 32));
+        }
+        else if(mode == PIN_IRQ_MODE_LOW_LEVEL)
+        {
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL)  |= (0x0 << (irq - 32));
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq - 32));
+        }
+        else
+        {
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL)  |= (0x1 << (irq - 32));
+            HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32));
+        }
+    }
+}
+
+static void liointc_isr(rt_ubase_t reg_base, rt_ubase_t isr_base,
+                        int irq_base)
+{
+    rt_uint32_t isr, tmp;
+    int intx;
+    /* Mask to clear ISR */
+    isr = HWREG32(isr_base);
+
+    tmp = isr;
+    /* Handle each of them */
+    while (tmp)
+    {
+        rt_isr_handler_t irq_func;
+        void *param;
+        int irq;
+
+        intx = __rt_ffs(isr) - 1;
+        tmp &= ~(1 << intx);
+
+        irq = intx + irq_base;
+
+        irq_func = irq_handle_table[irq].handler;
+        param = irq_handle_table[irq].param;
+        irq_func(irq, param);
+#ifdef RT_USING_INTERRUPT_INFO
+        irq_handle_table[irq].counter++;
+#endif
+    }
+
+    /* Enable them again */
+    HWREG32(reg_base + LIOINTC_REG_INTC_ENABLE) = isr;
+}
+
 /**
  * This function will initialize hardware interrupt
  */
 void rt_hw_interrupt_init(void)
 {
     rt_uint32_t idx;
+
     rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
     for (idx = 0; idx < MAX_INTR; idx ++)
     {
         irq_handle_table[idx].handler = rt_hw_interrupt_handler;
     }
+
+    liointc_init();
 }
 
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
@@ -56,34 +181,57 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
         irq_handle_table[vector].param = param;
     }
 
+    if(vector <= 32)
+    {
+        mips_unmask_cpu_irq(2);
+    }
+    else
+    {
+        mips_unmask_cpu_irq(3);
+    }
+     
     return old_handler;
 }
 
-void rt_hw_timer_handler(void);
-
 void rt_do_mips_cpu_irq(rt_uint32_t ip)
 {
     void *param;
     rt_isr_handler_t irq_func;
-
-    if (ip == 7) {
+    if (ip == 7)
+    {
         rt_hw_timer_handler();
-    } else {
-        irq_func = irq_handle_table[ip].handler;
-                param = irq_handle_table[ip].param;
-
-                /* do interrupt */
-                irq_func(ip, param);
+    }
+    else if (ip == 2)
+    {
+        liointc_isr(LIOINTC0_BASE, CORE0_INTISR0, LIOINTC0_IRQBASE);
+    }
+    else if (ip == 3)
+    {
+        liointc_isr(LIOINTC1_BASE, CORE0_INTISR1, LIOINTC1_IRQBASE);
     }
 }
 
 void rt_hw_interrupt_umask(int irq)
 {
-    mips_unmask_cpu_irq(irq);
+    if(irq < LIOINTC0_IRQBASE + 32)
+    {
+        HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_ENABLE) = (1 << irq);
+    }
+    else if(irq < LIOINTC1_IRQBASE + 32)
+    {
+        HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_ENABLE) = (1 << (irq - 32));
+    }
 }
 
 void rt_hw_interrupt_mask(int irq)
 {
-    mips_mask_cpu_irq(irq);
+    if(irq < LIOINTC0_IRQBASE + 32)
+    {
+        HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_DISABLE) = (1 << irq);
+    }
+    else if(irq < LIOINTC1_IRQBASE + 32)
+    {
+        HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_DISABLE) = (1 << (irq - 32));
+    }
 }
 /*@}*/
diff --git a/bsp/ls2kdev/drivers/interrupt.h b/bsp/ls2kdev/drivers/interrupt.h
new file mode 100644
index 0000000000..18707f7321
--- /dev/null
+++ b/bsp/ls2kdev/drivers/interrupt.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-21     bigmagic     Initial version
+ */
+
+#ifndef _DRV_INTERRUPT_H__
+#define _DRV_INTERRUPT_H__
+
+#define LS2K_UART_0_1_2_3_IRQ       (0)
+#define LS2K_UART_4_5_6_7_IRQ       (1)
+#define LS2K_UART_8_9_10_11_IRQ     (2)
+#define LS2K_EL_IRQ                 (3)
+#define LS2K_HDA_IRQ                (4)
+#define LS2K_I2S_IRQ                (5)
+#define LS2K_RESERVED1_IRQ          (6)
+#define LS2K_THSENS_IRQ             (7)
+#define LS2K_TOY_TICK_IRQ           (8)
+#define LS2K_RTC_TICK_IRQ           (9)
+#define LS2K_CAM_TICK_IRQ           (10)
+#define LS2K_RESERVED2_IRQ          (11)
+#define LS2K_GMAC0_SBD_IRQ          (12)
+#define LS2K_GMAC0_PMT_IRQ          (13)
+#define LS2K_GMAC1_SBD_IRQ          (14)
+#define LS2K_GMAC1_PMT_IRQ          (15)
+#define LS2K_CANO_IRQ               (16)
+#define LS2K_CAN1_IRQ               (17)
+#define LS2K_BOOT_IRQ               (18)
+#define LS2K_SATA_IRQ               (19)
+#define LS2K_NAND_IRQ               (20)
+#define LS2K_HPET_IRQ               (21)
+#define LS2K_I2C0_IRQ               (21)
+#define LS2K_I2C1_IRQ               (22)
+#define LS2K_I2C2_IRQ               (23)
+#define LS2K_PWM0_IRQ               (24)
+#define LS2K_PWM1_IRQ               (25)
+#define LS2K_PWM2_IRQ               (26)
+#define LS2K_PWM3_IRQ               (27)
+#define LS2K_DC_IRQ                 (28)
+#define LS2K_GPU_IRQ                (29)
+#define LS2K_VPU_IRQ                (30)
+#define LS2K_SDIO_IRQ               (31)
+//#define LS2K_PCIE0_IRQ              (32~35)
+//#define LS2K_PCIE1_IRQ              (36~37)
+#define LS2K_HPET1_IRQ              (38)
+#define LS2K_HPET2_IRQ              (39)
+//#define LS2K_TOY_IRQ                (40~43)
+//#define LS2K_DMA_IRQ                (44~48)
+#define LS2K_OTG_IRQ                (49)
+#define LS2K_EHCI_IRQ               (50)
+#define LS2K_OHCI_IRQ               (51)
+//#define LS2K_RTC_IRQ                (52~54)
+#define LS2K_RSA_IRQ                (55)
+#define LS2K_AES_IRQ                (56)
+#define LS2K_DES_IRQ                (57)
+#define LS2K_GPIO_INTLO_IRQ         (58)
+#define LS2K_GPIO_INTHI_IRQ         (59)
+#define LS2K_GPIO0_INT_IRQ          (60)
+#define LS2K_GPIO1_INT_IRQ          (61)
+#define LS2K_GPIO2_INT_IRQ          (62)
+#define LS2K_GPIO3_INT_IRQ          (63)
+
+#define MAX_INTR 64
+#define LIOINTC0_IRQBASE 0
+#define LIOINTC1_IRQBASE 32
+
+#define LIOINTC_SHIFT_INTx 4
+#define LIOINTC_COREx_INTy(x, y)   ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
+
+#define LIOINTC_INTC_CHIP_START	    0x20
+
+#define LIOINTC_REG_INTC_STATUS	    (LIOINTC_INTC_CHIP_START + 0x00)
+#define LIOINTC_REG_INTC_EN_STATUS	(LIOINTC_INTC_CHIP_START + 0x04)
+#define LIOINTC_REG_INTC_ENABLE	    (LIOINTC_INTC_CHIP_START + 0x08)
+#define LIOINTC_REG_INTC_DISABLE	(LIOINTC_INTC_CHIP_START + 0x0c)
+#define LIOINTC_REG_INTC_POL	    (LIOINTC_INTC_CHIP_START + 0x10)
+#define LIOINTC_REG_INTC_EDGE	    (LIOINTC_INTC_CHIP_START + 0x14)
+
+void liointc_set_irq_mode(int irq, int mode);
+
+#endif
\ No newline at end of file
diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h
index 90adf4a6ed..cb6586525e 100644
--- a/bsp/ls2kdev/drivers/ls2k1000.h
+++ b/bsp/ls2kdev/drivers/ls2k1000.h
@@ -2,12 +2,23 @@
 #define _LS2K1000_H__
 
 #include <mips.h>
+#include "interrupt.h"
+
+#define APB_BASE         CKSEG1ADDR(0xbfe00000)
 
 #define UART0_BASE_ADDR 0xbfe00000
 #define UART0_OFF   0x0
 #define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
 
-#define GPIO_BASE 0xFFFFFFFFBFE10500
+#define UARTx_BASE(x)   ((APB_BASE | (0x0 << 12) | (x << 8)))
+
+#define LIOINTC0_BASE    CKSEG1ADDR(0x1fe11400)
+#define CORE0_INTISR0    CKSEG1ADDR(0x1fe11040)
+
+#define LIOINTC1_BASE    CKSEG1ADDR(0x1fe11440)
+#define CORE0_INTISR1    CKSEG1ADDR(0x1fe11048)
+
+#define GPIO_BASE    0xFFFFFFFFBFE10500
 #define PLL_SYS_BASE 0xFFFFFFFFBFE10480
 
 void rt_hw_timer_handler(void);
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index cd7d97e6c0..84bb0446d6 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -39,7 +39,7 @@ void rt_hw_interrupt_enable(rt_base_t level)
 /**
  * exception handle table
  */
-#define RT_EXCEPTION_MAX	31
+#define RT_EXCEPTION_MAX 31
 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
 
 /**
@@ -59,10 +59,13 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func)
     return old_handler;
 }
 
-void mips_dump_regs(struct pt_regs *regs) {
+void mips_dump_regs(struct pt_regs *regs)
+{
     int i, j;
-    for(i = 0; i < 32 / 4; i++) {
-        for(j = 0; j < 4; j++) {
+    for (i = 0; i < 32 / 4; i++)
+    {
+        for (j = 0; j < 4; j++)
+        {
             int reg = 4 * i + j;
             rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]);
         }
@@ -84,9 +87,10 @@ void cache_error_handler(void)
 
 static void unhandled_exception_handle(struct pt_regs *regs)
 {
-    rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause());
-    rt_kprintf("ST0: 0x%08x ",regs->cp0_status);
-    rt_kprintf("ErrorPC: 0x%08x\n",read_c0_errorepc());
+    rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(),
+               read_c0_cause());
+    rt_kprintf("ST0: 0x%08x ", regs->cp0_status);
+    rt_kprintf("ErrorPC: 0x%08x\n", read_c0_errorepc());
     mips_dump_regs(regs);
     rt_hw_cpu_shutdown();
 }
@@ -95,8 +99,9 @@ static void install_default_exception_handler(void)
 {
     rt_int32_t i;
 
-    for (i=0; i<RT_EXCEPTION_MAX; i++)
-        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
+    for (i = 0; i < RT_EXCEPTION_MAX; i++)
+        sys_exception_handlers[i] =
+                (exception_func_t)unhandled_exception_handle;
 }
 
 int rt_hw_exception_init(void)
@@ -117,14 +122,16 @@ int rt_hw_exception_init(void)
 
 void rt_general_exc_dispatch(struct pt_regs *regs)
 {
-    rt_ubase_t exccode = 0;
+    rt_ubase_t cause, exccode;
+    cause = read_c0_cause();
+    exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;    
 
-
-    if (exccode == 0) {
+    if (exccode == 0)
+    {
         rt_ubase_t status, pending;
-        status = read_c0_status();
 
-        pending =  (CAUSEF_IP) & (status & ST0_IM);
+        status = read_c0_status();
+        pending = (cause & CAUSEF_IP) & (status & ST0_IM);
         if (pending & CAUSEF_IP0)
             rt_do_mips_cpu_irq(0);
         if (pending & CAUSEF_IP1)
@@ -141,7 +148,9 @@ void rt_general_exc_dispatch(struct pt_regs *regs)
             rt_do_mips_cpu_irq(6);
         if (pending & CAUSEF_IP7)
             rt_do_mips_cpu_irq(7);
-    } else {
+    }
+    else
+    {
         if (sys_exception_handlers[exccode])
             sys_exception_handlers[exccode](regs);
     }
-- 
cgit v1.3.1


From dae274e1f27296f5217b2567486458b10c405429 Mon Sep 17 00:00:00 2001
From: shaojinchun <shaojinchun@rt-thread.com>
Date: Tue, 30 Jun 2020 17:32:14 +0800
Subject: fix gic ack irq problem

---
 libcpu/arm/cortex-a/gic.c | 3 +--
 libcpu/arm/zynq7000/gic.c | 5 ++---
 2 files changed, 3 insertions(+), 5 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c
index 2a46142b54..2e94b88277 100644
--- a/libcpu/arm/cortex-a/gic.c
+++ b/libcpu/arm/cortex-a/gic.c
@@ -74,9 +74,8 @@ void arm_gic_ack(rt_uint32_t index, int irq)
     irq = irq - _gic_table[index].offset;
     RT_ASSERT(irq >= 0);
 
-    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
     GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
-    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
 void arm_gic_mask(rt_uint32_t index, int irq)
diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c
index e23a359e6e..76404d4c46 100644
--- a/libcpu/arm/zynq7000/gic.c
+++ b/libcpu/arm/zynq7000/gic.c
@@ -37,7 +37,7 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
 #define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + (n/32) * 4)
 #define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + (n/32) * 4)
 #define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200)
-#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + (n/32) * 4)
 #define GIC_DIST_ACTIVE_BIT(hw_base)        __REG32((hw_base) + 0x300)
 #define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  (n/4) * 4)
 #define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  (n/4) * 4)
@@ -68,9 +68,8 @@ void arm_gic_ack(rt_uint32_t index, int irq)
     irq = irq - _gic_table[index].offset;
     RT_ASSERT(irq >= 0);
 
-    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
     GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
-    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
 void arm_gic_mask(rt_uint32_t index, int irq)
-- 
cgit v1.3.1


From 3ce53f9c797e4dae2da3b9235494f059b9a48c59 Mon Sep 17 00:00:00 2001
From: michael <michael5hzg@gmail.com>
Date: Wed, 19 Aug 2020 10:03:52 +0800
Subject: MIPS:remove redundant #ifdef ARCH_MIPS64

there exist redundant #ifdef ARCH_MIPS64 in asm.h, remove it
---
 libcpu/mips/common/asm.h | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h
index 6a5353b803..1b39eea05a 100644
--- a/libcpu/mips/common/asm.h
+++ b/libcpu/mips/common/asm.h
@@ -261,11 +261,7 @@ symbol		=	value
 #define LONG_SRAV	srav
 
 #define LONG		.word
-#ifdef ARCH_MIPS64
-#define LONGSIZE	8
-#else
 #define LONGSIZE	4
-#endif
 #define LONGMASK	3
 #define LONGLOG		2
 
-- 
cgit v1.3.1


From 3d0bdf4bb65bcb676b120ae273c8c28e7f52b911 Mon Sep 17 00:00:00 2001
From: michael <michael5hzg@gmail.com>
Date: Tue, 25 Aug 2020 11:52:07 +0800
Subject: MIPS:improvement FPU support

---
 libcpu/mips/common/stackframe.h | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h
index 258f9a994f..4f1157aebf 100644
--- a/libcpu/mips/common/stackframe.h
+++ b/libcpu/mips/common/stackframe.h
@@ -22,7 +22,9 @@
 #ifdef RT_USING_FPU
     /* Ensure CU1 (FPU) is enabled */
     MFC0 v1, CP0_STATUS
-    ori v1, ST0_CU1
+    lui t1, %hi(ST0_CU1)
+    addiu t1, t1, %lo(ST0_CU1)
+    or v1, v1, t1
     MTC0 v1, CP0_STATUS
     SSNOP
     cfc1 v1, fcr31
@@ -125,11 +127,13 @@
 #ifdef RT_USING_FPU
     /* Ensure CU1 (FPU) is enabled */
     MFC0 v1, CP0_STATUS
-    ori v1, ST0_CU1
+    lui t1, %hi(ST0_CU1)
+    addiu t1, t1, %lo(ST0_CU1)
+    or v1, v1, t1
     MTC0 v1, CP0_STATUS
     SSNOP
     LONG_L v1, PT_FPU_FCSR31(sp)
-    ctc1 v1, fcsr31
+    ctc1 v1, fcr31
     l.d $f0, PT_FPU_R0(sp)
     l.d $f2, PT_FPU_R2(sp)
     l.d $f4, PT_FPU_R4(sp)
-- 
cgit v1.3.1


From eb00fbeda7d9139805a5cf525779d15022188f18 Mon Sep 17 00:00:00 2001
From: Huaqi Fang <578567190@qq.com>
Date: Thu, 3 Sep 2020 18:10:08 +0800
Subject: libcpu/nuclei: Fix wrong RT_KERNEL_INTERRUPT_LEVEL

RT_KERNEL_INTERRUPT_LEVEL set to 0 is the lowest level.

Signed-off-by: Huaqi Fang <578567190@qq.com>
---
 libcpu/risc-v/nuclei/cpuport.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c
index fad9afdf4c..e456438f70 100644
--- a/libcpu/risc-v/nuclei/cpuport.c
+++ b/libcpu/risc-v/nuclei/cpuport.c
@@ -19,7 +19,7 @@
 #define SYSTICK_TICK_CONST                      (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
 
 /* Interrupt level for kernel systimer interrupt and software timer interrupt */
-#define RT_KERNEL_INTERRUPT_LEVEL               1
+#define RT_KERNEL_INTERRUPT_LEVEL               0
 
 /* Initial CSR MSTATUS value when thread created */
 #define RT_INITIAL_MSTATUS                      (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL)
-- 
cgit v1.3.1


From bd95f3a94f53d1fd379e659ea9a56789d9fe471d Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Wed, 26 Aug 2020 12:03:01 +0800
Subject: fix mips stackframe and exception

---
 libcpu/Kconfig                     |  4 ++++
 libcpu/mips/common/context_gcc.S   | 21 +++++++++++----------
 libcpu/mips/common/exception_gcc.S |  8 +++++++-
 libcpu/mips/common/stackframe.h    |  2 ++
 4 files changed, 24 insertions(+), 11 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/Kconfig b/libcpu/Kconfig
index e355664de2..ae2767dec9 100644
--- a/libcpu/Kconfig
+++ b/libcpu/Kconfig
@@ -82,6 +82,10 @@ config ARCH_MIPS
 
 config ARCH_MIPS64
     bool
+	select ARCH_CPU_64BIT
+	
+config ARCH_CPU_64BIT
+		bool
 
 config ARCH_MIPS_XBURST
     bool
diff --git a/libcpu/mips/common/context_gcc.S b/libcpu/mips/common/context_gcc.S
index cdcdede39a..3fdbe374c9 100644
--- a/libcpu/mips/common/context_gcc.S
+++ b/libcpu/mips/common/context_gcc.S
@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2019-12-04     Jiaxun Yang  Initial version
+ * 2020-07-26     lizhirui     Fixed some problems
  */
 
 #ifndef __ASSEMBLY__
@@ -56,12 +57,12 @@ rt_hw_context_switch_interrupt:
     bnez    t1, _reswitch
     nop
     li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
+    LONG_S      t1, 0(t0)
     PTR_LA      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
+    LONG_S      a0, 0(t0)
 _reswitch:
     PTR_LA      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
+    LONG_S      a1, 0(t0)
     jr      ra
     nop
 
@@ -97,24 +98,24 @@ mips_irq_handle:
     * rt_hw_context_switch_interrupt_do and do not return
     */
     PTR_LA  k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
+    LONG_L  k1, 0(k0)
     beqz    k1, spurious_interrupt
     nop
-    sw      zero, 0(k0)                     /* clear flag */
+    LONG_S  zero, 0(k0)                     /* clear flag */
     nop
 
     /*
     * switch to the new thread
     */
     PTR_LA  k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
+    LONG_L  k1, 0(k0)
     nop
-    sw      sp, 0(k1)                       /* store sp in preempted task TCB */
+    LONG_S  sp, 0(k1)                       /* store sp in preempted task TCB */
 
     PTR_LA  k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
+    LONG_L  k1, 0(k0)
     nop
-    lw      sp, 0(k1)                       /* get new task stack pointer */
+    LONG_L  sp, 0(k1)                       /* get new task stack pointer */
     j       spurious_interrupt
     nop
 
diff --git a/libcpu/mips/common/exception_gcc.S b/libcpu/mips/common/exception_gcc.S
index 9664438ac1..c685928a84 100644
--- a/libcpu/mips/common/exception_gcc.S
+++ b/libcpu/mips/common/exception_gcc.S
@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2019-12-04     Jiaxun Yang  Initial version
+ * 2020-07-26     lizhirui     Add xtlb exception entry
  */
 #ifndef __ASSEMBLY__
 #define __ASSEMBLY__
@@ -26,6 +27,11 @@ tlb_refill_exception:
     b	_general_exception_handler
     nop
 
+    /* 0x080 - XTLB refill handler */
+    .org ebase_start + 0x080
+    b	_general_exception_handler
+    nop
+
     /* 0x100 - Cache error handler */
     .org ebase_start + 0x100
     j	cache_error_handler
diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h
index 4f1157aebf..bb92a18c9c 100644
--- a/libcpu/mips/common/stackframe.h
+++ b/libcpu/mips/common/stackframe.h
@@ -206,6 +206,8 @@
     li	v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
     and	v0, v1
     or	v0, a0
+    li  v1, (ST0_KX | ST0_SX | ST0_UX)
+    or  v0, v1
     mtc0	v0, CP0_STATUS
     LONG_L	v1, PT_EPC(sp)
     MTC0	v1, CP0_EPC
-- 
cgit v1.3.1


From 1556ba8e7f84f34c56c7f3c13d5a5540371658d4 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Fri, 4 Sep 2020 09:31:42 +0800
Subject: add ls2k mmu

---
 libcpu/mips/common/exception.c |  44 ++-
 libcpu/mips/gs264/cache.c      |  70 ++++
 libcpu/mips/gs264/cache.h      |  24 ++
 libcpu/mips/gs264/mips_mmu.c   | 222 +++++++++++
 libcpu/mips/gs264/mips_mmu.h   | 100 +++++
 libcpu/mips/gs264/mipscfg.c    |  79 ++++
 libcpu/mips/gs264/mmu.c        | 819 +++++++++++++++++++++++++++++++++++++++++
 libcpu/mips/gs264/mmu.h        | 113 ++++++
 8 files changed, 1467 insertions(+), 4 deletions(-)
 create mode 100644 libcpu/mips/gs264/cache.c
 create mode 100644 libcpu/mips/gs264/cache.h
 create mode 100644 libcpu/mips/gs264/mips_mmu.c
 create mode 100644 libcpu/mips/gs264/mips_mmu.h
 create mode 100644 libcpu/mips/gs264/mipscfg.c
 create mode 100644 libcpu/mips/gs264/mmu.c
 create mode 100644 libcpu/mips/gs264/mmu.h

(limited to 'libcpu')

diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index 84bb0446d6..8eb89b1e1b 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -24,6 +24,41 @@ rt_ubase_t rt_interrupt_from_thread;
 rt_ubase_t rt_interrupt_to_thread;
 rt_ubase_t rt_thread_switch_interrupt_flag;
 
+const char *exception_name[] = {
+                                "Interrupt",
+                                "(X)TLB Modify Exception",
+                                "(X)TLB Read/Fetch Exception",
+                                "(X)TLB Write Exception",
+                                "Address Read/Fetch Exception",
+                                "Address Write Exception",
+                                "",
+                                "",
+                                "Syscall",
+                                "Breakpoint",
+                                "Reversed Instruction Exception",
+                                "Coprocessor Unit Invalid",
+                                "Overflow",
+                                "Trap",
+                                "FPU Exception in Vector Instruction",
+                                "FPU Exception",
+                                "Loongson Custom Exception",
+                                "",
+                                "",
+                                "(X)TLB Read Denied Exception",
+                                "(X)TLB Execute Denied Exception",
+                                "Vector Module Disabled Exception",
+                                "",
+                                "",
+                                "",
+                                "",
+                                "",
+                                "",
+                                "",
+                                "",
+                                "Cache Error Exception",
+                                ""
+                                };
+
 rt_base_t rt_hw_interrupt_disable(void)
 {
     rt_base_t status = read_c0_status();
@@ -87,10 +122,11 @@ void cache_error_handler(void)
 
 static void unhandled_exception_handle(struct pt_regs *regs)
 {
-    rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(),
-               read_c0_cause());
-    rt_kprintf("ST0: 0x%08x ", regs->cp0_status);
-    rt_kprintf("ErrorPC: 0x%08x\n", read_c0_errorepc());
+    rt_kprintf("Unknown Exception, EPC: 0x%p, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause());
+    rt_kprintf("Exception Name:%s\n",exception_name[(read_c0_cause() >> 2) & 0x1f]);
+    rt_kprintf("ExeCode = 0x%08x,BadAddr = 0x%p\n",(read_c0_cause() >> 2) & 0x1f,mmu_tlb_get_bad_vaddr());
+    rt_kprintf("ST0: 0x%08x ",regs->cp0_status);
+    rt_kprintf("ErrorPC: 0x%p\n",read_c0_errorepc());
     mips_dump_regs(regs);
     rt_hw_cpu_shutdown();
 }
diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c
new file mode 100644
index 0000000000..cfb4c6bb3c
--- /dev/null
+++ b/libcpu/mips/gs264/cache.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-29     quanzhao     the first version
+ * 2020-07-26     lizhirui     porting to ls2k
+ */
+
+#include <rthw.h>
+#include <rtdef.h>
+
+rt_inline rt_uint64_t rt_cpu_icache_line_size(void)
+{
+    rt_uint64_t ctr;
+    return 4 << (ctr & 0xF);
+}
+
+rt_inline rt_uint64_t rt_cpu_dcache_line_size(void)
+{
+    rt_uint64_t ctr;
+    return 4 << ((ctr >> 16) & 0xF);
+}
+
+void rt_hw_cpu_icache_invalidate(void *addr, int size)
+{
+    rt_uint64_t line_size = rt_cpu_icache_line_size();
+    rt_uint64_t start_addr = (rt_uint64_t)addr;
+    rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1;
+}
+
+void rt_hw_cpu_dcache_invalidate(void *addr, int size)
+{
+    rt_uint64_t line_size = rt_cpu_dcache_line_size();
+    rt_uint64_t start_addr = (rt_uint64_t)addr;
+    rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1;
+}
+
+void rt_hw_cpu_dcache_clean(void *addr, int size)
+{
+    rt_uint64_t line_size = rt_cpu_dcache_line_size();
+    rt_uint64_t start_addr = (rt_uint64_t)addr;
+    rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1;
+}
+
+void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_INVALIDATE)
+        rt_hw_cpu_icache_invalidate(addr, size);
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_FLUSH)
+        rt_hw_cpu_dcache_clean(addr, size);
+    else if (ops == RT_HW_CACHE_INVALIDATE)
+        rt_hw_cpu_dcache_invalidate(addr, size);
+}
+
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}
\ No newline at end of file
diff --git a/libcpu/mips/gs264/cache.h b/libcpu/mips/gs264/cache.h
new file mode 100644
index 0000000000..10a4afd899
--- /dev/null
+++ b/libcpu/mips/gs264/cache.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-25     quanzhao     the first version
+ */
+#ifndef __CACHE_H__
+#define __CACHE_H__
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_dcache_clean_flush(void);
+void rt_cpu_icache_flush(void);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+
+#endif
diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c
new file mode 100644
index 0000000000..bfc694ab45
--- /dev/null
+++ b/libcpu/mips/gs264/mips_mmu.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-26 	  lizhirui 	   the first version
+ */
+
+#include <string.h>
+#include <stdlib.h>
+
+#include "mips.h"
+#include "mips_mmu.h"
+
+void mmu_init()
+{
+    uint32_t status = read_c0_status();
+    status |= 0x07 << 5;//ux = 1,sx = 1,kx = 1
+    write_c0_status(status);
+    
+    mmu_clear_tlb();
+    mmu_clear_itlb();
+}
+
+void mmu_set_cpu_mode(cpu_mode_t cpu_mode)
+{
+    uint32_t status = read_c0_status();
+    status &= ~(0x03 << 3);
+    status |= ((uint32_t)cpu_mode & 0x03) << 3;
+    write_c0_status(status);
+}
+
+cpu_mode_t mmu_get_cpu_mode()
+{
+    uint32_t status = read_c0_status();
+    return (cpu_mode_t)((status >> 3) & 0x03);
+}
+
+void mmu_clear_tlb()
+{
+    uint32_t max_tlb_index = mmu_get_max_tlb_index();
+    uint64_t va = KSEG0BASE;
+    uint32_t entry;
+    tlb_item_t tlb_item;
+
+    for(entry = 0;entry <= max_tlb_index;entry++)
+    {
+        mmu_tlb_item_init(&tlb_item);
+        mmu_tlb_write_indexed(entry,&tlb_item);
+    }
+}
+
+void mmu_clear_itlb()
+{
+    uint32_t diag = read_c0_diag();
+    write_c0_diag(diag | (0x01 << 2));//write ITLB bit
+    read_c0_entrylo0();
+}
+
+uint32_t mmu_get_max_tlb_index()
+{
+    uint32_t config1 = read_c0_config1();
+    return ((config1 >> 25) & 0x3F);
+}
+
+void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item)
+{
+    tlb_item -> entry_lo[0].g |= tlb_item -> entry_lo[1].g;
+    tlb_item -> entry_lo[1].g |= tlb_item -> entry_lo[0].g;
+    mmu_tlb_set_index(index);
+    write_c0_entrylo0(reg_type_convert(tlb_item -> entry_lo[0],uint64_t));
+    write_c0_entrylo1(reg_type_convert(tlb_item -> entry_lo[1],uint64_t));
+    write_c0_entryhi(reg_type_convert(tlb_item -> entry_hi,uint64_t));
+    write_c0_pagemask(reg_type_convert(tlb_item -> page_mask,uint64_t));
+    tlb_write_indexed();
+    read_c0_entrylo0();
+}
+
+void mmu_tlb_write_random(tlb_item_t *tlb_item)
+{
+    tlb_item -> entry_lo[0].g |= tlb_item -> entry_lo[1].g;
+    tlb_item -> entry_lo[1].g |= tlb_item -> entry_lo[0].g;
+    write_c0_entrylo0(reg_type_convert(tlb_item -> entry_lo[0],uint64_t));
+    write_c0_entrylo1(reg_type_convert(tlb_item -> entry_lo[1],uint64_t));
+    write_c0_entryhi(reg_type_convert(tlb_item -> entry_hi,uint64_t));
+    write_c0_pagemask(reg_type_convert(tlb_item -> page_mask,uint64_t));
+    tlb_write_random();
+    read_c0_entrylo0();
+}
+
+void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item)
+{
+    mmu_tlb_set_index(index);
+    tlb_read();
+    uint64_t entrylo[2];
+    uint64_t entryhi;
+    uint64_t page_mask;
+    entrylo[0] = read_c0_entrylo0();
+    entrylo[1] = read_c0_entrylo1();
+    entryhi = read_c0_entryhi();
+    page_mask = read_c0_pagemask();
+    tlb_item -> entry_lo[0] = reg_type_convert(entrylo[0],entry_lo_t);
+    tlb_item -> entry_lo[1] = reg_type_convert(entrylo[1],entry_lo_t);
+    tlb_item -> entry_hi = reg_type_convert(entryhi,entry_hi_t);
+    tlb_item -> page_mask = reg_type_convert(page_mask,page_mask_t);
+}
+
+uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index)
+{
+    entry_hi_t entry_hi;
+    entry_hi.r = (vpn >> 62) & 0x03;
+    entry_hi.vpn2 = (vpn >> 13) & 0x7FFFFFFU;
+    entry_hi.asid = asid & 0xFFU;
+    tlb_item_t tlb_item;
+    //mmu_tlb_read(6,&tlb_item);
+    //tlb_dump();
+    mmu_tlb_item_init(&tlb_item);
+    tlb_item.entry_lo[0].g = tlb_item.entry_lo[1].g = 1;
+    read_c0_entrylo0();//i don't know why,but if i don't read any register of mmu,tplb will be failed in qemu.
+    write_c0_entrylo0(reg_type_convert(tlb_item.entry_lo[0],uint64_t));
+    write_c0_entrylo1(reg_type_convert(tlb_item.entry_lo[1],uint64_t));
+    write_c0_entryhi(reg_type_convert(entry_hi,uint64_t));
+    //__asm__ __volatile__("ehb");
+    //read_c0_entryhi();
+    //rt_kprintf("entry_hi = %p\n",read_c0_entryhi());
+    tlb_probe();
+    *index = mmu_tlb_get_index();
+    return mmu_tlb_is_matched();
+}
+
+void mmu_tlb_item_init(tlb_item_t *tlb_item)
+{
+    memset(tlb_item,0,sizeof(tlb_item_t));
+    tlb_item -> entry_lo[0].c = 0x03;
+    tlb_item -> entry_lo[1].c = 0x03;
+}
+
+void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global)
+{
+    uint64_t page_mask_v = (uint64_t)page_mask;
+
+    /*if(page_mask_v & (1 << 13))
+    {
+        page_mask_v |= (1 << 12);
+    }*/
+
+    uint64_t lb = lowbit((~(page_mask_v)) << 12);
+    uint64_t pn_remained = ((~(page_mask_v)) << 12) | lb;
+    vpn &= pn_remained;
+    ppn &= pn_remained;
+    uint64_t odd_vpn = vpn | lb;
+    uint64_t even_vpn = vpn & (~lb);
+    uint32_t index;
+    tlb_item_t tlb_item,tlb2_item;
+    
+    mmu_tlb_item_init(&tlb_item);
+    mmu_tlb_item_init(&tlb2_item);
+    tlb_item.page_mask.mask = page_mask;
+
+    if(mmu_tlb_find(vpn & (~lb),asid,&index))
+    {
+        mmu_tlb_read(index,&tlb_item);
+        mmu_tlb_write_indexed(index,&tlb2_item);
+    }
+
+    entry_lo_t *entry_lo = &tlb_item.entry_lo[vpn == even_vpn ? 0 : 1];
+    tlb_item.entry_lo[0].g = tlb_item.entry_lo[1].g = global;
+    entry_lo -> d = 1;
+    entry_lo -> ri = 0;
+    entry_lo -> xi = 0;
+    entry_lo -> v = 1;
+    entry_lo -> pfn = ppn >> 12;
+    tlb_item.entry_hi.r = (vpn >> 62) & 0x03;
+    tlb_item.entry_hi.vpn2 = (vpn >> 13) & 0x7FFFFFFU;
+    tlb_item.entry_hi.asid = asid & 0xFFU;
+    mmu_tlb_write_random(&tlb_item);
+}
+
+uint32_t mmu_tlb_get_random()
+{
+    return read_c0_random();
+}
+
+uint32_t mmu_tlb_get_index()
+{
+    return read_c0_index() & 0x3F;
+}
+
+void mmu_tlb_set_index(uint32_t index)
+{
+    write_c0_index(index & 0x3F);
+}
+
+uint32_t mmu_tlb_is_matched()
+{
+    return (read_c0_index() & 0x80000000) == 0;
+}
+
+uint64_t mmu_tlb_get_bad_vaddr()
+{
+    return read_c0_badvaddr();
+}
+
+void tlb_dump()
+{
+	uint32_t max_index = mmu_get_max_tlb_index();
+	//uint32_t max_index = 10;
+	uint32_t entry;
+	tlb_item_t tlb_item;
+
+	for(entry = 0;entry <= max_index;entry++)
+	{
+		mmu_tlb_read(entry,&tlb_item);
+		//mmu_tlb_write_indexed(entry,&tlb_item);
+		//mmu_tlb_read(entry,&tlb_item);
+		rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12);
+		rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c);
+		rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c);
+	}
+}
\ No newline at end of file
diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h
new file mode 100644
index 0000000000..c0b33ecf89
--- /dev/null
+++ b/libcpu/mips/gs264/mips_mmu.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-26 	  lizhirui 	   the first version
+ */
+
+#ifndef __MIPS_MMU_H__
+#define __MIPS_MMU_H__
+
+    typedef enum cpu_mode_t
+    {
+        CPU_MODE_KERNEL = 0x00,
+        CPU_MODE_SUPERVISOR = 0x01,
+        CPU_MODE_USER = 0x02
+    }cpu_mode_t;
+
+    typedef enum page_mask_enum_t
+    {
+        PAGE_MASK_4KB = 0x00,
+        PAGE_MASK_16KB = 0x03,
+        PAGE_MASK_64KB = 0x0F,
+        PAGE_MASK_256KB = 0x3F,
+        PAGE_MASK_1MB = 0xFF,
+        PAGE_MASK_4MB = 0x3FF,
+        PAGE_MASK_16MB = 0xFFF,
+        PAGE_MASK_64MB = 0x3FFF,
+        PAGE_MASK_256MB = 0xFFFF,
+        PAGE_MASK_1GB = 0x3FFFF
+    }page_mask_enum_t;
+
+    typedef struct page_mask_t
+    {
+        uint64_t : 11;
+        uint64_t : 2;
+        uint64_t mask : 18;
+        uint64_t : 33;
+    }page_mask_t;
+
+    typedef struct entry_lo_t
+    {
+        uint64_t g : 1;
+        uint64_t v : 1;
+        uint64_t d : 1;
+        uint64_t c : 3;
+        uint64_t pfn : 24;
+        uint64_t pfnx : 3;
+        uint64_t : 29;
+        uint64_t xi : 1;
+        uint64_t ri : 1;
+    }entry_lo_t;
+
+    typedef struct entry_hi_t
+    {
+        uint64_t asid : 8;
+        uint64_t : 5;
+        uint64_t vpn2 : 27;
+        uint64_t : 22;
+        uint64_t r : 2;
+    }entry_hi_t;
+
+    typedef struct tlb_item_t
+    {
+        entry_lo_t entry_lo[2];
+        entry_hi_t entry_hi;
+        page_mask_t page_mask;
+    }tlb_item_t;
+
+    #define read_c0_diag()		__read_32bit_c0_register($22, 0)
+    #define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
+    #define read_c0_badvaddr()  __read_64bit_c0_register($8, 0)
+    #define read_c0_random()  __read_32bit_c0_register($1, 0)
+
+    #define reg_type_convert(variable,new_type) *((new_type *)(&variable))
+    #define lowbit(x) ((x) & (-(x)))
+
+    void mmu_init();
+    void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
+    cpu_mode_t mmu_get_cpu_mode();
+    void mmu_clear_tlb();
+    void mmu_clear_itlb();
+    uint32_t mmu_get_max_tlb_index();
+    void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
+    void mmu_tlb_write_random(tlb_item_t *tlb_item);
+    void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
+    uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
+    void mmu_tlb_item_init(tlb_item_t *tlb_item);
+    void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
+    uint32_t mmu_tlb_get_random();
+    uint32_t mmu_tlb_get_index();
+    void mmu_tlb_set_index(uint32_t index);
+    uint32_t mmu_tlb_is_matched();
+    uint64_t mmu_tlb_get_bad_vaddr();
+
+    void tlb_dump();
+
+#endif
\ No newline at end of file
diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c
new file mode 100644
index 0000000000..f6c73095d9
--- /dev/null
+++ b/libcpu/mips/gs264/mipscfg.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-28     lizhirui       first version
+ */
+#include <rtthread.h>
+#include <mips.h>
+
+mips32_core_cfg_t g_mips_core =
+{
+    64,		/* icache_line_size */
+    128,	/* icache_lines_per_way */
+    4,		/* icache_ways */
+    32768,
+    64,		/* dcache_line_size */
+    128,	/* dcache_lines_per_way */
+    4,		/* dcache_ways */
+    32768,
+    64,		/* max_tlb_entries */
+};
+
+static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
+{
+    rt_uint16_t rets = 1;
+
+    while (n--)
+        rets *= b;
+
+    return rets;
+}
+
+static rt_uint16_t m_log2(rt_uint16_t b)
+{
+    rt_uint16_t rets = 0;
+
+    while (b != 1)
+    {
+        b /= 2;
+        rets++;
+    }
+
+    return rets;
+}
+
+/**
+ * read core attribute
+ */
+void mips32_cfg_init(void)
+{
+    rt_uint16_t val;
+    rt_uint32_t cp0_config1;
+
+    cp0_config1 = read_c0_config();
+    if (cp0_config1 & 0x80000000)
+    {
+        cp0_config1 = read_c0_config1();
+
+        val = (cp0_config1 & (7<<22))>>22;
+        g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
+        val = (cp0_config1 & (7<<19))>>19;
+        g_mips_core.icache_line_size = 2 * m_pow(2, val);
+        val = (cp0_config1 & (7<<16))>>16;
+        g_mips_core.icache_ways = val + 1;
+
+        val = (cp0_config1 & (7<<13))>>13;
+        g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
+        val = (cp0_config1 & (7<<10))>>10;
+        g_mips_core.dcache_line_size = 2 * m_pow(2, val);
+        val = (cp0_config1 & (7<<7))>>7;
+        g_mips_core.dcache_ways = val + 1;
+
+        val = (cp0_config1 & (0x3F<<25))>>25;
+        g_mips_core.max_tlb_entries = val + 1;
+    }
+}
diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c
new file mode 100644
index 0000000000..b08bdf4c65
--- /dev/null
+++ b/libcpu/mips/gs264/mmu.c
@@ -0,0 +1,819 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ * 2020-07-26     lizhirui     porting to ls2k
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "cache.h"
+#include "mips_mmu.h"
+#include "mmu.h"
+
+void *current_mmu_table = RT_NULL;
+
+void *mmu_table_get()
+{
+	return current_mmu_table;
+}
+
+void switch_mmu(void *mmu_table)
+{
+	current_mmu_table = mmu_table;
+
+    mmu_clear_tlb();
+	mmu_clear_itlb();
+}
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    //asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    //asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_cpu_dcache_clean(void *addr, int size);
+void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size)
+{
+    /* set page table */
+    for(; size > 0; size--)
+    {
+        rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
+                mdesc->paddr_start, mdesc->attr);
+        mdesc++;
+    }
+    rt_hw_cpu_dcache_clean((void*)MMUTable, sizeof MMUTable);
+}
+
+void rt_hw_mmu_init(void)
+{
+    rt_cpu_dcache_clean_flush();
+    rt_cpu_icache_flush();
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+
+/*
+ mem map
+*/
+
+void rt_hw_cpu_dcache_clean(void *addr, int size);
+
+int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off)
+{
+    size_t l1_off, va_s, va_e;
+    rt_base_t level;
+
+    if (!mmu_info || !vtable)
+    {
+        return -1;
+    }
+
+    va_s = (size_t)v_address;
+    va_e = (size_t)v_address + size - 1;
+
+    if ( va_e < va_s)
+    {
+        return -1;
+    }
+
+    va_s >>= ARCH_SECTION_SHIFT;
+    va_e >>= ARCH_SECTION_SHIFT;
+
+    if (va_s == 0)
+    {
+        return -1;
+    }
+
+    level = rt_hw_interrupt_disable();
+
+    for (l1_off = va_s; l1_off <= va_e; l1_off++)
+    {
+        size_t v = vtable[l1_off];
+
+        if (v & ARCH_MMU_USED_MASK)
+        {
+            rt_kprintf("Error:vtable[%d] = 0x%p(is not zero),va_s = 0x%p,va_e = 0x%p!\n",l1_off,v,va_s,va_e);
+            rt_hw_interrupt_enable(level);
+            return -1;
+        }
+    }
+
+    mmu_info->vtable = vtable;
+    mmu_info->vstart = va_s;
+    mmu_info->vend = va_e;
+    mmu_info->pv_off = pv_off;
+
+    rt_hw_interrupt_enable(level);
+
+    return 0;
+}
+
+static size_t find_vaddr(rt_mmu_info *mmu_info, int pages)
+{
+    size_t l1_off, l2_off;
+    size_t *mmu_l1, *mmu_l2;
+    size_t find_off = 0;
+    size_t find_va = 0;
+    int n = 0;
+
+    if (!pages)
+    {
+        return 0;
+    }
+
+    if (!mmu_info)
+    {
+        return 0;
+    }
+
+    for (l1_off = mmu_info->vstart; l1_off <= mmu_info->vend; l1_off++)
+    {
+        mmu_l1 =  (size_t*)mmu_info->vtable + l1_off;
+        if (*mmu_l1 & ARCH_MMU_USED_MASK)
+        {
+            mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off);
+            for (l2_off = 0; l2_off < (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); l2_off++)
+            {
+                if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK)
+                {
+                    /* in use */
+                    n = 0;
+                }
+                else
+                {
+                    if (!n)
+                    {
+                        find_va = l1_off;
+                        find_off = l2_off;
+                    }
+                    n++;
+                    if (n >= pages)
+                    {
+                        return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT);
+                    }
+                }
+            }
+        }
+        else
+        {
+            if (!n)
+            {
+                find_va = l1_off;
+                find_off = 0;
+            }
+            n += (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE);
+            if (n >= pages)
+            {
+                return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT);
+            }
+        }
+    }
+    return 0;
+}
+
+#ifdef RT_USING_USERSPACE
+static int check_vaddr(rt_mmu_info *mmu_info, void *va, int pages)
+{
+    size_t loop_va = (size_t)va & ~ARCH_PAGE_MASK;
+    size_t l1_off, l2_off;
+    size_t *mmu_l1, *mmu_l2;
+
+    if (!pages)
+    {
+        return -1;
+    }
+
+    if (!mmu_info)
+    {
+        return -1;
+    }
+
+    while (pages--)
+    {
+        l1_off = (loop_va >> ARCH_SECTION_SHIFT);
+        l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT);
+        mmu_l1 =  (size_t*)mmu_info->vtable + l1_off;
+
+        if (*mmu_l1 & ARCH_MMU_USED_MASK)
+        {
+            mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off);
+            if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK)
+            {
+                return -1;
+            }
+        }
+        loop_va += ARCH_PAGE_SIZE;
+    }
+    return 0;
+}
+#endif
+
+static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages)
+{
+    size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK;
+    size_t l1_off, l2_off;
+    size_t *mmu_l1, *mmu_l2;
+    size_t *ref_cnt;
+
+    if (!mmu_info)
+    {
+        return;
+    }
+
+    while (npages--)
+    {
+        l1_off = (loop_va >> ARCH_SECTION_SHIFT);
+        if (l1_off < mmu_info->vstart || l1_off > mmu_info->vend)
+        {
+            return;
+        }
+
+        l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT);
+        mmu_l1 =  (size_t*)mmu_info->vtable + l1_off;
+
+        if (*mmu_l1 & ARCH_MMU_USED_MASK)
+        {
+            mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off);
+        }
+        else
+        {
+            return;
+        }
+
+        if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) 
+        {
+            *(mmu_l2 + l2_off) = 0;
+            /* cache maintain */
+            rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4);
+
+            ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE);
+            (*ref_cnt)--;
+            if (!*ref_cnt)
+            {
+#ifdef RT_USING_USERSPACE
+                rt_pages_free(mmu_l2, 0);
+#else
+                rt_free_align(mmu_l2);
+#endif
+                *mmu_l1 = 0;
+
+                /* cache maintain */
+                rt_hw_cpu_dcache_clean(mmu_l1, 4);
+            }
+        }
+        loop_va += ARCH_PAGE_SIZE;
+    }
+}
+
+static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, size_t npages, size_t attr)
+{
+    size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK;
+    size_t loop_pa = (size_t)p_addr & ~ARCH_PAGE_MASK;
+    size_t l1_off, l2_off;
+    size_t *mmu_l1, *mmu_l2;
+    size_t *ref_cnt;
+
+    if (!mmu_info)
+    {
+        return -1;
+    }
+
+    while (npages--)
+    {
+        l1_off = (loop_va >> ARCH_SECTION_SHIFT);
+        l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT);
+        mmu_l1 =  (size_t*)mmu_info->vtable + l1_off;
+
+        if (*mmu_l1 & ARCH_MMU_USED_MASK)
+        {
+            mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off);
+        }
+        else
+        {
+#ifdef RT_USING_USERSPACE
+            mmu_l2 = (size_t*)rt_pages_alloc(0);
+#else
+            mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE);
+#endif
+            if (mmu_l2)
+            {
+                rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2);
+                /* cache maintain */
+                rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE);
+
+                *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1);
+                /* cache maintain */
+                rt_hw_cpu_dcache_clean(mmu_l1, 4);
+            }
+            else
+            {
+                /* error, unmap and quit */
+                __rt_hw_mmu_unmap(mmu_info, v_addr, npages);
+                return -1;
+            }
+        }
+
+        ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE);
+        (*ref_cnt)++;
+
+        *(mmu_l2 + l2_off) = (loop_pa | attr);
+        /* cache maintain */
+        rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4);
+
+        loop_va += ARCH_PAGE_SIZE;
+        loop_pa += ARCH_PAGE_SIZE;
+    }
+    return 0;
+}
+
+static void rt_hw_cpu_tlb_invalidate(void)
+{
+    mmu_clear_tlb();
+	mmu_clear_itlb();
+}
+
+#ifdef RT_USING_USERSPACE
+void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr)
+{
+    size_t pa_s, pa_e;
+    size_t vaddr;
+    int pages;
+    int ret;
+
+    if (!size)
+    {
+        return 0;
+    }
+    pa_s = (size_t)p_addr;
+    pa_e = (size_t)p_addr + size - 1;
+    pa_s >>= ARCH_PAGE_SHIFT;
+    pa_e >>= ARCH_PAGE_SHIFT;
+    pages = pa_e - pa_s + 1;
+    if (v_addr)
+    {
+        vaddr = (size_t)v_addr;
+        pa_s = (size_t)p_addr;
+        if ((vaddr & ARCH_PAGE_MASK) != (pa_s & ARCH_PAGE_MASK))
+        {
+            return 0;
+        }
+        vaddr &= ~ARCH_PAGE_MASK;
+        if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0)
+        {
+            return 0;
+        }
+    }
+    else
+    {
+        vaddr = find_vaddr(mmu_info, pages);
+    }
+    if (vaddr) {
+        ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr);
+        if (ret == 0)
+        {
+            rt_hw_cpu_tlb_invalidate();
+            return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK));
+        }
+    }
+    return 0;
+}
+#else
+void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr)
+{
+    size_t pa_s, pa_e;
+    size_t vaddr;
+    int pages;
+    int ret;
+
+    pa_s = (size_t)p_addr;
+    pa_e = (size_t)p_addr + size - 1;
+    pa_s >>= ARCH_PAGE_SHIFT;
+    pa_e >>= ARCH_PAGE_SHIFT;
+    pages = pa_e - pa_s + 1;
+    vaddr = find_vaddr(mmu_info, pages);
+    if (vaddr) {
+        ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr);
+        if (ret == 0)
+        {
+            rt_hw_cpu_tlb_invalidate();
+            return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK));
+        }
+    }
+    return 0;
+}
+#endif
+
+#ifdef RT_USING_USERSPACE
+static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void* v_addr, size_t npages, size_t attr)
+{
+    size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK;
+    size_t loop_pa;
+    size_t l1_off, l2_off;
+    size_t *mmu_l1, *mmu_l2;
+    size_t *ref_cnt;
+
+    if (!mmu_info)
+    {
+        return -1;
+    }
+
+    while (npages--)
+    {
+        loop_pa = (size_t)rt_pages_alloc(0) + mmu_info->pv_off;
+        if (!loop_pa)
+            goto err;
+
+        //rt_kprintf("vaddr = %08x is mapped to paddr = %08x\n",v_addr,loop_pa);
+        l1_off = (loop_va >> ARCH_SECTION_SHIFT);
+        l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT);
+        mmu_l1 =  (size_t*)mmu_info->vtable + l1_off;
+
+        if (*mmu_l1 & ARCH_MMU_USED_MASK)
+        {
+            mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off);
+        }
+        else
+        {
+            //mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE);
+            mmu_l2 = (size_t*)rt_pages_alloc(0);
+            if (mmu_l2)
+            {
+                rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2);
+                /* cache maintain */
+                rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE);
+
+                *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1);
+                /* cache maintain */
+                rt_hw_cpu_dcache_clean(mmu_l1, 4);
+            }
+            else
+                goto err;
+        }
+
+        ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE);
+        (*ref_cnt)++;
+
+        //loop_pa += mmu_info->pv_off;
+        *(mmu_l2 + l2_off) = (loop_pa | attr);
+        /* cache maintain */
+        rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4);
+
+        loop_va += ARCH_PAGE_SIZE;
+    }
+    return 0;
+err:
+    {
+        /* error, unmap and quit */
+        int i;
+        void *va, *pa;
+
+        va = (void*)((size_t)v_addr & ~ARCH_PAGE_MASK);
+        for (i = 0; i < npages; i++)
+        {
+            pa = rt_hw_mmu_v2p(mmu_info, va);
+            pa -= mmu_info->pv_off;
+            rt_pages_free(pa, 0);
+            va += ARCH_PAGE_SIZE;
+        }
+
+        __rt_hw_mmu_unmap(mmu_info, v_addr, npages);
+        return -1;
+    }
+}
+
+void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr)
+{
+    size_t vaddr;
+    size_t offset;
+    int pages;
+    int ret;
+
+    if (!size)
+    {
+        return 0;
+    }
+    offset = (size_t)v_addr & ARCH_PAGE_MASK;
+    size += (offset + ARCH_PAGE_SIZE - 1);
+    pages = (size >> ARCH_PAGE_SHIFT);
+    if (v_addr)
+    {
+        vaddr = (size_t)v_addr;
+        vaddr &= ~ARCH_PAGE_MASK;
+        if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0)
+        {
+            return 0;
+        }
+    }
+    else
+    {
+        vaddr = find_vaddr(mmu_info, pages);
+    }
+    if (vaddr) {
+        ret = __rt_hw_mmu_map_auto(mmu_info, (void*)vaddr, pages, attr);
+        if (ret == 0)
+        {
+            rt_hw_cpu_tlb_invalidate();
+            return (void*)vaddr + offset;
+        }
+    }
+    return 0;
+}
+#endif
+
+void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size)
+{
+    size_t va_s, va_e;
+    int pages;
+
+    va_s = (size_t)v_addr;
+    va_e = (size_t)v_addr + size - 1;
+    va_s >>= ARCH_PAGE_SHIFT;
+    va_e >>= ARCH_PAGE_SHIFT;
+    pages = va_e - va_s + 1;
+    __rt_hw_mmu_unmap(mmu_info, v_addr, pages);
+    rt_hw_cpu_tlb_invalidate();
+}
+
+//va --> pa
+void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size)
+{
+    void *p_addr = 0;
+
+    return p_addr;
+}
+
+//pa --> va
+void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size)
+{   
+    void *v_addr = 0;
+
+    #ifdef RT_USING_USERSPACE
+    extern rt_mmu_info mmu_info;
+    v_addr = rt_hw_mmu_map(&mmu_info, 0, p_addr, size, MMU_MAP_K_RW);
+    #else
+    v_addr = p_addr;
+    #endif
+
+    return v_addr;
+}
+
+#ifdef RT_USING_USERSPACE
+void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr)
+{
+    void *ret;
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+    ret = _rt_hw_mmu_map(mmu_info, v_addr, p_addr, size, attr);
+    rt_hw_interrupt_enable(level);
+    return ret;
+}
+
+void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr)
+{
+    void *ret;
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+    ret = _rt_hw_mmu_map_auto(mmu_info, v_addr, size, attr);
+    rt_hw_interrupt_enable(level);
+    return ret;
+}
+#endif
+
+void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size)
+{
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+    _rt_hw_mmu_unmap(mmu_info, v_addr, size);
+    rt_hw_interrupt_enable(level);
+}
+
+void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr)
+{
+    size_t l1_off, l2_off;
+    size_t *mmu_l1, *mmu_l2;
+    size_t tmp;
+    size_t pa;
+
+    l1_off = (size_t)v_addr >> ARCH_SECTION_SHIFT;
+
+    if (!mmu_info)
+    {
+        return (void*)0;
+    }
+
+    mmu_l1 =  (size_t*)mmu_info->vtable + l1_off;
+
+    tmp = *mmu_l1;
+
+    switch (tmp & ARCH_MMU_USED_MASK)
+    {
+        case 0: /* not used */
+            break;
+        case 1: /* page table */
+            mmu_l2 = (size_t *)((tmp & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off);
+            l2_off = (((size_t)v_addr & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT);
+            pa = *(mmu_l2 + l2_off);
+            if (pa & ARCH_MMU_USED_MASK)
+            {
+                if ((pa & ARCH_MMU_USED_MASK) == 1)
+                {
+                    /* lage page, not support */
+                    break;
+                }
+                pa &= ~(ARCH_PAGE_MASK);
+                pa += ((size_t)v_addr & ARCH_PAGE_MASK);
+                return (void*)pa;
+            }
+            break;
+        case 2:
+        case 3:
+            /* section */
+            if (tmp & ARCH_TYPE_SUPERSECTION)
+            {
+                /* super section, not support */
+                break;
+            }
+            pa = (tmp & ~ARCH_SECTION_MASK);
+            pa += ((size_t)v_addr & ARCH_SECTION_MASK);
+            return (void*)pa;
+    }
+    return (void*)0;
+}
+
+void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr)
+{
+    void *ret;
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+    ret = _rt_hw_mmu_v2p(mmu_info, v_addr);
+    rt_hw_interrupt_enable(level);
+    return ret;
+}
+
+#ifdef RT_USING_USERSPACE
+void init_mm_setup(unsigned int *mtbl, unsigned int size, unsigned int pv_off) {
+    unsigned int va;
+
+    for (va = 0; va < 0x1000; va++) {
+        unsigned int vaddr = (va << 20);
+        if (vaddr >= KERNEL_VADDR_START && vaddr - KERNEL_VADDR_START < size) {
+            mtbl[va] = ((va << 20) + pv_off) | NORMAL_MEM;
+        } else if (vaddr >= (KERNEL_VADDR_START + pv_off) && vaddr - (KERNEL_VADDR_START + pv_off) < size) {
+            mtbl[va] = (va << 20) | NORMAL_MEM;
+        } else {
+            mtbl[va] = 0;
+        }
+    }
+}
+#endif
diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h
new file mode 100644
index 0000000000..f2d4d11bc3
--- /dev/null
+++ b/libcpu/mips/gs264/mmu.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-25     quanzhao     the first version
+ * 2020-07-26     lizhirui     porting to ls2k
+ */
+#ifndef __MMU_H_
+#define __MMU_H_
+
+#include <rtthread.h>
+
+#define DESC_SEC       (0x2)
+#define MEMWBWA        ((1<<12)|(3<<2))     /* write back, write allocate */
+#define MEMWB          (3<<2)  /* write back, no write allocate */
+#define MEMWT          (2<<2)  /* write through, no write allocate */
+#define SHAREDEVICE    (1<<2)  /* shared device */
+#define STRONGORDER    (0<<2)  /* strong ordered */
+#define XN             (1<<4)  /* eXecute Never */
+#ifdef RT_USING_USERSPACE
+#define AP_RW          (1<<10) /* supervisor=RW, user=No */
+#define AP_RO          ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */
+#else
+#define AP_RW          (3<<10) /* supervisor=RW, user=RW */
+#define AP_RO          ((2<<10) /* supervisor=RW, user=RO */
+#endif
+
+#define SHARED         (1<<16) /* shareable */
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* device mapping type */
+#define DEVICE_MEM     (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN)
+/* normal memory mapping type */
+#define NORMAL_MEM     (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)
+
+#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC)
+
+struct mem_desc
+{
+    rt_uint32_t vaddr_start;
+    rt_uint32_t vaddr_end;
+    rt_uint32_t paddr_start;
+    rt_uint32_t attr;
+};
+
+#define MMU_MAP_MTBL_XN       (1<<0)
+#define MMU_MAP_MTBL_A        (1<<1)
+#define MMU_MAP_MTBL_B        (1<<2)
+#define MMU_MAP_MTBL_C        (1<<3)
+#define MMU_MAP_MTBL_AP01(x)  (x<<4)
+#define MMU_MAP_MTBL_TEX(x)   (x<<6)
+#define MMU_MAP_MTBL_AP2(x)   (x<<9)
+#define MMU_MAP_MTBL_SHARE    (1<<10)
+
+#define MMU_MAP_K_RO          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_RWCB        (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_RW          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_DEVICE      (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RO          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RWCB        (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RW          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_DEVICE      (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
+
+#define ARCH_SECTION_SHIFT  20
+#define ARCH_SECTION_SIZE   (1 << ARCH_SECTION_SHIFT)
+#define ARCH_SECTION_MASK   (ARCH_SECTION_SIZE - 1)
+#define ARCH_PAGE_SHIFT     14
+#define ARCH_PAGE_SIZE      (1 << ARCH_PAGE_SHIFT)
+#define ARCH_PAGE_MASK      (ARCH_PAGE_SIZE - 1)
+#define ARCH_PAGE_TBL_SHIFT 10
+#define ARCH_PAGE_TBL_SIZE  (1 << ARCH_PAGE_TBL_SHIFT)
+#define ARCH_PAGE_TBL_MASK  (ARCH_PAGE_TBL_SIZE - 1)
+
+#define ARCH_MMU_USED_MASK  3
+
+#define ARCH_TYPE_SUPERSECTION (1 << 18)
+
+typedef struct
+{
+    size_t *vtable;
+    size_t vstart;
+    size_t vend;
+    size_t pv_off;
+} rt_mmu_info;
+
+void *mmu_table_get();
+void switch_mmu(void *mmu_table);
+
+int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off);
+#ifdef RT_USING_USERSPACE
+void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr);
+void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr);
+#else
+void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr);
+#endif
+void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size);
+void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr);
+
+void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size);
+void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size);
+
+#endif
-- 
cgit v1.3.1


From c66314a8b6a12412e34440e8369d9c77d43aaada Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Fri, 4 Sep 2020 11:57:35 +0800
Subject: fixed loongson bsp build on windows

---
 bsp/ls1bdev/SConstruct         | 1 +
 bsp/ls1cdev/SConstruct         | 2 +-
 libcpu/mips/common/exception.c | 4 ++++
 3 files changed, 6 insertions(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/bsp/ls1bdev/SConstruct b/bsp/ls1bdev/SConstruct
index 3fe0da6a6f..a77c5dfd9b 100644
--- a/bsp/ls1bdev/SConstruct
+++ b/bsp/ls1bdev/SConstruct
@@ -11,6 +11,7 @@ sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
 
 TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+rtconfig.AFLAGS += ' -I' + str('.') + ' -I ' + RTT_ROOT + '/libcpu/mips/common/'
 
 DefaultEnvironment(tools=[])
 env = Environment(tools = ['mingw'],
diff --git a/bsp/ls1cdev/SConstruct b/bsp/ls1cdev/SConstruct
index 4ea8c066ec..0541a75c4f 100644
--- a/bsp/ls1cdev/SConstruct
+++ b/bsp/ls1cdev/SConstruct
@@ -12,7 +12,7 @@ from building import *
 
 TARGET = 'rtthread.' + rtconfig.TARGET_EXT
 
-rtconfig.AFLAGS += ' -I' + str(Dir('#'))
+rtconfig.AFLAGS += ' -I' + str('.') + ' -I ' + RTT_ROOT + '/libcpu/mips/gs232/'+ ' -I ' + RTT_ROOT + '/libcpu/mips/common/'
 
 DefaultEnvironment(tools=[])
 env = Environment(tools = ['mingw'],
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index 8eb89b1e1b..94be475878 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -124,7 +124,11 @@ static void unhandled_exception_handle(struct pt_regs *regs)
 {
     rt_kprintf("Unknown Exception, EPC: 0x%p, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause());
     rt_kprintf("Exception Name:%s\n",exception_name[(read_c0_cause() >> 2) & 0x1f]);
+#ifdef SOC_LS2K1000
     rt_kprintf("ExeCode = 0x%08x,BadAddr = 0x%p\n",(read_c0_cause() >> 2) & 0x1f,mmu_tlb_get_bad_vaddr());
+#else
+    rt_kprintf("ExeCode = 0x%08x\n",(read_c0_cause() >> 2) & 0x1f);
+#endif
     rt_kprintf("ST0: 0x%08x ",regs->cp0_status);
     rt_kprintf("ErrorPC: 0x%p\n",read_c0_errorepc());
     mips_dump_regs(regs);
-- 
cgit v1.3.1


From 60287b69fdff377ea9fdfd2f06b4ea3f6f34e32a Mon Sep 17 00:00:00 2001
From: chenzx <zhixing_chen@c-sky.com>
Date: Fri, 11 Sep 2020 10:11:25 +0800
Subject: add t-head smart-evb bsp, and risc-v cpu e906

---
 bsp/thead-smart/.config                 |  417 +++++
 bsp/thead-smart/Kconfig                 |   36 +
 bsp/thead-smart/README.md               |   45 +
 bsp/thead-smart/SConscript              |   14 +
 bsp/thead-smart/SConstruct              |   33 +
 bsp/thead-smart/applications/SConscript |   13 +
 bsp/thead-smart/applications/main.c     |   19 +
 bsp/thead-smart/drivers/SConscript      |   13 +
 bsp/thead-smart/drivers/board.c         |   48 +
 bsp/thead-smart/drivers/board.h         |   18 +
 bsp/thead-smart/drivers/board_uart.c    |  207 +++
 bsp/thead-smart/drivers/ck_irq.c        |   88 +
 bsp/thead-smart/drivers/ck_usart.c      | 1141 +++++++++++++
 bsp/thead-smart/drivers/ck_usart.h      |   92 +
 bsp/thead-smart/drivers/core_rv32.h     | 1130 ++++++++++++
 bsp/thead-smart/drivers/csi_config.h    |   29 +
 bsp/thead-smart/drivers/csi_core.h      |   53 +
 bsp/thead-smart/drivers/csi_rv32_gcc.h  | 2849 +++++++++++++++++++++++++++++++
 bsp/thead-smart/drivers/drv_common.h    |   59 +
 bsp/thead-smart/drivers/drv_errno.h     |   96 ++
 bsp/thead-smart/drivers/drv_gpio.h      |  144 ++
 bsp/thead-smart/drivers/drv_irq.h       |   41 +
 bsp/thead-smart/drivers/drv_timer.h     |  154 ++
 bsp/thead-smart/drivers/drv_usart.h     |  446 +++++
 bsp/thead-smart/drivers/dw_gpio.c       |  635 +++++++
 bsp/thead-smart/drivers/dw_gpio.h       |   52 +
 bsp/thead-smart/drivers/dw_timer.c      |  409 +++++
 bsp/thead-smart/drivers/dw_timer.h      |   48 +
 bsp/thead-smart/drivers/isr.c           |  195 +++
 bsp/thead-smart/drivers/novic_irq_tbl.c |   32 +
 bsp/thead-smart/drivers/pin_name.h      |   56 +
 bsp/thead-smart/drivers/soc.h           |  119 ++
 bsp/thead-smart/drivers/startup_gcc.S   |  132 ++
 bsp/thead-smart/drivers/sys_freq.c      |   61 +
 bsp/thead-smart/drivers/sys_freq.h      |   36 +
 bsp/thead-smart/drivers/system.c        |   85 +
 bsp/thead-smart/drivers/trap_c.c        |   50 +
 bsp/thead-smart/drivers/vectors.S       |  349 ++++
 bsp/thead-smart/gcc_csky.ld             |  184 ++
 bsp/thead-smart/rtconfig.h              |  158 ++
 bsp/thead-smart/rtconfig.py             |   68 +
 libcpu/risc-v/SConscript                |   13 +-
 libcpu/risc-v/t-head/e906/SConscript    |   12 +
 libcpu/risc-v/t-head/e906/context_gcc.S |  323 ++++
 libcpu/risc-v/t-head/e906/cpuport.c     |  170 ++
 libcpu/risc-v/t-head/e906/cpuport.h     |   55 +
 46 files changed, 10424 insertions(+), 3 deletions(-)
 create mode 100644 bsp/thead-smart/.config
 create mode 100644 bsp/thead-smart/Kconfig
 create mode 100644 bsp/thead-smart/README.md
 create mode 100644 bsp/thead-smart/SConscript
 create mode 100644 bsp/thead-smart/SConstruct
 create mode 100644 bsp/thead-smart/applications/SConscript
 create mode 100644 bsp/thead-smart/applications/main.c
 create mode 100644 bsp/thead-smart/drivers/SConscript
 create mode 100644 bsp/thead-smart/drivers/board.c
 create mode 100644 bsp/thead-smart/drivers/board.h
 create mode 100644 bsp/thead-smart/drivers/board_uart.c
 create mode 100644 bsp/thead-smart/drivers/ck_irq.c
 create mode 100644 bsp/thead-smart/drivers/ck_usart.c
 create mode 100644 bsp/thead-smart/drivers/ck_usart.h
 create mode 100644 bsp/thead-smart/drivers/core_rv32.h
 create mode 100644 bsp/thead-smart/drivers/csi_config.h
 create mode 100644 bsp/thead-smart/drivers/csi_core.h
 create mode 100644 bsp/thead-smart/drivers/csi_rv32_gcc.h
 create mode 100644 bsp/thead-smart/drivers/drv_common.h
 create mode 100644 bsp/thead-smart/drivers/drv_errno.h
 create mode 100644 bsp/thead-smart/drivers/drv_gpio.h
 create mode 100644 bsp/thead-smart/drivers/drv_irq.h
 create mode 100644 bsp/thead-smart/drivers/drv_timer.h
 create mode 100644 bsp/thead-smart/drivers/drv_usart.h
 create mode 100644 bsp/thead-smart/drivers/dw_gpio.c
 create mode 100644 bsp/thead-smart/drivers/dw_gpio.h
 create mode 100644 bsp/thead-smart/drivers/dw_timer.c
 create mode 100644 bsp/thead-smart/drivers/dw_timer.h
 create mode 100644 bsp/thead-smart/drivers/isr.c
 create mode 100644 bsp/thead-smart/drivers/novic_irq_tbl.c
 create mode 100644 bsp/thead-smart/drivers/pin_name.h
 create mode 100644 bsp/thead-smart/drivers/soc.h
 create mode 100644 bsp/thead-smart/drivers/startup_gcc.S
 create mode 100644 bsp/thead-smart/drivers/sys_freq.c
 create mode 100644 bsp/thead-smart/drivers/sys_freq.h
 create mode 100644 bsp/thead-smart/drivers/system.c
 create mode 100644 bsp/thead-smart/drivers/trap_c.c
 create mode 100644 bsp/thead-smart/drivers/vectors.S
 create mode 100644 bsp/thead-smart/gcc_csky.ld
 create mode 100644 bsp/thead-smart/rtconfig.h
 create mode 100644 bsp/thead-smart/rtconfig.py
 create mode 100644 libcpu/risc-v/t-head/e906/SConscript
 create mode 100644 libcpu/risc-v/t-head/e906/context_gcc.S
 create mode 100644 libcpu/risc-v/t-head/e906/cpuport.c
 create mode 100644 libcpu/risc-v/t-head/e906/cpuport.h

(limited to 'libcpu')

diff --git a/bsp/thead-smart/.config b/bsp/thead-smart/.config
new file mode 100644
index 0000000000..d0dbd85a46
--- /dev/null
+++ b/bsp/thead-smart/.config
@@ -0,0 +1,417 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+# CONFIG_RT_USING_TIMER_SOFT is not set
+# CONFIG_RT_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40003
+
+#
+# RT-Thread CPU arch and features
+#
+# CONFIG_ARCH_CSKY is not set
+
+#
+# risc-v arch
+#
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV_32=y
+# CONFIG_ARCH_RISCV_64 is not set
+CONFIG_ARCH_RISCV_FPU=y
+CONFIG_ARCH_RISCV_FPU_S=y
+# CONFIG_ARCH_RISCV_FPU_D is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=1
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=2048
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_SOC_THEAD_SMART=y
+CONFIG_RT_USING_UART1=y
diff --git a/bsp/thead-smart/Kconfig b/bsp/thead-smart/Kconfig
new file mode 100644
index 0000000000..b2fde84dc0
--- /dev/null
+++ b/bsp/thead-smart/Kconfig
@@ -0,0 +1,36 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_THEAD_SMART
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+if RT_USING_SERIAL
+
+    config RT_USING_UART1
+        bool "Using uart1"
+        default y 
+
+endif
diff --git a/bsp/thead-smart/README.md b/bsp/thead-smart/README.md
new file mode 100644
index 0000000000..990818a606
--- /dev/null
+++ b/bsp/thead-smart/README.md
@@ -0,0 +1,45 @@
+# T-HEAD SMART-EVB Introduction
+SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide implementation, integrating T-HEAD's RISC-V CPU (eg. E902/E906/C906) and C-SKY CPU (eg. E805/E804/E803/E802 ), integrates basic peripheral resources such as GPIO/TIMER/UART/RAM.
+
+##The main resources on board are as follows:
+1. SMART-EVB for E906/E906F/E906FD
+| res | description |
+| -- | -- |
+|ISA | RISCV |
+|CPU | E906  |
+|FREQ| 20MHz |
+|SRAM| 768KB |
+
+
+2. SMART-EVB for E804/E804F/E804D
+| res | description |
+| -- | -- |
+|ISA | C-SKY |
+|CPU | E804  |
+|FREQ| 20MHz |
+|SRAM| 768KB |
+
+
+# Compile T-HEAD BSP
+SMART-EVB BSP supports GCC compiler, the version information is:
+1. SMART-EVB for E906/E906F/E906FD
+| IDE/Compiler| version|
+| - | - |
+| GCC | gcc version 8.4.0 (C-SKY RISCV Tools V1.9.6 B20200616) |
+
+# run smart-evb bsp
+1. Connect JTAG
+2. Connect the serial port
+3. riscv64-unknown-elf-gdb rtthread-e906f.elf
+
+run log as follows:
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Sep  2 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh >
+```
+
+
+
diff --git a/bsp/thead-smart/SConscript b/bsp/thead-smart/SConscript
new file mode 100644
index 0000000000..744d8d7821
--- /dev/null
+++ b/bsp/thead-smart/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/thead-smart/SConstruct b/bsp/thead-smart/SConstruct
new file mode 100644
index 0000000000..9a283c2884
--- /dev/null
+++ b/bsp/thead-smart/SConstruct
@@ -0,0 +1,33 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-' + rtconfig.CPU + '.' + rtconfig.TARGET_EXT
+
+env  = Environment(tools = ['mingw'],
+AS   = rtconfig.AS,   ASFLAGS   = rtconfig.AFLAGS,
+CC   = rtconfig.CC,   CCFLAGS   = rtconfig.CFLAGS,
+CXX  = rtconfig.CXX,  CXXFLAGS  = rtconfig.CXXFLAGS,
+AR   = rtconfig.AR,   ARFLAGS   = '-rc',
+LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+# add --start-group and --end-group for GNU GCC
+env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/thead-smart/applications/SConscript b/bsp/thead-smart/applications/SConscript
new file mode 100644
index 0000000000..b95023ca41
--- /dev/null
+++ b/bsp/thead-smart/applications/SConscript
@@ -0,0 +1,13 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = GetCurrentDir()
+
+CCFLAGS = ' -c -ffunction-sections'
+
+group   = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CCFLAGS=CCFLAGS)
+
+Return('group')
diff --git a/bsp/thead-smart/applications/main.c b/bsp/thead-smart/applications/main.c
new file mode 100644
index 0000000000..61046f4a4b
--- /dev/null
+++ b/bsp/thead-smart/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      first version
+ */
+
+#include <rtthread.h>
+
+int main(void)
+{
+    
+    return 0;
+}
+
+/*@}*/
diff --git a/bsp/thead-smart/drivers/SConscript b/bsp/thead-smart/drivers/SConscript
new file mode 100644
index 0000000000..96f82751bb
--- /dev/null
+++ b/bsp/thead-smart/drivers/SConscript
@@ -0,0 +1,13 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+
+# add the general drivers.
+src     = Glob("*.c") + Glob("*.cpp") + Glob("*.S")
+
+CPPPATH = [cwd]
+group   = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/thead-smart/drivers/board.c b/bsp/thead-smart/drivers/board.c
new file mode 100644
index 0000000000..386d40d3a5
--- /dev/null
+++ b/bsp/thead-smart/drivers/board.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      add T-HEAD header file csi_core.h
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "csi_core.h"
+#include "drv_usart.h"
+
+extern int __bss_end__;
+#define SYS_HEAP_BEGIN    (&__bss_end__)
+
+#include "core_rv32.h"
+
+
+extern usart_handle_t console_handle;
+extern void ioreuse_initial(void);
+
+
+/**
+ * This function will initial smartl-evb(e906) board.
+ */
+void rt_hw_board_init(void)
+{
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+    /* initialize hardware usart */
+    rt_hw_usart_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)SYS_HEAP_BEGIN, (void *)E906FD_IRAM_END);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/thead-smart/drivers/board.h b/bsp/thead-smart/drivers/board.h
new file mode 100644
index 0000000000..786246bd9a
--- /dev/null
+++ b/bsp/thead-smart/drivers/board.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      add E906 ram size
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#define APB_DEFAULT_FREQ         20000000   /* Hz */
+#define E906FD_IRAM_SIZE         128
+#define E906FD_IRAM_END          (0x20000000 + E906FD_IRAM_SIZE * 1024)
+
+#endif /* __BOARD_H__ */
diff --git a/bsp/thead-smart/drivers/board_uart.c b/bsp/thead-smart/drivers/board_uart.c
new file mode 100644
index 0000000000..d4f857f0bb
--- /dev/null
+++ b/bsp/thead-smart/drivers/board_uart.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      first implementation
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_CONSOLE
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#include "board.h"
+#include "soc.h"
+#include "ck_usart.h"
+#include "drv_usart.h"
+#include "pin_name.h"
+
+
+
+__attribute__((isr)) void ck_usart0_irqhandler(void);
+
+struct
+{
+    uint32_t base;
+    uint32_t irq;
+    void *handler;
+} 
+const sg_usart_config[CONFIG_USART_NUM] =
+{
+    {CSKY_UART_BASE, UART_IRQn, ck_usart0_irqhandler},
+};
+
+
+int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq, void **handler)
+{
+    if (idx >= CONFIG_USART_NUM) 
+    {
+        return -1;
+    }
+
+    if (base != NULL) 
+    {
+        *base = sg_usart_config[idx].base;
+    }
+
+    if (irq != NULL) 
+    {
+        *irq = sg_usart_config[idx].irq;
+    }
+
+    if (handler != NULL) 
+    {
+        *handler = sg_usart_config[idx].handler;
+    }
+
+    return idx;
+}
+
+
+#ifdef RT_USING_UART1
+#define UART_TXD1     PA10_TXD1_PWM1_XX_SIROUT1
+#define UART_RXD1     PA11_RXD1_PWM2_XX_SIRIN1
+
+static  usart_handle_t uart1_handle;
+static struct rt_serial_device  serial1;
+
+__attribute__((isr)) void ck_usart0_irqhandler(void)
+{
+    rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_RX_IND);
+}
+#endif
+
+/*
+ * UART interface
+ */
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    int ret;
+    usart_handle_t uart;
+
+    uint32_t bauds;
+    usart_mode_e mode;
+    usart_parity_e parity;
+    usart_stop_bits_e stopbits;
+    usart_data_bits_e databits;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    /* set baudrate parity...*/
+    bauds = cfg->baud_rate;
+    mode = USART_MODE_ASYNCHRONOUS;
+
+    if (cfg->parity == PARITY_EVEN)
+        parity = USART_PARITY_EVEN;
+    else if (cfg->parity == PARITY_ODD)
+        parity = USART_PARITY_ODD;
+    else
+        parity = USART_PARITY_NONE;
+
+    stopbits = USART_STOP_BITS_1 ;
+    databits = USART_DATA_BITS_8;
+
+    ret = csi_usart_config(uart, bauds, USART_MODE_ASYNCHRONOUS, parity, stopbits, databits);
+
+    if (ret < 0)
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* Disable the UART Interrupt */
+        ck_usart_clr_int_flag(uart,IER_RDA_INT_ENABLE);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* Enable the UART Interrupt */
+        ck_usart_set_int_flag(uart,IER_RDA_INT_ENABLE);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    csi_usart_putchar(uart,c);
+
+    return (1);
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+
+    ch = csi_uart_getchar(uart);
+
+    return ch;
+}
+
+const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+
+int rt_hw_usart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART1
+    serial1.ops                 = & _uart_ops;
+    serial1.config              = config;
+    serial1.config.bufsz        = 2048;
+    serial1.config.baud_rate    = 115200;
+
+    uart1_handle = csi_usart_initialize(0, NULL);
+
+    rt_hw_serial_register(&serial1,
+                          "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart1_handle);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_usart_init);
+#endif
diff --git a/bsp/thead-smart/drivers/ck_irq.c b/bsp/thead-smart/drivers/ck_irq.c
new file mode 100644
index 0000000000..8863ec7580
--- /dev/null
+++ b/bsp/thead-smart/drivers/ck_irq.c
@@ -0,0 +1,88 @@
+
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Source File for IRQ Driver
+ */
+
+#include <stdint.h>
+#include <soc.h>
+#include <csi_core.h>
+#include <csi_config.h>
+
+extern void Default_Handler(void);
+extern void (*g_irqvector[])(void);
+extern void (*g_nmivector)(void);
+
+/**
+  \brief       enable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_enable(uint32_t irq_num)
+{
+    if (NMI_EXPn != irq_num) 
+    {
+    #ifdef CONFIG_SYSTEM_SECURE
+        csi_vic_enable_sirq(irq_num);
+    #else
+        csi_vic_enable_irq(irq_num);
+    #endif
+    }
+}
+
+/**
+  \brief       disable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_disable(uint32_t irq_num)
+{
+    if (NMI_EXPn != irq_num) 
+    {
+    #ifdef CONFIG_SYSTEM_SECURE
+        csi_vic_disable_sirq(irq_num);
+    #else
+        csi_vic_disable_irq(irq_num);
+    #endif
+    }
+}
+
+/**
+  \brief       register irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \param[in]   irq_handler IRQ Handler.
+  \return      None.
+*/
+void drv_irq_register(uint32_t irq_num, void *irq_handler)
+{
+    if (NMI_EXPn != irq_num) 
+    {
+        g_irqvector[irq_num] = irq_handler;
+    } 
+    else 
+    {
+        g_nmivector = irq_handler;
+    }
+}
+
+/**
+  \brief       unregister irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_unregister(uint32_t irq_num)
+{
+    if (NMI_EXPn != irq_num) 
+    {
+        g_irqvector[irq_num] = (void *)Default_Handler;
+    } 
+    else 
+    {
+        g_nmivector = (void *)Default_Handler;
+    }
+}
diff --git a/bsp/thead-smart/drivers/ck_usart.c b/bsp/thead-smart/drivers/ck_usart.c
new file mode 100644
index 0000000000..bedec214ab
--- /dev/null
+++ b/bsp/thead-smart/drivers/ck_usart.c
@@ -0,0 +1,1141 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Source File for usart Driver
+ */
+
+#include <csi_config.h>
+#include <stdbool.h>
+#include <string.h>
+#include <drv_irq.h>
+#include <drv_usart.h>
+#include <ck_usart.h>
+#include <soc.h>
+#include <csi_core.h>
+
+#define ERR_USART(errno) (CSI_DRV_ERRNO_USART_BASE | errno)
+
+/*
+ * setting config may be accessed when the USART is not
+ * busy(USR[0]=0) and the DLAB bit(LCR[7]) is set.
+ */
+
+#define WAIT_USART_IDLE(addr)\
+    do {                       \
+        int32_t timecount = 0;  \
+        while ((addr->USR & USR_UART_BUSY) && (timecount < UART_BUSY_TIMEOUT)) {\
+            timecount++;\
+        }\
+        if (timecount >= UART_BUSY_TIMEOUT) {\
+            return ERR_USART(DRV_ERROR_TIMEOUT);\
+        }                                   \
+    } while(0)
+
+#define USART_NULL_PARAM_CHK(para) HANDLE_PARAM_CHK(para, ERR_USART(DRV_ERROR_PARAMETER))
+
+typedef struct 
+{
+    uint32_t base;
+    uint32_t irq;
+    usart_event_cb_t cb_event;           ///< Event callback
+    uint32_t rx_total_num;
+    uint32_t tx_total_num;
+    uint8_t *rx_buf;
+    uint8_t *tx_buf;
+    volatile uint32_t rx_cnt;
+    volatile uint32_t tx_cnt;
+    volatile uint32_t tx_busy;
+    volatile uint32_t rx_busy;
+    uint32_t last_tx_num;
+    uint32_t last_rx_num;
+    int32_t idx;
+} ck_usart_priv_t;
+
+extern int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq, void **handler);
+
+static ck_usart_priv_t usart_instance[CONFIG_USART_NUM];
+
+static const usart_capabilities_t usart_capabilities = 
+{
+    .asynchronous = 1,          /* supports USART (Asynchronous) mode */
+    .synchronous_master = 0,    /* supports Synchronous Master mode */
+    .synchronous_slave = 0,     /* supports Synchronous Slave mode */
+    .single_wire = 0,           /* supports USART Single-wire mode */
+    .event_tx_complete = 1,     /* Transmit completed event */
+    .event_rx_timeout = 0,      /* Signal receive character timeout event */
+};
+
+/**
+  \brief       set the bautrate of usart.
+  \param[in]   addr  usart base to operate.
+  \return      error code
+*/
+int32_t csi_usart_config_baudrate(usart_handle_t handle, uint32_t baud)
+{
+    USART_NULL_PARAM_CHK(handle);
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+
+    WAIT_USART_IDLE(addr);
+
+    /* baudrate=(seriak clock freq)/(16*divisor); algorithm :rounding*/
+    uint32_t divisor = ((drv_get_usart_freq(usart_priv->idx)  * 10) / baud) >> 4;
+
+    if ((divisor % 10) >= 5) 
+    {
+        divisor = (divisor / 10) + 1;
+    } else 
+    {
+        divisor = divisor / 10;
+    }
+
+    addr->LCR |= LCR_SET_DLAB;
+    /* DLL and DLH is lower 8-bits and higher 8-bits of divisor.*/
+    addr->DLL = divisor & 0xff;
+    addr->DLH = (divisor >> 8) & 0xff;
+    /*
+     * The DLAB must be cleared after the baudrate is setted
+     * to access other registers.
+     */
+    addr->LCR &= (~LCR_SET_DLAB);
+
+    return 0;
+}
+
+/**
+  \brief       config usart mode.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   mode    \ref usart_mode_e
+  \return      error code
+*/
+int32_t csi_usart_config_mode(usart_handle_t handle, usart_mode_e mode)
+{
+    USART_NULL_PARAM_CHK(handle);
+
+    if (mode == USART_MODE_ASYNCHRONOUS) 
+    {
+        return 0;
+    }
+
+    return ERR_USART(USART_ERROR_MODE);
+}
+
+/**
+  \brief       config usart parity.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   parity    \ref usart_parity_e
+  \return      error code
+*/
+int32_t csi_usart_config_parity(usart_handle_t handle, usart_parity_e parity)
+{
+    USART_NULL_PARAM_CHK(handle);
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    WAIT_USART_IDLE(addr);
+
+    switch (parity) 
+    {
+        case USART_PARITY_NONE:
+            /*CLear the PEN bit(LCR[3]) to disable parity.*/
+            addr->LCR &= (~LCR_PARITY_ENABLE);
+            break;
+
+        case USART_PARITY_ODD:
+            /* Set PEN and clear EPS(LCR[4]) to set the ODD parity. */
+            addr->LCR |= LCR_PARITY_ENABLE;
+            addr->LCR &= LCR_PARITY_ODD;
+            break;
+
+        case USART_PARITY_EVEN:
+            /* Set PEN and EPS(LCR[4]) to set the EVEN parity.*/
+            addr->LCR |= LCR_PARITY_ENABLE;
+            addr->LCR |= LCR_PARITY_EVEN;
+            break;
+
+        default:
+            return ERR_USART(USART_ERROR_PARITY);
+    }
+
+    return 0;
+}
+
+/**
+  \brief       config usart stop bit number.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   stopbits  \ref usart_stop_bits_e
+  \return      error code
+*/
+int32_t csi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit)
+{
+    USART_NULL_PARAM_CHK(handle);
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    WAIT_USART_IDLE(addr);
+
+    switch (stopbit) 
+    {
+        case USART_STOP_BITS_1:
+            /* Clear the STOP bit to set 1 stop bit*/
+            addr->LCR &= LCR_STOP_BIT1;
+            break;
+
+        case USART_STOP_BITS_2:
+            /*
+            * If the STOP bit is set "1",we'd gotten 1.5 stop
+            * bits when DLS(LCR[1:0]) is zero, else 2 stop bits.
+            */
+            addr->LCR |= LCR_STOP_BIT2;
+            break;
+
+        default:
+            return ERR_USART(USART_ERROR_STOP_BITS);
+    }
+
+    return 0;
+}
+
+/**
+  \brief       config usart data length.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   databits      \ref usart_data_bits_e
+  \return      error code
+*/
+int32_t csi_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits)
+{
+    USART_NULL_PARAM_CHK(handle);
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    WAIT_USART_IDLE(addr);
+    /* The word size decides by the DLS bits(LCR[1:0]), and the
+     * corresponding relationship between them is:
+     *   DLS   word size
+     *       00 -- 5 bits
+     *       01 -- 6 bits
+     *       10 -- 7 bits
+     *       11 -- 8 bits
+     */
+
+    switch (databits) 
+    {
+        case USART_DATA_BITS_5:
+            addr->LCR &= LCR_WORD_SIZE_5;
+            break;
+
+        case USART_DATA_BITS_6:
+            addr->LCR &= 0xfd;
+            addr->LCR |= LCR_WORD_SIZE_6;
+            break;
+
+        case USART_DATA_BITS_7:
+            addr->LCR &= 0xfe;
+            addr->LCR |= LCR_WORD_SIZE_7;
+            break;
+
+        case USART_DATA_BITS_8:
+            addr->LCR |= LCR_WORD_SIZE_8;
+            break;
+
+        default:
+            return ERR_USART(USART_ERROR_DATA_BITS);
+    }
+
+    return 0;
+}
+
+
+int32_t ck_usart_set_int_flag(usart_handle_t handle,uint32_t flag)
+{
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    addr->IER |= flag;
+
+    return 0;
+}
+
+int32_t ck_usart_clr_int_flag(usart_handle_t handle,uint32_t flag)
+{
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    addr->IER &= ~flag;
+
+    return 0;
+}
+
+
+/**
+  \brief       get character in query mode.
+  \param[in]   instance  usart instance to operate.
+  \param[in]   the pointer to the recieve charater.
+  \return      error code
+*/
+int32_t csi_usart_getchar(usart_handle_t handle, uint8_t *ch)
+{
+    USART_NULL_PARAM_CHK(handle);
+    USART_NULL_PARAM_CHK(ch);
+
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    while (!(addr->LSR & LSR_DATA_READY));
+
+    *ch = addr->RBR;
+
+    return 0;
+}
+
+
+/**
+  \brief       get character in query mode.
+  \param[in]   instance  usart instance to operate.
+  \param[in]   the pointer to the recieve charater.
+  \return      error code
+*/
+int csi_uart_getchar(usart_handle_t handle)
+{
+    volatile int ch;
+    USART_NULL_PARAM_CHK(handle);
+
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    ch = -1;
+
+    if (addr->LSR & LSR_DATA_READY)
+    {
+    	ch = addr->RBR & 0xff;
+    }
+
+    return ch;
+}
+
+
+/**
+  \brief       transmit character in query mode.
+  \param[in]   instance  usart instance to operate.
+  \param[in]   ch  the input charater
+  \return      error code
+*/
+int32_t csi_usart_putchar(usart_handle_t handle, uint8_t ch)
+{
+    USART_NULL_PARAM_CHK(handle);
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+    uint32_t timecount = 0;
+
+    while ((!(addr->LSR & DW_LSR_TRANS_EMPTY))) 
+    {
+        timecount++;
+
+        if (timecount >= UART_BUSY_TIMEOUT) 
+        {
+            return ERR_USART(DRV_ERROR_TIMEOUT);
+        }
+    }
+
+    addr->THR = ch;
+
+    return 0;
+
+}
+
+/**
+  \brief       interrupt service function for transmitter holding register empty.
+  \param[in]   usart_priv usart private to operate.
+*/
+void ck_usart_intr_threshold_empty(int32_t idx, ck_usart_priv_t *usart_priv)
+{
+    if (usart_priv->tx_total_num == 0) 
+    {
+        return;
+    }
+
+    volatile int i = 500;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    if (usart_priv->tx_cnt >= usart_priv->tx_total_num) 
+    {
+        addr->IER &= (~IER_THRE_INT_ENABLE);
+        usart_priv->last_tx_num = usart_priv->tx_total_num;
+
+        /* fix hardware bug */
+        while (addr->USR & USR_UART_BUSY);
+
+        i = 500;
+
+        while (i--);
+
+        usart_priv->tx_cnt = 0;
+        usart_priv->tx_busy = 0;
+        usart_priv->tx_buf = NULL;
+        usart_priv->tx_total_num = 0;
+
+        if (usart_priv->cb_event) 
+        {
+            usart_priv->cb_event(idx, USART_EVENT_SEND_COMPLETE);
+        }
+    } else 
+    {
+        /* fix hardware bug */
+        while (addr->USR & USR_UART_BUSY);
+
+        i = 500;
+
+        while (i--);
+
+        addr->THR = *((uint8_t *)usart_priv->tx_buf);
+        usart_priv->tx_cnt++;
+        usart_priv->tx_buf++;
+    }
+}
+
+/**
+  \brief        interrupt service function for receiver data available.
+  \param[in]   usart_priv usart private to operate.
+*/
+static void ck_usart_intr_recv_data(int32_t idx, ck_usart_priv_t *usart_priv)
+{
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+    uint8_t data = addr->RBR;
+
+    *((uint8_t *)usart_priv->rx_buf) = data;
+    usart_priv->rx_cnt++;
+    usart_priv->rx_buf++;
+
+    if (usart_priv->rx_cnt >= usart_priv->rx_total_num) 
+    {
+        usart_priv->last_rx_num = usart_priv->rx_total_num;
+        usart_priv->rx_cnt = 0;
+        usart_priv->rx_buf = NULL;
+        usart_priv->rx_busy = 0;
+        usart_priv->rx_total_num = 0;
+
+        if (usart_priv->cb_event) 
+        {
+            usart_priv->cb_event(idx, USART_EVENT_RECEIVE_COMPLETE);
+        }
+    }
+
+}
+
+/**
+  \brief        interrupt service function for receiver line.
+  \param[in]   usart_priv usart private to operate.
+*/
+static void ck_usart_intr_recv_line(int32_t idx, ck_usart_priv_t *usart_priv)
+{
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+    uint32_t lsr_stat = addr->LSR;
+
+    addr->IER &= (~IER_THRE_INT_ENABLE);
+
+    uint32_t timecount = 0;
+
+    while (addr->LSR & 0x1) 
+    {
+        addr->RBR;
+        timecount++;
+
+        if (timecount >= UART_BUSY_TIMEOUT) 
+        {
+            if (usart_priv->cb_event) 
+            {
+                usart_priv->cb_event(idx, USART_EVENT_RX_TIMEOUT);
+            }
+
+            return;
+        }
+    }
+
+    /** Break Interrupt bit. This is used to indicate the detection of a
+      * break sequence on the serial input data.
+      */
+    if (lsr_stat & DW_LSR_BI) 
+    {
+        if (usart_priv->cb_event) 
+        {
+            usart_priv->cb_event(idx, USART_EVENT_RX_BREAK);
+        }
+
+        return;
+    }
+
+    /** Framing Error bit. This is used to indicate the occurrence of a
+      * framing error in the receiver. A framing error occurs when the receiver
+      * does not detect a valid STOP bit in the received data.
+      */
+    if (lsr_stat & DW_LSR_FE) 
+    {
+        if (usart_priv->cb_event) 
+        {
+            usart_priv->cb_event(idx, USART_EVENT_RX_FRAMING_ERROR);
+        }
+
+        return;
+    }
+
+    /** Framing Error bit. This is used to indicate the occurrence of a
+      * framing error in the receiver. A framing error occurs when the
+      * receiver does not detect a valid STOP bit in the received data.
+      */
+    if (lsr_stat & DW_LSR_PE) 
+    {
+        if (usart_priv->cb_event) 
+        {
+            usart_priv->cb_event(idx, USART_EVENT_RX_PARITY_ERROR);
+        }
+
+        return;
+    }
+
+    /** Overrun error bit. This is used to indicate the occurrence of an overrun error.
+      * This occurs if a new data character was received before the previous data was read.
+      */
+    if (lsr_stat & DW_LSR_OE) 
+    {
+        if (usart_priv->cb_event) 
+        {
+            usart_priv->cb_event(idx, USART_EVENT_RX_OVERFLOW);
+        }
+
+        return;
+    }
+}
+/**
+  \brief        interrupt service function for character timeout.
+  \param[in]   usart_priv usart private to operate.
+*/
+static void ck_usart_intr_char_timeout(int32_t idx, ck_usart_priv_t *usart_priv)
+{
+    if ((usart_priv->rx_total_num != 0) && (usart_priv->rx_buf != NULL)) 
+    {
+        ck_usart_intr_recv_data(idx, usart_priv);
+        return;
+    }
+
+    if (usart_priv->cb_event) 
+    {
+        usart_priv->cb_event(idx, USART_EVENT_RECEIVED);
+    } else 
+    {
+        ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+        uint32_t timecount = 0;
+
+        while (addr->LSR & 0x1) 
+        {
+            addr->RBR;
+            timecount++;
+
+            if (timecount >= UART_BUSY_TIMEOUT) 
+            {
+                if (usart_priv->cb_event) 
+                {
+                    usart_priv->cb_event(idx, USART_EVENT_RX_TIMEOUT);
+                }
+
+                return;
+            }
+        }
+    }
+}
+
+/**
+  \brief       the interrupt service function.
+  \param[in]   index of usart instance.
+*/
+void ck_usart_irqhandler(int32_t idx)
+{
+    ck_usart_priv_t *usart_priv = &usart_instance[idx];
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    uint8_t intr_state = addr->IIR & 0xf;
+
+    switch (intr_state) 
+    {
+        case DW_IIR_THR_EMPTY:       /* interrupt source:transmitter holding register empty */
+            ck_usart_intr_threshold_empty(idx, usart_priv);
+            break;
+
+        case DW_IIR_RECV_DATA:       /* interrupt source:receiver data available or receiver fifo trigger level reached */
+            ck_usart_intr_char_timeout(idx, usart_priv);
+            //ck_usart_intr_recv_data(idx, usart_priv);
+            break;
+
+        case DW_IIR_RECV_LINE:
+            ck_usart_intr_recv_line(idx, usart_priv);
+            break;
+
+        case DW_IIR_CHAR_TIMEOUT:
+            ck_usart_intr_char_timeout(idx, usart_priv);
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+  \brief       Get driver capabilities.
+  \param[in]   idx usart index
+  \return      \ref usart_capabilities_t
+*/
+usart_capabilities_t csi_usart_get_capabilities(int32_t idx)
+{
+    if (idx < 0 || idx >= CONFIG_USART_NUM) 
+    {
+        usart_capabilities_t ret;
+        memset(&ret, 0, sizeof(usart_capabilities_t));
+        return ret;
+    }
+
+    return usart_capabilities;
+}
+
+/**
+  \brief       Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function
+  \param[in]   idx usart index
+  \param[in]   cb_event  Pointer to \ref usart_event_cb_t
+  \return      return usart handle if success
+*/
+usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event)
+{
+    uint32_t base = 0u;
+    uint32_t irq = 0u;
+    void *handler;
+
+    int32_t ret = target_usart_init(idx, &base, &irq, &handler);
+
+    if (ret < 0 || ret >= CONFIG_USART_NUM) 
+    {
+        return NULL;
+    }
+
+    ck_usart_priv_t *usart_priv = &usart_instance[idx];
+    usart_priv->base = base;
+    usart_priv->irq = irq;
+    usart_priv->cb_event = cb_event;
+    usart_priv->idx = idx;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    /* enable received data available */
+    addr->IER = IER_RDA_INT_ENABLE | IIR_RECV_LINE_ENABLE;
+    drv_irq_register(usart_priv->irq, handler);
+    drv_irq_enable(usart_priv->irq);
+
+    return usart_priv;
+}
+
+/**
+  \brief       De-initialize UART Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_uninitialize(usart_handle_t handle)
+{
+    USART_NULL_PARAM_CHK(handle);
+
+    ck_usart_priv_t *usart_priv = handle;
+
+    drv_irq_disable(usart_priv->irq);
+    drv_irq_unregister(usart_priv->irq);
+    usart_priv->cb_event   = NULL;
+
+    return 0;
+}
+
+/**
+  \brief       config usart mode.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   baud      baud rate
+  \param[in]   mode      \ref usart_mode_e
+  \param[in]   parity    \ref usart_parity_e
+  \param[in]   stopbits  \ref usart_stop_bits_e
+  \param[in]   bits      \ref usart_data_bits_e
+  \return      error code
+*/
+int32_t csi_usart_config(usart_handle_t handle,
+                         uint32_t baud,
+                         usart_mode_e mode,
+                         usart_parity_e parity,
+                         usart_stop_bits_e stopbits,
+                         usart_data_bits_e bits)
+{
+    int32_t ret;
+
+    /* control the data_bit of the usart*/
+    ret = csi_usart_config_baudrate(handle, baud);
+
+    if (ret < 0) 
+    {
+        return ret;
+    }
+
+    /* control mode of the usart*/
+    ret = csi_usart_config_mode(handle, mode);
+
+    if (ret < 0) 
+    {
+        return ret;
+    }
+
+    /* control the parity of the usart*/
+    ret = csi_usart_config_parity(handle, parity);
+
+    if (ret < 0) 
+    {
+        return ret;
+    }
+
+    /* control the stopbit of the usart*/
+    ret = csi_usart_config_stopbits(handle, stopbits);
+
+    if (ret < 0) 
+    {
+        return ret;
+    }
+
+    ret = csi_usart_config_databits(handle, bits);
+
+    if (ret < 0) 
+    {
+        return ret;
+    }
+
+    return 0;
+}
+
+
+/**
+  \brief       Start sending data to UART transmitter,(received data is ignored).
+               The function is non-blocking,UART_EVENT_TRANSFER_COMPLETE is signaled when transfer completes.
+               csi_usart_get_status can indicates if transmission is still in progress or pending
+  \param[in]   handle  usart handle to operate.
+  \param[in]   data  Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 1..8 data bits, uint16_t for 9..16 data bits,uint32_t for 17..32 data bits,
+  \param[in]   num   Number of data items to send
+  \return      error code
+*/
+int32_t csi_usart_send(usart_handle_t handle, const void *data, uint32_t num)
+{
+    USART_NULL_PARAM_CHK(handle);
+    USART_NULL_PARAM_CHK(data);
+
+    if (num == 0) 
+    {
+        return ERR_USART(DRV_ERROR_PARAMETER);
+    }
+
+    ck_usart_priv_t *usart_priv = handle;
+
+    usart_priv->tx_buf = (uint8_t *)data;
+    usart_priv->tx_total_num = num;
+    usart_priv->tx_cnt = 0;
+    usart_priv->tx_busy = 1;
+    usart_priv->last_tx_num = 0;
+
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+    ck_usart_intr_threshold_empty(usart_priv->idx, usart_priv);
+    /* enable the interrupt*/
+    addr->IER |= IER_THRE_INT_ENABLE;
+    return 0;
+}
+
+/**
+  \brief       Abort Send data to UART transmitter
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_send(usart_handle_t handle)
+{
+    USART_NULL_PARAM_CHK(handle);
+    ck_usart_priv_t *usart_priv = handle;
+
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+    addr->IER &= (~IER_THRE_INT_ENABLE);
+
+    usart_priv->tx_cnt = usart_priv->tx_total_num;
+    usart_priv->tx_cnt = 0;
+    usart_priv->tx_busy = 0;
+    usart_priv->tx_buf = NULL;
+    usart_priv->tx_total_num = 0;
+    return 0;
+}
+
+/**
+  \brief       Start receiving data from UART receiver.transmits the default value as specified by csi_usart_set_default_tx_value
+  \param[in]   handle  usart handle to operate.
+  \param[out]  data  Pointer to buffer for data to receive from UART receiver
+  \param[in]   num   Number of data items to receive
+  \return      error code
+*/
+int32_t csi_usart_receive(usart_handle_t handle, void *data, uint32_t num)
+{
+    USART_NULL_PARAM_CHK(handle);
+    USART_NULL_PARAM_CHK(data);
+
+    ck_usart_priv_t *usart_priv = handle;
+
+    usart_priv->rx_buf = (uint8_t *)data;   // Save receive buffer usart
+    usart_priv->rx_total_num = num;         // Save number of data to be received
+    usart_priv->rx_cnt = 0;
+    usart_priv->rx_busy = 1;
+    usart_priv->last_rx_num = 0;
+
+    return 0;
+
+}
+
+/**
+  \brief       query data from UART receiver FIFO.
+  \param[in]   handle  usart handle to operate.
+  \param[out]  data  Pointer to buffer for data to receive from UART receiver
+  \param[in]   num   Number of data items to receive
+  \return      receive fifo data num
+*/
+int32_t csi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num)
+{
+    USART_NULL_PARAM_CHK(handle);
+    USART_NULL_PARAM_CHK(data);
+
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+    int32_t recv_num = 0;
+    uint8_t *dest = (uint8_t *)data;
+
+    while (addr->LSR & 0x1) 
+    {
+        *dest++ = addr->RBR;
+        recv_num++;
+
+        if (recv_num >= num) 
+        {
+            break;
+        }
+    }
+
+    return recv_num;
+
+}
+
+/**
+  \brief       Abort Receive data from UART receiver
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_receive(usart_handle_t handle)
+{
+    USART_NULL_PARAM_CHK(handle);
+    ck_usart_priv_t *usart_priv = handle;
+
+    usart_priv->rx_cnt = usart_priv->rx_total_num;
+    return 0;
+}
+
+/**
+  \brief       Start sending/receiving data to/from UART transmitter/receiver.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver
+  \param[in]   num       Number of data items to transfer
+  \return      error code
+*/
+int32_t csi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num)
+{
+    USART_NULL_PARAM_CHK(handle);
+    return ERR_USART(DRV_ERROR_UNSUPPORTED);
+}
+
+/**
+  \brief       abort sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_transfer(usart_handle_t handle)
+{
+    USART_NULL_PARAM_CHK(handle);
+    return ERR_USART(DRV_ERROR_UNSUPPORTED);
+}
+
+/**
+  \brief       Get USART status.
+  \param[in]   handle  usart handle to operate.
+  \return      USART status \ref usart_status_t
+*/
+usart_status_t csi_usart_get_status(usart_handle_t handle)
+{
+    usart_status_t usart_status;
+
+    memset(&usart_status, 0, sizeof(usart_status_t));
+
+    if (handle == NULL) 
+    {
+        return usart_status;
+    }
+
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+    uint32_t line_status_reg    = addr->LSR;
+
+    usart_status.tx_busy = usart_priv->tx_busy;
+    usart_status.rx_busy = usart_priv->rx_busy;
+
+    if (line_status_reg & DW_LSR_BI) 
+    {
+        usart_status.rx_break = 1;
+    }
+
+    if (line_status_reg & DW_LSR_FE) 
+    {
+        usart_status.rx_framing_error = 1;
+    }
+
+    if (line_status_reg & DW_LSR_PE) 
+    {
+        usart_status.rx_parity_error = 1;
+    }
+
+    usart_status.tx_enable  = 1;
+    usart_status.rx_enable  = 1;
+
+    return usart_status;
+}
+
+/**
+  \brief       control the transmit.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   1 - enable the transmitter. 0 - disable the transmitter
+  \return      error code
+*/
+int32_t csi_usart_control_tx(usart_handle_t handle, uint32_t enable)
+{
+    USART_NULL_PARAM_CHK(handle);
+    return 0;
+}
+
+/**
+  \brief       control the receive.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   1 - enable the receiver. 0 - disable the receiver
+  \return      error code
+*/
+int32_t csi_usart_control_rx(usart_handle_t handle, uint32_t enable)
+{
+    USART_NULL_PARAM_CHK(handle);
+    return 0;
+}
+
+/**
+  \brief       control the break.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   1- Enable continuous Break transmission,0 - disable continuous Break transmission
+  \return      error code
+*/
+int32_t csi_usart_control_break(usart_handle_t handle, uint32_t enable)
+{
+    USART_NULL_PARAM_CHK(handle);
+    return ERR_USART(DRV_ERROR_UNSUPPORTED);
+}
+
+/**
+  \brief       flush receive/send data.
+  \param[in]   handle usart handle to operate.
+  \param[in]   type \ref usart_flush_type_e.
+  \return      error code
+*/
+int32_t csi_usart_flush(usart_handle_t handle, usart_flush_type_e type)
+{
+    USART_NULL_PARAM_CHK(handle);
+
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    uint32_t timecount = 0;
+
+    if (type == USART_FLUSH_WRITE) {
+        while ((!(addr->LSR & DW_LSR_TEMT))) 
+        {
+            timecount++;
+
+            if (timecount >= UART_BUSY_TIMEOUT) 
+            {
+                return ERR_USART(DRV_ERROR_TIMEOUT);
+            }
+        }
+    } else if (type == USART_FLUSH_READ) 
+    {
+        while (addr->LSR & 0x1) {
+            timecount++;
+
+            if (timecount >= UART_BUSY_TIMEOUT) 
+            {
+                return ERR_USART(DRV_ERROR_TIMEOUT);
+            }
+        }
+    } else 
+    {
+        return ERR_USART(DRV_ERROR_PARAMETER);
+    }
+
+    return 0;
+}
+
+/**
+  \brief       set interrupt mode.
+  \param[in]   handle usart handle to operate.
+  \param[in]   type \ref usart_intr_type_e.
+  \param[in]   flag 0-OFF, 1-ON.
+  \return      error code
+*/
+int32_t csi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag)
+{
+    USART_NULL_PARAM_CHK(handle);
+
+    ck_usart_priv_t *usart_priv = handle;
+    ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
+
+    switch (type) 
+    {
+        case USART_INTR_WRITE:
+            if (flag == 0) 
+            {
+                addr->IER &= ~IER_THRE_INT_ENABLE;
+            } else if (flag == 1) 
+            {
+                addr->IER |= IER_THRE_INT_ENABLE;
+            } else 
+            {
+                return ERR_USART(DRV_ERROR_PARAMETER);
+            }
+
+            break;
+
+        case USART_INTR_READ:
+            if (flag == 0) 
+            {
+                addr->IER &= ~IER_RDA_INT_ENABLE;
+            } else if (flag == 1) 
+            {
+                addr->IER |= IER_RDA_INT_ENABLE;
+            } else 
+            {
+                return ERR_USART(DRV_ERROR_PARAMETER);
+            }
+
+            break;
+
+        default:
+            return ERR_USART(DRV_ERROR_PARAMETER);
+
+    }
+
+    return 0;
+}
+
+/**
+  \brief       Get usart send data count.
+  \param[in]   handle  usart handle to operate.
+  \return      number of currently transmitted data bytes
+*/
+uint32_t csi_usart_get_tx_count(usart_handle_t handle)
+{
+    USART_NULL_PARAM_CHK(handle);
+
+    ck_usart_priv_t *usart_priv = handle;
+
+    if (usart_priv->tx_busy) 
+    {
+        return usart_priv->tx_cnt;
+    } else 
+    {
+        return usart_priv->last_tx_num;
+    }
+}
+
+/**
+  \brief       Get usart receive data count.
+  \param[in]   handle  usart handle to operate.
+  \return      number of currently received data bytes
+*/
+uint32_t csi_usart_get_rx_count(usart_handle_t handle)
+{
+    USART_NULL_PARAM_CHK(handle);
+    ck_usart_priv_t *usart_priv = handle;
+
+    if (usart_priv->rx_busy) 
+    {
+        return usart_priv->rx_cnt;
+    } else 
+    {
+        return usart_priv->last_rx_num;
+    }
+}
+
+/**
+  \brief       control usart power.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_usart_power_control(usart_handle_t handle, csi_power_stat_e state)
+{
+    USART_NULL_PARAM_CHK(handle);
+    return ERR_USART(DRV_ERROR_UNSUPPORTED);
+}
+
+/**
+  \brief       config usart flow control type.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   flowctrl_type   flow control type.\ref usart_flowctrl_type_e.
+  \return      error code
+*/
+int32_t csi_usart_config_flowctrl(usart_handle_t handle,
+                                  usart_flowctrl_type_e flowctrl_type)
+{
+    USART_NULL_PARAM_CHK(handle);
+
+    switch (flowctrl_type) 
+    {
+        case USART_FLOWCTRL_CTS:
+            return ERR_USART(DRV_ERROR_UNSUPPORTED);
+
+        case USART_FLOWCTRL_RTS:
+            return ERR_USART(DRV_ERROR_UNSUPPORTED);
+
+        case USART_FLOWCTRL_CTS_RTS:
+            return ERR_USART(DRV_ERROR_UNSUPPORTED);
+            break;
+
+        case USART_FLOWCTRL_NONE:
+            return ERR_USART(DRV_ERROR_UNSUPPORTED);
+            break;
+
+        default:
+            return ERR_USART(DRV_ERROR_UNSUPPORTED);
+    }
+
+    return 0;
+}
+
+
+/**
+  \brief       config usart clock Polarity and Phase.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   cpol    Clock Polarity.\ref usart_cpol_e.
+  \param[in]   cpha    Clock Phase.\ref usart_cpha_e.
+  \return      error code
+*/
+int32_t csi_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha)
+{
+    USART_NULL_PARAM_CHK(handle);
+    return ERR_USART(DRV_ERROR_UNSUPPORTED);
+}
+
diff --git a/bsp/thead-smart/drivers/ck_usart.h b/bsp/thead-smart/drivers/ck_usart.h
new file mode 100644
index 0000000000..bdaba45c4c
--- /dev/null
+++ b/bsp/thead-smart/drivers/ck_usart.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for usart driver
+ */
+
+#ifndef __CK_USART_H
+#define __CK_USART_H
+
+#include <stdio.h>
+#include "errno.h"
+#include "soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BAUDRATE_DEFAULT	19200
+#define UART_BUSY_TIMEOUT       1000000
+#define UART_RECEIVE_TIMEOUT    1000
+#define UART_TRANSMIT_TIMEOUT   1000
+#define UART_MAX_FIFO	        0x10
+/* UART register bit definitions */
+
+#define USR_UART_BUSY           0x01
+#define USR_UART_TFE            0x04
+#define USR_UART_RFNE           0x08
+#define LSR_DATA_READY          0x01
+#define LSR_THR_EMPTY           0x20
+#define IER_RDA_INT_ENABLE      0x01
+#define IER_THRE_INT_ENABLE     0x02
+#define IIR_RECV_LINE_ENABLE    0x04
+#define IIR_NO_ISQ_PEND         0x01
+
+#define LCR_SET_DLAB            0x80   /* enable r/w DLR to set the baud rate */
+#define LCR_PARITY_ENABLE       0x08   /* parity enabled */
+#define LCR_PARITY_EVEN         0x10   /* Even parity enabled */
+#define LCR_PARITY_ODD          0xef   /* Odd parity enabled */
+#define LCR_WORD_SIZE_5         0xfc   /* the data length is 5 bits */
+#define LCR_WORD_SIZE_6         0x01   /* the data length is 6 bits */
+#define LCR_WORD_SIZE_7         0x02   /* the data length is 7 bits */
+#define LCR_WORD_SIZE_8         0x03   /* the data length is 8 bits */
+#define LCR_STOP_BIT1           0xfb   /* 1 stop bit */
+#define LCR_STOP_BIT2           0x04   /* 1.5 stop bit */
+
+#define DW_LSR_PFE              0x80
+#define DW_LSR_TEMT             0x40
+#define DW_LSR_THRE             0x40
+#define DW_LSR_BI               0x10
+#define DW_LSR_FE               0x08
+#define DW_LSR_PE               0x04
+#define DW_LSR_OE               0x02
+#define DW_LSR_DR               0x01
+#define DW_LSR_TRANS_EMPTY      0x20
+
+#define DW_IIR_THR_EMPTY        0x02    /* threshold empty */
+#define DW_IIR_RECV_DATA        0x04    /* received data available */
+#define DW_IIR_RECV_LINE        0x06    /* receiver line status */
+#define DW_IIR_CHAR_TIMEOUT     0x0c    /* character timeout */
+
+typedef struct
+{
+    union 
+    {
+        __IM uint32_t RBR;           /* Offset: 0x000 (R/ )  Receive buffer register */
+        __OM uint32_t THR;           /* Offset: 0x000 ( /W)  Transmission hold register */
+        __IOM uint32_t DLL;          /* Offset: 0x000 (R/W)  Clock frequency division low section register */
+    };
+    union 
+    {
+        __IOM uint32_t DLH;          /* Offset: 0x004 (R/W)  Clock frequency division high section register */
+        __IOM uint32_t IER;          /* Offset: 0x004 (R/W)  Interrupt enable register */
+    };
+    __IM uint32_t IIR;             /* Offset: 0x008 (R/ )  Interrupt indicia register */
+    __IOM uint32_t LCR;            /* Offset: 0x00C (R/W)  Transmission control register */
+    uint32_t RESERVED0;
+    __IM uint32_t LSR;             /* Offset: 0x014 (R/ )  Transmission state register */
+    __IM uint32_t MSR;             /* Offset: 0x018 (R/ )  Modem state register */
+    uint32_t RESERVED1[24];
+    __IM uint32_t USR;             /* Offset: 0x07c (R/ )  UART state register */
+} ck_usart_reg_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CK_USART_H */
+
diff --git a/bsp/thead-smart/drivers/core_rv32.h b/bsp/thead-smart/drivers/core_rv32.h
new file mode 100644
index 0000000000..87fccfba72
--- /dev/null
+++ b/bsp/thead-smart/drivers/core_rv32.h
@@ -0,0 +1,1130 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI RV32 Core Peripheral Access Layer Header File
+ */
+
+#ifndef __CORE_RV32_H_GENERIC
+#define __CORE_RV32_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CSI definitions
+ ******************************************************************************/
+/**
+  \ingroup RV32
+  @{
+ */
+
+#ifndef __RV32
+#define __RV32                (0x01U)
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_RV32_H_GENERIC */
+
+#ifndef __CSI_GENERIC
+
+#ifndef __CORE_RV32_H_DEPENDANT
+#define __CORE_RV32_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#ifndef __RV32_REV
+#define __RV32_REV               0x0000U
+#endif
+
+#ifndef __VIC_PRIO_BITS
+#define __VIC_PRIO_BITS           2U
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    1U
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             1U
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          1U
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          1U
+#endif
+
+#include <csi_rv32_gcc.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CSI_glob_defs CSI Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define     __I      volatile             /*!< Defines 'read only' permissions */
+#else
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group CK802 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core CLIC Register
+ ******************************************************************************/
+/**
+  \defgroup CSI_core_register Defines and Type Definitions
+  \brief Type definitions and defines for CK80X processor based devices.
+*/
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_CLIC Core-Local Interrupt Controller (CLIC)
+  \brief      Type definitions for the CLIC Registers
+  @{
+ */
+
+/**
+  \brief Access to the structure of a vector interrupt controller.
+ */
+typedef struct
+{
+    __IOM uint8_t IP;           /*!< Offset: 0x000 (R/W)  Interrupt set pending register */
+    __IOM uint8_t IE;           /*!< Offset: 0x004 (R/W)  Interrupt set enable register */
+    __IOM uint8_t ATTR;         /*!< Offset: 0x008 (R/W)  Interrupt set attribute register */
+    __IOM uint8_t CTL;          /*!< Offset: 0x00C (R/W)  Interrupt control register */
+} CLIC_INT_Control;
+
+typedef struct
+{
+    __IOM uint32_t CLICCFG:8;                 /*!< Offset: 0x000 (R/W)  CLIC configure register */
+    __IM  uint32_t CLICINFO;
+    __IOM uint32_t MINTTHRESH;
+    uint32_t RESERVED[1021];
+    CLIC_INT_Control CLICINT[4096];
+} CLIC_Type;
+
+#define CLIC_INFO_CLICINTCTLBITS_Pos           21U
+#define CLIC_INFO_CLICINTCTLBITS_Msk           (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos)
+
+#define CLIC_INTIP_IP_Pos                      0U                                    /*!< CLIC INTIP: IP Position */
+#define CLIC_INTIP_IP_Msk                      (0x1UL << CLIC_INTIP_IP_Pos)          /*!< CLIC INTIP: IP Mask */
+
+#define CLIC_INTIE_IE_Pos                      0U                                    /*!< CLIC INTIE: IE Position */
+#define CLIC_INTIE_IE_Msk                      (0x1UL << CLIC_INTIE_IE_Pos)          /*!< CLIC INTIE: IE Mask */
+
+#define CLIC_INTIE_T_Pos                       7U                                    /*!< CLIC INTIE: T Position */
+#define CLIC_INTIE_T_Msk                       (0x1UL << CLIC_INTIE_T_Pos)           /*!< CLIC INTIE: T Mask */
+
+#define CLIC_INTATTR_TRIG_Pos                  1U                                    /*!< CLIC INTATTR: TRIG Position */
+#define CLIC_INTATTR_TRIG_Msk                  (0x3UL << CLIC_INTATTR_TRIG_Pos)      /*!< CLIC INTATTR: TRIG Mask */
+
+#define CLIC_INTATTR_SHV_Pos                   0U                                    /*!< CLIC INTATTR: SHV Position */
+#define CLIC_INTATTR_SHV_Msk                   (0x1UL << CLIC_INTATTR_SHV_Pos)       /*!< CLIC INTATTR: SHV Mask */
+
+#define CLIC_INTCFG_NVBIT_Pos                  5U                                    /*!< CLIC INTCFG: NVBIT Position */
+#define CLIC_INTCFG_NVBIT_Msk                  (0x1UL << CLIC_INTCFG_NVBIT_Pos)      /*!< CLIC INTCFG: NVBIT Mask */
+
+#define CLIC_INTCFG_PRIO_Pos                   5U                                    /*!< CLIC INTCFG: INTCFG Position */
+#define CLIC_INTCFG_PRIO_Msk                   (0x7UL << CLIC_INTCFG_PRIO_Pos)       /*!< CLIC INTCFG: INTCFG Mask */
+
+#define CLIC_CLICCFG_NVBIT_Pos                 0U                                    /*!< CLIC CLICCFG: NVBIT Position */
+#define CLIC_CLICCFG_NVBIT_Msk                 (0x1UL << CLIC_CLICCFG_NVBIT_Pos)     /*!< CLIC CLICCFG: NVBIT Mask */
+
+#define CLIC_CLICCFG_NLBIT_Pos                 1U                                    /*!< CLIC CLICCFG: NLBIT Position */
+#define CLIC_CLICCFG_NLBIT_Msk                 (0xFUL << CLIC_CLICCFG_NLBIT_Pos)     /*!< CLIC CLICCFG: NLBIT Mask */
+
+#define CLIC_CLICCFG_NMBIT_Pos                 5U                                    /*!< CLIC CLICCFG: NMBIT Position */
+#define CLIC_CLICCFG_NMBIT_Msk                 (0x3UL << CLIC_CLICCFG_NMBIT_Pos)     /*!< CLIC CLICCFG: NMBIT Mask */
+
+/*@} end of group CSI_CLIC */
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_PMP Physical Memory Protection (PMP)
+  \brief      Type definitions for the PMP Registers
+  @{
+ */
+
+#define PMP_PMPCFG_R_Pos                       0U                                    /*!< PMP PMPCFG: R Position */
+#define PMP_PMPCFG_R_Msk                       (0x1UL << PMP_PMPCFG_R_Pos)           /*!< PMP PMPCFG: R Mask */
+
+#define PMP_PMPCFG_W_Pos                       1U                                    /*!< PMP PMPCFG: W Position */
+#define PMP_PMPCFG_W_Msk                       (0x1UL << PMP_PMPCFG_W_Pos)           /*!< PMP PMPCFG: W Mask */
+
+#define PMP_PMPCFG_X_Pos                       2U                                    /*!< PMP PMPCFG: X Position */
+#define PMP_PMPCFG_X_Msk                       (0x1UL << PMP_PMPCFG_X_Pos)           /*!< PMP PMPCFG: X Mask */
+
+#define PMP_PMPCFG_A_Pos                       3U                                    /*!< PMP PMPCFG: A Position */
+#define PMP_PMPCFG_A_Msk                       (0x3UL << PMP_PMPCFG_A_Pos)           /*!< PMP PMPCFG: A Mask */
+
+#define PMP_PMPCFG_L_Pos                       7U                                    /*!< PMP PMPCFG: L Position */
+#define PMP_PMPCFG_L_Msk                       (0x1UL << PMP_PMPCFG_L_Pos)           /*!< PMP PMPCFG: L Mask */
+
+typedef enum
+{
+    REGION_SIZE_4B       = -1,
+    REGION_SIZE_8B       = 0,
+    REGION_SIZE_16B      = 1,
+    REGION_SIZE_32B      = 2,
+    REGION_SIZE_64B      = 3,
+    REGION_SIZE_128B     = 4,
+    REGION_SIZE_256B     = 5,
+    REGION_SIZE_512B     = 6,
+    REGION_SIZE_1KB      = 7,
+    REGION_SIZE_2KB      = 8,
+    REGION_SIZE_4KB      = 9,
+    REGION_SIZE_8KB      = 10,
+    REGION_SIZE_16KB     = 11,
+    REGION_SIZE_32KB     = 12,
+    REGION_SIZE_64KB     = 13,
+    REGION_SIZE_128KB    = 14,
+    REGION_SIZE_256KB    = 15,
+    REGION_SIZE_512KB    = 16,
+    REGION_SIZE_1MB      = 17,
+    REGION_SIZE_2MB      = 18,
+    REGION_SIZE_4MB      = 19,
+    REGION_SIZE_8MB      = 20,
+    REGION_SIZE_16MB     = 21,
+    REGION_SIZE_32MB     = 22,
+    REGION_SIZE_64MB     = 23,
+    REGION_SIZE_128MB    = 24,
+    REGION_SIZE_256MB    = 25,
+    REGION_SIZE_512MB    = 26,
+    REGION_SIZE_1GB      = 27,
+    REGION_SIZE_2GB      = 28,
+    REGION_SIZE_4GB      = 29,
+    REGION_SIZE_8GB      = 30,
+    REGION_SIZE_16GB     = 31
+} region_size_e;
+
+typedef enum
+{
+    ADDRESS_MATCHING_TOR   = 1,
+    ADDRESS_MATCHING_NAPOT = 3
+} address_matching_e;
+
+typedef struct
+{
+    uint32_t r: 1;           /* readable enable */
+    uint32_t w: 1;           /* writeable enable */
+    uint32_t x: 1;           /* execable enable */
+    address_matching_e a: 2; /* address matching mode */
+    uint32_t reserved: 2;    /* reserved */
+    uint32_t l: 1;           /* lock enable */
+} mpu_region_attr_t;
+
+/*@} end of group CSI_PMP */
+
+/* CACHE Register Definitions */
+#define CACHE_MHCR_L0BTB_Pos                   12U                                           /*!< CACHE MHCR: L0BTB Position */
+#define CACHE_MHCR_L0BTB_Msk                   (0x1UL << CACHE_MHCR_L0BTB_Pos)               /*!< CACHE MHCR: WA Mask */
+
+#define CACHE_MHCR_BPE_Pos                     5U                                            /*!< CACHE MHCR: BPE Position */
+#define CACHE_MHCR_BPE_Msk                     (0x1UL << CACHE_MHCR_BPE_Pos)                 /*!< CACHE MHCR: BPE Mask */
+
+#define CACHE_MHCR_RS_Pos                      4U                                            /*!< CACHE MHCR: RS Position */
+#define CACHE_MHCR_RS_Msk                      (0x1UL << CACHE_MHCR_RS_Pos)                  /*!< CACHE MHCR: RS Mask */
+
+#define CACHE_MHCR_WA_Pos                      3U                                            /*!< CACHE MHCR: WA Position */
+#define CACHE_MHCR_WA_Msk                      (0x1UL << CACHE_MHCR_WA_Pos)                  /*!< CACHE MHCR: WA Mask */
+
+#define CACHE_MHCR_WB_Pos                      2U                                            /*!< CACHE MHCR: WB Position */
+#define CACHE_MHCR_WB_Msk                      (0x1UL << CACHE_MHCR_WB_Pos)                  /*!< CACHE MHCR: WB Mask */
+
+#define CACHE_MHCR_DE_Pos                      1U                                            /*!< CACHE MHCR: DE Position */
+#define CACHE_MHCR_DE_Msk                      (0x1UL << CACHE_MHCR_DE_Pos)                  /*!< CACHE MHCR: DE Mask */
+
+#define CACHE_MHCR_IE_Pos                      0U                                            /*!< CACHE MHCR: IE Position */
+#define CACHE_MHCR_IE_Msk                      (0x1UL << CACHE_MHCR_IE_Pos)                  /*!< CACHE MHCR: IE Mask */
+
+#define CACHE_INV_ADDR_Pos                     5U
+#define CACHE_INV_ADDR_Msk                     (0xFFFFFFFFUL << CACHE_INV_ADDR_Pos)
+
+/*@} end of group CSI_CACHE */
+
+
+/**
+  \ingroup  CSI_core_register
+  \defgroup CSI_SysTick     System Tick Timer (CORET)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  The data structure of the access system timer.
+ */
+typedef struct
+{
+    __IOM unsigned long long MTIMECMP;            /*!< Offset: 0x000 (R/W) Timer compare register */
+    uint32_t RESERVED[8187];
+    __IM  unsigned long long MTIME;               /*!< Offset: 0x7FFC (R)  Timer current register */
+} CORET_Type;
+
+/*@} end of group CSI_SysTick */
+
+/**
+  \ingroup  CSI_core_register
+  \defgroup CSI_DCC
+  \brief    Type definitions for the DCC.
+  @{
+ */
+
+/**
+  \brief  Access to the data structure of DCC.
+ */
+typedef struct
+{
+    uint32_t RESERVED0[13U];
+    __IOM uint32_t HCR;                    /*!< Offset: 0x034 (R/W) */
+    __IM  uint32_t EHSR;                   /*!< Offset: 0x03C (R/ ) */
+    uint32_t RESERVED1[6U];
+    union {
+        __IM uint32_t DERJW;               /*!< Offset: 0x058 (R/ )  Data exchange register CPU read*/
+        __OM uint32_t DERJR;               /*!< Offset: 0x058 ( /W)  Data exchange register CPU writer*/
+    };
+
+} DCC_Type;
+
+#define DCC_HCR_JW_Pos                   18U                                            /*!< DCC HCR: jw_int_en Position */
+#define DCC_HCR_JW_Msk                   (1UL << DCC_HCR_JW_Pos)                        /*!< DCC HCR: jw_int_en Mask */
+
+#define DCC_HCR_JR_Pos                   19U                                            /*!< DCC HCR: jr_int_en Position */
+#define DCC_HCR_JR_Msk                   (1UL << DCC_HCR_JR_Pos)                        /*!< DCC HCR: jr_int_en Mask */
+
+#define DCC_EHSR_JW_Pos                  1U                                             /*!< DCC EHSR: jw_vld Position */
+#define DCC_EHSR_JW_Msk                  (1UL << DCC_EHSR_JW_Pos)                       /*!< DCC EHSR: jw_vld Mask */
+
+#define DCC_EHSR_JR_Pos                  2U                                             /*!< DCC EHSR: jr_vld Position */
+#define DCC_EHSR_JR_Msk                  (1UL << DCC_EHSR_JR_Pos)                       /*!< DCC EHSR: jr_vld Mask */
+
+/*@} end of group CSI_DCC */
+
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CSI_core_bitfield */
+
+/**
+  \ingroup    CSI_core_register
+  \defgroup   CSI_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of CK802 Hardware */
+#define TCIP_BASE           (0xE000E000UL)                            /*!< Titly Coupled IP Base Address */
+#define CORET_BASE          (0xE0004000UL)                            /*!< CORET Base Address */
+#define CLIC_BASE           (0xE0800000UL)                            /*!< CLIC Base Address */
+#define DCC_BASE            (0xE4010000UL)                            /*!< DCC Base Address */
+#define CACHE_BASE          (TCIP_BASE +  0x1000UL)                   /*!< CACHE Base Address */
+
+#define CORET               ((CORET_Type   *)     CORET_BASE  )       /*!< SysTick configuration struct */
+#define CLIC                ((CLIC_Type    *)     CLIC_BASE   )       /*!< CLIC configuration struct */
+#define DCC                 ((DCC_Type     *)     DCC_BASE    )       /*!< DCC configuration struct */
+#define CACHE               ((CACHE_Type   *)     CACHE_BASE  )       /*!< cache configuration struct */
+
+/*@} */
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core VIC Functions
+  - Core CORET Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+/* ##########################   VIC functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_VICFunctions VIC Functions
+  \brief    Functions that manage interrupts and exceptions via the VIC.
+  @{
+ */
+
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    5UL)      )
+#define _IP2_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+/**
+  \brief   Enable External Interrupt
+  \details Enable a device-specific interrupt in the VIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
+{
+    CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk;
+}
+
+/**
+  \brief   Disable External Interrupt
+  \details Disable a device-specific interrupt in the VIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
+{
+    CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk;
+}
+
+/**
+  \brief   Enable External Secure Interrupt
+  \details Enable a secure device-specific interrupt in the VIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
+{
+    CLIC->CLICINT[IRQn].IE |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
+}
+
+/**
+  \brief   Disable External Secure Interrupt
+  \details Disable a secure device-specific interrupt in the VIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
+{
+    CLIC->CLICINT[IRQn].IE &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
+}
+
+/**
+  \brief   Check Interrupt is Enabled or not
+  \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not enabled.
+  \return             1  Interrupt status is enabled.
+ */
+__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
+{
+    return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk);
+}
+
+/**
+  \brief   Check Interrupt is Pending or not
+  \details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
+{
+    return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk);
+}
+
+/**
+  \brief   Set Pending Interrupt
+  \details Set the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
+{
+    CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk;
+}
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clear the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
+{
+    CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk;
+}
+
+/**
+  \brief   Set Interrupt Priority
+  \details Set the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
+{
+    uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
+    CLIC->CLICINT[IRQn].CTL = (CLIC->CLICINT[IRQn].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (priority << (8 - nlbits));
+}
+
+/**
+  \brief   Get Interrupt Priority
+  \details Read the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
+{
+    uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
+    return CLIC->CLICINT[IRQn].CTL >> (8 - nlbits);
+}
+
+/**
+  \brief   Set interrupt handler
+  \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]   handler  Interrupt handler.
+ */
+__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
+{
+    if (IRQn >= 0 && IRQn < 1024) {
+        uint32_t *vectors = (uint32_t *)__get_MTVT();
+        vectors[IRQn] = handler;
+    }
+}
+
+/**
+  \brief   Get interrupt handler
+  \details Get the address of interrupt handler function.
+  \param [in]      IRQn  Interrupt number.
+ */
+__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
+{
+    if (IRQn >= 0 && IRQn < 1024) {
+        uint32_t *vectors = (uint32_t *)__get_MTVT();
+        return (uint32_t)vectors[IRQn];
+    }
+
+    return 0;
+}
+
+/*@} end of CSI_Core_VICFunctions */
+
+/* ##########################   PMP functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_PMPFunctions PMP Functions
+  \brief    Functions that manage interrupts and exceptions via the VIC.
+  @{
+ */
+
+/**
+  \brief  configure memory protected region.
+  \details
+  \param [in]  idx        memory protected region (0, 1, 2, ..., 15).
+  \param [in]  base_addr  base address must be aligned with page size.
+  \param [in]  size       \ref region_size_e. memory protected region size.
+  \param [in]  attr       \ref region_size_t. memory protected region attribute.
+  \param [in]  enable     enable or disable memory protected region.
+  */
+__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
+                                           mpu_region_attr_t attr, uint32_t enable)
+{
+    uint8_t  pmpxcfg = 0;
+    uint32_t addr = 0;
+
+    if (idx > 15) {
+        return;
+    }
+
+    if (!enable) {
+        attr.a = 0;
+    }
+
+    if (attr.a == ADDRESS_MATCHING_TOR) {
+        addr = base_addr >> 2;
+    } else {
+        if (size == REGION_SIZE_4B) {
+            addr = base_addr >> 2;
+            attr.a = 2;
+        } else {
+            addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1);
+        }
+    }
+
+    __set_PMPADDRx(idx, addr);
+
+    pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) |
+               (attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) |
+               (attr.l << PMP_PMPCFG_L_Pos);
+
+    __set_PMPxCFG(idx, pmpxcfg);
+}
+
+/**
+  \brief  disable mpu region by idx.
+  \details
+  \param [in]  idx        memory protected region (0, 1, 2, ..., 15).
+  */
+__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
+{
+    __set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk));
+}
+
+/*@} end of CSI_Core_PMPFunctions */
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+
+/**
+  \brief   CORE timer Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \param [in]  IRQn   core timer Interrupt number.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
+{
+    if (CORET->MTIMECMP) {
+        CORET->MTIMECMP = CORET->MTIMECMP + ticks;
+    } else {
+        CORET->MTIMECMP = CORET->MTIME + ticks;
+    }
+    return (0UL);
+}
+
+/**
+  \brief   get CORE timer reload value
+  \return          CORE timer counter value.
+ */
+__STATIC_INLINE uint32_t csi_coret_get_load(void)
+{
+    return CORET->MTIMECMP & 0xFFFFFFFF;
+}
+
+/**
+  \brief   get CORE timer reload high value
+  \return          CORE timer counter value.
+ */
+__STATIC_INLINE uint32_t csi_coret_get_loadh(void)
+{
+    return (CORET->MTIMECMP >> 32) & 0xFFFFFFFF;
+}
+
+/**
+  \brief   get CORE timer counter value
+  \return          CORE timer counter value.
+ */
+__STATIC_INLINE uint32_t csi_coret_get_value(void)
+{
+    return CORET->MTIME & 0xFFFFFFFF;
+}
+
+/**
+  \brief   get CORE timer counter high value
+  \return          CORE timer counter value.
+ */
+__STATIC_INLINE uint32_t csi_coret_get_valueh(void)
+{
+    return (CORET->MTIME >> 32) & 0xFFFFFFFF;
+}
+
+/*@} end of CSI_Core_SysTickFunctions */
+
+/* ##################################### DCC function ########################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_core_DebugFunctions HAD Functions
+  \brief    Functions that access the HAD debug interface.
+  @{
+ */
+
+/**
+  \brief   HAD Send Character
+  \details Transmits a character via the HAD channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
+{
+    DCC->DERJR = (uint8_t)ch;
+
+    return (ch);
+}
+
+
+/**
+  \brief   HAD Receive Character
+  \details Inputs a character via the external variable \ref HAD_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t csi_had_receive_char(void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
+        ch = DCC->DERJW;
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   HAD Check Character
+  \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t csi_had_check_char(void)
+{
+    return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR);                              /* no character available */
+}
+
+/*@} end of CSI_core_DebugFunctions */
+
+
+/* ##########################  sleep and Reset functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_SleepAndResetFunctions Sleep and Reset Functions
+  \brief    Functions that configure Sleep and Reset.
+  @{
+ */
+
+
+/* MEXSTATUS Register Definitions */
+#define MEXSTATUS_RESET_Pos                           0U
+#define MEXSTATUS_RESET_Msk                      (0x3UL << MEXSTATUS_RESET_Pos)                                             /*!< MEXSTATUS: RESET Position */
+#define MEXSTATUS_SLEEP_Pos                           2U
+#define MEXSTATUS_SLEEP_Msk                      (0x3UL << MEXSTATUS_SLEEP_Pos)                                             /*!< MEXSTATUS: RESET Position */
+/*@} end of group CSI_MEXSTATUS */
+
+
+
+/**
+  \brief   CPU System Reset
+  \details Triggle CPU System Reset
+  */
+__STATIC_INLINE void csi_system_reset (void)
+{
+    uint32_t mexstatus;
+    mexstatus = __get_MEXSTATUS();
+    mexstatus &= (~(MEXSTATUS_RESET_Msk));
+    mexstatus |= (uint32_t)(0x2 << MEXSTATUS_RESET_Pos);
+    __set_MEXSTATUS(mexstatus);
+}
+
+/**
+  \brief   CPU Core Reset
+  \details Triggle CPU Core Reset
+  */
+__STATIC_INLINE void csi_core_reset (void)
+{
+    uint32_t mexstatus;
+    mexstatus = __get_MEXSTATUS();
+    mexstatus &= (~(MEXSTATUS_RESET_Msk));
+    mexstatus |= (uint32_t)(0x1 << MEXSTATUS_RESET_Pos);
+    __set_MEXSTATUS(mexstatus);
+}
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CSI_Core_FunctionInterface
+  \defgroup CSI_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void csi_icache_enable (void)
+{
+#if (__ICACHE_PRESENT == 1U)
+    uint32_t cache;
+    __DSB();
+    __ISB();
+    __ICACHE_IALL();
+    cache = __get_MHCR();
+    cache |= CACHE_MHCR_IE_Msk;
+    __set_MHCR(cache);
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void csi_icache_disable (void)
+{
+#if (__ICACHE_PRESENT == 1U)
+    uint32_t cache;
+    __DSB();
+    __ISB();
+    cache = __get_MHCR();
+    cache &= ~CACHE_MHCR_IE_Msk;            /* disable icache */
+    __set_MHCR(cache);
+    __ICACHE_IALL();                        /* invalidate all icache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void csi_icache_invalid (void)
+{
+#if (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    __ICACHE_IALL();                        /* invalidate all icache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  \note    I-Cache also turns on.
+  */
+__STATIC_INLINE void csi_dcache_enable (void)
+{
+#if (__DCACHE_PRESENT == 1U)
+    uint32_t cache;
+    __DSB();
+    __ISB();
+    __DCACHE_IALL();                        /* invalidate all dcache */
+    cache = __get_MHCR();
+    cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk);      /* enable all Cache */
+    __set_MHCR(cache);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  \note    I-Cache also turns off.
+  */
+__STATIC_INLINE void csi_dcache_disable (void)
+{
+#if (__DCACHE_PRESENT == 1U)
+    uint32_t cache;
+    __DSB();
+    __ISB();
+    cache = __get_MHCR();
+    cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */
+    __set_MHCR(cache);
+    __DCACHE_IALL();                             /* invalidate all Cache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  \note    I-Cache also invalid
+  */
+__STATIC_INLINE void csi_dcache_invalid (void)
+{
+#if (__DCACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    __DCACHE_IALL();                            /* invalidate all Cache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  \note    I-Cache also cleans
+  */
+__STATIC_INLINE void csi_dcache_clean (void)
+{
+#if (__DCACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    __DCACHE_CALL();                                     /* clean all Cache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  \note    I-Cache also flush.
+  */
+__STATIC_INLINE void csi_dcache_clean_invalid (void)
+{
+#if (__DCACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    __DCACHE_CIALL();                                   /* clean and inv all Cache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+#if (__DCACHE_PRESENT == 1U)
+    int32_t op_size = dsize + (uint32_t)addr % 32;
+    uint32_t op_addr = (uint32_t)addr;
+    int32_t linesize = 32;
+
+    __DSB();
+
+    while (op_size > 0) {
+        __DCACHE_IPA(op_addr);
+        op_addr += linesize;
+        op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+
+#if (__DCACHE_PRESENT == 1)
+    int32_t op_size = dsize + (uint32_t)addr % 32;
+    uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk;
+    int32_t linesize = 32;
+
+    __DSB();
+
+    while (op_size > 0) {
+        __DCACHE_CPA(op_addr);
+        op_addr += linesize;
+        op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
+*/
+__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+#if (__DCACHE_PRESENT == 1U)
+    int32_t op_size = dsize + (uint32_t)addr % 32;
+    uint32_t op_addr = (uint32_t) addr;
+    int32_t linesize = 32;
+
+    __DSB();
+
+    while (op_size > 0) {
+        __DCACHE_CIPA(op_addr);
+        op_addr += linesize;
+        op_size -= linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+/**
+  \brief   setup cacheable range Cache
+  \details setup Cache range
+  */
+__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
+{
+    ;
+}
+
+/**
+  \brief   Enable cache profile
+  \details Turns on Cache profile
+  */
+__STATIC_INLINE void csi_cache_enable_profile (void)
+{
+    ;
+}
+
+/**
+  \brief   Disable cache profile
+  \details Turns off Cache profile
+  */
+__STATIC_INLINE void csi_cache_disable_profile (void)
+{
+    ;
+}
+
+/**
+  \brief   Reset cache profile
+  \details Reset Cache profile
+  */
+__STATIC_INLINE void csi_cache_reset_profile (void)
+{
+    ;
+}
+
+/**
+  \brief   cache access times
+  \details Cache access times
+  \note    every 256 access add 1.
+  \return          cache access times, actual times should be multiplied by 256
+  */
+__STATIC_INLINE uint32_t csi_cache_get_access_time (void)
+{
+    return 0;
+}
+
+/**
+  \brief   cache miss times
+  \details Cache miss times
+  \note    every 256 miss add 1.
+  \return          cache miss times, actual times should be multiplied by 256
+  */
+__STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
+{
+    return 0;
+}
+
+/*@} end of CSI_Core_CacheFunctions */
+
+/*@} end of CSI_core_DebugFunctions */
+
+/* ##################################    IRQ Functions  ############################################ */
+
+/**
+  \brief   Save the Irq context
+  \details save the psr result before disable irq.
+ */
+__STATIC_INLINE uint32_t csi_irq_save(void)
+{
+    uint32_t result;
+    result = __get_MSTATUS();
+    __disable_irq();
+    return(result);
+}
+
+/**
+  \brief   Restore the Irq context
+  \details restore saved primask state.
+  \param [in]      irq_state  psr irq state.
+ */
+__STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
+{
+    __set_MSTATUS(irq_state);
+}
+
+/*@} end of IRQ Functions */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_RV32_H_DEPENDANT */
+
+#endif /* __CSI_GENERIC */
diff --git a/bsp/thead-smart/drivers/csi_config.h b/bsp/thead-smart/drivers/csi_config.h
new file mode 100644
index 0000000000..75185caff4
--- /dev/null
+++ b/bsp/thead-smart/drivers/csi_config.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      config file
+ */
+
+/* csi_config.h -- Autogenerated! Do not edit. */
+
+#ifndef __CSI_CONFIG_H
+#define __CSI_CONFIG_H
+
+#define CONFIG_ARCH_RV32 1
+#define CONFIG_CPU_E906FD 1
+#define CONFIG_RV32_CORETIM 1
+#define CONFIG_CHIP_SMARTL_RV32 1
+#define CONFIG_BOARD_SMARTL_E906_EVB 1
+#define CONFIG_BOARD_NAME_STR "smartl_e906_evb"
+#define CONFIG_SUPPORT_TSPEND 1
+#define CONFIG_ARCH_INTERRUPTSTACK 4096
+#define CONFIG_NEWLIB_WRAP 1
+#define CONFIG_USER_DEFINED_LD_DIR_STR ""
+
+#define CONFIG_KERNEL_RTTHREAD 1
+#endif /* __CONFIG_H */
+
diff --git a/bsp/thead-smart/drivers/csi_core.h b/bsp/thead-smart/drivers/csi_core.h
new file mode 100644
index 0000000000..49659a499b
--- /dev/null
+++ b/bsp/thead-smart/drivers/csi_core.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Core Layer Header File
+ */
+
+
+#ifndef _CORE_H_
+#define _CORE_H_
+
+#include <stdint.h>
+
+#if defined(__CK801__) || defined(__E801__)
+#include <core_801.h>
+#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
+#include <core_802.h>
+#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__)  || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
+#include <core_804.h>
+#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
+#include <core_803.h>
+#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
+#include <core_805.h>
+#elif defined(__CK610__)
+#include <core_ck610.h>
+#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
+#include <core_810.h>
+#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
+#include <core_807.h>
+#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
+#include <core_rv32_old.h>
+#elif defined(__riscv)
+#include <core_rv32.h>
+#endif
+
+#ifdef __riscv
+#include <csi_rv32_gcc.h>
+#else
+#include <csi_gcc.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CORE_H_ */
diff --git a/bsp/thead-smart/drivers/csi_rv32_gcc.h b/bsp/thead-smart/drivers/csi_rv32_gcc.h
new file mode 100644
index 0000000000..bc52d66426
--- /dev/null
+++ b/bsp/thead-smart/drivers/csi_rv32_gcc.h
@@ -0,0 +1,2849 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Header File for GCC.
+ */
+
+#ifndef _CSI_RV32_GCC_H_
+#define _CSI_RV32_GCC_H_
+
+#include <stdlib.h>
+
+#ifndef __ASM
+#define __ASM                   __asm     /*!< asm keyword for GNU Compiler */
+#endif
+
+#ifndef __INLINE
+#define __INLINE                inline    /*!< inline keyword for GNU Compiler */
+#endif
+
+#ifndef __ALWAYS_STATIC_INLINE
+#define __ALWAYS_STATIC_INLINE  __attribute__((always_inline)) static inline
+#endif
+
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE         static inline
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CSI_Core_FunctionInterface
+    \defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions
+  @{
+ */
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by setting the IE-bit in the PSR.
+           Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile("csrs mstatus, 8");
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by clearing the IE-bit in the PSR.
+  Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __disable_irq(void)
+{
+    __ASM volatile("csrc mstatus, 8");
+}
+
+/**
+  \brief   Get MXSTATUS
+  \details Returns the content of the MXSTATUS Register.
+  \return               MXSTATUS Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MXSTATUS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mxstatus" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MXSTATUS
+  \details Writes the given value to the MXSTATUS Register.
+  \param [in]    MXSTATUS Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MXSTATUS(uint32_t mxstatus)
+{
+    __ASM volatile("csrw mxstatus, %0" : : "r"(mxstatus));
+}
+
+/**
+  \brief   Get MEXSTATUS
+  \details Returns the content of the MEXSTATUS Register.
+  \return               MEXSTATUS Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MEXSTATUS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mexstatus" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MEXSTATUS
+  \details Writes the given value to the MSTATUS Register.
+  \param [in]    MEXSTATUS Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MEXSTATUS(uint32_t mexstatus)
+{
+    __ASM volatile("csrw mexstatus, %0" : : "r"(mexstatus));
+}
+
+
+/**
+  \brief   Get MRADDR
+  \details Returns the content of the MRADDR Register.
+  \return               MRADDR Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MRADDR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mraddr" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get FXCR
+  \details Returns the content of the FXCR Register.
+  \return               FXCR Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_FXCR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, fxcr" : "=r"(result));
+    return (result);
+}
+
+
+/**
+  \brief   Set FXCR
+  \details Writes the given value to the FXCR Register.
+  \param [in]     FXCR Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_FXCR(uint32_t fxcr)
+{
+    __ASM volatile("csrw fxcr, %0" : : "r"(fxcr));
+}
+
+/**
+  \brief   Get MSTATUS
+  \details Returns the content of the MSTATUS Register.
+  \return               MSTATUS Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MSTATUS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mstatus" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MSTATUS
+  \details Writes the given value to the MSTATUS Register.
+  \param [in]    mstatus  MSTATUS Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MSTATUS(uint32_t mstatus)
+{
+    __ASM volatile("csrw mstatus, %0" : : "r"(mstatus));
+}
+
+/**
+  \brief   Get MHCR
+  \details Returns the content of the MHCR Register.
+  \return               MHCR Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MHCR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mhcr" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MHCR
+  \details Writes the given value to the MHCR Register.
+  \param [in]    mstatus  MHCR Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MHCR(uint32_t mhcr)
+{
+    __ASM volatile("csrw mhcr, %0" : : "r"(mhcr));
+}
+
+/**
+  \brief   Get MISA Register
+  \details Returns the content of the MISA Register.
+  \return               MISA Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MISA(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, misa" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MISA
+  \details Writes the given value to the MISA Register.
+  \param [in]    misa  MISA Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MISA(uint32_t misa)
+{
+    __ASM volatile("csrw misa, %0" : : "r"(misa));
+}
+
+/**
+  \brief   Get MIE Register
+  \details Returns the content of the MIE Register.
+  \return               MIE Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MIE(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mie" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MIE
+  \details Writes the given value to the MIE Register.
+  \param [in]    mie  MIE Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MIE(uint32_t mie)
+{
+    __ASM volatile("csrw mie, %0" : : "r"(mie));
+}
+
+/**
+  \brief   Get MTVEC Register
+  \details Returns the content of the MTVEC Register.
+  \return               MTVEC Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MTVEC(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mtvec" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MTVEC
+  \details Writes the given value to the MTVEC Register.
+  \param [in]    mtvec  MTVEC Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MTVEC(uint32_t mtvec)
+{
+    __ASM volatile("csrw mtvec, %0" : : "r"(mtvec));
+}
+
+/**
+  \brief   Set MTVT
+  \details Writes the given value to the MTVT Register.
+  \param [in]    mtvt  MTVT Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MTVT(uint32_t mtvt)
+{
+    __ASM volatile("csrw mtvt, %0" : : "r"(mtvt));
+}
+
+/**
+  \brief   Get MTVT Register
+  \details Returns the content of the MTVT Register.
+  \return               MTVT Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MTVT(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mtvt" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get SP
+  \details Returns the content of the SP Register.
+  \return               SP Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_SP(void)
+{
+    uint32_t result;
+
+    __ASM volatile("mv %0, sp" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set SP
+  \details Writes the given value to the SP Register.
+  \param [in]    sp  SP Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp)
+{
+    __ASM volatile("mv sp, %0" : : "r"(sp): "sp");
+}
+
+/**
+  \brief   Get MSCRATCH Register
+  \details Returns the content of the MSCRATCH Register.
+  \return               MSCRATCH Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MSCRATCH(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mscratch" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MSCRATCH
+  \details Writes the given value to the MSCRATCH Register.
+  \param [in]    mscratch  MSCRATCH Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MSCRATCH(uint32_t mscratch)
+{
+    __ASM volatile("csrw mscratch, %0" : : "r"(mscratch));
+}
+
+/**
+  \brief   Get MEPC Register
+  \details Returns the content of the MEPC Register.
+  \return               MEPC Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MEPC(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mepc" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MEPC
+  \details Writes the given value to the MEPC Register.
+  \param [in]    mepc  MEPC Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MEPC(uint32_t mepc)
+{
+    __ASM volatile("csrw mepc, %0" : : "r"(mepc));
+}
+
+/**
+  \brief   Get MCAUSE Register
+  \details Returns the content of the MCAUSE Register.
+  \return               MCAUSE Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MCAUSE(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mcause" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MNXTI Register
+  \details Returns the content of the MNXTI Register.
+  \return               MNXTI Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MNXTI(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mnxti" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MNXTI
+  \details Writes the given value to the MNXTI Register.
+  \param [in]    mnxti  MNXTI Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MNXTI(uint32_t mnxti)
+{
+    __ASM volatile("csrw mnxti, %0" : : "r"(mnxti));
+}
+
+/**
+  \brief   Get MINTSTATUS Register
+  \details Returns the content of the MINTSTATUS Register.
+  \return               MINTSTATUS Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MINTSTATUS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mintstatus" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MTVAL Register
+  \details Returns the content of the MTVAL Register.
+  \return               MTVAL Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MTVAL(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mtval" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MIP Register
+  \details Returns the content of the MIP Register.
+  \return               MIP Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MIP(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mip" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MIP
+  \details Writes the given value to the MIP Register.
+  \param [in]    mip  MIP Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_MIP(uint32_t mip)
+{
+    __ASM volatile("csrw mip, %0" : : "r"(mip));
+}
+
+/**
+  \brief   Get MCYCLEL Register
+  \details Returns the content of the MCYCLEL Register.
+  \return               MCYCLE Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLE(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mcycle" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MCYCLEH Register
+  \details Returns the content of the MCYCLEH Register.
+  \return               MCYCLEH Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLEH(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mcycleh" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MINSTRET Register
+  \details Returns the content of the MINSTRET Register.
+  \return               MINSTRET Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRET(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, minstret" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MINSTRETH Register
+  \details Returns the content of the MINSTRETH Register.
+  \return               MINSTRETH Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRETH(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, minstreth" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MVENDORID Register
+  \details Returns the content of the MVENDROID Register.
+  \return               MVENDORID Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MVENDORID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mvendorid" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MARCHID Register
+  \details Returns the content of the MARCHID Register.
+  \return               MARCHID Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MARCHID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, marchid" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MIMPID Register
+  \details Returns the content of the MIMPID Register.
+  \return               MIMPID Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MIMPID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mimpid" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get MHARTID Register
+  \details Returns the content of the MHARTID Register.
+  \return               MHARTID Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_MHARTID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, mhartid" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get PMPCFGx Register
+  \details Returns the content of the PMPCFGx Register.
+  \return               PMPCFGx Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG0(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpcfg0" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG1(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpcfg1" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG2(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpcfg2" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG3(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpcfg3" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get PMPxCFG Register by index
+  \details Returns the content of the PMPxCFG Register.
+  \param [in]    idx    PMP region index
+  \return               PMPxCFG Register value
+ */
+__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
+{
+    uint32_t pmpcfgx = 0;
+
+    if (idx < 4) {
+        pmpcfgx = __get_PMPCFG0();
+    } else if (idx >=4 && idx < 8) {
+        idx -= 4;
+        pmpcfgx = __get_PMPCFG1();
+    } else if (idx >=8 && idx < 12) {
+        idx -= 8;
+        pmpcfgx = __get_PMPCFG2();
+    } else if (idx >=12 && idx < 16) {
+        idx -= 12;
+        pmpcfgx = __get_PMPCFG3();
+    } else {
+        return 0;
+    }
+
+    return (uint8_t)((pmpcfgx & (0xFF << (idx << 3))) >> (idx << 3));
+}
+
+/**
+  \brief   Set PMPCFGx
+  \details Writes the given value to the PMPCFGx Register.
+  \param [in]    pmpcfg  PMPCFGx Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_PMPCFG0(uint32_t pmpcfg)
+{
+    __ASM volatile("csrw pmpcfg0, %0" : : "r"(pmpcfg));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPCFG1(uint32_t pmpcfg)
+{
+    __ASM volatile("csrw pmpcfg1, %0" : : "r"(pmpcfg));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPCFG2(uint32_t pmpcfg)
+{
+    __ASM volatile("csrw pmpcfg2, %0" : : "r"(pmpcfg));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPCFG3(uint32_t pmpcfg)
+{
+    __ASM volatile("csrw pmpcfg3, %0" : : "r"(pmpcfg));
+}
+
+/**
+  \brief   Set PMPxCFG by index
+  \details Writes the given value to the PMPxCFG Register.
+  \param [in]    idx      PMPx region index
+  \param [in]    pmpxcfg  PMPxCFG Register value to set
+ */
+__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
+{
+    uint32_t pmpcfgx = 0;
+
+    if (idx < 4) {
+        pmpcfgx = __get_PMPCFG0();
+        pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
+        __set_PMPCFG0(pmpcfgx);
+    } else if (idx >=4 && idx < 8) {
+        idx -= 4;
+        pmpcfgx = __get_PMPCFG1();
+        pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
+        __set_PMPCFG1(pmpcfgx);
+    } else if (idx >=8 && idx < 12) {
+        idx -= 8;
+        pmpcfgx = __get_PMPCFG2();
+        pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
+        __set_PMPCFG2(pmpcfgx);
+    } else if (idx >=12 && idx < 16) {
+        idx -= 12;
+        pmpcfgx = __get_PMPCFG3();
+        pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
+        __set_PMPCFG3(pmpcfgx);
+    } else {
+        return;
+    }
+}
+
+/**
+  \brief   Get PMPADDRx Register
+  \details Returns the content of the PMPADDRx Register.
+  \return               PMPADDRx Register value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR0(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr0" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR1(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr1" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR2(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr2" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR3(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr3" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR4(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr4" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR5(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr5" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR6(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr6" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR7(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr7" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR8(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr8" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR9(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr9" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR10(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr10" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR11(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr11" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR12(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr12" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR13(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr13" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR14(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr14" : "=r"(result));
+    return (result);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR15(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0, pmpaddr15" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Get PMPADDRx Register by index
+  \details Returns the content of the PMPADDRx Register.
+  \param [in]    idx    PMP region index
+  \return               PMPADDRx Register value
+ */
+__STATIC_INLINE uint32_t __get_PMPADDRx(uint32_t idx)
+{
+    switch (idx) {
+    case 0: return __get_PMPADDR0();
+    case 1: return __get_PMPADDR1();
+    case 2: return __get_PMPADDR2();
+    case 3: return __get_PMPADDR3();
+    case 4: return __get_PMPADDR4();
+    case 5: return __get_PMPADDR5();
+    case 6: return __get_PMPADDR6();
+    case 7: return __get_PMPADDR7();
+    case 8: return __get_PMPADDR8();
+    case 9: return __get_PMPADDR9();
+    case 10: return __get_PMPADDR10();
+    case 11: return __get_PMPADDR11();
+    case 12: return __get_PMPADDR12();
+    case 13: return __get_PMPADDR13();
+    case 14: return __get_PMPADDR14();
+    case 15: return __get_PMPADDR15();
+    default: return 0;
+    }
+}
+
+/**
+  \brief   Set PMPADDRx
+  \details Writes the given value to the PMPADDRx Register.
+  \param [in]    pmpaddr  PMPADDRx Register value to set
+ */
+__ALWAYS_STATIC_INLINE void __set_PMPADDR0(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr0, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR1(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr1, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR2(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr2, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR3(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr3, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR4(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr4, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR5(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr5, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR6(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr6, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR7(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr7, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR8(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr8, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR9(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr9, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR10(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr10, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR11(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr11, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR12(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr12, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR13(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr13, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR14(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr14, %0" : : "r"(pmpaddr));
+}
+
+__ALWAYS_STATIC_INLINE void __set_PMPADDR15(uint32_t pmpaddr)
+{
+    __ASM volatile("csrw pmpaddr15, %0" : : "r"(pmpaddr));
+}
+
+/**
+  \brief   Set PMPADDRx by index
+  \details Writes the given value to the PMPADDRx Register.
+  \param [in]    idx      PMP region index
+  \param [in]    pmpaddr  PMPADDRx Register value to set
+ */
+__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, uint32_t pmpaddr)
+{
+    switch (idx) {
+    case 0: __set_PMPADDR0(pmpaddr); break;
+    case 1: __set_PMPADDR1(pmpaddr); break;
+    case 2: __set_PMPADDR2(pmpaddr); break;
+    case 3: __set_PMPADDR3(pmpaddr); break;
+    case 4: __set_PMPADDR4(pmpaddr); break;
+    case 5: __set_PMPADDR5(pmpaddr); break;
+    case 6: __set_PMPADDR6(pmpaddr); break;
+    case 7: __set_PMPADDR7(pmpaddr); break;
+    case 8: __set_PMPADDR8(pmpaddr); break;
+    case 9: __set_PMPADDR9(pmpaddr); break;
+    case 10: __set_PMPADDR10(pmpaddr); break;
+    case 11: __set_PMPADDR11(pmpaddr); break;
+    case 12: __set_PMPADDR12(pmpaddr); break;
+    case 13: __set_PMPADDR13(pmpaddr); break;
+    case 14: __set_PMPADDR14(pmpaddr); break;
+    case 15: __set_PMPADDR15(pmpaddr); break;
+    default: return;
+    }
+}
+
+/**
+  \brief   Enable interrupts and exceptions
+  \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR.
+           Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __enable_excp_irq(void)
+{
+    __enable_irq();
+}
+
+
+/**
+  \brief   Disable interrupts and exceptions
+  \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR.
+           Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __disable_excp_irq(void)
+{
+    __disable_irq();
+}
+
+#define __CSI_GCC_OUT_REG(r) "=r" (r)
+#define __CSI_GCC_USE_REG(r) "r" (r)
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__ALWAYS_STATIC_INLINE void __NOP(void)
+{
+    __ASM volatile("nop");
+}
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__ALWAYS_STATIC_INLINE void __WFI(void)
+{
+    __ASM volatile("wfi");
+}
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
+ */
+__ALWAYS_STATIC_INLINE void __WAIT(void)
+{
+    __ASM volatile("wfi");
+}
+
+/**
+  \brief   Doze For Interrupt
+  \details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
+ */
+__ALWAYS_STATIC_INLINE void __DOZE(void)
+{
+    __ASM volatile("wfi");
+}
+
+/**
+  \brief   Stop For Interrupt
+  \details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs.
+ */
+__ALWAYS_STATIC_INLINE void __STOP(void)
+{
+    __ASM volatile("wfi");
+}
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__ALWAYS_STATIC_INLINE void __ISB(void)
+{
+    __ASM volatile("fence");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__ALWAYS_STATIC_INLINE void __DSB(void)
+{
+    __ASM volatile("fence");
+}
+
+/**
+  \brief   Invalid all icache
+  \details invalid all icache.
+ */
+__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
+{
+    __ASM volatile("icache.iall");
+}
+
+/**
+  \brief   Invalid Icache by addr
+  \details Invalid Icache by addr.
+  \param [in] addr  operate addr
+ */
+__ALWAYS_STATIC_INLINE void __ICACHE_IPA(uint32_t addr)
+{
+    __ASM volatile("icache.ipa %0" : : "r"(addr));
+}
+
+/**
+  \brief   Invalid all dcache
+  \details invalid all dcache.
+ */
+__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
+{
+    __ASM volatile("dcache.iall");
+}
+
+/**
+  \brief   Clear all dcache
+  \details clear all dcache.
+ */
+__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
+{
+    __ASM volatile("dcache.call");
+}
+
+/**
+  \brief   Clear&invalid all dcache
+  \details clear & invalid all dcache.
+ */
+__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
+{
+    __ASM volatile("dcache.ciall");
+}
+
+/**
+  \brief   Invalid Dcache by addr
+  \details Invalid Dcache by addr.
+  \param [in] addr  operate addr
+ */
+__ALWAYS_STATIC_INLINE void __DCACHE_IPA(uint32_t addr)
+{
+    __ASM volatile("dcache.ipa %0" : : "r"(addr));
+}
+
+/**
+  \brief   Clear Dcache by addr
+  \details Clear Dcache by addr.
+  \param [in] addr  operate addr
+ */
+__ALWAYS_STATIC_INLINE void __DCACHE_CPA(uint32_t addr)
+{
+    __ASM volatile("dcache.cpa %0" : : "r"(addr));
+}
+
+/**
+  \brief   Clear & Invalid Dcache by addr
+  \details Clear & Invalid Dcache by addr.
+  \param [in] addr  operate addr
+ */
+__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(uint32_t addr)
+{
+    __ASM volatile("dcache.cipa %0" : : "r"(addr));
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__ALWAYS_STATIC_INLINE void __DMB(void)
+{
+    __ASM volatile("fence");
+}
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+    return __builtin_bswap32(value);
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+
+    result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) |
+             ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8);
+
+    return (result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+    return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8));
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ */
+__ALWAYS_STATIC_INLINE void __BKPT(void)
+{
+    __ASM volatile("ebreak");
+}
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+
+    int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+
+    for (value >>= 1U; value; value >>= 1U) {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+
+    result <<= s;                        /* shift when v's highest bits are zero */
+
+    return (result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+/**
+  \details This function saturates a signed value.
+  \param [in]    x   Value to be saturated
+  \param [in]    y   Bit position to saturate to [1..32]
+  \return            Saturated value.
+ */
+__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y)
+{
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+
+    for (i = 0; i < (y - 1); i++) {
+        posMax = posMax * 2;
+    }
+
+    if (x > 0) {
+        posMax = (posMax - 1);
+
+        if (x > posMax) {
+            x = posMax;
+        }
+
+//    x &= (posMax * 2 + 1);
+    } else {
+        negMin = -posMax;
+
+        if (x < negMin) {
+            x = negMin;
+        }
+
+//    x &= (posMax * 2 - 1);
+    }
+
+    return (x);
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat)
+{
+    uint32_t result;
+
+    if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
+        result = 0xFFFFFFFF >> (32 - sat);
+    } else {
+        result = value;
+    }
+
+    return (result);
+}
+
+/**
+  \brief   Unsigned Saturate for internal use
+  \details Saturates an unsigned value, should not call directly.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat)
+{
+    uint32_t result;
+
+    if (value & 0x80000000) { /* only overflow set bit-31 */
+        result = 0;
+    } else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
+        result = 0xFFFFFFFF >> (32 - sat);
+    } else {
+        result = value;
+    }
+
+    return (result);
+}
+
+/**
+  \brief   Rotate Right with Extend
+  \details This function moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \note    carry input will always 0.
+  \param [in]    op1  Value to rotate
+  \return               Rotated value
+ */
+__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1)
+{
+    return 0;
+}
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    addr  Pointer to location
+  \return             value of type uint8_t at (*ptr)
+ */
+__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+    __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr));
+
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    addr  Pointer to location
+  \return        value of type uint16_t at (*ptr)
+ */
+__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+    __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr));
+
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    addr  Pointer to location
+  \return        value of type uint32_t at (*ptr)
+ */
+__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+    __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr));
+
+    return (result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    addr  Pointer to location
+ */
+__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+    __ASM volatile("sb %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    addr  Pointer to location
+ */
+__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+    __ASM volatile("sh %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    addr  Pointer to location
+ */
+__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+    __ASM volatile("sw %1, 0(%0)" :: "r"(addr), "r"(value) : "memory");
+}
+
+/*@}*/ /* end of group CSI_Core_InstructionInterface */
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics
+  Access to dedicated SIMD instructions \n
+  Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.
+
+  @{
+*/
+
+/**
+  \brief   Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16]
+           of val2 levitated with the val3.
+  \details Combine a halfword from one register with a halfword from another register.
+           The second argument can be left-shifted before extraction of the halfword.
+  \param [in]    val1   first 16-bit operands
+  \param [in]    val2   second 16-bit operands
+  \param [in]    val3   value for left-shifting val2. Value range [0..31].
+  \return               the combination of halfwords.
+  \remark
+                 res[15:0]  = val1[15:0]              \n
+                 res[31:16] = val2[31:16] << val3
+ */
+__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3)
+{
+    return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000));
+}
+
+/**
+  \brief   Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0]
+           of val2 right-shifted with the val3.
+  \details Combine a halfword from one register with a halfword from another register.
+           The second argument can be right-shifted before extraction of the halfword.
+  \param [in]    val1   first 16-bit operands
+  \param [in]    val2   second 16-bit operands
+  \param [in]    val3   value for right-shifting val2. Value range [1..32].
+  \return               the combination of halfwords.
+  \remark
+                 res[15:0]  = val2[15:0] >> val3        \n
+                 res[31:16] = val1[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3)
+{
+    return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF));
+}
+
+/**
+  \brief   Dual 16-bit signed saturate.
+  \details This function saturates a signed value.
+  \param [in]    x   two signed 16-bit values to be saturated.
+  \param [in]    y   bit position for saturation, an integral constant expression in the range 1 to 16.
+  \return        the sum of the absolute differences of the following bytes, added to the accumulation value:\n
+                 the signed saturation of the low halfword in val1, saturated to the bit position specified in
+                 val2 and returned in the low halfword of the return value.\n
+                 the signed saturation of the high halfword in val1, saturated to the bit position specified in
+                 val2 and returned in the high halfword of the return value.
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y)
+{
+    int32_t r = 0, s = 0;
+
+    r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF;
+    s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned saturate.
+  \details This function enables you to saturate two signed 16-bit values to a selected unsigned range.
+  \param [in]    x   two signed 16-bit values to be saturated.
+  \param [in]    y   bit position for saturation, an integral constant expression in the range 1 to 16.
+  \return        the saturation of the two signed 16-bit values, as non-negative values:
+                 the saturation of the low halfword in val1, saturated to the bit position specified in
+                 val2 and returned in the low halfword of the return value.\n
+                 the saturation of the high halfword in val1, saturated to the bit position specified in
+                 val2 and returned in the high halfword of the return value.
+ */
+__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y)
+{
+    int32_t r = 0, s = 0;
+
+    r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF;
+    s = __IUSAT(((x) >> 16), y) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Quad 8-bit saturating addition.
+  \details This function enables you to perform four 8-bit integer additions,
+           saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
+  \param [in]    x   first four 8-bit summands.
+  \param [in]    y   second four 8-bit summands.
+  \return        the saturated addition of the first byte of each operand in the first byte of the return value.\n
+                 the saturated addition of the second byte of each operand in the second byte of the return value.\n
+                 the saturated addition of the third byte of each operand in the third byte of the return value.\n
+                 the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
+                 The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
+  \remark
+                 res[7:0]   = val1[7:0]   + val2[7:0]        \n
+                 res[15:8]  = val1[15:8]  + val2[15:8]       \n
+                 res[23:16] = val1[23:16] + val2[23:16]      \n
+                 res[31:24] = val1[31:24] + val2[31:24]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((int32_t)x <<  8) >> 24) + (((int32_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r)));
+}
+
+/**
+  \brief   Quad 8-bit unsigned saturating addition.
+  \details This function enables you to perform four unsigned 8-bit integer additions,
+           saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
+  \param [in]    x   first four 8-bit summands.
+  \param [in]    y   second four 8-bit summands.
+  \return        the saturated addition of the first byte of each operand in the first byte of the return value.\n
+                 the saturated addition of the second byte of each operand in the second byte of the return value.\n
+                 the saturated addition of the third byte of each operand in the third byte of the return value.\n
+                 the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n
+                 The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1.
+  \remark
+                 res[7:0]   = val1[7:0]   + val2[7:0]        \n
+                 res[15:8]  = val1[15:8]  + val2[15:8]       \n
+                 res[23:16] = val1[23:16] + val2[23:16]      \n
+                 res[31:24] = val1[31:24] + val2[31:24]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF;
+    s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF;
+    t = __IUSAT((((x <<  8) >> 24) + ((y <<  8) >> 24)), 8) & 0x000000FF;
+    u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF;
+
+    return ((u << 24) | (t << 16) | (s <<  8) | (r));
+}
+
+/**
+  \brief   Quad 8-bit signed addition.
+  \details This function performs four 8-bit signed integer additions.
+  \param [in]    x  first four 8-bit summands.
+  \param [in]    y  second four 8-bit summands.
+  \return        the addition of the first bytes from each operand, in the first byte of the return value.\n
+                 the addition of the second bytes of each operand, in the second byte of the return value.\n
+                 the addition of the third bytes of each operand, in the third byte of the return value.\n
+                 the addition of the fourth bytes of each operand, in the fourth byte of the return value.
+  \remark
+                 res[7:0]   = val1[7:0]   + val2[7:0]        \n
+                 res[15:8]  = val1[15:8]  + val2[15:8]       \n
+                 res[23:16] = val1[23:16] + val2[23:16]      \n
+                 res[31:24] = val1[31:24] + val2[31:24]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
+    s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
+    t = ((((int32_t)x <<  8) >> 24) + (((int32_t)y <<  8) >> 24)) & (int32_t)0x000000FF;
+    u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r)));
+}
+
+/**
+  \brief   Quad 8-bit unsigned addition.
+  \details This function performs four unsigned 8-bit integer additions.
+  \param [in]    x  first four 8-bit summands.
+  \param [in]    y  second four 8-bit summands.
+  \return        the addition of the first bytes from each operand, in the first byte of the return value.\n
+                 the addition of the second bytes of each operand, in the second byte of the return value.\n
+                 the addition of the third bytes of each operand, in the third byte of the return value.\n
+                 the addition of the fourth bytes of each operand, in the fourth byte of the return value.
+  \remark
+                 res[7:0]   = val1[7:0]   + val2[7:0]        \n
+                 res[15:8]  = val1[15:8]  + val2[15:8]       \n
+                 res[23:16] = val1[23:16] + val2[23:16]      \n
+                 res[31:24] = val1[31:24] + val2[31:24]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF;
+    s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF;
+    t = (((x <<  8) >> 24) + ((y <<  8) >> 24)) & 0x000000FF;
+    u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF;
+
+    return ((u << 24) | (t << 16) | (s <<  8) | (r));
+}
+
+/**
+  \brief   Quad 8-bit saturating subtract.
+  \details This function enables you to perform four 8-bit integer subtractions,
+           saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
+  \param [in]    x   first four 8-bit summands.
+  \param [in]    y   second four 8-bit summands.
+  \return        the subtraction of the first byte of each operand in the first byte of the return value.\n
+                 the subtraction of the second byte of each operand in the second byte of the return value.\n
+                 the subtraction of the third byte of each operand in the third byte of the return value.\n
+                 the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
+                 The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1.
+  \remark
+                 res[7:0]   = val1[7:0]   - val2[7:0]        \n
+                 res[15:8]  = val1[15:8]  - val2[15:8]       \n
+                 res[23:16] = val1[23:16] - val2[23:16]      \n
+                 res[31:24] = val1[31:24] - val2[31:24]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((int32_t)x <<  8) >> 24) - (((int32_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r)));
+}
+
+/**
+  \brief   Quad 8-bit unsigned saturating subtraction.
+  \details This function enables you to perform four unsigned 8-bit integer subtractions,
+           saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1.
+  \param [in]    x   first four 8-bit summands.
+  \param [in]    y   second four 8-bit summands.
+  \return        the subtraction of the first byte of each operand in the first byte of the return value.\n
+                 the subtraction of the second byte of each operand in the second byte of the return value.\n
+                 the subtraction of the third byte of each operand in the third byte of the return value.\n
+                 the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n
+                 The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1.
+  \remark
+                 res[7:0]   = val1[7:0]   - val2[7:0]        \n
+                 res[15:8]  = val1[15:8]  - val2[15:8]       \n
+                 res[23:16] = val1[23:16] - val2[23:16]      \n
+                 res[31:24] = val1[31:24] - val2[31:24]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF;
+    s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF;
+    t = __IUSAT((((x <<  8) >> 24) - ((y <<  8) >> 24)), 8) & 0x000000FF;
+    u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF;
+
+    return ((u << 24) | (t << 16) | (s <<  8) | (r));
+}
+
+/**
+  \brief   Quad 8-bit signed subtraction.
+  \details This function enables you to perform four 8-bit signed integer subtractions.
+  \param [in]    x  first four 8-bit operands of each subtraction.
+  \param [in]    y  second four 8-bit operands of each subtraction.
+  \return        the subtraction of the first bytes from each operand, in the first byte of the return value.\n
+                 the subtraction of the second bytes of each operand, in the second byte of the return value.\n
+                 the subtraction of the third bytes of each operand, in the third byte of the return value.\n
+                 the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
+  \remark
+                 res[7:0]   = val1[7:0]   - val2[7:0]        \n
+                 res[15:8]  = val1[15:8]  - val2[15:8]       \n
+                 res[23:16] = val1[23:16] - val2[23:16]      \n
+                 res[31:24] = val1[31:24] - val2[31:24]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF;
+    s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF;
+    t = ((((int32_t)x <<  8) >> 24) - (((int32_t)y <<  8) >> 24)) & (int32_t)0x000000FF;
+    u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r)));
+}
+
+/**
+  \brief   Quad 8-bit unsigned subtract.
+  \details This function enables you to perform four 8-bit unsigned integer subtractions.
+  \param [in]    x  first four 8-bit operands of each subtraction.
+  \param [in]    y  second four 8-bit operands of each subtraction.
+  \return        the subtraction of the first bytes from each operand, in the first byte of the return value.\n
+                 the subtraction of the second bytes of each operand, in the second byte of the return value.\n
+                 the subtraction of the third bytes of each operand, in the third byte of the return value.\n
+                 the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
+  \remark
+                 res[7:0]   = val1[7:0]   - val2[7:0]        \n
+                 res[15:8]  = val1[15:8]  - val2[15:8]       \n
+                 res[23:16] = val1[23:16] - val2[23:16]      \n
+                 res[31:24] = val1[31:24] - val2[31:24]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
+    s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
+    t = (((x <<  8) >> 24) - ((y <<  8) >> 24)) & 0x000000FF;
+    u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
+
+    return ((u << 24) | (t << 16) | (s <<  8) | (r));
+}
+
+/**
+  \brief   Unsigned sum of quad 8-bit unsigned absolute difference.
+  \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
+           of the differences together, returning the result as a single unsigned integer.
+  \param [in]    x  first four 8-bit operands of each subtraction.
+  \param [in]    y  second four 8-bit operands of each subtraction.
+  \return        the subtraction of the first bytes from each operand, in the first byte of the return value.\n
+                 the subtraction of the second bytes of each operand, in the second byte of the return value.\n
+                 the subtraction of the third bytes of each operand, in the third byte of the return value.\n
+                 the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n
+                 The sum is returned as a single unsigned integer.
+  \remark
+                 absdiff1   = val1[7:0]   - val2[7:0]        \n
+                 absdiff2   = val1[15:8]  - val2[15:8]       \n
+                 absdiff3   = val1[23:16] - val2[23:16]      \n
+                 absdiff4   = val1[31:24] - val2[31:24]      \n
+                 res[31:0]  = absdiff1 + absdiff2 + absdiff3 + absdiff4
+ */
+__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF;
+    s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF;
+    t = (((x <<  8) >> 24) - ((y <<  8) >> 24)) & 0x000000FF;
+    u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF;
+
+    return (u + t + s + r);
+}
+
+/**
+  \brief   Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.
+  \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
+           of the differences to a 32-bit accumulate operand.
+  \param [in]    x  first four 8-bit operands of each subtraction.
+  \param [in]    y  second four 8-bit operands of each subtraction.
+  \param [in]  sum  accumulation value.
+  \return        the sum of the absolute differences of the following bytes, added to the accumulation value:
+                 the subtraction of the first bytes from each operand, in the first byte of the return value.\n
+                 the subtraction of the second bytes of each operand, in the second byte of the return value.\n
+                 the subtraction of the third bytes of each operand, in the third byte of the return value.\n
+                 the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.
+  \remark
+                 absdiff1 = val1[7:0]   - val2[7:0]        \n
+                 absdiff2 = val1[15:8]  - val2[15:8]       \n
+                 absdiff3 = val1[23:16] - val2[23:16]      \n
+                 absdiff4 = val1[31:24] - val2[31:24]      \n
+                 sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n
+                 res[31:0] = sum[31:0] + val3[31:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum)
+{
+    int32_t r, s, t, u;
+
+#ifdef __cplusplus
+    r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
+    s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
+    t = (abs((long long)((x <<  8) >> 24) - ((y <<  8) >> 24))) & 0x000000FF;
+    u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF;
+#else
+    r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
+    s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
+    t = (abs(((x <<  8) >> 24) - ((y <<  8) >> 24))) & 0x000000FF;
+    u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF;
+#endif
+    return (u + t + s + r + sum);
+}
+
+/**
+  \brief   Dual 16-bit saturating addition.
+  \details This function enables you to perform two 16-bit integer arithmetic additions in parallel,
+           saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \param [in]    x   first two 16-bit summands.
+  \param [in]    y   second two 16-bit summands.
+  \return        the saturated addition of the low halfwords, in the low halfword of the return value.\n
+                 the saturated addition of the high halfwords, in the high halfword of the return value.\n
+                 The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \remark
+                 res[15:0]  = val1[15:0]  + val2[15:0]        \n
+                 res[31:16] = val1[31:16] + val2[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y)
+{
+    int32_t r = 0, s = 0;
+
+    r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned saturating addition.
+  \details This function enables you to perform two unsigned 16-bit integer additions, saturating
+           the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
+  \param [in]    x   first two 16-bit summands.
+  \param [in]    y   second two 16-bit summands.
+  \return        the saturated addition of the low halfwords, in the low halfword of the return value.\n
+                 the saturated addition of the high halfwords, in the high halfword of the return value.\n
+                 The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
+  \remark
+                 res[15:0]  = val1[15:0]  + val2[15:0]        \n
+                 res[31:16] = val1[31:16] + val2[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y)
+{
+    int32_t r = 0, s = 0;
+
+    r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
+    s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit signed addition.
+  \details This function enables you to perform two 16-bit signed integer additions.
+  \param [in]    x   first two 16-bit summands.
+  \param [in]    y   second two 16-bit summands.
+  \return        the addition of the low halfwords in the low halfword of the return value.\n
+                 the addition of the high halfwords in the high halfword of the return value.
+  \remark
+                 res[15:0]  = val1[15:0]  + val2[15:0]        \n
+                 res[31:16] = val1[31:16] + val2[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y)
+{
+    int32_t r = 0, s = 0;
+
+    r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
+    s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned addition
+  \details This function enables you to perform two 16-bit unsigned integer additions.
+  \param [in]    x   first two 16-bit summands for each addition.
+  \param [in]    y   second two 16-bit summands for each addition.
+  \return        the addition of the low halfwords in the low halfword of the return value.\n
+                 the addition of the high halfwords in the high halfword of the return value.
+  \remark
+                 res[15:0]  = val1[15:0]  + val2[15:0]        \n
+                 res[31:16] = val1[31:16] + val2[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y)
+{
+    int32_t r = 0, s = 0;
+
+    r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
+    s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+
+/**
+  \brief   Dual 16-bit signed addition with halved results.
+  \details This function enables you to perform two signed 16-bit integer additions, halving the results.
+  \param [in]    x   first two 16-bit summands.
+  \param [in]    y   second two 16-bit summands.
+  \return        the halved addition of the low halfwords, in the low halfword of the return value.\n
+                 the halved addition of the high halfwords, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = (val1[15:0]  + val2[15:0]) >> 1        \n
+                 res[31:16] = (val1[31:16] + val2[31:16]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned addition with halved results.
+  \details This function enables you to perform two unsigned 16-bit integer additions, halving the results.
+  \param [in]    x   first two 16-bit summands.
+  \param [in]    y   second two 16-bit summands.
+  \return        the halved addition of the low halfwords, in the low halfword of the return value.\n
+                 the halved addition of the high halfwords, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = (val1[15:0]  + val2[15:0]) >> 1        \n
+                 res[31:16] = (val1[31:16] + val2[31:16]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
+    s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Quad 8-bit signed addition with halved results.
+  \details This function enables you to perform four signed 8-bit integer additions, halving the results.
+  \param [in]    x   first four 8-bit summands.
+  \param [in]    y   second four 8-bit summands.
+  \return        the halved addition of the first bytes from each operand, in the first byte of the return value.\n
+                 the halved addition of the second bytes from each operand, in the second byte of the return value.\n
+                 the halved addition of the third bytes from each operand, in the third byte of the return value.\n
+                 the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
+  \remark
+                 res[7:0]   = (val1[7:0]   + val2[7:0]  ) >> 1    \n
+                 res[15:8]  = (val1[15:8]  + val2[15:8] ) >> 1    \n
+                 res[23:16] = (val1[23:16] + val2[23:16]) >> 1    \n
+                 res[31:24] = (val1[31:24] + val2[31:24]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
+    s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
+    t = (((((int32_t)x <<  8) >> 24) + (((int32_t)y <<  8) >> 24)) >> 1) & (int32_t)0x000000FF;
+    u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r)));
+}
+
+/**
+  \brief   Quad 8-bit unsigned addition with halved results.
+  \details This function enables you to perform four unsigned 8-bit integer additions, halving the results.
+  \param [in]    x   first four 8-bit summands.
+  \param [in]    y   second four 8-bit summands.
+  \return        the halved addition of the first bytes from each operand, in the first byte of the return value.\n
+                 the halved addition of the second bytes from each operand, in the second byte of the return value.\n
+                 the halved addition of the third bytes from each operand, in the third byte of the return value.\n
+                 the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
+  \remark
+                 res[7:0]   = (val1[7:0]   + val2[7:0]  ) >> 1    \n
+                 res[15:8]  = (val1[15:8]  + val2[15:8] ) >> 1    \n
+                 res[23:16] = (val1[23:16] + val2[23:16]) >> 1    \n
+                 res[31:24] = (val1[31:24] + val2[31:24]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF;
+    s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF;
+    t = ((((x <<  8) >> 24) + ((y <<  8) >> 24)) >> 1) & 0x000000FF;
+    u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF;
+
+    return ((u << 24) | (t << 16) | (s <<  8) | (r));
+}
+
+/**
+  \brief   Dual 16-bit saturating subtract.
+  \details This function enables you to perform two 16-bit integer subtractions in parallel,
+           saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \param [in]    x   first two 16-bit summands.
+  \param [in]    y   second two 16-bit summands.
+  \return        the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
+                 the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
+                 The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \remark
+                 res[15:0]  = val1[15:0]  - val2[15:0]        \n
+                 res[31:16] = val1[31:16] - val2[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned saturating subtraction.
+  \details This function enables you to perform two unsigned 16-bit integer subtractions,
+           saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1.
+  \param [in]    x   first two 16-bit operands for each subtraction.
+  \param [in]    y   second two 16-bit operands for each subtraction.
+  \return        the saturated subtraction of the low halfwords, in the low halfword of the return value.\n
+                 the saturated subtraction of the high halfwords, in the high halfword of the return value.\n
+                 The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \remark
+                 res[15:0]  = val1[15:0]  - val2[15:0]        \n
+                 res[31:16] = val1[31:16] - val2[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
+    s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit signed subtraction.
+  \details This function enables you to perform two 16-bit signed integer subtractions.
+  \param [in]    x   first two 16-bit operands of each subtraction.
+  \param [in]    y   second two 16-bit operands of each subtraction.
+  \return        the subtraction of the low halfword in the second operand from the low
+                 halfword in the first operand, in the low halfword of the return value. \n
+                 the subtraction of the high halfword in the second operand from the high
+                 halfword in the first operand, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = val1[15:0]  - val2[15:0]        \n
+                 res[31:16] = val1[31:16] - val2[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
+    s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned subtract.
+  \details This function enables you to perform two 16-bit unsigned integer subtractions.
+  \param [in]    x   first two 16-bit operands of each subtraction.
+  \param [in]    y   second two 16-bit operands of each subtraction.
+  \return        the subtraction of the low halfword in the second operand from the low
+                 halfword in the first operand, in the low halfword of the return value. \n
+                 the subtraction of the high halfword in the second operand from the high
+                 halfword in the first operand, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = val1[15:0]  - val2[15:0]        \n
+                 res[31:16] = val1[31:16] - val2[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
+    s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit signed subtraction with halved results.
+  \details This function enables you to perform two signed 16-bit integer subtractions, halving the results.
+  \param [in]    x   first two 16-bit summands.
+  \param [in]    y   second two 16-bit summands.
+  \return        the halved subtraction of the low halfwords, in the low halfword of the return value.\n
+                 the halved subtraction of the high halfwords, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = (val1[15:0]  - val2[15:0]) >> 1        \n
+                 res[31:16] = (val1[31:16] - val2[31:16]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned subtraction with halved results.
+  \details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.
+  \param [in]    x   first two 16-bit summands.
+  \param [in]    y   second two 16-bit summands.
+  \return        the halved subtraction of the low halfwords, in the low halfword of the return value.\n
+                 the halved subtraction of the high halfwords, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = (val1[15:0]  - val2[15:0]) >> 1        \n
+                 res[31:16] = (val1[31:16] - val2[31:16]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
+    s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Quad 8-bit signed addition with halved results.
+  \details This function enables you to perform four signed 8-bit integer subtractions, halving the results.
+  \param [in]    x   first four 8-bit summands.
+  \param [in]    y   second four 8-bit summands.
+  \return        the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
+                 the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
+                 the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
+                 the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
+  \remark
+                 res[7:0]   = (val1[7:0]   - val2[7:0]  ) >> 1    \n
+                 res[15:8]  = (val1[15:8]  - val2[15:8] ) >> 1    \n
+                 res[23:16] = (val1[23:16] - val2[23:16]) >> 1    \n
+                 res[31:24] = (val1[31:24] - val2[31:24]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF;
+    s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF;
+    t = (((((int32_t)x <<  8) >> 24) - (((int32_t)y <<  8) >> 24)) >> 1) & (int32_t)0x000000FF;
+    u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r)));
+}
+
+/**
+  \brief   Quad 8-bit unsigned subtraction with halved results.
+  \details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.
+  \param [in]    x   first four 8-bit summands.
+  \param [in]    y   second four 8-bit summands.
+  \return        the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n
+                 the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n
+                 the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n
+                 the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value.
+  \remark
+                 res[7:0]   = (val1[7:0]   - val2[7:0]  ) >> 1    \n
+                 res[15:8]  = (val1[15:8]  - val2[15:8] ) >> 1    \n
+                 res[23:16] = (val1[23:16] - val2[23:16]) >> 1    \n
+                 res[31:24] = (val1[31:24] - val2[31:24]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y)
+{
+    int32_t r, s, t, u;
+
+    r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF;
+    s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF;
+    t = ((((x <<  8) >> 24) - ((y <<  8) >> 24)) >> 1) & 0x000000FF;
+    u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF;
+
+    return ((u << 24) | (t << 16) | (s <<  8) | (r));
+}
+
+/**
+  \brief   Dual 16-bit add and subtract with exchange.
+  \details This function enables you to exchange the halfwords of the one operand,
+           then add the high halfwords and subtract the low halfwords,
+           saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \param [in]    x   first operand for the subtraction in the low halfword,
+                     and the first operand for the addition in the high halfword.
+  \param [in]    y   second operand for the subtraction in the high halfword,
+                     and the second operand for the addition in the low halfword.
+  \return        the saturated subtraction of the high halfword in the second operand from the
+                 low halfword in the first operand, in the low halfword of the return value.\n
+                 the saturated addition of the high halfword in the first operand and the
+                 low halfword in the second operand, in the high halfword of the return value.\n
+                 The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \remark
+                 res[15:0]  = val1[15:0]  - val2[31:16]        \n
+                 res[31:16] = val1[31:16] + val2[15:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned saturating addition and subtraction with exchange.
+  \details This function enables you to exchange the halfwords of the second operand and
+           perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction,
+           saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
+  \param [in]    x   first operand for the subtraction in the low halfword,
+                     and the first operand for the addition in the high halfword.
+  \param [in]    y   second operand for the subtraction in the high halfword,
+                     and the second operand for the addition in the low halfword.
+  \return        the saturated subtraction of the high halfword in the second operand from the
+                 low halfword in the first operand, in the low halfword of the return value.\n
+                 the saturated addition of the high halfword in the first operand and the
+                 low halfword in the second operand, in the high halfword of the return value.\n
+                 The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
+  \remark
+                 res[15:0]  = val1[15:0]  - val2[31:16]        \n
+                 res[31:16] = val1[31:16] + val2[15:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF;
+    s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit addition and subtraction with exchange.
+  \details It enables you to exchange the halfwords of the second operand, add the high halfwords
+           and subtract the low halfwords.
+  \param [in]    x   first operand for the subtraction in the low halfword,
+                     and the first operand for the addition in the high halfword.
+  \param [in]    y   second operand for the subtraction in the high halfword,
+                     and the second operand for the addition in the low halfword.
+  \return        the subtraction of the high halfword in the second operand from the
+                 low halfword in the first operand, in the low halfword of the return value.\n
+                 the addition of the high halfword in the first operand and the
+                 low halfword in the second operand, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = val1[15:0]  - val2[31:16]        \n
+                 res[31:16] = val1[31:16] + val2[15:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
+    s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned addition and subtraction with exchange.
+  \details This function enables you to exchange the two halfwords of the second operand,
+           add the high halfwords and subtract the low halfwords.
+  \param [in]    x   first operand for the subtraction in the low halfword,
+                     and the first operand for the addition in the high halfword.
+  \param [in]    y   second operand for the subtraction in the high halfword,
+                     and the second operand for the addition in the low halfword.
+  \return        the subtraction of the high halfword in the second operand from the
+                 low halfword in the first operand, in the low halfword of the return value.\n
+                 the addition of the high halfword in the first operand and the
+                 low halfword in the second operand, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = val1[15:0]  - val2[31:16]        \n
+                 res[31:16] = val1[31:16] + val2[15:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF;
+    s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit signed addition and subtraction with halved results.
+  \details This function enables you to exchange the two halfwords of one operand, perform one
+           signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
+  \param [in]    x   first 16-bit operands.
+  \param [in]    y   second 16-bit operands.
+  \return        the halved subtraction of the high halfword in the second operand from the
+                 low halfword in the first operand, in the low halfword of the return value.\n
+                 the halved addition of the low halfword in the second operand from the high
+                 halfword in the first operand, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1        \n
+                 res[31:16] = (val1[31:16] + val2[15:0]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned addition and subtraction with halved results and exchange.
+  \details This function enables you to exchange the halfwords of the second operand,
+           add the high halfwords and subtract the low halfwords, halving the results.
+  \param [in]    x   first operand for the subtraction in the low halfword, and
+                     the first operand for the addition in the high halfword.
+  \param [in]    y   second operand for the subtraction in the high halfword, and
+                     the second operand for the addition in the low halfword.
+  \return        the halved subtraction of the high halfword in the second operand from the
+                 low halfword in the first operand, in the low halfword of the return value.\n
+                 the halved addition of the low halfword in the second operand from the high
+                 halfword in the first operand, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1        \n
+                 res[31:16] = (val1[31:16] + val2[15:0]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF;
+    s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit subtract and add with exchange.
+  \details This function enables you to exchange the halfwords of one operand,
+           then subtract the high halfwords and add the low halfwords,
+           saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \param [in]    x   first operand for the addition in the low halfword,
+                     and the first operand for the subtraction in the high halfword.
+  \param [in]    y   second operand for the addition in the high halfword,
+                     and the second operand for the subtraction in the low halfword.
+  \return        the saturated addition of the low halfword of the first operand and the high
+                 halfword of the second operand, in the low halfword of the return value.\n
+                 the saturated subtraction of the low halfword of the second operand from the
+                 high halfword of the first operand, in the high halfword of the return value.\n
+                 The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1.
+  \remark
+                 res[15:0]  = val1[15:0]  + val2[31:16]        \n
+                 res[31:16] = val1[31:16] - val2[15:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned saturating subtraction and addition with exchange.
+  \details This function enables you to exchange the halfwords of the second operand and perform
+           one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating
+           the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
+  \param [in]    x   first operand for the addition in the low halfword,
+                     and the first operand for the subtraction in the high halfword.
+  \param [in]    y   second operand for the addition in the high halfword,
+                     and the second operand for the subtraction in the low halfword.
+  \return        the saturated addition of the low halfword of the first operand and the high
+                 halfword of the second operand, in the low halfword of the return value.\n
+                 the saturated subtraction of the low halfword of the second operand from the
+                 high halfword of the first operand, in the high halfword of the return value.\n
+                 The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1.
+  \remark
+                 res[15:0]  = val1[15:0]  + val2[31:16]        \n
+                 res[31:16] = val1[31:16] - val2[15:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF;
+    s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit unsigned subtract and add with exchange.
+  \details This function enables you to exchange the halfwords of the second operand,
+           subtract the high halfwords and add the low halfwords.
+  \param [in]    x   first operand for the addition in the low halfword,
+                     and the first operand for the subtraction in the high halfword.
+  \param [in]    y   second operand for the addition in the high halfword,
+                     and the second operand for the subtraction in the low halfword.
+  \return        the addition of the low halfword of the first operand and the high
+                 halfword of the second operand, in the low halfword of the return value.\n
+                 the subtraction of the low halfword of the second operand from the
+                 high halfword of the first operand, in the high halfword of the return value.\n
+  \remark
+                 res[15:0]  = val1[15:0]  + val2[31:16]        \n
+                 res[31:16] = val1[31:16] - val2[15:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF;
+    s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit signed subtraction and addition with exchange.
+  \details This function enables you to exchange the two halfwords of one operand and perform one
+           16-bit integer subtraction and one 16-bit addition.
+  \param [in]    x   first operand for the addition in the low halfword, and the first operand
+                     for the subtraction in the high halfword.
+  \param [in]    y   second operand for the addition in the high halfword, and the second
+                     operand for the subtraction in the low halfword.
+  \return        the addition of the low halfword of the first operand and the high
+                 halfword of the second operand, in the low halfword of the return value.\n
+                 the subtraction of the low halfword of the second operand from the
+                 high halfword of the first operand, in the high halfword of the return value.\n
+  \remark
+                 res[15:0]  = val1[15:0]  + val2[31:16]        \n
+                 res[31:16] = val1[31:16] - val2[15:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF;
+    s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+
+/**
+  \brief   Dual 16-bit signed subtraction and addition with halved results.
+  \details This function enables you to exchange the two halfwords of one operand, perform one signed
+           16-bit integer subtraction and one signed 16-bit addition, and halve the results.
+  \param [in]    x   first 16-bit operands.
+  \param [in]    y   second 16-bit operands.
+  \return        the halved addition of the low halfword in the first operand and the
+                 high halfword in the second operand, in the low halfword of the return value.\n
+                 the halved subtraction of the low halfword in the second operand from the
+                 high halfword in the first operand, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1        \n
+                 res[31:16] = (val1[31:16] - val2[15:0]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r)));
+}
+
+/**
+  \brief   Dual 16-bit unsigned subtraction and addition with halved results and exchange.
+  \details This function enables you to exchange the halfwords of the second operand,
+           subtract the high halfwords and add the low halfwords, halving the results.
+  \param [in]    x   first operand for the addition in the low halfword, and
+                     the first operand for the subtraction in the high halfword.
+  \param [in]    y   second operand for the addition in the high halfword, and
+                     the second operand for the subtraction in the low halfword.
+  \return        the halved addition of the low halfword in the first operand and the
+                 high halfword in the second operand, in the low halfword of the return value.\n
+                 the halved subtraction of the low halfword in the second operand from the
+                 high halfword in the first operand, in the high halfword of the return value.
+  \remark
+                 res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1        \n
+                 res[31:16] = (val1[31:16] - val2[15:0]) >> 1
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y)
+{
+    int32_t r, s;
+
+    r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF;
+    s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF;
+
+    return ((s << 16) | (r));
+}
+
+/**
+  \brief   Dual 16-bit signed multiply with exchange returning difference.
+  \details This function enables you to perform two 16-bit signed multiplications, subtracting
+           one of the products from the other. The halfwords of the second operand are exchanged
+           before performing the arithmetic. This produces top * bottom and bottom * top multiplication.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \return        the difference of the products of the two 16-bit signed multiplications.
+  \remark
+                 p1 = val1[15:0]  * val2[31:16]       \n
+                 p2 = val1[31:16] * val2[15:0]        \n
+                 res[31:0] = p1 - p2
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y)
+{
+    return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
+                       ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
+}
+
+/**
+  \brief   Sum of dual 16-bit signed multiply with exchange.
+  \details This function enables you to perform two 16-bit signed multiplications with exchanged
+           halfwords of the second operand, adding the products together.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \return        the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
+  \remark
+                 p1 = val1[15:0]  * val2[31:16]       \n
+                 p2 = val1[31:16] * val2[15:0]        \n
+                 res[31:0] = p1 + p2
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y)
+{
+    return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
+                       ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16))));
+}
+
+
+/**
+  \brief   Saturating add.
+  \details This function enables you to obtain the saturating add of two integers.
+  \param [in]    x   first summand of the saturating add operation.
+  \param [in]    y   second summand of the saturating add operation.
+  \return        the saturating addition of val1 and val2.
+  \remark
+                 res[31:0] = SAT(val1 + SAT(val2))
+ */
+__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
+{
+    int32_t result;
+
+    if (y >= 0) {
+        if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) {
+            result = x + y;
+        } else {
+            result = 0x7FFFFFFF;
+        }
+    } else {
+        if ((int32_t)((uint32_t)x + (uint32_t)y) < x) {
+            result = x + y;
+        } else {
+            result = 0x80000000;
+        }
+    }
+
+    return result;
+}
+
+/**
+  \brief   Saturating subtract.
+  \details This function enables you to obtain the saturating add of two integers.
+  \param [in]    x   first summand of the saturating add operation.
+  \param [in]    y   second summand of the saturating add operation.
+  \return        the saturating addition of val1 and val2.
+  \remark
+                 res[31:0] = SAT(val1 - SAT(val2))
+ */
+__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
+{
+    int64_t tmp;
+    int32_t result;
+
+    tmp = (int64_t)x - (int64_t)y;
+
+    if (tmp > 0x7fffffff) {
+        tmp = 0x7fffffff;
+    } else if (tmp < (-2147483647 - 1)) {
+        tmp = -2147483647 - 1;
+    }
+
+    result = tmp;
+    return result;
+}
+
+/**
+  \brief   Dual 16-bit signed multiply with single 32-bit accumulator.
+  \details This function enables you to perform two signed 16-bit multiplications,
+           adding both results to a 32-bit accumulate operand.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the product of each multiplication added to the accumulate value, as a 32-bit integer.
+  \remark
+                 p1 = val1[15:0]  * val2[15:0]      \n
+                 p2 = val1[31:16] * val2[31:16]     \n
+                 res[31:0] = p1 + p2 + val3[31:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum)
+{
+    return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
+                       ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
+                       (((int32_t)sum))));
+}
+
+/**
+  \brief   Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.
+  \details This function enables you to perform two signed 16-bit multiplications with exchanged
+           halfwords of the second operand, adding both results to a 32-bit accumulate operand.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the product of each multiplication with exchanged halfwords of the second
+                 operand added to the accumulate value, as a 32-bit integer.
+  \remark
+                 p1 = val1[15:0]  * val2[31:16]     \n
+                 p2 = val1[31:16] * val2[15:0]      \n
+                 res[31:0] = p1 + p2 + val3[31:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum)
+{
+    return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
+                       ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
+                       (((int32_t)sum))));
+}
+
+/**
+  \brief   Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
+  \details This function enables you to perform two 16-bit signed multiplications, take the
+           difference of the products, subtracting the high halfword product from the low
+           halfword product, and add the difference to a 32-bit accumulate operand.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the difference of the product of each multiplication, added to the accumulate value.
+  \remark
+                 p1 = val1[15:0]  * val2[15:0]       \n
+                 p2 = val1[31:16] * val2[31:16]      \n
+                 res[31:0] = p1 - p2 + val3[31:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum)
+{
+    return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
+                       ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
+                       (((int32_t)sum))));
+}
+
+/**
+  \brief   Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
+  \details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit
+           signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the difference of the product of each multiplication, added to the accumulate value.
+  \remark
+                 p1 = val1[15:0]  * val2[31:16]     \n
+                 p2 = val1[31:16] * val2[15:0]      \n
+                 res[31:0] = p1 - p2 + val3[31:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum)
+{
+    return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
+                       ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
+                       (((int32_t)sum))));
+}
+
+/**
+  \brief   Dual 16-bit signed multiply with single 64-bit accumulator.
+  \details This function enables you to perform two signed 16-bit multiplications, adding both results
+           to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition.
+           This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the product of each multiplication added to the accumulate value.
+  \remark
+                 p1 = val1[15:0]  * val2[15:0]      \n
+                 p2 = val1[31:16] * val2[31:16]     \n
+                 sum = p1 + p2 + val3[63:32][31:0]  \n
+                 res[63:32] = sum[63:32]            \n
+                 res[31:0]  = sum[31:0]
+ */
+__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum)
+{
+    return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
+                       ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
+                       (((uint64_t)sum))));
+}
+
+/**
+  \brief   Dual 16-bit signed multiply with exchange with single 64-bit accumulator.
+  \details This function enables you to exchange the halfwords of the second operand, and perform two
+           signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow
+           is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs.
+           Instead, the result wraps around modulo2^64.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the product of each multiplication added to the accumulate value.
+  \remark
+                 p1 = val1[15:0]  * val2[31:16]     \n
+                 p2 = val1[31:16] * val2[15:0]      \n
+                 sum = p1 + p2 + val3[63:32][31:0]  \n
+                 res[63:32] = sum[63:32]            \n
+                 res[31:0]  = sum[31:0]
+ */
+__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum)
+{
+    return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) +
+                       ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
+                       (((uint64_t)sum))));
+}
+
+/**
+  \brief   dual 16-bit signed multiply subtract with 64-bit accumulate.
+  \details This function It enables you to perform two 16-bit signed multiplications, take the difference
+           of the products, subtracting the high halfword product from the low halfword product, and add the
+           difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the
+           subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not
+           detected. Instead, the result wraps round to modulo2^64.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the difference of the product of each multiplication, added to the accumulate value.
+  \remark
+                 p1 = val1[15:0]  * val2[15:0]      \n
+                 p2 = val1[31:16] * val2[31:16]     \n
+                 res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
+ */
+__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum)
+{
+    return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
+                       ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) +
+                       (((uint64_t)sum))));
+}
+
+/**
+  \brief   Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.
+  \details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications,
+           adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the
+           multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow
+           is not detected. Instead, the result wraps round to modulo2^64.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the difference of the product of each multiplication, added to the accumulate value.
+  \remark
+                 p1 = val1[15:0]  * val2[31:16]      \n
+                 p2 = val1[31:16] * val2[15:0]       \n
+                 res[63:32][31:0] = p1 - p2 + val3[63:32][31:0]
+ */
+__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum)
+{
+    return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) -
+                       ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) +
+                       (((uint64_t)sum))));
+}
+
+/**
+  \brief   32-bit signed multiply with 32-bit truncated accumulator.
+  \details This function enables you to perform a signed 32-bit multiplications, adding the most
+           significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
+  \param [in]    x   first operand for multiplication.
+  \param [in]    y   second operand for multiplication.
+  \param [in]  sum   accumulate value.
+  \return        the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
+  \remark
+                 p = val1 * val2      \n
+                 res[31:0] = p[63:32] + val3[31:0]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum)
+{
+    return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum);
+}
+
+/**
+  \brief   Sum of dual 16-bit signed multiply.
+  \details This function enables you to perform two 16-bit signed multiplications, adding the products together.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \return        the sum of the products of the two 16-bit signed multiplications.
+  \remark
+                 p1 = val1[15:0]  * val2[15:0]      \n
+                 p2 = val1[31:16] * val2[31:16]     \n
+                 res[31:0] = p1 + p2
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y)
+{
+    return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) +
+                       ((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
+}
+
+/**
+  \brief   Dual 16-bit signed multiply returning difference.
+  \details This function enables you to perform two 16-bit signed multiplications, taking the difference
+           of the products by subtracting the high halfword product from the low halfword product.
+  \param [in]    x   first 16-bit operands for each multiplication.
+  \param [in]    y   second 16-bit operands for each multiplication.
+  \return        the difference of the products of the two 16-bit signed multiplications.
+  \remark
+                 p1 = val1[15:0]  * val2[15:0]      \n
+                 p2 = val1[31:16] * val2[31:16]     \n
+                 res[31:0] = p1 - p2
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y)
+{
+    return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) -
+                       ((((int32_t)x) >> 16) * (((int32_t)y) >> 16))));
+}
+
+/**
+  \brief   Dual extracted 8-bit to 16-bit signed addition.
+  \details This function enables you to extract two 8-bit values from the second operand (at bit positions
+           [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.
+  \param [in]    x   values added to the sign-extended to 16-bit values.
+  \param [in]    y   two 8-bit values to be extracted and sign-extended.
+  \return        the addition of val1 and val2, where the 8-bit values in val2[7:0] and
+                 val2[23:16] have been extracted and sign-extended prior to the addition.
+  \remark
+                 res[15:0]  = val1[15:0] + SignExtended(val2[7:0])      \n
+                 res[31:16] = val1[31:16] + SignExtended(val2[23:16])
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y)
+{
+    return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) |
+                       (((((int32_t)y <<  8) >>  8)  + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000)));
+}
+
+/**
+  \brief   Extracted 16-bit to 32-bit unsigned addition.
+  \details This function enables you to extract two 8-bit values from one operand, zero-extend
+           them to 16 bits each, and add the results to two 16-bit values from another operand.
+  \param [in]    x   values added to the zero-extended to 16-bit values.
+  \param [in]    y   two 8-bit values to be extracted and zero-extended.
+  \return        the addition of val1 and val2, where the 8-bit values in val2[7:0] and
+                 val2[23:16] have been extracted and zero-extended prior to the addition.
+  \remark
+                 res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]      \n
+                 res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y)
+{
+    return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) |
+                       ((((y <<  8) >>  8) + ((x >> 16) << 16)) & 0xFFFF0000)));
+}
+
+/**
+  \brief   Dual extract 8-bits and sign extend each to 16-bits.
+  \details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.
+  \param [in]    x   two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+  \return        the 8-bit values sign-extended to 16-bit values.\n
+                 sign-extended value of val[7:0] in the low halfword of the return value.\n
+                 sign-extended value of val[23:16] in the high halfword of the return value.
+  \remark
+                 res[15:0]  = SignExtended(val[7:0])       \n
+                 res[31:16] = SignExtended(val[23:16])
+ */
+__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x)
+{
+    return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) |
+                       ((((int32_t)x <<  8) >>  8) & (int32_t)0xFFFF0000)));
+}
+
+/**
+  \brief   Dual extract 8-bits and zero-extend to 16-bits.
+  \details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.
+  \param [in]    x   two 8-bit values in val[7:0] and val[23:16] to be zero-extended.
+  \return        the 8-bit values sign-extended to 16-bit values.\n
+                 sign-extended value of val[7:0] in the low halfword of the return value.\n
+                 sign-extended value of val[23:16] in the high halfword of the return value.
+  \remark
+                 res[15:0]  = SignExtended(val[7:0])       \n
+                 res[31:16] = SignExtended(val[23:16])
+ */
+__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x)
+{
+    return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) |
+                       (((x <<  8) >>  8) & 0xFFFF0000)));
+}
+
+#endif /* _CSI_RV32_GCC_H_ */
diff --git a/bsp/thead-smart/drivers/drv_common.h b/bsp/thead-smart/drivers/drv_common.h
new file mode 100644
index 0000000000..bc43b11e2c
--- /dev/null
+++ b/bsp/thead-smart/drivers/drv_common.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      Header File for Common Driver
+ */
+
+#ifndef _DRV_COMMON_H_
+#define _DRV_COMMON_H_
+
+#include <stdint.h>
+#include <drv_errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// \details driver handle
+typedef void *drv_handle_t;
+
+#ifndef CONFIG_PARAM_NOT_CHECK
+#define HANDLE_PARAM_CHK(para, err)                                                                \
+    do {                                                                                           \
+        if ((int32_t)para == (int32_t)NULL) {                                                      \
+            return (err);                                                                          \
+        }                                                                                          \
+    } while (0)
+
+#define HANDLE_PARAM_CHK_NORETVAL(para, err)                                                          \
+    do {                                                                                           \
+        if ((int32_t)para == (int32_t)NULL) {                                                      \
+            return;                                                                                \
+        }                                                                                          \
+    } while (0)
+#else
+#define HANDLE_PARAM_CHK(para, err)
+#define HANDLE_PARAM_CHK_NORETVAL(para, err)
+#endif
+
+/**
+\brief General power states
+*/
+typedef enum  
+{
+    DRV_POWER_OFF,                        ///< Power off: no operation possible
+    DRV_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+    DRV_POWER_FULL,                       ///< Power on: full operation at maximum performance
+    DRV_POWER_SUSPEND,                    ///< Power suspend: power saving operation
+} csi_power_stat_e;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_COMMON_H */
+
diff --git a/bsp/thead-smart/drivers/drv_errno.h b/bsp/thead-smart/drivers/drv_errno.h
new file mode 100644
index 0000000000..33fe6574de
--- /dev/null
+++ b/bsp/thead-smart/drivers/drv_errno.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for error num
+ */
+
+
+#ifndef _DRV_ERRNO_H_
+#define _DRV_ERRNO_H_
+
+#include <errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ERRNO_DRV_START 0X80
+
+/* driver General error codes */
+typedef enum
+{
+    DRV_ERROR = ERRNO_DRV_START,   ///< Unspecified error
+    DRV_ERROR_BUSY,                ///< Driver is busy
+    DRV_ERROR_TIMEOUT,             ///< Timeout occurred
+    DRV_ERROR_UNSUPPORTED,         ///< Operation not supported
+    DRV_ERROR_PARAMETER,           ///< Parameter error
+    DRV_ERROR_SPECIFIC             ///< Start of driver specific errors
+} drv_err_e;
+
+
+/** Get error type */
+#define GET_ERROR_TYPE(errno) \
+    (error & 0xFF000000 >> 24)
+/** Get error module */
+#define GET_ERROR_MODULE(error) \
+    (error & 0x00FF0000 >> 16)
+/** Get error API */
+#define GET_ERROR_API(error) \
+    (error & 0x0000FF00 >> 8)
+/** Get errno */
+#define GET_ERROR_NUM(error) \
+    (error & 0x000000FF)
+
+#ifndef CSI_DRV_ERRNO_BASE
+#define CSI_DRV_ERRNO_BASE                  0x81000000
+#endif
+
+/** driver module id definition*/
+#define CSI_DRV_ERRNO_GPIO_BASE             0x81010000
+#define CSI_DRV_ERRNO_USART_BASE            0x81020000
+#define CSI_DRV_ERRNO_SPI_BASE              0x81030000
+#define CSI_DRV_ERRNO_IIC_BASE              0x81040000
+#define CSI_DRV_ERRNO_PWM_BASE              0x81050000
+#define CSI_DRV_ERRNO_RTC_BASE              0x81060000
+#define CSI_DRV_ERRNO_TIMER_BASE            0x81070000
+#define CSI_DRV_ERRNO_WDT_BASE              0x81080000
+#define CSI_DRV_ERRNO_AES_BASE              0x81090000
+#define CSI_DRV_ERRNO_CRC_BASE              0x810A0000
+#define CSI_DRV_ERRNO_RSA_BASE              0x810B0000
+#define CSI_DRV_ERRNO_SHA_BASE              0x810C0000
+#define CSI_DRV_ERRNO_TRNG_BASE             0x810D0000
+#define CSI_DRV_ERRNO_EFLASH_BASE           0x810E0000
+#define CSI_DRV_ERRNO_DMA_BASE              0x810F0000
+#define CSI_DRV_ERRNO_NORFLASH_BASE         0x81100000
+#define CSI_DRV_ERRNO_INTC_BASE             0x81110000
+#define CSI_DRV_ERRNO_SPU_BASE              0x81120000
+#define CSI_DRV_ERRNO_ADC_BASE              0x81130000
+#define CSI_DRV_ERRNO_PMU_BASE              0x81140000
+#define CSI_DRV_ERRNO_BMU_BASE              0x81150000
+#define CSI_DRV_ERRNO_ETB_BASE              0x81160000
+#define CSI_DRV_ERRNO_I2S_BASE              0x81170000
+#define CSI_DRV_ERRNO_USI_BASE              0x81180000
+#define CSI_DRV_ERRNO_SPIFLASH_BASE         0x81190000
+#define CSI_DRV_ERRNO_ACMP_BASE             0x811A0000
+#define CSI_DRV_ERRNO_MAILBOX_BASE          0x811B0000
+#define CSI_DRV_ERRNO_EFUSEC_BASE           0x811C0000
+#define CSI_DRV_ERRNO_CODEC_BASE            0x811D0000
+#define CSI_DRV_ERRNO_DPU_BASE              0x811E0000
+#define CSI_DRV_ERRNO_VPU_BASE              0x811F0000
+#define CSI_DRV_ERRNO_CAMERA_BASE           0x81200000
+#define CSI_DRV_ERRNO_MIPI_CSI_BASE         0x81210000
+#define CSI_DRV_ERRNO_MIPI_CSI_READER_BASE  0x81220000
+#define CSI_DRV_ERRNO_GMAC_BASE             0x81230000
+#define CSI_DRV_ERRNO_ETHPHY_BASE           0x81240000
+#define CSI_DRV_ERRNO_QW_EFUSE_BASE         0x81250000
+#define CSI_DRV_ERRNO_RESET_BASE            0x81260000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CSI_DRV_ERRNO_H */
diff --git a/bsp/thead-smart/drivers/drv_gpio.h b/bsp/thead-smart/drivers/drv_gpio.h
new file mode 100644
index 0000000000..1ee5944a69
--- /dev/null
+++ b/bsp/thead-smart/drivers/drv_gpio.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for gpio driver
+ */
+
+#ifndef _CSI_GPIO_H_
+#define _CSI_GPIO_H_
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// definition for gpio pin handle.
+typedef void *gpio_pin_handle_t;
+
+/****** GPIO specific error codes *****/
+typedef enum
+{
+    GPIO_ERROR_MODE  = (DRV_ERROR_SPECIFIC + 1),      ///< Specified Mode not supported
+    GPIO_ERROR_DIRECTION,                        ///< Specified direction not supported
+    GPIO_ERROR_IRQ_MODE,                         ///< Specified irq mode not supported
+} gpio_error_e;
+
+/*----- GPIO Control Codes: Mode -----*/
+typedef enum
+{
+    GPIO_MODE_PULLNONE         = 0,    ///< pull none for input
+    GPIO_MODE_PULLUP,                  ///< pull up for input
+    GPIO_MODE_PULLDOWN,                ///< pull down for input
+    GPIO_MODE_OPEN_DRAIN,              ///< open drain mode for output
+    GPIO_MODE_PUSH_PULL,               ///< push-pull mode for output
+} gpio_mode_e;
+
+/*----- GPIO Control Codes: Mode Parameters: Data Bits -----*/
+typedef enum
+{
+    GPIO_DIRECTION_INPUT             = 0,    ///< gpio as input
+    GPIO_DIRECTION_OUTPUT,                   ///< gpio as output
+} gpio_direction_e;
+
+/*----- GPIO Control Codes: Mode Parameters: Parity -----*/
+typedef enum
+{
+    GPIO_IRQ_MODE_RISING_EDGE     = 0,       ///< interrupt mode for rising edge
+    GPIO_IRQ_MODE_FALLING_EDGE,              ///< interrupt mode for falling edge
+    GPIO_IRQ_MODE_DOUBLE_EDGE,               ///< interrupt mode for double edge
+    GPIO_IRQ_MODE_LOW_LEVEL,                 ///< interrupt mode for low level
+    GPIO_IRQ_MODE_HIGH_LEVEL,                ///< interrupt mode for high level
+} gpio_irq_mode_e;
+
+typedef void (*gpio_event_cb_t)(int32_t idx);   ///< gpio Event call back.
+
+/**
+  \brief       Initialize GPIO handle.
+  \param[in]   gpio_pin    gpio pin idx.
+  \param[in]   cb_event  event callback function \ref gpio_event_cb_t
+  \return      gpio_pin_handle
+*/
+gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event);
+
+/**
+  \brief       De-initialize GPIO pin handle.stops operation and releases the software resources used by the handle.
+  \param[in]   handle    gpio pin handle to operate.
+  \return      error code
+*/
+int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle);
+
+/**
+  \brief       control gpio power.
+  \param[in]   handle  gpio handle to operate.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state);
+
+/**
+  \brief       config pin mode
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   mode      \ref gpio_mode_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle,
+                                 gpio_mode_e mode);
+
+/**
+  \brief       config pin direction
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   dir       \ref gpio_direction_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle,
+                                      gpio_direction_e dir);
+
+/**
+  \brief       config pin
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   mode      \ref gpio_mode_e
+  \param[in]   dir       \ref gpio_direction_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config(gpio_pin_handle_t handle,
+                            gpio_mode_e mode,
+                            gpio_direction_e dir);
+
+/**
+  \brief       Set one or zero to the selected GPIO pin.
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   value     value to be set
+  \return      error code
+*/
+int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value);
+
+/**
+  \brief       Get the value of  selected GPIO pin.
+  \param[in]   pin       gpio pin handle to operate.
+  \param[out]  value     buffer to store the pin value
+  \return      error code
+*/
+int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value);
+
+/**
+  \brief       set GPIO interrupt mode.
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   mode      irq mode to be set
+  \param[in]   enable    enable flag
+  \return      error code
+*/
+int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_GPIO_H_ */
diff --git a/bsp/thead-smart/drivers/drv_irq.h b/bsp/thead-smart/drivers/drv_irq.h
new file mode 100644
index 0000000000..80c2edddd9
--- /dev/null
+++ b/bsp/thead-smart/drivers/drv_irq.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header File for IRQ Driver
+ */
+
+#include <stdint.h>
+
+/**
+  \brief       enable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_enable(uint32_t irq_num);
+
+/**
+  \brief       disable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_disable(uint32_t irq_num);
+
+/**
+  \brief       register irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \param[in]   irq_handler IRQ Handler.
+  \return      None.
+*/
+void drv_irq_register(uint32_t irq_num, void *irq_handler);
+
+/**
+  \brief       unregister irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \param[in]   irq_handler IRQ Handler.
+  \return      None.
+*/
+void drv_irq_unregister(uint32_t irq_num);
diff --git a/bsp/thead-smart/drivers/drv_timer.h b/bsp/thead-smart/drivers/drv_timer.h
new file mode 100644
index 0000000000..12feda3c4c
--- /dev/null
+++ b/bsp/thead-smart/drivers/drv_timer.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      timer driver header file
+ */
+
+/******************************************************************************
+ * @file     drv_timer.h
+ * @brief    header file for timer driver
+ * @version  V1.0
+ * @date     02. June 2017
+ * @model    timer
+ ******************************************************************************/
+
+#ifndef _CSI_TIMER_H_
+#define _CSI_TIMER_H_
+
+
+#include <stdint.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// definition for timer handle.
+typedef void *timer_handle_t;
+
+/*----- TIMER Control Codes: Mode -----*/
+typedef enum
+{
+    TIMER_MODE_FREE_RUNNING                 = 0,   ///< free running mode
+    TIMER_MODE_RELOAD                              ///< reload mode
+} timer_mode_e;
+
+/**
+\brief TIMER Status
+*/
+typedef struct
+{
+    uint32_t active   : 1;                        ///< timer active flag
+    uint32_t timeout  : 1;                        ///< timeout flag
+} timer_status_t;
+
+/**
+\brief TIMER Event
+*/
+typedef enum
+{
+    TIMER_EVENT_TIMEOUT  = 0   ///< time out event
+} timer_event_e;
+
+typedef void (*timer_event_cb_t)(int32_t idx, timer_event_e event);   ///< Pointer to \ref timer_event_cb_t : TIMER Event call back.
+
+/**
+  \brief       Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function
+  \param[in]   idx  timer index
+  \param[in]   cb_event  event call back function \ref timer_event_cb_t
+  \param[in]   cb_arg    arguments of cb_event
+  \return      pointer to timer instance
+*/
+timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event);
+
+/**
+  \brief       De-initialize TIMER Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_uninitialize(timer_handle_t handle);
+
+/**
+  \brief       control timer power.
+  \param[in]   handle  timer handle to operate.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state);
+
+/**
+  \brief       config timer mode.
+  \param[in]   handle timer handle to operate.
+  \param[in]   mode      \ref timer_mode_e
+  \return      error code
+*/
+int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode);
+
+/**
+  \brief       Set timeout just for the reload mode.
+  \param[in]   handle timer handle to operate.
+  \param[in]   timeout the timeout value in microseconds(us).
+  \return      error code
+*/
+int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout);
+
+/**
+  \brief       Start timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_start(timer_handle_t handle);
+
+/**
+  \brief       Stop timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_stop(timer_handle_t handle);
+
+/**
+  \brief       suspend timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_suspend(timer_handle_t handle);
+
+/**
+  \brief       resume timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_resume(timer_handle_t handle);
+
+/**
+  \brief       get timer current value
+  \param[in]   handle timer handle to operate.
+  \param[out]   value     timer current value
+  \return      error code
+*/
+int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value);
+
+/**
+  \brief       Get TIMER status.
+  \param[in]   handle timer handle to operate.
+  \return      TIMER status \ref timer_status_t
+*/
+timer_status_t csi_timer_get_status(timer_handle_t handle);
+
+/**
+  \brief       get timer reload value
+  \param[in]   handle timer handle to operate.
+  \param[out]   value    timer reload value
+  \return      error code
+*/
+int32_t csi_timer_get_load_value(timer_handle_t handle, uint32_t *value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_TIMER_H_ */
+
diff --git a/bsp/thead-smart/drivers/drv_usart.h b/bsp/thead-smart/drivers/drv_usart.h
new file mode 100644
index 0000000000..57a69fead6
--- /dev/null
+++ b/bsp/thead-smart/drivers/drv_usart.h
@@ -0,0 +1,446 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for usart driver
+ */
+
+#ifndef _CSI_USART_H_
+#define _CSI_USART_H_
+
+
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// definition for usart handle.
+typedef void *usart_handle_t;
+
+/****** USART specific error codes *****/
+typedef enum
+{
+    USART_ERROR_MODE  = (DRV_ERROR_SPECIFIC + 1),      ///< Specified Mode not supported
+    USART_ERROR_BAUDRATE,                         ///< Specified baudrate not supported
+    USART_ERROR_DATA_BITS,                        ///< Specified number of Data bits not supported
+    USART_ERROR_PARITY,                           ///< Specified Parity not supported
+    USART_ERROR_STOP_BITS,                        ///< Specified number of Stop bits not supported
+    USART_ERROR_FLOW_CONTROL,                     ///< Specified Flow Control not supported
+    USART_ERROR_CPOL,                             ///< Specified Clock Polarity not supported
+    USART_ERROR_CPHA                              ///< Specified Clock Phase not supported
+} usart_error_e;
+
+/*----- USART Control Codes: Mode -----*/
+typedef enum
+{
+    USART_MODE_ASYNCHRONOUS         = 0,   ///< USART (Asynchronous)
+    USART_MODE_SYNCHRONOUS_MASTER,         ///< Synchronous Master
+    USART_MODE_SYNCHRONOUS_SLAVE,          ///< Synchronous Slave (external clock signal)
+    USART_MODE_SINGLE_WIRE,                 ///< USART Single-wire (half-duplex)
+    USART_MODE_SINGLE_IRDA,                 ///< UART IrDA
+    USART_MODE_SINGLE_SMART_CARD,           ///< UART Smart Card
+} usart_mode_e;
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+typedef enum
+{
+    USART_DATA_BITS_5             = 0,    ///< 5 Data bits
+    USART_DATA_BITS_6,                    ///< 6 Data bit
+    USART_DATA_BITS_7,                    ///< 7 Data bits
+    USART_DATA_BITS_8,                    ///< 8 Data bits (default)
+    USART_DATA_BITS_9                     ///< 9 Data bits
+} usart_data_bits_e;
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+typedef enum
+{
+    USART_PARITY_NONE            = 0,       ///< No Parity (default)
+    USART_PARITY_EVEN,                      ///< Even Parity
+    USART_PARITY_ODD,                       ///< Odd Parity
+    USART_PARITY_1,                         ///< Parity forced to 1
+    USART_PARITY_0                          ///< Parity forced to 0
+} usart_parity_e;
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+typedef enum
+{
+    USART_STOP_BITS_1            = 0,    ///< 1 Stop bit (default)
+    USART_STOP_BITS_2,                   ///< 2 Stop bits
+    USART_STOP_BITS_1_5,                 ///< 1.5 Stop bits
+    USART_STOP_BITS_0_5                  ///< 0.5 Stop bits
+} usart_stop_bits_e;
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+typedef enum
+{
+    USART_CPOL0                  = 0,    ///< CPOL = 0 (default). data are captured on rising edge (low->high transition)
+    USART_CPOL1                          ///< CPOL = 1. data are captured on falling edge (high->lowh transition)
+} usart_cpol_e;
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+typedef enum
+{
+    USART_CPHA0                  = 0,   ///< CPHA = 0 (default). sample on first (leading) edge
+    USART_CPHA1                         ///< CPHA = 1. sample on second (trailing) edge
+} usart_cpha_e;
+
+/*----- USART Control Codes: flush data type-----*/
+typedef enum
+{
+    USART_FLUSH_WRITE,
+    USART_FLUSH_READ
+} usart_flush_type_e;
+
+/*----- USART Control Codes: flow control type-----*/
+typedef enum
+{
+    USART_FLOWCTRL_NONE,
+    USART_FLOWCTRL_CTS,
+    USART_FLOWCTRL_RTS,
+    USART_FLOWCTRL_CTS_RTS
+} usart_flowctrl_type_e;
+
+/*----- USART Modem Control -----*/
+typedef enum
+{
+    USART_RTS_CLEAR,                  ///< Deactivate RTS
+    USART_RTS_SET,                    ///< Activate RTS
+    USART_DTR_CLEAR,                  ///< Deactivate DTR
+    USART_DTR_SET                     ///< Activate DTR
+} usart_modem_ctrl_e;
+
+/*----- USART Modem Status -----*/
+typedef struct
+{
+    uint32_t cts : 1;                     ///< CTS state: 1=Active, 0=Inactive
+    uint32_t dsr : 1;                     ///< DSR state: 1=Active, 0=Inactive
+    uint32_t dcd : 1;                     ///< DCD state: 1=Active, 0=Inactive
+    uint32_t ri  : 1;                     ///< RI  state: 1=Active, 0=Inactive
+} usart_modem_stat_t;
+
+/*----- USART Control Codes: on-off intrrupte type-----*/
+typedef enum
+{
+    USART_INTR_WRITE,
+    USART_INTR_READ
+} usart_intr_type_e;
+
+/**
+\brief USART Status
+*/
+typedef struct  {
+    uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+    uint32_t rx_busy          : 1;        ///< Receiver busy flag
+    uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)(Synchronous Slave)
+    uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+    uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)
+    uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)
+    uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)
+    uint32_t tx_enable        : 1;        ///< Transmitter enable flag
+    uint32_t rx_enable        : 1;        ///< Receiver enbale flag
+} usart_status_t;
+
+/****** USART Event *****/
+typedef enum
+{
+    USART_EVENT_SEND_COMPLETE       = 0,  ///< Send completed; however USART may still transmit data
+    USART_EVENT_RECEIVE_COMPLETE    = 1,  ///< Receive completed
+    USART_EVENT_TRANSFER_COMPLETE   = 2,  ///< Transfer completed
+    USART_EVENT_TX_COMPLETE         = 3,  ///< Transmit completed (optional)
+    USART_EVENT_TX_UNDERFLOW        = 4,  ///< Transmit data not available (Synchronous Slave)
+    USART_EVENT_RX_OVERFLOW         = 5,  ///< Receive data overflow
+    USART_EVENT_RX_TIMEOUT          = 6,  ///< Receive character timeout (optional)
+    USART_EVENT_RX_BREAK            = 7,  ///< Break detected on receive
+    USART_EVENT_RX_FRAMING_ERROR    = 8,  ///< Framing error detected on receive
+    USART_EVENT_RX_PARITY_ERROR     = 9,  ///< Parity error detected on receive
+    USART_EVENT_CTS                 = 10, ///< CTS state changed (optional)
+    USART_EVENT_DSR                 = 11, ///< DSR state changed (optional)
+    USART_EVENT_DCD                 = 12, ///< DCD state changed (optional)
+    USART_EVENT_RI                  = 13, ///< RI  state changed (optional)
+    USART_EVENT_RECEIVED            = 14, ///< Data Received, only in usart fifo, call receive()/transfer() get the data
+} usart_event_e;
+
+typedef void (*usart_event_cb_t)(int32_t idx, usart_event_e event);   ///< Pointer to \ref usart_event_cb_t : USART Event call back.
+
+/**
+\brief USART Driver Capabilities.
+*/
+typedef struct  {
+    uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode
+    uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode
+    uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode
+    uint32_t single_wire        : 1;      ///< supports UART Single-wire mode
+    uint32_t irda               : 1;      ///< supports UART IrDA mode
+    uint32_t smart_card         : 1;      ///< supports UART Smart Card mode
+    uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available
+    uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available
+    uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available
+    uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \ref USART_EVENT_TX_COMPLETE
+    uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \ref USART_EVENT_RX_TIMEOUT
+    uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available
+    uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available
+    uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available
+    uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available
+    uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available
+    uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available
+    uint32_t event_cts          : 1;      ///< Signal CTS change event: \ref USART_EVENT_CTS
+    uint32_t event_dsr          : 1;      ///< Signal DSR change event: \ref USART_EVENT_DSR
+    uint32_t event_dcd          : 1;      ///< Signal DCD change event: \ref USART_EVENT_DCD
+    uint32_t event_ri           : 1;      ///< Signal RI change event: \ref USART_EVENT_RI
+} usart_capabilities_t;
+
+/**
+  \brief       Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function
+  \param[in]   idx usart index
+  \param[in]   cb_event  event call back function \ref usart_event_cb_t
+  \return      return usart handle if success
+*/
+usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event);
+
+/**
+  \brief       De-initialize USART Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_uninitialize(usart_handle_t handle);
+/**
+  \brief       Get driver capabilities.
+  \param[in]   idx usart index
+  \return      \ref usart_capabilities_t
+*/
+usart_capabilities_t csi_usart_get_capabilities(int32_t idx);
+
+/**
+  \brief       config usart mode.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   baud      baud rate.
+  \param[in]   mode      \ref usart_mode_e .
+  \param[in]   parity    \ref usart_parity_e .
+  \param[in]   stopbits  \ref usart_stop_bits_e .
+  \param[in]   bits      \ref usart_data_bits_e .
+  \return      error code
+*/
+int32_t csi_usart_config(usart_handle_t handle,
+                         uint32_t baud,
+                         usart_mode_e mode,
+                         usart_parity_e parity,
+                         usart_stop_bits_e stopbits,
+                         usart_data_bits_e bits);
+
+
+/**
+  \brief       Start sending data to USART transmitter,(received data is ignored).
+               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
+               \ref csi_usart_get_status can get operation status.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num   Number of data items to send
+  \return      error code
+*/
+int32_t csi_usart_send(usart_handle_t handle, const void *data, uint32_t num);
+
+/**
+  \brief       Abort Send data to USART transmitter
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_send(usart_handle_t handle);
+
+/**
+  \brief       Start receiving data from USART receiver. \n
+               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
+               \ref csi_usart_get_status can get operation status.
+  \param[in]   handle  usart handle to operate.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num   Number of data items to receive
+  \return      error code
+*/
+int32_t csi_usart_receive(usart_handle_t handle, void *data, uint32_t num);
+
+/**
+  \brief       query data from UART receiver FIFO.
+  \param[in]   handle  usart handle to operate.
+  \param[out]  data  Pointer to buffer for data to receive from UART receiver
+  \param[in]   num   Number of data items to receive
+  \return      fifo data num to receive
+*/
+int32_t csi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num);
+
+/**
+  \brief       Abort Receive data from USART receiver
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_receive(usart_handle_t handle);
+
+/**
+  \brief       Start synchronously sends data to the USART transmitter and receives data from the USART receiver. used in synchronous mode
+               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
+               \ref csi_usart_get_status can get operation status.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num       Number of data items to transfer
+  \return      error code
+*/
+int32_t csi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num);
+
+/**
+  \brief       abort sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_transfer(usart_handle_t handle);
+
+/**
+  \brief       Get USART status.
+  \param[in]   handle  usart handle to operate.
+  \return      USART status \ref usart_status_t
+*/
+usart_status_t csi_usart_get_status(usart_handle_t handle);
+
+/**
+  \brief       flush receive/send data.
+  \param[in]   handle usart handle to operate.
+  \param[in]   type \ref usart_flush_type_e .
+  \return      error code
+*/
+int32_t csi_usart_flush(usart_handle_t handle, usart_flush_type_e type);
+
+/**
+  \brief       set interrupt mode.
+  \param[in]   handle usart handle to operate.
+  \param[in]   type \ref usart_intr_type_e.
+  \param[in]   flag 0-OFF, 1-ON.
+  \return      error code
+*/
+int32_t csi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag);
+
+/**
+  \brief       set the baud rate of usart.
+  \param[in]   baud  usart base to operate.
+  \param[in]   baudrate baud rate
+  \return      error code
+*/
+int32_t csi_usart_config_baudrate(usart_handle_t handle, uint32_t baud);
+
+/**
+  \brief       config usart mode.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   mode    \ref usart_mode_e
+  \return      error code
+*/
+int32_t csi_usart_config_mode(usart_handle_t handle, usart_mode_e mode);
+
+/**
+  \brief       config usart parity.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   parity    \ref usart_parity_e
+  \return      error code
+*/
+int32_t csi_usart_config_parity(usart_handle_t handle, usart_parity_e parity);
+
+/**
+  \brief       config usart stop bit number.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   stopbits  \ref usart_stop_bits_e
+  \return      error code
+*/
+int32_t csi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit);
+
+/**
+  \brief       config usart data length.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   databits      \ref usart_data_bits_e
+  \return      error code
+*/
+int32_t csi_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits);
+
+/**
+  \brief       get character in query mode.
+  \param[in]   handle  usart handle to operate.
+  \param[out]  ch the pointer to the received character.
+  \return      error code
+*/
+int32_t csi_usart_getchar(usart_handle_t handle, uint8_t *ch);
+
+/**
+  \brief       transmit character in query mode.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   ch  the input character
+  \return      error code
+*/
+int32_t csi_usart_putchar(usart_handle_t handle, uint8_t ch);
+
+/**
+  \brief       Get usart send data count.
+  \param[in]   handle  usart handle to operate.
+  \return      number of currently transmitted data bytes
+*/
+uint32_t csi_usart_get_tx_count(usart_handle_t handle);
+
+/**
+  \brief       Get usart received data count.
+  \param[in]   handle  usart handle to operate.
+  \return      number of currently received data bytes
+*/
+uint32_t csi_usart_get_rx_count(usart_handle_t handle);
+
+/**
+  \brief       control usart power.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_usart_power_control(usart_handle_t handle, csi_power_stat_e state);
+
+/**
+  \brief       config usart flow control type.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   flowctrl_type   flow control type.\ref usart_flowctrl_type_e.
+  \return      error code
+*/
+int32_t csi_usart_config_flowctrl(usart_handle_t handle,
+                                  usart_flowctrl_type_e flowctrl_type);
+
+/**
+  \brief       config usart clock Polarity and Phase.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   cpol    Clock Polarity.\ref usart_cpol_e.
+  \param[in]   cpha    Clock Phase.\ref usart_cpha_e.
+  \return      error code
+*/
+int32_t csi_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha);
+
+/**
+  \brief       control the transmitter.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   enable  1 - enable the transmitter. 0 - disable the transmitter
+  \return      error code
+*/
+int32_t csi_usart_control_tx(usart_handle_t handle, uint32_t enable);
+
+/**
+  \brief       control the receiver.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   enable  1 - enable the receiver. 0 - disable the receiver
+  \return      error code
+*/
+int32_t csi_usart_control_rx(usart_handle_t handle, uint32_t enable);
+
+/**
+  \brief       control the break.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   enable  1- Enable continuous Break transmission,0 - disable continuous Break transmission
+  \return      error code
+*/
+int32_t csi_usart_control_break(usart_handle_t handle, uint32_t enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_USART_H_ */
diff --git a/bsp/thead-smart/drivers/dw_gpio.c b/bsp/thead-smart/drivers/dw_gpio.c
new file mode 100644
index 0000000000..9ee3a3e429
--- /dev/null
+++ b/bsp/thead-smart/drivers/dw_gpio.c
@@ -0,0 +1,635 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      gpio driver
+ */
+
+/******************************************************************************
+ * @file     dw_gpio.c
+ * @brief    CSI Source File for GPIO Driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#include <csi_config.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <drv_irq.h>
+#include <drv_gpio.h>
+#include <dw_gpio.h>
+#include <csi_core.h>
+#include <pin_name.h>
+
+extern int32_t drv_pin_config_mode(port_name_e port, uint8_t offset, gpio_mode_e pin_mode);
+
+#define ERR_GPIO(errno) (CSI_DRV_ERRNO_GPIO_BASE | errno)
+#define GPIO_NULL_PARAM_CHK(para)    HANDLE_PARAM_CHK(para, ERR_GPIO(DRV_ERROR_PARAMETER))
+
+typedef void *gpio_port_handle_t;
+
+typedef struct 
+{
+#ifdef CONFIG_LPM
+    uint8_t gpio_power_status;
+    uint32_t gpio_regs_saved[7];
+#endif
+    uint32_t base;              ///< handle register base
+    uint32_t irq;               ///< irq of this handle
+    uint32_t pin_num;           ///< pin number of this handle
+    gpio_mode_e mode;           ///< gpio mode
+    gpio_direction_e dir;       ///< gpio direction
+    uint32_t mask;              ///< gpio mask bit
+    uint32_t value;             ///< gpio value
+} dw_gpio_priv_t;
+
+typedef struct 
+{
+    uint8_t     portidx;
+    uint8_t     idx;
+    uint8_t     offset;
+    gpio_event_cb_t cb;
+} dw_gpio_pin_priv_t;
+
+extern int32_t target_gpio_port_init(port_name_e port, uint32_t *base, uint32_t *irq, void **handler, uint32_t *pin_num);
+extern int32_t target_gpio_pin_init(int32_t gpio_pin, uint32_t *port_idx);
+
+static dw_gpio_priv_t gpio_handle[CONFIG_GPIO_NUM];
+static dw_gpio_pin_priv_t gpio_pin_handle[CONFIG_GPIO_PIN_NUM];
+
+//
+// Functions
+//
+static int32_t gpio_set_direction(
+    void *port,
+    gpio_direction_e direction
+)
+{
+    dw_gpio_priv_t *gpio_priv = port;
+    dw_gpio_reg_t *gpio_reg = (dw_gpio_reg_t *)(gpio_priv->base);
+
+    if (direction == GPIO_DIRECTION_INPUT) 
+    {
+        gpio_reg->SWPORT_DDR &= (~gpio_priv->mask);
+    } else if (direction == GPIO_DIRECTION_OUTPUT) 
+    {
+        gpio_reg->SWPORT_DDR |= gpio_priv->mask;
+    } else 
+    {
+        return ERR_GPIO(GPIO_ERROR_DIRECTION);
+    }
+
+    return 0;
+}
+
+/*
+ * Read the statu of the Port choosed.
+ * Parameters:
+ *   port:  use to choose a I/O port among Port A, B, or C.
+ * return: the value of the corresponding Port.
+ */
+
+static int32_t gpio_read(void *port, uint32_t *value)
+{
+    dw_gpio_priv_t *gpio_priv = port;
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(gpio_priv->base + 0x30);
+    *value = gpio_control_reg->EXT_PORTA;
+    return 0;
+}
+
+
+/*
+ * Write an output value to corresponding Port.
+ * Parameters:
+ *   port:  use to choose a I/O port among Port A, B, or C.
+ *   output: value that will be written to the corresponding Port.
+ * return: SUCCESS
+ */
+
+static int32_t gpio_write(void *port, uint32_t mask)
+{
+    dw_gpio_priv_t *gpio_priv = port;
+    dw_gpio_reg_t *gpio_reg = (dw_gpio_reg_t *)(gpio_priv->base);
+
+    uint32_t value = gpio_reg->SWPORT_DR;
+
+    value &= ~(mask);
+    value |= gpio_priv->value;
+    gpio_reg->SWPORT_DR = value;
+    return 0;
+}
+
+/**
+ * Configure a GPIO gpio_set_irq_mode.
+ * @param[in]   pin         the addr store the pin num.
+ * @param[in]   _irqmode    the irqmode of gpio
+ * @return      zero on success. -1 on falure.
+ */
+static int32_t gpio_set_irq_mode(gpio_pin_handle_t pin, gpio_irq_mode_e irq_mode)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = pin;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30);
+    uint32_t offset = gpio_pin_priv->idx;
+    uint32_t mask = 1 << offset;
+
+    switch (irq_mode) 
+    {
+        /* rising edge interrupt mode */
+        case GPIO_IRQ_MODE_RISING_EDGE:
+            gpio_control_reg->INTTYPE_LEVEL |= mask;
+            gpio_control_reg->INT_POLARITY |= mask;
+            break;
+
+        /* falling edge interrupt mode */
+        case GPIO_IRQ_MODE_FALLING_EDGE:
+            gpio_control_reg->INTTYPE_LEVEL |= mask;
+            gpio_control_reg->INT_POLARITY &= (~mask);
+            break;
+
+        /* low level interrupt mode */
+        case GPIO_IRQ_MODE_LOW_LEVEL:
+            gpio_control_reg->INTTYPE_LEVEL &= (~mask);
+            gpio_control_reg->INT_POLARITY &= (~mask);
+            break;
+
+        /* high level interrupt mode */
+        case GPIO_IRQ_MODE_HIGH_LEVEL:
+            gpio_control_reg->INTTYPE_LEVEL &= (~mask);
+            gpio_control_reg->INT_POLARITY |= mask;
+            break;
+
+        /* double edge interrupt mode */
+        case GPIO_IRQ_MODE_DOUBLE_EDGE:
+            return ERR_GPIO(DRV_ERROR_UNSUPPORTED);
+
+        default:
+            return ERR_GPIO(GPIO_ERROR_IRQ_MODE);
+    }
+
+    return 0;
+}
+
+/*
+ * Clear one or more interrupts of PortA.
+ * Parameters:
+ *   pinno:
+ * return: SUCCESS.
+ */
+
+static void gpio_irq_clear(gpio_pin_handle_t pin, uint32_t idx)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = pin;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30);
+
+    gpio_control_reg->PORTA_EOI = idx;
+}
+
+
+/*
+ * Enable one or more interrupts of PortA.
+ * Parameters:
+ *   pinno:
+ * return: SUCCESS.
+ */
+static void gpio_irq_enable(gpio_pin_handle_t pin)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = pin;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30);
+    uint32_t offset = gpio_pin_priv->idx;
+    uint32_t val = gpio_control_reg->INTEN;
+    val |= (1 << offset);
+    gpio_control_reg->INTEN = val;
+}
+
+
+/*
+ * Disable one or more interrupts of PortA.
+ * Parameters:
+ *   pinno:
+ * return: SUCCESS.
+ */
+
+static void gpio_irq_disable(gpio_pin_handle_t pin)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = pin;
+    uint32_t offset = gpio_pin_priv->idx;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30);
+    uint32_t val = gpio_control_reg->INTEN;
+    val &= ~(1 << offset);
+    gpio_control_reg->INTEN = val;
+}
+
+void dw_gpio_irqhandler(int idx)
+{
+    if (idx >= CONFIG_GPIO_NUM) 
+    {
+        return;
+    }
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(gpio_handle[idx].base + 0x30);
+
+    uint32_t value = gpio_control_reg->INTSTATUS;
+    uint8_t i;
+
+    /* find the interrput pin */
+    for (i = 0; i < 32; i++) 
+    {
+        if (value & (1U << i)) 
+        {
+            uint32_t pin_idx = i;
+
+#ifndef CONFIG_CHIP_DANICA
+            uint8_t j;
+
+            if (idx > 0) 
+            {
+                for (j = 0; j < idx; j++) 
+                {
+                    pin_idx += gpio_handle[j].pin_num;
+                }
+            }
+
+            if (pin_idx >= CONFIG_GPIO_PIN_NUM) 
+            {
+                return;
+            }
+
+#endif
+            dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)&gpio_pin_handle[pin_idx];
+
+            gpio_irq_clear(gpio_pin_priv, (1 << i));  //clear the gpio interrupt
+
+            /* execute the callback function */
+            if ((gpio_event_cb_t)(gpio_pin_priv->cb)) 
+            {
+                ((gpio_event_cb_t)(gpio_pin_priv->cb))(gpio_pin_priv->offset);
+            }
+        }
+    }
+}
+
+/**
+  \brief       Initialize GPIO module. 1. Initializes the resources needed for the GPIO handle 2.registers event callback function
+                3.get gpio_port_handle
+  \param[in]   port      port_name.
+  \return      gpio_port_handle
+*/
+gpio_port_handle_t csi_gpio_port_initialize(int32_t port)
+{
+    dw_gpio_priv_t *gpio_priv = NULL;
+
+    /* obtain the gpio port information */
+    uint32_t base = 0u;
+    uint32_t pin_num;
+    uint32_t irq;
+    void *handler;
+    int32_t idx = target_gpio_port_init(port, &base, &irq, &handler, &pin_num);
+
+    if (idx < 0 || idx >= CONFIG_GPIO_NUM) 
+    {
+        return NULL;
+    }
+
+    gpio_priv = &gpio_handle[idx];
+
+    gpio_priv->base = base;
+    gpio_priv->irq  = irq;
+    gpio_priv->pin_num  = pin_num;
+
+#ifdef CONFIG_LPM
+    csi_gpio_power_control(gpio_priv, DRV_POWER_FULL);
+#endif
+
+    drv_irq_register(gpio_priv->irq, handler);
+    drv_irq_enable(gpio_priv->irq);
+
+    return (gpio_port_handle_t)gpio_priv;
+}
+
+/**
+  \brief       De-initialize GPIO handle. stops operation and releases the software resources used by the handle
+  \param[in]   handle   gpio port handle to operate.
+  \return      error code
+*/
+int32_t csi_gpio_port_uninitialize(gpio_port_handle_t handle)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    dw_gpio_priv_t *gpio_priv = handle;
+
+    drv_irq_disable(gpio_priv->irq);
+    drv_irq_unregister(gpio_priv->irq);
+
+#ifdef CONFIG_LPM
+    csi_gpio_power_control(gpio_priv, DRV_POWER_OFF);
+#endif
+
+    return 0;
+}
+
+#ifdef CONFIG_LPM
+static void manage_clock(gpio_pin_handle_t handle, uint8_t enable)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle;
+    uint8_t device[] = {CLOCK_MANAGER_GPIO0, CLOCK_MANAGER_GPIO1};
+
+    drv_clock_manager_config(device[gpio_pin_priv->portidx], enable);
+}
+
+static void do_prepare_sleep_action(void *handle)
+{
+    dw_gpio_priv_t *gpio_handle = handle;
+    uint32_t *gbase = (uint32_t *)(gpio_handle->base);
+    uint32_t *control_base = (uint32_t *)(gpio_handle->base + 0x30);
+    registers_save(gpio_handle->gpio_regs_saved, gbase, 3);
+    registers_save(&gpio_handle->gpio_regs_saved[3], control_base, 4);
+}
+
+static void do_wakeup_sleep_action(void *handle)
+{
+    dw_gpio_priv_t *gpio_handle = handle;
+    uint32_t *gbase = (uint32_t *)(gpio_handle->base);
+    uint32_t *control_base = (uint32_t *)(gpio_handle->base + 0x30);
+    registers_restore(gbase, gpio_handle->gpio_regs_saved, 3);
+    registers_restore(control_base, &gpio_handle->gpio_regs_saved[3], 4);
+}
+#endif
+
+/**
+  \brief       Initialize GPIO handle.
+  \param[in]   gpio_pin    Pointer to the int32_t.
+  \param[in]   cb_event    Pointer to \ref gpio_event_cb_t.
+  \param[in]   arg    Pointer to \ref arg used for the callback.
+  \return      gpio_pin_handle
+*/
+gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event)
+{
+
+    if (gpio_pin < 0 || gpio_pin >= CONFIG_GPIO_PIN_NUM) 
+    {
+        return NULL;
+    }
+
+    uint32_t i;
+
+    for (i = 0; i < CONFIG_GPIO_NUM; i++) 
+    {
+        csi_gpio_port_initialize(i);
+    }
+
+    /* obtain the gpio pin information */
+    uint32_t port_idx;
+    int32_t pin_idx = target_gpio_pin_init(gpio_pin, &port_idx);
+
+    if (pin_idx < 0) 
+    {
+        return NULL;
+    }
+
+    int32_t idx = pin_idx;
+
+    for (i = 0; i < port_idx; i++) 
+    {
+        idx += (gpio_handle[i].pin_num);
+    }
+
+    dw_gpio_pin_priv_t *gpio_pin_priv = &(gpio_pin_handle[idx]);
+    gpio_pin_priv->portidx = port_idx;
+
+
+    gpio_pin_priv->idx = pin_idx;
+    gpio_pin_priv->cb = cb_event;
+    gpio_pin_priv->offset = gpio_pin;
+
+    return (gpio_pin_handle_t)gpio_pin_priv;
+}
+
+/**
+  \brief       De-initialize GPIO pin handle. stops operation and releases the software resources used by the handle
+  \param[in]   handle   gpio pin handle to operate.
+  \return      error code
+*/
+int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle)
+{
+    if (handle == NULL) 
+    {
+        return ERR_GPIO(DRV_ERROR_PARAMETER);
+    }
+
+    dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle;
+    gpio_pin_priv->cb = NULL;
+
+    gpio_irq_disable(handle);
+
+    return 0;
+}
+
+/**
+  \brief       control gpio power.
+  \param[in]   idx  gpio index.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+#ifdef CONFIG_LPM
+    dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle;
+    power_cb_t callback = 
+    {
+        .wakeup = do_wakeup_sleep_action,
+        .sleep = do_prepare_sleep_action,
+        .manage_clock = manage_clock
+    };
+    return drv_soc_power_control(&gpio_handle[gpio_pin_priv->portidx], state, &callback);
+#else
+    return ERR_GPIO(DRV_ERROR_UNSUPPORTED);
+#endif
+}
+
+/**
+  \brief       config pin mode
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   mode      \ref gpio_mode_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle,
+                                 gpio_mode_e mode)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    /* config the gpio pin mode direction mask bits */
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+
+    uint8_t offset = gpio_pin_priv->idx;
+
+    int32_t ret = drv_pin_config_mode(gpio_pin_priv->portidx, offset, mode);
+
+    return ret;
+}
+/**
+  \brief       config pin direction
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   dir       \ref gpio_direction_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle,
+                                      gpio_direction_e dir)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    /* config the gpio pin mode direction mask bits */
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *gpio_priv = &gpio_handle[gpio_pin_priv->portidx];
+
+    gpio_priv->dir = dir;
+    gpio_priv->mask = 1 << gpio_pin_priv->idx;
+
+    uint32_t ret = gpio_set_direction(gpio_priv, dir);
+
+    if (ret) 
+    {
+        return ret;
+    }
+
+    return 0;
+}
+
+/**
+  \brief       config pin
+  \param[in]   handle       gpio pin handle to operate.
+  \param[in]   mode      \ref gpio_mode_e
+  \param[in]   dir       \ref gpio_direction_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config(gpio_pin_handle_t handle,
+                            gpio_mode_e mode,
+                            gpio_direction_e dir)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    /* config the gpio pin mode direction mask bits */
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *gpio_priv = &gpio_handle[gpio_pin_priv->portidx];
+
+    gpio_priv->mode = mode;
+    gpio_priv->dir = dir;
+    gpio_priv->mask = 1 << gpio_pin_priv->idx;
+
+    uint32_t ret = gpio_set_direction(gpio_priv, dir);
+
+    if (ret) 
+    {
+        return ret;
+    }
+
+    return 0;
+
+}
+
+/**
+  \brief       Set one or zero to the selected GPIO pin.
+  \param[in]   handle       gpio pin handle to operate.
+  \param[in]   value     the value to be set
+  \return      error code
+*/
+int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    uint8_t offset = gpio_pin_priv->idx;
+    uint32_t port_value = value << offset;
+
+    port_handle->value = port_value;
+    gpio_write(port_handle, (1 << offset));
+
+    return 0;
+
+}
+
+/**
+  \brief       Get the value of  selected GPIO pin.
+  \param[in]   handle       gpio pin handle to operate.
+  \param[out]  value     buf to store the pin value
+  \return      error code
+*/
+int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+    GPIO_NULL_PARAM_CHK(value);
+
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+    uint32_t port_value;
+    uint8_t offset = gpio_pin_priv->idx;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    gpio_read(port_handle, &port_value);
+    *value = (port_value & (1 << offset)) >> offset;
+
+    return 0;
+}
+
+/**
+  \brief       set GPIO interrupt mode.
+  \param[in]   handle       gpio pin handle to operate.
+  \param[in]   mode      the irq mode to be set
+  \param[in]   enable    the enable flag
+  \return      error code
+*/
+int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    uint32_t ret = 0;
+
+    if (enable) 
+    {
+        ret = gpio_set_irq_mode(handle, mode);
+
+        if (ret) 
+        {
+            return ret;
+        }
+
+        gpio_irq_enable(handle);
+
+    } else 
+    {
+        gpio_irq_disable(handle);
+
+    }
+
+    return ret;
+}
+
diff --git a/bsp/thead-smart/drivers/dw_gpio.h b/bsp/thead-smart/drivers/dw_gpio.h
new file mode 100644
index 0000000000..768cdf1b1d
--- /dev/null
+++ b/bsp/thead-smart/drivers/dw_gpio.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for GPIO Driver
+ */
+
+#ifndef _DW_GPIO_H_
+#define _DW_GPIO_H_
+
+#include "drv_gpio.h"
+#include "soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef struct 
+{
+    __IOM uint32_t SWPORT_DR;                     /* Offset: 0x000 (W/R)  PortA data register */
+    __IOM uint32_t SWPORT_DDR;                    /* Offset: 0x004 (W/R)  PortA data direction register */
+    __IOM uint32_t PORT_CTL;                      /* Offset: 0x008 (W/R)  PortA source register */
+
+} dw_gpio_reg_t;
+
+typedef struct
+{
+    __IOM uint32_t INTEN;                         /* Offset: 0x000 (W/R)  Interrupt enable register */
+    __IOM uint32_t INTMASK;                       /* Offset: 0x004 (W/R)  Interrupt mask register */
+    __IOM uint32_t INTTYPE_LEVEL;                 /* Offset: 0x008 (W/R)  Interrupt level register */
+    __IOM uint32_t INT_POLARITY;                  /* Offset: 0x00c (W/R)  Interrupt polarity register */
+    __IM  uint32_t INTSTATUS;                     /* Offset: 0x010 (R)    Interrupt status of Port */
+    __IM  uint32_t RAWINTSTATUS;                  /* Offset: 0x014 (W/R)  Raw interrupt status of Port */
+    __IOM uint32_t revreg1;                       /* Offset: 0x018 (W/R)  Reserve register */
+    __OM  uint32_t PORTA_EOI;                     /* Offset: 0x01c (W/R)  Port clear interrupt register */
+    __IM  uint32_t EXT_PORTA;                     /* Offset: 0x020 (W/R)  PortA external port register */
+    __IM  uint32_t EXT_PORTB;                     /* Offset: 0x024 (W/R)  PortB external port register */
+    __IOM uint32_t revreg2[2];                    /* Offset: 0x028 (W/R)  Reserve register */
+    __IOM uint32_t LS_SYNC;                       /* Offset: 0x030 (W/R)  Level-sensitive synchronization enable register */
+
+} dw_gpio_control_reg_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/bsp/thead-smart/drivers/dw_timer.c b/bsp/thead-smart/drivers/dw_timer.c
new file mode 100644
index 0000000000..5792d47a73
--- /dev/null
+++ b/bsp/thead-smart/drivers/dw_timer.c
@@ -0,0 +1,409 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Source File for timer Driver
+ */
+
+
+#include <csi_config.h>
+#include <drv_irq.h>
+#include <drv_timer.h>
+#include <dw_timer.h>
+#include <soc.h>
+#include <csi_core.h>
+
+#define ERR_TIMER(errno) (CSI_DRV_ERRNO_TIMER_BASE | errno)
+
+#define TIMER_NULL_PARAM_CHK(para)  HANDLE_PARAM_CHK(para, ERR_TIMER(DRV_ERROR_PARAMETER))
+
+typedef struct 
+{
+#ifdef CONFIG_LPM
+    uint8_t timer_power_status;
+    uint32_t timer_regs_saved[2];
+#endif
+    uint8_t idx;
+    uint32_t base;
+    uint32_t irq;
+    timer_event_cb_t cb_event;
+    uint32_t timeout;                  ///< the set time (us)
+    uint32_t timeout_flag;
+} dw_timer_priv_t;
+
+extern int32_t target_get_timer_count(void);
+extern int32_t target_get_timer(int32_t idx, uint32_t *base, uint32_t *irq, void **handler);
+
+static dw_timer_priv_t timer_instance[CONFIG_TIMER_NUM];
+/**
+  \brief      Make all the timers in the idle state.
+  \param[in]  pointer to timer register base
+*/
+static void timer_deactive_control(dw_timer_reg_t *addr)
+{
+    /* stop the corresponding timer */
+    addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE;
+    /* Disable interrupt. */
+    addr->TxControl |= DW_TIMER_TXCONTROL_INTMASK;
+}
+
+void dw_timer_irqhandler(int idx)
+{
+    dw_timer_priv_t *timer_priv = &timer_instance[idx];
+    timer_priv->timeout_flag = 1;
+
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    addr->TxEOI;
+
+    if (timer_priv->cb_event) 
+    {
+        return timer_priv->cb_event(idx, TIMER_EVENT_TIMEOUT);
+    }
+
+}
+
+#ifdef CONFIG_LPM
+static void manage_clock(timer_handle_t handle, uint8_t enable)
+{
+    if (handle == &timer_instance[0] || handle == &timer_instance[1]) 
+    {
+        drv_clock_manager_config(CLOCK_MANAGER_TIM, enable);
+    } else if (handle == &timer_instance[3] || handle == &timer_instance[2]) 
+    {
+        drv_clock_manager_config(CLOCK_MANAGER_TIM1, enable);
+    }
+}
+
+static void do_prepare_sleep_action(timer_handle_t handle)
+{
+    dw_timer_priv_t *timer_priv = (dw_timer_priv_t *)handle;
+    uint32_t *tbase = (uint32_t *)(timer_priv->base);
+    registers_save(timer_priv->timer_regs_saved, tbase, 1);
+    registers_save(&timer_priv->timer_regs_saved[1], tbase + 2, 1);
+}
+
+static void do_wakeup_sleep_action(timer_handle_t handle)
+{
+    dw_timer_priv_t *timer_priv = (dw_timer_priv_t *)handle;
+    uint32_t *tbase = (uint32_t *)(timer_priv->base);
+    registers_restore(tbase, timer_priv->timer_regs_saved, 1);
+    registers_restore(tbase + 2, &timer_priv->timer_regs_saved[1], 1);
+}
+#endif
+
+/**
+  \brief       Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function
+  \param[in]   idx  instance timer index
+  \param[in]   cb_event  Pointer to \ref timer_event_cb_t
+  \return      pointer to timer instance
+*/
+timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event)
+{
+    if (idx < 0 || idx >= CONFIG_TIMER_NUM) 
+    {
+        return NULL;
+    }
+
+    uint32_t base = 0u;
+    uint32_t irq = 0u;
+    void *handler;
+
+    int32_t real_idx = target_get_timer(idx, &base, &irq, &handler);
+
+    if (real_idx != idx) 
+    {
+        return NULL;
+    }
+
+    dw_timer_priv_t *timer_priv = &timer_instance[idx];
+    timer_priv->base = base;
+    timer_priv->irq  = irq;
+    timer_priv->idx = idx;
+
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+    timer_priv->timeout = DW_TIMER_INIT_DEFAULT_VALUE;
+
+#ifdef CONFIG_LPM
+    csi_timer_power_control(timer_priv, DRV_POWER_FULL);
+#endif
+
+    timer_deactive_control(addr);
+    timer_priv->cb_event = cb_event;
+
+    if (cb_event != NULL) 
+    {
+        drv_irq_register(timer_priv->irq, handler);
+        drv_irq_enable(timer_priv->irq);
+    }
+
+    return (timer_handle_t)timer_priv;
+}
+
+/**
+  \brief       De-initialize TIMER Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_uninitialize(timer_handle_t handle)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+
+    dw_timer_priv_t *timer_priv = (dw_timer_priv_t *)handle;
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    timer_deactive_control(addr);
+    timer_priv->cb_event = NULL;
+
+    drv_irq_disable(timer_priv->irq);
+    drv_irq_unregister(timer_priv->irq);
+
+#ifdef CONFIG_LPM
+    csi_timer_power_control(timer_priv, DRV_POWER_OFF);
+#endif
+
+    return 0;
+}
+
+int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+#ifdef CONFIG_LPM
+    power_cb_t callback = 
+    {
+        .wakeup = do_wakeup_sleep_action,
+        .sleep = do_prepare_sleep_action,
+        .manage_clock = manage_clock
+    };
+    return drv_soc_power_control(handle, state, &callback);
+#else
+    return ERR_TIMER(DRV_ERROR_UNSUPPORTED);
+#endif
+}
+
+/**
+  \brief       config timer mode.
+  \param[in]   handle timer handle to operate.
+  \param[in]   mode      \ref timer_mode_e
+  \return      error code
+*/
+int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+
+    dw_timer_priv_t *timer_priv = handle;
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    switch (mode) 
+    {
+        case TIMER_MODE_FREE_RUNNING:
+            addr->TxControl &= ~DW_TIMER_TXCONTROL_MODE;
+            break;
+
+        case TIMER_MODE_RELOAD:
+            addr->TxControl |= DW_TIMER_TXCONTROL_MODE;
+            break;
+
+        default:
+            return ERR_TIMER(DRV_ERROR_PARAMETER);
+    }
+
+    addr->TxControl |= (DW_TIMER_TXCONTROL_TRIGGER);
+
+    return 0;
+}
+
+/**
+  \brief       Set timer.
+  \param[in]   instance  timer instance to operate.
+  \param[in]   timeout the timeout value in microseconds(us).
+  \return      error code
+*/
+int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+
+    dw_timer_priv_t *timer_priv = handle;
+    timer_priv->timeout = timeout;
+    return 0;
+}
+
+/**
+  \brief       Start timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+
+int32_t csi_timer_start(timer_handle_t handle)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+
+    dw_timer_priv_t *timer_priv = handle;
+
+    timer_priv->timeout_flag = 0;
+
+    uint32_t min_us = drv_get_timer_freq(timer_priv->idx) / 1000000;
+    uint32_t load;
+
+    if (((timer_priv->timeout * drv_get_timer_freq(timer_priv->idx)) / 1000000) > 0xffffffff) 
+    {
+        return ERR_TIMER(DRV_ERROR_PARAMETER);
+    }
+
+    if (min_us) 
+    {
+        load = (uint32_t)(timer_priv->timeout * min_us);
+    } else 
+    {
+        load = (uint32_t)(((uint64_t)(timer_priv->timeout) * drv_get_timer_freq(timer_priv->idx)) / 1000000);
+    }
+
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    if (timer_priv->timeout == 0) {
+        addr->TxLoadCount = 0xffffffff;                           /* load time(us) */
+    } else 
+    {
+        if ((addr->TxControl | 0x2) == 0x2) {
+            addr->TxLoadCount = 0xffffffff;                           /* load time(us) */
+        } else 
+        {
+            addr->TxLoadCount = load;                           /* load time(us) */
+        }
+    }
+
+    addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE;      /* disable the timer */
+    addr->TxControl |= DW_TIMER_TXCONTROL_ENABLE;       /* enable the corresponding timer */
+    addr->TxControl &= ~DW_TIMER_TXCONTROL_INTMASK;     /* enable interrupt */
+
+    /* avoid timer bug on yunvoice soc */
+#ifdef CONFIG_CHIP_YUNVOICE
+
+    if (addr->TxCurrentValue > addr->TxLoadCount) {
+        addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE;      /* disable the timer */
+        addr->TxControl |= DW_TIMER_TXCONTROL_ENABLE;       /* enable the corresponding timer */
+        addr->TxControl &= ~DW_TIMER_TXCONTROL_INTMASK;     /* enable interrupt */
+    }
+
+#endif
+
+    return 0;
+}
+
+/**
+  \brief       Stop timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_stop(timer_handle_t handle)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+
+    dw_timer_priv_t *timer_priv = handle;
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    addr->TxControl |= DW_TIMER_TXCONTROL_INTMASK;      /* enable interrupt */
+    addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE;      /* disable the timer */
+
+    return 0;
+}
+
+/**
+  \brief       suspend timer.
+  \param[in]   instance  timer instance to operate.
+  \return      error code
+*/
+int32_t csi_timer_suspend(timer_handle_t handle)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+
+    return ERR_TIMER(DRV_ERROR_UNSUPPORTED);
+}
+
+/**
+  \brief       resume timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_resume(timer_handle_t handle)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+
+    dw_timer_priv_t *timer_priv = handle;
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE;      /* stop the corresponding timer */
+    addr->TxControl &= DW_TIMER_TXCONTROL_ENABLE;       /* restart the corresponding timer */
+
+    return 0;
+}
+
+/**
+  \brief       get timer current value
+  \param[in]   handle timer handle to operate.
+  \param[out]   value     timer current value
+  \return      error code
+*/
+int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+    TIMER_NULL_PARAM_CHK(value);
+
+    dw_timer_priv_t *timer_priv = handle;
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    *value = addr->TxCurrentValue;
+    return 0;
+}
+
+/**
+  \brief       Get TIMER status.
+  \param[in]   handle timer handle to operate.
+  \return      TIMER status \ref timer_status_t
+*/
+timer_status_t csi_timer_get_status(timer_handle_t handle)
+{
+    timer_status_t timer_status = {0};
+
+    if (handle == NULL) 
+    {
+        return timer_status;
+    }
+
+    dw_timer_priv_t *timer_priv = handle;
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    if (addr->TxControl & DW_TIMER_TXCONTROL_ENABLE) 
+    {
+        timer_status.active = 1;
+    }
+
+    if (timer_priv->timeout_flag == 1) 
+    {
+        timer_status.timeout = 1;
+    }
+
+    return timer_status;
+}
+
+/**
+  \brief       get timer reload value
+  \param[in]   handle timer handle to operate.
+  \param[out]   value    timer reload value
+  \return      error code
+*/
+int32_t csi_timer_get_load_value(timer_handle_t handle, uint32_t *value)
+{
+    TIMER_NULL_PARAM_CHK(handle);
+    TIMER_NULL_PARAM_CHK(value);
+
+    dw_timer_priv_t *timer_priv = handle;
+    dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
+
+    *value = addr->TxLoadCount;
+    return 0;
+}
+
diff --git a/bsp/thead-smart/drivers/dw_timer.h b/bsp/thead-smart/drivers/dw_timer.h
new file mode 100644
index 0000000000..7b418cac70
--- /dev/null
+++ b/bsp/thead-smart/drivers/dw_timer.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for timer driver
+ */
+
+#ifndef __DW_TIMER_H
+#define __DW_TIMER_H
+
+#include <stdio.h>
+#include "soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  define the bits for TxControl
+ */
+#define DW_TIMER_TXCONTROL_ENABLE      (1UL << 0)
+#define DW_TIMER_TXCONTROL_MODE        (1UL << 1)
+#define DW_TIMER_TXCONTROL_INTMASK     (1UL << 2)
+#define DW_TIMER_TXCONTROL_TRIGGER     (1UL << 4)
+
+#define DW_TIMER_INIT_DEFAULT_VALUE     (0xffffffff / drv_get_timer_freq(0) * 1000000)
+
+typedef struct
+{
+    __IOM uint32_t TxLoadCount;              /* Offset: 0x000 (R/W)  Receive buffer register */
+    __IM  uint32_t TxCurrentValue;            /* Offset: 0x004 (R)  Transmission hold register */
+    __IOM uint8_t  TxControl: 5;              /* Offset: 0x008 (R/W)  Clock frequency division low section register */
+    uint8_t  	   RESERVED0[3];
+    __IM  uint8_t  TxEOI: 1;                   /* Offset: 0x00c (R)  Clock frequency division high section register */
+    uint8_t  	   RESERVED1[3];
+    __IM  uint8_t  TxIntStatus: 1;             /* Offset: 0x010 (R)  Interrupt enable register */
+    uint8_t  	   RESERVED2[3];
+} dw_timer_reg_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DW_TIMER_H */
+
diff --git a/bsp/thead-smart/drivers/isr.c b/bsp/thead-smart/drivers/isr.c
new file mode 100644
index 0000000000..1a42a81bcf
--- /dev/null
+++ b/bsp/thead-smart/drivers/isr.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      source file for the interrupt server route
+ */
+
+#include <drv_common.h>
+#include <csi_config.h>
+#include "soc.h"
+
+#ifndef CONFIG_SYSTICK_HZ
+#define CONFIG_SYSTICK_HZ 100
+#endif
+
+extern volatile uint32_t rt_thread_switch_interrupt_flag;
+
+extern void ck_usart_irqhandler(int32_t idx);
+extern void dw_timer_irqhandler(int32_t idx);
+extern void dw_gpio_irqhandler(int32_t idx);
+extern void systick_handler(void);
+extern void xPortSysTickHandler(void);
+extern void OSTimeTick(void);
+
+#define  ATTRIBUTE_ISR
+
+#define readl(addr) \
+    ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+
+#if(CONFIG_KERNEL_RTTHREAD == 1)
+#define  CSI_INTRPT_ENTER()  rt_interrupt_enter()
+#define  CSI_INTRPT_EXIT()   rt_interrupt_leave()
+#endif
+
+
+void __attribute__((isr)) SysTick_Handler(void)
+{
+#if(CONFIG_KERNEL_RTTHREAD == 1)
+    CSI_INTRPT_ENTER();
+#endif
+
+    csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, CORET_IRQn);
+    
+#if defined(CONFIG_KERNEL_RHINO)
+    systick_handler();
+#elif defined(CONFIG_KERNEL_FREERTOS)
+    xPortSysTickHandler();
+#elif defined(CONFIG_KERNEL_RTTHREAD)
+    rt_tick_increase();
+#elif defined(CONFIG_KERNEL_UCOS)
+    OSTimeTick();
+#endif
+
+#if(CONFIG_KERNEL_RTTHREAD == 1)
+    CSI_INTRPT_EXIT();
+#endif
+}
+
+ATTRIBUTE_ISR void USART_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    ck_usart0_irqhandler();
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void TIM0_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(0);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void TIM1_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(1);
+    CSI_INTRPT_EXIT();
+}
+ATTRIBUTE_ISR void TIM2_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(2);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void TIM3_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(3);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void TIM4_NMIHandler(void)
+{
+    dw_timer_irqhandler(4);
+}
+
+ATTRIBUTE_ISR void TIM6_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(6);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void TIM7_IRQHandler(void)
+{
+    dw_timer_irqhandler(7);
+}
+
+ATTRIBUTE_ISR void TIM8_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(8);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void TIM9_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(9);
+    CSI_INTRPT_EXIT();
+}
+ATTRIBUTE_ISR void TIM10_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(10);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void TIM11_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_timer_irqhandler(11);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void GPIO0_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_gpio_irqhandler(0);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void GPIO1_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_gpio_irqhandler(1);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void GPIO2_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_gpio_irqhandler(2);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void GPIO3_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_gpio_irqhandler(3);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void GPIO4_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_gpio_irqhandler(4);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void GPIO5_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_gpio_irqhandler(5);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void GPIO6_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_gpio_irqhandler(6);
+    CSI_INTRPT_EXIT();
+}
+
+ATTRIBUTE_ISR void GPIO7_IRQHandler(void)
+{
+    CSI_INTRPT_ENTER();
+    dw_gpio_irqhandler(7);
+    CSI_INTRPT_EXIT();
+}
diff --git a/bsp/thead-smart/drivers/novic_irq_tbl.c b/bsp/thead-smart/drivers/novic_irq_tbl.c
new file mode 100644
index 0000000000..cadfac5f98
--- /dev/null
+++ b/bsp/thead-smart/drivers/novic_irq_tbl.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      novic table init
+ */
+
+#include <csi_config.h>
+#include <soc.h>
+
+extern void Default_Handler(void);
+extern void SysTick_Handler(void);
+extern void TIM4_NMIHandler(void);
+
+void (*g_irqvector[48])(void);
+void (*g_nmivector)(void);
+
+void irq_vectors_init(void)
+{
+    int i;
+
+    for (i = 0; i < 48; i++) 
+    {
+        g_irqvector[i] = Default_Handler;
+    }
+
+    g_irqvector[CORET_IRQn] = SysTick_Handler;
+    g_nmivector = TIM4_NMIHandler;
+}
diff --git a/bsp/thead-smart/drivers/pin_name.h b/bsp/thead-smart/drivers/pin_name.h
new file mode 100644
index 0000000000..78aa4bc18a
--- /dev/null
+++ b/bsp/thead-smart/drivers/pin_name.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for the pin_name
+ */
+
+#ifndef _PINNAMES_H
+#define _PINNAMES_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef enum
+{
+    PA0 = 0,
+    PA1,
+    PA2,
+    PA3,
+    PA4,
+    PA5,
+    PA6,
+    PA7,
+    PAD_UART0_SIN,
+    PAD_UART0_SOUT
+}
+pin_name_e;
+
+typedef enum
+{
+    PORTA = 0,
+    PORTB = 1,
+    PORTC = 2,
+    PORTD = 3,
+    PORTE = 4,
+    PORTF = 5,
+    PORTG = 6,
+    PORTH = 7
+} port_name_e;
+
+typedef enum
+{
+    NONE = 0
+} pin_func_e;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/thead-smart/drivers/soc.h b/bsp/thead-smart/drivers/soc.h
new file mode 100644
index 0000000000..656e944995
--- /dev/null
+++ b/bsp/thead-smart/drivers/soc.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Core Peripheral Access Layer Header File for
+ *                             CSKYSOC Device Series
+ */
+
+#ifndef _SOC_H_
+#define _SOC_H_
+
+#include <stdint.h>
+#include <csi_core.h>
+#include <sys_freq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef IHS_VALUE
+#define  IHS_VALUE    (20000000)
+#endif
+
+#ifndef EHS_VALUE
+#define  EHS_VALUE    (20000000)
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+typedef enum IRQn {
+    NMI_EXPn                        =   -2,      /* NMI Exception */
+    /* ----------------------  SmartL Specific Interrupt Numbers  --------------------- */
+    Machine_Software_IRQn           =   3,      /* Machine software interrupt */
+    User_Timer_IRQn                 =   4,      /* User timer interrupt */
+    Supervisor_Timer_IRQn           =   5,      /* Supervisor timer interrupt */
+    CORET_IRQn                      =   7,      /* core Timer Interrupt */
+    Machine_External_IRQn           =   11,     /* Machine external interrupt */
+    UART_IRQn                       =   16,     /* uart Interrupt */
+    TIM0_IRQn                       =   18,     /* timer0 Interrupt */
+    TIM1_IRQn                       =   19,     /* timer1 Interrupt */
+    TIM2_IRQn                       =   20,     /* timer2 Interrupt */
+    TIM3_IRQn                       =   21,     /* timer3 Interrupt */
+    GPIO0_IRQn                      =   23,     /* gpio0 Interrupt */
+    GPIO1_IRQn                      =   24,     /* gpio1 Interrupt */
+    GPIO2_IRQn                      =   25,     /* gpio2 Interrupt */
+    GPIO3_IRQn                      =   26,     /* gpio3 Interrupt */
+    GPIO4_IRQn                      =   27,     /* gpio4 Interrupt */
+    GPIO5_IRQn                      =   28,     /* gpio5 Interrupt */
+    GPIO6_IRQn                      =   29,     /* gpio6 Interrupt */
+    GPIO7_IRQn                      =   30,     /* gpio7 Interrupt */
+    STIM0_IRQn                      =   31,     /* stimer0 Interrupt */
+    STIM1_IRQn                      =   32,     /* stimer1 Interrupt */
+    STIM2_IRQn                      =   33,     /* stimer2 Interrupt */
+    STIM3_IRQn                      =   34,     /* stimer3 Interrupt */
+    PAD_IRQn                        =   35,     /* pad Interrupt */
+    TIM6_IRQn                       =   36,     /* timer6 Interrupt */
+    TIM7_IRQn                       =   37,     /* timer7 Interrupt */
+    TIM8_IRQn                       =   38,     /* timer8 Interrupt */
+    TIM9_IRQn                       =   39,     /* timer9 Interrupt */
+    TIM10_IRQn                      =   40,     /* timer10 Interrupt */
+    TIM11_IRQn                      =   41,     /* timer11 Interrupt */
+}
+IRQn_Type;
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+#define CONFIG_TIMER_NUM    12
+#define CONFIG_USART_NUM    1
+#define CONFIG_GPIO_NUM     8
+#define CONFIG_GPIO_PIN_NUM 8
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+/* --------------------------  CPU FPGA memory map  ------------------------------- */
+#define CSKY_SRAM_BASE              (0x20000000UL)
+
+#define CSKY_UART_BASE              (0x40015000UL)
+#define CSKY_PMU_BASE               (0x40016000UL)
+#define CSKY_TIMER0_BASE            (0x40011000UL)
+#define CSKY_TIMER1_BASE            (0x40011014UL)
+#define CSKY_TIMER2_BASE            (0x40011028UL)
+#define CSKY_TIMER3_BASE            (0x4001103cUL)
+#define CSKY_TIMER4_BASE            (0x40021000UL)
+#define CSKY_TIMER5_BASE            (0x40021014UL)
+#define CSKY_TIMER6_BASE            (0x40021028UL)
+#define CSKY_TIMER7_BASE            (0x4002103cUL)
+#define CSKY_TIMER8_BASE            (0x40031000UL)
+#define CSKY_TIMER9_BASE            (0x40031014UL)
+#define CSKY_TIMER10_BASE           (0x40031028UL)
+#define CSKY_TIMER11_BASE           (0x4003103cUL)
+
+#define CSKY_TIMER_CONTROL_BASE     (0x400110a0UL)
+#define CSKY_CLK_GEN_BASE           (0x40017000UL)
+#define CSKY_STIMER0_BASE           (0x40018000UL)
+#define CSKY_STIMER1_BASE           (0x40018014UL)
+#define CSKY_STIMER2_BASE           (0x40018028UL)
+#define CSKY_STIMER3_BASE           (0x4001803cUL)
+#define CSKY_STIMER_CONTROL_BASE    (0x400110a0UL)
+
+#define CSKY_GPIOA_BASE             (0x40019000UL)
+#define CSKY_GPIOA_CONTROL_BASE     (0x40019030UL)
+#define CSKY_SMPU_BASE              (0x4001a000UL)
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+#define CSKY_UART                  ((   CSKY_UART_TypeDef *)    CSKY_UART_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_H_ */
diff --git a/bsp/thead-smart/drivers/startup_gcc.S b/bsp/thead-smart/drivers/startup_gcc.S
new file mode 100644
index 0000000000..f71164c599
--- /dev/null
+++ b/bsp/thead-smart/drivers/startup_gcc.S
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      startup file. Should use with
+ *          		       GCC for T-HEAD Embedded Processors
+ */
+
+#include <csi_config.h>
+
+
+.section .vectors, "aw", @progbits
+    .align  6
+    .globl  __Vectors
+    .type   __Vectors, @object
+__Vectors:
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   PendSV_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_IRQHandler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+
+    /* External interrupts */
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+    .long   Default_IRQHandler
+
+    .text
+    .align  2
+_start:
+    .text
+    .align  2
+    .globl  Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+.option push
+.option norelax
+    la      gp, __global_pointer$
+.option pop
+    la      a0, Default_Handler
+    ori     a0, a0, 3
+    csrw    mtvec, a0
+    la      a0, __Vectors
+    csrw    mtvt, a0
+    la      sp, __StackTop
+    csrw    mscratch, sp
+
+    /* Load data section */
+    la      a0, __erodata
+    la      a1, __data_start__
+    la      a2, __data_end__
+    bgeu    a1, a2, 2f
+1:
+    lw      t0, (a0)
+    sw      t0, (a1)
+    addi    a0, a0, 4
+    addi    a1, a1, 4
+    bltu    a1, a2, 1b
+2:
+
+    /* Clear bss section */
+    la      a0, __bss_start__
+    la      a1, __bss_end__
+    bgeu    a0, a1, 2f
+1:
+    sw      zero, (a0)
+    addi    a0, a0, 4
+    bltu    a0, a1, 1b
+2:
+
+#ifndef __NO_SYSTEM_INIT
+    jal     SystemInit
+#endif
+
+    jal     entry
+
+    .size   Reset_Handler, . - Reset_Handler
+
+__exit:
+    j      __exit
+
+.section .bss
+
+    .align  3
+    .global g_base_irqstack
+    .global g_top_irqstack
+g_base_irqstack:
+    .space CONFIG_ARCH_INTERRUPTSTACK
+g_top_irqstack:
diff --git a/bsp/thead-smart/drivers/sys_freq.c b/bsp/thead-smart/drivers/sys_freq.c
new file mode 100644
index 0000000000..7a3341d506
--- /dev/null
+++ b/bsp/thead-smart/drivers/sys_freq.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      setting system frequency
+ */
+
+
+#include <stdint.h>
+#include <soc.h>
+#include <sys_freq.h>
+
+extern int g_system_clock;
+
+int32_t drv_get_cpu_freq(int32_t idx)
+{
+    return g_system_clock;
+}
+
+int32_t drv_get_usi_freq(int32_t idx)
+{
+    return g_system_clock;
+}
+
+int32_t drv_get_usart_freq(int32_t idx)
+{
+    return g_system_clock;
+}
+
+int32_t drv_get_pwm_freq(int32_t idx)
+{
+    return g_system_clock;
+}
+
+int32_t drv_get_i2s_freq(int32_t idx)
+{
+    return g_system_clock;
+}
+
+int32_t drv_get_sys_freq(void)
+{
+    return g_system_clock;
+}
+
+int32_t drv_get_rtc_freq(int32_t idx)
+{
+    return g_system_clock;
+}
+
+int32_t drv_get_apb_freq(void)
+{
+    return g_system_clock;
+}
+
+int32_t drv_get_timer_freq(int32_t idx)
+{
+    return g_system_clock;
+}
diff --git a/bsp/thead-smart/drivers/sys_freq.h b/bsp/thead-smart/drivers/sys_freq.h
new file mode 100644
index 0000000000..5bf2086833
--- /dev/null
+++ b/bsp/thead-smart/drivers/sys_freq.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for setting system frequency
+ */
+
+#ifndef _SYS_FREQ_H_
+#define _SYS_FREQ_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32_t drv_get_i2s_freq(int32_t idx);
+int32_t drv_get_pwm_freq(int32_t idx);
+int32_t drv_get_usart_freq(int32_t idx);
+int32_t drv_get_usi_freq(int32_t idx);
+int32_t drv_get_sys_freq(void);
+int32_t drv_get_apb_freq(void);
+int32_t drv_get_rtc_freq(int32_t idx);
+int32_t drv_get_timer_freq(int32_t idx);
+
+int32_t drv_get_cpu_freq(int32_t idx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_FREQ_H_ */
+
diff --git a/bsp/thead-smart/drivers/system.c b/bsp/thead-smart/drivers/system.c
new file mode 100644
index 0000000000..31a05f1afa
--- /dev/null
+++ b/bsp/thead-smart/drivers/system.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Device System Source File
+ */
+
+#include <csi_config.h>
+#include <soc.h>
+#include <csi_core.h>
+#include <drv_irq.h>
+
+#ifndef CONFIG_SYSTICK_HZ
+#define CONFIG_SYSTICK_HZ 100
+#endif
+
+int g_system_clock = IHS_VALUE;
+extern int32_t g_top_irqstack;
+extern void irq_vectors_init(void);
+extern void mm_heap_initialize(void);
+
+int SystemCoreClock = IHS_VALUE;  /* System Core Clock Frequency      */
+extern int __Vectors;
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = IHS_VALUE;
+}
+
+
+static void _system_init_for_kernel(void)
+{
+    irq_vectors_init();
+
+    csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, CORET_IRQn);    //10ms
+    drv_irq_enable(CORET_IRQn);
+}
+
+/**
+  * @brief  initialize the system
+  *         Initialize the psr and vbr.
+  * @param  None
+  * @return None
+  */
+void SystemInit(void)
+{
+    int i;
+    /* enable mstatus FS */
+#if ((CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
+    uint32_t mstatus = __get_MSTATUS();
+    mstatus |= (1 << 13);
+    __set_MSTATUS(mstatus);
+#endif
+
+    /* enable mxstatus THEADISAEE */
+    uint32_t mxstatus = __get_MXSTATUS();
+    mxstatus |= (1 << 22);
+    /* enable mxstatus MM */
+#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
+    mxstatus |= (1 << 15);
+#endif
+    __set_MXSTATUS(mxstatus);
+
+
+    /* get interrupt level from info */
+    CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
+
+    for (i = 0; i < 64; i++) 
+    {
+        CLIC->CLICINT[i].IP = 0;
+        CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
+    }
+
+    /* tspend use positive interrupt */
+    CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
+
+    csi_dcache_enable();
+    csi_icache_enable();
+    drv_irq_enable(Machine_Software_IRQn);
+
+    _system_init_for_kernel();
+}
diff --git a/bsp/thead-smart/drivers/trap_c.c b/bsp/thead-smart/drivers/trap_c.c
new file mode 100644
index 0000000000..b236714100
--- /dev/null
+++ b/bsp/thead-smart/drivers/trap_c.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      source file for the trap process
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <csi_config.h>
+#include <csi_core.h>
+
+void (*trap_c_callback)(void);
+
+void trap_c(uint32_t *regs)
+{
+    int i;
+    uint32_t vec = 0;
+
+    vec = __get_MCAUSE() & 0x3FF;
+
+    printf("CPU Exception: NO.%d", vec);
+    printf("\n");
+
+    for (i = 0; i < 31; i++) 
+    {
+        printf("x%d: %08x\t", i + 1, regs[i]);
+
+        if ((i % 4) == 3) 
+        {
+            printf("\n");
+        }
+    }
+
+    printf("\n");
+    printf("mepc   : %08x\n", regs[31]);
+    printf("mstatus: %08x\n", regs[32]);
+
+    if (trap_c_callback) 
+    {
+        trap_c_callback();
+    }
+
+    while (1);
+}
+
diff --git a/bsp/thead-smart/drivers/vectors.S b/bsp/thead-smart/drivers/vectors.S
new file mode 100644
index 0000000000..3bfa3c70b7
--- /dev/null
+++ b/bsp/thead-smart/drivers/vectors.S
@@ -0,0 +1,349 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      define default vector handlers.
+ */
+
+
+#include <csi_config.h>
+
+/* Enable interrupts when returning from the handler */
+#define MSTATUS_PRV1 0x1880
+
+.section .bss
+    .align  2
+    .globl  g_trapstackalloc
+    .global g_trapstackbase
+    .global g_top_trapstack
+g_trapstackalloc:
+g_trapstackbase:
+    .space 768
+g_top_trapstack:
+
+    .align 2
+    .globl g_trap_sp
+    .type  g_trap_sp, object
+g_trap_sp:
+    .long 0
+    .size g_trap_sp, .-g_trap_sp
+
+irq_nested_level:
+.long 0
+#ifdef ARCH_RISCV_FPU
+irq_mstatus_fs_flag:
+.long 0
+#endif
+
+.text
+
+    .align  2
+    .global Default_IRQHandler
+    .weak   Default_IRQHandler
+    .type   Default_IRQHandler, %function
+Default_IRQHandler:
+    ipush
+
+#ifdef ARCH_RISCV_FPU
+    csrr    t1, mstatus
+    srli    t1, t1, 13
+    andi    t1, t1, 0x3
+    la      t3, irq_mstatus_fs_flag
+    sw      t1, (t3)
+    li      t0, 0x3
+    bne     t1, t0,  .F_RegNotSave1
+
+    addi    sp, sp, -(20 * FREGBYTES)
+
+    FSTORE  ft0,   0 * FREGBYTES(sp)
+    FSTORE  ft1,   1 * FREGBYTES(sp)
+    FSTORE  ft2,   2 * FREGBYTES(sp)
+    FSTORE  ft3,   3 * FREGBYTES(sp)
+    FSTORE  ft4,   4 * FREGBYTES(sp)
+    FSTORE  ft5,   5 * FREGBYTES(sp)
+    FSTORE  ft6,   6 * FREGBYTES(sp)
+    FSTORE  ft7,   7 * FREGBYTES(sp)
+    FSTORE  fa0,   8 * FREGBYTES(sp)
+    FSTORE  fa1,   9 * FREGBYTES(sp)
+    FSTORE  fa2,  10 * FREGBYTES(sp)
+    FSTORE  fa3,  11 * FREGBYTES(sp)
+    FSTORE  fa4,  12 * FREGBYTES(sp)
+    FSTORE  fa5,  13 * FREGBYTES(sp)
+    FSTORE  fa6,  14 * FREGBYTES(sp)
+    FSTORE  fa7,  15 * FREGBYTES(sp)
+    FSTORE  ft8,  16 * FREGBYTES(sp)
+    FSTORE  ft9,  17 * FREGBYTES(sp)
+    FSTORE  ft10, 18 * FREGBYTES(sp)
+    FSTORE  ft11, 19 * FREGBYTES(sp)
+.F_RegNotSave1:
+#endif
+
+    csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    slli    t1, t1, 2
+    la      t0, g_irqvector
+    add     t0, t0, t1
+    lw      t2, (t0)
+    jalr    t2
+
+    li      t0, MSTATUS_PRV1
+    csrs    mstatus, t0
+
+#ifdef ARCH_RISCV_FPU    
+    la      t0, irq_mstatus_fs_flag
+    lw      t1, (t0)
+    li      t0, 0x3
+    bne     t1, t0,  .F_RegNotLoad
+
+    FLOAD   ft0,  0 * FREGBYTES(sp)
+    FLOAD   ft1,  1 * FREGBYTES(sp)
+    FLOAD   ft2,  2 * FREGBYTES(sp)
+    FLOAD   ft3,  3 * FREGBYTES(sp)
+    FLOAD   ft4,  4 * FREGBYTES(sp)
+    FLOAD   ft5,  5 * FREGBYTES(sp)
+    FLOAD   ft6,  6 * FREGBYTES(sp)
+    FLOAD   ft7,  7 * FREGBYTES(sp)
+    FLOAD   fa0,  8 * FREGBYTES(sp)
+    FLOAD   fa1,  9 * FREGBYTES(sp)
+    FLOAD   fa2, 10 * FREGBYTES(sp)
+    FLOAD   fa3, 11 * FREGBYTES(sp)
+    FLOAD   fa4, 12 * FREGBYTES(sp)
+    FLOAD   fa5, 13 * FREGBYTES(sp)
+    FLOAD   fa6, 14 * FREGBYTES(sp)
+    FLOAD   fa7, 15 * FREGBYTES(sp)
+    FLOAD   ft8, 16 * FREGBYTES(sp)
+    FLOAD   ft9, 17 * FREGBYTES(sp)
+    FLOAD   ft10,18 * FREGBYTES(sp)
+    FLOAD   ft11,19 * FREGBYTES(sp)
+
+    addi    sp, sp, (20 * FREGBYTES)
+.F_RegNotLoad:
+#endif
+    ipop
+
+
+/******************************************************************************
+ * Functions:
+ *     void trap(void);
+ * default exception handler
+ ******************************************************************************/
+    .align  2
+    .global trap
+    .type   trap, %function
+trap:
+    /* Check for interrupt */
+    addi    sp, sp, -4
+    sw      t0, 0x0(sp)
+    csrr    t0, mcause
+    blt     t0, x0, .Lirq
+    addi    sp, sp, 4
+    la      t0, g_trap_sp
+
+    addi    t0, t0, -132
+
+    sw      x1,    0(t0)
+    sw      x2,    4(t0)
+    sw      x3,    8(t0)
+    sw      x4,   12(t0)
+    sw      x6,   20(t0)
+    sw      x7,   24(t0)
+    sw      x8,   28(t0)
+    sw      x9,   32(t0)
+    sw      x10,  36(t0)
+    sw      x11,  40(t0)
+    sw      x12,  44(t0)
+    sw      x13,  48(t0)
+    sw      x14,  52(t0)
+    sw      x15,  56(t0)
+    sw      x16,  60(t0)
+    sw      x17,  64(t0)
+    sw      x18,  68(t0)
+    sw      x19,  72(t0)
+    sw      x20,  76(t0)
+    sw      x21,  80(t0)
+    sw      x22,  84(t0)
+    sw      x23,  88(t0)
+    sw      x24,  92(t0)
+    sw      x25,  96(t0)
+    sw      x26, 100(t0)
+    sw      x27, 104(t0)
+    sw      x28, 108(t0)
+    sw      x29, 112(t0)
+    sw      x30, 116(t0)
+    sw      x31, 120(t0)
+
+    csrr    a0, mepc
+    sw      a0, 124(t0)
+    csrr    a0, mstatus
+    sw      a0, 128(t0)
+
+    mv      a0, t0
+    lw      t0, -4(sp)
+    mv      sp, a0
+    sw      t0, 16(sp)
+
+    jal     trap_c
+
+
+.Lirq:
+    lw      t0, 0x0(sp)
+    addi    sp, sp, 4
+    j       Default_IRQHandler
+
+    .align  6
+    .weak   Default_Handler
+    .global Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    /* Check for nmi */
+    addi    sp, sp, -8
+    sw      t0, 0x0(sp)
+    sw      t1, 0x4(sp)
+    csrr    t0, mcause
+    andi    t0, t0, 0x3FF
+    li      t1, 24
+    beq     t0, t1, .NMI_Handler
+    lw      t0, 0x0(sp)
+    lw      t1, 0x4(sp)
+    addi    sp, sp, 8
+    j       trap
+
+.NMI_Handler:
+    lw      t0, 0x0(sp)
+    lw      t1, 0x4(sp)
+    addi    sp, sp, 8
+    
+    addi    sp, sp, -64
+
+    sw      ra,  0(sp)
+    sw      t0,  4(sp)
+    sw      t1,  8(sp)
+    sw      t2, 12(sp)
+    sw      a0, 16(sp)
+    sw      a1, 20(sp)
+    sw      a2, 24(sp)
+    sw      a3, 28(sp)
+    sw      a4, 32(sp)
+    sw      a5, 36(sp)
+    sw      a6, 40(sp)
+    sw      a7, 44(sp)
+    sw      t3, 48(sp)
+    sw      t4, 52(sp)
+    sw      t5, 56(sp)
+    sw      t6, 60(sp)
+
+#ifdef ARCH_RISCV_FPU
+    addi    sp,    sp, -(20*FREGBYTES)
+    FSTORE  ft0,   0 * FREGBYTES(sp)
+    FSTORE  ft1,   1 * FREGBYTES(sp)
+    FSTORE  ft2,   2 * FREGBYTES(sp)
+    FSTORE  ft3,   3 * FREGBYTES(sp)
+    FSTORE  ft4,   4 * FREGBYTES(sp)
+    FSTORE  ft5,   5 * FREGBYTES(sp)
+    FSTORE  ft6,   6 * FREGBYTES(sp)
+    FSTORE  ft7,   7 * FREGBYTES(sp)
+    FSTORE  fa0,   8 * FREGBYTES(sp)
+    FSTORE  fa1,   9 * FREGBYTES(sp)
+    FSTORE  fa2,  10 * FREGBYTES(sp)
+    FSTORE  fa3,  11 * FREGBYTES(sp)
+    FSTORE  fa4,  12 * FREGBYTES(sp)
+    FSTORE  fa5,  13 * FREGBYTES(sp)
+    FSTORE  fa6,  14 * FREGBYTES(sp)
+    FSTORE  fa7,  15 * FREGBYTES(sp)
+    FSTORE  ft8,  16 * FREGBYTES(sp)
+    FSTORE  ft9,  17 * FREGBYTES(sp)
+    FSTORE  ft10, 18 * FREGBYTES(sp)
+    FSTORE  ft11, 19 * FREGBYTES(sp)
+#endif
+
+    la      t0, g_nmivector
+    lw      t0, (t0)
+    jalr    t0
+
+#ifdef ARCH_RISCV_FPU
+    FLOAD   ft0,   0 * FREGBYTES(sp)
+    FLOAD   ft1,   1 * FREGBYTES(sp)
+    FLOAD   ft2,   2 * FREGBYTES(sp)
+    FLOAD   ft3,   3 * FREGBYTES(sp)
+    FLOAD   ft4,   4 * FREGBYTES(sp)
+    FLOAD   ft5,   5 * FREGBYTES(sp)
+    FLOAD   ft6,   6 * FREGBYTES(sp)
+    FLOAD   ft7,   7 * FREGBYTES(sp)
+    FLOAD   fa0,   8 * FREGBYTES(sp)
+    FLOAD   fa1,   9 * FREGBYTES(sp)
+    FLOAD   fa2,  10 * FREGBYTES(sp)
+    FLOAD   fa3,  11 * FREGBYTES(sp)
+    FLOAD   fa4,  12 * FREGBYTES(sp)
+    FLOAD   fa5,  13 * FREGBYTES(sp)
+    FLOAD   fa6,  14 * FREGBYTES(sp)
+    FLOAD   fa7,  15 * FREGBYTES(sp)
+    FLOAD   ft8,  16 * FREGBYTES(sp)
+    FLOAD   ft9,  17 * FREGBYTES(sp)
+    FLOAD   ft10, 18 * FREGBYTES(sp)
+    FLOAD   ft11, 19 * FREGBYTES(sp)
+
+    addi    sp, sp, (20 * FREGBYTES)
+#endif
+
+    lw      ra,  0(sp)
+    lw      t0,  4(sp)
+    lw      t1,  8(sp)
+    lw      t2, 12(sp)
+    lw      a0, 16(sp)
+    lw      a1, 20(sp)
+    lw      a2, 24(sp)
+    lw      a3, 28(sp)
+    lw      a4, 32(sp)
+    lw      a5, 36(sp)
+    lw      a6, 40(sp)
+    lw      a7, 44(sp)
+    lw      t3, 48(sp)
+    lw      t4, 52(sp)
+    lw      t5, 56(sp)
+    lw      t6, 60(sp)
+
+    addi    sp, sp, 64
+    mret
+
+
+    .size   Default_Handler, . - Default_Handler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro  def_irq_handler handler_name
+    .weak   \handler_name
+    .globl  \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler PendSV_Handler
+    def_irq_handler SysTick_Handler
+    def_irq_handler STIM0_IRQHandler
+    def_irq_handler STIM1_IRQHandler
+    def_irq_handler STIM2_IRQHandler
+    def_irq_handler STIM3_IRQHandler
+    def_irq_handler TIM0_IRQHandler
+    def_irq_handler TIM1_IRQHandler
+    def_irq_handler TIM2_IRQHandler
+    def_irq_handler TIM3_IRQHandler
+    def_irq_handler USART_IRQHandler
+    def_irq_handler GPIO0_IRQHandler
+    def_irq_handler GPIO1_IRQHandler
+    def_irq_handler GPIO2_IRQHandler
+    def_irq_handler GPIO3_IRQHandler
+    def_irq_handler GPIO4_IRQHandler
+    def_irq_handler GPIO5_IRQHandler
+    def_irq_handler GPIO6_IRQHandler
+    def_irq_handler GPIO7_IRQHandler
+    def_irq_handler PAD_IRQHandler
+    def_irq_handler TIM6_IRQHandler
+    def_irq_handler TIM7_IRQHandler
+    def_irq_handler TIM8_IRQHandler
+    def_irq_handler TIM9_IRQHandler
+    def_irq_handler TIM10_IRQHandler
+    def_irq_handler TIM11_IRQHandler
+
diff --git a/bsp/thead-smart/gcc_csky.ld b/bsp/thead-smart/gcc_csky.ld
new file mode 100644
index 0000000000..a0303d19eb
--- /dev/null
+++ b/bsp/thead-smart/gcc_csky.ld
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     gcc_csky.h
+ * @brief    csky linker file for PHOBOS
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+MEMORY
+{
+    I-SRAM : ORIGIN = 0x0        , LENGTH = 0x40000   /* I-SRAM  256KB */
+    D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0xc0000   /* D-SRAM  768KB */
+    O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000   /* off-chip SRAM 8MB */
+    SRAM   : ORIGIN = 0x60000000 , LENGTH = 0x20000   /* on-chip SRAM 128KB */
+}
+
+PROVIDE (__StackTop = 0x200c0000 - 0x8);
+PROVIDE (Stack_Size = 0x1000);
+
+REGION_ALIAS("REGION_TEXT",    I-SRAM);
+REGION_ALIAS("REGION_RODATA",  I-SRAM);
+REGION_ALIAS("REGION_CUSTOM1", D-SRAM);
+REGION_ALIAS("REGION_CUSTOM2", D-SRAM);
+REGION_ALIAS("REGION_DATA",    D-SRAM);
+REGION_ALIAS("REGION_BSS",     D-SRAM);
+
+ENTRY(Reset_Handler)
+SECTIONS
+{
+  .text : AT(ADDR(.text)){
+  . = ALIGN(0x4) ;
+  __stext = . ;
+  KEEP(*startup.o(*.text*))
+  *(.text)
+  *(.text*)
+  *(.text.*)
+  *(.gnu.warning)
+  *(.stub)
+  *(.gnu.linkonce.t*)
+  *(.glue_7t)
+  *(.glue_7)
+  *(.jcr)
+  *(.init)
+  *(.fini)
+  . = ALIGN (4) ;
+  PROVIDE(__ctbp = .);
+  *(.call_table_data)
+  *(.call_table_text)
+
+	/* section information for finsh shell */
+	. = ALIGN(4);
+	__fsymtab_start = .;
+	KEEP(*(FSymTab))
+	__fsymtab_end = .;
+	. = ALIGN(4);
+	__vsymtab_start = .;
+	KEEP(*(VSymTab))
+	__vsymtab_end = .;
+	. = ALIGN(4);
+
+	/* section information for initial. */
+	. = ALIGN(4);
+	__rt_init_start = .;
+	KEEP(*(SORT(.rti_fn*)))
+	__rt_init_end = .;
+	. = ALIGN(4);
+  . = ALIGN(0x10) ;
+  __etext = . ;
+ } > REGION_TEXT
+ .eh_frame_hdr : {
+  *(.eh_frame_hdr)
+ } > REGION_TEXT
+ .eh_frame : ONLY_IF_RO {
+  KEEP (*(.eh_frame))
+ } > REGION_TEXT
+ .gcc_except_table : ONLY_IF_RO {
+  *(.gcc_except_table .gcc_except_table.*)
+ } > REGION_TEXT
+ .rodata :{
+  . = ALIGN(0x4) ;
+  __srodata = .;
+  *(.rdata)
+  *(.rdata*)
+  *(.rdata1)
+  *(.rdata.*)
+  *(.rodata)
+  *(.rodata1)
+  *(.rodata*)
+  *(.rodata.*)
+  *(.rodata.str1.4)
+  . = ALIGN(0x4) ;
+  __ctor_start__ = .;
+  KEEP (*(SORT(.ctors.*)))
+  KEEP (*(.ctors))
+  __ctor_end__ = .;
+  KEEP (*(SORT(.dtors.*)))
+  KEEP (*(.dtors))
+  __dtor_end__ = .;
+  . = ALIGN(0x4) ;
+  __erodata = .;
+  __rodata_end__ = .;
+ } > REGION_RODATA
+ .data : {
+  . = ALIGN(0x4) ;
+  __sdata = . ;
+  __data_start__ = . ;
+  data_start = . ;
+  KEEP(*startup.o(*.vectors*))
+  *(.got.plt)
+  *(.got)
+  *(.gnu.linkonce.r*)
+  *(.data)
+  *(.data*)
+  *(.data1)
+  *(.data.*)
+  *(.gnu.linkonce.d*)
+  *(.data1)
+  *(.gcc_except_table)
+  *(.gcc_except_table*)
+  __start_init_call = .;
+  *(.initcall.init)
+  __stop_init_call = .;
+  __start_cmd = .;
+  *(.bootloaddata.cmd)
+  . = ALIGN(4) ;
+  __stop_cmd = .;
+  __global_pointer$ = .;
+  *(.sdata)
+  *(.sdata.*)
+  *(.gnu.linkonce.s.*)
+  *(__libc_atexit)
+  *(__libc_subinit)
+  *(__libc_subfreeres)
+  *(.note.ABI-tag)
+  __edata = .;
+  __data_end__ = .;
+  . = ALIGN(0x4) ;
+
+ } > REGION_DATA AT > REGION_RODATA
+ .eh_frame : ONLY_IF_RW {
+  KEEP (*(.eh_frame))
+ } > REGION_DATA AT > REGION_RODATA
+ .gcc_except_table : ONLY_IF_RW {
+  *(.gcc_except_table .gcc_except_table.*)
+  __edata = .;
+  __data_end__ = .;
+ } > REGION_DATA AT > REGION_RODATA
+
+
+ .bss : {
+  . = ALIGN(0x4) ;
+  __sbss = ALIGN(0x4) ;
+  __bss_start__ = . ;
+  *(.dynsbss)
+  *(.sbss)
+  *(.sbss.*)
+  *(.scommon)
+  *(.dynbss)
+  *(.bss)
+  *(.bss.*)
+  *(COMMON)
+  . = ALIGN(0x4) ;
+  __ebss = . ;
+  __end = . ;
+  end = . ;
+  __bss_end__ = .;
+ } > REGION_BSS
+  /* End of uninitalized data segement */
+  PROVIDE(end = .);
+}
diff --git a/bsp/thead-smart/rtconfig.h b/bsp/thead-smart/rtconfig.h
new file mode 100644
index 0000000000..12e38cb703
--- /dev/null
+++ b/bsp/thead-smart/rtconfig.h
@@ -0,0 +1,158 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40003
+
+/* RT-Thread CPU arch and features */
+
+
+/* risc-v arch */
+
+#define ARCH_RISCV
+#define ARCH_RISCV_32
+#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 1
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 2048
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define SOC_THEAD_SMART
+#define RT_USING_UART1
+
+#endif
diff --git a/bsp/thead-smart/rtconfig.py b/bsp/thead-smart/rtconfig.py
new file mode 100644
index 0000000000..be45bc8e84
--- /dev/null
+++ b/bsp/thead-smart/rtconfig.py
@@ -0,0 +1,68 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+CPU         ='e906'
+CPUNAME     ='e906f'
+VENDOR      ='t-head'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/home/xinge/tools/riscv64-elf-x86_64-20200616-1.9.6/bin'
+else:
+    print 'Please make sure your toolchains is GNU GCC!'
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+# BUILD = 'debug'
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'g++'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+    STRIP   = PREFIX + 'strip'
+
+    if CPUNAME == 'e906fd':
+        DEVICE = ' -march=rv32imafdcxthead -mabi=ilp32d'
+    if CPUNAME == 'e906f':
+        DEVICE = ' -march=rv32imafcxthead -mabi=ilp32f'
+    if CPUNAME == 'e906':
+        DEVICE = ' -march=rv32imacxthead -mabi=ilp32'
+
+    CFLAGS  = DEVICE + ' -c -g -ffunction-sections -fdata-sections -Wall -mcmodel=medlow'
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--no-whole-archive -T gcc_csky.ld -lm -lc -lgcc -Wl,-gc-sections -Wl,-zmax-page-size=1024'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2 -g2'
+
+    CXXFLAGS = CFLAGS
+
+#    M_CFLAGS = DEVICE + ' -EL -G0 -O2 -mno-abicalls -fno-common -fno-exceptions -fno-omit-frame-pointer -mlong-calls -fno-pic '
+ #   M_CXXFLAGS = M_CFLAGS
+ #   M_LFLAGS = DEVICE + ' -EL -r -Wl,--gc-sections,-z,max-page-size=0x4' +\
+  #                                  ' -nostartfiles -static-libgcc'
+ #   M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 024cc5ba44..5055b533e6 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -10,10 +10,17 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-if rtconfig.CPU != "nuclei":
-    group = group + SConscript(os.path.join('common', 'SConscript'))
+if   rtconfig.VENDOR == "t-head" :
+    group = group
+elif rtconfig.CPU == "nuclei" :
+    group = group
+else :
+    group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+if  rtconfig.VENDOR == "t-head" :
+    group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
+else :
+    group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
 
 Return('group')
diff --git a/libcpu/risc-v/t-head/e906/SConscript b/libcpu/risc-v/t-head/e906/SConscript
new file mode 100644
index 0000000000..2f698f530a
--- /dev/null
+++ b/libcpu/risc-v/t-head/e906/SConscript
@@ -0,0 +1,12 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/t-head/e906/context_gcc.S b/libcpu/risc-v/t-head/e906/context_gcc.S
new file mode 100644
index 0000000000..2f5223ae63
--- /dev/null
+++ b/libcpu/risc-v/t-head/e906/context_gcc.S
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/08/20     zx.chen      The T-HEAD RISC-V CPU E906 porting implementation
+ */
+
+#include "cpuport.h"
+
+#ifdef RT_USING_SMP
+#define rt_hw_interrupt_disable rt_hw_local_irq_disable
+#define rt_hw_interrupt_enable  rt_hw_local_irq_enable
+#endif
+
+/*
+ * Functions: vPortYield
+ */
+.global vPortYield
+.type   vPortYield, %function
+vPortYield:
+    li      t0, 0xE080100C
+    lb      t1, (t0)
+    li      t2, 0x01
+    or      t1, t1, t2
+    sb      t1, (t0)
+
+    ret
+
+
+
+/*
+ * #ifdef RT_USING_SMP
+ * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
+ * #else
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * #endif
+ * a0 --> to
+ * a1 --> to_thread
+ */
+    .globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    /* save a0 to to_thread */
+    la      t0, rt_interrupt_to_thread
+    STORE   a0, (t0)
+    
+    /* save 0 to from_thread */
+    la      t0, rt_interrupt_from_thread
+    li      t1, 0
+    STORE   t1, (t0)
+    
+    /* set rt_thread_switch_interrupt_flag=1 */
+    la      t0, rt_thread_switch_interrupt_flag
+    li      t1, 1
+    STORE   t1, (t0)
+
+    /* enable mexstatus SPUSHEN and SPSWAPEN */
+#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
+    uint32_t mexstatus;
+    mexstatus  = __get_MEXSTATUS();
+    mexstatus |= (0x2 << 16);
+    __set_MEXSTATUS(mexstatus);
+#endif
+
+    csrw    mscratch, sp
+    /* set software interrupt */
+    li      t0, 0xE080100C
+    lb      t1, (t0)
+    li      t2, 0x01
+    or      t1, t1, t2
+    sb      t1, (t0)
+
+    /* enable global interrup */
+    csrsi   mstatus, 8
+
+    ret
+
+/*
+ * #ifdef RT_USING_SMP
+ * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
+ * #else
+ * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
+ * #endif
+ *
+ * a0 --> from
+ * a1 --> to
+ * a2 --> to_thread
+ */
+    .globl rt_hw_context_switch
+rt_hw_context_switch:
+    .globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    /* check rt_thread_switch_interrupt_flag */
+    la      t0, rt_thread_switch_interrupt_flag
+    lw      t1, (t0)
+    li      t2, 1
+    beq     t1, t2, .reswitch
+    /*  set rt_thread_switch_interrupt_flag=1 */
+    STORE   t2, (t0)
+  
+    /* update from_thread */
+    la      t0, rt_interrupt_from_thread
+    STORE   a0, (t0)
+
+.reswitch:
+    /* update to_thread */
+    la      t0, rt_interrupt_to_thread
+    STORE   a1, (t0)
+    /* set software interrupt */
+    li      t0, 0xE080100C
+    lb      t1, (t0)
+    li      t2, 0x01
+    or      t1, t1, t2
+    sb      t1, (t0)
+
+    ret
+
+/*
+ *    PendSV_Handler
+ */
+.global PendSV_Handler
+.type   PendSV_Handler, %function
+PendSV_Handler:
+
+    /* check rt_thread_switch_interrupt_flag */
+    sw      t0, (-4)(sp)
+    sw      t1, (-8)(sp)
+    la      t0, rt_thread_switch_interrupt_flag
+    lw      t1, (t0)
+    beqz    t1, .pendsv_exit
+
+    /* clear rt_thread_switch_interrupt_flag */
+    li      t1, 0x0
+    sw      t1, (t0)
+
+    /* check rt_interrupt_from_thread */
+    la      t0, rt_interrupt_from_thread
+    lw      t1, (t0)
+    beqz    t1, .switch_to_thead
+    
+    /* save from thread context */
+    lw      t0, (-4)(sp)
+    lw      t1, (-8)(sp)
+
+#ifdef ARCH_RISCV_FPU
+    addi    sp, sp, -32 * FREGBYTES
+
+    FSTORE  f0, 0 * FREGBYTES(sp)
+    FSTORE  f1, 1 * FREGBYTES(sp)
+    FSTORE  f2, 2 * FREGBYTES(sp)
+    FSTORE  f3, 3 * FREGBYTES(sp)
+    FSTORE  f4, 4 * FREGBYTES(sp)
+    FSTORE  f5, 5 * FREGBYTES(sp)
+    FSTORE  f6, 6 * FREGBYTES(sp)
+    FSTORE  f7, 7 * FREGBYTES(sp)
+    FSTORE  f8, 8 * FREGBYTES(sp)
+    FSTORE  f9, 9 * FREGBYTES(sp)
+    FSTORE  f10, 10 * FREGBYTES(sp)
+    FSTORE  f11, 11 * FREGBYTES(sp)
+    FSTORE  f12, 12 * FREGBYTES(sp)
+    FSTORE  f13, 13 * FREGBYTES(sp)
+    FSTORE  f14, 14 * FREGBYTES(sp)
+    FSTORE  f15, 15 * FREGBYTES(sp)
+    FSTORE  f16, 16 * FREGBYTES(sp)
+    FSTORE  f17, 17 * FREGBYTES(sp)
+    FSTORE  f18, 18 * FREGBYTES(sp)
+    FSTORE  f19, 19 * FREGBYTES(sp)
+    FSTORE  f20, 20 * FREGBYTES(sp)
+    FSTORE  f21, 21 * FREGBYTES(sp)
+    FSTORE  f22, 22 * FREGBYTES(sp)
+    FSTORE  f23, 23 * FREGBYTES(sp)
+    FSTORE  f24, 24 * FREGBYTES(sp)
+    FSTORE  f25, 25 * FREGBYTES(sp)
+    FSTORE  f26, 26 * FREGBYTES(sp)
+    FSTORE  f27, 27 * FREGBYTES(sp)
+    FSTORE  f28, 28 * FREGBYTES(sp)
+    FSTORE  f29, 29 * FREGBYTES(sp)
+    FSTORE  f30, 30 * FREGBYTES(sp)
+    FSTORE  f31, 31 * FREGBYTES(sp)
+#endif
+
+    addi    sp, sp, -32 * REGBYTES
+
+    STORE   x1, 1 * REGBYTES(sp)
+    csrr    x1, mepc
+    STORE   x1, 0 * REGBYTES(sp)
+    csrr    x1, mstatus
+    andi    x1, x1, 8
+    beqz    x1, .save_mpie
+    li      x1, 0x80
+.save_mpie:
+    STORE   x1, 2 * REGBYTES(sp)
+    /* x3 don't need save */
+    STORE   x4, 4 * REGBYTES(sp)
+    STORE   x5, 5 * REGBYTES(sp)
+    STORE   x6, 6 * REGBYTES(sp)
+    STORE   x7, 7 * REGBYTES(sp)
+    STORE   x8, 8 * REGBYTES(sp)
+    STORE   x9, 9 * REGBYTES(sp)
+    STORE   x10, 10 * REGBYTES(sp)
+    STORE   x11, 11 * REGBYTES(sp)
+    STORE   x12, 12 * REGBYTES(sp)
+    STORE   x13, 13 * REGBYTES(sp)
+    STORE   x14, 14 * REGBYTES(sp)
+    STORE   x15, 15 * REGBYTES(sp)
+    STORE   x16, 16 * REGBYTES(sp)
+    STORE   x17, 17 * REGBYTES(sp)
+    STORE   x18, 18 * REGBYTES(sp)
+    STORE   x19, 19 * REGBYTES(sp)
+    STORE   x20, 20 * REGBYTES(sp)
+    STORE   x21, 21 * REGBYTES(sp)
+    STORE   x22, 22 * REGBYTES(sp)
+    STORE   x23, 23 * REGBYTES(sp)
+    STORE   x24, 24 * REGBYTES(sp)
+    STORE   x25, 25 * REGBYTES(sp)
+    STORE   x26, 26 * REGBYTES(sp)
+    STORE   x27, 27 * REGBYTES(sp)
+    STORE   x28, 28 * REGBYTES(sp)
+    STORE   x29, 29 * REGBYTES(sp)
+    STORE   x30, 30 * REGBYTES(sp)
+    STORE   x31, 31 * REGBYTES(sp)
+
+    /* store from_thread sp */
+    la      t0, rt_interrupt_from_thread
+    lw      t0, (t0)
+    sw      sp, (t0)
+
+.switch_to_thead:
+    /* restore to thread context
+     * sp(0) -> epc;
+     * sp(1) -> ra;
+     * sp(i) -> x(i+2)
+     */
+    la      t0, rt_interrupt_to_thread
+    lw      t0, (t0)
+    LOAD    sp, (t0)
+
+    /* restore ra to mepc */
+    LOAD    a1, 0 * REGBYTES(sp)
+    csrw    mepc, a1
+    LOAD    x1, 1 * REGBYTES(sp)
+
+    /* force to machin mode(MPP=11) */
+    li      a1, 0x1880
+    csrs    mstatus, a1
+    LOAD    a1, 2 * REGBYTES(sp)
+    csrs    mstatus, a1
+    /* x3 don't need restore */
+    LOAD    x4, 4 * REGBYTES(sp)
+    LOAD    x5, 5 * REGBYTES(sp)
+    LOAD    x6, 6 * REGBYTES(sp)
+    LOAD    x7, 7 * REGBYTES(sp)
+    LOAD    x8, 8 * REGBYTES(sp)
+    LOAD    x9, 9 * REGBYTES(sp)
+    LOAD    x10, 10 * REGBYTES(sp)
+    LOAD    x11, 11 * REGBYTES(sp)
+    LOAD    x12, 12 * REGBYTES(sp)
+    LOAD    x13, 13 * REGBYTES(sp)
+    LOAD    x14, 14 * REGBYTES(sp)
+    LOAD    x15, 15 * REGBYTES(sp)
+    LOAD    x16, 16 * REGBYTES(sp)
+    LOAD    x17, 17 * REGBYTES(sp)
+    LOAD    x18, 18 * REGBYTES(sp)
+    LOAD    x19, 19 * REGBYTES(sp)
+    LOAD    x20, 20 * REGBYTES(sp)
+    LOAD    x21, 21 * REGBYTES(sp)
+    LOAD    x22, 22 * REGBYTES(sp)
+    LOAD    x23, 23 * REGBYTES(sp)
+    LOAD    x24, 24 * REGBYTES(sp)
+    LOAD    x25, 25 * REGBYTES(sp)
+    LOAD    x26, 26 * REGBYTES(sp)
+    LOAD    x27, 27 * REGBYTES(sp)
+    LOAD    x28, 28 * REGBYTES(sp)
+    LOAD    x29, 29 * REGBYTES(sp)
+    LOAD    x30, 30 * REGBYTES(sp)
+    LOAD    x31, 31 * REGBYTES(sp)
+
+    addi    sp, sp, 32 * REGBYTES
+
+#ifdef ARCH_RISCV_FPU
+    FLOAD   f0, 0 * FREGBYTES(sp)
+    FLOAD   f1, 1 * FREGBYTES(sp)
+    FLOAD   f2, 2 * FREGBYTES(sp)
+    FLOAD   f3, 3 * FREGBYTES(sp)
+    FLOAD   f4, 4 * FREGBYTES(sp)
+    FLOAD   f5, 5 * FREGBYTES(sp)
+    FLOAD   f6, 6 * FREGBYTES(sp)
+    FLOAD   f7, 7 * FREGBYTES(sp)
+    FLOAD   f8, 8 * FREGBYTES(sp)
+    FLOAD   f9, 9 * FREGBYTES(sp)
+    FLOAD   f10, 10 * FREGBYTES(sp)
+    FLOAD   f11, 11 * FREGBYTES(sp)
+    FLOAD   f12, 12 * FREGBYTES(sp)
+    FLOAD   f13, 13 * FREGBYTES(sp)
+    FLOAD   f14, 14 * FREGBYTES(sp)
+    FLOAD   f15, 15 * FREGBYTES(sp)
+    FLOAD   f16, 16 * FREGBYTES(sp)
+    FLOAD   f17, 17 * FREGBYTES(sp)
+    FLOAD   f18, 18 * FREGBYTES(sp)
+    FLOAD   f19, 19 * FREGBYTES(sp)
+    FLOAD   f20, 20 * FREGBYTES(sp)
+    FLOAD   f21, 21 * FREGBYTES(sp)
+    FLOAD   f22, 22 * FREGBYTES(sp)
+    FLOAD   f23, 23 * FREGBYTES(sp)
+    FLOAD   f24, 24 * FREGBYTES(sp)
+    FLOAD   f25, 25 * FREGBYTES(sp)
+    FLOAD   f26, 26 * FREGBYTES(sp)
+    FLOAD   f27, 27 * FREGBYTES(sp)
+    FLOAD   f28, 28 * FREGBYTES(sp)
+    FLOAD   f29, 29 * FREGBYTES(sp)
+    FLOAD   f30, 30 * FREGBYTES(sp)
+    FLOAD   f31, 31 * FREGBYTES(sp)
+
+    addi    sp, sp, 32 * FREGBYTES
+#endif
+
+.pendsv_exit:
+    mret
+ 
+
+
diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e906/cpuport.c
new file mode 100644
index 0000000000..5597aa237a
--- /dev/null
+++ b/libcpu/risc-v/t-head/e906/cpuport.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/08/20     zx.chen      The T-HEAD RISC-V CPU E906 porting code.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "cpuport.h"
+
+#ifndef RT_USING_SMP
+volatile rt_ubase_t  rt_interrupt_from_thread = 0;
+volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
+volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
+#endif
+
+struct rt_hw_stack_frame
+{
+    rt_ubase_t epc;        /* epc - epc    - program counter                     */
+    rt_ubase_t ra;         /* x1  - ra     - return address for jumps            */
+    rt_ubase_t mstatus;    /*              - machine status register             */
+    rt_ubase_t gp;         /* x3  - gp     - global pointer                      */
+    rt_ubase_t tp;         /* x4  - tp     - thread pointer                      */
+    rt_ubase_t t0;         /* x5  - t0     - temporary register 0                */
+    rt_ubase_t t1;         /* x6  - t1     - temporary register 1                */
+    rt_ubase_t t2;         /* x7  - t2     - temporary register 2                */
+    rt_ubase_t s0_fp;      /* x8  - s0/fp  - saved register 0 or frame pointer   */
+    rt_ubase_t s1;         /* x9  - s1     - saved register 1                    */
+    rt_ubase_t a0;         /* x10 - a0     - return value or function argument 0 */
+    rt_ubase_t a1;         /* x11 - a1     - return value or function argument 1 */
+    rt_ubase_t a2;         /* x12 - a2     - function argument 2                 */
+    rt_ubase_t a3;         /* x13 - a3     - function argument 3                 */
+    rt_ubase_t a4;         /* x14 - a4     - function argument 4                 */
+    rt_ubase_t a5;         /* x15 - a5     - function argument 5                 */
+    rt_ubase_t a6;         /* x16 - a6     - function argument 6                 */
+    rt_ubase_t a7;         /* x17 - s7     - function argument 7                 */
+    rt_ubase_t s2;         /* x18 - s2     - saved register 2                    */
+    rt_ubase_t s3;         /* x19 - s3     - saved register 3                    */
+    rt_ubase_t s4;         /* x20 - s4     - saved register 4                    */
+    rt_ubase_t s5;         /* x21 - s5     - saved register 5                    */
+    rt_ubase_t s6;         /* x22 - s6     - saved register 6                    */
+    rt_ubase_t s7;         /* x23 - s7     - saved register 7                    */
+    rt_ubase_t s8;         /* x24 - s8     - saved register 8                    */
+    rt_ubase_t s9;         /* x25 - s9     - saved register 9                    */
+    rt_ubase_t s10;        /* x26 - s10    - saved register 10                   */
+    rt_ubase_t s11;        /* x27 - s11    - saved register 11                   */
+    rt_ubase_t t3;         /* x28 - t3     - temporary register 3                */
+    rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
+    rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
+    rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
+#ifdef ARCH_RISCV_FPU
+    rv_floatreg_t f0;      /* f0  */
+    rv_floatreg_t f1;      /* f1  */
+    rv_floatreg_t f2;      /* f2  */
+    rv_floatreg_t f3;      /* f3  */
+    rv_floatreg_t f4;      /* f4  */
+    rv_floatreg_t f5;      /* f5  */
+    rv_floatreg_t f6;      /* f6  */
+    rv_floatreg_t f7;      /* f7  */
+    rv_floatreg_t f8;      /* f8  */
+    rv_floatreg_t f9;      /* f9  */
+    rv_floatreg_t f10;     /* f10 */
+    rv_floatreg_t f11;     /* f11 */
+    rv_floatreg_t f12;     /* f12 */
+    rv_floatreg_t f13;     /* f13 */
+    rv_floatreg_t f14;     /* f14 */
+    rv_floatreg_t f15;     /* f15 */
+    rv_floatreg_t f16;     /* f16 */
+    rv_floatreg_t f17;     /* f17 */
+    rv_floatreg_t f18;     /* f18 */
+    rv_floatreg_t f19;     /* f19 */
+    rv_floatreg_t f20;     /* f20 */
+    rv_floatreg_t f21;     /* f21 */
+    rv_floatreg_t f22;     /* f22 */
+    rv_floatreg_t f23;     /* f23 */
+    rv_floatreg_t f24;     /* f24 */
+    rv_floatreg_t f25;     /* f25 */
+    rv_floatreg_t f26;     /* f26 */
+    rv_floatreg_t f27;     /* f27 */
+    rv_floatreg_t f28;     /* f28 */
+    rv_floatreg_t f29;     /* f29 */
+    rv_floatreg_t f30;     /* f30 */
+    rv_floatreg_t f31;     /* f31 */
+#endif
+};
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct rt_hw_stack_frame *frame;
+    rt_uint8_t         *stk;
+    int                i;
+
+    stk  = stack_addr + sizeof(rt_ubase_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
+    stk -= sizeof(struct rt_hw_stack_frame);
+
+    frame = (struct rt_hw_stack_frame *)stk;
+
+    for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
+    {
+        ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
+    }
+
+    frame->ra      = (rt_ubase_t)texit;
+    frame->a0      = (rt_ubase_t)parameter;
+    frame->epc     = (rt_ubase_t)tentry;
+
+    /* force to machine mode(MPP=11) and set MPIE to 1 */
+    frame->mstatus = 0x00007880;
+
+    return stk;
+}
+
+
+/**
+ * This function will disable global interrupt 
+ *
+ * @param none
+ *
+ * @return zero
+ */
+
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    __asm volatile("csrc mstatus, 8");
+    return 0;
+}
+
+/**
+ * This function will ennable global interrupt 
+ *
+ * @param level not used
+ *
+ * @return none
+ */
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    __asm volatile("csrs mstatus, 8");
+}
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
diff --git a/libcpu/risc-v/t-head/e906/cpuport.h b/libcpu/risc-v/t-head/e906/cpuport.h
new file mode 100644
index 0000000000..90efc07653
--- /dev/null
+++ b/libcpu/risc-v/t-head/e906/cpuport.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      The first version
+ */
+
+#ifndef CPUPORT_H__
+#define CPUPORT_H__
+
+#include <rtconfig.h>
+
+/* bytes of register width  */
+#ifdef ARCH_RISCV_64
+#define DFSTORE                 fsd
+#define DFLOAD                  fld
+#define SFSTORE                 fsw
+#define SFLOAD                  flw
+#define STORE                   sd
+#define LOAD                    ld
+#define REGBYTES                8
+#define SFREGBYTES              4
+#define DFREGBYTES              8
+#else
+#define DFSTORE                 fsd
+#define DFLOAD                  fld
+#define SFSTORE                 fsw
+#define SFLOAD                  flw
+#define STORE                   sw
+#define LOAD                    lw
+
+#define REGBYTES                4
+#define SFREGBYTES              4
+#define DFREGBYTES              8
+#endif
+
+#ifdef ARCH_RISCV_FPU
+#ifdef ARCH_RISCV_FPU_D
+#define FSTORE                  fsd
+#define FLOAD                   fld
+#define FREGBYTES               8
+#define rv_floatreg_t           rt_int64_t  	       
+#endif
+#ifdef ARCH_RISCV_FPU_S
+#define FSTORE                  fsw
+#define FLOAD                   flw
+#define FREGBYTES               4
+#define rv_floatreg_t           rt_int32_t  	       
+#endif
+#endif
+
+#endif
-- 
cgit v1.3.1


From a97b0a0d3972ad332a6afb2b7472163ff7f57ac0 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Fri, 11 Sep 2020 11:44:49 +0800
Subject: code format

---
 bsp/ls2kdev/drivers/board.h              |    2 +-
 bsp/ls2kdev/drivers/clk.c                |    1 -
 bsp/ls2kdev/drivers/drv_gpio.c           |    4 +-
 bsp/ls2kdev/drivers/drv_gpio.h           |    3 +-
 bsp/ls2kdev/drivers/drv_uart.h           |  149 ++-
 bsp/ls2kdev/drivers/interrupt.h          |   26 +-
 bsp/ls2kdev/drivers/ls2k1000.h           |   16 +-
 bsp/ls2kdev/drivers/net/mii.c            |    2 +-
 bsp/ls2kdev/drivers/net/mii.h            |   34 +-
 bsp/ls2kdev/drivers/net/synopGMAC.c      |    4 -
 bsp/ls2kdev/drivers/net/synopGMAC_Dev.c  |  172 ++-
 bsp/ls2kdev/drivers/net/synopGMAC_Dev.h  | 1694 +++++++++++++++---------------
 bsp/ls2kdev/drivers/net/synopGMAC_plat.h |    2 +-
 libcpu/mips/gs264/cache.c                |    2 +-
 libcpu/mips/gs264/cpuinit_gcc.S          |    8 +-
 libcpu/mips/gs264/mips_mmu.c             |   32 +-
 libcpu/mips/gs264/mips_mmu.h             |  155 ++-
 libcpu/mips/gs264/mipscfg.c              |   14 +-
 libcpu/mips/gs264/mmu.c                  |    8 +-
 libcpu/mips/gs264/mmu.h                  |   24 +-
 20 files changed, 1140 insertions(+), 1212 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/ls2kdev/drivers/board.h b/bsp/ls2kdev/drivers/board.h
index 927a789af0..ca57ebf3f2 100644
--- a/bsp/ls2kdev/drivers/board.h
+++ b/bsp/ls2kdev/drivers/board.h
@@ -15,7 +15,7 @@
 
 extern unsigned char __bss_end;
 
-#define CPU_HZ	(1000 * 1000 * 1000) //QEMU 200*1000*1000
+#define CPU_HZ              (1000 * 1000 * 1000) //QEMU 200*1000*1000
 #define RT_HW_HEAP_BEGIN    (void*)&__bss_end
 #define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
 
diff --git a/bsp/ls2kdev/drivers/clk.c b/bsp/ls2kdev/drivers/clk.c
index aba08bd87a..7a043e9ff4 100644
--- a/bsp/ls2kdev/drivers/clk.c
+++ b/bsp/ls2kdev/drivers/clk.c
@@ -14,7 +14,6 @@
 #include <rtthread.h>
 #include "ls2k1000.h"
 
-
 struct loongson_pll {
     rt_uint64_t PLL_SYS_0;
     rt_uint64_t PLL_SYS_1;
diff --git a/bsp/ls2kdev/drivers/drv_gpio.c b/bsp/ls2kdev/drivers/drv_gpio.c
index 155807461f..abf9fdc8af 100644
--- a/bsp/ls2kdev/drivers/drv_gpio.c
+++ b/bsp/ls2kdev/drivers/drv_gpio.c
@@ -5,8 +5,8 @@
  * Change Logs:
  * Date           Author       Notes
  * 2015-01-20     Bernard      the first version
- * 2017-10-20      ZYH          add mode open drain and input pull down
- * 2020-06-01     Du Huanpeng   GPIO driver based on <components/drivers/include/drivers/pin.h>
+ * 2017-10-20      ZYH         add mode open drain and input pull down
+ * 2020-06-01     Du Huanpeng  GPIO driver based on <components/drivers/include/drivers/pin.h>
  */
 #include <rtthread.h>
 #include <drivers/pin.h>
diff --git a/bsp/ls2kdev/drivers/drv_gpio.h b/bsp/ls2kdev/drivers/drv_gpio.h
index 51a75c306e..4bf1ba80f5 100644
--- a/bsp/ls2kdev/drivers/drv_gpio.h
+++ b/bsp/ls2kdev/drivers/drv_gpio.h
@@ -6,7 +6,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2017-11-24     勤为本          first version
+ * 2017-11-24     勤为本        first version
  * 2018-05-11     zhuangwei    add gpio interrupt ops
  */
 
@@ -36,6 +36,5 @@ struct loongson_gpio {
 
 int loongson_pin_init(void);
 
-
 #endif
 
diff --git a/bsp/ls2kdev/drivers/drv_uart.h b/bsp/ls2kdev/drivers/drv_uart.h
index 4d17b99b35..ca3e856d06 100644
--- a/bsp/ls2kdev/drivers/drv_uart.h
+++ b/bsp/ls2kdev/drivers/drv_uart.h
@@ -15,100 +15,99 @@
 #include <rthw.h>
 
 /* UART registers */
-#define UART_DAT(base)		HWREG8(base + 0x00)
-#define UART_IER(base)		HWREG8(base + 0x01)
-#define UART_IIR(base)		HWREG8(base + 0x02)
-#define UART_FCR(base)		HWREG8(base + 0x02)
-#define UART_LCR(base)		HWREG8(base + 0x03)
-#define UART_MCR(base)		HWREG8(base + 0x04)
-#define UART_LSR(base)		HWREG8(base + 0x05)
-#define UART_MSR(base)		HWREG8(base + 0x06)
+#define UART_DAT(base)        HWREG8(base + 0x00)
+#define UART_IER(base)        HWREG8(base + 0x01)
+#define UART_IIR(base)        HWREG8(base + 0x02)
+#define UART_FCR(base)        HWREG8(base + 0x02)
+#define UART_LCR(base)        HWREG8(base + 0x03)
+#define UART_MCR(base)        HWREG8(base + 0x04)
+#define UART_LSR(base)        HWREG8(base + 0x05)
+#define UART_MSR(base)        HWREG8(base + 0x06)
 
-#define UART_LSB(base)		HWREG8(base + 0x00)
-#define UART_MSB(base)		HWREG8(base + 0x01)
+#define UART_LSB(base)        HWREG8(base + 0x00)
+#define UART_MSB(base)        HWREG8(base + 0x01)
 
 /* interrupt enable register */
-#define	IER_IRxE	0x1
-#define	IER_ITxE	0x2
-#define	IER_ILE	    0x4
-#define	IER_IME	    0x8
+#define    IER_IRxE         0x1
+#define    IER_ITxE         0x2
+#define    IER_ILE          0x4
+#define    IER_IME          0x8
 
 /* interrupt identification register */
-#define	IIR_IMASK	0xf	/* mask */
-#define	IIR_RXTOUT	0xc	/* receive timeout */
-#define	IIR_RLS		0x6	/* receive line status */
-#define	IIR_RXRDY	0x4	/* receive ready */
-#define	IIR_TXRDY	0x2	/* transmit ready */
-#define	IIR_NOPEND	0x1	/* nothing */
-#define	IIR_MLSC	0x0	/* modem status */
-#define	IIR_FIFO_MASK	0xc0	/* set if FIFOs are enabled */
+#define    IIR_IMASK        0xf    /* mask */
+#define    IIR_RXTOUT       0xc    /* receive timeout */
+#define    IIR_RLS          0x6    /* receive line status */
+#define    IIR_RXRDY        0x4    /* receive ready */
+#define    IIR_TXRDY        0x2    /* transmit ready */
+#define    IIR_NOPEND       0x1    /* nothing */
+#define    IIR_MLSC         0x0    /* modem status */
+#define    IIR_FIFO_MASK    0xc0    /* set if FIFOs are enabled */
 
 /* fifo control register */
-#define	FIFO_ENABLE	    0x01	/* enable fifo */
-#define	FIFO_RCV_RST	0x02	/* reset receive fifo */
-#define	FIFO_XMT_RST	0x04	/* reset transmit fifo */
-#define	FIFO_DMA_MODE	0x08	/* enable dma mode */
-#define	FIFO_TRIGGER_1	0x00	/* trigger at 1 char */
-#define	FIFO_TRIGGER_4	0x40	/* trigger at 4 chars */
-#define	FIFO_TRIGGER_8	0x80	/* trigger at 8 chars */
-#define	FIFO_TRIGGER_14	0xc0	/* trigger at 14 chars */
+#define    FIFO_ENABLE      0x01    /* enable fifo */
+#define    FIFO_RCV_RST     0x02    /* reset receive fifo */
+#define    FIFO_XMT_RST     0x04    /* reset transmit fifo */
+#define    FIFO_DMA_MODE    0x08    /* enable dma mode */
+#define    FIFO_TRIGGER_1   0x00    /* trigger at 1 char */
+#define    FIFO_TRIGGER_4   0x40    /* trigger at 4 chars */
+#define    FIFO_TRIGGER_8   0x80    /* trigger at 8 chars */
+#define    FIFO_TRIGGER_14  0xc0    /* trigger at 14 chars */
 
-// 线路控制寄存器
 /* character format control register */
-#define	CFCR_DLAB	0x80	/* divisor latch */
-#define	CFCR_SBREAK	0x40	/* send break */
-#define	CFCR_PZERO	0x30	/* zero parity */
-#define	CFCR_PONE	0x20	/* one parity */
-#define	CFCR_PEVEN	0x10	/* even parity */
-#define	CFCR_PODD	0x00	/* odd parity */
-#define	CFCR_PENAB	0x08	/* parity enable */
-#define	CFCR_STOPB	0x04	/* 2 stop bits */
-#define	CFCR_8BITS	0x03	/* 8 data bits */
-#define	CFCR_7BITS	0x02	/* 7 data bits */
-#define	CFCR_6BITS	0x01	/* 6 data bits */
-#define	CFCR_5BITS	0x00	/* 5 data bits */
+#define    CFCR_DLAB        0x80    /* divisor latch */
+#define    CFCR_SBREAK      0x40    /* send break */
+#define    CFCR_PZERO       0x30    /* zero parity */
+#define    CFCR_PONE        0x20    /* one parity */
+#define    CFCR_PEVEN       0x10    /* even parity */
+#define    CFCR_PODD        0x00    /* odd parity */
+#define    CFCR_PENAB       0x08    /* parity enable */
+#define    CFCR_STOPB       0x04    /* 2 stop bits */
+#define    CFCR_8BITS       0x03    /* 8 data bits */
+#define    CFCR_7BITS       0x02    /* 7 data bits */
+#define    CFCR_6BITS       0x01    /* 6 data bits */
+#define    CFCR_5BITS       0x00    /* 5 data bits */
 
 /* modem control register */
-#define	MCR_LOOPBACK	0x10	/* loopback */
-#define	MCR_IENABLE	0x08	/* output 2 = int enable */
-#define	MCR_DRS		0x04	/* output 1 = xxx */
-#define	MCR_RTS		0x02	/* enable RTS */
-#define	MCR_DTR		0x01	/* enable DTR */
+#define    MCR_LOOPBACK     0x10    /* loopback */
+#define    MCR_IENABLE      0x08    /* output 2 = int enable */
+#define    MCR_DRS          0x04    /* output 1 = xxx */
+#define    MCR_RTS          0x02    /* enable RTS */
+#define    MCR_DTR          0x01    /* enable DTR */
 
 /* line status register */
-#define	LSR_RCV_FIFO	0x80	/* error in receive fifo */
-#define	LSR_TSRE	0x40	/* transmitter empty */
-#define	LSR_TXRDY	0x20	/* transmitter ready */
-#define	LSR_BI		0x10	/* break detected */
-#define	LSR_FE		0x08	/* framing error */
-#define	LSR_PE		0x04	/* parity error */
-#define	LSR_OE		0x02	/* overrun error */
-#define	LSR_RXRDY	0x01	/* receiver ready */
-#define	LSR_RCV_MASK	0x1f
+#define    LSR_RCV_FIFO     0x80    /* error in receive fifo */
+#define    LSR_TSRE         0x40    /* transmitter empty */
+#define    LSR_TXRDY        0x20    /* transmitter ready */
+#define    LSR_BI           0x10    /* break detected */
+#define    LSR_FE           0x08    /* framing error */
+#define    LSR_PE           0x04    /* parity error */
+#define    LSR_OE           0x02    /* overrun error */
+#define    LSR_RXRDY        0x01    /* receiver ready */
+#define    LSR_RCV_MASK     0x1f
 
 
 /* UART interrupt enable register value */
-#define UARTIER_IME		(1 << 3)
-#define UARTIER_ILE		(1 << 2)
-#define UARTIER_ITXE	(1 << 1)
-#define UARTIER_IRXE	(1 << 0)
+#define UARTIER_IME       (1 << 3)
+#define UARTIER_ILE       (1 << 2)
+#define UARTIER_ITXE      (1 << 1)
+#define UARTIER_IRXE      (1 << 0)
 
 /* UART line control register value */
-#define UARTLCR_DLAB	(1 << 7)
-#define UARTLCR_BCB		(1 << 6)
-#define UARTLCR_SPB		(1 << 5)
-#define UARTLCR_EPS		(1 << 4)
-#define UARTLCR_PE		(1 << 3)
-#define UARTLCR_SB		(1 << 2)
+#define UARTLCR_DLAB      (1 << 7)
+#define UARTLCR_BCB       (1 << 6)
+#define UARTLCR_SPB       (1 << 5)
+#define UARTLCR_EPS       (1 << 4)
+#define UARTLCR_PE        (1 << 3)
+#define UARTLCR_SB        (1 << 2)
 
 /* UART line status register value */
-#define UARTLSR_ERROR	(1 << 7)
-#define UARTLSR_TE		(1 << 6)
-#define UARTLSR_TFE		(1 << 5)
-#define UARTLSR_BI		(1 << 4)
-#define UARTLSR_FE		(1 << 3)
-#define UARTLSR_PE		(1 << 2)
-#define UARTLSR_OE		(1 << 1)
-#define UARTLSR_DR		(1 << 0)
+#define UARTLSR_ERROR     (1 << 7)
+#define UARTLSR_TE        (1 << 6)
+#define UARTLSR_TFE       (1 << 5)
+#define UARTLSR_BI        (1 << 4)
+#define UARTLSR_FE        (1 << 3)
+#define UARTLSR_PE        (1 << 2)
+#define UARTLSR_OE        (1 << 1)
+#define UARTLSR_DR        (1 << 0)
 
 #endif
diff --git a/bsp/ls2kdev/drivers/interrupt.h b/bsp/ls2kdev/drivers/interrupt.h
index 18707f7321..df55437cf9 100644
--- a/bsp/ls2kdev/drivers/interrupt.h
+++ b/bsp/ls2kdev/drivers/interrupt.h
@@ -64,22 +64,22 @@
 #define LS2K_GPIO2_INT_IRQ          (62)
 #define LS2K_GPIO3_INT_IRQ          (63)
 
-#define MAX_INTR 64
-#define LIOINTC0_IRQBASE 0
-#define LIOINTC1_IRQBASE 32
+#define MAX_INTR                    (64)
+#define LIOINTC0_IRQBASE            (0)
+#define LIOINTC1_IRQBASE            (32)
 
-#define LIOINTC_SHIFT_INTx 4
-#define LIOINTC_COREx_INTy(x, y)   ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
+#define LIOINTC_SHIFT_INTx          (4)
+#define LIOINTC_COREx_INTy(x, y)    ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
 
-#define LIOINTC_INTC_CHIP_START	    0x20
+#define LIOINTC_INTC_CHIP_START      0x20
 
-#define LIOINTC_REG_INTC_STATUS	    (LIOINTC_INTC_CHIP_START + 0x00)
-#define LIOINTC_REG_INTC_EN_STATUS	(LIOINTC_INTC_CHIP_START + 0x04)
-#define LIOINTC_REG_INTC_ENABLE	    (LIOINTC_INTC_CHIP_START + 0x08)
-#define LIOINTC_REG_INTC_DISABLE	(LIOINTC_INTC_CHIP_START + 0x0c)
-#define LIOINTC_REG_INTC_POL	    (LIOINTC_INTC_CHIP_START + 0x10)
-#define LIOINTC_REG_INTC_EDGE	    (LIOINTC_INTC_CHIP_START + 0x14)
+#define LIOINTC_REG_INTC_STATUS      (LIOINTC_INTC_CHIP_START + 0x00)
+#define LIOINTC_REG_INTC_EN_STATUS   (LIOINTC_INTC_CHIP_START + 0x04)
+#define LIOINTC_REG_INTC_ENABLE      (LIOINTC_INTC_CHIP_START + 0x08)
+#define LIOINTC_REG_INTC_DISABLE     (LIOINTC_INTC_CHIP_START + 0x0c)
+#define LIOINTC_REG_INTC_POL         (LIOINTC_INTC_CHIP_START + 0x10)
+#define LIOINTC_REG_INTC_EDGE        (LIOINTC_INTC_CHIP_START + 0x14)
 
 void liointc_set_irq_mode(int irq, int mode);
 
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h
index 24396e7d3b..38e83875fb 100644
--- a/bsp/ls2kdev/drivers/ls2k1000.h
+++ b/bsp/ls2kdev/drivers/ls2k1000.h
@@ -6,11 +6,11 @@
 
 #define APB_BASE         CKSEG1ADDR(0xbfe00000)
 
-#define UART0_BASE_ADDR 0xbfe00000
-#define UART0_OFF   0x0
-#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
+#define UART0_BASE_ADDR  (0xbfe00000)
+#define UART0_OFF        (0x0)
+#define UART0_BASE       CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
 
-#define UARTx_BASE(x)   ((APB_BASE | (0x0 << 12) | (x << 8)))
+#define UARTx_BASE(x)    ((APB_BASE | (0x0 << 12) | (x << 8)))
 
 #define LIOINTC0_BASE    CKSEG1ADDR(0x1fe11400)
 #define CORE0_INTISR0    CKSEG1ADDR(0x1fe11040)
@@ -18,11 +18,11 @@
 #define LIOINTC1_BASE    CKSEG1ADDR(0x1fe11440)
 #define CORE0_INTISR1    CKSEG1ADDR(0x1fe11048)
 
-#define GPIO_BASE    0xFFFFFFFFBFE10500
-#define PLL_SYS_BASE 0xFFFFFFFFBFE10480
-#define RTC_BASE 0xFFFFFFFFBFE07820
+#define GPIO_BASE        (0xFFFFFFFFBFE10500)
+#define PLL_SYS_BASE     (0xFFFFFFFFBFE10480)
+#define RTC_BASE         (0xFFFFFFFFBFE07820)
 
-#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420
+#define GEN_CONFIG0_REG  (0xFFFFFFFFBfe10420)
 
 void rt_hw_timer_handler(void);
 void rt_hw_uart_init(void);
diff --git a/bsp/ls2kdev/drivers/net/mii.c b/bsp/ls2kdev/drivers/net/mii.c
index b06475df12..a0b3a7adce 100644
--- a/bsp/ls2kdev/drivers/net/mii.c
+++ b/bsp/ls2kdev/drivers/net/mii.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/ls2kdev/drivers/net/mii.h b/bsp/ls2kdev/drivers/net/mii.h
index 994d560c50..bc6d6c7a0c 100644
--- a/bsp/ls2kdev/drivers/net/mii.h
+++ b/bsp/ls2kdev/drivers/net/mii.h
@@ -37,7 +37,7 @@
 
 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
-#define BMCR_SPEED1000        0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
@@ -135,8 +135,8 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
-#define ESTATUS_1000_TFULL    0x2000    /* Can do 1000BT Full */
-#define ESTATUS_1000_THALF    0x1000    /* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL      0x2000    /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF      0x1000    /* Can do 1000BT Half */
 
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
@@ -170,11 +170,11 @@
 
 
 /* Which connector port. */
-#define PORT_TP         0x00
-#define PORT_AUI        0x01
-#define PORT_MII        0x02 
-#define PORT_FIBRE      0x03
-#define PORT_BNC        0x04
+#define PORT_TP             0x00
+#define PORT_AUI            0x01
+#define PORT_MII            0x02 
+#define PORT_FIBRE          0x03
+#define PORT_BNC            0x04
 
 /* Which transceiver to use. */
 #define XCVR_INTERNAL       0x00
@@ -183,18 +183,18 @@
 #define XCVR_DUMMY2         0x03 
 #define XCVR_DUMMY3         0x04
 
-#define AUTONEG_DISABLE        0x00
-#define AUTONEG_ENABLE         0x01
+#define AUTONEG_DISABLE     0x00
+#define AUTONEG_ENABLE      0x01
 
 
-#define SPEED_10          10
-#define SPEED_100         100
-#define SPEED_1000        1000
-#define SPEED_2500        2500
-#define SPEED_10000       10000
+#define SPEED_10            10
+#define SPEED_100           100
+#define SPEED_1000          1000
+#define SPEED_2500          2500
+#define SPEED_10000         10000
 
-#define DUPLEX_HALF        0x00
-#define DUPLEX_FULL        0x01
+#define DUPLEX_HALF         0x00
+#define DUPLEX_FULL         0x01
 
 struct ethtool_cmd {
     u32    cmd;
diff --git a/bsp/ls2kdev/drivers/net/synopGMAC.c b/bsp/ls2kdev/drivers/net/synopGMAC.c
index 38a6345236..f58f67ff5f 100644
--- a/bsp/ls2kdev/drivers/net/synopGMAC.c
+++ b/bsp/ls2kdev/drivers/net/synopGMAC.c
@@ -260,7 +260,6 @@ s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter)
     return gmacdev->Speed | (gmacdev->DuplexMode << 4);
 }
 
-
 static int Mac_change_check(u8 *macaddr0, u8 *macaddr1)
 {
     int i;
@@ -894,7 +893,6 @@ int rt_hw_eth_init(void)
     struct synopGMACNetworkAdapter *synopGMACadapter;
     static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS;
     int index;
-    //rt_kprintf("rt_hw_eth_init 1\n");
     rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
     rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
@@ -958,8 +956,6 @@ int rt_hw_eth_init(void)
     
     eth_device_init(&(eth_dev.parent), "e0");
     eth_device_linkchange(&eth_dev.parent, RT_TRUE);   //linkup the e0 for lwip to check
-    //rt_kprintf("rt_hw_eth_init 2\n");
     return 0;
 }
-
 INIT_COMPONENT_EXPORT(rt_hw_eth_init);
diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c
index ade261563d..cdd4585670 100644
--- a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c
+++ b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c
@@ -860,7 +860,6 @@ void synopGMAC_promisc_disable(synopGMACdevice *gmacdev)
     return;
 }
 
-
 /**
   * Enables unicast hash filtering.
   * When enabled GMAC performs the destination address filtering of unicast frames according to the hash table.
@@ -1032,7 +1031,6 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev)
     synopGMACWriteReg(gmacdev -> MacBase,GmacFlowControl,mac_flow_control_reg);
 
     return;
-
 }
 
 /**
@@ -1352,10 +1350,9 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
     desc -> length = 0; 
     #else
     desc -> length = last_ring_desc ? TxDescEndOfRing : 0;
-  desc -> status = 0;
+    desc -> status = 0;
     #endif
 //sw    
-
     desc -> buffer1 = 0;
     desc -> buffer2 = 0;
     desc -> data1 = 0;
@@ -1365,8 +1362,6 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
     return;
 }
 
-
-
 /**
   * Initialize the rx descriptors for chain mode of operation.
   *     - Status field is initialized to 0.
@@ -1409,7 +1404,6 @@ void synopGMAC_tx_desc_init_chain(DmaDesc * desc)
     return;
 }
 
-
 s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev)
 {
     s32 i;
@@ -1817,7 +1811,6 @@ void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1
     }
     
     return;
-
 }
 
 #ifdef ENH_DESC_8W
@@ -1912,10 +1905,7 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
     u32  txover      = gmacdev->TxBusy;
     DmaDesc * txdesc = gmacdev->TxBusyDesc;
     int i;
-    
 //sw: dbg
-    
-
     //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R);
     //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W);
 #if SYNOP_TX_DEBUG
@@ -1954,12 +1944,12 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
     gmacdev->TxBusy     = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1;
 
     if(synopGMAC_is_tx_desc_chained(txdesc))
-  {
-           gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2;
+    {
+        gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2;
         synopGMAC_tx_desc_init_chain(txdesc);
     }
     else
-  {
+    {
         gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1);
         synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc));
     }
@@ -2008,37 +1998,40 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
 
     (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now
     
-    if(synopGMAC_is_tx_desc_chained(txdesc)){
-        txdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
-        #ifdef ENH_DESC
-        txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
-        #else
-        txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor
-        #endif
-
-         txdesc->buffer1 = Buffer1;
-        txdesc->data1 = Data1;
-
-    if(offload_needed){
-        /*
-         Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
-         before calling any of the functions given below.         
-         */
-        synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc);
-        synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc);
+    if(synopGMAC_is_tx_desc_chained(txdesc))
+    {
+      txdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
+      #ifdef ENH_DESC
+      txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
+      #else
+      txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor
+      #endif
+
+      txdesc->buffer1 = Buffer1;
+      txdesc->data1 = Data1;
+
+      if(offload_needed)
+      {
+          /*
+           Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
+           before calling any of the functions given below.         
+           */
+          synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc);
+          synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc);
 //        synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc);
+      }
+      #ifdef ENH_DESC
+      txdesc->status |= DescOwnByDma;//ENH_DESC
+      #else
+      txdesc->status = DescOwnByDma;
+      #endif
+
+      gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1;
+          gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2;
     }
-        #ifdef ENH_DESC
-        txdesc->status |= DescOwnByDma;//ENH_DESC
-        #else
-        txdesc->status = DescOwnByDma;
-        #endif
-
-        gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1;
-           gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2;
-    }
-    else{
-//        printf("synopGMAC_set_tx_qptr:in ring mode\n");
+    else
+    {
+//      printf("synopGMAC_set_tx_qptr:in ring mode\n");
         txdesc->length |= (((Length1 <<DescSize1Shift) & DescSize1Mask) | ((Length2 <<DescSize2Shift) & DescSize2Mask));
         #ifdef ENH_DESC
         txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
@@ -2046,13 +2039,14 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
         txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor
         #endif
 
-         txdesc->buffer1 = Buffer1;
+        txdesc->buffer1 = Buffer1;
         txdesc->data1 = Data1;
 
-         txdesc->buffer2 = Buffer2;
+        txdesc->buffer2 = Buffer2;
         txdesc->data2 = Data2;
 
-        if(offload_needed){
+        if(offload_needed)
+        {
         /*
          Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
          before calling any of the functions given below.         
@@ -2638,8 +2632,7 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev)
         else{
             synopGMAC_take_desc_ownership(desc + i);
         }
-    }
-    
+    }  
 }
 
 /**
@@ -2668,15 +2661,8 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev)
     data = synopGMACReadReg(gmacdev->DmaBase, DmaControl);
       data &= (~DmaRxStart); 
     synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data);
-}
-
-
-    
+}   
 /*******************PMT APIs***************************************/
-
-
-
-
 /**
   * Enables the assertion of PMT interrupt.
   * This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame
@@ -2835,9 +2821,9 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte
 
 }
 #endif
+
 /*******************PMT APIs***************************************/
 /*******************MMC APIs***************************************/
-
 /**
   * Freezes the MMC counters.
   * This function call freezes the MMC counters. None of the MMC counters are updated
@@ -3081,7 +3067,6 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev)
   * \return returns TRUE or FALSE
   */
 #ifdef ENH_DESC_8W
-
 /**
   * This function indicates whether extended status is available in the RDES0.
   * Any function which accesses the fields of extended status register must ensure a check on this has been made
@@ -3132,8 +3117,6 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status)
 }
 #endif
 
-
-
 /**
   * Decodes the Rx Descriptor status to various checksum error conditions.
   * @param[in] pointer to synopGMACdevice.
@@ -3172,7 +3155,6 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta
     return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError);
 }
 
-
 /**
   * Checks if any payload checksum error in the frame just transmitted.
   * This serves as indication that error occureed in the payload checksum insertion.
@@ -3199,7 +3181,6 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des
     #else
     desc->length = (desc->length & (~DescTxCisMask));
     #endif
-
 }
 /**
   * The check summ offload engine is enabled to do only IPV4 header checksum.
@@ -3215,7 +3196,6 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de
     #else
     desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);
     #endif
-
 }
 
 /**
@@ -3233,7 +3213,6 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de
     #else
     desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);
     #endif
-
 }
 /**
   * The check summ offload engine is enabled to do complete checksum computation.
@@ -3254,14 +3233,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc
 
 }
 /*******************Ip checksum offloading APIs***************************************/
-
-
-
-
-
 /*******************IEEE 1588 Timestamping API***************************************/
-
-
 /*
  * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled.
  * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced
@@ -3295,7 +3267,6 @@ void synopGMAC_TS_disable(synopGMACdevice *gmacdev)
     return;
 }
 
-
 /**
   * Enable the interrupt to get timestamping interrupt. 
   * This enables the host to get the interrupt when (1) system time is greater or equal to the 
@@ -3344,7 +3315,6 @@ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev)
     return;
 }
 
-
 /**
   * Selet the type of clock mode for PTP. 
   * Please note to use one of the follwoing as the clk_type argument.
@@ -3493,7 +3463,6 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev)
     return;
 }
 
-
 /**
   * Snoop PTP packet for version 2 format 
   * When set the PTP packets are snooped using the version 2 format.
@@ -3584,11 +3553,10 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value)
         if(loop_variable < DEFAULT_LOOP_VARIABLE)
                synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSADDREG);
         else{
-        TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
-    return -ESYNOPGMACPHYERR;
+          TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
+          return -ESYNOPGMACPHYERR;
         }
-return -ESYNOPGMACNOERR;
-
+    return -ESYNOPGMACNOERR;
 }
 /**
   * time stamp Update 
@@ -3602,21 +3570,21 @@ return -ESYNOPGMACNOERR;
 s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value)
 {
     u32 loop_variable;
-        synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
-        synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
-        for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
+    synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
+    synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
+    for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
         if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break
-        break;
+            break;
         } 
         plat_delay(DEFAULT_DELAY_VARIABLE);
-        }
-        if(loop_variable < DEFAULT_LOOP_VARIABLE)
-               synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT);
-        else{
+    }
+    if(loop_variable < DEFAULT_LOOP_VARIABLE)
+        synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT);
+    else{
         TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
-    return -ESYNOPGMACPHYERR;
-        }
-return -ESYNOPGMACNOERR;
+        return -ESYNOPGMACPHYERR;
+    }
+    return -ESYNOPGMACNOERR;
 }
 
 /**
@@ -3631,21 +3599,21 @@ return -ESYNOPGMACNOERR;
 s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value)
 {
     u32 loop_variable;
-        synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
-        synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
-        for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
+    synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
+    synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
+    for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
         if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break
-        break;
+            break;
         } 
         plat_delay(DEFAULT_DELAY_VARIABLE);
-        }
-        if(loop_variable < DEFAULT_LOOP_VARIABLE)
-               synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT);
-        else{
+    }
+    if(loop_variable < DEFAULT_LOOP_VARIABLE)
+        synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT);
+    else{
         TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
-    return -ESYNOPGMACPHYERR;
-        }
-return -ESYNOPGMACNOERR;
+        return -ESYNOPGMACPHYERR;
+    }
+    return -ESYNOPGMACNOERR;
 }
 
 /**
@@ -3696,8 +3664,8 @@ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value
 void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 *  sub_sec_val)
 {
     * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask);
-        * sec_val        = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh);
-        * sub_sec_val    = synopGMACReadReg(gmacdev->MacBase,GmacTSLow);
+    * sec_val        = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh);
+    * sub_sec_val    = synopGMACReadReg(gmacdev->MacBase,GmacTSLow);
     return;
 }
 /**
diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h
index fceb7af1fb..f47046d5ba 100644
--- a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h
+++ b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h
@@ -15,17 +15,17 @@
 #define SYNOP_GMAC_DEV_H 1
 
 /*******************************************************************/
-#define SYNOP_LOOPBACK_MODE 0
-#define SYNOP_LOOPBACK_DEBUG 0
-#define SYNOP_PHY_LOOPBACK 0
+#define SYNOP_LOOPBACK_MODE     (0)
+#define SYNOP_LOOPBACK_DEBUG    (0)
+#define SYNOP_PHY_LOOPBACK      (0)
 
-#define SYNOP_TX_TEST 0
-#define SYNOP_RX_TEST 0
+#define SYNOP_TX_TEST           (0)
+#define SYNOP_RX_TEST           (0)
 
-#define SYNOP_TOP_DEBUG 0
-#define SYNOP_REG_DEBUG 0
-#define SYNOP_RX_DEBUG 0
-#define SYNOP_TX_DEBUG 0
+#define SYNOP_TOP_DEBUG         (0)
+#define SYNOP_REG_DEBUG         (0)
+#define SYNOP_RX_DEBUG          (0)
+#define SYNOP_TX_DEBUG          (0)
 
 #define ENH_DESC
 /*******************************************************************/
@@ -49,35 +49,35 @@
 
 enum GMACPhyBase
 {
-    PHY0  = 0,            //The device can support 32 phys, but we use first phy only
+    PHY0  = 0,                    //The device can support 32 phys, but we use first phy only
     PHY1  = 1,
     PHY16 = 16,
     PHY31 = 31,
 };
 
 
-//#define TRANSMIT_DESC_SIZE  256        //Tx Descriptors needed in the Descriptor pool/queue
-//#define RECEIVE_DESC_SIZE   256     //Rx Descriptors needed in the Descriptor pool/queue
-//#define TRANSMIT_DESC_SIZE  13//256    //Tx Descriptors needed in the Descriptor pool/queue
-#define TRANSMIT_DESC_SIZE  36 //48    //Tx Descriptors needed in the Descriptor pool/queue
-#define RECEIVE_DESC_SIZE   36 //96    //Rx Descriptors needed in the Descriptor pool/queue
+//#define TRANSMIT_DESC_SIZE    256        //Tx Descriptors needed in the Descriptor pool/queue
+//#define RECEIVE_DESC_SIZE     256        //Rx Descriptors needed in the Descriptor pool/queue
+//#define TRANSMIT_DESC_SIZE    13//256    //Tx Descriptors needed in the Descriptor pool/queue
+#define TRANSMIT_DESC_SIZE      36 //48      //Tx Descriptors needed in the Descriptor pool/queue
+#define RECEIVE_DESC_SIZE       36 //96      //Rx Descriptors needed in the Descriptor pool/queue
 
-#define ETHERNET_HEADER             14    //6 byte Dest addr, 6 byte Src addr, 2 byte length/type
-#define ETHERNET_CRC                 4    //Ethernet CRC
-#define ETHERNET_EXTRA             2  //Only God knows about this?????
-#define ETHERNET_PACKET_COPY       250  // Maximum length when received data is copied on to a new skb  
-#define ETHERNET_PACKET_EXTRA        18  // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA  
-#define VLAN_TAG             4  //optional 802.1q VLAN Tag
-#define MIN_ETHERNET_PAYLOAD        46  //Minimum Ethernet payload size
-#define MAX_ETHERNET_PAYLOAD      1500  //Maximum Ethernet payload size
-#define JUMBO_FRAME_PAYLOAD       9000  //Jumbo frame payload size
+#define ETHERNET_HEADER         14           //6 byte Dest addr, 6 byte Src addr, 2 byte length/type
+#define ETHERNET_CRC            4            //Ethernet CRC
+#define ETHERNET_EXTRA          2            //Only God knows about this?????
+#define ETHERNET_PACKET_COPY    250          // Maximum length when received data is copied on to a new skb  
+#define ETHERNET_PACKET_EXTRA   18           // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA  
+#define VLAN_TAG                4            //optional 802.1q VLAN Tag
+#define MIN_ETHERNET_PAYLOAD    46           //Minimum Ethernet payload size
+#define MAX_ETHERNET_PAYLOAD    1500         //Maximum Ethernet payload size
+#define JUMBO_FRAME_PAYLOAD     9000         //Jumbo frame payload size
 
-#define TX_BUF_SIZE        ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000
-#define RX_BUF_SIZE        ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000
+#define TX_BUF_SIZE             ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000
+#define RX_BUF_SIZE             ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000
 
 
 // This is the IP's phy address. This is unique address for every MAC in the universe
-#define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7}
+#define DEFAULT_MAC_ADDRESS     {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7}
 
 /*
 DMA Descriptor Structure
@@ -98,31 +98,31 @@ In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DES
 #ifdef ENH_DESC_8W
 typedef struct DmaDescStruct    
 {         
-  u32   status;         /* Status                                     */
-  u32   length;         /* Buffer 1  and Buffer 2 length                         */
-  u32   buffer1;        /* Network Buffer 1 pointer (Dma-able)                             */
-  u32   buffer2;        /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure     */
+    u32   status;         /* Status                                     */
+    u32   length;         /* Buffer 1  and Buffer 2 length                         */
+    u32   buffer1;        /* Network Buffer 1 pointer (Dma-able)                             */
+    u32   buffer2;        /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure     */
               /* This data below is used only by driver                    */
-  u32   extstatus;      /* Extended status of a Rx Descriptor                                           */
-  u32   reserved1;      /* Reserved word                                                                */
-  u32   timestamplow;   /* Lower 32 bits of the 64 bit timestamp value                                  */
-  u32   timestamphigh;  /* Higher 32 bits of the 64 bit timestamp value                                  */
-  u64   data1;          /* This holds virtual address of buffer1, not used by DMA              */
-  u64   data2;          /* This holds virtual address of buffer2, not used by DMA              */
+    u32   extstatus;      /* Extended status of a Rx Descriptor                                           */
+    u32   reserved1;      /* Reserved word                                                                */
+    u32   timestamplow;   /* Lower 32 bits of the 64 bit timestamp value                                  */
+    u32   timestamphigh;  /* Higher 32 bits of the 64 bit timestamp value                                  */
+    u64   data1;          /* This holds virtual address of buffer1, not used by DMA              */
+    u64   data2;          /* This holds virtual address of buffer2, not used by DMA              */
 } DmaDesc;
 #else
 typedef struct DmaDescStruct    
 {                               
-  u32   status;         /* Status                                     */
-  u32   length;         /* Buffer 1  and Buffer 2 length                         */
-  u32   buffer1;        /* Network Buffer 1 pointer (Dma-able)                             */
-  u32   buffer2;        /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure     */
-              /* This data below is used only by driver                    */
-  u64   data1;          /* This holds virtual address of buffer1, not used by DMA              */
-  u64   data2;          /* This holds virtual address of buffer2, not used by DMA              */
+    u32   status;         /* Status                                     */
+    u32   length;         /* Buffer 1  and Buffer 2 length                         */
+    u32   buffer1;        /* Network Buffer 1 pointer (Dma-able)                             */
+    u32   buffer2;        /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure     */
+                        /* This data below is used only by driver                    */
+    u64   data1;          /* This holds virtual address of buffer1, not used by DMA              */
+    u64   data2;          /* This holds virtual address of buffer2, not used by DMA              */
 
-  //u32     dummy1;        //sw: for addr align
-  //u32   dummy2;        //  
+    //u32   dummy1;        //sw: for addr align
+    //u32   dummy2;        //  
 
 } DmaDesc;
 #endif
@@ -130,137 +130,130 @@ typedef struct DmaDescStruct
 enum DescMode
 {
     RINGMODE    = 0x00000001,
-    CHAINMODE    = 0x00000002,
+    CHAINMODE   = 0x00000002,
 };
 
 enum BufferMode
 {
-    SINGLEBUF    = 0x00000001,
-    DUALBUF        = 0x00000002,
+    SINGLEBUF   = 0x00000001,
+    DUALBUF     = 0x00000002,
 };
 
 /* synopGMAC device data */
 
 typedef struct synopGMACDeviceStruct    
 {
-  u64 MacBase;                  /* base address of MAC registers         */
-  u64 DmaBase;                  /* base address of DMA registers         */
-  u64 PhyBase;               /* PHY device address on MII interface   */
-  u32 Version;                     /* Gmac Revision version              */        
+    u64 MacBase;                  /* base address of MAC registers         */
+    u64 DmaBase;                  /* base address of DMA registers         */
+    u64 PhyBase;                  /* PHY device address on MII interface   */
+    u32 Version;                  /* Gmac Revision version                 */        
     
+    dma_addr_t TxDescDma;         /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/
+    dma_addr_t RxDescDma;         /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ 
+    DmaDesc *TxDesc;              /* start address of TX descriptors ring or chain, this is used by the driver  */
+    DmaDesc *RxDesc;              /* start address of RX descriptors ring or chain, this is used by the driver  */
 
-  dma_addr_t TxDescDma;         /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/
-  dma_addr_t RxDescDma;      /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ 
-  DmaDesc *TxDesc;               /* start address of TX descriptors ring or chain, this is used by the driver  */
-  DmaDesc *RxDesc;               /* start address of RX descriptors ring or chain, this is used by the driver  */
-
-  u32 BusyTxDesc;         /* Number of Tx Descriptors owned by DMA at any given time*/  
-  u32 BusyRxDesc;         /* Number of Rx Descriptors owned by DMA at any given time*/  
-  
-  u32  RxDescCount;              /* number of rx descriptors in the tx descriptor queue/pool */
-  u32  TxDescCount;              /* number of tx descriptors in the rx descriptor queue/pool */
+    u32 BusyTxDesc;               /* Number of Tx Descriptors owned by DMA at any given time*/  
+    u32 BusyRxDesc;               /* Number of Rx Descriptors owned by DMA at any given time*/  
   
-  u32  TxBusy;                   /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr()                */
-  u32  TxNext;                   /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */
-  u32  RxBusy;                   /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr()                   */
-  u32  RxNext;                   /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */
-
-  DmaDesc * TxBusyDesc;          /* Tx Descriptor address corresponding to the index TxBusy */
-  DmaDesc * TxNextDesc;          /* Tx Descriptor address corresponding to the index TxNext */
-  DmaDesc * RxBusyDesc;          /* Rx Descriptor address corresponding to the index TxBusy */
-  DmaDesc * RxNextDesc;          /* Rx Descriptor address corresponding to the index RxNext */
-
-  /*Phy related stuff*/
-  u32 ClockDivMdc;        /* Clock divider value programmed in the hardware           */
-  /* The status of the link */
-  u32 LinkState0;        /* Link status as reported by the Marvel Phy                */
-  u32 LinkState;        /* Link status as reported by the Marvel Phy                */
-  u32 DuplexMode;               /* Duplex mode of the Phy                    */
-  u32 Speed;            /* Speed of the Phy                        */
-  u32 LoopBackMode;         /* Loopback status of the Phy                    */
+    u32 RxDescCount;              /* number of rx descriptors in the tx descriptor queue/pool */
+    u32 TxDescCount;              /* number of tx descriptors in the rx descriptor queue/pool */
   
+    u32 TxBusy;                   /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr()                */
+    u32 TxNext;                   /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */
+    u32 RxBusy;                   /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr()                   */
+    u32 RxNext;                   /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */
+
+    DmaDesc * TxBusyDesc;          /* Tx Descriptor address corresponding to the index TxBusy */
+    DmaDesc * TxNextDesc;          /* Tx Descriptor address corresponding to the index TxNext */
+    DmaDesc * RxBusyDesc;          /* Rx Descriptor address corresponding to the index TxBusy */
+    DmaDesc * RxNextDesc;          /* Rx Descriptor address corresponding to the index RxNext */
+
+    /*Phy related stuff*/
+    u32 ClockDivMdc;               /* Clock divider value programmed in the hardware           */
+    /* The status of the link */
+    u32 LinkState0;                /* Link status as reported by the Marvel Phy                */
+    u32 LinkState;                 /* Link status as reported by the Marvel Phy                */
+    u32 DuplexMode;                /* Duplex mode of the Phy                    */
+    u32 Speed;                     /* Speed of the Phy                        */
+    u32 LoopBackMode;              /* Loopback status of the Phy                    */
 //  void * FirstTxDesc;
 //  void * FirstRxDesc;
 //  u32 skb_array[RECEIVE_DESC_SIZE];
 } synopGMACdevice;
 
-
-
 /* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" 
  * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter.
  * Since the Phy register map is standard, this map hardly changes to a different Ppy
  */
-
 enum MiiRegisters
 {
-  PHY_CONTROL_REG           = 0x0000,        /*Control Register*/
-  PHY_STATUS_REG            = 0x0001,        /*Status Register */
-  PHY_ID_HI_REG             = 0x0002,        /*PHY Identifier High Register*/
-  PHY_ID_LOW_REG            = 0x0003,        /*PHY Identifier High Register*/
-  PHY_AN_ADV_REG            = 0x0004,        /*Auto-Negotiation Advertisement Register*/
-  PHY_LNK_PART_ABl_REG      = 0x0005,        /*Link Partner Ability Register (Base Page)*/
-  PHY_AN_EXP_REG            = 0x0006,        /*Auto-Negotiation Expansion Register*/
-  PHY_AN_NXT_PAGE_TX_REG    = 0x0007,        /*Next Page Transmit Register*/
-  PHY_LNK_PART_NXT_PAGE_REG = 0x0008,        /*Link Partner Next Page Register*/
-  PHY_1000BT_CTRL_REG       = 0x0009,        /*1000BASE-T Control Register*/
-  PHY_1000BT_STATUS_REG     = 0x000a,        /*1000BASE-T Status Register*/
-  PHY_SPECIFIC_CTRL_REG     = 0x0010,        /*Phy specific control register*/
-  PHY_SPECIFIC_STATUS_REG   = 0x0011,        /*Phy specific status register*/
-  PHY_INTERRUPT_ENABLE_REG  = 0x0012,        /*Phy interrupt enable register*/
-  PHY_INTERRUPT_STATUS_REG  = 0x0013,        /*Phy interrupt status register*/
-  PHY_EXT_PHY_SPC_CTRL        = 0x0014,        /*Extended Phy specific control*/
-  PHY_RX_ERR_COUNTER        = 0x0015,        /*Receive Error Counter*/
-  PHY_EXT_ADDR_CBL_DIAG     = 0x0016,        /*Extended address for cable diagnostic register*/
-  PHY_LED_CONTROL        = 0x0018,        /*LED Control*/            
-  PHY_MAN_LED_OVERIDE       = 0x0019,        /*Manual LED override register*/
-  PHY_EXT_PHY_SPC_CTRL2     = 0x001a,        /*Extended Phy specific control 2*/
-  PHY_EXT_PHY_SPC_STATUS    = 0x001b,        /*Extended Phy specific status*/
-  PHY_CBL_DIAG_REG        = 0x001c,        /*Cable diagnostic registers*/
+    PHY_CONTROL_REG           = 0x0000,        /*Control Register*/
+    PHY_STATUS_REG            = 0x0001,        /*Status Register */
+    PHY_ID_HI_REG             = 0x0002,        /*PHY Identifier High Register*/
+    PHY_ID_LOW_REG            = 0x0003,        /*PHY Identifier High Register*/
+    PHY_AN_ADV_REG            = 0x0004,        /*Auto-Negotiation Advertisement Register*/
+    PHY_LNK_PART_ABl_REG      = 0x0005,        /*Link Partner Ability Register (Base Page)*/
+    PHY_AN_EXP_REG            = 0x0006,        /*Auto-Negotiation Expansion Register*/
+    PHY_AN_NXT_PAGE_TX_REG    = 0x0007,        /*Next Page Transmit Register*/
+    PHY_LNK_PART_NXT_PAGE_REG = 0x0008,        /*Link Partner Next Page Register*/
+    PHY_1000BT_CTRL_REG       = 0x0009,        /*1000BASE-T Control Register*/
+    PHY_1000BT_STATUS_REG     = 0x000a,        /*1000BASE-T Status Register*/
+    PHY_SPECIFIC_CTRL_REG     = 0x0010,        /*Phy specific control register*/
+    PHY_SPECIFIC_STATUS_REG   = 0x0011,        /*Phy specific status register*/
+    PHY_INTERRUPT_ENABLE_REG  = 0x0012,        /*Phy interrupt enable register*/
+    PHY_INTERRUPT_STATUS_REG  = 0x0013,        /*Phy interrupt status register*/
+    PHY_EXT_PHY_SPC_CTRL      = 0x0014,        /*Extended Phy specific control*/
+    PHY_RX_ERR_COUNTER        = 0x0015,        /*Receive Error Counter*/
+    PHY_EXT_ADDR_CBL_DIAG     = 0x0016,        /*Extended address for cable diagnostic register*/
+    PHY_LED_CONTROL           = 0x0018,        /*LED Control*/            
+    PHY_MAN_LED_OVERIDE       = 0x0019,        /*Manual LED override register*/
+    PHY_EXT_PHY_SPC_CTRL2     = 0x001a,        /*Extended Phy specific control 2*/
+    PHY_EXT_PHY_SPC_STATUS    = 0x001b,        /*Extended Phy specific status*/
+    PHY_CBL_DIAG_REG          = 0x001c,        /*Cable diagnostic registers*/
 };
 
-
 /* This is Control register layout. Control register is of 16 bit wide.
 */
-
 enum Mii_GEN_CTRL
-{                              /*    Description                   bits           R/W    default value  */
-    Mii_reset         = 0x8000, 
-      Mii_Speed_10            = 0x0000,   /* 10   Mbps                    6:13             RW                      */
-    Mii_Speed_100        = 0x2000,   /* 100  Mbps                    6:13             RW                      */
-    Mii_Speed_1000          = 0x0040,   /* 1000 Mbit/s                  6:13             RW                      */
+{                                        /*    Description               bits           R/W    default value  */
+    Mii_reset                = 0x8000, 
+    Mii_Speed_10             = 0x0000,   /* 10   Mbps                    6:13           RW                      */
+    Mii_Speed_100            = 0x2000,   /* 100  Mbps                    6:13           RW                      */
+    Mii_Speed_1000           = 0x0040,   /* 1000 Mbit/s                  6:13           RW                      */
 
-    Mii_Duplex              = 0x0100,   /* Full Duplex mode             8                   RW                      */
+    Mii_Duplex               = 0x0100,   /* Full Duplex mode             8              RW                      */
      
-    Mii_Manual_Master_Config = 0x0800,   /* Manual Master Config         11                  RW            */
+    Mii_Manual_Master_Config = 0x0800,   /* Manual Master Config         11             RW                      */
     
-    Mii_Loopback            = 0x4000,   /* Enable Loop back             14                  RW                      */
-    Mii_NoLoopback          = 0x0000,   /* Enable Loop back             14                  RW                      */
+    Mii_Loopback             = 0x4000,   /* Enable Loop back             14             RW                      */
+    Mii_NoLoopback           = 0x0000,   /* Enable Loop back             14             RW                      */
 };
 
 enum Mii_Phy_Status
 {
     Mii_phy_status_speed_10         = 0x0000,
-    Mii_phy_status_speed_100      = 0x4000,
-    Mii_phy_status_speed_1000    = 0x8000,
+    Mii_phy_status_speed_100        = 0x4000,
+    Mii_phy_status_speed_1000       = 0x8000,
     
-    Mii_phy_status_full_duplex    = 0x2000,
-    Mii_phy_status_half_duplex    = 0x0000,
+    Mii_phy_status_full_duplex      = 0x2000,
+    Mii_phy_status_half_duplex      = 0x0000,
     
-    Mii_phy_status_link_up        = 0x0400,    //lyf:rtl 8211 phy
+    Mii_phy_status_link_up          = 0x0400,    //lyf:rtl 8211 phy
 //    Mii_phy_status_link_up        = 0x0100,    //sw: broadcom BCM5461 PHY
 };
 /* This is Status register layout. Status register is of 16 bit wide.
 */
 enum Mii_GEN_STATUS
 {
-    Mii_AutoNegCmplt     = 0x0020,   /* Autonegotiation completed      5              RW                   */
-    Mii_Link             = 0x0004,   /* Link status                    2              RW                   */
+    Mii_AutoNegCmplt                = 0x0020,   /* Autonegotiation completed      5              RW                   */
+    Mii_Link                        = 0x0004,   /* Link status                    2              RW                   */
 };
 
 enum Mii_Link_Status
 {
-    LINKDOWN    = 0,
-    LINKUP        = 1,
+    LINKDOWN   = 0,
+    LINKUP     = 1,
 };
 
 enum Mii_Duplex_Mode
@@ -281,8 +274,6 @@ enum Mii_Loop_Back
     LOOPBACK    = 1,
 };
 
-
-
 /**********************************************************
  * GMAC registers Map
  * For Pci based system address is BARx + GmacRegisterBase
@@ -290,76 +281,76 @@ enum Mii_Loop_Back
  **********************************************************/
 enum GmacRegisters              
 {
-  GmacConfig           = 0x0000,    /* Mac config Register                       */
-  GmacFrameFilter        = 0x0004,    /* Mac frame filtering controls              */
-  GmacHashHigh           = 0x0008,    /* Multi-cast hash table high                */
-  GmacHashLow            = 0x000C,    /* Multi-cast hash table low                 */
-  GmacGmiiAddr           = 0x0010,    /* GMII address Register(ext. Phy)           */
-  GmacGmiiData           = 0x0014,    /* GMII data Register(ext. Phy)              */
-  GmacFlowControl        = 0x0018,    /* Flow control Register                     */
-  GmacVlan               = 0x001C,    /* VLAN tag Register (IEEE 802.1Q)           */
+    GmacConfig             = 0x0000,    /* Mac config Register                       */
+    GmacFrameFilter        = 0x0004,    /* Mac frame filtering controls              */
+    GmacHashHigh           = 0x0008,    /* Multi-cast hash table high                */
+    GmacHashLow            = 0x000C,    /* Multi-cast hash table low                 */
+    GmacGmiiAddr           = 0x0010,    /* GMII address Register(ext. Phy)           */
+    GmacGmiiData           = 0x0014,    /* GMII data Register(ext. Phy)              */
+    GmacFlowControl        = 0x0018,    /* Flow control Register                     */
+    GmacVlan               = 0x001C,    /* VLAN tag Register (IEEE 802.1Q)           */
   
-  GmacVersion           = 0x0020,    /* GMAC Core Version Register                */ 
-  GmacWakeupAddr        = 0x0028,    /* GMAC wake-up frame filter adrress reg     */ 
-  GmacPmtCtrlStatus        = 0x002C,    /* PMT control and status register           */ 
+    GmacVersion            = 0x0020,    /* GMAC Core Version Register                */ 
+    GmacWakeupAddr         = 0x0028,    /* GMAC wake-up frame filter adrress reg     */ 
+    GmacPmtCtrlStatus      = 0x002C,    /* PMT control and status register           */ 
   
-  GmacInterruptStatus      = 0x0038,    /* Mac Interrupt ststus register           */  
-  GmacInterruptMask       = 0x003C,    /* Mac Interrupt Mask register           */  
+    GmacInterruptStatus    = 0x0038,    /* Mac Interrupt ststus register           */  
+    GmacInterruptMask      = 0x003C,    /* Mac Interrupt Mask register           */  
  
-  GmacAddr0High          = 0x0040,    /* Mac address0 high Register                */
-  GmacAddr0Low          = 0x0044,    /* Mac address0 low Register                 */
-  GmacAddr1High          = 0x0048,    /* Mac address1 high Register                */
-  GmacAddr1Low           = 0x004C,    /* Mac address1 low Register                 */
-  GmacAddr2High         = 0x0050,    /* Mac address2 high Register                */
-  GmacAddr2Low           = 0x0054,    /* Mac address2 low Register                 */
-  GmacAddr3High          = 0x0058,    /* Mac address3 high Register                */
-  GmacAddr3Low           = 0x005C,    /* Mac address3 low Register                 */
-  GmacAddr4High          = 0x0060,    /* Mac address4 high Register                */
-  GmacAddr4Low           = 0x0064,    /* Mac address4 low Register                 */
-  GmacAddr5High          = 0x0068,    /* Mac address5 high Register                */
-  GmacAddr5Low           = 0x006C,    /* Mac address5 low Register                 */
-  GmacAddr6High          = 0x0070,    /* Mac address6 high Register                */
-  GmacAddr6Low           = 0x0074,    /* Mac address6 low Register                 */
-  GmacAddr7High          = 0x0078,    /* Mac address7 high Register                */
-  GmacAddr7Low           = 0x007C,    /* Mac address7 low Register                 */
-  GmacAddr8High          = 0x0080,    /* Mac address8 high Register                */
-  GmacAddr8Low           = 0x0084,    /* Mac address8 low Register                 */
-  GmacAddr9High          = 0x0088,    /* Mac address9 high Register                */
-  GmacAddr9Low            = 0x008C,    /* Mac address9 low Register                 */
-  GmacAddr10High          = 0x0090,    /* Mac address10 high Register               */
-  GmacAddr10Low          = 0x0094,    /* Mac address10 low Register                */
-  GmacAddr11High         = 0x0098,    /* Mac address11 high Register               */
-  GmacAddr11Low          = 0x009C,    /* Mac address11 low Register                */
-  GmacAddr12High         = 0x00A0,    /* Mac address12 high Register               */
-  GmacAddr12Low           = 0x00A4,    /* Mac address12 low Register                */
-  GmacAddr13High         = 0x00A8,    /* Mac address13 high Register               */
-  GmacAddr13Low         = 0x00AC,    /* Mac address13 low Register                */
-  GmacAddr14High         = 0x00B0,    /* Mac address14 high Register               */
-  GmacAddr14Low              = 0x00B4,    /* Mac address14 low Register                */
-  GmacAddr15High           = 0x00B8,    /* Mac address15 high Register               */
-  GmacAddr15Low        = 0x00BC,    /* Mac address15 low Register                */
-  GmacStatus          = 0x00d8,    /*MAC status*/
+    GmacAddr0High          = 0x0040,    /* Mac address0 high Register                */
+    GmacAddr0Low           = 0x0044,    /* Mac address0 low Register                 */
+    GmacAddr1High          = 0x0048,    /* Mac address1 high Register                */
+    GmacAddr1Low           = 0x004C,    /* Mac address1 low Register                 */
+    GmacAddr2High          = 0x0050,    /* Mac address2 high Register                */
+    GmacAddr2Low           = 0x0054,    /* Mac address2 low Register                 */
+    GmacAddr3High          = 0x0058,    /* Mac address3 high Register                */
+    GmacAddr3Low           = 0x005C,    /* Mac address3 low Register                 */
+    GmacAddr4High          = 0x0060,    /* Mac address4 high Register                */
+    GmacAddr4Low           = 0x0064,    /* Mac address4 low Register                 */
+    GmacAddr5High          = 0x0068,    /* Mac address5 high Register                */
+    GmacAddr5Low           = 0x006C,    /* Mac address5 low Register                 */
+    GmacAddr6High          = 0x0070,    /* Mac address6 high Register                */
+    GmacAddr6Low           = 0x0074,    /* Mac address6 low Register                 */
+    GmacAddr7High          = 0x0078,    /* Mac address7 high Register                */
+    GmacAddr7Low           = 0x007C,    /* Mac address7 low Register                 */
+    GmacAddr8High          = 0x0080,    /* Mac address8 high Register                */
+    GmacAddr8Low           = 0x0084,    /* Mac address8 low Register                 */
+    GmacAddr9High          = 0x0088,    /* Mac address9 high Register                */
+    GmacAddr9Low           = 0x008C,    /* Mac address9 low Register                 */
+    GmacAddr10High         = 0x0090,    /* Mac address10 high Register               */
+    GmacAddr10Low          = 0x0094,    /* Mac address10 low Register                */
+    GmacAddr11High         = 0x0098,    /* Mac address11 high Register               */
+    GmacAddr11Low          = 0x009C,    /* Mac address11 low Register                */
+    GmacAddr12High         = 0x00A0,    /* Mac address12 high Register               */
+    GmacAddr12Low          = 0x00A4,    /* Mac address12 low Register                */
+    GmacAddr13High         = 0x00A8,    /* Mac address13 high Register               */
+    GmacAddr13Low          = 0x00AC,    /* Mac address13 low Register                */
+    GmacAddr14High         = 0x00B0,    /* Mac address14 high Register               */
+    GmacAddr14Low          = 0x00B4,    /* Mac address14 low Register                */
+    GmacAddr15High         = 0x00B8,    /* Mac address15 high Register               */
+    GmacAddr15Low          = 0x00BC,    /* Mac address15 low Register                */
+    GmacStatus             = 0x00d8,    /* MAC status                                */
 
   /*Time Stamp Register Map*/
-  GmacTSControl              = 0x0700,  /* Controls the Timestamp update logic                         : only when IEEE 1588 time stamping is enabled in corekit            */
+    GmacTSControl          = 0x0700,  /* Controls the Timestamp update logic                         : only when IEEE 1588 time stamping is enabled in corekit            */
 
-  GmacTSSubSecIncr           = 0x0704,  /* 8 bit value by which sub second register is incremented     : only when IEEE 1588 time stamping without external timestamp input */
+    GmacTSSubSecIncr       = 0x0704,  /* 8 bit value by which sub second register is incremented     : only when IEEE 1588 time stamping without external timestamp input */
 
-  GmacTSHigh                = 0x0708,  /* 32 bit seconds(MS)                                          : only when IEEE 1588 time stamping without external timestamp input */
-  GmacTSLow                 = 0x070C,  /* 32 bit nano seconds(MS)                                     : only when IEEE 1588 time stamping without external timestamp input */
+    GmacTSHigh             = 0x0708,  /* 32 bit seconds(MS)                                          : only when IEEE 1588 time stamping without external timestamp input */
+    GmacTSLow              = 0x070C,  /* 32 bit nano seconds(MS)                                     : only when IEEE 1588 time stamping without external timestamp input */
   
-  GmacTSHighUpdate        = 0x0710,  /* 32 bit seconds(MS) to be written/added/subtracted           : only when IEEE 1588 time stamping without external timestamp input */
-  GmacTSLowUpdate         = 0x0714,  /* 32 bit nano seconds(MS) to be writeen/added/subtracted      : only when IEEE 1588 time stamping without external timestamp input */
+    GmacTSHighUpdate       = 0x0710,  /* 32 bit seconds(MS) to be written/added/subtracted           : only when IEEE 1588 time stamping without external timestamp input */
+    GmacTSLowUpdate        = 0x0714,  /* 32 bit nano seconds(MS) to be writeen/added/subtracted      : only when IEEE 1588 time stamping without external timestamp input */
   
-  GmacTSAddend            = 0x0718,  /* Used by Software to readjust the clock frequency linearly   : only when IEEE 1588 time stamping without external timestamp input */
+    GmacTSAddend           = 0x0718,  /* Used by Software to readjust the clock frequency linearly   : only when IEEE 1588 time stamping without external timestamp input */
   
-  GmacTSTargetTimeHigh       = 0x071C,  /* 32 bit seconds(MS) to be compared with system time          : only when IEEE 1588 time stamping without external timestamp input */
-  GmacTSTargetTimeLow     = 0x0720,  /* 32 bit nano seconds(MS) to be compared with system time     : only when IEEE 1588 time stamping without external timestamp input */
+    GmacTSTargetTimeHigh   = 0x071C,  /* 32 bit seconds(MS) to be compared with system time          : only when IEEE 1588 time stamping without external timestamp input */
+    GmacTSTargetTimeLow    = 0x0720,  /* 32 bit nano seconds(MS) to be compared with system time     : only when IEEE 1588 time stamping without external timestamp input */
 
-  GmacTSHighWord          = 0x0724,  /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid                                                   */
-  //GmacTSHighWordUpdate    = 0x072C,  /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid                                            */
+    GmacTSHighWord         = 0x0724,  /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid                                                   */
+//GmacTSHighWordUpdate    = 0x072C,  /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid                                            */
   
-  GmacTSStatus            = 0x0728,  /* Time Stamp Status Register                                                                                                       */
+    GmacTSStatus           = 0x0728,  /* Time Stamp Status Register                                                                                                       */
 };
 
 /**********************************************************
@@ -376,214 +367,211 @@ enum GmacRegisters
 /* GmacConfig              = 0x0000,    Mac config Register  Layout */
 enum GmacConfigReg      
 { 
-                                           /* Bit description                      Bits         R/W   Reset value  */
-  GmacWatchdog           = 0x00800000,
-  GmacWatchdogDisable      = 0x00800000,     /* (WD)Disable watchdog timer on Rx      23           RW                */
-  GmacWatchdogEnable       = 0x00000000,     /* Enable watchdog timer                                        0       */
-
-  GmacJabber           = 0x00400000,
-  GmacJabberDisable        = 0x00400000,     /* (JD)Disable jabber timer on Tx        22           RW                */
-  GmacJabberEnable         = 0x00000000,     /* Enable jabber timer                                          0       */
-
-  GmacFrameBurst           = 0x00200000,
-  GmacFrameBurstEnable     = 0x00200000,     /* (BE)Enable frame bursting during Tx   21           RW                */
-  GmacFrameBurstDisable    = 0x00000000,     /* Disable frame bursting                                       0       */
+                                             /* Bit description                      Bits         R/W   Reset value  */
+    GmacWatchdog             = 0x00800000,
+    GmacWatchdogDisable      = 0x00800000,     /* (WD)Disable watchdog timer on Rx      23           RW                */
+    GmacWatchdogEnable       = 0x00000000,     /* Enable watchdog timer                                        0       */
+
+    GmacJabber               = 0x00400000,
+    GmacJabberDisable        = 0x00400000,     /* (JD)Disable jabber timer on Tx        22           RW                */
+    GmacJabberEnable         = 0x00000000,     /* Enable jabber timer                                          0       */
+
+    GmacFrameBurst           = 0x00200000,
+    GmacFrameBurstEnable     = 0x00200000,     /* (BE)Enable frame bursting during Tx   21           RW                */
+    GmacFrameBurstDisable    = 0x00000000,     /* Disable frame bursting                                       0       */
   
-  GmacJumboFrame           = 0x00100000,
-  GmacJumboFrameEnable     = 0x00100000,     /* (JE)Enable jumbo frame for Tx         20           RW                */
-  GmacJumboFrameDisable    = 0x00000000,     /* Disable jumbo frame                                          0       */
-
-  GmacInterFrameGap7       = 0x000E0000,     /* (IFG) Config7 - 40 bit times          19:17        RW                */
-  GmacInterFrameGap6       = 0x000C0000,     /* (IFG) Config6 - 48 bit times                                         */
-  GmacInterFrameGap5       = 0x000A0000,     /* (IFG) Config5 - 56 bit times                                         */
-  GmacInterFrameGap4       = 0x00080000,     /* (IFG) Config4 - 64 bit times                                         */
-  GmacInterFrameGap3       = 0x00040000,     /* (IFG) Config3 - 72 bit times                                         */
-  GmacInterFrameGap2       = 0x00020000,     /* (IFG) Config2 - 80 bit times                                         */
-  GmacInterFrameGap1       = 0x00010000,     /* (IFG) Config1 - 88 bit times                                         */
-  GmacInterFrameGap0       = 0x00000000,     /* (IFG) Config0 - 96 bit times                                 000     */
+    GmacJumboFrame           = 0x00100000,
+    GmacJumboFrameEnable     = 0x00100000,     /* (JE)Enable jumbo frame for Tx         20           RW                */
+    GmacJumboFrameDisable    = 0x00000000,     /* Disable jumbo frame                                          0       */
+
+    GmacInterFrameGap7       = 0x000E0000,     /* (IFG) Config7 - 40 bit times          19:17        RW                */
+    GmacInterFrameGap6       = 0x000C0000,     /* (IFG) Config6 - 48 bit times                                         */
+    GmacInterFrameGap5       = 0x000A0000,     /* (IFG) Config5 - 56 bit times                                         */
+    GmacInterFrameGap4       = 0x00080000,     /* (IFG) Config4 - 64 bit times                                         */
+    GmacInterFrameGap3       = 0x00040000,     /* (IFG) Config3 - 72 bit times                                         */
+    GmacInterFrameGap2       = 0x00020000,     /* (IFG) Config2 - 80 bit times                                         */
+    GmacInterFrameGap1       = 0x00010000,     /* (IFG) Config1 - 88 bit times                                         */
+    GmacInterFrameGap0       = 0x00000000,     /* (IFG) Config0 - 96 bit times                                 000     */
  
-  GmacDisableCrs       = 0x00010000, 
-  GmacMiiGmii           = 0x00008000,
-  GmacSelectMii            = 0x00008000,     /* (PS)Port Select-MII mode              15           RW                */
-  GmacSelectGmii           = 0x00000000,     /* GMII mode                                                    0       */
+    GmacDisableCrs           = 0x00010000, 
+    GmacMiiGmii              = 0x00008000,
+    GmacSelectMii            = 0x00008000,     /* (PS)Port Select-MII mode              15           RW                */
+    GmacSelectGmii           = 0x00000000,     /* GMII mode                                                    0       */
 
-  GmacFESpeed100           = 0x00004000,     /*(FES)Fast Ethernet speed 100Mbps       14           RW                */ 
-  GmacFESpeed10            = 0x00000000,     /* 10Mbps                                                       0       */ 
+    GmacFESpeed100           = 0x00004000,     /*(FES)Fast Ethernet speed 100Mbps       14           RW                */ 
+    GmacFESpeed10            = 0x00000000,     /* 10Mbps                                                       0       */ 
 
-  GmacRxOwn           = 0x00002000, 
-  GmacDisableRxOwn         = 0x00002000,     /* (DO)Disable receive own packets       13           RW                */
-  GmacEnableRxOwn          = 0x00000000,     /* Enable receive own packets                                   0       */
+    GmacRxOwn                = 0x00002000, 
+    GmacDisableRxOwn         = 0x00002000,     /* (DO)Disable receive own packets       13           RW                */
+    GmacEnableRxOwn          = 0x00000000,     /* Enable receive own packets                                   0       */
   
-  GmacLoopback           = 0x00001000,
-  GmacLoopbackOn           = 0x00001000,     /* (LM)Loopback mode for GMII/MII        12           RW                */
-  GmacLoopbackOff          = 0x00000000,     /* Normal mode                                                  0       */
+    GmacLoopback             = 0x00001000,
+    GmacLoopbackOn           = 0x00001000,     /* (LM)Loopback mode for GMII/MII        12           RW                */
+    GmacLoopbackOff          = 0x00000000,     /* Normal mode                                                  0       */
 
-  GmacDuplex           = 0x00000800,
-  GmacFullDuplex           = 0x00000800,     /* (DM)Full duplex mode                  11           RW                */
-  GmacHalfDuplex           = 0x00000000,     /* Half duplex mode                                             0       */
+    GmacDuplex               = 0x00000800,
+    GmacFullDuplex           = 0x00000800,     /* (DM)Full duplex mode                  11           RW                */
+    GmacHalfDuplex           = 0x00000000,     /* Half duplex mode                                             0       */
 
-  GmacRxIpcOffload       = 0x00000400,     /*IPC checksum offload              10           RW        0       */
+    GmacRxIpcOffload         = 0x00000400,     /* IPC checksum offload                  10           RW        0       */
 
-  GmacRetry           = 0x00000200,
-  GmacRetryDisable         = 0x00000200,     /* (DR)Disable Retry                      9           RW                */
-  GmacRetryEnable          = 0x00000000,     /* Enable retransmission as per BL                              0       */
+    GmacRetry                = 0x00000200,
+    GmacRetryDisable         = 0x00000200,     /* (DR)Disable Retry                      9           RW                */
+    GmacRetryEnable          = 0x00000000,     /* Enable retransmission as per BL                              0       */
 
-  GmacLinkUp               = 0x00000100,     /* (LUD)Link UP                           8           RW                */ 
-  GmacLinkDown             = 0x00000100,     /* Link Down                                                    0       */ 
+    GmacLinkUp               = 0x00000100,     /* (LUD)Link UP                           8           RW                */ 
+    GmacLinkDown             = 0x00000100,     /* Link Down                                                    0       */ 
   
-  GmacPadCrcStrip       = 0x00000080,
-  GmacPadCrcStripEnable    = 0x00000080,     /* (ACS) Automatic Pad/Crc strip enable   7           RW                */
-  GmacPadCrcStripDisable   = 0x00000000,     /* Automatic Pad/Crc stripping disable                          0       */
+    GmacPadCrcStrip          = 0x00000080,
+    GmacPadCrcStripEnable    = 0x00000080,     /* (ACS) Automatic Pad/Crc strip enable   7           RW                */
+    GmacPadCrcStripDisable   = 0x00000000,     /* Automatic Pad/Crc stripping disable                          0       */
   
-  GmacBackoffLimit       = 0x00000060,
-  GmacBackoffLimit3        = 0x00000060,     /* (BL)Back-off limit in HD mode          6:5         RW                */
-  GmacBackoffLimit2        = 0x00000040,     /*                                                                      */
-  GmacBackoffLimit1        = 0x00000020,     /*                                                                      */
-  GmacBackoffLimit0        = 0x00000000,     /*                                                              00      */
-
-  GmacDeferralCheck       = 0x00000010,
-  GmacDeferralCheckEnable  = 0x00000010,     /* (DC)Deferral check enable in HD mode   4           RW                */
-  GmacDeferralCheckDisable = 0x00000000,     /* Deferral check disable                                       0       */
+    GmacBackoffLimit         = 0x00000060,
+    GmacBackoffLimit3        = 0x00000060,     /* (BL)Back-off limit in HD mode          6:5         RW                */
+    GmacBackoffLimit2        = 0x00000040,     /*                                                                      */
+    GmacBackoffLimit1        = 0x00000020,     /*                                                                      */
+    GmacBackoffLimit0        = 0x00000000,     /*                                                              00      */
+
+    GmacDeferralCheck        = 0x00000010,
+    GmacDeferralCheckEnable  = 0x00000010,     /* (DC)Deferral check enable in HD mode   4           RW                */
+    GmacDeferralCheckDisable = 0x00000000,     /* Deferral check disable                                       0       */
    
-  GmacTx           = 0x00000008,
-  GmacTxEnable             = 0x00000008,     /* (TE)Transmitter enable                 3           RW                */
-  GmacTxDisable            = 0x00000000,     /* Transmitter disable                                          0       */
+    GmacTx                   = 0x00000008,
+    GmacTxEnable             = 0x00000008,     /* (TE)Transmitter enable                 3           RW                */
+    GmacTxDisable            = 0x00000000,     /* Transmitter disable                                          0       */
 
-  GmacRx           = 0x00000004,
-  GmacRxEnable             = 0x00000004,     /* (RE)Receiver enable                    2           RW                */
-  GmacRxDisable            = 0x00000000,     /* Receiver disable                                             0       */
+    GmacRx                   = 0x00000004,
+    GmacRxEnable             = 0x00000004,     /* (RE)Receiver enable                    2           RW                */
+    GmacRxDisable            = 0x00000000,     /* Receiver disable                                             0       */
 };
 
 /* GmacFrameFilter    = 0x0004,     Mac frame filtering controls Register Layout*/
 enum GmacFrameFilterReg 
 {
-  GmacFilter           = 0x80000000,
-  GmacFilterOff            = 0x80000000,     /* (RA)Receive all incoming packets       31         RW                 */
-  GmacFilterOn             = 0x00000000,     /* Receive filtered packets only                                0       */
+    GmacFilter               = 0x80000000,
+    GmacFilterOff            = 0x80000000,     /* (RA)Receive all incoming packets       31         RW                 */
+    GmacFilterOn             = 0x00000000,     /* Receive filtered packets only                                0       */
 
-  GmacHashPerfectFilter       = 0x00000400,     /*Hash or Perfect Filter enable           10         RW         0       */
+    GmacHashPerfectFilter    = 0x00000400,     /*Hash or Perfect Filter enable           10         RW         0       */
 
-  GmacSrcAddrFilter       = 0x00000200,
-  GmacSrcAddrFilterEnable  = 0x00000200,     /* (SAF)Source Address Filter enable       9         RW                 */
-  GmacSrcAddrFilterDisable = 0x00000000,     /*                                                              0       */
+    GmacSrcAddrFilter        = 0x00000200,
+    GmacSrcAddrFilterEnable  = 0x00000200,     /* (SAF)Source Address Filter enable       9         RW                 */
+    GmacSrcAddrFilterDisable = 0x00000000,     /*                                                              0       */
 
-  GmacSrcInvaAddrFilter    = 0x00000100,
-  GmacSrcInvAddrFilterEn   = 0x00000100,     /* (SAIF)Inv Src Addr Filter enable        8         RW                 */
-  GmacSrcInvAddrFilterDis  = 0x00000000,     /*                                                              0       */
+    GmacSrcInvaAddrFilter    = 0x00000100,
+    GmacSrcInvAddrFilterEn   = 0x00000100,     /* (SAIF)Inv Src Addr Filter enable        8         RW                 */
+    GmacSrcInvAddrFilterDis  = 0x00000000,     /*                                                              0       */
 
-  GmacPassControl       = 0x000000C0,
-  GmacPassControl3         = 0x000000C0,     /* (PCS)Forwards ctrl frms that pass AF    7:6       RW                 */
-  GmacPassControl2         = 0x00000080,     /* Forwards all control frames                                          */
-  GmacPassControl1         = 0x00000040,     /* Does not pass control frames                                         */
-  GmacPassControl0         = 0x00000000,     /* Does not pass control frames                                 00      */
+    GmacPassControl          = 0x000000C0,
+    GmacPassControl3         = 0x000000C0,     /* (PCS)Forwards ctrl frms that pass AF    7:6       RW                 */
+    GmacPassControl2         = 0x00000080,     /* Forwards all control frames                                          */
+    GmacPassControl1         = 0x00000040,     /* Does not pass control frames                                         */
+    GmacPassControl0         = 0x00000000,     /* Does not pass control frames                                 00      */
 
-  GmacBroadcast           = 0x00000020,
-  GmacBroadcastDisable     = 0x00000020,     /* (DBF)Disable Rx of broadcast frames     5         RW                 */
-  GmacBroadcastEnable      = 0x00000000,     /* Enable broadcast frames                                      0       */
+    GmacBroadcast            = 0x00000020,
+    GmacBroadcastDisable     = 0x00000020,     /* (DBF)Disable Rx of broadcast frames     5         RW                 */
+    GmacBroadcastEnable      = 0x00000000,     /* Enable broadcast frames                                      0       */
 
-  GmacMulticastFilter      = 0x00000010,
-  GmacMulticastFilterOff   = 0x00000010,     /* (PM) Pass all multicast packets         4         RW                 */
-  GmacMulticastFilterOn    = 0x00000000,     /* Pass filtered multicast packets                              0       */
+    GmacMulticastFilter      = 0x00000010,
+    GmacMulticastFilterOff   = 0x00000010,     /* (PM) Pass all multicast packets         4         RW                 */
+    GmacMulticastFilterOn    = 0x00000000,     /* Pass filtered multicast packets                              0       */
 
-  GmacDestAddrFilter       = 0x00000008,
-  GmacDestAddrFilterInv    = 0x00000008,     /* (DAIF)Inverse filtering for DA          3         RW                 */
-  GmacDestAddrFilterNor    = 0x00000000,     /* Normal filtering for DA                                      0       */
+    GmacDestAddrFilter       = 0x00000008,
+    GmacDestAddrFilterInv    = 0x00000008,     /* (DAIF)Inverse filtering for DA          3         RW                 */
+    GmacDestAddrFilterNor    = 0x00000000,     /* Normal filtering for DA                                      0       */
 
-  GmacMcastHashFilter      = 0x00000004,
-  GmacMcastHashFilterOn    = 0x00000004,     /* (HMC)perfom multicast hash filtering    2         RW                 */
-  GmacMcastHashFilterOff   = 0x00000000,     /* perfect filtering only                                       0       */
+    GmacMcastHashFilter      = 0x00000004,
+    GmacMcastHashFilterOn    = 0x00000004,     /* (HMC)perfom multicast hash filtering    2         RW                 */
+    GmacMcastHashFilterOff   = 0x00000000,     /* perfect filtering only                                       0       */
 
-  GmacUcastHashFilter      = 0x00000002,
-  GmacUcastHashFilterOn    = 0x00000002,     /* (HUC)Unicast Hash filtering only        1         RW                 */
-  GmacUcastHashFilterOff   = 0x00000000,     /* perfect filtering only                                       0       */
+    GmacUcastHashFilter      = 0x00000002,
+    GmacUcastHashFilterOn    = 0x00000002,     /* (HUC)Unicast Hash filtering only        1         RW                 */
+    GmacUcastHashFilterOff   = 0x00000000,     /* perfect filtering only                                       0       */
 
-  GmacPromiscuousMode      = 0x00000001,
-  GmacPromiscuousModeOn    = 0x00000001,     /* Receive all frames                      0         RW                 */
-  GmacPromiscuousModeOff   = 0x00000000,     /* Receive filtered packets only                                0       */
+    GmacPromiscuousMode      = 0x00000001,
+    GmacPromiscuousModeOn    = 0x00000001,     /* Receive all frames                      0         RW                 */
+    GmacPromiscuousModeOff   = 0x00000000,     /* Receive filtered packets only                                0       */
 };
 
- 
 /*GmacGmiiAddr             = 0x0010,    GMII address Register(ext. Phy) Layout          */
 enum GmacGmiiAddrReg      
 {
-  GmiiDevMask              = 0x0000F800,     /* (PA)GMII device address                 15:11     RW         0x00    */
-  GmiiDevShift             = 11,
+    GmiiDevMask              = 0x0000F800,     /* (PA)GMII device address                 15:11     RW         0x00    */
+    GmiiDevShift             = 11,
 
-  GmiiRegMask              = 0x000007C0,     /* (GR)GMII register in selected Phy       10:6      RW         0x00    */
-  GmiiRegShift             = 6,
+    GmiiRegMask              = 0x000007C0,     /* (GR)GMII register in selected Phy       10:6      RW         0x00    */
+    GmiiRegShift             = 6,
   
-  GmiiCsrClkMask       = 0x0000001C,     /*CSR Clock bit Mask             4:2                 */
-  GmiiCsrClk5              = 0x00000014,     /* (CR)CSR Clock Range     250-300 MHz      4:2      RW         000     */
-  GmiiCsrClk4              = 0x00000010,     /*                         150-250 MHz                                  */
-  GmiiCsrClk3              = 0x0000000C,     /*                         35-60 MHz                                    */
-  GmiiCsrClk2              = 0x00000008,     /*                         20-35 MHz                                    */
-  GmiiCsrClk1              = 0x00000004,     /*                         100-150 MHz                                  */
-  GmiiCsrClk0              = 0x00000000,     /*                         60-100 MHz                                   */
-
-  GmiiWrite                = 0x00000002,     /* (GW)Write to register                      1      RW                 */
-  GmiiRead                 = 0x00000000,     /* Read from register                                            0      */
-
-  GmiiBusy                 = 0x00000001,     /* (GB)GMII interface is busy                 0      RW          0      */
+    GmiiCsrClkMask           = 0x0000001C,     /* CSR Clock bit Mask             4:2                 */
+    GmiiCsrClk5              = 0x00000014,     /* (CR)CSR Clock Range     250-300 MHz      4:2      RW         000     */
+    GmiiCsrClk4              = 0x00000010,     /*                         150-250 MHz                                  */
+    GmiiCsrClk3              = 0x0000000C,     /*                         35-60 MHz                                    */
+    GmiiCsrClk2              = 0x00000008,     /*                         20-35 MHz                                    */
+    GmiiCsrClk1              = 0x00000004,     /*                         100-150 MHz                                  */
+    GmiiCsrClk0              = 0x00000000,     /*                         60-100 MHz                                   */
+
+    GmiiWrite                = 0x00000002,     /* (GW)Write to register                      1      RW                 */
+    GmiiRead                 = 0x00000000,     /* Read from register                                            0      */
+
+    GmiiBusy                 = 0x00000001,     /* (GB)GMII interface is busy                 0      RW          0      */
 };
 
 /* GmacGmiiData            = 0x0014,    GMII data Register(ext. Phy) Layout             */
 enum GmacGmiiDataReg      
 {
-  GmiiDataMask             = 0x0000FFFF,     /* (GD)GMII Data                             15:0    RW         0x0000  */
+    GmiiDataMask             = 0x0000FFFF,     /* (GD)GMII Data                             15:0    RW         0x0000  */
 };
 
-
 /*GmacFlowControl    = 0x0018,    Flow control Register   Layout                  */
 enum GmacFlowControlReg  
 {                                          
-  GmacPauseTimeMask        = 0xFFFF0000,     /* (PT) PAUSE TIME field in the control frame  31:16   RW       0x0000  */
-  GmacPauseTimeShift       = 16,
+    GmacPauseTimeMask        = 0xFFFF0000,     /* (PT) PAUSE TIME field in the control frame  31:16   RW       0x0000  */
+    GmacPauseTimeShift       = 16,
   
-  GmacPauseLowThresh       = 0x00000030,
-  GmacPauseLowThresh3      = 0x00000030,     /* (PLT)thresh for pause tmr 256 slot time      5:4    RW               */
-  GmacPauseLowThresh2      = 0x00000020,     /*                           144 slot time                              */
-  GmacPauseLowThresh1      = 0x00000010,     /*                            28 slot time                              */
-  GmacPauseLowThresh0      = 0x00000000,     /*                             4 slot time                       000    */
-
-  GmacUnicastPauseFrame    = 0x00000008,
-  GmacUnicastPauseFrameOn  = 0x00000008,     /* (UP)Detect pause frame with unicast addr.     3    RW                */
-  GmacUnicastPauseFrameOff = 0x00000000,     /* Detect only pause frame with multicast addr.                   0     */
-
-  GmacRxFlowControl       = 0x00000004,
-  GmacRxFlowControlEnable  = 0x00000004,     /* (RFE)Enable Rx flow control                   2    RW                */
-  GmacRxFlowControlDisable = 0x00000000,     /* Disable Rx flow control                                        0     */
-
-  GmacTxFlowControl          = 0x00000002,
-  GmacTxFlowControlEnable  = 0x00000002,     /* (TFE)Enable Tx flow control                   1    RW                */
-  GmacTxFlowControlDisable = 0x00000000,     /* Disable flow control                                           0     */
-
-  GmacFlowControlBackPressure= 0x00000001,
-  GmacSendPauseFrame       = 0x00000001,     /* (FCB/PBA)send pause frm/Apply back pressure   0    RW          0     */
+    GmacPauseLowThresh       = 0x00000030,
+    GmacPauseLowThresh3      = 0x00000030,     /* (PLT)thresh for pause tmr 256 slot time      5:4    RW               */
+    GmacPauseLowThresh2      = 0x00000020,     /*                           144 slot time                              */
+    GmacPauseLowThresh1      = 0x00000010,     /*                            28 slot time                              */
+    GmacPauseLowThresh0      = 0x00000000,     /*                             4 slot time                       000    */
+
+    GmacUnicastPauseFrame    = 0x00000008,
+    GmacUnicastPauseFrameOn  = 0x00000008,     /* (UP)Detect pause frame with unicast addr.     3    RW                */
+    GmacUnicastPauseFrameOff = 0x00000000,     /* Detect only pause frame with multicast addr.                   0     */
+
+    GmacRxFlowControl       = 0x00000004,
+    GmacRxFlowControlEnable  = 0x00000004,     /* (RFE)Enable Rx flow control                   2    RW                */
+    GmacRxFlowControlDisable = 0x00000000,     /* Disable Rx flow control                                        0     */
+
+    GmacTxFlowControl          = 0x00000002,
+    GmacTxFlowControlEnable  = 0x00000002,     /* (TFE)Enable Tx flow control                   1    RW                */
+    GmacTxFlowControlDisable = 0x00000000,     /* Disable flow control                                           0     */
+
+    GmacFlowControlBackPressure= 0x00000001,
+    GmacSendPauseFrame       = 0x00000001,     /* (FCB/PBA)send pause frm/Apply back pressure   0    RW          0     */
 };
 
 /*  GmacInterruptStatus      = 0x0038,     Mac Interrupt ststus register           */  
 enum GmacInterruptStatusBitDefinition
 {
-  GmacTSIntSts           = 0x00000200,    /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/
-  GmacMmcRxChksumOffload   = 0x00000080,    /* set if int generated in MMC RX CHECKSUM OFFLOAD int register                      */ 
-  GmacMmcTxIntSts       = 0x00000040,    /* set if int generated in MMC TX Int register               */
-  GmacMmcRxIntSts       = 0x00000020,    /* set if int generated in MMC RX Int register                */
-  GmacMmcIntSts           = 0x00000010,    /* set if any of the above bit [7:5] is set               */
-  GmacPmtIntSts           = 0x00000008,    /* set whenver magic pkt/wake-on-lan frame is received           */
-  GmacPcsAnComplete       = 0x00000004,    /* set when AN is complete in TBI/RTBI/SGMIII phy interface        */
-  GmacPcsLnkStsChange       = 0x00000002,    /* set if any lnk status change in TBI/RTBI/SGMII interface        */
-  GmacRgmiiIntSts       = 0x00000001,    /* set if any change in lnk status of RGMII interface           */
-
+    GmacTSIntSts             = 0x00000200,      /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/
+    GmacMmcRxChksumOffload   = 0x00000080,      /* set if int generated in MMC RX CHECKSUM OFFLOAD int register                      */ 
+    GmacMmcTxIntSts          = 0x00000040,      /* set if int generated in MMC TX Int register               */
+    GmacMmcRxIntSts          = 0x00000020,      /* set if int generated in MMC RX Int register                */
+    GmacMmcIntSts            = 0x00000010,      /* set if any of the above bit [7:5] is set               */
+    GmacPmtIntSts            = 0x00000008,      /* set whenver magic pkt/wake-on-lan frame is received           */
+    GmacPcsAnComplete        = 0x00000004,      /* set when AN is complete in TBI/RTBI/SGMIII phy interface        */
+    GmacPcsLnkStsChange      = 0x00000002,      /* set if any lnk status change in TBI/RTBI/SGMII interface        */
+    GmacRgmiiIntSts          = 0x00000001,      /* set if any change in lnk status of RGMII interface           */
 };
 
 /*  GmacInterruptMask       = 0x003C,     Mac Interrupt Mask register           */  
 enum GmacInterruptMaskBitDefinition
 {
-  GmacTSIntMask           = 0x00000200,    /* when set disables the time stamp interrupt generation            */
-  GmacPmtIntMask       = 0x00000008,    /* when set Disables the assertion of PMT interrupt                 */
-  GmacPcsAnIntMask       = 0x00000004,    /* When set disables the assertion of PCS AN complete interrupt              */
-  GmacPcsLnkStsIntMask       = 0x00000002,    /* when set disables the assertion of PCS lnk status change interrupt    */
-  GmacRgmiiIntMask       = 0x00000001,    /* when set disables the assertion of RGMII int             */
+    GmacTSIntMask              = 0x00000200,    /* when set disables the time stamp interrupt generation            */
+    GmacPmtIntMask             = 0x00000008,    /* when set Disables the assertion of PMT interrupt                 */
+    GmacPcsAnIntMask           = 0x00000004,    /* When set disables the assertion of PCS AN complete interrupt              */
+    GmacPcsLnkStsIntMask       = 0x00000002,    /* when set disables the assertion of PCS lnk status change interrupt    */
+    GmacRgmiiIntMask           = 0x00000001,    /* when set disables the assertion of RGMII int             */
 };
 
 /**********************************************************
@@ -591,22 +579,21 @@ enum GmacInterruptMaskBitDefinition
  * For Pci based system address is BARx + GmaDmaBase
  * For any other system translation is done accordingly
  **********************************************************/
-
 enum DmaRegisters             
 {
-  DmaBusMode        = 0x0000,    /* CSR0 - Bus Mode Register                          */
-  DmaTxPollDemand   = 0x0004,    /* CSR1 - Transmit Poll Demand Register              */
-  DmaRxPollDemand   = 0x0008,    /* CSR2 - Receive Poll Demand Register               */
-  DmaRxBaseAddr     = 0x000C,    /* CSR3 - Receive Descriptor list base address       */
-  DmaTxBaseAddr     = 0x0010,    /* CSR4 - Transmit Descriptor list base address      */
-  DmaStatus         = 0x0014,    /* CSR5 - Dma status Register                        */
-  DmaControl        = 0x0018,    /* CSR6 - Dma Operation Mode Register                */
-  DmaInterrupt      = 0x001C,    /* CSR7 - Interrupt enable                           */
-  DmaMissedFr       = 0x0020,    /* CSR8 - Missed Frame & Buffer overflow Counter     */
-  DmaTxCurrDesc     = 0x0048,    /*      - Current host Tx Desc Register              */ 
-  DmaRxCurrDesc     = 0x004C,    /*      - Current host Rx Desc Register              */ 
-  DmaTxCurrAddr     = 0x0050,    /* CSR20 - Current host transmit buffer address      */
-  DmaRxCurrAddr     = 0x0054,    /* CSR21 - Current host receive buffer address       */
+    DmaBusMode        = 0x0000,    /* CSR0 - Bus Mode Register                          */
+    DmaTxPollDemand   = 0x0004,    /* CSR1 - Transmit Poll Demand Register              */
+    DmaRxPollDemand   = 0x0008,    /* CSR2 - Receive Poll Demand Register               */
+    DmaRxBaseAddr     = 0x000C,    /* CSR3 - Receive Descriptor list base address       */
+    DmaTxBaseAddr     = 0x0010,    /* CSR4 - Transmit Descriptor list base address      */
+    DmaStatus         = 0x0014,    /* CSR5 - Dma status Register                        */
+    DmaControl        = 0x0018,    /* CSR6 - Dma Operation Mode Register                */
+    DmaInterrupt      = 0x001C,    /* CSR7 - Interrupt enable                           */
+    DmaMissedFr       = 0x0020,    /* CSR8 - Missed Frame & Buffer overflow Counter     */
+    DmaTxCurrDesc     = 0x0048,    /*      - Current host Tx Desc Register              */ 
+    DmaRxCurrDesc     = 0x004C,    /*      - Current host Rx Desc Register              */ 
+    DmaTxCurrAddr     = 0x0050,    /* CSR20 - Current host transmit buffer address      */
+    DmaRxCurrAddr     = 0x0054,    /* CSR21 - Current host receive buffer address       */
 };
 
 /**********************************************************
@@ -616,165 +603,164 @@ enum DmaRegisters
 /*DmaBusMode               = 0x0000,    CSR0 - Bus Mode */
 enum DmaBusModeReg         
 {                                         /* Bit description                                Bits     R/W   Reset value */
-  DmaFixedBurstEnable     = 0x00010000,   /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16   16     RW                */
-  DmaFixedBurstDisable    = 0x00000000,   /*             SINGLE, INCR                                          0       */
+    DmaFixedBurstEnable     = 0x00010000,   /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16   16     RW                */
+    DmaFixedBurstDisable    = 0x00000000,   /*             SINGLE, INCR                                          0       */
 
-  DmaTxPriorityRatio11    = 0x00000000,   /* (PR)TX:RX DMA priority ratio 1:1                15:14   RW        00      */ 
-  DmaTxPriorityRatio21    = 0x00004000,   /* (PR)TX:RX DMA priority ratio 2:1                                          */ 
-  DmaTxPriorityRatio31    = 0x00008000,   /* (PR)TX:RX DMA priority ratio 3:1                                          */ 
-  DmaTxPriorityRatio41    = 0x0000C000,   /* (PR)TX:RX DMA priority ratio 4:1                                          */ 
+    DmaTxPriorityRatio11    = 0x00000000,   /* (PR)TX:RX DMA priority ratio 1:1                15:14   RW        00      */ 
+    DmaTxPriorityRatio21    = 0x00004000,   /* (PR)TX:RX DMA priority ratio 2:1                                          */ 
+    DmaTxPriorityRatio31    = 0x00008000,   /* (PR)TX:RX DMA priority ratio 3:1                                          */ 
+    DmaTxPriorityRatio41    = 0x0000C000,   /* (PR)TX:RX DMA priority ratio 4:1                                          */ 
   
-  DmaBurstLengthx8        = 0x01000000,   /* When set mutiplies the PBL by 8                  24      RW        0      */ 
+    DmaBurstLengthx8        = 0x01000000,   /* When set mutiplies the PBL by 8                  24      RW        0      */ 
   
-  DmaBurstLength256       = 0x01002000,   /*(DmaBurstLengthx8 | DmaBurstLength32) = 256      [24]:13:8                 */  
-  DmaBurstLength128       = 0x01001000,   /*(DmaBurstLengthx8 | DmaBurstLength16) = 128      [24]:13:8                 */
-  DmaBurstLength64        = 0x01000800,   /*(DmaBurstLengthx8 | DmaBurstLength8) = 64        [24]:13:8                 */
-  DmaBurstLength32        = 0x00002000,   /* (PBL) programmable Dma burst length = 32        13:8    RW                */
-  DmaBurstLength16        = 0x00001000,   /* Dma burst length = 16                                                     */
-  DmaBurstLength8         = 0x00000800,   /* Dma burst length = 8                                                      */
-  DmaBurstLength4         = 0x00000400,   /* Dma burst length = 4                                                      */
-  DmaBurstLength2         = 0x00000200,   /* Dma burst length = 2                                                      */
-  DmaBurstLength1         = 0x00000100,   /* Dma burst length = 1                                                      */
-  DmaBurstLength0         = 0x00000000,   /* Dma burst length = 0                                               0x00   */
-
-  DmaDescriptor8Words     = 0x00000080,   /* Enh Descriptor works  1=> 8 word descriptor      7                  0    */
-  DmaDescriptor4Words     = 0x00000000,   /* Enh Descriptor works  0=> 4 word descriptor      7                  0    */
-
-  DmaDescriptorSkip16     = 0x00000040,   /* (DSL)Descriptor skip length (no.of dwords)       6:2     RW               */
-  DmaDescriptorSkip8      = 0x00000020,   /* between two unchained descriptors                                         */
-  DmaDescriptorSkip4      = 0x00000010,   /*                                                                           */
-  DmaDescriptorSkip2      = 0x00000008,   /*                                                                           */
-  DmaDescriptorSkip1      = 0x00000004,   /*                                                                           */
-  DmaDescriptorSkip0      = 0x00000000,   /*                                                                    0x00   */
-
-  DmaArbitRr              = 0x00000000,   /* (DA) DMA RR arbitration                            1     RW         0     */ 
-  DmaArbitPr              = 0x00000002,   /* Rx has priority over Tx                                                   */  
+    DmaBurstLength256       = 0x01002000,   /*(DmaBurstLengthx8 | DmaBurstLength32) = 256      [24]:13:8                 */  
+    DmaBurstLength128       = 0x01001000,   /*(DmaBurstLengthx8 | DmaBurstLength16) = 128      [24]:13:8                 */
+    DmaBurstLength64        = 0x01000800,   /*(DmaBurstLengthx8 | DmaBurstLength8) = 64        [24]:13:8                 */
+    DmaBurstLength32        = 0x00002000,   /* (PBL) programmable Dma burst length = 32        13:8    RW                */
+    DmaBurstLength16        = 0x00001000,   /* Dma burst length = 16                                                     */
+    DmaBurstLength8         = 0x00000800,   /* Dma burst length = 8                                                      */
+    DmaBurstLength4         = 0x00000400,   /* Dma burst length = 4                                                      */
+    DmaBurstLength2         = 0x00000200,   /* Dma burst length = 2                                                      */
+    DmaBurstLength1         = 0x00000100,   /* Dma burst length = 1                                                      */
+    DmaBurstLength0         = 0x00000000,   /* Dma burst length = 0                                               0x00   */
+
+    DmaDescriptor8Words     = 0x00000080,   /* Enh Descriptor works  1=> 8 word descriptor      7                  0    */
+    DmaDescriptor4Words     = 0x00000000,   /* Enh Descriptor works  0=> 4 word descriptor      7                  0    */
+
+    DmaDescriptorSkip16     = 0x00000040,   /* (DSL)Descriptor skip length (no.of dwords)       6:2     RW               */
+    DmaDescriptorSkip8      = 0x00000020,   /* between two unchained descriptors                                         */
+    DmaDescriptorSkip4      = 0x00000010,   /*                                                                           */
+    DmaDescriptorSkip2      = 0x00000008,   /*                                                                           */
+    DmaDescriptorSkip1      = 0x00000004,   /*                                                                           */
+    DmaDescriptorSkip0      = 0x00000000,   /*                                                                    0x00   */
+
+    DmaArbitRr              = 0x00000000,   /* (DA) DMA RR arbitration                            1     RW         0     */ 
+    DmaArbitPr              = 0x00000002,   /* Rx has priority over Tx                                                   */  
   
-  DmaResetOn              = 0x00000001,   /* (SWR)Software Reset DMA engine                     0     RW               */
-  DmaResetOff             = 0x00000000,   /*                                                                      0    */
+    DmaResetOn              = 0x00000001,   /* (SWR)Software Reset DMA engine                     0     RW               */
+    DmaResetOff             = 0x00000000,   /*                                                                      0    */
 };
 
-
 /*DmaStatus         = 0x0014,    CSR5 - Dma status Register                        */
 enum DmaStatusReg         
 { 
   /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/                      
-  GmacPmtIntr             = 0x10000000,   /* (GPI)Gmac subsystem interrupt                      28     RO       0       */ 
-  GmacMmcIntr             = 0x08000000,   /* (GMI)Gmac MMC subsystem interrupt                  27     RO       0       */ 
-  GmacLineIntfIntr        = 0x04000000,   /* Line interface interrupt                           26     RO       0       */
-
-  DmaErrorBit2            = 0x02000000,   /* (EB)Error bits 0-data buffer, 1-desc. access       25     RO       0       */
-  DmaErrorBit1            = 0x01000000,   /* (EB)Error bits 0-write trnsf, 1-read transfr       24     RO       0       */
-  DmaErrorBit0            = 0x00800000,   /* (EB)Error bits 0-Rx DMA, 1-Tx DMA                  23     RO       0       */
-
-  DmaTxState              = 0x00700000,   /* (TS)Transmit process state                         22:20  RO               */
-  DmaTxStopped            = 0x00000000,   /* Stopped - Reset or Stop Tx Command issued                         000      */
-  DmaTxFetching           = 0x00100000,   /* Running - fetching the Tx descriptor                                       */
-  DmaTxWaiting            = 0x00200000,   /* Running - waiting for status                                               */
-  DmaTxReading            = 0x00300000,   /* Running - reading the data from host memory                                */
-  DmaTxSuspended          = 0x00600000,   /* Suspended - Tx Descriptor unavailabe                                       */
-  DmaTxClosing            = 0x00700000,   /* Running - closing Rx descriptor                                            */
-
-  DmaRxState              = 0x000E0000,   /* (RS)Receive process state                         19:17  RO                */
-  DmaRxStopped            = 0x00000000,   /* Stopped - Reset or Stop Rx Command issued                         000      */
-  DmaRxFetching           = 0x00020000,   /* Running - fetching the Rx descriptor                                       */
-  DmaRxWaiting            = 0x00060000,   /* Running - waiting for packet                                               */
-  DmaRxSuspended          = 0x00080000,   /* Suspended - Rx Descriptor unavailable                                      */
-  DmaRxClosing            = 0x000A0000,   /* Running - closing descriptor                                               */
-  DmaRxQueuing            = 0x000E0000,   /* Running - queuing the recieve frame into host memory                       */
-
-  DmaIntNormal            = 0x00010000,   /* (NIS)Normal interrupt summary                     16     RW        0       */
-  DmaIntAbnormal          = 0x00008000,   /* (AIS)Abnormal interrupt summary                   15     RW        0       */
-
-  DmaIntEarlyRx           = 0x00004000,   /* Early receive interrupt (Normal)       RW        0       */
-  DmaIntBusError          = 0x00002000,   /* Fatal bus error (Abnormal)             RW        0       */
-  DmaIntEarlyTx           = 0x00000400,   /* Early transmit interrupt (Abnormal)    RW        0       */
-  DmaIntRxWdogTO          = 0x00000200,   /* Receive Watchdog Timeout (Abnormal)    RW        0       */
-  DmaIntRxStopped         = 0x00000100,   /* Receive process stopped (Abnormal)     RW        0       */
-  DmaIntRxNoBuffer        = 0x00000080,   /* Receive buffer unavailable (Abnormal)  RW        0       */
-  DmaIntRxCompleted       = 0x00000040,   /* Completion of frame reception (Normal) RW        0       */
-  DmaIntTxUnderflow       = 0x00000020,   /* Transmit underflow (Abnormal)          RW        0       */
-  DmaIntRcvOverflow       = 0x00000010,   /* Receive Buffer overflow interrupt      RW        0       */
-  DmaIntTxJabberTO        = 0x00000008,   /* Transmit Jabber Timeout (Abnormal)     RW        0       */
-  DmaIntTxNoBuffer        = 0x00000004,   /* Transmit buffer unavailable (Normal)   RW        0       */
-  DmaIntTxStopped         = 0x00000002,   /* Transmit process stopped (Abnormal)    RW        0       */
-  DmaIntTxCompleted       = 0x00000001,   /* Transmit completed (Normal)            RW        0       */
+    GmacPmtIntr             = 0x10000000,   /* (GPI)Gmac subsystem interrupt                      28     RO       0       */ 
+    GmacMmcIntr             = 0x08000000,   /* (GMI)Gmac MMC subsystem interrupt                  27     RO       0       */ 
+    GmacLineIntfIntr        = 0x04000000,   /* Line interface interrupt                           26     RO       0       */
+
+    DmaErrorBit2            = 0x02000000,   /* (EB)Error bits 0-data buffer, 1-desc. access       25     RO       0       */
+    DmaErrorBit1            = 0x01000000,   /* (EB)Error bits 0-write trnsf, 1-read transfr       24     RO       0       */
+    DmaErrorBit0            = 0x00800000,   /* (EB)Error bits 0-Rx DMA, 1-Tx DMA                  23     RO       0       */
+
+    DmaTxState              = 0x00700000,   /* (TS)Transmit process state                         22:20  RO               */
+    DmaTxStopped            = 0x00000000,   /* Stopped - Reset or Stop Tx Command issued                         000      */
+    DmaTxFetching           = 0x00100000,   /* Running - fetching the Tx descriptor                                       */
+    DmaTxWaiting            = 0x00200000,   /* Running - waiting for status                                               */
+    DmaTxReading            = 0x00300000,   /* Running - reading the data from host memory                                */
+    DmaTxSuspended          = 0x00600000,   /* Suspended - Tx Descriptor unavailabe                                       */
+    DmaTxClosing            = 0x00700000,   /* Running - closing Rx descriptor                                            */
+
+    DmaRxState              = 0x000E0000,   /* (RS)Receive process state                         19:17  RO                */
+    DmaRxStopped            = 0x00000000,   /* Stopped - Reset or Stop Rx Command issued                         000      */
+    DmaRxFetching           = 0x00020000,   /* Running - fetching the Rx descriptor                                       */
+    DmaRxWaiting            = 0x00060000,   /* Running - waiting for packet                                               */
+    DmaRxSuspended          = 0x00080000,   /* Suspended - Rx Descriptor unavailable                                      */
+    DmaRxClosing            = 0x000A0000,   /* Running - closing descriptor                                               */
+    DmaRxQueuing            = 0x000E0000,   /* Running - queuing the recieve frame into host memory                       */
+
+    DmaIntNormal            = 0x00010000,   /* (NIS)Normal interrupt summary                     16     RW        0       */
+    DmaIntAbnormal          = 0x00008000,   /* (AIS)Abnormal interrupt summary                   15     RW        0       */
+
+    DmaIntEarlyRx           = 0x00004000,   /* Early receive interrupt (Normal)       RW        0       */
+    DmaIntBusError          = 0x00002000,   /* Fatal bus error (Abnormal)             RW        0       */
+    DmaIntEarlyTx           = 0x00000400,   /* Early transmit interrupt (Abnormal)    RW        0       */
+    DmaIntRxWdogTO          = 0x00000200,   /* Receive Watchdog Timeout (Abnormal)    RW        0       */
+    DmaIntRxStopped         = 0x00000100,   /* Receive process stopped (Abnormal)     RW        0       */
+    DmaIntRxNoBuffer        = 0x00000080,   /* Receive buffer unavailable (Abnormal)  RW        0       */
+    DmaIntRxCompleted       = 0x00000040,   /* Completion of frame reception (Normal) RW        0       */
+    DmaIntTxUnderflow       = 0x00000020,   /* Transmit underflow (Abnormal)          RW        0       */
+    DmaIntRcvOverflow       = 0x00000010,   /* Receive Buffer overflow interrupt      RW        0       */
+    DmaIntTxJabberTO        = 0x00000008,   /* Transmit Jabber Timeout (Abnormal)     RW        0       */
+    DmaIntTxNoBuffer        = 0x00000004,   /* Transmit buffer unavailable (Normal)   RW        0       */
+    DmaIntTxStopped         = 0x00000002,   /* Transmit process stopped (Abnormal)    RW        0       */
+    DmaIntTxCompleted       = 0x00000001,   /* Transmit completed (Normal)            RW        0       */
 };
 
 /*DmaControl        = 0x0018,     CSR6 - Dma Operation Mode Register                */
 enum DmaControlReg        
 { 
-  DmaDisableDropTcpCs      = 0x04000000,   /* (DT) Dis. drop. of tcp/ip CS error frames        26      RW        0       */
+    DmaDisableDropTcpCs      = 0x04000000,   /* (DT) Dis. drop. of tcp/ip CS error frames        26      RW        0       */
                                         
-  DmaStoreAndForward      = 0x02200000,   /* (SF)Store and forward                            21      RW        0       */
-  DmaFlushTxFifo          = 0x00100000,   /* (FTF)Tx FIFO controller is reset to default      20      RW        0       */ 
+    DmaStoreAndForward      = 0x02200000,   /* (SF)Store and forward                            21      RW        0       */
+    DmaFlushTxFifo          = 0x00100000,   /* (FTF)Tx FIFO controller is reset to default      20      RW        0       */ 
   
-  DmaTxThreshCtrl         = 0x0001C000,   /* (TTC)Controls thre Threh of MTL tx Fifo          16:14   RW                */ 
-  DmaTxThreshCtrl16       = 0x0001C000,   /* (TTC)Controls thre Threh of MTL tx Fifo 16       16:14   RW                */ 
-  DmaTxThreshCtrl24       = 0x00018000,   /* (TTC)Controls thre Threh of MTL tx Fifo 24       16:14   RW                */ 
-  DmaTxThreshCtrl32       = 0x00014000,   /* (TTC)Controls thre Threh of MTL tx Fifo 32       16:14   RW                */ 
-  DmaTxThreshCtrl40       = 0x00010000,   /* (TTC)Controls thre Threh of MTL tx Fifo 40       16:14   RW                */   
-  DmaTxThreshCtrl256      = 0x0000c000,   /* (TTC)Controls thre Threh of MTL tx Fifo 256      16:14   RW                */   
-  DmaTxThreshCtrl192      = 0x00008000,   /* (TTC)Controls thre Threh of MTL tx Fifo 192      16:14   RW                */   
-  DmaTxThreshCtrl128      = 0x00004000,   /* (TTC)Controls thre Threh of MTL tx Fifo 128      16:14   RW                */   
-  DmaTxThreshCtrl64       = 0x00000000,   /* (TTC)Controls thre Threh of MTL tx Fifo 64       16:14   RW        000     */ 
+    DmaTxThreshCtrl         = 0x0001C000,   /* (TTC)Controls thre Threh of MTL tx Fifo          16:14   RW                */ 
+    DmaTxThreshCtrl16       = 0x0001C000,   /* (TTC)Controls thre Threh of MTL tx Fifo 16       16:14   RW                */ 
+    DmaTxThreshCtrl24       = 0x00018000,   /* (TTC)Controls thre Threh of MTL tx Fifo 24       16:14   RW                */ 
+    DmaTxThreshCtrl32       = 0x00014000,   /* (TTC)Controls thre Threh of MTL tx Fifo 32       16:14   RW                */ 
+    DmaTxThreshCtrl40       = 0x00010000,   /* (TTC)Controls thre Threh of MTL tx Fifo 40       16:14   RW                */   
+    DmaTxThreshCtrl256      = 0x0000c000,   /* (TTC)Controls thre Threh of MTL tx Fifo 256      16:14   RW                */   
+    DmaTxThreshCtrl192      = 0x00008000,   /* (TTC)Controls thre Threh of MTL tx Fifo 192      16:14   RW                */   
+    DmaTxThreshCtrl128      = 0x00004000,   /* (TTC)Controls thre Threh of MTL tx Fifo 128      16:14   RW                */   
+    DmaTxThreshCtrl64       = 0x00000000,   /* (TTC)Controls thre Threh of MTL tx Fifo 64       16:14   RW        000     */ 
   
-  DmaTxStart              = 0x00002000,   /* (ST)Start/Stop transmission                      13      RW        0       */
-
-  DmaRxFlowCtrlDeact      = 0x00401800,   /* (RFD)Rx flow control deact. threhold             [22]:12:11   RW                 */ 
-  DmaRxFlowCtrlDeact1K    = 0x00000000,   /* (RFD)Rx flow control deact. threhold (1kbytes)   [22]:12:11   RW        00       */ 
-  DmaRxFlowCtrlDeact2K    = 0x00000800,   /* (RFD)Rx flow control deact. threhold (2kbytes)   [22]:12:11   RW                 */ 
-  DmaRxFlowCtrlDeact3K    = 0x00001000,   /* (RFD)Rx flow control deact. threhold (3kbytes)   [22]:12:11   RW                 */ 
-  DmaRxFlowCtrlDeact4K    = 0x00001800,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */     
-  DmaRxFlowCtrlDeact5K    = 0x00400000,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */     
-  DmaRxFlowCtrlDeact6K    = 0x00400800,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */     
-  DmaRxFlowCtrlDeact7K    = 0x00401000,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */     
+    DmaTxStart              = 0x00002000,   /* (ST)Start/Stop transmission                      13      RW        0       */
+
+    DmaRxFlowCtrlDeact      = 0x00401800,   /* (RFD)Rx flow control deact. threhold             [22]:12:11   RW                 */ 
+    DmaRxFlowCtrlDeact1K    = 0x00000000,   /* (RFD)Rx flow control deact. threhold (1kbytes)   [22]:12:11   RW        00       */ 
+    DmaRxFlowCtrlDeact2K    = 0x00000800,   /* (RFD)Rx flow control deact. threhold (2kbytes)   [22]:12:11   RW                 */ 
+    DmaRxFlowCtrlDeact3K    = 0x00001000,   /* (RFD)Rx flow control deact. threhold (3kbytes)   [22]:12:11   RW                 */ 
+    DmaRxFlowCtrlDeact4K    = 0x00001800,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */     
+    DmaRxFlowCtrlDeact5K    = 0x00400000,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */     
+    DmaRxFlowCtrlDeact6K    = 0x00400800,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */     
+    DmaRxFlowCtrlDeact7K    = 0x00401000,   /* (RFD)Rx flow control deact. threhold (4kbytes)   [22]:12:11   RW                 */     
   
-  DmaRxFlowCtrlAct        = 0x00800600,   /* (RFA)Rx flow control Act. threhold              [23]:10:09   RW                 */ 
-  DmaRxFlowCtrlAct1K      = 0x00000000,   /* (RFA)Rx flow control Act. threhold (1kbytes)    [23]:10:09   RW        00       */ 
-  DmaRxFlowCtrlAct2K      = 0x00000200,   /* (RFA)Rx flow control Act. threhold (2kbytes)    [23]:10:09   RW                 */ 
-  DmaRxFlowCtrlAct3K      = 0x00000400,   /* (RFA)Rx flow control Act. threhold (3kbytes)    [23]:10:09   RW                 */ 
-  DmaRxFlowCtrlAct4K      = 0x00000600,   /* (RFA)Rx flow control Act. threhold (4kbytes)    [23]:10:09   RW                 */     
-  DmaRxFlowCtrlAct5K      = 0x00800000,   /* (RFA)Rx flow control Act. threhold (5kbytes)    [23]:10:09   RW                 */     
-  DmaRxFlowCtrlAct6K      = 0x00800200,   /* (RFA)Rx flow control Act. threhold (6kbytes)    [23]:10:09   RW                 */     
-  DmaRxFlowCtrlAct7K      = 0x00800400,   /* (RFA)Rx flow control Act. threhold (7kbytes)    [23]:10:09   RW                 */     
+    DmaRxFlowCtrlAct        = 0x00800600,   /* (RFA)Rx flow control Act. threhold              [23]:10:09   RW                 */ 
+    DmaRxFlowCtrlAct1K      = 0x00000000,   /* (RFA)Rx flow control Act. threhold (1kbytes)    [23]:10:09   RW        00       */ 
+    DmaRxFlowCtrlAct2K      = 0x00000200,   /* (RFA)Rx flow control Act. threhold (2kbytes)    [23]:10:09   RW                 */ 
+    DmaRxFlowCtrlAct3K      = 0x00000400,   /* (RFA)Rx flow control Act. threhold (3kbytes)    [23]:10:09   RW                 */ 
+    DmaRxFlowCtrlAct4K      = 0x00000600,   /* (RFA)Rx flow control Act. threhold (4kbytes)    [23]:10:09   RW                 */     
+    DmaRxFlowCtrlAct5K      = 0x00800000,   /* (RFA)Rx flow control Act. threhold (5kbytes)    [23]:10:09   RW                 */     
+    DmaRxFlowCtrlAct6K      = 0x00800200,   /* (RFA)Rx flow control Act. threhold (6kbytes)    [23]:10:09   RW                 */     
+    DmaRxFlowCtrlAct7K      = 0x00800400,   /* (RFA)Rx flow control Act. threhold (7kbytes)    [23]:10:09   RW                 */     
   
-  DmaRxThreshCtrl         = 0x00000018,   /* (RTC)Controls thre Threh of MTL rx Fifo          4:3   RW                */ 
-  DmaRxThreshCtrl64       = 0x00000000,   /* (RTC)Controls thre Threh of MTL tx Fifo 64       4:3   RW                */ 
-  DmaRxThreshCtrl32       = 0x00000008,   /* (RTC)Controls thre Threh of MTL tx Fifo 32       4:3   RW                */ 
-  DmaRxThreshCtrl96       = 0x00000010,   /* (RTC)Controls thre Threh of MTL tx Fifo 96       4:3   RW                */ 
-  DmaRxThreshCtrl128      = 0x00000018,   /* (RTC)Controls thre Threh of MTL tx Fifo 128      4:3   RW                */ 
-
-  DmaEnHwFlowCtrl         = 0x00000100,   /* (EFC)Enable HW flow control                      8       RW                 */ 
-  DmaDisHwFlowCtrl        = 0x00000000,   /* Disable HW flow control                                            0        */ 
+    DmaRxThreshCtrl         = 0x00000018,   /* (RTC)Controls thre Threh of MTL rx Fifo          4:3   RW                */ 
+    DmaRxThreshCtrl64       = 0x00000000,   /* (RTC)Controls thre Threh of MTL tx Fifo 64       4:3   RW                */ 
+    DmaRxThreshCtrl32       = 0x00000008,   /* (RTC)Controls thre Threh of MTL tx Fifo 32       4:3   RW                */ 
+    DmaRxThreshCtrl96       = 0x00000010,   /* (RTC)Controls thre Threh of MTL tx Fifo 96       4:3   RW                */ 
+    DmaRxThreshCtrl128      = 0x00000018,   /* (RTC)Controls thre Threh of MTL tx Fifo 128      4:3   RW                */ 
+
+    DmaEnHwFlowCtrl         = 0x00000100,   /* (EFC)Enable HW flow control                      8       RW                 */ 
+    DmaDisHwFlowCtrl        = 0x00000000,   /* Disable HW flow control                                            0        */ 
         
-  DmaFwdErrorFrames       = 0x00000080,   /* (FEF)Forward error frames                        7       RW        0       */
-  DmaFwdUnderSzFrames     = 0x00000040,   /* (FUF)Forward undersize frames                    6       RW        0       */
-  DmaTxSecondFrame        = 0x00000004,   /* (OSF)Operate on second frame                     4       RW        0       */
-  DmaRxStart              = 0x00000002,   /* (SR)Start/Stop reception                         1       RW        0       */
+    DmaFwdErrorFrames       = 0x00000080,   /* (FEF)Forward error frames                        7       RW        0       */
+    DmaFwdUnderSzFrames     = 0x00000040,   /* (FUF)Forward undersize frames                    6       RW        0       */
+    DmaTxSecondFrame        = 0x00000004,   /* (OSF)Operate on second frame                     4       RW        0       */
+    DmaRxStart              = 0x00000002,   /* (SR)Start/Stop reception                         1       RW        0       */
 };
 
 
 /*DmaInterrupt      = 0x001C,    CSR7 - Interrupt enable Register Layout     */
 enum  DmaInterruptReg
 {                     
-  DmaIeNormal            = DmaIntNormal     ,   /* Normal interrupt enable                 RW        0       */
-  DmaIeAbnormal          = DmaIntAbnormal   ,   /* Abnormal interrupt enable               RW        0       */
-
-  DmaIeEarlyRx           = DmaIntEarlyRx    ,   /* Early receive interrupt enable          RW        0       */
-  DmaIeBusError          = DmaIntBusError   ,   /* Fatal bus error enable                  RW        0       */
-  DmaIeEarlyTx           = DmaIntEarlyTx    ,   /* Early transmit interrupt enable         RW        0       */
-  DmaIeRxWdogTO          = DmaIntRxWdogTO   ,   /* Receive Watchdog Timeout enable         RW        0       */
-  DmaIeRxStopped         = DmaIntRxStopped  ,   /* Receive process stopped enable          RW        0       */
-  DmaIeRxNoBuffer        = DmaIntRxNoBuffer ,   /* Receive buffer unavailable enable       RW        0       */
-  DmaIeRxCompleted       = DmaIntRxCompleted,   /* Completion of frame reception enable    RW        0       */
-  DmaIeTxUnderflow       = DmaIntTxUnderflow,   /* Transmit underflow enable               RW        0       */
-
-  DmaIeRxOverflow        = DmaIntRcvOverflow,   /* Receive Buffer overflow interrupt       RW        0       */
-  DmaIeTxJabberTO        = DmaIntTxJabberTO ,   /* Transmit Jabber Timeout enable          RW        0       */
-  DmaIeTxNoBuffer        = DmaIntTxNoBuffer ,   /* Transmit buffer unavailable enable      RW        0       */
-  DmaIeTxStopped         = DmaIntTxStopped  ,   /* Transmit process stopped enable         RW        0       */
-  DmaIeTxCompleted       = DmaIntTxCompleted,   /* Transmit completed enable               RW        0       */
+    DmaIeNormal            = DmaIntNormal     ,   /* Normal interrupt enable                 RW        0       */
+    DmaIeAbnormal          = DmaIntAbnormal   ,   /* Abnormal interrupt enable               RW        0       */
+
+    DmaIeEarlyRx           = DmaIntEarlyRx    ,   /* Early receive interrupt enable          RW        0       */
+    DmaIeBusError          = DmaIntBusError   ,   /* Fatal bus error enable                  RW        0       */
+    DmaIeEarlyTx           = DmaIntEarlyTx    ,   /* Early transmit interrupt enable         RW        0       */
+    DmaIeRxWdogTO          = DmaIntRxWdogTO   ,   /* Receive Watchdog Timeout enable         RW        0       */
+    DmaIeRxStopped         = DmaIntRxStopped  ,   /* Receive process stopped enable          RW        0       */
+    DmaIeRxNoBuffer        = DmaIntRxNoBuffer ,   /* Receive buffer unavailable enable       RW        0       */
+    DmaIeRxCompleted       = DmaIntRxCompleted,   /* Completion of frame reception enable    RW        0       */
+    DmaIeTxUnderflow       = DmaIntTxUnderflow,   /* Transmit underflow enable               RW        0       */
+
+    DmaIeRxOverflow        = DmaIntRcvOverflow,   /* Receive Buffer overflow interrupt       RW        0       */
+    DmaIeTxJabberTO        = DmaIntTxJabberTO ,   /* Transmit Jabber Timeout enable          RW        0       */
+    DmaIeTxNoBuffer        = DmaIntTxNoBuffer ,   /* Transmit buffer unavailable enable      RW        0       */
+    DmaIeTxStopped         = DmaIntTxStopped  ,   /* Transmit process stopped enable         RW        0       */
+    DmaIeTxCompleted       = DmaIntTxCompleted,   /* Transmit completed enable               RW        0       */
 };
 
 
@@ -818,126 +804,119 @@ DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format
 
 enum DmaDescriptorStatus    /* status word of DMA descriptor */
 {
-  DescOwnByDma          = 0x80000000,   /* (OWN)Descriptor is owned by DMA engine              31      RW                  */
+    DescOwnByDma          = 0x80000000,   /* (OWN)Descriptor is owned by DMA engine              31      RW                  */
 
-  DescDAFilterFail      = 0x40000000,   /* (AFM)Rx - DA Filter Fail for the rx frame           30                          */
+    DescDAFilterFail      = 0x40000000,   /* (AFM)Rx - DA Filter Fail for the rx frame           30                          */
   
-  DescFrameLengthMask   = 0x3FFF0000,   /* (FL)Receive descriptor frame length                 29:16                       */
-  DescFrameLengthShift  = 16,
+    DescFrameLengthMask   = 0x3FFF0000,   /* (FL)Receive descriptor frame length                 29:16                       */
+    DescFrameLengthShift  = 16,
 
-  DescError             = 0x00008000,   /* (ES)Error summary bit  - OR of the follo. bits:     15                          */
+    DescError             = 0x00008000,   /* (ES)Error summary bit  - OR of the follo. bits:     15                          */
                     /*  DE || OE || IPC || LC || RWT || RE || CE */
-  DescRxTruncated       = 0x00004000,   /* (DE)Rx - no more descriptors for receive frame      14                          */
-  DescSAFilterFail      = 0x00002000,   /* (SAF)Rx - SA Filter Fail for the received frame     13                          */
-  DescRxLengthError    = 0x00001000,   /* (LE)Rx - frm size not matching with len field       12                          */
-  DescRxDamaged         = 0x00000800,   /* (OE)Rx - frm was damaged due to buffer overflow     11                          */
-  DescRxVLANTag         = 0x00000400,   /* (VLAN)Rx - received frame is a VLAN frame           10                          */
-  DescRxFirst           = 0x00000200,   /* (FS)Rx - first descriptor of the frame              9                          */
-  DescRxLast            = 0x00000100,   /* (LS)Rx - last descriptor of the frame               8                          */
-  DescRxLongFrame       = 0x00000080,   /* (Giant Frame)Rx - frame is longer than 1518/1522    7                          */
-  DescRxCollision       = 0x00000040,   /* (LC)Rx - late collision occurred during reception   6                          */
-  DescRxFrameEther      = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
-  DescRxWatchdog        = 0x00000010,   /* (RWT)Rx - watchdog timer expired during reception   4                          */
-  DescRxMiiError        = 0x00000008,   /* (RE)Rx - error reported by MII interface            3                          */
-  DescRxDribbling       = 0x00000004,   /* (DE)Rx - frame contains non int multiple of 8 bits  2                          */
-  DescRxCrc             = 0x00000002,   /* (CE)Rx - CRC error                                  1                          */
+    DescRxTruncated       = 0x00004000,   /* (DE)Rx - no more descriptors for receive frame      14                          */
+    DescSAFilterFail      = 0x00002000,   /* (SAF)Rx - SA Filter Fail for the received frame     13                          */
+    DescRxLengthError    = 0x00001000,   /* (LE)Rx - frm size not matching with len field       12                          */
+    DescRxDamaged         = 0x00000800,   /* (OE)Rx - frm was damaged due to buffer overflow     11                          */
+    DescRxVLANTag         = 0x00000400,   /* (VLAN)Rx - received frame is a VLAN frame           10                          */
+    DescRxFirst           = 0x00000200,   /* (FS)Rx - first descriptor of the frame              9                          */
+    DescRxLast            = 0x00000100,   /* (LS)Rx - last descriptor of the frame               8                          */
+    DescRxLongFrame       = 0x00000080,   /* (Giant Frame)Rx - frame is longer than 1518/1522    7                          */
+    DescRxCollision       = 0x00000040,   /* (LC)Rx - late collision occurred during reception   6                          */
+    DescRxFrameEther      = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
+    DescRxWatchdog        = 0x00000010,   /* (RWT)Rx - watchdog timer expired during reception   4                          */
+    DescRxMiiError        = 0x00000008,   /* (RE)Rx - error reported by MII interface            3                          */
+    DescRxDribbling       = 0x00000004,   /* (DE)Rx - frame contains non int multiple of 8 bits  2                          */
+    DescRxCrc             = 0x00000002,   /* (CE)Rx - CRC error                                  1                          */
 //  DescRxMacMatch        = 0x00000001,   /* (RX MAC Address) Rx mac address reg(1 to 15)match   0                          */ 
 
-  DescRxEXTsts          = 0x00000001,   /* Extended Status Available (RDES4)                           0                          */ 
+    DescRxEXTsts          = 0x00000001,   /* Extended Status Available (RDES4)                           0                          */ 
   
-  DescTxIntEnable       = 0x40000000,   /* (IC)Tx - interrupt on completion                    30                       */
-  DescTxLast            = 0x20000000,   /* (LS)Tx - Last segment of the frame                  29                       */
-  DescTxFirst           = 0x10000000,   /* (FS)Tx - First segment of the frame                 28                       */
-  DescTxDisableCrc      = 0x08000000,   /* (DC)Tx - Add CRC disabled (first segment only)      27                       */
-  DescTxDisablePadd    = 0x04000000,   /* (DP)disable padding, added by - reyaz               26                       */
-
-  DescTxCisMask      = 0x00c00000,   /* Tx checksum offloading control mask               23:22            */
-  DescTxCisBypass    = 0x00000000,   /* Checksum bypass                                */
-  DescTxCisIpv4HdrCs    = 0x00400000,    /* IPv4 header checksum                                */
-  DescTxCisTcpOnlyCs    = 0x00800000,    /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present    */
-  DescTxCisTcpPseudoCs  = 0x00c00000,    /* TCP/UDP/ICMP checksum fully in hardware including pseudo header        */
-
-  TxDescEndOfRing       = 0x00200000,   /* (TER)End of descriptors ring                        21                       */
-  TxDescChain           = 0x00100000,   /* (TCH)Second buffer address is chain address         20                       */
+    DescTxIntEnable       = 0x40000000,   /* (IC)Tx - interrupt on completion                    30                       */
+    DescTxLast            = 0x20000000,   /* (LS)Tx - Last segment of the frame                  29                       */
+    DescTxFirst           = 0x10000000,   /* (FS)Tx - First segment of the frame                 28                       */
+    DescTxDisableCrc      = 0x08000000,   /* (DC)Tx - Add CRC disabled (first segment only)      27                       */
+    DescTxDisablePadd     = 0x04000000,   /* (DP)disable padding, added by - reyaz               26                       */
+
+    DescTxCisMask         = 0x00c00000,   /* Tx checksum offloading control mask               23:22            */
+    DescTxCisBypass       = 0x00000000,   /* Checksum bypass                                */
+    DescTxCisIpv4HdrCs    = 0x00400000,    /* IPv4 header checksum                                */
+    DescTxCisTcpOnlyCs    = 0x00800000,    /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present    */
+    DescTxCisTcpPseudoCs  = 0x00c00000,    /* TCP/UDP/ICMP checksum fully in hardware including pseudo header        */
+
+    TxDescEndOfRing       = 0x00200000,   /* (TER)End of descriptors ring                        21                       */
+    TxDescChain           = 0x00100000,   /* (TCH)Second buffer address is chain address         20                       */
   
-  DescRxChkBit0        = 0x00000001,   /*()  Rx - Rx Payload Checksum Error                   0                          */
-  DescRxChkBit7        = 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error       7                          */
-  DescRxChkBit5        = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
+    DescRxChkBit0         = 0x00000001,   /*()  Rx - Rx Payload Checksum Error                   0                          */
+    DescRxChkBit7         = 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error       7                          */
+    DescRxChkBit5         = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
   
-  DescRxTSavail         = 0x00000080,   /* Time stamp available                                7                          */  
-  DescRxFrameType    = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
-
-  DescTxIpv4ChkError    = 0x00010000,   /* (IHE) Tx Ip header error                            16                         */
-  DescTxTimeout         = 0x00004000,   /* (JT)Tx - Transmit jabber timeout                    14                         */
-  DescTxFrameFlushed    = 0x00002000,   /* (FF)Tx - DMA/MTL flushed the frame due to SW flush  13                         */
-  DescTxPayChkError     = 0x00001000,   /* (PCE) Tx Payload checksum Error                     12                         */
-  DescTxLostCarrier     = 0x00000800,   /* (LC)Tx - carrier lost during tramsmission           11                         */
-  DescTxNoCarrier       = 0x00000400,   /* (NC)Tx - no carrier signal from the tranceiver      10                         */
-  DescTxLateCollision   = 0x00000200,   /* (LC)Tx - transmission aborted due to collision      9                         */
-  DescTxExcCollisions   = 0x00000100,   /* (EC)Tx - transmission aborted after 16 collisions   8                         */
-  DescTxVLANFrame       = 0x00000080,   /* (VF)Tx - VLAN-type frame                            7                         */
+    DescRxTSavail         = 0x00000080,   /* Time stamp available                                7                          */  
+    DescRxFrameType       = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3     5                          */
+
+    DescTxIpv4ChkError    = 0x00010000,   /* (IHE) Tx Ip header error                            16                         */
+    DescTxTimeout         = 0x00004000,   /* (JT)Tx - Transmit jabber timeout                    14                         */
+    DescTxFrameFlushed    = 0x00002000,   /* (FF)Tx - DMA/MTL flushed the frame due to SW flush  13                         */
+    DescTxPayChkError     = 0x00001000,   /* (PCE) Tx Payload checksum Error                     12                         */
+    DescTxLostCarrier     = 0x00000800,   /* (LC)Tx - carrier lost during tramsmission           11                         */
+    DescTxNoCarrier       = 0x00000400,   /* (NC)Tx - no carrier signal from the tranceiver      10                         */
+    DescTxLateCollision   = 0x00000200,   /* (LC)Tx - transmission aborted due to collision      9                         */
+    DescTxExcCollisions   = 0x00000100,   /* (EC)Tx - transmission aborted after 16 collisions   8                         */
+    DescTxVLANFrame       = 0x00000080,   /* (VF)Tx - VLAN-type frame                            7                         */
  
-  DescTxCollMask        = 0x00000078,   /* (CC)Tx - Collision count                            6:3                        */
-  DescTxCollShift       = 3,
+    DescTxCollMask        = 0x00000078,   /* (CC)Tx - Collision count                            6:3                        */
+    DescTxCollShift       = 3,
   
-  DescTxExcDeferral     = 0x00000004,   /* (ED)Tx - excessive deferral                         2                        */
-  DescTxUnderflow       = 0x00000002,   /* (UF)Tx - late data arrival from the memory          1                        */
-  DescTxDeferred        = 0x00000001,   /* (DB)Tx - frame transmision deferred                 0                        */
-
+    DescTxExcDeferral     = 0x00000004,   /* (ED)Tx - excessive deferral                         2                        */
+    DescTxUnderflow       = 0x00000002,   /* (UF)Tx - late data arrival from the memory          1                        */
+    DescTxDeferred        = 0x00000001,   /* (DB)Tx - frame transmision deferred                 0                        */
     /*
     This explains the RDES1/TDES1 bits layout
               --------------------------------------------------------------------
         RDES1/TDES1  | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1          |
               --------------------------------------------------------------------
-
     */
 // DmaDescriptorLength     length word of DMA descriptor 
-
-
-  RxDisIntCompl        = 0x80000000,    /* (Disable Rx int on completion)             31            */
-  RxDescEndOfRing       = 0x00008000,   /* (TER)End of descriptors ring                         15                       */
-  RxDescChain           = 0x00004000,   /* (TCH)Second buffer address is chain address          14                       */
-
-
-  DescSize2Mask         = 0x1FFF0000,   /* (TBS2) Buffer 2 size                                28:16                    */
-  DescSize2Shift        = 16,
-  DescSize1Mask         = 0x00001FFF,   /* (TBS1) Buffer 1 size                                12:0                     */
-  DescSize1Shift        = 0,
-
-
+    RxDisIntCompl        = 0x80000000,    /* (Disable Rx int on completion)             31            */
+    RxDescEndOfRing       = 0x00008000,   /* (TER)End of descriptors ring                         15                       */
+    RxDescChain           = 0x00004000,   /* (TCH)Second buffer address is chain address          14                       */
+
+    DescSize2Mask         = 0x1FFF0000,   /* (TBS2) Buffer 2 size                                28:16                    */
+    DescSize2Shift        = 16,
+    DescSize1Mask         = 0x00001FFF,   /* (TBS1) Buffer 1 size                                12:0                     */
+    DescSize1Shift        = 0,
     /*
     This explains the RDES4 Extended Status bits layout
               --------------------------------------------------------------------
         RDES4        |                             Extended Status                        |
               --------------------------------------------------------------------
     */
-  DescRxPtpAvail        = 0x00004000,    /* PTP snapshot available                              14                        */
-  DescRxPtpVer          = 0x00002000,    /* When set indicates IEEE1584 Version 2 (else Ver1)   13                        */
-  DescRxPtpFrameType    = 0x00001000,    /* PTP frame type Indicates PTP sent over ethernet     12                        */
-  DescRxPtpMessageType  = 0x00000F00,    /* Message Type                                        11:8                      */
-  DescRxPtpNo           = 0x00000000,    /* 0000 => No PTP message received                                               */
-  DescRxPtpSync         = 0x00000100,    /* 0001 => Sync (all clock types) received                                       */
-  DescRxPtpFollowUp     = 0x00000200,    /* 0010 => Follow_Up (all clock types) received                                  */
-  DescRxPtpDelayReq     = 0x00000300,    /* 0011 => Delay_Req (all clock types) received                                  */
-  DescRxPtpDelayResp    = 0x00000400,    /* 0100 => Delay_Resp (all clock types) received                                 */
-  DescRxPtpPdelayReq    = 0x00000500,    /* 0101 => Pdelay_Req (in P to P tras clk)  or Announce in Ord and Bound clk     */
-  DescRxPtpPdelayResp   = 0x00000600,    /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk   */
-  DescRxPtpPdelayRespFP = 0x00000700,    /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk   */
-  DescRxPtpIPV6         = 0x00000080,    /* Received Packet is  in IPV6 Packet                  7                         */
-  DescRxPtpIPV4         = 0x00000040,    /* Received Packet is  in IPV4 Packet                  6                         */
+    DescRxPtpAvail        = 0x00004000,    /* PTP snapshot available                              14                        */
+    DescRxPtpVer          = 0x00002000,    /* When set indicates IEEE1584 Version 2 (else Ver1)   13                        */
+    DescRxPtpFrameType    = 0x00001000,    /* PTP frame type Indicates PTP sent over ethernet     12                        */
+    DescRxPtpMessageType  = 0x00000F00,    /* Message Type                                        11:8                      */
+    DescRxPtpNo           = 0x00000000,    /* 0000 => No PTP message received                                               */
+    DescRxPtpSync         = 0x00000100,    /* 0001 => Sync (all clock types) received                                       */
+    DescRxPtpFollowUp     = 0x00000200,    /* 0010 => Follow_Up (all clock types) received                                  */
+    DescRxPtpDelayReq     = 0x00000300,    /* 0011 => Delay_Req (all clock types) received                                  */
+    DescRxPtpDelayResp    = 0x00000400,    /* 0100 => Delay_Resp (all clock types) received                                 */
+    DescRxPtpPdelayReq    = 0x00000500,    /* 0101 => Pdelay_Req (in P to P tras clk)  or Announce in Ord and Bound clk     */
+    DescRxPtpPdelayResp   = 0x00000600,    /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk   */
+    DescRxPtpPdelayRespFP = 0x00000700,    /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk   */
+    DescRxPtpIPV6         = 0x00000080,    /* Received Packet is  in IPV6 Packet                  7                         */
+    DescRxPtpIPV4         = 0x00000040,    /* Received Packet is  in IPV4 Packet                  6                         */
  
-  DescRxChkSumBypass    = 0x00000020,    /* When set indicates checksum offload engine          5
+    DescRxChkSumBypass    = 0x00000020,    /* When set indicates checksum offload engine          5
                                             is bypassed                                                                   */
-  DescRxIpPayloadError  = 0x00000010,    /* When set indicates 16bit IP payload CS is in error  4                         */
-  DescRxIpHeaderError   = 0x00000008,    /* When set indicates 16bit IPV4 header CS is in       3
+    DescRxIpPayloadError  = 0x00000010,    /* When set indicates 16bit IP payload CS is in error  4                         */
+    DescRxIpHeaderError   = 0x00000008,    /* When set indicates 16bit IPV4 header CS is in       3
                                             error or IP datagram version is not consistent 
                                             with Ethernet type value                                                      */
-  DescRxIpPayloadType   = 0x00000007,     /* Indicate the type of payload encapsulated          2:0
+    DescRxIpPayloadType   = 0x00000007,     /* Indicate the type of payload encapsulated          2:0
                                              in IPdatagram processed by COE (Rx)                                          */
-  DescRxIpPayloadUnknown= 0x00000000,     /* Unknown or didnot process IP payload                                         */
-  DescRxIpPayloadUDP    = 0x00000001,     /* UDP                                                                          */
-  DescRxIpPayloadTCP    = 0x00000002,     /* TCP                                                                          */
-  DescRxIpPayloadICMP   = 0x00000003,     /* ICMP                                                                         */
+    DescRxIpPayloadUnknown= 0x00000000,     /* Unknown or didnot process IP payload                                         */
+    DescRxIpPayloadUDP    = 0x00000001,     /* UDP                                                                          */
+    DescRxIpPayloadTCP    = 0x00000002,     /* TCP                                                                          */
+    DescRxIpPayloadICMP   = 0x00000003,     /* ICMP                                                                         */
 
 };
 
@@ -965,55 +944,55 @@ DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format
 */
 enum DmaDescriptorStatus    /* status word of DMA descriptor */
 {
-  DescOwnByDma          = 0x80000000,   /* (OWN)Descriptor is owned by DMA engine            31      RW                  */
+    DescOwnByDma          = 0x80000000,   /* (OWN)Descriptor is owned by DMA engine            31      RW                  */
 
-  DescDAFilterFail      = 0x40000000,   /* (AFM)Rx - DA Filter Fail for the rx frame         30                          */
+    DescDAFilterFail      = 0x40000000,   /* (AFM)Rx - DA Filter Fail for the rx frame         30                          */
   
-  DescFrameLengthMask   = 0x3FFF0000,   /* (FL)Receive descriptor frame length               29:16                       */
-  DescFrameLengthShift  = 16,
+    DescFrameLengthMask   = 0x3FFF0000,   /* (FL)Receive descriptor frame length               29:16                       */
+    DescFrameLengthShift  = 16,
 
-  DescError             = 0x00008000,   /* (ES)Error summary bit  - OR of the follo. bits:   15                          */
+    DescError             = 0x00008000,   /* (ES)Error summary bit  - OR of the follo. bits:   15                          */
                     /*  DE || OE || IPC || LC || RWT || RE || CE */
-  DescRxTruncated       = 0x00004000,   /* (DE)Rx - no more descriptors for receive frame    14                          */
-  DescSAFilterFail      = 0x00002000,   /* (SAF)Rx - SA Filter Fail for the received frame   13                          */
-  DescRxLengthError    = 0x00001000,   /* (LE)Rx - frm size not matching with len field     12                          */
-  DescRxDamaged         = 0x00000800,   /* (OE)Rx - frm was damaged due to buffer overflow   11                          */
-  DescRxVLANTag         = 0x00000400,   /* (VLAN)Rx - received frame is a VLAN frame         10                          */
-  DescRxFirst           = 0x00000200,   /* (FS)Rx - first descriptor of the frame             9                          */
-  DescRxLast            = 0x00000100,   /* (LS)Rx - last descriptor of the frame              8                          */
-  DescRxLongFrame       = 0x00000080,   /* (Giant Frame)Rx - frame is longer than 1518/1522   7                          */
-  DescRxCollision       = 0x00000040,   /* (LC)Rx - late collision occurred during reception  6                          */
-  DescRxFrameEther      = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3    5                          */
-  DescRxWatchdog        = 0x00000010,   /* (RWT)Rx - watchdog timer expired during reception  4                          */
-  DescRxMiiError        = 0x00000008,   /* (RE)Rx - error reported by MII interface           3                          */
-  DescRxDribbling       = 0x00000004,   /* (DE)Rx - frame contains non int multiple of 8 bits 2                          */
-  DescRxCrc             = 0x00000002,   /* (CE)Rx - CRC error                                 1                          */
-  DescRxMacMatch        = 0x00000001,   /* (RX MAC Address) Rx mac address reg(1 to 15)match  0                          */ 
-
-  //Rx Descriptor Checksum Offload engine (type 2) encoding
-  //DescRxPayChkError     = 0x00000001,   /* ()  Rx - Rx Payload Checksum Error                 0                          */  
-  //DescRxIpv4ChkError    = 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error      7                          */
+    DescRxTruncated       = 0x00004000,   /* (DE)Rx - no more descriptors for receive frame    14                          */
+    DescSAFilterFail      = 0x00002000,   /* (SAF)Rx - SA Filter Fail for the received frame   13                          */
+    DescRxLengthError     = 0x00001000,   /* (LE)Rx - frm size not matching with len field     12                          */
+    DescRxDamaged         = 0x00000800,   /* (OE)Rx - frm was damaged due to buffer overflow   11                          */
+    DescRxVLANTag         = 0x00000400,   /* (VLAN)Rx - received frame is a VLAN frame         10                          */
+    DescRxFirst           = 0x00000200,   /* (FS)Rx - first descriptor of the frame             9                          */
+    DescRxLast            = 0x00000100,   /* (LS)Rx - last descriptor of the frame              8                          */
+    DescRxLongFrame       = 0x00000080,   /* (Giant Frame)Rx - frame is longer than 1518/1522   7                          */
+    DescRxCollision       = 0x00000040,   /* (LC)Rx - late collision occurred during reception  6                          */
+    DescRxFrameEther      = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3    5                          */
+    DescRxWatchdog        = 0x00000010,   /* (RWT)Rx - watchdog timer expired during reception  4                          */
+    DescRxMiiError        = 0x00000008,   /* (RE)Rx - error reported by MII interface           3                          */
+    DescRxDribbling       = 0x00000004,   /* (DE)Rx - frame contains non int multiple of 8 bits 2                          */
+    DescRxCrc             = 0x00000002,   /* (CE)Rx - CRC error                                 1                          */
+    DescRxMacMatch        = 0x00000001,   /* (RX MAC Address) Rx mac address reg(1 to 15)match  0                          */ 
+
+//Rx Descriptor Checksum Offload engine (type 2) encoding
+//DescRxPayChkError     = 0x00000001,   /* ()  Rx - Rx Payload Checksum Error                 0                          */  
+//DescRxIpv4ChkError    = 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error      7                          */
   
-  DescRxChkBit0        = 0x00000001,   /*()  Rx - Rx Payload Checksum Error                  0                          */
-  DescRxChkBit7        = 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error      7                          */
-  DescRxChkBit5        = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3    5                          */
+    DescRxChkBit0         = 0x00000001,   /*()  Rx - Rx Payload Checksum Error                  0                          */
+    DescRxChkBit7         = 0x00000080,   /* (IPC CS ERROR)Rx - Ipv4 header checksum error      7                          */
+    DescRxChkBit5         = 0x00000020,   /* (FT)Rx - Frame type - Ethernet, otherwise 802.3    5                          */
   
-  DescTxIpv4ChkError    = 0x00010000,   /* (IHE) Tx Ip header error                           16                         */
-  DescTxTimeout         = 0x00004000,   /* (JT)Tx - Transmit jabber timeout                   14                         */
-  DescTxFrameFlushed    = 0x00002000,   /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13                         */
-  DescTxPayChkError     = 0x00001000,   /* (PCE) Tx Payload checksum Error                    12                         */
-  DescTxLostCarrier     = 0x00000800,   /* (LC)Tx - carrier lost during tramsmission          11                         */
-  DescTxNoCarrier       = 0x00000400,   /* (NC)Tx - no carrier signal from the tranceiver     10                         */
-  DescTxLateCollision   = 0x00000200,   /* (LC)Tx - transmission aborted due to collision      9                         */
-  DescTxExcCollisions   = 0x00000100,   /* (EC)Tx - transmission aborted after 16 collisions   8                         */
-  DescTxVLANFrame       = 0x00000080,   /* (VF)Tx - VLAN-type frame                            7                         */
+    DescTxIpv4ChkError    = 0x00010000,   /* (IHE) Tx Ip header error                           16                         */
+    DescTxTimeout         = 0x00004000,   /* (JT)Tx - Transmit jabber timeout                   14                         */
+    DescTxFrameFlushed    = 0x00002000,   /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13                         */
+    DescTxPayChkError     = 0x00001000,   /* (PCE) Tx Payload checksum Error                    12                         */
+    DescTxLostCarrier     = 0x00000800,   /* (LC)Tx - carrier lost during tramsmission          11                         */
+    DescTxNoCarrier       = 0x00000400,   /* (NC)Tx - no carrier signal from the tranceiver     10                         */
+    DescTxLateCollision   = 0x00000200,   /* (LC)Tx - transmission aborted due to collision      9                         */
+    DescTxExcCollisions   = 0x00000100,   /* (EC)Tx - transmission aborted after 16 collisions   8                         */
+    DescTxVLANFrame       = 0x00000080,   /* (VF)Tx - VLAN-type frame                            7                         */
  
-  DescTxCollMask        = 0x00000078,   /* (CC)Tx - Collision count                           6:3                        */
-  DescTxCollShift       = 3,
+    DescTxCollMask        = 0x00000078,   /* (CC)Tx - Collision count                           6:3                        */
+    DescTxCollShift       = 3,
   
-  DescTxExcDeferral     = 0x00000004,   /* (ED)Tx - excessive deferral                          2                        */
-  DescTxUnderflow       = 0x00000002,   /* (UF)Tx - late data arrival from the memory           1                        */
-  DescTxDeferred        = 0x00000001,   /* (DB)Tx - frame transmision deferred                  0                        */
+    DescTxExcDeferral     = 0x00000004,   /* (ED)Tx - excessive deferral                          2                        */
+    DescTxUnderflow       = 0x00000002,   /* (UF)Tx - late data arrival from the memory           1                        */
+    DescTxDeferred        = 0x00000001,   /* (DB)Tx - frame transmision deferred                  0                        */
   
     /*
     This explains the RDES1/TDES1 bits layout
@@ -1023,46 +1002,44 @@ enum DmaDescriptorStatus    /* status word of DMA descriptor */
 
     */    
 //DmaDescriptorLength     length word of DMA descriptor
-
-  DescTxIntEnable       = 0x80000000,   /* (IC)Tx - interrupt on completion                    31                       */
-  DescTxLast            = 0x40000000,   /* (LS)Tx - Last segment of the frame                  30                       */
-  DescTxFirst           = 0x20000000,   /* (FS)Tx - First segment of the frame                 29                       */
-  DescTxDisableCrc      = 0x04000000,   /* (DC)Tx - Add CRC disabled (first segment only)      26                       */
-
-  RxDisIntCompl        = 0x80000000,    /* (Disable Rx int on completion)             31            */
-  RxDescEndOfRing       = 0x02000000,   /* (TER)End of descriptors ring                                                 */
-  RxDescChain           = 0x01000000,   /* (TCH)Second buffer address is chain address         24                       */
+    DescTxIntEnable       = 0x80000000,   /* (IC)Tx - interrupt on completion                    31                       */
+    DescTxLast            = 0x40000000,   /* (LS)Tx - Last segment of the frame                  30                       */
+    DescTxFirst           = 0x20000000,   /* (FS)Tx - First segment of the frame                 29                       */
+    DescTxDisableCrc      = 0x04000000,   /* (DC)Tx - Add CRC disabled (first segment only)      26                       */
+
+    RxDisIntCompl         = 0x80000000,    /* (Disable Rx int on completion)             31            */
+    RxDescEndOfRing       = 0x02000000,   /* (TER)End of descriptors ring                                                 */
+    RxDescChain           = 0x01000000,   /* (TCH)Second buffer address is chain address         24                       */
   
-  DescTxDisablePadd    = 0x00800000,   /* (DP)disable padding, added by - reyaz               23                       */
+    DescTxDisablePadd     = 0x00800000,   /* (DP)disable padding, added by - reyaz               23                       */
 
-  TxDescEndOfRing       = 0x02000000,   /* (TER)End of descriptors ring                                                 */
-  TxDescChain           = 0x01000000,   /* (TCH)Second buffer address is chain address         24                       */
+    TxDescEndOfRing       = 0x02000000,   /* (TER)End of descriptors ring                                                 */
+    TxDescChain           = 0x01000000,   /* (TCH)Second buffer address is chain address         24                       */
   
-  DescSize2Mask         = 0x003FF800,   /* (TBS2) Buffer 2 size                                21:11                    */
-  DescSize2Shift        = 11,
-  DescSize1Mask         = 0x000007FF,   /* (TBS1) Buffer 1 size                                10:0                     */
-  DescSize1Shift        = 0,
-
-
-  DescTxCisMask      = 0x18000000,   /* Tx checksum offloading control mask            28:27            */
-  DescTxCisBypass    = 0x00000000,   /* Checksum bypass                                */
-  DescTxCisIpv4HdrCs    = 0x08000000,    /* IPv4 header checksum                                */
-  DescTxCisTcpOnlyCs    = 0x10000000,    /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present    */
-  DescTxCisTcpPseudoCs  = 0x18000000,    /* TCP/UDP/ICMP checksum fully in hardware including pseudo header        */
+    DescSize2Mask         = 0x003FF800,   /* (TBS2) Buffer 2 size                                21:11                    */
+    DescSize2Shift        = 11,
+    DescSize1Mask         = 0x000007FF,   /* (TBS1) Buffer 1 size                                10:0                     */
+    DescSize1Shift        = 0,
+
+    DescTxCisMask         = 0x18000000,   /* Tx checksum offloading control mask            28:27            */
+    DescTxCisBypass       = 0x00000000,   /* Checksum bypass                                */
+    DescTxCisIpv4HdrCs    = 0x08000000,    /* IPv4 header checksum                                */
+    DescTxCisTcpOnlyCs    = 0x10000000,    /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present    */
+    DescTxCisTcpPseudoCs  = 0x18000000,    /* TCP/UDP/ICMP checksum fully in hardware including pseudo header        */
 };
 #endif
 
 // Rx Descriptor COE type2 encoding
 enum RxDescCOEEncode
 {
-  RxLenLT600            = 0,    /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600            */
-  RxIpHdrPayLoadChkBypass    = 1,    /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload)         */
-  RxIpHdrPayLoadRes        = 2,    /* Bit(5:7:0)=>2 Reserved                                 */
-  RxChkBypass            = 3,    /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed                  */
-  RxNoChkError            = 4,    /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected                    */
-  RxPayLoadChkError        = 5,    /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames            */
-  RxIpHdrChkError        = 6,    /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames            */
-  RxIpHdrPayLoadChkError    = 7,    /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames    */
+    RxLenLT600                 = 0,    /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600            */
+    RxIpHdrPayLoadChkBypass    = 1,    /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload)         */
+    RxIpHdrPayLoadRes          = 2,    /* Bit(5:7:0)=>2 Reserved                                 */
+    RxChkBypass                = 3,    /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed                  */
+    RxNoChkError               = 4,    /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected                    */
+    RxPayLoadChkError          = 5,    /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames            */
+    RxIpHdrChkError            = 6,    /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames            */
+    RxIpHdrPayLoadChkError     = 7,    /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames    */
 };
 
 /**********************************************************
@@ -1071,13 +1048,13 @@ enum RxDescCOEEncode
  
  enum synopGMACDmaIntEnum  /* Intrerrupt types */
 {
-  synopGMACDmaRxNormal   = 0x01,   /* normal receiver interrupt */
-  synopGMACDmaRxAbnormal = 0x02,   /* abnormal receiver interrupt */
-  synopGMACDmaRxStopped  = 0x04,   /* receiver stopped */
-  synopGMACDmaTxNormal   = 0x08,   /* normal transmitter interrupt */
-  synopGMACDmaTxAbnormal = 0x10,   /* abnormal transmitter interrupt */
-  synopGMACDmaTxStopped  = 0x20,   /* transmitter stopped */
-  synopGMACDmaError      = 0x80,   /* Dma engine error */
+    synopGMACDmaRxNormal   = 0x01,   /* normal receiver interrupt */
+    synopGMACDmaRxAbnormal = 0x02,   /* abnormal receiver interrupt */
+    synopGMACDmaRxStopped  = 0x04,   /* receiver stopped */
+    synopGMACDmaTxNormal   = 0x08,   /* normal transmitter interrupt */
+    synopGMACDmaTxAbnormal = 0x10,   /* abnormal transmitter interrupt */
+    synopGMACDmaTxStopped  = 0x20,   /* transmitter stopped */
+    synopGMACDmaError      = 0x80,   /* Dma engine error */
 };
 
 
@@ -1087,45 +1064,45 @@ enum RxDescCOEEncode
 enum InitialRegisters
 {
    /* Full-duplex mode with perfect filter on */
-  GmacConfigInitFdx1000   = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable | GmacJumboFrameDisable
-                          | GmacSelectGmii     | GmacEnableRxOwn          | GmacLoopbackOff
-                          | GmacFullDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable
-                          | GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
+    GmacConfigInitFdx1000   = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable | GmacJumboFrameDisable
+                            | GmacSelectGmii     | GmacEnableRxOwn          | GmacLoopbackOff
+                            | GmacFullDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable
+                            | GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
   
   /* Full-duplex mode with perfect filter on */
-  GmacConfigInitFdx110    = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
-                          | GmacSelectMii      | GmacEnableRxOwn          | GmacLoopbackOff
-                          | GmacFullDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable
-                          | GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
+    GmacConfigInitFdx110    = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
+                            | GmacSelectMii      | GmacEnableRxOwn          | GmacLoopbackOff
+                            | GmacFullDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable
+                            | GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
 
    /* Full-duplex mode */
    // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast 
    // Hash filter. 
    /*                        = GmacFilterOff         | GmacPassControlOff | GmacBroadcastEnable */
-   GmacFrameFilterInitFdx = GmacFilterOn          | GmacPassControl0   | GmacBroadcastEnable |  GmacSrcAddrFilterDisable
-                           | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff
-                          | GmacPromiscuousModeOff | GmacUcastHashFilterOff,
+     GmacFrameFilterInitFdx = GmacFilterOn          | GmacPassControl0   | GmacBroadcastEnable |  GmacSrcAddrFilterDisable
+                            | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff
+                            | GmacPromiscuousModeOff | GmacUcastHashFilterOff,
    
    /* Full-duplex mode */
-   GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable,
+    GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable,
 
    /* Full-duplex mode */
-   GmacGmiiAddrInitFdx    = GmiiCsrClk2,
+    GmacGmiiAddrInitFdx    = GmiiCsrClk2,
 
 
    /* Half-duplex mode with perfect filter on */
    // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip,                 
    /*| GmacSelectMii      | GmacLittleEndian         | GmacDisableRxOwn      | GmacLoopbackOff*/
-   GmacConfigInitHdx1000  = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
-                          | GmacSelectGmii     | GmacDisableRxOwn         | GmacLoopbackOff
-                          | GmacHalfDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable   
-                          | GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
+    GmacConfigInitHdx1000  = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
+                           | GmacSelectGmii     | GmacDisableRxOwn         | GmacLoopbackOff
+                           | GmacHalfDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable   
+                           | GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
 
    /* Half-duplex mode with perfect filter on */
-   GmacConfigInitHdx110   = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
-                          | GmacSelectMii      | GmacDisableRxOwn         | GmacLoopbackOff
-                          | GmacHalfDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable 
-                          | GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
+    GmacConfigInitHdx110   = GmacWatchdogEnable | GmacJabberEnable         | GmacFrameBurstEnable  | GmacJumboFrameDisable
+                           | GmacSelectMii      | GmacDisableRxOwn         | GmacLoopbackOff
+                           | GmacHalfDuplex     | GmacRetryEnable          | GmacPadCrcStripDisable 
+                           | GmacBackoffLimit0  | GmacDeferralCheckDisable | GmacTxEnable          | GmacRxEnable,
 
    /* Half-duplex mode */
    GmacFrameFilterInitHdx = GmacFilterOn          | GmacPassControl0        | GmacBroadcastEnable | GmacSrcAddrFilterDisable
@@ -1138,39 +1115,37 @@ enum InitialRegisters
    /* Half-duplex mode */
    GmacGmiiAddrInitHdx    = GmiiCsrClk2,
 
-
-
    /**********************************************
    *DMA configurations
    **********************************************/
 
-  DmaBusModeInit         = DmaFixedBurstEnable |   DmaBurstLength8   | DmaDescriptorSkip1       | DmaResetOff,
+    DmaBusModeInit         = DmaFixedBurstEnable |   DmaBurstLength8   | DmaDescriptorSkip1       | DmaResetOff,
 //   DmaBusModeInit         = DmaFixedBurstEnable |   DmaBurstLength8   | DmaDescriptorSkip4       | DmaResetOff,
    
    /* 1000 Mb/s mode */
-   DmaControlInit1000     = DmaStoreAndForward,//       | DmaTxSecondFrame ,
+   DmaControlInit1000      = DmaStoreAndForward,//       | DmaTxSecondFrame ,
 
    /* 100 Mb/s mode */
-   DmaControlInit100      = DmaStoreAndForward,
+   DmaControlInit100       = DmaStoreAndForward,
    
    /* 10 Mb/s mode */
-   DmaControlInit10       = DmaStoreAndForward,
+   DmaControlInit10        = DmaStoreAndForward,
 
   /* Interrupt groups */
-  DmaIntErrorMask         = DmaIntBusError,           /* Error */
-  DmaIntRxAbnMask         = DmaIntRxNoBuffer,         /* receiver abnormal interrupt */
-  DmaIntRxNormMask        = DmaIntRxCompleted,        /* receiver normal interrupt   */
-  DmaIntRxStoppedMask     = DmaIntRxStopped,          /* receiver stopped */
-  DmaIntTxAbnMask         = DmaIntTxUnderflow,        /* transmitter abnormal interrupt */
-  DmaIntTxNormMask        = DmaIntTxCompleted,        /* transmitter normal interrupt */
-  DmaIntTxStoppedMask     = DmaIntTxStopped,          /* transmitter stopped */
-
-  DmaIntEnable            = DmaIeNormal     | DmaIeAbnormal    | DmaIntErrorMask
-//DmaIntEnable            = DmaIeNormal     | DmaIntErrorMask
-                          | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask
-//                          | DmaIntRxNormMask | DmaIntRxStoppedMask
-                          | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask,
-  DmaIntDisable           = 0,
+  DmaIntErrorMask          = DmaIntBusError,           /* Error */
+  DmaIntRxAbnMask          = DmaIntRxNoBuffer,         /* receiver abnormal interrupt */
+  DmaIntRxNormMask         = DmaIntRxCompleted,        /* receiver normal interrupt   */
+  DmaIntRxStoppedMask      = DmaIntRxStopped,          /* receiver stopped */
+  DmaIntTxAbnMask          = DmaIntTxUnderflow,        /* transmitter abnormal interrupt */
+  DmaIntTxNormMask         = DmaIntTxCompleted,        /* transmitter normal interrupt */
+  DmaIntTxStoppedMask      = DmaIntTxStopped,          /* transmitter stopped */
+
+  DmaIntEnable             = DmaIeNormal     | DmaIeAbnormal    | DmaIntErrorMask
+//DmaIntEnable             = DmaIeNormal     | DmaIntErrorMask
+                           | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask
+//                         | DmaIntRxNormMask | DmaIntRxStoppedMask
+                           | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask,
+  DmaIntDisable            = 0,
 };
 
 
@@ -1180,186 +1155,185 @@ enum InitialRegisters
 
 enum MMC_ENABLE
 {
-    GmacMmcCntrl            = 0x0100,    /* mmc control for operating mode of MMC                        */
-    GmacMmcIntrRx            = 0x0104,    /* maintains interrupts generated by rx counters                    */
-    GmacMmcIntrTx            = 0x0108,    /* maintains interrupts generated by tx counters                    */
-    GmacMmcIntrMaskRx        = 0x010C,    /* mask for interrupts generated from rx counters                    */
-    GmacMmcIntrMaskTx        = 0x0110,    /* mask for interrupts generated from tx counters                    */
+    GmacMmcCntrl               = 0x0100,    /* mmc control for operating mode of MMC                        */
+    GmacMmcIntrRx              = 0x0104,    /* maintains interrupts generated by rx counters                    */
+    GmacMmcIntrTx              = 0x0108,    /* maintains interrupts generated by tx counters                    */
+    GmacMmcIntrMaskRx          = 0x010C,    /* mask for interrupts generated from rx counters                    */
+    GmacMmcIntrMaskTx          = 0x0110,    /* mask for interrupts generated from tx counters                    */
 };
 enum MMC_TX
 {
-    GmacMmcTxOctetCountGb        = 0x0114,    /*Bytes Tx excl. of preamble and retried bytes     (Good or Bad)            */
-    GmacMmcTxFrameCountGb        = 0x0118,    /*Frames Tx excl. of retried frames               (Good or Bad)            */
-    GmacMmcTxBcFramesG        = 0x011C,    /*Broadcast Frames Tx                    (Good)                */
-    GmacMmcTxMcFramesG        = 0x0120,    /*Multicast Frames Tx                   (Good)                */
+    GmacMmcTxOctetCountGb      = 0x0114,    /*Bytes Tx excl. of preamble and retried bytes     (Good or Bad)            */
+    GmacMmcTxFrameCountGb      = 0x0118,    /*Frames Tx excl. of retried frames               (Good or Bad)            */
+    GmacMmcTxBcFramesG         = 0x011C,    /*Broadcast Frames Tx                    (Good)                */
+    GmacMmcTxMcFramesG         = 0x0120,    /*Multicast Frames Tx                   (Good)                */
     
     GmacMmcTx64OctetsGb        = 0x0124,    /*Tx with len 64 bytes excl. of pre and retried    (Good or Bad)            */
-    GmacMmcTx65To127OctetsGb    = 0x0128,    /*Tx with len >64 bytes <=127 excl. of pre and retried    (Good or Bad)            */
-    GmacMmcTx128To255OctetsGb    = 0x012C,    /*Tx with len >128 bytes <=255 excl. of pre and retried   (Good or Bad)            */
-    GmacMmcTx256To511OctetsGb    = 0x0130,    /*Tx with len >256 bytes <=511 excl. of pre and retried   (Good or Bad)            */
-    GmacMmcTx512To1023OctetsGb    = 0x0134,    /*Tx with len >512 bytes <=1023 excl. of pre and retried  (Good or Bad)            */
-    GmacMmcTx1024ToMaxOctetsGb    = 0x0138,    /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad)        */
+    GmacMmcTx65To127OctetsGb   = 0x0128,    /*Tx with len >64 bytes <=127 excl. of pre and retried    (Good or Bad)            */
+    GmacMmcTx128To255OctetsGb  = 0x012C,    /*Tx with len >128 bytes <=255 excl. of pre and retried   (Good or Bad)            */
+    GmacMmcTx256To511OctetsGb  = 0x0130,    /*Tx with len >256 bytes <=511 excl. of pre and retried   (Good or Bad)            */
+    GmacMmcTx512To1023OctetsGb = 0x0134,    /*Tx with len >512 bytes <=1023 excl. of pre and retried  (Good or Bad)            */
+    GmacMmcTx1024ToMaxOctetsGb = 0x0138,    /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad)        */
     
     GmacMmcTxUcFramesGb        = 0x013C,    /*Unicast Frames Tx                      (Good or Bad)            */
     GmacMmcTxMcFramesGb        = 0x0140,    /*Multicast Frames Tx                   (Good and Bad)            */
     GmacMmcTxBcFramesGb        = 0x0144,    /*Broadcast Frames Tx                    (Good and Bad)            */
-    GmacMmcTxUnderFlowError        = 0x0148,    /*Frames aborted due to Underflow error                            */
+    GmacMmcTxUnderFlowError    = 0x0148,    /*Frames aborted due to Underflow error                            */
     GmacMmcTxSingleColG        = 0x014C,    /*Successfully Tx Frames after singel collision in Half duplex mode            */
-    GmacMmcTxMultiColG        = 0x0150,    /*Successfully Tx Frames after more than singel collision in Half duplex mode        */
-    GmacMmcTxDeferred        = 0x0154,    /*Successfully Tx Frames after a deferral in Half duplex mode                */
-    GmacMmcTxLateCol        = 0x0158,    /*Frames aborted due to late collision error                        */
-    GmacMmcTxExessCol        = 0x015C,    /*Frames aborted due to excessive (16) collision errors                    */
-    GmacMmcTxCarrierError        = 0x0160,    /*Frames aborted due to carrier sense error (No carrier or Loss of carrier)        */
-    GmacMmcTxOctetCountG        = 0x0164,    /*Bytes Tx excl. of preamble and retried bytes     (Good)                 */
-    GmacMmcTxFrameCountG        = 0x0168,    /*Frames Tx                            (Good)                */
-    GmacMmcTxExessDef        = 0x016C,    /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/
+    GmacMmcTxMultiColG         = 0x0150,    /*Successfully Tx Frames after more than singel collision in Half duplex mode        */
+    GmacMmcTxDeferred          = 0x0154,    /*Successfully Tx Frames after a deferral in Half duplex mode                */
+    GmacMmcTxLateCol           = 0x0158,    /*Frames aborted due to late collision error                        */
+    GmacMmcTxExessCol          = 0x015C,    /*Frames aborted due to excessive (16) collision errors                    */
+    GmacMmcTxCarrierError      = 0x0160,    /*Frames aborted due to carrier sense error (No carrier or Loss of carrier)        */
+    GmacMmcTxOctetCountG       = 0x0164,    /*Bytes Tx excl. of preamble and retried bytes     (Good)                 */
+    GmacMmcTxFrameCountG       = 0x0168,    /*Frames Tx                            (Good)                */
+    GmacMmcTxExessDef          = 0x016C,    /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/
     
-    GmacMmcTxPauseFrames        = 0x0170,    /*Number of good pause frames Tx.                            */
-    GmacMmcTxVlanFramesG        = 0x0174,    /*Number of good Vlan frames Tx excl. retried frames                    */
+    GmacMmcTxPauseFrames       = 0x0170,    /*Number of good pause frames Tx.                            */
+    GmacMmcTxVlanFramesG       = 0x0174,    /*Number of good Vlan frames Tx excl. retried frames                    */
 };
 enum MMC_RX
 {
-    GmacMmcRxFrameCountGb        = 0x0180,    /*Frames Rx                            (Good or Bad)            */
-    GmacMmcRxOctetCountGb        = 0x0184,    /*Bytes Rx excl. of preamble and retried bytes     (Good or Bad)            */
-    GmacMmcRxOctetCountG        = 0x0188,    /*Bytes Rx excl. of preamble and retried bytes     (Good)                 */
-    GmacMmcRxBcFramesG        = 0x018C,    /*Broadcast Frames Rx                    (Good)                */
-    GmacMmcRxMcFramesG        = 0x0190,    /*Multicast Frames Rx                   (Good)                */
+    GmacMmcRxFrameCountGb      = 0x0180,    /*Frames Rx                            (Good or Bad)            */
+    GmacMmcRxOctetCountGb      = 0x0184,    /*Bytes Rx excl. of preamble and retried bytes     (Good or Bad)            */
+    GmacMmcRxOctetCountG       = 0x0188,    /*Bytes Rx excl. of preamble and retried bytes     (Good)                 */
+    GmacMmcRxBcFramesG         = 0x018C,    /*Broadcast Frames Rx                    (Good)                */
+    GmacMmcRxMcFramesG         = 0x0190,    /*Multicast Frames Rx                   (Good)                */
     
-    GmacMmcRxCrcError        = 0x0194,    /*Number of frames received with CRC error                        */
+    GmacMmcRxCrcError          = 0x0194,    /*Number of frames received with CRC error                        */
     GmacMmcRxAlignError        = 0x0198,    /*Number of frames received with alignment (dribble) error. Only in 10/100mode        */
-    GmacMmcRxRuntError        = 0x019C,    /*Number of frames received with runt (<64 bytes and CRC error) error            */
-    GmacMmcRxJabberError        = 0x01A0,    /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC)             */
+    GmacMmcRxRuntError         = 0x019C,    /*Number of frames received with runt (<64 bytes and CRC error) error            */
+    GmacMmcRxJabberError       = 0x01A0,    /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC)             */
     GmacMmcRxUnderSizeG        = 0x01A4,    /*Number of frames received with <64 bytes without any error                */
-    GmacMmcRxOverSizeG        = 0x01A8,    /*Number of frames received with >1518/1522 bytes without any error            */
+    GmacMmcRxOverSizeG         = 0x01A8,    /*Number of frames received with >1518/1522 bytes without any error            */
     
     GmacMmcRx64OctetsGb        = 0x01AC,    /*Rx with len 64 bytes excl. of pre and retried    (Good or Bad)            */
-    GmacMmcRx65To127OctetsGb    = 0x01B0,    /*Rx with len >64 bytes <=127 excl. of pre and retried    (Good or Bad)            */
-    GmacMmcRx128To255OctetsGb    = 0x01B4,    /*Rx with len >128 bytes <=255 excl. of pre and retried   (Good or Bad)            */
-    GmacMmcRx256To511OctetsGb    = 0x01B8,    /*Rx with len >256 bytes <=511 excl. of pre and retried   (Good or Bad)            */
-    GmacMmcRx512To1023OctetsGb    = 0x01BC,    /*Rx with len >512 bytes <=1023 excl. of pre and retried  (Good or Bad)            */
-    GmacMmcRx1024ToMaxOctetsGb    = 0x01C0,    /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad)        */
+    GmacMmcRx65To127OctetsGb   = 0x01B0,    /*Rx with len >64 bytes <=127 excl. of pre and retried    (Good or Bad)            */
+    GmacMmcRx128To255OctetsGb  = 0x01B4,    /*Rx with len >128 bytes <=255 excl. of pre and retried   (Good or Bad)            */
+    GmacMmcRx256To511OctetsGb  = 0x01B8,    /*Rx with len >256 bytes <=511 excl. of pre and retried   (Good or Bad)            */
+    GmacMmcRx512To1023OctetsGb = 0x01BC,    /*Rx with len >512 bytes <=1023 excl. of pre and retried  (Good or Bad)            */
+    GmacMmcRx1024ToMaxOctetsGb = 0x01C0,    /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad)        */
     
-    GmacMmcRxUcFramesG        = 0x01C4,    /*Unicast Frames Rx                      (Good)                */
-    GmacMmcRxLengthError        = 0x01C8,    /*Number of frames received with Length type field != frame size            */
-    GmacMmcRxOutOfRangeType        = 0x01CC,    /*Number of frames received with length field != valid frame size            */
+    GmacMmcRxUcFramesG         = 0x01C4,    /*Unicast Frames Rx                      (Good)                */
+    GmacMmcRxLengthError       = 0x01C8,    /*Number of frames received with Length type field != frame size            */
+    GmacMmcRxOutOfRangeType    = 0x01CC,    /*Number of frames received with length field != valid frame size            */
     
-    GmacMmcRxPauseFrames        = 0x01D0,    /*Number of good pause frames Rx.                            */
-    GmacMmcRxFifoOverFlow        = 0x01D4,    /*Number of missed rx frames due to FIFO overflow                    */
-    GmacMmcRxVlanFramesGb        = 0x01D8,    /*Number of good Vlan frames Rx                             */
+    GmacMmcRxPauseFrames       = 0x01D0,    /*Number of good pause frames Rx.                            */
+    GmacMmcRxFifoOverFlow      = 0x01D4,    /*Number of missed rx frames due to FIFO overflow                    */
+    GmacMmcRxVlanFramesGb      = 0x01D8,    /*Number of good Vlan frames Rx                             */
     
-    GmacMmcRxWatchdobError        = 0x01DC,    /*Number of frames rx with error due to watchdog timeout error                */
+    GmacMmcRxWatchdobError     = 0x01DC,    /*Number of frames rx with error due to watchdog timeout error                */
 };
+
 enum MMC_IP_RELATED
 {
-    GmacMmcRxIpcIntrMask        = 0x0200,    /*Maintains the mask for interrupt generated from rx IPC statistic counters         */
-    GmacMmcRxIpcIntr        = 0x0208,    /*Maintains the interrupt that rx IPC statistic counters generate            */
+    GmacMmcRxIpcIntrMask           = 0x0200,    /*Maintains the mask for interrupt generated from rx IPC statistic counters         */
+    GmacMmcRxIpcIntr               = 0x0208,    /*Maintains the interrupt that rx IPC statistic counters generate            */
     
-    GmacMmcRxIpV4FramesG        = 0x0210,    /*Good IPV4 datagrams received                                */
-    GmacMmcRxIpV4HdrErrFrames    = 0x0214,    /*Number of IPV4 datagrams received with header errors                    */
-    GmacMmcRxIpV4NoPayFrames    = 0x0218,    /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload        */
+    GmacMmcRxIpV4FramesG           = 0x0210,    /*Good IPV4 datagrams received                                */
+    GmacMmcRxIpV4HdrErrFrames      = 0x0214,    /*Number of IPV4 datagrams received with header errors                    */
+    GmacMmcRxIpV4NoPayFrames       = 0x0218,    /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload        */
     GmacMmcRxIpV4FragFrames        = 0x021C,    /*Number of IPV4 datagrams received with fragmentation                    */
-    GmacMmcRxIpV4UdpChkDsblFrames    = 0x0220,    /*Number of IPV4 datagrams received that had a UDP payload checksum disabled        */
+    GmacMmcRxIpV4UdpChkDsblFrames  = 0x0220,    /*Number of IPV4 datagrams received that had a UDP payload checksum disabled        */
     
-    GmacMmcRxIpV6FramesG        = 0x0224,    /*Good IPV6 datagrams received                                */
-    GmacMmcRxIpV6HdrErrFrames    = 0x0228,    /*Number of IPV6 datagrams received with header errors                    */
-    GmacMmcRxIpV6NoPayFrames    = 0x022C,    /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload        */
+    GmacMmcRxIpV6FramesG           = 0x0224,    /*Good IPV6 datagrams received                                */
+    GmacMmcRxIpV6HdrErrFrames      = 0x0228,    /*Number of IPV6 datagrams received with header errors                    */
+    GmacMmcRxIpV6NoPayFrames       = 0x022C,    /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload        */
     
-    GmacMmcRxUdpFramesG        = 0x0230,    /*Number of good IP datagrams with good UDP payload                    */
+    GmacMmcRxUdpFramesG            = 0x0230,    /*Number of good IP datagrams with good UDP payload                    */
     GmacMmcRxUdpErrorFrames        = 0x0234,    /*Number of good IP datagrams with UDP payload having checksum error            */
     
-    GmacMmcRxTcpFramesG        = 0x0238,    /*Number of good IP datagrams with good TDP payload                    */
+    GmacMmcRxTcpFramesG            = 0x0238,    /*Number of good IP datagrams with good TDP payload                    */
     GmacMmcRxTcpErrorFrames        = 0x023C,    /*Number of good IP datagrams with TCP payload having checksum error            */
 
-    GmacMmcRxIcmpFramesG        = 0x0240,    /*Number of good IP datagrams with good Icmp payload                    */
-    GmacMmcRxIcmpErrorFrames    = 0x0244,    /*Number of good IP datagrams with Icmp payload having checksum error            */
+    GmacMmcRxIcmpFramesG           = 0x0240,    /*Number of good IP datagrams with good Icmp payload                    */
+    GmacMmcRxIcmpErrorFrames       = 0x0244,    /*Number of good IP datagrams with Icmp payload having checksum error            */
     
-    GmacMmcRxIpV4OctetsG        = 0x0250,    /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes            */
+    GmacMmcRxIpV4OctetsG           = 0x0250,    /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes            */
     GmacMmcRxIpV4HdrErrorOctets    = 0x0254,    /*Number of bytes in IPV4 datagram with header errors                    */
-    GmacMmcRxIpV4NoPayOctets    = 0x0258,    /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload                */
+    GmacMmcRxIpV4NoPayOctets       = 0x0258,    /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload                */
     GmacMmcRxIpV4FragOctets        = 0x025C,    /*Number of bytes received in fragmented IPV4 datagrams                 */
-    GmacMmcRxIpV4UdpChkDsblOctets    = 0x0260,    /*Number of bytes received in UDP segment that had UDP checksum disabled        */
+    GmacMmcRxIpV4UdpChkDsblOctets  = 0x0260,    /*Number of bytes received in UDP segment that had UDP checksum disabled        */
     
-    GmacMmcRxIpV6OctetsG        = 0x0264,    /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes            */
+    GmacMmcRxIpV6OctetsG           = 0x0264,    /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes            */
     GmacMmcRxIpV6HdrErrorOctets    = 0x0268,    /*Number of bytes in IPV6 datagram with header errors                    */
-    GmacMmcRxIpV6NoPayOctets    = 0x026C,    /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload                */
+    GmacMmcRxIpV6NoPayOctets       = 0x026C,    /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload                */
     
-    GmacMmcRxUdpOctetsG        = 0x0270,    /*Number of bytes in IP datagrams with good UDP payload                    */
+    GmacMmcRxUdpOctetsG            = 0x0270,    /*Number of bytes in IP datagrams with good UDP payload                    */
     GmacMmcRxUdpErrorOctets        = 0x0274,    /*Number of bytes in IP datagrams with UDP payload having checksum error        */
     
-    GmacMmcRxTcpOctetsG        = 0x0278,    /*Number of bytes in IP datagrams with good TDP payload                    */
+    GmacMmcRxTcpOctetsG            = 0x0278,    /*Number of bytes in IP datagrams with good TDP payload                    */
     GmacMmcRxTcpErrorOctets        = 0x027C,    /*Number of bytes in IP datagrams with TCP payload having checksum error        */
     
-    GmacMmcRxIcmpOctetsG        = 0x0280,    /*Number of bytes in IP datagrams with good Icmp payload                */
-    GmacMmcRxIcmpErrorOctets    = 0x0284,    /*Number of bytes in IP datagrams with Icmp payload having checksum error        */
+    GmacMmcRxIcmpOctetsG           = 0x0280,    /*Number of bytes in IP datagrams with good Icmp payload                */
+    GmacMmcRxIcmpErrorOctets       = 0x0284,    /*Number of bytes in IP datagrams with Icmp payload having checksum error        */
 };
 
 
 enum MMC_CNTRL_REG_BIT_DESCRIPTIONS
 {
-    GmacMmcCounterFreeze        = 0x00000008,        /* when set MMC counters freeze to current value                */
-    GmacMmcCounterResetOnRead    = 0x00000004,        /* when set MMC counters will be reset to 0 after read                */
+    GmacMmcCounterFreeze          = 0x00000008,        /* when set MMC counters freeze to current value                */
+    GmacMmcCounterResetOnRead     = 0x00000004,        /* when set MMC counters will be reset to 0 after read                */
     GmacMmcCounterStopRollover    = 0x00000002,        /* when set counters will not rollover after max value                */
-    GmacMmcCounterReset        = 0x00000001,        /* when set all counters wil be reset (automatically cleared after 1 clk)    */
-    
+    GmacMmcCounterReset           = 0x00000001,        /* when set all counters wil be reset (automatically cleared after 1 clk)    */
 };
 
 enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
 {
-    GmacMmcRxWDInt            = 0x00800000,        /* set when rxwatchdog error reaches half of max value                */
-    GmacMmcRxVlanInt        = 0x00400000,        /* set when GmacMmcRxVlanFramesGb counter reaches half of max value        */
-    GmacMmcRxFifoOverFlowInt    = 0x00200000,        /* set when GmacMmcRxFifoOverFlow counter reaches half of max value        */
+    GmacMmcRxWDInt                = 0x00800000,        /* set when rxwatchdog error reaches half of max value                */
+    GmacMmcRxVlanInt              = 0x00400000,        /* set when GmacMmcRxVlanFramesGb counter reaches half of max value        */
+    GmacMmcRxFifoOverFlowInt      = 0x00200000,        /* set when GmacMmcRxFifoOverFlow counter reaches half of max value        */
     GmacMmcRxPauseFrameInt        = 0x00100000,        /* set when GmacMmcRxPauseFrames counter reaches half of max value        */
     GmacMmcRxOutOfRangeInt        = 0x00080000,        /* set when GmacMmcRxOutOfRangeType counter reaches half of max value        */
-    GmacMmcRxLengthErrorInt        = 0x00040000,        /* set when GmacMmcRxLengthError counter reaches half of max value        */
-    GmacMmcRxUcFramesInt        = 0x00020000,        /* set when GmacMmcRxUcFramesG counter reaches half of max value        */
-    GmacMmcRx1024OctInt        = 0x00010000,        /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value    */
-    GmacMmcRx512OctInt        = 0x00008000,        /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value    */
-    GmacMmcRx256OctInt        = 0x00004000,        /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value        */
-    GmacMmcRx128OctInt        = 0x00002000,        /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value        */
-    GmacMmcRx65OctInt        = 0x00001000,        /* set when GmacMmcRx65To127OctetsG counter reaches half of max value        */
-    GmacMmcRx64OctInt        = 0x00000800,        /* set when GmacMmcRx64OctetsGb counter reaches half of max value        */
-    GmacMmcRxOverSizeInt        = 0x00000400,        /* set when GmacMmcRxOverSizeG counter reaches half of max value        */
-    GmacMmcRxUnderSizeInt        = 0x00000200,        /* set when GmacMmcRxUnderSizeG counter reaches half of max value        */
-    GmacMmcRxJabberErrorInt        = 0x00000100,        /* set when GmacMmcRxJabberError counter reaches half of max value        */
-    GmacMmcRxRuntErrorInt        = 0x00000080,        /* set when GmacMmcRxRuntError counter reaches half of max value        */
+    GmacMmcRxLengthErrorInt       = 0x00040000,        /* set when GmacMmcRxLengthError counter reaches half of max value        */
+    GmacMmcRxUcFramesInt          = 0x00020000,        /* set when GmacMmcRxUcFramesG counter reaches half of max value        */
+    GmacMmcRx1024OctInt           = 0x00010000,        /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value    */
+    GmacMmcRx512OctInt            = 0x00008000,        /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value    */
+    GmacMmcRx256OctInt            = 0x00004000,        /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value        */
+    GmacMmcRx128OctInt            = 0x00002000,        /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value        */
+    GmacMmcRx65OctInt             = 0x00001000,        /* set when GmacMmcRx65To127OctetsG counter reaches half of max value        */
+    GmacMmcRx64OctInt             = 0x00000800,        /* set when GmacMmcRx64OctetsGb counter reaches half of max value        */
+    GmacMmcRxOverSizeInt          = 0x00000400,        /* set when GmacMmcRxOverSizeG counter reaches half of max value        */
+    GmacMmcRxUnderSizeInt         = 0x00000200,        /* set when GmacMmcRxUnderSizeG counter reaches half of max value        */
+    GmacMmcRxJabberErrorInt       = 0x00000100,        /* set when GmacMmcRxJabberError counter reaches half of max value        */
+    GmacMmcRxRuntErrorInt         = 0x00000080,        /* set when GmacMmcRxRuntError counter reaches half of max value        */
     GmacMmcRxAlignErrorInt        = 0x00000040,        /* set when GmacMmcRxAlignError counter reaches half of max value        */
-    GmacMmcRxCrcErrorInt        = 0x00000020,        /* set when GmacMmcRxCrcError counter reaches half of max value            */
-    GmacMmcRxMcFramesInt        = 0x00000010,        /* set when GmacMmcRxMcFramesG counter reaches half of max value        */
-    GmacMmcRxBcFramesInt        = 0x00000008,        /* set when GmacMmcRxBcFramesG counter reaches half of max value        */
-    GmacMmcRxOctetGInt        = 0x00000004,        /* set when GmacMmcRxOctetCountG counter reaches half of max value        */
-    GmacMmcRxOctetGbInt        = 0x00000002,        /* set when GmacMmcRxOctetCountGb counter reaches half of max value        */
-    GmacMmcRxFrameInt        = 0x00000001,        /* set when GmacMmcRxFrameCountGb counter reaches half of max value        */
+    GmacMmcRxCrcErrorInt          = 0x00000020,        /* set when GmacMmcRxCrcError counter reaches half of max value            */
+    GmacMmcRxMcFramesInt          = 0x00000010,        /* set when GmacMmcRxMcFramesG counter reaches half of max value        */
+    GmacMmcRxBcFramesInt          = 0x00000008,        /* set when GmacMmcRxBcFramesG counter reaches half of max value        */
+    GmacMmcRxOctetGInt            = 0x00000004,        /* set when GmacMmcRxOctetCountG counter reaches half of max value        */
+    GmacMmcRxOctetGbInt           = 0x00000002,        /* set when GmacMmcRxOctetCountGb counter reaches half of max value        */
+    GmacMmcRxFrameInt             = 0x00000001,        /* set when GmacMmcRxFrameCountGb counter reaches half of max value        */
 };
 
 enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
 {
 
-    GmacMmcTxVlanInt        = 0x01000000,        /* set when GmacMmcTxVlanFramesG counter reaches half of max value        */
+    GmacMmcTxVlanInt              = 0x01000000,        /* set when GmacMmcTxVlanFramesG counter reaches half of max value        */
     GmacMmcTxPauseFrameInt        = 0x00800000,        /* set when GmacMmcTxPauseFrames counter reaches half of max value        */
-    GmacMmcTxExessDefInt        = 0x00400000,        /* set when GmacMmcTxExessDef counter reaches half of max value            */
-    GmacMmcTxFrameInt        = 0x00200000,        /* set when GmacMmcTxFrameCount counter reaches half of max value        */
-    GmacMmcTxOctetInt        = 0x00100000,        /* set when GmacMmcTxOctetCountG counter reaches half of max value        */
-    GmacMmcTxCarrierErrorInt    = 0x00080000,        /* set when GmacMmcTxCarrierError counter reaches half of max value        */
-    GmacMmcTxExessColInt        = 0x00040000,        /* set when GmacMmcTxExessCol counter reaches half of max value            */
-    GmacMmcTxLateColInt        = 0x00020000,        /* set when GmacMmcTxLateCol counter reaches half of max value            */
-    GmacMmcTxDeferredInt        = 0x00010000,        /* set when GmacMmcTxDeferred counter reaches half of max value            */
-    GmacMmcTxMultiColInt        = 0x00008000,        /* set when GmacMmcTxMultiColG counter reaches half of max value        */
-    GmacMmcTxSingleCol        = 0x00004000,        /* set when GmacMmcTxSingleColG    counter reaches half of max value        */
+    GmacMmcTxExessDefInt          = 0x00400000,        /* set when GmacMmcTxExessDef counter reaches half of max value            */
+    GmacMmcTxFrameInt             = 0x00200000,        /* set when GmacMmcTxFrameCount counter reaches half of max value        */
+    GmacMmcTxOctetInt             = 0x00100000,        /* set when GmacMmcTxOctetCountG counter reaches half of max value        */
+    GmacMmcTxCarrierErrorInt      = 0x00080000,        /* set when GmacMmcTxCarrierError counter reaches half of max value        */
+    GmacMmcTxExessColInt          = 0x00040000,        /* set when GmacMmcTxExessCol counter reaches half of max value            */
+    GmacMmcTxLateColInt           = 0x00020000,        /* set when GmacMmcTxLateCol counter reaches half of max value            */
+    GmacMmcTxDeferredInt          = 0x00010000,        /* set when GmacMmcTxDeferred counter reaches half of max value            */
+    GmacMmcTxMultiColInt          = 0x00008000,        /* set when GmacMmcTxMultiColG counter reaches half of max value        */
+    GmacMmcTxSingleCol            = 0x00004000,        /* set when GmacMmcTxSingleColG    counter reaches half of max value        */
     GmacMmcTxUnderFlowErrorInt    = 0x00002000,        /* set when GmacMmcTxUnderFlowError counter reaches half of max value        */
-    GmacMmcTxBcFramesGbInt         = 0x00001000,        /* set when GmacMmcTxBcFramesGb    counter reaches half of max value        */
-    GmacMmcTxMcFramesGbInt         = 0x00000800,        /* set when GmacMmcTxMcFramesGb    counter reaches half of max value        */
-    GmacMmcTxUcFramesInt         = 0x00000400,        /* set when GmacMmcTxUcFramesGb counter reaches half of max value        */
-    GmacMmcTx1024OctInt         = 0x00000200,        /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value    */
-    GmacMmcTx512OctInt         = 0x00000100,        /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value    */
-    GmacMmcTx256OctInt         = 0x00000080,        /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value        */
-    GmacMmcTx128OctInt         = 0x00000040,        /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value        */
-    GmacMmcTx65OctInt         = 0x00000020,        /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value        */
-    GmacMmcTx64OctInt         = 0x00000010,        /* set when GmacMmcTx64OctetsGb    counter reaches half of max value        */
-    GmacMmcTxMcFramesInt         = 0x00000008,        /* set when GmacMmcTxMcFramesG counter reaches half of max value        */
-    GmacMmcTxBcFramesInt         = 0x00000004,        /* set when GmacMmcTxBcFramesG counter reaches half of max value        */
-    GmacMmcTxFrameGbInt         = 0x00000002,        /* set when GmacMmcTxFrameCountGb counter reaches half of max value        */
-    GmacMmcTxOctetGbInt         = 0x00000001,        /* set when GmacMmcTxOctetCountGb counter reaches half of max value        */
-    
+    GmacMmcTxBcFramesGbInt        = 0x00001000,        /* set when GmacMmcTxBcFramesGb    counter reaches half of max value        */
+    GmacMmcTxMcFramesGbInt        = 0x00000800,        /* set when GmacMmcTxMcFramesGb    counter reaches half of max value        */
+    GmacMmcTxUcFramesInt          = 0x00000400,        /* set when GmacMmcTxUcFramesGb counter reaches half of max value        */
+    GmacMmcTx1024OctInt           = 0x00000200,        /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value    */
+    GmacMmcTx512OctInt            = 0x00000100,        /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value    */
+    GmacMmcTx256OctInt            = 0x00000080,        /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value        */
+    GmacMmcTx128OctInt            = 0x00000040,        /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value        */
+    GmacMmcTx65OctInt             = 0x00000020,        /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value        */
+    GmacMmcTx64OctInt             = 0x00000010,        /* set when GmacMmcTx64OctetsGb    counter reaches half of max value        */
+    GmacMmcTxMcFramesInt          = 0x00000008,        /* set when GmacMmcTxMcFramesG counter reaches half of max value        */
+    GmacMmcTxBcFramesInt          = 0x00000004,        /* set when GmacMmcTxBcFramesG counter reaches half of max value        */
+    GmacMmcTxFrameGbInt           = 0x00000002,        /* set when GmacMmcTxFrameCountGb counter reaches half of max value        */
+    GmacMmcTxOctetGbInt           = 0x00000001,        /* set when GmacMmcTxOctetCountGb counter reaches half of max value        */
 };
 
 
@@ -1385,45 +1359,40 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
 
 enum GmacPmtCtrlStatusBitDefinition
 {
-    GmacPmtFrmFilterPtrReset    = 0x80000000,        /* when set remote wake-up frame filter register pointer to 3'b000 */
-    GmacPmtGlobalUnicast        = 0x00000200,        /* When set enables any unicast packet to be a wake-up frame       */
+    GmacPmtFrmFilterPtrReset      = 0x80000000,        /* when set remote wake-up frame filter register pointer to 3'b000 */
+    GmacPmtGlobalUnicast          = 0x00000200,        /* When set enables any unicast packet to be a wake-up frame       */
     GmacPmtWakeupFrameReceived    = 0x00000040,        /* Wake up frame received                       */
-    GmacPmtMagicPktReceived        = 0x00000020,        /* Magic Packet received                       */
-    GmacPmtWakeupFrameEnable    = 0x00000004,        /* Wake-up frame enable                           */
-    GmacPmtMagicPktEnable        = 0x00000002,        /* Magic packet enable                           */
-    GmacPmtPowerDown        = 0x00000001,        /* Power Down                               */
+    GmacPmtMagicPktReceived       = 0x00000020,        /* Magic Packet received                       */
+    GmacPmtWakeupFrameEnable      = 0x00000004,        /* Wake-up frame enable                           */
+    GmacPmtMagicPktEnable         = 0x00000002,        /* Magic packet enable                           */
+    GmacPmtPowerDown              = 0x00000001,        /* Power Down                               */
 };
 
-
-
-
 /**********************************************************
  * IEEE 1588-2008 Precision Time Protocol (PTP) Support 
  **********************************************************/
 enum PTPMessageType
 {
-    SYNC               = 0x0,
-    Delay_Req           = 0x1,
-    Pdelay_Req             = 0x2,
-    Pdelay_Resp            = 0x3,
-    Follow_up              = 0x8,
-    Delay_Resp             = 0x9,
-    Pdelay_Resp_Follow_Up  = 0xA,
-    Announce               = 0xB,
-    Signaling              = 0xC,
-    Management             = 0xD,
+    SYNC                          = 0x0,
+    Delay_Req                     = 0x1,
+    Pdelay_Req                    = 0x2,
+    Pdelay_Resp                   = 0x3,
+    Follow_up                     = 0x8,
+    Delay_Resp                    = 0x9,
+    Pdelay_Resp_Follow_Up         = 0xA,
+    Announce                      = 0xB,
+    Signaling                     = 0xC,
+    Management                    = 0xD,
 };
 
-
-
 typedef struct TimeStampStruct    
 { 
-  u32   TSversion;      /* PTP Version 1 or PTP version2                                                                          */
-  u32   TSmessagetype;  /* Message type associated with this time stamp                                                           */                              
+    u32   TSversion;      /* PTP Version 1 or PTP version2                                                                          */
+    u32   TSmessagetype;  /* Message type associated with this time stamp                                                           */                              
 
-  u16   TShighest16;    /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit          */
-  u32   TSupper32;      /* Most significant 32 bit time stamp value                                  */
-  u32   TSlower32;      /* Least Significat 32 bit time stamp value                                  */
+    u16   TShighest16;    /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit          */
+    u32   TSupper32;      /* Most significant 32 bit time stamp value                                  */
+    u32   TSlower32;      /* Least Significat 32 bit time stamp value                                  */
 
 } TimeStamp;
 
@@ -1441,9 +1410,9 @@ typedef struct TimeStampStruct
 /* GmacTSControl  = 0x0700,   Controls the Timestamp update logic  : only when IEEE 1588 time stamping is enabled in corekit         */
 enum GmacTSControlReg
 {
-  GmacTSENMACADDR      = 0x00040000,     /* Enable Mac Addr for PTP filtering     18            RW         0     */
+    GmacTSENMACADDR        = 0x00040000,     /* Enable Mac Addr for PTP filtering     18            RW         0     */
   
-  GmacTSCLKTYPE          = 0x00030000,     /* Select the type of clock node         17:16         RW         00    */
+    GmacTSCLKTYPE          = 0x00030000,     /* Select the type of clock node         17:16         RW         00    */
   /*
       TSCLKTYPE        TSMSTRENA      TSEVNTENA         Messages for wihich TS snapshot is taken
        00/01                X             0              SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP
@@ -1454,40 +1423,40 @@ enum GmacTSControlReg
         11                  NA            0              SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP
         11                  NA            1              SYNC, PDELAY_REQ, PDELAY_RESP        
   */
-  GmacTSOrdClk          = 0x00000000,        /* 00=> Ordinary clock*/
-  GmacTSBouClk          = 0x00010000,        /* 01=> Boundary clock*/
-  GmacTSEtoEClk          = 0x00020000,        /* 10=> End-to-End transparent clock*/
-  GmacTSPtoPClk          = 0x00030000,        /* 11=> P-to-P transparent clock*/
+    GmacTSOrdClk           = 0x00000000,        /* 00=> Ordinary clock*/
+    GmacTSBouClk           = 0x00010000,        /* 01=> Boundary clock*/
+    GmacTSEtoEClk          = 0x00020000,        /* 10=> End-to-End transparent clock*/
+    GmacTSPtoPClk          = 0x00030000,        /* 11=> P-to-P transparent clock*/
 
-  GmacTSMSTRENA          = 0x00008000,        /* Ena TS Snapshot for Master Messages   15            RW         0     */
-  GmacTSEVNTENA          = 0x00004000,        /* Ena TS Snapshot for Event Messages    14            RW         0     */
-  GmacTSIPV4ENA          = 0x00002000,        /* Ena TS snapshot for IPv4              13            RW         1     */
-  GmacTSIPV6ENA          = 0x00001000,        /* Ena TS snapshot for IPv6              12            RW         0     */
-  GmacTSIPENA          = 0x00000800,        /* Ena TS snapshot for PTP over E'net    11            RW         0     */
-  GmacTSVER2ENA          = 0x00000400,        /* Ena PTP snooping for version 2        10            RW         0     */
+    GmacTSMSTRENA          = 0x00008000,        /* Ena TS Snapshot for Master Messages   15            RW         0     */
+    GmacTSEVNTENA          = 0x00004000,        /* Ena TS Snapshot for Event Messages    14            RW         0     */
+    GmacTSIPV4ENA          = 0x00002000,        /* Ena TS snapshot for IPv4              13            RW         1     */
+    GmacTSIPV6ENA          = 0x00001000,        /* Ena TS snapshot for IPv6              12            RW         0     */
+    GmacTSIPENA            = 0x00000800,        /* Ena TS snapshot for PTP over E'net    11            RW         0     */
+    GmacTSVER2ENA          = 0x00000400,        /* Ena PTP snooping for version 2        10            RW         0     */
 
-  GmacTSCTRLSSR           = 0x00000200,      /* Digital or Binary Rollover           9             RW         0     */
+    GmacTSCTRLSSR          = 0x00000200,      /* Digital or Binary Rollover           9             RW         0     */
 
-  GmacTSENALL             = 0x00000100,      /* Enable TS fro all frames (Ver2 only) 8             RW         0     */
+    GmacTSENALL            = 0x00000100,      /* Enable TS fro all frames (Ver2 only) 8             RW         0     */
 
-  GmacTSADDREG          = 0x00000020,         /* Addend Register Update             5             RW_SC      0     */
-  GmacTSUPDT          = 0x00000008,         /* Time Stamp Update             3             RW_SC      0     */
-  GmacTSINT          = 0x00000004,         /* Time Atamp Initialize             2             RW_SC      0     */
+    GmacTSADDREG           = 0x00000020,         /* Addend Register Update             5             RW_SC      0     */
+    GmacTSUPDT             = 0x00000008,         /* Time Stamp Update             3             RW_SC      0     */
+    GmacTSINT              = 0x00000004,         /* Time Atamp Initialize             2             RW_SC      0     */
  
-  GmacTSTRIG          = 0x00000010,         /* Time stamp interrupt Trigger Enable  4             RW_SC      0     */
+    GmacTSTRIG             = 0x00000010,         /* Time stamp interrupt Trigger Enable  4             RW_SC      0     */
 
-  GmacTSCFUPDT          = 0x00000002,         /* Time Stamp Fine/Coarse             1             RW         0     */
-  GmacTSCUPDTCoarse      = 0x00000000,         /* 0=> Time Stamp update method is coarse                        */
-  GmacTSCUPDTFine      = 0x00000002,         /* 1=> Time Stamp update method is fine                    */
+    GmacTSCFUPDT           = 0x00000002,         /* Time Stamp Fine/Coarse             1             RW         0     */
+    GmacTSCUPDTCoarse      = 0x00000000,         /* 0=> Time Stamp update method is coarse                        */
+    GmacTSCUPDTFine        = 0x00000002,         /* 1=> Time Stamp update method is fine                    */
 
-  GmacTSENA          = 0x00000001,      /* Time Stamp Enable                    0             RW         0     */
+    GmacTSENA              = 0x00000001,      /* Time Stamp Enable                    0             RW         0     */
 };
 
 
 /*  GmacTSSubSecIncr           = 0x0704,   8 bit value by which sub second register is incremented     : only when IEEE 1588 time stamping without external timestamp input */
 enum GmacTSSubSecIncrReg
 {
-  GmacSSINCMsk            = 0x000000FF,       /* Only Lower 8 bits are valid bits     7:0           RW         00    */
+  GmacSSINCMsk             = 0x000000FF,       /* Only Lower 8 bits are valid bits     7:0           RW         00    */
 };
 
 /*  GmacTSLow         = 0x070C,   Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */
@@ -1516,7 +1485,6 @@ enum GmacTSStatusReg
   GmacTSSecondsOverflow   = 0x00000001,     /* Time Stamp Seconds Overflow             0             RO          0    */
 };            
 
-
 /**********************************************************
  * Time stamp related functions
  **********************************************************/
diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_plat.h b/bsp/ls2kdev/drivers/net/synopGMAC_plat.h
index 9bbcc49ef0..3b6eaca197 100644
--- a/bsp/ls2kdev/drivers/net/synopGMAC_plat.h
+++ b/bsp/ls2kdev/drivers/net/synopGMAC_plat.h
@@ -239,4 +239,4 @@ static bool  synopGMACCheckBits(u64 RegBase, u32 RegOffset, u32 BitPos)
     }
 }
 
-#endif
\ No newline at end of file
+#endif
diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c
index cfb4c6bb3c..54d38d0d3f 100644
--- a/libcpu/mips/gs264/cache.c
+++ b/libcpu/mips/gs264/cache.c
@@ -67,4 +67,4 @@ rt_base_t rt_hw_cpu_icache_status(void)
 rt_base_t rt_hw_cpu_dcache_status(void)
 {
     return 0;
-}
\ No newline at end of file
+}
diff --git a/libcpu/mips/gs264/cpuinit_gcc.S b/libcpu/mips/gs264/cpuinit_gcc.S
index bd84663350..592fedd88a 100644
--- a/libcpu/mips/gs264/cpuinit_gcc.S
+++ b/libcpu/mips/gs264/cpuinit_gcc.S
@@ -19,8 +19,8 @@
 
     .globl  rt_cpu_early_init
 rt_cpu_early_init:
-     mfc0	t0, CP0_CONFIG
-     ori	t0, 3
-     mtc0	t0, CP0_CONFIG
+     mfc0    t0, CP0_CONFIG
+     ori     t0, 3
+     mtc0    t0, CP0_CONFIG
      ehb
-     jr	ra
\ No newline at end of file
+     jr      ra
diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c
index bfc694ab45..7bed69596a 100644
--- a/libcpu/mips/gs264/mips_mmu.c
+++ b/libcpu/mips/gs264/mips_mmu.c
@@ -5,7 +5,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2020-07-26 	  lizhirui 	   the first version
+ * 2020-07-26     lizhirui     the first version
  */
 
 #include <string.h>
@@ -205,18 +205,18 @@ uint64_t mmu_tlb_get_bad_vaddr()
 
 void tlb_dump()
 {
-	uint32_t max_index = mmu_get_max_tlb_index();
-	//uint32_t max_index = 10;
-	uint32_t entry;
-	tlb_item_t tlb_item;
-
-	for(entry = 0;entry <= max_index;entry++)
-	{
-		mmu_tlb_read(entry,&tlb_item);
-		//mmu_tlb_write_indexed(entry,&tlb_item);
-		//mmu_tlb_read(entry,&tlb_item);
-		rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12);
-		rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c);
-		rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c);
-	}
-}
\ No newline at end of file
+    uint32_t max_index = mmu_get_max_tlb_index();
+    //uint32_t max_index = 10;
+    uint32_t entry;
+    tlb_item_t tlb_item;
+
+    for(entry = 0;entry <= max_index;entry++)
+    {
+        mmu_tlb_read(entry,&tlb_item);
+        //mmu_tlb_write_indexed(entry,&tlb_item);
+        //mmu_tlb_read(entry,&tlb_item);
+        rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12);
+        rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c);
+        rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c);
+    }
+}
diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h
index c0b33ecf89..fcbcef3621 100644
--- a/libcpu/mips/gs264/mips_mmu.h
+++ b/libcpu/mips/gs264/mips_mmu.h
@@ -5,96 +5,95 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2020-07-26 	  lizhirui 	   the first version
+ * 2020-07-26     lizhirui     the first version
  */
-
 #ifndef __MIPS_MMU_H__
 #define __MIPS_MMU_H__
 
-    typedef enum cpu_mode_t
-    {
-        CPU_MODE_KERNEL = 0x00,
-        CPU_MODE_SUPERVISOR = 0x01,
-        CPU_MODE_USER = 0x02
-    }cpu_mode_t;
+typedef enum cpu_mode_t
+{
+    CPU_MODE_KERNEL = 0x00,
+    CPU_MODE_SUPERVISOR = 0x01,
+    CPU_MODE_USER = 0x02
+}cpu_mode_t;
 
-    typedef enum page_mask_enum_t
-    {
-        PAGE_MASK_4KB = 0x00,
-        PAGE_MASK_16KB = 0x03,
-        PAGE_MASK_64KB = 0x0F,
-        PAGE_MASK_256KB = 0x3F,
-        PAGE_MASK_1MB = 0xFF,
-        PAGE_MASK_4MB = 0x3FF,
-        PAGE_MASK_16MB = 0xFFF,
-        PAGE_MASK_64MB = 0x3FFF,
-        PAGE_MASK_256MB = 0xFFFF,
-        PAGE_MASK_1GB = 0x3FFFF
-    }page_mask_enum_t;
+typedef enum page_mask_enum_t
+{
+    PAGE_MASK_4KB = 0x00,
+    PAGE_MASK_16KB = 0x03,
+    PAGE_MASK_64KB = 0x0F,
+    PAGE_MASK_256KB = 0x3F,
+    PAGE_MASK_1MB = 0xFF,
+    PAGE_MASK_4MB = 0x3FF,
+    PAGE_MASK_16MB = 0xFFF,
+    PAGE_MASK_64MB = 0x3FFF,
+    PAGE_MASK_256MB = 0xFFFF,
+    PAGE_MASK_1GB = 0x3FFFF
+}page_mask_enum_t;
 
-    typedef struct page_mask_t
-    {
-        uint64_t : 11;
-        uint64_t : 2;
-        uint64_t mask : 18;
-        uint64_t : 33;
-    }page_mask_t;
+typedef struct page_mask_t
+{
+    uint64_t : 11;
+    uint64_t : 2;
+    uint64_t mask : 18;
+    uint64_t : 33;
+}page_mask_t;
 
-    typedef struct entry_lo_t
-    {
-        uint64_t g : 1;
-        uint64_t v : 1;
-        uint64_t d : 1;
-        uint64_t c : 3;
-        uint64_t pfn : 24;
-        uint64_t pfnx : 3;
-        uint64_t : 29;
-        uint64_t xi : 1;
-        uint64_t ri : 1;
-    }entry_lo_t;
+typedef struct entry_lo_t
+{
+    uint64_t g : 1;
+    uint64_t v : 1;
+    uint64_t d : 1;
+    uint64_t c : 3;
+    uint64_t pfn : 24;
+    uint64_t pfnx : 3;
+    uint64_t : 29;
+    uint64_t xi : 1;
+    uint64_t ri : 1;
+}entry_lo_t;
 
-    typedef struct entry_hi_t
-    {
-        uint64_t asid : 8;
-        uint64_t : 5;
-        uint64_t vpn2 : 27;
-        uint64_t : 22;
-        uint64_t r : 2;
-    }entry_hi_t;
+typedef struct entry_hi_t
+{
+    uint64_t asid : 8;
+    uint64_t : 5;
+    uint64_t vpn2 : 27;
+    uint64_t : 22;
+    uint64_t r : 2;
+}entry_hi_t;
 
-    typedef struct tlb_item_t
-    {
-        entry_lo_t entry_lo[2];
-        entry_hi_t entry_hi;
-        page_mask_t page_mask;
-    }tlb_item_t;
+typedef struct tlb_item_t
+{
+    entry_lo_t entry_lo[2];
+    entry_hi_t entry_hi;
+    page_mask_t page_mask;
+}tlb_item_t;
 
-    #define read_c0_diag()		__read_32bit_c0_register($22, 0)
-    #define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
-    #define read_c0_badvaddr()  __read_64bit_c0_register($8, 0)
-    #define read_c0_random()  __read_32bit_c0_register($1, 0)
+#define read_c0_diag()        __read_32bit_c0_register($22, 0)
+#define write_c0_diag(val)    __write_32bit_c0_register($22, 0, val)
+#define read_c0_badvaddr()    __read_64bit_c0_register($8, 0)
+#define read_c0_random()      __read_32bit_c0_register($1, 0)
 
-    #define reg_type_convert(variable,new_type) *((new_type *)(&variable))
-    #define lowbit(x) ((x) & (-(x)))
+#define reg_type_convert(variable,new_type) *((new_type *)(&variable))
+#define lowbit(x) ((x) & (-(x)))
 
-    void mmu_init();
-    void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
-    cpu_mode_t mmu_get_cpu_mode();
-    void mmu_clear_tlb();
-    void mmu_clear_itlb();
-    uint32_t mmu_get_max_tlb_index();
-    void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
-    void mmu_tlb_write_random(tlb_item_t *tlb_item);
-    void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
-    uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
-    void mmu_tlb_item_init(tlb_item_t *tlb_item);
-    void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
-    uint32_t mmu_tlb_get_random();
-    uint32_t mmu_tlb_get_index();
-    void mmu_tlb_set_index(uint32_t index);
-    uint32_t mmu_tlb_is_matched();
-    uint64_t mmu_tlb_get_bad_vaddr();
+void mmu_init();
+void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
+cpu_mode_t mmu_get_cpu_mode();
+void mmu_clear_tlb();
+void mmu_clear_itlb();
+uint32_t mmu_get_max_tlb_index();
+void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
+void mmu_tlb_write_random(tlb_item_t *tlb_item);
+void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
+uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
+void mmu_tlb_item_init(tlb_item_t *tlb_item);
+void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
+uint32_t mmu_tlb_get_random();
+uint32_t mmu_tlb_get_index();
+void mmu_tlb_set_index(uint32_t index);
+uint32_t mmu_tlb_is_matched();
+uint64_t mmu_tlb_get_bad_vaddr();
 
-    void tlb_dump();
+void tlb_dump();
 
 #endif
\ No newline at end of file
diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c
index f6c73095d9..b2aed120ae 100644
--- a/libcpu/mips/gs264/mipscfg.c
+++ b/libcpu/mips/gs264/mipscfg.c
@@ -12,15 +12,15 @@
 
 mips32_core_cfg_t g_mips_core =
 {
-    64,		/* icache_line_size */
-    128,	/* icache_lines_per_way */
-    4,		/* icache_ways */
+    64,        /* icache_line_size */
+    128,       /* icache_lines_per_way */
+    4,         /* icache_ways */
     32768,
-    64,		/* dcache_line_size */
-    128,	/* dcache_lines_per_way */
-    4,		/* dcache_ways */
+    64,        /* dcache_line_size */
+    128,       /* dcache_lines_per_way */
+    4,         /* dcache_ways */
     32768,
-    64,		/* max_tlb_entries */
+    64,        /* max_tlb_entries */
 };
 
 static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c
index b08bdf4c65..b5bedace50 100644
--- a/libcpu/mips/gs264/mmu.c
+++ b/libcpu/mips/gs264/mmu.c
@@ -21,15 +21,15 @@ void *current_mmu_table = RT_NULL;
 
 void *mmu_table_get()
 {
-	return current_mmu_table;
+    return current_mmu_table;
 }
 
 void switch_mmu(void *mmu_table)
 {
-	current_mmu_table = mmu_table;
+    current_mmu_table = mmu_table;
 
     mmu_clear_tlb();
-	mmu_clear_itlb();
+    mmu_clear_itlb();
 }
 
 /* dump 2nd level page table */
@@ -476,7 +476,7 @@ static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, si
 static void rt_hw_cpu_tlb_invalidate(void)
 {
     mmu_clear_tlb();
-	mmu_clear_itlb();
+    mmu_clear_itlb();
 }
 
 #ifdef RT_USING_USERSPACE
diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h
index f2d4d11bc3..2472bf975f 100644
--- a/libcpu/mips/gs264/mmu.h
+++ b/libcpu/mips/gs264/mmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,21 +14,21 @@
 #include <rtthread.h>
 
 #define DESC_SEC       (0x2)
-#define MEMWBWA        ((1<<12)|(3<<2))     /* write back, write allocate */
-#define MEMWB          (3<<2)  /* write back, no write allocate */
-#define MEMWT          (2<<2)  /* write through, no write allocate */
-#define SHAREDEVICE    (1<<2)  /* shared device */
-#define STRONGORDER    (0<<2)  /* strong ordered */
-#define XN             (1<<4)  /* eXecute Never */
+#define MEMWBWA        ((1<<12)|(3<<2))      /* write back, write allocate */
+#define MEMWB          (3<<2)                /* write back, no write allocate */
+#define MEMWT          (2<<2)                /* write through, no write allocate */
+#define SHAREDEVICE    (1<<2)                /* shared device */
+#define STRONGORDER    (0<<2)                /* strong ordered */
+#define XN             (1<<4)                /* execute Never */
 #ifdef RT_USING_USERSPACE
-#define AP_RW          (1<<10) /* supervisor=RW, user=No */
-#define AP_RO          ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */
+#define AP_RW          (1<<10)               /* supervisor=RW, user=No */
+#define AP_RO          ((1<<10) |(1 << 15))  /* supervisor=RW, user=No */
 #else
-#define AP_RW          (3<<10) /* supervisor=RW, user=RW */
-#define AP_RO          ((2<<10) /* supervisor=RW, user=RO */
+#define AP_RW          (3<<10)               /* supervisor=RW, user=RW */
+#define AP_RO          ((2<<10)              /* supervisor=RW, user=RO */
 #endif
 
-#define SHARED         (1<<16) /* shareable */
+#define SHARED         (1<<16)               /* shareable */
 
 #define DOMAIN_FAULT   (0x0)
 #define DOMAIN_CHK     (0x1)
-- 
cgit v1.3.1


From a8928c881ed935a1e2a45bb02bd0b2a7fe8d45d4 Mon Sep 17 00:00:00 2001
From: michael <michael5hzg@gmail.com>
Date: Mon, 14 Sep 2020 11:10:44 +0800
Subject: MIPS:fix the RT_EXCEPTION_MAX value

from <see mips run> know that cp0_cause's ExcCode have 5 bit filed and
the max exception is 32.
---
 libcpu/mips/common/exception.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index 94be475878..3da8ecead6 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -74,7 +74,7 @@ void rt_hw_interrupt_enable(rt_base_t level)
 /**
  * exception handle table
  */
-#define RT_EXCEPTION_MAX 31
+#define RT_EXCEPTION_MAX 32
 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
 
 /**
-- 
cgit v1.3.1


From 7f330c7b79ee1d3b2b5c167d67ec6773887b57c3 Mon Sep 17 00:00:00 2001
From: GFWisshit <qq979818120@gmail.com>
Date: Fri, 16 Oct 2020 11:38:52 +0800
Subject: Add support for architecture sparc-v8 and soc bm3803.

---
 bsp/bm3803/.config                   | 456 ++++++++++++++++++++++++
 bsp/bm3803/Kconfig                   |  38 ++
 bsp/bm3803/SConscript                |  14 +
 bsp/bm3803/SConstruct                |  31 ++
 bsp/bm3803/applications/SConscript   |  11 +
 bsp/bm3803/applications/board.c      |  58 +++
 bsp/bm3803/applications/board.h      |  24 ++
 bsp/bm3803/applications/main.c       |   9 +
 bsp/bm3803/bm3803.lds                |  90 +++++
 bsp/bm3803/drivers/SConscript        |  22 ++
 bsp/bm3803/drivers/uart.c            | 174 +++++++++
 bsp/bm3803/drivers/uart.h            |  20 ++
 bsp/bm3803/drivers/uart_reg.h        |  12 +
 bsp/bm3803/rtconfig.h                | 156 ++++++++
 bsp/bm3803/rtconfig.py               |  43 +++
 libcpu/sparc-v8/SConscript           |  16 +
 libcpu/sparc-v8/bm3803/SConscript    |  17 +
 libcpu/sparc-v8/bm3803/bm3803.h      |  99 ++++++
 libcpu/sparc-v8/bm3803/context_gcc.S |  83 +++++
 libcpu/sparc-v8/bm3803/interrupt.c   |  90 +++++
 libcpu/sparc-v8/bm3803/interrupt.h   |  20 ++
 libcpu/sparc-v8/bm3803/stack.c       |  63 ++++
 libcpu/sparc-v8/bm3803/start_gcc.S   | 664 +++++++++++++++++++++++++++++++++++
 libcpu/sparc-v8/bm3803/trap.c        |  28 ++
 libcpu/sparc-v8/bm3803/vector_gcc.S  | 168 +++++++++
 libcpu/sparc-v8/common/SConscript    |  23 ++
 26 files changed, 2429 insertions(+)
 create mode 100644 bsp/bm3803/.config
 create mode 100644 bsp/bm3803/Kconfig
 create mode 100644 bsp/bm3803/SConscript
 create mode 100644 bsp/bm3803/SConstruct
 create mode 100644 bsp/bm3803/applications/SConscript
 create mode 100644 bsp/bm3803/applications/board.c
 create mode 100644 bsp/bm3803/applications/board.h
 create mode 100644 bsp/bm3803/applications/main.c
 create mode 100644 bsp/bm3803/bm3803.lds
 create mode 100644 bsp/bm3803/drivers/SConscript
 create mode 100644 bsp/bm3803/drivers/uart.c
 create mode 100644 bsp/bm3803/drivers/uart.h
 create mode 100644 bsp/bm3803/drivers/uart_reg.h
 create mode 100644 bsp/bm3803/rtconfig.h
 create mode 100644 bsp/bm3803/rtconfig.py
 create mode 100644 libcpu/sparc-v8/SConscript
 create mode 100644 libcpu/sparc-v8/bm3803/SConscript
 create mode 100644 libcpu/sparc-v8/bm3803/bm3803.h
 create mode 100644 libcpu/sparc-v8/bm3803/context_gcc.S
 create mode 100644 libcpu/sparc-v8/bm3803/interrupt.c
 create mode 100644 libcpu/sparc-v8/bm3803/interrupt.h
 create mode 100644 libcpu/sparc-v8/bm3803/stack.c
 create mode 100644 libcpu/sparc-v8/bm3803/start_gcc.S
 create mode 100644 libcpu/sparc-v8/bm3803/trap.c
 create mode 100644 libcpu/sparc-v8/bm3803/vector_gcc.S
 create mode 100644 libcpu/sparc-v8/common/SConscript

(limited to 'libcpu')

diff --git a/bsp/bm3803/.config b/bsp/bm3803/.config
new file mode 100644
index 0000000000..c062cf4890
--- /dev/null
+++ b/bsp/bm3803/.config
@@ -0,0 +1,456 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=4096
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+CONFIG_RT_USING_DEVICE_OPS=y
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_PPOOL is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+CONFIG_SOC_BM3803=y
+CONFIG_RT_USING_UART1=y
diff --git a/bsp/bm3803/Kconfig b/bsp/bm3803/Kconfig
new file mode 100644
index 0000000000..2e34f6fc57
--- /dev/null
+++ b/bsp/bm3803/Kconfig
@@ -0,0 +1,38 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+    
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example: default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+    
+config ENV_DIR
+    string
+    option env="ENV_ROOT"
+    default "/"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_BM3803
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+config RT_USING_UART1
+    bool "Using RT_USING_UART1"
+    default y
+
diff --git a/bsp/bm3803/SConscript b/bsp/bm3803/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/bm3803/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bm3803/SConstruct b/bsp/bm3803/SConstruct
new file mode 100644
index 0000000000..afa8291469
--- /dev/null
+++ b/bsp/bm3803/SConstruct
@@ -0,0 +1,31 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-bm3803.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/bm3803/applications/SConscript b/bsp/bm3803/applications/SConscript
new file mode 100644
index 0000000000..01eb940dfb
--- /dev/null
+++ b/bsp/bm3803/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bm3803/applications/board.c b/bsp/bm3803/applications/board.c
new file mode 100644
index 0000000000..043fceda03
--- /dev/null
+++ b/bsp/bm3803/applications/board.c
@@ -0,0 +1,58 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <finsh.h>
+
+#include "board.h"
+#include <interrupt.h>
+
+extern int __bss_end;
+
+static void rt_hw_timer_isr(int vector, void* param)
+{
+	rt_tick_increase();
+	/* timer interrupt cleared by hardware */
+}
+
+int rt_hw_timer_init(void)
+{
+	unsigned int counter = 1000000 / RT_TICK_PER_SECOND;
+	volatile struct lregs *regs = (struct lregs*)PREGS;
+    
+    regs->scalercnt = CPU_FREQ / 1000000 - 1;
+    regs->scalerload = CPU_FREQ / 1000000 - 1;
+    regs->timercnt2 = counter - 1;
+    regs->timerload2 = counter - 1;
+
+	rt_hw_interrupt_install(TIMER2_TT, rt_hw_timer_isr, RT_NULL, "tick");
+	rt_hw_interrupt_umask(TIMER2_TT);
+
+	/* start timer */
+	regs->timerctrl2 = 0x7;
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+/**
+ * This function will initialize beaglebone board
+ */
+void rt_hw_board_init(void)
+{
+	rt_system_heap_init((void*)&__bss_end, (void*)&__bss_end + 0x01000000);
+    rt_components_board_init();
+	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
diff --git a/bsp/bm3803/applications/board.h b/bsp/bm3803/applications/board.h
new file mode 100644
index 0000000000..becb93cf3b
--- /dev/null
+++ b/bsp/bm3803/applications/board.h
@@ -0,0 +1,24 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <bm3803.h>
+
+#define CPU_FREQ 90000000
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bm3803/applications/main.c b/bsp/bm3803/applications/main.c
new file mode 100644
index 0000000000..d77e7a2a8b
--- /dev/null
+++ b/bsp/bm3803/applications/main.c
@@ -0,0 +1,9 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(void)
+{
+    printf("hello rt-thread\n");
+    return 0;
+}
diff --git a/bsp/bm3803/bm3803.lds b/bsp/bm3803/bm3803.lds
new file mode 100644
index 0000000000..e8984325c1
--- /dev/null
+++ b/bsp/bm3803/bm3803.lds
@@ -0,0 +1,90 @@
+OUTPUT_ARCH(sparc)
+SECTIONS
+{
+    . = 0x40000000;
+
+    __text_start = .;
+    .text :
+    {
+        *(.vectors)
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);	
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(8);
+    __data_start = .;
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(8);
+    __bss_start = .;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}
diff --git a/bsp/bm3803/drivers/SConscript b/bsp/bm3803/drivers/SConscript
new file mode 100644
index 0000000000..a630c8a7c4
--- /dev/null
+++ b/bsp/bm3803/drivers/SConscript
@@ -0,0 +1,22 @@
+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_LWIP') == False:
+    src_need_remove = ['dm9000.c'] # need remove file list.
+    SrcRemove(src, src_need_remove)
+
+if GetDepend('RT_USING_DFS') == False:
+    src_need_remove = ['sd.c'] # need remove file list.
+    SrcRemove(src, src_need_remove)
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bm3803/drivers/uart.c b/bsp/bm3803/drivers/uart.c
new file mode 100644
index 0000000000..bdfe522958
--- /dev/null
+++ b/bsp/bm3803/drivers/uart.c
@@ -0,0 +1,174 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <board.h>
+#include <interrupt.h>
+#include "uart.h"
+#include "uart_reg.h"
+
+struct bm3803_uart
+{
+    void *uart_base;
+    int irq;
+};
+
+static void bm3803_uart_isr(int tt, void* param)
+{
+    struct bm3803_uart* uart;
+    struct rt_serial_device *serial;
+    struct uart_reg* uart_base;
+
+    serial = (struct rt_serial_device*)param;
+    uart = (struct bm3803_uart *)serial->parent.user_data;
+    uart_base = uart->uart_base;
+    
+    if (uart_base->uartstatus & 0x1)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+}
+
+#define NOT_IMPLEMENTED() RT_ASSERT(0)
+
+static rt_err_t bm3803_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct bm3803_uart* uart;
+    struct uart_reg* uart_base;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct bm3803_uart *)serial->parent.user_data;
+    RT_ASSERT(uart);
+    uart_base = uart->uart_base;
+
+    if (cfg->baud_rate == BAUD_RATE_115200)
+    {
+		uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 115200)) - 5) / 10);
+    }
+    else if (cfg->baud_rate == BAUD_RATE_9600)
+    {
+		uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 9600)) - 5) / 10);
+    }
+    else
+    {
+        NOT_IMPLEMENTED();
+    }
+    
+    uart_base->uartctrl |= 0x3;
+
+    return RT_EOK;
+}
+
+static rt_err_t bm3803_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct bm3803_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct bm3803_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        rt_hw_interrupt_mask(uart->irq);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        rt_hw_interrupt_umask(uart->irq);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int bm3803_putc(struct rt_serial_device *serial, char c)
+{
+    struct bm3803_uart* uart;
+	struct uart_reg* uart_base;
+	
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct bm3803_uart *)serial->parent.user_data;
+    uart_base = uart->uart_base;
+    
+    while (!(uart_base->uartstatus & 0x4));
+    uart_base->uartdata = c;
+
+    return 1;
+}
+
+static int bm3803_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct bm3803_uart* uart;
+    struct uart_reg* uart_base;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct bm3803_uart *)serial->parent.user_data;
+	uart_base = uart->uart_base;
+	
+    ch = -1;
+    if (uart_base->uartstatus & 0x1)
+    {
+        ch = uart_base->uartdata;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops bm3803_uart_ops =
+{
+	bm3803_configure,
+    bm3803_control,
+    bm3803_putc,
+    bm3803_getc,
+};
+
+/* UART device driver structure */
+#ifdef RT_USING_UART1
+struct bm3803_uart uart1 =
+{
+    (void*)UART1_BASE,
+    UART1_TT,
+};
+struct rt_serial_device serial1;
+#endif
+
+int rt_hw_serial_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART1
+	volatile struct lregs *regs = (struct lregs*)PREGS;
+    serial1.ops = &bm3803_uart_ops;
+    serial1.config = config;
+    /* configure gpio direction */
+    regs->piodir |= (1 << 15);
+    regs->piodir &= ~(1 << 14);
+    /* enable RX interrupt */
+    regs->uartctrl1 = 0;
+    regs->uartctrl1 |= 0x4;
+    /* install ISR */
+    rt_hw_interrupt_install(uart1.irq, bm3803_uart_isr, &serial1, "uart1");
+    rt_hw_interrupt_mask(uart1.irq);
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+            &uart1);
+#endif
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_serial_init);
diff --git a/bsp/bm3803/drivers/uart.h b/bsp/bm3803/drivers/uart.h
new file mode 100644
index 0000000000..46a7df5d89
--- /dev/null
+++ b/bsp/bm3803/drivers/uart.h
@@ -0,0 +1,20 @@
+/*
+ * File      : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+int rt_hw_serial_init(void);
+
+#endif
diff --git a/bsp/bm3803/drivers/uart_reg.h b/bsp/bm3803/drivers/uart_reg.h
new file mode 100644
index 0000000000..c0911149df
--- /dev/null
+++ b/bsp/bm3803/drivers/uart_reg.h
@@ -0,0 +1,12 @@
+#ifndef SERIAL_REG_H
+#define SERIAL_REG_H
+
+struct uart_reg
+{
+	unsigned int uartdata;
+	unsigned int uartstatus;
+	unsigned int uartctrl;
+	unsigned int uartscaler;
+};
+
+#endif /* end of include guard: SERIAL_REG_H */
diff --git a/bsp/bm3803/rtconfig.h b/bsp/bm3803/rtconfig.h
new file mode 100644
index 0000000000..001e275191
--- /dev/null
+++ b/bsp/bm3803/rtconfig.h
@@ -0,0 +1,156 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 4096
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_MEMHEAP
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40003
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 4096
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_RB_BUFSZ 64
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define SOC_BM3803
+#define RT_USING_UART1
+
+#endif
diff --git a/bsp/bm3803/rtconfig.py b/bsp/bm3803/rtconfig.py
new file mode 100644
index 0000000000..1a382b4891
--- /dev/null
+++ b/bsp/bm3803/rtconfig.py
@@ -0,0 +1,43 @@
+import os
+
+# toolchains options
+ARCH='sparc-v8'
+CPU='bm3803'
+CROSS_TOOL='gcc'
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM 	= 'gcc'
+    EXEC_PATH 	= r'C:\Users\97981\Downloads\bcc-2.1.1-gcc\bin'
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'sparc-gaisler-elf-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=v8 -nostartfiles'
+    #DEVICE = ' '
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS = DEVICE + ' -Wl,-Map=rtthread-bm3803.map -T bm3803.lds -Ttext=0x40000000'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -Wall'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2 -Wall'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
+                  SIZE + ' $TARGET \n'
diff --git a/libcpu/sparc-v8/SConscript b/libcpu/sparc-v8/SConscript
new file mode 100644
index 0000000000..f6ea13fb91
--- /dev/null
+++ b/libcpu/sparc-v8/SConscript
@@ -0,0 +1,16 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd = GetCurrentDir()
+
+# add common code files
+group = SConscript(os.path.join('common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+
+Return('group')
diff --git a/libcpu/sparc-v8/bm3803/SConscript b/libcpu/sparc-v8/bm3803/SConscript
new file mode 100644
index 0000000000..1e96ff5837
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/SConscript
@@ -0,0 +1,17 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/sparc-v8/bm3803/bm3803.h b/libcpu/sparc-v8/bm3803/bm3803.h
new file mode 100644
index 0000000000..a90663f199
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/bm3803.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+#ifndef __BM3803_H__
+#define __BM3803_H__
+
+struct lregs
+{
+	/* address = 0x80000000 */
+	unsigned int memcfg1;		    /* 0x00 */
+	unsigned int memcfg2;
+	unsigned int memcfg3;
+	unsigned int failaddr;
+
+	unsigned int memstatus;		/* 0x10 */
+	unsigned int cachectrl;
+	unsigned int powerdown;
+	unsigned int writeprot1;
+
+	unsigned int writeprot2;	    /* 0x20 */
+	unsigned int pcr;
+	unsigned int dummy2;
+	unsigned int dummy3;
+
+	unsigned int dummy4;	        /* 0x30 */
+	unsigned int dummy5;
+	unsigned int dummy6;
+	unsigned int dummy7;
+
+	unsigned int timercnt1;		/* 0x40 */
+	unsigned int timerload1;
+	unsigned int timerctrl1;
+	unsigned int wdog;
+
+	unsigned int timercnt2;        /* 0x50 */
+	unsigned int timerload2;
+	unsigned int timerctrl2;
+	unsigned int dummy8;
+
+	unsigned int scalercnt;        /* 0x60 */
+	unsigned int scalerload;
+	unsigned int dummy9;
+	unsigned int dummy10;
+
+	unsigned int uartdata1;        /* 0x70 */
+	unsigned int uartstatus1;
+	unsigned int uartctrl1;
+	unsigned int uartscaler1;
+
+	unsigned int uartdata2;        /* 0x80 */
+	unsigned int uartstatus2;
+	unsigned int uartctrl2;
+	unsigned int uartscaler2;
+
+	unsigned int irqmask;           /* 0x90 */
+	unsigned int irqpend;
+	unsigned int irqforce;
+	unsigned int irqclear;
+
+	unsigned int piodata;            /* 0xA0 */
+	unsigned int piodir;
+	unsigned int pioirq;
+	unsigned int dummy11;
+
+	unsigned int imask2;            /* 0xB0 */
+	unsigned int ipend2;
+	unsigned int istat2;
+	unsigned int dummy12;
+
+	unsigned int dummy13;          /* 0xC0 */
+	unsigned int dcomstatus;
+	unsigned int dcomctrl;
+	unsigned int dcomscaler;
+
+	unsigned int dummy14;	        /* 0xD0 */
+	unsigned int dummy15;
+	unsigned int dummy16;
+	unsigned int dummy17;
+
+	unsigned int uartdata3;         /* 0xE0 */
+	unsigned int uartstatus3;
+	unsigned int uartctrl3;
+	unsigned int uartscaler3;
+};
+
+#define	PREGS 0x80000000
+
+#define UART1_BASE (PREGS + 0x70)
+
+#define TIMER2_TT 0x19
+#define UART1_TT 0x13
+
+#endif
diff --git a/libcpu/sparc-v8/bm3803/context_gcc.S b/libcpu/sparc-v8/bm3803/context_gcc.S
new file mode 100644
index 0000000000..c0344a81d5
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/context_gcc.S
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#define SPARC_PSR_PIL_MASK 0x00000F00
+#define SPARC_PSR_ET_MASK 0x00000020
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+	mov %psr, %o0
+	or %o0, SPARC_PSR_PIL_MASK, %o1
+	mov %o1, %psr
+	nop
+	nop
+	nop
+	retl
+	nop
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+	mov %o0, %psr
+	nop
+	nop
+	nop
+	retl
+	nop
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * o0 --> from
+ * o1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+	ta 2
+	retl
+	nop
+	
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * o0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+	mov %o0, %o1
+	ta 3
+	retl
+	nop
+	
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+	set rt_thread_switch_interrupt_flag, %o2
+	ld [%o2], %o3
+	cmp %o3, 1
+	be _reswitch
+	nop
+	mov 1, %o3
+	st %o3, [%o2]
+	set rt_interrupt_from_thread, %o2
+	st %o0, [%o2]
+_reswitch:
+	set rt_interrupt_to_thread, %o2
+	st %o1, [%o2]
+	retl
+	nop
diff --git a/libcpu/sparc-v8/bm3803/interrupt.c b/libcpu/sparc-v8/bm3803/interrupt.c
new file mode 100644
index 0000000000..e3f9b5b3de
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/interrupt.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "bm3803.h"
+#include "interrupt.h"
+
+#define MAX_HANDLERS 256
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    /* init exceptions table */
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+	if (vector > 0x1F || vector < 0x11)
+		return;
+	volatile struct lregs *regs = (struct lregs*)PREGS;
+	regs->irqmask &= ~(1 << (vector - 0x10));
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+	if (vector > 0x1F || vector < 0x11)
+		return;
+	volatile struct lregs *regs = (struct lregs*)PREGS;
+	regs->irqmask |= 1 << (vector - 0x10);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector < MAX_HANDLERS || vector >= 0)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
diff --git a/libcpu/sparc-v8/bm3803/interrupt.h b/libcpu/sparc-v8/bm3803/interrupt.h
new file mode 100644
index 0000000000..7632195e70
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/interrupt.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+void rt_hw_interrupt_control(int vector, int priority, int route);
+int rt_hw_interrupt_get_active(int fiq_irq);
+void rt_hw_interrupt_ack(int fiq_irq);
+void rt_hw_interrupt_trigger(int vector);
+void rt_hw_interrupt_clear(int vector);
+
+#endif
diff --git a/libcpu/sparc-v8/bm3803/stack.c b/libcpu/sparc-v8/bm3803/stack.c
new file mode 100644
index 0000000000..3563692cdd
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/stack.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+#include <rtthread.h>
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+    int window_index;
+    int register_index;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk      = (rt_uint32_t *)stack_addr;
+    
+	stk -= 24;
+	stk -= 8;
+	
+	for (register_index = 0; register_index != 8; register_index++)
+		stk[register_index] = 0xdeadbeef;
+	
+	for (window_index = 0; window_index != 8; window_index++)
+	{
+		stk -= 16;
+		for (register_index = 0; register_index != 16; register_index++)
+		    stk[register_index] = 0xdeadbeef;
+		if (window_index == 0)
+		{
+		    stk[8] = (rt_uint32_t)parameter;
+		    stk[15] = (rt_uint32_t)texit - 8;
+		}
+	}
+	
+	stk -= 34;
+	for (register_index = 0; register_index != 34; register_index++)
+		stk[register_index] = 0;
+	
+	stk -= 4;
+	stk[0] = (rt_uint32_t)tentry; //pc
+	stk[1] = (rt_uint32_t)tentry + 4; //npc
+	stk[2] = 0x10C7; //psr
+	stk[3] = 0x2; //wim
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/sparc-v8/bm3803/start_gcc.S b/libcpu/sparc-v8/bm3803/start_gcc.S
new file mode 100644
index 0000000000..0f87aa17db
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/start_gcc.S
@@ -0,0 +1,664 @@
+/*
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#define PSR_INIT 0x10C0
+#define PREGS 0x80000000
+#define IMASK 0x90
+#define ICLEAR 0x9c
+#define NWINDOWS 8
+#define CPU_INTERRUPT_FRAME_SIZE (0x60 + 0x50 + 34 * 4)
+#define SPARC_PSR_PIL_MASK 0x00000F00
+#define SPARC_PSR_ET_MASK 0x00000020
+#define SPARC_PSR_CWP_MASK 0x07
+
+.text
+
+.globl system_vectors
+.globl _reset
+.globl _context_switch
+
+_reset:
+	mov %g0, %asr16
+	mov %g0, %asr17
+	nop
+	nop
+	nop
+	
+	set PSR_INIT, %g1
+	mov %g1, %psr
+	nop
+	nop
+	nop
+	
+	mov %g0, %wim
+	nop
+	nop
+	nop
+	
+	mov %g0, %g1
+	mov %g0, %g2
+	mov %g0, %g3
+	mov %g0, %g4
+	mov %g0, %g5
+	mov %g0, %g6
+	mov %g0, %g7
+	
+	mov 0x8, %g1
+1:
+	mov %g0, %l0
+	mov %g0, %l1
+	mov %g0, %l2
+	mov %g0, %l3
+	mov %g0, %l4
+	mov %g0, %l5
+	mov %g0, %l6
+	mov %g0, %l7
+	mov %g0, %i0
+	mov %g0, %i1
+	mov %g0, %i2
+	mov %g0, %i3
+	mov %g0, %i4
+	mov %g0, %i5
+	mov %g0, %i6
+	mov %g0, %i7
+	subcc %g1, 1, %g1
+	save
+	bne 1b
+	nop
+	
+	set 2, %g1
+	mov %g1, %wim
+	nop
+	nop
+	nop
+	
+	sethi %hi(system_vectors), %g1
+	mov %g1, %tbr
+	nop
+	nop
+	nop
+	
+	set PREGS, %g1
+	set 0xffff, %g2
+	st %g2, [%g1 + ICLEAR]
+	st %g0, [%g1 + IMASK]
+	
+	set 0x7C47907F, %g2
+	st %g2, [%g1 + 4]
+	
+	set PSR_INIT | 0x20, %g1
+	mov %g1, %psr
+	nop
+	nop
+	nop
+	
+	set _fsrinit, %g1
+	ld [%g1], %fsr
+	nop
+	nop
+	nop
+
+	set _fpdata, %g1
+	ldd [%g1], %f0
+	ldd [%g1], %f2
+	ldd [%g1], %f4
+	ldd [%g1], %f6
+	ldd [%g1], %f8
+	ldd [%g1], %f10
+	ldd [%g1], %f12
+	ldd [%g1], %f14
+	ldd [%g1], %f16
+	ldd [%g1], %f18
+	ldd [%g1], %f20
+	ldd [%g1], %f22
+	ldd [%g1], %f24
+	ldd [%g1], %f26
+	ldd [%g1], %f28
+	ldd [%g1], %f30
+
+	set __bss_start, %g2
+	set __bss_end, %g3
+	mov %g0, %g1
+bss_loop:
+	std %g0, [%g2]
+	add %g2, 8, %g2
+	cmp %g2, %g3
+	bleu,a bss_loop
+	nop
+	
+	set 0x401FFF00, %g1
+	mov %g1, %sp
+
+    /* start RT-Thread Kernel */
+    call rtthread_startup
+    nop
+    
+/*
+l0 = psr
+l1 = pc
+l2 = npc
+l3 = tbr
+*/
+.globl _ISR_Handler
+_ISR_Handler:
+	mov %g4, %l4
+	mov %g5, %l5
+	mov %wim, %g4
+	srl %g4, %l0, %g5
+	cmp %g5, 1
+	bne dont_do_the_window
+	nop
+	srl %g4, 1, %g5
+	sll %g4, NWINDOWS - 1, %g4
+	or %g4, %g5, %g4
+	save
+	mov %g4, %wim
+	nop
+	nop
+	nop
+	
+	std %l0, [%sp + 0x00]
+	std %l2, [%sp + 0x08]
+	std %l4, [%sp + 0x10]
+	std %l6, [%sp + 0x18]
+
+	std %i0, [%sp + 0x20]
+	std %i2, [%sp + 0x28]
+	std %i4, [%sp + 0x30]
+	std %i6, [%sp + 0x38]
+	
+	restore
+	nop
+
+dont_do_the_window:
+	sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
+	
+	std %l0, [%sp + 0x60]
+	st %l2, [%sp + 0x68]
+	st %g1, [%sp + 0x6c]
+	std %g2, [%sp + 0x70]
+	std %l4, [%sp + 0x78]
+	std %g6, [%sp + 0x80]
+	
+	std %i0, [%sp + 0x88]
+	std %i2, [%sp + 0x90]
+	std %i4, [%sp + 0x98]
+	std %i6, [%sp + 0xA0]
+	
+	mov %y, %g1
+	st %g1, [%sp + 0xA8]
+	st %l6, [%sp + 0xAc]
+
+	std %f0, [%sp + 0xB0 + 8 * 0x0]
+	std %f2, [%sp + 0xB0 + 8 * 0x1]
+	std %f4, [%sp + 0xB0 + 8 * 0x2]
+	std %f6, [%sp + 0xB0 + 8 * 0x3]
+	std %f8, [%sp + 0xB0 + 8 * 0x4]
+	std %f10, [%sp + 0xB0 + 8 * 0x5]
+	std %f12, [%sp + 0xB0 + 8 * 0x6]
+	std %f14, [%sp + 0xB0 + 8 * 0x7]
+	std %f16, [%sp + 0xB0 + 8 * 0x8]
+	std %f18, [%sp + 0xB0 + 8 * 0x9]
+	std %f20, [%sp + 0xB0 + 8 * 0xA]
+	std %f22, [%sp + 0xB0 + 8 * 0xB]
+	std %f24, [%sp + 0xB0 + 8 * 0xC]
+	std %f26, [%sp + 0xB0 + 8 * 0xD]
+	std %f28, [%sp + 0xB0 + 8 * 0xE]
+	std %f30, [%sp + 0xB0 + 8 * 0xF]
+	st %fsr, [%sp + 0xB0 + 8 * 0x10]
+	
+	mov %l0, %g5
+	or %g5, SPARC_PSR_PIL_MASK, %g5
+	wr %g5, SPARC_PSR_ET_MASK, %psr
+	nop
+	nop
+	nop
+	
+	call rt_interrupt_enter
+	nop
+	
+	and %l3, 0x0FF0, %l3
+	srl %l3, 4, %o0
+	mov %sp, %o1
+	
+	call rt_hw_trap
+	nop
+	
+	call rt_interrupt_leave
+	nop
+	
+	mov %l0, %psr
+	nop
+	nop
+	nop
+	
+	ld [%sp + 0xA8], %l5
+	mov %l5, %y
+	ldd [%sp + 0x60], %l0
+	ld [%sp + 0x68], %l2
+	
+	ld [%sp + 0x6c], %g1
+	ldd [%sp + 0x70], %g2
+	ldd [%sp + 0x78], %g4
+	ldd [%sp + 0x80], %g6
+
+	ldd [%sp + 0x88], %i0
+	ldd [%sp + 0x90], %i2
+	ldd [%sp + 0x98], %i4
+	ldd [%sp + 0xA0], %i6
+
+	ldd [%sp + 0xB0 + 8 * 0x0], %f0
+	ldd [%sp + 0xB0 + 8 * 0x1], %f2
+	ldd [%sp + 0xB0 + 8 * 0x2], %f4
+	ldd [%sp + 0xB0 + 8 * 0x3], %f6
+	ldd [%sp + 0xB0 + 8 * 0x4], %f8
+	ldd [%sp + 0xB0 + 8 * 0x5], %f10
+	ldd [%sp + 0xB0 + 8 * 0x6], %f12
+	ldd [%sp + 0xB0 + 8 * 0x7], %f14
+	ldd [%sp + 0xB0 + 8 * 0x8], %f16
+	ldd [%sp + 0xB0 + 8 * 0x9], %f18
+	ldd [%sp + 0xB0 + 8 * 0xA], %f20
+	ldd [%sp + 0xB0 + 8 * 0xB], %f22
+	ldd [%sp + 0xB0 + 8 * 0xC], %f24
+	ldd [%sp + 0xB0 + 8 * 0xD], %f26
+	ldd [%sp + 0xB0 + 8 * 0xE], %f28
+	ldd [%sp + 0xB0 + 8 * 0xF], %f30
+	ld [%sp + 0xB0 + 8 * 0x10], %fsr
+	nop
+	nop
+	nop
+	
+	mov %wim, %l4
+	add %l0, 1, %l6
+	and %l6, SPARC_PSR_CWP_MASK, %l6
+	srl %l4, %l6, %l5
+	cmp %l5, 1
+	bne good_task_window
+	nop
+	sll %l4, 1, %l5
+	srl %l4, NWINDOWS - 1, %l4
+	or %l4, %l5, %l4
+	mov %l4, %wim
+	nop
+	nop
+	nop
+	
+	restore
+	ldd [%sp + 0], %l0             ! Restore window from the stack
+	ldd [%sp + 8], %l2
+	ldd [%sp + 16], %l4
+	ldd [%sp + 24], %l6
+	ldd [%sp + 32], %i0
+	ldd [%sp + 40], %i2
+	ldd [%sp + 48], %i4
+	ldd [%sp + 56], %i6
+	save
+	
+good_task_window:
+	set rt_thread_switch_interrupt_flag, %l4
+	ld [%l4], %l5
+	cmp %l5, 1
+	be rt_hw_context_switch_interrupt_do
+	nop
+
+	mov %l0, %psr
+	nop
+	nop
+	nop
+	
+	jmp %l1
+	rett %l2
+
+rt_hw_context_switch_interrupt_do:
+	st %g0, [%l4]
+	
+	sub %fp, 0x20, %sp
+	std %g0, [%sp + 0x00]
+	std %g2, [%sp + 0x08]
+	std %g4, [%sp + 0x10]
+	std %g6, [%sp + 0x18]
+	
+	mov %sp, %g3
+	mov %l1, %g4
+	mov %l2, %g5
+	mov %l0, %g6
+	mov %wim, %g7
+	
+	mov %g0, %wim
+	nop
+	nop
+	nop
+	set 0xFFFFFFF8, %g1
+	and %g1, %g6, %g1
+	mov %g1, %psr
+	nop
+	nop
+	nop
+	
+	mov %g0, %g1
+save_loop:
+	save
+	sub %g3, 0x40, %g3
+	std %l0, [%g3 + 0x00]
+	std %l2, [%g3 + 0x08]
+	std %l4, [%g3 + 0x10]
+	std %l6, [%g3 + 0x18]
+	std %i0, [%g3 + 0x20]
+	std %i2, [%g3 + 0x28]
+	std %i4, [%g3 + 0x30]
+	std %i6, [%g3 + 0x38]
+	inc %g1
+	cmp %g1, NWINDOWS
+	bne save_loop
+	nop
+	
+	sub %g3, 0x88, %g3
+	std %f0, [%g3 + 0x00]
+	std %f2, [%g3 + 0x08]
+	std %f4, [%g3 + 0x10]
+	std %f6, [%g3 + 0x18]
+	std %f8, [%g3 + 0x20]
+	std %f10, [%g3 + 0x28]
+	std %f12, [%g3 + 0x30]
+	std %f14, [%g3 + 0x38]
+	std %f16, [%g3 + 0x40]
+	std %f18, [%g3 + 0x48]
+	std %f20, [%g3 + 0x50]
+	std %f22, [%g3 + 0x58]
+	std %f24, [%g3 + 0x60]
+	std %f26, [%g3 + 0x68]
+	std %f28, [%g3 + 0x70]
+	std %f30, [%g3 + 0x78]
+	mov %y, %g1
+	st %g1, [%g3 + 0x80]
+	st %fsr, [%g3 + 0x84]
+	
+	sub %g3, 0x10, %g3
+	std %g4, [%g3 + 0x00]
+	std %g6, [%g3 + 0x08]
+	
+	set rt_interrupt_from_thread, %g1
+	ld [%g1], %g2
+	st %g3, [%g2]
+	
+	set rt_interrupt_to_thread, %g1
+	ld [%g1], %g1
+	ld [%g1], %g3
+
+	ldd [%g3 + 0x00], %g4
+	ldd [%g3 + 0x08], %g6
+	add %g3, 0x10, %g3
+	
+	ldd [%g3 + 0x00], %f0
+	ldd [%g3 + 0x08], %f2
+	ldd [%g3 + 0x10], %f4
+	ldd [%g3 + 0x18], %f6
+	ldd [%g3 + 0x20], %f8
+	ldd [%g3 + 0x28], %f10
+	ldd [%g3 + 0x30], %f12
+	ldd [%g3 + 0x38], %f14
+	ldd [%g3 + 0x40], %f16
+	ldd [%g3 + 0x48], %f18
+	ldd [%g3 + 0x50], %f20
+	ldd [%g3 + 0x58], %f22
+	ldd [%g3 + 0x60], %f24
+	ldd [%g3 + 0x68], %f26
+	ldd [%g3 + 0x70], %f28
+	ldd [%g3 + 0x78], %f30
+	ld [%g3 + 0x80], %g1
+	mov %g1, %y
+	ld [%g3 + 0x84], %fsr
+	add %g3, 0x88, %g3
+	
+	set NWINDOWS - 1, %g1
+	or %g1, %g6, %g1
+	mov %g1, %psr
+	nop
+	nop
+	nop
+	
+	mov %g0, %g1
+restore_loop:
+	restore
+	ldd [%g3 + 0x00], %l0
+	ldd [%g3 + 0x08], %l2
+	ldd [%g3 + 0x10], %l4
+	ldd [%g3 + 0x18], %l6 
+	ldd [%g3 + 0x20], %i0
+	ldd [%g3 + 0x28], %i2
+	ldd [%g3 + 0x30], %i4
+	ldd [%g3 + 0x38], %i6
+	add %g3, 0x40, %g3
+	inc %g1
+	cmp %g1, NWINDOWS
+	bne restore_loop
+	nop
+	
+	mov %g6, %psr
+	nop
+	nop
+	nop
+	mov %g7, %wim
+	nop
+	nop
+	nop
+	
+	mov %g4, %l1
+	mov %g5, %l2
+	mov %g3, %sp
+	
+	ldd [%sp + 0x00], %g0
+	ldd [%sp + 0x08], %g2
+	ldd [%sp + 0x10], %g4
+	ldd [%sp + 0x18], %g6	
+	add %sp, 0x20, %fp
+	jmp %l1
+	rett %l2
+
+/*
+l0 = psr
+l1 = pc
+l2 = npc
+l3 = tbr
+*/
+_context_switch:
+	mov %l2, %l1
+	add %l2, 4, %l2
+	
+	mov %g4, %l4
+	mov %g5, %l5
+	mov %wim, %g4
+	srl %g4, %l0, %g5
+	cmp %g5, 1
+	bne good_window
+	nop
+	srl %g4, 1, %g5
+	sll %g4, NWINDOWS - 1, %g4
+	or %g4, %g5, %g4
+	save
+	mov %g4, %wim
+	nop
+	nop
+	nop
+	
+	std %l0, [%sp + 0x00]
+	std %l2, [%sp + 0x08]
+	std %l4, [%sp + 0x10]
+	std %l6, [%sp + 0x18]
+
+	std %i0, [%sp + 0x20]
+	std %i2, [%sp + 0x28]
+	std %i4, [%sp + 0x30]
+	std %i6, [%sp + 0x38]
+	
+	restore
+	nop
+
+good_window:
+	and %l3, 0x0FF0, %l3
+	srl %l3, 4, %l4
+	cmp %l4, 0x82
+	bne switch_to
+	nop
+	
+	sub %fp, 0x20, %sp
+	std %g0, [%sp + 0x00]
+	std %g2, [%sp + 0x08]
+	std %g4, [%sp + 0x10]
+	std %g6, [%sp + 0x18]
+	
+	mov %sp, %g3
+	mov %l1, %g4
+	mov %l2, %g5
+	mov %l0, %g6
+	mov %wim, %g7
+	
+	mov %g0, %wim
+	nop
+	nop
+	nop
+	set 0xFFFFFFF8, %g1
+	and %g1, %g6, %g1
+	mov %g1, %psr
+	nop
+	nop
+	nop
+	
+	mov %g0, %g1
+save_window:
+	save
+	sub %g3, 0x40, %g3
+	std %l0, [%g3 + 0x00]
+	std %l2, [%g3 + 0x08]
+	std %l4, [%g3 + 0x10]
+	std %l6, [%g3 + 0x18]
+	std %i0, [%g3 + 0x20]
+	std %i2, [%g3 + 0x28]
+	std %i4, [%g3 + 0x30]
+	std %i6, [%g3 + 0x38]
+	inc %g1
+	cmp %g1, NWINDOWS
+	bne save_window
+	nop
+	
+	sub %g3, 0x88, %g3
+	std %f0, [%g3 + 0x00]
+	std %f2, [%g3 + 0x08]
+	std %f4, [%g3 + 0x10]
+	std %f6, [%g3 + 0x18]
+	std %f8, [%g3 + 0x20]
+	std %f10, [%g3 + 0x28]
+	std %f12, [%g3 + 0x30]
+	std %f14, [%g3 + 0x38]
+	std %f16, [%g3 + 0x40]
+	std %f18, [%g3 + 0x48]
+	std %f20, [%g3 + 0x50]
+	std %f22, [%g3 + 0x58]
+	std %f24, [%g3 + 0x60]
+	std %f26, [%g3 + 0x68]
+	std %f28, [%g3 + 0x70]
+	std %f30, [%g3 + 0x78]
+	mov %y, %g1
+	st %g1, [%g3 + 0x80]
+	st %fsr, [%g3 + 0x84]
+	
+	sub %g3, 0x10, %g3
+	std %g4, [%g3 + 0x00]
+	std %g6, [%g3 + 0x08]
+	
+	mov %g6, %psr
+	nop
+	nop
+	nop
+	
+	st %g3, [%i0]
+switch_to:
+	mov %g0, %wim
+	nop
+	nop
+	nop
+	ld [%i1], %g3
+
+	ldd [%g3 + 0x00], %g4
+	ldd [%g3 + 0x08], %g6
+	add %g3, 0x10, %g3
+	
+	ldd [%g3 + 0x00], %f0
+	ldd [%g3 + 0x08], %f2
+	ldd [%g3 + 0x10], %f4
+	ldd [%g3 + 0x18], %f6
+	ldd [%g3 + 0x20], %f8
+	ldd [%g3 + 0x28], %f10
+	ldd [%g3 + 0x30], %f12
+	ldd [%g3 + 0x38], %f14
+	ldd [%g3 + 0x40], %f16
+	ldd [%g3 + 0x48], %f18
+	ldd [%g3 + 0x50], %f20
+	ldd [%g3 + 0x58], %f22
+	ldd [%g3 + 0x60], %f24
+	ldd [%g3 + 0x68], %f26
+	ldd [%g3 + 0x70], %f28
+	ldd [%g3 + 0x78], %f30
+	ld [%g3 + 0x80], %g1
+	mov %g1, %y
+	ld [%g3 + 0x84], %fsr
+	add %g3, 0x88, %g3
+	
+	set NWINDOWS - 1, %g1
+	or %g1, %g6, %g1
+	mov %g1, %psr
+	nop
+	nop
+	nop
+	
+	mov %g0, %g1
+restore_window:
+	restore
+	ldd [%g3 + 0x00], %l0
+	ldd [%g3 + 0x08], %l2
+	ldd [%g3 + 0x10], %l4
+	ldd [%g3 + 0x18], %l6 
+	ldd [%g3 + 0x20], %i0
+	ldd [%g3 + 0x28], %i2
+	ldd [%g3 + 0x30], %i4
+	ldd [%g3 + 0x38], %i6
+	add %g3, 0x40, %g3
+	inc %g1
+	cmp %g1, NWINDOWS
+	bne restore_window
+	nop
+	
+	mov %g6, %psr
+	nop
+	nop
+	nop
+	mov %g7, %wim
+	nop
+	nop
+	nop
+	
+	mov %g4, %l1
+	mov %g5, %l2
+	mov %g3, %sp
+	
+	ldd [%sp + 0x00], %g0
+	ldd [%sp + 0x08], %g2
+	ldd [%sp + 0x10], %g4
+	ldd [%sp + 0x18], %g6	
+	add %sp, 0x20, %fp
+	jmp %l1
+	rett %l2
+	
+.data 
+.align 8
+_fpdata:
+	.word 0, 0
+_fsrinit:
+	.word 0
diff --git a/libcpu/sparc-v8/bm3803/trap.c b/libcpu/sparc-v8/bm3803/trap.c
new file mode 100644
index 0000000000..05a0416dfa
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/trap.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+extern struct rt_irq_desc isr_table[];
+
+void rt_hw_trap(int tt, unsigned int *sp)
+{
+	void *param;
+	rt_isr_handler_t isr_func;
+	
+	/* get interrupt service routine */
+	isr_func = isr_table[tt].handler;
+	param = isr_table[tt].param;
+	
+	/* turn to interrupt service routine */
+    if (isr_func != RT_NULL)
+        isr_func(tt, param);
+}
diff --git a/libcpu/sparc-v8/bm3803/vector_gcc.S b/libcpu/sparc-v8/bm3803/vector_gcc.S
new file mode 100644
index 0000000000..0d243bee33
--- /dev/null
+++ b/libcpu/sparc-v8/bm3803/vector_gcc.S
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
+
+#define TRAPL(H) mov %g0, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop;
+#define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop;
+#define TRAP_ENTRY(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); mov %tbr, %l3;
+#define BAD_TRAP ta 0; nop; nop; nop;
+#define SOFT_TRAP BAD_TRAP
+#define NWINDOWS 8
+
+.section .vectors, "ax"
+
+.globl _ISR_Handler
+.globl _window_overflow
+.globl _window_underflow
+.globl _reset
+.globl _context_switch
+
+.globl system_vectors
+system_vectors:
+    TRAPL(_reset);       ! 00 reset trap
+    BAD_TRAP;			 ! 01 instruction_access_exception
+    BAD_TRAP;			 ! 02 illegal_instruction
+    BAD_TRAP;			 ! 03 priveleged_instruction
+    BAD_TRAP;
+    TRAP(_window_overflow);	            ! 05 window_overflow
+    TRAP(_window_underflow);	        ! 06 window_underflow
+    BAD_TRAP;			 ! 07 memory_add0ress_not_aligned
+    BAD_TRAP;			 ! 08 fp_exception
+    BAD_TRAP;			 ! 09 data_access_exception
+    BAD_TRAP;			 ! 0A tag_overflow
+    BAD_TRAP;			 ! 0B undefined
+    BAD_TRAP;			 ! 0C undefined
+    BAD_TRAP;			 ! 0D undefined
+    BAD_TRAP;			 ! 0E undefined
+    BAD_TRAP;			 ! 0F undefined
+    BAD_TRAP;			 ! 10 undefined
+
+    /* Interrupt entries */
+    TRAP_ENTRY(_ISR_Handler) 	       ! 11 interrupt level 1
+    TRAP_ENTRY(_ISR_Handler) 		   ! 12 interrupt level 2
+    TRAP_ENTRY(_ISR_Handler) 		   ! 13 interrupt level 3
+    TRAP_ENTRY(_ISR_Handler) 		   ! 14 interrupt level 4
+    TRAP_ENTRY(_ISR_Handler) 		   ! 15 interrupt level 5
+    TRAP_ENTRY(_ISR_Handler) 		   ! 16 interrupt level 6
+    TRAP_ENTRY(_ISR_Handler) 		   ! 17 interrupt level 7
+    TRAP_ENTRY(_ISR_Handler) 		   ! 18 interrupt level 8
+    TRAP_ENTRY(_ISR_Handler) 		   ! 19 interrupt level 9
+    TRAP_ENTRY(_ISR_Handler) 		   ! 1A interrupt level 1
+    TRAP_ENTRY(_ISR_Handler) 		   ! 1B interrupt level 11
+    TRAP_ENTRY(_ISR_Handler) 		   ! 1C interrupt level 12
+    TRAP_ENTRY(_ISR_Handler) 		   ! 1D interrupt level 13
+    TRAP_ENTRY(_ISR_Handler) 		   ! 1E interrupt level 14
+    TRAP_ENTRY(_ISR_Handler) 		   ! 1F interrupt level 15
+
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 20 - 23 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;		! 24 - 27 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;     ! 28 - 2B undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 2C - 2F undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 30 - 33 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 34 - 37 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 38 - 3B undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 3C - 3F undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 40 - 43 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 44 - 47 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 48 - 4B undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 4C - 4F undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 50 - 53 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 54 - 57 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 58 - 5B undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 5C - 5F undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 60 - 63 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 64 - 67 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 68 - 6B undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 6C - 6F undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 70 - 73 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 74 - 77 undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 78 - 7B undefined
+    BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;	    ! 7C - 7F undefined
+
+    /* Software traps */
+    SOFT_TRAP; SOFT_TRAP; TRAP_ENTRY(_context_switch); TRAP_ENTRY(_context_switch) ! 80 - 83
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 84 - 87
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 88 - 8B
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 8C - 8F
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 90 - 93
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 94 - 97
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 98 - 9B
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! 9C - 9F
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! A0 - A3
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! A4 - A7
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! A8 - AB
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! AC - AF
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! B0 - B3
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! B4 - B7
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! B8 - BB
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! BC - BF
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! C0 - C3
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! C4 - C7
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! C8 - CB
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! CC - CF
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! D0 - D3
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! D4 - D7
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! D8 - DB
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! DC - DF
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! E0 - E3
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! E4 - E7
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! E8 - EB
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! EC - EF
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! F0 - F3
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! F4 - F7
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! F8 - FB
+    SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;	! FC - FF
+    
+_window_overflow:
+	mov %wim, %l3                   ! Calculate next WIM
+	mov %g1, %l7
+	srl %l3, 1, %g1
+	sll %l3, NWINDOWS - 1, %l4
+	or %l4, %g1, %g1
+	save                             ! Get into window to be saved.
+	mov %g1, %wim
+	nop
+	nop
+	nop
+	std %l0, [%sp + 0]
+	std %l2, [%sp + 8]
+	std %l4, [%sp + 16]
+	std %l6, [%sp + 24]
+	std %i0, [%sp + 32]
+	std %i2, [%sp + 40]
+	std %i4, [%sp + 48]
+	std %i6, [%sp + 56]
+	restore                          ! Go back to trap window.
+	mov %l7, %g1
+	jmp %l1                         ! Re-execute save.
+	rett %l2
+	
+_window_underflow:
+	mov %wim, %l3                   ! Calculate next WIM
+	sll %l3, 1, %l4
+	srl %l3, NWINDOWS - 1, %l5
+	or %l5, %l4, %l5
+	mov %l5, %wim
+	nop
+	nop
+	nop
+	restore                          ! Two restores to get into the
+	restore                          ! window to restore
+	ldd [%sp + 0], %l0             ! Restore window from the stack
+	ldd [%sp + 8], %l2
+	ldd [%sp + 16], %l4
+	ldd [%sp + 24], %l6
+	ldd [%sp + 32], %i0
+	ldd [%sp + 40], %i2
+	ldd [%sp + 48], %i4
+	ldd [%sp + 56], %i6
+	save                             ! Get back to the trap window.
+	save
+	jmp %l1                         ! Re-execute restore.
+	rett %l2
diff --git a/libcpu/sparc-v8/common/SConscript b/libcpu/sparc-v8/common/SConscript
new file mode 100644
index 0000000000..9ff30a796b
--- /dev/null
+++ b/libcpu/sparc-v8/common/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
-- 
cgit v1.3.1


From c1f4d6c691498287830af97679548d4c83c3ca02 Mon Sep 17 00:00:00 2001
From: GFWisshit <qq979818120@gmail.com>
Date: Tue, 20 Oct 2020 17:28:59 +0800
Subject: 修改license header，修改driver目录下的SConscript。
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 bsp/bm3803/applications/board.c      |  54 ++++++-----
 bsp/bm3803/applications/board.h      |  30 +++---
 bsp/bm3803/applications/main.c       |  20 ++++
 bsp/bm3803/drivers/SConscript        |  13 +--
 bsp/bm3803/drivers/uart.c            |  78 ++++++++-------
 bsp/bm3803/drivers/uart.h            |  30 +++---
 bsp/bm3803/drivers/uart_reg.h        |  28 +++++-
 libcpu/sparc-v8/bm3803/bm3803.h      | 179 +++++++++++++++++++----------------
 libcpu/sparc-v8/bm3803/context_gcc.S |  26 +++--
 libcpu/sparc-v8/bm3803/interrupt.c   |  44 +++++----
 libcpu/sparc-v8/bm3803/interrupt.h   |  26 +++--
 libcpu/sparc-v8/bm3803/stack.c       |  83 +++++++++-------
 libcpu/sparc-v8/bm3803/start_gcc.S   |  26 +++--
 libcpu/sparc-v8/bm3803/trap.c        |  42 ++++----
 libcpu/sparc-v8/bm3803/vector_gcc.S  |  26 +++--
 15 files changed, 420 insertions(+), 285 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/bm3803/applications/board.c b/bsp/bm3803/applications/board.c
index 043fceda03..ee400cc0e1 100644
--- a/bsp/bm3803/applications/board.c
+++ b/bsp/bm3803/applications/board.c
@@ -1,16 +1,22 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #include <rthw.h>
 #include <rtthread.h>
@@ -21,27 +27,27 @@
 
 extern int __bss_end;
 
-static void rt_hw_timer_isr(int vector, void* param)
+static void rt_hw_timer_isr(int vector, void *param)
 {
-	rt_tick_increase();
-	/* timer interrupt cleared by hardware */
+    rt_tick_increase();
+    /* timer interrupt cleared by hardware */
 }
 
 int rt_hw_timer_init(void)
 {
-	unsigned int counter = 1000000 / RT_TICK_PER_SECOND;
-	volatile struct lregs *regs = (struct lregs*)PREGS;
-    
+    unsigned int counter = 1000000 / RT_TICK_PER_SECOND;
+    volatile struct lregs *regs = (struct lregs *)PREGS;
+
     regs->scalercnt = CPU_FREQ / 1000000 - 1;
     regs->scalerload = CPU_FREQ / 1000000 - 1;
     regs->timercnt2 = counter - 1;
     regs->timerload2 = counter - 1;
 
-	rt_hw_interrupt_install(TIMER2_TT, rt_hw_timer_isr, RT_NULL, "tick");
-	rt_hw_interrupt_umask(TIMER2_TT);
+    rt_hw_interrupt_install(TIMER2_TT, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(TIMER2_TT);
 
-	/* start timer */
-	regs->timerctrl2 = 0x7;
+    /* start timer */
+    regs->timerctrl2 = 0x7;
 
     return 0;
 }
@@ -52,7 +58,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init);
  */
 void rt_hw_board_init(void)
 {
-	rt_system_heap_init((void*)&__bss_end, (void*)&__bss_end + 0x01000000);
+    rt_system_heap_init((void *)&__bss_end, (void *)&__bss_end + 0x01000000);
     rt_components_board_init();
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 }
diff --git a/bsp/bm3803/applications/board.h b/bsp/bm3803/applications/board.h
index becb93cf3b..88d477e492 100644
--- a/bsp/bm3803/applications/board.h
+++ b/bsp/bm3803/applications/board.h
@@ -1,16 +1,22 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #ifndef __BOARD_H__
 #define __BOARD_H__
diff --git a/bsp/bm3803/applications/main.c b/bsp/bm3803/applications/main.c
index d77e7a2a8b..e24fdf2b90 100644
--- a/bsp/bm3803/applications/main.c
+++ b/bsp/bm3803/applications/main.c
@@ -1,3 +1,23 @@
+/*
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
+
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
diff --git a/bsp/bm3803/drivers/SConscript b/bsp/bm3803/drivers/SConscript
index a630c8a7c4..5e45e1bad3 100644
--- a/bsp/bm3803/drivers/SConscript
+++ b/bsp/bm3803/drivers/SConscript
@@ -3,20 +3,9 @@ Import('RTT_ROOT')
 Import('rtconfig')
 from building import *
 
-cwd     = GetCurrentDir()
+cwd = GetCurrentDir()
 src	= Glob('*.c')
-
-# remove no need file.
-if GetDepend('RT_USING_LWIP') == False:
-    src_need_remove = ['dm9000.c'] # need remove file list.
-    SrcRemove(src, src_need_remove)
-
-if GetDepend('RT_USING_DFS') == False:
-    src_need_remove = ['sd.c'] # need remove file list.
-    SrcRemove(src, src_need_remove)
-
 CPPPATH = [cwd]
-
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/bsp/bm3803/drivers/uart.c b/bsp/bm3803/drivers/uart.c
index bdfe522958..4f07c26123 100644
--- a/bsp/bm3803/drivers/uart.c
+++ b/bsp/bm3803/drivers/uart.c
@@ -1,16 +1,22 @@
 /*
- * File      : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #include <rthw.h>
 #include <rtthread.h>
@@ -27,16 +33,16 @@ struct bm3803_uart
     int irq;
 };
 
-static void bm3803_uart_isr(int tt, void* param)
+static void bm3803_uart_isr(int tt, void *param)
 {
-    struct bm3803_uart* uart;
+    struct bm3803_uart *uart;
     struct rt_serial_device *serial;
-    struct uart_reg* uart_base;
+    struct uart_reg *uart_base;
 
-    serial = (struct rt_serial_device*)param;
+    serial = (struct rt_serial_device *)param;
     uart = (struct bm3803_uart *)serial->parent.user_data;
     uart_base = uart->uart_base;
-    
+
     if (uart_base->uartstatus & 0x1)
     {
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
@@ -47,8 +53,8 @@ static void bm3803_uart_isr(int tt, void* param)
 
 static rt_err_t bm3803_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
-    struct bm3803_uart* uart;
-    struct uart_reg* uart_base;
+    struct bm3803_uart *uart;
+    struct uart_reg *uart_base;
 
     RT_ASSERT(serial != RT_NULL);
     uart = (struct bm3803_uart *)serial->parent.user_data;
@@ -57,17 +63,17 @@ static rt_err_t bm3803_configure(struct rt_serial_device *serial, struct serial_
 
     if (cfg->baud_rate == BAUD_RATE_115200)
     {
-		uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 115200)) - 5) / 10);
+        uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 115200)) - 5) / 10);
     }
     else if (cfg->baud_rate == BAUD_RATE_9600)
     {
-		uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 9600)) - 5) / 10);
+        uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 9600)) - 5) / 10);
     }
     else
     {
         NOT_IMPLEMENTED();
     }
-    
+
     uart_base->uartctrl |= 0x3;
 
     return RT_EOK;
@@ -75,7 +81,7 @@ static rt_err_t bm3803_configure(struct rt_serial_device *serial, struct serial_
 
 static rt_err_t bm3803_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
-    struct bm3803_uart* uart;
+    struct bm3803_uart *uart;
 
     RT_ASSERT(serial != RT_NULL);
     uart = (struct bm3803_uart *)serial->parent.user_data;
@@ -97,13 +103,13 @@ static rt_err_t bm3803_control(struct rt_serial_device *serial, int cmd, void *a
 
 static int bm3803_putc(struct rt_serial_device *serial, char c)
 {
-    struct bm3803_uart* uart;
-	struct uart_reg* uart_base;
-	
+    struct bm3803_uart *uart;
+    struct uart_reg *uart_base;
+
     RT_ASSERT(serial != RT_NULL);
     uart = (struct bm3803_uart *)serial->parent.user_data;
     uart_base = uart->uart_base;
-    
+
     while (!(uart_base->uartstatus & 0x4));
     uart_base->uartdata = c;
 
@@ -113,13 +119,13 @@ static int bm3803_putc(struct rt_serial_device *serial, char c)
 static int bm3803_getc(struct rt_serial_device *serial)
 {
     int ch;
-    struct bm3803_uart* uart;
-    struct uart_reg* uart_base;
+    struct bm3803_uart *uart;
+    struct uart_reg *uart_base;
 
     RT_ASSERT(serial != RT_NULL);
     uart = (struct bm3803_uart *)serial->parent.user_data;
-	uart_base = uart->uart_base;
-	
+    uart_base = uart->uart_base;
+
     ch = -1;
     if (uart_base->uartstatus & 0x1)
     {
@@ -131,7 +137,7 @@ static int bm3803_getc(struct rt_serial_device *serial)
 
 static const struct rt_uart_ops bm3803_uart_ops =
 {
-	bm3803_configure,
+    bm3803_configure,
     bm3803_control,
     bm3803_putc,
     bm3803_getc,
@@ -141,7 +147,7 @@ static const struct rt_uart_ops bm3803_uart_ops =
 #ifdef RT_USING_UART1
 struct bm3803_uart uart1 =
 {
-    (void*)UART1_BASE,
+    (void *)UART1_BASE,
     UART1_TT,
 };
 struct rt_serial_device serial1;
@@ -152,7 +158,7 @@ int rt_hw_serial_init(void)
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
 #ifdef RT_USING_UART1
-	volatile struct lregs *regs = (struct lregs*)PREGS;
+    volatile struct lregs *regs = (struct lregs *)PREGS;
     serial1.ops = &bm3803_uart_ops;
     serial1.config = config;
     /* configure gpio direction */
@@ -166,8 +172,8 @@ int rt_hw_serial_init(void)
     rt_hw_interrupt_mask(uart1.irq);
     /* register UART1 device */
     rt_hw_serial_register(&serial1, "uart1",
-            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-            &uart1);
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &uart1);
 #endif
     return 0;
 }
diff --git a/bsp/bm3803/drivers/uart.h b/bsp/bm3803/drivers/uart.h
index 46a7df5d89..a16ea99913 100644
--- a/bsp/bm3803/drivers/uart.h
+++ b/bsp/bm3803/drivers/uart.h
@@ -1,16 +1,22 @@
 /*
- * File      : serial.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #ifndef __SERIAL_H__
 #define __SERIAL_H__
diff --git a/bsp/bm3803/drivers/uart_reg.h b/bsp/bm3803/drivers/uart_reg.h
index c0911149df..3edd98a6f7 100644
--- a/bsp/bm3803/drivers/uart_reg.h
+++ b/bsp/bm3803/drivers/uart_reg.h
@@ -1,12 +1,32 @@
+/*
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
+
 #ifndef SERIAL_REG_H
 #define SERIAL_REG_H
 
 struct uart_reg
 {
-	unsigned int uartdata;
-	unsigned int uartstatus;
-	unsigned int uartctrl;
-	unsigned int uartscaler;
+    unsigned int uartdata;
+    unsigned int uartstatus;
+    unsigned int uartctrl;
+    unsigned int uartscaler;
 };
 
 #endif /* end of include guard: SERIAL_REG_H */
diff --git a/libcpu/sparc-v8/bm3803/bm3803.h b/libcpu/sparc-v8/bm3803/bm3803.h
index a90663f199..4a4c750975 100644
--- a/libcpu/sparc-v8/bm3803/bm3803.h
+++ b/libcpu/sparc-v8/bm3803/bm3803.h
@@ -1,95 +1,106 @@
 /*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
+
 #ifndef __BM3803_H__
 #define __BM3803_H__
 
 struct lregs
 {
-	/* address = 0x80000000 */
-	unsigned int memcfg1;		    /* 0x00 */
-	unsigned int memcfg2;
-	unsigned int memcfg3;
-	unsigned int failaddr;
-
-	unsigned int memstatus;		/* 0x10 */
-	unsigned int cachectrl;
-	unsigned int powerdown;
-	unsigned int writeprot1;
-
-	unsigned int writeprot2;	    /* 0x20 */
-	unsigned int pcr;
-	unsigned int dummy2;
-	unsigned int dummy3;
-
-	unsigned int dummy4;	        /* 0x30 */
-	unsigned int dummy5;
-	unsigned int dummy6;
-	unsigned int dummy7;
-
-	unsigned int timercnt1;		/* 0x40 */
-	unsigned int timerload1;
-	unsigned int timerctrl1;
-	unsigned int wdog;
-
-	unsigned int timercnt2;        /* 0x50 */
-	unsigned int timerload2;
-	unsigned int timerctrl2;
-	unsigned int dummy8;
-
-	unsigned int scalercnt;        /* 0x60 */
-	unsigned int scalerload;
-	unsigned int dummy9;
-	unsigned int dummy10;
-
-	unsigned int uartdata1;        /* 0x70 */
-	unsigned int uartstatus1;
-	unsigned int uartctrl1;
-	unsigned int uartscaler1;
-
-	unsigned int uartdata2;        /* 0x80 */
-	unsigned int uartstatus2;
-	unsigned int uartctrl2;
-	unsigned int uartscaler2;
-
-	unsigned int irqmask;           /* 0x90 */
-	unsigned int irqpend;
-	unsigned int irqforce;
-	unsigned int irqclear;
-
-	unsigned int piodata;            /* 0xA0 */
-	unsigned int piodir;
-	unsigned int pioirq;
-	unsigned int dummy11;
-
-	unsigned int imask2;            /* 0xB0 */
-	unsigned int ipend2;
-	unsigned int istat2;
-	unsigned int dummy12;
-
-	unsigned int dummy13;          /* 0xC0 */
-	unsigned int dcomstatus;
-	unsigned int dcomctrl;
-	unsigned int dcomscaler;
-
-	unsigned int dummy14;	        /* 0xD0 */
-	unsigned int dummy15;
-	unsigned int dummy16;
-	unsigned int dummy17;
-
-	unsigned int uartdata3;         /* 0xE0 */
-	unsigned int uartstatus3;
-	unsigned int uartctrl3;
-	unsigned int uartscaler3;
+    /* address = 0x80000000 */
+    unsigned int memcfg1;           /* 0x00 */
+    unsigned int memcfg2;
+    unsigned int memcfg3;
+    unsigned int failaddr;
+
+    unsigned int memstatus;     /* 0x10 */
+    unsigned int cachectrl;
+    unsigned int powerdown;
+    unsigned int writeprot1;
+
+    unsigned int writeprot2;        /* 0x20 */
+    unsigned int pcr;
+    unsigned int dummy2;
+    unsigned int dummy3;
+
+    unsigned int dummy4;            /* 0x30 */
+    unsigned int dummy5;
+    unsigned int dummy6;
+    unsigned int dummy7;
+
+    unsigned int timercnt1;     /* 0x40 */
+    unsigned int timerload1;
+    unsigned int timerctrl1;
+    unsigned int wdog;
+
+    unsigned int timercnt2;        /* 0x50 */
+    unsigned int timerload2;
+    unsigned int timerctrl2;
+    unsigned int dummy8;
+
+    unsigned int scalercnt;        /* 0x60 */
+    unsigned int scalerload;
+    unsigned int dummy9;
+    unsigned int dummy10;
+
+    unsigned int uartdata1;        /* 0x70 */
+    unsigned int uartstatus1;
+    unsigned int uartctrl1;
+    unsigned int uartscaler1;
+
+    unsigned int uartdata2;        /* 0x80 */
+    unsigned int uartstatus2;
+    unsigned int uartctrl2;
+    unsigned int uartscaler2;
+
+    unsigned int irqmask;           /* 0x90 */
+    unsigned int irqpend;
+    unsigned int irqforce;
+    unsigned int irqclear;
+
+    unsigned int piodata;            /* 0xA0 */
+    unsigned int piodir;
+    unsigned int pioirq;
+    unsigned int dummy11;
+
+    unsigned int imask2;            /* 0xB0 */
+    unsigned int ipend2;
+    unsigned int istat2;
+    unsigned int dummy12;
+
+    unsigned int dummy13;          /* 0xC0 */
+    unsigned int dcomstatus;
+    unsigned int dcomctrl;
+    unsigned int dcomscaler;
+
+    unsigned int dummy14;           /* 0xD0 */
+    unsigned int dummy15;
+    unsigned int dummy16;
+    unsigned int dummy17;
+
+    unsigned int uartdata3;         /* 0xE0 */
+    unsigned int uartstatus3;
+    unsigned int uartctrl3;
+    unsigned int uartscaler3;
 };
 
-#define	PREGS 0x80000000
+#define PREGS 0x80000000
 
 #define UART1_BASE (PREGS + 0x70)
 
diff --git a/libcpu/sparc-v8/bm3803/context_gcc.S b/libcpu/sparc-v8/bm3803/context_gcc.S
index c0344a81d5..478793588e 100644
--- a/libcpu/sparc-v8/bm3803/context_gcc.S
+++ b/libcpu/sparc-v8/bm3803/context_gcc.S
@@ -1,12 +1,22 @@
 /*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #define SPARC_PSR_PIL_MASK 0x00000F00
 #define SPARC_PSR_ET_MASK 0x00000020
diff --git a/libcpu/sparc-v8/bm3803/interrupt.c b/libcpu/sparc-v8/bm3803/interrupt.c
index e3f9b5b3de..8ce03dd4c0 100644
--- a/libcpu/sparc-v8/bm3803/interrupt.c
+++ b/libcpu/sparc-v8/bm3803/interrupt.c
@@ -1,12 +1,22 @@
 /*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #include <rthw.h>
 #include <rtthread.h>
@@ -43,10 +53,10 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int vector)
 {
-	if (vector > 0x1F || vector < 0x11)
-		return;
-	volatile struct lregs *regs = (struct lregs*)PREGS;
-	regs->irqmask &= ~(1 << (vector - 0x10));
+    if (vector > 0x1F || vector < 0x11)
+        return;
+    volatile struct lregs *regs = (struct lregs *)PREGS;
+    regs->irqmask &= ~(1 << (vector - 0x10));
 }
 
 /**
@@ -55,10 +65,10 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-	if (vector > 0x1F || vector < 0x11)
-		return;
-	volatile struct lregs *regs = (struct lregs*)PREGS;
-	regs->irqmask |= 1 << (vector - 0x10);
+    if (vector > 0x1F || vector < 0x11)
+        return;
+    volatile struct lregs *regs = (struct lregs *)PREGS;
+    regs->irqmask |= 1 << (vector - 0x10);
 }
 
 /**
@@ -72,7 +82,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 {
     rt_isr_handler_t old_handler = RT_NULL;
 
-    if(vector < MAX_HANDLERS || vector >= 0)
+    if (vector < MAX_HANDLERS || vector >= 0)
     {
         old_handler = isr_table[vector].handler;
 
diff --git a/libcpu/sparc-v8/bm3803/interrupt.h b/libcpu/sparc-v8/bm3803/interrupt.h
index 7632195e70..5c97d5caa5 100644
--- a/libcpu/sparc-v8/bm3803/interrupt.h
+++ b/libcpu/sparc-v8/bm3803/interrupt.h
@@ -1,12 +1,22 @@
 /*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #ifndef __INTERRUPT_H__
 #define __INTERRUPT_H__
diff --git a/libcpu/sparc-v8/bm3803/stack.c b/libcpu/sparc-v8/bm3803/stack.c
index 3563692cdd..70c1b60d8c 100644
--- a/libcpu/sparc-v8/bm3803/stack.c
+++ b/libcpu/sparc-v8/bm3803/stack.c
@@ -1,12 +1,23 @@
 /*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
+
 #include <rtthread.h>
 
 /**
@@ -29,34 +40,34 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     stack_addr += sizeof(rt_uint32_t);
     stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
     stk      = (rt_uint32_t *)stack_addr;
-    
-	stk -= 24;
-	stk -= 8;
-	
-	for (register_index = 0; register_index != 8; register_index++)
-		stk[register_index] = 0xdeadbeef;
-	
-	for (window_index = 0; window_index != 8; window_index++)
-	{
-		stk -= 16;
-		for (register_index = 0; register_index != 16; register_index++)
-		    stk[register_index] = 0xdeadbeef;
-		if (window_index == 0)
-		{
-		    stk[8] = (rt_uint32_t)parameter;
-		    stk[15] = (rt_uint32_t)texit - 8;
-		}
-	}
-	
-	stk -= 34;
-	for (register_index = 0; register_index != 34; register_index++)
-		stk[register_index] = 0;
-	
-	stk -= 4;
-	stk[0] = (rt_uint32_t)tentry; //pc
-	stk[1] = (rt_uint32_t)tentry + 4; //npc
-	stk[2] = 0x10C7; //psr
-	stk[3] = 0x2; //wim
+
+    stk -= 24;
+    stk -= 8;
+
+    for (register_index = 0; register_index != 8; register_index++)
+        stk[register_index] = 0xdeadbeef;
+
+    for (window_index = 0; window_index != 8; window_index++)
+    {
+        stk -= 16;
+        for (register_index = 0; register_index != 16; register_index++)
+            stk[register_index] = 0xdeadbeef;
+        if (window_index == 0)
+        {
+            stk[8] = (rt_uint32_t)parameter;
+            stk[15] = (rt_uint32_t)texit - 8;
+        }
+    }
+
+    stk -= 34;
+    for (register_index = 0; register_index != 34; register_index++)
+        stk[register_index] = 0;
+
+    stk -= 4;
+    stk[0] = (rt_uint32_t)tentry; //pc
+    stk[1] = (rt_uint32_t)tentry + 4; //npc
+    stk[2] = 0x10C7; //psr
+    stk[3] = 0x2; //wim
 
     /* return task's current stack address */
     return (rt_uint8_t *)stk;
diff --git a/libcpu/sparc-v8/bm3803/start_gcc.S b/libcpu/sparc-v8/bm3803/start_gcc.S
index 0f87aa17db..fd613375c9 100644
--- a/libcpu/sparc-v8/bm3803/start_gcc.S
+++ b/libcpu/sparc-v8/bm3803/start_gcc.S
@@ -1,12 +1,22 @@
 /*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #define PSR_INIT 0x10C0
 #define PREGS 0x80000000
diff --git a/libcpu/sparc-v8/bm3803/trap.c b/libcpu/sparc-v8/bm3803/trap.c
index 05a0416dfa..545073ed18 100644
--- a/libcpu/sparc-v8/bm3803/trap.c
+++ b/libcpu/sparc-v8/bm3803/trap.c
@@ -1,12 +1,22 @@
 /*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #include <rtthread.h>
 #include <rthw.h>
@@ -15,14 +25,14 @@ extern struct rt_irq_desc isr_table[];
 
 void rt_hw_trap(int tt, unsigned int *sp)
 {
-	void *param;
-	rt_isr_handler_t isr_func;
-	
-	/* get interrupt service routine */
-	isr_func = isr_table[tt].handler;
-	param = isr_table[tt].param;
-	
-	/* turn to interrupt service routine */
+    void *param;
+    rt_isr_handler_t isr_func;
+
+    /* get interrupt service routine */
+    isr_func = isr_table[tt].handler;
+    param = isr_table[tt].param;
+
+    /* turn to interrupt service routine */
     if (isr_func != RT_NULL)
         isr_func(tt, param);
 }
diff --git a/libcpu/sparc-v8/bm3803/vector_gcc.S b/libcpu/sparc-v8/bm3803/vector_gcc.S
index 0d243bee33..114fe45536 100644
--- a/libcpu/sparc-v8/bm3803/vector_gcc.S
+++ b/libcpu/sparc-v8/bm3803/vector_gcc.S
@@ -1,12 +1,22 @@
 /*
- * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2020-10-16     Dystopia     the first version
- */
+Copyright 2020 Shenzhen Academy of Aerospace Technology
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Change Logs:
+Date           Author       Notes
+2020-10-16     Dystopia     the first version
+*/
 
 #define TRAPL(H) mov %g0, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop;
 #define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop;
-- 
cgit v1.3.1


From ad917d90109a8e628ab7ea440acbbfaa8273d780 Mon Sep 17 00:00:00 2001
From: GFWisshit <qq979818120@gmail.com>
Date: Wed, 21 Oct 2020 15:08:13 +0800
Subject: 修改了license
 header，修改了sconscipt，修改了board.c指针的强制转换类型，interrupt.c添加了新的函数。
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 bsp/bm3803/applications/board.c      | 28 +++++++++-------------------
 bsp/bm3803/applications/board.h      | 26 ++++++++------------------
 bsp/bm3803/applications/main.c       | 26 ++++++++------------------
 bsp/bm3803/drivers/uart.c            | 26 ++++++++------------------
 bsp/bm3803/drivers/uart.h            | 26 ++++++++------------------
 bsp/bm3803/drivers/uart_reg.h        | 26 ++++++++------------------
 libcpu/sparc-v8/bm3803/bm3803.h      | 26 ++++++++------------------
 libcpu/sparc-v8/bm3803/context_gcc.S | 26 ++++++++------------------
 libcpu/sparc-v8/bm3803/interrupt.c   | 34 ++++++++++++++++------------------
 libcpu/sparc-v8/bm3803/interrupt.h   | 31 +++++++++----------------------
 libcpu/sparc-v8/bm3803/stack.c       | 26 ++++++++------------------
 libcpu/sparc-v8/bm3803/start_gcc.S   | 26 ++++++++------------------
 libcpu/sparc-v8/bm3803/trap.c        | 26 ++++++++------------------
 libcpu/sparc-v8/bm3803/vector_gcc.S  | 26 ++++++++------------------
 libcpu/sparc-v8/common/SConscript    |  6 ------
 15 files changed, 122 insertions(+), 263 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/bm3803/applications/board.c b/bsp/bm3803/applications/board.c
index ee400cc0e1..37460f268f 100644
--- a/bsp/bm3803/applications/board.c
+++ b/bsp/bm3803/applications/board.c
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #include <rthw.h>
 #include <rtthread.h>
@@ -58,7 +48,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init);
  */
 void rt_hw_board_init(void)
 {
-    rt_system_heap_init((void *)&__bss_end, (void *)&__bss_end + 0x01000000);
+    rt_system_heap_init((void *)&__bss_end, (unsigned char *)&__bss_end + 0x01000000);
     rt_components_board_init();
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 }
diff --git a/bsp/bm3803/applications/board.h b/bsp/bm3803/applications/board.h
index 88d477e492..e12389331f 100644
--- a/bsp/bm3803/applications/board.h
+++ b/bsp/bm3803/applications/board.h
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #ifndef __BOARD_H__
 #define __BOARD_H__
diff --git a/bsp/bm3803/applications/main.c b/bsp/bm3803/applications/main.c
index e24fdf2b90..047393b2cf 100644
--- a/bsp/bm3803/applications/main.c
+++ b/bsp/bm3803/applications/main.c
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #include <stdint.h>
 #include <stdio.h>
diff --git a/bsp/bm3803/drivers/uart.c b/bsp/bm3803/drivers/uart.c
index 4f07c26123..d43b660d1a 100644
--- a/bsp/bm3803/drivers/uart.c
+++ b/bsp/bm3803/drivers/uart.c
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #include <rthw.h>
 #include <rtthread.h>
diff --git a/bsp/bm3803/drivers/uart.h b/bsp/bm3803/drivers/uart.h
index a16ea99913..11923d24fe 100644
--- a/bsp/bm3803/drivers/uart.h
+++ b/bsp/bm3803/drivers/uart.h
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #ifndef __SERIAL_H__
 #define __SERIAL_H__
diff --git a/bsp/bm3803/drivers/uart_reg.h b/bsp/bm3803/drivers/uart_reg.h
index 3edd98a6f7..179f767b3e 100644
--- a/bsp/bm3803/drivers/uart_reg.h
+++ b/bsp/bm3803/drivers/uart_reg.h
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #ifndef SERIAL_REG_H
 #define SERIAL_REG_H
diff --git a/libcpu/sparc-v8/bm3803/bm3803.h b/libcpu/sparc-v8/bm3803/bm3803.h
index 4a4c750975..17a9882eb2 100644
--- a/libcpu/sparc-v8/bm3803/bm3803.h
+++ b/libcpu/sparc-v8/bm3803/bm3803.h
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #ifndef __BM3803_H__
 #define __BM3803_H__
diff --git a/libcpu/sparc-v8/bm3803/context_gcc.S b/libcpu/sparc-v8/bm3803/context_gcc.S
index 478793588e..c0344a81d5 100644
--- a/libcpu/sparc-v8/bm3803/context_gcc.S
+++ b/libcpu/sparc-v8/bm3803/context_gcc.S
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #define SPARC_PSR_PIL_MASK 0x00000F00
 #define SPARC_PSR_ET_MASK 0x00000020
diff --git a/libcpu/sparc-v8/bm3803/interrupt.c b/libcpu/sparc-v8/bm3803/interrupt.c
index 8ce03dd4c0..b3625862b4 100644
--- a/libcpu/sparc-v8/bm3803/interrupt.c
+++ b/libcpu/sparc-v8/bm3803/interrupt.c
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #include <rthw.h>
 #include <rtthread.h>
@@ -98,3 +88,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 
     return old_handler;
 }
+
+void rt_hw_interrupt_clear(int vector)
+{
+    if (vector > 0x1F || vector < 0x11)
+        return;
+    volatile struct lregs *regs = (struct lregs *)PREGS;
+    regs->irqclear |= 1 << (vector - 0x10);
+}
diff --git a/libcpu/sparc-v8/bm3803/interrupt.h b/libcpu/sparc-v8/bm3803/interrupt.h
index 5c97d5caa5..666d5268f5 100644
--- a/libcpu/sparc-v8/bm3803/interrupt.h
+++ b/libcpu/sparc-v8/bm3803/interrupt.h
@@ -1,30 +1,17 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ * 2020-10-21     Dystopia     Add new function
+ */
 
 #ifndef __INTERRUPT_H__
 #define __INTERRUPT_H__
 
-void rt_hw_interrupt_control(int vector, int priority, int route);
-int rt_hw_interrupt_get_active(int fiq_irq);
-void rt_hw_interrupt_ack(int fiq_irq);
-void rt_hw_interrupt_trigger(int vector);
 void rt_hw_interrupt_clear(int vector);
 
 #endif
diff --git a/libcpu/sparc-v8/bm3803/stack.c b/libcpu/sparc-v8/bm3803/stack.c
index 70c1b60d8c..2fdc37b539 100644
--- a/libcpu/sparc-v8/bm3803/stack.c
+++ b/libcpu/sparc-v8/bm3803/stack.c
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #include <rtthread.h>
 
diff --git a/libcpu/sparc-v8/bm3803/start_gcc.S b/libcpu/sparc-v8/bm3803/start_gcc.S
index fd613375c9..0f87aa17db 100644
--- a/libcpu/sparc-v8/bm3803/start_gcc.S
+++ b/libcpu/sparc-v8/bm3803/start_gcc.S
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #define PSR_INIT 0x10C0
 #define PREGS 0x80000000
diff --git a/libcpu/sparc-v8/bm3803/trap.c b/libcpu/sparc-v8/bm3803/trap.c
index 545073ed18..b896a0d941 100644
--- a/libcpu/sparc-v8/bm3803/trap.c
+++ b/libcpu/sparc-v8/bm3803/trap.c
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #include <rtthread.h>
 #include <rthw.h>
diff --git a/libcpu/sparc-v8/bm3803/vector_gcc.S b/libcpu/sparc-v8/bm3803/vector_gcc.S
index 114fe45536..0d243bee33 100644
--- a/libcpu/sparc-v8/bm3803/vector_gcc.S
+++ b/libcpu/sparc-v8/bm3803/vector_gcc.S
@@ -1,22 +1,12 @@
 /*
-Copyright 2020 Shenzhen Academy of Aerospace Technology
-
-Licensed under the Apache License, Version 2.0 (the "License");
-you may not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    http://www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-Change Logs:
-Date           Author       Notes
-2020-10-16     Dystopia     the first version
-*/
+ * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-10-16     Dystopia     the first version
+ */
 
 #define TRAPL(H) mov %g0, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop;
 #define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop;
diff --git a/libcpu/sparc-v8/common/SConscript b/libcpu/sparc-v8/common/SConscript
index 9ff30a796b..1e96ff5837 100644
--- a/libcpu/sparc-v8/common/SConscript
+++ b/libcpu/sparc-v8/common/SConscript
@@ -8,16 +8,10 @@ cwd     = GetCurrentDir()
 src     = Glob('*.c') + Glob('*.cpp')
 CPPPATH = [cwd]
 
-if rtconfig.PLATFORM == 'armcc':
-    src += Glob('*_rvds.S')
-
 if rtconfig.PLATFORM == 'gcc':
     src += Glob('*_init.S')
     src += Glob('*_gcc.S')
 
-if rtconfig.PLATFORM == 'iar':
-    src += Glob('*_iar.S')
-
 group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
-- 
cgit v1.3.1


From 2f68120e49ab352027b216c3008c2dbe087b2307 Mon Sep 17 00:00:00 2001
From: tangweikang <tangweikang@rt-thread.com>
Date: Thu, 29 Oct 2020 10:54:53 +0800
Subject: [libcpu][risc-v] Fixed bsp k210 failing to compile | 修复 k210
 无法编译的问题。
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/risc-v/SConscript | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 5055b533e6..dece8b0423 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -10,7 +10,7 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-if   rtconfig.VENDOR == "t-head" :
+if   rtconfig.CPU == "e906" :
     group = group
 elif rtconfig.CPU == "nuclei" :
     group = group
@@ -18,7 +18,7 @@ else :
     group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
 
 # cpu porting code files
-if  rtconfig.VENDOR == "t-head" :
+if  rtconfig.CPU == "e906" :
     group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
 else :
     group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
-- 
cgit v1.3.1