From 01b27b9e9117e8a5eba3bac64f02213b1d4734bc Mon Sep 17 00:00:00 2001 From: Xiao Lifan Date: Thu, 5 Dec 2019 21:50:48 +0800 Subject: [libcpu][c28x]add support for c28x mcu hardware fpu --- libcpu/ti-dsp/c28x/context.s | 38 +++++++++++++++++++++++++++++++++++++- libcpu/ti-dsp/c28x/cpuport.c | 19 +++++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) (limited to 'libcpu') diff --git a/libcpu/ti-dsp/c28x/context.s b/libcpu/ti-dsp/c28x/context.s index f21e0ddb6e..460ad701e5 100644 --- a/libcpu/ti-dsp/c28x/context.s +++ b/libcpu/ti-dsp/c28x/context.s @@ -8,6 +8,7 @@ ; 2018-09-01 xuzhuoyi the first version. ; 2019-06-17 zhaoxiaowei fix bugs of old c28x interrupt api. ; 2019-07-03 zhaoxiaowei add _rt_hw_calc_csb function to support __rt_ffs. +; 2019-12-05 xiaolifan add support for hardware fpu32 ; .ref _rt_interrupt_to_thread @@ -24,6 +25,16 @@ .def _rt_hw_interrupt_thread_switch .def _rt_hw_interrupt_disable .def _rt_hw_interrupt_enable + +;workaround for importing fpu settings from the compiler + .cdecls C,NOLIST + %{ + #ifdef __TMS320C28XX_FPU32__ + #define __FPU32__ 1 + #else + #define __FPU32__ 0 + #endif + %} RT_CTX_SAVE .macro @@ -38,12 +49,37 @@ RT_CTX_SAVE .macro PUSH XAR7 PUSH XT PUSH RPC - + + .if __FPU32__ + PUSH RB + MOV32 *SP++, STF + MOV32 *SP++, R0H + MOV32 *SP++, R1H + MOV32 *SP++, R2H + MOV32 *SP++, R3H + MOV32 *SP++, R4H + MOV32 *SP++, R5H + MOV32 *SP++, R6H + MOV32 *SP++, R7H + .endif .endm RT_CTX_RESTORE .macro + + .if __FPU32__ + MOV32 R7H, *--SP, UNCF + MOV32 R6H, *--SP, UNCF + MOV32 R5H, *--SP, UNCF + MOV32 R4H, *--SP, UNCF + MOV32 R3H, *--SP, UNCF + MOV32 R2H, *--SP, UNCF + MOV32 R1H, *--SP, UNCF + MOV32 R0H, *--SP, UNCF + MOV32 STF, *--SP + POP RB + .endif POP RPC POP XT diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c index 3f88606c65..e16210f447 100644 --- a/libcpu/ti-dsp/c28x/cpuport.c +++ b/libcpu/ti-dsp/c28x/cpuport.c @@ -7,6 +7,7 @@ * Date Author Notes * 2018-09-01 xuzhuoyi the first version. * 2019-07-03 zhaoxiaowei add support for __rt_ffs. + * 2019-12-05 xiaolifan add support for hardware fpu32 */ #include @@ -22,6 +23,7 @@ extern rt_uint16_t rt_hw_get_st0(void); extern rt_uint16_t rt_hw_get_st1(void); extern int rt_hw_calc_csb(int value); + struct exception_stack_frame { rt_uint32_t t_st0; @@ -49,6 +51,18 @@ struct stack_frame rt_uint32_t xt; rt_uint32_t rpc; +#ifdef __TMS320C28XX_FPU32__ + rt_uint32_t rb; + rt_uint32_t stf; + rt_uint32_t r0h; + rt_uint32_t r1h; + rt_uint32_t r2h; + rt_uint32_t r3h; + rt_uint32_t r4h; + rt_uint32_t r5h; + rt_uint32_t r6h; + rt_uint32_t r7h; +#endif }; @@ -83,6 +97,11 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, stack_frame->exception_stack_frame.return_address = (unsigned long)tentry; /* return_address */ stack_frame->rpc = (unsigned long)texit; +#ifdef __TMS320C28XX_FPU32__ + stack_frame->stf = 0x00000200; + stack_frame->rb = 0; +#endif + /* return task's current stack address */ return stk + sizeof(struct stack_frame); } -- cgit v1.3.1 From 66d1510ac728cd2d92c289bc4801ccb8a6711262 Mon Sep 17 00:00:00 2001 From: Xiao Lifan Date: Mon, 9 Dec 2019 09:29:12 +0800 Subject: convert intentation tabs to spaces --- libcpu/ti-dsp/c28x/context.s | 64 ++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'libcpu') diff --git a/libcpu/ti-dsp/c28x/context.s b/libcpu/ti-dsp/c28x/context.s index 460ad701e5..323d97b180 100644 --- a/libcpu/ti-dsp/c28x/context.s +++ b/libcpu/ti-dsp/c28x/context.s @@ -27,14 +27,14 @@ .def _rt_hw_interrupt_enable ;workaround for importing fpu settings from the compiler - .cdecls C,NOLIST - %{ - #ifdef __TMS320C28XX_FPU32__ - #define __FPU32__ 1 - #else - #define __FPU32__ 0 - #endif - %} + .cdecls C,NOLIST + %{ + #ifdef __TMS320C28XX_FPU32__ + #define __FPU32__ 1 + #else + #define __FPU32__ 0 + #endif + %} RT_CTX_SAVE .macro @@ -50,36 +50,36 @@ RT_CTX_SAVE .macro PUSH XT PUSH RPC - .if __FPU32__ - PUSH RB - MOV32 *SP++, STF - MOV32 *SP++, R0H - MOV32 *SP++, R1H - MOV32 *SP++, R2H - MOV32 *SP++, R3H - MOV32 *SP++, R4H - MOV32 *SP++, R5H - MOV32 *SP++, R6H - MOV32 *SP++, R7H - .endif + .if __FPU32__ + PUSH RB + MOV32 *SP++, STF + MOV32 *SP++, R0H + MOV32 *SP++, R1H + MOV32 *SP++, R2H + MOV32 *SP++, R3H + MOV32 *SP++, R4H + MOV32 *SP++, R5H + MOV32 *SP++, R6H + MOV32 *SP++, R7H + .endif .endm RT_CTX_RESTORE .macro - .if __FPU32__ - MOV32 R7H, *--SP, UNCF - MOV32 R6H, *--SP, UNCF - MOV32 R5H, *--SP, UNCF - MOV32 R4H, *--SP, UNCF - MOV32 R3H, *--SP, UNCF - MOV32 R2H, *--SP, UNCF - MOV32 R1H, *--SP, UNCF - MOV32 R0H, *--SP, UNCF - MOV32 STF, *--SP - POP RB - .endif + .if __FPU32__ + MOV32 R7H, *--SP, UNCF + MOV32 R6H, *--SP, UNCF + MOV32 R5H, *--SP, UNCF + MOV32 R4H, *--SP, UNCF + MOV32 R3H, *--SP, UNCF + MOV32 R2H, *--SP, UNCF + MOV32 R1H, *--SP, UNCF + MOV32 R0H, *--SP, UNCF + MOV32 STF, *--SP + POP RB + .endif POP RPC POP XT -- cgit v1.3.1 From d2eaa452d652c205aef16ee7385cb1a5d188c942 Mon Sep 17 00:00:00 2001 From: xieyangrun Date: Thu, 18 Jun 2020 09:18:48 +0800 Subject: [libcpu/arm/*/cpuport.c]fixed __rt_ffs bug on account of armclang LTO. --- libcpu/arm/cortex-m3/cpuport.c | 4 ++-- libcpu/arm/cortex-m33/cpuport.c | 4 ++-- libcpu/arm/cortex-m4/cpuport.c | 4 ++-- libcpu/arm/cortex-m7/cpuport.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'libcpu') diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index d17d4fdf2e..d58782e2c5 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -388,13 +388,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" : "=r"(value) : "r"(value) diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c index 415f560911..a589ba3462 100644 --- a/libcpu/arm/cortex-m33/cpuport.c +++ b/libcpu/arm/cortex-m33/cpuport.c @@ -475,13 +475,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" "BX lr \n" : "=r"(value) diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index f556ba0c26..dc8a9aab59 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -472,13 +472,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" : "=r"(value) : "r"(value) diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index c22242f140..e701a52307 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -472,13 +472,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" : "=r"(value) : "r"(value) -- cgit v1.3.1 From 1f2a7b564cca0610b246db11a035504ce9d9d1c7 Mon Sep 17 00:00:00 2001 From: xuzhuoyi Date: Thu, 18 Jun 2020 10:53:34 +0800 Subject: [libcpu][arm][cortex-m23] Change exception return call address to 0xFFFFFFFD --- libcpu/arm/cortex-m23/context_gcc.S | 2 +- libcpu/arm/cortex-m23/context_iar.S | 2 +- libcpu/arm/cortex-m23/context_rvds.S | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'libcpu') diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S index 067348181d..48f90413d9 100644 --- a/libcpu/arm/cortex-m23/context_gcc.S +++ b/libcpu/arm/cortex-m23/context_gcc.S @@ -137,7 +137,7 @@ pendsv_exit: /* restore interrupt */ MSR PRIMASK, R2 - MOVS R0, #0x04 + MOVS R0, #0x03 RSBS R0, R0, #0x00 BX R0 /* diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S index 4d50d0fdec..c7d85cc5e2 100644 --- a/libcpu/arm/cortex-m23/context_iar.S +++ b/libcpu/arm/cortex-m23/context_iar.S @@ -139,7 +139,7 @@ pendsv_exit ; restore interrupt MSR PRIMASK, r2 - MOVS r0, #0x04 + MOVS r0, #0x03 RSBS r0, r0, #0x00 BX r0 diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S index 4486ceaf08..ca381d0f8f 100644 --- a/libcpu/arm/cortex-m23/context_rvds.S +++ b/libcpu/arm/cortex-m23/context_rvds.S @@ -143,7 +143,7 @@ pendsv_exit ; restore interrupt MSR PRIMASK, r2 - MOVS r0, #0x04 + MOVS r0, #0x03 RSBS r0, r0, #0x00 BX r0 ENDP -- cgit v1.3.1 From 1ec681a55121b9b1d5fcdb274a3c3d10d408a960 Mon Sep 17 00:00:00 2001 From: bigamgic Date: Sun, 21 Jun 2020 23:25:32 +0800 Subject: fix ls2k libc and irq --- bsp/ls2kdev/drivers/drv_gpio.c | 147 +++++++++++++++++++++++++++++---- bsp/ls2kdev/drivers/drv_gpio.h | 20 +++++ bsp/ls2kdev/drivers/drv_uart.c | 24 +++--- bsp/ls2kdev/drivers/drv_uart.h | 2 +- bsp/ls2kdev/drivers/interrupt.c | 178 ++++++++++++++++++++++++++++++++++++---- bsp/ls2kdev/drivers/interrupt.h | 85 +++++++++++++++++++ bsp/ls2kdev/drivers/ls2k1000.h | 13 ++- libcpu/mips/common/exception.c | 39 +++++---- 8 files changed, 449 insertions(+), 59 deletions(-) create mode 100644 bsp/ls2kdev/drivers/interrupt.h (limited to 'libcpu') diff --git a/bsp/ls2kdev/drivers/drv_gpio.c b/bsp/ls2kdev/drivers/drv_gpio.c index bcbecd9e2c..e1c5d61331 100644 --- a/bsp/ls2kdev/drivers/drv_gpio.c +++ b/bsp/ls2kdev/drivers/drv_gpio.c @@ -8,25 +8,14 @@ * 2017-10-20 ZYH add mode open drain and input pull down * 2020-06-01 Du Huanpeng GPIO driver based on */ - - #include #include -#include #include - -struct loongson_gpio { - rt_uint64_t GPIO0_OEN; - rt_uint64_t GPIO1_OEN; /* Reserved */ - rt_uint64_t GPIO0_O; - rt_uint64_t GPIO1_O; /* Reserved */ - rt_uint64_t GPIO0_I; - rt_uint64_t GPIO1_I; /* Reserved */ - rt_uint64_t GPIO0_INTEN; - rt_uint64_t GPIO1_INTEN; /* Reserved */ -}; +#include "drv_gpio.h" #ifdef RT_USING_PIN +#define GPIO_IRQ_NUM (64) +static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM]; static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode) { @@ -92,13 +81,36 @@ static int loongson_pin_read(struct rt_device *device, rt_base_t pin) return rc; } - /* TODO: add GPIO interrupt */ +/* TODO: add GPIO interrupt */ static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) { + rt_uint8_t index; + rt_uint64_t m; struct loongson_gpio *gpio; gpio = (void *)device->user_data; + if(pin < 4) + { + index = pin; + } + else if(pin < 32) + { + index = 5; + } + else + { + index = 6; + } + + _g_gpio_irq_tbl[index].irq_cb[pin] = hdr; + _g_gpio_irq_tbl[index].irq_arg[pin] = args; + _g_gpio_irq_tbl[index].irq_type[pin] = mode; + + liointc_set_irq_mode(index, mode); + m = (rt_uint64_t)1 << pin; + gpio->GPIO0_INTEN |= m; + return RT_EOK; } static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_int32_t pin) @@ -107,6 +119,24 @@ static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_int32_t pin gpio = (void *)device->user_data; + rt_uint8_t index; + if(pin < 4) + { + index = pin; + } + else if(pin < 32) + { + index = 5; + } + else + { + index = 6; + } + _g_gpio_irq_tbl[index].irq_cb[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_arg[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_type[pin] = RT_NULL; + _g_gpio_irq_tbl[index].state[pin] = RT_NULL; + return RT_EOK; } static rt_err_t loongson_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) @@ -115,9 +145,72 @@ static rt_err_t loongson_pin_irq_enable(struct rt_device *device, rt_base_t pin, gpio = (void *)device->user_data; + rt_uint8_t index; + if(pin < 4) + { + index = pin; + } + else if(pin < 32) + { + index = 5; + } + else + { + index = 6; + } + + if (enabled) + _g_gpio_irq_tbl[index].state[pin] = 1; + else + _g_gpio_irq_tbl[index].state[pin] = 0; return RT_EOK; } +static void gpio_irq_handler(int irq, void *param) +{ + struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param; + rt_uint32_t pin; + rt_uint32_t value; + rt_uint32_t tmpvalue; + + if(irq == LS2K_GPIO0_INT_IRQ) + { + pin = 0; + } + else if(irq == LS2K_GPIO1_INT_IRQ) + { + pin = 1; + } + else if(irq == LS2K_GPIO2_INT_IRQ) + { + pin = 2; + } + else if(irq == LS2K_GPIO3_INT_IRQ) + { + pin = 3; + } + else if(irq == LS2K_GPIO_INTLO_IRQ) + { + pin = 4; + } + else + { + pin = 32; + } + + while (value) + { + if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL)) + { + if(irq_def->state[pin]) + { + irq_def->irq_cb[pin](irq_def->irq_arg[pin]); + } + } + pin++; + value = value >> 1; + } +} static struct rt_pin_ops loongson_pin_ops = { .pin_mode = loongson_pin_mode, @@ -139,6 +232,30 @@ int loongson_pin_init(void) loongson_gpio_priv = (void *)GPIO_BASE; rc = rt_device_pin_register("pin", &loongson_pin_ops, loongson_gpio_priv); + //gpio0 + rt_hw_interrupt_install(LS2K_GPIO0_INT_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq"); + rt_hw_interrupt_umask(LS2K_GPIO0_INT_IRQ); + + //gpio1 + rt_hw_interrupt_install(LS2K_GPIO1_INT_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq"); + rt_hw_interrupt_umask(LS2K_GPIO1_INT_IRQ); + + //gpio2 + rt_hw_interrupt_install(LS2K_GPIO2_INT_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq"); + rt_hw_interrupt_umask(LS2K_GPIO2_INT_IRQ); + + //gpio3 + rt_hw_interrupt_install(LS2K_GPIO3_INT_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[3], "gpio3_irq"); + rt_hw_interrupt_umask(LS2K_GPIO3_INT_IRQ); + + //gpio4~gpio31 + rt_hw_interrupt_install(LS2K_GPIO_INTLO_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[4], "gpio4_irq"); + rt_hw_interrupt_umask(LS2K_GPIO_INTLO_IRQ); + + //gpio32~gpio63 + rt_hw_interrupt_install(LS2K_GPIO_INTHI_IRQ, gpio_irq_handler, &_g_gpio_irq_tbl[5], "gpio5_irq"); + rt_hw_interrupt_umask(LS2K_GPIO_INTHI_IRQ); + return rc; } INIT_BOARD_EXPORT(loongson_pin_init); diff --git a/bsp/ls2kdev/drivers/drv_gpio.h b/bsp/ls2kdev/drivers/drv_gpio.h index 6d505c1294..51a75c306e 100644 --- a/bsp/ls2kdev/drivers/drv_gpio.h +++ b/bsp/ls2kdev/drivers/drv_gpio.h @@ -13,6 +13,26 @@ #ifndef __DRV_GPIO_H__ #define __DRV_GPIO_H__ +#include + +struct gpio_irq_def +{ + void *irq_arg[32]; + void (*irq_cb[32])(void *param); + rt_uint8_t irq_type[32]; + rt_uint8_t state[32]; +}; + +struct loongson_gpio { + rt_uint64_t GPIO0_OEN; + rt_uint64_t GPIO1_OEN; /* Reserved */ + rt_uint64_t GPIO0_O; + rt_uint64_t GPIO1_O; /* Reserved */ + rt_uint64_t GPIO0_I; + rt_uint64_t GPIO1_I; /* Reserved */ + rt_uint64_t GPIO0_INTEN; + rt_uint64_t GPIO1_INTEN; /* Reserved */ +}; int loongson_pin_init(void); diff --git a/bsp/ls2kdev/drivers/drv_uart.c b/bsp/ls2kdev/drivers/drv_uart.c index 428393dcc4..baed70b61f 100644 --- a/bsp/ls2kdev/drivers/drv_uart.c +++ b/bsp/ls2kdev/drivers/drv_uart.c @@ -28,7 +28,7 @@ struct rt_uart_ls2k rt_uint32_t IRQ; }; -static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct rt_uart_ls2k *uart_dev = RT_NULL; @@ -48,7 +48,7 @@ static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct s return RT_EOK; } -static rt_err_t mipssim_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +static rt_err_t ls2k_uart_control(struct rt_serial_device *serial, int cmd, void *arg) { struct rt_uart_ls2k *uart_dev = RT_NULL; @@ -88,7 +88,7 @@ static rt_bool_t uart_is_transmit_empty(struct rt_uart_ls2k *uart_dev) } } -static int mipssim_uart_putc(struct rt_serial_device *serial, char c) +static int ls2k_uart_putc(struct rt_serial_device *serial, char c) { struct rt_uart_ls2k *uart_dev = RT_NULL; @@ -104,7 +104,7 @@ static int mipssim_uart_putc(struct rt_serial_device *serial, char c) return 1; } -static int mipssim_uart_getc(struct rt_serial_device *serial) +static int ls2k_uart_getc(struct rt_serial_device *serial) { struct rt_uart_ls2k *uart_dev = RT_NULL; @@ -141,18 +141,18 @@ static void uart_irq_handler(int vector, void *param) } -static const struct rt_uart_ops mipssim_uart_ops = +static const struct rt_uart_ops ls2k_uart_ops = { - mipssim_uart_configure, - mipssim_uart_control, - mipssim_uart_putc, - mipssim_uart_getc, + ls2k_uart_configure, + ls2k_uart_control, + ls2k_uart_putc, + ls2k_uart_getc, }; struct rt_uart_ls2k uart_dev0 = { - (void *)UART0_BASE, - 4, + (void *)UARTx_BASE(0), + LS2K_UART_0_1_2_3_IRQ, }; struct rt_serial_device serial; @@ -164,7 +164,7 @@ void rt_hw_uart_init(void) uart = &uart_dev0; - serial.ops = &mipssim_uart_ops; + serial.ops = &ls2k_uart_ops; serial.config = config; rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART"); diff --git a/bsp/ls2kdev/drivers/drv_uart.h b/bsp/ls2kdev/drivers/drv_uart.h index 95c69a0442..4d17b99b35 100644 --- a/bsp/ls2kdev/drivers/drv_uart.h +++ b/bsp/ls2kdev/drivers/drv_uart.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2019-04-05 bigmagic Initial version + * 2020-04-05 bigmagic Initial version */ #ifndef _DRV_UART_H__ diff --git a/bsp/ls2kdev/drivers/interrupt.c b/bsp/ls2kdev/drivers/interrupt.c index 6473e5aa94..97f5994ec7 100644 --- a/bsp/ls2kdev/drivers/interrupt.c +++ b/bsp/ls2kdev/drivers/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,8 +17,9 @@ #include #include #include - -#define MAX_INTR 32 +#include +#include "ls2k1000.h" +#include "interrupt.h" static struct rt_irq_desc irq_handle_table[MAX_INTR]; @@ -27,17 +28,141 @@ static void rt_hw_interrupt_handler(int vector, void *param) rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } +static void liointc_init(void) +{ + int i; + /* Router for LIOINTC0, to Core 0, INT0 (CPU IP2) */ + for (i = 0; i < 32; i ++) + { + HWREG8(LIOINTC0_BASE + i) = LIOINTC_COREx_INTy(0, 0); + } + + /* Router for LIOINTC1, to Core 0, INT1 (CPU IP3) */ + for (i = 0; i < 32; i ++) + { + HWREG8(LIOINTC1_BASE + i) = LIOINTC_COREx_INTy(0, 1); + } + + /* Disable all IRQs */ + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_DISABLE) = 0xffffffff; + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_DISABLE) = 0xffffffff; + + /* Set all IRQs to low level triggered (Default?) */ + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) = 0x0; + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) = 0x0; + + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) = 0x0; + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) = 0x0; +} + +//set irq mode +void liointc_set_irq_mode(int irq, int mode) +{ + if(irq < 32) + { + if(mode == PIN_IRQ_MODE_RISING) + { + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq)); + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq)); + } + else if(mode == PIN_IRQ_MODE_FALLING) + { + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq)); + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq)); + } + else if(mode == PIN_IRQ_MODE_HIGH_LEVEL) + { + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq)); + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq)); + } + else if(mode == PIN_IRQ_MODE_LOW_LEVEL) + { + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq)); + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq)); + } + else + { + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq)); + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq)); + } + } + else + { + if(mode == PIN_IRQ_MODE_RISING) + { + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq - 32)); + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32)); + } + else if(mode == PIN_IRQ_MODE_FALLING) + { + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq - 32)); + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32)); + } + else if(mode == PIN_IRQ_MODE_HIGH_LEVEL) + { + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq - 32)); + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq - 32)); + } + else if(mode == PIN_IRQ_MODE_LOW_LEVEL) + { + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq - 32)); + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq - 32)); + } + else + { + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq - 32)); + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32)); + } + } +} + +static void liointc_isr(rt_ubase_t reg_base, rt_ubase_t isr_base, + int irq_base) +{ + rt_uint32_t isr, tmp; + int intx; + /* Mask to clear ISR */ + isr = HWREG32(isr_base); + + tmp = isr; + /* Handle each of them */ + while (tmp) + { + rt_isr_handler_t irq_func; + void *param; + int irq; + + intx = __rt_ffs(isr) - 1; + tmp &= ~(1 << intx); + + irq = intx + irq_base; + + irq_func = irq_handle_table[irq].handler; + param = irq_handle_table[irq].param; + irq_func(irq, param); +#ifdef RT_USING_INTERRUPT_INFO + irq_handle_table[irq].counter++; +#endif + } + + /* Enable them again */ + HWREG32(reg_base + LIOINTC_REG_INTC_ENABLE) = isr; +} + /** * This function will initialize hardware interrupt */ void rt_hw_interrupt_init(void) { rt_uint32_t idx; + rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table)); for (idx = 0; idx < MAX_INTR; idx ++) { irq_handle_table[idx].handler = rt_hw_interrupt_handler; } + + liointc_init(); } rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, @@ -56,34 +181,57 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_handle_table[vector].param = param; } + if(vector <= 32) + { + mips_unmask_cpu_irq(2); + } + else + { + mips_unmask_cpu_irq(3); + } + return old_handler; } -void rt_hw_timer_handler(void); - void rt_do_mips_cpu_irq(rt_uint32_t ip) { void *param; rt_isr_handler_t irq_func; - - if (ip == 7) { + if (ip == 7) + { rt_hw_timer_handler(); - } else { - irq_func = irq_handle_table[ip].handler; - param = irq_handle_table[ip].param; - - /* do interrupt */ - irq_func(ip, param); + } + else if (ip == 2) + { + liointc_isr(LIOINTC0_BASE, CORE0_INTISR0, LIOINTC0_IRQBASE); + } + else if (ip == 3) + { + liointc_isr(LIOINTC1_BASE, CORE0_INTISR1, LIOINTC1_IRQBASE); } } void rt_hw_interrupt_umask(int irq) { - mips_unmask_cpu_irq(irq); + if(irq < LIOINTC0_IRQBASE + 32) + { + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_ENABLE) = (1 << irq); + } + else if(irq < LIOINTC1_IRQBASE + 32) + { + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_ENABLE) = (1 << (irq - 32)); + } } void rt_hw_interrupt_mask(int irq) { - mips_mask_cpu_irq(irq); + if(irq < LIOINTC0_IRQBASE + 32) + { + HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_DISABLE) = (1 << irq); + } + else if(irq < LIOINTC1_IRQBASE + 32) + { + HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_DISABLE) = (1 << (irq - 32)); + } } /*@}*/ diff --git a/bsp/ls2kdev/drivers/interrupt.h b/bsp/ls2kdev/drivers/interrupt.h new file mode 100644 index 0000000000..18707f7321 --- /dev/null +++ b/bsp/ls2kdev/drivers/interrupt.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-21 bigmagic Initial version + */ + +#ifndef _DRV_INTERRUPT_H__ +#define _DRV_INTERRUPT_H__ + +#define LS2K_UART_0_1_2_3_IRQ (0) +#define LS2K_UART_4_5_6_7_IRQ (1) +#define LS2K_UART_8_9_10_11_IRQ (2) +#define LS2K_EL_IRQ (3) +#define LS2K_HDA_IRQ (4) +#define LS2K_I2S_IRQ (5) +#define LS2K_RESERVED1_IRQ (6) +#define LS2K_THSENS_IRQ (7) +#define LS2K_TOY_TICK_IRQ (8) +#define LS2K_RTC_TICK_IRQ (9) +#define LS2K_CAM_TICK_IRQ (10) +#define LS2K_RESERVED2_IRQ (11) +#define LS2K_GMAC0_SBD_IRQ (12) +#define LS2K_GMAC0_PMT_IRQ (13) +#define LS2K_GMAC1_SBD_IRQ (14) +#define LS2K_GMAC1_PMT_IRQ (15) +#define LS2K_CANO_IRQ (16) +#define LS2K_CAN1_IRQ (17) +#define LS2K_BOOT_IRQ (18) +#define LS2K_SATA_IRQ (19) +#define LS2K_NAND_IRQ (20) +#define LS2K_HPET_IRQ (21) +#define LS2K_I2C0_IRQ (21) +#define LS2K_I2C1_IRQ (22) +#define LS2K_I2C2_IRQ (23) +#define LS2K_PWM0_IRQ (24) +#define LS2K_PWM1_IRQ (25) +#define LS2K_PWM2_IRQ (26) +#define LS2K_PWM3_IRQ (27) +#define LS2K_DC_IRQ (28) +#define LS2K_GPU_IRQ (29) +#define LS2K_VPU_IRQ (30) +#define LS2K_SDIO_IRQ (31) +//#define LS2K_PCIE0_IRQ (32~35) +//#define LS2K_PCIE1_IRQ (36~37) +#define LS2K_HPET1_IRQ (38) +#define LS2K_HPET2_IRQ (39) +//#define LS2K_TOY_IRQ (40~43) +//#define LS2K_DMA_IRQ (44~48) +#define LS2K_OTG_IRQ (49) +#define LS2K_EHCI_IRQ (50) +#define LS2K_OHCI_IRQ (51) +//#define LS2K_RTC_IRQ (52~54) +#define LS2K_RSA_IRQ (55) +#define LS2K_AES_IRQ (56) +#define LS2K_DES_IRQ (57) +#define LS2K_GPIO_INTLO_IRQ (58) +#define LS2K_GPIO_INTHI_IRQ (59) +#define LS2K_GPIO0_INT_IRQ (60) +#define LS2K_GPIO1_INT_IRQ (61) +#define LS2K_GPIO2_INT_IRQ (62) +#define LS2K_GPIO3_INT_IRQ (63) + +#define MAX_INTR 64 +#define LIOINTC0_IRQBASE 0 +#define LIOINTC1_IRQBASE 32 + +#define LIOINTC_SHIFT_INTx 4 +#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx))) + +#define LIOINTC_INTC_CHIP_START 0x20 + +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00) +#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) +#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) +#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) +#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) +#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) + +void liointc_set_irq_mode(int irq, int mode); + +#endif \ No newline at end of file diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h index 90adf4a6ed..cb6586525e 100644 --- a/bsp/ls2kdev/drivers/ls2k1000.h +++ b/bsp/ls2kdev/drivers/ls2k1000.h @@ -2,12 +2,23 @@ #define _LS2K1000_H__ #include +#include "interrupt.h" + +#define APB_BASE CKSEG1ADDR(0xbfe00000) #define UART0_BASE_ADDR 0xbfe00000 #define UART0_OFF 0x0 #define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF) -#define GPIO_BASE 0xFFFFFFFFBFE10500 +#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8))) + +#define LIOINTC0_BASE CKSEG1ADDR(0x1fe11400) +#define CORE0_INTISR0 CKSEG1ADDR(0x1fe11040) + +#define LIOINTC1_BASE CKSEG1ADDR(0x1fe11440) +#define CORE0_INTISR1 CKSEG1ADDR(0x1fe11048) + +#define GPIO_BASE 0xFFFFFFFFBFE10500 #define PLL_SYS_BASE 0xFFFFFFFFBFE10480 void rt_hw_timer_handler(void); diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index cd7d97e6c0..84bb0446d6 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -39,7 +39,7 @@ void rt_hw_interrupt_enable(rt_base_t level) /** * exception handle table */ -#define RT_EXCEPTION_MAX 31 +#define RT_EXCEPTION_MAX 31 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; /** @@ -59,10 +59,13 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func) return old_handler; } -void mips_dump_regs(struct pt_regs *regs) { +void mips_dump_regs(struct pt_regs *regs) +{ int i, j; - for(i = 0; i < 32 / 4; i++) { - for(j = 0; j < 4; j++) { + for (i = 0; i < 32 / 4; i++) + { + for (j = 0; j < 4; j++) + { int reg = 4 * i + j; rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]); } @@ -84,9 +87,10 @@ void cache_error_handler(void) static void unhandled_exception_handle(struct pt_regs *regs) { - rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause()); - rt_kprintf("ST0: 0x%08x ",regs->cp0_status); - rt_kprintf("ErrorPC: 0x%08x\n",read_c0_errorepc()); + rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), + read_c0_cause()); + rt_kprintf("ST0: 0x%08x ", regs->cp0_status); + rt_kprintf("ErrorPC: 0x%08x\n", read_c0_errorepc()); mips_dump_regs(regs); rt_hw_cpu_shutdown(); } @@ -95,8 +99,9 @@ static void install_default_exception_handler(void) { rt_int32_t i; - for (i=0; i> CAUSEB_EXCCODE; - - if (exccode == 0) { + if (exccode == 0) + { rt_ubase_t status, pending; - status = read_c0_status(); - pending = (CAUSEF_IP) & (status & ST0_IM); + status = read_c0_status(); + pending = (cause & CAUSEF_IP) & (status & ST0_IM); if (pending & CAUSEF_IP0) rt_do_mips_cpu_irq(0); if (pending & CAUSEF_IP1) @@ -141,7 +148,9 @@ void rt_general_exc_dispatch(struct pt_regs *regs) rt_do_mips_cpu_irq(6); if (pending & CAUSEF_IP7) rt_do_mips_cpu_irq(7); - } else { + } + else + { if (sys_exception_handlers[exccode]) sys_exception_handlers[exccode](regs); } -- cgit v1.3.1 From dae274e1f27296f5217b2567486458b10c405429 Mon Sep 17 00:00:00 2001 From: shaojinchun Date: Tue, 30 Jun 2020 17:32:14 +0800 Subject: fix gic ack irq problem --- libcpu/arm/cortex-a/gic.c | 3 +-- libcpu/arm/zynq7000/gic.c | 5 ++--- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'libcpu') diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2a46142b54..2e94b88277 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -74,9 +74,8 @@ void arm_gic_ack(rt_uint32_t index, int irq) irq = irq - _gic_table[index].offset; RT_ASSERT(irq >= 0); - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } void arm_gic_mask(rt_uint32_t index, int irq) diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c index e23a359e6e..76404d4c46 100644 --- a/libcpu/arm/zynq7000/gic.c +++ b/libcpu/arm/zynq7000/gic.c @@ -37,7 +37,7 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4) #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4) #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + (n/32) * 4) #define GIC_DIST_ACTIVE_BIT(hw_base) __REG32((hw_base) + 0x300) #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4) #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4) @@ -68,9 +68,8 @@ void arm_gic_ack(rt_uint32_t index, int irq) irq = irq - _gic_table[index].offset; RT_ASSERT(irq >= 0); - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } void arm_gic_mask(rt_uint32_t index, int irq) -- cgit v1.3.1 From 3ce53f9c797e4dae2da3b9235494f059b9a48c59 Mon Sep 17 00:00:00 2001 From: michael Date: Wed, 19 Aug 2020 10:03:52 +0800 Subject: MIPS:remove redundant #ifdef ARCH_MIPS64 there exist redundant #ifdef ARCH_MIPS64 in asm.h, remove it --- libcpu/mips/common/asm.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'libcpu') diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h index 6a5353b803..1b39eea05a 100644 --- a/libcpu/mips/common/asm.h +++ b/libcpu/mips/common/asm.h @@ -261,11 +261,7 @@ symbol = value #define LONG_SRAV srav #define LONG .word -#ifdef ARCH_MIPS64 -#define LONGSIZE 8 -#else #define LONGSIZE 4 -#endif #define LONGMASK 3 #define LONGLOG 2 -- cgit v1.3.1 From 3d0bdf4bb65bcb676b120ae273c8c28e7f52b911 Mon Sep 17 00:00:00 2001 From: michael Date: Tue, 25 Aug 2020 11:52:07 +0800 Subject: MIPS:improvement FPU support --- libcpu/mips/common/stackframe.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'libcpu') diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index 258f9a994f..4f1157aebf 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -22,7 +22,9 @@ #ifdef RT_USING_FPU /* Ensure CU1 (FPU) is enabled */ MFC0 v1, CP0_STATUS - ori v1, ST0_CU1 + lui t1, %hi(ST0_CU1) + addiu t1, t1, %lo(ST0_CU1) + or v1, v1, t1 MTC0 v1, CP0_STATUS SSNOP cfc1 v1, fcr31 @@ -125,11 +127,13 @@ #ifdef RT_USING_FPU /* Ensure CU1 (FPU) is enabled */ MFC0 v1, CP0_STATUS - ori v1, ST0_CU1 + lui t1, %hi(ST0_CU1) + addiu t1, t1, %lo(ST0_CU1) + or v1, v1, t1 MTC0 v1, CP0_STATUS SSNOP LONG_L v1, PT_FPU_FCSR31(sp) - ctc1 v1, fcsr31 + ctc1 v1, fcr31 l.d $f0, PT_FPU_R0(sp) l.d $f2, PT_FPU_R2(sp) l.d $f4, PT_FPU_R4(sp) -- cgit v1.3.1 From eb00fbeda7d9139805a5cf525779d15022188f18 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Thu, 3 Sep 2020 18:10:08 +0800 Subject: libcpu/nuclei: Fix wrong RT_KERNEL_INTERRUPT_LEVEL RT_KERNEL_INTERRUPT_LEVEL set to 0 is the lowest level. Signed-off-by: Huaqi Fang <578567190@qq.com> --- libcpu/risc-v/nuclei/cpuport.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'libcpu') diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c index fad9afdf4c..e456438f70 100644 --- a/libcpu/risc-v/nuclei/cpuport.c +++ b/libcpu/risc-v/nuclei/cpuport.c @@ -19,7 +19,7 @@ #define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND) /* Interrupt level for kernel systimer interrupt and software timer interrupt */ -#define RT_KERNEL_INTERRUPT_LEVEL 1 +#define RT_KERNEL_INTERRUPT_LEVEL 0 /* Initial CSR MSTATUS value when thread created */ #define RT_INITIAL_MSTATUS (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL) -- cgit v1.3.1 From bd95f3a94f53d1fd379e659ea9a56789d9fe471d Mon Sep 17 00:00:00 2001 From: bigmagic Date: Wed, 26 Aug 2020 12:03:01 +0800 Subject: fix mips stackframe and exception --- libcpu/Kconfig | 4 ++++ libcpu/mips/common/context_gcc.S | 21 +++++++++++---------- libcpu/mips/common/exception_gcc.S | 8 +++++++- libcpu/mips/common/stackframe.h | 2 ++ 4 files changed, 24 insertions(+), 11 deletions(-) (limited to 'libcpu') diff --git a/libcpu/Kconfig b/libcpu/Kconfig index e355664de2..ae2767dec9 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -82,6 +82,10 @@ config ARCH_MIPS config ARCH_MIPS64 bool + select ARCH_CPU_64BIT + +config ARCH_CPU_64BIT + bool config ARCH_MIPS_XBURST bool diff --git a/libcpu/mips/common/context_gcc.S b/libcpu/mips/common/context_gcc.S index cdcdede39a..3fdbe374c9 100644 --- a/libcpu/mips/common/context_gcc.S +++ b/libcpu/mips/common/context_gcc.S @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-12-04 Jiaxun Yang Initial version + * 2020-07-26 lizhirui Fixed some problems */ #ifndef __ASSEMBLY__ @@ -56,12 +57,12 @@ rt_hw_context_switch_interrupt: bnez t1, _reswitch nop li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) + LONG_S t1, 0(t0) PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) + LONG_S a0, 0(t0) _reswitch: PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) + LONG_S a1, 0(t0) jr ra nop @@ -97,24 +98,24 @@ mips_irq_handle: * rt_hw_context_switch_interrupt_do and do not return */ PTR_LA k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) + LONG_L k1, 0(k0) beqz k1, spurious_interrupt nop - sw zero, 0(k0) /* clear flag */ + LONG_S zero, 0(k0) /* clear flag */ nop /* * switch to the new thread */ PTR_LA k0, rt_interrupt_from_thread - lw k1, 0(k0) + LONG_L k1, 0(k0) nop - sw sp, 0(k1) /* store sp in preempted task TCB */ + LONG_S sp, 0(k1) /* store sp in preempted task TCB */ PTR_LA k0, rt_interrupt_to_thread - lw k1, 0(k0) + LONG_L k1, 0(k0) nop - lw sp, 0(k1) /* get new task stack pointer */ + LONG_L sp, 0(k1) /* get new task stack pointer */ j spurious_interrupt nop diff --git a/libcpu/mips/common/exception_gcc.S b/libcpu/mips/common/exception_gcc.S index 9664438ac1..c685928a84 100644 --- a/libcpu/mips/common/exception_gcc.S +++ b/libcpu/mips/common/exception_gcc.S @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-12-04 Jiaxun Yang Initial version + * 2020-07-26 lizhirui Add xtlb exception entry */ #ifndef __ASSEMBLY__ #define __ASSEMBLY__ @@ -26,6 +27,11 @@ tlb_refill_exception: b _general_exception_handler nop + /* 0x080 - XTLB refill handler */ + .org ebase_start + 0x080 + b _general_exception_handler + nop + /* 0x100 - Cache error handler */ .org ebase_start + 0x100 j cache_error_handler diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index 4f1157aebf..bb92a18c9c 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -206,6 +206,8 @@ li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) and v0, v1 or v0, a0 + li v1, (ST0_KX | ST0_SX | ST0_UX) + or v0, v1 mtc0 v0, CP0_STATUS LONG_L v1, PT_EPC(sp) MTC0 v1, CP0_EPC -- cgit v1.3.1 From 1556ba8e7f84f34c56c7f3c13d5a5540371658d4 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Fri, 4 Sep 2020 09:31:42 +0800 Subject: add ls2k mmu --- libcpu/mips/common/exception.c | 44 ++- libcpu/mips/gs264/cache.c | 70 ++++ libcpu/mips/gs264/cache.h | 24 ++ libcpu/mips/gs264/mips_mmu.c | 222 +++++++++++ libcpu/mips/gs264/mips_mmu.h | 100 +++++ libcpu/mips/gs264/mipscfg.c | 79 ++++ libcpu/mips/gs264/mmu.c | 819 +++++++++++++++++++++++++++++++++++++++++ libcpu/mips/gs264/mmu.h | 113 ++++++ 8 files changed, 1467 insertions(+), 4 deletions(-) create mode 100644 libcpu/mips/gs264/cache.c create mode 100644 libcpu/mips/gs264/cache.h create mode 100644 libcpu/mips/gs264/mips_mmu.c create mode 100644 libcpu/mips/gs264/mips_mmu.h create mode 100644 libcpu/mips/gs264/mipscfg.c create mode 100644 libcpu/mips/gs264/mmu.c create mode 100644 libcpu/mips/gs264/mmu.h (limited to 'libcpu') diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index 84bb0446d6..8eb89b1e1b 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -24,6 +24,41 @@ rt_ubase_t rt_interrupt_from_thread; rt_ubase_t rt_interrupt_to_thread; rt_ubase_t rt_thread_switch_interrupt_flag; +const char *exception_name[] = { + "Interrupt", + "(X)TLB Modify Exception", + "(X)TLB Read/Fetch Exception", + "(X)TLB Write Exception", + "Address Read/Fetch Exception", + "Address Write Exception", + "", + "", + "Syscall", + "Breakpoint", + "Reversed Instruction Exception", + "Coprocessor Unit Invalid", + "Overflow", + "Trap", + "FPU Exception in Vector Instruction", + "FPU Exception", + "Loongson Custom Exception", + "", + "", + "(X)TLB Read Denied Exception", + "(X)TLB Execute Denied Exception", + "Vector Module Disabled Exception", + "", + "", + "", + "", + "", + "", + "", + "", + "Cache Error Exception", + "" + }; + rt_base_t rt_hw_interrupt_disable(void) { rt_base_t status = read_c0_status(); @@ -87,10 +122,11 @@ void cache_error_handler(void) static void unhandled_exception_handle(struct pt_regs *regs) { - rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), - read_c0_cause()); - rt_kprintf("ST0: 0x%08x ", regs->cp0_status); - rt_kprintf("ErrorPC: 0x%08x\n", read_c0_errorepc()); + rt_kprintf("Unknown Exception, EPC: 0x%p, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause()); + rt_kprintf("Exception Name:%s\n",exception_name[(read_c0_cause() >> 2) & 0x1f]); + rt_kprintf("ExeCode = 0x%08x,BadAddr = 0x%p\n",(read_c0_cause() >> 2) & 0x1f,mmu_tlb_get_bad_vaddr()); + rt_kprintf("ST0: 0x%08x ",regs->cp0_status); + rt_kprintf("ErrorPC: 0x%p\n",read_c0_errorepc()); mips_dump_regs(regs); rt_hw_cpu_shutdown(); } diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c new file mode 100644 index 0000000000..cfb4c6bb3c --- /dev/null +++ b/libcpu/mips/gs264/cache.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-29 quanzhao the first version + * 2020-07-26 lizhirui porting to ls2k + */ + +#include +#include + +rt_inline rt_uint64_t rt_cpu_icache_line_size(void) +{ + rt_uint64_t ctr; + return 4 << (ctr & 0xF); +} + +rt_inline rt_uint64_t rt_cpu_dcache_line_size(void) +{ + rt_uint64_t ctr; + return 4 << ((ctr >> 16) & 0xF); +} + +void rt_hw_cpu_icache_invalidate(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_icache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_dcache_invalidate(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_dcache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_dcache_clean(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_dcache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_icache_invalidate(addr, size); +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + rt_hw_cpu_dcache_clean(addr, size); + else if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_dcache_invalidate(addr, size); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} \ No newline at end of file diff --git a/libcpu/mips/gs264/cache.h b/libcpu/mips/gs264/cache.h new file mode 100644 index 0000000000..10a4afd899 --- /dev/null +++ b/libcpu/mips/gs264/cache.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-25 quanzhao the first version + */ +#ifndef __CACHE_H__ +#define __CACHE_H__ + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(unsigned int addr); + +#endif diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c new file mode 100644 index 0000000000..bfc694ab45 --- /dev/null +++ b/libcpu/mips/gs264/mips_mmu.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-26 lizhirui the first version + */ + +#include +#include + +#include "mips.h" +#include "mips_mmu.h" + +void mmu_init() +{ + uint32_t status = read_c0_status(); + status |= 0x07 << 5;//ux = 1,sx = 1,kx = 1 + write_c0_status(status); + + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +void mmu_set_cpu_mode(cpu_mode_t cpu_mode) +{ + uint32_t status = read_c0_status(); + status &= ~(0x03 << 3); + status |= ((uint32_t)cpu_mode & 0x03) << 3; + write_c0_status(status); +} + +cpu_mode_t mmu_get_cpu_mode() +{ + uint32_t status = read_c0_status(); + return (cpu_mode_t)((status >> 3) & 0x03); +} + +void mmu_clear_tlb() +{ + uint32_t max_tlb_index = mmu_get_max_tlb_index(); + uint64_t va = KSEG0BASE; + uint32_t entry; + tlb_item_t tlb_item; + + for(entry = 0;entry <= max_tlb_index;entry++) + { + mmu_tlb_item_init(&tlb_item); + mmu_tlb_write_indexed(entry,&tlb_item); + } +} + +void mmu_clear_itlb() +{ + uint32_t diag = read_c0_diag(); + write_c0_diag(diag | (0x01 << 2));//write ITLB bit + read_c0_entrylo0(); +} + +uint32_t mmu_get_max_tlb_index() +{ + uint32_t config1 = read_c0_config1(); + return ((config1 >> 25) & 0x3F); +} + +void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item) +{ + tlb_item -> entry_lo[0].g |= tlb_item -> entry_lo[1].g; + tlb_item -> entry_lo[1].g |= tlb_item -> entry_lo[0].g; + mmu_tlb_set_index(index); + write_c0_entrylo0(reg_type_convert(tlb_item -> entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item -> entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(tlb_item -> entry_hi,uint64_t)); + write_c0_pagemask(reg_type_convert(tlb_item -> page_mask,uint64_t)); + tlb_write_indexed(); + read_c0_entrylo0(); +} + +void mmu_tlb_write_random(tlb_item_t *tlb_item) +{ + tlb_item -> entry_lo[0].g |= tlb_item -> entry_lo[1].g; + tlb_item -> entry_lo[1].g |= tlb_item -> entry_lo[0].g; + write_c0_entrylo0(reg_type_convert(tlb_item -> entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item -> entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(tlb_item -> entry_hi,uint64_t)); + write_c0_pagemask(reg_type_convert(tlb_item -> page_mask,uint64_t)); + tlb_write_random(); + read_c0_entrylo0(); +} + +void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item) +{ + mmu_tlb_set_index(index); + tlb_read(); + uint64_t entrylo[2]; + uint64_t entryhi; + uint64_t page_mask; + entrylo[0] = read_c0_entrylo0(); + entrylo[1] = read_c0_entrylo1(); + entryhi = read_c0_entryhi(); + page_mask = read_c0_pagemask(); + tlb_item -> entry_lo[0] = reg_type_convert(entrylo[0],entry_lo_t); + tlb_item -> entry_lo[1] = reg_type_convert(entrylo[1],entry_lo_t); + tlb_item -> entry_hi = reg_type_convert(entryhi,entry_hi_t); + tlb_item -> page_mask = reg_type_convert(page_mask,page_mask_t); +} + +uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index) +{ + entry_hi_t entry_hi; + entry_hi.r = (vpn >> 62) & 0x03; + entry_hi.vpn2 = (vpn >> 13) & 0x7FFFFFFU; + entry_hi.asid = asid & 0xFFU; + tlb_item_t tlb_item; + //mmu_tlb_read(6,&tlb_item); + //tlb_dump(); + mmu_tlb_item_init(&tlb_item); + tlb_item.entry_lo[0].g = tlb_item.entry_lo[1].g = 1; + read_c0_entrylo0();//i don't know why,but if i don't read any register of mmu,tplb will be failed in qemu. + write_c0_entrylo0(reg_type_convert(tlb_item.entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item.entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(entry_hi,uint64_t)); + //__asm__ __volatile__("ehb"); + //read_c0_entryhi(); + //rt_kprintf("entry_hi = %p\n",read_c0_entryhi()); + tlb_probe(); + *index = mmu_tlb_get_index(); + return mmu_tlb_is_matched(); +} + +void mmu_tlb_item_init(tlb_item_t *tlb_item) +{ + memset(tlb_item,0,sizeof(tlb_item_t)); + tlb_item -> entry_lo[0].c = 0x03; + tlb_item -> entry_lo[1].c = 0x03; +} + +void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global) +{ + uint64_t page_mask_v = (uint64_t)page_mask; + + /*if(page_mask_v & (1 << 13)) + { + page_mask_v |= (1 << 12); + }*/ + + uint64_t lb = lowbit((~(page_mask_v)) << 12); + uint64_t pn_remained = ((~(page_mask_v)) << 12) | lb; + vpn &= pn_remained; + ppn &= pn_remained; + uint64_t odd_vpn = vpn | lb; + uint64_t even_vpn = vpn & (~lb); + uint32_t index; + tlb_item_t tlb_item,tlb2_item; + + mmu_tlb_item_init(&tlb_item); + mmu_tlb_item_init(&tlb2_item); + tlb_item.page_mask.mask = page_mask; + + if(mmu_tlb_find(vpn & (~lb),asid,&index)) + { + mmu_tlb_read(index,&tlb_item); + mmu_tlb_write_indexed(index,&tlb2_item); + } + + entry_lo_t *entry_lo = &tlb_item.entry_lo[vpn == even_vpn ? 0 : 1]; + tlb_item.entry_lo[0].g = tlb_item.entry_lo[1].g = global; + entry_lo -> d = 1; + entry_lo -> ri = 0; + entry_lo -> xi = 0; + entry_lo -> v = 1; + entry_lo -> pfn = ppn >> 12; + tlb_item.entry_hi.r = (vpn >> 62) & 0x03; + tlb_item.entry_hi.vpn2 = (vpn >> 13) & 0x7FFFFFFU; + tlb_item.entry_hi.asid = asid & 0xFFU; + mmu_tlb_write_random(&tlb_item); +} + +uint32_t mmu_tlb_get_random() +{ + return read_c0_random(); +} + +uint32_t mmu_tlb_get_index() +{ + return read_c0_index() & 0x3F; +} + +void mmu_tlb_set_index(uint32_t index) +{ + write_c0_index(index & 0x3F); +} + +uint32_t mmu_tlb_is_matched() +{ + return (read_c0_index() & 0x80000000) == 0; +} + +uint64_t mmu_tlb_get_bad_vaddr() +{ + return read_c0_badvaddr(); +} + +void tlb_dump() +{ + uint32_t max_index = mmu_get_max_tlb_index(); + //uint32_t max_index = 10; + uint32_t entry; + tlb_item_t tlb_item; + + for(entry = 0;entry <= max_index;entry++) + { + mmu_tlb_read(entry,&tlb_item); + //mmu_tlb_write_indexed(entry,&tlb_item); + //mmu_tlb_read(entry,&tlb_item); + rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c); + } +} \ No newline at end of file diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h new file mode 100644 index 0000000000..c0b33ecf89 --- /dev/null +++ b/libcpu/mips/gs264/mips_mmu.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-26 lizhirui the first version + */ + +#ifndef __MIPS_MMU_H__ +#define __MIPS_MMU_H__ + + typedef enum cpu_mode_t + { + CPU_MODE_KERNEL = 0x00, + CPU_MODE_SUPERVISOR = 0x01, + CPU_MODE_USER = 0x02 + }cpu_mode_t; + + typedef enum page_mask_enum_t + { + PAGE_MASK_4KB = 0x00, + PAGE_MASK_16KB = 0x03, + PAGE_MASK_64KB = 0x0F, + PAGE_MASK_256KB = 0x3F, + PAGE_MASK_1MB = 0xFF, + PAGE_MASK_4MB = 0x3FF, + PAGE_MASK_16MB = 0xFFF, + PAGE_MASK_64MB = 0x3FFF, + PAGE_MASK_256MB = 0xFFFF, + PAGE_MASK_1GB = 0x3FFFF + }page_mask_enum_t; + + typedef struct page_mask_t + { + uint64_t : 11; + uint64_t : 2; + uint64_t mask : 18; + uint64_t : 33; + }page_mask_t; + + typedef struct entry_lo_t + { + uint64_t g : 1; + uint64_t v : 1; + uint64_t d : 1; + uint64_t c : 3; + uint64_t pfn : 24; + uint64_t pfnx : 3; + uint64_t : 29; + uint64_t xi : 1; + uint64_t ri : 1; + }entry_lo_t; + + typedef struct entry_hi_t + { + uint64_t asid : 8; + uint64_t : 5; + uint64_t vpn2 : 27; + uint64_t : 22; + uint64_t r : 2; + }entry_hi_t; + + typedef struct tlb_item_t + { + entry_lo_t entry_lo[2]; + entry_hi_t entry_hi; + page_mask_t page_mask; + }tlb_item_t; + + #define read_c0_diag() __read_32bit_c0_register($22, 0) + #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) + #define read_c0_badvaddr() __read_64bit_c0_register($8, 0) + #define read_c0_random() __read_32bit_c0_register($1, 0) + + #define reg_type_convert(variable,new_type) *((new_type *)(&variable)) + #define lowbit(x) ((x) & (-(x))) + + void mmu_init(); + void mmu_set_cpu_mode(cpu_mode_t cpu_mode); + cpu_mode_t mmu_get_cpu_mode(); + void mmu_clear_tlb(); + void mmu_clear_itlb(); + uint32_t mmu_get_max_tlb_index(); + void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item); + void mmu_tlb_write_random(tlb_item_t *tlb_item); + void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item); + uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index); + void mmu_tlb_item_init(tlb_item_t *tlb_item); + void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global); + uint32_t mmu_tlb_get_random(); + uint32_t mmu_tlb_get_index(); + void mmu_tlb_set_index(uint32_t index); + uint32_t mmu_tlb_is_matched(); + uint64_t mmu_tlb_get_bad_vaddr(); + + void tlb_dump(); + +#endif \ No newline at end of file diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c new file mode 100644 index 0000000000..f6c73095d9 --- /dev/null +++ b/libcpu/mips/gs264/mipscfg.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-28 lizhirui first version + */ +#include +#include + +mips32_core_cfg_t g_mips_core = +{ + 64, /* icache_line_size */ + 128, /* icache_lines_per_way */ + 4, /* icache_ways */ + 32768, + 64, /* dcache_line_size */ + 128, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 32768, + 64, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** + * read core attribute + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c new file mode 100644 index 0000000000..b08bdf4c65 --- /dev/null +++ b/libcpu/mips/gs264/mmu.c @@ -0,0 +1,819 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + * 2020-07-26 lizhirui porting to ls2k + */ + +#include +#include +#include + +#include "cache.h" +#include "mips_mmu.h" +#include "mmu.h" + +void *current_mmu_table = RT_NULL; + +void *mmu_table_get() +{ + return current_mmu_table; +} + +void switch_mmu(void *mmu_table) +{ + current_mmu_table = mmu_table; + + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + //asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + //asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_cpu_dcache_clean(void *addr, int size); +void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) +{ + /* set page table */ + for(; size > 0; size--) + { + rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, + mdesc->paddr_start, mdesc->attr); + mdesc++; + } + rt_hw_cpu_dcache_clean((void*)MMUTable, sizeof MMUTable); +} + +void rt_hw_mmu_init(void) +{ + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + +/* + mem map +*/ + +void rt_hw_cpu_dcache_clean(void *addr, int size); + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off) +{ + size_t l1_off, va_s, va_e; + rt_base_t level; + + if (!mmu_info || !vtable) + { + return -1; + } + + va_s = (size_t)v_address; + va_e = (size_t)v_address + size - 1; + + if ( va_e < va_s) + { + return -1; + } + + va_s >>= ARCH_SECTION_SHIFT; + va_e >>= ARCH_SECTION_SHIFT; + + if (va_s == 0) + { + return -1; + } + + level = rt_hw_interrupt_disable(); + + for (l1_off = va_s; l1_off <= va_e; l1_off++) + { + size_t v = vtable[l1_off]; + + if (v & ARCH_MMU_USED_MASK) + { + rt_kprintf("Error:vtable[%d] = 0x%p(is not zero),va_s = 0x%p,va_e = 0x%p!\n",l1_off,v,va_s,va_e); + rt_hw_interrupt_enable(level); + return -1; + } + } + + mmu_info->vtable = vtable; + mmu_info->vstart = va_s; + mmu_info->vend = va_e; + mmu_info->pv_off = pv_off; + + rt_hw_interrupt_enable(level); + + return 0; +} + +static size_t find_vaddr(rt_mmu_info *mmu_info, int pages) +{ + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t find_off = 0; + size_t find_va = 0; + int n = 0; + + if (!pages) + { + return 0; + } + + if (!mmu_info) + { + return 0; + } + + for (l1_off = mmu_info->vstart; l1_off <= mmu_info->vend; l1_off++) + { + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + for (l2_off = 0; l2_off < (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); l2_off++) + { + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + /* in use */ + n = 0; + } + else + { + if (!n) + { + find_va = l1_off; + find_off = l2_off; + } + n++; + if (n >= pages) + { + return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT); + } + } + } + } + else + { + if (!n) + { + find_va = l1_off; + find_off = 0; + } + n += (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + if (n >= pages) + { + return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT); + } + } + } + return 0; +} + +#ifdef RT_USING_USERSPACE +static int check_vaddr(rt_mmu_info *mmu_info, void *va, int pages) +{ + size_t loop_va = (size_t)va & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + + if (!pages) + { + return -1; + } + + if (!mmu_info) + { + return -1; + } + + while (pages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + return -1; + } + } + loop_va += ARCH_PAGE_SIZE; + } + return 0; +} +#endif + +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return; + } + + while (npages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + if (l1_off < mmu_info->vstart || l1_off > mmu_info->vend) + { + return; + } + + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { + return; + } + + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + *(mmu_l2 + l2_off) = 0; + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)--; + if (!*ref_cnt) + { +#ifdef RT_USING_USERSPACE + rt_pages_free(mmu_l2, 0); +#else + rt_free_align(mmu_l2); +#endif + *mmu_l1 = 0; + + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + } + loop_va += ARCH_PAGE_SIZE; + } +} + +static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa = (size_t)p_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { +#ifdef RT_USING_USERSPACE + mmu_l2 = (size_t*)rt_pages_alloc(0); +#else + mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); +#endif + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + { + /* error, unmap and quit */ + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } + } + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)++; + + *(mmu_l2 + l2_off) = (loop_pa | attr); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + loop_va += ARCH_PAGE_SIZE; + loop_pa += ARCH_PAGE_SIZE; + } + return 0; +} + +static void rt_hw_cpu_tlb_invalidate(void) +{ + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +#ifdef RT_USING_USERSPACE +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + if (!size) + { + return 0; + } + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + if (v_addr) + { + vaddr = (size_t)v_addr; + pa_s = (size_t)p_addr; + if ((vaddr & ARCH_PAGE_MASK) != (pa_s & ARCH_PAGE_MASK)) + { + return 0; + } + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#else +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + vaddr = find_vaddr(mmu_info, pages); + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#endif + +#ifdef RT_USING_USERSPACE +static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void* v_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + loop_pa = (size_t)rt_pages_alloc(0) + mmu_info->pv_off; + if (!loop_pa) + goto err; + + //rt_kprintf("vaddr = %08x is mapped to paddr = %08x\n",v_addr,loop_pa); + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { + //mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); + mmu_l2 = (size_t*)rt_pages_alloc(0); + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + goto err; + } + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)++; + + //loop_pa += mmu_info->pv_off; + *(mmu_l2 + l2_off) = (loop_pa | attr); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + loop_va += ARCH_PAGE_SIZE; + } + return 0; +err: + { + /* error, unmap and quit */ + int i; + void *va, *pa; + + va = (void*)((size_t)v_addr & ~ARCH_PAGE_MASK); + for (i = 0; i < npages; i++) + { + pa = rt_hw_mmu_v2p(mmu_info, va); + pa -= mmu_info->pv_off; + rt_pages_free(pa, 0); + va += ARCH_PAGE_SIZE; + } + + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } +} + +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) +{ + size_t vaddr; + size_t offset; + int pages; + int ret; + + if (!size) + { + return 0; + } + offset = (size_t)v_addr & ARCH_PAGE_MASK; + size += (offset + ARCH_PAGE_SIZE - 1); + pages = (size >> ARCH_PAGE_SHIFT); + if (v_addr) + { + vaddr = (size_t)v_addr; + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) { + ret = __rt_hw_mmu_map_auto(mmu_info, (void*)vaddr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)vaddr + offset; + } + } + return 0; +} +#endif + +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size) +{ + size_t va_s, va_e; + int pages; + + va_s = (size_t)v_addr; + va_e = (size_t)v_addr + size - 1; + va_s >>= ARCH_PAGE_SHIFT; + va_e >>= ARCH_PAGE_SHIFT; + pages = va_e - va_s + 1; + __rt_hw_mmu_unmap(mmu_info, v_addr, pages); + rt_hw_cpu_tlb_invalidate(); +} + +//va --> pa +void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size) +{ + void *p_addr = 0; + + return p_addr; +} + +//pa --> va +void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size) +{ + void *v_addr = 0; + + #ifdef RT_USING_USERSPACE + extern rt_mmu_info mmu_info; + v_addr = rt_hw_mmu_map(&mmu_info, 0, p_addr, size, MMU_MAP_K_RW); + #else + v_addr = p_addr; + #endif + + return v_addr; +} + +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info, v_addr, p_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} + +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map_auto(mmu_info, v_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} +#endif + +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + _rt_hw_mmu_unmap(mmu_info, v_addr, size); + rt_hw_interrupt_enable(level); +} + +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) +{ + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t tmp; + size_t pa; + + l1_off = (size_t)v_addr >> ARCH_SECTION_SHIFT; + + if (!mmu_info) + { + return (void*)0; + } + + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + tmp = *mmu_l1; + + switch (tmp & ARCH_MMU_USED_MASK) + { + case 0: /* not used */ + break; + case 1: /* page table */ + mmu_l2 = (size_t *)((tmp & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + l2_off = (((size_t)v_addr & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + pa = *(mmu_l2 + l2_off); + if (pa & ARCH_MMU_USED_MASK) + { + if ((pa & ARCH_MMU_USED_MASK) == 1) + { + /* lage page, not support */ + break; + } + pa &= ~(ARCH_PAGE_MASK); + pa += ((size_t)v_addr & ARCH_PAGE_MASK); + return (void*)pa; + } + break; + case 2: + case 3: + /* section */ + if (tmp & ARCH_TYPE_SUPERSECTION) + { + /* super section, not support */ + break; + } + pa = (tmp & ~ARCH_SECTION_MASK); + pa += ((size_t)v_addr & ARCH_SECTION_MASK); + return (void*)pa; + } + return (void*)0; +} + +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_v2p(mmu_info, v_addr); + rt_hw_interrupt_enable(level); + return ret; +} + +#ifdef RT_USING_USERSPACE +void init_mm_setup(unsigned int *mtbl, unsigned int size, unsigned int pv_off) { + unsigned int va; + + for (va = 0; va < 0x1000; va++) { + unsigned int vaddr = (va << 20); + if (vaddr >= KERNEL_VADDR_START && vaddr - KERNEL_VADDR_START < size) { + mtbl[va] = ((va << 20) + pv_off) | NORMAL_MEM; + } else if (vaddr >= (KERNEL_VADDR_START + pv_off) && vaddr - (KERNEL_VADDR_START + pv_off) < size) { + mtbl[va] = (va << 20) | NORMAL_MEM; + } else { + mtbl[va] = 0; + } + } +} +#endif diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h new file mode 100644 index 0000000000..f2d4d11bc3 --- /dev/null +++ b/libcpu/mips/gs264/mmu.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-25 quanzhao the first version + * 2020-07-26 lizhirui porting to ls2k + */ +#ifndef __MMU_H_ +#define __MMU_H_ + +#include + +#define DESC_SEC (0x2) +#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ +#define MEMWB (3<<2) /* write back, no write allocate */ +#define MEMWT (2<<2) /* write through, no write allocate */ +#define SHAREDEVICE (1<<2) /* shared device */ +#define STRONGORDER (0<<2) /* strong ordered */ +#define XN (1<<4) /* eXecute Never */ +#ifdef RT_USING_USERSPACE +#define AP_RW (1<<10) /* supervisor=RW, user=No */ +#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ +#else +#define AP_RW (3<<10) /* supervisor=RW, user=RW */ +#define AP_RO ((2<<10) /* supervisor=RW, user=RO */ +#endif + +#define SHARED (1<<16) /* shareable */ + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* device mapping type */ +#define DEVICE_MEM (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN) +/* normal memory mapping type */ +#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC) + +#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC) + +struct mem_desc +{ + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t attr; +}; + +#define MMU_MAP_MTBL_XN (1<<0) +#define MMU_MAP_MTBL_A (1<<1) +#define MMU_MAP_MTBL_B (1<<2) +#define MMU_MAP_MTBL_C (1<<3) +#define MMU_MAP_MTBL_AP01(x) (x<<4) +#define MMU_MAP_MTBL_TEX(x) (x<<6) +#define MMU_MAP_MTBL_AP2(x) (x<<9) +#define MMU_MAP_MTBL_SHARE (1<<10) + +#define MMU_MAP_K_RO (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_RWCB (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_RW (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_DEVICE (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RO (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RWCB (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RW (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_DEVICE (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE) + +#define ARCH_SECTION_SHIFT 20 +#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT) +#define ARCH_SECTION_MASK (ARCH_SECTION_SIZE - 1) +#define ARCH_PAGE_SHIFT 14 +#define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT) +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_TBL_SHIFT 10 +#define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT) +#define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1) + +#define ARCH_MMU_USED_MASK 3 + +#define ARCH_TYPE_SUPERSECTION (1 << 18) + +typedef struct +{ + size_t *vtable; + size_t vstart; + size_t vend; + size_t pv_off; +} rt_mmu_info; + +void *mmu_table_get(); +void switch_mmu(void *mmu_table); + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off); +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr); +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr); +#else +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr); +#endif +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size); +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr); + +void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size); +void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size); + +#endif -- cgit v1.3.1 From c66314a8b6a12412e34440e8369d9c77d43aaada Mon Sep 17 00:00:00 2001 From: bigmagic Date: Fri, 4 Sep 2020 11:57:35 +0800 Subject: fixed loongson bsp build on windows --- bsp/ls1bdev/SConstruct | 1 + bsp/ls1cdev/SConstruct | 2 +- libcpu/mips/common/exception.c | 4 ++++ 3 files changed, 6 insertions(+), 1 deletion(-) (limited to 'libcpu') diff --git a/bsp/ls1bdev/SConstruct b/bsp/ls1bdev/SConstruct index 3fe0da6a6f..a77c5dfd9b 100644 --- a/bsp/ls1bdev/SConstruct +++ b/bsp/ls1bdev/SConstruct @@ -11,6 +11,7 @@ sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * TARGET = 'rtthread.' + rtconfig.TARGET_EXT +rtconfig.AFLAGS += ' -I' + str('.') + ' -I ' + RTT_ROOT + '/libcpu/mips/common/' DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], diff --git a/bsp/ls1cdev/SConstruct b/bsp/ls1cdev/SConstruct index 4ea8c066ec..0541a75c4f 100644 --- a/bsp/ls1cdev/SConstruct +++ b/bsp/ls1cdev/SConstruct @@ -12,7 +12,7 @@ from building import * TARGET = 'rtthread.' + rtconfig.TARGET_EXT -rtconfig.AFLAGS += ' -I' + str(Dir('#')) +rtconfig.AFLAGS += ' -I' + str('.') + ' -I ' + RTT_ROOT + '/libcpu/mips/gs232/'+ ' -I ' + RTT_ROOT + '/libcpu/mips/common/' DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index 8eb89b1e1b..94be475878 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -124,7 +124,11 @@ static void unhandled_exception_handle(struct pt_regs *regs) { rt_kprintf("Unknown Exception, EPC: 0x%p, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause()); rt_kprintf("Exception Name:%s\n",exception_name[(read_c0_cause() >> 2) & 0x1f]); +#ifdef SOC_LS2K1000 rt_kprintf("ExeCode = 0x%08x,BadAddr = 0x%p\n",(read_c0_cause() >> 2) & 0x1f,mmu_tlb_get_bad_vaddr()); +#else + rt_kprintf("ExeCode = 0x%08x\n",(read_c0_cause() >> 2) & 0x1f); +#endif rt_kprintf("ST0: 0x%08x ",regs->cp0_status); rt_kprintf("ErrorPC: 0x%p\n",read_c0_errorepc()); mips_dump_regs(regs); -- cgit v1.3.1 From 60287b69fdff377ea9fdfd2f06b4ea3f6f34e32a Mon Sep 17 00:00:00 2001 From: chenzx Date: Fri, 11 Sep 2020 10:11:25 +0800 Subject: add t-head smart-evb bsp, and risc-v cpu e906 --- bsp/thead-smart/.config | 417 +++++ bsp/thead-smart/Kconfig | 36 + bsp/thead-smart/README.md | 45 + bsp/thead-smart/SConscript | 14 + bsp/thead-smart/SConstruct | 33 + bsp/thead-smart/applications/SConscript | 13 + bsp/thead-smart/applications/main.c | 19 + bsp/thead-smart/drivers/SConscript | 13 + bsp/thead-smart/drivers/board.c | 48 + bsp/thead-smart/drivers/board.h | 18 + bsp/thead-smart/drivers/board_uart.c | 207 +++ bsp/thead-smart/drivers/ck_irq.c | 88 + bsp/thead-smart/drivers/ck_usart.c | 1141 +++++++++++++ bsp/thead-smart/drivers/ck_usart.h | 92 + bsp/thead-smart/drivers/core_rv32.h | 1130 ++++++++++++ bsp/thead-smart/drivers/csi_config.h | 29 + bsp/thead-smart/drivers/csi_core.h | 53 + bsp/thead-smart/drivers/csi_rv32_gcc.h | 2849 +++++++++++++++++++++++++++++++ bsp/thead-smart/drivers/drv_common.h | 59 + bsp/thead-smart/drivers/drv_errno.h | 96 ++ bsp/thead-smart/drivers/drv_gpio.h | 144 ++ bsp/thead-smart/drivers/drv_irq.h | 41 + bsp/thead-smart/drivers/drv_timer.h | 154 ++ bsp/thead-smart/drivers/drv_usart.h | 446 +++++ bsp/thead-smart/drivers/dw_gpio.c | 635 +++++++ bsp/thead-smart/drivers/dw_gpio.h | 52 + bsp/thead-smart/drivers/dw_timer.c | 409 +++++ bsp/thead-smart/drivers/dw_timer.h | 48 + bsp/thead-smart/drivers/isr.c | 195 +++ bsp/thead-smart/drivers/novic_irq_tbl.c | 32 + bsp/thead-smart/drivers/pin_name.h | 56 + bsp/thead-smart/drivers/soc.h | 119 ++ bsp/thead-smart/drivers/startup_gcc.S | 132 ++ bsp/thead-smart/drivers/sys_freq.c | 61 + bsp/thead-smart/drivers/sys_freq.h | 36 + bsp/thead-smart/drivers/system.c | 85 + bsp/thead-smart/drivers/trap_c.c | 50 + bsp/thead-smart/drivers/vectors.S | 349 ++++ bsp/thead-smart/gcc_csky.ld | 184 ++ bsp/thead-smart/rtconfig.h | 158 ++ bsp/thead-smart/rtconfig.py | 68 + libcpu/risc-v/SConscript | 13 +- libcpu/risc-v/t-head/e906/SConscript | 12 + libcpu/risc-v/t-head/e906/context_gcc.S | 323 ++++ libcpu/risc-v/t-head/e906/cpuport.c | 170 ++ libcpu/risc-v/t-head/e906/cpuport.h | 55 + 46 files changed, 10424 insertions(+), 3 deletions(-) create mode 100644 bsp/thead-smart/.config create mode 100644 bsp/thead-smart/Kconfig create mode 100644 bsp/thead-smart/README.md create mode 100644 bsp/thead-smart/SConscript create mode 100644 bsp/thead-smart/SConstruct create mode 100644 bsp/thead-smart/applications/SConscript create mode 100644 bsp/thead-smart/applications/main.c create mode 100644 bsp/thead-smart/drivers/SConscript create mode 100644 bsp/thead-smart/drivers/board.c create mode 100644 bsp/thead-smart/drivers/board.h create mode 100644 bsp/thead-smart/drivers/board_uart.c create mode 100644 bsp/thead-smart/drivers/ck_irq.c create mode 100644 bsp/thead-smart/drivers/ck_usart.c create mode 100644 bsp/thead-smart/drivers/ck_usart.h create mode 100644 bsp/thead-smart/drivers/core_rv32.h create mode 100644 bsp/thead-smart/drivers/csi_config.h create mode 100644 bsp/thead-smart/drivers/csi_core.h create mode 100644 bsp/thead-smart/drivers/csi_rv32_gcc.h create mode 100644 bsp/thead-smart/drivers/drv_common.h create mode 100644 bsp/thead-smart/drivers/drv_errno.h create mode 100644 bsp/thead-smart/drivers/drv_gpio.h create mode 100644 bsp/thead-smart/drivers/drv_irq.h create mode 100644 bsp/thead-smart/drivers/drv_timer.h create mode 100644 bsp/thead-smart/drivers/drv_usart.h create mode 100644 bsp/thead-smart/drivers/dw_gpio.c create mode 100644 bsp/thead-smart/drivers/dw_gpio.h create mode 100644 bsp/thead-smart/drivers/dw_timer.c create mode 100644 bsp/thead-smart/drivers/dw_timer.h create mode 100644 bsp/thead-smart/drivers/isr.c create mode 100644 bsp/thead-smart/drivers/novic_irq_tbl.c create mode 100644 bsp/thead-smart/drivers/pin_name.h create mode 100644 bsp/thead-smart/drivers/soc.h create mode 100644 bsp/thead-smart/drivers/startup_gcc.S create mode 100644 bsp/thead-smart/drivers/sys_freq.c create mode 100644 bsp/thead-smart/drivers/sys_freq.h create mode 100644 bsp/thead-smart/drivers/system.c create mode 100644 bsp/thead-smart/drivers/trap_c.c create mode 100644 bsp/thead-smart/drivers/vectors.S create mode 100644 bsp/thead-smart/gcc_csky.ld create mode 100644 bsp/thead-smart/rtconfig.h create mode 100644 bsp/thead-smart/rtconfig.py create mode 100644 libcpu/risc-v/t-head/e906/SConscript create mode 100644 libcpu/risc-v/t-head/e906/context_gcc.S create mode 100644 libcpu/risc-v/t-head/e906/cpuport.c create mode 100644 libcpu/risc-v/t-head/e906/cpuport.h (limited to 'libcpu') diff --git a/bsp/thead-smart/.config b/bsp/thead-smart/.config new file mode 100644 index 0000000000..d0dbd85a46 --- /dev/null +++ b/bsp/thead-smart/.config @@ -0,0 +1,417 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40003 + +# +# RT-Thread CPU arch and features +# +# CONFIG_ARCH_CSKY is not set + +# +# risc-v arch +# +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV_32=y +# CONFIG_ARCH_RISCV_64 is not set +CONFIG_ARCH_RISCV_FPU=y +CONFIG_ARCH_RISCV_FPU_S=y +# CONFIG_ARCH_RISCV_FPU_D is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=1 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=2048 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_URLENCODE is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_THEAD_SMART=y +CONFIG_RT_USING_UART1=y diff --git a/bsp/thead-smart/Kconfig b/bsp/thead-smart/Kconfig new file mode 100644 index 0000000000..b2fde84dc0 --- /dev/null +++ b/bsp/thead-smart/Kconfig @@ -0,0 +1,36 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_THEAD_SMART + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +if RT_USING_SERIAL + + config RT_USING_UART1 + bool "Using uart1" + default y + +endif diff --git a/bsp/thead-smart/README.md b/bsp/thead-smart/README.md new file mode 100644 index 0000000000..990818a606 --- /dev/null +++ b/bsp/thead-smart/README.md @@ -0,0 +1,45 @@ +# T-HEAD SMART-EVB Introduction +SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide implementation, integrating T-HEAD's RISC-V CPU (eg. E902/E906/C906) and C-SKY CPU (eg. E805/E804/E803/E802 ), integrates basic peripheral resources such as GPIO/TIMER/UART/RAM. + +##The main resources on board are as follows: +1. SMART-EVB for E906/E906F/E906FD +| res | description | +| -- | -- | +|ISA | RISCV | +|CPU | E906 | +|FREQ| 20MHz | +|SRAM| 768KB | + + +2. SMART-EVB for E804/E804F/E804D +| res | description | +| -- | -- | +|ISA | C-SKY | +|CPU | E804 | +|FREQ| 20MHz | +|SRAM| 768KB | + + +# Compile T-HEAD BSP +SMART-EVB BSP supports GCC compiler, the version information is: +1. SMART-EVB for E906/E906F/E906FD +| IDE/Compiler| version| +| - | - | +| GCC | gcc version 8.4.0 (C-SKY RISCV Tools V1.9.6 B20200616) | + +# run smart-evb bsp +1. Connect JTAG +2. Connect the serial port +3. riscv64-unknown-elf-gdb rtthread-e906f.elf + +run log as follows: +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Sep 2 2020 + 2006 - 2020 Copyright by rt-thread team +msh > +``` + + + diff --git a/bsp/thead-smart/SConscript b/bsp/thead-smart/SConscript new file mode 100644 index 0000000000..744d8d7821 --- /dev/null +++ b/bsp/thead-smart/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/thead-smart/SConstruct b/bsp/thead-smart/SConstruct new file mode 100644 index 0000000000..9a283c2884 --- /dev/null +++ b/bsp/thead-smart/SConstruct @@ -0,0 +1,33 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-' + rtconfig.CPU + '.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], +AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, +CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, +CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, +AR = rtconfig.AR, ARFLAGS = '-rc', +LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +# add --start-group and --end-group for GNU GCC +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/thead-smart/applications/SConscript b/bsp/thead-smart/applications/SConscript new file mode 100644 index 0000000000..b95023ca41 --- /dev/null +++ b/bsp/thead-smart/applications/SConscript @@ -0,0 +1,13 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = GetCurrentDir() + +CCFLAGS = ' -c -ffunction-sections' + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CCFLAGS=CCFLAGS) + +Return('group') diff --git a/bsp/thead-smart/applications/main.c b/bsp/thead-smart/applications/main.c new file mode 100644 index 0000000000..61046f4a4b --- /dev/null +++ b/bsp/thead-smart/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen first version + */ + +#include + +int main(void) +{ + + return 0; +} + +/*@}*/ diff --git a/bsp/thead-smart/drivers/SConscript b/bsp/thead-smart/drivers/SConscript new file mode 100644 index 0000000000..96f82751bb --- /dev/null +++ b/bsp/thead-smart/drivers/SConscript @@ -0,0 +1,13 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Glob("*.c") + Glob("*.cpp") + Glob("*.S") + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/thead-smart/drivers/board.c b/bsp/thead-smart/drivers/board.c new file mode 100644 index 0000000000..386d40d3a5 --- /dev/null +++ b/bsp/thead-smart/drivers/board.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen add T-HEAD header file csi_core.h + */ + +#include +#include + +#include "board.h" +#include "csi_core.h" +#include "drv_usart.h" + +extern int __bss_end__; +#define SYS_HEAP_BEGIN (&__bss_end__) + +#include "core_rv32.h" + + +extern usart_handle_t console_handle; +extern void ioreuse_initial(void); + + +/** + * This function will initial smartl-evb(e906) board. + */ +void rt_hw_board_init(void) +{ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + /* initialize hardware usart */ + rt_hw_usart_init(); + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)SYS_HEAP_BEGIN, (void *)E906FD_IRAM_END); +#endif +} + +/*@}*/ diff --git a/bsp/thead-smart/drivers/board.h b/bsp/thead-smart/drivers/board.h new file mode 100644 index 0000000000..786246bd9a --- /dev/null +++ b/bsp/thead-smart/drivers/board.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen add E906 ram size + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#define APB_DEFAULT_FREQ 20000000 /* Hz */ +#define E906FD_IRAM_SIZE 128 +#define E906FD_IRAM_END (0x20000000 + E906FD_IRAM_SIZE * 1024) + +#endif /* __BOARD_H__ */ diff --git a/bsp/thead-smart/drivers/board_uart.c b/bsp/thead-smart/drivers/board_uart.c new file mode 100644 index 0000000000..d4f857f0bb --- /dev/null +++ b/bsp/thead-smart/drivers/board_uart.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen first implementation + */ + +#include + +#ifdef RT_USING_CONSOLE + +#include +#include + +#include +#include +#include +#include + +#include "board.h" +#include "soc.h" +#include "ck_usart.h" +#include "drv_usart.h" +#include "pin_name.h" + + + +__attribute__((isr)) void ck_usart0_irqhandler(void); + +struct +{ + uint32_t base; + uint32_t irq; + void *handler; +} +const sg_usart_config[CONFIG_USART_NUM] = +{ + {CSKY_UART_BASE, UART_IRQn, ck_usart0_irqhandler}, +}; + + +int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq, void **handler) +{ + if (idx >= CONFIG_USART_NUM) + { + return -1; + } + + if (base != NULL) + { + *base = sg_usart_config[idx].base; + } + + if (irq != NULL) + { + *irq = sg_usart_config[idx].irq; + } + + if (handler != NULL) + { + *handler = sg_usart_config[idx].handler; + } + + return idx; +} + + +#ifdef RT_USING_UART1 +#define UART_TXD1 PA10_TXD1_PWM1_XX_SIROUT1 +#define UART_RXD1 PA11_RXD1_PWM2_XX_SIRIN1 + +static usart_handle_t uart1_handle; +static struct rt_serial_device serial1; + +__attribute__((isr)) void ck_usart0_irqhandler(void) +{ + rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_RX_IND); +} +#endif + +/* + * UART interface + */ +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + int ret; + usart_handle_t uart; + + uint32_t bauds; + usart_mode_e mode; + usart_parity_e parity; + usart_stop_bits_e stopbits; + usart_data_bits_e databits; + + RT_ASSERT(serial != RT_NULL); + uart = (usart_handle_t)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + /* set baudrate parity...*/ + bauds = cfg->baud_rate; + mode = USART_MODE_ASYNCHRONOUS; + + if (cfg->parity == PARITY_EVEN) + parity = USART_PARITY_EVEN; + else if (cfg->parity == PARITY_ODD) + parity = USART_PARITY_ODD; + else + parity = USART_PARITY_NONE; + + stopbits = USART_STOP_BITS_1 ; + databits = USART_DATA_BITS_8; + + ret = csi_usart_config(uart, bauds, USART_MODE_ASYNCHRONOUS, parity, stopbits, databits); + + if (ret < 0) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + usart_handle_t uart; + + RT_ASSERT(serial != RT_NULL); + uart = (usart_handle_t)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* Disable the UART Interrupt */ + ck_usart_clr_int_flag(uart,IER_RDA_INT_ENABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* Enable the UART Interrupt */ + ck_usart_set_int_flag(uart,IER_RDA_INT_ENABLE); + break; + } + + return (RT_EOK); +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + usart_handle_t uart; + + RT_ASSERT(serial != RT_NULL); + uart = (usart_handle_t)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + csi_usart_putchar(uart,c); + + return (1); +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + usart_handle_t uart; + + RT_ASSERT(serial != RT_NULL); + uart = (usart_handle_t)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + + ch = csi_uart_getchar(uart); + + return ch; +} + +const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + + +int rt_hw_usart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef RT_USING_UART1 + serial1.ops = & _uart_ops; + serial1.config = config; + serial1.config.bufsz = 2048; + serial1.config.baud_rate = 115200; + + uart1_handle = csi_usart_initialize(0, NULL); + + rt_hw_serial_register(&serial1, + "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart1_handle); +#endif + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_usart_init); +#endif diff --git a/bsp/thead-smart/drivers/ck_irq.c b/bsp/thead-smart/drivers/ck_irq.c new file mode 100644 index 0000000000..8863ec7580 --- /dev/null +++ b/bsp/thead-smart/drivers/ck_irq.c @@ -0,0 +1,88 @@ + +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen CSI Source File for IRQ Driver + */ + +#include +#include +#include +#include + +extern void Default_Handler(void); +extern void (*g_irqvector[])(void); +extern void (*g_nmivector)(void); + +/** + \brief enable irq. + \param[in] irq_num Number of IRQ. + \return None. +*/ +void drv_irq_enable(uint32_t irq_num) +{ + if (NMI_EXPn != irq_num) + { + #ifdef CONFIG_SYSTEM_SECURE + csi_vic_enable_sirq(irq_num); + #else + csi_vic_enable_irq(irq_num); + #endif + } +} + +/** + \brief disable irq. + \param[in] irq_num Number of IRQ. + \return None. +*/ +void drv_irq_disable(uint32_t irq_num) +{ + if (NMI_EXPn != irq_num) + { + #ifdef CONFIG_SYSTEM_SECURE + csi_vic_disable_sirq(irq_num); + #else + csi_vic_disable_irq(irq_num); + #endif + } +} + +/** + \brief register irq handler. + \param[in] irq_num Number of IRQ. + \param[in] irq_handler IRQ Handler. + \return None. +*/ +void drv_irq_register(uint32_t irq_num, void *irq_handler) +{ + if (NMI_EXPn != irq_num) + { + g_irqvector[irq_num] = irq_handler; + } + else + { + g_nmivector = irq_handler; + } +} + +/** + \brief unregister irq handler. + \param[in] irq_num Number of IRQ. + \return None. +*/ +void drv_irq_unregister(uint32_t irq_num) +{ + if (NMI_EXPn != irq_num) + { + g_irqvector[irq_num] = (void *)Default_Handler; + } + else + { + g_nmivector = (void *)Default_Handler; + } +} diff --git a/bsp/thead-smart/drivers/ck_usart.c b/bsp/thead-smart/drivers/ck_usart.c new file mode 100644 index 0000000000..bedec214ab --- /dev/null +++ b/bsp/thead-smart/drivers/ck_usart.c @@ -0,0 +1,1141 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen CSI Source File for usart Driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ERR_USART(errno) (CSI_DRV_ERRNO_USART_BASE | errno) + +/* + * setting config may be accessed when the USART is not + * busy(USR[0]=0) and the DLAB bit(LCR[7]) is set. + */ + +#define WAIT_USART_IDLE(addr)\ + do { \ + int32_t timecount = 0; \ + while ((addr->USR & USR_UART_BUSY) && (timecount < UART_BUSY_TIMEOUT)) {\ + timecount++;\ + }\ + if (timecount >= UART_BUSY_TIMEOUT) {\ + return ERR_USART(DRV_ERROR_TIMEOUT);\ + } \ + } while(0) + +#define USART_NULL_PARAM_CHK(para) HANDLE_PARAM_CHK(para, ERR_USART(DRV_ERROR_PARAMETER)) + +typedef struct +{ + uint32_t base; + uint32_t irq; + usart_event_cb_t cb_event; ///< Event callback + uint32_t rx_total_num; + uint32_t tx_total_num; + uint8_t *rx_buf; + uint8_t *tx_buf; + volatile uint32_t rx_cnt; + volatile uint32_t tx_cnt; + volatile uint32_t tx_busy; + volatile uint32_t rx_busy; + uint32_t last_tx_num; + uint32_t last_rx_num; + int32_t idx; +} ck_usart_priv_t; + +extern int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq, void **handler); + +static ck_usart_priv_t usart_instance[CONFIG_USART_NUM]; + +static const usart_capabilities_t usart_capabilities = +{ + .asynchronous = 1, /* supports USART (Asynchronous) mode */ + .synchronous_master = 0, /* supports Synchronous Master mode */ + .synchronous_slave = 0, /* supports Synchronous Slave mode */ + .single_wire = 0, /* supports USART Single-wire mode */ + .event_tx_complete = 1, /* Transmit completed event */ + .event_rx_timeout = 0, /* Signal receive character timeout event */ +}; + +/** + \brief set the bautrate of usart. + \param[in] addr usart base to operate. + \return error code +*/ +int32_t csi_usart_config_baudrate(usart_handle_t handle, uint32_t baud) +{ + USART_NULL_PARAM_CHK(handle); + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + + WAIT_USART_IDLE(addr); + + /* baudrate=(seriak clock freq)/(16*divisor); algorithm :rounding*/ + uint32_t divisor = ((drv_get_usart_freq(usart_priv->idx) * 10) / baud) >> 4; + + if ((divisor % 10) >= 5) + { + divisor = (divisor / 10) + 1; + } else + { + divisor = divisor / 10; + } + + addr->LCR |= LCR_SET_DLAB; + /* DLL and DLH is lower 8-bits and higher 8-bits of divisor.*/ + addr->DLL = divisor & 0xff; + addr->DLH = (divisor >> 8) & 0xff; + /* + * The DLAB must be cleared after the baudrate is setted + * to access other registers. + */ + addr->LCR &= (~LCR_SET_DLAB); + + return 0; +} + +/** + \brief config usart mode. + \param[in] handle usart handle to operate. + \param[in] mode \ref usart_mode_e + \return error code +*/ +int32_t csi_usart_config_mode(usart_handle_t handle, usart_mode_e mode) +{ + USART_NULL_PARAM_CHK(handle); + + if (mode == USART_MODE_ASYNCHRONOUS) + { + return 0; + } + + return ERR_USART(USART_ERROR_MODE); +} + +/** + \brief config usart parity. + \param[in] handle usart handle to operate. + \param[in] parity \ref usart_parity_e + \return error code +*/ +int32_t csi_usart_config_parity(usart_handle_t handle, usart_parity_e parity) +{ + USART_NULL_PARAM_CHK(handle); + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + WAIT_USART_IDLE(addr); + + switch (parity) + { + case USART_PARITY_NONE: + /*CLear the PEN bit(LCR[3]) to disable parity.*/ + addr->LCR &= (~LCR_PARITY_ENABLE); + break; + + case USART_PARITY_ODD: + /* Set PEN and clear EPS(LCR[4]) to set the ODD parity. */ + addr->LCR |= LCR_PARITY_ENABLE; + addr->LCR &= LCR_PARITY_ODD; + break; + + case USART_PARITY_EVEN: + /* Set PEN and EPS(LCR[4]) to set the EVEN parity.*/ + addr->LCR |= LCR_PARITY_ENABLE; + addr->LCR |= LCR_PARITY_EVEN; + break; + + default: + return ERR_USART(USART_ERROR_PARITY); + } + + return 0; +} + +/** + \brief config usart stop bit number. + \param[in] handle usart handle to operate. + \param[in] stopbits \ref usart_stop_bits_e + \return error code +*/ +int32_t csi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit) +{ + USART_NULL_PARAM_CHK(handle); + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + WAIT_USART_IDLE(addr); + + switch (stopbit) + { + case USART_STOP_BITS_1: + /* Clear the STOP bit to set 1 stop bit*/ + addr->LCR &= LCR_STOP_BIT1; + break; + + case USART_STOP_BITS_2: + /* + * If the STOP bit is set "1",we'd gotten 1.5 stop + * bits when DLS(LCR[1:0]) is zero, else 2 stop bits. + */ + addr->LCR |= LCR_STOP_BIT2; + break; + + default: + return ERR_USART(USART_ERROR_STOP_BITS); + } + + return 0; +} + +/** + \brief config usart data length. + \param[in] handle usart handle to operate. + \param[in] databits \ref usart_data_bits_e + \return error code +*/ +int32_t csi_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits) +{ + USART_NULL_PARAM_CHK(handle); + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + WAIT_USART_IDLE(addr); + /* The word size decides by the DLS bits(LCR[1:0]), and the + * corresponding relationship between them is: + * DLS word size + * 00 -- 5 bits + * 01 -- 6 bits + * 10 -- 7 bits + * 11 -- 8 bits + */ + + switch (databits) + { + case USART_DATA_BITS_5: + addr->LCR &= LCR_WORD_SIZE_5; + break; + + case USART_DATA_BITS_6: + addr->LCR &= 0xfd; + addr->LCR |= LCR_WORD_SIZE_6; + break; + + case USART_DATA_BITS_7: + addr->LCR &= 0xfe; + addr->LCR |= LCR_WORD_SIZE_7; + break; + + case USART_DATA_BITS_8: + addr->LCR |= LCR_WORD_SIZE_8; + break; + + default: + return ERR_USART(USART_ERROR_DATA_BITS); + } + + return 0; +} + + +int32_t ck_usart_set_int_flag(usart_handle_t handle,uint32_t flag) +{ + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + addr->IER |= flag; + + return 0; +} + +int32_t ck_usart_clr_int_flag(usart_handle_t handle,uint32_t flag) +{ + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + addr->IER &= ~flag; + + return 0; +} + + +/** + \brief get character in query mode. + \param[in] instance usart instance to operate. + \param[in] the pointer to the recieve charater. + \return error code +*/ +int32_t csi_usart_getchar(usart_handle_t handle, uint8_t *ch) +{ + USART_NULL_PARAM_CHK(handle); + USART_NULL_PARAM_CHK(ch); + + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + while (!(addr->LSR & LSR_DATA_READY)); + + *ch = addr->RBR; + + return 0; +} + + +/** + \brief get character in query mode. + \param[in] instance usart instance to operate. + \param[in] the pointer to the recieve charater. + \return error code +*/ +int csi_uart_getchar(usart_handle_t handle) +{ + volatile int ch; + USART_NULL_PARAM_CHK(handle); + + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + ch = -1; + + if (addr->LSR & LSR_DATA_READY) + { + ch = addr->RBR & 0xff; + } + + return ch; +} + + +/** + \brief transmit character in query mode. + \param[in] instance usart instance to operate. + \param[in] ch the input charater + \return error code +*/ +int32_t csi_usart_putchar(usart_handle_t handle, uint8_t ch) +{ + USART_NULL_PARAM_CHK(handle); + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + uint32_t timecount = 0; + + while ((!(addr->LSR & DW_LSR_TRANS_EMPTY))) + { + timecount++; + + if (timecount >= UART_BUSY_TIMEOUT) + { + return ERR_USART(DRV_ERROR_TIMEOUT); + } + } + + addr->THR = ch; + + return 0; + +} + +/** + \brief interrupt service function for transmitter holding register empty. + \param[in] usart_priv usart private to operate. +*/ +void ck_usart_intr_threshold_empty(int32_t idx, ck_usart_priv_t *usart_priv) +{ + if (usart_priv->tx_total_num == 0) + { + return; + } + + volatile int i = 500; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + if (usart_priv->tx_cnt >= usart_priv->tx_total_num) + { + addr->IER &= (~IER_THRE_INT_ENABLE); + usart_priv->last_tx_num = usart_priv->tx_total_num; + + /* fix hardware bug */ + while (addr->USR & USR_UART_BUSY); + + i = 500; + + while (i--); + + usart_priv->tx_cnt = 0; + usart_priv->tx_busy = 0; + usart_priv->tx_buf = NULL; + usart_priv->tx_total_num = 0; + + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_SEND_COMPLETE); + } + } else + { + /* fix hardware bug */ + while (addr->USR & USR_UART_BUSY); + + i = 500; + + while (i--); + + addr->THR = *((uint8_t *)usart_priv->tx_buf); + usart_priv->tx_cnt++; + usart_priv->tx_buf++; + } +} + +/** + \brief interrupt service function for receiver data available. + \param[in] usart_priv usart private to operate. +*/ +static void ck_usart_intr_recv_data(int32_t idx, ck_usart_priv_t *usart_priv) +{ + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + uint8_t data = addr->RBR; + + *((uint8_t *)usart_priv->rx_buf) = data; + usart_priv->rx_cnt++; + usart_priv->rx_buf++; + + if (usart_priv->rx_cnt >= usart_priv->rx_total_num) + { + usart_priv->last_rx_num = usart_priv->rx_total_num; + usart_priv->rx_cnt = 0; + usart_priv->rx_buf = NULL; + usart_priv->rx_busy = 0; + usart_priv->rx_total_num = 0; + + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_RECEIVE_COMPLETE); + } + } + +} + +/** + \brief interrupt service function for receiver line. + \param[in] usart_priv usart private to operate. +*/ +static void ck_usart_intr_recv_line(int32_t idx, ck_usart_priv_t *usart_priv) +{ + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + uint32_t lsr_stat = addr->LSR; + + addr->IER &= (~IER_THRE_INT_ENABLE); + + uint32_t timecount = 0; + + while (addr->LSR & 0x1) + { + addr->RBR; + timecount++; + + if (timecount >= UART_BUSY_TIMEOUT) + { + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_RX_TIMEOUT); + } + + return; + } + } + + /** Break Interrupt bit. This is used to indicate the detection of a + * break sequence on the serial input data. + */ + if (lsr_stat & DW_LSR_BI) + { + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_RX_BREAK); + } + + return; + } + + /** Framing Error bit. This is used to indicate the occurrence of a + * framing error in the receiver. A framing error occurs when the receiver + * does not detect a valid STOP bit in the received data. + */ + if (lsr_stat & DW_LSR_FE) + { + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_RX_FRAMING_ERROR); + } + + return; + } + + /** Framing Error bit. This is used to indicate the occurrence of a + * framing error in the receiver. A framing error occurs when the + * receiver does not detect a valid STOP bit in the received data. + */ + if (lsr_stat & DW_LSR_PE) + { + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_RX_PARITY_ERROR); + } + + return; + } + + /** Overrun error bit. This is used to indicate the occurrence of an overrun error. + * This occurs if a new data character was received before the previous data was read. + */ + if (lsr_stat & DW_LSR_OE) + { + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_RX_OVERFLOW); + } + + return; + } +} +/** + \brief interrupt service function for character timeout. + \param[in] usart_priv usart private to operate. +*/ +static void ck_usart_intr_char_timeout(int32_t idx, ck_usart_priv_t *usart_priv) +{ + if ((usart_priv->rx_total_num != 0) && (usart_priv->rx_buf != NULL)) + { + ck_usart_intr_recv_data(idx, usart_priv); + return; + } + + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_RECEIVED); + } else + { + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + uint32_t timecount = 0; + + while (addr->LSR & 0x1) + { + addr->RBR; + timecount++; + + if (timecount >= UART_BUSY_TIMEOUT) + { + if (usart_priv->cb_event) + { + usart_priv->cb_event(idx, USART_EVENT_RX_TIMEOUT); + } + + return; + } + } + } +} + +/** + \brief the interrupt service function. + \param[in] index of usart instance. +*/ +void ck_usart_irqhandler(int32_t idx) +{ + ck_usart_priv_t *usart_priv = &usart_instance[idx]; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + uint8_t intr_state = addr->IIR & 0xf; + + switch (intr_state) + { + case DW_IIR_THR_EMPTY: /* interrupt source:transmitter holding register empty */ + ck_usart_intr_threshold_empty(idx, usart_priv); + break; + + case DW_IIR_RECV_DATA: /* interrupt source:receiver data available or receiver fifo trigger level reached */ + ck_usart_intr_char_timeout(idx, usart_priv); + //ck_usart_intr_recv_data(idx, usart_priv); + break; + + case DW_IIR_RECV_LINE: + ck_usart_intr_recv_line(idx, usart_priv); + break; + + case DW_IIR_CHAR_TIMEOUT: + ck_usart_intr_char_timeout(idx, usart_priv); + break; + + default: + break; + } +} + +/** + \brief Get driver capabilities. + \param[in] idx usart index + \return \ref usart_capabilities_t +*/ +usart_capabilities_t csi_usart_get_capabilities(int32_t idx) +{ + if (idx < 0 || idx >= CONFIG_USART_NUM) + { + usart_capabilities_t ret; + memset(&ret, 0, sizeof(usart_capabilities_t)); + return ret; + } + + return usart_capabilities; +} + +/** + \brief Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function + \param[in] idx usart index + \param[in] cb_event Pointer to \ref usart_event_cb_t + \return return usart handle if success +*/ +usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event) +{ + uint32_t base = 0u; + uint32_t irq = 0u; + void *handler; + + int32_t ret = target_usart_init(idx, &base, &irq, &handler); + + if (ret < 0 || ret >= CONFIG_USART_NUM) + { + return NULL; + } + + ck_usart_priv_t *usart_priv = &usart_instance[idx]; + usart_priv->base = base; + usart_priv->irq = irq; + usart_priv->cb_event = cb_event; + usart_priv->idx = idx; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + /* enable received data available */ + addr->IER = IER_RDA_INT_ENABLE | IIR_RECV_LINE_ENABLE; + drv_irq_register(usart_priv->irq, handler); + drv_irq_enable(usart_priv->irq); + + return usart_priv; +} + +/** + \brief De-initialize UART Interface. stops operation and releases the software resources used by the interface + \param[in] handle usart handle to operate. + \return error code +*/ +int32_t csi_usart_uninitialize(usart_handle_t handle) +{ + USART_NULL_PARAM_CHK(handle); + + ck_usart_priv_t *usart_priv = handle; + + drv_irq_disable(usart_priv->irq); + drv_irq_unregister(usart_priv->irq); + usart_priv->cb_event = NULL; + + return 0; +} + +/** + \brief config usart mode. + \param[in] handle usart handle to operate. + \param[in] baud baud rate + \param[in] mode \ref usart_mode_e + \param[in] parity \ref usart_parity_e + \param[in] stopbits \ref usart_stop_bits_e + \param[in] bits \ref usart_data_bits_e + \return error code +*/ +int32_t csi_usart_config(usart_handle_t handle, + uint32_t baud, + usart_mode_e mode, + usart_parity_e parity, + usart_stop_bits_e stopbits, + usart_data_bits_e bits) +{ + int32_t ret; + + /* control the data_bit of the usart*/ + ret = csi_usart_config_baudrate(handle, baud); + + if (ret < 0) + { + return ret; + } + + /* control mode of the usart*/ + ret = csi_usart_config_mode(handle, mode); + + if (ret < 0) + { + return ret; + } + + /* control the parity of the usart*/ + ret = csi_usart_config_parity(handle, parity); + + if (ret < 0) + { + return ret; + } + + /* control the stopbit of the usart*/ + ret = csi_usart_config_stopbits(handle, stopbits); + + if (ret < 0) + { + return ret; + } + + ret = csi_usart_config_databits(handle, bits); + + if (ret < 0) + { + return ret; + } + + return 0; +} + + +/** + \brief Start sending data to UART transmitter,(received data is ignored). + The function is non-blocking,UART_EVENT_TRANSFER_COMPLETE is signaled when transfer completes. + csi_usart_get_status can indicates if transmission is still in progress or pending + \param[in] handle usart handle to operate. + \param[in] data Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 1..8 data bits, uint16_t for 9..16 data bits,uint32_t for 17..32 data bits, + \param[in] num Number of data items to send + \return error code +*/ +int32_t csi_usart_send(usart_handle_t handle, const void *data, uint32_t num) +{ + USART_NULL_PARAM_CHK(handle); + USART_NULL_PARAM_CHK(data); + + if (num == 0) + { + return ERR_USART(DRV_ERROR_PARAMETER); + } + + ck_usart_priv_t *usart_priv = handle; + + usart_priv->tx_buf = (uint8_t *)data; + usart_priv->tx_total_num = num; + usart_priv->tx_cnt = 0; + usart_priv->tx_busy = 1; + usart_priv->last_tx_num = 0; + + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + ck_usart_intr_threshold_empty(usart_priv->idx, usart_priv); + /* enable the interrupt*/ + addr->IER |= IER_THRE_INT_ENABLE; + return 0; +} + +/** + \brief Abort Send data to UART transmitter + \param[in] handle usart handle to operate. + \return error code +*/ +int32_t csi_usart_abort_send(usart_handle_t handle) +{ + USART_NULL_PARAM_CHK(handle); + ck_usart_priv_t *usart_priv = handle; + + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + addr->IER &= (~IER_THRE_INT_ENABLE); + + usart_priv->tx_cnt = usart_priv->tx_total_num; + usart_priv->tx_cnt = 0; + usart_priv->tx_busy = 0; + usart_priv->tx_buf = NULL; + usart_priv->tx_total_num = 0; + return 0; +} + +/** + \brief Start receiving data from UART receiver.transmits the default value as specified by csi_usart_set_default_tx_value + \param[in] handle usart handle to operate. + \param[out] data Pointer to buffer for data to receive from UART receiver + \param[in] num Number of data items to receive + \return error code +*/ +int32_t csi_usart_receive(usart_handle_t handle, void *data, uint32_t num) +{ + USART_NULL_PARAM_CHK(handle); + USART_NULL_PARAM_CHK(data); + + ck_usart_priv_t *usart_priv = handle; + + usart_priv->rx_buf = (uint8_t *)data; // Save receive buffer usart + usart_priv->rx_total_num = num; // Save number of data to be received + usart_priv->rx_cnt = 0; + usart_priv->rx_busy = 1; + usart_priv->last_rx_num = 0; + + return 0; + +} + +/** + \brief query data from UART receiver FIFO. + \param[in] handle usart handle to operate. + \param[out] data Pointer to buffer for data to receive from UART receiver + \param[in] num Number of data items to receive + \return receive fifo data num +*/ +int32_t csi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num) +{ + USART_NULL_PARAM_CHK(handle); + USART_NULL_PARAM_CHK(data); + + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + int32_t recv_num = 0; + uint8_t *dest = (uint8_t *)data; + + while (addr->LSR & 0x1) + { + *dest++ = addr->RBR; + recv_num++; + + if (recv_num >= num) + { + break; + } + } + + return recv_num; + +} + +/** + \brief Abort Receive data from UART receiver + \param[in] handle usart handle to operate. + \return error code +*/ +int32_t csi_usart_abort_receive(usart_handle_t handle) +{ + USART_NULL_PARAM_CHK(handle); + ck_usart_priv_t *usart_priv = handle; + + usart_priv->rx_cnt = usart_priv->rx_total_num; + return 0; +} + +/** + \brief Start sending/receiving data to/from UART transmitter/receiver. + \param[in] handle usart handle to operate. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return error code +*/ +int32_t csi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num) +{ + USART_NULL_PARAM_CHK(handle); + return ERR_USART(DRV_ERROR_UNSUPPORTED); +} + +/** + \brief abort sending/receiving data to/from USART transmitter/receiver. + \param[in] handle usart handle to operate. + \return error code +*/ +int32_t csi_usart_abort_transfer(usart_handle_t handle) +{ + USART_NULL_PARAM_CHK(handle); + return ERR_USART(DRV_ERROR_UNSUPPORTED); +} + +/** + \brief Get USART status. + \param[in] handle usart handle to operate. + \return USART status \ref usart_status_t +*/ +usart_status_t csi_usart_get_status(usart_handle_t handle) +{ + usart_status_t usart_status; + + memset(&usart_status, 0, sizeof(usart_status_t)); + + if (handle == NULL) + { + return usart_status; + } + + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + uint32_t line_status_reg = addr->LSR; + + usart_status.tx_busy = usart_priv->tx_busy; + usart_status.rx_busy = usart_priv->rx_busy; + + if (line_status_reg & DW_LSR_BI) + { + usart_status.rx_break = 1; + } + + if (line_status_reg & DW_LSR_FE) + { + usart_status.rx_framing_error = 1; + } + + if (line_status_reg & DW_LSR_PE) + { + usart_status.rx_parity_error = 1; + } + + usart_status.tx_enable = 1; + usart_status.rx_enable = 1; + + return usart_status; +} + +/** + \brief control the transmit. + \param[in] handle usart handle to operate. + \param[in] 1 - enable the transmitter. 0 - disable the transmitter + \return error code +*/ +int32_t csi_usart_control_tx(usart_handle_t handle, uint32_t enable) +{ + USART_NULL_PARAM_CHK(handle); + return 0; +} + +/** + \brief control the receive. + \param[in] handle usart handle to operate. + \param[in] 1 - enable the receiver. 0 - disable the receiver + \return error code +*/ +int32_t csi_usart_control_rx(usart_handle_t handle, uint32_t enable) +{ + USART_NULL_PARAM_CHK(handle); + return 0; +} + +/** + \brief control the break. + \param[in] handle usart handle to operate. + \param[in] 1- Enable continuous Break transmission,0 - disable continuous Break transmission + \return error code +*/ +int32_t csi_usart_control_break(usart_handle_t handle, uint32_t enable) +{ + USART_NULL_PARAM_CHK(handle); + return ERR_USART(DRV_ERROR_UNSUPPORTED); +} + +/** + \brief flush receive/send data. + \param[in] handle usart handle to operate. + \param[in] type \ref usart_flush_type_e. + \return error code +*/ +int32_t csi_usart_flush(usart_handle_t handle, usart_flush_type_e type) +{ + USART_NULL_PARAM_CHK(handle); + + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + uint32_t timecount = 0; + + if (type == USART_FLUSH_WRITE) { + while ((!(addr->LSR & DW_LSR_TEMT))) + { + timecount++; + + if (timecount >= UART_BUSY_TIMEOUT) + { + return ERR_USART(DRV_ERROR_TIMEOUT); + } + } + } else if (type == USART_FLUSH_READ) + { + while (addr->LSR & 0x1) { + timecount++; + + if (timecount >= UART_BUSY_TIMEOUT) + { + return ERR_USART(DRV_ERROR_TIMEOUT); + } + } + } else + { + return ERR_USART(DRV_ERROR_PARAMETER); + } + + return 0; +} + +/** + \brief set interrupt mode. + \param[in] handle usart handle to operate. + \param[in] type \ref usart_intr_type_e. + \param[in] flag 0-OFF, 1-ON. + \return error code +*/ +int32_t csi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag) +{ + USART_NULL_PARAM_CHK(handle); + + ck_usart_priv_t *usart_priv = handle; + ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base); + + switch (type) + { + case USART_INTR_WRITE: + if (flag == 0) + { + addr->IER &= ~IER_THRE_INT_ENABLE; + } else if (flag == 1) + { + addr->IER |= IER_THRE_INT_ENABLE; + } else + { + return ERR_USART(DRV_ERROR_PARAMETER); + } + + break; + + case USART_INTR_READ: + if (flag == 0) + { + addr->IER &= ~IER_RDA_INT_ENABLE; + } else if (flag == 1) + { + addr->IER |= IER_RDA_INT_ENABLE; + } else + { + return ERR_USART(DRV_ERROR_PARAMETER); + } + + break; + + default: + return ERR_USART(DRV_ERROR_PARAMETER); + + } + + return 0; +} + +/** + \brief Get usart send data count. + \param[in] handle usart handle to operate. + \return number of currently transmitted data bytes +*/ +uint32_t csi_usart_get_tx_count(usart_handle_t handle) +{ + USART_NULL_PARAM_CHK(handle); + + ck_usart_priv_t *usart_priv = handle; + + if (usart_priv->tx_busy) + { + return usart_priv->tx_cnt; + } else + { + return usart_priv->last_tx_num; + } +} + +/** + \brief Get usart receive data count. + \param[in] handle usart handle to operate. + \return number of currently received data bytes +*/ +uint32_t csi_usart_get_rx_count(usart_handle_t handle) +{ + USART_NULL_PARAM_CHK(handle); + ck_usart_priv_t *usart_priv = handle; + + if (usart_priv->rx_busy) + { + return usart_priv->rx_cnt; + } else + { + return usart_priv->last_rx_num; + } +} + +/** + \brief control usart power. + \param[in] handle usart handle to operate. + \param[in] state power state.\ref csi_power_stat_e. + \return error code +*/ +int32_t csi_usart_power_control(usart_handle_t handle, csi_power_stat_e state) +{ + USART_NULL_PARAM_CHK(handle); + return ERR_USART(DRV_ERROR_UNSUPPORTED); +} + +/** + \brief config usart flow control type. + \param[in] handle usart handle to operate. + \param[in] flowctrl_type flow control type.\ref usart_flowctrl_type_e. + \return error code +*/ +int32_t csi_usart_config_flowctrl(usart_handle_t handle, + usart_flowctrl_type_e flowctrl_type) +{ + USART_NULL_PARAM_CHK(handle); + + switch (flowctrl_type) + { + case USART_FLOWCTRL_CTS: + return ERR_USART(DRV_ERROR_UNSUPPORTED); + + case USART_FLOWCTRL_RTS: + return ERR_USART(DRV_ERROR_UNSUPPORTED); + + case USART_FLOWCTRL_CTS_RTS: + return ERR_USART(DRV_ERROR_UNSUPPORTED); + break; + + case USART_FLOWCTRL_NONE: + return ERR_USART(DRV_ERROR_UNSUPPORTED); + break; + + default: + return ERR_USART(DRV_ERROR_UNSUPPORTED); + } + + return 0; +} + + +/** + \brief config usart clock Polarity and Phase. + \param[in] handle usart handle to operate. + \param[in] cpol Clock Polarity.\ref usart_cpol_e. + \param[in] cpha Clock Phase.\ref usart_cpha_e. + \return error code +*/ +int32_t csi_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha) +{ + USART_NULL_PARAM_CHK(handle); + return ERR_USART(DRV_ERROR_UNSUPPORTED); +} + diff --git a/bsp/thead-smart/drivers/ck_usart.h b/bsp/thead-smart/drivers/ck_usart.h new file mode 100644 index 0000000000..bdaba45c4c --- /dev/null +++ b/bsp/thead-smart/drivers/ck_usart.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header file for usart driver + */ + +#ifndef __CK_USART_H +#define __CK_USART_H + +#include +#include "errno.h" +#include "soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define BAUDRATE_DEFAULT 19200 +#define UART_BUSY_TIMEOUT 1000000 +#define UART_RECEIVE_TIMEOUT 1000 +#define UART_TRANSMIT_TIMEOUT 1000 +#define UART_MAX_FIFO 0x10 +/* UART register bit definitions */ + +#define USR_UART_BUSY 0x01 +#define USR_UART_TFE 0x04 +#define USR_UART_RFNE 0x08 +#define LSR_DATA_READY 0x01 +#define LSR_THR_EMPTY 0x20 +#define IER_RDA_INT_ENABLE 0x01 +#define IER_THRE_INT_ENABLE 0x02 +#define IIR_RECV_LINE_ENABLE 0x04 +#define IIR_NO_ISQ_PEND 0x01 + +#define LCR_SET_DLAB 0x80 /* enable r/w DLR to set the baud rate */ +#define LCR_PARITY_ENABLE 0x08 /* parity enabled */ +#define LCR_PARITY_EVEN 0x10 /* Even parity enabled */ +#define LCR_PARITY_ODD 0xef /* Odd parity enabled */ +#define LCR_WORD_SIZE_5 0xfc /* the data length is 5 bits */ +#define LCR_WORD_SIZE_6 0x01 /* the data length is 6 bits */ +#define LCR_WORD_SIZE_7 0x02 /* the data length is 7 bits */ +#define LCR_WORD_SIZE_8 0x03 /* the data length is 8 bits */ +#define LCR_STOP_BIT1 0xfb /* 1 stop bit */ +#define LCR_STOP_BIT2 0x04 /* 1.5 stop bit */ + +#define DW_LSR_PFE 0x80 +#define DW_LSR_TEMT 0x40 +#define DW_LSR_THRE 0x40 +#define DW_LSR_BI 0x10 +#define DW_LSR_FE 0x08 +#define DW_LSR_PE 0x04 +#define DW_LSR_OE 0x02 +#define DW_LSR_DR 0x01 +#define DW_LSR_TRANS_EMPTY 0x20 + +#define DW_IIR_THR_EMPTY 0x02 /* threshold empty */ +#define DW_IIR_RECV_DATA 0x04 /* received data available */ +#define DW_IIR_RECV_LINE 0x06 /* receiver line status */ +#define DW_IIR_CHAR_TIMEOUT 0x0c /* character timeout */ + +typedef struct +{ + union + { + __IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */ + __OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */ + __IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */ + }; + union + { + __IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */ + __IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */ + }; + __IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */ + __IOM uint32_t LCR; /* Offset: 0x00C (R/W) Transmission control register */ + uint32_t RESERVED0; + __IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */ + __IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */ + uint32_t RESERVED1[24]; + __IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */ +} ck_usart_reg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* __CK_USART_H */ + diff --git a/bsp/thead-smart/drivers/core_rv32.h b/bsp/thead-smart/drivers/core_rv32.h new file mode 100644 index 0000000000..87fccfba72 --- /dev/null +++ b/bsp/thead-smart/drivers/core_rv32.h @@ -0,0 +1,1130 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen CSI RV32 Core Peripheral Access Layer Header File + */ + +#ifndef __CORE_RV32_H_GENERIC +#define __CORE_RV32_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * CSI definitions + ******************************************************************************/ +/** + \ingroup RV32 + @{ + */ + +#ifndef __RV32 +#define __RV32 (0x01U) +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_GENERIC */ + +#ifndef __CSI_GENERIC + +#ifndef __CORE_RV32_H_DEPENDANT +#define __CORE_RV32_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#ifndef __RV32_REV +#define __RV32_REV 0x0000U +#endif + +#ifndef __VIC_PRIO_BITS +#define __VIC_PRIO_BITS 2U +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 1U +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 1U +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 1U +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 1U +#endif + +#include + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CSI_glob_defs CSI Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group CK802 */ + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core CLIC Register + ******************************************************************************/ +/** + \defgroup CSI_core_register Defines and Type Definitions + \brief Type definitions and defines for CK80X processor based devices. +*/ + +/** + \ingroup CSI_core_register + \defgroup CSI_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \ingroup CSI_core_register + \defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC) + \brief Type definitions for the CLIC Registers + @{ + */ + +/** + \brief Access to the structure of a vector interrupt controller. + */ +typedef struct +{ + __IOM uint8_t IP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */ + __IOM uint8_t IE; /*!< Offset: 0x004 (R/W) Interrupt set enable register */ + __IOM uint8_t ATTR; /*!< Offset: 0x008 (R/W) Interrupt set attribute register */ + __IOM uint8_t CTL; /*!< Offset: 0x00C (R/W) Interrupt control register */ +} CLIC_INT_Control; + +typedef struct +{ + __IOM uint32_t CLICCFG:8; /*!< Offset: 0x000 (R/W) CLIC configure register */ + __IM uint32_t CLICINFO; + __IOM uint32_t MINTTHRESH; + uint32_t RESERVED[1021]; + CLIC_INT_Control CLICINT[4096]; +} CLIC_Type; + +#define CLIC_INFO_CLICINTCTLBITS_Pos 21U +#define CLIC_INFO_CLICINTCTLBITS_Msk (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos) + +#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */ +#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */ + +#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */ +#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */ + +#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */ +#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */ + +#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */ +#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */ + +#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */ +#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */ + +#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */ +#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */ + +#define CLIC_INTCFG_PRIO_Pos 5U /*!< CLIC INTCFG: INTCFG Position */ +#define CLIC_INTCFG_PRIO_Msk (0x7UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */ + +#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */ +#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */ + +#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */ +#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */ + +#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */ +#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */ + +/*@} end of group CSI_CLIC */ + +/** + \ingroup CSI_core_register + \defgroup CSI_PMP Physical Memory Protection (PMP) + \brief Type definitions for the PMP Registers + @{ + */ + +#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */ +#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */ + +#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */ +#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */ + +#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */ +#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */ + +#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */ +#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */ + +#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */ +#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */ + +typedef enum +{ + REGION_SIZE_4B = -1, + REGION_SIZE_8B = 0, + REGION_SIZE_16B = 1, + REGION_SIZE_32B = 2, + REGION_SIZE_64B = 3, + REGION_SIZE_128B = 4, + REGION_SIZE_256B = 5, + REGION_SIZE_512B = 6, + REGION_SIZE_1KB = 7, + REGION_SIZE_2KB = 8, + REGION_SIZE_4KB = 9, + REGION_SIZE_8KB = 10, + REGION_SIZE_16KB = 11, + REGION_SIZE_32KB = 12, + REGION_SIZE_64KB = 13, + REGION_SIZE_128KB = 14, + REGION_SIZE_256KB = 15, + REGION_SIZE_512KB = 16, + REGION_SIZE_1MB = 17, + REGION_SIZE_2MB = 18, + REGION_SIZE_4MB = 19, + REGION_SIZE_8MB = 20, + REGION_SIZE_16MB = 21, + REGION_SIZE_32MB = 22, + REGION_SIZE_64MB = 23, + REGION_SIZE_128MB = 24, + REGION_SIZE_256MB = 25, + REGION_SIZE_512MB = 26, + REGION_SIZE_1GB = 27, + REGION_SIZE_2GB = 28, + REGION_SIZE_4GB = 29, + REGION_SIZE_8GB = 30, + REGION_SIZE_16GB = 31 +} region_size_e; + +typedef enum +{ + ADDRESS_MATCHING_TOR = 1, + ADDRESS_MATCHING_NAPOT = 3 +} address_matching_e; + +typedef struct +{ + uint32_t r: 1; /* readable enable */ + uint32_t w: 1; /* writeable enable */ + uint32_t x: 1; /* execable enable */ + address_matching_e a: 2; /* address matching mode */ + uint32_t reserved: 2; /* reserved */ + uint32_t l: 1; /* lock enable */ +} mpu_region_attr_t; + +/*@} end of group CSI_PMP */ + +/* CACHE Register Definitions */ +#define CACHE_MHCR_L0BTB_Pos 12U /*!< CACHE MHCR: L0BTB Position */ +#define CACHE_MHCR_L0BTB_Msk (0x1UL << CACHE_MHCR_L0BTB_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */ +#define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */ + +#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */ +#define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */ + +#define CACHE_MHCR_WA_Pos 3U /*!< CACHE MHCR: WA Position */ +#define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_WB_Pos 2U /*!< CACHE MHCR: WB Position */ +#define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */ + +#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */ +#define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */ + +#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */ +#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */ + +#define CACHE_INV_ADDR_Pos 5U +#define CACHE_INV_ADDR_Msk (0xFFFFFFFFUL << CACHE_INV_ADDR_Pos) + +/*@} end of group CSI_CACHE */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_SysTick System Tick Timer (CORET) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief The data structure of the access system timer. + */ +typedef struct +{ + __IOM unsigned long long MTIMECMP; /*!< Offset: 0x000 (R/W) Timer compare register */ + uint32_t RESERVED[8187]; + __IM unsigned long long MTIME; /*!< Offset: 0x7FFC (R) Timer current register */ +} CORET_Type; + +/*@} end of group CSI_SysTick */ + +/** + \ingroup CSI_core_register + \defgroup CSI_DCC + \brief Type definitions for the DCC. + @{ + */ + +/** + \brief Access to the data structure of DCC. + */ +typedef struct +{ + uint32_t RESERVED0[13U]; + __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */ + __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */ + uint32_t RESERVED1[6U]; + union { + __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/ + __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/ + }; + +} DCC_Type; + +#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */ +#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */ + +#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */ +#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */ + +#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */ +#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */ + +#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */ +#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */ + +/*@} end of group CSI_DCC */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CSI_core_bitfield */ + +/** + \ingroup CSI_core_register + \defgroup CSI_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of CK802 Hardware */ +#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */ +#define CORET_BASE (0xE0004000UL) /*!< CORET Base Address */ +#define CLIC_BASE (0xE0800000UL) /*!< CLIC Base Address */ +#define DCC_BASE (0xE4010000UL) /*!< DCC Base Address */ +#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */ + +#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */ +#define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */ +#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */ +#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */ + +/*@} */ + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core VIC Functions + - Core CORET Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference +*/ + +/* ########################## VIC functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_VICFunctions VIC Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) ) +#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +/** + \brief Enable External Interrupt + \details Enable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk; +} + +/** + \brief Disable External Interrupt + \details Disable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk; +} + +/** + \brief Enable External Secure Interrupt + \details Enable a secure device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk); +} + +/** + \brief Disable External Secure Interrupt + \details Disable a secure device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk); +} + +/** + \brief Check Interrupt is Enabled or not + \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not enabled. + \return 1 Interrupt status is enabled. + */ +__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn) +{ + return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk); +} + +/** + \brief Check Interrupt is Pending or not + \details Read the pending register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn) +{ + return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk); +} + +/** + \brief Set Pending Interrupt + \details Set the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk; +} + +/** + \brief Clear Pending Interrupt + \details Clear the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk; +} + +/** + \brief Set Interrupt Priority + \details Set the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority) +{ + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + CLIC->CLICINT[IRQn].CTL = (CLIC->CLICINT[IRQn].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (priority << (8 - nlbits)); +} + +/** + \brief Get Interrupt Priority + \details Read the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn) +{ + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + return CLIC->CLICINT[IRQn].CTL >> (8 - nlbits); +} + +/** + \brief Set interrupt handler + \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors. + \param [in] IRQn Interrupt number. + \param [in] handler Interrupt handler. + */ +__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler) +{ + if (IRQn >= 0 && IRQn < 1024) { + uint32_t *vectors = (uint32_t *)__get_MTVT(); + vectors[IRQn] = handler; + } +} + +/** + \brief Get interrupt handler + \details Get the address of interrupt handler function. + \param [in] IRQn Interrupt number. + */ +__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn) +{ + if (IRQn >= 0 && IRQn < 1024) { + uint32_t *vectors = (uint32_t *)__get_MTVT(); + return (uint32_t)vectors[IRQn]; + } + + return 0; +} + +/*@} end of CSI_Core_VICFunctions */ + +/* ########################## PMP functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_PMPFunctions PMP Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/** + \brief configure memory protected region. + \details + \param [in] idx memory protected region (0, 1, 2, ..., 15). + \param [in] base_addr base address must be aligned with page size. + \param [in] size \ref region_size_e. memory protected region size. + \param [in] attr \ref region_size_t. memory protected region attribute. + \param [in] enable enable or disable memory protected region. + */ +__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size, + mpu_region_attr_t attr, uint32_t enable) +{ + uint8_t pmpxcfg = 0; + uint32_t addr = 0; + + if (idx > 15) { + return; + } + + if (!enable) { + attr.a = 0; + } + + if (attr.a == ADDRESS_MATCHING_TOR) { + addr = base_addr >> 2; + } else { + if (size == REGION_SIZE_4B) { + addr = base_addr >> 2; + attr.a = 2; + } else { + addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); + } + } + + __set_PMPADDRx(idx, addr); + + pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) | + (attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) | + (attr.l << PMP_PMPCFG_L_Pos); + + __set_PMPxCFG(idx, pmpxcfg); +} + +/** + \brief disable mpu region by idx. + \details + \param [in] idx memory protected region (0, 1, 2, ..., 15). + */ +__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx) +{ + __set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk)); +} + +/*@} end of CSI_Core_PMPFunctions */ + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + + +/** + \brief CORE timer Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \param [in] IRQn core timer Interrupt number. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn) +{ + if (CORET->MTIMECMP) { + CORET->MTIMECMP = CORET->MTIMECMP + ticks; + } else { + CORET->MTIMECMP = CORET->MTIME + ticks; + } + return (0UL); +} + +/** + \brief get CORE timer reload value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_load(void) +{ + return CORET->MTIMECMP & 0xFFFFFFFF; +} + +/** + \brief get CORE timer reload high value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_loadh(void) +{ + return (CORET->MTIMECMP >> 32) & 0xFFFFFFFF; +} + +/** + \brief get CORE timer counter value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_value(void) +{ + return CORET->MTIME & 0xFFFFFFFF; +} + +/** + \brief get CORE timer counter high value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_valueh(void) +{ + return (CORET->MTIME >> 32) & 0xFFFFFFFF; +} + +/*@} end of CSI_Core_SysTickFunctions */ + +/* ##################################### DCC function ########################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_core_DebugFunctions HAD Functions + \brief Functions that access the HAD debug interface. + @{ + */ + +/** + \brief HAD Send Character + \details Transmits a character via the HAD channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch) +{ + DCC->DERJR = (uint8_t)ch; + + return (ch); +} + + +/** + \brief HAD Receive Character + \details Inputs a character via the external variable \ref HAD_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t csi_had_receive_char(void) +{ + int32_t ch = -1; /* no character available */ + + if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) { + ch = DCC->DERJW; + } + + return (ch); +} + + +/** + \brief HAD Check Character + \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t csi_had_check_char(void) +{ + return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */ +} + +/*@} end of CSI_core_DebugFunctions */ + + +/* ########################## sleep and Reset functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SleepAndResetFunctions Sleep and Reset Functions + \brief Functions that configure Sleep and Reset. + @{ + */ + + +/* MEXSTATUS Register Definitions */ +#define MEXSTATUS_RESET_Pos 0U +#define MEXSTATUS_RESET_Msk (0x3UL << MEXSTATUS_RESET_Pos) /*!< MEXSTATUS: RESET Position */ +#define MEXSTATUS_SLEEP_Pos 2U +#define MEXSTATUS_SLEEP_Msk (0x3UL << MEXSTATUS_SLEEP_Pos) /*!< MEXSTATUS: RESET Position */ +/*@} end of group CSI_MEXSTATUS */ + + + +/** + \brief CPU System Reset + \details Triggle CPU System Reset + */ +__STATIC_INLINE void csi_system_reset (void) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus &= (~(MEXSTATUS_RESET_Msk)); + mexstatus |= (uint32_t)(0x2 << MEXSTATUS_RESET_Pos); + __set_MEXSTATUS(mexstatus); +} + +/** + \brief CPU Core Reset + \details Triggle CPU Core Reset + */ +__STATIC_INLINE void csi_core_reset (void) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus &= (~(MEXSTATUS_RESET_Msk)); + mexstatus |= (uint32_t)(0x1 << MEXSTATUS_RESET_Pos); + __set_MEXSTATUS(mexstatus); +} + +/* ########################## Cache functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void csi_icache_enable (void) +{ +#if (__ICACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + __ICACHE_IALL(); + cache = __get_MHCR(); + cache |= CACHE_MHCR_IE_Msk; + __set_MHCR(cache); + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void csi_icache_disable (void) +{ +#if (__ICACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + cache = __get_MHCR(); + cache &= ~CACHE_MHCR_IE_Msk; /* disable icache */ + __set_MHCR(cache); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void csi_icache_invalid (void) +{ +#if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + \note I-Cache also turns on. + */ +__STATIC_INLINE void csi_dcache_enable (void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + __DCACHE_IALL(); /* invalidate all dcache */ + cache = __get_MHCR(); + cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */ + __set_MHCR(cache); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + \note I-Cache also turns off. + */ +__STATIC_INLINE void csi_dcache_disable (void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + cache = __get_MHCR(); + cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */ + __set_MHCR(cache); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + \note I-Cache also invalid + */ +__STATIC_INLINE void csi_dcache_invalid (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + \note I-Cache also cleans + */ +__STATIC_INLINE void csi_dcache_clean (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_CALL(); /* clean all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + \note I-Cache also flush. + */ +__STATIC_INLINE void csi_dcache_clean_invalid (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_CIALL(); /* clean and inv all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_IPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize) +{ + +#if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_CPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif + +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (aligned to 16-byte boundary) +*/ +__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_CIPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + +/** + \brief setup cacheable range Cache + \details setup Cache range + */ +__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable) +{ + ; +} + +/** + \brief Enable cache profile + \details Turns on Cache profile + */ +__STATIC_INLINE void csi_cache_enable_profile (void) +{ + ; +} + +/** + \brief Disable cache profile + \details Turns off Cache profile + */ +__STATIC_INLINE void csi_cache_disable_profile (void) +{ + ; +} + +/** + \brief Reset cache profile + \details Reset Cache profile + */ +__STATIC_INLINE void csi_cache_reset_profile (void) +{ + ; +} + +/** + \brief cache access times + \details Cache access times + \note every 256 access add 1. + \return cache access times, actual times should be multiplied by 256 + */ +__STATIC_INLINE uint32_t csi_cache_get_access_time (void) +{ + return 0; +} + +/** + \brief cache miss times + \details Cache miss times + \note every 256 miss add 1. + \return cache miss times, actual times should be multiplied by 256 + */ +__STATIC_INLINE uint32_t csi_cache_get_miss_time (void) +{ + return 0; +} + +/*@} end of CSI_Core_CacheFunctions */ + +/*@} end of CSI_core_DebugFunctions */ + +/* ################################## IRQ Functions ############################################ */ + +/** + \brief Save the Irq context + \details save the psr result before disable irq. + */ +__STATIC_INLINE uint32_t csi_irq_save(void) +{ + uint32_t result; + result = __get_MSTATUS(); + __disable_irq(); + return(result); +} + +/** + \brief Restore the Irq context + \details restore saved primask state. + \param [in] irq_state psr irq state. + */ +__STATIC_INLINE void csi_irq_restore(uint32_t irq_state) +{ + __set_MSTATUS(irq_state); +} + +/*@} end of IRQ Functions */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_DEPENDANT */ + +#endif /* __CSI_GENERIC */ diff --git a/bsp/thead-smart/drivers/csi_config.h b/bsp/thead-smart/drivers/csi_config.h new file mode 100644 index 0000000000..75185caff4 --- /dev/null +++ b/bsp/thead-smart/drivers/csi_config.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen config file + */ + +/* csi_config.h -- Autogenerated! Do not edit. */ + +#ifndef __CSI_CONFIG_H +#define __CSI_CONFIG_H + +#define CONFIG_ARCH_RV32 1 +#define CONFIG_CPU_E906FD 1 +#define CONFIG_RV32_CORETIM 1 +#define CONFIG_CHIP_SMARTL_RV32 1 +#define CONFIG_BOARD_SMARTL_E906_EVB 1 +#define CONFIG_BOARD_NAME_STR "smartl_e906_evb" +#define CONFIG_SUPPORT_TSPEND 1 +#define CONFIG_ARCH_INTERRUPTSTACK 4096 +#define CONFIG_NEWLIB_WRAP 1 +#define CONFIG_USER_DEFINED_LD_DIR_STR "" + +#define CONFIG_KERNEL_RTTHREAD 1 +#endif /* __CONFIG_H */ + diff --git a/bsp/thead-smart/drivers/csi_core.h b/bsp/thead-smart/drivers/csi_core.h new file mode 100644 index 0000000000..49659a499b --- /dev/null +++ b/bsp/thead-smart/drivers/csi_core.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen CSI Core Layer Header File + */ + + +#ifndef _CORE_H_ +#define _CORE_H_ + +#include + +#if defined(__CK801__) || defined(__E801__) +#include +#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__) +#include +#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__) +#include +#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__) +#include +#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__) +#include +#elif defined(__CK610__) +#include +#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__) +#include +#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__) +#include +#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM) +#include +#elif defined(__riscv) +#include +#endif + +#ifdef __riscv +#include +#else +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _CORE_H_ */ diff --git a/bsp/thead-smart/drivers/csi_rv32_gcc.h b/bsp/thead-smart/drivers/csi_rv32_gcc.h new file mode 100644 index 0000000000..bc52d66426 --- /dev/null +++ b/bsp/thead-smart/drivers/csi_rv32_gcc.h @@ -0,0 +1,2849 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen CSI Header File for GCC. + */ + +#ifndef _CSI_RV32_GCC_H_ +#define _CSI_RV32_GCC_H_ + +#include + +#ifndef __ASM +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#endif + +#ifndef __INLINE +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#endif + +#ifndef __ALWAYS_STATIC_INLINE +#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline +#endif + +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions + @{ + */ +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("csrs mstatus, 8"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("csrc mstatus, 8"); +} + +/** + \brief Get MXSTATUS + \details Returns the content of the MXSTATUS Register. + \return MXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MXSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mxstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MXSTATUS + \details Writes the given value to the MXSTATUS Register. + \param [in] MXSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MXSTATUS(uint32_t mxstatus) +{ + __ASM volatile("csrw mxstatus, %0" : : "r"(mxstatus)); +} + +/** + \brief Get MEXSTATUS + \details Returns the content of the MEXSTATUS Register. + \return MEXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEXSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mexstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MEXSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] MEXSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEXSTATUS(uint32_t mexstatus) +{ + __ASM volatile("csrw mexstatus, %0" : : "r"(mexstatus)); +} + + +/** + \brief Get MRADDR + \details Returns the content of the MRADDR Register. + \return MRADDR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MRADDR(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mraddr" : "=r"(result)); + return (result); +} + +/** + \brief Get FXCR + \details Returns the content of the FXCR Register. + \return FXCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_FXCR(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, fxcr" : "=r"(result)); + return (result); +} + + +/** + \brief Set FXCR + \details Writes the given value to the FXCR Register. + \param [in] FXCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_FXCR(uint32_t fxcr) +{ + __ASM volatile("csrw fxcr, %0" : : "r"(fxcr)); +} + +/** + \brief Get MSTATUS + \details Returns the content of the MSTATUS Register. + \return MSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] mstatus MSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSTATUS(uint32_t mstatus) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(mstatus)); +} + +/** + \brief Get MHCR + \details Returns the content of the MHCR Register. + \return MHCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MHCR(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mhcr" : "=r"(result)); + return (result); +} + +/** + \brief Set MHCR + \details Writes the given value to the MHCR Register. + \param [in] mstatus MHCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHCR(uint32_t mhcr) +{ + __ASM volatile("csrw mhcr, %0" : : "r"(mhcr)); +} + +/** + \brief Get MISA Register + \details Returns the content of the MISA Register. + \return MISA Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, misa" : "=r"(result)); + return (result); +} + +/** + \brief Set MISA + \details Writes the given value to the MISA Register. + \param [in] misa MISA Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MISA(uint32_t misa) +{ + __ASM volatile("csrw misa, %0" : : "r"(misa)); +} + +/** + \brief Get MIE Register + \details Returns the content of the MIE Register. + \return MIE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mie" : "=r"(result)); + return (result); +} + +/** + \brief Set MIE + \details Writes the given value to the MIE Register. + \param [in] mie MIE Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIE(uint32_t mie) +{ + __ASM volatile("csrw mie, %0" : : "r"(mie)); +} + +/** + \brief Get MTVEC Register + \details Returns the content of the MTVEC Register. + \return MTVEC Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtvec" : "=r"(result)); + return (result); +} + +/** + \brief Set MTVEC + \details Writes the given value to the MTVEC Register. + \param [in] mtvec MTVEC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVEC(uint32_t mtvec) +{ + __ASM volatile("csrw mtvec, %0" : : "r"(mtvec)); +} + +/** + \brief Set MTVT + \details Writes the given value to the MTVT Register. + \param [in] mtvt MTVT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVT(uint32_t mtvt) +{ + __ASM volatile("csrw mtvt, %0" : : "r"(mtvt)); +} + +/** + \brief Get MTVT Register + \details Returns the content of the MTVT Register. + \return MTVT Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVT(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtvt" : "=r"(result)); + return (result); +} + +/** + \brief Get SP + \details Returns the content of the SP Register. + \return SP Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0, sp" : "=r"(result)); + return (result); +} + +/** + \brief Set SP + \details Writes the given value to the SP Register. + \param [in] sp SP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp) +{ + __ASM volatile("mv sp, %0" : : "r"(sp): "sp"); +} + +/** + \brief Get MSCRATCH Register + \details Returns the content of the MSCRATCH Register. + \return MSCRATCH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mscratch" : "=r"(result)); + return (result); +} + +/** + \brief Set MSCRATCH + \details Writes the given value to the MSCRATCH Register. + \param [in] mscratch MSCRATCH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSCRATCH(uint32_t mscratch) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(mscratch)); +} + +/** + \brief Get MEPC Register + \details Returns the content of the MEPC Register. + \return MEPC Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mepc" : "=r"(result)); + return (result); +} + +/** + \brief Set MEPC + \details Writes the given value to the MEPC Register. + \param [in] mepc MEPC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEPC(uint32_t mepc) +{ + __ASM volatile("csrw mepc, %0" : : "r"(mepc)); +} + +/** + \brief Get MCAUSE Register + \details Returns the content of the MCAUSE Register. + \return MCAUSE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcause" : "=r"(result)); + return (result); +} + +/** + \brief Get MNXTI Register + \details Returns the content of the MNXTI Register. + \return MNXTI Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MNXTI(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mnxti" : "=r"(result)); + return (result); +} + +/** + \brief Set MNXTI + \details Writes the given value to the MNXTI Register. + \param [in] mnxti MNXTI Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MNXTI(uint32_t mnxti) +{ + __ASM volatile("csrw mnxti, %0" : : "r"(mnxti)); +} + +/** + \brief Get MINTSTATUS Register + \details Returns the content of the MINTSTATUS Register. + \return MINTSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINTSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mintstatus" : "=r"(result)); + return (result); +} + +/** + \brief Get MTVAL Register + \details Returns the content of the MTVAL Register. + \return MTVAL Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtval" : "=r"(result)); + return (result); +} + +/** + \brief Get MIP Register + \details Returns the content of the MIP Register. + \return MIP Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIP(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mip" : "=r"(result)); + return (result); +} + +/** + \brief Set MIP + \details Writes the given value to the MIP Register. + \param [in] mip MIP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIP(uint32_t mip) +{ + __ASM volatile("csrw mip, %0" : : "r"(mip)); +} + +/** + \brief Get MCYCLEL Register + \details Returns the content of the MCYCLEL Register. + \return MCYCLE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcycle" : "=r"(result)); + return (result); +} + +/** + \brief Get MCYCLEH Register + \details Returns the content of the MCYCLEH Register. + \return MCYCLEH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLEH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcycleh" : "=r"(result)); + return (result); +} + +/** + \brief Get MINSTRET Register + \details Returns the content of the MINSTRET Register. + \return MINSTRET Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRET(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, minstret" : "=r"(result)); + return (result); +} + +/** + \brief Get MINSTRETH Register + \details Returns the content of the MINSTRETH Register. + \return MINSTRETH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRETH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, minstreth" : "=r"(result)); + return (result); +} + +/** + \brief Get MVENDORID Register + \details Returns the content of the MVENDROID Register. + \return MVENDORID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mvendorid" : "=r"(result)); + return (result); +} + +/** + \brief Get MARCHID Register + \details Returns the content of the MARCHID Register. + \return MARCHID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, marchid" : "=r"(result)); + return (result); +} + +/** + \brief Get MIMPID Register + \details Returns the content of the MIMPID Register. + \return MIMPID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mimpid" : "=r"(result)); + return (result); +} + +/** + \brief Get MHARTID Register + \details Returns the content of the MHARTID Register. + \return MHARTID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mhartid" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPCFGx Register + \details Returns the content of the PMPCFGx Register. + \return PMPCFGx Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG0(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG1(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG2(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG3(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg3" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPxCFG Register by index + \details Returns the content of the PMPxCFG Register. + \param [in] idx PMP region index + \return PMPxCFG Register value + */ +__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) +{ + uint32_t pmpcfgx = 0; + + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + } else if (idx >=4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + } else if (idx >=8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + } else if (idx >=12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + } else { + return 0; + } + + return (uint8_t)((pmpcfgx & (0xFF << (idx << 3))) >> (idx << 3)); +} + +/** + \brief Set PMPCFGx + \details Writes the given value to the PMPCFGx Register. + \param [in] pmpcfg PMPCFGx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPCFG0(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg0, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG1(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg1, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG2(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg2, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG3(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg3, %0" : : "r"(pmpcfg)); +} + +/** + \brief Set PMPxCFG by index + \details Writes the given value to the PMPxCFG Register. + \param [in] idx PMPx region index + \param [in] pmpxcfg PMPxCFG Register value to set + */ +__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) +{ + uint32_t pmpcfgx = 0; + + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG0(pmpcfgx); + } else if (idx >=4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG1(pmpcfgx); + } else if (idx >=8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG2(pmpcfgx); + } else if (idx >=12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG3(pmpcfgx); + } else { + return; + } +} + +/** + \brief Get PMPADDRx Register + \details Returns the content of the PMPADDRx Register. + \return PMPADDRx Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR0(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR1(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR2(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR3(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr3" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR4(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr4" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR5(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr5" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR6(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr6" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR7(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr7" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR8(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr8" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR9(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr9" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR10(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr10" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR11(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr11" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR12(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr12" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR13(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr13" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR14(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr14" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR15(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr15" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPADDRx Register by index + \details Returns the content of the PMPADDRx Register. + \param [in] idx PMP region index + \return PMPADDRx Register value + */ +__STATIC_INLINE uint32_t __get_PMPADDRx(uint32_t idx) +{ + switch (idx) { + case 0: return __get_PMPADDR0(); + case 1: return __get_PMPADDR1(); + case 2: return __get_PMPADDR2(); + case 3: return __get_PMPADDR3(); + case 4: return __get_PMPADDR4(); + case 5: return __get_PMPADDR5(); + case 6: return __get_PMPADDR6(); + case 7: return __get_PMPADDR7(); + case 8: return __get_PMPADDR8(); + case 9: return __get_PMPADDR9(); + case 10: return __get_PMPADDR10(); + case 11: return __get_PMPADDR11(); + case 12: return __get_PMPADDR12(); + case 13: return __get_PMPADDR13(); + case 14: return __get_PMPADDR14(); + case 15: return __get_PMPADDR15(); + default: return 0; + } +} + +/** + \brief Set PMPADDRx + \details Writes the given value to the PMPADDRx Register. + \param [in] pmpaddr PMPADDRx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPADDR0(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr0, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR1(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr1, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR2(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr2, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR3(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr3, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR4(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr4, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR5(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr5, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR6(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr6, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR7(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr7, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR8(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr8, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR9(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr9, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR10(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr10, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR11(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr11, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR12(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr12, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR13(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr13, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR14(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr14, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR15(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr15, %0" : : "r"(pmpaddr)); +} + +/** + \brief Set PMPADDRx by index + \details Writes the given value to the PMPADDRx Register. + \param [in] idx PMP region index + \param [in] pmpaddr PMPADDRx Register value to set + */ +__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, uint32_t pmpaddr) +{ + switch (idx) { + case 0: __set_PMPADDR0(pmpaddr); break; + case 1: __set_PMPADDR1(pmpaddr); break; + case 2: __set_PMPADDR2(pmpaddr); break; + case 3: __set_PMPADDR3(pmpaddr); break; + case 4: __set_PMPADDR4(pmpaddr); break; + case 5: __set_PMPADDR5(pmpaddr); break; + case 6: __set_PMPADDR6(pmpaddr); break; + case 7: __set_PMPADDR7(pmpaddr); break; + case 8: __set_PMPADDR8(pmpaddr); break; + case 9: __set_PMPADDR9(pmpaddr); break; + case 10: __set_PMPADDR10(pmpaddr); break; + case 11: __set_PMPADDR11(pmpaddr); break; + case 12: __set_PMPADDR12(pmpaddr); break; + case 13: __set_PMPADDR13(pmpaddr); break; + case 14: __set_PMPADDR14(pmpaddr); break; + case 15: __set_PMPADDR15(pmpaddr); break; + default: return; + } +} + +/** + \brief Enable interrupts and exceptions + \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_excp_irq(void) +{ + __enable_irq(); +} + + +/** + \brief Disable interrupts and exceptions + \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_excp_irq(void) +{ + __disable_irq(); +} + +#define __CSI_GCC_OUT_REG(r) "=r" (r) +#define __CSI_GCC_USE_REG(r) "r" (r) + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__ALWAYS_STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__ALWAYS_STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __WAIT(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Doze For Interrupt + \details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __DOZE(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Stop For Interrupt + \details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __STOP(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__ALWAYS_STATIC_INLINE void __ISB(void) +{ + __ASM volatile("fence"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__ALWAYS_STATIC_INLINE void __DSB(void) +{ + __ASM volatile("fence"); +} + +/** + \brief Invalid all icache + \details invalid all icache. + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void) +{ + __ASM volatile("icache.iall"); +} + +/** + \brief Invalid Icache by addr + \details Invalid Icache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IPA(uint32_t addr) +{ + __ASM volatile("icache.ipa %0" : : "r"(addr)); +} + +/** + \brief Invalid all dcache + \details invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void) +{ + __ASM volatile("dcache.iall"); +} + +/** + \brief Clear all dcache + \details clear all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void) +{ + __ASM volatile("dcache.call"); +} + +/** + \brief Clear&invalid all dcache + \details clear & invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void) +{ + __ASM volatile("dcache.ciall"); +} + +/** + \brief Invalid Dcache by addr + \details Invalid Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IPA(uint32_t addr) +{ + __ASM volatile("dcache.ipa %0" : : "r"(addr)); +} + +/** + \brief Clear Dcache by addr + \details Clear Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CPA(uint32_t addr) +{ + __ASM volatile("dcache.cpa %0" : : "r"(addr)); +} + +/** + \brief Clear & Invalid Dcache by addr + \details Clear & Invalid Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(uint32_t addr) +{ + __ASM volatile("dcache.cipa %0" : : "r"(addr)); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__ALWAYS_STATIC_INLINE void __DMB(void) +{ + __ASM volatile("fence"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | + ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8); + + return (result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value) +{ + return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8)); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + */ +__ALWAYS_STATIC_INLINE void __BKPT(void) +{ + __ASM volatile("ebreak"); +} + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ + + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz +/** + \details This function saturates a signed value. + \param [in] x Value to be saturated + \param [in] y Bit position to saturate to [1..32] + \return Saturated value. + */ +__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + +// x &= (posMax * 2 + 1); + } else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + +// x &= (posMax * 2 - 1); + } + + return (x); +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Unsigned Saturate for internal use + \details Saturates an unsigned value, should not call directly. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if (value & 0x80000000) { /* only overflow set bit-31 */ + result = 0; + } else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Rotate Right with Extend + \details This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \note carry input will always 0. + \param [in] op1 Value to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1) +{ + return 0; +} + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] addr Pointer to location + \return value of type uint8_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] addr Pointer to location + \return value of type uint16_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] addr Pointer to location + \return value of type uint32_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile("sb %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile("sh %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile("sw %1, 0(%0)" :: "r"(addr), "r"(value) : "memory"); +} + +/*@}*/ /* end of group CSI_Core_InstructionInterface */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics + Access to dedicated SIMD instructions \n + Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used. + + @{ +*/ + +/** + \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] + of val2 levitated with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be left-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for left-shifting val2. Value range [0..31]. + \return the combination of halfwords. + \remark + res[15:0] = val1[15:0] \n + res[31:16] = val2[31:16] << val3 + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000)); +} + +/** + \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] + of val2 right-shifted with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be right-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for right-shifting val2. Value range [1..32]. + \return the combination of halfwords. + \remark + res[15:0] = val2[15:0] >> val3 \n + res[31:16] = val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF)); +} + +/** + \brief Dual 16-bit signed saturate. + \details This function saturates a signed value. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the sum of the absolute differences of the following bytes, added to the accumulation value:\n + the signed saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the signed saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF; + s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturate. + \details This function enables you to saturate two signed 16-bit values to a selected unsigned range. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the saturation of the two signed 16-bit values, as non-negative values: + the saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF; + s = __IUSAT(((x) >> 16), y) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit saturating addition. + \details This function enables you to perform four 8-bit integer additions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating addition. + \details This function enables you to perform four unsigned 8-bit integer additions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed addition. + \details This function performs four 8-bit signed integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition. + \details This function performs four unsigned 8-bit integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit saturating subtract. + \details This function enables you to perform four 8-bit integer subtractions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating subtraction. + \details This function enables you to perform four unsigned 8-bit integer subtractions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed subtraction. + \details This function enables you to perform four 8-bit signed integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtract. + \details This function enables you to perform four 8-bit unsigned integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences together, returning the result as a single unsigned integer. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n + The sum is returned as a single unsigned integer. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 + */ +__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return (u + t + s + r); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences to a 32-bit accumulate operand. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \param [in] sum accumulation value. + \return the sum of the absolute differences of the following bytes, added to the accumulation value: + the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n + res[31:0] = sum[31:0] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum) +{ + int32_t r, s, t, u; + +#ifdef __cplusplus + r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#else + r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#endif + return (u + t + s + r + sum); +} + +/** + \brief Dual 16-bit saturating addition. + \details This function enables you to perform two 16-bit integer arithmetic additions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition. + \details This function enables you to perform two unsigned 16-bit integer additions, saturating + the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition. + \details This function enables you to perform two 16-bit signed integer additions. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition + \details This function enables you to perform two 16-bit unsigned integer additions. + \param [in] x first two 16-bit summands for each addition. + \param [in] y second two 16-bit summands for each addition. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + + +/** + \brief Dual 16-bit signed addition with halved results. + \details This function enables you to perform two signed 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition with halved results. + \details This function enables you to perform two unsigned 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition with halved results. + \details This function enables you to perform four unsigned 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit saturating subtract. + \details This function enables you to perform two 16-bit integer subtractions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction. + \details This function enables you to perform two unsigned 16-bit integer subtractions, + saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit operands for each subtraction. + \param [in] y second two 16-bit operands for each subtraction. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction. + \details This function enables you to perform two 16-bit signed integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtract. + \details This function enables you to perform two 16-bit unsigned integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction with halved results. + \details This function enables you to perform two signed 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction with halved results. + \details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtraction with halved results. + \details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit add and subtract with exchange. + \details This function enables you to exchange the halfwords of the one operand, + then add the high halfwords and subtract the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition and subtraction with exchange. + \details This function enables you to exchange the halfwords of the second operand and + perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, + saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit addition and subtraction with exchange. + \details It enables you to exchange the halfwords of the second operand, add the high halfwords + and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with exchange. + \details This function enables you to exchange the two halfwords of the second operand, + add the high halfwords and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition and subtraction with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one + signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + add the high halfwords and subtract the low halfwords, halving the results. + \param [in] x first operand for the subtraction in the low halfword, and + the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, and + the second operand for the addition in the low halfword. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit subtract and add with exchange. + \details This function enables you to exchange the halfwords of one operand, + then subtract the high halfwords and add the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction and addition with exchange. + \details This function enables you to exchange the halfwords of the second operand and perform + one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating + the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit unsigned subtract and add with exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction and addition with exchange. + \details This function enables you to exchange the two halfwords of one operand and perform one + 16-bit integer subtraction and one 16-bit addition. + \param [in] x first operand for the addition in the low halfword, and the first operand + for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and the second + operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/** + \brief Dual 16-bit signed subtraction and addition with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one signed + 16-bit integer subtraction and one signed 16-bit addition, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction and addition with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords, halving the results. + \param [in] x first operand for the addition in the low halfword, and + the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and + the second operand for the subtraction in the low halfword. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed multiply with exchange returning difference. + \details This function enables you to perform two 16-bit signed multiplications, subtracting + one of the products from the other. The halfwords of the second operand are exchanged + before performing the arithmetic. This produces top * bottom and bottom * top multiplication. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + +/** + \brief Sum of dual 16-bit signed multiply with exchange. + \details This function enables you to perform two 16-bit signed multiplications with exchanged + halfwords of the second operand, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + + +/** + \brief Saturating add. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 + SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y) +{ + int32_t result; + + if (y >= 0) { + if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) { + result = x + y; + } else { + result = 0x7FFFFFFF; + } + } else { + if ((int32_t)((uint32_t)x + (uint32_t)y) < x) { + result = x + y; + } else { + result = 0x80000000; + } + } + + return result; +} + +/** + \brief Saturating subtract. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 - SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y) +{ + int64_t tmp; + int32_t result; + + tmp = (int64_t)x - (int64_t)y; + + if (tmp > 0x7fffffff) { + tmp = 0x7fffffff; + } else if (tmp < (-2147483647 - 1)) { + tmp = -2147483647 - 1; + } + + result = tmp; + return result; +} + +/** + \brief Dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, + adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications with exchanged + halfwords of the second operand, adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication with exchanged halfwords of the second + operand added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to perform two 16-bit signed multiplications, take the + difference of the products, subtracting the high halfword product from the low + halfword product, and add the difference to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit + signed multiplications. The difference of the products is added to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with single 64-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, adding both results + to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. + This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. + \details This function enables you to exchange the halfwords of the second operand, and perform two + signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow + is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. + Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief dual 16-bit signed multiply subtract with 64-bit accumulate. + \details This function It enables you to perform two 16-bit signed multiplications, take the difference + of the products, subtracting the high halfword product from the low halfword product, and add the + difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the + subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not + detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. + \details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, + adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the + multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow + is not detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief 32-bit signed multiply with 32-bit truncated accumulator. + \details This function enables you to perform a signed 32-bit multiplications, adding the most + significant 32 bits of the 64-bit result to a 32-bit accumulate operand. + \param [in] x first operand for multiplication. + \param [in] y second operand for multiplication. + \param [in] sum accumulate value. + \return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer. + \remark + p = val1 * val2 \n + res[31:0] = p[63:32] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum) +{ + return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum); +} + +/** + \brief Sum of dual 16-bit signed multiply. + \details This function enables you to perform two 16-bit signed multiplications, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual 16-bit signed multiply returning difference. + \details This function enables you to perform two 16-bit signed multiplications, taking the difference + of the products by subtracting the high halfword product from the low halfword product. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual extracted 8-bit to 16-bit signed addition. + \details This function enables you to extract two 8-bit values from the second operand (at bit positions + [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand. + \param [in] x values added to the sign-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and sign-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and sign-extended prior to the addition. + \remark + res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n + res[31:16] = val1[31:16] + SignExtended(val2[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) | + (((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000))); +} + +/** + \brief Extracted 16-bit to 32-bit unsigned addition. + \details This function enables you to extract two 8-bit values from one operand, zero-extend + them to 16 bits each, and add the results to two 16-bit values from another operand. + \param [in] x values added to the zero-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and zero-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and zero-extended prior to the addition. + \remark + res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n + res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) | + ((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and sign extend each to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x) +{ + return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) | + ((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and zero-extend to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x) +{ + return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000))); +} + +#endif /* _CSI_RV32_GCC_H_ */ diff --git a/bsp/thead-smart/drivers/drv_common.h b/bsp/thead-smart/drivers/drv_common.h new file mode 100644 index 0000000000..bc43b11e2c --- /dev/null +++ b/bsp/thead-smart/drivers/drv_common.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen Header File for Common Driver + */ + +#ifndef _DRV_COMMON_H_ +#define _DRV_COMMON_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// \details driver handle +typedef void *drv_handle_t; + +#ifndef CONFIG_PARAM_NOT_CHECK +#define HANDLE_PARAM_CHK(para, err) \ + do { \ + if ((int32_t)para == (int32_t)NULL) { \ + return (err); \ + } \ + } while (0) + +#define HANDLE_PARAM_CHK_NORETVAL(para, err) \ + do { \ + if ((int32_t)para == (int32_t)NULL) { \ + return; \ + } \ + } while (0) +#else +#define HANDLE_PARAM_CHK(para, err) +#define HANDLE_PARAM_CHK_NORETVAL(para, err) +#endif + +/** +\brief General power states +*/ +typedef enum +{ + DRV_POWER_OFF, ///< Power off: no operation possible + DRV_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + DRV_POWER_FULL, ///< Power on: full operation at maximum performance + DRV_POWER_SUSPEND, ///< Power suspend: power saving operation +} csi_power_stat_e; + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_COMMON_H */ + diff --git a/bsp/thead-smart/drivers/drv_errno.h b/bsp/thead-smart/drivers/drv_errno.h new file mode 100644 index 0000000000..33fe6574de --- /dev/null +++ b/bsp/thead-smart/drivers/drv_errno.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header file for error num + */ + + +#ifndef _DRV_ERRNO_H_ +#define _DRV_ERRNO_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ERRNO_DRV_START 0X80 + +/* driver General error codes */ +typedef enum +{ + DRV_ERROR = ERRNO_DRV_START, ///< Unspecified error + DRV_ERROR_BUSY, ///< Driver is busy + DRV_ERROR_TIMEOUT, ///< Timeout occurred + DRV_ERROR_UNSUPPORTED, ///< Operation not supported + DRV_ERROR_PARAMETER, ///< Parameter error + DRV_ERROR_SPECIFIC ///< Start of driver specific errors +} drv_err_e; + + +/** Get error type */ +#define GET_ERROR_TYPE(errno) \ + (error & 0xFF000000 >> 24) +/** Get error module */ +#define GET_ERROR_MODULE(error) \ + (error & 0x00FF0000 >> 16) +/** Get error API */ +#define GET_ERROR_API(error) \ + (error & 0x0000FF00 >> 8) +/** Get errno */ +#define GET_ERROR_NUM(error) \ + (error & 0x000000FF) + +#ifndef CSI_DRV_ERRNO_BASE +#define CSI_DRV_ERRNO_BASE 0x81000000 +#endif + +/** driver module id definition*/ +#define CSI_DRV_ERRNO_GPIO_BASE 0x81010000 +#define CSI_DRV_ERRNO_USART_BASE 0x81020000 +#define CSI_DRV_ERRNO_SPI_BASE 0x81030000 +#define CSI_DRV_ERRNO_IIC_BASE 0x81040000 +#define CSI_DRV_ERRNO_PWM_BASE 0x81050000 +#define CSI_DRV_ERRNO_RTC_BASE 0x81060000 +#define CSI_DRV_ERRNO_TIMER_BASE 0x81070000 +#define CSI_DRV_ERRNO_WDT_BASE 0x81080000 +#define CSI_DRV_ERRNO_AES_BASE 0x81090000 +#define CSI_DRV_ERRNO_CRC_BASE 0x810A0000 +#define CSI_DRV_ERRNO_RSA_BASE 0x810B0000 +#define CSI_DRV_ERRNO_SHA_BASE 0x810C0000 +#define CSI_DRV_ERRNO_TRNG_BASE 0x810D0000 +#define CSI_DRV_ERRNO_EFLASH_BASE 0x810E0000 +#define CSI_DRV_ERRNO_DMA_BASE 0x810F0000 +#define CSI_DRV_ERRNO_NORFLASH_BASE 0x81100000 +#define CSI_DRV_ERRNO_INTC_BASE 0x81110000 +#define CSI_DRV_ERRNO_SPU_BASE 0x81120000 +#define CSI_DRV_ERRNO_ADC_BASE 0x81130000 +#define CSI_DRV_ERRNO_PMU_BASE 0x81140000 +#define CSI_DRV_ERRNO_BMU_BASE 0x81150000 +#define CSI_DRV_ERRNO_ETB_BASE 0x81160000 +#define CSI_DRV_ERRNO_I2S_BASE 0x81170000 +#define CSI_DRV_ERRNO_USI_BASE 0x81180000 +#define CSI_DRV_ERRNO_SPIFLASH_BASE 0x81190000 +#define CSI_DRV_ERRNO_ACMP_BASE 0x811A0000 +#define CSI_DRV_ERRNO_MAILBOX_BASE 0x811B0000 +#define CSI_DRV_ERRNO_EFUSEC_BASE 0x811C0000 +#define CSI_DRV_ERRNO_CODEC_BASE 0x811D0000 +#define CSI_DRV_ERRNO_DPU_BASE 0x811E0000 +#define CSI_DRV_ERRNO_VPU_BASE 0x811F0000 +#define CSI_DRV_ERRNO_CAMERA_BASE 0x81200000 +#define CSI_DRV_ERRNO_MIPI_CSI_BASE 0x81210000 +#define CSI_DRV_ERRNO_MIPI_CSI_READER_BASE 0x81220000 +#define CSI_DRV_ERRNO_GMAC_BASE 0x81230000 +#define CSI_DRV_ERRNO_ETHPHY_BASE 0x81240000 +#define CSI_DRV_ERRNO_QW_EFUSE_BASE 0x81250000 +#define CSI_DRV_ERRNO_RESET_BASE 0x81260000 + +#ifdef __cplusplus +} +#endif + +#endif /* CSI_DRV_ERRNO_H */ diff --git a/bsp/thead-smart/drivers/drv_gpio.h b/bsp/thead-smart/drivers/drv_gpio.h new file mode 100644 index 0000000000..1ee5944a69 --- /dev/null +++ b/bsp/thead-smart/drivers/drv_gpio.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header file for gpio driver + */ + +#ifndef _CSI_GPIO_H_ +#define _CSI_GPIO_H_ + + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +/// definition for gpio pin handle. +typedef void *gpio_pin_handle_t; + +/****** GPIO specific error codes *****/ +typedef enum +{ + GPIO_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported + GPIO_ERROR_DIRECTION, ///< Specified direction not supported + GPIO_ERROR_IRQ_MODE, ///< Specified irq mode not supported +} gpio_error_e; + +/*----- GPIO Control Codes: Mode -----*/ +typedef enum +{ + GPIO_MODE_PULLNONE = 0, ///< pull none for input + GPIO_MODE_PULLUP, ///< pull up for input + GPIO_MODE_PULLDOWN, ///< pull down for input + GPIO_MODE_OPEN_DRAIN, ///< open drain mode for output + GPIO_MODE_PUSH_PULL, ///< push-pull mode for output +} gpio_mode_e; + +/*----- GPIO Control Codes: Mode Parameters: Data Bits -----*/ +typedef enum +{ + GPIO_DIRECTION_INPUT = 0, ///< gpio as input + GPIO_DIRECTION_OUTPUT, ///< gpio as output +} gpio_direction_e; + +/*----- GPIO Control Codes: Mode Parameters: Parity -----*/ +typedef enum +{ + GPIO_IRQ_MODE_RISING_EDGE = 0, ///< interrupt mode for rising edge + GPIO_IRQ_MODE_FALLING_EDGE, ///< interrupt mode for falling edge + GPIO_IRQ_MODE_DOUBLE_EDGE, ///< interrupt mode for double edge + GPIO_IRQ_MODE_LOW_LEVEL, ///< interrupt mode for low level + GPIO_IRQ_MODE_HIGH_LEVEL, ///< interrupt mode for high level +} gpio_irq_mode_e; + +typedef void (*gpio_event_cb_t)(int32_t idx); ///< gpio Event call back. + +/** + \brief Initialize GPIO handle. + \param[in] gpio_pin gpio pin idx. + \param[in] cb_event event callback function \ref gpio_event_cb_t + \return gpio_pin_handle +*/ +gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event); + +/** + \brief De-initialize GPIO pin handle.stops operation and releases the software resources used by the handle. + \param[in] handle gpio pin handle to operate. + \return error code +*/ +int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle); + +/** + \brief control gpio power. + \param[in] handle gpio handle to operate. + \param[in] state power state.\ref csi_power_stat_e. + \return error code +*/ +int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state); + +/** + \brief config pin mode + \param[in] pin gpio pin handle to operate. + \param[in] mode \ref gpio_mode_e + \return error code +*/ +int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle, + gpio_mode_e mode); + +/** + \brief config pin direction + \param[in] pin gpio pin handle to operate. + \param[in] dir \ref gpio_direction_e + \return error code +*/ +int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle, + gpio_direction_e dir); + +/** + \brief config pin + \param[in] pin gpio pin handle to operate. + \param[in] mode \ref gpio_mode_e + \param[in] dir \ref gpio_direction_e + \return error code +*/ +int32_t csi_gpio_pin_config(gpio_pin_handle_t handle, + gpio_mode_e mode, + gpio_direction_e dir); + +/** + \brief Set one or zero to the selected GPIO pin. + \param[in] pin gpio pin handle to operate. + \param[in] value value to be set + \return error code +*/ +int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value); + +/** + \brief Get the value of selected GPIO pin. + \param[in] pin gpio pin handle to operate. + \param[out] value buffer to store the pin value + \return error code +*/ +int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value); + +/** + \brief set GPIO interrupt mode. + \param[in] pin gpio pin handle to operate. + \param[in] mode irq mode to be set + \param[in] enable enable flag + \return error code +*/ +int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable); + + +#ifdef __cplusplus +} +#endif + +#endif /* _CSI_GPIO_H_ */ diff --git a/bsp/thead-smart/drivers/drv_irq.h b/bsp/thead-smart/drivers/drv_irq.h new file mode 100644 index 0000000000..80c2edddd9 --- /dev/null +++ b/bsp/thead-smart/drivers/drv_irq.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header File for IRQ Driver + */ + +#include + +/** + \brief enable irq. + \param[in] irq_num Number of IRQ. + \return None. +*/ +void drv_irq_enable(uint32_t irq_num); + +/** + \brief disable irq. + \param[in] irq_num Number of IRQ. + \return None. +*/ +void drv_irq_disable(uint32_t irq_num); + +/** + \brief register irq handler. + \param[in] irq_num Number of IRQ. + \param[in] irq_handler IRQ Handler. + \return None. +*/ +void drv_irq_register(uint32_t irq_num, void *irq_handler); + +/** + \brief unregister irq handler. + \param[in] irq_num Number of IRQ. + \param[in] irq_handler IRQ Handler. + \return None. +*/ +void drv_irq_unregister(uint32_t irq_num); diff --git a/bsp/thead-smart/drivers/drv_timer.h b/bsp/thead-smart/drivers/drv_timer.h new file mode 100644 index 0000000000..12feda3c4c --- /dev/null +++ b/bsp/thead-smart/drivers/drv_timer.h @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen timer driver header file + */ + +/****************************************************************************** + * @file drv_timer.h + * @brief header file for timer driver + * @version V1.0 + * @date 02. June 2017 + * @model timer + ******************************************************************************/ + +#ifndef _CSI_TIMER_H_ +#define _CSI_TIMER_H_ + + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +/// definition for timer handle. +typedef void *timer_handle_t; + +/*----- TIMER Control Codes: Mode -----*/ +typedef enum +{ + TIMER_MODE_FREE_RUNNING = 0, ///< free running mode + TIMER_MODE_RELOAD ///< reload mode +} timer_mode_e; + +/** +\brief TIMER Status +*/ +typedef struct +{ + uint32_t active : 1; ///< timer active flag + uint32_t timeout : 1; ///< timeout flag +} timer_status_t; + +/** +\brief TIMER Event +*/ +typedef enum +{ + TIMER_EVENT_TIMEOUT = 0 ///< time out event +} timer_event_e; + +typedef void (*timer_event_cb_t)(int32_t idx, timer_event_e event); ///< Pointer to \ref timer_event_cb_t : TIMER Event call back. + +/** + \brief Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function + \param[in] idx timer index + \param[in] cb_event event call back function \ref timer_event_cb_t + \param[in] cb_arg arguments of cb_event + \return pointer to timer instance +*/ +timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event); + +/** + \brief De-initialize TIMER Interface. stops operation and releases the software resources used by the interface + \param[in] handle timer handle to operate. + \return error code +*/ +int32_t csi_timer_uninitialize(timer_handle_t handle); + +/** + \brief control timer power. + \param[in] handle timer handle to operate. + \param[in] state power state.\ref csi_power_stat_e. + \return error code +*/ +int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state); + +/** + \brief config timer mode. + \param[in] handle timer handle to operate. + \param[in] mode \ref timer_mode_e + \return error code +*/ +int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode); + +/** + \brief Set timeout just for the reload mode. + \param[in] handle timer handle to operate. + \param[in] timeout the timeout value in microseconds(us). + \return error code +*/ +int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout); + +/** + \brief Start timer. + \param[in] handle timer handle to operate. + \return error code +*/ +int32_t csi_timer_start(timer_handle_t handle); + +/** + \brief Stop timer. + \param[in] handle timer handle to operate. + \return error code +*/ +int32_t csi_timer_stop(timer_handle_t handle); + +/** + \brief suspend timer. + \param[in] handle timer handle to operate. + \return error code +*/ +int32_t csi_timer_suspend(timer_handle_t handle); + +/** + \brief resume timer. + \param[in] handle timer handle to operate. + \return error code +*/ +int32_t csi_timer_resume(timer_handle_t handle); + +/** + \brief get timer current value + \param[in] handle timer handle to operate. + \param[out] value timer current value + \return error code +*/ +int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value); + +/** + \brief Get TIMER status. + \param[in] handle timer handle to operate. + \return TIMER status \ref timer_status_t +*/ +timer_status_t csi_timer_get_status(timer_handle_t handle); + +/** + \brief get timer reload value + \param[in] handle timer handle to operate. + \param[out] value timer reload value + \return error code +*/ +int32_t csi_timer_get_load_value(timer_handle_t handle, uint32_t *value); + +#ifdef __cplusplus +} +#endif + +#endif /* _CSI_TIMER_H_ */ + diff --git a/bsp/thead-smart/drivers/drv_usart.h b/bsp/thead-smart/drivers/drv_usart.h new file mode 100644 index 0000000000..57a69fead6 --- /dev/null +++ b/bsp/thead-smart/drivers/drv_usart.h @@ -0,0 +1,446 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header file for usart driver + */ + +#ifndef _CSI_USART_H_ +#define _CSI_USART_H_ + + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/// definition for usart handle. +typedef void *usart_handle_t; + +/****** USART specific error codes *****/ +typedef enum +{ + USART_ERROR_MODE = (DRV_ERROR_SPECIFIC + 1), ///< Specified Mode not supported + USART_ERROR_BAUDRATE, ///< Specified baudrate not supported + USART_ERROR_DATA_BITS, ///< Specified number of Data bits not supported + USART_ERROR_PARITY, ///< Specified Parity not supported + USART_ERROR_STOP_BITS, ///< Specified number of Stop bits not supported + USART_ERROR_FLOW_CONTROL, ///< Specified Flow Control not supported + USART_ERROR_CPOL, ///< Specified Clock Polarity not supported + USART_ERROR_CPHA ///< Specified Clock Phase not supported +} usart_error_e; + +/*----- USART Control Codes: Mode -----*/ +typedef enum +{ + USART_MODE_ASYNCHRONOUS = 0, ///< USART (Asynchronous) + USART_MODE_SYNCHRONOUS_MASTER, ///< Synchronous Master + USART_MODE_SYNCHRONOUS_SLAVE, ///< Synchronous Slave (external clock signal) + USART_MODE_SINGLE_WIRE, ///< USART Single-wire (half-duplex) + USART_MODE_SINGLE_IRDA, ///< UART IrDA + USART_MODE_SINGLE_SMART_CARD, ///< UART Smart Card +} usart_mode_e; + +/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ +typedef enum +{ + USART_DATA_BITS_5 = 0, ///< 5 Data bits + USART_DATA_BITS_6, ///< 6 Data bit + USART_DATA_BITS_7, ///< 7 Data bits + USART_DATA_BITS_8, ///< 8 Data bits (default) + USART_DATA_BITS_9 ///< 9 Data bits +} usart_data_bits_e; + +/*----- USART Control Codes: Mode Parameters: Parity -----*/ +typedef enum +{ + USART_PARITY_NONE = 0, ///< No Parity (default) + USART_PARITY_EVEN, ///< Even Parity + USART_PARITY_ODD, ///< Odd Parity + USART_PARITY_1, ///< Parity forced to 1 + USART_PARITY_0 ///< Parity forced to 0 +} usart_parity_e; + +/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ +typedef enum +{ + USART_STOP_BITS_1 = 0, ///< 1 Stop bit (default) + USART_STOP_BITS_2, ///< 2 Stop bits + USART_STOP_BITS_1_5, ///< 1.5 Stop bits + USART_STOP_BITS_0_5 ///< 0.5 Stop bits +} usart_stop_bits_e; + +/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ +typedef enum +{ + USART_CPOL0 = 0, ///< CPOL = 0 (default). data are captured on rising edge (low->high transition) + USART_CPOL1 ///< CPOL = 1. data are captured on falling edge (high->lowh transition) +} usart_cpol_e; + +/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ +typedef enum +{ + USART_CPHA0 = 0, ///< CPHA = 0 (default). sample on first (leading) edge + USART_CPHA1 ///< CPHA = 1. sample on second (trailing) edge +} usart_cpha_e; + +/*----- USART Control Codes: flush data type-----*/ +typedef enum +{ + USART_FLUSH_WRITE, + USART_FLUSH_READ +} usart_flush_type_e; + +/*----- USART Control Codes: flow control type-----*/ +typedef enum +{ + USART_FLOWCTRL_NONE, + USART_FLOWCTRL_CTS, + USART_FLOWCTRL_RTS, + USART_FLOWCTRL_CTS_RTS +} usart_flowctrl_type_e; + +/*----- USART Modem Control -----*/ +typedef enum +{ + USART_RTS_CLEAR, ///< Deactivate RTS + USART_RTS_SET, ///< Activate RTS + USART_DTR_CLEAR, ///< Deactivate DTR + USART_DTR_SET ///< Activate DTR +} usart_modem_ctrl_e; + +/*----- USART Modem Status -----*/ +typedef struct +{ + uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive + uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive + uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive + uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive +} usart_modem_stat_t; + +/*----- USART Control Codes: on-off intrrupte type-----*/ +typedef enum +{ + USART_INTR_WRITE, + USART_INTR_READ +} usart_intr_type_e; + +/** +\brief USART Status +*/ +typedef struct { + uint32_t tx_busy : 1; ///< Transmitter busy flag + uint32_t rx_busy : 1; ///< Receiver busy flag + uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)(Synchronous Slave) + uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) + uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) + uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) + uint32_t tx_enable : 1; ///< Transmitter enable flag + uint32_t rx_enable : 1; ///< Receiver enbale flag +} usart_status_t; + +/****** USART Event *****/ +typedef enum +{ + USART_EVENT_SEND_COMPLETE = 0, ///< Send completed; however USART may still transmit data + USART_EVENT_RECEIVE_COMPLETE = 1, ///< Receive completed + USART_EVENT_TRANSFER_COMPLETE = 2, ///< Transfer completed + USART_EVENT_TX_COMPLETE = 3, ///< Transmit completed (optional) + USART_EVENT_TX_UNDERFLOW = 4, ///< Transmit data not available (Synchronous Slave) + USART_EVENT_RX_OVERFLOW = 5, ///< Receive data overflow + USART_EVENT_RX_TIMEOUT = 6, ///< Receive character timeout (optional) + USART_EVENT_RX_BREAK = 7, ///< Break detected on receive + USART_EVENT_RX_FRAMING_ERROR = 8, ///< Framing error detected on receive + USART_EVENT_RX_PARITY_ERROR = 9, ///< Parity error detected on receive + USART_EVENT_CTS = 10, ///< CTS state changed (optional) + USART_EVENT_DSR = 11, ///< DSR state changed (optional) + USART_EVENT_DCD = 12, ///< DCD state changed (optional) + USART_EVENT_RI = 13, ///< RI state changed (optional) + USART_EVENT_RECEIVED = 14, ///< Data Received, only in usart fifo, call receive()/transfer() get the data +} usart_event_e; + +typedef void (*usart_event_cb_t)(int32_t idx, usart_event_e event); ///< Pointer to \ref usart_event_cb_t : USART Event call back. + +/** +\brief USART Driver Capabilities. +*/ +typedef struct { + uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode + uint32_t synchronous_master : 1; ///< supports Synchronous Master mode + uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode + uint32_t single_wire : 1; ///< supports UART Single-wire mode + uint32_t irda : 1; ///< supports UART IrDA mode + uint32_t smart_card : 1; ///< supports UART Smart Card mode + uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available + uint32_t flow_control_rts : 1; ///< RTS Flow Control available + uint32_t flow_control_cts : 1; ///< CTS Flow Control available + uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref USART_EVENT_TX_COMPLETE + uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref USART_EVENT_RX_TIMEOUT + uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available + uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available + uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available + uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available + uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available + uint32_t ri : 1; ///< RI Line: 0=not available, 1=available + uint32_t event_cts : 1; ///< Signal CTS change event: \ref USART_EVENT_CTS + uint32_t event_dsr : 1; ///< Signal DSR change event: \ref USART_EVENT_DSR + uint32_t event_dcd : 1; ///< Signal DCD change event: \ref USART_EVENT_DCD + uint32_t event_ri : 1; ///< Signal RI change event: \ref USART_EVENT_RI +} usart_capabilities_t; + +/** + \brief Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function + \param[in] idx usart index + \param[in] cb_event event call back function \ref usart_event_cb_t + \return return usart handle if success +*/ +usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event); + +/** + \brief De-initialize USART Interface. stops operation and releases the software resources used by the interface + \param[in] handle usart handle to operate. + \return error code +*/ +int32_t csi_usart_uninitialize(usart_handle_t handle); +/** + \brief Get driver capabilities. + \param[in] idx usart index + \return \ref usart_capabilities_t +*/ +usart_capabilities_t csi_usart_get_capabilities(int32_t idx); + +/** + \brief config usart mode. + \param[in] handle usart handle to operate. + \param[in] baud baud rate. + \param[in] mode \ref usart_mode_e . + \param[in] parity \ref usart_parity_e . + \param[in] stopbits \ref usart_stop_bits_e . + \param[in] bits \ref usart_data_bits_e . + \return error code +*/ +int32_t csi_usart_config(usart_handle_t handle, + uint32_t baud, + usart_mode_e mode, + usart_parity_e parity, + usart_stop_bits_e stopbits, + usart_data_bits_e bits); + + +/** + \brief Start sending data to USART transmitter,(received data is ignored). + This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens. + \ref csi_usart_get_status can get operation status. + \param[in] handle usart handle to operate. + \param[in] data Pointer to buffer with data to send to USART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits + \param[in] num Number of data items to send + \return error code +*/ +int32_t csi_usart_send(usart_handle_t handle, const void *data, uint32_t num); + +/** + \brief Abort Send data to USART transmitter + \param[in] handle usart handle to operate. + \return error code +*/ +int32_t csi_usart_abort_send(usart_handle_t handle); + +/** + \brief Start receiving data from USART receiver. \n + This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens. + \ref csi_usart_get_status can get operation status. + \param[in] handle usart handle to operate. + \param[out] data Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits + \param[in] num Number of data items to receive + \return error code +*/ +int32_t csi_usart_receive(usart_handle_t handle, void *data, uint32_t num); + +/** + \brief query data from UART receiver FIFO. + \param[in] handle usart handle to operate. + \param[out] data Pointer to buffer for data to receive from UART receiver + \param[in] num Number of data items to receive + \return fifo data num to receive +*/ +int32_t csi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num); + +/** + \brief Abort Receive data from USART receiver + \param[in] handle usart handle to operate. + \return error code +*/ +int32_t csi_usart_abort_receive(usart_handle_t handle); + +/** + \brief Start synchronously sends data to the USART transmitter and receives data from the USART receiver. used in synchronous mode + This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens. + \ref csi_usart_get_status can get operation status. + \param[in] handle usart handle to operate. + \param[in] data_out Pointer to buffer with data to send to USART transmitter.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits + \param[out] data_in Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits + \param[in] num Number of data items to transfer + \return error code +*/ +int32_t csi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num); + +/** + \brief abort sending/receiving data to/from USART transmitter/receiver. + \param[in] handle usart handle to operate. + \return error code +*/ +int32_t csi_usart_abort_transfer(usart_handle_t handle); + +/** + \brief Get USART status. + \param[in] handle usart handle to operate. + \return USART status \ref usart_status_t +*/ +usart_status_t csi_usart_get_status(usart_handle_t handle); + +/** + \brief flush receive/send data. + \param[in] handle usart handle to operate. + \param[in] type \ref usart_flush_type_e . + \return error code +*/ +int32_t csi_usart_flush(usart_handle_t handle, usart_flush_type_e type); + +/** + \brief set interrupt mode. + \param[in] handle usart handle to operate. + \param[in] type \ref usart_intr_type_e. + \param[in] flag 0-OFF, 1-ON. + \return error code +*/ +int32_t csi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag); + +/** + \brief set the baud rate of usart. + \param[in] baud usart base to operate. + \param[in] baudrate baud rate + \return error code +*/ +int32_t csi_usart_config_baudrate(usart_handle_t handle, uint32_t baud); + +/** + \brief config usart mode. + \param[in] handle usart handle to operate. + \param[in] mode \ref usart_mode_e + \return error code +*/ +int32_t csi_usart_config_mode(usart_handle_t handle, usart_mode_e mode); + +/** + \brief config usart parity. + \param[in] handle usart handle to operate. + \param[in] parity \ref usart_parity_e + \return error code +*/ +int32_t csi_usart_config_parity(usart_handle_t handle, usart_parity_e parity); + +/** + \brief config usart stop bit number. + \param[in] handle usart handle to operate. + \param[in] stopbits \ref usart_stop_bits_e + \return error code +*/ +int32_t csi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit); + +/** + \brief config usart data length. + \param[in] handle usart handle to operate. + \param[in] databits \ref usart_data_bits_e + \return error code +*/ +int32_t csi_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits); + +/** + \brief get character in query mode. + \param[in] handle usart handle to operate. + \param[out] ch the pointer to the received character. + \return error code +*/ +int32_t csi_usart_getchar(usart_handle_t handle, uint8_t *ch); + +/** + \brief transmit character in query mode. + \param[in] handle usart handle to operate. + \param[in] ch the input character + \return error code +*/ +int32_t csi_usart_putchar(usart_handle_t handle, uint8_t ch); + +/** + \brief Get usart send data count. + \param[in] handle usart handle to operate. + \return number of currently transmitted data bytes +*/ +uint32_t csi_usart_get_tx_count(usart_handle_t handle); + +/** + \brief Get usart received data count. + \param[in] handle usart handle to operate. + \return number of currently received data bytes +*/ +uint32_t csi_usart_get_rx_count(usart_handle_t handle); + +/** + \brief control usart power. + \param[in] handle usart handle to operate. + \param[in] state power state.\ref csi_power_stat_e. + \return error code +*/ +int32_t csi_usart_power_control(usart_handle_t handle, csi_power_stat_e state); + +/** + \brief config usart flow control type. + \param[in] handle usart handle to operate. + \param[in] flowctrl_type flow control type.\ref usart_flowctrl_type_e. + \return error code +*/ +int32_t csi_usart_config_flowctrl(usart_handle_t handle, + usart_flowctrl_type_e flowctrl_type); + +/** + \brief config usart clock Polarity and Phase. + \param[in] handle usart handle to operate. + \param[in] cpol Clock Polarity.\ref usart_cpol_e. + \param[in] cpha Clock Phase.\ref usart_cpha_e. + \return error code +*/ +int32_t csi_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha); + +/** + \brief control the transmitter. + \param[in] handle usart handle to operate. + \param[in] enable 1 - enable the transmitter. 0 - disable the transmitter + \return error code +*/ +int32_t csi_usart_control_tx(usart_handle_t handle, uint32_t enable); + +/** + \brief control the receiver. + \param[in] handle usart handle to operate. + \param[in] enable 1 - enable the receiver. 0 - disable the receiver + \return error code +*/ +int32_t csi_usart_control_rx(usart_handle_t handle, uint32_t enable); + +/** + \brief control the break. + \param[in] handle usart handle to operate. + \param[in] enable 1- Enable continuous Break transmission,0 - disable continuous Break transmission + \return error code +*/ +int32_t csi_usart_control_break(usart_handle_t handle, uint32_t enable); + +#ifdef __cplusplus +} +#endif + +#endif /* _CSI_USART_H_ */ diff --git a/bsp/thead-smart/drivers/dw_gpio.c b/bsp/thead-smart/drivers/dw_gpio.c new file mode 100644 index 0000000000..9ee3a3e429 --- /dev/null +++ b/bsp/thead-smart/drivers/dw_gpio.c @@ -0,0 +1,635 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen gpio driver + */ + +/****************************************************************************** + * @file dw_gpio.c + * @brief CSI Source File for GPIO Driver + * @version V1.0 + * @date 02. June 2017 + ******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern int32_t drv_pin_config_mode(port_name_e port, uint8_t offset, gpio_mode_e pin_mode); + +#define ERR_GPIO(errno) (CSI_DRV_ERRNO_GPIO_BASE | errno) +#define GPIO_NULL_PARAM_CHK(para) HANDLE_PARAM_CHK(para, ERR_GPIO(DRV_ERROR_PARAMETER)) + +typedef void *gpio_port_handle_t; + +typedef struct +{ +#ifdef CONFIG_LPM + uint8_t gpio_power_status; + uint32_t gpio_regs_saved[7]; +#endif + uint32_t base; ///< handle register base + uint32_t irq; ///< irq of this handle + uint32_t pin_num; ///< pin number of this handle + gpio_mode_e mode; ///< gpio mode + gpio_direction_e dir; ///< gpio direction + uint32_t mask; ///< gpio mask bit + uint32_t value; ///< gpio value +} dw_gpio_priv_t; + +typedef struct +{ + uint8_t portidx; + uint8_t idx; + uint8_t offset; + gpio_event_cb_t cb; +} dw_gpio_pin_priv_t; + +extern int32_t target_gpio_port_init(port_name_e port, uint32_t *base, uint32_t *irq, void **handler, uint32_t *pin_num); +extern int32_t target_gpio_pin_init(int32_t gpio_pin, uint32_t *port_idx); + +static dw_gpio_priv_t gpio_handle[CONFIG_GPIO_NUM]; +static dw_gpio_pin_priv_t gpio_pin_handle[CONFIG_GPIO_PIN_NUM]; + +// +// Functions +// +static int32_t gpio_set_direction( + void *port, + gpio_direction_e direction +) +{ + dw_gpio_priv_t *gpio_priv = port; + dw_gpio_reg_t *gpio_reg = (dw_gpio_reg_t *)(gpio_priv->base); + + if (direction == GPIO_DIRECTION_INPUT) + { + gpio_reg->SWPORT_DDR &= (~gpio_priv->mask); + } else if (direction == GPIO_DIRECTION_OUTPUT) + { + gpio_reg->SWPORT_DDR |= gpio_priv->mask; + } else + { + return ERR_GPIO(GPIO_ERROR_DIRECTION); + } + + return 0; +} + +/* + * Read the statu of the Port choosed. + * Parameters: + * port: use to choose a I/O port among Port A, B, or C. + * return: the value of the corresponding Port. + */ + +static int32_t gpio_read(void *port, uint32_t *value) +{ + dw_gpio_priv_t *gpio_priv = port; + dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(gpio_priv->base + 0x30); + *value = gpio_control_reg->EXT_PORTA; + return 0; +} + + +/* + * Write an output value to corresponding Port. + * Parameters: + * port: use to choose a I/O port among Port A, B, or C. + * output: value that will be written to the corresponding Port. + * return: SUCCESS + */ + +static int32_t gpio_write(void *port, uint32_t mask) +{ + dw_gpio_priv_t *gpio_priv = port; + dw_gpio_reg_t *gpio_reg = (dw_gpio_reg_t *)(gpio_priv->base); + + uint32_t value = gpio_reg->SWPORT_DR; + + value &= ~(mask); + value |= gpio_priv->value; + gpio_reg->SWPORT_DR = value; + return 0; +} + +/** + * Configure a GPIO gpio_set_irq_mode. + * @param[in] pin the addr store the pin num. + * @param[in] _irqmode the irqmode of gpio + * @return zero on success. -1 on falure. + */ +static int32_t gpio_set_irq_mode(gpio_pin_handle_t pin, gpio_irq_mode_e irq_mode) +{ + dw_gpio_pin_priv_t *gpio_pin_priv = pin; + + /* convert portidx to port handle */ + dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx]; + + dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30); + uint32_t offset = gpio_pin_priv->idx; + uint32_t mask = 1 << offset; + + switch (irq_mode) + { + /* rising edge interrupt mode */ + case GPIO_IRQ_MODE_RISING_EDGE: + gpio_control_reg->INTTYPE_LEVEL |= mask; + gpio_control_reg->INT_POLARITY |= mask; + break; + + /* falling edge interrupt mode */ + case GPIO_IRQ_MODE_FALLING_EDGE: + gpio_control_reg->INTTYPE_LEVEL |= mask; + gpio_control_reg->INT_POLARITY &= (~mask); + break; + + /* low level interrupt mode */ + case GPIO_IRQ_MODE_LOW_LEVEL: + gpio_control_reg->INTTYPE_LEVEL &= (~mask); + gpio_control_reg->INT_POLARITY &= (~mask); + break; + + /* high level interrupt mode */ + case GPIO_IRQ_MODE_HIGH_LEVEL: + gpio_control_reg->INTTYPE_LEVEL &= (~mask); + gpio_control_reg->INT_POLARITY |= mask; + break; + + /* double edge interrupt mode */ + case GPIO_IRQ_MODE_DOUBLE_EDGE: + return ERR_GPIO(DRV_ERROR_UNSUPPORTED); + + default: + return ERR_GPIO(GPIO_ERROR_IRQ_MODE); + } + + return 0; +} + +/* + * Clear one or more interrupts of PortA. + * Parameters: + * pinno: + * return: SUCCESS. + */ + +static void gpio_irq_clear(gpio_pin_handle_t pin, uint32_t idx) +{ + dw_gpio_pin_priv_t *gpio_pin_priv = pin; + + /* convert portidx to port handle */ + dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx]; + + dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30); + + gpio_control_reg->PORTA_EOI = idx; +} + + +/* + * Enable one or more interrupts of PortA. + * Parameters: + * pinno: + * return: SUCCESS. + */ +static void gpio_irq_enable(gpio_pin_handle_t pin) +{ + dw_gpio_pin_priv_t *gpio_pin_priv = pin; + + /* convert portidx to port handle */ + dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx]; + + dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30); + uint32_t offset = gpio_pin_priv->idx; + uint32_t val = gpio_control_reg->INTEN; + val |= (1 << offset); + gpio_control_reg->INTEN = val; +} + + +/* + * Disable one or more interrupts of PortA. + * Parameters: + * pinno: + * return: SUCCESS. + */ + +static void gpio_irq_disable(gpio_pin_handle_t pin) +{ + dw_gpio_pin_priv_t *gpio_pin_priv = pin; + uint32_t offset = gpio_pin_priv->idx; + + /* convert portidx to port handle */ + dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx]; + + dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30); + uint32_t val = gpio_control_reg->INTEN; + val &= ~(1 << offset); + gpio_control_reg->INTEN = val; +} + +void dw_gpio_irqhandler(int idx) +{ + if (idx >= CONFIG_GPIO_NUM) + { + return; + } + + dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(gpio_handle[idx].base + 0x30); + + uint32_t value = gpio_control_reg->INTSTATUS; + uint8_t i; + + /* find the interrput pin */ + for (i = 0; i < 32; i++) + { + if (value & (1U << i)) + { + uint32_t pin_idx = i; + +#ifndef CONFIG_CHIP_DANICA + uint8_t j; + + if (idx > 0) + { + for (j = 0; j < idx; j++) + { + pin_idx += gpio_handle[j].pin_num; + } + } + + if (pin_idx >= CONFIG_GPIO_PIN_NUM) + { + return; + } + +#endif + dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)&gpio_pin_handle[pin_idx]; + + gpio_irq_clear(gpio_pin_priv, (1 << i)); //clear the gpio interrupt + + /* execute the callback function */ + if ((gpio_event_cb_t)(gpio_pin_priv->cb)) + { + ((gpio_event_cb_t)(gpio_pin_priv->cb))(gpio_pin_priv->offset); + } + } + } +} + +/** + \brief Initialize GPIO module. 1. Initializes the resources needed for the GPIO handle 2.registers event callback function + 3.get gpio_port_handle + \param[in] port port_name. + \return gpio_port_handle +*/ +gpio_port_handle_t csi_gpio_port_initialize(int32_t port) +{ + dw_gpio_priv_t *gpio_priv = NULL; + + /* obtain the gpio port information */ + uint32_t base = 0u; + uint32_t pin_num; + uint32_t irq; + void *handler; + int32_t idx = target_gpio_port_init(port, &base, &irq, &handler, &pin_num); + + if (idx < 0 || idx >= CONFIG_GPIO_NUM) + { + return NULL; + } + + gpio_priv = &gpio_handle[idx]; + + gpio_priv->base = base; + gpio_priv->irq = irq; + gpio_priv->pin_num = pin_num; + +#ifdef CONFIG_LPM + csi_gpio_power_control(gpio_priv, DRV_POWER_FULL); +#endif + + drv_irq_register(gpio_priv->irq, handler); + drv_irq_enable(gpio_priv->irq); + + return (gpio_port_handle_t)gpio_priv; +} + +/** + \brief De-initialize GPIO handle. stops operation and releases the software resources used by the handle + \param[in] handle gpio port handle to operate. + \return error code +*/ +int32_t csi_gpio_port_uninitialize(gpio_port_handle_t handle) +{ + GPIO_NULL_PARAM_CHK(handle); + + dw_gpio_priv_t *gpio_priv = handle; + + drv_irq_disable(gpio_priv->irq); + drv_irq_unregister(gpio_priv->irq); + +#ifdef CONFIG_LPM + csi_gpio_power_control(gpio_priv, DRV_POWER_OFF); +#endif + + return 0; +} + +#ifdef CONFIG_LPM +static void manage_clock(gpio_pin_handle_t handle, uint8_t enable) +{ + dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle; + uint8_t device[] = {CLOCK_MANAGER_GPIO0, CLOCK_MANAGER_GPIO1}; + + drv_clock_manager_config(device[gpio_pin_priv->portidx], enable); +} + +static void do_prepare_sleep_action(void *handle) +{ + dw_gpio_priv_t *gpio_handle = handle; + uint32_t *gbase = (uint32_t *)(gpio_handle->base); + uint32_t *control_base = (uint32_t *)(gpio_handle->base + 0x30); + registers_save(gpio_handle->gpio_regs_saved, gbase, 3); + registers_save(&gpio_handle->gpio_regs_saved[3], control_base, 4); +} + +static void do_wakeup_sleep_action(void *handle) +{ + dw_gpio_priv_t *gpio_handle = handle; + uint32_t *gbase = (uint32_t *)(gpio_handle->base); + uint32_t *control_base = (uint32_t *)(gpio_handle->base + 0x30); + registers_restore(gbase, gpio_handle->gpio_regs_saved, 3); + registers_restore(control_base, &gpio_handle->gpio_regs_saved[3], 4); +} +#endif + +/** + \brief Initialize GPIO handle. + \param[in] gpio_pin Pointer to the int32_t. + \param[in] cb_event Pointer to \ref gpio_event_cb_t. + \param[in] arg Pointer to \ref arg used for the callback. + \return gpio_pin_handle +*/ +gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event) +{ + + if (gpio_pin < 0 || gpio_pin >= CONFIG_GPIO_PIN_NUM) + { + return NULL; + } + + uint32_t i; + + for (i = 0; i < CONFIG_GPIO_NUM; i++) + { + csi_gpio_port_initialize(i); + } + + /* obtain the gpio pin information */ + uint32_t port_idx; + int32_t pin_idx = target_gpio_pin_init(gpio_pin, &port_idx); + + if (pin_idx < 0) + { + return NULL; + } + + int32_t idx = pin_idx; + + for (i = 0; i < port_idx; i++) + { + idx += (gpio_handle[i].pin_num); + } + + dw_gpio_pin_priv_t *gpio_pin_priv = &(gpio_pin_handle[idx]); + gpio_pin_priv->portidx = port_idx; + + + gpio_pin_priv->idx = pin_idx; + gpio_pin_priv->cb = cb_event; + gpio_pin_priv->offset = gpio_pin; + + return (gpio_pin_handle_t)gpio_pin_priv; +} + +/** + \brief De-initialize GPIO pin handle. stops operation and releases the software resources used by the handle + \param[in] handle gpio pin handle to operate. + \return error code +*/ +int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle) +{ + if (handle == NULL) + { + return ERR_GPIO(DRV_ERROR_PARAMETER); + } + + dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle; + gpio_pin_priv->cb = NULL; + + gpio_irq_disable(handle); + + return 0; +} + +/** + \brief control gpio power. + \param[in] idx gpio index. + \param[in] state power state.\ref csi_power_stat_e. + \return error code +*/ +int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state) +{ + GPIO_NULL_PARAM_CHK(handle); + +#ifdef CONFIG_LPM + dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle; + power_cb_t callback = + { + .wakeup = do_wakeup_sleep_action, + .sleep = do_prepare_sleep_action, + .manage_clock = manage_clock + }; + return drv_soc_power_control(&gpio_handle[gpio_pin_priv->portidx], state, &callback); +#else + return ERR_GPIO(DRV_ERROR_UNSUPPORTED); +#endif +} + +/** + \brief config pin mode + \param[in] pin gpio pin handle to operate. + \param[in] mode \ref gpio_mode_e + \return error code +*/ +int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle, + gpio_mode_e mode) +{ + GPIO_NULL_PARAM_CHK(handle); + + /* config the gpio pin mode direction mask bits */ + dw_gpio_pin_priv_t *gpio_pin_priv = handle; + + uint8_t offset = gpio_pin_priv->idx; + + int32_t ret = drv_pin_config_mode(gpio_pin_priv->portidx, offset, mode); + + return ret; +} +/** + \brief config pin direction + \param[in] pin gpio pin handle to operate. + \param[in] dir \ref gpio_direction_e + \return error code +*/ +int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle, + gpio_direction_e dir) +{ + GPIO_NULL_PARAM_CHK(handle); + + /* config the gpio pin mode direction mask bits */ + dw_gpio_pin_priv_t *gpio_pin_priv = handle; + + /* convert portidx to port handle */ + dw_gpio_priv_t *gpio_priv = &gpio_handle[gpio_pin_priv->portidx]; + + gpio_priv->dir = dir; + gpio_priv->mask = 1 << gpio_pin_priv->idx; + + uint32_t ret = gpio_set_direction(gpio_priv, dir); + + if (ret) + { + return ret; + } + + return 0; +} + +/** + \brief config pin + \param[in] handle gpio pin handle to operate. + \param[in] mode \ref gpio_mode_e + \param[in] dir \ref gpio_direction_e + \return error code +*/ +int32_t csi_gpio_pin_config(gpio_pin_handle_t handle, + gpio_mode_e mode, + gpio_direction_e dir) +{ + GPIO_NULL_PARAM_CHK(handle); + + /* config the gpio pin mode direction mask bits */ + dw_gpio_pin_priv_t *gpio_pin_priv = handle; + + /* convert portidx to port handle */ + dw_gpio_priv_t *gpio_priv = &gpio_handle[gpio_pin_priv->portidx]; + + gpio_priv->mode = mode; + gpio_priv->dir = dir; + gpio_priv->mask = 1 << gpio_pin_priv->idx; + + uint32_t ret = gpio_set_direction(gpio_priv, dir); + + if (ret) + { + return ret; + } + + return 0; + +} + +/** + \brief Set one or zero to the selected GPIO pin. + \param[in] handle gpio pin handle to operate. + \param[in] value the value to be set + \return error code +*/ +int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value) +{ + GPIO_NULL_PARAM_CHK(handle); + + dw_gpio_pin_priv_t *gpio_pin_priv = handle; + + /* convert portidx to port handle */ + dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx]; + + uint8_t offset = gpio_pin_priv->idx; + uint32_t port_value = value << offset; + + port_handle->value = port_value; + gpio_write(port_handle, (1 << offset)); + + return 0; + +} + +/** + \brief Get the value of selected GPIO pin. + \param[in] handle gpio pin handle to operate. + \param[out] value buf to store the pin value + \return error code +*/ +int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value) +{ + GPIO_NULL_PARAM_CHK(handle); + GPIO_NULL_PARAM_CHK(value); + + dw_gpio_pin_priv_t *gpio_pin_priv = handle; + uint32_t port_value; + uint8_t offset = gpio_pin_priv->idx; + + /* convert portidx to port handle */ + dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx]; + + gpio_read(port_handle, &port_value); + *value = (port_value & (1 << offset)) >> offset; + + return 0; +} + +/** + \brief set GPIO interrupt mode. + \param[in] handle gpio pin handle to operate. + \param[in] mode the irq mode to be set + \param[in] enable the enable flag + \return error code +*/ +int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable) +{ + GPIO_NULL_PARAM_CHK(handle); + + uint32_t ret = 0; + + if (enable) + { + ret = gpio_set_irq_mode(handle, mode); + + if (ret) + { + return ret; + } + + gpio_irq_enable(handle); + + } else + { + gpio_irq_disable(handle); + + } + + return ret; +} + diff --git a/bsp/thead-smart/drivers/dw_gpio.h b/bsp/thead-smart/drivers/dw_gpio.h new file mode 100644 index 0000000000..768cdf1b1d --- /dev/null +++ b/bsp/thead-smart/drivers/dw_gpio.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header file for GPIO Driver + */ + +#ifndef _DW_GPIO_H_ +#define _DW_GPIO_H_ + +#include "drv_gpio.h" +#include "soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct +{ + __IOM uint32_t SWPORT_DR; /* Offset: 0x000 (W/R) PortA data register */ + __IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (W/R) PortA data direction register */ + __IOM uint32_t PORT_CTL; /* Offset: 0x008 (W/R) PortA source register */ + +} dw_gpio_reg_t; + +typedef struct +{ + __IOM uint32_t INTEN; /* Offset: 0x000 (W/R) Interrupt enable register */ + __IOM uint32_t INTMASK; /* Offset: 0x004 (W/R) Interrupt mask register */ + __IOM uint32_t INTTYPE_LEVEL; /* Offset: 0x008 (W/R) Interrupt level register */ + __IOM uint32_t INT_POLARITY; /* Offset: 0x00c (W/R) Interrupt polarity register */ + __IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */ + __IM uint32_t RAWINTSTATUS; /* Offset: 0x014 (W/R) Raw interrupt status of Port */ + __IOM uint32_t revreg1; /* Offset: 0x018 (W/R) Reserve register */ + __OM uint32_t PORTA_EOI; /* Offset: 0x01c (W/R) Port clear interrupt register */ + __IM uint32_t EXT_PORTA; /* Offset: 0x020 (W/R) PortA external port register */ + __IM uint32_t EXT_PORTB; /* Offset: 0x024 (W/R) PortB external port register */ + __IOM uint32_t revreg2[2]; /* Offset: 0x028 (W/R) Reserve register */ + __IOM uint32_t LS_SYNC; /* Offset: 0x030 (W/R) Level-sensitive synchronization enable register */ + +} dw_gpio_control_reg_t; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/thead-smart/drivers/dw_timer.c b/bsp/thead-smart/drivers/dw_timer.c new file mode 100644 index 0000000000..5792d47a73 --- /dev/null +++ b/bsp/thead-smart/drivers/dw_timer.c @@ -0,0 +1,409 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen CSI Source File for timer Driver + */ + + +#include +#include +#include +#include +#include +#include + +#define ERR_TIMER(errno) (CSI_DRV_ERRNO_TIMER_BASE | errno) + +#define TIMER_NULL_PARAM_CHK(para) HANDLE_PARAM_CHK(para, ERR_TIMER(DRV_ERROR_PARAMETER)) + +typedef struct +{ +#ifdef CONFIG_LPM + uint8_t timer_power_status; + uint32_t timer_regs_saved[2]; +#endif + uint8_t idx; + uint32_t base; + uint32_t irq; + timer_event_cb_t cb_event; + uint32_t timeout; ///< the set time (us) + uint32_t timeout_flag; +} dw_timer_priv_t; + +extern int32_t target_get_timer_count(void); +extern int32_t target_get_timer(int32_t idx, uint32_t *base, uint32_t *irq, void **handler); + +static dw_timer_priv_t timer_instance[CONFIG_TIMER_NUM]; +/** + \brief Make all the timers in the idle state. + \param[in] pointer to timer register base +*/ +static void timer_deactive_control(dw_timer_reg_t *addr) +{ + /* stop the corresponding timer */ + addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE; + /* Disable interrupt. */ + addr->TxControl |= DW_TIMER_TXCONTROL_INTMASK; +} + +void dw_timer_irqhandler(int idx) +{ + dw_timer_priv_t *timer_priv = &timer_instance[idx]; + timer_priv->timeout_flag = 1; + + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + addr->TxEOI; + + if (timer_priv->cb_event) + { + return timer_priv->cb_event(idx, TIMER_EVENT_TIMEOUT); + } + +} + +#ifdef CONFIG_LPM +static void manage_clock(timer_handle_t handle, uint8_t enable) +{ + if (handle == &timer_instance[0] || handle == &timer_instance[1]) + { + drv_clock_manager_config(CLOCK_MANAGER_TIM, enable); + } else if (handle == &timer_instance[3] || handle == &timer_instance[2]) + { + drv_clock_manager_config(CLOCK_MANAGER_TIM1, enable); + } +} + +static void do_prepare_sleep_action(timer_handle_t handle) +{ + dw_timer_priv_t *timer_priv = (dw_timer_priv_t *)handle; + uint32_t *tbase = (uint32_t *)(timer_priv->base); + registers_save(timer_priv->timer_regs_saved, tbase, 1); + registers_save(&timer_priv->timer_regs_saved[1], tbase + 2, 1); +} + +static void do_wakeup_sleep_action(timer_handle_t handle) +{ + dw_timer_priv_t *timer_priv = (dw_timer_priv_t *)handle; + uint32_t *tbase = (uint32_t *)(timer_priv->base); + registers_restore(tbase, timer_priv->timer_regs_saved, 1); + registers_restore(tbase + 2, &timer_priv->timer_regs_saved[1], 1); +} +#endif + +/** + \brief Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function + \param[in] idx instance timer index + \param[in] cb_event Pointer to \ref timer_event_cb_t + \return pointer to timer instance +*/ +timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event) +{ + if (idx < 0 || idx >= CONFIG_TIMER_NUM) + { + return NULL; + } + + uint32_t base = 0u; + uint32_t irq = 0u; + void *handler; + + int32_t real_idx = target_get_timer(idx, &base, &irq, &handler); + + if (real_idx != idx) + { + return NULL; + } + + dw_timer_priv_t *timer_priv = &timer_instance[idx]; + timer_priv->base = base; + timer_priv->irq = irq; + timer_priv->idx = idx; + + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + timer_priv->timeout = DW_TIMER_INIT_DEFAULT_VALUE; + +#ifdef CONFIG_LPM + csi_timer_power_control(timer_priv, DRV_POWER_FULL); +#endif + + timer_deactive_control(addr); + timer_priv->cb_event = cb_event; + + if (cb_event != NULL) + { + drv_irq_register(timer_priv->irq, handler); + drv_irq_enable(timer_priv->irq); + } + + return (timer_handle_t)timer_priv; +} + +/** + \brief De-initialize TIMER Interface. stops operation and releases the software resources used by the interface + \param[in] handle timer handle to operate. + \return error code +*/ +int32_t csi_timer_uninitialize(timer_handle_t handle) +{ + TIMER_NULL_PARAM_CHK(handle); + + dw_timer_priv_t *timer_priv = (dw_timer_priv_t *)handle; + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + timer_deactive_control(addr); + timer_priv->cb_event = NULL; + + drv_irq_disable(timer_priv->irq); + drv_irq_unregister(timer_priv->irq); + +#ifdef CONFIG_LPM + csi_timer_power_control(timer_priv, DRV_POWER_OFF); +#endif + + return 0; +} + +int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state) +{ + TIMER_NULL_PARAM_CHK(handle); +#ifdef CONFIG_LPM + power_cb_t callback = + { + .wakeup = do_wakeup_sleep_action, + .sleep = do_prepare_sleep_action, + .manage_clock = manage_clock + }; + return drv_soc_power_control(handle, state, &callback); +#else + return ERR_TIMER(DRV_ERROR_UNSUPPORTED); +#endif +} + +/** + \brief config timer mode. + \param[in] handle timer handle to operate. + \param[in] mode \ref timer_mode_e + \return error code +*/ +int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode) +{ + TIMER_NULL_PARAM_CHK(handle); + + dw_timer_priv_t *timer_priv = handle; + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + switch (mode) + { + case TIMER_MODE_FREE_RUNNING: + addr->TxControl &= ~DW_TIMER_TXCONTROL_MODE; + break; + + case TIMER_MODE_RELOAD: + addr->TxControl |= DW_TIMER_TXCONTROL_MODE; + break; + + default: + return ERR_TIMER(DRV_ERROR_PARAMETER); + } + + addr->TxControl |= (DW_TIMER_TXCONTROL_TRIGGER); + + return 0; +} + +/** + \brief Set timer. + \param[in] instance timer instance to operate. + \param[in] timeout the timeout value in microseconds(us). + \return error code +*/ +int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout) +{ + TIMER_NULL_PARAM_CHK(handle); + + dw_timer_priv_t *timer_priv = handle; + timer_priv->timeout = timeout; + return 0; +} + +/** + \brief Start timer. + \param[in] handle timer handle to operate. + \return error code +*/ + +int32_t csi_timer_start(timer_handle_t handle) +{ + TIMER_NULL_PARAM_CHK(handle); + + dw_timer_priv_t *timer_priv = handle; + + timer_priv->timeout_flag = 0; + + uint32_t min_us = drv_get_timer_freq(timer_priv->idx) / 1000000; + uint32_t load; + + if (((timer_priv->timeout * drv_get_timer_freq(timer_priv->idx)) / 1000000) > 0xffffffff) + { + return ERR_TIMER(DRV_ERROR_PARAMETER); + } + + if (min_us) + { + load = (uint32_t)(timer_priv->timeout * min_us); + } else + { + load = (uint32_t)(((uint64_t)(timer_priv->timeout) * drv_get_timer_freq(timer_priv->idx)) / 1000000); + } + + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + if (timer_priv->timeout == 0) { + addr->TxLoadCount = 0xffffffff; /* load time(us) */ + } else + { + if ((addr->TxControl | 0x2) == 0x2) { + addr->TxLoadCount = 0xffffffff; /* load time(us) */ + } else + { + addr->TxLoadCount = load; /* load time(us) */ + } + } + + addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE; /* disable the timer */ + addr->TxControl |= DW_TIMER_TXCONTROL_ENABLE; /* enable the corresponding timer */ + addr->TxControl &= ~DW_TIMER_TXCONTROL_INTMASK; /* enable interrupt */ + + /* avoid timer bug on yunvoice soc */ +#ifdef CONFIG_CHIP_YUNVOICE + + if (addr->TxCurrentValue > addr->TxLoadCount) { + addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE; /* disable the timer */ + addr->TxControl |= DW_TIMER_TXCONTROL_ENABLE; /* enable the corresponding timer */ + addr->TxControl &= ~DW_TIMER_TXCONTROL_INTMASK; /* enable interrupt */ + } + +#endif + + return 0; +} + +/** + \brief Stop timer. + \param[in] handle timer handle to operate. + \return error code +*/ +int32_t csi_timer_stop(timer_handle_t handle) +{ + TIMER_NULL_PARAM_CHK(handle); + + dw_timer_priv_t *timer_priv = handle; + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + addr->TxControl |= DW_TIMER_TXCONTROL_INTMASK; /* enable interrupt */ + addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE; /* disable the timer */ + + return 0; +} + +/** + \brief suspend timer. + \param[in] instance timer instance to operate. + \return error code +*/ +int32_t csi_timer_suspend(timer_handle_t handle) +{ + TIMER_NULL_PARAM_CHK(handle); + + return ERR_TIMER(DRV_ERROR_UNSUPPORTED); +} + +/** + \brief resume timer. + \param[in] handle timer handle to operate. + \return error code +*/ +int32_t csi_timer_resume(timer_handle_t handle) +{ + TIMER_NULL_PARAM_CHK(handle); + + dw_timer_priv_t *timer_priv = handle; + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + addr->TxControl &= ~DW_TIMER_TXCONTROL_ENABLE; /* stop the corresponding timer */ + addr->TxControl &= DW_TIMER_TXCONTROL_ENABLE; /* restart the corresponding timer */ + + return 0; +} + +/** + \brief get timer current value + \param[in] handle timer handle to operate. + \param[out] value timer current value + \return error code +*/ +int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value) +{ + TIMER_NULL_PARAM_CHK(handle); + TIMER_NULL_PARAM_CHK(value); + + dw_timer_priv_t *timer_priv = handle; + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + *value = addr->TxCurrentValue; + return 0; +} + +/** + \brief Get TIMER status. + \param[in] handle timer handle to operate. + \return TIMER status \ref timer_status_t +*/ +timer_status_t csi_timer_get_status(timer_handle_t handle) +{ + timer_status_t timer_status = {0}; + + if (handle == NULL) + { + return timer_status; + } + + dw_timer_priv_t *timer_priv = handle; + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + if (addr->TxControl & DW_TIMER_TXCONTROL_ENABLE) + { + timer_status.active = 1; + } + + if (timer_priv->timeout_flag == 1) + { + timer_status.timeout = 1; + } + + return timer_status; +} + +/** + \brief get timer reload value + \param[in] handle timer handle to operate. + \param[out] value timer reload value + \return error code +*/ +int32_t csi_timer_get_load_value(timer_handle_t handle, uint32_t *value) +{ + TIMER_NULL_PARAM_CHK(handle); + TIMER_NULL_PARAM_CHK(value); + + dw_timer_priv_t *timer_priv = handle; + dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base); + + *value = addr->TxLoadCount; + return 0; +} + diff --git a/bsp/thead-smart/drivers/dw_timer.h b/bsp/thead-smart/drivers/dw_timer.h new file mode 100644 index 0000000000..7b418cac70 --- /dev/null +++ b/bsp/thead-smart/drivers/dw_timer.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header file for timer driver + */ + +#ifndef __DW_TIMER_H +#define __DW_TIMER_H + +#include +#include "soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * define the bits for TxControl + */ +#define DW_TIMER_TXCONTROL_ENABLE (1UL << 0) +#define DW_TIMER_TXCONTROL_MODE (1UL << 1) +#define DW_TIMER_TXCONTROL_INTMASK (1UL << 2) +#define DW_TIMER_TXCONTROL_TRIGGER (1UL << 4) + +#define DW_TIMER_INIT_DEFAULT_VALUE (0xffffffff / drv_get_timer_freq(0) * 1000000) + +typedef struct +{ + __IOM uint32_t TxLoadCount; /* Offset: 0x000 (R/W) Receive buffer register */ + __IM uint32_t TxCurrentValue; /* Offset: 0x004 (R) Transmission hold register */ + __IOM uint8_t TxControl: 5; /* Offset: 0x008 (R/W) Clock frequency division low section register */ + uint8_t RESERVED0[3]; + __IM uint8_t TxEOI: 1; /* Offset: 0x00c (R) Clock frequency division high section register */ + uint8_t RESERVED1[3]; + __IM uint8_t TxIntStatus: 1; /* Offset: 0x010 (R) Interrupt enable register */ + uint8_t RESERVED2[3]; +} dw_timer_reg_t; + +#ifdef __cplusplus +} +#endif + +#endif /* __DW_TIMER_H */ + diff --git a/bsp/thead-smart/drivers/isr.c b/bsp/thead-smart/drivers/isr.c new file mode 100644 index 0000000000..1a42a81bcf --- /dev/null +++ b/bsp/thead-smart/drivers/isr.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen source file for the interrupt server route + */ + +#include +#include +#include "soc.h" + +#ifndef CONFIG_SYSTICK_HZ +#define CONFIG_SYSTICK_HZ 100 +#endif + +extern volatile uint32_t rt_thread_switch_interrupt_flag; + +extern void ck_usart_irqhandler(int32_t idx); +extern void dw_timer_irqhandler(int32_t idx); +extern void dw_gpio_irqhandler(int32_t idx); +extern void systick_handler(void); +extern void xPortSysTickHandler(void); +extern void OSTimeTick(void); + +#define ATTRIBUTE_ISR + +#define readl(addr) \ + ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) + + +#if(CONFIG_KERNEL_RTTHREAD == 1) +#define CSI_INTRPT_ENTER() rt_interrupt_enter() +#define CSI_INTRPT_EXIT() rt_interrupt_leave() +#endif + + +void __attribute__((isr)) SysTick_Handler(void) +{ +#if(CONFIG_KERNEL_RTTHREAD == 1) + CSI_INTRPT_ENTER(); +#endif + + csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, CORET_IRQn); + +#if defined(CONFIG_KERNEL_RHINO) + systick_handler(); +#elif defined(CONFIG_KERNEL_FREERTOS) + xPortSysTickHandler(); +#elif defined(CONFIG_KERNEL_RTTHREAD) + rt_tick_increase(); +#elif defined(CONFIG_KERNEL_UCOS) + OSTimeTick(); +#endif + +#if(CONFIG_KERNEL_RTTHREAD == 1) + CSI_INTRPT_EXIT(); +#endif +} + +ATTRIBUTE_ISR void USART_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + ck_usart0_irqhandler(); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void TIM0_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(0); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void TIM1_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(1); + CSI_INTRPT_EXIT(); +} +ATTRIBUTE_ISR void TIM2_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(2); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void TIM3_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(3); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void TIM4_NMIHandler(void) +{ + dw_timer_irqhandler(4); +} + +ATTRIBUTE_ISR void TIM6_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(6); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void TIM7_IRQHandler(void) +{ + dw_timer_irqhandler(7); +} + +ATTRIBUTE_ISR void TIM8_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(8); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void TIM9_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(9); + CSI_INTRPT_EXIT(); +} +ATTRIBUTE_ISR void TIM10_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(10); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void TIM11_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_timer_irqhandler(11); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void GPIO0_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_gpio_irqhandler(0); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void GPIO1_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_gpio_irqhandler(1); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void GPIO2_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_gpio_irqhandler(2); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void GPIO3_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_gpio_irqhandler(3); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void GPIO4_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_gpio_irqhandler(4); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void GPIO5_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_gpio_irqhandler(5); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void GPIO6_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_gpio_irqhandler(6); + CSI_INTRPT_EXIT(); +} + +ATTRIBUTE_ISR void GPIO7_IRQHandler(void) +{ + CSI_INTRPT_ENTER(); + dw_gpio_irqhandler(7); + CSI_INTRPT_EXIT(); +} diff --git a/bsp/thead-smart/drivers/novic_irq_tbl.c b/bsp/thead-smart/drivers/novic_irq_tbl.c new file mode 100644 index 0000000000..cadfac5f98 --- /dev/null +++ b/bsp/thead-smart/drivers/novic_irq_tbl.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen novic table init + */ + +#include +#include + +extern void Default_Handler(void); +extern void SysTick_Handler(void); +extern void TIM4_NMIHandler(void); + +void (*g_irqvector[48])(void); +void (*g_nmivector)(void); + +void irq_vectors_init(void) +{ + int i; + + for (i = 0; i < 48; i++) + { + g_irqvector[i] = Default_Handler; + } + + g_irqvector[CORET_IRQn] = SysTick_Handler; + g_nmivector = TIM4_NMIHandler; +} diff --git a/bsp/thead-smart/drivers/pin_name.h b/bsp/thead-smart/drivers/pin_name.h new file mode 100644 index 0000000000..78aa4bc18a --- /dev/null +++ b/bsp/thead-smart/drivers/pin_name.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header file for the pin_name + */ + +#ifndef _PINNAMES_H +#define _PINNAMES_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef enum +{ + PA0 = 0, + PA1, + PA2, + PA3, + PA4, + PA5, + PA6, + PA7, + PAD_UART0_SIN, + PAD_UART0_SOUT +} +pin_name_e; + +typedef enum +{ + PORTA = 0, + PORTB = 1, + PORTC = 2, + PORTD = 3, + PORTE = 4, + PORTF = 5, + PORTG = 6, + PORTH = 7 +} port_name_e; + +typedef enum +{ + NONE = 0 +} pin_func_e; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/thead-smart/drivers/soc.h b/bsp/thead-smart/drivers/soc.h new file mode 100644 index 0000000000..656e944995 --- /dev/null +++ b/bsp/thead-smart/drivers/soc.h @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen CSI Core Peripheral Access Layer Header File for + * CSKYSOC Device Series + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef IHS_VALUE +#define IHS_VALUE (20000000) +#endif + +#ifndef EHS_VALUE +#define EHS_VALUE (20000000) +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ +typedef enum IRQn { + NMI_EXPn = -2, /* NMI Exception */ + /* ---------------------- SmartL Specific Interrupt Numbers --------------------- */ + Machine_Software_IRQn = 3, /* Machine software interrupt */ + User_Timer_IRQn = 4, /* User timer interrupt */ + Supervisor_Timer_IRQn = 5, /* Supervisor timer interrupt */ + CORET_IRQn = 7, /* core Timer Interrupt */ + Machine_External_IRQn = 11, /* Machine external interrupt */ + UART_IRQn = 16, /* uart Interrupt */ + TIM0_IRQn = 18, /* timer0 Interrupt */ + TIM1_IRQn = 19, /* timer1 Interrupt */ + TIM2_IRQn = 20, /* timer2 Interrupt */ + TIM3_IRQn = 21, /* timer3 Interrupt */ + GPIO0_IRQn = 23, /* gpio0 Interrupt */ + GPIO1_IRQn = 24, /* gpio1 Interrupt */ + GPIO2_IRQn = 25, /* gpio2 Interrupt */ + GPIO3_IRQn = 26, /* gpio3 Interrupt */ + GPIO4_IRQn = 27, /* gpio4 Interrupt */ + GPIO5_IRQn = 28, /* gpio5 Interrupt */ + GPIO6_IRQn = 29, /* gpio6 Interrupt */ + GPIO7_IRQn = 30, /* gpio7 Interrupt */ + STIM0_IRQn = 31, /* stimer0 Interrupt */ + STIM1_IRQn = 32, /* stimer1 Interrupt */ + STIM2_IRQn = 33, /* stimer2 Interrupt */ + STIM3_IRQn = 34, /* stimer3 Interrupt */ + PAD_IRQn = 35, /* pad Interrupt */ + TIM6_IRQn = 36, /* timer6 Interrupt */ + TIM7_IRQn = 37, /* timer7 Interrupt */ + TIM8_IRQn = 38, /* timer8 Interrupt */ + TIM9_IRQn = 39, /* timer9 Interrupt */ + TIM10_IRQn = 40, /* timer10 Interrupt */ + TIM11_IRQn = 41, /* timer11 Interrupt */ +} +IRQn_Type; + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +#define CONFIG_TIMER_NUM 12 +#define CONFIG_USART_NUM 1 +#define CONFIG_GPIO_NUM 8 +#define CONFIG_GPIO_PIN_NUM 8 + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ +/* -------------------------- CPU FPGA memory map ------------------------------- */ +#define CSKY_SRAM_BASE (0x20000000UL) + +#define CSKY_UART_BASE (0x40015000UL) +#define CSKY_PMU_BASE (0x40016000UL) +#define CSKY_TIMER0_BASE (0x40011000UL) +#define CSKY_TIMER1_BASE (0x40011014UL) +#define CSKY_TIMER2_BASE (0x40011028UL) +#define CSKY_TIMER3_BASE (0x4001103cUL) +#define CSKY_TIMER4_BASE (0x40021000UL) +#define CSKY_TIMER5_BASE (0x40021014UL) +#define CSKY_TIMER6_BASE (0x40021028UL) +#define CSKY_TIMER7_BASE (0x4002103cUL) +#define CSKY_TIMER8_BASE (0x40031000UL) +#define CSKY_TIMER9_BASE (0x40031014UL) +#define CSKY_TIMER10_BASE (0x40031028UL) +#define CSKY_TIMER11_BASE (0x4003103cUL) + +#define CSKY_TIMER_CONTROL_BASE (0x400110a0UL) +#define CSKY_CLK_GEN_BASE (0x40017000UL) +#define CSKY_STIMER0_BASE (0x40018000UL) +#define CSKY_STIMER1_BASE (0x40018014UL) +#define CSKY_STIMER2_BASE (0x40018028UL) +#define CSKY_STIMER3_BASE (0x4001803cUL) +#define CSKY_STIMER_CONTROL_BASE (0x400110a0UL) + +#define CSKY_GPIOA_BASE (0x40019000UL) +#define CSKY_GPIOA_CONTROL_BASE (0x40019030UL) +#define CSKY_SMPU_BASE (0x4001a000UL) + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ +#define CSKY_UART (( CSKY_UART_TypeDef *) CSKY_UART_BASE) + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_H_ */ diff --git a/bsp/thead-smart/drivers/startup_gcc.S b/bsp/thead-smart/drivers/startup_gcc.S new file mode 100644 index 0000000000..f71164c599 --- /dev/null +++ b/bsp/thead-smart/drivers/startup_gcc.S @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen startup file. Should use with + * GCC for T-HEAD Embedded Processors + */ + +#include + + +.section .vectors, "aw", @progbits + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long PendSV_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_IRQHandler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + + /* External interrupts */ + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + + .text + .align 2 +_start: + .text + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +.option push +.option norelax + la gp, __global_pointer$ +.option pop + la a0, Default_Handler + ori a0, a0, 3 + csrw mtvec, a0 + la a0, __Vectors + csrw mtvt, a0 + la sp, __StackTop + csrw mscratch, sp + + /* Load data section */ + la a0, __erodata + la a1, __data_start__ + la a2, __data_end__ + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + + /* Clear bss section */ + la a0, __bss_start__ + la a1, __bss_end__ + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + +#ifndef __NO_SYSTEM_INIT + jal SystemInit +#endif + + jal entry + + .size Reset_Handler, . - Reset_Handler + +__exit: + j __exit + +.section .bss + + .align 3 + .global g_base_irqstack + .global g_top_irqstack +g_base_irqstack: + .space CONFIG_ARCH_INTERRUPTSTACK +g_top_irqstack: diff --git a/bsp/thead-smart/drivers/sys_freq.c b/bsp/thead-smart/drivers/sys_freq.c new file mode 100644 index 0000000000..7a3341d506 --- /dev/null +++ b/bsp/thead-smart/drivers/sys_freq.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen setting system frequency + */ + + +#include +#include +#include + +extern int g_system_clock; + +int32_t drv_get_cpu_freq(int32_t idx) +{ + return g_system_clock; +} + +int32_t drv_get_usi_freq(int32_t idx) +{ + return g_system_clock; +} + +int32_t drv_get_usart_freq(int32_t idx) +{ + return g_system_clock; +} + +int32_t drv_get_pwm_freq(int32_t idx) +{ + return g_system_clock; +} + +int32_t drv_get_i2s_freq(int32_t idx) +{ + return g_system_clock; +} + +int32_t drv_get_sys_freq(void) +{ + return g_system_clock; +} + +int32_t drv_get_rtc_freq(int32_t idx) +{ + return g_system_clock; +} + +int32_t drv_get_apb_freq(void) +{ + return g_system_clock; +} + +int32_t drv_get_timer_freq(int32_t idx) +{ + return g_system_clock; +} diff --git a/bsp/thead-smart/drivers/sys_freq.h b/bsp/thead-smart/drivers/sys_freq.h new file mode 100644 index 0000000000..5bf2086833 --- /dev/null +++ b/bsp/thead-smart/drivers/sys_freq.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen header file for setting system frequency + */ + +#ifndef _SYS_FREQ_H_ +#define _SYS_FREQ_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t drv_get_i2s_freq(int32_t idx); +int32_t drv_get_pwm_freq(int32_t idx); +int32_t drv_get_usart_freq(int32_t idx); +int32_t drv_get_usi_freq(int32_t idx); +int32_t drv_get_sys_freq(void); +int32_t drv_get_apb_freq(void); +int32_t drv_get_rtc_freq(int32_t idx); +int32_t drv_get_timer_freq(int32_t idx); + +int32_t drv_get_cpu_freq(int32_t idx); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_FREQ_H_ */ + diff --git a/bsp/thead-smart/drivers/system.c b/bsp/thead-smart/drivers/system.c new file mode 100644 index 0000000000..31a05f1afa --- /dev/null +++ b/bsp/thead-smart/drivers/system.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen CSI Device System Source File + */ + +#include +#include +#include +#include + +#ifndef CONFIG_SYSTICK_HZ +#define CONFIG_SYSTICK_HZ 100 +#endif + +int g_system_clock = IHS_VALUE; +extern int32_t g_top_irqstack; +extern void irq_vectors_init(void); +extern void mm_heap_initialize(void); + +int SystemCoreClock = IHS_VALUE; /* System Core Clock Frequency */ +extern int __Vectors; + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = IHS_VALUE; +} + + +static void _system_init_for_kernel(void) +{ + irq_vectors_init(); + + csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, CORET_IRQn); //10ms + drv_irq_enable(CORET_IRQn); +} + +/** + * @brief initialize the system + * Initialize the psr and vbr. + * @param None + * @return None + */ +void SystemInit(void) +{ + int i; + /* enable mstatus FS */ +#if ((CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1)) + uint32_t mstatus = __get_MSTATUS(); + mstatus |= (1 << 13); + __set_MSTATUS(mstatus); +#endif + + /* enable mxstatus THEADISAEE */ + uint32_t mxstatus = __get_MXSTATUS(); + mxstatus |= (1 << 22); + /* enable mxstatus MM */ +#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1)) + mxstatus |= (1 << 15); +#endif + __set_MXSTATUS(mxstatus); + + + /* get interrupt level from info */ + CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); + + for (i = 0; i < 64; i++) + { + CLIC->CLICINT[i].IP = 0; + CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ + } + + /* tspend use positive interrupt */ + CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; + + csi_dcache_enable(); + csi_icache_enable(); + drv_irq_enable(Machine_Software_IRQn); + + _system_init_for_kernel(); +} diff --git a/bsp/thead-smart/drivers/trap_c.c b/bsp/thead-smart/drivers/trap_c.c new file mode 100644 index 0000000000..b236714100 --- /dev/null +++ b/bsp/thead-smart/drivers/trap_c.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen source file for the trap process + */ + +#include +#include +#include +#include +#include + +void (*trap_c_callback)(void); + +void trap_c(uint32_t *regs) +{ + int i; + uint32_t vec = 0; + + vec = __get_MCAUSE() & 0x3FF; + + printf("CPU Exception: NO.%d", vec); + printf("\n"); + + for (i = 0; i < 31; i++) + { + printf("x%d: %08x\t", i + 1, regs[i]); + + if ((i % 4) == 3) + { + printf("\n"); + } + } + + printf("\n"); + printf("mepc : %08x\n", regs[31]); + printf("mstatus: %08x\n", regs[32]); + + if (trap_c_callback) + { + trap_c_callback(); + } + + while (1); +} + diff --git a/bsp/thead-smart/drivers/vectors.S b/bsp/thead-smart/drivers/vectors.S new file mode 100644 index 0000000000..3bfa3c70b7 --- /dev/null +++ b/bsp/thead-smart/drivers/vectors.S @@ -0,0 +1,349 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen define default vector handlers. + */ + + +#include + +/* Enable interrupts when returning from the handler */ +#define MSTATUS_PRV1 0x1880 + +.section .bss + .align 2 + .globl g_trapstackalloc + .global g_trapstackbase + .global g_top_trapstack +g_trapstackalloc: +g_trapstackbase: + .space 768 +g_top_trapstack: + + .align 2 + .globl g_trap_sp + .type g_trap_sp, object +g_trap_sp: + .long 0 + .size g_trap_sp, .-g_trap_sp + +irq_nested_level: +.long 0 +#ifdef ARCH_RISCV_FPU +irq_mstatus_fs_flag: +.long 0 +#endif + +.text + + .align 2 + .global Default_IRQHandler + .weak Default_IRQHandler + .type Default_IRQHandler, %function +Default_IRQHandler: + ipush + +#ifdef ARCH_RISCV_FPU + csrr t1, mstatus + srli t1, t1, 13 + andi t1, t1, 0x3 + la t3, irq_mstatus_fs_flag + sw t1, (t3) + li t0, 0x3 + bne t1, t0, .F_RegNotSave1 + + addi sp, sp, -(20 * FREGBYTES) + + FSTORE ft0, 0 * FREGBYTES(sp) + FSTORE ft1, 1 * FREGBYTES(sp) + FSTORE ft2, 2 * FREGBYTES(sp) + FSTORE ft3, 3 * FREGBYTES(sp) + FSTORE ft4, 4 * FREGBYTES(sp) + FSTORE ft5, 5 * FREGBYTES(sp) + FSTORE ft6, 6 * FREGBYTES(sp) + FSTORE ft7, 7 * FREGBYTES(sp) + FSTORE fa0, 8 * FREGBYTES(sp) + FSTORE fa1, 9 * FREGBYTES(sp) + FSTORE fa2, 10 * FREGBYTES(sp) + FSTORE fa3, 11 * FREGBYTES(sp) + FSTORE fa4, 12 * FREGBYTES(sp) + FSTORE fa5, 13 * FREGBYTES(sp) + FSTORE fa6, 14 * FREGBYTES(sp) + FSTORE fa7, 15 * FREGBYTES(sp) + FSTORE ft8, 16 * FREGBYTES(sp) + FSTORE ft9, 17 * FREGBYTES(sp) + FSTORE ft10, 18 * FREGBYTES(sp) + FSTORE ft11, 19 * FREGBYTES(sp) +.F_RegNotSave1: +#endif + + csrr t1, mcause + andi t1, t1, 0x3FF + slli t1, t1, 2 + la t0, g_irqvector + add t0, t0, t1 + lw t2, (t0) + jalr t2 + + li t0, MSTATUS_PRV1 + csrs mstatus, t0 + +#ifdef ARCH_RISCV_FPU + la t0, irq_mstatus_fs_flag + lw t1, (t0) + li t0, 0x3 + bne t1, t0, .F_RegNotLoad + + FLOAD ft0, 0 * FREGBYTES(sp) + FLOAD ft1, 1 * FREGBYTES(sp) + FLOAD ft2, 2 * FREGBYTES(sp) + FLOAD ft3, 3 * FREGBYTES(sp) + FLOAD ft4, 4 * FREGBYTES(sp) + FLOAD ft5, 5 * FREGBYTES(sp) + FLOAD ft6, 6 * FREGBYTES(sp) + FLOAD ft7, 7 * FREGBYTES(sp) + FLOAD fa0, 8 * FREGBYTES(sp) + FLOAD fa1, 9 * FREGBYTES(sp) + FLOAD fa2, 10 * FREGBYTES(sp) + FLOAD fa3, 11 * FREGBYTES(sp) + FLOAD fa4, 12 * FREGBYTES(sp) + FLOAD fa5, 13 * FREGBYTES(sp) + FLOAD fa6, 14 * FREGBYTES(sp) + FLOAD fa7, 15 * FREGBYTES(sp) + FLOAD ft8, 16 * FREGBYTES(sp) + FLOAD ft9, 17 * FREGBYTES(sp) + FLOAD ft10,18 * FREGBYTES(sp) + FLOAD ft11,19 * FREGBYTES(sp) + + addi sp, sp, (20 * FREGBYTES) +.F_RegNotLoad: +#endif + ipop + + +/****************************************************************************** + * Functions: + * void trap(void); + * default exception handler + ******************************************************************************/ + .align 2 + .global trap + .type trap, %function +trap: + /* Check for interrupt */ + addi sp, sp, -4 + sw t0, 0x0(sp) + csrr t0, mcause + blt t0, x0, .Lirq + addi sp, sp, 4 + la t0, g_trap_sp + + addi t0, t0, -132 + + sw x1, 0(t0) + sw x2, 4(t0) + sw x3, 8(t0) + sw x4, 12(t0) + sw x6, 20(t0) + sw x7, 24(t0) + sw x8, 28(t0) + sw x9, 32(t0) + sw x10, 36(t0) + sw x11, 40(t0) + sw x12, 44(t0) + sw x13, 48(t0) + sw x14, 52(t0) + sw x15, 56(t0) + sw x16, 60(t0) + sw x17, 64(t0) + sw x18, 68(t0) + sw x19, 72(t0) + sw x20, 76(t0) + sw x21, 80(t0) + sw x22, 84(t0) + sw x23, 88(t0) + sw x24, 92(t0) + sw x25, 96(t0) + sw x26, 100(t0) + sw x27, 104(t0) + sw x28, 108(t0) + sw x29, 112(t0) + sw x30, 116(t0) + sw x31, 120(t0) + + csrr a0, mepc + sw a0, 124(t0) + csrr a0, mstatus + sw a0, 128(t0) + + mv a0, t0 + lw t0, -4(sp) + mv sp, a0 + sw t0, 16(sp) + + jal trap_c + + +.Lirq: + lw t0, 0x0(sp) + addi sp, sp, 4 + j Default_IRQHandler + + .align 6 + .weak Default_Handler + .global Default_Handler + .type Default_Handler, %function +Default_Handler: + /* Check for nmi */ + addi sp, sp, -8 + sw t0, 0x0(sp) + sw t1, 0x4(sp) + csrr t0, mcause + andi t0, t0, 0x3FF + li t1, 24 + beq t0, t1, .NMI_Handler + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 + j trap + +.NMI_Handler: + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 + + addi sp, sp, -64 + + sw ra, 0(sp) + sw t0, 4(sp) + sw t1, 8(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#ifdef ARCH_RISCV_FPU + addi sp, sp, -(20*FREGBYTES) + FSTORE ft0, 0 * FREGBYTES(sp) + FSTORE ft1, 1 * FREGBYTES(sp) + FSTORE ft2, 2 * FREGBYTES(sp) + FSTORE ft3, 3 * FREGBYTES(sp) + FSTORE ft4, 4 * FREGBYTES(sp) + FSTORE ft5, 5 * FREGBYTES(sp) + FSTORE ft6, 6 * FREGBYTES(sp) + FSTORE ft7, 7 * FREGBYTES(sp) + FSTORE fa0, 8 * FREGBYTES(sp) + FSTORE fa1, 9 * FREGBYTES(sp) + FSTORE fa2, 10 * FREGBYTES(sp) + FSTORE fa3, 11 * FREGBYTES(sp) + FSTORE fa4, 12 * FREGBYTES(sp) + FSTORE fa5, 13 * FREGBYTES(sp) + FSTORE fa6, 14 * FREGBYTES(sp) + FSTORE fa7, 15 * FREGBYTES(sp) + FSTORE ft8, 16 * FREGBYTES(sp) + FSTORE ft9, 17 * FREGBYTES(sp) + FSTORE ft10, 18 * FREGBYTES(sp) + FSTORE ft11, 19 * FREGBYTES(sp) +#endif + + la t0, g_nmivector + lw t0, (t0) + jalr t0 + +#ifdef ARCH_RISCV_FPU + FLOAD ft0, 0 * FREGBYTES(sp) + FLOAD ft1, 1 * FREGBYTES(sp) + FLOAD ft2, 2 * FREGBYTES(sp) + FLOAD ft3, 3 * FREGBYTES(sp) + FLOAD ft4, 4 * FREGBYTES(sp) + FLOAD ft5, 5 * FREGBYTES(sp) + FLOAD ft6, 6 * FREGBYTES(sp) + FLOAD ft7, 7 * FREGBYTES(sp) + FLOAD fa0, 8 * FREGBYTES(sp) + FLOAD fa1, 9 * FREGBYTES(sp) + FLOAD fa2, 10 * FREGBYTES(sp) + FLOAD fa3, 11 * FREGBYTES(sp) + FLOAD fa4, 12 * FREGBYTES(sp) + FLOAD fa5, 13 * FREGBYTES(sp) + FLOAD fa6, 14 * FREGBYTES(sp) + FLOAD fa7, 15 * FREGBYTES(sp) + FLOAD ft8, 16 * FREGBYTES(sp) + FLOAD ft9, 17 * FREGBYTES(sp) + FLOAD ft10, 18 * FREGBYTES(sp) + FLOAD ft11, 19 * FREGBYTES(sp) + + addi sp, sp, (20 * FREGBYTES) +#endif + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 64 + mret + + + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .globl \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler STIM0_IRQHandler + def_irq_handler STIM1_IRQHandler + def_irq_handler STIM2_IRQHandler + def_irq_handler STIM3_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM1_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler TIM3_IRQHandler + def_irq_handler USART_IRQHandler + def_irq_handler GPIO0_IRQHandler + def_irq_handler GPIO1_IRQHandler + def_irq_handler GPIO2_IRQHandler + def_irq_handler GPIO3_IRQHandler + def_irq_handler GPIO4_IRQHandler + def_irq_handler GPIO5_IRQHandler + def_irq_handler GPIO6_IRQHandler + def_irq_handler GPIO7_IRQHandler + def_irq_handler PAD_IRQHandler + def_irq_handler TIM6_IRQHandler + def_irq_handler TIM7_IRQHandler + def_irq_handler TIM8_IRQHandler + def_irq_handler TIM9_IRQHandler + def_irq_handler TIM10_IRQHandler + def_irq_handler TIM11_IRQHandler + diff --git a/bsp/thead-smart/gcc_csky.ld b/bsp/thead-smart/gcc_csky.ld new file mode 100644 index 0000000000..a0303d19eb --- /dev/null +++ b/bsp/thead-smart/gcc_csky.ld @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file gcc_csky.h + * @brief csky linker file for PHOBOS + * @version V1.0 + * @date 02. June 2017 + ******************************************************************************/ +MEMORY +{ + I-SRAM : ORIGIN = 0x0 , LENGTH = 0x40000 /* I-SRAM 256KB */ + D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0xc0000 /* D-SRAM 768KB */ + O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000 /* off-chip SRAM 8MB */ + SRAM : ORIGIN = 0x60000000 , LENGTH = 0x20000 /* on-chip SRAM 128KB */ +} + +PROVIDE (__StackTop = 0x200c0000 - 0x8); +PROVIDE (Stack_Size = 0x1000); + +REGION_ALIAS("REGION_TEXT", I-SRAM); +REGION_ALIAS("REGION_RODATA", I-SRAM); +REGION_ALIAS("REGION_CUSTOM1", D-SRAM); +REGION_ALIAS("REGION_CUSTOM2", D-SRAM); +REGION_ALIAS("REGION_DATA", D-SRAM); +REGION_ALIAS("REGION_BSS", D-SRAM); + +ENTRY(Reset_Handler) +SECTIONS +{ + .text : AT(ADDR(.text)){ + . = ALIGN(0x4) ; + __stext = . ; + KEEP(*startup.o(*.text*)) + *(.text) + *(.text*) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.gnu.linkonce.t*) + *(.glue_7t) + *(.glue_7) + *(.jcr) + *(.init) + *(.fini) + . = ALIGN (4) ; + PROVIDE(__ctbp = .); + *(.call_table_data) + *(.call_table_text) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + . = ALIGN(0x10) ; + __etext = . ; + } > REGION_TEXT + .eh_frame_hdr : { + *(.eh_frame_hdr) + } > REGION_TEXT + .eh_frame : ONLY_IF_RO { + KEEP (*(.eh_frame)) + } > REGION_TEXT + .gcc_except_table : ONLY_IF_RO { + *(.gcc_except_table .gcc_except_table.*) + } > REGION_TEXT + .rodata :{ + . = ALIGN(0x4) ; + __srodata = .; + *(.rdata) + *(.rdata*) + *(.rdata1) + *(.rdata.*) + *(.rodata) + *(.rodata1) + *(.rodata*) + *(.rodata.*) + *(.rodata.str1.4) + . = ALIGN(0x4) ; + __ctor_start__ = .; + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __ctor_end__ = .; + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __dtor_end__ = .; + . = ALIGN(0x4) ; + __erodata = .; + __rodata_end__ = .; + } > REGION_RODATA + .data : { + . = ALIGN(0x4) ; + __sdata = . ; + __data_start__ = . ; + data_start = . ; + KEEP(*startup.o(*.vectors*)) + *(.got.plt) + *(.got) + *(.gnu.linkonce.r*) + *(.data) + *(.data*) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + *(.data1) + *(.gcc_except_table) + *(.gcc_except_table*) + __start_init_call = .; + *(.initcall.init) + __stop_init_call = .; + __start_cmd = .; + *(.bootloaddata.cmd) + . = ALIGN(4) ; + __stop_cmd = .; + __global_pointer$ = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(__libc_atexit) + *(__libc_subinit) + *(__libc_subfreeres) + *(.note.ABI-tag) + __edata = .; + __data_end__ = .; + . = ALIGN(0x4) ; + + } > REGION_DATA AT > REGION_RODATA + .eh_frame : ONLY_IF_RW { + KEEP (*(.eh_frame)) + } > REGION_DATA AT > REGION_RODATA + .gcc_except_table : ONLY_IF_RW { + *(.gcc_except_table .gcc_except_table.*) + __edata = .; + __data_end__ = .; + } > REGION_DATA AT > REGION_RODATA + + + .bss : { + . = ALIGN(0x4) ; + __sbss = ALIGN(0x4) ; + __bss_start__ = . ; + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.scommon) + *(.dynbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(0x4) ; + __ebss = . ; + __end = . ; + end = . ; + __bss_end__ = .; + } > REGION_BSS + /* End of uninitalized data segement */ + PROVIDE(end = .); +} diff --git a/bsp/thead-smart/rtconfig.h b/bsp/thead-smart/rtconfig.h new file mode 100644 index 0000000000..12e38cb703 --- /dev/null +++ b/bsp/thead-smart/rtconfig.h @@ -0,0 +1,158 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40003 + +/* RT-Thread CPU arch and features */ + + +/* risc-v arch */ + +#define ARCH_RISCV +#define ARCH_RISCV_32 +#define ARCH_RISCV_FPU +#define ARCH_RISCV_FPU_S + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 1 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 2048 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_THEAD_SMART +#define RT_USING_UART1 + +#endif diff --git a/bsp/thead-smart/rtconfig.py b/bsp/thead-smart/rtconfig.py new file mode 100644 index 0000000000..be45bc8e84 --- /dev/null +++ b/bsp/thead-smart/rtconfig.py @@ -0,0 +1,68 @@ +import os + +# toolchains options +ARCH ='risc-v' +CPU ='e906' +CPUNAME ='e906f' +VENDOR ='t-head' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/home/xinge/tools/riscv64-elf-x86_64-20200616-1.9.6/bin' +else: + print 'Please make sure your toolchains is GNU GCC!' + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +# BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'riscv64-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'g++' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + if CPUNAME == 'e906fd': + DEVICE = ' -march=rv32imafdcxthead -mabi=ilp32d' + if CPUNAME == 'e906f': + DEVICE = ' -march=rv32imafcxthead -mabi=ilp32f' + if CPUNAME == 'e906': + DEVICE = ' -march=rv32imacxthead -mabi=ilp32' + + CFLAGS = DEVICE + ' -c -g -ffunction-sections -fdata-sections -Wall -mcmodel=medlow' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--no-whole-archive -T gcc_csky.ld -lm -lc -lgcc -Wl,-gc-sections -Wl,-zmax-page-size=1024' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2 -g2' + + CXXFLAGS = CFLAGS + +# M_CFLAGS = DEVICE + ' -EL -G0 -O2 -mno-abicalls -fno-common -fno-exceptions -fno-omit-frame-pointer -mlong-calls -fno-pic ' + # M_CXXFLAGS = M_CFLAGS + # M_LFLAGS = DEVICE + ' -EL -r -Wl,--gc-sections,-z,max-page-size=0x4' +\ + # ' -nostartfiles -static-libgcc' + # M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index 024cc5ba44..5055b533e6 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -10,10 +10,17 @@ group = [] list = os.listdir(cwd) # add common code files -if rtconfig.CPU != "nuclei": - group = group + SConscript(os.path.join('common', 'SConscript')) +if rtconfig.VENDOR == "t-head" : + group = group +elif rtconfig.CPU == "nuclei" : + group = group +else : + group = group + SConscript(os.path.join(cwd, 'common', 'SConscript')) # cpu porting code files -group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) +if rtconfig.VENDOR == "t-head" : + group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript')) +else : + group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript')) Return('group') diff --git a/libcpu/risc-v/t-head/e906/SConscript b/libcpu/risc-v/t-head/e906/SConscript new file mode 100644 index 0000000000..2f698f530a --- /dev/null +++ b/libcpu/risc-v/t-head/e906/SConscript @@ -0,0 +1,12 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/t-head/e906/context_gcc.S b/libcpu/risc-v/t-head/e906/context_gcc.S new file mode 100644 index 0000000000..2f5223ae63 --- /dev/null +++ b/libcpu/risc-v/t-head/e906/context_gcc.S @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting implementation + */ + +#include "cpuport.h" + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + +/* + * Functions: vPortYield + */ +.global vPortYield +.type vPortYield, %function +vPortYield: + li t0, 0xE080100C + lb t1, (t0) + li t2, 0x01 + or t1, t1, t2 + sb t1, (t0) + + ret + + + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_to(rt_ubase_t to); + * #endif + * a0 --> to + * a1 --> to_thread + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + /* save a0 to to_thread */ + la t0, rt_interrupt_to_thread + STORE a0, (t0) + + /* save 0 to from_thread */ + la t0, rt_interrupt_from_thread + li t1, 0 + STORE t1, (t0) + + /* set rt_thread_switch_interrupt_flag=1 */ + la t0, rt_thread_switch_interrupt_flag + li t1, 1 + STORE t1, (t0) + + /* enable mexstatus SPUSHEN and SPSWAPEN */ +#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1)) + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus |= (0x2 << 16); + __set_MEXSTATUS(mexstatus); +#endif + + csrw mscratch, sp + /* set software interrupt */ + li t0, 0xE080100C + lb t1, (t0) + li t2, 0x01 + or t1, t1, t2 + sb t1, (t0) + + /* enable global interrup */ + csrsi mstatus, 8 + + ret + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * #endif + * + * a0 --> from + * a1 --> to + * a2 --> to_thread + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + /* check rt_thread_switch_interrupt_flag */ + la t0, rt_thread_switch_interrupt_flag + lw t1, (t0) + li t2, 1 + beq t1, t2, .reswitch + /* set rt_thread_switch_interrupt_flag=1 */ + STORE t2, (t0) + + /* update from_thread */ + la t0, rt_interrupt_from_thread + STORE a0, (t0) + +.reswitch: + /* update to_thread */ + la t0, rt_interrupt_to_thread + STORE a1, (t0) + /* set software interrupt */ + li t0, 0xE080100C + lb t1, (t0) + li t2, 0x01 + or t1, t1, t2 + sb t1, (t0) + + ret + +/* + * PendSV_Handler + */ +.global PendSV_Handler +.type PendSV_Handler, %function +PendSV_Handler: + + /* check rt_thread_switch_interrupt_flag */ + sw t0, (-4)(sp) + sw t1, (-8)(sp) + la t0, rt_thread_switch_interrupt_flag + lw t1, (t0) + beqz t1, .pendsv_exit + + /* clear rt_thread_switch_interrupt_flag */ + li t1, 0x0 + sw t1, (t0) + + /* check rt_interrupt_from_thread */ + la t0, rt_interrupt_from_thread + lw t1, (t0) + beqz t1, .switch_to_thead + + /* save from thread context */ + lw t0, (-4)(sp) + lw t1, (-8)(sp) + +#ifdef ARCH_RISCV_FPU + addi sp, sp, -32 * FREGBYTES + + FSTORE f0, 0 * FREGBYTES(sp) + FSTORE f1, 1 * FREGBYTES(sp) + FSTORE f2, 2 * FREGBYTES(sp) + FSTORE f3, 3 * FREGBYTES(sp) + FSTORE f4, 4 * FREGBYTES(sp) + FSTORE f5, 5 * FREGBYTES(sp) + FSTORE f6, 6 * FREGBYTES(sp) + FSTORE f7, 7 * FREGBYTES(sp) + FSTORE f8, 8 * FREGBYTES(sp) + FSTORE f9, 9 * FREGBYTES(sp) + FSTORE f10, 10 * FREGBYTES(sp) + FSTORE f11, 11 * FREGBYTES(sp) + FSTORE f12, 12 * FREGBYTES(sp) + FSTORE f13, 13 * FREGBYTES(sp) + FSTORE f14, 14 * FREGBYTES(sp) + FSTORE f15, 15 * FREGBYTES(sp) + FSTORE f16, 16 * FREGBYTES(sp) + FSTORE f17, 17 * FREGBYTES(sp) + FSTORE f18, 18 * FREGBYTES(sp) + FSTORE f19, 19 * FREGBYTES(sp) + FSTORE f20, 20 * FREGBYTES(sp) + FSTORE f21, 21 * FREGBYTES(sp) + FSTORE f22, 22 * FREGBYTES(sp) + FSTORE f23, 23 * FREGBYTES(sp) + FSTORE f24, 24 * FREGBYTES(sp) + FSTORE f25, 25 * FREGBYTES(sp) + FSTORE f26, 26 * FREGBYTES(sp) + FSTORE f27, 27 * FREGBYTES(sp) + FSTORE f28, 28 * FREGBYTES(sp) + FSTORE f29, 29 * FREGBYTES(sp) + FSTORE f30, 30 * FREGBYTES(sp) + FSTORE f31, 31 * FREGBYTES(sp) +#endif + + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + csrr x1, mepc + STORE x1, 0 * REGBYTES(sp) + csrr x1, mstatus + andi x1, x1, 8 + beqz x1, .save_mpie + li x1, 0x80 +.save_mpie: + STORE x1, 2 * REGBYTES(sp) + /* x3 don't need save */ + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + /* store from_thread sp */ + la t0, rt_interrupt_from_thread + lw t0, (t0) + sw sp, (t0) + +.switch_to_thead: + /* restore to thread context + * sp(0) -> epc; + * sp(1) -> ra; + * sp(i) -> x(i+2) + */ + la t0, rt_interrupt_to_thread + lw t0, (t0) + LOAD sp, (t0) + + /* restore ra to mepc */ + LOAD a1, 0 * REGBYTES(sp) + csrw mepc, a1 + LOAD x1, 1 * REGBYTES(sp) + + /* force to machin mode(MPP=11) */ + li a1, 0x1880 + csrs mstatus, a1 + LOAD a1, 2 * REGBYTES(sp) + csrs mstatus, a1 + /* x3 don't need restore */ + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + +#ifdef ARCH_RISCV_FPU + FLOAD f0, 0 * FREGBYTES(sp) + FLOAD f1, 1 * FREGBYTES(sp) + FLOAD f2, 2 * FREGBYTES(sp) + FLOAD f3, 3 * FREGBYTES(sp) + FLOAD f4, 4 * FREGBYTES(sp) + FLOAD f5, 5 * FREGBYTES(sp) + FLOAD f6, 6 * FREGBYTES(sp) + FLOAD f7, 7 * FREGBYTES(sp) + FLOAD f8, 8 * FREGBYTES(sp) + FLOAD f9, 9 * FREGBYTES(sp) + FLOAD f10, 10 * FREGBYTES(sp) + FLOAD f11, 11 * FREGBYTES(sp) + FLOAD f12, 12 * FREGBYTES(sp) + FLOAD f13, 13 * FREGBYTES(sp) + FLOAD f14, 14 * FREGBYTES(sp) + FLOAD f15, 15 * FREGBYTES(sp) + FLOAD f16, 16 * FREGBYTES(sp) + FLOAD f17, 17 * FREGBYTES(sp) + FLOAD f18, 18 * FREGBYTES(sp) + FLOAD f19, 19 * FREGBYTES(sp) + FLOAD f20, 20 * FREGBYTES(sp) + FLOAD f21, 21 * FREGBYTES(sp) + FLOAD f22, 22 * FREGBYTES(sp) + FLOAD f23, 23 * FREGBYTES(sp) + FLOAD f24, 24 * FREGBYTES(sp) + FLOAD f25, 25 * FREGBYTES(sp) + FLOAD f26, 26 * FREGBYTES(sp) + FLOAD f27, 27 * FREGBYTES(sp) + FLOAD f28, 28 * FREGBYTES(sp) + FLOAD f29, 29 * FREGBYTES(sp) + FLOAD f30, 30 * FREGBYTES(sp) + FLOAD f31, 31 * FREGBYTES(sp) + + addi sp, sp, 32 * FREGBYTES +#endif + +.pendsv_exit: + mret + + + diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e906/cpuport.c new file mode 100644 index 0000000000..5597aa237a --- /dev/null +++ b/libcpu/risc-v/t-head/e906/cpuport.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting code. + */ + +#include +#include + +#include "cpuport.h" + +#ifndef RT_USING_SMP +volatile rt_ubase_t rt_interrupt_from_thread = 0; +volatile rt_ubase_t rt_interrupt_to_thread = 0; +volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; +#endif + +struct rt_hw_stack_frame +{ + rt_ubase_t epc; /* epc - epc - program counter */ + rt_ubase_t ra; /* x1 - ra - return address for jumps */ + rt_ubase_t mstatus; /* - machine status register */ + rt_ubase_t gp; /* x3 - gp - global pointer */ + rt_ubase_t tp; /* x4 - tp - thread pointer */ + rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /* x9 - s1 - saved register 1 */ + rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /* x12 - a2 - function argument 2 */ + rt_ubase_t a3; /* x13 - a3 - function argument 3 */ + rt_ubase_t a4; /* x14 - a4 - function argument 4 */ + rt_ubase_t a5; /* x15 - a5 - function argument 5 */ + rt_ubase_t a6; /* x16 - a6 - function argument 6 */ + rt_ubase_t a7; /* x17 - s7 - function argument 7 */ + rt_ubase_t s2; /* x18 - s2 - saved register 2 */ + rt_ubase_t s3; /* x19 - s3 - saved register 3 */ + rt_ubase_t s4; /* x20 - s4 - saved register 4 */ + rt_ubase_t s5; /* x21 - s5 - saved register 5 */ + rt_ubase_t s6; /* x22 - s6 - saved register 6 */ + rt_ubase_t s7; /* x23 - s7 - saved register 7 */ + rt_ubase_t s8; /* x24 - s8 - saved register 8 */ + rt_ubase_t s9; /* x25 - s9 - saved register 9 */ + rt_ubase_t s10; /* x26 - s10 - saved register 10 */ + rt_ubase_t s11; /* x27 - s11 - saved register 11 */ + rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ +#ifdef ARCH_RISCV_FPU + rv_floatreg_t f0; /* f0 */ + rv_floatreg_t f1; /* f1 */ + rv_floatreg_t f2; /* f2 */ + rv_floatreg_t f3; /* f3 */ + rv_floatreg_t f4; /* f4 */ + rv_floatreg_t f5; /* f5 */ + rv_floatreg_t f6; /* f6 */ + rv_floatreg_t f7; /* f7 */ + rv_floatreg_t f8; /* f8 */ + rv_floatreg_t f9; /* f9 */ + rv_floatreg_t f10; /* f10 */ + rv_floatreg_t f11; /* f11 */ + rv_floatreg_t f12; /* f12 */ + rv_floatreg_t f13; /* f13 */ + rv_floatreg_t f14; /* f14 */ + rv_floatreg_t f15; /* f15 */ + rv_floatreg_t f16; /* f16 */ + rv_floatreg_t f17; /* f17 */ + rv_floatreg_t f18; /* f18 */ + rv_floatreg_t f19; /* f19 */ + rv_floatreg_t f20; /* f20 */ + rv_floatreg_t f21; /* f21 */ + rv_floatreg_t f22; /* f22 */ + rv_floatreg_t f23; /* f23 */ + rv_floatreg_t f24; /* f24 */ + rv_floatreg_t f25; /* f25 */ + rv_floatreg_t f26; /* f26 */ + rv_floatreg_t f27; /* f27 */ + rv_floatreg_t f28; /* f28 */ + rv_floatreg_t f29; /* f29 */ + rv_floatreg_t f30; /* f30 */ + rv_floatreg_t f31; /* f31 */ +#endif +}; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + + /* force to machine mode(MPP=11) and set MPIE to 1 */ + frame->mstatus = 0x00007880; + + return stk; +} + + +/** + * This function will disable global interrupt + * + * @param none + * + * @return zero + */ + +rt_base_t rt_hw_interrupt_disable(void) +{ + __asm volatile("csrc mstatus, 8"); + return 0; +} + +/** + * This function will ennable global interrupt + * + * @param level not used + * + * @return none + */ +void rt_hw_interrupt_enable(rt_base_t level) +{ + __asm volatile("csrs mstatus, 8"); +} + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} diff --git a/libcpu/risc-v/t-head/e906/cpuport.h b/libcpu/risc-v/t-head/e906/cpuport.h new file mode 100644 index 0000000000..90efc07653 --- /dev/null +++ b/libcpu/risc-v/t-head/e906/cpuport.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen The first version + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include + +/* bytes of register width */ +#ifdef ARCH_RISCV_64 +#define DFSTORE fsd +#define DFLOAD fld +#define SFSTORE fsw +#define SFLOAD flw +#define STORE sd +#define LOAD ld +#define REGBYTES 8 +#define SFREGBYTES 4 +#define DFREGBYTES 8 +#else +#define DFSTORE fsd +#define DFLOAD fld +#define SFSTORE fsw +#define SFLOAD flw +#define STORE sw +#define LOAD lw + +#define REGBYTES 4 +#define SFREGBYTES 4 +#define DFREGBYTES 8 +#endif + +#ifdef ARCH_RISCV_FPU +#ifdef ARCH_RISCV_FPU_D +#define FSTORE fsd +#define FLOAD fld +#define FREGBYTES 8 +#define rv_floatreg_t rt_int64_t +#endif +#ifdef ARCH_RISCV_FPU_S +#define FSTORE fsw +#define FLOAD flw +#define FREGBYTES 4 +#define rv_floatreg_t rt_int32_t +#endif +#endif + +#endif -- cgit v1.3.1 From a97b0a0d3972ad332a6afb2b7472163ff7f57ac0 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Fri, 11 Sep 2020 11:44:49 +0800 Subject: code format --- bsp/ls2kdev/drivers/board.h | 2 +- bsp/ls2kdev/drivers/clk.c | 1 - bsp/ls2kdev/drivers/drv_gpio.c | 4 +- bsp/ls2kdev/drivers/drv_gpio.h | 3 +- bsp/ls2kdev/drivers/drv_uart.h | 149 ++- bsp/ls2kdev/drivers/interrupt.h | 26 +- bsp/ls2kdev/drivers/ls2k1000.h | 16 +- bsp/ls2kdev/drivers/net/mii.c | 2 +- bsp/ls2kdev/drivers/net/mii.h | 34 +- bsp/ls2kdev/drivers/net/synopGMAC.c | 4 - bsp/ls2kdev/drivers/net/synopGMAC_Dev.c | 172 ++- bsp/ls2kdev/drivers/net/synopGMAC_Dev.h | 1694 +++++++++++++++--------------- bsp/ls2kdev/drivers/net/synopGMAC_plat.h | 2 +- libcpu/mips/gs264/cache.c | 2 +- libcpu/mips/gs264/cpuinit_gcc.S | 8 +- libcpu/mips/gs264/mips_mmu.c | 32 +- libcpu/mips/gs264/mips_mmu.h | 155 ++- libcpu/mips/gs264/mipscfg.c | 14 +- libcpu/mips/gs264/mmu.c | 8 +- libcpu/mips/gs264/mmu.h | 24 +- 20 files changed, 1140 insertions(+), 1212 deletions(-) (limited to 'libcpu') diff --git a/bsp/ls2kdev/drivers/board.h b/bsp/ls2kdev/drivers/board.h index 927a789af0..ca57ebf3f2 100644 --- a/bsp/ls2kdev/drivers/board.h +++ b/bsp/ls2kdev/drivers/board.h @@ -15,7 +15,7 @@ extern unsigned char __bss_end; -#define CPU_HZ (1000 * 1000 * 1000) //QEMU 200*1000*1000 +#define CPU_HZ (1000 * 1000 * 1000) //QEMU 200*1000*1000 #define RT_HW_HEAP_BEGIN (void*)&__bss_end #define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024) diff --git a/bsp/ls2kdev/drivers/clk.c b/bsp/ls2kdev/drivers/clk.c index aba08bd87a..7a043e9ff4 100644 --- a/bsp/ls2kdev/drivers/clk.c +++ b/bsp/ls2kdev/drivers/clk.c @@ -14,7 +14,6 @@ #include #include "ls2k1000.h" - struct loongson_pll { rt_uint64_t PLL_SYS_0; rt_uint64_t PLL_SYS_1; diff --git a/bsp/ls2kdev/drivers/drv_gpio.c b/bsp/ls2kdev/drivers/drv_gpio.c index 155807461f..abf9fdc8af 100644 --- a/bsp/ls2kdev/drivers/drv_gpio.c +++ b/bsp/ls2kdev/drivers/drv_gpio.c @@ -5,8 +5,8 @@ * Change Logs: * Date Author Notes * 2015-01-20 Bernard the first version - * 2017-10-20 ZYH add mode open drain and input pull down - * 2020-06-01 Du Huanpeng GPIO driver based on + * 2017-10-20 ZYH add mode open drain and input pull down + * 2020-06-01 Du Huanpeng GPIO driver based on */ #include #include diff --git a/bsp/ls2kdev/drivers/drv_gpio.h b/bsp/ls2kdev/drivers/drv_gpio.h index 51a75c306e..4bf1ba80f5 100644 --- a/bsp/ls2kdev/drivers/drv_gpio.h +++ b/bsp/ls2kdev/drivers/drv_gpio.h @@ -6,7 +6,7 @@ * * Change Logs: * Date Author Notes - * 2017-11-24 勤为本 first version + * 2017-11-24 勤为本 first version * 2018-05-11 zhuangwei add gpio interrupt ops */ @@ -36,6 +36,5 @@ struct loongson_gpio { int loongson_pin_init(void); - #endif diff --git a/bsp/ls2kdev/drivers/drv_uart.h b/bsp/ls2kdev/drivers/drv_uart.h index 4d17b99b35..ca3e856d06 100644 --- a/bsp/ls2kdev/drivers/drv_uart.h +++ b/bsp/ls2kdev/drivers/drv_uart.h @@ -15,100 +15,99 @@ #include /* UART registers */ -#define UART_DAT(base) HWREG8(base + 0x00) -#define UART_IER(base) HWREG8(base + 0x01) -#define UART_IIR(base) HWREG8(base + 0x02) -#define UART_FCR(base) HWREG8(base + 0x02) -#define UART_LCR(base) HWREG8(base + 0x03) -#define UART_MCR(base) HWREG8(base + 0x04) -#define UART_LSR(base) HWREG8(base + 0x05) -#define UART_MSR(base) HWREG8(base + 0x06) +#define UART_DAT(base) HWREG8(base + 0x00) +#define UART_IER(base) HWREG8(base + 0x01) +#define UART_IIR(base) HWREG8(base + 0x02) +#define UART_FCR(base) HWREG8(base + 0x02) +#define UART_LCR(base) HWREG8(base + 0x03) +#define UART_MCR(base) HWREG8(base + 0x04) +#define UART_LSR(base) HWREG8(base + 0x05) +#define UART_MSR(base) HWREG8(base + 0x06) -#define UART_LSB(base) HWREG8(base + 0x00) -#define UART_MSB(base) HWREG8(base + 0x01) +#define UART_LSB(base) HWREG8(base + 0x00) +#define UART_MSB(base) HWREG8(base + 0x01) /* interrupt enable register */ -#define IER_IRxE 0x1 -#define IER_ITxE 0x2 -#define IER_ILE 0x4 -#define IER_IME 0x8 +#define IER_IRxE 0x1 +#define IER_ITxE 0x2 +#define IER_ILE 0x4 +#define IER_IME 0x8 /* interrupt identification register */ -#define IIR_IMASK 0xf /* mask */ -#define IIR_RXTOUT 0xc /* receive timeout */ -#define IIR_RLS 0x6 /* receive line status */ -#define IIR_RXRDY 0x4 /* receive ready */ -#define IIR_TXRDY 0x2 /* transmit ready */ -#define IIR_NOPEND 0x1 /* nothing */ -#define IIR_MLSC 0x0 /* modem status */ -#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ +#define IIR_IMASK 0xf /* mask */ +#define IIR_RXTOUT 0xc /* receive timeout */ +#define IIR_RLS 0x6 /* receive line status */ +#define IIR_RXRDY 0x4 /* receive ready */ +#define IIR_TXRDY 0x2 /* transmit ready */ +#define IIR_NOPEND 0x1 /* nothing */ +#define IIR_MLSC 0x0 /* modem status */ +#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ /* fifo control register */ -#define FIFO_ENABLE 0x01 /* enable fifo */ -#define FIFO_RCV_RST 0x02 /* reset receive fifo */ -#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ -#define FIFO_DMA_MODE 0x08 /* enable dma mode */ -#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ -#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ -#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ -#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ +#define FIFO_ENABLE 0x01 /* enable fifo */ +#define FIFO_RCV_RST 0x02 /* reset receive fifo */ +#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ +#define FIFO_DMA_MODE 0x08 /* enable dma mode */ +#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ +#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ +#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ +#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ -// 线路控制寄存器 /* character format control register */ -#define CFCR_DLAB 0x80 /* divisor latch */ -#define CFCR_SBREAK 0x40 /* send break */ -#define CFCR_PZERO 0x30 /* zero parity */ -#define CFCR_PONE 0x20 /* one parity */ -#define CFCR_PEVEN 0x10 /* even parity */ -#define CFCR_PODD 0x00 /* odd parity */ -#define CFCR_PENAB 0x08 /* parity enable */ -#define CFCR_STOPB 0x04 /* 2 stop bits */ -#define CFCR_8BITS 0x03 /* 8 data bits */ -#define CFCR_7BITS 0x02 /* 7 data bits */ -#define CFCR_6BITS 0x01 /* 6 data bits */ -#define CFCR_5BITS 0x00 /* 5 data bits */ +#define CFCR_DLAB 0x80 /* divisor latch */ +#define CFCR_SBREAK 0x40 /* send break */ +#define CFCR_PZERO 0x30 /* zero parity */ +#define CFCR_PONE 0x20 /* one parity */ +#define CFCR_PEVEN 0x10 /* even parity */ +#define CFCR_PODD 0x00 /* odd parity */ +#define CFCR_PENAB 0x08 /* parity enable */ +#define CFCR_STOPB 0x04 /* 2 stop bits */ +#define CFCR_8BITS 0x03 /* 8 data bits */ +#define CFCR_7BITS 0x02 /* 7 data bits */ +#define CFCR_6BITS 0x01 /* 6 data bits */ +#define CFCR_5BITS 0x00 /* 5 data bits */ /* modem control register */ -#define MCR_LOOPBACK 0x10 /* loopback */ -#define MCR_IENABLE 0x08 /* output 2 = int enable */ -#define MCR_DRS 0x04 /* output 1 = xxx */ -#define MCR_RTS 0x02 /* enable RTS */ -#define MCR_DTR 0x01 /* enable DTR */ +#define MCR_LOOPBACK 0x10 /* loopback */ +#define MCR_IENABLE 0x08 /* output 2 = int enable */ +#define MCR_DRS 0x04 /* output 1 = xxx */ +#define MCR_RTS 0x02 /* enable RTS */ +#define MCR_DTR 0x01 /* enable DTR */ /* line status register */ -#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ -#define LSR_TSRE 0x40 /* transmitter empty */ -#define LSR_TXRDY 0x20 /* transmitter ready */ -#define LSR_BI 0x10 /* break detected */ -#define LSR_FE 0x08 /* framing error */ -#define LSR_PE 0x04 /* parity error */ -#define LSR_OE 0x02 /* overrun error */ -#define LSR_RXRDY 0x01 /* receiver ready */ -#define LSR_RCV_MASK 0x1f +#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ +#define LSR_TSRE 0x40 /* transmitter empty */ +#define LSR_TXRDY 0x20 /* transmitter ready */ +#define LSR_BI 0x10 /* break detected */ +#define LSR_FE 0x08 /* framing error */ +#define LSR_PE 0x04 /* parity error */ +#define LSR_OE 0x02 /* overrun error */ +#define LSR_RXRDY 0x01 /* receiver ready */ +#define LSR_RCV_MASK 0x1f /* UART interrupt enable register value */ -#define UARTIER_IME (1 << 3) -#define UARTIER_ILE (1 << 2) -#define UARTIER_ITXE (1 << 1) -#define UARTIER_IRXE (1 << 0) +#define UARTIER_IME (1 << 3) +#define UARTIER_ILE (1 << 2) +#define UARTIER_ITXE (1 << 1) +#define UARTIER_IRXE (1 << 0) /* UART line control register value */ -#define UARTLCR_DLAB (1 << 7) -#define UARTLCR_BCB (1 << 6) -#define UARTLCR_SPB (1 << 5) -#define UARTLCR_EPS (1 << 4) -#define UARTLCR_PE (1 << 3) -#define UARTLCR_SB (1 << 2) +#define UARTLCR_DLAB (1 << 7) +#define UARTLCR_BCB (1 << 6) +#define UARTLCR_SPB (1 << 5) +#define UARTLCR_EPS (1 << 4) +#define UARTLCR_PE (1 << 3) +#define UARTLCR_SB (1 << 2) /* UART line status register value */ -#define UARTLSR_ERROR (1 << 7) -#define UARTLSR_TE (1 << 6) -#define UARTLSR_TFE (1 << 5) -#define UARTLSR_BI (1 << 4) -#define UARTLSR_FE (1 << 3) -#define UARTLSR_PE (1 << 2) -#define UARTLSR_OE (1 << 1) -#define UARTLSR_DR (1 << 0) +#define UARTLSR_ERROR (1 << 7) +#define UARTLSR_TE (1 << 6) +#define UARTLSR_TFE (1 << 5) +#define UARTLSR_BI (1 << 4) +#define UARTLSR_FE (1 << 3) +#define UARTLSR_PE (1 << 2) +#define UARTLSR_OE (1 << 1) +#define UARTLSR_DR (1 << 0) #endif diff --git a/bsp/ls2kdev/drivers/interrupt.h b/bsp/ls2kdev/drivers/interrupt.h index 18707f7321..df55437cf9 100644 --- a/bsp/ls2kdev/drivers/interrupt.h +++ b/bsp/ls2kdev/drivers/interrupt.h @@ -64,22 +64,22 @@ #define LS2K_GPIO2_INT_IRQ (62) #define LS2K_GPIO3_INT_IRQ (63) -#define MAX_INTR 64 -#define LIOINTC0_IRQBASE 0 -#define LIOINTC1_IRQBASE 32 +#define MAX_INTR (64) +#define LIOINTC0_IRQBASE (0) +#define LIOINTC1_IRQBASE (32) -#define LIOINTC_SHIFT_INTx 4 -#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx))) +#define LIOINTC_SHIFT_INTx (4) +#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx))) -#define LIOINTC_INTC_CHIP_START 0x20 +#define LIOINTC_INTC_CHIP_START 0x20 -#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00) -#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) -#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) -#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) -#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) -#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00) +#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) +#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) +#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) +#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) +#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) void liointc_set_irq_mode(int irq, int mode); -#endif \ No newline at end of file +#endif diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h index 24396e7d3b..38e83875fb 100644 --- a/bsp/ls2kdev/drivers/ls2k1000.h +++ b/bsp/ls2kdev/drivers/ls2k1000.h @@ -6,11 +6,11 @@ #define APB_BASE CKSEG1ADDR(0xbfe00000) -#define UART0_BASE_ADDR 0xbfe00000 -#define UART0_OFF 0x0 -#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF) +#define UART0_BASE_ADDR (0xbfe00000) +#define UART0_OFF (0x0) +#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF) -#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8))) +#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8))) #define LIOINTC0_BASE CKSEG1ADDR(0x1fe11400) #define CORE0_INTISR0 CKSEG1ADDR(0x1fe11040) @@ -18,11 +18,11 @@ #define LIOINTC1_BASE CKSEG1ADDR(0x1fe11440) #define CORE0_INTISR1 CKSEG1ADDR(0x1fe11048) -#define GPIO_BASE 0xFFFFFFFFBFE10500 -#define PLL_SYS_BASE 0xFFFFFFFFBFE10480 -#define RTC_BASE 0xFFFFFFFFBFE07820 +#define GPIO_BASE (0xFFFFFFFFBFE10500) +#define PLL_SYS_BASE (0xFFFFFFFFBFE10480) +#define RTC_BASE (0xFFFFFFFFBFE07820) -#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420 +#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420) void rt_hw_timer_handler(void); void rt_hw_uart_init(void); diff --git a/bsp/ls2kdev/drivers/net/mii.c b/bsp/ls2kdev/drivers/net/mii.c index b06475df12..a0b3a7adce 100644 --- a/bsp/ls2kdev/drivers/net/mii.c +++ b/bsp/ls2kdev/drivers/net/mii.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/ls2kdev/drivers/net/mii.h b/bsp/ls2kdev/drivers/net/mii.h index 994d560c50..bc6d6c7a0c 100644 --- a/bsp/ls2kdev/drivers/net/mii.h +++ b/bsp/ls2kdev/drivers/net/mii.h @@ -37,7 +37,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -135,8 +135,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -170,11 +170,11 @@ /* Which connector port. */ -#define PORT_TP 0x00 -#define PORT_AUI 0x01 -#define PORT_MII 0x02 -#define PORT_FIBRE 0x03 -#define PORT_BNC 0x04 +#define PORT_TP 0x00 +#define PORT_AUI 0x01 +#define PORT_MII 0x02 +#define PORT_FIBRE 0x03 +#define PORT_BNC 0x04 /* Which transceiver to use. */ #define XCVR_INTERNAL 0x00 @@ -183,18 +183,18 @@ #define XCVR_DUMMY2 0x03 #define XCVR_DUMMY3 0x04 -#define AUTONEG_DISABLE 0x00 -#define AUTONEG_ENABLE 0x01 +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 -#define SPEED_2500 2500 -#define SPEED_10000 10000 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 struct ethtool_cmd { u32 cmd; diff --git a/bsp/ls2kdev/drivers/net/synopGMAC.c b/bsp/ls2kdev/drivers/net/synopGMAC.c index 38a6345236..f58f67ff5f 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC.c +++ b/bsp/ls2kdev/drivers/net/synopGMAC.c @@ -260,7 +260,6 @@ s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter) return gmacdev->Speed | (gmacdev->DuplexMode << 4); } - static int Mac_change_check(u8 *macaddr0, u8 *macaddr1) { int i; @@ -894,7 +893,6 @@ int rt_hw_eth_init(void) struct synopGMACNetworkAdapter *synopGMACadapter; static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS; int index; - //rt_kprintf("rt_hw_eth_init 1\n"); rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO); rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); @@ -958,8 +956,6 @@ int rt_hw_eth_init(void) eth_device_init(&(eth_dev.parent), "e0"); eth_device_linkchange(ð_dev.parent, RT_TRUE); //linkup the e0 for lwip to check - //rt_kprintf("rt_hw_eth_init 2\n"); return 0; } - INIT_COMPONENT_EXPORT(rt_hw_eth_init); diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c index ade261563d..cdd4585670 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c +++ b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c @@ -860,7 +860,6 @@ void synopGMAC_promisc_disable(synopGMACdevice *gmacdev) return; } - /** * Enables unicast hash filtering. * When enabled GMAC performs the destination address filtering of unicast frames according to the hash table. @@ -1032,7 +1031,6 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev) synopGMACWriteReg(gmacdev -> MacBase,GmacFlowControl,mac_flow_control_reg); return; - } /** @@ -1352,10 +1350,9 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) desc -> length = 0; #else desc -> length = last_ring_desc ? TxDescEndOfRing : 0; - desc -> status = 0; + desc -> status = 0; #endif //sw - desc -> buffer1 = 0; desc -> buffer2 = 0; desc -> data1 = 0; @@ -1365,8 +1362,6 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) return; } - - /** * Initialize the rx descriptors for chain mode of operation. * - Status field is initialized to 0. @@ -1409,7 +1404,6 @@ void synopGMAC_tx_desc_init_chain(DmaDesc * desc) return; } - s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev) { s32 i; @@ -1817,7 +1811,6 @@ void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1 } return; - } #ifdef ENH_DESC_8W @@ -1912,10 +1905,7 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 u32 txover = gmacdev->TxBusy; DmaDesc * txdesc = gmacdev->TxBusyDesc; int i; - //sw: dbg - - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R); //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG @@ -1954,12 +1944,12 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; if(synopGMAC_is_tx_desc_chained(txdesc)) - { - gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; + { + gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; synopGMAC_tx_desc_init_chain(txdesc); } else - { + { gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); } @@ -2008,37 +1998,40 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now - if(synopGMAC_is_tx_desc_chained(txdesc)){ - txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC - #else - txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor - #endif - - txdesc->buffer1 = Buffer1; - txdesc->data1 = Data1; - - if(offload_needed){ - /* - Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, - before calling any of the functions given below. - */ - synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); - synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); + if(synopGMAC_is_tx_desc_chained(txdesc)) + { + txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC + #else + txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor + #endif + + txdesc->buffer1 = Buffer1; + txdesc->data1 = Data1; + + if(offload_needed) + { + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); // synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } + #ifdef ENH_DESC + txdesc->status |= DescOwnByDma;//ENH_DESC + #else + txdesc->status = DescOwnByDma; + #endif + + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; } - #ifdef ENH_DESC - txdesc->status |= DescOwnByDma;//ENH_DESC - #else - txdesc->status = DescOwnByDma; - #endif - - gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; - gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; - } - else{ -// printf("synopGMAC_set_tx_qptr:in ring mode\n"); + else + { +// printf("synopGMAC_set_tx_qptr:in ring mode\n"); txdesc->length |= (((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC @@ -2046,13 +2039,14 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor #endif - txdesc->buffer1 = Buffer1; + txdesc->buffer1 = Buffer1; txdesc->data1 = Data1; - txdesc->buffer2 = Buffer2; + txdesc->buffer2 = Buffer2; txdesc->data2 = Data2; - if(offload_needed){ + if(offload_needed) + { /* Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, before calling any of the functions given below. @@ -2638,8 +2632,7 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) else{ synopGMAC_take_desc_ownership(desc + i); } - } - + } } /** @@ -2668,15 +2661,8 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); data &= (~DmaRxStart); synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); -} - - - +} /*******************PMT APIs***************************************/ - - - - /** * Enables the assertion of PMT interrupt. * This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame @@ -2835,9 +2821,9 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte } #endif + /*******************PMT APIs***************************************/ /*******************MMC APIs***************************************/ - /** * Freezes the MMC counters. * This function call freezes the MMC counters. None of the MMC counters are updated @@ -3081,7 +3067,6 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) * \return returns TRUE or FALSE */ #ifdef ENH_DESC_8W - /** * This function indicates whether extended status is available in the RDES0. * Any function which accesses the fields of extended status register must ensure a check on this has been made @@ -3132,8 +3117,6 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) } #endif - - /** * Decodes the Rx Descriptor status to various checksum error conditions. * @param[in] pointer to synopGMACdevice. @@ -3172,7 +3155,6 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); } - /** * Checks if any payload checksum error in the frame just transmitted. * This serves as indication that error occureed in the payload checksum insertion. @@ -3199,7 +3181,6 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des #else desc->length = (desc->length & (~DescTxCisMask)); #endif - } /** * The check summ offload engine is enabled to do only IPV4 header checksum. @@ -3215,7 +3196,6 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de #else desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs); #endif - } /** @@ -3233,7 +3213,6 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de #else desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs); #endif - } /** * The check summ offload engine is enabled to do complete checksum computation. @@ -3254,14 +3233,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc } /*******************Ip checksum offloading APIs***************************************/ - - - - - /*******************IEEE 1588 Timestamping API***************************************/ - - /* * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled. * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced @@ -3295,7 +3267,6 @@ void synopGMAC_TS_disable(synopGMACdevice *gmacdev) return; } - /** * Enable the interrupt to get timestamping interrupt. * This enables the host to get the interrupt when (1) system time is greater or equal to the @@ -3344,7 +3315,6 @@ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev) return; } - /** * Selet the type of clock mode for PTP. * Please note to use one of the follwoing as the clk_type argument. @@ -3493,7 +3463,6 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev) return; } - /** * Snoop PTP packet for version 2 format * When set the PTP packets are snooped using the version 2 format. @@ -3584,11 +3553,10 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value) if(loop_variable < DEFAULT_LOOP_VARIABLE) synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSADDREG); else{ - TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; } -return -ESYNOPGMACNOERR; - + return -ESYNOPGMACNOERR; } /** * time stamp Update @@ -3602,21 +3570,21 @@ return -ESYNOPGMACNOERR; s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { u32 loop_variable; - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register - synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time + synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register + synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break - break; + break; } plat_delay(DEFAULT_DELAY_VARIABLE); - } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT); - else{ + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT); + else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; - } -return -ESYNOPGMACNOERR; + return -ESYNOPGMACPHYERR; + } + return -ESYNOPGMACNOERR; } /** @@ -3631,21 +3599,21 @@ return -ESYNOPGMACNOERR; s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { u32 loop_variable; - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register - synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time + synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register + synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break - break; + break; } plat_delay(DEFAULT_DELAY_VARIABLE); - } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT); - else{ + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT); + else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; - } -return -ESYNOPGMACNOERR; + return -ESYNOPGMACPHYERR; + } + return -ESYNOPGMACNOERR; } /** @@ -3696,8 +3664,8 @@ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val) { * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); - * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh); - * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSLow); + * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh); + * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSLow); return; } /** diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h index fceb7af1fb..f47046d5ba 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h +++ b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.h @@ -15,17 +15,17 @@ #define SYNOP_GMAC_DEV_H 1 /*******************************************************************/ -#define SYNOP_LOOPBACK_MODE 0 -#define SYNOP_LOOPBACK_DEBUG 0 -#define SYNOP_PHY_LOOPBACK 0 +#define SYNOP_LOOPBACK_MODE (0) +#define SYNOP_LOOPBACK_DEBUG (0) +#define SYNOP_PHY_LOOPBACK (0) -#define SYNOP_TX_TEST 0 -#define SYNOP_RX_TEST 0 +#define SYNOP_TX_TEST (0) +#define SYNOP_RX_TEST (0) -#define SYNOP_TOP_DEBUG 0 -#define SYNOP_REG_DEBUG 0 -#define SYNOP_RX_DEBUG 0 -#define SYNOP_TX_DEBUG 0 +#define SYNOP_TOP_DEBUG (0) +#define SYNOP_REG_DEBUG (0) +#define SYNOP_RX_DEBUG (0) +#define SYNOP_TX_DEBUG (0) #define ENH_DESC /*******************************************************************/ @@ -49,35 +49,35 @@ enum GMACPhyBase { - PHY0 = 0, //The device can support 32 phys, but we use first phy only + PHY0 = 0, //The device can support 32 phys, but we use first phy only PHY1 = 1, PHY16 = 16, PHY31 = 31, }; -//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue -//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue -//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue -#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue -#define RECEIVE_DESC_SIZE 36 //96 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue +//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue +#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue +#define RECEIVE_DESC_SIZE 36 //96 //Rx Descriptors needed in the Descriptor pool/queue -#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type -#define ETHERNET_CRC 4 //Ethernet CRC -#define ETHERNET_EXTRA 2 //Only God knows about this????? -#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb -#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA -#define VLAN_TAG 4 //optional 802.1q VLAN Tag -#define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size -#define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size -#define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size +#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type +#define ETHERNET_CRC 4 //Ethernet CRC +#define ETHERNET_EXTRA 2 //Only God knows about this????? +#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb +#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA +#define VLAN_TAG 4 //optional 802.1q VLAN Tag +#define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size +#define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size +#define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size -#define TX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000 -#define RX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000 +#define TX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000 +#define RX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + 1000 // This is the IP's phy address. This is unique address for every MAC in the universe -#define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7} +#define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7} /* DMA Descriptor Structure @@ -98,31 +98,31 @@ In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DES #ifdef ENH_DESC_8W typedef struct DmaDescStruct { - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ /* This data below is used only by driver */ - u32 extstatus; /* Extended status of a Rx Descriptor */ - u32 reserved1; /* Reserved word */ - u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ - u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ - u64 data1; /* This holds virtual address of buffer1, not used by DMA */ - u64 data2; /* This holds virtual address of buffer2, not used by DMA */ + u32 extstatus; /* Extended status of a Rx Descriptor */ + u32 reserved1; /* Reserved word */ + u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ + u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ + u64 data1; /* This holds virtual address of buffer1, not used by DMA */ + u64 data2; /* This holds virtual address of buffer2, not used by DMA */ } DmaDesc; #else typedef struct DmaDescStruct { - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ - /* This data below is used only by driver */ - u64 data1; /* This holds virtual address of buffer1, not used by DMA */ - u64 data2; /* This holds virtual address of buffer2, not used by DMA */ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ + u64 data1; /* This holds virtual address of buffer1, not used by DMA */ + u64 data2; /* This holds virtual address of buffer2, not used by DMA */ - //u32 dummy1; //sw: for addr align - //u32 dummy2; // + //u32 dummy1; //sw: for addr align + //u32 dummy2; // } DmaDesc; #endif @@ -130,137 +130,130 @@ typedef struct DmaDescStruct enum DescMode { RINGMODE = 0x00000001, - CHAINMODE = 0x00000002, + CHAINMODE = 0x00000002, }; enum BufferMode { - SINGLEBUF = 0x00000001, - DUALBUF = 0x00000002, + SINGLEBUF = 0x00000001, + DUALBUF = 0x00000002, }; /* synopGMAC device data */ typedef struct synopGMACDeviceStruct { - u64 MacBase; /* base address of MAC registers */ - u64 DmaBase; /* base address of DMA registers */ - u64 PhyBase; /* PHY device address on MII interface */ - u32 Version; /* Gmac Revision version */ + u64 MacBase; /* base address of MAC registers */ + u64 DmaBase; /* base address of DMA registers */ + u64 PhyBase; /* PHY device address on MII interface */ + u32 Version; /* Gmac Revision version */ + dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ + dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ + DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ + DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ - dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ - dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ - DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ - DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ - - u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ - u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ - - u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ - u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ + u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ + u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ - u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ - u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ - u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ - u32 RxNext; /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */ - - DmaDesc * TxBusyDesc; /* Tx Descriptor address corresponding to the index TxBusy */ - DmaDesc * TxNextDesc; /* Tx Descriptor address corresponding to the index TxNext */ - DmaDesc * RxBusyDesc; /* Rx Descriptor address corresponding to the index TxBusy */ - DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ - - /*Phy related stuff*/ - u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ - /* The status of the link */ - u32 LinkState0; /* Link status as reported by the Marvel Phy */ - u32 LinkState; /* Link status as reported by the Marvel Phy */ - u32 DuplexMode; /* Duplex mode of the Phy */ - u32 Speed; /* Speed of the Phy */ - u32 LoopBackMode; /* Loopback status of the Phy */ + u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ + u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ + u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ + u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ + u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ + u32 RxNext; /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */ + + DmaDesc * TxBusyDesc; /* Tx Descriptor address corresponding to the index TxBusy */ + DmaDesc * TxNextDesc; /* Tx Descriptor address corresponding to the index TxNext */ + DmaDesc * RxBusyDesc; /* Rx Descriptor address corresponding to the index TxBusy */ + DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ + + /*Phy related stuff*/ + u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ + /* The status of the link */ + u32 LinkState0; /* Link status as reported by the Marvel Phy */ + u32 LinkState; /* Link status as reported by the Marvel Phy */ + u32 DuplexMode; /* Duplex mode of the Phy */ + u32 Speed; /* Speed of the Phy */ + u32 LoopBackMode; /* Loopback status of the Phy */ // void * FirstTxDesc; // void * FirstRxDesc; // u32 skb_array[RECEIVE_DESC_SIZE]; } synopGMACdevice; - - /* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter. * Since the Phy register map is standard, this map hardly changes to a different Ppy */ - enum MiiRegisters { - PHY_CONTROL_REG = 0x0000, /*Control Register*/ - PHY_STATUS_REG = 0x0001, /*Status Register */ - PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ - PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ - PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ - PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ - PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ - PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ - PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ - PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ - PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ - PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ - PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ - PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ - PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ - PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ - PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ - PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ - PHY_LED_CONTROL = 0x0018, /*LED Control*/ - PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ - PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ - PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ - PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ + PHY_CONTROL_REG = 0x0000, /*Control Register*/ + PHY_STATUS_REG = 0x0001, /*Status Register */ + PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ + PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ + PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ + PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ + PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ + PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ + PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ + PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ + PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ + PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ + PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ + PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ + PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ + PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ + PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ + PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ + PHY_LED_CONTROL = 0x0018, /*LED Control*/ + PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ + PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ + PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ + PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ }; - /* This is Control register layout. Control register is of 16 bit wide. */ - enum Mii_GEN_CTRL -{ /* Description bits R/W default value */ - Mii_reset = 0x8000, - Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ - Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ - Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ +{ /* Description bits R/W default value */ + Mii_reset = 0x8000, + Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ + Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ + Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ - Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ + Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ - Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ + Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ - Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ - Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ + Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ + Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ }; enum Mii_Phy_Status { Mii_phy_status_speed_10 = 0x0000, - Mii_phy_status_speed_100 = 0x4000, - Mii_phy_status_speed_1000 = 0x8000, + Mii_phy_status_speed_100 = 0x4000, + Mii_phy_status_speed_1000 = 0x8000, - Mii_phy_status_full_duplex = 0x2000, - Mii_phy_status_half_duplex = 0x0000, + Mii_phy_status_full_duplex = 0x2000, + Mii_phy_status_half_duplex = 0x0000, - Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy + Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy // Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY }; /* This is Status register layout. Status register is of 16 bit wide. */ enum Mii_GEN_STATUS { - Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ - Mii_Link = 0x0004, /* Link status 2 RW */ + Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ + Mii_Link = 0x0004, /* Link status 2 RW */ }; enum Mii_Link_Status { - LINKDOWN = 0, - LINKUP = 1, + LINKDOWN = 0, + LINKUP = 1, }; enum Mii_Duplex_Mode @@ -281,8 +274,6 @@ enum Mii_Loop_Back LOOPBACK = 1, }; - - /********************************************************** * GMAC registers Map * For Pci based system address is BARx + GmacRegisterBase @@ -290,76 +281,76 @@ enum Mii_Loop_Back **********************************************************/ enum GmacRegisters { - GmacConfig = 0x0000, /* Mac config Register */ - GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ - GmacHashHigh = 0x0008, /* Multi-cast hash table high */ - GmacHashLow = 0x000C, /* Multi-cast hash table low */ - GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ - GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ - GmacFlowControl = 0x0018, /* Flow control Register */ - GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ + GmacConfig = 0x0000, /* Mac config Register */ + GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ + GmacHashHigh = 0x0008, /* Multi-cast hash table high */ + GmacHashLow = 0x000C, /* Multi-cast hash table low */ + GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ + GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ + GmacFlowControl = 0x0018, /* Flow control Register */ + GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ - GmacVersion = 0x0020, /* GMAC Core Version Register */ - GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ - GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ + GmacVersion = 0x0020, /* GMAC Core Version Register */ + GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ + GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ - GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ - GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ + GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ + GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ - GmacAddr0High = 0x0040, /* Mac address0 high Register */ - GmacAddr0Low = 0x0044, /* Mac address0 low Register */ - GmacAddr1High = 0x0048, /* Mac address1 high Register */ - GmacAddr1Low = 0x004C, /* Mac address1 low Register */ - GmacAddr2High = 0x0050, /* Mac address2 high Register */ - GmacAddr2Low = 0x0054, /* Mac address2 low Register */ - GmacAddr3High = 0x0058, /* Mac address3 high Register */ - GmacAddr3Low = 0x005C, /* Mac address3 low Register */ - GmacAddr4High = 0x0060, /* Mac address4 high Register */ - GmacAddr4Low = 0x0064, /* Mac address4 low Register */ - GmacAddr5High = 0x0068, /* Mac address5 high Register */ - GmacAddr5Low = 0x006C, /* Mac address5 low Register */ - GmacAddr6High = 0x0070, /* Mac address6 high Register */ - GmacAddr6Low = 0x0074, /* Mac address6 low Register */ - GmacAddr7High = 0x0078, /* Mac address7 high Register */ - GmacAddr7Low = 0x007C, /* Mac address7 low Register */ - GmacAddr8High = 0x0080, /* Mac address8 high Register */ - GmacAddr8Low = 0x0084, /* Mac address8 low Register */ - GmacAddr9High = 0x0088, /* Mac address9 high Register */ - GmacAddr9Low = 0x008C, /* Mac address9 low Register */ - GmacAddr10High = 0x0090, /* Mac address10 high Register */ - GmacAddr10Low = 0x0094, /* Mac address10 low Register */ - GmacAddr11High = 0x0098, /* Mac address11 high Register */ - GmacAddr11Low = 0x009C, /* Mac address11 low Register */ - GmacAddr12High = 0x00A0, /* Mac address12 high Register */ - GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ - GmacAddr13High = 0x00A8, /* Mac address13 high Register */ - GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ - GmacAddr14High = 0x00B0, /* Mac address14 high Register */ - GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ - GmacAddr15High = 0x00B8, /* Mac address15 high Register */ - GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ - GmacStatus = 0x00d8, /*MAC status*/ + GmacAddr0High = 0x0040, /* Mac address0 high Register */ + GmacAddr0Low = 0x0044, /* Mac address0 low Register */ + GmacAddr1High = 0x0048, /* Mac address1 high Register */ + GmacAddr1Low = 0x004C, /* Mac address1 low Register */ + GmacAddr2High = 0x0050, /* Mac address2 high Register */ + GmacAddr2Low = 0x0054, /* Mac address2 low Register */ + GmacAddr3High = 0x0058, /* Mac address3 high Register */ + GmacAddr3Low = 0x005C, /* Mac address3 low Register */ + GmacAddr4High = 0x0060, /* Mac address4 high Register */ + GmacAddr4Low = 0x0064, /* Mac address4 low Register */ + GmacAddr5High = 0x0068, /* Mac address5 high Register */ + GmacAddr5Low = 0x006C, /* Mac address5 low Register */ + GmacAddr6High = 0x0070, /* Mac address6 high Register */ + GmacAddr6Low = 0x0074, /* Mac address6 low Register */ + GmacAddr7High = 0x0078, /* Mac address7 high Register */ + GmacAddr7Low = 0x007C, /* Mac address7 low Register */ + GmacAddr8High = 0x0080, /* Mac address8 high Register */ + GmacAddr8Low = 0x0084, /* Mac address8 low Register */ + GmacAddr9High = 0x0088, /* Mac address9 high Register */ + GmacAddr9Low = 0x008C, /* Mac address9 low Register */ + GmacAddr10High = 0x0090, /* Mac address10 high Register */ + GmacAddr10Low = 0x0094, /* Mac address10 low Register */ + GmacAddr11High = 0x0098, /* Mac address11 high Register */ + GmacAddr11Low = 0x009C, /* Mac address11 low Register */ + GmacAddr12High = 0x00A0, /* Mac address12 high Register */ + GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ + GmacAddr13High = 0x00A8, /* Mac address13 high Register */ + GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ + GmacAddr14High = 0x00B0, /* Mac address14 high Register */ + GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ + GmacAddr15High = 0x00B8, /* Mac address15 high Register */ + GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ + GmacStatus = 0x00d8, /* MAC status */ /*Time Stamp Register Map*/ - GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ + GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ - GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ - //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ + GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ +//GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ - GmacTSStatus = 0x0728, /* Time Stamp Status Register */ + GmacTSStatus = 0x0728, /* Time Stamp Status Register */ }; /********************************************************** @@ -376,214 +367,211 @@ enum GmacRegisters /* GmacConfig = 0x0000, Mac config Register Layout */ enum GmacConfigReg { - /* Bit description Bits R/W Reset value */ - GmacWatchdog = 0x00800000, - GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ - GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ - - GmacJabber = 0x00400000, - GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ - GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ - - GmacFrameBurst = 0x00200000, - GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ - GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ + /* Bit description Bits R/W Reset value */ + GmacWatchdog = 0x00800000, + GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ + GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ + + GmacJabber = 0x00400000, + GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ + GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ + + GmacFrameBurst = 0x00200000, + GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ + GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ - GmacJumboFrame = 0x00100000, - GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ - GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ - - GmacInterFrameGap7 = 0x000E0000, /* (IFG) Config7 - 40 bit times 19:17 RW */ - GmacInterFrameGap6 = 0x000C0000, /* (IFG) Config6 - 48 bit times */ - GmacInterFrameGap5 = 0x000A0000, /* (IFG) Config5 - 56 bit times */ - GmacInterFrameGap4 = 0x00080000, /* (IFG) Config4 - 64 bit times */ - GmacInterFrameGap3 = 0x00040000, /* (IFG) Config3 - 72 bit times */ - GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ - GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ - GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ + GmacJumboFrame = 0x00100000, + GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ + GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ + + GmacInterFrameGap7 = 0x000E0000, /* (IFG) Config7 - 40 bit times 19:17 RW */ + GmacInterFrameGap6 = 0x000C0000, /* (IFG) Config6 - 48 bit times */ + GmacInterFrameGap5 = 0x000A0000, /* (IFG) Config5 - 56 bit times */ + GmacInterFrameGap4 = 0x00080000, /* (IFG) Config4 - 64 bit times */ + GmacInterFrameGap3 = 0x00040000, /* (IFG) Config3 - 72 bit times */ + GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ + GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ + GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ - GmacDisableCrs = 0x00010000, - GmacMiiGmii = 0x00008000, - GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ - GmacSelectGmii = 0x00000000, /* GMII mode 0 */ + GmacDisableCrs = 0x00010000, + GmacMiiGmii = 0x00008000, + GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ + GmacSelectGmii = 0x00000000, /* GMII mode 0 */ - GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ - GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ + GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ + GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ - GmacRxOwn = 0x00002000, - GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ - GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ + GmacRxOwn = 0x00002000, + GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ + GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ - GmacLoopback = 0x00001000, - GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ - GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ + GmacLoopback = 0x00001000, + GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ + GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ - GmacDuplex = 0x00000800, - GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ - GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ + GmacDuplex = 0x00000800, + GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ + GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ - GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ + GmacRxIpcOffload = 0x00000400, /* IPC checksum offload 10 RW 0 */ - GmacRetry = 0x00000200, - GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ - GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ + GmacRetry = 0x00000200, + GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ + GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ - GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ - GmacLinkDown = 0x00000100, /* Link Down 0 */ + GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ + GmacLinkDown = 0x00000100, /* Link Down 0 */ - GmacPadCrcStrip = 0x00000080, - GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ - GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ + GmacPadCrcStrip = 0x00000080, + GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ + GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ - GmacBackoffLimit = 0x00000060, - GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ - GmacBackoffLimit2 = 0x00000040, /* */ - GmacBackoffLimit1 = 0x00000020, /* */ - GmacBackoffLimit0 = 0x00000000, /* 00 */ - - GmacDeferralCheck = 0x00000010, - GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ - GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ + GmacBackoffLimit = 0x00000060, + GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ + GmacBackoffLimit2 = 0x00000040, /* */ + GmacBackoffLimit1 = 0x00000020, /* */ + GmacBackoffLimit0 = 0x00000000, /* 00 */ + + GmacDeferralCheck = 0x00000010, + GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ + GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ - GmacTx = 0x00000008, - GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ - GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ + GmacTx = 0x00000008, + GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ + GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ - GmacRx = 0x00000004, - GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ - GmacRxDisable = 0x00000000, /* Receiver disable 0 */ + GmacRx = 0x00000004, + GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ + GmacRxDisable = 0x00000000, /* Receiver disable 0 */ }; /* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/ enum GmacFrameFilterReg { - GmacFilter = 0x80000000, - GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ - GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ + GmacFilter = 0x80000000, + GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ + GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ - GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ + GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ - GmacSrcAddrFilter = 0x00000200, - GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ - GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ + GmacSrcAddrFilter = 0x00000200, + GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ + GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ - GmacSrcInvaAddrFilter = 0x00000100, - GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ - GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ + GmacSrcInvaAddrFilter = 0x00000100, + GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ + GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ - GmacPassControl = 0x000000C0, - GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ - GmacPassControl2 = 0x00000080, /* Forwards all control frames */ - GmacPassControl1 = 0x00000040, /* Does not pass control frames */ - GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ + GmacPassControl = 0x000000C0, + GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ + GmacPassControl2 = 0x00000080, /* Forwards all control frames */ + GmacPassControl1 = 0x00000040, /* Does not pass control frames */ + GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ - GmacBroadcast = 0x00000020, - GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ - GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ + GmacBroadcast = 0x00000020, + GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ + GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ - GmacMulticastFilter = 0x00000010, - GmacMulticastFilterOff = 0x00000010, /* (PM) Pass all multicast packets 4 RW */ - GmacMulticastFilterOn = 0x00000000, /* Pass filtered multicast packets 0 */ + GmacMulticastFilter = 0x00000010, + GmacMulticastFilterOff = 0x00000010, /* (PM) Pass all multicast packets 4 RW */ + GmacMulticastFilterOn = 0x00000000, /* Pass filtered multicast packets 0 */ - GmacDestAddrFilter = 0x00000008, - GmacDestAddrFilterInv = 0x00000008, /* (DAIF)Inverse filtering for DA 3 RW */ - GmacDestAddrFilterNor = 0x00000000, /* Normal filtering for DA 0 */ + GmacDestAddrFilter = 0x00000008, + GmacDestAddrFilterInv = 0x00000008, /* (DAIF)Inverse filtering for DA 3 RW */ + GmacDestAddrFilterNor = 0x00000000, /* Normal filtering for DA 0 */ - GmacMcastHashFilter = 0x00000004, - GmacMcastHashFilterOn = 0x00000004, /* (HMC)perfom multicast hash filtering 2 RW */ - GmacMcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ + GmacMcastHashFilter = 0x00000004, + GmacMcastHashFilterOn = 0x00000004, /* (HMC)perfom multicast hash filtering 2 RW */ + GmacMcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ - GmacUcastHashFilter = 0x00000002, - GmacUcastHashFilterOn = 0x00000002, /* (HUC)Unicast Hash filtering only 1 RW */ - GmacUcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ + GmacUcastHashFilter = 0x00000002, + GmacUcastHashFilterOn = 0x00000002, /* (HUC)Unicast Hash filtering only 1 RW */ + GmacUcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ - GmacPromiscuousMode = 0x00000001, - GmacPromiscuousModeOn = 0x00000001, /* Receive all frames 0 RW */ - GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ + GmacPromiscuousMode = 0x00000001, + GmacPromiscuousModeOn = 0x00000001, /* Receive all frames 0 RW */ + GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ }; - /*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */ enum GmacGmiiAddrReg { - GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ - GmiiDevShift = 11, + GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ + GmiiDevShift = 11, - GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ - GmiiRegShift = 6, + GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ + GmiiRegShift = 6, - GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ - GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ - GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ - GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ - GmiiCsrClk2 = 0x00000008, /* 20-35 MHz */ - GmiiCsrClk1 = 0x00000004, /* 100-150 MHz */ - GmiiCsrClk0 = 0x00000000, /* 60-100 MHz */ - - GmiiWrite = 0x00000002, /* (GW)Write to register 1 RW */ - GmiiRead = 0x00000000, /* Read from register 0 */ - - GmiiBusy = 0x00000001, /* (GB)GMII interface is busy 0 RW 0 */ + GmiiCsrClkMask = 0x0000001C, /* CSR Clock bit Mask 4:2 */ + GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ + GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ + GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ + GmiiCsrClk2 = 0x00000008, /* 20-35 MHz */ + GmiiCsrClk1 = 0x00000004, /* 100-150 MHz */ + GmiiCsrClk0 = 0x00000000, /* 60-100 MHz */ + + GmiiWrite = 0x00000002, /* (GW)Write to register 1 RW */ + GmiiRead = 0x00000000, /* Read from register 0 */ + + GmiiBusy = 0x00000001, /* (GB)GMII interface is busy 0 RW 0 */ }; /* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */ enum GmacGmiiDataReg { - GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ + GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ }; - /*GmacFlowControl = 0x0018, Flow control Register Layout */ enum GmacFlowControlReg { - GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ - GmacPauseTimeShift = 16, + GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ + GmacPauseTimeShift = 16, - GmacPauseLowThresh = 0x00000030, - GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ - GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ - GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ - GmacPauseLowThresh0 = 0x00000000, /* 4 slot time 000 */ - - GmacUnicastPauseFrame = 0x00000008, - GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ - GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ - - GmacRxFlowControl = 0x00000004, - GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ - GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ - - GmacTxFlowControl = 0x00000002, - GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ - GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ - - GmacFlowControlBackPressure= 0x00000001, - GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ + GmacPauseLowThresh = 0x00000030, + GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ + GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ + GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ + GmacPauseLowThresh0 = 0x00000000, /* 4 slot time 000 */ + + GmacUnicastPauseFrame = 0x00000008, + GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ + GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ + + GmacRxFlowControl = 0x00000004, + GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ + GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ + + GmacTxFlowControl = 0x00000002, + GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ + GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ + + GmacFlowControlBackPressure= 0x00000001, + GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ }; /* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ enum GmacInterruptStatusBitDefinition { - GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ - GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ - GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ - GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ - GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ - GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ - GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ - GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ - GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ - + GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ + GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ + GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ + GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ + GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ + GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ + GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ + GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ }; /* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ enum GmacInterruptMaskBitDefinition { - GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ - GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ - GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ - GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ - GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ + GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ + GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ + GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ + GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ + GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ }; /********************************************************** @@ -591,22 +579,21 @@ enum GmacInterruptMaskBitDefinition * For Pci based system address is BARx + GmaDmaBase * For any other system translation is done accordingly **********************************************************/ - enum DmaRegisters { - DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ - DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ - DmaRxPollDemand = 0x0008, /* CSR2 - Receive Poll Demand Register */ - DmaRxBaseAddr = 0x000C, /* CSR3 - Receive Descriptor list base address */ - DmaTxBaseAddr = 0x0010, /* CSR4 - Transmit Descriptor list base address */ - DmaStatus = 0x0014, /* CSR5 - Dma status Register */ - DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ - DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ - DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ - DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ - DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ - DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ - DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ + DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ + DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ + DmaRxPollDemand = 0x0008, /* CSR2 - Receive Poll Demand Register */ + DmaRxBaseAddr = 0x000C, /* CSR3 - Receive Descriptor list base address */ + DmaTxBaseAddr = 0x0010, /* CSR4 - Transmit Descriptor list base address */ + DmaStatus = 0x0014, /* CSR5 - Dma status Register */ + DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ + DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ + DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ + DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ + DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ + DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ + DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ }; /********************************************************** @@ -616,165 +603,164 @@ enum DmaRegisters /*DmaBusMode = 0x0000, CSR0 - Bus Mode */ enum DmaBusModeReg { /* Bit description Bits R/W Reset value */ - DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ - DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ + DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ + DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ - DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ - DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ - DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ - DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ + DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ + DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ + DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ + DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ - DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ + DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ - DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ - DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ - DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ - DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ - DmaBurstLength16 = 0x00001000, /* Dma burst length = 16 */ - DmaBurstLength8 = 0x00000800, /* Dma burst length = 8 */ - DmaBurstLength4 = 0x00000400, /* Dma burst length = 4 */ - DmaBurstLength2 = 0x00000200, /* Dma burst length = 2 */ - DmaBurstLength1 = 0x00000100, /* Dma burst length = 1 */ - DmaBurstLength0 = 0x00000000, /* Dma burst length = 0 0x00 */ - - DmaDescriptor8Words = 0x00000080, /* Enh Descriptor works 1=> 8 word descriptor 7 0 */ - DmaDescriptor4Words = 0x00000000, /* Enh Descriptor works 0=> 4 word descriptor 7 0 */ - - DmaDescriptorSkip16 = 0x00000040, /* (DSL)Descriptor skip length (no.of dwords) 6:2 RW */ - DmaDescriptorSkip8 = 0x00000020, /* between two unchained descriptors */ - DmaDescriptorSkip4 = 0x00000010, /* */ - DmaDescriptorSkip2 = 0x00000008, /* */ - DmaDescriptorSkip1 = 0x00000004, /* */ - DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ - - DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ - DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ + DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ + DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ + DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ + DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ + DmaBurstLength16 = 0x00001000, /* Dma burst length = 16 */ + DmaBurstLength8 = 0x00000800, /* Dma burst length = 8 */ + DmaBurstLength4 = 0x00000400, /* Dma burst length = 4 */ + DmaBurstLength2 = 0x00000200, /* Dma burst length = 2 */ + DmaBurstLength1 = 0x00000100, /* Dma burst length = 1 */ + DmaBurstLength0 = 0x00000000, /* Dma burst length = 0 0x00 */ + + DmaDescriptor8Words = 0x00000080, /* Enh Descriptor works 1=> 8 word descriptor 7 0 */ + DmaDescriptor4Words = 0x00000000, /* Enh Descriptor works 0=> 4 word descriptor 7 0 */ + + DmaDescriptorSkip16 = 0x00000040, /* (DSL)Descriptor skip length (no.of dwords) 6:2 RW */ + DmaDescriptorSkip8 = 0x00000020, /* between two unchained descriptors */ + DmaDescriptorSkip4 = 0x00000010, /* */ + DmaDescriptorSkip2 = 0x00000008, /* */ + DmaDescriptorSkip1 = 0x00000004, /* */ + DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ + + DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ + DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ - DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ - DmaResetOff = 0x00000000, /* 0 */ + DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ + DmaResetOff = 0x00000000, /* 0 */ }; - /*DmaStatus = 0x0014, CSR5 - Dma status Register */ enum DmaStatusReg { /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ - GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ - GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ - GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ - - DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ - DmaErrorBit1 = 0x01000000, /* (EB)Error bits 0-write trnsf, 1-read transfr 24 RO 0 */ - DmaErrorBit0 = 0x00800000, /* (EB)Error bits 0-Rx DMA, 1-Tx DMA 23 RO 0 */ - - DmaTxState = 0x00700000, /* (TS)Transmit process state 22:20 RO */ - DmaTxStopped = 0x00000000, /* Stopped - Reset or Stop Tx Command issued 000 */ - DmaTxFetching = 0x00100000, /* Running - fetching the Tx descriptor */ - DmaTxWaiting = 0x00200000, /* Running - waiting for status */ - DmaTxReading = 0x00300000, /* Running - reading the data from host memory */ - DmaTxSuspended = 0x00600000, /* Suspended - Tx Descriptor unavailabe */ - DmaTxClosing = 0x00700000, /* Running - closing Rx descriptor */ - - DmaRxState = 0x000E0000, /* (RS)Receive process state 19:17 RO */ - DmaRxStopped = 0x00000000, /* Stopped - Reset or Stop Rx Command issued 000 */ - DmaRxFetching = 0x00020000, /* Running - fetching the Rx descriptor */ - DmaRxWaiting = 0x00060000, /* Running - waiting for packet */ - DmaRxSuspended = 0x00080000, /* Suspended - Rx Descriptor unavailable */ - DmaRxClosing = 0x000A0000, /* Running - closing descriptor */ - DmaRxQueuing = 0x000E0000, /* Running - queuing the recieve frame into host memory */ - - DmaIntNormal = 0x00010000, /* (NIS)Normal interrupt summary 16 RW 0 */ - DmaIntAbnormal = 0x00008000, /* (AIS)Abnormal interrupt summary 15 RW 0 */ - - DmaIntEarlyRx = 0x00004000, /* Early receive interrupt (Normal) RW 0 */ - DmaIntBusError = 0x00002000, /* Fatal bus error (Abnormal) RW 0 */ - DmaIntEarlyTx = 0x00000400, /* Early transmit interrupt (Abnormal) RW 0 */ - DmaIntRxWdogTO = 0x00000200, /* Receive Watchdog Timeout (Abnormal) RW 0 */ - DmaIntRxStopped = 0x00000100, /* Receive process stopped (Abnormal) RW 0 */ - DmaIntRxNoBuffer = 0x00000080, /* Receive buffer unavailable (Abnormal) RW 0 */ - DmaIntRxCompleted = 0x00000040, /* Completion of frame reception (Normal) RW 0 */ - DmaIntTxUnderflow = 0x00000020, /* Transmit underflow (Abnormal) RW 0 */ - DmaIntRcvOverflow = 0x00000010, /* Receive Buffer overflow interrupt RW 0 */ - DmaIntTxJabberTO = 0x00000008, /* Transmit Jabber Timeout (Abnormal) RW 0 */ - DmaIntTxNoBuffer = 0x00000004, /* Transmit buffer unavailable (Normal) RW 0 */ - DmaIntTxStopped = 0x00000002, /* Transmit process stopped (Abnormal) RW 0 */ - DmaIntTxCompleted = 0x00000001, /* Transmit completed (Normal) RW 0 */ + GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ + GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ + GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ + + DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ + DmaErrorBit1 = 0x01000000, /* (EB)Error bits 0-write trnsf, 1-read transfr 24 RO 0 */ + DmaErrorBit0 = 0x00800000, /* (EB)Error bits 0-Rx DMA, 1-Tx DMA 23 RO 0 */ + + DmaTxState = 0x00700000, /* (TS)Transmit process state 22:20 RO */ + DmaTxStopped = 0x00000000, /* Stopped - Reset or Stop Tx Command issued 000 */ + DmaTxFetching = 0x00100000, /* Running - fetching the Tx descriptor */ + DmaTxWaiting = 0x00200000, /* Running - waiting for status */ + DmaTxReading = 0x00300000, /* Running - reading the data from host memory */ + DmaTxSuspended = 0x00600000, /* Suspended - Tx Descriptor unavailabe */ + DmaTxClosing = 0x00700000, /* Running - closing Rx descriptor */ + + DmaRxState = 0x000E0000, /* (RS)Receive process state 19:17 RO */ + DmaRxStopped = 0x00000000, /* Stopped - Reset or Stop Rx Command issued 000 */ + DmaRxFetching = 0x00020000, /* Running - fetching the Rx descriptor */ + DmaRxWaiting = 0x00060000, /* Running - waiting for packet */ + DmaRxSuspended = 0x00080000, /* Suspended - Rx Descriptor unavailable */ + DmaRxClosing = 0x000A0000, /* Running - closing descriptor */ + DmaRxQueuing = 0x000E0000, /* Running - queuing the recieve frame into host memory */ + + DmaIntNormal = 0x00010000, /* (NIS)Normal interrupt summary 16 RW 0 */ + DmaIntAbnormal = 0x00008000, /* (AIS)Abnormal interrupt summary 15 RW 0 */ + + DmaIntEarlyRx = 0x00004000, /* Early receive interrupt (Normal) RW 0 */ + DmaIntBusError = 0x00002000, /* Fatal bus error (Abnormal) RW 0 */ + DmaIntEarlyTx = 0x00000400, /* Early transmit interrupt (Abnormal) RW 0 */ + DmaIntRxWdogTO = 0x00000200, /* Receive Watchdog Timeout (Abnormal) RW 0 */ + DmaIntRxStopped = 0x00000100, /* Receive process stopped (Abnormal) RW 0 */ + DmaIntRxNoBuffer = 0x00000080, /* Receive buffer unavailable (Abnormal) RW 0 */ + DmaIntRxCompleted = 0x00000040, /* Completion of frame reception (Normal) RW 0 */ + DmaIntTxUnderflow = 0x00000020, /* Transmit underflow (Abnormal) RW 0 */ + DmaIntRcvOverflow = 0x00000010, /* Receive Buffer overflow interrupt RW 0 */ + DmaIntTxJabberTO = 0x00000008, /* Transmit Jabber Timeout (Abnormal) RW 0 */ + DmaIntTxNoBuffer = 0x00000004, /* Transmit buffer unavailable (Normal) RW 0 */ + DmaIntTxStopped = 0x00000002, /* Transmit process stopped (Abnormal) RW 0 */ + DmaIntTxCompleted = 0x00000001, /* Transmit completed (Normal) RW 0 */ }; /*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */ enum DmaControlReg { - DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ + DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ - DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */ - DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ + DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */ + DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ - DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ - DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ - DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ - DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ - DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ - DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ - DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ - DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ - DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ + DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ + DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ + DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ + DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ + DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ + DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ + DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ + DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ + DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ - DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ - - DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ - DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ - DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ + + DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ + DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ + DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ - DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ - DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct4K = 0x00000600, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ + DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ + DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct4K = 0x00000600, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ - DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ - DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ - DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ - DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ - DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ - - DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ - DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ + DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ + DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ + DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ + DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ + DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + + DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ + DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ - DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ - DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ - DmaRxStart = 0x00000002, /* (SR)Start/Stop reception 1 RW 0 */ + DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ + DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ + DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ + DmaRxStart = 0x00000002, /* (SR)Start/Stop reception 1 RW 0 */ }; /*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */ enum DmaInterruptReg { - DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ - DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ - - DmaIeEarlyRx = DmaIntEarlyRx , /* Early receive interrupt enable RW 0 */ - DmaIeBusError = DmaIntBusError , /* Fatal bus error enable RW 0 */ - DmaIeEarlyTx = DmaIntEarlyTx , /* Early transmit interrupt enable RW 0 */ - DmaIeRxWdogTO = DmaIntRxWdogTO , /* Receive Watchdog Timeout enable RW 0 */ - DmaIeRxStopped = DmaIntRxStopped , /* Receive process stopped enable RW 0 */ - DmaIeRxNoBuffer = DmaIntRxNoBuffer , /* Receive buffer unavailable enable RW 0 */ - DmaIeRxCompleted = DmaIntRxCompleted, /* Completion of frame reception enable RW 0 */ - DmaIeTxUnderflow = DmaIntTxUnderflow, /* Transmit underflow enable RW 0 */ - - DmaIeRxOverflow = DmaIntRcvOverflow, /* Receive Buffer overflow interrupt RW 0 */ - DmaIeTxJabberTO = DmaIntTxJabberTO , /* Transmit Jabber Timeout enable RW 0 */ - DmaIeTxNoBuffer = DmaIntTxNoBuffer , /* Transmit buffer unavailable enable RW 0 */ - DmaIeTxStopped = DmaIntTxStopped , /* Transmit process stopped enable RW 0 */ - DmaIeTxCompleted = DmaIntTxCompleted, /* Transmit completed enable RW 0 */ + DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ + DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ + + DmaIeEarlyRx = DmaIntEarlyRx , /* Early receive interrupt enable RW 0 */ + DmaIeBusError = DmaIntBusError , /* Fatal bus error enable RW 0 */ + DmaIeEarlyTx = DmaIntEarlyTx , /* Early transmit interrupt enable RW 0 */ + DmaIeRxWdogTO = DmaIntRxWdogTO , /* Receive Watchdog Timeout enable RW 0 */ + DmaIeRxStopped = DmaIntRxStopped , /* Receive process stopped enable RW 0 */ + DmaIeRxNoBuffer = DmaIntRxNoBuffer , /* Receive buffer unavailable enable RW 0 */ + DmaIeRxCompleted = DmaIntRxCompleted, /* Completion of frame reception enable RW 0 */ + DmaIeTxUnderflow = DmaIntTxUnderflow, /* Transmit underflow enable RW 0 */ + + DmaIeRxOverflow = DmaIntRcvOverflow, /* Receive Buffer overflow interrupt RW 0 */ + DmaIeTxJabberTO = DmaIntTxJabberTO , /* Transmit Jabber Timeout enable RW 0 */ + DmaIeTxNoBuffer = DmaIntTxNoBuffer , /* Transmit buffer unavailable enable RW 0 */ + DmaIeTxStopped = DmaIntTxStopped , /* Transmit process stopped enable RW 0 */ + DmaIeTxCompleted = DmaIntTxCompleted, /* Transmit completed enable RW 0 */ }; @@ -818,126 +804,119 @@ DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format enum DmaDescriptorStatus /* status word of DMA descriptor */ { - DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ + DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ - DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ + DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ - DescFrameLengthShift = 16, + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ + DescFrameLengthShift = 16, - DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ + DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ /* DE || OE || IPC || LC || RWT || RE || CE */ - DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ - DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ - DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ - DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ - DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ - DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ - DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ - DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ - DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ - DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ - DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ - DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ + DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ + DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ + DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ + DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ + DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ + DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ + DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ + DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ + DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ + DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ + DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ // DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ - DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ + DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ - DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ - DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ - DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ - DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ - - DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ - - TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ - TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ + DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ + DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ + DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ + DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ + DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ + + DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + + TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ + TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - DescRxTSavail = 0x00000080, /* Time stamp available 7 */ - DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - - DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ - DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ - DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ - DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ - DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ - DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ - DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ - DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ - DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ + DescRxTSavail = 0x00000080, /* Time stamp available 7 */ + DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ + DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ + DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ + DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ + DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ + DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ + DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ + DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ + DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ - DescTxCollShift = 3, + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ + DescTxCollShift = 3, - DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ - DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ - DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ + DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ + DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ /* This explains the RDES1/TDES1 bits layout -------------------------------------------------------------------- RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | -------------------------------------------------------------------- - */ // DmaDescriptorLength length word of DMA descriptor - - - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ - RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ - RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ - - - DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */ - DescSize2Shift = 16, - DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */ - DescSize1Shift = 0, - - + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ + RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ + + DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */ + DescSize2Shift = 16, + DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */ + DescSize1Shift = 0, /* This explains the RDES4 Extended Status bits layout -------------------------------------------------------------------- RDES4 | Extended Status | -------------------------------------------------------------------- */ - DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ - DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ - DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ - DescRxPtpMessageType = 0x00000F00, /* Message Type 11:8 */ - DescRxPtpNo = 0x00000000, /* 0000 => No PTP message received */ - DescRxPtpSync = 0x00000100, /* 0001 => Sync (all clock types) received */ - DescRxPtpFollowUp = 0x00000200, /* 0010 => Follow_Up (all clock types) received */ - DescRxPtpDelayReq = 0x00000300, /* 0011 => Delay_Req (all clock types) received */ - DescRxPtpDelayResp = 0x00000400, /* 0100 => Delay_Resp (all clock types) received */ - DescRxPtpPdelayReq = 0x00000500, /* 0101 => Pdelay_Req (in P to P tras clk) or Announce in Ord and Bound clk */ - DescRxPtpPdelayResp = 0x00000600, /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk */ - DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ - DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ - DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ + DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ + DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ + DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ + DescRxPtpMessageType = 0x00000F00, /* Message Type 11:8 */ + DescRxPtpNo = 0x00000000, /* 0000 => No PTP message received */ + DescRxPtpSync = 0x00000100, /* 0001 => Sync (all clock types) received */ + DescRxPtpFollowUp = 0x00000200, /* 0010 => Follow_Up (all clock types) received */ + DescRxPtpDelayReq = 0x00000300, /* 0011 => Delay_Req (all clock types) received */ + DescRxPtpDelayResp = 0x00000400, /* 0100 => Delay_Resp (all clock types) received */ + DescRxPtpPdelayReq = 0x00000500, /* 0101 => Pdelay_Req (in P to P tras clk) or Announce in Ord and Bound clk */ + DescRxPtpPdelayResp = 0x00000600, /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk */ + DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ + DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ + DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ - DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 + DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 is bypassed */ - DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ - DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 + DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ + DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 error or IP datagram version is not consistent with Ethernet type value */ - DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 + DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 in IPdatagram processed by COE (Rx) */ - DescRxIpPayloadUnknown= 0x00000000, /* Unknown or didnot process IP payload */ - DescRxIpPayloadUDP = 0x00000001, /* UDP */ - DescRxIpPayloadTCP = 0x00000002, /* TCP */ - DescRxIpPayloadICMP = 0x00000003, /* ICMP */ + DescRxIpPayloadUnknown= 0x00000000, /* Unknown or didnot process IP payload */ + DescRxIpPayloadUDP = 0x00000001, /* UDP */ + DescRxIpPayloadTCP = 0x00000002, /* TCP */ + DescRxIpPayloadICMP = 0x00000003, /* ICMP */ }; @@ -965,55 +944,55 @@ DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format */ enum DmaDescriptorStatus /* status word of DMA descriptor */ { - DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ + DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ - DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ + DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ - DescFrameLengthShift = 16, + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ + DescFrameLengthShift = 16, - DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ + DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ /* DE || OE || IPC || LC || RWT || RE || CE */ - DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ - DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ - DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ - DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ - DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ - DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ - DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ - DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ - DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ - DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ - DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ - DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ - DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ - - //Rx Descriptor Checksum Offload engine (type 2) encoding - //DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ - //DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ + DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ + DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ + DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ + DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ + DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ + DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ + DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ + DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ + DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ + DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ + DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + +//Rx Descriptor Checksum Offload engine (type 2) encoding +//DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ +//DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ - DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ - DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ - DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ - DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ - DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ - DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ - DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ - DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ + DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ + DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ + DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ + DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ + DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ + DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ + DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ + DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ - DescTxCollShift = 3, + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ + DescTxCollShift = 3, - DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ - DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ - DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ + DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ + DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ /* This explains the RDES1/TDES1 bits layout @@ -1023,46 +1002,44 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ */ //DmaDescriptorLength length word of DMA descriptor - - DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */ - DescTxLast = 0x40000000, /* (LS)Tx - Last segment of the frame 30 */ - DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */ - DescTxDisableCrc = 0x04000000, /* (DC)Tx - Add CRC disabled (first segment only) 26 */ - - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ - RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ - RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ + DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */ + DescTxLast = 0x40000000, /* (LS)Tx - Last segment of the frame 30 */ + DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */ + DescTxDisableCrc = 0x04000000, /* (DC)Tx - Add CRC disabled (first segment only) 26 */ + + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ + RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ + DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ - TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ - TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ + TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ + TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */ - DescSize2Shift = 11, - DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */ - DescSize1Shift = 0, - - - DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */ + DescSize2Shift = 11, + DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */ + DescSize1Shift = 0, + + DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ }; #endif // Rx Descriptor COE type2 encoding enum RxDescCOEEncode { - RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ - RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ - RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ - RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ - RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ - RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ - RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ - RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ + RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ + RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ + RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ + RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ + RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ + RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ + RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ + RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ }; /********************************************************** @@ -1071,13 +1048,13 @@ enum RxDescCOEEncode enum synopGMACDmaIntEnum /* Intrerrupt types */ { - synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ - synopGMACDmaRxAbnormal = 0x02, /* abnormal receiver interrupt */ - synopGMACDmaRxStopped = 0x04, /* receiver stopped */ - synopGMACDmaTxNormal = 0x08, /* normal transmitter interrupt */ - synopGMACDmaTxAbnormal = 0x10, /* abnormal transmitter interrupt */ - synopGMACDmaTxStopped = 0x20, /* transmitter stopped */ - synopGMACDmaError = 0x80, /* Dma engine error */ + synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ + synopGMACDmaRxAbnormal = 0x02, /* abnormal receiver interrupt */ + synopGMACDmaRxStopped = 0x04, /* receiver stopped */ + synopGMACDmaTxNormal = 0x08, /* normal transmitter interrupt */ + synopGMACDmaTxAbnormal = 0x10, /* abnormal transmitter interrupt */ + synopGMACDmaTxStopped = 0x20, /* transmitter stopped */ + synopGMACDmaError = 0x80, /* Dma engine error */ }; @@ -1087,45 +1064,45 @@ enum RxDescCOEEncode enum InitialRegisters { /* Full-duplex mode with perfect filter on */ - GmacConfigInitFdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable - | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff - | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable - | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + GmacConfigInitFdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff + | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode with perfect filter on */ - GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable - | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff - | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable - | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff + | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode */ // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast // Hash filter. /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */ - GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable - | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff - | GmacPromiscuousModeOff | GmacUcastHashFilterOff, + GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable + | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff + | GmacPromiscuousModeOff | GmacUcastHashFilterOff, /* Full-duplex mode */ - GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, + GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, /* Full-duplex mode */ - GmacGmiiAddrInitFdx = GmiiCsrClk2, + GmacGmiiAddrInitFdx = GmiiCsrClk2, /* Half-duplex mode with perfect filter on */ // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/ - GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable - | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable - | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode with perfect filter on */ - GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable - | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable - | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode */ GmacFrameFilterInitHdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable @@ -1138,39 +1115,37 @@ enum InitialRegisters /* Half-duplex mode */ GmacGmiiAddrInitHdx = GmiiCsrClk2, - - /********************************************** *DMA configurations **********************************************/ - DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip1 | DmaResetOff, + DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip1 | DmaResetOff, // DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff, /* 1000 Mb/s mode */ - DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , + DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , /* 100 Mb/s mode */ - DmaControlInit100 = DmaStoreAndForward, + DmaControlInit100 = DmaStoreAndForward, /* 10 Mb/s mode */ - DmaControlInit10 = DmaStoreAndForward, + DmaControlInit10 = DmaStoreAndForward, /* Interrupt groups */ - DmaIntErrorMask = DmaIntBusError, /* Error */ - DmaIntRxAbnMask = DmaIntRxNoBuffer, /* receiver abnormal interrupt */ - DmaIntRxNormMask = DmaIntRxCompleted, /* receiver normal interrupt */ - DmaIntRxStoppedMask = DmaIntRxStopped, /* receiver stopped */ - DmaIntTxAbnMask = DmaIntTxUnderflow, /* transmitter abnormal interrupt */ - DmaIntTxNormMask = DmaIntTxCompleted, /* transmitter normal interrupt */ - DmaIntTxStoppedMask = DmaIntTxStopped, /* transmitter stopped */ - - DmaIntEnable = DmaIeNormal | DmaIeAbnormal | DmaIntErrorMask -//DmaIntEnable = DmaIeNormal | DmaIntErrorMask - | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask -// | DmaIntRxNormMask | DmaIntRxStoppedMask - | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask, - DmaIntDisable = 0, + DmaIntErrorMask = DmaIntBusError, /* Error */ + DmaIntRxAbnMask = DmaIntRxNoBuffer, /* receiver abnormal interrupt */ + DmaIntRxNormMask = DmaIntRxCompleted, /* receiver normal interrupt */ + DmaIntRxStoppedMask = DmaIntRxStopped, /* receiver stopped */ + DmaIntTxAbnMask = DmaIntTxUnderflow, /* transmitter abnormal interrupt */ + DmaIntTxNormMask = DmaIntTxCompleted, /* transmitter normal interrupt */ + DmaIntTxStoppedMask = DmaIntTxStopped, /* transmitter stopped */ + + DmaIntEnable = DmaIeNormal | DmaIeAbnormal | DmaIntErrorMask +//DmaIntEnable = DmaIeNormal | DmaIntErrorMask + | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask +// | DmaIntRxNormMask | DmaIntRxStoppedMask + | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask, + DmaIntDisable = 0, }; @@ -1180,186 +1155,185 @@ enum InitialRegisters enum MMC_ENABLE { - GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ - GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ - GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ - GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ - GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ + GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ + GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ + GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ + GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ + GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ }; enum MMC_TX { - GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ - GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ - GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ + GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ + GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ + GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ - GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ + GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ - GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ - GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ - GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ - GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ - GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ - GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ - GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ - GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ + GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ + GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ + GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ + GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ + GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ + GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ + GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ + GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ - GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ - GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ + GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ + GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ }; enum MMC_RX { - GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ - GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ - GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ - GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ + GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ + GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ + GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ + GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ - GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ + GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ - GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ - GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ + GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ + GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ - GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ + GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ - GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ - GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ + GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ + GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ + GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ - GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ - GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ - GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ + GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ + GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ + GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ - GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ + GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ }; + enum MMC_IP_RELATED { - GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ - GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ + GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ + GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ - GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ - GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ - GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ + GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ + GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ - GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ + GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ - GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ - GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ - GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ + GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ + GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ + GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ - GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ + GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ - GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ + GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ - GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ + GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ - GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ - GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ + GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ - GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ + GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ - GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ - GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ + GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ - GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ + GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ - GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ + GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ - GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ + GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ }; enum MMC_CNTRL_REG_BIT_DESCRIPTIONS { - GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ - GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ + GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ + GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ - GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ - + GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ }; enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ - GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ - GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ + GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ + GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ + GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ - GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ - GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ - GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ - GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ - GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ - GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ - GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ - GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ - GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ - GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ - GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ + GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ + GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ + GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ + GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ + GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ + GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ + GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ + GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ + GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ + GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ + GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ - GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ - GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ - GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ - GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ - GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ - GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ + GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ + GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ + GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ + GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ + GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ + GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ }; enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ + GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ - GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ - GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ - GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ - GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ - GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ - GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ - GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ - GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ - GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ + GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ + GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ + GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ + GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ + GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ + GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ + GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ + GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ + GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ - GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ - GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ - GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ - GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ - GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ - GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ - GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ - GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ - GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ - GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ - GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ - GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ - + GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ + GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ + GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ + GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ + GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ + GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ + GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ + GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ + GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ + GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ + GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ + GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ }; @@ -1385,45 +1359,40 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS enum GmacPmtCtrlStatusBitDefinition { - GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ - GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ + GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ + GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ - GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ - GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ - GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ - GmacPmtPowerDown = 0x00000001, /* Power Down */ + GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ + GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ + GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ + GmacPmtPowerDown = 0x00000001, /* Power Down */ }; - - - /********************************************************** * IEEE 1588-2008 Precision Time Protocol (PTP) Support **********************************************************/ enum PTPMessageType { - SYNC = 0x0, - Delay_Req = 0x1, - Pdelay_Req = 0x2, - Pdelay_Resp = 0x3, - Follow_up = 0x8, - Delay_Resp = 0x9, - Pdelay_Resp_Follow_Up = 0xA, - Announce = 0xB, - Signaling = 0xC, - Management = 0xD, + SYNC = 0x0, + Delay_Req = 0x1, + Pdelay_Req = 0x2, + Pdelay_Resp = 0x3, + Follow_up = 0x8, + Delay_Resp = 0x9, + Pdelay_Resp_Follow_Up = 0xA, + Announce = 0xB, + Signaling = 0xC, + Management = 0xD, }; - - typedef struct TimeStampStruct { - u32 TSversion; /* PTP Version 1 or PTP version2 */ - u32 TSmessagetype; /* Message type associated with this time stamp */ + u32 TSversion; /* PTP Version 1 or PTP version2 */ + u32 TSmessagetype; /* Message type associated with this time stamp */ - u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ - u32 TSupper32; /* Most significant 32 bit time stamp value */ - u32 TSlower32; /* Least Significat 32 bit time stamp value */ + u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ + u32 TSupper32; /* Most significant 32 bit time stamp value */ + u32 TSlower32; /* Least Significat 32 bit time stamp value */ } TimeStamp; @@ -1441,9 +1410,9 @@ typedef struct TimeStampStruct /* GmacTSControl = 0x0700, Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ enum GmacTSControlReg { - GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ + GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ - GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ + GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ /* TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken 00/01 X 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP @@ -1454,40 +1423,40 @@ enum GmacTSControlReg 11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP */ - GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ - GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ - GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ - GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ + GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ + GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ + GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ + GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ - GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ - GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ - GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ - GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ - GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ - GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ + GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ + GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ + GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ + GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ + GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ + GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ - GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ + GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ - GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ + GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ - GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ - GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ - GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ + GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ + GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ + GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ + GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ - GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ - GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ - GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ + GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ + GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ - GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ + GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ }; /* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ enum GmacTSSubSecIncrReg { - GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ + GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ }; /* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ @@ -1516,7 +1485,6 @@ enum GmacTSStatusReg GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */ }; - /********************************************************** * Time stamp related functions **********************************************************/ diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_plat.h b/bsp/ls2kdev/drivers/net/synopGMAC_plat.h index 9bbcc49ef0..3b6eaca197 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC_plat.h +++ b/bsp/ls2kdev/drivers/net/synopGMAC_plat.h @@ -239,4 +239,4 @@ static bool synopGMACCheckBits(u64 RegBase, u32 RegOffset, u32 BitPos) } } -#endif \ No newline at end of file +#endif diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c index cfb4c6bb3c..54d38d0d3f 100644 --- a/libcpu/mips/gs264/cache.c +++ b/libcpu/mips/gs264/cache.c @@ -67,4 +67,4 @@ rt_base_t rt_hw_cpu_icache_status(void) rt_base_t rt_hw_cpu_dcache_status(void) { return 0; -} \ No newline at end of file +} diff --git a/libcpu/mips/gs264/cpuinit_gcc.S b/libcpu/mips/gs264/cpuinit_gcc.S index bd84663350..592fedd88a 100644 --- a/libcpu/mips/gs264/cpuinit_gcc.S +++ b/libcpu/mips/gs264/cpuinit_gcc.S @@ -19,8 +19,8 @@ .globl rt_cpu_early_init rt_cpu_early_init: - mfc0 t0, CP0_CONFIG - ori t0, 3 - mtc0 t0, CP0_CONFIG + mfc0 t0, CP0_CONFIG + ori t0, 3 + mtc0 t0, CP0_CONFIG ehb - jr ra \ No newline at end of file + jr ra diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c index bfc694ab45..7bed69596a 100644 --- a/libcpu/mips/gs264/mips_mmu.c +++ b/libcpu/mips/gs264/mips_mmu.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-07-26 lizhirui the first version + * 2020-07-26 lizhirui the first version */ #include @@ -205,18 +205,18 @@ uint64_t mmu_tlb_get_bad_vaddr() void tlb_dump() { - uint32_t max_index = mmu_get_max_tlb_index(); - //uint32_t max_index = 10; - uint32_t entry; - tlb_item_t tlb_item; - - for(entry = 0;entry <= max_index;entry++) - { - mmu_tlb_read(entry,&tlb_item); - //mmu_tlb_write_indexed(entry,&tlb_item); - //mmu_tlb_read(entry,&tlb_item); - rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12); - rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c); - rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c); - } -} \ No newline at end of file + uint32_t max_index = mmu_get_max_tlb_index(); + //uint32_t max_index = 10; + uint32_t entry; + tlb_item_t tlb_item; + + for(entry = 0;entry <= max_index;entry++) + { + mmu_tlb_read(entry,&tlb_item); + //mmu_tlb_write_indexed(entry,&tlb_item); + //mmu_tlb_read(entry,&tlb_item); + rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c); + } +} diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h index c0b33ecf89..fcbcef3621 100644 --- a/libcpu/mips/gs264/mips_mmu.h +++ b/libcpu/mips/gs264/mips_mmu.h @@ -5,96 +5,95 @@ * * Change Logs: * Date Author Notes - * 2020-07-26 lizhirui the first version + * 2020-07-26 lizhirui the first version */ - #ifndef __MIPS_MMU_H__ #define __MIPS_MMU_H__ - typedef enum cpu_mode_t - { - CPU_MODE_KERNEL = 0x00, - CPU_MODE_SUPERVISOR = 0x01, - CPU_MODE_USER = 0x02 - }cpu_mode_t; +typedef enum cpu_mode_t +{ + CPU_MODE_KERNEL = 0x00, + CPU_MODE_SUPERVISOR = 0x01, + CPU_MODE_USER = 0x02 +}cpu_mode_t; - typedef enum page_mask_enum_t - { - PAGE_MASK_4KB = 0x00, - PAGE_MASK_16KB = 0x03, - PAGE_MASK_64KB = 0x0F, - PAGE_MASK_256KB = 0x3F, - PAGE_MASK_1MB = 0xFF, - PAGE_MASK_4MB = 0x3FF, - PAGE_MASK_16MB = 0xFFF, - PAGE_MASK_64MB = 0x3FFF, - PAGE_MASK_256MB = 0xFFFF, - PAGE_MASK_1GB = 0x3FFFF - }page_mask_enum_t; +typedef enum page_mask_enum_t +{ + PAGE_MASK_4KB = 0x00, + PAGE_MASK_16KB = 0x03, + PAGE_MASK_64KB = 0x0F, + PAGE_MASK_256KB = 0x3F, + PAGE_MASK_1MB = 0xFF, + PAGE_MASK_4MB = 0x3FF, + PAGE_MASK_16MB = 0xFFF, + PAGE_MASK_64MB = 0x3FFF, + PAGE_MASK_256MB = 0xFFFF, + PAGE_MASK_1GB = 0x3FFFF +}page_mask_enum_t; - typedef struct page_mask_t - { - uint64_t : 11; - uint64_t : 2; - uint64_t mask : 18; - uint64_t : 33; - }page_mask_t; +typedef struct page_mask_t +{ + uint64_t : 11; + uint64_t : 2; + uint64_t mask : 18; + uint64_t : 33; +}page_mask_t; - typedef struct entry_lo_t - { - uint64_t g : 1; - uint64_t v : 1; - uint64_t d : 1; - uint64_t c : 3; - uint64_t pfn : 24; - uint64_t pfnx : 3; - uint64_t : 29; - uint64_t xi : 1; - uint64_t ri : 1; - }entry_lo_t; +typedef struct entry_lo_t +{ + uint64_t g : 1; + uint64_t v : 1; + uint64_t d : 1; + uint64_t c : 3; + uint64_t pfn : 24; + uint64_t pfnx : 3; + uint64_t : 29; + uint64_t xi : 1; + uint64_t ri : 1; +}entry_lo_t; - typedef struct entry_hi_t - { - uint64_t asid : 8; - uint64_t : 5; - uint64_t vpn2 : 27; - uint64_t : 22; - uint64_t r : 2; - }entry_hi_t; +typedef struct entry_hi_t +{ + uint64_t asid : 8; + uint64_t : 5; + uint64_t vpn2 : 27; + uint64_t : 22; + uint64_t r : 2; +}entry_hi_t; - typedef struct tlb_item_t - { - entry_lo_t entry_lo[2]; - entry_hi_t entry_hi; - page_mask_t page_mask; - }tlb_item_t; +typedef struct tlb_item_t +{ + entry_lo_t entry_lo[2]; + entry_hi_t entry_hi; + page_mask_t page_mask; +}tlb_item_t; - #define read_c0_diag() __read_32bit_c0_register($22, 0) - #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) - #define read_c0_badvaddr() __read_64bit_c0_register($8, 0) - #define read_c0_random() __read_32bit_c0_register($1, 0) +#define read_c0_diag() __read_32bit_c0_register($22, 0) +#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) +#define read_c0_badvaddr() __read_64bit_c0_register($8, 0) +#define read_c0_random() __read_32bit_c0_register($1, 0) - #define reg_type_convert(variable,new_type) *((new_type *)(&variable)) - #define lowbit(x) ((x) & (-(x))) +#define reg_type_convert(variable,new_type) *((new_type *)(&variable)) +#define lowbit(x) ((x) & (-(x))) - void mmu_init(); - void mmu_set_cpu_mode(cpu_mode_t cpu_mode); - cpu_mode_t mmu_get_cpu_mode(); - void mmu_clear_tlb(); - void mmu_clear_itlb(); - uint32_t mmu_get_max_tlb_index(); - void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item); - void mmu_tlb_write_random(tlb_item_t *tlb_item); - void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item); - uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index); - void mmu_tlb_item_init(tlb_item_t *tlb_item); - void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global); - uint32_t mmu_tlb_get_random(); - uint32_t mmu_tlb_get_index(); - void mmu_tlb_set_index(uint32_t index); - uint32_t mmu_tlb_is_matched(); - uint64_t mmu_tlb_get_bad_vaddr(); +void mmu_init(); +void mmu_set_cpu_mode(cpu_mode_t cpu_mode); +cpu_mode_t mmu_get_cpu_mode(); +void mmu_clear_tlb(); +void mmu_clear_itlb(); +uint32_t mmu_get_max_tlb_index(); +void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item); +void mmu_tlb_write_random(tlb_item_t *tlb_item); +void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item); +uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index); +void mmu_tlb_item_init(tlb_item_t *tlb_item); +void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global); +uint32_t mmu_tlb_get_random(); +uint32_t mmu_tlb_get_index(); +void mmu_tlb_set_index(uint32_t index); +uint32_t mmu_tlb_is_matched(); +uint64_t mmu_tlb_get_bad_vaddr(); - void tlb_dump(); +void tlb_dump(); #endif \ No newline at end of file diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c index f6c73095d9..b2aed120ae 100644 --- a/libcpu/mips/gs264/mipscfg.c +++ b/libcpu/mips/gs264/mipscfg.c @@ -12,15 +12,15 @@ mips32_core_cfg_t g_mips_core = { - 64, /* icache_line_size */ - 128, /* icache_lines_per_way */ - 4, /* icache_ways */ + 64, /* icache_line_size */ + 128, /* icache_lines_per_way */ + 4, /* icache_ways */ 32768, - 64, /* dcache_line_size */ - 128, /* dcache_lines_per_way */ - 4, /* dcache_ways */ + 64, /* dcache_line_size */ + 128, /* dcache_lines_per_way */ + 4, /* dcache_ways */ 32768, - 64, /* max_tlb_entries */ + 64, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c index b08bdf4c65..b5bedace50 100644 --- a/libcpu/mips/gs264/mmu.c +++ b/libcpu/mips/gs264/mmu.c @@ -21,15 +21,15 @@ void *current_mmu_table = RT_NULL; void *mmu_table_get() { - return current_mmu_table; + return current_mmu_table; } void switch_mmu(void *mmu_table) { - current_mmu_table = mmu_table; + current_mmu_table = mmu_table; mmu_clear_tlb(); - mmu_clear_itlb(); + mmu_clear_itlb(); } /* dump 2nd level page table */ @@ -476,7 +476,7 @@ static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, si static void rt_hw_cpu_tlb_invalidate(void) { mmu_clear_tlb(); - mmu_clear_itlb(); + mmu_clear_itlb(); } #ifdef RT_USING_USERSPACE diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h index f2d4d11bc3..2472bf975f 100644 --- a/libcpu/mips/gs264/mmu.h +++ b/libcpu/mips/gs264/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,21 +14,21 @@ #include #define DESC_SEC (0x2) -#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ -#define MEMWB (3<<2) /* write back, no write allocate */ -#define MEMWT (2<<2) /* write through, no write allocate */ -#define SHAREDEVICE (1<<2) /* shared device */ -#define STRONGORDER (0<<2) /* strong ordered */ -#define XN (1<<4) /* eXecute Never */ +#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ +#define MEMWB (3<<2) /* write back, no write allocate */ +#define MEMWT (2<<2) /* write through, no write allocate */ +#define SHAREDEVICE (1<<2) /* shared device */ +#define STRONGORDER (0<<2) /* strong ordered */ +#define XN (1<<4) /* execute Never */ #ifdef RT_USING_USERSPACE -#define AP_RW (1<<10) /* supervisor=RW, user=No */ -#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ +#define AP_RW (1<<10) /* supervisor=RW, user=No */ +#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ #else -#define AP_RW (3<<10) /* supervisor=RW, user=RW */ -#define AP_RO ((2<<10) /* supervisor=RW, user=RO */ +#define AP_RW (3<<10) /* supervisor=RW, user=RW */ +#define AP_RO ((2<<10) /* supervisor=RW, user=RO */ #endif -#define SHARED (1<<16) /* shareable */ +#define SHARED (1<<16) /* shareable */ #define DOMAIN_FAULT (0x0) #define DOMAIN_CHK (0x1) -- cgit v1.3.1 From a8928c881ed935a1e2a45bb02bd0b2a7fe8d45d4 Mon Sep 17 00:00:00 2001 From: michael Date: Mon, 14 Sep 2020 11:10:44 +0800 Subject: MIPS:fix the RT_EXCEPTION_MAX value from know that cp0_cause's ExcCode have 5 bit filed and the max exception is 32. --- libcpu/mips/common/exception.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'libcpu') diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index 94be475878..3da8ecead6 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -74,7 +74,7 @@ void rt_hw_interrupt_enable(rt_base_t level) /** * exception handle table */ -#define RT_EXCEPTION_MAX 31 +#define RT_EXCEPTION_MAX 32 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; /** -- cgit v1.3.1 From 7f330c7b79ee1d3b2b5c167d67ec6773887b57c3 Mon Sep 17 00:00:00 2001 From: GFWisshit Date: Fri, 16 Oct 2020 11:38:52 +0800 Subject: Add support for architecture sparc-v8 and soc bm3803. --- bsp/bm3803/.config | 456 ++++++++++++++++++++++++ bsp/bm3803/Kconfig | 38 ++ bsp/bm3803/SConscript | 14 + bsp/bm3803/SConstruct | 31 ++ bsp/bm3803/applications/SConscript | 11 + bsp/bm3803/applications/board.c | 58 +++ bsp/bm3803/applications/board.h | 24 ++ bsp/bm3803/applications/main.c | 9 + bsp/bm3803/bm3803.lds | 90 +++++ bsp/bm3803/drivers/SConscript | 22 ++ bsp/bm3803/drivers/uart.c | 174 +++++++++ bsp/bm3803/drivers/uart.h | 20 ++ bsp/bm3803/drivers/uart_reg.h | 12 + bsp/bm3803/rtconfig.h | 156 ++++++++ bsp/bm3803/rtconfig.py | 43 +++ libcpu/sparc-v8/SConscript | 16 + libcpu/sparc-v8/bm3803/SConscript | 17 + libcpu/sparc-v8/bm3803/bm3803.h | 99 ++++++ libcpu/sparc-v8/bm3803/context_gcc.S | 83 +++++ libcpu/sparc-v8/bm3803/interrupt.c | 90 +++++ libcpu/sparc-v8/bm3803/interrupt.h | 20 ++ libcpu/sparc-v8/bm3803/stack.c | 63 ++++ libcpu/sparc-v8/bm3803/start_gcc.S | 664 +++++++++++++++++++++++++++++++++++ libcpu/sparc-v8/bm3803/trap.c | 28 ++ libcpu/sparc-v8/bm3803/vector_gcc.S | 168 +++++++++ libcpu/sparc-v8/common/SConscript | 23 ++ 26 files changed, 2429 insertions(+) create mode 100644 bsp/bm3803/.config create mode 100644 bsp/bm3803/Kconfig create mode 100644 bsp/bm3803/SConscript create mode 100644 bsp/bm3803/SConstruct create mode 100644 bsp/bm3803/applications/SConscript create mode 100644 bsp/bm3803/applications/board.c create mode 100644 bsp/bm3803/applications/board.h create mode 100644 bsp/bm3803/applications/main.c create mode 100644 bsp/bm3803/bm3803.lds create mode 100644 bsp/bm3803/drivers/SConscript create mode 100644 bsp/bm3803/drivers/uart.c create mode 100644 bsp/bm3803/drivers/uart.h create mode 100644 bsp/bm3803/drivers/uart_reg.h create mode 100644 bsp/bm3803/rtconfig.h create mode 100644 bsp/bm3803/rtconfig.py create mode 100644 libcpu/sparc-v8/SConscript create mode 100644 libcpu/sparc-v8/bm3803/SConscript create mode 100644 libcpu/sparc-v8/bm3803/bm3803.h create mode 100644 libcpu/sparc-v8/bm3803/context_gcc.S create mode 100644 libcpu/sparc-v8/bm3803/interrupt.c create mode 100644 libcpu/sparc-v8/bm3803/interrupt.h create mode 100644 libcpu/sparc-v8/bm3803/stack.c create mode 100644 libcpu/sparc-v8/bm3803/start_gcc.S create mode 100644 libcpu/sparc-v8/bm3803/trap.c create mode 100644 libcpu/sparc-v8/bm3803/vector_gcc.S create mode 100644 libcpu/sparc-v8/common/SConscript (limited to 'libcpu') diff --git a/bsp/bm3803/.config b/bsp/bm3803/.config new file mode 100644 index 0000000000..c062cf4890 --- /dev/null +++ b/bsp/bm3803/.config @@ -0,0 +1,456 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +CONFIG_SOC_BM3803=y +CONFIG_RT_USING_UART1=y diff --git a/bsp/bm3803/Kconfig b/bsp/bm3803/Kconfig new file mode 100644 index 0000000000..2e34f6fc57 --- /dev/null +++ b/bsp/bm3803/Kconfig @@ -0,0 +1,38 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example: default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config ENV_DIR + string + option env="ENV_ROOT" + default "/" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_BM3803 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config RT_USING_UART1 + bool "Using RT_USING_UART1" + default y + diff --git a/bsp/bm3803/SConscript b/bsp/bm3803/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/bm3803/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/bm3803/SConstruct b/bsp/bm3803/SConstruct new file mode 100644 index 0000000000..afa8291469 --- /dev/null +++ b/bsp/bm3803/SConstruct @@ -0,0 +1,31 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-bm3803.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/bm3803/applications/SConscript b/bsp/bm3803/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/bm3803/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/bm3803/applications/board.c b/bsp/bm3803/applications/board.c new file mode 100644 index 0000000000..043fceda03 --- /dev/null +++ b/bsp/bm3803/applications/board.c @@ -0,0 +1,58 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#include +#include +#include + +#include "board.h" +#include + +extern int __bss_end; + +static void rt_hw_timer_isr(int vector, void* param) +{ + rt_tick_increase(); + /* timer interrupt cleared by hardware */ +} + +int rt_hw_timer_init(void) +{ + unsigned int counter = 1000000 / RT_TICK_PER_SECOND; + volatile struct lregs *regs = (struct lregs*)PREGS; + + regs->scalercnt = CPU_FREQ / 1000000 - 1; + regs->scalerload = CPU_FREQ / 1000000 - 1; + regs->timercnt2 = counter - 1; + regs->timerload2 = counter - 1; + + rt_hw_interrupt_install(TIMER2_TT, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(TIMER2_TT); + + /* start timer */ + regs->timerctrl2 = 0x7; + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); + +/** + * This function will initialize beaglebone board + */ +void rt_hw_board_init(void) +{ + rt_system_heap_init((void*)&__bss_end, (void*)&__bss_end + 0x01000000); + rt_components_board_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} diff --git a/bsp/bm3803/applications/board.h b/bsp/bm3803/applications/board.h new file mode 100644 index 0000000000..becb93cf3b --- /dev/null +++ b/bsp/bm3803/applications/board.h @@ -0,0 +1,24 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#define CPU_FREQ 90000000 + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/bm3803/applications/main.c b/bsp/bm3803/applications/main.c new file mode 100644 index 0000000000..d77e7a2a8b --- /dev/null +++ b/bsp/bm3803/applications/main.c @@ -0,0 +1,9 @@ +#include +#include +#include + +int main(void) +{ + printf("hello rt-thread\n"); + return 0; +} diff --git a/bsp/bm3803/bm3803.lds b/bsp/bm3803/bm3803.lds new file mode 100644 index 0000000000..e8984325c1 --- /dev/null +++ b/bsp/bm3803/bm3803.lds @@ -0,0 +1,90 @@ +OUTPUT_ARCH(sparc) +SECTIONS +{ + . = 0x40000000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } =0 + __text_end = .; + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(8); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/bsp/bm3803/drivers/SConscript b/bsp/bm3803/drivers/SConscript new file mode 100644 index 0000000000..a630c8a7c4 --- /dev/null +++ b/bsp/bm3803/drivers/SConscript @@ -0,0 +1,22 @@ +import copy +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +# remove no need file. +if GetDepend('RT_USING_LWIP') == False: + src_need_remove = ['dm9000.c'] # need remove file list. + SrcRemove(src, src_need_remove) + +if GetDepend('RT_USING_DFS') == False: + src_need_remove = ['sd.c'] # need remove file list. + SrcRemove(src, src_need_remove) + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/bm3803/drivers/uart.c b/bsp/bm3803/drivers/uart.c new file mode 100644 index 0000000000..bdfe522958 --- /dev/null +++ b/bsp/bm3803/drivers/uart.c @@ -0,0 +1,174 @@ +/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#include +#include +#include + +#include +#include +#include "uart.h" +#include "uart_reg.h" + +struct bm3803_uart +{ + void *uart_base; + int irq; +}; + +static void bm3803_uart_isr(int tt, void* param) +{ + struct bm3803_uart* uart; + struct rt_serial_device *serial; + struct uart_reg* uart_base; + + serial = (struct rt_serial_device*)param; + uart = (struct bm3803_uart *)serial->parent.user_data; + uart_base = uart->uart_base; + + if (uart_base->uartstatus & 0x1) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } +} + +#define NOT_IMPLEMENTED() RT_ASSERT(0) + +static rt_err_t bm3803_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct bm3803_uart* uart; + struct uart_reg* uart_base; + + RT_ASSERT(serial != RT_NULL); + uart = (struct bm3803_uart *)serial->parent.user_data; + RT_ASSERT(uart); + uart_base = uart->uart_base; + + if (cfg->baud_rate == BAUD_RATE_115200) + { + uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 115200)) - 5) / 10); + } + else if (cfg->baud_rate == BAUD_RATE_9600) + { + uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 9600)) - 5) / 10); + } + else + { + NOT_IMPLEMENTED(); + } + + uart_base->uartctrl |= 0x3; + + return RT_EOK; +} + +static rt_err_t bm3803_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct bm3803_uart* uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct bm3803_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + rt_hw_interrupt_mask(uart->irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + rt_hw_interrupt_umask(uart->irq); + break; + } + + return RT_EOK; +} + +static int bm3803_putc(struct rt_serial_device *serial, char c) +{ + struct bm3803_uart* uart; + struct uart_reg* uart_base; + + RT_ASSERT(serial != RT_NULL); + uart = (struct bm3803_uart *)serial->parent.user_data; + uart_base = uart->uart_base; + + while (!(uart_base->uartstatus & 0x4)); + uart_base->uartdata = c; + + return 1; +} + +static int bm3803_getc(struct rt_serial_device *serial) +{ + int ch; + struct bm3803_uart* uart; + struct uart_reg* uart_base; + + RT_ASSERT(serial != RT_NULL); + uart = (struct bm3803_uart *)serial->parent.user_data; + uart_base = uart->uart_base; + + ch = -1; + if (uart_base->uartstatus & 0x1) + { + ch = uart_base->uartdata; + } + + return ch; +} + +static const struct rt_uart_ops bm3803_uart_ops = +{ + bm3803_configure, + bm3803_control, + bm3803_putc, + bm3803_getc, +}; + +/* UART device driver structure */ +#ifdef RT_USING_UART1 +struct bm3803_uart uart1 = +{ + (void*)UART1_BASE, + UART1_TT, +}; +struct rt_serial_device serial1; +#endif + +int rt_hw_serial_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef RT_USING_UART1 + volatile struct lregs *regs = (struct lregs*)PREGS; + serial1.ops = &bm3803_uart_ops; + serial1.config = config; + /* configure gpio direction */ + regs->piodir |= (1 << 15); + regs->piodir &= ~(1 << 14); + /* enable RX interrupt */ + regs->uartctrl1 = 0; + regs->uartctrl1 |= 0x4; + /* install ISR */ + rt_hw_interrupt_install(uart1.irq, bm3803_uart_isr, &serial1, "uart1"); + rt_hw_interrupt_mask(uart1.irq); + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + &uart1); +#endif + return 0; +} +INIT_BOARD_EXPORT(rt_hw_serial_init); diff --git a/bsp/bm3803/drivers/uart.h b/bsp/bm3803/drivers/uart.h new file mode 100644 index 0000000000..46a7df5d89 --- /dev/null +++ b/bsp/bm3803/drivers/uart.h @@ -0,0 +1,20 @@ +/* + * File : serial.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#ifndef __SERIAL_H__ +#define __SERIAL_H__ + +int rt_hw_serial_init(void); + +#endif diff --git a/bsp/bm3803/drivers/uart_reg.h b/bsp/bm3803/drivers/uart_reg.h new file mode 100644 index 0000000000..c0911149df --- /dev/null +++ b/bsp/bm3803/drivers/uart_reg.h @@ -0,0 +1,12 @@ +#ifndef SERIAL_REG_H +#define SERIAL_REG_H + +struct uart_reg +{ + unsigned int uartdata; + unsigned int uartstatus; + unsigned int uartctrl; + unsigned int uartscaler; +}; + +#endif /* end of include guard: SERIAL_REG_H */ diff --git a/bsp/bm3803/rtconfig.h b/bsp/bm3803/rtconfig.h new file mode 100644 index 0000000000..001e275191 --- /dev/null +++ b/bsp/bm3803/rtconfig.h @@ -0,0 +1,156 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 4096 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40003 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_BM3803 +#define RT_USING_UART1 + +#endif diff --git a/bsp/bm3803/rtconfig.py b/bsp/bm3803/rtconfig.py new file mode 100644 index 0000000000..1a382b4891 --- /dev/null +++ b/bsp/bm3803/rtconfig.py @@ -0,0 +1,43 @@ +import os + +# toolchains options +ARCH='sparc-v8' +CPU='bm3803' +CROSS_TOOL='gcc' + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\97981\Downloads\bcc-2.1.1-gcc\bin' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'sparc-gaisler-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=v8 -nostartfiles' + #DEVICE = ' ' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -Wl,-Map=rtthread-bm3803.map -T bm3803.lds -Ttext=0x40000000' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -Wall' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2 -Wall' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ + SIZE + ' $TARGET \n' diff --git a/libcpu/sparc-v8/SConscript b/libcpu/sparc-v8/SConscript new file mode 100644 index 0000000000..f6ea13fb91 --- /dev/null +++ b/libcpu/sparc-v8/SConscript @@ -0,0 +1,16 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() + +# add common code files +group = SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/sparc-v8/bm3803/SConscript b/libcpu/sparc-v8/bm3803/SConscript new file mode 100644 index 0000000000..1e96ff5837 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/SConscript @@ -0,0 +1,17 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/sparc-v8/bm3803/bm3803.h b/libcpu/sparc-v8/bm3803/bm3803.h new file mode 100644 index 0000000000..a90663f199 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/bm3803.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ +#ifndef __BM3803_H__ +#define __BM3803_H__ + +struct lregs +{ + /* address = 0x80000000 */ + unsigned int memcfg1; /* 0x00 */ + unsigned int memcfg2; + unsigned int memcfg3; + unsigned int failaddr; + + unsigned int memstatus; /* 0x10 */ + unsigned int cachectrl; + unsigned int powerdown; + unsigned int writeprot1; + + unsigned int writeprot2; /* 0x20 */ + unsigned int pcr; + unsigned int dummy2; + unsigned int dummy3; + + unsigned int dummy4; /* 0x30 */ + unsigned int dummy5; + unsigned int dummy6; + unsigned int dummy7; + + unsigned int timercnt1; /* 0x40 */ + unsigned int timerload1; + unsigned int timerctrl1; + unsigned int wdog; + + unsigned int timercnt2; /* 0x50 */ + unsigned int timerload2; + unsigned int timerctrl2; + unsigned int dummy8; + + unsigned int scalercnt; /* 0x60 */ + unsigned int scalerload; + unsigned int dummy9; + unsigned int dummy10; + + unsigned int uartdata1; /* 0x70 */ + unsigned int uartstatus1; + unsigned int uartctrl1; + unsigned int uartscaler1; + + unsigned int uartdata2; /* 0x80 */ + unsigned int uartstatus2; + unsigned int uartctrl2; + unsigned int uartscaler2; + + unsigned int irqmask; /* 0x90 */ + unsigned int irqpend; + unsigned int irqforce; + unsigned int irqclear; + + unsigned int piodata; /* 0xA0 */ + unsigned int piodir; + unsigned int pioirq; + unsigned int dummy11; + + unsigned int imask2; /* 0xB0 */ + unsigned int ipend2; + unsigned int istat2; + unsigned int dummy12; + + unsigned int dummy13; /* 0xC0 */ + unsigned int dcomstatus; + unsigned int dcomctrl; + unsigned int dcomscaler; + + unsigned int dummy14; /* 0xD0 */ + unsigned int dummy15; + unsigned int dummy16; + unsigned int dummy17; + + unsigned int uartdata3; /* 0xE0 */ + unsigned int uartstatus3; + unsigned int uartctrl3; + unsigned int uartscaler3; +}; + +#define PREGS 0x80000000 + +#define UART1_BASE (PREGS + 0x70) + +#define TIMER2_TT 0x19 +#define UART1_TT 0x13 + +#endif diff --git a/libcpu/sparc-v8/bm3803/context_gcc.S b/libcpu/sparc-v8/bm3803/context_gcc.S new file mode 100644 index 0000000000..c0344a81d5 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/context_gcc.S @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#define SPARC_PSR_PIL_MASK 0x00000F00 +#define SPARC_PSR_ET_MASK 0x00000020 + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mov %psr, %o0 + or %o0, SPARC_PSR_PIL_MASK, %o1 + mov %o1, %psr + nop + nop + nop + retl + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mov %o0, %psr + nop + nop + nop + retl + nop + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * o0 --> from + * o1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + ta 2 + retl + nop + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * o0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + mov %o0, %o1 + ta 3 + retl + nop + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + set rt_thread_switch_interrupt_flag, %o2 + ld [%o2], %o3 + cmp %o3, 1 + be _reswitch + nop + mov 1, %o3 + st %o3, [%o2] + set rt_interrupt_from_thread, %o2 + st %o0, [%o2] +_reswitch: + set rt_interrupt_to_thread, %o2 + st %o1, [%o2] + retl + nop diff --git a/libcpu/sparc-v8/bm3803/interrupt.c b/libcpu/sparc-v8/bm3803/interrupt.c new file mode 100644 index 0000000000..e3f9b5b3de --- /dev/null +++ b/libcpu/sparc-v8/bm3803/interrupt.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#include +#include + +#include "bm3803.h" +#include "interrupt.h" + +#define MAX_HANDLERS 256 + +extern volatile rt_uint8_t rt_interrupt_nest; +struct rt_irq_desc isr_table[MAX_HANDLERS]; +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + /* init exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + if (vector > 0x1F || vector < 0x11) + return; + volatile struct lregs *regs = (struct lregs*)PREGS; + regs->irqmask &= ~(1 << (vector - 0x10)); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + if (vector > 0x1F || vector < 0x11) + return; + volatile struct lregs *regs = (struct lregs*)PREGS; + regs->irqmask |= 1 << (vector - 0x10); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if(vector < MAX_HANDLERS || vector >= 0) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} diff --git a/libcpu/sparc-v8/bm3803/interrupt.h b/libcpu/sparc-v8/bm3803/interrupt.h new file mode 100644 index 0000000000..7632195e70 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/interrupt.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +void rt_hw_interrupt_control(int vector, int priority, int route); +int rt_hw_interrupt_get_active(int fiq_irq); +void rt_hw_interrupt_ack(int fiq_irq); +void rt_hw_interrupt_trigger(int vector); +void rt_hw_interrupt_clear(int vector); + +#endif diff --git a/libcpu/sparc-v8/bm3803/stack.c b/libcpu/sparc-v8/bm3803/stack.c new file mode 100644 index 0000000000..3563692cdd --- /dev/null +++ b/libcpu/sparc-v8/bm3803/stack.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ +#include + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + int window_index; + int register_index; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + + stk -= 24; + stk -= 8; + + for (register_index = 0; register_index != 8; register_index++) + stk[register_index] = 0xdeadbeef; + + for (window_index = 0; window_index != 8; window_index++) + { + stk -= 16; + for (register_index = 0; register_index != 16; register_index++) + stk[register_index] = 0xdeadbeef; + if (window_index == 0) + { + stk[8] = (rt_uint32_t)parameter; + stk[15] = (rt_uint32_t)texit - 8; + } + } + + stk -= 34; + for (register_index = 0; register_index != 34; register_index++) + stk[register_index] = 0; + + stk -= 4; + stk[0] = (rt_uint32_t)tentry; //pc + stk[1] = (rt_uint32_t)tentry + 4; //npc + stk[2] = 0x10C7; //psr + stk[3] = 0x2; //wim + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/libcpu/sparc-v8/bm3803/start_gcc.S b/libcpu/sparc-v8/bm3803/start_gcc.S new file mode 100644 index 0000000000..0f87aa17db --- /dev/null +++ b/libcpu/sparc-v8/bm3803/start_gcc.S @@ -0,0 +1,664 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#define PSR_INIT 0x10C0 +#define PREGS 0x80000000 +#define IMASK 0x90 +#define ICLEAR 0x9c +#define NWINDOWS 8 +#define CPU_INTERRUPT_FRAME_SIZE (0x60 + 0x50 + 34 * 4) +#define SPARC_PSR_PIL_MASK 0x00000F00 +#define SPARC_PSR_ET_MASK 0x00000020 +#define SPARC_PSR_CWP_MASK 0x07 + +.text + +.globl system_vectors +.globl _reset +.globl _context_switch + +_reset: + mov %g0, %asr16 + mov %g0, %asr17 + nop + nop + nop + + set PSR_INIT, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %wim + nop + nop + nop + + mov %g0, %g1 + mov %g0, %g2 + mov %g0, %g3 + mov %g0, %g4 + mov %g0, %g5 + mov %g0, %g6 + mov %g0, %g7 + + mov 0x8, %g1 +1: + mov %g0, %l0 + mov %g0, %l1 + mov %g0, %l2 + mov %g0, %l3 + mov %g0, %l4 + mov %g0, %l5 + mov %g0, %l6 + mov %g0, %l7 + mov %g0, %i0 + mov %g0, %i1 + mov %g0, %i2 + mov %g0, %i3 + mov %g0, %i4 + mov %g0, %i5 + mov %g0, %i6 + mov %g0, %i7 + subcc %g1, 1, %g1 + save + bne 1b + nop + + set 2, %g1 + mov %g1, %wim + nop + nop + nop + + sethi %hi(system_vectors), %g1 + mov %g1, %tbr + nop + nop + nop + + set PREGS, %g1 + set 0xffff, %g2 + st %g2, [%g1 + ICLEAR] + st %g0, [%g1 + IMASK] + + set 0x7C47907F, %g2 + st %g2, [%g1 + 4] + + set PSR_INIT | 0x20, %g1 + mov %g1, %psr + nop + nop + nop + + set _fsrinit, %g1 + ld [%g1], %fsr + nop + nop + nop + + set _fpdata, %g1 + ldd [%g1], %f0 + ldd [%g1], %f2 + ldd [%g1], %f4 + ldd [%g1], %f6 + ldd [%g1], %f8 + ldd [%g1], %f10 + ldd [%g1], %f12 + ldd [%g1], %f14 + ldd [%g1], %f16 + ldd [%g1], %f18 + ldd [%g1], %f20 + ldd [%g1], %f22 + ldd [%g1], %f24 + ldd [%g1], %f26 + ldd [%g1], %f28 + ldd [%g1], %f30 + + set __bss_start, %g2 + set __bss_end, %g3 + mov %g0, %g1 +bss_loop: + std %g0, [%g2] + add %g2, 8, %g2 + cmp %g2, %g3 + bleu,a bss_loop + nop + + set 0x401FFF00, %g1 + mov %g1, %sp + + /* start RT-Thread Kernel */ + call rtthread_startup + nop + +/* +l0 = psr +l1 = pc +l2 = npc +l3 = tbr +*/ +.globl _ISR_Handler +_ISR_Handler: + mov %g4, %l4 + mov %g5, %l5 + mov %wim, %g4 + srl %g4, %l0, %g5 + cmp %g5, 1 + bne dont_do_the_window + nop + srl %g4, 1, %g5 + sll %g4, NWINDOWS - 1, %g4 + or %g4, %g5, %g4 + save + mov %g4, %wim + nop + nop + nop + + std %l0, [%sp + 0x00] + std %l2, [%sp + 0x08] + std %l4, [%sp + 0x10] + std %l6, [%sp + 0x18] + + std %i0, [%sp + 0x20] + std %i2, [%sp + 0x28] + std %i4, [%sp + 0x30] + std %i6, [%sp + 0x38] + + restore + nop + +dont_do_the_window: + sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp + + std %l0, [%sp + 0x60] + st %l2, [%sp + 0x68] + st %g1, [%sp + 0x6c] + std %g2, [%sp + 0x70] + std %l4, [%sp + 0x78] + std %g6, [%sp + 0x80] + + std %i0, [%sp + 0x88] + std %i2, [%sp + 0x90] + std %i4, [%sp + 0x98] + std %i6, [%sp + 0xA0] + + mov %y, %g1 + st %g1, [%sp + 0xA8] + st %l6, [%sp + 0xAc] + + std %f0, [%sp + 0xB0 + 8 * 0x0] + std %f2, [%sp + 0xB0 + 8 * 0x1] + std %f4, [%sp + 0xB0 + 8 * 0x2] + std %f6, [%sp + 0xB0 + 8 * 0x3] + std %f8, [%sp + 0xB0 + 8 * 0x4] + std %f10, [%sp + 0xB0 + 8 * 0x5] + std %f12, [%sp + 0xB0 + 8 * 0x6] + std %f14, [%sp + 0xB0 + 8 * 0x7] + std %f16, [%sp + 0xB0 + 8 * 0x8] + std %f18, [%sp + 0xB0 + 8 * 0x9] + std %f20, [%sp + 0xB0 + 8 * 0xA] + std %f22, [%sp + 0xB0 + 8 * 0xB] + std %f24, [%sp + 0xB0 + 8 * 0xC] + std %f26, [%sp + 0xB0 + 8 * 0xD] + std %f28, [%sp + 0xB0 + 8 * 0xE] + std %f30, [%sp + 0xB0 + 8 * 0xF] + st %fsr, [%sp + 0xB0 + 8 * 0x10] + + mov %l0, %g5 + or %g5, SPARC_PSR_PIL_MASK, %g5 + wr %g5, SPARC_PSR_ET_MASK, %psr + nop + nop + nop + + call rt_interrupt_enter + nop + + and %l3, 0x0FF0, %l3 + srl %l3, 4, %o0 + mov %sp, %o1 + + call rt_hw_trap + nop + + call rt_interrupt_leave + nop + + mov %l0, %psr + nop + nop + nop + + ld [%sp + 0xA8], %l5 + mov %l5, %y + ldd [%sp + 0x60], %l0 + ld [%sp + 0x68], %l2 + + ld [%sp + 0x6c], %g1 + ldd [%sp + 0x70], %g2 + ldd [%sp + 0x78], %g4 + ldd [%sp + 0x80], %g6 + + ldd [%sp + 0x88], %i0 + ldd [%sp + 0x90], %i2 + ldd [%sp + 0x98], %i4 + ldd [%sp + 0xA0], %i6 + + ldd [%sp + 0xB0 + 8 * 0x0], %f0 + ldd [%sp + 0xB0 + 8 * 0x1], %f2 + ldd [%sp + 0xB0 + 8 * 0x2], %f4 + ldd [%sp + 0xB0 + 8 * 0x3], %f6 + ldd [%sp + 0xB0 + 8 * 0x4], %f8 + ldd [%sp + 0xB0 + 8 * 0x5], %f10 + ldd [%sp + 0xB0 + 8 * 0x6], %f12 + ldd [%sp + 0xB0 + 8 * 0x7], %f14 + ldd [%sp + 0xB0 + 8 * 0x8], %f16 + ldd [%sp + 0xB0 + 8 * 0x9], %f18 + ldd [%sp + 0xB0 + 8 * 0xA], %f20 + ldd [%sp + 0xB0 + 8 * 0xB], %f22 + ldd [%sp + 0xB0 + 8 * 0xC], %f24 + ldd [%sp + 0xB0 + 8 * 0xD], %f26 + ldd [%sp + 0xB0 + 8 * 0xE], %f28 + ldd [%sp + 0xB0 + 8 * 0xF], %f30 + ld [%sp + 0xB0 + 8 * 0x10], %fsr + nop + nop + nop + + mov %wim, %l4 + add %l0, 1, %l6 + and %l6, SPARC_PSR_CWP_MASK, %l6 + srl %l4, %l6, %l5 + cmp %l5, 1 + bne good_task_window + nop + sll %l4, 1, %l5 + srl %l4, NWINDOWS - 1, %l4 + or %l4, %l5, %l4 + mov %l4, %wim + nop + nop + nop + + restore + ldd [%sp + 0], %l0 ! Restore window from the stack + ldd [%sp + 8], %l2 + ldd [%sp + 16], %l4 + ldd [%sp + 24], %l6 + ldd [%sp + 32], %i0 + ldd [%sp + 40], %i2 + ldd [%sp + 48], %i4 + ldd [%sp + 56], %i6 + save + +good_task_window: + set rt_thread_switch_interrupt_flag, %l4 + ld [%l4], %l5 + cmp %l5, 1 + be rt_hw_context_switch_interrupt_do + nop + + mov %l0, %psr + nop + nop + nop + + jmp %l1 + rett %l2 + +rt_hw_context_switch_interrupt_do: + st %g0, [%l4] + + sub %fp, 0x20, %sp + std %g0, [%sp + 0x00] + std %g2, [%sp + 0x08] + std %g4, [%sp + 0x10] + std %g6, [%sp + 0x18] + + mov %sp, %g3 + mov %l1, %g4 + mov %l2, %g5 + mov %l0, %g6 + mov %wim, %g7 + + mov %g0, %wim + nop + nop + nop + set 0xFFFFFFF8, %g1 + and %g1, %g6, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %g1 +save_loop: + save + sub %g3, 0x40, %g3 + std %l0, [%g3 + 0x00] + std %l2, [%g3 + 0x08] + std %l4, [%g3 + 0x10] + std %l6, [%g3 + 0x18] + std %i0, [%g3 + 0x20] + std %i2, [%g3 + 0x28] + std %i4, [%g3 + 0x30] + std %i6, [%g3 + 0x38] + inc %g1 + cmp %g1, NWINDOWS + bne save_loop + nop + + sub %g3, 0x88, %g3 + std %f0, [%g3 + 0x00] + std %f2, [%g3 + 0x08] + std %f4, [%g3 + 0x10] + std %f6, [%g3 + 0x18] + std %f8, [%g3 + 0x20] + std %f10, [%g3 + 0x28] + std %f12, [%g3 + 0x30] + std %f14, [%g3 + 0x38] + std %f16, [%g3 + 0x40] + std %f18, [%g3 + 0x48] + std %f20, [%g3 + 0x50] + std %f22, [%g3 + 0x58] + std %f24, [%g3 + 0x60] + std %f26, [%g3 + 0x68] + std %f28, [%g3 + 0x70] + std %f30, [%g3 + 0x78] + mov %y, %g1 + st %g1, [%g3 + 0x80] + st %fsr, [%g3 + 0x84] + + sub %g3, 0x10, %g3 + std %g4, [%g3 + 0x00] + std %g6, [%g3 + 0x08] + + set rt_interrupt_from_thread, %g1 + ld [%g1], %g2 + st %g3, [%g2] + + set rt_interrupt_to_thread, %g1 + ld [%g1], %g1 + ld [%g1], %g3 + + ldd [%g3 + 0x00], %g4 + ldd [%g3 + 0x08], %g6 + add %g3, 0x10, %g3 + + ldd [%g3 + 0x00], %f0 + ldd [%g3 + 0x08], %f2 + ldd [%g3 + 0x10], %f4 + ldd [%g3 + 0x18], %f6 + ldd [%g3 + 0x20], %f8 + ldd [%g3 + 0x28], %f10 + ldd [%g3 + 0x30], %f12 + ldd [%g3 + 0x38], %f14 + ldd [%g3 + 0x40], %f16 + ldd [%g3 + 0x48], %f18 + ldd [%g3 + 0x50], %f20 + ldd [%g3 + 0x58], %f22 + ldd [%g3 + 0x60], %f24 + ldd [%g3 + 0x68], %f26 + ldd [%g3 + 0x70], %f28 + ldd [%g3 + 0x78], %f30 + ld [%g3 + 0x80], %g1 + mov %g1, %y + ld [%g3 + 0x84], %fsr + add %g3, 0x88, %g3 + + set NWINDOWS - 1, %g1 + or %g1, %g6, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %g1 +restore_loop: + restore + ldd [%g3 + 0x00], %l0 + ldd [%g3 + 0x08], %l2 + ldd [%g3 + 0x10], %l4 + ldd [%g3 + 0x18], %l6 + ldd [%g3 + 0x20], %i0 + ldd [%g3 + 0x28], %i2 + ldd [%g3 + 0x30], %i4 + ldd [%g3 + 0x38], %i6 + add %g3, 0x40, %g3 + inc %g1 + cmp %g1, NWINDOWS + bne restore_loop + nop + + mov %g6, %psr + nop + nop + nop + mov %g7, %wim + nop + nop + nop + + mov %g4, %l1 + mov %g5, %l2 + mov %g3, %sp + + ldd [%sp + 0x00], %g0 + ldd [%sp + 0x08], %g2 + ldd [%sp + 0x10], %g4 + ldd [%sp + 0x18], %g6 + add %sp, 0x20, %fp + jmp %l1 + rett %l2 + +/* +l0 = psr +l1 = pc +l2 = npc +l3 = tbr +*/ +_context_switch: + mov %l2, %l1 + add %l2, 4, %l2 + + mov %g4, %l4 + mov %g5, %l5 + mov %wim, %g4 + srl %g4, %l0, %g5 + cmp %g5, 1 + bne good_window + nop + srl %g4, 1, %g5 + sll %g4, NWINDOWS - 1, %g4 + or %g4, %g5, %g4 + save + mov %g4, %wim + nop + nop + nop + + std %l0, [%sp + 0x00] + std %l2, [%sp + 0x08] + std %l4, [%sp + 0x10] + std %l6, [%sp + 0x18] + + std %i0, [%sp + 0x20] + std %i2, [%sp + 0x28] + std %i4, [%sp + 0x30] + std %i6, [%sp + 0x38] + + restore + nop + +good_window: + and %l3, 0x0FF0, %l3 + srl %l3, 4, %l4 + cmp %l4, 0x82 + bne switch_to + nop + + sub %fp, 0x20, %sp + std %g0, [%sp + 0x00] + std %g2, [%sp + 0x08] + std %g4, [%sp + 0x10] + std %g6, [%sp + 0x18] + + mov %sp, %g3 + mov %l1, %g4 + mov %l2, %g5 + mov %l0, %g6 + mov %wim, %g7 + + mov %g0, %wim + nop + nop + nop + set 0xFFFFFFF8, %g1 + and %g1, %g6, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %g1 +save_window: + save + sub %g3, 0x40, %g3 + std %l0, [%g3 + 0x00] + std %l2, [%g3 + 0x08] + std %l4, [%g3 + 0x10] + std %l6, [%g3 + 0x18] + std %i0, [%g3 + 0x20] + std %i2, [%g3 + 0x28] + std %i4, [%g3 + 0x30] + std %i6, [%g3 + 0x38] + inc %g1 + cmp %g1, NWINDOWS + bne save_window + nop + + sub %g3, 0x88, %g3 + std %f0, [%g3 + 0x00] + std %f2, [%g3 + 0x08] + std %f4, [%g3 + 0x10] + std %f6, [%g3 + 0x18] + std %f8, [%g3 + 0x20] + std %f10, [%g3 + 0x28] + std %f12, [%g3 + 0x30] + std %f14, [%g3 + 0x38] + std %f16, [%g3 + 0x40] + std %f18, [%g3 + 0x48] + std %f20, [%g3 + 0x50] + std %f22, [%g3 + 0x58] + std %f24, [%g3 + 0x60] + std %f26, [%g3 + 0x68] + std %f28, [%g3 + 0x70] + std %f30, [%g3 + 0x78] + mov %y, %g1 + st %g1, [%g3 + 0x80] + st %fsr, [%g3 + 0x84] + + sub %g3, 0x10, %g3 + std %g4, [%g3 + 0x00] + std %g6, [%g3 + 0x08] + + mov %g6, %psr + nop + nop + nop + + st %g3, [%i0] +switch_to: + mov %g0, %wim + nop + nop + nop + ld [%i1], %g3 + + ldd [%g3 + 0x00], %g4 + ldd [%g3 + 0x08], %g6 + add %g3, 0x10, %g3 + + ldd [%g3 + 0x00], %f0 + ldd [%g3 + 0x08], %f2 + ldd [%g3 + 0x10], %f4 + ldd [%g3 + 0x18], %f6 + ldd [%g3 + 0x20], %f8 + ldd [%g3 + 0x28], %f10 + ldd [%g3 + 0x30], %f12 + ldd [%g3 + 0x38], %f14 + ldd [%g3 + 0x40], %f16 + ldd [%g3 + 0x48], %f18 + ldd [%g3 + 0x50], %f20 + ldd [%g3 + 0x58], %f22 + ldd [%g3 + 0x60], %f24 + ldd [%g3 + 0x68], %f26 + ldd [%g3 + 0x70], %f28 + ldd [%g3 + 0x78], %f30 + ld [%g3 + 0x80], %g1 + mov %g1, %y + ld [%g3 + 0x84], %fsr + add %g3, 0x88, %g3 + + set NWINDOWS - 1, %g1 + or %g1, %g6, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %g1 +restore_window: + restore + ldd [%g3 + 0x00], %l0 + ldd [%g3 + 0x08], %l2 + ldd [%g3 + 0x10], %l4 + ldd [%g3 + 0x18], %l6 + ldd [%g3 + 0x20], %i0 + ldd [%g3 + 0x28], %i2 + ldd [%g3 + 0x30], %i4 + ldd [%g3 + 0x38], %i6 + add %g3, 0x40, %g3 + inc %g1 + cmp %g1, NWINDOWS + bne restore_window + nop + + mov %g6, %psr + nop + nop + nop + mov %g7, %wim + nop + nop + nop + + mov %g4, %l1 + mov %g5, %l2 + mov %g3, %sp + + ldd [%sp + 0x00], %g0 + ldd [%sp + 0x08], %g2 + ldd [%sp + 0x10], %g4 + ldd [%sp + 0x18], %g6 + add %sp, 0x20, %fp + jmp %l1 + rett %l2 + +.data +.align 8 +_fpdata: + .word 0, 0 +_fsrinit: + .word 0 diff --git a/libcpu/sparc-v8/bm3803/trap.c b/libcpu/sparc-v8/bm3803/trap.c new file mode 100644 index 0000000000..05a0416dfa --- /dev/null +++ b/libcpu/sparc-v8/bm3803/trap.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#include +#include + +extern struct rt_irq_desc isr_table[]; + +void rt_hw_trap(int tt, unsigned int *sp) +{ + void *param; + rt_isr_handler_t isr_func; + + /* get interrupt service routine */ + isr_func = isr_table[tt].handler; + param = isr_table[tt].param; + + /* turn to interrupt service routine */ + if (isr_func != RT_NULL) + isr_func(tt, param); +} diff --git a/libcpu/sparc-v8/bm3803/vector_gcc.S b/libcpu/sparc-v8/bm3803/vector_gcc.S new file mode 100644 index 0000000000..0d243bee33 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/vector_gcc.S @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#define TRAPL(H) mov %g0, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop; +#define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop; +#define TRAP_ENTRY(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); mov %tbr, %l3; +#define BAD_TRAP ta 0; nop; nop; nop; +#define SOFT_TRAP BAD_TRAP +#define NWINDOWS 8 + +.section .vectors, "ax" + +.globl _ISR_Handler +.globl _window_overflow +.globl _window_underflow +.globl _reset +.globl _context_switch + +.globl system_vectors +system_vectors: + TRAPL(_reset); ! 00 reset trap + BAD_TRAP; ! 01 instruction_access_exception + BAD_TRAP; ! 02 illegal_instruction + BAD_TRAP; ! 03 priveleged_instruction + BAD_TRAP; + TRAP(_window_overflow); ! 05 window_overflow + TRAP(_window_underflow); ! 06 window_underflow + BAD_TRAP; ! 07 memory_add0ress_not_aligned + BAD_TRAP; ! 08 fp_exception + BAD_TRAP; ! 09 data_access_exception + BAD_TRAP; ! 0A tag_overflow + BAD_TRAP; ! 0B undefined + BAD_TRAP; ! 0C undefined + BAD_TRAP; ! 0D undefined + BAD_TRAP; ! 0E undefined + BAD_TRAP; ! 0F undefined + BAD_TRAP; ! 10 undefined + + /* Interrupt entries */ + TRAP_ENTRY(_ISR_Handler) ! 11 interrupt level 1 + TRAP_ENTRY(_ISR_Handler) ! 12 interrupt level 2 + TRAP_ENTRY(_ISR_Handler) ! 13 interrupt level 3 + TRAP_ENTRY(_ISR_Handler) ! 14 interrupt level 4 + TRAP_ENTRY(_ISR_Handler) ! 15 interrupt level 5 + TRAP_ENTRY(_ISR_Handler) ! 16 interrupt level 6 + TRAP_ENTRY(_ISR_Handler) ! 17 interrupt level 7 + TRAP_ENTRY(_ISR_Handler) ! 18 interrupt level 8 + TRAP_ENTRY(_ISR_Handler) ! 19 interrupt level 9 + TRAP_ENTRY(_ISR_Handler) ! 1A interrupt level 1 + TRAP_ENTRY(_ISR_Handler) ! 1B interrupt level 11 + TRAP_ENTRY(_ISR_Handler) ! 1C interrupt level 12 + TRAP_ENTRY(_ISR_Handler) ! 1D interrupt level 13 + TRAP_ENTRY(_ISR_Handler) ! 1E interrupt level 14 + TRAP_ENTRY(_ISR_Handler) ! 1F interrupt level 15 + + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 24 - 27 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 28 - 2B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7C - 7F undefined + + /* Software traps */ + SOFT_TRAP; SOFT_TRAP; TRAP_ENTRY(_context_switch); TRAP_ENTRY(_context_switch) ! 80 - 83 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF + +_window_overflow: + mov %wim, %l3 ! Calculate next WIM + mov %g1, %l7 + srl %l3, 1, %g1 + sll %l3, NWINDOWS - 1, %l4 + or %l4, %g1, %g1 + save ! Get into window to be saved. + mov %g1, %wim + nop + nop + nop + std %l0, [%sp + 0] + std %l2, [%sp + 8] + std %l4, [%sp + 16] + std %l6, [%sp + 24] + std %i0, [%sp + 32] + std %i2, [%sp + 40] + std %i4, [%sp + 48] + std %i6, [%sp + 56] + restore ! Go back to trap window. + mov %l7, %g1 + jmp %l1 ! Re-execute save. + rett %l2 + +_window_underflow: + mov %wim, %l3 ! Calculate next WIM + sll %l3, 1, %l4 + srl %l3, NWINDOWS - 1, %l5 + or %l5, %l4, %l5 + mov %l5, %wim + nop + nop + nop + restore ! Two restores to get into the + restore ! window to restore + ldd [%sp + 0], %l0 ! Restore window from the stack + ldd [%sp + 8], %l2 + ldd [%sp + 16], %l4 + ldd [%sp + 24], %l6 + ldd [%sp + 32], %i0 + ldd [%sp + 40], %i2 + ldd [%sp + 48], %i4 + ldd [%sp + 56], %i6 + save ! Get back to the trap window. + save + jmp %l1 ! Re-execute restore. + rett %l2 diff --git a/libcpu/sparc-v8/common/SConscript b/libcpu/sparc-v8/common/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/sparc-v8/common/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') -- cgit v1.3.1 From c1f4d6c691498287830af97679548d4c83c3ca02 Mon Sep 17 00:00:00 2001 From: GFWisshit Date: Tue, 20 Oct 2020 17:28:59 +0800 Subject: 修改license header，修改driver目录下的SConscript。 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/bm3803/applications/board.c | 54 ++++++----- bsp/bm3803/applications/board.h | 30 +++--- bsp/bm3803/applications/main.c | 20 ++++ bsp/bm3803/drivers/SConscript | 13 +-- bsp/bm3803/drivers/uart.c | 78 ++++++++------- bsp/bm3803/drivers/uart.h | 30 +++--- bsp/bm3803/drivers/uart_reg.h | 28 +++++- libcpu/sparc-v8/bm3803/bm3803.h | 179 +++++++++++++++++++---------------- libcpu/sparc-v8/bm3803/context_gcc.S | 26 +++-- libcpu/sparc-v8/bm3803/interrupt.c | 44 +++++---- libcpu/sparc-v8/bm3803/interrupt.h | 26 +++-- libcpu/sparc-v8/bm3803/stack.c | 83 +++++++++------- libcpu/sparc-v8/bm3803/start_gcc.S | 26 +++-- libcpu/sparc-v8/bm3803/trap.c | 42 ++++---- libcpu/sparc-v8/bm3803/vector_gcc.S | 26 +++-- 15 files changed, 420 insertions(+), 285 deletions(-) (limited to 'libcpu') diff --git a/bsp/bm3803/applications/board.c b/bsp/bm3803/applications/board.c index 043fceda03..ee400cc0e1 100644 --- a/bsp/bm3803/applications/board.c +++ b/bsp/bm3803/applications/board.c @@ -1,16 +1,22 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #include #include @@ -21,27 +27,27 @@ extern int __bss_end; -static void rt_hw_timer_isr(int vector, void* param) +static void rt_hw_timer_isr(int vector, void *param) { - rt_tick_increase(); - /* timer interrupt cleared by hardware */ + rt_tick_increase(); + /* timer interrupt cleared by hardware */ } int rt_hw_timer_init(void) { - unsigned int counter = 1000000 / RT_TICK_PER_SECOND; - volatile struct lregs *regs = (struct lregs*)PREGS; - + unsigned int counter = 1000000 / RT_TICK_PER_SECOND; + volatile struct lregs *regs = (struct lregs *)PREGS; + regs->scalercnt = CPU_FREQ / 1000000 - 1; regs->scalerload = CPU_FREQ / 1000000 - 1; regs->timercnt2 = counter - 1; regs->timerload2 = counter - 1; - rt_hw_interrupt_install(TIMER2_TT, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_umask(TIMER2_TT); + rt_hw_interrupt_install(TIMER2_TT, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(TIMER2_TT); - /* start timer */ - regs->timerctrl2 = 0x7; + /* start timer */ + regs->timerctrl2 = 0x7; return 0; } @@ -52,7 +58,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init); */ void rt_hw_board_init(void) { - rt_system_heap_init((void*)&__bss_end, (void*)&__bss_end + 0x01000000); + rt_system_heap_init((void *)&__bss_end, (void *)&__bss_end + 0x01000000); rt_components_board_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); } diff --git a/bsp/bm3803/applications/board.h b/bsp/bm3803/applications/board.h index becb93cf3b..88d477e492 100644 --- a/bsp/bm3803/applications/board.h +++ b/bsp/bm3803/applications/board.h @@ -1,16 +1,22 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #ifndef __BOARD_H__ #define __BOARD_H__ diff --git a/bsp/bm3803/applications/main.c b/bsp/bm3803/applications/main.c index d77e7a2a8b..e24fdf2b90 100644 --- a/bsp/bm3803/applications/main.c +++ b/bsp/bm3803/applications/main.c @@ -1,3 +1,23 @@ +/* +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ + #include #include #include diff --git a/bsp/bm3803/drivers/SConscript b/bsp/bm3803/drivers/SConscript index a630c8a7c4..5e45e1bad3 100644 --- a/bsp/bm3803/drivers/SConscript +++ b/bsp/bm3803/drivers/SConscript @@ -3,20 +3,9 @@ Import('RTT_ROOT') Import('rtconfig') from building import * -cwd = GetCurrentDir() +cwd = GetCurrentDir() src = Glob('*.c') - -# remove no need file. -if GetDepend('RT_USING_LWIP') == False: - src_need_remove = ['dm9000.c'] # need remove file list. - SrcRemove(src, src_need_remove) - -if GetDepend('RT_USING_DFS') == False: - src_need_remove = ['sd.c'] # need remove file list. - SrcRemove(src, src_need_remove) - CPPPATH = [cwd] - group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/bm3803/drivers/uart.c b/bsp/bm3803/drivers/uart.c index bdfe522958..4f07c26123 100644 --- a/bsp/bm3803/drivers/uart.c +++ b/bsp/bm3803/drivers/uart.c @@ -1,16 +1,22 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #include #include @@ -27,16 +33,16 @@ struct bm3803_uart int irq; }; -static void bm3803_uart_isr(int tt, void* param) +static void bm3803_uart_isr(int tt, void *param) { - struct bm3803_uart* uart; + struct bm3803_uart *uart; struct rt_serial_device *serial; - struct uart_reg* uart_base; + struct uart_reg *uart_base; - serial = (struct rt_serial_device*)param; + serial = (struct rt_serial_device *)param; uart = (struct bm3803_uart *)serial->parent.user_data; uart_base = uart->uart_base; - + if (uart_base->uartstatus & 0x1) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); @@ -47,8 +53,8 @@ static void bm3803_uart_isr(int tt, void* param) static rt_err_t bm3803_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct bm3803_uart* uart; - struct uart_reg* uart_base; + struct bm3803_uart *uart; + struct uart_reg *uart_base; RT_ASSERT(serial != RT_NULL); uart = (struct bm3803_uart *)serial->parent.user_data; @@ -57,17 +63,17 @@ static rt_err_t bm3803_configure(struct rt_serial_device *serial, struct serial_ if (cfg->baud_rate == BAUD_RATE_115200) { - uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 115200)) - 5) / 10); + uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 115200)) - 5) / 10); } else if (cfg->baud_rate == BAUD_RATE_9600) { - uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 9600)) - 5) / 10); + uart_base->uartscaler = ((((CPU_FREQ * 10) / (8 * 9600)) - 5) / 10); } else { NOT_IMPLEMENTED(); } - + uart_base->uartctrl |= 0x3; return RT_EOK; @@ -75,7 +81,7 @@ static rt_err_t bm3803_configure(struct rt_serial_device *serial, struct serial_ static rt_err_t bm3803_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct bm3803_uart* uart; + struct bm3803_uart *uart; RT_ASSERT(serial != RT_NULL); uart = (struct bm3803_uart *)serial->parent.user_data; @@ -97,13 +103,13 @@ static rt_err_t bm3803_control(struct rt_serial_device *serial, int cmd, void *a static int bm3803_putc(struct rt_serial_device *serial, char c) { - struct bm3803_uart* uart; - struct uart_reg* uart_base; - + struct bm3803_uart *uart; + struct uart_reg *uart_base; + RT_ASSERT(serial != RT_NULL); uart = (struct bm3803_uart *)serial->parent.user_data; uart_base = uart->uart_base; - + while (!(uart_base->uartstatus & 0x4)); uart_base->uartdata = c; @@ -113,13 +119,13 @@ static int bm3803_putc(struct rt_serial_device *serial, char c) static int bm3803_getc(struct rt_serial_device *serial) { int ch; - struct bm3803_uart* uart; - struct uart_reg* uart_base; + struct bm3803_uart *uart; + struct uart_reg *uart_base; RT_ASSERT(serial != RT_NULL); uart = (struct bm3803_uart *)serial->parent.user_data; - uart_base = uart->uart_base; - + uart_base = uart->uart_base; + ch = -1; if (uart_base->uartstatus & 0x1) { @@ -131,7 +137,7 @@ static int bm3803_getc(struct rt_serial_device *serial) static const struct rt_uart_ops bm3803_uart_ops = { - bm3803_configure, + bm3803_configure, bm3803_control, bm3803_putc, bm3803_getc, @@ -141,7 +147,7 @@ static const struct rt_uart_ops bm3803_uart_ops = #ifdef RT_USING_UART1 struct bm3803_uart uart1 = { - (void*)UART1_BASE, + (void *)UART1_BASE, UART1_TT, }; struct rt_serial_device serial1; @@ -152,7 +158,7 @@ int rt_hw_serial_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef RT_USING_UART1 - volatile struct lregs *regs = (struct lregs*)PREGS; + volatile struct lregs *regs = (struct lregs *)PREGS; serial1.ops = &bm3803_uart_ops; serial1.config = config; /* configure gpio direction */ @@ -166,8 +172,8 @@ int rt_hw_serial_init(void) rt_hw_interrupt_mask(uart1.irq); /* register UART1 device */ rt_hw_serial_register(&serial1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - &uart1); + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + &uart1); #endif return 0; } diff --git a/bsp/bm3803/drivers/uart.h b/bsp/bm3803/drivers/uart.h index 46a7df5d89..a16ea99913 100644 --- a/bsp/bm3803/drivers/uart.h +++ b/bsp/bm3803/drivers/uart.h @@ -1,16 +1,22 @@ /* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2020, Shenzhen Academy of Aerospace Technology - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #ifndef __SERIAL_H__ #define __SERIAL_H__ diff --git a/bsp/bm3803/drivers/uart_reg.h b/bsp/bm3803/drivers/uart_reg.h index c0911149df..3edd98a6f7 100644 --- a/bsp/bm3803/drivers/uart_reg.h +++ b/bsp/bm3803/drivers/uart_reg.h @@ -1,12 +1,32 @@ +/* +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ + #ifndef SERIAL_REG_H #define SERIAL_REG_H struct uart_reg { - unsigned int uartdata; - unsigned int uartstatus; - unsigned int uartctrl; - unsigned int uartscaler; + unsigned int uartdata; + unsigned int uartstatus; + unsigned int uartctrl; + unsigned int uartscaler; }; #endif /* end of include guard: SERIAL_REG_H */ diff --git a/libcpu/sparc-v8/bm3803/bm3803.h b/libcpu/sparc-v8/bm3803/bm3803.h index a90663f199..4a4c750975 100644 --- a/libcpu/sparc-v8/bm3803/bm3803.h +++ b/libcpu/sparc-v8/bm3803/bm3803.h @@ -1,95 +1,106 @@ /* - * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ + #ifndef __BM3803_H__ #define __BM3803_H__ struct lregs { - /* address = 0x80000000 */ - unsigned int memcfg1; /* 0x00 */ - unsigned int memcfg2; - unsigned int memcfg3; - unsigned int failaddr; - - unsigned int memstatus; /* 0x10 */ - unsigned int cachectrl; - unsigned int powerdown; - unsigned int writeprot1; - - unsigned int writeprot2; /* 0x20 */ - unsigned int pcr; - unsigned int dummy2; - unsigned int dummy3; - - unsigned int dummy4; /* 0x30 */ - unsigned int dummy5; - unsigned int dummy6; - unsigned int dummy7; - - unsigned int timercnt1; /* 0x40 */ - unsigned int timerload1; - unsigned int timerctrl1; - unsigned int wdog; - - unsigned int timercnt2; /* 0x50 */ - unsigned int timerload2; - unsigned int timerctrl2; - unsigned int dummy8; - - unsigned int scalercnt; /* 0x60 */ - unsigned int scalerload; - unsigned int dummy9; - unsigned int dummy10; - - unsigned int uartdata1; /* 0x70 */ - unsigned int uartstatus1; - unsigned int uartctrl1; - unsigned int uartscaler1; - - unsigned int uartdata2; /* 0x80 */ - unsigned int uartstatus2; - unsigned int uartctrl2; - unsigned int uartscaler2; - - unsigned int irqmask; /* 0x90 */ - unsigned int irqpend; - unsigned int irqforce; - unsigned int irqclear; - - unsigned int piodata; /* 0xA0 */ - unsigned int piodir; - unsigned int pioirq; - unsigned int dummy11; - - unsigned int imask2; /* 0xB0 */ - unsigned int ipend2; - unsigned int istat2; - unsigned int dummy12; - - unsigned int dummy13; /* 0xC0 */ - unsigned int dcomstatus; - unsigned int dcomctrl; - unsigned int dcomscaler; - - unsigned int dummy14; /* 0xD0 */ - unsigned int dummy15; - unsigned int dummy16; - unsigned int dummy17; - - unsigned int uartdata3; /* 0xE0 */ - unsigned int uartstatus3; - unsigned int uartctrl3; - unsigned int uartscaler3; + /* address = 0x80000000 */ + unsigned int memcfg1; /* 0x00 */ + unsigned int memcfg2; + unsigned int memcfg3; + unsigned int failaddr; + + unsigned int memstatus; /* 0x10 */ + unsigned int cachectrl; + unsigned int powerdown; + unsigned int writeprot1; + + unsigned int writeprot2; /* 0x20 */ + unsigned int pcr; + unsigned int dummy2; + unsigned int dummy3; + + unsigned int dummy4; /* 0x30 */ + unsigned int dummy5; + unsigned int dummy6; + unsigned int dummy7; + + unsigned int timercnt1; /* 0x40 */ + unsigned int timerload1; + unsigned int timerctrl1; + unsigned int wdog; + + unsigned int timercnt2; /* 0x50 */ + unsigned int timerload2; + unsigned int timerctrl2; + unsigned int dummy8; + + unsigned int scalercnt; /* 0x60 */ + unsigned int scalerload; + unsigned int dummy9; + unsigned int dummy10; + + unsigned int uartdata1; /* 0x70 */ + unsigned int uartstatus1; + unsigned int uartctrl1; + unsigned int uartscaler1; + + unsigned int uartdata2; /* 0x80 */ + unsigned int uartstatus2; + unsigned int uartctrl2; + unsigned int uartscaler2; + + unsigned int irqmask; /* 0x90 */ + unsigned int irqpend; + unsigned int irqforce; + unsigned int irqclear; + + unsigned int piodata; /* 0xA0 */ + unsigned int piodir; + unsigned int pioirq; + unsigned int dummy11; + + unsigned int imask2; /* 0xB0 */ + unsigned int ipend2; + unsigned int istat2; + unsigned int dummy12; + + unsigned int dummy13; /* 0xC0 */ + unsigned int dcomstatus; + unsigned int dcomctrl; + unsigned int dcomscaler; + + unsigned int dummy14; /* 0xD0 */ + unsigned int dummy15; + unsigned int dummy16; + unsigned int dummy17; + + unsigned int uartdata3; /* 0xE0 */ + unsigned int uartstatus3; + unsigned int uartctrl3; + unsigned int uartscaler3; }; -#define PREGS 0x80000000 +#define PREGS 0x80000000 #define UART1_BASE (PREGS + 0x70) diff --git a/libcpu/sparc-v8/bm3803/context_gcc.S b/libcpu/sparc-v8/bm3803/context_gcc.S index c0344a81d5..478793588e 100644 --- a/libcpu/sparc-v8/bm3803/context_gcc.S +++ b/libcpu/sparc-v8/bm3803/context_gcc.S @@ -1,12 +1,22 @@ /* - * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #define SPARC_PSR_PIL_MASK 0x00000F00 #define SPARC_PSR_ET_MASK 0x00000020 diff --git a/libcpu/sparc-v8/bm3803/interrupt.c b/libcpu/sparc-v8/bm3803/interrupt.c index e3f9b5b3de..8ce03dd4c0 100644 --- a/libcpu/sparc-v8/bm3803/interrupt.c +++ b/libcpu/sparc-v8/bm3803/interrupt.c @@ -1,12 +1,22 @@ /* - * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #include #include @@ -43,10 +53,10 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - if (vector > 0x1F || vector < 0x11) - return; - volatile struct lregs *regs = (struct lregs*)PREGS; - regs->irqmask &= ~(1 << (vector - 0x10)); + if (vector > 0x1F || vector < 0x11) + return; + volatile struct lregs *regs = (struct lregs *)PREGS; + regs->irqmask &= ~(1 << (vector - 0x10)); } /** @@ -55,10 +65,10 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if (vector > 0x1F || vector < 0x11) - return; - volatile struct lregs *regs = (struct lregs*)PREGS; - regs->irqmask |= 1 << (vector - 0x10); + if (vector > 0x1F || vector < 0x11) + return; + volatile struct lregs *regs = (struct lregs *)PREGS; + regs->irqmask |= 1 << (vector - 0x10); } /** @@ -72,7 +82,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, { rt_isr_handler_t old_handler = RT_NULL; - if(vector < MAX_HANDLERS || vector >= 0) + if (vector < MAX_HANDLERS || vector >= 0) { old_handler = isr_table[vector].handler; diff --git a/libcpu/sparc-v8/bm3803/interrupt.h b/libcpu/sparc-v8/bm3803/interrupt.h index 7632195e70..5c97d5caa5 100644 --- a/libcpu/sparc-v8/bm3803/interrupt.h +++ b/libcpu/sparc-v8/bm3803/interrupt.h @@ -1,12 +1,22 @@ /* - * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #ifndef __INTERRUPT_H__ #define __INTERRUPT_H__ diff --git a/libcpu/sparc-v8/bm3803/stack.c b/libcpu/sparc-v8/bm3803/stack.c index 3563692cdd..70c1b60d8c 100644 --- a/libcpu/sparc-v8/bm3803/stack.c +++ b/libcpu/sparc-v8/bm3803/stack.c @@ -1,12 +1,23 @@ /* - * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ + #include /** @@ -29,34 +40,34 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, stack_addr += sizeof(rt_uint32_t); stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); stk = (rt_uint32_t *)stack_addr; - - stk -= 24; - stk -= 8; - - for (register_index = 0; register_index != 8; register_index++) - stk[register_index] = 0xdeadbeef; - - for (window_index = 0; window_index != 8; window_index++) - { - stk -= 16; - for (register_index = 0; register_index != 16; register_index++) - stk[register_index] = 0xdeadbeef; - if (window_index == 0) - { - stk[8] = (rt_uint32_t)parameter; - stk[15] = (rt_uint32_t)texit - 8; - } - } - - stk -= 34; - for (register_index = 0; register_index != 34; register_index++) - stk[register_index] = 0; - - stk -= 4; - stk[0] = (rt_uint32_t)tentry; //pc - stk[1] = (rt_uint32_t)tentry + 4; //npc - stk[2] = 0x10C7; //psr - stk[3] = 0x2; //wim + + stk -= 24; + stk -= 8; + + for (register_index = 0; register_index != 8; register_index++) + stk[register_index] = 0xdeadbeef; + + for (window_index = 0; window_index != 8; window_index++) + { + stk -= 16; + for (register_index = 0; register_index != 16; register_index++) + stk[register_index] = 0xdeadbeef; + if (window_index == 0) + { + stk[8] = (rt_uint32_t)parameter; + stk[15] = (rt_uint32_t)texit - 8; + } + } + + stk -= 34; + for (register_index = 0; register_index != 34; register_index++) + stk[register_index] = 0; + + stk -= 4; + stk[0] = (rt_uint32_t)tentry; //pc + stk[1] = (rt_uint32_t)tentry + 4; //npc + stk[2] = 0x10C7; //psr + stk[3] = 0x2; //wim /* return task's current stack address */ return (rt_uint8_t *)stk; diff --git a/libcpu/sparc-v8/bm3803/start_gcc.S b/libcpu/sparc-v8/bm3803/start_gcc.S index 0f87aa17db..fd613375c9 100644 --- a/libcpu/sparc-v8/bm3803/start_gcc.S +++ b/libcpu/sparc-v8/bm3803/start_gcc.S @@ -1,12 +1,22 @@ /* - * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #define PSR_INIT 0x10C0 #define PREGS 0x80000000 diff --git a/libcpu/sparc-v8/bm3803/trap.c b/libcpu/sparc-v8/bm3803/trap.c index 05a0416dfa..545073ed18 100644 --- a/libcpu/sparc-v8/bm3803/trap.c +++ b/libcpu/sparc-v8/bm3803/trap.c @@ -1,12 +1,22 @@ /* - * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #include #include @@ -15,14 +25,14 @@ extern struct rt_irq_desc isr_table[]; void rt_hw_trap(int tt, unsigned int *sp) { - void *param; - rt_isr_handler_t isr_func; - - /* get interrupt service routine */ - isr_func = isr_table[tt].handler; - param = isr_table[tt].param; - - /* turn to interrupt service routine */ + void *param; + rt_isr_handler_t isr_func; + + /* get interrupt service routine */ + isr_func = isr_table[tt].handler; + param = isr_table[tt].param; + + /* turn to interrupt service routine */ if (isr_func != RT_NULL) isr_func(tt, param); } diff --git a/libcpu/sparc-v8/bm3803/vector_gcc.S b/libcpu/sparc-v8/bm3803/vector_gcc.S index 0d243bee33..114fe45536 100644 --- a/libcpu/sparc-v8/bm3803/vector_gcc.S +++ b/libcpu/sparc-v8/bm3803/vector_gcc.S @@ -1,12 +1,22 @@ /* - * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-10-16 Dystopia the first version - */ +Copyright 2020 Shenzhen Academy of Aerospace Technology + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Change Logs: +Date Author Notes +2020-10-16 Dystopia the first version +*/ #define TRAPL(H) mov %g0, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop; #define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop; -- cgit v1.3.1 From ad917d90109a8e628ab7ea440acbbfaa8273d780 Mon Sep 17 00:00:00 2001 From: GFWisshit Date: Wed, 21 Oct 2020 15:08:13 +0800 Subject: 修改了license header，修改了sconscipt，修改了board.c指针的强制转换类型，interrupt.c添加了新的函数。 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/bm3803/applications/board.c | 28 +++++++++------------------- bsp/bm3803/applications/board.h | 26 ++++++++------------------ bsp/bm3803/applications/main.c | 26 ++++++++------------------ bsp/bm3803/drivers/uart.c | 26 ++++++++------------------ bsp/bm3803/drivers/uart.h | 26 ++++++++------------------ bsp/bm3803/drivers/uart_reg.h | 26 ++++++++------------------ libcpu/sparc-v8/bm3803/bm3803.h | 26 ++++++++------------------ libcpu/sparc-v8/bm3803/context_gcc.S | 26 ++++++++------------------ libcpu/sparc-v8/bm3803/interrupt.c | 34 ++++++++++++++++------------------ libcpu/sparc-v8/bm3803/interrupt.h | 31 +++++++++---------------------- libcpu/sparc-v8/bm3803/stack.c | 26 ++++++++------------------ libcpu/sparc-v8/bm3803/start_gcc.S | 26 ++++++++------------------ libcpu/sparc-v8/bm3803/trap.c | 26 ++++++++------------------ libcpu/sparc-v8/bm3803/vector_gcc.S | 26 ++++++++------------------ libcpu/sparc-v8/common/SConscript | 6 ------ 15 files changed, 122 insertions(+), 263 deletions(-) (limited to 'libcpu') diff --git a/bsp/bm3803/applications/board.c b/bsp/bm3803/applications/board.c index ee400cc0e1..37460f268f 100644 --- a/bsp/bm3803/applications/board.c +++ b/bsp/bm3803/applications/board.c @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #include #include @@ -58,7 +48,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init); */ void rt_hw_board_init(void) { - rt_system_heap_init((void *)&__bss_end, (void *)&__bss_end + 0x01000000); + rt_system_heap_init((void *)&__bss_end, (unsigned char *)&__bss_end + 0x01000000); rt_components_board_init(); rt_console_set_device(RT_CONSOLE_DEVICE_NAME); } diff --git a/bsp/bm3803/applications/board.h b/bsp/bm3803/applications/board.h index 88d477e492..e12389331f 100644 --- a/bsp/bm3803/applications/board.h +++ b/bsp/bm3803/applications/board.h @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #ifndef __BOARD_H__ #define __BOARD_H__ diff --git a/bsp/bm3803/applications/main.c b/bsp/bm3803/applications/main.c index e24fdf2b90..047393b2cf 100644 --- a/bsp/bm3803/applications/main.c +++ b/bsp/bm3803/applications/main.c @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #include #include diff --git a/bsp/bm3803/drivers/uart.c b/bsp/bm3803/drivers/uart.c index 4f07c26123..d43b660d1a 100644 --- a/bsp/bm3803/drivers/uart.c +++ b/bsp/bm3803/drivers/uart.c @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #include #include diff --git a/bsp/bm3803/drivers/uart.h b/bsp/bm3803/drivers/uart.h index a16ea99913..11923d24fe 100644 --- a/bsp/bm3803/drivers/uart.h +++ b/bsp/bm3803/drivers/uart.h @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #ifndef __SERIAL_H__ #define __SERIAL_H__ diff --git a/bsp/bm3803/drivers/uart_reg.h b/bsp/bm3803/drivers/uart_reg.h index 3edd98a6f7..179f767b3e 100644 --- a/bsp/bm3803/drivers/uart_reg.h +++ b/bsp/bm3803/drivers/uart_reg.h @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #ifndef SERIAL_REG_H #define SERIAL_REG_H diff --git a/libcpu/sparc-v8/bm3803/bm3803.h b/libcpu/sparc-v8/bm3803/bm3803.h index 4a4c750975..17a9882eb2 100644 --- a/libcpu/sparc-v8/bm3803/bm3803.h +++ b/libcpu/sparc-v8/bm3803/bm3803.h @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #ifndef __BM3803_H__ #define __BM3803_H__ diff --git a/libcpu/sparc-v8/bm3803/context_gcc.S b/libcpu/sparc-v8/bm3803/context_gcc.S index 478793588e..c0344a81d5 100644 --- a/libcpu/sparc-v8/bm3803/context_gcc.S +++ b/libcpu/sparc-v8/bm3803/context_gcc.S @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #define SPARC_PSR_PIL_MASK 0x00000F00 #define SPARC_PSR_ET_MASK 0x00000020 diff --git a/libcpu/sparc-v8/bm3803/interrupt.c b/libcpu/sparc-v8/bm3803/interrupt.c index 8ce03dd4c0..b3625862b4 100644 --- a/libcpu/sparc-v8/bm3803/interrupt.c +++ b/libcpu/sparc-v8/bm3803/interrupt.c @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #include #include @@ -98,3 +88,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, return old_handler; } + +void rt_hw_interrupt_clear(int vector) +{ + if (vector > 0x1F || vector < 0x11) + return; + volatile struct lregs *regs = (struct lregs *)PREGS; + regs->irqclear |= 1 << (vector - 0x10); +} diff --git a/libcpu/sparc-v8/bm3803/interrupt.h b/libcpu/sparc-v8/bm3803/interrupt.h index 5c97d5caa5..666d5268f5 100644 --- a/libcpu/sparc-v8/bm3803/interrupt.h +++ b/libcpu/sparc-v8/bm3803/interrupt.h @@ -1,30 +1,17 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + * 2020-10-21 Dystopia Add new function + */ #ifndef __INTERRUPT_H__ #define __INTERRUPT_H__ -void rt_hw_interrupt_control(int vector, int priority, int route); -int rt_hw_interrupt_get_active(int fiq_irq); -void rt_hw_interrupt_ack(int fiq_irq); -void rt_hw_interrupt_trigger(int vector); void rt_hw_interrupt_clear(int vector); #endif diff --git a/libcpu/sparc-v8/bm3803/stack.c b/libcpu/sparc-v8/bm3803/stack.c index 70c1b60d8c..2fdc37b539 100644 --- a/libcpu/sparc-v8/bm3803/stack.c +++ b/libcpu/sparc-v8/bm3803/stack.c @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #include diff --git a/libcpu/sparc-v8/bm3803/start_gcc.S b/libcpu/sparc-v8/bm3803/start_gcc.S index fd613375c9..0f87aa17db 100644 --- a/libcpu/sparc-v8/bm3803/start_gcc.S +++ b/libcpu/sparc-v8/bm3803/start_gcc.S @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #define PSR_INIT 0x10C0 #define PREGS 0x80000000 diff --git a/libcpu/sparc-v8/bm3803/trap.c b/libcpu/sparc-v8/bm3803/trap.c index 545073ed18..b896a0d941 100644 --- a/libcpu/sparc-v8/bm3803/trap.c +++ b/libcpu/sparc-v8/bm3803/trap.c @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #include #include diff --git a/libcpu/sparc-v8/bm3803/vector_gcc.S b/libcpu/sparc-v8/bm3803/vector_gcc.S index 114fe45536..0d243bee33 100644 --- a/libcpu/sparc-v8/bm3803/vector_gcc.S +++ b/libcpu/sparc-v8/bm3803/vector_gcc.S @@ -1,22 +1,12 @@ /* -Copyright 2020 Shenzhen Academy of Aerospace Technology - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Change Logs: -Date Author Notes -2020-10-16 Dystopia the first version -*/ + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ #define TRAPL(H) mov %g0, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop; #define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop; diff --git a/libcpu/sparc-v8/common/SConscript b/libcpu/sparc-v8/common/SConscript index 9ff30a796b..1e96ff5837 100644 --- a/libcpu/sparc-v8/common/SConscript +++ b/libcpu/sparc-v8/common/SConscript @@ -8,16 +8,10 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -if rtconfig.PLATFORM == 'armcc': - src += Glob('*_rvds.S') - if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') src += Glob('*_gcc.S') -if rtconfig.PLATFORM == 'iar': - src += Glob('*_iar.S') - group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') -- cgit v1.3.1 From 2f68120e49ab352027b216c3008c2dbe087b2307 Mon Sep 17 00:00:00 2001 From: tangweikang Date: Thu, 29 Oct 2020 10:54:53 +0800 Subject: [libcpu][risc-v] Fixed bsp k210 failing to compile | 修复 k210 无法编译的问题。 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/risc-v/SConscript | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'libcpu') diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index 5055b533e6..dece8b0423 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -10,7 +10,7 @@ group = [] list = os.listdir(cwd) # add common code files -if rtconfig.VENDOR == "t-head" : +if rtconfig.CPU == "e906" : group = group elif rtconfig.CPU == "nuclei" : group = group @@ -18,7 +18,7 @@ else : group = group + SConscript(os.path.join(cwd, 'common', 'SConscript')) # cpu porting code files -if rtconfig.VENDOR == "t-head" : +if rtconfig.CPU == "e906" : group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript')) else : group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript')) -- cgit v1.3.1 From 111ecae6ad0483ede349483c04ffee66f2cdd2fe Mon Sep 17 00:00:00 2001 From: wanghongzhu Date: Wed, 11 Nov 2020 09:58:20 +0800 Subject: fix long call linker error with 'jal', 'j' or conditional branch instruction --- libcpu/risc-v/common/context_gcc.S | 4 ++-- libcpu/risc-v/k210/interrupt_gcc.S | 4 ++-- libcpu/risc-v/k210/startup_gcc.S | 7 +++++-- 3 files changed, 9 insertions(+), 6 deletions(-) (limited to 'libcpu') diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index 5c9f05c4e8..96afaa4c65 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -47,7 +47,7 @@ rt_hw_context_switch_to: #ifdef RT_USING_SMP mv a0, a1 - jal rt_cpus_lock_status_restore + call rt_cpus_lock_status_restore #endif LOAD a0, 2 * REGBYTES(sp) csrw mstatus, a0 @@ -123,7 +123,7 @@ save_mpie: #ifdef RT_USING_SMP mv a0, a2 - jal rt_cpus_lock_status_restore + call rt_cpus_lock_status_restore #endif /*RT_USING_SMP*/ j rt_hw_context_switch_exit diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S index 0393ea51f8..5cfa2bb170 100644 --- a/libcpu/risc-v/k210/interrupt_gcc.S +++ b/libcpu/risc-v/k210/interrupt_gcc.S @@ -82,7 +82,7 @@ trap_entry: mv sp, s0 mv a0, s0 call rt_scheduler_do_irq_switch - j rt_hw_context_switch_exit + tail rt_hw_context_switch_exit #else @@ -106,4 +106,4 @@ trap_entry: #endif spurious_interrupt: - j rt_hw_context_switch_exit + tail rt_hw_context_switch_exit diff --git a/libcpu/risc-v/k210/startup_gcc.S b/libcpu/risc-v/k210/startup_gcc.S index f5c0d8fa94..8df41b52c2 100644 --- a/libcpu/risc-v/k210/startup_gcc.S +++ b/libcpu/risc-v/k210/startup_gcc.S @@ -116,18 +116,21 @@ _start: /* other cpu core, jump to cpu entry directly */ bnez a0, secondary_cpu_entry - j primary_cpu_entry + tail primary_cpu_entry secondary_cpu_entry: #ifdef RT_USING_SMP la a0, secondary_boot_flag ld a0, 0(a0) li a1, 0xa55a - beq a0, a1, secondary_cpu_c_start + beq a0, a1, 1f #endif j secondary_cpu_entry #ifdef RT_USING_SMP +1: + tail secondary_cpu_c_start + .data .global secondary_boot_flag .align 3 -- cgit v1.3.1 From 355f8dd95cddcf784eb60bfea0a8d6ebf130fdf3 Mon Sep 17 00:00:00 2001 From: 张世争 Date: Fri, 20 Nov 2020 08:49:51 +0800 Subject: [libcpu][update]重启与关机函数：rt_hw_cpu_shutdown、rt_hw_cpu_reset，补充WEAK属性 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/aarch64/common/cpu.c | 2 +- libcpu/arc/em/cpuport.c | 2 +- libcpu/arm/AT91SAM7S/cpu.c | 4 ++-- libcpu/arm/AT91SAM7X/cpu.c | 4 ++-- libcpu/arm/am335x/cpu.c | 2 +- libcpu/arm/arm926/cpuport.c | 4 ++-- libcpu/arm/armv6/cpuport.c | 4 ++-- libcpu/arm/cortex-a/cpu.c | 2 +- libcpu/arm/cortex-m3/cpuport.c | 2 +- libcpu/arm/cortex-m33/cpuport.c | 2 +- libcpu/arm/cortex-m4/cpuport.c | 2 +- libcpu/arm/cortex-m7/cpuport.c | 2 +- libcpu/arm/cortex-r4/cpu.c | 4 ++-- libcpu/arm/dm36x/cpuport.c | 4 ++-- libcpu/arm/lpc214x/cpuport.c | 4 ++-- libcpu/arm/lpc24xx/cpu.c | 4 ++-- libcpu/arm/realview-a8-vmm/cpu.c | 2 +- libcpu/arm/s3c24x0/cpu.c | 4 ++-- libcpu/arm/s3c44b0/cpu.c | 4 ++-- libcpu/arm/sep4020/cpu.c | 4 ++-- libcpu/arm/zynq7000/cpu.c | 4 ++-- libcpu/avr32/uc3/cpu.c | 2 +- libcpu/mips/gs232/cpuport.c | 4 ++-- libcpu/risc-v/common/cpuport.c | 2 +- libcpu/risc-v/nuclei/cpuport.c | 2 +- libcpu/risc-v/t-head/e906/cpuport.c | 2 +- libcpu/rx/cpuport.c | 2 +- libcpu/ti-dsp/c28x/cpuport.c | 2 +- libcpu/unicore32/sep6200/cpu.c | 4 ++-- libcpu/xilinx/microblaze/cpu.c | 4 ++-- 30 files changed, 45 insertions(+), 45 deletions(-) (limited to 'libcpu') diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c index 962a53a071..84d3df2e8a 100644 --- a/libcpu/aarch64/common/cpu.c +++ b/libcpu/aarch64/common/cpu.c @@ -76,7 +76,7 @@ void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) /*@{*/ /** shutdown CPU */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arc/em/cpuport.c b/libcpu/arc/em/cpuport.c index 34f538881f..1a2593644a 100644 --- a/libcpu/arc/em/cpuport.c +++ b/libcpu/arc/em/cpuport.c @@ -32,7 +32,7 @@ struct init_stack_frame { /** * shutdown CPU */ -void rt_hw_cpu_shutdown(void) +RT_WEAK void rt_hw_cpu_shutdown(void) { } diff --git a/libcpu/arm/AT91SAM7S/cpu.c b/libcpu/arm/AT91SAM7S/cpu.c index 8d28063eb1..b24ab5644b 100644 --- a/libcpu/arm/AT91SAM7S/cpu.c +++ b/libcpu/arm/AT91SAM7S/cpu.c @@ -20,7 +20,7 @@ * this function will reset CPU * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { } @@ -28,7 +28,7 @@ void rt_hw_cpu_reset() * this function will shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/AT91SAM7X/cpu.c b/libcpu/arm/AT91SAM7X/cpu.c index 484c19d10a..046f7e8ced 100644 --- a/libcpu/arm/AT91SAM7X/cpu.c +++ b/libcpu/arm/AT91SAM7X/cpu.c @@ -20,7 +20,7 @@ * this function will reset CPU * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { } @@ -28,7 +28,7 @@ void rt_hw_cpu_reset() * this function will shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/am335x/cpu.c b/libcpu/arm/am335x/cpu.c index cae865fe50..469276466b 100644 --- a/libcpu/arm/am335x/cpu.c +++ b/libcpu/arm/am335x/cpu.c @@ -149,7 +149,7 @@ rt_base_t rt_hw_cpu_dcache_status() * shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/arm926/cpuport.c b/libcpu/arm/arm926/cpuport.c index 035e97d543..dc93f42ed6 100644 --- a/libcpu/arm/arm926/cpuport.c +++ b/libcpu/arm/arm926/cpuport.c @@ -146,7 +146,7 @@ rt_base_t rt_hw_cpu_dcache_status() * reset cpu by dog's time-out * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { rt_kprintf("Restarting system...\n"); @@ -161,7 +161,7 @@ void rt_hw_cpu_reset() * shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/armv6/cpuport.c b/libcpu/arm/armv6/cpuport.c index c8e9201722..f886e7e164 100644 --- a/libcpu/arm/armv6/cpuport.c +++ b/libcpu/arm/armv6/cpuport.c @@ -147,7 +147,7 @@ rt_base_t rt_hw_cpu_dcache_status() * reset cpu by dog's time-out * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { rt_kprintf("Restarting system...\n"); @@ -162,7 +162,7 @@ void rt_hw_cpu_reset() * shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c index 7c6bf58a4b..6775b781bc 100644 --- a/libcpu/arm/cortex-a/cpu.c +++ b/libcpu/arm/cortex-a/cpu.c @@ -74,7 +74,7 @@ void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) /*@{*/ /** shutdown CPU */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index d58782e2c5..b6c4c9743c 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -344,7 +344,7 @@ void rt_hw_hard_fault_exception(struct exception_info * exception_info) /** * shutdown CPU */ -void rt_hw_cpu_shutdown(void) +RT_WEAK void rt_hw_cpu_shutdown(void) { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c index a589ba3462..42b5798507 100644 --- a/libcpu/arm/cortex-m33/cpuport.c +++ b/libcpu/arm/cortex-m33/cpuport.c @@ -431,7 +431,7 @@ void rt_hw_hard_fault_exception(struct exception_info *exception_info) /** * shutdown CPU */ -void rt_hw_cpu_shutdown(void) +RT_WEAK void rt_hw_cpu_shutdown(void) { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index dc8a9aab59..2e47832259 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -428,7 +428,7 @@ void rt_hw_hard_fault_exception(struct exception_info *exception_info) /** * shutdown CPU */ -void rt_hw_cpu_shutdown(void) +RT_WEAK void rt_hw_cpu_shutdown(void) { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index e701a52307..aeb9f14ac5 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -428,7 +428,7 @@ void rt_hw_hard_fault_exception(struct exception_info *exception_info) /** * shutdown CPU */ -void rt_hw_cpu_shutdown(void) +RT_WEAK void rt_hw_cpu_shutdown(void) { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index d2e8130e7c..23c16e383c 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -20,7 +20,7 @@ * this function will reset CPU * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { } @@ -28,7 +28,7 @@ void rt_hw_cpu_reset() * this function will shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/dm36x/cpuport.c b/libcpu/arm/dm36x/cpuport.c index f6e8a20056..99edb96260 100644 --- a/libcpu/arm/dm36x/cpuport.c +++ b/libcpu/arm/dm36x/cpuport.c @@ -145,7 +145,7 @@ rt_base_t rt_hw_cpu_dcache_status() * reset cpu by dog's time-out * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { rt_kprintf("Restarting system...\n"); @@ -160,7 +160,7 @@ void rt_hw_cpu_reset() * shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/lpc214x/cpuport.c b/libcpu/arm/lpc214x/cpuport.c index 2543a5e0a9..54e7e9b0c8 100644 --- a/libcpu/arm/lpc214x/cpuport.c +++ b/libcpu/arm/lpc214x/cpuport.c @@ -163,7 +163,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, * this function will reset CPU * */ -void rt_hw_cpu_reset(void) +RT_WEAK void rt_hw_cpu_reset(void) { } @@ -171,7 +171,7 @@ void rt_hw_cpu_reset(void) * this function will shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/lpc24xx/cpu.c b/libcpu/arm/lpc24xx/cpu.c index f3a61e16a3..0453722d1d 100644 --- a/libcpu/arm/lpc24xx/cpu.c +++ b/libcpu/arm/lpc24xx/cpu.c @@ -20,7 +20,7 @@ * this function will reset CPU * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { } @@ -28,7 +28,7 @@ void rt_hw_cpu_reset() * this function will shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/realview-a8-vmm/cpu.c b/libcpu/arm/realview-a8-vmm/cpu.c index 2d78715011..dbdb4ac515 100644 --- a/libcpu/arm/realview-a8-vmm/cpu.c +++ b/libcpu/arm/realview-a8-vmm/cpu.c @@ -18,7 +18,7 @@ /*@{*/ /** shutdown CPU */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c index 4d3bf3c1ab..2adf526a5c 100644 --- a/libcpu/arm/s3c24x0/cpu.c +++ b/libcpu/arm/s3c24x0/cpu.c @@ -148,7 +148,7 @@ rt_base_t rt_hw_cpu_dcache_status() * reset cpu by dog's time-out * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { /* Disable all interrupt except the WDT */ INTMSK = (~((rt_uint32_t)1 << INTWDT)); @@ -171,7 +171,7 @@ void rt_hw_cpu_reset() * shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/s3c44b0/cpu.c b/libcpu/arm/s3c44b0/cpu.c index 03ebefba18..9d60b09688 100644 --- a/libcpu/arm/s3c44b0/cpu.c +++ b/libcpu/arm/s3c44b0/cpu.c @@ -100,7 +100,7 @@ rt_base_t rt_hw_cpu_dcache_status() * this function will reset CPU * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { } @@ -108,7 +108,7 @@ void rt_hw_cpu_reset() * this function will shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/sep4020/cpu.c b/libcpu/arm/sep4020/cpu.c index ee4eab626b..92ba2cf86a 100644 --- a/libcpu/arm/sep4020/cpu.c +++ b/libcpu/arm/sep4020/cpu.c @@ -152,7 +152,7 @@ rt_base_t rt_hw_cpu_dcache_status() * reset cpu by dog's time-out * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { /* enable watchdog */ @@ -173,7 +173,7 @@ void rt_hw_cpu_reset() * shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t UNUSED level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/arm/zynq7000/cpu.c b/libcpu/arm/zynq7000/cpu.c index 5f3a3e7b02..f6b7f5d852 100644 --- a/libcpu/arm/zynq7000/cpu.c +++ b/libcpu/arm/zynq7000/cpu.c @@ -16,7 +16,7 @@ * reset cpu by dog's time-out * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { while (1); /* loop forever and wait for reset to happen */ @@ -27,7 +27,7 @@ void rt_hw_cpu_reset() * shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/avr32/uc3/cpu.c b/libcpu/avr32/uc3/cpu.c index b77e78dc5b..fdd8a4d56c 100644 --- a/libcpu/avr32/uc3/cpu.c +++ b/libcpu/avr32/uc3/cpu.c @@ -23,7 +23,7 @@ * reset cpu by dog's time-out * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { /*NOTREACHED*/ } diff --git a/libcpu/mips/gs232/cpuport.c b/libcpu/mips/gs232/cpuport.c index 1b13719449..e3c078241f 100644 --- a/libcpu/mips/gs232/cpuport.c +++ b/libcpu/mips/gs232/cpuport.c @@ -23,7 +23,7 @@ * this function will reset CPU * */ -void rt_hw_cpu_reset(void) +RT_WEAK void rt_hw_cpu_reset(void) { /* open the watch-dog */ WDT_EN = 0x01; /* watch dog enable */ @@ -38,7 +38,7 @@ void rt_hw_cpu_reset(void) * this function will shutdown CPU * */ -void rt_hw_cpu_shutdown(void) +RT_WEAK void rt_hw_cpu_shutdown(void) { rt_kprintf("shutdown...\n"); diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c index a44dc40f79..5da3e85645 100644 --- a/libcpu/risc-v/common/cpuport.c +++ b/libcpu/risc-v/common/cpuport.c @@ -116,7 +116,7 @@ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) #endif /* end of RT_USING_SMP */ /** shutdown CPU */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c index e456438f70..717e9bb1c7 100644 --- a/libcpu/risc-v/nuclei/cpuport.c +++ b/libcpu/risc-v/nuclei/cpuport.c @@ -152,7 +152,7 @@ void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) * @brief shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e906/cpuport.c index 5597aa237a..998bfdc340 100644 --- a/libcpu/risc-v/t-head/e906/cpuport.c +++ b/libcpu/risc-v/t-head/e906/cpuport.c @@ -157,7 +157,7 @@ void rt_hw_interrupt_enable(rt_base_t level) } /** shutdown CPU */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c index 681c0e8e6e..a01f598e99 100644 --- a/libcpu/rx/cpuport.c +++ b/libcpu/rx/cpuport.c @@ -182,7 +182,7 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) * * @author LXZ (2014/11/8) */ -void rt_hw_cpu_shutdown(void) +RT_WEAK void rt_hw_cpu_shutdown(void) { rt_kprintf("shutdown...\n"); diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c index 3f88606c65..0c7dce2a4e 100644 --- a/libcpu/ti-dsp/c28x/cpuport.c +++ b/libcpu/ti-dsp/c28x/cpuport.c @@ -121,7 +121,7 @@ int __rt_ffs(int value) /** * shutdown CPU */ -void rt_hw_cpu_shutdown(void) +RT_WEAK void rt_hw_cpu_shutdown(void) { rt_kprintf("shutdown...\n"); diff --git a/libcpu/unicore32/sep6200/cpu.c b/libcpu/unicore32/sep6200/cpu.c index ebea8750e1..9452b4e59d 100644 --- a/libcpu/unicore32/sep6200/cpu.c +++ b/libcpu/unicore32/sep6200/cpu.c @@ -259,7 +259,7 @@ static void sep6200_poweroff(void) * reset cpu by dog's time-out * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { rt_kprintf("Soft reset, Restarting system...\n"); @@ -274,7 +274,7 @@ void rt_hw_cpu_reset() * shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_uint32_t level; rt_kprintf("shutdown...\n"); diff --git a/libcpu/xilinx/microblaze/cpu.c b/libcpu/xilinx/microblaze/cpu.c index 50a0e34dcd..d37dcda350 100755 --- a/libcpu/xilinx/microblaze/cpu.c +++ b/libcpu/xilinx/microblaze/cpu.c @@ -18,7 +18,7 @@ * this function will reset CPU * */ -void rt_hw_cpu_reset() +RT_WEAK void rt_hw_cpu_reset() { } @@ -26,7 +26,7 @@ void rt_hw_cpu_reset() * this function will shutdown CPU * */ -void rt_hw_cpu_shutdown() +RT_WEAK void rt_hw_cpu_shutdown() { rt_kprintf("shutdown...\n"); -- cgit v1.3.1 From 91261e25b90d6258073f620ae14c003dae9eb16e Mon Sep 17 00:00:00 2001 From: yangjie11 Date: Fri, 20 Nov 2020 13:38:11 +0800 Subject: [SConscript]rename group name --- bsp/CME_M7/StdPeriph_Driver/SConscript | 2 +- bsp/allwinner_tina/drivers/spi/SConscript | 2 +- bsp/allwinner_tina/libcpu/SConscript | 2 +- bsp/ck802/libraries/SConscript | 2 +- bsp/efm32/Libraries/SConscript | 2 +- bsp/fh8620/drivers/SConscript | 2 +- bsp/gd32303e-eval/Libraries/SConscript | 2 +- bsp/gd32450z-eval/Libraries/SConscript | 2 +- bsp/gd32e230k-start/Libraries/SConscript | 2 +- bsp/gkipc/drivers/SConscript | 2 +- bsp/imxrt/libraries/peripherals/SConscript | 2 +- bsp/nv32f100x/lib/SConscript | 2 +- bsp/raspberry-pi/raspi2/cpu/SConscript | 2 +- bsp/raspberry-pi/raspi3-32/cpu/SConscript | 2 +- bsp/raspberry-pi/raspi4-32/driver/SConscript | 2 +- bsp/samd21/applications/SConscript | 2 +- bsp/stm32/libraries/STM32F0xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32F1xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32F2xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32F4xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32F7xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32G0xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32G4xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32H7xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32L0xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32L1xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32L4xx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32MPxx_HAL/SConscript | 2 +- bsp/stm32/libraries/STM32WBxx_HAL/SConscript | 2 +- bsp/stm32/stm32f429-st-disco/board/ports/touch/SConscript | 2 +- bsp/stm32/stm32f469-st-disco/board/ports/touch/SConscript | 2 +- bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript | 2 +- bsp/stm32f20x/Libraries/SConscript | 2 +- bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript | 2 +- components/finsh/SConscript | 2 +- components/libc/compilers/armlibc/SConscript | 2 +- components/libc/compilers/common/SConscript | 2 +- components/libc/compilers/minilibc/SConscript | 2 +- components/libc/compilers/newlib/SConscript | 2 +- components/libc/getline/SConscript | 2 +- components/libc/libdl/SConscript | 2 +- components/libc/mmap/SConscript | 2 +- components/libc/pthreads/SConscript | 2 +- components/libc/signal/SConscript | 2 +- components/libc/termios/SConscript | 2 +- components/libc/time/SConscript | 2 +- components/net/lwip-2.0.2/SConscript | 2 +- components/net/lwip-2.1.2/SConscript | 2 +- components/net/lwip_dhcpd/SConscript | 2 +- components/net/netdev/SConscript | 2 +- components/utilities/utest/SConscript | 2 +- examples/kernel/SConscript | 2 +- examples/libc/SConscript | 2 +- libcpu/aarch64/common/SConscript | 2 +- libcpu/aarch64/cortex-a53/SConscript | 2 +- libcpu/aarch64/cortex-a72/SConscript | 2 +- libcpu/arc/common/SConscript | 2 +- libcpu/arc/em/SConscript | 2 +- libcpu/arm/AT91SAM7S/SConscript | 2 +- libcpu/arm/AT91SAM7X/SConscript | 2 +- libcpu/arm/am335x/SConscript | 2 +- libcpu/arm/arm926/SConscript | 2 +- libcpu/arm/armv6/SConscript | 2 +- libcpu/arm/common/SConscript | 2 +- libcpu/arm/cortex-a/SConscript | 2 +- libcpu/arm/cortex-m0/SConscript | 2 +- libcpu/arm/cortex-m23/SConscript | 2 +- libcpu/arm/cortex-m3/SConscript | 2 +- libcpu/arm/cortex-m33/SConscript | 2 +- libcpu/arm/cortex-m4/SConscript | 2 +- libcpu/arm/cortex-m7/SConscript | 2 +- libcpu/arm/cortex-r4/SConscript | 2 +- libcpu/arm/dm36x/SConscript | 2 +- libcpu/arm/lpc214x/SConscript | 2 +- libcpu/arm/lpc24xx/SConscript | 2 +- libcpu/arm/realview-a8-vmm/SConscript | 2 +- libcpu/arm/s3c24x0/SConscript | 2 +- libcpu/arm/s3c44b0/SConscript | 2 +- libcpu/arm/sep4020/SConscript | 2 +- libcpu/arm/zynq7000/SConscript | 2 +- libcpu/avr32/uc3/SConscript | 2 +- libcpu/blackfin/bf53x/SConscript | 2 +- libcpu/c-sky/ck802/SConscript | 2 +- libcpu/c-sky/common/SConscript | 2 +- libcpu/ia32/SConscript | 2 +- libcpu/m16c/m16c62p/SConscript | 2 +- libcpu/mips/common/SConscript | 2 +- libcpu/mips/gs232/SConscript | 2 +- libcpu/mips/gs264/SConscript | 2 +- libcpu/mips/pic32/SConscript | 2 +- libcpu/nios/nios_ii/SConscript | 2 +- libcpu/ppc/common/SConscript | 2 +- libcpu/ppc/ppc405/SConscript | 2 +- libcpu/risc-v/bumblebee/SConscript | 2 +- libcpu/risc-v/common/SConscript | 2 +- libcpu/risc-v/e310/SConscript | 2 +- libcpu/risc-v/k210/SConscript | 2 +- libcpu/risc-v/nuclei/SConscript | 2 +- libcpu/risc-v/rv32m1/SConscript | 2 +- libcpu/risc-v/t-head/e906/SConscript | 2 +- libcpu/rx/SConscript | 2 +- libcpu/sim/posix/SConscript | 2 +- libcpu/sim/win32/SConscript | 2 +- libcpu/sparc-v8/bm3803/SConscript | 2 +- libcpu/sparc-v8/common/SConscript | 2 +- libcpu/ti-dsp/c28x/SConscript | 2 +- libcpu/unicore32/sep6200/SConscript | 2 +- libcpu/v850/70f34/SConscript | 2 +- libcpu/xilinx/microblaze/SConscript | 2 +- 109 files changed, 109 insertions(+), 109 deletions(-) (limited to 'libcpu') diff --git a/bsp/CME_M7/StdPeriph_Driver/SConscript b/bsp/CME_M7/StdPeriph_Driver/SConscript index bcc08ad28e..07493050d6 100644 --- a/bsp/CME_M7/StdPeriph_Driver/SConscript +++ b/bsp/CME_M7/StdPeriph_Driver/SConscript @@ -9,6 +9,6 @@ src = Glob('src/*.c') path = [cwd + '/inc'] -group = DefineGroup('StdPeriph_Driver', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/allwinner_tina/drivers/spi/SConscript b/bsp/allwinner_tina/drivers/spi/SConscript index 6995b9ebda..cc32e09500 100644 --- a/bsp/allwinner_tina/drivers/spi/SConscript +++ b/bsp/allwinner_tina/drivers/spi/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd, str(Dir('#'))] -group = DefineGroup('spi', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/allwinner_tina/libcpu/SConscript b/bsp/allwinner_tina/libcpu/SConscript index aa13c2b179..7fd3011498 100644 --- a/bsp/allwinner_tina/libcpu/SConscript +++ b/bsp/allwinner_tina/libcpu/SConscript @@ -8,6 +8,6 @@ CPPPATH = [cwd] if rtconfig.PLATFORM == 'gcc': src += Glob('*_gcc.S') -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/ck802/libraries/SConscript b/bsp/ck802/libraries/SConscript index 862d3c70c3..4b800240c5 100644 --- a/bsp/ck802/libraries/SConscript +++ b/bsp/ck802/libraries/SConscript @@ -43,6 +43,6 @@ path = [cwd + '/include', cwd + '/common/wdt' ] -group = DefineGroup('libraries', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/efm32/Libraries/SConscript b/bsp/efm32/Libraries/SConscript index 17d69a4668..0cb8856f89 100644 --- a/bsp/efm32/Libraries/SConscript +++ b/bsp/efm32/Libraries/SConscript @@ -72,6 +72,6 @@ path = [cwd + '/emlib/inc', CPPDEFINES = [rtconfig.EFM32_TYPE] #group = DefineGroup('EFM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES, LINKFLAGS = linker_scripts[rtconfig.EFM32_FAMILY]) -group = DefineGroup('EFM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/fh8620/drivers/SConscript b/bsp/fh8620/drivers/SConscript index e9f7715967..e98eb13101 100644 --- a/bsp/fh8620/drivers/SConscript +++ b/bsp/fh8620/drivers/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('drivers', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/gd32303e-eval/Libraries/SConscript b/bsp/gd32303e-eval/Libraries/SConscript index 2c3a08337a..2d3b323d2e 100644 --- a/bsp/gd32303e-eval/Libraries/SConscript +++ b/bsp/gd32303e-eval/Libraries/SConscript @@ -28,6 +28,6 @@ if GetDepend(['RT_USING_BSP_USB']): CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F30X_HD'] -group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/gd32450z-eval/Libraries/SConscript b/bsp/gd32450z-eval/Libraries/SConscript index 82e5540be0..75df263b3e 100644 --- a/bsp/gd32450z-eval/Libraries/SConscript +++ b/bsp/gd32450z-eval/Libraries/SConscript @@ -28,6 +28,6 @@ if GetDepend(['RT_USING_BSP_USB']): CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F4XX'] -group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/gd32e230k-start/Libraries/SConscript b/bsp/gd32e230k-start/Libraries/SConscript index e79dc34216..f621432d3d 100644 --- a/bsp/gd32e230k-start/Libraries/SConscript +++ b/bsp/gd32e230k-start/Libraries/SConscript @@ -22,6 +22,6 @@ path = [ CPPDEFINES = ['GD32E230'] -group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/gkipc/drivers/SConscript b/bsp/gkipc/drivers/SConscript index 65750c9285..86fc613654 100644 --- a/bsp/gkipc/drivers/SConscript +++ b/bsp/gkipc/drivers/SConscript @@ -19,6 +19,6 @@ path += [cwd + '/../platform'] libcwd = str(Dir('#')) -group = DefineGroup('drivers', src, depend = [''], CPPPATH = path) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/imxrt/libraries/peripherals/SConscript b/bsp/imxrt/libraries/peripherals/SConscript index 13d040cf2b..6d41c2b7c9 100644 --- a/bsp/imxrt/libraries/peripherals/SConscript +++ b/bsp/imxrt/libraries/peripherals/SConscript @@ -11,6 +11,6 @@ if GetDepend('BSP_USING_PHY') and GetDepend('PHY_USING_KSZ8081'): path = [cwd] -group = DefineGroup('Peripherals', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/nv32f100x/lib/SConscript b/bsp/nv32f100x/lib/SConscript index 9f78108059..d92d8ba176 100644 --- a/bsp/nv32f100x/lib/SConscript +++ b/bsp/nv32f100x/lib/SConscript @@ -11,6 +11,6 @@ path = [cwd + '/inc' CPPDEFINES = ['NV32', 'KEIL'] -group = DefineGroup('Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/raspberry-pi/raspi2/cpu/SConscript b/bsp/raspberry-pi/raspi2/cpu/SConscript index eb4ee7a585..748b06eeb1 100644 --- a/bsp/raspberry-pi/raspi2/cpu/SConscript +++ b/bsp/raspberry-pi/raspi2/cpu/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/raspberry-pi/raspi3-32/cpu/SConscript b/bsp/raspberry-pi/raspi3-32/cpu/SConscript index eb4ee7a585..748b06eeb1 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/SConscript +++ b/bsp/raspberry-pi/raspi3-32/cpu/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/raspberry-pi/raspi4-32/driver/SConscript b/bsp/raspberry-pi/raspi4-32/driver/SConscript index 64c764c1b3..a7f9eef8f3 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/SConscript +++ b/bsp/raspberry-pi/raspi4-32/driver/SConscript @@ -4,7 +4,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd, str(Dir('#'))] -group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) # build for sub-directory list = os.listdir(cwd) diff --git a/bsp/samd21/applications/SConscript b/bsp/samd21/applications/SConscript index 3c69933a88..7f8f92dd28 100644 --- a/bsp/samd21/applications/SConscript +++ b/bsp/samd21/applications/SConscript @@ -9,6 +9,6 @@ CPPPATH = [cwd, str(Dir('#'))] #remove other no use files #SrcRemove(src, '*.c') -group = DefineGroup('Application', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) Return('group') \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32F0xx_HAL/SConscript b/bsp/stm32/libraries/STM32F0xx_HAL/SConscript index 0149cd46f2..83a63eae5e 100644 --- a/bsp/stm32/libraries/STM32F0xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F0xx_HAL/SConscript @@ -81,6 +81,6 @@ path = [cwd + '/CMSIS/Device/ST/STM32F0xx/Include', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/SConscript b/bsp/stm32/libraries/STM32F1xx_HAL/SConscript index ff87a4aa25..36c204e860 100644 --- a/bsp/stm32/libraries/STM32F1xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F1xx_HAL/SConscript @@ -87,6 +87,6 @@ path = [cwd + '/CMSIS/Device/ST/STM32F1xx/Include', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/SConscript b/bsp/stm32/libraries/STM32F2xx_HAL/SConscript index b69484d566..37aee93257 100644 --- a/bsp/stm32/libraries/STM32F2xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F2xx_HAL/SConscript @@ -82,6 +82,6 @@ path = [cwd + '/CMSIS/Device/ST/STM32F2xx/Include', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32F4xx_HAL/SConscript b/bsp/stm32/libraries/STM32F4xx_HAL/SConscript index 87c000ae18..cb9fcd81c7 100644 --- a/bsp/stm32/libraries/STM32F4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F4xx_HAL/SConscript @@ -109,6 +109,6 @@ path = [cwd + '/STM32F4xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32F7xx_HAL/SConscript b/bsp/stm32/libraries/STM32F7xx_HAL/SConscript index 096cba78c7..50ec582b66 100644 --- a/bsp/stm32/libraries/STM32F7xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F7xx_HAL/SConscript @@ -105,7 +105,7 @@ path = [cwd + '/STM32F7xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32G0xx_HAL/SConscript b/bsp/stm32/libraries/STM32G0xx_HAL/SConscript index 3d712c5d0b..c2ffc079f7 100644 --- a/bsp/stm32/libraries/STM32G0xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32G0xx_HAL/SConscript @@ -60,6 +60,6 @@ path = [cwd + '/STM32G0xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/SConscript b/bsp/stm32/libraries/STM32G4xx_HAL/SConscript index d367a99fc3..025acb8c57 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32G4xx_HAL/SConscript @@ -110,6 +110,6 @@ path = [cwd + '/STM32G4xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32H7xx_HAL/SConscript b/bsp/stm32/libraries/STM32H7xx_HAL/SConscript index 7e4817c62a..52b622b25e 100644 --- a/bsp/stm32/libraries/STM32H7xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32H7xx_HAL/SConscript @@ -109,7 +109,7 @@ path = [cwd + '/STM32H7xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32L0xx_HAL/SConscript b/bsp/stm32/libraries/STM32L0xx_HAL/SConscript index 84d5daca28..4da0214df9 100644 --- a/bsp/stm32/libraries/STM32L0xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32L0xx_HAL/SConscript @@ -88,6 +88,6 @@ path = [cwd + '/STM32L0xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/SConscript b/bsp/stm32/libraries/STM32L1xx_HAL/SConscript index 199d58696d..4dcd76b906 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32L1xx_HAL/SConscript @@ -77,6 +77,6 @@ path = [cwd + '/CMSIS/Device/ST/STM32L1xx/Include', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript index 037f91893e..2055b3558f 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript @@ -113,6 +113,6 @@ path = [cwd + '/STM32L4xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript index 427cc65ac6..32ac00af16 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript @@ -108,6 +108,6 @@ path = [cwd + '/STM32MP1xx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/SConscript b/bsp/stm32/libraries/STM32WBxx_HAL/SConscript index d2f47a473d..e4fe5d3259 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32WBxx_HAL/SConscript @@ -84,6 +84,6 @@ path = [cwd + '/STM32WBxx_HAL_Driver/Inc', cwd + '/CMSIS/Include'] CPPDEFINES = ['USE_HAL_DRIVER'] -group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/SConscript b/bsp/stm32/stm32f429-st-disco/board/ports/touch/SConscript index f65574f8c4..280e1cd6d1 100644 --- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/SConscript +++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd, str(Dir('#'))] -group = DefineGroup('touch', src, depend = ['BSP_USING_TOUCH'], CPPPATH = CPPPATH) +group = DefineGroup('Touch', src, depend = ['BSP_USING_TOUCH'], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/SConscript b/bsp/stm32/stm32f469-st-disco/board/ports/touch/SConscript index f65574f8c4..280e1cd6d1 100644 --- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/SConscript +++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd, str(Dir('#'))] -group = DefineGroup('touch', src, depend = ['BSP_USING_TOUCH'], CPPPATH = CPPPATH) +group = DefineGroup('Touch', src, depend = ['BSP_USING_TOUCH'], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript index 51c6e3b601..3d5802831b 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript @@ -15,6 +15,6 @@ if rtconfig.CROSS_TOOL == 'gcc': elif rtconfig.CROSS_TOOL == 'keil': LOCAL_CCFLAGS += ' --c99' -group = DefineGroup('fal', src, depend = ['PKG_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS) +group = DefineGroup('Fal', src, depend = ['PKG_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS) Return('group') diff --git a/bsp/stm32f20x/Libraries/SConscript b/bsp/stm32f20x/Libraries/SConscript index bc87c26f8d..d057702dc8 100644 --- a/bsp/stm32f20x/Libraries/SConscript +++ b/bsp/stm32f20x/Libraries/SConscript @@ -64,6 +64,6 @@ if GetDepend('RT_USING_LWIP') == True: CPPDEFINES = ['USE_STDPERIPH_DRIVER'] -group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript b/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript index 9178aeaa35..7871c9ec09 100644 --- a/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript @@ -68,6 +68,6 @@ path = [cwd + '/tm4c123_driverlib', cwd + '/tm4c123_driverlib/driverlib', cwd + '/tm4c123_driverlib/driverlib/inc'] -group = DefineGroup('TM4C123_HAL', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') diff --git a/components/finsh/SConscript b/components/finsh/SConscript index be04c56616..88d4713d58 100644 --- a/components/finsh/SConscript +++ b/components/finsh/SConscript @@ -34,6 +34,6 @@ if not GetDepend('FINSH_USING_MSH_ONLY'): CPPPATH = [cwd] -group = DefineGroup('finsh', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH) +group = DefineGroup('Finsh', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/compilers/armlibc/SConscript b/components/libc/compilers/armlibc/SConscript index 52f7a6d93a..2d366901c4 100644 --- a/components/libc/compilers/armlibc/SConscript +++ b/components/libc/compilers/armlibc/SConscript @@ -15,7 +15,7 @@ if GetDepend('RT_USING_MODULE') == False: SrcRemove(src, ['libc_syms.c']) if rtconfig.PLATFORM == 'armcc' or rtconfig.PLATFORM == 'armclang': - group = DefineGroup('libc', src, depend = ['RT_USING_LIBC'], + group = DefineGroup('Libc', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/compilers/common/SConscript b/components/libc/compilers/common/SConscript index 2407301405..21a49d9c57 100644 --- a/components/libc/compilers/common/SConscript +++ b/components/libc/compilers/common/SConscript @@ -17,6 +17,6 @@ if GetDepend('RT_USING_POSIX') == False: SrcRemove(src, ['unistd.c']) if not GetDepend('RT_USING_MINILIBC') and (GetDepend('RT_USING_LIBC') or GetDepend('RT_LIBC_USING_TIME')): - group = DefineGroup('libc', src, depend = [''], CPPPATH = CPPPATH) + group = DefineGroup('Libc', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/compilers/minilibc/SConscript b/components/libc/compilers/minilibc/SConscript index dec657028f..efdcf5d097 100644 --- a/components/libc/compilers/minilibc/SConscript +++ b/components/libc/compilers/minilibc/SConscript @@ -9,7 +9,7 @@ CPPPATH = [cwd] CPPDEFINES = ['RT_USING_MINILIBC'] if rtconfig.PLATFORM == 'gcc' and rtconfig.ARCH != 'sim' and not GetDepend('RT_USING_LIBC') and GetDepend('RT_USING_MINILIBC'): - group = DefineGroup('libc', src, depend = [''], + group = DefineGroup('Libc', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/compilers/newlib/SConscript b/components/libc/compilers/newlib/SConscript index 06e5faad09..bd444ab732 100644 --- a/components/libc/compilers/newlib/SConscript +++ b/components/libc/compilers/newlib/SConscript @@ -15,7 +15,7 @@ CPPDEFINES = ['RT_USING_NEWLIB'] LIBS = ['c', 'm'] if rtconfig.PLATFORM == 'gcc': - group = DefineGroup('newlib', src, depend = ['RT_USING_LIBC'], + group = DefineGroup('Newlib', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LIBS = LIBS) Return('group') diff --git a/components/libc/getline/SConscript b/components/libc/getline/SConscript index fa4c8618c1..f85843dada 100644 --- a/components/libc/getline/SConscript +++ b/components/libc/getline/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('libc', src, +group = DefineGroup('Libc', src, depend = ['RT_USING_LIBC', 'RT_USING_POSIX','RT_USING_POSIX_GETLINE'], CPPPATH = CPPPATH) diff --git a/components/libc/libdl/SConscript b/components/libc/libdl/SConscript index 93636e4b7a..05efab351c 100644 --- a/components/libc/libdl/SConscript +++ b/components/libc/libdl/SConscript @@ -7,7 +7,7 @@ group = [] CPPPATH = [cwd] if rtconfig.PLATFORM == 'gcc': - group = DefineGroup('libc', src, + group = DefineGroup('Libc', src, depend = ['RT_USING_MODULE'], CPPPATH = CPPPATH) diff --git a/components/libc/mmap/SConscript b/components/libc/mmap/SConscript index 1a36a15710..0b84003241 100644 --- a/components/libc/mmap/SConscript +++ b/components/libc/mmap/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('libc', src, +group = DefineGroup('Libc', src, depend = ['RT_USING_DFS', 'RT_USING_POSIX_MMAP'], CPPPATH = CPPPATH) diff --git a/components/libc/pthreads/SConscript b/components/libc/pthreads/SConscript index e154ee0aa9..dff99aa01d 100644 --- a/components/libc/pthreads/SConscript +++ b/components/libc/pthreads/SConscript @@ -16,7 +16,7 @@ try: except : pass -group = DefineGroup('pthreads', src, +group = DefineGroup('Pthreads', src, depend = ['RT_USING_PTHREADS', 'RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/signal/SConscript b/components/libc/signal/SConscript index f07ff58f6e..407d60c728 100644 --- a/components/libc/signal/SConscript +++ b/components/libc/signal/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('libc', src, +group = DefineGroup('Libc', src, depend = ['RT_USING_SIGNALS', 'RT_USING_PTHREADS', 'RT_USING_LIBC'], CPPPATH = CPPPATH) diff --git a/components/libc/termios/SConscript b/components/libc/termios/SConscript index 381eb5ad8b..977ff7e0a2 100644 --- a/components/libc/termios/SConscript +++ b/components/libc/termios/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('libc', src, +group = DefineGroup('Libc', src, depend = ['RT_USING_LIBC', 'RT_USING_POSIX', 'RT_USING_POSIX_TERMIOS'], CPPPATH = CPPPATH) diff --git a/components/libc/time/SConscript b/components/libc/time/SConscript index 4ecd5d24bc..67d1824b9f 100644 --- a/components/libc/time/SConscript +++ b/components/libc/time/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('pthreads', src, +group = DefineGroup('Pthreads', src, depend = ['RT_USING_PTHREADS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/net/lwip-2.0.2/SConscript b/components/net/lwip-2.0.2/SConscript index df04b42324..910ce63539 100644 --- a/components/net/lwip-2.0.2/SConscript +++ b/components/net/lwip-2.0.2/SConscript @@ -84,6 +84,6 @@ if GetDepend(['RT_USING_LWIP_IPV6']): if GetDepend(['RT_LWIP_USING_PING']): src += Glob('src/apps/ping/ping.c') -group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP202'], CPPPATH = path) +group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP202'], CPPPATH = path) Return('group') diff --git a/components/net/lwip-2.1.2/SConscript b/components/net/lwip-2.1.2/SConscript index 04f59167d5..20afc37534 100644 --- a/components/net/lwip-2.1.2/SConscript +++ b/components/net/lwip-2.1.2/SConscript @@ -260,6 +260,6 @@ if GetDepend(['RT_USING_LWIP_IPV6']): if GetDepend(['RT_LWIP_USING_PING']): src += lwipping_SRCS -group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP212'], CPPPATH = path) +group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP212'], CPPPATH = path) Return('group') diff --git a/components/net/lwip_dhcpd/SConscript b/components/net/lwip_dhcpd/SConscript index 16c673036a..d4ef6da41c 100644 --- a/components/net/lwip_dhcpd/SConscript +++ b/components/net/lwip_dhcpd/SConscript @@ -9,6 +9,6 @@ else: CPPPATH = [cwd] -group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'LWIP_USING_DHCPD'], CPPPATH = CPPPATH) +group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'LWIP_USING_DHCPD'], CPPPATH = CPPPATH) Return('group') diff --git a/components/net/netdev/SConscript b/components/net/netdev/SConscript index fca31a268b..5fa858e968 100644 --- a/components/net/netdev/SConscript +++ b/components/net/netdev/SConscript @@ -8,6 +8,6 @@ src = Glob('src/*.c') CPPPATH = [cwd + '/include'] -group = DefineGroup('netdev', src, depend = ['RT_USING_NETDEV'], CPPPATH = CPPPATH) +group = DefineGroup('Netdev', src, depend = ['RT_USING_NETDEV'], CPPPATH = CPPPATH) Return('group') diff --git a/components/utilities/utest/SConscript b/components/utilities/utest/SConscript index dc77bc2591..ea7efcfbc9 100644 --- a/components/utilities/utest/SConscript +++ b/components/utilities/utest/SConscript @@ -3,6 +3,6 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('utest', src, depend = ['RT_USING_UTEST'], CPPPATH = CPPPATH) +group = DefineGroup('Utest', src, depend = ['RT_USING_UTEST'], CPPPATH = CPPPATH) Return('group') diff --git a/examples/kernel/SConscript b/examples/kernel/SConscript index 4cffe1c38c..e627d852be 100644 --- a/examples/kernel/SConscript +++ b/examples/kernel/SConscript @@ -34,7 +34,7 @@ memp_simple.c tc_sample.c """) -group = DefineGroup('examples', src, +group = DefineGroup('Examples', src, depend = ['RT_USING_TC'], CPPPATH=[GetCurrentDir()]) diff --git a/examples/libc/SConscript b/examples/libc/SConscript index 7801049c07..601acd22a1 100644 --- a/examples/libc/SConscript +++ b/examples/libc/SConscript @@ -1,6 +1,6 @@ from building import * src = Glob('*.c') -group = DefineGroup('libc_test', src, depend = ['RT_USING_NEWLIB', 'RT_USING_PTHREADS']) +group = DefineGroup('LibcTest', src, depend = ['RT_USING_NEWLIB', 'RT_USING_PTHREADS']) Return('group') diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript index 72fb8e26c3..e44dd04b5b 100644 --- a/libcpu/aarch64/common/SConscript +++ b/libcpu/aarch64/common/SConscript @@ -8,7 +8,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) # build for sub-directory list = os.listdir(cwd) diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript index c6a4817802..1dfa9022c5 100644 --- a/libcpu/aarch64/cortex-a53/SConscript +++ b/libcpu/aarch64/cortex-a53/SConscript @@ -8,6 +8,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/aarch64/cortex-a72/SConscript b/libcpu/aarch64/cortex-a72/SConscript index c6a4817802..1dfa9022c5 100644 --- a/libcpu/aarch64/cortex-a72/SConscript +++ b/libcpu/aarch64/cortex-a72/SConscript @@ -8,6 +8,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arc/common/SConscript b/libcpu/arc/common/SConscript index 1c77347e61..1962dec615 100644 --- a/libcpu/arc/common/SConscript +++ b/libcpu/arc/common/SConscript @@ -5,6 +5,6 @@ src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('cpu', src, depend = [], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arc/em/SConscript b/libcpu/arc/em/SConscript index ff1d8c134d..2210cba597 100644 --- a/libcpu/arc/em/SConscript +++ b/libcpu/arc/em/SConscript @@ -10,6 +10,6 @@ CPPPATH = [cwd] src += Glob('*.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/AT91SAM7S/SConscript b/libcpu/arm/AT91SAM7S/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/AT91SAM7S/SConscript +++ b/libcpu/arm/AT91SAM7S/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/AT91SAM7X/SConscript b/libcpu/arm/AT91SAM7X/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/AT91SAM7X/SConscript +++ b/libcpu/arm/AT91SAM7X/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/am335x/SConscript b/libcpu/arm/am335x/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/am335x/SConscript +++ b/libcpu/arm/am335x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/arm926/SConscript b/libcpu/arm/arm926/SConscript index 00785a135b..705307f210 100644 --- a/libcpu/arm/arm926/SConscript +++ b/libcpu/arm/arm926/SConscript @@ -20,6 +20,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/arm/armv6/SConscript b/libcpu/arm/armv6/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/armv6/SConscript +++ b/libcpu/arm/armv6/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/common/SConscript b/libcpu/arm/common/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/common/SConscript +++ b/libcpu/arm/common/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/cortex-a/SConscript +++ b/libcpu/arm/cortex-a/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m0/SConscript b/libcpu/arm/cortex-m0/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/cortex-m0/SConscript +++ b/libcpu/arm/cortex-m0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m23/SConscript b/libcpu/arm/cortex-m23/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/cortex-m23/SConscript +++ b/libcpu/arm/cortex-m23/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m3/SConscript b/libcpu/arm/cortex-m3/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/cortex-m3/SConscript +++ b/libcpu/arm/cortex-m3/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m33/SConscript b/libcpu/arm/cortex-m33/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/cortex-m33/SConscript +++ b/libcpu/arm/cortex-m33/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m4/SConscript b/libcpu/arm/cortex-m4/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/cortex-m4/SConscript +++ b/libcpu/arm/cortex-m4/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m7/SConscript b/libcpu/arm/cortex-m7/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/cortex-m7/SConscript +++ b/libcpu/arm/cortex-m7/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-r4/SConscript b/libcpu/arm/cortex-r4/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/cortex-r4/SConscript +++ b/libcpu/arm/cortex-r4/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/dm36x/SConscript b/libcpu/arm/dm36x/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/dm36x/SConscript +++ b/libcpu/arm/dm36x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/lpc214x/SConscript b/libcpu/arm/lpc214x/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/lpc214x/SConscript +++ b/libcpu/arm/lpc214x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/lpc24xx/SConscript b/libcpu/arm/lpc24xx/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/lpc24xx/SConscript +++ b/libcpu/arm/lpc24xx/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/realview-a8-vmm/SConscript b/libcpu/arm/realview-a8-vmm/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/realview-a8-vmm/SConscript +++ b/libcpu/arm/realview-a8-vmm/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/s3c24x0/SConscript b/libcpu/arm/s3c24x0/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/s3c24x0/SConscript +++ b/libcpu/arm/s3c24x0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/s3c44b0/SConscript b/libcpu/arm/s3c44b0/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/s3c44b0/SConscript +++ b/libcpu/arm/s3c44b0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/sep4020/SConscript b/libcpu/arm/sep4020/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/sep4020/SConscript +++ b/libcpu/arm/sep4020/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript index 9ff30a796b..729d9c03df 100644 --- a/libcpu/arm/zynq7000/SConscript +++ b/libcpu/arm/zynq7000/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/avr32/uc3/SConscript b/libcpu/avr32/uc3/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/avr32/uc3/SConscript +++ b/libcpu/avr32/uc3/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/blackfin/bf53x/SConscript b/libcpu/blackfin/bf53x/SConscript index af9ba4bc81..86d5d3973d 100644 --- a/libcpu/blackfin/bf53x/SConscript +++ b/libcpu/blackfin/bf53x/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_vdsp.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/c-sky/ck802/SConscript b/libcpu/c-sky/ck802/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/c-sky/ck802/SConscript +++ b/libcpu/c-sky/ck802/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/c-sky/common/SConscript b/libcpu/c-sky/common/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/c-sky/common/SConscript +++ b/libcpu/c-sky/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ia32/SConscript b/libcpu/ia32/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/ia32/SConscript +++ b/libcpu/ia32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/m16c/m16c62p/SConscript b/libcpu/m16c/m16c62p/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/m16c/m16c62p/SConscript +++ b/libcpu/m16c/m16c62p/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/common/SConscript b/libcpu/mips/common/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/mips/common/SConscript +++ b/libcpu/mips/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/gs232/SConscript b/libcpu/mips/gs232/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/mips/gs232/SConscript +++ b/libcpu/mips/gs232/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/gs264/SConscript b/libcpu/mips/gs264/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/mips/gs264/SConscript +++ b/libcpu/mips/gs264/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/pic32/SConscript b/libcpu/mips/pic32/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/mips/pic32/SConscript +++ b/libcpu/mips/pic32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/nios/nios_ii/SConscript b/libcpu/nios/nios_ii/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/nios/nios_ii/SConscript +++ b/libcpu/nios/nios_ii/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ppc/common/SConscript b/libcpu/ppc/common/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/ppc/common/SConscript +++ b/libcpu/ppc/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ppc/ppc405/SConscript b/libcpu/ppc/ppc405/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/ppc/ppc405/SConscript +++ b/libcpu/ppc/ppc405/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/bumblebee/SConscript b/libcpu/risc-v/bumblebee/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/risc-v/bumblebee/SConscript +++ b/libcpu/risc-v/bumblebee/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/common/SConscript b/libcpu/risc-v/common/SConscript index 2f698f530a..6d6f2fca51 100644 --- a/libcpu/risc-v/common/SConscript +++ b/libcpu/risc-v/common/SConscript @@ -7,6 +7,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/e310/SConscript b/libcpu/risc-v/e310/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/risc-v/e310/SConscript +++ b/libcpu/risc-v/e310/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/k210/SConscript b/libcpu/risc-v/k210/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/risc-v/k210/SConscript +++ b/libcpu/risc-v/k210/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/risc-v/nuclei/SConscript +++ b/libcpu/risc-v/nuclei/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/rv32m1/SConscript b/libcpu/risc-v/rv32m1/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/risc-v/rv32m1/SConscript +++ b/libcpu/risc-v/rv32m1/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/t-head/e906/SConscript b/libcpu/risc-v/t-head/e906/SConscript index 2f698f530a..6d6f2fca51 100644 --- a/libcpu/risc-v/t-head/e906/SConscript +++ b/libcpu/risc-v/t-head/e906/SConscript @@ -7,6 +7,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/rx/SConscript b/libcpu/rx/SConscript index e5890498c9..37ea22c449 100644 --- a/libcpu/rx/SConscript +++ b/libcpu/rx/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_iar.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sim/posix/SConscript b/libcpu/sim/posix/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/sim/posix/SConscript +++ b/libcpu/sim/posix/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sim/win32/SConscript b/libcpu/sim/win32/SConscript index afab42d47c..91589d8f5c 100644 --- a/libcpu/sim/win32/SConscript +++ b/libcpu/sim/win32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sparc-v8/bm3803/SConscript b/libcpu/sparc-v8/bm3803/SConscript index 1e96ff5837..e80809d85b 100644 --- a/libcpu/sparc-v8/bm3803/SConscript +++ b/libcpu/sparc-v8/bm3803/SConscript @@ -12,6 +12,6 @@ if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') src += Glob('*_gcc.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/sparc-v8/common/SConscript b/libcpu/sparc-v8/common/SConscript index 1e96ff5837..e80809d85b 100644 --- a/libcpu/sparc-v8/common/SConscript +++ b/libcpu/sparc-v8/common/SConscript @@ -12,6 +12,6 @@ if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') src += Glob('*_gcc.S') -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/ti-dsp/c28x/SConscript b/libcpu/ti-dsp/c28x/SConscript index 08b274341b..7690eb5960 100644 --- a/libcpu/ti-dsp/c28x/SConscript +++ b/libcpu/ti-dsp/c28x/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*.s') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/unicore32/sep6200/SConscript b/libcpu/unicore32/sep6200/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/unicore32/sep6200/SConscript +++ b/libcpu/unicore32/sep6200/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/v850/70f34/SConscript b/libcpu/v850/70f34/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/v850/70f34/SConscript +++ b/libcpu/v850/70f34/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/xilinx/microblaze/SConscript b/libcpu/xilinx/microblaze/SConscript index b0ae20ba02..fa3e28e56a 100644 --- a/libcpu/xilinx/microblaze/SConscript +++ b/libcpu/xilinx/microblaze/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') -- cgit v1.3.1 From c8deffcf56df79cbf817b02cb1d9b62c61565022 Mon Sep 17 00:00:00 2001 From: tangweikang Date: Fri, 20 Nov 2020 12:05:37 +0800 Subject: [libcpu/risc-v][K210] add FPU support --- libcpu/Kconfig | 8 ++++ libcpu/risc-v/common/context_gcc.S | 78 +++++++++++++++++++++++++++++++++++++- libcpu/risc-v/common/cpuport.c | 35 +++++++++++++++++ libcpu/risc-v/common/cpuport.h | 16 ++++++++ libcpu/risc-v/k210/interrupt_gcc.S | 37 ++++++++++++++++++ 5 files changed, 173 insertions(+), 1 deletion(-) (limited to 'libcpu') diff --git a/libcpu/Kconfig b/libcpu/Kconfig index ae2767dec9..974c421138 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -106,6 +106,14 @@ config ARCH_RISCV config ARCH_RISCV_FPU bool +config ARCH_RISCV_FPU_S + select ARCH_RISCV_FPU + bool + +config ARCH_RISCV_FPU_D + select ARCH_RISCV_FPU + bool + config ARCH_RISCV32 select ARCH_RISCV bool diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index 5c9f05c4e8..9f356f4191 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -7,6 +7,7 @@ * Date Author Notes * 2018/10/28 Bernard The unify RISC-V porting implementation * 2018/12/27 Jesven Add SMP support + * 2020/11/20 BalanceTWK Add FPU support */ #include "cpuport.h" @@ -72,6 +73,43 @@ rt_hw_context_switch: * mstatus.mie -> sp(2) * x(i) -> sp(i-4) */ +#ifdef ARCH_RISCV_FPU + addi sp, sp, -32 * FREGBYTES + + FSTORE f0, 0 * FREGBYTES(sp) + FSTORE f1, 1 * FREGBYTES(sp) + FSTORE f2, 2 * FREGBYTES(sp) + FSTORE f3, 3 * FREGBYTES(sp) + FSTORE f4, 4 * FREGBYTES(sp) + FSTORE f5, 5 * FREGBYTES(sp) + FSTORE f6, 6 * FREGBYTES(sp) + FSTORE f7, 7 * FREGBYTES(sp) + FSTORE f8, 8 * FREGBYTES(sp) + FSTORE f9, 9 * FREGBYTES(sp) + FSTORE f10, 10 * FREGBYTES(sp) + FSTORE f11, 11 * FREGBYTES(sp) + FSTORE f12, 12 * FREGBYTES(sp) + FSTORE f13, 13 * FREGBYTES(sp) + FSTORE f14, 14 * FREGBYTES(sp) + FSTORE f15, 15 * FREGBYTES(sp) + FSTORE f16, 16 * FREGBYTES(sp) + FSTORE f17, 17 * FREGBYTES(sp) + FSTORE f18, 18 * FREGBYTES(sp) + FSTORE f19, 19 * FREGBYTES(sp) + FSTORE f20, 20 * FREGBYTES(sp) + FSTORE f21, 21 * FREGBYTES(sp) + FSTORE f22, 22 * FREGBYTES(sp) + FSTORE f23, 23 * FREGBYTES(sp) + FSTORE f24, 24 * FREGBYTES(sp) + FSTORE f25, 25 * FREGBYTES(sp) + FSTORE f26, 26 * FREGBYTES(sp) + FSTORE f27, 27 * FREGBYTES(sp) + FSTORE f28, 28 * FREGBYTES(sp) + FSTORE f29, 29 * FREGBYTES(sp) + FSTORE f30, 30 * FREGBYTES(sp) + FSTORE f31, 31 * FREGBYTES(sp) + +#endif addi sp, sp, -32 * REGBYTES STORE sp, (a0) @@ -174,7 +212,7 @@ rt_hw_context_switch_exit: LOAD x1, 1 * REGBYTES(sp) - li t0, 0x00001800 + li t0, 0x00007800 csrw mstatus, t0 LOAD a0, 2 * REGBYTES(sp) csrs mstatus, a0 @@ -209,4 +247,42 @@ rt_hw_context_switch_exit: LOAD x31, 31 * REGBYTES(sp) addi sp, sp, 32 * REGBYTES + +#ifdef ARCH_RISCV_FPU + FLOAD f0, 0 * FREGBYTES(sp) + FLOAD f1, 1 * FREGBYTES(sp) + FLOAD f2, 2 * FREGBYTES(sp) + FLOAD f3, 3 * FREGBYTES(sp) + FLOAD f4, 4 * FREGBYTES(sp) + FLOAD f5, 5 * FREGBYTES(sp) + FLOAD f6, 6 * FREGBYTES(sp) + FLOAD f7, 7 * FREGBYTES(sp) + FLOAD f8, 8 * FREGBYTES(sp) + FLOAD f9, 9 * FREGBYTES(sp) + FLOAD f10, 10 * FREGBYTES(sp) + FLOAD f11, 11 * FREGBYTES(sp) + FLOAD f12, 12 * FREGBYTES(sp) + FLOAD f13, 13 * FREGBYTES(sp) + FLOAD f14, 14 * FREGBYTES(sp) + FLOAD f15, 15 * FREGBYTES(sp) + FLOAD f16, 16 * FREGBYTES(sp) + FLOAD f17, 17 * FREGBYTES(sp) + FLOAD f18, 18 * FREGBYTES(sp) + FLOAD f19, 19 * FREGBYTES(sp) + FLOAD f20, 20 * FREGBYTES(sp) + FLOAD f21, 21 * FREGBYTES(sp) + FLOAD f22, 22 * FREGBYTES(sp) + FLOAD f23, 23 * FREGBYTES(sp) + FLOAD f24, 24 * FREGBYTES(sp) + FLOAD f25, 25 * FREGBYTES(sp) + FLOAD f26, 26 * FREGBYTES(sp) + FLOAD f27, 27 * FREGBYTES(sp) + FLOAD f28, 28 * FREGBYTES(sp) + FLOAD f29, 29 * FREGBYTES(sp) + FLOAD f30, 30 * FREGBYTES(sp) + FLOAD f31, 31 * FREGBYTES(sp) + + addi sp, sp, 32 * FREGBYTES +#endif + mret diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c index a44dc40f79..7542f65855 100644 --- a/libcpu/risc-v/common/cpuport.c +++ b/libcpu/risc-v/common/cpuport.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018/10/28 Bernard The unify RISC-V porting code. + * 2020/11/20 BalanceTWK Add FPU support */ #include @@ -53,6 +54,40 @@ struct rt_hw_stack_frame rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ +#ifdef ARCH_RISCV_FPU + rv_floatreg_t f0; /* f0 */ + rv_floatreg_t f1; /* f1 */ + rv_floatreg_t f2; /* f2 */ + rv_floatreg_t f3; /* f3 */ + rv_floatreg_t f4; /* f4 */ + rv_floatreg_t f5; /* f5 */ + rv_floatreg_t f6; /* f6 */ + rv_floatreg_t f7; /* f7 */ + rv_floatreg_t f8; /* f8 */ + rv_floatreg_t f9; /* f9 */ + rv_floatreg_t f10; /* f10 */ + rv_floatreg_t f11; /* f11 */ + rv_floatreg_t f12; /* f12 */ + rv_floatreg_t f13; /* f13 */ + rv_floatreg_t f14; /* f14 */ + rv_floatreg_t f15; /* f15 */ + rv_floatreg_t f16; /* f16 */ + rv_floatreg_t f17; /* f17 */ + rv_floatreg_t f18; /* f18 */ + rv_floatreg_t f19; /* f19 */ + rv_floatreg_t f20; /* f20 */ + rv_floatreg_t f21; /* f21 */ + rv_floatreg_t f22; /* f22 */ + rv_floatreg_t f23; /* f23 */ + rv_floatreg_t f24; /* f24 */ + rv_floatreg_t f25; /* f25 */ + rv_floatreg_t f26; /* f26 */ + rv_floatreg_t f27; /* f27 */ + rv_floatreg_t f28; /* f28 */ + rv_floatreg_t f29; /* f29 */ + rv_floatreg_t f30; /* f30 */ + rv_floatreg_t f31; /* f31 */ +#endif }; /** diff --git a/libcpu/risc-v/common/cpuport.h b/libcpu/risc-v/common/cpuport.h index 95268732cb..d6cec2f0cf 100644 --- a/libcpu/risc-v/common/cpuport.h +++ b/libcpu/risc-v/common/cpuport.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-10-03 Bernard The first version + * 2020/11/20 BalanceTWK Add FPU support */ #ifndef CPUPORT_H__ @@ -24,4 +25,19 @@ #define REGBYTES 4 #endif +#ifdef ARCH_RISCV_FPU +#ifdef ARCH_RISCV_FPU_D +#define FSTORE fsd +#define FLOAD fld +#define FREGBYTES 8 +#define rv_floatreg_t rt_int64_t +#endif +#ifdef ARCH_RISCV_FPU_S +#define FSTORE fsw +#define FLOAD flw +#define FREGBYTES 4 +#define rv_floatreg_t rt_int32_t +#endif +#endif + #endif diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S index 0393ea51f8..dc4a720dea 100644 --- a/libcpu/risc-v/k210/interrupt_gcc.S +++ b/libcpu/risc-v/k210/interrupt_gcc.S @@ -15,6 +15,43 @@ .align 2 .global trap_entry trap_entry: +#ifdef ARCH_RISCV_FPU + addi sp, sp, -32 * FREGBYTES + + FSTORE f0, 0 * FREGBYTES(sp) + FSTORE f1, 1 * FREGBYTES(sp) + FSTORE f2, 2 * FREGBYTES(sp) + FSTORE f3, 3 * FREGBYTES(sp) + FSTORE f4, 4 * FREGBYTES(sp) + FSTORE f5, 5 * FREGBYTES(sp) + FSTORE f6, 6 * FREGBYTES(sp) + FSTORE f7, 7 * FREGBYTES(sp) + FSTORE f8, 8 * FREGBYTES(sp) + FSTORE f9, 9 * FREGBYTES(sp) + FSTORE f10, 10 * FREGBYTES(sp) + FSTORE f11, 11 * FREGBYTES(sp) + FSTORE f12, 12 * FREGBYTES(sp) + FSTORE f13, 13 * FREGBYTES(sp) + FSTORE f14, 14 * FREGBYTES(sp) + FSTORE f15, 15 * FREGBYTES(sp) + FSTORE f16, 16 * FREGBYTES(sp) + FSTORE f17, 17 * FREGBYTES(sp) + FSTORE f18, 18 * FREGBYTES(sp) + FSTORE f19, 19 * FREGBYTES(sp) + FSTORE f20, 20 * FREGBYTES(sp) + FSTORE f21, 21 * FREGBYTES(sp) + FSTORE f22, 22 * FREGBYTES(sp) + FSTORE f23, 23 * FREGBYTES(sp) + FSTORE f24, 24 * FREGBYTES(sp) + FSTORE f25, 25 * FREGBYTES(sp) + FSTORE f26, 26 * FREGBYTES(sp) + FSTORE f27, 27 * FREGBYTES(sp) + FSTORE f28, 28 * FREGBYTES(sp) + FSTORE f29, 29 * FREGBYTES(sp) + FSTORE f30, 30 * FREGBYTES(sp) + FSTORE f31, 31 * FREGBYTES(sp) + +#endif /* save thread context to thread stack */ addi sp, sp, -32 * REGBYTES -- cgit v1.3.1 From c72c44221d4762e96a5389ed595fca9364ad2646 Mon Sep 17 00:00:00 2001 From: David Lin Date: Fri, 20 Nov 2020 18:43:10 +0800 Subject: Update exception_gcc.S thead- > thread --- libcpu/avr32/uc3/exception_gcc.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'libcpu') diff --git a/libcpu/avr32/uc3/exception_gcc.S b/libcpu/avr32/uc3/exception_gcc.S index d5051af253..cdf2576f54 100644 --- a/libcpu/avr32/uc3/exception_gcc.S +++ b/libcpu/avr32/uc3/exception_gcc.S @@ -289,7 +289,7 @@ rt_hw_context_switch_interrupt_do: ld.w r12, r12[0] lda.w r11, rt_interrupt_to_thread /* Get new thread SP */ ld.w r11, r11[0] - st.w r12[0], sp /* Store old thead SP */ + st.w r12[0], sp /* Store old thread SP */ ld.w sp, r11[0] /* Load new thread SP */ ldm sp++, r0-r7 /* Pop R0-R7 (new thread) */ rete /* RETE pops R8-R12, LR, PC, SR automatically */ -- cgit v1.3.1 From 732382c676622c1d026fd8adcf09012f739f6814 Mon Sep 17 00:00:00 2001 From: tangweikang Date: Sat, 21 Nov 2020 13:47:58 +0800 Subject: [K210] update compile parameters and startup_gcc.S --- bsp/k210/rtconfig.py | 2 +- libcpu/risc-v/k210/startup_gcc.S | 64 ++++++++++++++++++++-------------------- 2 files changed, 33 insertions(+), 33 deletions(-) (limited to 'libcpu') diff --git a/bsp/k210/rtconfig.py b/bsp/k210/rtconfig.py index b9258cd374..0f336d545e 100755 --- a/bsp/k210/rtconfig.py +++ b/bsp/k210/rtconfig.py @@ -38,7 +38,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64d' + DEVICE = ' -mcmodel=medany -march=rv64imafc -mabi=lp64f -fsingle-precision-constant' CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' diff --git a/libcpu/risc-v/k210/startup_gcc.S b/libcpu/risc-v/k210/startup_gcc.S index f5c0d8fa94..cc7126e8ab 100644 --- a/libcpu/risc-v/k210/startup_gcc.S +++ b/libcpu/risc-v/k210/startup_gcc.S @@ -67,38 +67,38 @@ _start: csrs mstatus, t0 fssr x0 - fmv.d.x f0, x0 - fmv.d.x f1, x0 - fmv.d.x f2, x0 - fmv.d.x f3, x0 - fmv.d.x f4, x0 - fmv.d.x f5, x0 - fmv.d.x f6, x0 - fmv.d.x f7, x0 - fmv.d.x f8, x0 - fmv.d.x f9, x0 - fmv.d.x f10,x0 - fmv.d.x f11,x0 - fmv.d.x f12,x0 - fmv.d.x f13,x0 - fmv.d.x f14,x0 - fmv.d.x f15,x0 - fmv.d.x f16,x0 - fmv.d.x f17,x0 - fmv.d.x f18,x0 - fmv.d.x f19,x0 - fmv.d.x f20,x0 - fmv.d.x f21,x0 - fmv.d.x f22,x0 - fmv.d.x f23,x0 - fmv.d.x f24,x0 - fmv.d.x f25,x0 - fmv.d.x f26,x0 - fmv.d.x f27,x0 - fmv.d.x f28,x0 - fmv.d.x f29,x0 - fmv.d.x f30,x0 - fmv.d.x f31,x0 + fmv.w.x f0, x0 + fmv.w.x f1, x0 + fmv.w.x f2, x0 + fmv.w.x f3, x0 + fmv.w.x f4, x0 + fmv.w.x f5, x0 + fmv.w.x f6, x0 + fmv.w.x f7, x0 + fmv.w.x f8, x0 + fmv.w.x f9, x0 + fmv.w.x f10,x0 + fmv.w.x f11,x0 + fmv.w.x f12,x0 + fmv.w.x f13,x0 + fmv.w.x f14,x0 + fmv.w.x f15,x0 + fmv.w.x f16,x0 + fmv.w.x f17,x0 + fmv.w.x f18,x0 + fmv.w.x f19,x0 + fmv.w.x f20,x0 + fmv.w.x f21,x0 + fmv.w.x f22,x0 + fmv.w.x f23,x0 + fmv.w.x f24,x0 + fmv.w.x f25,x0 + fmv.w.x f26,x0 + fmv.w.x f27,x0 + fmv.w.x f28,x0 + fmv.w.x f29,x0 + fmv.w.x f30,x0 + fmv.w.x f31,x0 .option push .option norelax -- cgit v1.3.1 From 72583289231b5664b38363c1d3d5d411a970bb57 Mon Sep 17 00:00:00 2001 From: Wang-Huachen Date: Mon, 30 Nov 2020 13:13:08 +0800 Subject: bsp: add support to zynqmp-r5 core and zynqmp-r5-axu4ev board --- bsp/zynqmp-r5-axu4ev/.config | 515 ++++++ bsp/zynqmp-r5-axu4ev/Kconfig | 27 + bsp/zynqmp-r5-axu4ev/README.md | 112 ++ bsp/zynqmp-r5-axu4ev/README_zh.md | 133 ++ bsp/zynqmp-r5-axu4ev/SConscript | 14 + bsp/zynqmp-r5-axu4ev/SConstruct | 30 + bsp/zynqmp-r5-axu4ev/applications/SConscript | 11 + bsp/zynqmp-r5-axu4ev/applications/main.c | 18 + bsp/zynqmp-r5-axu4ev/drivers/Kconfig | 35 + bsp/zynqmp-r5-axu4ev/drivers/SConscript | 26 + .../drivers/Zynq_HAL_Driver/SConscript | 17 + .../drivers/Zynq_HAL_Driver/gpiops_v3_7/SConscript | 15 + .../drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c | 808 +++++++++ .../drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h | 267 +++ .../Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c | 31 + .../Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c | 240 +++ .../Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h | 146 ++ .../Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c | 805 +++++++++ .../Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c | 112 ++ .../Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c | 75 + .../drivers/Zynq_HAL_Driver/sdps_v3_9/SConscript | 15 + .../drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c | 420 +++++ .../drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h | 295 ++++ .../drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c | 1510 ++++++++++++++++ .../drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_core.h | 115 ++ .../drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c | 49 + .../drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c | 1801 ++++++++++++++++++++ .../drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h | 1323 ++++++++++++++ .../Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c | 698 ++++++++ .../Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c | 75 + .../drivers/Zynq_HAL_Driver/sleep.h | 31 + .../drivers/Zynq_HAL_Driver/xil_assert.h | 21 + .../drivers/Zynq_HAL_Driver/xil_cache.h | 18 + .../drivers/Zynq_HAL_Driver/xil_io.h | 204 +++ .../drivers/Zynq_HAL_Driver/xil_printf.h | 16 + .../drivers/Zynq_HAL_Driver/xil_types.h | 96 ++ .../drivers/Zynq_HAL_Driver/xparameters.h | 1511 ++++++++++++++++ .../drivers/Zynq_HAL_Driver/xparameters_ps.h | 325 ++++ .../drivers/Zynq_HAL_Driver/xplatform_info.h | 64 + .../drivers/Zynq_HAL_Driver/xstatus.h | 513 ++++++ bsp/zynqmp-r5-axu4ev/drivers/board.c | 76 + bsp/zynqmp-r5-axu4ev/drivers/board.h | 18 + bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c | 85 + bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.h | 13 + bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c | 472 +++++ bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.h | 13 + bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c | 65 + bsp/zynqmp-r5-axu4ev/drivers/drv_timer.h | 48 + bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c | 318 ++++ bsp/zynqmp-r5-axu4ev/drivers/drv_uart.h | 281 +++ bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h | 41 + bsp/zynqmp-r5-axu4ev/rtconfig.h | 190 +++ bsp/zynqmp-r5-axu4ev/rtconfig.py | 49 + bsp/zynqmp-r5-axu4ev/zynqmp-r5.ld | 127 ++ libcpu/arm/zynqmp-r5/SConscript | 23 + libcpu/arm/zynqmp-r5/armv7.h | 67 + libcpu/arm/zynqmp-r5/cache.c | 200 +++ libcpu/arm/zynqmp-r5/context_gcc.S | 113 ++ libcpu/arm/zynqmp-r5/cpu.c | 36 + libcpu/arm/zynqmp-r5/gic.c | 209 +++ libcpu/arm/zynqmp-r5/gic.h | 30 + libcpu/arm/zynqmp-r5/interrupt.c | 133 ++ libcpu/arm/zynqmp-r5/interrupt.h | 28 + libcpu/arm/zynqmp-r5/mpu.c | 288 ++++ libcpu/arm/zynqmp-r5/stack.c | 72 + libcpu/arm/zynqmp-r5/start_gcc.S | 424 +++++ libcpu/arm/zynqmp-r5/trap.c | 180 ++ libcpu/arm/zynqmp-r5/vector_gcc.S | 51 + libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h | 249 +++ libcpu/arm/zynqmp-r5/xreg_cortexr5.h | 419 +++++ 70 files changed, 16855 insertions(+) create mode 100644 bsp/zynqmp-r5-axu4ev/.config create mode 100644 bsp/zynqmp-r5-axu4ev/Kconfig create mode 100644 bsp/zynqmp-r5-axu4ev/README.md create mode 100644 bsp/zynqmp-r5-axu4ev/README_zh.md create mode 100644 bsp/zynqmp-r5-axu4ev/SConscript create mode 100644 bsp/zynqmp-r5-axu4ev/SConstruct create mode 100644 bsp/zynqmp-r5-axu4ev/applications/SConscript create mode 100644 bsp/zynqmp-r5-axu4ev/applications/main.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Kconfig create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/SConscript create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/SConscript create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/SConscript create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/SConscript create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_core.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/board.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/board.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/drv_timer.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/drv_uart.h create mode 100644 bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h create mode 100644 bsp/zynqmp-r5-axu4ev/rtconfig.h create mode 100644 bsp/zynqmp-r5-axu4ev/rtconfig.py create mode 100644 bsp/zynqmp-r5-axu4ev/zynqmp-r5.ld create mode 100644 libcpu/arm/zynqmp-r5/SConscript create mode 100644 libcpu/arm/zynqmp-r5/armv7.h create mode 100644 libcpu/arm/zynqmp-r5/cache.c create mode 100644 libcpu/arm/zynqmp-r5/context_gcc.S create mode 100644 libcpu/arm/zynqmp-r5/cpu.c create mode 100644 libcpu/arm/zynqmp-r5/gic.c create mode 100644 libcpu/arm/zynqmp-r5/gic.h create mode 100644 libcpu/arm/zynqmp-r5/interrupt.c create mode 100644 libcpu/arm/zynqmp-r5/interrupt.h create mode 100644 libcpu/arm/zynqmp-r5/mpu.c create mode 100644 libcpu/arm/zynqmp-r5/stack.c create mode 100644 libcpu/arm/zynqmp-r5/start_gcc.S create mode 100644 libcpu/arm/zynqmp-r5/trap.c create mode 100644 libcpu/arm/zynqmp-r5/vector_gcc.S create mode 100644 libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h create mode 100644 libcpu/arm/zynqmp-r5/xreg_cortexr5.h (limited to 'libcpu') diff --git a/bsp/zynqmp-r5-axu4ev/.config b/bsp/zynqmp-r5-axu4ev/.config new file mode 100644 index 0000000000..629096a979 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/.config @@ -0,0 +1,515 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=20 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# Using RapidIO +# +# CONFIG_RT_USING_RAPIDIO is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +CONFIG_SOC_ZYNQMP_R5=y + +# +# Hardware Drivers Config +# + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SD0=y + +# +# Board extended module Drivers +# diff --git a/bsp/zynqmp-r5-axu4ev/Kconfig b/bsp/zynqmp-r5-axu4ev/Kconfig new file mode 100644 index 0000000000..f2dd6a2550 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ZYNQMP_R5 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/zynqmp-r5-axu4ev/README.md b/bsp/zynqmp-r5-axu4ev/README.md new file mode 100644 index 0000000000..a67c9c86ee --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/README.md @@ -0,0 +1,112 @@ +# AXU4EV-E BSP (Board Support Package) Execution Instruction + +[中文页](README_zh.md) | + +## **Introduction** + +This document records the execution instruction of the BSP (board support package) for the AXU4EV-E development board. + +The document is covered in three parts: + +- AXU4EV-E Board Resources Introduction +- Quickly Get Started +- Advanced Features +- BSP Migration + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## AXU4EV-E Resources Introduction + +ALINX AXU4EV-E: Xilinx Zynq UltraScale+ MPSOC XCZU4EV-1SFVC784I Ethernet FPGA development board, the SoM Core board is the smallest system, mainly composed of XCZU4EV-1SFVC784I + 5 DDR4 + eMMC + 1 QSPI FLASH. The Carrier board expands a wealth of peripheral interfaces for the core board, including 1 SATA M.2 interface, 1 DP output interface, 4 USB3.0 interfaces, 2 Gigabit Ethernet interfaces, 2 UART interfaces, 1 SD card interface, 2*40-pin Expansion Connectors for Modules, 2 CAN bus interfaces, 2 RS485 interfaces, 1 MIPI interface, Keys and LEDs. High-speed data exchange and transmission, data storage, pre-verification and post-application of data processing, video transmission processing, deep learning, artificial intelligence and industrial control, is a professional ZYNQ development platform. suitable for students, engineers and other groups engaged in the development of MPSoCs. + +For more details about this board, please refer to [Alinx Electronic Technology (Shanghai) Co.,Ltd.](http://www.alinx.com/en/)。 + +## **Peripheral Condition** + +Each peripheral supporting condition for this BSP is as follows: + +| **Core** | **Support** | **Remark** | +| :----------------- | :----------: | :------------------------------------- | +| R5-CPU0 | Support | The R5-CPU0 is running the system | +| **On-board Peripherals** | **Support** | **Remark** | +| None | | | +| **On-chip Peripherals** | **Support** | **Remark** | +| GPIO | Support | | +| UART | Support | UART0 | +| TIMER | Support | TTC0 provides system clock | +| EMMC | Support | SD0 Controller | + +## Execution Instruction + +### Quickly Get Started + +This BSP only support the GCC development environment. Here's an example to introduce how to run the system. + +#### Compile and Download + +1. Open the env tool under BSP. Enter `scons` to compile. + +2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory. + +3. Use Xilinx Vitis to generate fsbl, and then create "Debug Configuration", select the `rtthread-zynqmp-r5.elf` file as the application. + +4. Use the debugger to connect the PC and the development board. Set the dial switch to JTAG to start. Then connect the power supply. Click start debugging or running. + + Since the compiler has debugging information by default (see rtconfig.py In BUILD, so when debugging in Xilinx Vitis, you can also open source files to set breakpoints for debugging. + +#### Software Solidification + +1. Open the env tool under BSP. Enter `scons` to compile. + +2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory. + +3. Use Xilinx Vitis or Xilinx SDK to generate fsbl, and then use the bootgen tool provided by Xilinx to make fsbl BOOT.bin Documents. + + For example, use the command line: + + ``` + bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on + ``` + + And the outpu.bif file could be： + ``` + //arch = zynqmp; split = false; format = BIN + the_ROM_image: + { + [bootloader, destination_cpu = r5-0]./fsbl.elf + [destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf + } + ``` + +4. According to the document provided by Alinx, put BOOT.bin into SD card or burn to QSPI flash, set the startup mode through dial switch, and then connect the power supply to start. + + +#### Running Results + +Once the project is successfully downloaded, the system runs automatically. + +Connect the serial port of the board to PC, communicate with it via a serial terminal tool (115200bps, 8N1). Restart the board and the startup information of RT-Thread will be observed: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Nov 27 2020 + 2006 - 2020 Copyright by rt-thread team +msh /> +``` + +### **Advanced Features** + +This BSP enables EMMC driver and DFS file system by default. If you need to use a file system, you can format and mount it by yourself. + +## BSP Migration + +If you need to ported the BSP to another development board of Xilinx Zynq UltraScale+ MPSOC development platform, it is also convenient. The main modifications are as follows: + +1. Memory: `psu_r5_ddr_0_MEM_0` in `zynqmp-r5.ld` (if DDR memory is less than 2G) +2. Main Frequency: `XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ` in `zynqmp-r5.h` +3. Pin and Frequency of Serial Port: `rxmio`, `txmio` and `XPAR_PSU_UART_0_UART_CLK_FREQ_HZ` in `drv_uart.c` +4. Timer Frequency: `XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ` in `drv_timer.c` +5. SD Controller: Block device driver initialization in `drv_sdcard.c` + +The parameter macro definition in `xparameters.h` does not need to be modified manually. You can directly copy the `xparameters.h` file of the development board generated in Xilinx Vitis. diff --git a/bsp/zynqmp-r5-axu4ev/README_zh.md b/bsp/zynqmp-r5-axu4ev/README_zh.md new file mode 100644 index 0000000000..2735f9a353 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/README_zh.md @@ -0,0 +1,133 @@ +# AXU4EV-E 开发板 BSP 说明 + +## 简介 + +本文档是为 AXU4EV-E 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +AXU4EV-E 开发板是 芯驿电子科技（上海）有限公司 推出的一款基于 XILINX Zynq UltraScale+ MPSoCs 开发平台的开发板。这款 MPSoCs 开发平台采用核心板加扩展板的模式，方便用户对核心板的二次开发利用。核心板使用 XILINX Zynq UltraScale+ EV 芯片 ZU4EV 的解决方案，它采用Processing System(PS)+Programmable Logic(PL)技术将四核ARM Cortex-A53 和FPGA 可编程逻辑集成在一颗芯片上。另外核心板上 PS 端带有 4 片共 4GB 高速 DDR4 SDRAM 芯片，1 片 8GB的 eMMC 存储芯片和 1 片 256Mb 的 QSPI FLASH 芯片；核心板上 PL 端带有 1 片 1GB 的DDR4 SDRAM 芯片 。 + +开发板更多详细信息请参考[芯驿电子科技（上海）有限公司](http://www.alinx.cn/)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **核心** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| R5-CPU0 | 支持 | 运行系统的为R5核的CPU0 | +| **板载外设** | **支持情况** | **备注** | +| 无 | | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART0 | +| TIMER | 支持 | TTC0提供系统时钟 | +| EMMC | 支持 | SD0控制器 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为仅支持 GCC 开发环境，下面介绍如何将系统运行起来。 + +#### 编译下载 + +1. 在 bsp 下打开 env 工具，输入`scons`进行编译。 + +2. 编译完成后在 bsp 目录下会生成 `rtthread-zynqmp-r5.elf` 文件。 + +3. 使用 Xilinx Vitis 产生 FSBL，然后创建 “Debug Configuration”，Application 选择`rtthread-zynqmp-r5.elf` 文件。 + +4. 使用调试器连接 PC 和开发板，通过拨码开关设置为 JTAG 启动，然后连接电源，点击开始调试或运行即可。 + + 由于编译时默认带有调试信息（见 rtconfig.py 中 BUILD），所以在 Xilinx Vitis 中调试时同样可以打开源文件设断点进行调试。 + +#### 固化程序 + +1. 在 bsp 下打开 env 工具，输入`scons`进行编译。 + +2. 编译完成后在 bsp 目录下会生成 `rtthread-zynqmp-r5.elf` 文件。 + +3. 使用 Xilinx Vitis 或 Xilinx SDK 产生 FSBL，然后使用 Xilinx 提供的 bootgen 工具制作 BOOT.bin 文件。 + + 例如使用命令行方式： + + ``` + bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on + ``` + + 其中 output.bif 文件可以是： + ``` + //arch = zynqmp; split = false; format = BIN + the_ROM_image: + { + [bootloader, destination_cpu = r5-0]./fsbl.elf + [destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf + } + ``` + +4. 根据 ALINX 提供的文档将 BOOT.bin 放进SD卡或烧录到 QSPI FLASH 中，通过拨码开关设置启动方式，然后连接电源即可启动。 + + +#### 运行结果 + +下载程序成功之后，系统会自动运行。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Nov 27 2020 + 2006 - 2020 Copyright by rt-thread team +msh /> +``` + +### 进阶使用 + +此 BSP 默认开启了 EMMC 驱动和 DFS 文件系统，如果需要使用文件系统可以自行格式化并挂载。 + + +## 板级移植 + +如果需要将BSP移植到其他 XILINX Zynq UltraScale+ MPSoCs 开发平台的开发板上也比较方便，主要修改的地方有以下几点： + +1. 内存： 如果 DDR memory 小于 2G，需要修改`zynqmp-r5.ld`链接文件中的`psu_r5_ddr_0_MEM_0` +2. 主频： `xparameters.h`中的`XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ` +3. 串口引脚和频率：`drv_uart.c`中的`rxmio`, `txmio` 和`xparameters.h`中的`XPAR_PSU_UART_0_UART_CLK_FREQ_HZ` +4. 定时器频率：`xparameters.h`中的`XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ` +5. SD控制器：`drv_sdcard.c`中的块设备驱动初始化 + +以上需要修改的`xparameters.h`中的参数宏定义不需要手动修改，可以直接将Xilinx Vitis中产生的开发板的`xparameters.h`文件复制过来即可。 + + + +## 注意事项 + +- 无 + +## 联系人信息 + +维护人: + +- [王华辰](https://github.com/Wang-Huachen/) diff --git a/bsp/zynqmp-r5-axu4ev/SConscript b/bsp/zynqmp-r5-axu4ev/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/zynqmp-r5-axu4ev/SConstruct b/bsp/zynqmp-r5-axu4ev/SConstruct new file mode 100644 index 0000000000..6184c03b76 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/SConstruct @@ -0,0 +1,30 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-zynqmp-r5.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/zynqmp-r5-axu4ev/applications/SConscript b/bsp/zynqmp-r5-axu4ev/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/zynqmp-r5-axu4ev/applications/main.c b/bsp/zynqmp-r5-axu4ev/applications/main.c new file mode 100644 index 0000000000..fc02d95e80 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/applications/main.c @@ -0,0 +1,18 @@ +#include +#include + +#define LED_PIN 40 +int main(void) +{ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Kconfig b/bsp/zynqmp-r5-axu4ev/drivers/Kconfig new file mode 100644 index 0000000000..fd16c490f9 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Kconfig @@ -0,0 +1,35 @@ +menu "Hardware Drivers Config" + + menu "Onboard Peripheral Drivers" + + endmenu + + menu "On-chip Peripheral Drivers" + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default y + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default y + if BSP_USING_SDIO + config BSP_USING_SD0 + bool "Enable SD0 EMMC" + default y + endif + + endmenu + + menu "Board extended module Drivers" + + endmenu + +endmenu + diff --git a/bsp/zynqmp-r5-axu4ev/drivers/SConscript b/bsp/zynqmp-r5-axu4ev/drivers/SConscript new file mode 100644 index 0000000000..9538525944 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/SConscript @@ -0,0 +1,26 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +list = os.listdir(cwd) +CPPPATH = [cwd] +objs = [] + +if not GetDepend('BSP_USING_UART'): + SrcRemove(src, ['drv_uart.c']) + +if not GetDepend('BSP_USING_SDIO'): + SrcRemove(src, ['drv_sdcard.c']) + +if not GetDepend('RT_USING_PIN'): + SrcRemove(src, ['drv_gpio.c']) + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group + +Return('objs') diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/SConscript b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/SConscript new file mode 100644 index 0000000000..03f0e5d26d --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/SConscript @@ -0,0 +1,17 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] +objs = [] + +group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH) + +if GetDepend('BSP_USING_SDIO'): + objs = objs + SConscript('sdps_v3_9/SConscript') +if GetDepend('RT_USING_PIN'): + objs = objs + SConscript('gpiops_v3_7/SConscript') + +objs = objs + group + +Return('objs') diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/SConscript b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/SConscript new file mode 100644 index 0000000000..8e5fc7069e --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/SConscript @@ -0,0 +1,15 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() +CPPPATH = [cwd] + +# The set of source files associated with this SConscript file. + +src = Glob('*.c') +path = cwd + +group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c new file mode 100644 index 0000000000..7a318e3819 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c @@ -0,0 +1,808 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xgpiops.c +* @addtogroup gpiops_v3_7 +* @{ +* +* The XGpioPs driver. Functions in this file are the minimum required functions +* for this driver. See xgpiops.h for a detailed description of the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device. The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1   aru  07/13/18 Resolved doxygen reported warnings. CR# 1006331.
+* 3.4   aru  08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+* 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
+*                     in safety mode and modified the code such as
+*                     Use of mixed mode arithmetic,Declared the pointer param
+*                     as Pointer to const,Casting operation to a pointer,
+*                     Literal value requires a U suffix.
+* 3.5   sne  03/13/19 Added Versal support.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xgpiops.h" + +/************************** Constant Definitions *****************************/ +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + +extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status); + +/*****************************************************************************/ +/* +* +* This function initializes a XGpioPs instance/driver. +* All members of the XGpioPs instance structure are initialized and +* StubHandlers are assigned to the Bank Status Handlers. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param ConfigPtr points to the XGpioPs device configuration structure. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. If the address translation is not used then the +* physical address should be passed. +* Unexpected errors may occur if the address mapping is changed +* after this function is invoked. +* +* @return XST_SUCCESS always. +* +* @note None. +* +******************************************************************************/ +s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr, + u32 EffectiveAddr) +{ + s32 Status = XST_SUCCESS; + u8 i; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + Xil_AssertNonvoid(EffectiveAddr != (u32)0); + /* + * Set some default values for instance data, don't indicate the device + * is ready to use until everything has been initialized successfully. + */ + InstancePtr->IsReady = 0U; + InstancePtr->GpioConfig.BaseAddr = EffectiveAddr; + InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Handler = (XGpioPs_Handler)StubHandler; + InstancePtr->Platform = XGetPlatform_Info(); + + /* Initialize the Bank data based on platform */ + if (InstancePtr->Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) { + /* + * Max pins in the ZynqMP GPIO device + * 0 - 25, Bank 0 + * 26 - 51, Bank 1 + * 52 - 77, Bank 2 + * 78 - 109, Bank 3 + * 110 - 141, Bank 4 + * 142 - 173, Bank 5 + */ + InstancePtr->MaxPinNum = (u32)174; + InstancePtr->MaxBanks = (u8)6; + } + else if (InstancePtr->Platform == (u32)XPLAT_VERSAL) + { + if(InstancePtr->PmcGpio == (u32)FALSE) + { + /* Max pins in the PS_GPIO devices + * 0 -25, Bank 0 + * 26-57, Bank 3 + */ + InstancePtr->MaxPinNum = (u32)58; + InstancePtr->MaxBanks = (u8)4; + } + else + { + /* Max pins in the PMC_GPIO devices + * 0 - 25,Bank 0 + * 26 - 51,Bank 1 + * 52 - 83,Bank 3 + * 84 - 115, Bank 4 + */ + InstancePtr->MaxPinNum = (u32)116; + InstancePtr->MaxBanks = (u8)5; + } + } + else { + /* + * Max pins in the GPIO device + * 0 - 31, Bank 0 + * 32 - 53, Bank 1 + * 54 - 85, Bank 2 + * 86 - 117, Bank 3 + */ + InstancePtr->MaxPinNum = (u32)118; + InstancePtr->MaxBanks = (u8)4; + } + + /* + * By default, interrupts are not masked in GPIO. Disable + * interrupts for all pins in all the 4 banks. + */ + for (i=(u8)0U;iMaxBanks;i++) { + if (InstancePtr->Platform == XPLAT_VERSAL){ + if(InstancePtr->PmcGpio == (u32)FALSE) + { + if((i== (u8)XGPIOPS_ONE)||(i== (u8)XGPIOPS_TWO)) + { + continue; + } + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); + } + else + { + if(i==(u32)XGPIOPS_TWO) + { + continue; + } + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); + + } + } + else + { + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU); + } + } + + /* Indicate the component is now ready to use. */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return Status; +} + +/****************************************************************************/ +/** +* +* Read the Data register of the specified GPIO bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* +* @return Current value of the Data register. +* +* @note This function is used for reading the state of all the GPIO pins +* of specified bank. +* +*****************************************************************************/ +u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertNonvoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) + + XGPIOPS_DATA_RO_OFFSET); +} + +/****************************************************************************/ +/** +* +* Read Data from the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number for which the data has to be read. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* See xgpiops.h for the mapping of the pin numbers in the banks. +* +* @return Current value of the Pin (0 or 1). +* +* @note This function is used for reading the state of the specified +* GPIO pin. +* +*****************************************************************************/ +u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin) +{ + u8 Bank; + u8 PinNumber; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) + + XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1; + +} + +/****************************************************************************/ +/** +* +* Write to the Data register of the specified GPIO bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* @param Data is the value to be written to the Data register. +* +* @return None. +* +* @note This function is used for writing to all the GPIO pins of +* the bank. The previous state of the pins is not maintained. +* +*****************************************************************************/ +void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertVoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) + + XGPIOPS_DATA_OFFSET, Data); +} + +/****************************************************************************/ +/** +* +* Write data to the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number to which the Data is to be written. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* @param Data is the data to be written to the specified pin (0 or 1). +* +* @return None. +* +* @note This function does a masked write to the specified pin of +* the specified GPIO bank. The previous state of other pins +* is maintained. +* +*****************************************************************************/ +void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data) +{ + u32 RegOffset; + u32 Value; + u8 Bank; + u8 PinNumber; + u32 DataVar = Data; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + if (PinNumber > 15U) { + /* There are only 16 data bits in bit maskable register. */ + PinNumber -= (u8)16; + RegOffset = XGPIOPS_DATA_MSW_OFFSET; + } else { + RegOffset = XGPIOPS_DATA_LSW_OFFSET; + } + + /* + * Get the 32 bit value to be written to the Mask/Data register where + * the upper 16 bits is the mask and lower 16 bits is the data. + */ + DataVar &= (u32)0x01; + Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U); + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) + + RegOffset, Value); + +} + + + +/****************************************************************************/ +/** +* +* Set the Direction of the pins of the specified GPIO Bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* @param Direction is the 32 bit mask of the Pin direction to be set for +* all the pins in the Bank. Bits with 0 are set to Input mode, +* bits with 1 are set to Output Mode. +* +* @return None. +* +* @note This function is used for setting the direction of all the pins +* in the specified bank. The previous state of the pins is +* not maintained. +* +*****************************************************************************/ +void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertVoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_DIRM_OFFSET, Direction); +} + +/****************************************************************************/ +/** +* +* Set the Direction of the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number to which the Data is to be written. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* @param Direction is the direction to be set for the specified pin. +* Valid values are 0 for Input Direction, 1 for Output Direction. +* +* @return None. +* +*****************************************************************************/ +void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction) +{ + u8 Bank; + u8 PinNumber; + u32 DirModeReg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); + Xil_AssertVoid(Direction <= (u32)1); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_DIRM_OFFSET); + + if (Direction!=(u32)0) { /* Output Direction */ + DirModeReg |= ((u32)1 << (u32)PinNumber); + } else { /* Input Direction */ + DirModeReg &= ~ ((u32)1 << (u32)PinNumber); + } + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_DIRM_OFFSET, DirModeReg); +} + +/****************************************************************************/ +/** +* +* Get the Direction of the pins of the specified GPIO Bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* +* @return Returns a 32 bit mask of the Direction register. Bits with 0 are +* in Input mode, bits with 1 are in Output Mode. +* +* @note None. +* +*****************************************************************************/ +u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertNonvoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_DIRM_OFFSET); +} + +/****************************************************************************/ +/** +* +* Get the Direction of the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number for which the Direction is to be +* retrieved. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* +* @return Direction of the specified pin. +* - 0 for Input Direction +* - 1 for Output Direction +* +* @note None. +* +*****************************************************************************/ +u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin) +{ + u8 Bank; + u8 PinNumber; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1; +} + +/****************************************************************************/ +/** +* +* Set the Output Enable of the pins of the specified GPIO Bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* @param OpEnable is the 32 bit mask of the Output Enables to be set for +* all the pins in the Bank. The Output Enable of bits with 0 are +* disabled, the Output Enable of bits with 1 are enabled. +* +* @return None. +* +* @note This function is used for setting the Output Enables of all the +* pins in the specified bank. The previous state of the Output +* Enables is not maintained. +* +*****************************************************************************/ +void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertVoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_OUTEN_OFFSET, OpEnable); +} + +/****************************************************************************/ +/** +* +* Set the Output Enable of the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number to which the Data is to be written. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* @param OpEnable specifies whether the Output Enable for the specified +* pin should be enabled. +* Valid values are 0 for Disabling Output Enable, +* 1 for Enabling Output Enable. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable) +{ + u8 Bank; + u8 PinNumber; + u32 OpEnableReg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); + Xil_AssertVoid(OpEnable <= (u32)1); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_OUTEN_OFFSET); + + if (OpEnable != (u32)0) { /* Enable Output Enable */ + OpEnableReg |= ((u32)1 << (u32)PinNumber); + } else { /* Disable Output Enable */ + OpEnableReg &= ~ ((u32)1 << (u32)PinNumber); + } + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_OUTEN_OFFSET, OpEnableReg); +} +/****************************************************************************/ +/** +* +* Get the Output Enable status of the pins of the specified GPIO Bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* +* @return Returns a a 32 bit mask of the Output Enable register. +* Bits with 0 are in Disabled state, bits with 1 are in +* Enabled State. +* +* @note None. +* +*****************************************************************************/ +u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertNonvoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_OUTEN_OFFSET); +} + +/****************************************************************************/ +/** +* +* Get the Output Enable status of the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number for which the Output Enable status is to +* be retrieved. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* +* @return Output Enable of the specified pin. +* - 0 if Output Enable is disabled for this pin +* - 1 if Output Enable is enabled for this pin +* +* @note None. +* +*****************************************************************************/ +u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin) +{ + u8 Bank; + u8 PinNumber; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1; +} + +/****************************************************************************/ +/* +* +* Get the Bank number and the Pin number in the Bank, for the given PinNumber +* in the GPIO device. +* +* @param PinNumber is the Pin number in the GPIO device. +* @param BankNumber returns the Bank in which this GPIO pin is present. +* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. +* @param PinNumberInBank returns the Pin Number within the Bank. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#ifdef versal +void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank) +#else +void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank) +#endif +{ + u32 XGpioPsPinTable[6] = {0}; +#ifdef versal + u8 i=(u8)0; +#endif + u32 Platform = XGetPlatform_Info(); + + if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) { + /* + * This structure defines the mapping of the pin numbers to the banks when + * the driver APIs are used for working on the individual pins. + */ + + XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */ + XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */ + XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */ + XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */ + XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */ + XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */ + + *BankNumber = 0U; + while (*BankNumber < XGPIOPS_SIX) { + if (PinNumber <= XGpioPsPinTable[*BankNumber]) { + break; + } + (*BankNumber)++; + } + } +#ifdef versal + else if(Platform == XPLAT_VERSAL) + { + if(InstancePtr->PmcGpio == (u32)(FALSE)) + { + XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */ + XGpioPsPinTable[1] = (u32)57; /* 26 - 57, Bank 3 */ + *BankNumber =0U; + if(PinNumber <= XGpioPsPinTable[*BankNumber]) + { + *BankNumber = (u8)XGPIOPS_ZERO; + } + else + { + *BankNumber = (u8)XGPIOPS_THREE; + } + + } + else + { + XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */ + XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */ + XGpioPsPinTable[2] = (u32)83; /* 52 - 83, Bank 3 */ + XGpioPsPinTable[3] = (u32)115; /*84 - 115, Bank 4 */ + + *BankNumber =0U; + while(i < XGPIOPS_FOUR) + { + if(i <= (u8)XGPIOPS_ONE) + { + if (PinNumber <= XGpioPsPinTable[i]) + { + *BankNumber = (u8)i; + break; + } + i++; + } + else + { + if (PinNumber <= XGpioPsPinTable[i]) + { + *BankNumber = (u8)i+1U; + break; + } + i++; + } + + } + } + + } +#endif + else { + XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */ + XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */ + XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */ + XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */ + + *BankNumber = 0U; + while (*BankNumber < XGPIOPS_FOUR) { + if (PinNumber <= XGpioPsPinTable[*BankNumber]) { + break; + } + (*BankNumber)++; + } + } + if (*BankNumber == (u8)0) { + *PinNumberInBank = PinNumber; + } + +#ifdef versal + else if(Platform == XPLAT_VERSAL) + { + if(InstancePtr->PmcGpio == (u32)(FALSE)) + { + *PinNumberInBank = (u8)((u32)PinNumber - (XGpioPsPinTable[0] + (u32)1)); + } + else { + if((*BankNumber ==(u8)XGPIOPS_THREE) || (*BankNumber ==(u8)XGPIOPS_FOUR)) + { + *PinNumberInBank = (u8)((u32)PinNumber % + (XGpioPsPinTable[*BankNumber - (u8)XGPIOPS_TWO] + (u32)1)); + } + else + { + *PinNumberInBank = (u8)((u32)PinNumber % + (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1)); + } + } + + } +#endif + + else { + *PinNumberInBank = (u8)((u32)PinNumber % + (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1)); + } +} +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h new file mode 100644 index 0000000000..b030e60686 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h @@ -0,0 +1,267 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xgpiops.h +* @addtogroup gpiops_v3_7 +* @{ +* @details +* +* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO +* Controller. +* +* The GPIO Controller supports the following features: +* - 4 banks +* - Masked writes (There are no masked reads) +* - Bypass mode +* - Configurable Interrupts (Level/Edge) +* +* This driver is intended to be RTOS and processor independent. Any needs for +* dynamic memory management, threads or thread mutual exclusion, virtual +* memory, or cache control must be satisfied by the layer above this driver. + +* This driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the GPIO. +* +* Interrupts +* +* The driver provides interrupt management functions and an interrupt handler. +* Users of this driver need to provide callback functions. An interrupt handler +* example is available with the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XGpioPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*       ms   04/05/17 Added tabspace for return statements in functions of
+*                     gpiops examples for proper documentation while
+*                     generating doxygen.
+* 3.3   ms   04/17/17 Added notes about gpio input and output pin description
+*                     for zcu102 and zc702 boards in polled and interrupt
+*                     example, configured Interrupt pin to input pin for
+*                     proper functioning of interrupt example.
+* 3.4   aru  08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+* 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
+*                     in safety mode and modified the code such as
+*                     Use of mixed mode arithmetic,Declared the pointer param
+*                     as Pointer to const,Casting operation to a pointer,
+*                     Literal value requires a U suffix.
+* 3.5   sne  03/14/19 Added Versal support.
+* 3.6   mus  04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
+*                     sync with standalone BSP
+* 3.6	sne  06/12/19 Fixed IAR compiler warning.
+* 3.6   sne  08/14/19 Added interrupt handler support on versal.
+* 3.7	sne  12/04/19 Reverted versal examples support.
+*
+*
+* +******************************************************************************/ +#ifndef XGPIOPS_H /* prevent circular inclusions */ +#define XGPIOPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xgpiops_hw.h" +#include "xplatform_info.h" + +/************************** Constant Definitions *****************************/ + +/** @name Interrupt types + * @{ + * The following constants define the interrupt types that can be set for each + * GPIO pin. + */ +#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */ +#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */ +#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */ +/*@}*/ + +#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ +#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */ +#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */ +#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */ +#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */ + +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */ +#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */ +#endif + +#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a + * Zynq Ultrascale+ MP GPIO device + */ +#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */ + +#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the + * Zynq Ultrascale+ MP GPIO device + * 0 - 25, Bank 0 + * 26 - 51, Bank 1 + * 52 - 77, Bank 2 + * 78 - 109, Bank 3 + * 110 - 141, Bank 4 + * 142 - 173, Bank 5 + */ +#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device + * 0 - 31, Bank 0 + * 32 - 53, Bank 1 + * 54 - 85, Bank 2 + * 86 - 117, Bank 3 + */ + +/**************************** Type Definitions *******************************/ + +/****************************************************************************/ +/** + * This handler data type allows the user to define a callback function to + * handle the interrupts for the GPIO device. The application using this + * driver is expected to define a handler of this type, to support interrupt + * driven mode. The handler executes in an interrupt context such that minimal + * processing should be performed. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions for a GPIO bank. It is + * passed back to the upper layer when the callback is invoked. Its + * type is not important to the driver component, so it is a void + * pointer. + * @param Bank is the bank for which the interrupt status has changed. + * @param Status is the Interrupt status of the GPIO bank. + * + *****************************************************************************/ +typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status); + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XGpioPs_Config; + +/** + * The XGpioPs driver instance data. The user is required to allocate a + * variable of this type for the GPIO device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XGpioPs_Config GpioConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + XGpioPs_Handler Handler; /**< Status handlers for all banks */ + void *CallBackRef; /**< Callback ref for bank handlers */ + u32 Platform; /**< Platform data */ + u32 MaxPinNum; /**< Max pins in the GPIO device */ + u8 MaxBanks; /**< Max banks in a GPIO device */ + u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/ +} XGpioPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/* Functions in xgpiops.c */ +s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr, + u32 EffectiveAddr); + +/* Bank APIs in xgpiops.c */ +u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data); +void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction); +u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable); +u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank); +#ifdef versal +void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank); +#else +void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank); +#endif + +/* Pin APIs in xgpiops.c */ +u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data); +void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction); +u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable); +u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin); + +/* Diagnostic functions in xgpiops_selftest.c */ +s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr); + +/* Functions in xgpiops_intr.c */ +/* Bank APIs in xgpiops_intr.c */ +void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); +u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank); +u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType, + u32 IntrPolarity, u32 IntrOnAny); +void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, + u32 *IntrPolarity, u32 *IntrOnAny); +void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, + XGpioPs_Handler FuncPointer); +void XGpioPs_IntrHandler(const XGpioPs *InstancePtr); + +/* Pin APIs in xgpiops_intr.c */ +void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType); +u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin); + +void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin); + +/* Functions in xgpiops_sinit.c */ +XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c new file mode 100644 index 0000000000..43f53df958 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2020.1 +* DO NOT EDIT. +* +* Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xgpiops.h" + +/* +* The configuration table for devices +*/ + +XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = +{ + { + XPAR_PSU_GPIO_0_DEVICE_ID, + XPAR_PSU_GPIO_0_BASEADDR + } +}; + + diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c new file mode 100644 index 0000000000..86ed7e868e --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c @@ -0,0 +1,240 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xgpiops_hw.c +* @addtogroup gpiops_v3_7 +* @{ +* +* This file contains low level GPIO functions. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk   08/22/13 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
+*                     in safety mode and modified the code such as
+*                     Use of mixed mode arithmetic,Declared the pointer param
+*                     as Pointer to const,Casting operation to a pointer,
+*                     Literal value requires a U suffix.
+* 3.5   sne  03/14/19 Added versal support.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xgpiops_hw.h" +#include "xgpiops.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + + +/*****************************************************************************/ +/* +* +* This function resets the GPIO module by writing reset values to +* all registers +* +* @param Base address of GPIO module +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XGpioPs_ResetHw(u32 BaseAddress) +{ + u32 BankCount; + u32 Platform,MaxBanks; + + Platform = XGetPlatform_Info(); + if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) { + MaxBanks = (u32)6; + } + else if(Platform == (u32)XPLAT_VERSAL) + { + if (BaseAddress == (u32)XGPIOPS_PS_GPIO_BASEADDR) + { + MaxBanks = (u32)4; + } + else + { + MaxBanks = (u32)5; + } + } + else { + MaxBanks = (u32)4; + } + + if (Platform == (u32)XPLAT_VERSAL) + { + /* Write reset values to all mask data registers */ + for(BankCount = 3U; BankCount < (u32)MaxBanks; BankCount++) { + + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_DATA_MASK_OFFSET) + + XGPIOPS_DATA_LSW_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_DATA_MASK_OFFSET) + + XGPIOPS_DATA_MSW_OFFSET), 0x0U); + } + /* Write reset values to all output data registers */ + for(BankCount = 3U; BankCount < (u32)MaxBanks; BankCount++) { + + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_DATA_BANK_OFFSET) + + XGPIOPS_DATA_OFFSET), 0x0U); + } + + /* Reset all registers of all GPIO banks */ + for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) { + + + if((BaseAddress == (u32)XGPIOPS_PS_GPIO_BASEADDR) && ((BankCount == (u32)XGPIOPS_ONE) ||(BankCount == (u32)XGPIOPS_TWO))) + { + continue; + } + else + { + if((BaseAddress != (u32)XGPIOPS_PS_GPIO_BASEADDR) && (BankCount == (u32)XGPIOPS_ONE)) + { + continue; + } + } + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_DIRM_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_OUTEN_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTMASK_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTEN_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTDIS_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTSTS_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTPOL_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTANY_OFFSET), 0x0U); + + } + + /* Bank 0 Int type */ + XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET, + XGPIOPS_INTTYPE_BANK0_RESET); + /* Bank 1 Int type */ + XGpioPs_WriteReg(BaseAddress, + ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK1_RESET); + /* Bank 3 Int type */ + XGpioPs_WriteReg(BaseAddress, + (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK3_RESET); + /* Bank 4 Int type */ + XGpioPs_WriteReg(BaseAddress, + (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK4_RESET); + } + else + { + /* Write reset values to all mask data registers */ + for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) { + + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_DATA_MASK_OFFSET) + + XGPIOPS_DATA_LSW_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_DATA_MASK_OFFSET) + + XGPIOPS_DATA_MSW_OFFSET), 0x0U); + } + /* Write reset values to all output data registers */ + for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) { + + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_DATA_BANK_OFFSET) + + XGPIOPS_DATA_OFFSET), 0x0U); + } + /* Reset all registers of all GPIO banks */ + for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) { + + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_DIRM_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_OUTEN_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTMASK_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTEN_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTDIS_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTSTS_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTPOL_OFFSET), 0x0U); + XGpioPs_WriteReg(BaseAddress, + ((BankCount * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTANY_OFFSET), 0x0U); + } + /* Bank 0 Int type */ + XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET, + XGPIOPS_INTTYPE_BANK0_RESET); + /* Bank 1 Int type */ + XGpioPs_WriteReg(BaseAddress, + ((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK1_RESET); + /* Bank 2 Int type */ + XGpioPs_WriteReg(BaseAddress, + (((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK2_RESET); + /* Bank 3 Int type */ + XGpioPs_WriteReg(BaseAddress, + (((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK3_RESET); + + if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) { + /* Bank 4 Int type */ + XGpioPs_WriteReg(BaseAddress, + (((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK4_RESET); + /* Bank 5 Int type */ + XGpioPs_WriteReg(BaseAddress, + (((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), + XGPIOPS_INTTYPE_BANK5_RESET); + } + } + +} +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h new file mode 100644 index 0000000000..bb22e2d59f --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h @@ -0,0 +1,146 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xgpiops_hw.h +* @addtogroup gpiops_v3_7 +* @{ +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xgpiops.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+* 3.5   sne  03/14/19 Added versal support.
+*
+* +******************************************************************************/ +#ifndef XGPIOPS_HW_H /* prevent circular inclusions */ +#define XGPIOPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the GPIO. Each register is 32 bits. + * @{ + */ +#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */ +#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */ +#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */ +#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */ +#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */ +#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */ +#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */ +#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */ +#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/ +#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */ +#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */ +#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */ +#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */ +/* @} */ + +/** @name Register offsets for each Bank. + * @{ + */ +#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */ +#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */ +#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */ +/* @} */ + +/* For backwards compatibility */ +#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 + +/** @name Interrupt type reset values for each bank + * @{ + */ +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU +#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU +#else +#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */ +#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU +#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU +#endif + +#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */ +#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU +/* @} */ +#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /* Flag for Base Address for PS_GPIO in Versal */ +#define XGPIOPS_ZERO 0U /* Flag for 0 Value */ +#define XGPIOPS_ONE 1U /* Flag for 1 Value */ +#define XGPIOPS_TWO 2U /* Flag for 2 Value */ +#define XGPIOPS_THREE 3U /* Flag for 3 Value */ +#define XGPIOPS_FOUR 4U /* Flag for 4 Value */ +#define XGPIOPS_SIX 6U /* Flag for 6 Value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes to the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the offset of the register to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ + +void XGpioPs_ResetHw(u32 BaseAddress); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XGPIOPS_HW_H */ +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c new file mode 100644 index 0000000000..c70de1aec6 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c @@ -0,0 +1,805 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xgpiops_intr.c +* @addtogroup gpiops_v3_7 +* @{ +* +* This file contains functions related to GPIO interrupt handling. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to API's. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 3.1   aru  07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
+* 3.4   aru  08/09/18 Ressolved cppcheck warnings.
+* 3.4   aru  08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
+* 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
+*                     in safety mode and modified the code such as
+*                     Use of mixed mode arithmetic,Declared the pointer param
+*                     as Pointer to const,Casting operation to a pointer,
+*                     Literal value requires a U suffix.
+* 3.5   sne  03/14/19 Added Versal support.
+* 3.5   sne  03/20/19 Fixed multiple interrupts problem CR#1024556.
+* 3.6	sne  06/12/19 Fixed IAR compiler warning.
+* 3.6   sne  08/14/19 Added interrupt handler support on versal.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xgpiops.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void StubHandler(const void *CallBackRef, u32 Bank, u32 Status); + +/****************************************************************************/ +/** +* +* This function enables the interrupts for the specified pins in the specified +* bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* @param Mask is the bit mask of the pins for which interrupts are to +* be enabled. Bit positions of 1 will be enabled. Bit positions +* of 0 will keep the previous setting. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertVoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTEN_OFFSET, Mask); +} + +/****************************************************************************/ +/** +* +* This function enables the interrupt for the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number for which the interrupt is to be enabled. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin) +{ + u8 Bank; + u8 PinNumber; + u32 IntrReg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + IntrReg = ((u32)1 << (u32)PinNumber); + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTEN_OFFSET, IntrReg); +} + +/****************************************************************************/ +/** +* +* This function disables the interrupts for the specified pins in the specified +* bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* @param Mask is the bit mask of the pins for which interrupts are +* to be disabled. Bit positions of 1 will be disabled. Bit +* positions of 0 will keep the previous setting. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertVoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTDIS_OFFSET, Mask); +} + +/****************************************************************************/ +/** +* +* This function disables the interrupts for the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number for which the interrupt is to be disabled. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin) +{ + u8 Bank; + u8 PinNumber; + u32 IntrReg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + IntrReg = ((u32)1 << (u32)PinNumber); + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTDIS_OFFSET, IntrReg); +} + +/****************************************************************************/ +/** +* +* This function returns the interrupt enable status for a bank. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* +* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1 +* indicate that the interrupt for that pin is enabled, bit +* positions with 0 indicate that the interrupt for that pin is +* disabled. +* +* @note None. +* +*****************************************************************************/ +u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank) +{ + u32 IntrMask; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertNonvoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTMASK_OFFSET); + return (~IntrMask); +} + +/****************************************************************************/ +/** +* +* This function returns whether interrupts are enabled for the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number for which the interrupt enable status +* is to be known. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* +* @return +* - TRUE if the interrupt is enabled. +* - FALSE if the interrupt is disabled. +* +* @note None. +* +*****************************************************************************/ +u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin) +{ + u8 Bank; + u8 PinNumber; + u32 IntrReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTMASK_OFFSET); + + return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE); +} + +/****************************************************************************/ +/** +* +* This function returns interrupt status read from Interrupt Status Register. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* +* @return The value read from Interrupt Status Register. +* +* @note None. +* +*****************************************************************************/ +u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertNonvoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTSTS_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function returns interrupt enable status of the specified pin. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number for which the interrupt enable status +* is to be known. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* +* @return +* - TRUE if the interrupt has occurred. +* - FALSE if the interrupt has not occurred. +* +* @note None. +* +*****************************************************************************/ +u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin) +{ + u8 Bank; + u8 PinNumber; + u32 IntrReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTSTS_OFFSET); + + return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE); +} + +/****************************************************************************/ +/** +* +* This function clears pending interrupt(s) with the provided mask. This +* function should be called after the software has serviced the interrupts +* that are pending. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* @param Mask is the mask of the interrupts to be cleared. Bit positions +* of 1 will be cleared. Bit positions of 0 will not change the +* previous interrupt status. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertVoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + /* Clear the currently pending interrupts. */ + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTSTS_OFFSET, Mask); +} + +/****************************************************************************/ +/** +* +* This function clears the specified pending interrupt. This function should be +* called after the software has serviced the interrupts that are pending. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param Pin is the pin number for which the interrupt status is to be +* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin) +{ + u8 Bank; + u8 PinNumber; + u32 IntrReg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + /* Clear the specified pending interrupts. */ + IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTSTS_OFFSET); + + IntrReg &= ((u32)1 << PinNumber); + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTSTS_OFFSET, IntrReg); +} + +/****************************************************************************/ +/** +* +* This function is used for setting the Interrupt Type, Interrupt Polarity and +* Interrupt On Any for the specified GPIO Bank pins. +* +* @param InstancePtr is a pointer to an XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* @param IntrType is the 32 bit mask of the interrupt type. +* 0 means Level Sensitive and 1 means Edge Sensitive. +* @param IntrPolarity is the 32 bit mask of the interrupt polarity. +* 0 means Active Low or Falling Edge and 1 means Active High or +* Rising Edge. +* @param IntrOnAny is the 32 bit mask of the interrupt trigger for +* edge triggered interrupts. 0 means trigger on single edge using +* the configured interrupt polarity and 1 means trigger on both +* edges. +* +* @return None. +* +* @note This function is used for setting the interrupt related +* properties of all the pins in the specified bank. The previous +* state of the pins is not maintained. +* To change the Interrupt properties of a single GPIO pin, use the +* function XGpioPs_SetPinIntrType(). +* +*****************************************************************************/ +void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType, + u32 IntrPolarity, u32 IntrOnAny) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertVoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTTYPE_OFFSET, IntrType); + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTPOL_OFFSET, IntrPolarity); + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTANY_OFFSET, IntrOnAny); +} + +/****************************************************************************/ +/** +* +* This function is used for getting the Interrupt Type, Interrupt Polarity and +* Interrupt On Any for the specified GPIO Bank pins. +* +* @param InstancePtr is a pointer to an XGpioPs instance. +* @param Bank is the bank number of the GPIO to operate on. +* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP. +* @param IntrType returns the 32 bit mask of the interrupt type. +* 0 means Level Sensitive and 1 means Edge Sensitive. +* @param IntrPolarity returns the 32 bit mask of the interrupt +* polarity. 0 means Active Low or Falling Edge and 1 means +* Active High or Rising Edge. +* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for +* edge triggered interrupts. 0 means trigger on single edge using +* the configured interrupt polarity and 1 means trigger on both +* edges. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, + u32 *IntrPolarity, u32 *IntrOnAny) + +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Bank < InstancePtr->MaxBanks); +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + Xil_AssertVoid(Bank != XGPIOPS_TWO); + } else { + Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO)); + } +#endif + + *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTTYPE_OFFSET); + + *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTPOL_OFFSET); + + *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTANY_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function is used for setting the IRQ Type of a single GPIO pin. +* +* @param InstancePtr is a pointer to an XGpioPs instance. +* @param Pin is the pin number whose IRQ type is to be set. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_* +* defined in xgpiops.h to specify the IRQ type. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType) +{ + u32 IntrTypeReg; + u32 IntrPolReg; + u32 IntrOnAnyReg; + u8 Bank; + u8 PinNumber; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(Pin < InstancePtr->MaxPinNum); + Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTTYPE_OFFSET); + + IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTPOL_OFFSET); + + IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTANY_OFFSET); + + switch (IrqType) { + case XGPIOPS_IRQ_TYPE_EDGE_RISING: + IntrTypeReg |= ((u32)1 << (u32)PinNumber); + IntrPolReg |= ((u32)1 << (u32)PinNumber); + IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber); + break; + case XGPIOPS_IRQ_TYPE_EDGE_FALLING: + IntrTypeReg |= ((u32)1 << (u32)PinNumber); + IntrPolReg &= ~((u32)1 << (u32)PinNumber); + IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber); + break; + case XGPIOPS_IRQ_TYPE_EDGE_BOTH: + IntrTypeReg |= ((u32)1 << (u32)PinNumber); + IntrOnAnyReg |= ((u32)1 << (u32)PinNumber); + break; + case XGPIOPS_IRQ_TYPE_LEVEL_HIGH: + IntrTypeReg &= ~((u32)1 << (u32)PinNumber); + IntrPolReg |= ((u32)1 << (u32)PinNumber); + break; + case XGPIOPS_IRQ_TYPE_LEVEL_LOW: + IntrTypeReg &= ~((u32)1 << (u32)PinNumber); + IntrPolReg &= ~((u32)1 << (u32)PinNumber); + break; + default: + /**< Default statement is added for MISRA C compliance. */ + break; + } + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTTYPE_OFFSET, IntrTypeReg); + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTPOL_OFFSET, IntrPolReg); + + XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTANY_OFFSET, IntrOnAnyReg); +} + +/****************************************************************************/ +/** +* +* This function returns the IRQ Type of a given GPIO pin. +* +* @param InstancePtr is a pointer to an XGpioPs instance. +* @param Pin is the pin number whose IRQ type is to be obtained. +* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP. +* +* @return None. +* +* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type +* returned by this function. +* +*****************************************************************************/ +u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin) +{ + u32 IntrType; + u32 IntrPol; + u32 IntrOnAny; + u8 Bank; + u8 PinNumber; + u8 IrqType; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum); + + /* Get the Bank number and Pin number within the bank. */ +#ifdef versal + XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber); +#else + XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber); +#endif + + IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber); + + if (IntrType == ((u32)1 << PinNumber)) { + + IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber); + + IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber); + + + if (IntrOnAny == ((u32)1 << PinNumber)) { + IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH; + } else if (IntrPol == ((u32)1 << PinNumber)) { + IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING; + } else { + IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING; + } + } else { + + IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, + ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) + + XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber); + + if (IntrPol == ((u32)1 << PinNumber)) { + IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH; + } else { + IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW; + } + } + + return IrqType; +} + +/*****************************************************************************/ +/** +* +* This function sets the status callback function. The callback function is +* called by the XGpioPs_IntrHandler when an interrupt occurs. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* @param CallBackRef is the upper layer callback reference passed back +* when the callback function is invoked. +* @param FuncPointer is the pointer to the callback function. +* +* +* @return None. +* +* @note The handler is called within interrupt context, so it should do +* its work quickly and queue potentially time-consuming work to a +* task-level thread. +* +******************************************************************************/ +void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, + XGpioPs_Handler FuncPointer) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(FuncPointer != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + InstancePtr->Handler = FuncPointer; + InstancePtr->CallBackRef = CallBackRef; +} + +/*****************************************************************************/ +/** +* +* This function is the interrupt handler for GPIO interrupts.It checks the +* interrupt status registers of all the banks to determine the actual bank in +* which an interrupt has been triggered. It then calls the upper layer callback +* handler set by the function XGpioPs_SetBankHandler(). The callback is called +* when an interrupt +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* +* @return None. +* +* @note This function does not save and restore the processor context +* such that the user must provide this processing. +* +******************************************************************************/ +void XGpioPs_IntrHandler(const XGpioPs *InstancePtr) +{ + u8 Bank; + u32 IntrStatus; + u32 IntrEnabled; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) { +#ifdef versal + if(InstancePtr->PmcGpio == TRUE) { + if(Bank == XGPIOPS_TWO) { + continue; + } + } else { + if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) { + continue; + } + } +#endif + IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank); + IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank); + if ((IntrStatus & IntrEnabled) != (u32)0) { + XGpioPs_IntrClear(InstancePtr, Bank, + (IntrStatus & IntrEnabled)); + InstancePtr->Handler(InstancePtr-> + CallBackRef, Bank, + (IntrStatus & IntrEnabled)); + } + } +} + +/*****************************************************************************/ +/** +* +* This is a stub for the status callback. The stub is here in case the upper +* layers do not set the handler. +* +* @param CallBackRef is a pointer to the upper layer callback reference +* @param Bank is the GPIO Bank in which an interrupt occurred. +* @param Status is the Interrupt status of the GPIO bank. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void StubHandler(const void *CallBackRef, u32 Bank, u32 Status) +{ + (void) CallBackRef; + (void) Bank; + (void) Status; + + Xil_AssertVoidAlways(); +} +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c new file mode 100644 index 0000000000..6f5fcf799a --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xgpiops_selftest.c +* @addtogroup gpiops_v3_7 +* @{ +* +* This file contains a diagnostic self-test function for the XGpioPs driver. +* +* Read xgpiops.h file for more information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
+*                     in safety mode and modified the code such as
+*                     Use of mixed mode arithmetic,Declared the pointer param
+*                     as Pointer to const,Casting operation to a pointer,
+*                     Literal value requires a U suffix.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xstatus.h" +#include "xgpiops.h" + +/************************** Constant Definitions ****************************/ + + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the GPIO driver/device. This function +* does a register read/write test on some of the Interrupt Registers. +* +* @param InstancePtr is a pointer to the XGpioPs instance. +* +* @return +* - XST_SUCCESS if the self-test passed. +* - XST_FAILURE otherwise. +* +* +******************************************************************************/ +s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr) +{ + s32 Status = XST_SUCCESS; + u32 IntrEnabled; + u32 CurrentIntrType = 0U; + u32 CurrentIntrPolarity = 0U; + u32 CurrentIntrOnAny = 0U; + u32 IntrType = 0U; + u32 IntrPolarity = 0U; + u32 IntrOnAny = 0U; + u32 IntrTestValue = 0x22U; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Disable the Interrupts for Bank 0 . */ + IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0); + XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled); + + /* + * Get the Current Interrupt properties for Bank 0. + * Set them to a known value, read it back and compare. + */ + XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType, + &CurrentIntrPolarity, &CurrentIntrOnAny); + + XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue, + IntrTestValue, IntrTestValue); + + XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType, + &IntrPolarity, &IntrOnAny); + + if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) && + (IntrOnAny != IntrTestValue)) { + + Status = XST_FAILURE; + } + + /* + * Restore the contents of all the interrupt registers modified in this + * test. + */ + XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType, + CurrentIntrPolarity, CurrentIntrOnAny); + + XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled); + + return Status; +} +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c new file mode 100644 index 0000000000..bfc08a6aed --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xgpiops_sinit.c +* @addtogroup gpiops_v3_7 +* @{ +* +* This file contains the implementation of the XGpioPs driver's static +* initialization functionality. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xgpiops.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES]; + +/*****************************************************************************/ +/** +* +* This function looks for the device configuration based on the unique device +* ID. The table XGpioPs_ConfigTable[] contains the configuration information +* for each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId) +{ + XGpioPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) { + if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XGpioPs_ConfigTable[Index]; + break; + } + } + + return (XGpioPs_Config *)CfgPtr; +} +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/SConscript b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/SConscript new file mode 100644 index 0000000000..8e5fc7069e --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/SConscript @@ -0,0 +1,15 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() +CPPPATH = [cwd] + +# The set of source files associated with this SConscript file. + +src = Glob('*.c') +path = cwd + +group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c new file mode 100644 index 0000000000..d6542b0674 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c @@ -0,0 +1,420 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps.c +* @addtogroup sdps_v3_9 +* @{ +* +* Contains the interface functions of the XSdPs driver. +* See xsdps.h for a detailed description of the device and driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     05/17/17 Add support for 64bit DMA addressing
+*       mn     07/17/17 Add support for running SD at 200MHz
+*       mn     07/26/17 Fixed compilation warnings
+*       mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*       mn     08/17/17 Added CCI support for A53 and disabled data cache
+*                       operations when it is enabled.
+*       mn     08/22/17 Updated for Word Access System support
+*       mn     09/06/17 Resolved compilation errors with IAR toolchain
+*       mn     09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
+* 3.4   mn     10/17/17 Use different commands for single and multi block
+*                       transfers
+*       mn     03/02/18 Move UHS macro check to SD card initialization routine
+* 3.5   mn     04/18/18 Resolve compilation warnings for sdps driver
+* 3.6   mn     07/06/18 Fix Cppcheck and Doxygen warnings for sdps driver
+*       mn     08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+*       mn     08/01/18 Add cache invalidation call before returning from
+*                       ReadPolled API
+*       mn     08/14/18 Resolve compilation warnings for ARMCC toolchain
+*       mn     10/01/18 Change Expected Response for CMD3 to R1 for MMC
+*       mus    11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
+* 3.7   mn     02/01/19 Add support for idling of SDIO
+*       aru    03/12/19 Modified the code according to MISRAC-2012.
+* 3.8   mn     04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+*       mn     09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
+* 3.9   sd     02/07/20 Added clock support
+*       mn     03/03/20 Restructured the code for more readability and modularity
+*       mn     03/30/20 Return XST_DEVICE_IS_STARTED when host is already started
+*       mn     03/30/20 Move Clock enabling before checking for Host already started
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xsdps_core.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +/*****************************************************************************/ +/** +* +* @brief +* Initializes a specific XSdPs instance such that the driver is ready to use. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param ConfigPtr is a reference to a structure containing information +* about a specific SD device. This function initializes an +* InstancePtr object for a specific device specified by the +* contents of Config. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the address +* mapping from EffectiveAddr to the device physical base address +* unchanged once this function is invoked. Unexpected errors may +* occur if the address mapping changes after this function is +* called. If address translation is not used, use +* ConfigPtr->Config.BaseAddress for this device. +* +* @return +* - XST_SUCCESS if successful. +* - XST_DEVICE_IS_STARTED if the device is already started. +* It must be stopped to re-initialize. +* +* @note This function initializes the host controller. +* Initial clock of 400KHz is set. +* Voltage of 3.3V is selected as that is supported by host. +* Interrupts status is enabled and signal disabled by default. +* Default data direction is card to host and +* 32 bit ADMA2 is selected. Default Block size is 512 bytes. +* +******************************************************************************/ +s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, + u32 EffectiveAddr) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + +#if defined (XCLOCKING) + InstancePtr->Config.RefClk = ConfigPtr->RefClk; + Xil_ClockEnable(InstancePtr->Config.RefClk); +#endif + /* If this API is getting called twice, return value accordingly */ + if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY) { + Status = (s32)XST_DEVICE_IS_STARTED; + goto RETURN_PATH ; + } + + /* Set some default values. */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddr; + InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; + InstancePtr->Config.CardDetect = ConfigPtr->CardDetect; + InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect; + InstancePtr->Config.BusWidth = ConfigPtr->BusWidth; + InstancePtr->Config.BankNumber = ConfigPtr->BankNumber; + InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO; + InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent; + InstancePtr->SectorCount = 0U; + InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; + InstancePtr->OTapDelay = 0U; + InstancePtr->ITapDelay = 0U; + InstancePtr->Dma64BitAddr = 0U; + InstancePtr->SlcrBaseAddr = XPS_SYS_CTRL_BASEADDR; + + /* Host Controller version is read. */ + InstancePtr->HC_Version = + (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK); + + /* + * Read capabilities register and update it in Instance pointer. + * It is sufficient to read this once on power on. + */ + InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_CAPS_OFFSET); + + /* Reset the SD bus lines */ + Status = XSdPs_ResetConfig(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + /* Configure the SD Host Controller */ + XSdPs_HostConfig(InstancePtr); + + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + +RETURN_PATH: +#if defined (XCLOCKING) + Xil_ClockDisable(InstancePtr->Config.RefClk); +#endif + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief +* Initialize Card with Identification mode sequence +* +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because +* a) SD is already initialized +* b) There is no card inserted +* c) One of the steps (commands) in the +* initialization cycle failed +* +* +******************************************************************************/ +s32 XSdPs_CardInitialize(XSdPs *InstancePtr) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Default settings */ + InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH; + InstancePtr->CardType = XSDPS_CARD_SD; + InstancePtr->Switch1v8 = 0U; + InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ; + +#if defined (XCLOCKING) + Xil_ClockEnable(InstancePtr->Config.RefClk); +#endif + + /* Change the clock frequency to 400 KHz */ + Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + /* Identify the Card whether it is SD, MMC or eMMC */ + Status = XSdPs_IdentifyCard(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Initialize the identified card */ + if (InstancePtr->CardType == XSDPS_CARD_SD) { + Status = XSdPs_SdCardInitialize(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + Status = XSdPs_MmcCardInitialize(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + +RETURN_PATH: +#if defined (XCLOCKING) + Xil_ClockDisable(InstancePtr->Config.RefClk); +#endif + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function performs SD read in polled mode. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Arg is the address passed by the user that is to be sent as +* argument along with the command. +* @param BlkCnt - Block count passed by the user. +* @param Buff - Pointer to the data buffer for a DMA transfer. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because another transfer +* is in progress or command or data inhibit is set +* +******************************************************************************/ +s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + +#if defined (XCLOCKING) + Xil_ClockEnable(InstancePtr->Config.RefClk); +#endif + + /* Setup the Read Transfer */ + Status = XSdPs_SetupTransfer(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Read from the card */ + Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + +RETURN_PATH: +#if defined (XCLOCKING) + Xil_ClockDisable(InstancePtr->Config.RefClk); +#endif + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function performs SD write in polled mode. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Arg is the address passed by the user that is to be sent as +* argument along with the command. +* @param BlkCnt - Block count passed by the user. +* @param Buff - Pointer to the data buffer for a DMA transfer. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because another transfer +* is in progress or command or data inhibit is set +* +******************************************************************************/ +s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + +#if defined (XCLOCKING) + Xil_ClockEnable(InstancePtr->Config.RefClk); +#endif + + /* Setup the Write Transfer */ + Status = XSdPs_SetupTransfer(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Write to the card */ + Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + +RETURN_PATH: +#if defined (XCLOCKING) + Xil_ClockDisable(InstancePtr->Config.RefClk); +#endif + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief +* API to idle the SDIO Interface +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Idle(XSdPs *InstancePtr) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + +#if defined (XCLOCKING) + Xil_ClockEnable(InstancePtr->Config.RefClk); +#endif + + /* Check if the bus is idle */ + Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK + | XSDPS_PSR_INHIBIT_DAT_MASK + | XSDPS_PSR_DAT_ACTIVE_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + /* Disable the Bus Power */ + XSdPs_DisableBusPower(InstancePtr); + + /* Reset Command and Data Lines */ + Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + Status = XST_SUCCESS; + +RETURN_PATH: +#if defined (XCLOCKING) + Xil_ClockDisable(InstancePtr->Config.RefClk); +#endif + return Status; +} +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h new file mode 100644 index 0000000000..075b751bf0 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h @@ -0,0 +1,295 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps.h +* @addtogroup sdps_v3_9 +* @{ +* @details +* +* This file contains the implementation of XSdPs driver. +* This driver is used initialize read from and write to the SD card. +* Features such as switching bus width to 4-bit and switching to high speed, +* changing clock frequency, block size etc. are supported. +* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however +* is done using 1-bit bus width and 400KHz clock frequency. +* SD commands are classified as broadcast and addressed. Commands can be +* those with response only (using only command line) or +* response + data (using command and data lines). +* Only one command can be sent at a time. During a data transfer however, +* when dsta lines are in use, certain commands (which use only the command +* line) can be sent, most often to obtain status. +* This driver does not support multi card slots at present. +* +* Initialization: +* This includes initialization on the host controller side to select +* clock frequency, bus power and default transfer related parameters. +* The default voltage is 3.3V. +* On the SD card side, the initialization and identification state diagram is +* implemented. This resets the card, gives it a unique address/ID and +* identifies key card related specifications. +* +* Data transfer: +* The SD card is put in transfer state to read from or write to it. +* The default block size is 512 bytes and if supported, +* default bus width is 4-bit and bus speed is High speed. +* The read and write functions are implemented in polled mode using ADMA2. +* +* At any point, when key parameters such as block size or +* clock/speed or bus width are modified, this driver takes care of +* maintaining the same selection on host and card. +* All error bits in host controller are monitored by the driver and in the +* event one of them is set, driver will clear the interrupt status and +* communicate failure to the upper layer. +* +* File system use: +* This driver can be used with xilffs library to read and write files to SD. +* (Please refer to procedure in diskio.c). The file system read/write example +* in polled mode can used for reference. +* +* There is no example for using SD driver without file system at present. +* However, the driver can be used without the file system. The glue layer +* in filesystem can be used as reference for the same. The block count +* passed to the read/write function in one call is limited by the ADMA2 +* descriptor table and hence care will have to be taken to call read/write +* API's in a loop for large file sizes. +* +* Interrupt mode is not supported because it offers no improvement when used +* with file system. +* +* eMMC support: +* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. +* The features of eMMC supported by the driver will depend on those supported +* by the host controller. The current driver supports read/write on eMMC card +* using 4-bit and high speed mode currently. +* +* Features not supported include - card write protect, password setting, +* lock/unlock, interrupts, SDMA mode, programmed I/O mode and +* 64-bit addressed ADMA2, erase/pre-erase commands. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     05/17/17 Add support for 64bit DMA addressing
+* 	mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*       mn     08/17/17 Enabled CCI support for A53 by adding cache coherency
+*                       information.
+*       mn     09/06/17 Resolved compilation errors with IAR toolchain
+* 3.6   mn     08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
+* 3.7   mn     02/01/19 Add support for idling of SDIO
+* 3.8   mn     04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+*       mn     09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
+* 3.9   mn     03/03/20 Restructured the code for more readability and modularity
+*       mn     03/16/20 Move XSdPs_Select_Card API to User APIs
+*
+*
+* +******************************************************************************/ + + +#ifndef SDPS_H_ +#define SDPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xil_printf.h" +#include "xil_cache.h" +#include "xstatus.h" +#include "xsdps_hw.h" +#include "xplatform_info.h" +#include "sleep.h" +#include +#if defined (XCLOCKING) +#include "xil_clocking.h" +#endif + +/************************** Constant Definitions *****************************/ + +#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */ +#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */ +#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */ +#define XSDPS_CMD8_VOL_PATTERN 0x1AAU +#define XSDPS_RESPOCR_READY 0x80000000U +#define XSDPS_ACMD41_HCS 0x40000000U +#define XSDPS_ACMD41_3V3 0x00300000U +#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U +#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U +#define HIGH_SPEED_SUPPORT 0x2U +#define UHS_SDR12_SUPPORT 0x1U +#define UHS_SDR25_SUPPORT 0x2U +#define UHS_SDR50_SUPPORT 0x4U +#define UHS_SDR104_SUPPORT 0x8U +#define UHS_DDR50_SUPPORT 0x10U +#define WIDTH_4_BIT_SUPPORT 0x4U +#define SD_CLK_25_MHZ 25000000U +#define SD_CLK_19_MHZ 19000000U +#define SD_CLK_26_MHZ 26000000U +#define EXT_CSD_DEVICE_TYPE_BYTE 196U +#define EXT_CSD_SEC_COUNT_BYTE1 212U +#define EXT_CSD_SEC_COUNT_BYTE2 213U +#define EXT_CSD_SEC_COUNT_BYTE3 214U +#define EXT_CSD_SEC_COUNT_BYTE4 215U +#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U +#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U +#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U +#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U +#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U +#define CSD_SPEC_VER_3 0x3U +#define SCR_SPEC_VER_3 0x80U +#define ADDRESS_BEYOND_32BIT 0x100000000U + +/**************************** Type Definitions *******************************/ + +typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u32 CardDetect; /**< Card Detect */ + u32 WriteProtect; /**< Write Protect */ + u32 BusWidth; /**< Bus Width */ + u32 BankNumber; /**< MIO Bank selection for SD */ + u32 HasEMIO; /**< If SD is connected to EMIO */ + u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ +#if defined (XCLOCKING) + u32 RefClk; /**< Input clocks */ +#endif +} XSdPs_Config; + +/* ADMA2 32-Bit descriptor table */ +typedef struct { + u16 Attribute; /**< Attributes of descriptor */ + u16 Length; /**< Length of current dma transfer */ + u32 Address; /**< Address of current dma transfer */ +#ifdef __ICCARM__ +#pragma data_alignment = 32 +} XSdPs_Adma2Descriptor32; +#else +} __attribute__((__packed__))XSdPs_Adma2Descriptor32; +#endif + +/* ADMA2 64-Bit descriptor table */ +typedef struct { + u16 Attribute; /**< Attributes of descriptor */ + u16 Length; /**< Length of current dma transfer */ + u64 Address; /**< Address of current dma transfer */ +#ifdef __ICCARM__ +#pragma data_alignment = 32 +} XSdPs_Adma2Descriptor64; +#else +} __attribute__((__packed__))XSdPs_Adma2Descriptor64; +#endif + +/** + * The XSdPs driver instance data. The user is required to allocate a + * variable of this type for every SD device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XSdPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + u32 Host_Caps; /**< Capabilities of host controller */ + u32 Host_CapsExt; /**< Extended Capabilities */ + u32 HCS; /**< High capacity support in card */ + u8 CardType; /**< Type of card - SD/MMC/eMMC */ + u8 Card_Version; /**< Card version */ + u8 HC_Version; /**< Host controller version */ + u8 BusWidth; /**< Current operating bus width */ + u32 BusSpeed; /**< Current operating bus speed */ + u8 Switch1v8; /**< 1.8V Switch support */ + u32 CardID[4]; /**< Card ID Register */ + u32 RelCardAddr; /**< Relative Card Address */ + u32 CardSpecData[4]; /**< Card Specific Data Register */ + u32 SectorCount; /**< Sector Count */ + u32 SdCardConfig; /**< Sd Card Configuration Register */ + u32 Mode; /**< Bus Speed Mode */ + u32 OTapDelay; /**< Output Tap Delay */ + u32 ITapDelay; /**< Input Tap Delay */ + u64 Dma64BitAddr; /**< 64 Bit DMA Address */ + u16 TransferMode; /**< Transfer Mode */ + u32 SlcrBaseAddr; /**< SLCR base address*/ +} XSdPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); +s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, + u32 EffectiveAddr); +s32 XSdPs_CardInitialize(XSdPs *InstancePtr); +s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); +s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); +s32 XSdPs_Idle(XSdPs *InstancePtr); + +s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr); +s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq); +s32 XSdPs_Pullup(XSdPs *InstancePtr); +s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr); +s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg); +s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize); +s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg); +s32 XSdPs_Select_Card(XSdPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* SD_H_ */ +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c new file mode 100644 index 0000000000..9de30bd1e5 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c @@ -0,0 +1,1510 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps_card.c +* @addtogroup sdps_v3_9 +* @{ +* +* Contains the interface functions of the XSdPs driver. +* See xsdps.h for a detailed description of the device and driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 3.9   mn     03/03/20 Restructured the code for more readability and modularity
+*       mn     03/16/20 Move XSdPs_Select_Card API to User APIs
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xsdps_core.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* @brief +* This function performs SD read in polled mode. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Arg is the address passed by the user that is to be sent as +* argument along with the command. +* @param BlkCnt - Block count passed by the user. +* @param Buff - Pointer to the data buffer for a DMA transfer. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because another transfer +* is in progress or command or data inhibit is set +* +******************************************************************************/ +s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) +{ + s32 Status; + u16 BlkSize; + + BlkSize = XSDPS_BLK_SIZE_512_MASK; + + XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, Buff); + + if (BlkCnt == 1U) { + /* Send single block read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + /* Send multiple blocks read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheInvalidateRange((INTPTR)Buff, + (INTPTR)BlkCnt * BlkSize); + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function performs SD write in polled mode. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Arg is the address passed by the user that is to be sent as +* argument along with the command. +* @param BlkCnt - Block count passed by the user. +* @param Buff - Pointer to the data buffer for a DMA transfer. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because another transfer +* is in progress or command or data inhibit is set +* +******************************************************************************/ +s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) +{ + s32 Status; + u16 BlkSize; + + BlkSize = XSDPS_BLK_SIZE_512_MASK; + + XSdPs_SetupWriteDma(InstancePtr, BlkCnt, BlkSize, Buff); + + if (BlkCnt == 1U) { + /* Send single block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + /* Send multiple blocks write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; +} +/*****************************************************************************/ +/** +* +* @brief +* Identify type of card using CMD0 + CMD1 sequence +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +******************************************************************************/ +s32 XSdPs_IdentifyCard(XSdPs *InstancePtr) +{ + s32 Status; + + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) + == XSDPS_CAPS_EMB_SLOT)) { + InstancePtr->CardType = XSDPS_CHIP_EMMC; + Status = XST_SUCCESS; + goto RETURN_PATH; + } + + /* 74 CLK delay after card is powered up, before the first command. */ + usleep(XSDPS_INIT_DELAY); + + /* CMD0 no response expected */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Host High Capacity support & High voltage window */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD1, + XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); + if (Status != XST_SUCCESS) { + InstancePtr->CardType = XSDPS_CARD_SD; + } else { + InstancePtr->CardType = XSDPS_CARD_MMC; + } + + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); + + Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_CMD_LINE_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* SD initialization is done in this function +* +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because +* a) SD is already initialized +* b) There is no card inserted +* c) One of the steps (commands) in the + initialization cycle failed +* +* @note This function initializes the SD card by following its +* initialization and identification state diagram. +* CMD0 is sent to reset card. +* CMD8 and ACDM41 are sent to identify voltage and +* high capacity support +* CMD2 and CMD3 are sent to obtain Card ID and +* Relative card address respectively. +* CMD9 is sent to read the card specific data. +* +******************************************************************************/ +s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) +{ + s32 Status; + +#ifndef UHS_MODE_ENABLE + InstancePtr->Config.BusWidth = XSDPS_WIDTH_4; +#endif + + Status = XSdPs_SdCardEnum(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_SdModeInit(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* @brief +* Mmc initialization is done in this function +* +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because +* a) MMC is already initialized +* b) There is no card inserted +* c) One of the steps (commands) in the initialization +* cycle failed +* @note This function initializes the SD card by following its +* initialization and identification state diagram. +* CMD0 is sent to reset card. +* CMD1 sent to identify voltage and high capacity support +* CMD2 and CMD3 are sent to obtain Card ID and +* Relative card address respectively. +* CMD9 is sent to read the card specific data. +* +******************************************************************************/ +s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr) +{ + s32 Status; + + Status = XSdPs_MmcCardEnum(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if (((InstancePtr->CardType == XSDPS_CARD_MMC) && + (InstancePtr->Card_Version > CSD_SPEC_VER_3)) && + (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) { + Status = XSdPs_MmcModeInit(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC) { + Status = XSdPs_EmmcModeInit(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + Status = XST_FAILURE; + goto RETURN_PATH; + + } + + if (InstancePtr->Mode != XSDPS_DDR52_MODE) { + Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function checks if the card is present or not. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr) +{ + u32 PresentStateReg; + s32 Status; + + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) + == XSDPS_CAPS_EMB_SLOT)) { + Status = XST_SUCCESS; + goto RETURN_PATH; + } + + if(InstancePtr->Config.CardDetect != 0U) { + /* + * Check the present state register to make sure + * card is inserted and detected by host controller + */ + PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function sends CMD0 to reset the card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CardReset(XSdPs *InstancePtr) +{ + s32 Status; + + /* CMD0 no response expected */ + Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function sends command to get the card interface details. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CardIfCond(XSdPs *InstancePtr) +{ + u32 RespOCR; + s32 Status; + + /* + * CMD8; response expected + * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern + */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD8, + XSDPS_CMD8_VOL_PATTERN, 0U); + if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if (Status == XSDPS_CT_ERROR) { + Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_CMD_LINE_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + } + + RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP0_OFFSET); + if (RespOCR != XSDPS_CMD8_VOL_PATTERN) { + InstancePtr->Card_Version = XSDPS_SD_VER_1_0; + } else { + InstancePtr->Card_Version = XSDPS_SD_VER_2_0; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function sends command to get the card operating condition. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CardOpCond(XSdPs *InstancePtr) +{ + u32 RespOCR; + s32 Status; + u32 Arg; + + /* Send ACMD41 while card is still busy with power up */ + do { + if (InstancePtr->CardType == XSDPS_CARD_SD) { + Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { + Arg |= XSDPS_OCR_S18; + } + + /* 0x40300000 - Host High Capacity support & 3.3V window */ + Status = XSdPs_CmdTransfer(InstancePtr, ACMD41, + Arg, 0U); + } else { + /* Send CMD1 while card is still busy with power up */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD1, + XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U); + } + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Response with card capacity */ + RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP0_OFFSET); + } while ((RespOCR & XSDPS_RESPOCR_READY) == 0U); + + /* Update HCS support flag based on card capacity response */ + if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) { + InstancePtr->HCS = 1U; + } + + if ((RespOCR & XSDPS_OCR_S18) != 0U) { + InstancePtr->Switch1v8 = 1U; + Status = XSdPs_Switch_Voltage(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to get the card ID. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_GetCardId(XSdPs *InstancePtr) +{ + s32 Status; + + /* CMD2 for Card ID */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + InstancePtr->CardID[0] = + XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_RESP0_OFFSET); + InstancePtr->CardID[1] = + XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_RESP1_OFFSET); + InstancePtr->CardID[2] = + XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_RESP2_OFFSET); + InstancePtr->CardID[3] = + XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_RESP3_OFFSET); + + if(InstancePtr->CardType == XSDPS_CARD_SD) { + do { + Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* + * Relative card address is stored as the upper 16 bits + * This is to avoid shifting when sending commands + */ + InstancePtr->RelCardAddr = + XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP0_OFFSET) & 0xFFFF0000U; + } while (InstancePtr->RelCardAddr == 0U); + } else { + /* Set relative card address */ + InstancePtr->RelCardAddr = 0x12340000U; + Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to get the CSD register from the card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_GetCsd(XSdPs *InstancePtr) +{ + s32 Status; + u32 CSD[4]; + u32 BlkLen; + u32 DeviceSize; + u32 Mult; + + Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* + * Card specific data is read. + * Currently not used for any operation. + */ + CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP0_OFFSET); + CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP1_OFFSET); + CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP2_OFFSET); + CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP3_OFFSET); + + if (InstancePtr->CardType != XSDPS_CARD_SD) { + InstancePtr->Card_Version = (u8)((u32)(CSD[3] & CSD_SPEC_VER_MASK) >>18U); + Status = XST_SUCCESS; + goto RETURN_PATH; + } + + if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) { + BlkLen = 1U << ((u32)(CSD[2] & READ_BLK_LEN_MASK) >> 8U); + Mult = 1U << ((u32)((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U); + DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U; + DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U; + DeviceSize = (DeviceSize + 1U) * Mult; + DeviceSize = DeviceSize * BlkLen; + InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK); + } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) { + InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) + + 1U) * 1024U; + } else { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to set the card voltage to 1.8V. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr) +{ + s32 Status; + u16 CtrlReg; + u16 ClockReg; + + /* Stop the clock */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, + CtrlReg); + + /* Check for 1.8V signal enable bit is cleared by Host */ + Status = XSdPs_SetVoltage18(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + /* Enable the clock in the controller */ + Status = XSdPs_EnableClock(InstancePtr, ClockReg); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + /* Wait for 1mSec */ + (void)usleep(1000U); + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to do initial Reset Configuration. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_ResetConfig(XSdPs *InstancePtr) +{ + s32 Status; + + XSdPs_DisableBusPower(InstancePtr); + + Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + XSdPs_EnableBusPower(InstancePtr); + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to do initial Host Configuration. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XSdPs_HostConfig(XSdPs *InstancePtr) +{ + XSdPs_ConfigPower(InstancePtr); + + XSdPs_ConfigDma(InstancePtr); + + XSdPs_ConfigInterrupt(InstancePtr); + + /* + * Transfer mode register - default value + * DMA enabled, block count enabled, data direction card to host(read) + */ + InstancePtr->TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK; + + /* Set block size to 512 by default */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK); +} + +/*****************************************************************************/ +/** +* @brief +* This function checks for Reset Done bits to be cleared after a reset assert. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Value is the bits to be checked to be cleared. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value) +{ + u32 Timeout = 1000000U; + u32 ReadReg; + s32 Status; + + /* Proceed with initialization only after reset is complete */ + do { + ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, + XSDPS_SW_RST_OFFSET); + Timeout = Timeout - 1U; + usleep(1); + } while (((ReadReg & Value) != 0U) + && (Timeout != 0U)); + + if (Timeout == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to setup the voltage switch. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr) +{ + u32 Timeout = 10000; + s32 Status; + u32 ReadReg; + + /* Send switch voltage command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Wait for CMD and DATA line to go low */ + do { + ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + Timeout = Timeout - 1; + usleep(1); + } while (((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | + XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) + && (Timeout != 0U)); + + if (Timeout == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to check if the Cmd and Dat buses are high. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr) +{ + u32 Timeout = 10000; + s32 Status; + u32 ReadReg; + + /* Wait for CMD and DATA line to go high */ + Timeout = MAX_TIMEOUT; + do { + ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + Timeout = Timeout - 1; + usleep(1); + } while (((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) + != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) + && (Timeout != 0U)); + + if (Timeout == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief +* API to Identify the supported UHS mode. This API will assign the +* corresponding tap delay API to the Config_TapDelay pointer based on the +* supported bus speed. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param ReadBuff contains the response for CMD6 +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff) +{ + if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) && + (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104; + if (InstancePtr->Config.BankNumber == 2U) { + InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2; + } else { + InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0; + } + } else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) && + (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD50; + } else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) && + (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_DDR50; + InstancePtr->ITapDelay = SD_ITAPDLYSEL_SD_DDR50; + } else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) && + (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD; + InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD; + } else { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12; + } +} + +/*****************************************************************************/ +/** +* +* @brief +* API to set Tap Delay w.r.t speed modes +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_SetTapDelay(XSdPs *InstancePtr) +{ + if ((InstancePtr->Mode == XSDPS_DEFAULT_SPEED_MODE) || + (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR12)) { + return; + } + +#ifndef versal + /* Issue DLL Reset */ + XSdPs_DllRstCtrl(InstancePtr, 1U); +#endif + + /* Configure the Tap Delay Registers */ + XSdPs_ConfigTapDelay(InstancePtr); + +#ifndef versal + /* Release the DLL out of reset */ + XSdPs_DllRstCtrl(InstancePtr, 0U); +#endif +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to change the SD Bus Speed. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr) +{ + s32 Status; + u32 Arg; + u16 BlkCnt; + u16 BlkSize; + u16 CtrlReg; + u8 ReadBuff[64] = {0U}; + + Status = XSdPs_CalcBusSpeed(InstancePtr, &Arg); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; + BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; + + XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff); + + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + if (InstancePtr->Switch1v8 != 0U) { + /* Set UHS mode in controller */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET, + CtrlReg | InstancePtr->Mode); + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to change the eMMC bus speed. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_Change_MmcBusSpeed(XSdPs *InstancePtr) +{ + s32 Status; + u32 Arg; + + Status = XSdPs_CalcBusSpeed(InstancePtr, &Arg); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to do the Auto tuning. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_AutoTuning(XSdPs *InstancePtr) +{ + s32 Status; + u16 BlkSize; + u8 TuningCount; + + BlkSize = XSDPS_TUNING_CMD_BLKSIZE; + if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) + { + BlkSize = BlkSize*2U; + } + BlkSize &= XSDPS_BLK_SIZE_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, + BlkSize); + + InstancePtr->TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK; + + XSdPs_SetExecTuning(InstancePtr); + /* + * workaround which can work for 1.0/2.0 silicon for auto tuning. + * This can be revisited for 3.0 silicon if necessary. + */ + /* Wait for ~60 clock cycles to reset the tap values */ + (void)usleep(1U); + + for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) { + + if (InstancePtr->CardType == XSDPS_CARD_SD) { + Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U); + } else { + Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U); + } + + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) { + break; + } + } + + if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Wait for ~12 clock cycles to synchronize the new tap values */ + (void)usleep(1U); + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief +* API to setup ADMA2 descriptor table +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param BlkCnt - block count. +* @param Buff pointer to data buffer. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) +{ + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { + XSdPs_Setup64ADMA2DescTbl(InstancePtr, BlkCnt, Buff); + } else { + XSdPs_Setup32ADMA2DescTbl(InstancePtr, BlkCnt, Buff); + } +} + +/*****************************************************************************/ +/** +* +* @brief +* API to setup ADMA2 descriptor table for 64 Bit DMA +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param BlkCnt - block count. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt) +{ +#ifdef __ICCARM__ +#pragma data_alignment = 32 + static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32]; +#else + static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32] __attribute__ ((aligned(32))); +#endif + u32 TotalDescLines; + u64 DescNum; + u32 BlkSize; + + /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */ + BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_BLK_SIZE_OFFSET) & + XSDPS_BLK_SIZE_MASK; + + if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) { + + TotalDescLines = 1U; + + } else { + + TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH); + if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) { + TotalDescLines += 1U; + } + + } + + for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) { + Adma2_DescrTbl[DescNum].Address = + InstancePtr->Dma64BitAddr + + (DescNum*XSDPS_DESC_MAX_LENGTH); + Adma2_DescrTbl[DescNum].Attribute = + XSDPS_DESC_TRAN | XSDPS_DESC_VALID; + Adma2_DescrTbl[DescNum].Length = 0U; + } + + Adma2_DescrTbl[TotalDescLines-1].Address = + InstancePtr->Dma64BitAddr + + (DescNum*XSDPS_DESC_MAX_LENGTH); + + Adma2_DescrTbl[TotalDescLines-1].Attribute = + XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; + + Adma2_DescrTbl[TotalDescLines-1].Length = + (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH)); + + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, + (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0)); + + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]), + sizeof(XSdPs_Adma2Descriptor64) * 32U); + } + + /* Clear the 64-Bit Address variable */ + InstancePtr->Dma64BitAddr = 0U; + +} + +/*****************************************************************************/ +/** +* +* @brief +* API to reset the DLL +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_DllReset(XSdPs *InstancePtr) +{ + u32 ClockReg; + s32 Status; + + /* Disable clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, (u16)ClockReg); + + /* Issue DLL Reset to load zero tap values */ + XSdPs_DllRstCtrl(InstancePtr, 1U); + + /* Wait for 2 micro seconds */ + (void)usleep(2U); + + XSdPs_DllRstCtrl(InstancePtr, 0U); + + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + /* Enable the clock in the controller */ + Status = XSdPs_EnableClock(InstancePtr, ClockReg); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to identify the eMMC speed mode. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param ExtCsd is the extended CSD register from the card +* +* @return None +* +******************************************************************************/ +void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd) +{ + if (InstancePtr->BusWidth < XSDPS_4_BIT_WIDTH) { + InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; + } else { + /* Check for card supported speed */ + if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | + EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { + InstancePtr->Mode = XSDPS_HS200_MODE; + if (InstancePtr->Config.BankNumber == 2U) { + InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2; + } else { + InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0; + } + } else if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED | + EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) { + InstancePtr->Mode = XSDPS_DDR52_MODE; + InstancePtr->OTapDelay = SD_ITAPDLYSEL_EMMC_DDR50; + InstancePtr->ITapDelay = SD_ITAPDLYSEL_EMMC_DDR50; + } else if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_EMMC_HSD; + InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD; + } else { + InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; + } + } +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to check the eMMC timing. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param ExtCsd is the extended CSD register from the card +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd) +{ + s32 Status; + + Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) || + (InstancePtr->Mode == XSDPS_DDR52_MODE)) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + Status = XST_FAILURE; + } + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to set the clock to the passed frequency. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param SelFreq is the selected frequency +* +* @return None +* +******************************************************************************/ +s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq) +{ + u16 ClockReg; + s32 Status; + + /* Disable clock */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, 0U); + + /* If selected frequency is zero, return from here */ + if (SelFreq == 0U) { + Status = XST_SUCCESS; + goto RETURN_PATH ; + } + + /* Calculate the clock */ + ClockReg = XSdPs_CalcClock(InstancePtr, SelFreq); + + /* Enable the clock in the controller */ + Status = XSdPs_EnableClock(InstancePtr, ClockReg); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function checks if the voltage is set to 1.8V or not. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if voltage is 1.8V +* - XST_FAILURE if voltage is not 1.8V +* +******************************************************************************/ +s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr) +{ + u32 Status; + + if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_1V8_EN_MASK) == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function initializes the command sequence. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Arg is the address passed by the user that is to be sent as +* argument along with the command. +* @param BlkCnt - Block count passed by the user. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt) +{ + s32 Status; + + /* + * Check the command inhibit to make sure no other + * command transfer is in progress + */ + Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + /* Write block count register */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt); + + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU); + + /* Write argument register */ + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, + XSDPS_ARGMT_OFFSET, Arg); + + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function initiates the Cmd transfer to SD card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cmd is the command to be sent +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd) +{ + u32 PresentStateReg; + u32 CommandReg; + s32 Status; + + /* Command register is set to trigger transfer of command */ + CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd); + + /* + * Mask to avoid writing to reserved bits 31-30 + * This is necessary because 0x8000 is used by this software to + * distinguish between ACMD and CMD of same number + */ + CommandReg = CommandReg & 0x3FFFU; + + /* + * Check for data inhibit in case of command using DAT lines. + * For Tuning Commands DAT lines check can be ignored. + */ + if ((Cmd != CMD21) && (Cmd != CMD19)) { + PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + if (((PresentStateReg & XSDPS_PSR_INHIBIT_DAT_MASK) != 0U) && + ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, + (CommandReg << 16) | InstancePtr->TransferMode); + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; + +} + +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_core.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_core.h new file mode 100644 index 0000000000..aed8b1f9aa --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_core.h @@ -0,0 +1,115 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps_include.h +* @addtogroup sdps_v3_9 +* @{ +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xsdps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 3.9   mn     03/03/20 Restructured the code for more readability and modularity
+*       mn     03/16/20 Move XSdPs_Select_Card API to User APIs
+*
+*
+* +******************************************************************************/ + +#ifndef SDPS_INCLUDE_H_ +#define SDPS_INCLUDE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xsdps.h" +#if defined (__aarch64__) +#include "xil_smc.h" +#endif + +/** @cond INTERNAL */ +s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_IdentifyCard(XSdPs *InstancePtr); +s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); +s32 XSdPs_SetupTransfer(XSdPs *InstancePtr); +s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); +s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); +void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); +s32 XSdPs_DllReset(XSdPs *InstancePtr); +s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr); +void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt); +void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); +void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst); +void XSdPs_ConfigTapDelay(XSdPs *InstancePtr); +s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr); +void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); +void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); +u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd); +void XSdPs_SetTapDelay(XSdPs *InstancePtr); +s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value); +s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr); +s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt); +void XSdPs_SetExecTuning(XSdPs *InstancePtr); +s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr); +s32 XSdPs_CardReset(XSdPs *InstancePtr); +s32 XSdPs_CardIfCond(XSdPs *InstancePtr); +s32 XSdPs_CardOpCond(XSdPs *InstancePtr); +s32 XSdPs_GetCardId(XSdPs *InstancePtr); +s32 XSdPs_GetCsd(XSdPs *InstancePtr); +s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr); +s32 XSdPs_SdModeInit(XSdPs *InstancePtr); +s32 XSdPs_SdCardEnum(XSdPs *InstancePtr); +s32 XSdPs_MmcCardEnum(XSdPs *InstancePtr); +s32 XSdPs_MmcModeInit(XSdPs *InstancePtr); +s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr); +s32 XSdPs_ResetConfig(XSdPs *InstancePtr); +void XSdPs_HostConfig(XSdPs *InstancePtr); +s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value); +void XSdPs_DisableBusPower(XSdPs *InstancePtr); +void XSdPs_EnableBusPower(XSdPs *InstancePtr); +s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value); +s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr); +s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr); +s32 XSdPs_AutoTuning(XSdPs *InstancePtr); +s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq); +u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq); +s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg); +s32 XSdps_CheckTransferDone(XSdPs *InstancePtr); +s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr); +s32 XSdPs_Change_MmcBusSpeed(XSdPs *InstancePtr); +s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg); +void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff); +void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 *Buff); +s32 XSdPs_DoDmaTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); +s32 XSdPs_DoCmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); +s32 XSdPs_SetVoltage18(XSdPs *InstancePtr); +s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd); +void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd); +s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd); +void XSdPs_ConfigPower(XSdPs *InstancePtr); +void XSdPs_ConfigDma(XSdPs *InstancePtr); +void XSdPs_ConfigInterrupt(XSdPs *InstancePtr); + +#if EL1_NONSECURE && defined (__aarch64__) +void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val); +#endif +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c new file mode 100644 index 0000000000..17956382b0 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c @@ -0,0 +1,49 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2020.1 +* DO NOT EDIT. +* +* Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xsdps.h" + +/* +* The configuration table for devices +*/ + +XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] = +{ + { + XPAR_PSU_SD_0_DEVICE_ID, + XPAR_PSU_SD_0_BASEADDR, + XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ, + XPAR_PSU_SD_0_HAS_CD, + XPAR_PSU_SD_0_HAS_WP, + XPAR_PSU_SD_0_BUS_WIDTH, + XPAR_PSU_SD_0_MIO_BANK, + XPAR_PSU_SD_0_HAS_EMIO, + XPAR_PSU_SD_0_IS_CACHE_COHERENT + }, + { + XPAR_PSU_SD_1_DEVICE_ID, + XPAR_PSU_SD_1_BASEADDR, + XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ, + XPAR_PSU_SD_1_HAS_CD, + XPAR_PSU_SD_1_HAS_WP, + XPAR_PSU_SD_1_BUS_WIDTH, + XPAR_PSU_SD_1_MIO_BANK, + XPAR_PSU_SD_1_HAS_EMIO, + XPAR_PSU_SD_1_IS_CACHE_COHERENT + } +}; + + diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c new file mode 100644 index 0000000000..25b5bc54cc --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c @@ -0,0 +1,1801 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps_host.c +* @addtogroup sdps_v3_9 +* @{ +* +* Contains the interface functions of the XSdPs driver. +* See xsdps.h for a detailed description of the device and driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 3.9   mn     03/03/20 Restructured the code for more readability and modularity
+*       mn     03/16/20 Add code to get card ID for MMC/eMMC
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xsdps_core.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +#if EL1_NONSECURE && defined (__aarch64__) +void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val) +{ + (void)Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(InstancePtr->SlcrBaseAddr + + RegOffset) | ((u64)Mask << 32), + (u64)Val, 0, 0, 0, 0, 0); +} +#endif + +/*****************************************************************************/ +/** +* +* @brief +* Switches the SD card voltage from 3v3 to 1v8 +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +******************************************************************************/ +s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) +{ + s32 Status; + + /* Setup the voltage switching sequence */ + Status = XSdPs_SetupVoltageSwitch(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Set the card voltage to 1.8V */ + Status = XSdPs_CardSetVoltage18(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Check if the bus is high */ + Status = XSdPs_CheckBusHigh(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function initiates the transfer to or from SD card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_SetupTransfer(XSdPs *InstancePtr) +{ + u32 PresentStateReg; + s32 Status; + + if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || + ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) + != XSDPS_CAPS_EMB_SLOT)) { + if(InstancePtr->Config.CardDetect != 0U) { + /* Check status to ensure card is initialized */ + PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + } + + /* Set block size to 512 if not already set */ + if(XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) { + Status = XSdPs_SetBlkSize(InstancePtr, + XSDPS_BLK_SIZE_512_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* @brief +* This function resets the SD card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Value is the type of reset +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value) +{ + s32 Status; + + /* "Software reset for all" is initiated */ + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET, + Value); + + Status = XSdPs_CheckResetDone(InstancePtr, Value); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function sets bit to start execution of tuning. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XSdPs_SetExecTuning(XSdPs *InstancePtr) +{ + u16 CtrlReg; + + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET, CtrlReg); +} + +/*****************************************************************************/ +/** +* @brief +* This function does SD mode initialization. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if initialization is successful +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_SdModeInit(XSdPs *InstancePtr) +{ + s32 Status; +#ifdef __ICCARM__ +#pragma data_alignment = 32 + static u8 SCR[8] = { 0U }; +#else + static u8 SCR[8] __attribute__ ((aligned(32))) = { 0U }; +#endif + u8 ReadBuff[64] = { 0U }; + + Status = XSdPs_Get_BusWidth(InstancePtr, SCR); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) { + InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH; + Status = XSdPs_Change_BusWidth(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + /* Get speed supported by device */ + Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff); + if (Status != XST_SUCCESS) { + goto RETURN_PATH; + } + + if (((SCR[2] & SCR_SPEC_VER_3) != 0U) && + (ReadBuff[13] >= UHS_SDR50_SUPPORT) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) && + (InstancePtr->Switch1v8 == 0U)) { + + InstancePtr->Switch1v8 = 1U; + + Status = XSdPs_CardSetVoltage18(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + if (InstancePtr->Switch1v8 != 0U) { + + /* Identify the UHS mode supported by card */ + XSdPs_Identify_UhsMode(InstancePtr, ReadBuff); + + Status = XSdPs_Change_BusSpeed(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + /* + * card supports CMD6 when SD_SPEC field in SCR register + * indicates that the Physical Layer Specification Version + * is 1.10 or later. So for SD v1.0 cmd6 is not supported. + */ + if (SCR[0] != 0U) { + /* Check for high speed support */ + if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; + InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD; + InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD; + Status = XSdPs_Change_BusSpeed(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + } + } + + Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function does MMC mode initialization. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if initialization is successful +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_MmcModeInit(XSdPs *InstancePtr) +{ + s32 Status; +#ifdef __ICCARM__ +#pragma data_alignment = 32 + static u8 ExtCsd[512]; +#else + static u8 ExtCsd[512] __attribute__ ((aligned(32))); +#endif + + InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH; + Status = XSdPs_Change_BusWidth(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; + + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; + Status = XSdPs_Change_BusSpeed(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function does eMMC mode initialization. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if initialization is successful +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr) +{ + s32 Status; + +#ifdef __ICCARM__ +#pragma data_alignment = 32 + static u8 ExtCsd[512]; +#else + static u8 ExtCsd[512] __attribute__ ((aligned(32))); +#endif + + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { + /* in case of eMMC data width 8-bit */ + InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH; + } else if (InstancePtr->Config.BusWidth == XSDPS_WIDTH_4) { + /* in case of eMMC data width 4-bit */ + InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH; + } else { + /* in case of eMMC data width 1-bit */ + InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH; + } + + Status = XSdPs_Change_BusWidth(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Get Extended CSD */ + Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; + + XSdPs_IdentifyEmmcMode(InstancePtr, ExtCsd); + + if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) { + Status = XSdPs_Change_BusSpeed(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_CheckEmmcTiming(InstancePtr, ExtCsd); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + /* Enable Rst_n_Fun bit if it is disabled */ + if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) { + Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, XSDPS_MMC_RST_FUN_EN_ARG); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function disables the bus power. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XSdPs_DisableBusPower(XSdPs *InstancePtr) +{ + /* Disable SD bus power and issue eMMC HW reset */ + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK); + } else { + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, 0x0); + } + + /* 1ms delay to poweroff card */ + (void)usleep(1000U); +} + +/*****************************************************************************/ +/** +* @brief +* This function enables the bus power. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XSdPs_EnableBusPower(XSdPs *InstancePtr) +{ + /* Select voltage and enable bus power. */ + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, + (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) & + ~XSDPS_PC_EMMC_HW_RST_MASK); + } else { + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, + XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK); + } + + /* 0.2ms Delay after bus power on*/ + usleep(200); +} + +/*****************************************************************************/ +/** +* @brief +* This function enumerates the SD card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_SdCardEnum(XSdPs *InstancePtr) +{ + s32 Status; + + /* Check if the card is present */ + Status = XSdPs_CheckCardDetect(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Reset the SD card */ + Status = XSdPs_CardReset(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Get the card interface condition */ + Status = XSdPs_CardIfCond(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Get the card operating condition */ + Status = XSdPs_CardOpCond(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Get the card ID */ + Status = XSdPs_GetCardId(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Get the CSD register */ + Status = XSdPs_GetCsd(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Change clock to default clock 25MHz */ + /* + * SD default speed mode timing should be closed at 19 MHz. + * The reason for this is SD requires a voltage level shifter. + * This limitation applies to ZynqMPSoC. + */ + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { + InstancePtr->BusSpeed = SD_CLK_19_MHZ; + } else { + InstancePtr->BusSpeed = SD_CLK_25_MHZ; + } + Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Select the card to transition to transfer state */ + Status = XSdPs_Select_Card(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Pull-up disconnected during data transfer */ + Status = XSdPs_Pullup(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function enumerates the MMC card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_MmcCardEnum(XSdPs *InstancePtr) +{ + s32 Status; + + /* Check if the card is preset */ + Status = XSdPs_CheckCardDetect(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Reset the card */ + Status = XSdPs_CardReset(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Get the card operating condition */ + Status = XSdPs_CardOpCond(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Get the card ID */ + Status = XSdPs_GetCardId(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Get the CSD register */ + Status = XSdPs_GetCsd(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Change clock to default clock 26MHz */ + InstancePtr->BusSpeed = SD_CLK_26_MHZ; + Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Send select card command to transition to transfer state */ + Status = XSdPs_Select_Card(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function performs SD tuning. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) +{ + s32 Status; + +#ifndef versal + /* Issue DLL Reset to load new SDHC tuned tap values */ + Status = XSdPs_DllReset(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + +#endif + + /* Perform the auto tuning */ + Status = XSdPs_AutoTuning(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + +#ifndef versal + /* Issue DLL Reset to load new SDHC tuned tap values */ + Status = XSdPs_DllReset(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + +#endif + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to enable the clock. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param ClockReg is the clock value to be set. +* +* @return +* - XST_SUCCESS if success +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg) +{ + u32 Timeout = 150000U; + s32 Status; + u16 ReadReg; + + ClockReg |= (u16)XSDPS_CC_INT_CLK_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, ClockReg); + + /* Wait for 150ms for internal clock to stabilize */ + do { + ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + Timeout = Timeout - 1U; + usleep(1); + } while (((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) + && (Timeout != 0U)); + + if (Timeout == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + /* Enable SD clock */ + ClockReg |= XSDPS_CC_SD_CLK_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, ClockReg); + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to calculate the bus speed. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Arg is the argument to be sent along with the command. +* This could be address or any other information +* +* @return +* - XST_SUCCESS if success +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg) +{ + s32 Status = XST_SUCCESS; + + if (InstancePtr->CardType == XSDPS_CARD_SD) { + switch (InstancePtr->Mode) { + case XSDPS_UHS_SPEED_MODE_SDR12: + *Arg = XSDPS_SWITCH_CMD_SDR12_SET; + InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK; + break; + case XSDPS_UHS_SPEED_MODE_SDR25: + *Arg = XSDPS_SWITCH_CMD_SDR25_SET; + InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK; + break; + case XSDPS_UHS_SPEED_MODE_SDR50: + *Arg = XSDPS_SWITCH_CMD_SDR50_SET; + InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK; + break; + case XSDPS_UHS_SPEED_MODE_SDR104: + *Arg = XSDPS_SWITCH_CMD_SDR104_SET; + InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK; + break; + case XSDPS_UHS_SPEED_MODE_DDR50: + *Arg = XSDPS_SWITCH_CMD_DDR50_SET; + InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK; + break; + case XSDPS_HIGH_SPEED_MODE: + *Arg = XSDPS_SWITCH_CMD_HS_SET; + InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ; + break; + default: + Status = XST_FAILURE; + break; + } + } else { + switch (InstancePtr->Mode) { + case XSDPS_HS200_MODE: + *Arg = XSDPS_MMC_HS200_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; + break; + case XSDPS_DDR52_MODE: + *Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK; + break; + case XSDPS_HIGH_SPEED_MODE: + *Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK; + break; + default: + Status = XST_FAILURE; + break; + } + } + + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to do the DMA transfer to or from SD card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param BlkCnt - Block count passed by the user. +* @param BlkSize - Block size passed by the user. +* @param Buff - Pointer to the data buffer for a DMA transfer. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because another transfer +* is in progress or command or data inhibit is set +* +******************************************************************************/ +void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff) +{ + BlkSize &= XSDPS_BLK_SIZE_MASK; + + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_BLK_SIZE_OFFSET, BlkSize); + + if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) { + XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt); + } else { + XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheInvalidateRange((INTPTR)Buff, + (INTPTR)BlkCnt * BlkSize); + } + } + + if (BlkCnt == 1U) { + InstancePtr->TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; + } else { + InstancePtr->TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | + XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | + XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK; + } +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to do the DMA transfer to or from SD card. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param BlkCnt - Block count passed by the user. +* @param BlkSize - Block size passed by the user. +* @param Buff - Pointer to the data buffer for a DMA transfer. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because another transfer +* is in progress or command or data inhibit is set +* +******************************************************************************/ +void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 *Buff) +{ + BlkSize &= XSDPS_BLK_SIZE_MASK; + + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_BLK_SIZE_OFFSET, BlkSize); + + if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) { + XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt); + } else { + XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheFlushRange((INTPTR)Buff, + (INTPTR)BlkCnt * BlkSize); + } + } + + if (BlkCnt == 1U) { + InstancePtr->TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DMA_EN_MASK; + } else { + InstancePtr->TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | + XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK; + } +} + +/*****************************************************************************/ +/** +* +* @brief +* API to setup ADMA2 descriptor table for 32-bit DMA +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param BlkCnt - block count. +* @param Buff pointer to data buffer. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) +{ +#ifdef __ICCARM__ +#pragma data_alignment = 32 + static XSdPs_Adma2Descriptor32 Adma2_DescrTbl[32]; +#else + static XSdPs_Adma2Descriptor32 Adma2_DescrTbl[32] __attribute__ ((aligned(32))); +#endif + u32 TotalDescLines; + u64 DescNum; + u32 BlkSize; + + /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */ + BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_BLK_SIZE_OFFSET) & + XSDPS_BLK_SIZE_MASK; + + if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) { + TotalDescLines = 1U; + } else { + TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH); + if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) { + TotalDescLines += 1U; + } + } + + for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) { + Adma2_DescrTbl[DescNum].Address = + (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); + Adma2_DescrTbl[DescNum].Attribute = + XSDPS_DESC_TRAN | XSDPS_DESC_VALID; + Adma2_DescrTbl[DescNum].Length = 0U; + } + + Adma2_DescrTbl[TotalDescLines-1].Address = + (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); + + Adma2_DescrTbl[TotalDescLines-1].Attribute = + XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; + + Adma2_DescrTbl[TotalDescLines-1].Length = + (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH)); + + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, + (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0)); + + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]), + sizeof(XSdPs_Adma2Descriptor32) * 32U); + } +} + +/*****************************************************************************/ +/** +* +* @brief +* API to setup ADMA2 descriptor table for 64-bit DMA +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param BlkCnt - block count. +* @param Buff pointer to data buffer. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) +{ +#ifdef __ICCARM__ +#pragma data_alignment = 32 + static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32]; +#else + static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32] __attribute__ ((aligned(32))); +#endif + u32 TotalDescLines; + u64 DescNum; + u32 BlkSize; + + /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */ + BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_BLK_SIZE_OFFSET) & + XSDPS_BLK_SIZE_MASK; + + if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) { + TotalDescLines = 1U; + } else { + TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH); + if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) { + TotalDescLines += 1U; + } + } + + for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) { + Adma2_DescrTbl[DescNum].Address = + ((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); + Adma2_DescrTbl[DescNum].Attribute = + XSDPS_DESC_TRAN | XSDPS_DESC_VALID; + Adma2_DescrTbl[DescNum].Length = 0U; + } + + Adma2_DescrTbl[TotalDescLines-1].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); + + Adma2_DescrTbl[TotalDescLines-1].Attribute = + XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; + + Adma2_DescrTbl[TotalDescLines-1].Length = + (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH)); + +#if defined(__aarch64__) || defined(__arch64__) + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET, + (u32)((UINTPTR)(Adma2_DescrTbl)>>32U)); +#endif + + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, + (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0)); + + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]), + sizeof(XSdPs_Adma2Descriptor64) * 32U); + } +} + +/*****************************************************************************/ +/** +* @brief +* This function is used calculate the clock divisor value. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param SelFreq is the selected frequency +* +* @return Clock divisor value +* +******************************************************************************/ +u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq) +{ + u16 ClockVal = 0U; + u16 DivCnt; + u16 Divisor = 0U; + + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { + /* Calculate divisor */ + for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT; DivCnt++) { + if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) { + Divisor = DivCnt >> 1; + break; + } + } + } else { + /* Calculate divisor */ + for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_MAX_DIV_CNT; DivCnt <<= 1U) { + if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) { + Divisor = DivCnt / 2U; + break; + } + } + } + + ClockVal |= (Divisor & XSDPS_CC_SDCLK_FREQ_SEL_MASK) << XSDPS_CC_DIV_SHIFT; + ClockVal |= ((Divisor >> 8U) & XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK) << XSDPS_CC_EXT_DIV_SHIFT; + + return ClockVal; +} + +/*****************************************************************************/ +/** +* +* @brief +* API to Set or Reset the DLL +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param EnRst is a flag indicating whether to Assert or De-assert Reset. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst) +{ + u32 DeviceId; + u32 DllCtrl; + + DeviceId = InstancePtr->Config.DeviceId; +#ifdef versal +#ifdef XPAR_PSV_PMC_SD_0_DEVICE_ID + if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + + XSdps_Smc(InstancePtr, SD0_DLL_CTRL, SD_DLL_RST, (EnRst == 1U) ? SD0_DLL_RST : 0U); +#else /* EL1_NONSECURE && defined (__aarch64__) */ + DllCtrl = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD0_DLL_CTRL); + if (EnRst == 1U) { + DllCtrl |= SD_DLL_RST; + } else { + DllCtrl &= ~SD_DLL_RST; + } + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD0_DLL_CTRL, DllCtrl); +#endif /* EL1_NONSECURE && defined (__aarch64__) */ + } else { +#endif /* XPAR_PSV_PMC_SD_0_DEVICE_ID */ + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + + XSdps_Smc(InstancePtr, SD1_DLL_CTRL, SD_DLL_RST, (EnRst == 1U) ? SD_DLL_RST : 0U); +#else + DllCtrl = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD1_DLL_CTRL); + if (EnRst == 1U) { + DllCtrl |= SD_DLL_RST; + } else { + DllCtrl &= ~SD_DLL_RST; + } + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD1_DLL_CTRL, DllCtrl); +#endif +#ifdef XPAR_PSV_PMC_SD_0_DEVICE_ID + } +#endif /* XPAR_PSV_PMC_SD_0_DEVICE_ID */ +#else /* versal */ + +#ifdef XPAR_PSU_SD_0_DEVICE_ID + if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + + XSdps_Smc(InstancePtr, SD_DLL_CTRL, SD0_DLL_RST, (EnRst == 1U) ? SD0_DLL_RST : 0U); +#else + DllCtrl = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL); + if (EnRst == 1U) { + DllCtrl |= SD0_DLL_RST; + } else { + DllCtrl &= ~SD0_DLL_RST; + } + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL, DllCtrl); +#endif + } else { +#endif /* XPAR_PSU_SD_0_DEVICE_ID */ + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + + XSdps_Smc(InstancePtr, SD_DLL_CTRL, SD1_DLL_RST, (EnRst == 1U) ? SD1_DLL_RST : 0U); +#else + DllCtrl = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL); + if (EnRst == 1U) { + DllCtrl |= SD1_DLL_RST; + } else { + DllCtrl &= ~SD1_DLL_RST; + } + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL, DllCtrl); +#endif +#ifdef XPAR_PSU_SD_0_DEVICE_ID + } +#endif +#endif +} + +/*****************************************************************************/ +/** +* +* @brief +* Function to configure the Tap Delays. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_ConfigTapDelay(XSdPs *InstancePtr) +{ + u32 DeviceId; + u32 TapDelay; + u32 ITapDelay; + u32 OTapDelay; + + DeviceId = InstancePtr->Config.DeviceId ; + TapDelay = 0U; + ITapDelay = InstancePtr->ITapDelay; + OTapDelay = InstancePtr->OTapDelay; + +#ifdef versal + (void) DeviceId; + if (ITapDelay) { + TapDelay = SD_ITAPCHGWIN; + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay); + /* Program the ITAPDLY */ + TapDelay |= SD_ITAPDLYENA; + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay); + TapDelay |= ITapDelay; + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay); + TapDelay &= ~SD_ITAPCHGWIN; + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay); + } + if (OTapDelay) { + /* Program the OTAPDLY */ + TapDelay = SD_OTAPDLYENA; + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_OTAPDLY, TapDelay); + TapDelay |= OTapDelay; + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_OTAPDLY, TapDelay); + } +#else +#ifdef XPAR_PSU_SD_0_DEVICE_ID + if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (ITapDelay) { + XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPCHGWIN, SD0_ITAPCHGWIN); + XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPDLYENA, SD0_ITAPDLYENA); + XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPDLY_SEL_MASK, ITapDelay); + XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPCHGWIN, 0U); + } + if (OTapDelay) { + XSdps_Smc(InstancePtr, SD_OTAPDLY, SD0_OTAPDLY_SEL_MASK, OTapDelay); + } +#else + if (ITapDelay) { + TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY); + TapDelay |= SD0_ITAPCHGWIN; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); + /* Program the ITAPDLY */ + TapDelay |= SD0_ITAPDLYENA; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); + TapDelay |= ITapDelay; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); + TapDelay &= ~SD0_ITAPCHGWIN; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); + } + if (OTapDelay) { + /* Program the OTAPDLY */ + TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; + TapDelay |= OTapDelay; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay); + } +#endif + } else { +#endif + (void) DeviceId; + ITapDelay = ITapDelay << 16U; + OTapDelay = OTapDelay << 16U; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (ITapDelay) { + XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPCHGWIN, SD1_ITAPCHGWIN); + XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPDLYENA, SD1_ITAPDLYENA); + XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPDLY_SEL_MASK, ITapDelay); + XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPCHGWIN, 0U); + } + if (OTapDelay) { + XSdps_Smc(InstancePtr, SD_OTAPDLY, SD1_OTAPDLY_SEL_MASK, OTapDelay); + } +#else + if (ITapDelay) { + TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY); + TapDelay |= SD1_ITAPCHGWIN; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); + /* Program the ITAPDLY */ + TapDelay |= SD1_ITAPDLYENA; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); + TapDelay |= ITapDelay; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); + TapDelay &= ~SD1_ITAPCHGWIN; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay); + } + if (OTapDelay) { + /* Program the OTAPDLY */ + TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; + TapDelay |= OTapDelay; + XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay); + } +#endif +#ifdef XPAR_PSU_SD_0_DEVICE_ID + } +#endif +#endif /* versal */ +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to set voltage to 1.8V. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return +* - XST_SUCCESS if successful +* - XST_FAILURE if failure +* +******************************************************************************/ +s32 XSdPs_SetVoltage18(XSdPs *InstancePtr) +{ + s32 Status; + u16 CtrlReg; + + /* Enabling 1.8V in controller */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + CtrlReg |= XSDPS_HC2_1V8_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, + CtrlReg); + + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + Status = XSdPs_CheckVoltage18(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used configure the Power Level. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XSdPs_ConfigPower(XSdPs *InstancePtr) +{ + u8 PowerLevel; + + if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) { + PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK; + } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) { + PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK; + } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) { + PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK; + } else { + PowerLevel = 0U; + } + + /* Select voltage based on capability and enable bus power. */ + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, + PowerLevel | XSDPS_PC_BUS_PWR_MASK); +} + +/*****************************************************************************/ +/** +* @brief +* This function is used configure the DMA. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XSdPs_ConfigDma(XSdPs *InstancePtr) +{ + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { + /* Enable ADMA2 in 64bit mode. */ + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET, + XSDPS_HC_DMA_ADMA2_64_MASK); + } else { + /* Enable ADMA2 in 32bit mode. */ + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET, + XSDPS_HC_DMA_ADMA2_32_MASK); + } +} + +/*****************************************************************************/ +/** +* @brief +* This function is used configure the Interrupts. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +void XSdPs_ConfigInterrupt(XSdPs *InstancePtr) +{ + /* Enable all interrupt status except card interrupt initially */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_EN_OFFSET, + XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK)); + + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_EN_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); + + /* Disable all interrupt signals by default. */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U); + +} + +/*****************************************************************************/ +/** +* This function does SD command generation. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cmd is the command to be sent. +* @param Arg is the argument to be sent along with the command. +* This could be address or any other information +* @param BlkCnt - Block count passed by the user. +* +* @return +* - XST_SUCCESS if initialization was successful +* - XST_FAILURE if failure - could be because another transfer +* is in progress or command or data inhibit is set +* +******************************************************************************/ +s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) +{ + u32 Timeout = 10000000U; + u32 StatusReg; + s32 Status; + + Status = XSdPs_SetupCmd(InstancePtr, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_SendCmd(InstancePtr, Cmd); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Polling for response for now */ + do { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET); + if ((Cmd == CMD21) || (Cmd == CMD19)) { + if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK); + break; + } + } + + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { + Status = (s32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_OFFSET); + if (((u32)Status & ~XSDPS_INTR_ERR_CT_MASK) == 0U) { + Status = XSDPS_CT_ERROR; + } + /* Write to clear error bits */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); + goto RETURN_PATH; + } + Timeout = Timeout - 1U; + } while (((StatusReg & XSDPS_INTR_CC_MASK) == 0U) + && (Timeout != 0U)); + /* Write to clear bit */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, + XSDPS_INTR_CC_MASK); + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* This function is used to check if the transfer is completed successfully. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return None +* +******************************************************************************/ +s32 XSdps_CheckTransferDone(XSdPs *InstancePtr) +{ + u32 Timeout = 5000000U; + u16 StatusReg; + s32 Status; + + /* + * Check for transfer complete + * Polling for response for now + */ + do { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET); + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { + /* Write to clear error bits */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); + Status = XST_FAILURE; + goto RETURN_PATH; + } + Timeout = Timeout - 1U; + usleep(1); + } while (((StatusReg & XSDPS_INTR_TC_MASK) == 0U) + && (Timeout != 0U)); + + if (Timeout == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + /* Write to clear bit */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function is used to check if the CMD/DATA bus is idle or not. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Value is to selct Cmd bus or Dat bus +* +* @return None +* +******************************************************************************/ +s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value) +{ + u32 Timeout = 10000000U; + u32 PresentStateReg; + u32 StatusReg; + s32 Status; + + PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + /* Check for Card Present */ + if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) != 0U) { + /* Check for SD idle */ + do { + StatusReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_PRES_STATE_OFFSET); + Timeout = Timeout - 1; + usleep(1); + } while (((StatusReg & Value) != 0U) + && (Timeout != 0U)); + } + + if (Timeout == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + Status = XST_SUCCESS; + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* This function frames the Command register for a particular command. +* Note that this generates only the command register value i.e. +* the upper 16 bits of the transfer mode and command register. +* This value is already shifted to be upper 16 bits and can be directly +* OR'ed with transfer mode register value. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cmd is the Command to be sent. +* +* @return Command register value complete with response type and +* data, CRC and index related flags. +* +******************************************************************************/ +u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd) +{ + u32 RetVal; + + RetVal = Cmd; +#if 0 + switch(Cmd) { + case CMD0: + RetVal |= RESP_NONE; + break; + case CMD1: + RetVal |= RESP_R3; + break; + case CMD2: + RetVal |= RESP_R2; + break; + case CMD3: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= RESP_R6; + } else { + RetVal |= RESP_R1; + } + break; + case CMD4: + RetVal |= RESP_NONE; + break; + case CMD5: + RetVal |= RESP_R1B; + break; + case CMD6: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + } else { + RetVal |= RESP_R1B; + } + break; + case ACMD6: + RetVal |= RESP_R1; + break; + case CMD7: + RetVal |= RESP_R1; + break; + case CMD8: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= RESP_R1; + } else { + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + } + break; + case CMD9: + RetVal |= RESP_R2; + break; + case CMD11: + case CMD10: + case CMD12: + RetVal |= RESP_R1; + break; + case ACMD13: + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + break; + case CMD16: + RetVal |= RESP_R1; + break; + case CMD17: + case CMD18: + case CMD19: + case CMD21: + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + break; + case CMD23: + case ACMD23: + case CMD24: + case CMD25: + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + break; + case ACMD41: + RetVal |= RESP_R3; + break; + case ACMD42: + RetVal |= RESP_R1; + break; + case ACMD51: + RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + break; + case CMD52: + case CMD55: + RetVal |= RESP_R1; + break; + case CMD58: + break; + default : + RetVal |= Cmd; + break; + } +#else + switch(Cmd) { + case CMD0: + RetVal |= XSDPS_RESP_NONE; + break; + case CMD1: + RetVal |= XSDPS_RESP_R3; + break; + case CMD2: + RetVal |= XSDPS_RESP_R2; + break; + case CMD3: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= XSDPS_RESP_R6; + } else { + RetVal |= XSDPS_RESP_R1; + } + break; + case CMD4: + RetVal |= XSDPS_RESP_NONE; + break; + case CMD5: + RetVal |= XSDPS_RESP_R1B; + break; + case CMD6: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= XSDPS_RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + } else { + RetVal |= XSDPS_RESP_R1B; + } + break; + case ACMD6: + RetVal |= XSDPS_RESP_R1; + break; + case CMD7: + RetVal |= XSDPS_RESP_R1; + break; + case CMD8: + if (InstancePtr->CardType == XSDPS_CARD_SD) { + RetVal |= XSDPS_RESP_R1; + } else { + RetVal |= XSDPS_RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + } + break; + case CMD9: + RetVal |= XSDPS_RESP_R2; + break; + case CMD11: + case CMD10: + case CMD12: + RetVal |= XSDPS_RESP_R1; + break; + case ACMD13: + RetVal |= XSDPS_RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + break; + case CMD16: + RetVal |= XSDPS_RESP_R1; + break; + case CMD17: + case CMD18: + case CMD19: + case CMD21: + RetVal |= XSDPS_RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + break; + case CMD23: + case ACMD23: + case CMD24: + case CMD25: + RetVal |= XSDPS_RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + break; + case ACMD41: + RetVal |= XSDPS_RESP_R3; + break; + case ACMD42: + RetVal |= XSDPS_RESP_R1; + break; + case ACMD51: + RetVal |= XSDPS_RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK; + break; + case CMD52: + case CMD55: + RetVal |= XSDPS_RESP_R1; + break; + case CMD58: + break; + default : + RetVal |= Cmd; + break; + } +#endif + return RetVal; +} + +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h new file mode 100644 index 0000000000..7ddb221c77 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h @@ -0,0 +1,1323 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps_hw.h +* @addtogroup sdps_v3_9 +* @{ +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xsdps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     08/22/17 Updated for Word Access System support
+*       mn     09/06/17 Added support for ARMCC toolchain
+* 3.4   mn     01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6   mn     07/06/18 Fix Doxygen warnings for sdps driver
+* 3.8   mn     04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+*       mn     05/21/19 Set correct tap delays for Versal
+*       mn     05/21/19 Disable DLL Reset code for Versal
+*       mn     07/03/19 Update Input Tap Delays for Versal
+* 3.9   mn     03/03/20 Restructured the code for more readability and modularity
+*
+*
+* +******************************************************************************/ + +#ifndef SD_HW_H_ +#define SD_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an SD device. + * @{ + */ + +#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address + Register */ +#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET + /**< SDMA System Address + Low Register */ +#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */ +#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address + High Register */ +#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */ + +#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */ +#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */ +#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */ +#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET + /**< Argument1 Register */ +#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */ + +#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */ +#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */ +#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */ +#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */ +#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */ +#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */ +#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */ +#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */ +#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */ +#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */ +#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */ +#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */ +#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */ +#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */ +#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */ +#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt + Status Register */ +#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt + Status Register */ +#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt + Status Enable Register */ +#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt + Status Enable Register */ +#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt + Signal Enable Register */ +#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt + Signal Enable Register */ + +#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status + Register */ +#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */ +#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */ +#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */ +#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current + Capabilities Register */ +#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current + Capabilities Ext Register */ +#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for + Error Interrupt Status */ +#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt + Status Register */ +#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status + Register */ +#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address + Register */ +#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address + Extended Register */ +#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */ +#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control + register */ + +#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control + Register */ +#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status + Register */ +#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version + Register */ + +/* @} */ + +/** @name Control Register - Host control, Power control, + * Block Gap control and Wakeup control + * + * This register contains bits for various configuration options of + * the SD host controller. Read/Write apart from the reserved bits. + * @{ + */ + +#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */ +#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */ +#define XSDPS_HC_BUS_WIDTH_4 0x00000002U +#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */ +#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */ +#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */ +#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */ +#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */ +#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */ +#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */ +#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */ +#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */ + +#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */ +#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */ +#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */ +#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */ +#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */ +#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */ + +#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */ +#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */ +#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */ +#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */ +#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */ +#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */ +#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */ +#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */ + +#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */ +#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */ +#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */ + +/* @} */ + +/** @name Control Register - Clock control, Timeout control & Software reset + * + * This register contains bits for configuration options of clock, timeout and + * software reset. + * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits. + * @{ + */ + +#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U +#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U +#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U +#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U +#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x00000003U +#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU +#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U +#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U +#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U +#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U +#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U +#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U +#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U +#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U +#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U +#define XSDPS_CC_MAX_DIV_CNT 256U +#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U +#define XSDPS_CC_EXT_DIV_SHIFT 6U + +#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU + +#define XSDPS_SWRST_ALL_MASK 0x00000001U +#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U +#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U + +#define XSDPS_CC_MAX_NUM_OF_DIV 9U +#define XSDPS_CC_DIV_SHIFT 8U + +/* @} */ + +/** @name SD Interrupt Registers + * + * Normal and Error Interrupt Status Register + * This register shows the normal and error interrupt status. + * Status enable register affects reads of this register. + * If Signal enable register is set and the corresponding status bit is set, + * interrupt is generated. + * Write to clear except + * Error_interrupt and Card_Interrupt bits - Read only + * + * Normal and Error Interrupt Status Enable Register + * Setting this register bits enables Interrupt status. + * Read/Write except Fixed_to_0 bit (Read only) + * + * Normal and Error Interrupt Signal Enable Register + * This register is used to select which interrupt status is + * indicated to the Host System as the interrupt. + * Read/Write except Fixed_to_0 bit (Read only) + * + * All three registers have same bit definitions + * @{ + */ + +#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */ +#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */ +#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */ +#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */ +#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */ +#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */ +#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */ +#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */ +#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */ +#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */ +#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */ +#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */ +#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */ +#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv + Interrupt */ +#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate + Interrupt */ +#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */ +#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU + +#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout + Error */ +#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */ +#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit + Error */ +#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */ +#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */ +#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */ +#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */ +#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */ +#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */ +#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */ +#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */ +#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific + Error */ +#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */ +/* @} */ + +/** @name Block Size and Block Count Register + * + * This register contains the block count for current transfer, + * block size and SDMA buffer size. + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */ +#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */ +#define XSDPS_BLK_SIZE_1024 0x400U +#define XSDPS_BLK_SIZE_2048 0x800U +#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for + Current Transfer */ + +/* @} */ + +/** @name Transfer Mode and Command Register + * + * The Transfer Mode register is used to control the data transfers and + * Command register is used for command generation + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */ +#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */ +#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */ +#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer + Direction Select */ +#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single + Block Select */ + +#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type + Select */ +#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */ +#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */ +#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */ +#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 & + check busy after + response */ +#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check + Enable */ +#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check + Enable */ +#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */ +#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */ +#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */ +#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */ +#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */ +#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */ +#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask - + Set to CMD0-63, + AMCD0-63 */ + +/* @} */ + +/** @name Auto CMD Error Status Register + * + * This register is read only register which contains + * information about the error status of Auto CMD 12 and 23. + * Read Only + * @{ + */ +#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not + executed */ +#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout + Error */ +#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit + Error */ +#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by + Auto CMD12 Error */ +/* @} */ + +/** @name Host Control2 Register + * + * This register contains extended configuration bits. + * Read Write + * @{ + */ +#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */ +#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */ +#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */ +#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength + Selection */ +#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */ +#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */ +#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */ +#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */ +#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */ +#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock + Selection */ +#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt + Enable */ +#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */ + +/* @} */ + +/** @name Capabilities Register + * + * Capabilities register is a read only register which contains + * information about the host controller. + * Sufficient if read once after power on. + * Read Only + * @{ + */ +#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq + select */ +#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit - + MHz/KHz */ +#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */ +#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */ +#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */ +#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */ +#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */ + +#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */ +#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */ +#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */ +#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */ +#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume + support */ +#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */ +#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */ +#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */ + +#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus + support */ +/* Spec 2.0 */ +#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode + support */ +#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */ +#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */ + + +/* Spec 3.0 */ +#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt + support */ +#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */ +#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */ +#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */ +#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */ + +#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */ +#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */ +#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */ +#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */ +#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */ +#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */ +#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for + Re-tuning */ +#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs + tuning */ +#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes + support */ +#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */ +#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */ +#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */ +#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value + for Programmable clock + mode */ +#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */ +#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */ + +/* @} */ + +/** @name Present State Register + * + * Gives the current status of the host controller + * Read Only + * @{ + */ + +#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */ +#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */ +#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */ +#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */ +#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */ +#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */ +#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */ +#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */ +#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */ +#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */ +#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */ +#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch + pin level */ +#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */ +#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */ +#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */ + +/* @} */ + +/** @name Maximum Current Capabilities Register + * + * This register is read only register which contains + * information about current capabilities at each voltage levels. + * Read Only + * @{ + */ +#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current + Capability at 1.8V */ +#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current + Capability at 3.0V */ +#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current + Capability at 3.3V */ +/* @} */ + + +/** @name Force Event for Auto CMD Error Status Register + * + * This register is write only register which contains + * control bits to generate events for Auto CMD error status. + * Write Only + * @{ + */ +#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not + executed */ +#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout + Error */ +#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit + Error */ +#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by + Auto CMD12 Error */ +/* @} */ + + + +/** @name Force Event for Error Interrupt Status Register + * + * This register is write only register which contains + * control bits to generate events of error interrupt status register. + * Write Only + * @{ + */ +#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout + Error */ +#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */ +#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit + Error */ +#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */ +#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */ +#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */ +#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */ +#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */ +#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */ +#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */ +#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */ +#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific + Error */ + +/* @} */ + +/** @name ADMA Error Status Register + * + * This register is read only register which contains + * status information about ADMA errors. + * Read Only + * @{ + */ +#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch + Error */ +#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */ +#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State + STOP */ +#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State + FDS */ +#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State + TFR */ +/* @} */ + +/** @name Preset Values Register + * + * This register is read only register which contains + * preset values for each of speed modes. + * Read Only + * @{ + */ +#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency + Select Value */ +#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator + Mode Select */ +#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength + Select Value */ + +/* @} */ + +/** @name Slot Interrupt Status Register + * + * This register is read only register which contains + * interrupt slot signal for each slot. + * Read Only + * @{ + */ +#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal + mask */ + +/* @} */ + +/** @name Host Controller Version Register + * + * This register is read only register which contains + * Host Controller and Vendor Specific version. + * Read Only + * @{ + */ +#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor + Specification + version mask */ +#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host + Specification + version mask */ +#define XSDPS_HC_SPEC_V3 0x0002U +#define XSDPS_HC_SPEC_V2 0x0001U +#define XSDPS_HC_SPEC_V1 0x0000U + +/** @name Block size mask for 512 bytes + * + * Block size mask for 512 bytes - This is the default block size. + * @{ + */ + +#define XSDPS_BLK_SIZE_512_MASK 0x200U + +/* @} */ + +/** @name Commands + * + * Constant definitions for commands and response related to SD + * @{ + */ + +#define XSDPS_APP_CMD_PREFIX 0x8000U +#define CMD0 0x0000U +#define CMD1 0x0100U +#define CMD2 0x0200U +#define CMD3 0x0300U +#define CMD4 0x0400U +#define CMD5 0x0500U +#define CMD6 0x0600U +#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U) +#define CMD7 0x0700U +#define CMD8 0x0800U +#define CMD9 0x0900U +#define CMD10 0x0A00U +#define CMD11 0x0B00U +#define CMD12 0x0C00U +#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U) +#define CMD16 0x1000U +#define CMD17 0x1100U +#define CMD18 0x1200U +#define CMD19 0x1300U +#define CMD21 0x1500U +#define CMD23 0x1700U +#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U) +#define CMD24 0x1800U +#define CMD25 0x1900U +#define CMD41 0x2900U +#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U) +#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U) +#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U) +#define CMD52 0x3400U +#define CMD55 0x3700U +#define CMD58 0x3A00U + +#if 0 +#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK +#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \ + (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK +#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK + +#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK +#else +#define XSDPS_RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK +#define XSDPS_RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \ + (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define XSDPS_RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define XSDPS_RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK +#define XSDPS_RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK + +#define XSDPS_RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK +#endif + +/* @} */ + +/* Card Interface Conditions Definitions */ +#define XSDPS_CIC_CHK_PATTERN 0xAAU +#define XSDPS_CIC_VOLT_MASK (0xFU<<8) +#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8) +#define XSDPS_CIC_VOLT_LOW (1U<<9) + +/* Operation Conditions Register Definitions */ +#define XSDPS_OCR_PWRUP_STS (1U<<31) +#define XSDPS_OCR_CC_STS (1U<<30) +#define XSDPS_OCR_S18 (1U<<24) +#define XSDPS_OCR_3V5_3V6 (1U<<23) +#define XSDPS_OCR_3V4_3V5 (1U<<22) +#define XSDPS_OCR_3V3_3V4 (1U<<21) +#define XSDPS_OCR_3V2_3V3 (1U<<20) +#define XSDPS_OCR_3V1_3V2 (1U<<19) +#define XSDPS_OCR_3V0_3V1 (1U<<18) +#define XSDPS_OCR_2V9_3V0 (1U<<17) +#define XSDPS_OCR_2V8_2V9 (1U<<16) +#define XSDPS_OCR_2V7_2V8 (1U<<15) +#define XSDPS_OCR_1V7_1V95 (1U<<7) +#define XSDPS_OCR_HIGH_VOL 0x00FF8000U +#define XSDPS_OCR_LOW_VOL 0x00000080U + +/* SD Card Configuration Register Definitions */ +#define XSDPS_SCR_REG_LEN 8U +#define XSDPS_SCR_STRUCT_MASK (0xFU<<28) +#define XSDPS_SCR_SPEC_MASK (0xFU<<24) +#define XSDPS_SCR_SPEC_1V0 0U +#define XSDPS_SCR_SPEC_1V1 (1U<<24) +#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24) +#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23) +#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20) +#define XSDPS_SCR_SEC_SUPP_NONE 0U +#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20) +#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20) +#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20) +#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16) +#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16) +#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16) +#define XSDPS_SCR_SPEC3_MASK (1U<<12) +#define XSDPS_SCR_SPEC3_2V0 0U +#define XSDPS_SCR_SPEC3_3V0 (1U<<12) +#define XSDPS_SCR_CMD_SUPP_MASK 0x3U +#define XSDPS_SCR_CMD23_SUPP (1U<<1) +#define XSDPS_SCR_CMD20_SUPP (1U<<0) + +/* Card Status Register Definitions */ +#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31) +#define XSDPS_CD_STS_ADDR_ERR (1U<<30) +#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29) +#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28) +#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27) +#define XSDPS_CD_STS_WP_VIO (1U<<26) +#define XSDPS_CD_STS_IS_LOCKED (1U<<25) +#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24) +#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23) +#define XSDPS_CD_STS_ILGL_CMD (1U<<22) +#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21) +#define XSDPS_CD_STS_CC_ERR (1U<<20) +#define XSDPS_CD_STS_ERR (1U<<19) +#define XSDPS_CD_STS_CSD_OVRWR (1U<<16) +#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15) +#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14) +#define XSDPS_CD_STS_ER_RST (1U<<13) +#define XSDPS_CD_STS_CUR_STATE (0xFU<<9) +#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8) +#define XSDPS_CD_STS_APP_CMD (1U<<5) +#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2) + +/* Switch Function Definitions CMD6 */ +#define XSDPS_SWITCH_SD_RESP_LEN 64U + +#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31) +#define XSDPS_SWITCH_FUNC_CHECK 0U + +#define XSDPS_MODE_FUNC_GRP1 1U +#define XSDPS_MODE_FUNC_GRP2 2U +#define XSDPS_MODE_FUNC_GRP3 3U +#define XSDPS_MODE_FUNC_GRP4 4U +#define XSDPS_MODE_FUNC_GRP5 5U +#define XSDPS_MODE_FUNC_GRP6 6U + +#define XSDPS_FUNC_GRP_DEF_VAL 0xFU +#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU + +#define XSDPS_ACC_MODE_DEF_SDR12 0U +#define XSDPS_ACC_MODE_HS_SDR25 1U +#define XSDPS_ACC_MODE_SDR50 2U +#define XSDPS_ACC_MODE_SDR104 3U +#define XSDPS_ACC_MODE_DDR50 4U + +#define XSDPS_CMD_SYS_ARG_SHIFT 4U +#define XSDPS_CMD_SYS_DEF 0U +#define XSDPS_CMD_SYS_eC 1U +#define XSDPS_CMD_SYS_OTP 3U +#define XSDPS_CMD_SYS_ASSD 4U +#define XSDPS_CMD_SYS_VEND 5U + +#define XSDPS_DRV_TYPE_ARG_SHIFT 8U +#define XSDPS_DRV_TYPE_B 0U +#define XSDPS_DRV_TYPE_A 1U +#define XSDPS_DRV_TYPE_C 2U +#define XSDPS_DRV_TYPE_D 3U + +#define XSDPS_CUR_LIM_ARG_SHIFT 12U +#define XSDPS_CUR_LIM_200 0U +#define XSDPS_CUR_LIM_400 1U +#define XSDPS_CUR_LIM_600 2U +#define XSDPS_CUR_LIM_800 3U + +#define CSD_SPEC_VER_MASK 0x3C0000U +#define READ_BLK_LEN_MASK 0x00000F00U +#define C_SIZE_MULT_MASK 0x00000380U +#define C_SIZE_LOWER_MASK 0xFFC00000U +#define C_SIZE_UPPER_MASK 0x00000003U +#define CSD_STRUCT_MASK 0x00C00000U +#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U + +/* EXT_CSD field definitions */ +#define XSDPS_EXT_CSD_SIZE 512U + +#define EXT_CSD_WR_REL_PARAM_EN (1U<<2) + +#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U) +#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U) + +#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U) +#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U) +#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U) +#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U) +#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U) +#define EXT_CSD_PART_CONFIG_BYTE 179U +#define XSDPS_MMC_PART_CFG_0_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ + | (EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((0U) << 8U)) + +#define XSDPS_MMC_PART_CFG_1_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ + | (EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | (EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U)) + +#define XSDPS_MMC_PART_CFG_2_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ + | (EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | (EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U)) + +#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U) + +#define EXT_CSD_CMD_SET_NORMAL (1U<<0) +#define EXT_CSD_CMD_SET_SECURE (1U<<1) +#define EXT_CSD_CMD_SET_CPSECURE (1U<<2) + +#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */ + /* DDR mode @1.8V or 3V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */ + /* DDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) +#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */ + /* SDR mode @1.2V I/O */ +#define EXT_CSD_BUS_WIDTH_BYTE 183U +#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */ +#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */ + +#define EXT_CSD_HS_TIMING_BYTE 185U +#define EXT_CSD_HS_TIMING_DEF 0U +#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */ +#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */ + +#define EXT_CSD_RST_N_FUN_BYTE 162U +#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */ +#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */ +#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */ + +#define XSDPS_EXT_CSD_CMD_SET 0U +#define XSDPS_EXT_CSD_SET_BITS 1U +#define XSDPS_EXT_CSD_CLR_BITS 2U +#define XSDPS_EXT_CSD_WRITE_BYTE 3U + +#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) + +#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) + +#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) + +#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8)) + +#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) + +#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) + +#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) + +#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) + +#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ + | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) + +#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U + +/* @} */ + +/* @400KHz, in usec */ +#define XSDPS_74CLK_DELAY 2960U +#define XSDPS_100CLK_DELAY 4000U +#define XSDPS_INIT_DELAY 10000U + +#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK +#define XSDPS_CARD_DEF_ADDR 0x1234U + +#define XSDPS_CARD_SD 1U +#define XSDPS_CARD_MMC 2U +#define XSDPS_CARD_SDIO 3U +#define XSDPS_CARD_SDCOMBO 4U +#define XSDPS_CHIP_EMMC 5U + + +/** @name ADMA2 Descriptor related definitions + * + * ADMA2 Descriptor related definitions + * @{ + */ + +#define XSDPS_DESC_MAX_LENGTH 65536U + +#define XSDPS_DESC_VALID (0x1U << 0) +#define XSDPS_DESC_END (0x1U << 1) +#define XSDPS_DESC_INT (0x1U << 2) +#define XSDPS_DESC_TRAN (0x2U << 4) + +/* @} */ + +/* For changing clock frequencies */ +#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */ +#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */ +#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */ +#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */ +#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */ +#define XSDPS_SCR_BLKCNT 1U +#define XSDPS_SCR_BLKSIZE 8U +#define XSDPS_1_BIT_WIDTH 0x1U +#define XSDPS_4_BIT_WIDTH 0x2U +#define XSDPS_8_BIT_WIDTH 0x3U +#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U +#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U +#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U +#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U +#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U +#define XSDPS_HIGH_SPEED_MODE 0x5U +#define XSDPS_DEFAULT_SPEED_MODE 0x6U +#define XSDPS_HS200_MODE 0x7U +#define XSDPS_DDR52_MODE 0x4U +#define XSDPS_SWITCH_CMD_BLKCNT 1U +#define XSDPS_SWITCH_CMD_BLKSIZE 64U +#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U +#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U +#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U +#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U +#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U +#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U +#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U +#define XSDPS_EXT_CSD_CMD_BLKCNT 1U +#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U +#define XSDPS_TUNING_CMD_BLKCNT 1U +#define XSDPS_TUNING_CMD_BLKSIZE 64U +#define XSDPS_SD_STATUS_BLKCNT 1U +#define XSDPS_SD_STATUS_BLKSIZE 64U + +#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U +#define XSDPS_UHS_SDR104_MAX_CLK 208000000U +#define XSDPS_UHS_SDR50_MAX_CLK 100000000U +#define XSDPS_UHS_DDR50_MAX_CLK 50000000U +#define XSDPS_UHS_SDR25_MAX_CLK 50000000U +#define XSDPS_UHS_SDR12_MAX_CLK 25000000U + +#define SD_DRIVER_TYPE_B 0x01U +#define SD_DRIVER_TYPE_A 0x02U +#define SD_DRIVER_TYPE_C 0x04U +#define SD_DRIVER_TYPE_D 0x08U +#define SD_SET_CURRENT_LIMIT_200 0U +#define SD_SET_CURRENT_LIMIT_400 1U +#define SD_SET_CURRENT_LIMIT_600 2U +#define SD_SET_CURRENT_LIMIT_800 3U + +#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) +#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) +#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) +#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) + +#define XSDPS_SD_SDR12_MAX_CLK 25000000U +#define XSDPS_SD_SDR25_MAX_CLK 50000000U +#define XSDPS_SD_SDR50_MAX_CLK 100000000U +#define XSDPS_SD_DDR50_MAX_CLK 50000000U +#define XSDPS_SD_SDR104_MAX_CLK 208000000U +/* + * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller + * than the clock value coming from the core. This value is kept to safely + * switch to SDR104 mode if the SD card supports it. + */ +#define XSDPS_SD_INPUT_MAX_CLK 175000000U + +#define XSDPS_MMC_HS200_MAX_CLK 200000000U +#define XSDPS_MMC_HSD_MAX_CLK 52000000U +#define XSDPS_MMC_DDR_MAX_CLK 52000000U + +#define XSDPS_CARD_STATE_IDLE 0U +#define XSDPS_CARD_STATE_RDY 1U +#define XSDPS_CARD_STATE_IDEN 2U +#define XSDPS_CARD_STATE_STBY 3U +#define XSDPS_CARD_STATE_TRAN 4U +#define XSDPS_CARD_STATE_DATA 5U +#define XSDPS_CARD_STATE_RCV 6U +#define XSDPS_CARD_STATE_PROG 7U +#define XSDPS_CARD_STATE_DIS 8U +#define XSDPS_CARD_STATE_BTST 9U +#define XSDPS_CARD_STATE_SLP 10U + +#define XSDPS_SLOT_REM 0U +#define XSDPS_SLOT_EMB 1U + +#define XSDPS_WIDTH_8 8U +#define XSDPS_WIDTH_4 4U + + +#ifdef versal +#define SD_ITAPDLY_SEL_MASK 0x000000FFU +#define SD_OTAPDLY_SEL_MASK 0x0000003FU +#define SD_ITAPDLY 0x0000F0F8U +#define SD_OTAPDLY 0x0000F0FCU +#define SD0_DLL_CTRL 0x00000448U +#define SD1_DLL_CTRL 0x000004C8U +#define SD_DLL_RST 0x00000004U +#define SD_ITAPCHGWIN 0x00000200U +#define SD_ITAPDLYENA 0x00000100U +#define SD_OTAPDLYENA 0x00000040U +#define SD_OTAPDLYSEL_HS200_B0 0x00000002U +#define SD_OTAPDLYSEL_HS200_B2 0x00000002U +#define SD_ITAPDLYSEL_SD50 0x0000000EU +#define SD_OTAPDLYSEL_SD50 0x00000003U +#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U +#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU +#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U +#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U +#define SD_ITAPDLYSEL_HSD 0x0000002CU +#define SD_OTAPDLYSEL_SD_HSD 0x00000004U +#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U +#else +#define SD0_ITAPDLY_SEL_MASK 0x000000FFU +#define SD0_OTAPDLY_SEL_MASK 0x0000003FU +#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U +#define SD1_OTAPDLY_SEL_MASK 0x003F0000U +#define SD_DLL_CTRL 0x00000358U +#define SD_ITAPDLY 0x00000314U +#define SD_OTAPDLY 0x00000318U +#define SD0_DLL_RST 0x00000004U +#define SD1_DLL_RST 0x00040000U +#define SD0_ITAPCHGWIN 0x00000200U +#define SD0_ITAPDLYENA 0x00000100U +#define SD0_OTAPDLYENA 0x00000040U +#define SD1_ITAPCHGWIN 0x02000000U +#define SD1_ITAPDLYENA 0x01000000U +#define SD1_OTAPDLYENA 0x00400000U +#define SD_OTAPDLYSEL_HS200_B0 0x00000003U +#define SD_OTAPDLYSEL_HS200_B2 0x00000002U +#define SD_ITAPDLYSEL_SD50 0x00000014U +#define SD_OTAPDLYSEL_SD50 0x00000003U +#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU +#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U +#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U +#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U +#define SD_ITAPDLYSEL_HSD 0x00000015U +#define SD_OTAPDLYSEL_SD_HSD 0x00000005U +#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U +#endif + +#ifdef __MICROBLAZE__ +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U +#endif + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define XSdPs_In64 Xil_In64 +#define XSdPs_Out64 Xil_Out64 + +#define XSdPs_In32 Xil_In32 +#define XSdPs_Out32 Xil_Out32 + +#define XSdPs_In16 Xil_In16 +#define XSdPs_Out16 Xil_Out16 + +#define XSdPs_In8 Xil_In8 +#define XSdPs_Out8 Xil_Out8 + +/****************************************************************************/ +/** +* Read a register. +* +* @param InstancePtr is the pointer to the sdps instance. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg64(InstancePtr, RegOffset) \ + XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param InstancePtr is the pointer to the sdps instance. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset, +* u64 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \ + XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \ + (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg(BaseAddress, RegOffset) \ + XSdPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u16)Reg; +#else + return XSdPs_In16((BaseAddress) + (RegOffset)); +#endif +} + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ + +static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u8)Reg; +#else + return XSdPs_In8((BaseAddress) + (RegOffset)); +#endif +} +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} +/***************************************************************************/ +/** +* Macro to get present status register +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +#define XSdPs_GetPresentStatusReg(BaseAddress) \ + XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SD_HW_H_ */ +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c new file mode 100644 index 0000000000..ecf28d3589 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c @@ -0,0 +1,698 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps_options.c +* @addtogroup sdps_v3_9 +* @{ +* +* Contains API's for changing the various options in host and card. +* See xsdps.h for a detailed description of the device and driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       vns    03/13/17 Fixed MISRAC mandatory violation
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
+*       mn     08/07/17	Properly set OTAPDLY value by clearing previous bit
+* 			settings
+*       mn     08/17/17 Added CCI support for A53 and disabled data cache
+*                       operations when it is enabled.
+*       mn     08/22/17 Updated for Word Access System support
+* 3.4   mn     01/22/18 Separated out SDR104 and HS200 clock defines
+* 3.6   mn     07/06/18 Fix Cppcheck warnings for sdps driver
+* 3.7   aru    03/12/19 Modified the code according to MISRAC-2012.
+*       mn     03/27/19 Disable calls to dll_reset API for versal SPP Platforms
+* 3.8   mn     04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
+*       mn     05/21/19 Set correct tap delays for Versal
+*       mn     05/21/19 Disable DLL Reset code for Versal
+*       mn     08/29/19 Add call to Cache Invalidation API in XSdPs_Get_BusWidth
+* 3.9   mn     03/03/20 Restructured the code for more readability and modularity
+*       mn     03/16/20 Move XSdPs_Select_Card API to User APIs
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xsdps_core.h" +/************************** Constant Definitions *****************************/ +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* @brief +* API to change clock freq to given value. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param SelFreq - Clock frequency in Hz. +* +* @return None +* +* @note This API will change clock frequency to the value less than +* or equal to the given value using the permissible dividors. +* +******************************************************************************/ +s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { + /* Program the Tap delays */ + XSdPs_SetTapDelay(InstancePtr); + } + + Status = XSdPs_SetClock(InstancePtr, SelFreq); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + return Status; +} + +/*****************************************************************************/ +/** +* @brief +* Update Block size for read/write operations. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param BlkSize - Block size passed by the user. +* +* @return None +* +******************************************************************************/ +s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Status = XSdPs_CheckBusIdle(InstancePtr, (XSDPS_PSR_INHIBIT_CMD_MASK + | XSDPS_PSR_INHIBIT_DAT_MASK + | XSDPS_PSR_WR_ACTIVE_MASK + | XSDPS_PSR_RD_ACTIVE_MASK)); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH ; + } + + /* Send block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Set block size to the value passed */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, + BlkSize & XSDPS_BLK_SIZE_MASK); + +RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief +* API to get bus width support by card. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param SCR - buffer to store SCR register returned by card. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff) +{ + s32 Status; + u16 BlkCnt; + u16 BlkSize; + s32 LoopCnt; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) { + ReadBuff[LoopCnt] = 0U; + } + + /* Send block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD55, + InstancePtr->RelCardAddr, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + BlkCnt = XSDPS_SCR_BLKCNT; + BlkSize = XSDPS_SCR_BLKSIZE; + + XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff); + + Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, + (INTPTR)BlkCnt * BlkSize); + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief +* API to set bus width to 4-bit in card and host +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) +{ + s32 Status; + u32 StatusReg; + u32 Arg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * check for bus width for 3.0 controller and return if + * bus width is <4 + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) { + Status = XST_SUCCESS; + goto RETURN_PATH; + } + + if (InstancePtr->CardType == XSDPS_CARD_SD) { + + Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, + 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, (u32)InstancePtr->BusWidth, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG; + } else { + Arg = XSDPS_MMC_8_BIT_BUS_ARG; + } + } else { + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG; + } else { + Arg = XSDPS_MMC_4_BIT_BUS_ARG; + } + } + + Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + usleep(XSDPS_MMC_DELAY_FOR_SWITCH); + + StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET); + + /* Width setting in controller */ + if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { + StatusReg |= XSDPS_HC_EXT_BUS_WIDTH; + } else { + StatusReg |= XSDPS_HC_WIDTH_MASK; + } + + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET, + (u8)StatusReg); + + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + StatusReg &= (u32)(~XSDPS_HC2_UHS_MODE_MASK); + StatusReg |= InstancePtr->Mode; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg); + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief +* API to get bus speed supported by card. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param ReadBuff - buffer to store function group support data +* returned by card. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) +{ + s32 Status; + u32 Arg; + u16 BlkCnt; + u16 BlkSize; + s32 LoopCnt; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) { + ReadBuff[LoopCnt] = 0U; + } + + BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; + BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; + + XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff); + + Arg = XSDPS_SWITCH_CMD_HS_GET; + + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, + (INTPTR)BlkCnt * BlkSize); + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief +* API to get SD card status information. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param SdStatReg - buffer to store status data returned by card. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg) +{ + s32 Status; + u16 BlkCnt; + u16 BlkSize; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Send block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD55, + InstancePtr->RelCardAddr, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + BlkCnt = XSDPS_SD_STATUS_BLKCNT; + BlkSize = XSDPS_SD_STATUS_BLKSIZE; + + XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, SdStatReg); + + Status = XSdPs_CmdTransfer(InstancePtr, ACMD13, 0U, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheInvalidateRange((INTPTR)SdStatReg, + (INTPTR)BlkCnt * BlkSize); + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief +* API to set high speed in card and host. Changes clock in host accordingly. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) +{ + s32 Status; + u32 StatusReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->CardType == XSDPS_CARD_SD) { + Status = XSdPs_Change_SdBusSpeed(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + Status = XSdPs_Change_MmcBusSpeed(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if ((InstancePtr->Mode == XSDPS_HS200_MODE) || + (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR104) || + (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR50)) { + Status = XSdPs_Execute_Tuning(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + usleep(XSDPS_MMC_DELAY_FOR_SWITCH); + + StatusReg = (u32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET); + StatusReg |= XSDPS_HC_SPEED_MASK; + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief +* API to get EXT_CSD register of eMMC. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param ReadBuff - buffer to store EXT_CSD +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) +{ + s32 Status; + u32 Arg = 0U; + u16 BlkCnt; + u16 BlkSize; + s32 LoopCnt; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) { + ReadBuff[LoopCnt] = 0U; + } + + BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT; + BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE; + + XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff); + + /* Send SEND_EXT_CSD command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + if (InstancePtr->Config.IsCacheCoherent == 0U) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, + (INTPTR)BlkCnt * BlkSize); + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief +* API to write EXT_CSD register of eMMC. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param Arg is the argument to be sent along with the command +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Check for transfer done */ + Status = XSdps_CheckTransferDone(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief +* API to send pullup command to card before using DAT line 3(using 4-bit bus) +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Pullup(XSdPs *InstancePtr) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + Status = XSdPs_CmdTransfer(InstancePtr, CMD55, + InstancePtr->RelCardAddr, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief +* Selects card and sets default block size +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* - XSDPS_CT_ERROR if Command Transfer fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Select_Card (XSdPs *InstancePtr) +{ + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Send CMD7 - Select card */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD7, + InstancePtr->RelCardAddr, 0U); + + return Status; +} + +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c new file mode 100644 index 0000000000..cf5708a864 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps_sinit.c +* @addtogroup sdps_v3_9 +* @{ +* +* The implementation of the XSdPs component's static initialization +* functionality. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 3.7   aru    03/12/19 Modified the code according to MISRAC-2012.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xstatus.h" +#include "xsdps.h" +#include "xparameters.h" +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES]; + +/*****************************************************************************/ +/** +* +* @brief +* Looks up the device configuration based on the unique device ID. A table +* contains the configuration info for each device in the system. +* +* @param DeviceId contains the ID of the device to look up the +* configuration for. +* +* @return +* +* A pointer to the configuration found or NULL if the specified device ID was +* not found. See xsdps.h for the definition of XSdPs_Config. +* +* @note None. +* +******************************************************************************/ +XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId) +{ + XSdPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) { + if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XSdPs_ConfigTable[Index]; + break; + } + } + return (XSdPs_Config *)CfgPtr; +} +/** @} */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h new file mode 100644 index 0000000000..b49a864dc6 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h @@ -0,0 +1,31 @@ +#ifndef XLI_SLEEP_H +#define XLI_SLEEP_H + +#include +#include + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void usleep(unsigned long useconds) +{ + rt_uint32_t milliseconds = useconds/1000; + useconds = useconds%1000; + if (milliseconds) rt_thread_mdelay(milliseconds); + if (useconds) rt_hw_us_delay(useconds); +} + +static inline void sleep(unsigned int seconds) +{ + rt_thread_delay(seconds); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h new file mode 100644 index 0000000000..de095f1f4c --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h @@ -0,0 +1,21 @@ +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif +#define Xil_AssertNonvoid(Expression) RT_ASSERT(Expression) +#define Xil_AssertVoid(Expression) RT_ASSERT(Expression) +#define Xil_AssertVoidAlways() RT_ASSERT(0) + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_assert_apis". +*/ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h new file mode 100644 index 0000000000..1731e84850 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h @@ -0,0 +1,18 @@ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define Xil_DCacheFlushRange(addr, size) rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)(addr), (size)) +#define Xil_DCacheInvalidateRange(addr, size) rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void*)(addr), (size)) + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup r5_cache_apis". +*/ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h new file mode 100644 index 0000000000..c23ba948a3 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h @@ -0,0 +1,204 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* @addtogroup common_io_interfacing_apis Register IO interfacing APIs +* +* The xil_io.h file contains the interface for the general I/O component, which +* encapsulates the Input/Output functions for the processors that do not +* require any special I/O handling. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+* 7.20  har      01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
+*                         CR-1049218
+*
+******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_printf.h" +#include "xstatus.h" + +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) +#define INLINE inline +#else +#define INLINE __inline +#endif + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading +* from the specified address and returning the 8 bit Value read from +* that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 8 bit Value read from the specified input address. + +* +******************************************************************************/ +static INLINE u8 Xil_In8(UINTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading from +* the specified address and returning the 16 bit Value read from that +* address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 16 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u16 Xil_In16(UINTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by +* reading from the specified address and returning the 32 bit Value +* read from that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 32 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading the +* 64 bit Value read from that address. +* +* +* @param Addr: contains the address to perform the input operation +* +* @return The 64 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u64 Xil_In64(UINTPTR Addr) +{ + return *(volatile u64 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for an memory location by +* writing the 8 bit Value to the the specified address. +* +* @param Addr: contains the address to perform the output operation +* @param Value: contains the 8 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out8(UINTPTR Addr, u8 Value) +{ + volatile u8 *LocalAddr = (volatile u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 16 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out16(UINTPTR Addr, u16 Value) +{ + volatile u16 *LocalAddr = (volatile u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 32 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the 32 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out32(UINTPTR Addr, u32 Value) +{ +#ifndef ENABLE_SAFETY + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +#else + XStl_RegUpdate(Addr, Value); +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 64 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains 64 bit Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out64(UINTPTR Addr, u64 Value) +{ + volatile u64 *LocalAddr = (volatile u64 *)Addr; + *LocalAddr = Value; +} + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_io_interfacing_apis". +*/ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h new file mode 100644 index 0000000000..89b6c3cc32 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h @@ -0,0 +1,16 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define xil_printf rt_kprintf + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h new file mode 100644 index 0000000000..3970866971 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h @@ -0,0 +1,96 @@ +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ + +typedef rt_uint8_t u8; +typedef rt_uint16_t u16; +typedef rt_uint32_t u32; + +typedef char char8; +typedef rt_int8_t s8; +typedef rt_int16_t s16; +typedef rt_int32_t s32; +typedef rt_int64_t s64; +typedef rt_uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; + + +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +/** @{ */ +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#ifdef __cplusplus +} +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_types". +*/ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h new file mode 100644 index 0000000000..dc408009d7 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h @@ -0,0 +1,1511 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + +/* Definition for CPU ID */ +#define XPAR_CPU_ID 0U + +/* Definitions for peripheral PSU_CORTEXR5_0 */ +#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CORTEXR5_0 */ +#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 + + +/******************************************************************/ + + /* Definition for PSS REF CLK FREQUENCY */ +#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U + +#include "xparameters_ps.h" + +/******************************************************************/ + + /*Definitions for peripheral PSU_R5_DDR_1 */ +#define XPAR_PSU_R5_DDR_1_S_AXI_BASEADDR 0x0 +#define XPAR_PSU_R5_DDR_1_S_AXI_HIGHADDR 0x7fffffff + + +/* Number of Fabric Resets */ +#define XPAR_NUM_FABRIC_RESETS 1 + +#define STDIN_BASEADDRESS 0xFF000000 +#define STDOUT_BASEADDRESS 0xFF000000 + +/******************************************************************/ + +/* Platform specific definitions */ +#define PLATFORM_ZYNQMP + +/* Definitions for debug logic configuration in lockstep mode */ +#define LOCKSTEP_MODE_DEBUG 0U + +/* Definitions for sleep timer configuration */ +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + +/* Definitions for processor access to RPU/IOU slcr address space*/ +#define PROCESSOR_ACCESS_VALUE 255 + +/******************************************************************/ +/* Definitions for driver AVBUF */ +#define XPAR_XAVBUF_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DP */ +#define XPAR_PSU_DP_DEVICE_ID 0 +#define XPAR_PSU_DP_BASEADDR 0xFD4A0000 +#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_DP */ +#define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID +#define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000 +#define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF + + +/******************************************************************/ + +/* Definitions for driver AXIPMON */ +#define XPAR_XAXIPMON_NUM_INSTANCES 4U + +/* Definitions for peripheral PSU_APM_0 */ +#define XPAR_PSU_APM_0_DEVICE_ID 0U +#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U +#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU +#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U +#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U +#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_0_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_0_ENABLE_TRACE 0U +#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U + + +/* Definitions for peripheral PSU_APM_1 */ +#define XPAR_PSU_APM_1_DEVICE_ID 1U +#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U +#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU +#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_1_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_1_ENABLE_TRACE 0U +#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U + + +/* Definitions for peripheral PSU_APM_2 */ +#define XPAR_PSU_APM_2_DEVICE_ID 2U +#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U +#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU +#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_2_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_2_ENABLE_TRACE 0U +#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U + + +/* Definitions for peripheral PSU_APM_5 */ +#define XPAR_PSU_APM_5_DEVICE_ID 3U +#define XPAR_PSU_APM_5_BASEADDR 0xFD490000U +#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU +#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_5_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_5_ENABLE_TRACE 0U +#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_APM_0 */ +#define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID +#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U +#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU +#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U +#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U +#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_0_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_0_ENABLE_TRACE 0U +#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U + +/* Canonical definitions for peripheral PSU_APM_1 */ +#define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID +#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U +#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU +#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_1_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_1_ENABLE_TRACE 0U +#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U + +/* Canonical definitions for peripheral PSU_APM_2 */ +#define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID +#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U +#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU +#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_2_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_2_ENABLE_TRACE 0U +#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U + +/* Canonical definitions for peripheral PSU_APM_5 */ +#define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID +#define XPAR_AXIPMON_3_BASEADDR 0xFD490000U +#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU +#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_3_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_3_ENABLE_TRACE 0U +#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U + + +/******************************************************************/ + +/* Definitions for driver CANPS */ +#define XPAR_XCANPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_CAN_0 */ +#define XPAR_PSU_CAN_0_DEVICE_ID 0 +#define XPAR_PSU_CAN_0_BASEADDR 0xFF060000 +#define XPAR_PSU_CAN_0_HIGHADDR 0xFF06FFFF +#define XPAR_PSU_CAN_0_CAN_CLK_FREQ_HZ 99999001 + + +/* Definitions for peripheral PSU_CAN_1 */ +#define XPAR_PSU_CAN_1_DEVICE_ID 1 +#define XPAR_PSU_CAN_1_BASEADDR 0xFF070000 +#define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF +#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99999001 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CAN_0 */ +#define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_0_DEVICE_ID +#define XPAR_XCANPS_0_BASEADDR 0xFF060000 +#define XPAR_XCANPS_0_HIGHADDR 0xFF06FFFF +#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99999001 + +/* Canonical definitions for peripheral PSU_CAN_1 */ +#define XPAR_XCANPS_1_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID +#define XPAR_XCANPS_1_BASEADDR 0xFF070000 +#define XPAR_XCANPS_1_HIGHADDR 0xFF07FFFF +#define XPAR_XCANPS_1_CAN_CLK_FREQ_HZ 99999001 + + +/******************************************************************/ + +/* Definitions for driver CSUDMA */ +#define XPAR_XCSUDMA_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_CSUDMA */ +#define XPAR_PSU_CSUDMA_DEVICE_ID 0 +#define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000 +#define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF +#define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +#define XPAR_PSU_CSUDMA_DMATYPE 0 +/* Canonical definitions for peripheral PSU_CSUDMA */ +#define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID +#define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000 +#define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF +#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +/* Definitions for driver DDRCPSU */ +#define XPAR_XDDRCPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DDRC_0 */ +#define XPAR_PSU_DDRC_0_DEVICE_ID 0 +#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000 +#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF +#define XPAR_PSU_DDRC_0_HAS_ECC 0 +#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 599994019 + + +/******************************************************************/ + +#define XPAR_PSU_DDRC_0_DDR4_ADDR_MAPPING 0 +#define XPAR_PSU_DDRC_0_DDR_FREQ_MHZ 1199.988037 +#define XPAR_PSU_DDRC_0_VIDEO_BUFFER_SIZE 0 +#define XPAR_PSU_DDRC_0_BRC_MAPPING 0 +#define XPAR_PSU_DDRC_0_DDR_MEMORY_TYPE 4 +#define XPAR_PSU_DDRC_0_DDR_MEMORY_ADDRESS_MAP 0 +#define XPAR_PSU_DDRC_0_DDR_DATA_MASK_AND_DBI 7 +#define XPAR_PSU_DDRC_0_DDR_ADDRESS_MIRRORING 0 +#define XPAR_PSU_DDRC_0_DDR_2ND_CLOCK 0 +#define XPAR_PSU_DDRC_0_DDR_PARITY 0 +#define XPAR_PSU_DDRC_0_DDR_POWER_DOWN_ENABLE 0 +#define XPAR_PSU_DDRC_0_CLOCK_STOP 0 +#define XPAR_PSU_DDRC_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0 +#define XPAR_PSU_DDRC_0_DDR_TEMP_CONTROLLED_REFRESH 0 +#define XPAR_PSU_DDRC_0_DDR_MAX_OPERATING_TEMPARATURE 0 +#define XPAR_PSU_DDRC_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0 +#define XPAR_PSU_DDRC_0_DDR_SELF_REFRESH_ABORT 0 +/* Canonical definitions for peripheral PSU_DDRC_0 */ +#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID +#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000 +#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF +#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 599994019 + + +/******************************************************************/ + +#define XPAR_DDRCPSU_0_DDR4_ADDR_MAPPING 0 +#define XPAR_DDRCPSU_0_DDR_FREQ_MHZ 1199.988037 +#define XPAR_DDRCPSU_0_VIDEO_BUFFER_SIZE 0 +#define XPAR_DDRCPSU_0_BRC_MAPPING 0 +#define XPAR_DDRCPSU_0_DDR_MEMORY_TYPE 4 +#define XPAR_DDRCPSU_0_DDR_MEMORY_ADDRESS_MAP 0 +#define XPAR_DDRCPSU_0_DDR_DATA_MASK_AND_DBI 7 +#define XPAR_DDRCPSU_0_DDR_ADDRESS_MIRRORING 0 +#define XPAR_DDRCPSU_0_DDR_2ND_CLOCK 0 +#define XPAR_DDRCPSU_0_DDR_PARITY 0 +#define XPAR_DDRCPSU_0_DDR_POWER_DOWN_ENABLE 0 +#define XPAR_DDRCPSU_0_CLOCK_STOP 0 +#define XPAR_DDRCPSU_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0 +#define XPAR_DDRCPSU_0_DDR_TEMP_CONTROLLED_REFRESH 0 +#define XPAR_DDRCPSU_0_DDR_MAX_OPERATING_TEMPARATURE 0 +#define XPAR_DDRCPSU_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0 +#define XPAR_DDRCPSU_0_DDR_SELF_REFRESH_ABORT 0 +/* Definitions for driver DPDMA */ +#define XPAR_XDPDMA_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DPDMA */ +#define XPAR_PSU_DPDMA_DEVICE_ID 0 +#define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000 +#define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_DPDMA */ +#define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID +#define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000 +#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF + + +/******************************************************************/ + +/* Definitions for driver EMACPS */ +#define XPAR_XEMACPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_ETHERNET_3 */ +#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0 +#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000 +#define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF +#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10 +#define XPAR_PSU_ETHERNET_3_ENET_TSU_CLK_FREQ_HZ 249997498 + + +/******************************************************************/ + +#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0 +#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ETHERNET_3_REF_CLK 0xff +/* Canonical definitions for peripheral PSU_ETHERNET_3 */ +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID +#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000 +#define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249997498 + + +/******************************************************************/ + + +/* Definitions for peripheral PSU_AFI_0 */ +#define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000 +#define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF + + +/* Definitions for peripheral PSU_AFI_1 */ +#define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000 +#define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF + + +/* Definitions for peripheral PSU_AFI_2 */ +#define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000 +#define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF + + +/* Definitions for peripheral PSU_AFI_3 */ +#define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000 +#define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF + + +/* Definitions for peripheral PSU_AFI_4 */ +#define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000 +#define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF + + +/* Definitions for peripheral PSU_AFI_5 */ +#define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000 +#define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF + + +/* Definitions for peripheral PSU_AFI_6 */ +#define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000 +#define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF + + +/* Definitions for peripheral PSU_APU */ +#define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000 +#define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF + + +/* Definitions for peripheral PSU_CCI_GPV */ +#define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000 +#define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF + + +/* Definitions for peripheral PSU_CCI_REG */ +#define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000 +#define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF + + +/* Definitions for peripheral PSU_CRL_APB */ +#define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000 +#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF + + +/* Definitions for peripheral PSU_CSU_0 */ +#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000 +#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF + + +/* Definitions for peripheral PSU_CTRL_IPI */ +#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000 +#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF + + +/* Definitions for peripheral PSU_DDR_PHY */ +#define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000 +#define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF + + +/* Definitions for peripheral PSU_DDR_QOS_CTRL */ +#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000 +#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU0_CFG */ +#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000 +#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU1_CFG */ +#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000 +#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU2_CFG */ +#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000 +#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU3_CFG */ +#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000 +#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU4_CFG */ +#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000 +#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU5_CFG */ +#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000 +#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF + + +/* Definitions for peripheral PSU_EFUSE */ +#define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000 +#define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF + + +/* Definitions for peripheral PSU_FPD_GPV */ +#define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000 +#define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF + + +/* Definitions for peripheral PSU_FPD_SLCR */ +#define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000 +#define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF + + +/* Definitions for peripheral PSU_FPD_SLCR_SECURE */ +#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000 +#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF + + +/* Definitions for peripheral PSU_FPD_XMPU_CFG */ +#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000 +#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF + + +/* Definitions for peripheral PSU_FPD_XMPU_SINK */ +#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000 +#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF + + +/* Definitions for peripheral PSU_GPU */ +#define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000 +#define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF + + +/* Definitions for peripheral PSU_IOU_SCNTR */ +#define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000 +#define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF + + +/* Definitions for peripheral PSU_IOU_SCNTRS */ +#define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000 +#define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF + + +/* Definitions for peripheral PSU_IOUSECURE_SLCR */ +#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000 +#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF + + +/* Definitions for peripheral PSU_IOUSLCR_0 */ +#define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000 +#define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF + + +/* Definitions for peripheral PSU_LPD_SLCR */ +#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000 +#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF + + +/* Definitions for peripheral PSU_LPD_SLCR_SECURE */ +#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000 +#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF + + +/* Definitions for peripheral PSU_LPD_XPPU */ +#define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000 +#define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF + + +/* Definitions for peripheral PSU_LPD_XPPU_SINK */ +#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000 +#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF + + +/* Definitions for peripheral PSU_MBISTJTAG */ +#define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000 +#define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF + + +/* Definitions for peripheral PSU_MESSAGE_BUFFERS */ +#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000 +#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF + + +/* Definitions for peripheral PSU_OCM */ +#define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000 +#define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF + + +/* Definitions for peripheral PSU_OCM_RAM_0 */ +#define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000 +#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Definitions for peripheral PSU_OCM_XMPU_CFG */ +#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000 +#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF + + +/* Definitions for peripheral PSU_PMU_GLOBAL_0 */ +#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000 +#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF + + +/* Definitions for peripheral PSU_QSPI_LINEAR_0 */ +#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000 +#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF + + +/* Definitions for peripheral PSU_R5_0_ATCM */ +#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000 +#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF + + +/* Definitions for peripheral PSU_R5_0_BTCM */ +#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000 +#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF + + +/* Definitions for peripheral PSU_R5_DDR_0 */ +#define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000 +#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF + + +/* Definitions for peripheral PSU_R5_TCM_RAM_0 */ +#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000 +#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF + + +/* Definitions for peripheral PSU_RPU */ +#define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000 +#define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF + + +/* Definitions for peripheral PSU_RSA */ +#define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000 +#define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF + + +/* Definitions for peripheral PSU_SERDES */ +#define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000 +#define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF + + +/* Definitions for peripheral PSU_SIOU */ +#define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000 +#define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF + + +/* Definitions for peripheral PSU_SMMU_GPV */ +#define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000 +#define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF + + +/* Definitions for peripheral PSU_SMMU_REG */ +#define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000 +#define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF + + +/* Definitions for peripheral PSU_USB_0 */ +#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000 +#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF + + +/******************************************************************/ + +/* Definitions for driver GPIOPS */ +#define XPAR_XGPIOPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_GPIO_0 */ +#define XPAR_PSU_GPIO_0_DEVICE_ID 0 +#define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000 +#define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_GPIO_0 */ +#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID +#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000 +#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF + + +/******************************************************************/ + +/* Definitions for driver IICPS */ +#define XPAR_XIICPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_I2C_1 */ +#define XPAR_PSU_I2C_1_DEVICE_ID 0 +#define XPAR_PSU_I2C_1_BASEADDR 0xFF030000 +#define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF +#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99999001 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_I2C_1 */ +#define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID +#define XPAR_XIICPS_0_BASEADDR 0xFF030000 +#define XPAR_XIICPS_0_HIGHADDR 0xFF03FFFF +#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99999001 + + +/******************************************************************/ + +/* Definition for input Clock */ +#define XPAR_PSU_I2C_1_REF_CLK I2C1_REF +#define XPAR_XIPIPSU_NUM_INSTANCES 1U + +/* Parameter definitions for peripheral psu_ipi_1 */ +#define XPAR_PSU_IPI_1_DEVICE_ID 0U +#define XPAR_PSU_IPI_1_S_AXI_BASEADDR 0xFF310000U +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U +#define XPAR_PSU_IPI_1_INT_ID 65U + +/* Canonical definitions for peripheral psu_ipi_1 */ +#define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID +#define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_1_S_AXI_BASEADDR +#define XPAR_XIPIPSU_0_BIT_MASK XPAR_PSU_IPI_1_BIT_MASK +#define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX +#define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID + +#define XPAR_XIPIPSU_NUM_TARGETS 7U + +#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001U +#define XPAR_PSU_IPI_0_BUFFER_INDEX 2U +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U +#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200U +#define XPAR_PSU_IPI_2_BUFFER_INDEX 1U +#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000U +#define XPAR_PSU_IPI_3_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000U +#define XPAR_PSU_IPI_4_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000U +#define XPAR_PSU_IPI_5_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000U +#define XPAR_PSU_IPI_6_BUFFER_INDEX 7U +/* Target List for referring to processor IPI Targets */ + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0U + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0U + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0U + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0U + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1U + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_2_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2U + +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3U +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4U +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5U +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6U + +/* Definitions for driver PCIEPSU */ +#define XPAR_XPCIEPSU_NUM_INSTANCES 6 + +/* Definitions for peripheral PSU_PCIE */ +#define XPAR_PSU_PCIE_DEVICE_ID 0 +#define XPAR_PSU_PCIE_BASEADDR 0xFD0E0000 +#define XPAR_PSU_PCIE_HIGHADDR 0xFD0EFFFF + + +/* Definitions for peripheral PSU_PCIE_ATTRIB_0 */ +#define XPAR_PSU_PCIE_ATTRIB_0_DEVICE_ID 1 +#define XPAR_PSU_PCIE_ATTRIB_0_BASEADDR 0xFD480000 +#define XPAR_PSU_PCIE_ATTRIB_0_HIGHADDR 0xFD48FFFF + + +/* Definitions for peripheral PSU_PCIE_DMA */ +#define XPAR_PSU_PCIE_DMA_DEVICE_ID 2 +#define XPAR_PSU_PCIE_DMA_BASEADDR 0xFD0F0000 +#define XPAR_PSU_PCIE_DMA_HIGHADDR 0xFD0FFFFF + + +/* Definitions for peripheral PSU_PCIE_HIGH1 */ +#define XPAR_PSU_PCIE_HIGH1_DEVICE_ID 3 +#define XPAR_PSU_PCIE_HIGH1_BASEADDR 0x600000000 +#define XPAR_PSU_PCIE_HIGH1_HIGHADDR 0x7FFFFFFFF + + +/* Definitions for peripheral PSU_PCIE_HIGH2 */ +#define XPAR_PSU_PCIE_HIGH2_DEVICE_ID 4 +#define XPAR_PSU_PCIE_HIGH2_BASEADDR 0x8000000000 +#define XPAR_PSU_PCIE_HIGH2_HIGHADDR 0xBFFFFFFFFF + + +/* Definitions for peripheral PSU_PCIE_LOW */ +#define XPAR_PSU_PCIE_LOW_DEVICE_ID 5 +#define XPAR_PSU_PCIE_LOW_BASEADDR 0xE0000000 +#define XPAR_PSU_PCIE_LOW_HIGHADDR 0xEFFFFFFF + + +/******************************************************************/ + +#define XPAR_PSU_PCIE_PCIE_MODE 0x1 + +/* Canonical definitions for peripheral PSU_PCIE */ +#define XPAR_XPCIEPSU_0_DEVICE_ID XPAR_PSU_PCIE_DEVICE_ID +#define XPAR_XPCIEPSU_0_BASEADDR 0xFD0E0000 +#define XPAR_XPCIEPSU_0_HIGHADDR 0xFD0EFFFF +#define XPAR_XPCIEPSU_0_PCIE_MODE Root Port + +/* Canonical definitions for peripheral PSU_PCIE_ATTRIB_0 */ +#define XPAR_XPCIEPSU_1_DEVICE_ID XPAR_PSU_PCIE_ATTRIB_0_DEVICE_ID +#define XPAR_XPCIEPSU_1_BASEADDR 0xFD480000 +#define XPAR_XPCIEPSU_1_HIGHADDR 0xFD48FFFF +#define XPAR_XPCIEPSU_1_PCIE_MODE 0 + +/* Canonical definitions for peripheral PSU_PCIE_DMA */ +#define XPAR_XPCIEPSU_2_DEVICE_ID XPAR_PSU_PCIE_DMA_DEVICE_ID +#define XPAR_XPCIEPSU_2_BASEADDR 0xFD0F0000 +#define XPAR_XPCIEPSU_2_HIGHADDR 0xFD0FFFFF +#define XPAR_XPCIEPSU_2_PCIE_MODE 0 + +/* Canonical definitions for peripheral PSU_PCIE_HIGH1 */ +#define XPAR_XPCIEPSU_3_DEVICE_ID XPAR_PSU_PCIE_HIGH1_DEVICE_ID +#define XPAR_XPCIEPSU_3_BASEADDR 0x600000000 +#define XPAR_XPCIEPSU_3_HIGHADDR 0x7FFFFFFFF +#define XPAR_XPCIEPSU_3_PCIE_MODE 0 + +/* Canonical definitions for peripheral PSU_PCIE_HIGH2 */ +#define XPAR_XPCIEPSU_4_DEVICE_ID XPAR_PSU_PCIE_HIGH2_DEVICE_ID +#define XPAR_XPCIEPSU_4_BASEADDR 0x8000000000 +#define XPAR_XPCIEPSU_4_HIGHADDR 0xBFFFFFFFFF +#define XPAR_XPCIEPSU_4_PCIE_MODE 0 + +/* Canonical definitions for peripheral PSU_PCIE_LOW */ +#define XPAR_XPCIEPSU_5_DEVICE_ID XPAR_PSU_PCIE_LOW_DEVICE_ID +#define XPAR_XPCIEPSU_5_BASEADDR 0xE0000000 +#define XPAR_XPCIEPSU_5_HIGHADDR 0xEFFFFFFF +#define XPAR_XPCIEPSU_5_PCIE_MODE 0 + + +/******************************************************************/ + +/* Definitions for driver QSPIPSU */ +#define XPAR_XQSPIPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_QSPI_0 */ +#define XPAR_PSU_QSPI_0_DEVICE_ID 0 +#define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000 +#define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF +#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 299997009 +#define XPAR_PSU_QSPI_0_QSPI_MODE 0 +#define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_QSPI_0_REF_CLK 0xff +/* Canonical definitions for peripheral PSU_QSPI_0 */ +#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID +#define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000 +#define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF +#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 299997009 +#define XPAR_XQSPIPSU_0_QSPI_MODE 0 +#define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2 +#define XPAR_XQSPIPSU_0_IS_CACHE_COHERENT 0 + + +/******************************************************************/ + +/* Definitions for driver RESETPS and CLOCKPS */ +#define XPAR_XCRPSU_NUM_INSTANCES 1U + +/* Definitions for peripheral PSU_CR_0 */ +#define XPAR_PSU_CR_DEVICE_ID 0 + +/******************************************************************/ + +/* Definitions for peripheral PSU_CRF_APB */ +#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000 +#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CR_0 */ +#define XPAR_XCRPSU_0_DEVICE_ID 0 + +/******************************************************************/ + + +/* Definitions for peripheral PSU_PMU_IOMODULE */ +#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000 +#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF + + +/* Definitions for peripheral PSU_LPD_SLCR */ +#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000 +#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF + + +/******************************************************************/ + +/* Definitions for driver RTCPSU */ +#define XPAR_XRTCPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_RTC */ +#define XPAR_PSU_RTC_DEVICE_ID 0 +#define XPAR_PSU_RTC_BASEADDR 0xFFA60000 +#define XPAR_PSU_RTC_HIGHADDR 0xFFA6FFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_RTC */ +#define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSU_RTC_DEVICE_ID +#define XPAR_XRTCPSU_0_BASEADDR 0xFFA60000 +#define XPAR_XRTCPSU_0_HIGHADDR 0xFFA6FFFF + + +/******************************************************************/ + +/* Definitions for driver SCUGIC */ +#define XPAR_XSCUGIC_NUM_INSTANCES 1U + +/* Definitions for peripheral PSU_RCPU_GIC */ +#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0U +#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000U +#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFFU +#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000U + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_RCPU_GIC */ +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000U + + +/******************************************************************/ + +/* Definitions for driver SDPS */ +#define XPAR_XSDPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_SD_0 */ +#define XPAR_PSU_SD_0_DEVICE_ID 0 +#define XPAR_PSU_SD_0_BASEADDR 0xFF160000 +#define XPAR_PSU_SD_0_HIGHADDR 0xFF16FFFF +#define XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ 187498123 +#define XPAR_PSU_SD_0_HAS_CD 0 +#define XPAR_PSU_SD_0_HAS_WP 0 +#define XPAR_PSU_SD_0_BUS_WIDTH 8 +#define XPAR_PSU_SD_0_MIO_BANK 0 +#define XPAR_PSU_SD_0_HAS_EMIO 0 + + +/* Definitions for peripheral PSU_SD_1 */ +#define XPAR_PSU_SD_1_DEVICE_ID 1 +#define XPAR_PSU_SD_1_BASEADDR 0xFF170000 +#define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF +#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187498123 +#define XPAR_PSU_SD_1_HAS_CD 1 +#define XPAR_PSU_SD_1_HAS_WP 0 +#define XPAR_PSU_SD_1_BUS_WIDTH 4 +#define XPAR_PSU_SD_1_MIO_BANK 1 +#define XPAR_PSU_SD_1_HAS_EMIO 0 + + +/******************************************************************/ + +#define XPAR_PSU_SD_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_SD_0_REF_CLK 0xff +#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_SD_1_REF_CLK 0xff +/* Canonical definitions for peripheral PSU_SD_0 */ +#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_0_DEVICE_ID +#define XPAR_XSDPS_0_BASEADDR 0xFF160000 +#define XPAR_XSDPS_0_HIGHADDR 0xFF16FFFF +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187498123 +#define XPAR_XSDPS_0_HAS_CD 0 +#define XPAR_XSDPS_0_HAS_WP 0 +#define XPAR_XSDPS_0_BUS_WIDTH 8 +#define XPAR_XSDPS_0_MIO_BANK 0 +#define XPAR_XSDPS_0_HAS_EMIO 0 +#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0 + +/* Canonical definitions for peripheral PSU_SD_1 */ +#define XPAR_XSDPS_1_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID +#define XPAR_XSDPS_1_BASEADDR 0xFF170000 +#define XPAR_XSDPS_1_HIGHADDR 0xFF17FFFF +#define XPAR_XSDPS_1_SDIO_CLK_FREQ_HZ 187498123 +#define XPAR_XSDPS_1_HAS_CD 1 +#define XPAR_XSDPS_1_HAS_WP 0 +#define XPAR_XSDPS_1_BUS_WIDTH 4 +#define XPAR_XSDPS_1_MIO_BANK 1 +#define XPAR_XSDPS_1_HAS_EMIO 0 +#define XPAR_XSDPS_1_IS_CACHE_COHERENT 0 + + +/******************************************************************/ + +/* Definitions for driver SYSMONPSU */ +#define XPAR_XSYSMONPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_AMS */ +#define XPAR_PSU_AMS_DEVICE_ID 0 +#define XPAR_PSU_AMS_BASEADDR 0xFFA50000 +#define XPAR_PSU_AMS_HIGHADDR 0xFFA5FFFF + + +/******************************************************************/ + +#define XPAR_PSU_AMS_REF_FREQMHZ 49.999500 +/* Canonical definitions for peripheral PSU_AMS */ +#define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID +#define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000 +#define XPAR_XSYSMONPSU_0_HIGHADDR 0xFFA5FFFF + + +/******************************************************************/ + +#define XPAR_XSYSMONPSU_0_REF_FREQMHZ 49.999500 +/* Definitions for driver TTCPS */ +#define XPAR_XTTCPS_NUM_INSTANCES 12U + +/* Definitions for peripheral PSU_TTC_0 */ +#define XPAR_PSU_TTC_0_DEVICE_ID 0U +#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U +#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_1_DEVICE_ID 1U +#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U +#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_2_DEVICE_ID 2U +#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U +#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U + + +/* Definitions for peripheral PSU_TTC_1 */ +#define XPAR_PSU_TTC_3_DEVICE_ID 3U +#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U +#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_4_DEVICE_ID 4U +#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U +#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_5_DEVICE_ID 5U +#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U +#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U + + +/* Definitions for peripheral PSU_TTC_2 */ +#define XPAR_PSU_TTC_6_DEVICE_ID 6U +#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U +#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_7_DEVICE_ID 7U +#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U +#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_8_DEVICE_ID 8U +#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U +#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U + + +/* Definitions for peripheral PSU_TTC_3 */ +#define XPAR_PSU_TTC_9_DEVICE_ID 9U +#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U +#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_10_DEVICE_ID 10U +#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U +#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_11_DEVICE_ID 11U +#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U +#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_TTC_0 */ +#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID +#define XPAR_XTTCPS_0_BASEADDR 0xFF110000U +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID +#define XPAR_XTTCPS_1_BASEADDR 0xFF110004U +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID +#define XPAR_XTTCPS_2_BASEADDR 0xFF110008U +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U + +/* Canonical definitions for peripheral PSU_TTC_1 */ +#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID +#define XPAR_XTTCPS_3_BASEADDR 0xFF120000U +#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID +#define XPAR_XTTCPS_4_BASEADDR 0xFF120004U +#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID +#define XPAR_XTTCPS_5_BASEADDR 0xFF120008U +#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U + +/* Canonical definitions for peripheral PSU_TTC_2 */ +#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID +#define XPAR_XTTCPS_6_BASEADDR 0xFF130000U +#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID +#define XPAR_XTTCPS_7_BASEADDR 0xFF130004U +#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID +#define XPAR_XTTCPS_8_BASEADDR 0xFF130008U +#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U + +/* Canonical definitions for peripheral PSU_TTC_3 */ +#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID +#define XPAR_XTTCPS_9_BASEADDR 0xFF140000U +#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID +#define XPAR_XTTCPS_10_BASEADDR 0xFF140004U +#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID +#define XPAR_XTTCPS_11_BASEADDR 0xFF140008U +#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U + + +/******************************************************************/ + +/* Definitions for driver UARTPS */ +#define XPAR_XUARTPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_UART_0 */ +#define XPAR_PSU_UART_0_DEVICE_ID 0 +#define XPAR_PSU_UART_0_BASEADDR 0xFF000000 +#define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF +#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99999001 +#define XPAR_PSU_UART_0_HAS_MODEM 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_UART_0 */ +#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID +#define XPAR_XUARTPS_0_BASEADDR 0xFF000000 +#define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99999001 +#define XPAR_XUARTPS_0_HAS_MODEM 0 + + +/******************************************************************/ + +/* Definition for input Clock */ +#define XPAR_PSU_UART_0_REF_CLK UART0_REF +/* Definitions for driver USBPSU */ +#define XPAR_XUSBPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_USB_XHCI_0 */ +#define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0 +#define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000 +#define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF + + +/******************************************************************/ + +#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_USB_XHCI_0_REF_CLK 0xff +#define XPAR_PSU_USB_XHCI_0_SUPER_SPEED 1 +/* Canonical definitions for peripheral PSU_USB_XHCI_0 */ +#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID +#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000 +#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF + + +/******************************************************************/ + +/* Definitions for driver ZDMA */ +#define XPAR_XZDMA_NUM_INSTANCES 16 + +/* Definitions for peripheral PSU_ADMA_0 */ +#define XPAR_PSU_ADMA_0_DEVICE_ID 0 +#define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000 +#define XPAR_PSU_ADMA_0_DMA_MODE 1 +#define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF +#define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_1 */ +#define XPAR_PSU_ADMA_1_DEVICE_ID 1 +#define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000 +#define XPAR_PSU_ADMA_1_DMA_MODE 1 +#define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF +#define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_2 */ +#define XPAR_PSU_ADMA_2_DEVICE_ID 2 +#define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000 +#define XPAR_PSU_ADMA_2_DMA_MODE 1 +#define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF +#define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_3 */ +#define XPAR_PSU_ADMA_3_DEVICE_ID 3 +#define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000 +#define XPAR_PSU_ADMA_3_DMA_MODE 1 +#define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF +#define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_4 */ +#define XPAR_PSU_ADMA_4_DEVICE_ID 4 +#define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000 +#define XPAR_PSU_ADMA_4_DMA_MODE 1 +#define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF +#define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_5 */ +#define XPAR_PSU_ADMA_5_DEVICE_ID 5 +#define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000 +#define XPAR_PSU_ADMA_5_DMA_MODE 1 +#define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF +#define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_6 */ +#define XPAR_PSU_ADMA_6_DEVICE_ID 6 +#define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000 +#define XPAR_PSU_ADMA_6_DMA_MODE 1 +#define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF +#define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_7 */ +#define XPAR_PSU_ADMA_7_DEVICE_ID 7 +#define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000 +#define XPAR_PSU_ADMA_7_DMA_MODE 1 +#define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF +#define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_0 */ +#define XPAR_PSU_GDMA_0_DEVICE_ID 8 +#define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000 +#define XPAR_PSU_GDMA_0_DMA_MODE 0 +#define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF +#define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_1 */ +#define XPAR_PSU_GDMA_1_DEVICE_ID 9 +#define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000 +#define XPAR_PSU_GDMA_1_DMA_MODE 0 +#define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF +#define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_2 */ +#define XPAR_PSU_GDMA_2_DEVICE_ID 10 +#define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000 +#define XPAR_PSU_GDMA_2_DMA_MODE 0 +#define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF +#define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_3 */ +#define XPAR_PSU_GDMA_3_DEVICE_ID 11 +#define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000 +#define XPAR_PSU_GDMA_3_DMA_MODE 0 +#define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF +#define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_4 */ +#define XPAR_PSU_GDMA_4_DEVICE_ID 12 +#define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000 +#define XPAR_PSU_GDMA_4_DMA_MODE 0 +#define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF +#define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_5 */ +#define XPAR_PSU_GDMA_5_DEVICE_ID 13 +#define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000 +#define XPAR_PSU_GDMA_5_DMA_MODE 0 +#define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF +#define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_6 */ +#define XPAR_PSU_GDMA_6_DEVICE_ID 14 +#define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000 +#define XPAR_PSU_GDMA_6_DMA_MODE 0 +#define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF +#define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_7 */ +#define XPAR_PSU_GDMA_7_DEVICE_ID 15 +#define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000 +#define XPAR_PSU_GDMA_7_DMA_MODE 0 +#define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF +#define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +#define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PSU_ADMA_0 */ +#define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID +#define XPAR_XZDMA_0_BASEADDR 0xFFA80000 +#define XPAR_XZDMA_0_DMA_MODE 1 +#define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF +#define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_1 */ +#define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID +#define XPAR_XZDMA_1_BASEADDR 0xFFA90000 +#define XPAR_XZDMA_1_DMA_MODE 1 +#define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF +#define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_2 */ +#define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID +#define XPAR_XZDMA_2_BASEADDR 0xFFAA0000 +#define XPAR_XZDMA_2_DMA_MODE 1 +#define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF +#define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_3 */ +#define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID +#define XPAR_XZDMA_3_BASEADDR 0xFFAB0000 +#define XPAR_XZDMA_3_DMA_MODE 1 +#define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF +#define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_4 */ +#define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID +#define XPAR_XZDMA_4_BASEADDR 0xFFAC0000 +#define XPAR_XZDMA_4_DMA_MODE 1 +#define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF +#define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_5 */ +#define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID +#define XPAR_XZDMA_5_BASEADDR 0xFFAD0000 +#define XPAR_XZDMA_5_DMA_MODE 1 +#define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF +#define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_6 */ +#define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID +#define XPAR_XZDMA_6_BASEADDR 0xFFAE0000 +#define XPAR_XZDMA_6_DMA_MODE 1 +#define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF +#define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_7 */ +#define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID +#define XPAR_XZDMA_7_BASEADDR 0xFFAF0000 +#define XPAR_XZDMA_7_DMA_MODE 1 +#define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF +#define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_0 */ +#define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID +#define XPAR_XZDMA_8_BASEADDR 0xFD500000 +#define XPAR_XZDMA_8_DMA_MODE 0 +#define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF +#define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_1 */ +#define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID +#define XPAR_XZDMA_9_BASEADDR 0xFD510000 +#define XPAR_XZDMA_9_DMA_MODE 0 +#define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF +#define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_2 */ +#define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID +#define XPAR_XZDMA_10_BASEADDR 0xFD520000 +#define XPAR_XZDMA_10_DMA_MODE 0 +#define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF +#define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_3 */ +#define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID +#define XPAR_XZDMA_11_BASEADDR 0xFD530000 +#define XPAR_XZDMA_11_DMA_MODE 0 +#define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF +#define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_4 */ +#define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID +#define XPAR_XZDMA_12_BASEADDR 0xFD540000 +#define XPAR_XZDMA_12_DMA_MODE 0 +#define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF +#define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_5 */ +#define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID +#define XPAR_XZDMA_13_BASEADDR 0xFD550000 +#define XPAR_XZDMA_13_DMA_MODE 0 +#define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF +#define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_6 */ +#define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID +#define XPAR_XZDMA_14_BASEADDR 0xFD560000 +#define XPAR_XZDMA_14_DMA_MODE 0 +#define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF +#define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_7 */ +#define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID +#define XPAR_XZDMA_15_BASEADDR 0xFD570000 +#define XPAR_XZDMA_15_DMA_MODE 0 +#define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF +#define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +#endif /* end of protection macro */ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h new file mode 100644 index 0000000000..a3af88c450 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h @@ -0,0 +1,325 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* @addtogroup r5_peripheral_definitions Cortex R5 peripheral definitions +* +* The xparameters_ps.h file contains the canonical definitions and constant +* declarations for peripherals within hardblock, attached to the ARM Cortex R5 +* core. These definitions can be used by drivers or applications to access the +* peripherals. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp  	02/29/14 Initial version
+* 6.0   mus     08/18/16 Defined ARMR5 flag
+* 7.2	pm	03/25/20 Add wakeup Interrupt Id for usbpsu controller
+*
+* +******************************************************************************/ + +#ifndef XPARAMETERS_PS_H_ +#define XPARAMETERS_PS_H_ + +#ifndef ARMR5 +#define ARMR5 ARMR5 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID +#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID +#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_CSU_WDT_INT_ID +#define XPAR_XWDTPS_1_INTR XPS_LPD_SWDT_INT_ID +#define XPAR_XWDTPS_2_INTR XPS_FPD_SWDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID +#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID +#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID +#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID +#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID +#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID +#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID +#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID +#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID +#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID +#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID +#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID +#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID +#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID +#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID +#define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID +#define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID +#define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID +#define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID +#define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID +#define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID +#define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID +#define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID +#define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID +#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID +#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID +#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID +#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID +#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID +#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID +#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID +#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID +#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID +#define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID +#define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID +#define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID +#define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID +#define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID +#define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID +#define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID +#define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID +#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID +#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID +#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID +#define XPAR_XUSBPS_0_WAKE_INTR XPS_USB3_0_WAKE_INT_ID +#define XPAR_XUSBPS_1_WAKE_INTR XPS_USB3_1_WAKE_INT_ID +#define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID +#define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID +#define XPAR_XAPMPS_0_INTR XPS_APM0_INT_ID +#define XPAR_XAPMPS_1_INTR XPS_APM1_INT_ID +#define XPAR_XAPMPS_2_INTR XPS_APM2_INT_ID +#define XPAR_XAPMPS_5_INTR XPS_APM5_INT_ID +#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for bacwards compatibility + */ + +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U +#define XPS_SCU_PERIPH_BASE 0xF9000000U + + +/* Shared Peripheral Interrupts (SPI) */ +#define XPS_FPGA0_INT_ID 121U +#define XPS_FPGA1_INT_ID 122U +#define XPS_FPGA2_INT_ID 123U +#define XPS_FPGA3_INT_ID 124U +#define XPS_FPGA4_INT_ID 125U +#define XPS_FPGA5_INT_ID 126U +#define XPS_FPGA6_INT_ID 127U +#define XPS_FPGA7_INT_ID 128U +#define XPS_FPGA8_INT_ID 136U +#define XPS_FPGA9_INT_ID 137U +#define XPS_FPGA10_INT_ID 138U +#define XPS_FPGA11_INT_ID 139U +#define XPS_FPGA12_INT_ID 140U +#define XPS_FPGA13_INT_ID 141U +#define XPS_FPGA14_INT_ID 142U +#define XPS_FPGA15_INT_ID 143U + +/* Updated Interrupt-IDs */ +#define XPS_OCMINTR_INT_ID (10U + 32U) +#define XPS_NAND_INT_ID (14U + 32U) +#define XPS_QSPI_INT_ID (15U + 32U) +#define XPS_GPIO_INT_ID (16U + 32U) +#define XPS_I2C0_INT_ID (17U + 32U) +#define XPS_I2C1_INT_ID (18U + 32U) +#define XPS_SPI0_INT_ID (19U + 32U) +#define XPS_SPI1_INT_ID (20U + 32U) +#define XPS_UART0_INT_ID (21U + 32U) +#define XPS_UART1_INT_ID (22U + 32U) +#define XPS_CAN0_INT_ID (23U + 32U) +#define XPS_CAN1_INT_ID (24U + 32U) +#define XPS_RTC_ALARM_INT_ID (26U + 32U) +#define XPS_RTC_SEC_INT_ID (27U + 32U) +#define XPS_LPD_SWDT_INT_ID (52U + 32U) +#define XPS_CSU_WDT_INT_ID (53U + 32U) +#define XPS_FPD_SWDT_INT_ID (113U + 32U) +#define XPS_TTC0_0_INT_ID (36U + 32U) +#define XPS_TTC0_1_INT_ID (37U + 32U) +#define XPS_TTC0_2_INT_ID (38U + 32U) +#define XPS_TTC1_0_INT_ID (39U + 32U) +#define XPS_TTC1_1_INT_ID (40U + 32U) +#define XPS_TTC1_2_INT_ID (41U + 32U) +#define XPS_TTC2_0_INT_ID (42U + 32U) +#define XPS_TTC2_1_INT_ID (43U + 32U) +#define XPS_TTC2_2_INT_ID (44U + 32U) +#define XPS_TTC3_0_INT_ID (45U + 32U) +#define XPS_TTC3_1_INT_ID (46U + 32U) +#define XPS_TTC3_2_INT_ID (47U + 32U) +#define XPS_SDIO0_INT_ID (48U + 32U) +#define XPS_SDIO1_INT_ID (49U + 32U) +#define XPS_AMS_INT_ID (56U + 32U) +#define XPS_GEM0_INT_ID (57U + 32U) +#define XPS_GEM0_WAKE_INT_ID (58U + 32U) +#define XPS_GEM1_INT_ID (59U + 32U) +#define XPS_GEM1_WAKE_INT_ID (60U + 32U) +#define XPS_GEM2_INT_ID (61U + 32U) +#define XPS_GEM2_WAKE_INT_ID (62U + 32U) +#define XPS_GEM3_INT_ID (63U + 32U) +#define XPS_GEM3_WAKE_INT_ID (64U + 32U) +#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U) +#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U) +#define XPS_USB3_0_WAKE_INT_ID (75U + 32U) +#define XPS_USB3_1_WAKE_INT_ID (76U + 32U) +#define XPS_ADMA_CH0_INT_ID (77U + 32U) +#define XPS_ADMA_CH1_INT_ID (78U + 32U) +#define XPS_ADMA_CH2_INT_ID (79U + 32U) +#define XPS_ADMA_CH3_INT_ID (80U + 32U) +#define XPS_ADMA_CH4_INT_ID (81U + 32U) +#define XPS_ADMA_CH5_INT_ID (82U + 32U) +#define XPS_ADMA_CH6_INT_ID (83U + 32U) +#define XPS_ADMA_CH7_INT_ID (84U + 32U) +#define XPS_CSU_DMA_INT_ID (86U + 32U) +#define XPS_XMPU_LPD_INT_ID (88U + 32U) +#define XPS_ZDMA_CH0_INT_ID (124U + 32U) +#define XPS_ZDMA_CH1_INT_ID (125U + 32U) +#define XPS_ZDMA_CH2_INT_ID (126U + 32U) +#define XPS_ZDMA_CH3_INT_ID (127U + 32U) +#define XPS_ZDMA_CH4_INT_ID (128U + 32U) +#define XPS_ZDMA_CH5_INT_ID (129U + 32U) +#define XPS_ZDMA_CH6_INT_ID (130U + 32U) +#define XPS_ZDMA_CH7_INT_ID (131U + 32U) +#define XPS_XMPU_FPD_INT_ID (134U + 32U) +#define XPS_FPD_CCI_INT_ID (154U + 32U) +#define XPS_FPD_SMMU_INT_ID (155U + 32U) +#define XPS_APM0_INT_ID (123U + 32U) +#define XPS_APM1_INT_ID (25U + 32U) +#define XPS_APM2_INT_ID (25U + 32U) +#define XPS_APM5_INT_ID (123U + 32U) + +/* REDEFINES for TEST APP */ +#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID +#define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID +#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID +#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID +#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID +#define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID +#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID +#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_PSU_TTC_6_INTR XPS_TTC2_0_INT_ID +#define XPAR_PSU_TTC_7_INTR XPS_TTC2_1_INT_ID +#define XPAR_PSU_TTC_8_INTR XPS_TTC2_2_INT_ID +#define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID +#define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID +#define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID +#define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID + +#define XPAR_XADCPS_NUM_INSTANCES 1U +#define XPAR_XADCPS_0_DEVICE_ID 0U +#define XPAR_XADCPS_0_BASEADDR (0xF8007000U) +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibility */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ +/** +* @} End of "addtogroup r5_peripheral_definitions". +*/ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h new file mode 100644 index 0000000000..534785e134 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h @@ -0,0 +1,64 @@ +#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ +#define XPLATFORM_INFO_H /* by using protection macros */ + +#include "xil_types.h" +#include "xparameters.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (versal) +#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U +#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U +#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \ + XPAR_PMC_TAP_VERSION_OFFSET) +#else +#define XPAR_CSU_BASEADDR 0xFFCA0000U +#define XPAR_CSU_VER_OFFSET 0x00000044U +#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \ + XPAR_CSU_VER_OFFSET) +#endif +#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0 +#define XPLAT_ZYNQ_ULTRA_MP 0x1 +#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2 +#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3 +#define XPLAT_ZYNQ 0x4 +#define XPLAT_MICROBLAZE 0x5 +#define XPLAT_VERSAL 0x6U + +#define XPS_VERSION_1 0x0 +#define XPS_VERSION_2 0x1 +#define XPLAT_INFO_MASK (0xF) + +#if defined (versal) +#define XPS_VERSION_INFO_MASK 0xFF00U +#define XPS_VERSION_INFO_SHIFT 0x8U +#define XPLAT_INFO_SHIFT 0x18U +#else +#define XPS_VERSION_INFO_MASK (0xF) +#define XPS_VERSION_INFO_SHIFT 0x0U +#define XPLAT_INFO_SHIFT 0xCU +#endif + +static INLINE u32 XGetPlatform_Info() +{ +#if defined (versal) + return XPLAT_VERSAL; +#elif defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + return XPLAT_ZYNQ_ULTRA_MP; +#elif (__microblaze__) + return XPLAT_MICROBLAZE; +#else + return XPLAT_ZYNQ; +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_platform_info". +*/ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h new file mode 100644 index 0000000000..035aed445a --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h @@ -0,0 +1,513 @@ +/****************************************************************************** +* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* @addtogroup common_status_codes Xilinx® software status codes +* +* The xstatus.h file contains the Xilinx® software status codes.These codes are +* used throughout the Xilinx device drivers. +* +* @{ +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ +/** +@name Common Status Codes for All Device Drivers +@{ +*/ +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /*!< An error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /*!< An error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /*!< The device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /*!< There was no data available */ +#define XST_REGISTER_ERROR 14L /*!< A register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /*!< The device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */ +#define XST_NO_CALLBACK 18L /*!< A callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /*!< Device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /*!< Device is busy */ +#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /*!< Used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /*!< Used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /*!< Driver defined error */ +#define XST_RECV_ERROR 27L /*!< Generic receive error */ +#define XST_SEND_ERROR 28L /*!< Generic transmit error */ +#define XST_NOT_ENABLED 29L /*!< A requested service is not + available because it has not + been enabled */ +#define XST_NO_ACCESS 30L /* Generic access error */ +#define XST_TIMEOUT 31L /*!< Event timeout occurred */ + +/** @} */ +/***************** Utility Component statuses 401 - 500 *********************/ +/** +@name Utility Component Status Codes 401 - 500 +@{ +*/ +#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */ + +/** @} */ +/***************** Common Components statuses 501 - 1000 *********************/ +/** +@name Packet Fifo Status Codes 501 - 510 +@{ +*/ +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting + * empty and full simultaneously + */ +/** @} */ +/** +@name DMA Status Codes 511 - 530 +@{ +*/ +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been + put into the scatter gather + list to be committed */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor + error */ +/** @} */ +/** +@name IPIF Status Codes Codes 531 - 550 +@{ +*/ +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /*!< Generic ipif error */ +/** @} */ + +/****************** Device specific statuses 1001 - 4095 *********************/ +/** +@name Ethernet Status Codes 1001 - 1050 +@{ +*/ +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */ +#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late + * collision on polled send */ +/** @} */ +/** +@name UART Status Codes 1051 - 1075 +@{ +*/ +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/** @} */ +/** +@name IIC Status Codes 1076 - 1100 +@{ +*/ +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */ +#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */ +#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */ +/** @} */ +/** +@name ATMC Status Codes 1101 - 1125 +@{ +*/ +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ +/** @} */ +/** +@name Flash Status Codes 1126 - 1150 +@{ +*/ +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */ +/** @} */ +/** +@name SPI Status Codes 1151 - 1175 +@{ +*/ +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */ +#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the + device for status */ +/** @} */ +/** +@name OPB Arbiter Status Codes 1176 - 1200 +@{ +*/ +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ +/** @} */ +/** +@name INTC Status Codes 1201 - 1225 +@{ +*/ +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */ +/** @} */ +/** +@name TmrCtr Status Codes 1226 - 1250 +@{ +*/ +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */ +/** @} */ +/** +@name WdtTb Status Codes 1251 - 1275 +@{ +*/ +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L +/** @} */ +/** +@name PlbArb status Codes 1276 - 1300 +@{ +*/ +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L +/** @} */ +/** +@name Plb2Opb Status Codes 1301 - 1325 +@{ +*/ +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L +/** @} */ +/** +@name Opb2Plb Status 1326 - 1350 +@{ +*/ +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L +/** @} */ +/** +@name SysAce Status Codes 1351 - 1360 +@{ +*/ +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */ +/** @} */ +/** +@name PCI Bridge Status Codes 1361 - 1375 +@{ +*/ +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L +/** @} */ +/** +@name FlexRay Constants 1400 - 1409 +@{ +*/ +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 +/** @} */ +/** +@name USB constants 1410 - 1420 +@{ +*/ +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 +/** @} */ +/** +@name HWICAP constants 1421 - 1429 +@{ +*/ +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + +/** @} */ +/** +@name AXI VDMA constants 1430 - 1440 +@{ +*/ +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 +/** @} */ +/** +@name NAND Flash Status Codes 1441 - 1459 +@{ +*/ +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /*!< Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /*!< Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /*!< Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected + */ +/** @} */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_status_codes". +*/ diff --git a/bsp/zynqmp-r5-axu4ev/drivers/board.c b/bsp/zynqmp-r5-axu4ev/drivers/board.c new file mode 100644 index 0000000000..ebd6680305 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/board.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-11-24 WangHuachen the first version + */ +#include +#include +#include + +#include "board.h" +#include "drv_timer.h" + +#define ITERS_PER_USEC (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4000000) +void rt_hw_us_delay(rt_uint32_t us) +{ + __asm__ __volatile__ ( + "push {r0,r1,r3} \n" + "mov r0, %[usec] \n" + "mov r1, %[iter] \n" + "1: \n" + "mov r3, r1 \n" + "2: \n" + "subs r3, r3, #0x1\n" + "bne 2b \n" + "subs r0, r0, #0x1 \n" + "bne 1b \n" + "pop {r0,r1,r3} \n" + ::[iter] "r" (ITERS_PER_USEC), [usec] "r" (us) + ); +} + +#ifdef RT_USING_CONSOLE + +#include "drv_uart.h" +void rt_hw_serial_putc(const char c) +{ + UART_Registers *uart = (UART_Registers *)XPAR_PSU_UART_0_BASEADDR; + if (c == '\n') + rt_hw_serial_putc('\r'); + + while ((uart->SR) & UART_SR_TXFULL); + uart->FIFO = c; +} +void rt_hw_console_output(const char *str) +{ + while (*str) + { + rt_hw_serial_putc(*str++); + } +} +#endif + +/** + * This function will initialize beaglebone board + */ +void rt_hw_board_init(void) +{ + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + /* initialize system heap */ +#ifdef RT_USING_HEAP + rt_system_heap_init(HEAP_BEGIN, HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/drivers/board.h b/bsp/zynqmp-r5-axu4ev/drivers/board.h new file mode 100644 index 0000000000..07c43b5dc1 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/board.h @@ -0,0 +1,18 @@ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "zynqmp-r5.h" + +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit) +#elif defined(__GNUC__) +extern int __bss_end; +#define HEAP_BEGIN ((void*)&__bss_end) +#endif + +#define HEAP_END (void*)(0x80000000) + +void rt_hw_board_init(); + +#endif \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c b/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c new file mode 100644 index 0000000000..6ecf7630cb --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-11-27 WangHuachen the first version + */ + +#include +#include +#include "drv_gpio.h" +#include "xgpiops.h" + +#define DBG_TAG "drv.gpio" +#define DBG_LVL DBG_INFO +#include "rtdbg.h" + +#define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID +static XGpioPs Gpio; /* The driver instance for GPIO Device. */ + +void xgpiops_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + switch (mode) + { + case PIN_MODE_OUTPUT: + case PIN_MODE_OUTPUT_OD: + XGpioPs_SetDirectionPin(&Gpio, pin, 1); + XGpioPs_SetOutputEnablePin(&Gpio, pin, 1); + break; + case PIN_MODE_INPUT: + case PIN_MODE_INPUT_PULLUP: + case PIN_MODE_INPUT_PULLDOWN: + XGpioPs_SetDirectionPin(&Gpio, pin, 0); + break; + default: + break; + } +} + +void xgpiops_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + if (pin >= Gpio.MaxPinNum) + return; + + XGpioPs_WritePin(&Gpio, pin, (value == PIN_HIGH)?1:0); +} + +int xgpiops_pin_read(rt_device_t dev, rt_base_t pin) +{ + if (pin >= Gpio.MaxPinNum) + return 0; + + int DataRead = XGpioPs_ReadPin(&Gpio, pin); + return DataRead?PIN_HIGH:PIN_LOW; +} + +const static struct rt_pin_ops _xgpiops_pin_ops = + { + xgpiops_pin_mode, + xgpiops_pin_write, + xgpiops_pin_read, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + XGpioPs_Config *ConfigPtr; + /* Initialize the GPIO driver. */ + ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID); + + if (XGpioPs_CfgInitialize(&Gpio, ConfigPtr, + ConfigPtr->BaseAddr) == XST_SUCCESS) + { + result = rt_device_pin_register("pin", &_xgpiops_pin_ops, RT_NULL); + return result; + } + return -RT_ERROR; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.h b/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.h new file mode 100644 index 0000000000..dc9bfca911 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.h @@ -0,0 +1,13 @@ +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c b/bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c new file mode 100644 index 0000000000..b0d6f375c8 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c @@ -0,0 +1,472 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-11-24 WangHuachen the first version + */ +#include +#include +#include +#include +#include + +#include +#include + +#include "drv_sdcard.h" +#include "xsdps_core.h" + +#define DBG_TAG "drv.sdcard" +#define DBG_LVL DBG_INFO +#include "rtdbg.h" + +#define FILE_SYSTEM_INTERFACE_SD +#define SD_CD_DELAY 10000U + +typedef rt_uint8_t BYTE; +typedef rt_uint32_t DWORD; +typedef unsigned int UINT; + +/* Status of Disk Functions */ +typedef rt_uint8_t DSTATUS; + +/* Results of Disk Functions */ +typedef enum +{ + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + +static DSTATUS Stat[2] = {STA_NOINIT, STA_NOINIT}; /* Disk status */ + +#ifdef FILE_SYSTEM_INTERFACE_SD +static XSdPs SdInstance[2]; +static u32 BaseAddress; +static u32 CardDetect; +static u32 WriteProtect; +static u32 SlotType[2]; +static u8 HostCntrlrVer[2]; +#endif + +static BYTE sdcard_drvnum = 0; +static struct rt_device sdcard_device; +static struct dfs_partition part; +static struct rt_mutex sd_lock[2]; + +static DSTATUS disk_status( + BYTE pdrv /* Drive number (0) */ +) +{ + DSTATUS s = Stat[pdrv]; +#ifdef FILE_SYSTEM_INTERFACE_SD + u32 StatusReg; + u32 DelayCount = 0; + + if (SdInstance[pdrv].Config.BaseAddress == (u32)0) + { +#ifdef XPAR_XSDPS_1_DEVICE_ID + if (pdrv == 1) + { + BaseAddress = XPAR_XSDPS_1_BASEADDR; + CardDetect = XPAR_XSDPS_1_HAS_CD; + WriteProtect = XPAR_XSDPS_1_HAS_WP; + } + else + { +#endif + BaseAddress = XPAR_XSDPS_0_BASEADDR; + CardDetect = XPAR_XSDPS_0_HAS_CD; + WriteProtect = XPAR_XSDPS_0_HAS_WP; +#ifdef XPAR_XSDPS_1_DEVICE_ID + } +#endif + HostCntrlrVer[pdrv] = (u8)(XSdPs_ReadReg16(BaseAddress, + XSDPS_HOST_CTRL_VER_OFFSET) & + XSDPS_HC_SPEC_VER_MASK); + if (HostCntrlrVer[pdrv] == XSDPS_HC_SPEC_V3) + { + SlotType[pdrv] = XSdPs_ReadReg(BaseAddress, + XSDPS_CAPS_OFFSET) & + XSDPS_CAPS_SLOT_TYPE_MASK; + } + else + { + SlotType[pdrv] = 0; + } + } + + /* If SD is not powered up then mark it as not initialized */ + if ((XSdPs_ReadReg8((u32)BaseAddress, XSDPS_POWER_CTRL_OFFSET) & + XSDPS_PC_BUS_PWR_MASK) == 0U) + { + s |= STA_NOINIT; + } + + StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress); + if (SlotType[pdrv] != XSDPS_CAPS_EMB_SLOT) + { + if (CardDetect) + { + while ((StatusReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) + { + if (DelayCount == 500U) + { + s = STA_NODISK | STA_NOINIT; + goto Label; + } + else + { + /* Wait for 10 msec */ + usleep(SD_CD_DELAY); + DelayCount++; + StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress); + } + } + } + s &= ~STA_NODISK; + if (WriteProtect) + { + if ((StatusReg & XSDPS_PSR_WPS_PL_MASK) == 0U) + { + s |= STA_PROTECT; + goto Label; + } + } + s &= ~STA_PROTECT; + } + else + { + s &= ~STA_NODISK & ~STA_PROTECT; + } + +Label: + Stat[pdrv] = s; +#endif + + return s; +} + +static DSTATUS disk_initialize( + BYTE pdrv /* Physical drive number (0) */ +) +{ + DSTATUS s; +#ifdef FILE_SYSTEM_INTERFACE_SD + s32 Status = XST_FAILURE; + XSdPs_Config *SdConfig; +#endif + + s = disk_status(pdrv); + if ((s & STA_NODISK) != 0U) + { + return s; + } + + /* If disk is already initialized */ + if ((s & STA_NOINIT) == 0U) + { + return s; + } + +#ifdef FILE_SYSTEM_INTERFACE_SD + if (CardDetect) + { + /* + * Card detection check + * If the HC detects the No Card State, power will be cleared + */ + while (!((XSDPS_PSR_CARD_DPL_MASK | + XSDPS_PSR_CARD_STABLE_MASK | + XSDPS_PSR_CARD_INSRT_MASK) == + (XSdPs_GetPresentStatusReg((u32)BaseAddress) & + (XSDPS_PSR_CARD_DPL_MASK | + XSDPS_PSR_CARD_STABLE_MASK | + XSDPS_PSR_CARD_INSRT_MASK)))) + ; + } + + /* + * Initialize the host controller + */ + SdConfig = XSdPs_LookupConfig((u16)pdrv); + if (NULL == SdConfig) + { + s |= STA_NOINIT; + return s; + } + + Status = XSdPs_CfgInitialize(&SdInstance[pdrv], SdConfig, + SdConfig->BaseAddress); + if (Status != XST_SUCCESS) + { + s |= STA_NOINIT; + return s; + } + + Status = XSdPs_CardInitialize(&SdInstance[pdrv]); + if (Status != XST_SUCCESS) + { + s |= STA_NOINIT; + return s; + } + + /* + * Disk is initialized. + * Store the same in Stat. + */ + s &= (~STA_NOINIT); + + Stat[pdrv] = s; +#endif + +#ifdef FILE_SYSTEM_INTERFACE_RAM + /* Assign RAMFS address value from xparameters.h */ + dataramfs = (char *)RAMFS_START_ADDR; + + /* Clearing No init Status for RAM */ + s &= (~STA_NOINIT); + Stat[pdrv] = s; +#endif + + return s; +} + +static DRESULT disk_read( + BYTE pdrv, /* Physical drive number (0) */ + BYTE *buff, /* Pointer to the data buffer to store read data */ + DWORD sector, /* Start sector number (LBA) */ + UINT count /* Sector count (1..128) */ +) +{ + DSTATUS s; +#ifdef FILE_SYSTEM_INTERFACE_SD + s32 Status = XST_FAILURE; + DWORD LocSector = sector; +#endif + + s = disk_status(pdrv); + + if ((s & STA_NOINIT) != 0U) + { + return RES_NOTRDY; + } + if (count == 0U) + { + return RES_PARERR; + } + +#ifdef FILE_SYSTEM_INTERFACE_SD + /* Convert LBA to byte address if needed */ + if ((SdInstance[pdrv].HCS) == 0U) + { + LocSector *= (DWORD)XSDPS_BLK_SIZE_512_MASK; + } + + Status = XSdPs_ReadPolled(&SdInstance[pdrv], (u32)LocSector, count, buff); + if (Status != XST_SUCCESS) + { + return RES_ERROR; + } +#endif + +#ifdef FILE_SYSTEM_INTERFACE_RAM + memcpy(buff, dataramfs + (sector * SECTORSIZE), count * SECTORSIZE); +#endif + + return RES_OK; +} + +static DRESULT disk_write( + BYTE pdrv, /* Physical drive nmuber (0..) */ + const BYTE *buff, /* Data to be written */ + DWORD sector, /* Sector address (LBA) */ + UINT count /* Number of sectors to write (1..128) */ +) +{ + DSTATUS s; +#ifdef FILE_SYSTEM_INTERFACE_SD + s32 Status = XST_FAILURE; + DWORD LocSector = sector; +#endif + + s = disk_status(pdrv); + if ((s & STA_NOINIT) != 0U) + { + return RES_NOTRDY; + } + if (count == 0U) + { + return RES_PARERR; + } + +#ifdef FILE_SYSTEM_INTERFACE_SD + /* Convert LBA to byte address if needed */ + if ((SdInstance[pdrv].HCS) == 0U) + { + LocSector *= (DWORD)XSDPS_BLK_SIZE_512_MASK; + } + + Status = XSdPs_WritePolled(&SdInstance[pdrv], (u32)LocSector, count, buff); + if (Status != XST_SUCCESS) + { + return RES_ERROR; + } + +#endif + +#ifdef FILE_SYSTEM_INTERFACE_RAM + memcpy(dataramfs + (sector * SECTORSIZE), buff, count * SECTORSIZE); +#endif + + return RES_OK; +} + +static rt_err_t rt_sdcard_init(rt_device_t dev) +{ + char sdlock_name[20]; + BYTE drvnum = *((BYTE *)dev->user_data); + + rt_snprintf(sdlock_name, sizeof(sdlock_name), "sdlock%d", drvnum); + if (rt_mutex_init(&sd_lock[drvnum], sdlock_name, RT_IPC_FLAG_FIFO) != RT_EOK) + { + LOG_E("init sdlock semaphore failed\n"); + } + else + LOG_D("sdcard init OK\n"); + + return RT_EOK; +} + +static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_sdcard_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + RT_ASSERT(((rt_uint32_t)buffer % 4) == 0); + DRESULT status; + BYTE drvnum = *((BYTE *)dev->user_data); + + rt_mutex_take(&sd_lock[drvnum], RT_WAITING_FOREVER); + status = disk_read(drvnum, buffer, part.offset + pos, size); + rt_mutex_release(&sd_lock[drvnum]); + + if (status == RES_OK) + return size; + + LOG_E("sdcard read failed\n"); + return 0; +} + +static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + RT_ASSERT(((rt_uint32_t)buffer % 4) == 0); + DRESULT status; + BYTE drvnum = *((BYTE *)dev->user_data); + + rt_mutex_take(&sd_lock[drvnum], RT_WAITING_FOREVER); + status = disk_write(drvnum, buffer, part.offset + pos, size); + rt_mutex_release(&sd_lock[drvnum]); + + if (status == RES_OK) + return size; + + LOG_E("sdcard write failed\n"); + return 0; +} + +static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + BYTE drvnum = *((BYTE *)dev->user_data); + + if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) + { + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) + return -RT_ERROR; + + geometry->bytes_per_sector = 512; + geometry->block_size = 128; + geometry->sector_count = SdInstance[drvnum].SectorCount; + } + + return RT_EOK; +} + +#ifdef BSP_USING_SD0 +static int rh_hw_emmc_init(void) +{ + if (disk_initialize(sdcard_drvnum) == RES_OK) + { + DRESULT status; + rt_uint8_t *sector; + + /* get the first sector to read partition table */ + sector = (rt_uint8_t *)rt_malloc(512); + if (sector == RT_NULL) + { + LOG_E("allocate partition sector buffer failed\n"); + return -RT_ERROR; + } + status = disk_read(0, sector, 0, 1); + if (status == RES_OK) + { + /* get the first partition */ + if (dfs_filesystem_get_partition(&part, sector, 0) != 0) + { + /* there is no partition */ + part.offset = 0; + part.size = 0; + } + } + else + { + /* there is no partition table */ + part.offset = 0; + part.size = 0; + } + + /* release sector buffer */ + rt_free(sector); + + /* register sdcard device */ + sdcard_device.type = RT_Device_Class_Block; + sdcard_device.init = rt_sdcard_init; + sdcard_device.open = rt_sdcard_open; + sdcard_device.close = rt_sdcard_close; + sdcard_device.read = rt_sdcard_read; + sdcard_device.write = rt_sdcard_write; + sdcard_device.control = rt_sdcard_control; + + /* no private */ + sdcard_device.user_data = &sdcard_drvnum; + rt_device_register(&sdcard_device, "sd0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE); + return RT_EOK; + } + + return -RT_ERROR; +} +INIT_DEVICE_EXPORT(rh_hw_emmc_init); +#endif \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.h b/bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.h new file mode 100644 index 0000000000..c0c24e13e1 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.h @@ -0,0 +1,13 @@ +#ifndef __DRV_SDCARD_H__ +#define __DRV_SDCARD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c b/bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c new file mode 100644 index 0000000000..7b0c582790 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen the first version + */ +#include +#include +#include + +#include "drv_timer.h" + +#define TTC0_0_BASEADDR XPAR_PSU_TTC_0_BASEADDR +#define TTC0_0_CLK_FREQ_HZ XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ + + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + /* clear interrupt */ + TTC_ISR(TTC0_0_BASEADDR); +} + +static int rt_hw_timer_init(void) +{ + /* Stop timer */ + TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_DIS_MASK; + + /* Initialize TTC */ + TTC_CNT_CNTRL(TTC0_0_BASEADDR) = TTC_CNT_CNTRL_RESET_VALUE; + TTC_CLK_CNTRL(TTC0_0_BASEADDR) = 0x00; + TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = 0x00; + TTC_MATCH_0(TTC0_0_BASEADDR) = 0x00; + TTC_MATCH_1(TTC0_0_BASEADDR) = 0x00; + TTC_MATCH_2(TTC0_0_BASEADDR) = 0x00; + TTC_IER(TTC0_0_BASEADDR) = 0x00; + TTC_ISR(TTC0_0_BASEADDR) = 0x00; + + /* Reset counter */ + TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_RST_MASK; + + /* Interval mode select */ + TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_INT_MASK; + /* Setup interval */ + TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = TTC0_0_CLK_FREQ_HZ / RT_TICK_PER_SECOND; + /* Clear all of the prescaler control bits in the register */ + TTC_CLK_CNTRL(TTC0_0_BASEADDR) &= ~(TTC_CLK_CNTRL_PS_VAL_MASK | + TTC_CLK_CNTRL_PS_EN_MASK); + /* We do not need a prescaler*/ + + /* Register the ticker handler with the GIC */ + rt_hw_interrupt_install(XPAR_XTTCPS_0_INTR, rt_hw_timer_isr, RT_NULL, "tick"); + /* Enable TTC interrupts in the GIC */ + rt_hw_interrupt_umask(XPAR_XTTCPS_0_INTR); + /* Enable interval interrupt */ + TTC_IER(TTC0_0_BASEADDR) |= TTC_IXR_INTERVAL_MASK; + /* Start timer */ + TTC_CNT_CNTRL(TTC0_0_BASEADDR) &=~ TTC_CNT_CNTRL_DIS_MASK; + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_timer.h b/bsp/zynqmp-r5-axu4ev/drivers/drv_timer.h new file mode 100644 index 0000000000..f759faf081 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_timer.h @@ -0,0 +1,48 @@ +#ifndef __DRV_TIMER_H__ +#define __DRV_TIMER_H__ + +#include "board.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define TTC_CLK_CNTRL(hw_base) __REG32(hw_base + 0x00) +#define TTC_CLK_CNTRL_PS_EN_MASK 0x00000001 /**< Prescale enable */ +#define TTC_CLK_CNTRL_PS_VAL_MASK 0x0000001E /**< Prescale value */ +#define TTC_CLK_CNTRL_PS_VAL_SHIFT 1 /**< Prescale shift */ +#define TTC_CLK_CNTRL_PS_DISABLE 16 /**< Prescale disable */ +#define TTC_CLK_CNTRL_SRC_MASK 0x00000020 /**< Clock source */ +#define TTC_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /**< External Clock edge */ + +#define TTC_CNT_CNTRL(hw_base) __REG32(hw_base + 0x0C) +#define TTC_CNT_CNTRL_DIS_MASK 0x00000001 /**< Disable the counter */ +#define TTC_CNT_CNTRL_INT_MASK 0x00000002 /**< interval mode */ +#define TTC_CNT_CNTRL_DECR_MASK 0x00000004 /**< Decrement mode */ +#define TTC_CNT_CNTRL_MATCH_MASK 0x00000008 /**< Match mode */ +#define TTC_CNT_CNTRL_RST_MASK 0x00000010 /**< Reset counter */ +#define TTC_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /**< Enable waveform */ +#define TTC_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /**< Waveform polarity */ +#define TTC_CNT_CNTRL_RESET_VALUE 0x00000021 /**< Reset value */ + +#define TTC_COUNT_VALUE(hw_base) __REG32(hw_base + 0x18) +#define TTC_INTERVAL_VAL(hw_base) __REG32(hw_base + 0x24) +#define TTC_MATCH_0(hw_base) __REG32(hw_base + 0x30) +#define TTC_MATCH_1(hw_base) __REG32(hw_base + 0x3C) +#define TTC_MATCH_2(hw_base) __REG32(hw_base + 0x48) + +#define TTC_ISR(hw_base) __REG32(hw_base + 0x54) +#define TTC_IXR_INTERVAL_MASK 0x00000001 /**< interval Interrupt */ +#define TTC_IXR_MATCH_0_MASK 0x00000002 /**< Match 1 Interrupt */ +#define TTC_IXR_MATCH_1_MASK 0x00000004 /**< Match 2 Interrupt */ +#define TTC_IXR_MATCH_2_MASK 0x00000008 /**< Match 3 Interrupt */ +#define TTC_IXR_CNT_OVR_MASK 0x00000010 /**< Counter Overflow */ +#define TTC_IXR_ALL_MASK 0x0000001F /**< All valid Interrupts */ + +#define TTC_IER(hw_base) __REG32(hw_base + 0x60) + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c b/bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c new file mode 100644 index 0000000000..1de379e5ae --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen the first version + */ + +#include +#include + +#include "board.h" +#include "gic.h" + +#include "drv_uart.h" + +#define IOU_SLCR_BASE_ADDR XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR +#define ZynqMP_IOU_SLCR_MIO_PIN(x) (IOU_SLCR_BASE_ADDR + 0x04 * x) + +#define XUARTPS_MAX_RATE 921600U +#define XUARTPS_MIN_RATE 110U +#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */ + +#define ZynqMP_UART_INT_DISABLE(UART) \ + (UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL)) +#define ZynqMP_UART_INT_ENABLE(UART) \ + (UART->IER |= (UART_IXR_RXOVR | UART_IXR_RXFULL)) + +#define ZynqMP_UART_SENDCHAR(UART, ch) \ + do { \ + while ((UART->SR) & UART_SR_TXFULL); \ + UART->FIFO = ch; \ + } while(0) + +#define ZynqMP_UART_GETCHAR(UART, ch) \ + do { \ + if (UART->ISR & UART_IXR_RXOVR) \ + { \ + ch = UART->FIFO & 0xff; \ + UART->ISR = (UART_IXR_RXOVR | UART_IXR_RXFULL); \ + } \ + } while(0) + +static void UartEnable(UART_Registers* uart) +{ + uint32_t tmp = uart->CR; + tmp &= ~UART_CR_EN_DIS_MASK; + tmp |= (UART_CR_TX_EN | UART_CR_RX_EN); + + uart->CR = tmp; +} + +static void UartDisable(UART_Registers* uart) +{ + uint32_t tmp = uart->CR; + tmp &= ~UART_CR_EN_DIS_MASK; + tmp |= (UART_CR_TX_DIS | UART_CR_RX_DIS); + uart->CR = tmp; +} + +static void UartResetTXRXLogic(UART_Registers* uart) +{ + uart->CR |= (UART_CR_TXRST | UART_CR_RXRST); + while (uart->CR & (UART_CR_TXRST | UART_CR_RXRST)); +} + +/* UART TxD/RxD | L3 Mux | L2 Mux | L1 Mux */ +#define RX_MIO_PIN_MODE ((0x6 << 5) | (0x0 << 3) | (0x0 << 2) | (0x0 << 1)) +#define TX_MIO_PIN_MODE ((0x6 << 5) | (0x0 << 3) | (0x0 << 2) | (0x0 << 1)) + +struct hw_uart_device +{ + UART_Registers * uart; + rt_uint32_t irqno; + rt_uint32_t inputClockHz; + + /* MIO pin mode address */ + rt_uint32_t *rxmio; + rt_uint32_t *txmio; +}; + +/* RT-Thread UART interface */ + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t XUartPsSetBandRate(struct hw_uart_device *pdev, rt_uint32_t targetBandRate) +{ + rt_uint32_t IterBAUDDIV; /* Iterator for available baud divisor values */ + rt_uint32_t BRGR_Value; /* Calculated value for baud rate generator */ + rt_uint32_t CalcBaudRate; /* Calculated baud rate */ + rt_uint32_t BaudError; /* Diff between calculated and requested baud rate */ + rt_uint32_t Best_BRGR = 0U; /* Best value for baud rate generator */ + rt_uint8_t Best_BAUDDIV = 0U; /* Best value for baud divisor */ + rt_uint32_t Best_Error = 0xFFFFFFFFU; + rt_uint32_t PercentError; + rt_uint32_t ModeReg; + rt_uint32_t InputClk; + + if ((targetBandRate > (rt_uint32_t)XUARTPS_MAX_RATE) || + (targetBandRate < (rt_uint32_t)XUARTPS_MIN_RATE)) + return -RT_EINVAL; + /* + * Make sure the baud rate is not impossilby large. + * Fastest possible baud rate is Input Clock / 2. + */ + if ((targetBandRate * 2) > pdev->inputClockHz) + return -RT_EINVAL; + + /* Check whether the input clock is divided by 8 */ + ModeReg = pdev->uart->MR; + InputClk = pdev->inputClockHz; + if(ModeReg & UART_MR_CLKSEL) + InputClk = pdev->inputClockHz / 8; + + /* + * Determine the Baud divider. It can be 4to 254. + * Loop through all possible combinations + */ + for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) + { + /* Calculate the value for BRGR register */ + BRGR_Value = InputClk / (targetBandRate * (IterBAUDDIV + 1)); + + /* Calculate the baud rate from the BRGR value */ + CalcBaudRate = InputClk / (BRGR_Value * (IterBAUDDIV + 1)); + + /* Avoid unsigned integer underflow */ + if (targetBandRate > CalcBaudRate) + BaudError = targetBandRate - CalcBaudRate; + else + BaudError = CalcBaudRate - targetBandRate; + + /* Find the calculated baud rate closest to requested baud rate. */ + if (Best_Error > BaudError) + { + Best_BRGR = BRGR_Value; + Best_BAUDDIV = IterBAUDDIV; + Best_Error = BaudError; + } + } + + /* Make sure the best error is not too large. */ + PercentError = (Best_Error * 100) / targetBandRate; + if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) + return -RT_ERROR; + + pdev->uart->BAUDGEN = Best_BRGR; + pdev->uart->BAUDDIV = Best_BAUDDIV; + return RT_EOK; +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + uint32_t mr; + struct hw_uart_device *pdev = serial->parent.user_data; + UART_Registers *uart = pdev->uart; + + UartDisable(uart); + UartResetTXRXLogic(uart); + UartEnable(uart); + + mr = uart->MR & ~(UART_MR_CHARLEN_MASK | + UART_MR_STOPMODE_MASK | + UART_MR_PARITY_MASK); + + if (cfg->stop_bits == STOP_BITS_2) + mr |= UART_MR_STOPMODE_2_BIT; + else if (cfg->stop_bits == STOP_BITS_1) + mr |= UART_MR_STOPMODE_1_BIT; + else + return -RT_EINVAL; + + if (cfg->parity == PARITY_EVEN) + mr |= UART_MR_PARITY_EVEN; + else if (cfg->parity == PARITY_ODD) + mr |= UART_MR_PARITY_ODD; + else if (cfg->parity == PARITY_NONE) + mr |= UART_MR_PARITY_NONE; + else + return -RT_EINVAL; + + if (cfg->data_bits == DATA_BITS_8) + mr |= UART_MR_CHARLEN_8_BIT; + else if (cfg->data_bits == DATA_BITS_7) + mr |= UART_MR_CHARLEN_7_BIT; + else if (cfg->data_bits == DATA_BITS_6) + mr |= UART_MR_CHARLEN_6_BIT; + else + return -RT_EINVAL; + + uart->MR = mr; + + uart->TXWM = 8; + uart->RXWM = 1; + + if (XUartPsSetBandRate(pdev, cfg->baud_rate) != RT_EOK) + { + rt_kprintf("baudrate %d not implemented yet\n", cfg->baud_rate); + return -RT_EINVAL; + } + + /* disable all interrupts */ + uart->IDR = UART_IXR_MASK; + + /* configure the pin */ + *(pdev->txmio) = TX_MIO_PIN_MODE; + *(pdev->rxmio) = RX_MIO_PIN_MODE; + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *pdev; + + RT_ASSERT(serial != RT_NULL); + + pdev = serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + ZynqMP_UART_INT_DISABLE(pdev->uart); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + ZynqMP_UART_INT_ENABLE(pdev->uart); + rt_hw_interrupt_install(pdev->irqno, rt_hw_uart_isr, serial, serial->parent.parent.name); + /* set the interrupt to this cpu */ + arm_gic_set_cpu(0, pdev->irqno, 1 << rt_cpu_get_smp_id()); + rt_hw_interrupt_umask(pdev->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *dev; + + RT_ASSERT(serial != RT_NULL); + dev = (struct hw_uart_device *)serial->parent.user_data; + + ZynqMP_UART_SENDCHAR(dev->uart, c); + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct hw_uart_device *dev; + + RT_ASSERT(serial != RT_NULL); + dev = (struct hw_uart_device *)serial->parent.user_data; + + ch = -1; + ZynqMP_UART_GETCHAR(dev->uart, ch); + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +/* UART device driver structure */ +#ifdef BSP_USING_UART0 +static struct hw_uart_device _uart_device0 = +{ + .uart = (UART_Registers*)XPAR_PSU_UART_0_BASEADDR, + .irqno = XPAR_PSU_UART_0_INTR, + .inputClockHz = XPAR_PSU_UART_0_UART_CLK_FREQ_HZ, + + .rxmio = (rt_uint32_t*)ZynqMP_IOU_SLCR_MIO_PIN(42), /* MIO42 */ + .txmio = (rt_uint32_t*)ZynqMP_IOU_SLCR_MIO_PIN(43), /* MIO43 */ +}; +static struct rt_serial_device _serial0; +#endif + +int rt_hw_uart_init(void) +{ + struct serial_configure config; + + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; + + /* register uart device */ +#ifdef BSP_USING_UART0 + _serial0.ops = &_uart_ops; + _serial0.config = config; + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + &_uart_device0); +#endif + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_uart.h b/bsp/zynqmp-r5-axu4ev/drivers/drv_uart.h new file mode 100644 index 0000000000..77a64c9324 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_uart.h @@ -0,0 +1,281 @@ +#ifndef _DRV_UART_H_ +#define _DRV_UART_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @name Register Map + * + * Registers of the UART. + * @{ + */ +typedef struct +{ + volatile uint32_t CR; /**< Control Register */ + volatile uint32_t MR; /**< Mode Register */ + volatile uint32_t IER; /**< Interrupt Enable */ + volatile uint32_t IDR; /**< Interrupt Disable */ + volatile uint32_t IMR; /**< Interrupt Mask */ + volatile uint32_t ISR; /**< Interrupt Status */ + volatile uint32_t BAUDGEN; /**< Baud Rate Generator */ + volatile uint32_t RXTOUT; /**< RX Timeout */ + volatile uint32_t RXWM; /**< RX FIFO Trigger Level */ + volatile uint32_t MODEMCR; /**< Modem Control */ + volatile uint32_t MODEMSR; /**< Modem Status */ + volatile uint32_t SR; /**< Channel Status */ + volatile uint32_t FIFO; /**< FIFO */ + volatile uint32_t BAUDDIV; /**< Baud Rate Divider */ + volatile uint32_t FLOWDEL; /**< Flow Delay */ + volatile uint32_t RESERVED1; + volatile uint32_t RESERVED2; + volatile uint32_t TXWM; /* TX FIFO Trigger Level */ +} UART_Registers; +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ +#define UART_CR_STOPBRK 0x00000100 /**< Stop transmission of break */ +#define UART_CR_STARTBRK 0x00000080 /**< Set break */ +#define UART_CR_TORST 0x00000040 /**< RX timeout counter restart */ +#define UART_CR_TX_DIS 0x00000020 /**< TX disabled. */ +#define UART_CR_TX_EN 0x00000010 /**< TX enabled */ +#define UART_CR_RX_DIS 0x00000008 /**< RX disabled. */ +#define UART_CR_RX_EN 0x00000004 /**< RX enabled */ +#define UART_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */ +#define UART_CR_TXRST 0x00000002 /**< TX logic reset */ +#define UART_CR_RXRST 0x00000001 /**< RX logic reset */ +/* @}*/ + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ +#define UART_MR_CCLK 0x00000400 /**< Input clock selection */ +#define UART_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */ +#define UART_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */ +#define UART_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */ +#define UART_MR_CHMODE_NORM 0x00000000 /**< Normal mode */ +#define UART_MR_CHMODE_SHIFT 8 /**< Mode shift */ +#define UART_MR_CHMODE_MASK 0x00000300 /**< Mode mask */ +#define UART_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */ +#define UART_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */ +#define UART_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */ +#define UART_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */ +#define UART_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */ +#define UART_MR_PARITY_NONE 0x00000020 /**< No parity mode */ +#define UART_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */ +#define UART_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */ +#define UART_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */ +#define UART_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */ +#define UART_MR_PARITY_SHIFT 3 /**< Parity setting shift */ +#define UART_MR_PARITY_MASK 0x00000038 /**< Parity mask */ +#define UART_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */ +#define UART_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */ +#define UART_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */ +#define UART_MR_CHARLEN_SHIFT 1 /**< Data Length shift */ +#define UART_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */ +#define UART_MR_CLKSEL 0x00000001 /**< Input clock selection */ +/* @} */ + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ +#define UART_IXR_DMS 0x00000200 /**< Modem status change interrupt */ +#define UART_IXR_TOUT 0x00000100 /**< Timeout error interrupt */ +#define UART_IXR_PARITY 0x00000080 /**< Parity error interrupt */ +#define UART_IXR_FRAMING 0x00000040 /**< Framing error interrupt */ +#define UART_IXR_OVER 0x00000020 /**< Overrun error interrupt */ +#define UART_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */ +#define UART_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */ +#define UART_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */ +#define UART_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */ +#define UART_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */ +#define UART_IXR_MASK 0x00003FFF /**< Valid bit mask */ +/* @} */ + +/** @name Baud Rate Generator Register + * + * The baud rate generator control register (BRGR) is a 16 bit register that + * controls the receiver bit sample clock and baud rate. + * Valid values are 1 - 65535. + * + * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit + * in the MR register. + * @{ + */ +#define UART_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */ +#define UART_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */ +/* @} */ + +/** @name Baud Divisor Rate register + * + * The baud rate divider register (BDIV) controls how much the bit sample + * rate is divided by. It sets the baud rate. + * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. + * + * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by + * the MR_CCLK bit in the MR register. + * @{ + */ +#define UART_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */ +/* @} */ + + +/** @name Receiver Timeout Register + * + * Use the receiver timeout register (RTR) to detect an idle condition on + * the receiver data line. + * + * @{ + */ +#define UART_RXTOUT_DISABLE 0x00000000 /**< Disable time out */ +#define UART_RXTOUT_MASK 0x000000FF /**< Valid bits mask */ +/* @} */ + +/** @name Receiver FIFO Trigger Level Register + * + * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at + * which the RX FIFO triggers an interrupt event. + * @{ + */ +#define UART_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */ +#define UART_RXWM_MASK 0x0000003F /**< Valid bits mask */ +/* @} */ + +/** @name Modem Control Register + * + * This register (MODEMCR) controls the interface with the modem or data set, + * or a peripheral device emulating a modem. + * + * @{ + */ +#define UART_MODEMCR_FCM 0x00000010 /**< Flow control mode */ +#define UART_MODEMCR_RTS 0x00000002 /**< Request to send */ +#define UART_MODEMCR_DTR 0x00000001 /**< Data terminal ready */ +/* @} */ + +/** @name Modem Status Register + * + * This register (MODEMSR) indicates the current state of the control lines + * from a modem, or another peripheral device, to the CPU. In addition, four + * bits of the modem status register provide change information. These bits + * are set to a logic 1 whenever a control input from the modem changes state. + * + * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem + * status interrupt is generated and this is reflected in the modem status + * register. + * + * @{ + */ +#define UART_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */ +#define UART_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */ +#define UART_MODEMSR_RI 0x00000040 /**< Complement of RI input */ +#define UART_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */ +#define UART_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */ +#define UART_MEDEMSR_DCDX 0x00000008 /**< Delta DCD indicator */ +#define UART_MEDEMSR_RIX 0x00000004 /**< Change of RI */ +#define UART_MEDEMSR_DSRX 0x00000002 /**< Change of DSR */ +#define UART_MEDEMSR_CTSX 0x00000001 /**< Change of CTS */ +/* @} */ + +/** @name Channel Status Register + * + * The channel status register (CSR) is provided to enable the control logic + * to monitor the status of bits in the channel interrupt status register, + * even if these are masked out by the interrupt mask register. + * + * @{ + */ +#define UART_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */ +#define UART_SR_TACTIVE 0x00000800 /**< TX active */ +#define UART_SR_RACTIVE 0x00000400 /**< RX active */ +#define UART_SR_DMS 0x00000200 /**< Delta modem status change */ +#define UART_SR_TOUT 0x00000100 /**< RX timeout */ +#define UART_SR_PARITY 0x00000080 /**< RX parity error */ +#define UART_SR_FRAME 0x00000040 /**< RX frame error */ +#define UART_SR_OVER 0x00000020 /**< RX overflow error */ +#define UART_SR_TXFULL 0x00000010 /**< TX FIFO full */ +#define UART_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */ +#define UART_SR_RXFULL 0x00000004 /**< RX FIFO full */ +#define UART_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */ +#define UART_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */ +/* @} */ + +/** @name Flow Delay Register + * + * Operation of the flow delay register (FLOWDEL) is very similar to the + * receive FIFO trigger register. An internal trigger signal activates when the + * FIFO is filled to the level set by this register. This trigger will not + * cause an interrupt, although it can be read through the channel status + * register. In hardware flow control mode, RTS is deactivated when the trigger + * becomes active. RTS only resets when the FIFO level is four less than the + * level of the flow delay trigger and the flow delay trigger is not activated. + * A value less than 4 disables the flow delay. + * @{ + */ +#define UART_FLOWDEL_MASK UART_RXWM_MASK /**< Valid bit mask */ +/* @} */ + + +/****************************************************************************/ +/** +* Determine if there is receive data in the receiver and/or FIFO. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if there is receive data, FALSE otherwise. +* +* @note C-Style signature: +* uint32_t UartDataReceived(uint32_t BaseAddress) +* +******************************************************************************/ +#define UartDataReceived(BaseAddress) \ + !((__REG32((BaseAddress) + UART_SR_OFFSET) & \ + UART_SR_RXEMPTY) == UART_SR_RXEMPTY) + +/****************************************************************************/ +/** +* Determine if a byte of data can be sent with the transmitter. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the +* FIFO. +* +* @note C-Style signature: +* uint32_t UartTXFIFOFull(uint32_t BaseAddress) +* +******************************************************************************/ +#define UartTXFIFOFull(BaseAddress) \ + ((__REG32((BaseAddress) + UART_SR_OFFSET) & \ + UART_SR_TXFULL) == UART_SR_TXFULL) + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h b/bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h new file mode 100644 index 0000000000..6b2be30120 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h @@ -0,0 +1,41 @@ +#ifndef __ZYNQMP_R5_H__ +#define __ZYNQMP_R5_H__ + +#include "xparameters.h" + +#define __REG64(x) (*((volatile rt_uint64_t *)(x))) +#define __REG32(x) (*((volatile rt_uint32_t *)(x))) +#define __REG16(x) (*((volatile rt_uint16_t *)(x))) +#define __REG8(x) (*((volatile rt_uint8_t *)(x))) + +#define ZynqMP_CRL_APB_BASEADDR XPAR_PSU_CRL_APB_S_AXI_BASEADDR +#define ZynqMP_CRL_APB_IOPLL_CTRL 0x020 +#define ZynqMP_CRL_APB_IOPLL_CFG 0x024 +#define ZynqMP_CRL_APB_UART0_REF_CTRL 0x074 +#define ZynqMP_CRL_APB_UART1_REF_CTRL 0x078 +#define ZynqMP_CRL_APB_LPD_LSBUS_CTRL 0x0AC +#define ZynqMP_CRL_APB_RESET_CTRL 0x218 +#define ZynqMP_RESET_MASK 0x10 + +#define ZynqMP_GIC_CPU_BASE XPAR_PSU_RCPU_GIC_BASEADDR /* Generic interrupt controller CPU interface */ +#define ZynqMP_GIC_DIST_BASE XPAR_PSU_RCPU_GIC_DIST_BASEADDR /* Generic interrupt controller distributor */ + +/* ZynqMP on-board gic irq sources */ +#define IRQ_ZynqMP_MAXNR 195 + +#define ARM_GIC_NR_IRQS IRQ_ZynqMP_MAXNR +/* only one GIC available */ +#define ARM_GIC_MAX_NR 1 + +#define GIC_ACK_INTID_MASK 0x000003FF + +#define ZynqMP_R5_0_ID 0 +#define ZynqMP_R5_1_ID 1 +#define ZynqMP_R5_CPU_ID ZynqMP_R5_0_ID + +static inline unsigned long rt_cpu_get_smp_id(void) +{ + return ZynqMP_R5_CPU_ID; +} + +#endif diff --git a/bsp/zynqmp-r5-axu4ev/rtconfig.h b/bsp/zynqmp-r5-axu4ev/rtconfig.h new file mode 100644 index 0000000000..95d92ea09d --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/rtconfig.h @@ -0,0 +1,190 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 20 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40003 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* Using RapidIO */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_ZYNQMP_R5 + +/* Hardware Drivers Config */ + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_SDIO +#define BSP_USING_SD0 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/zynqmp-r5-axu4ev/rtconfig.py b/bsp/zynqmp-r5-axu4ev/rtconfig.py new file mode 100644 index 0000000000..e772c660d3 --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/rtconfig.py @@ -0,0 +1,49 @@ +import os + +# toolchains options +ARCH='arm' +CPU='zynqmp-r5' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# only support GNU GCC compiler +PLATFORM = 'gcc' +EXEC_PATH = '/opt/arm-none-eabi-gcc' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -Wall -mcpu=cortex-r5 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LINK_SCRIPT = 'zynqmp-r5.ld' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=zynqmp-r5.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ + SIZE + ' $TARGET \n' \ No newline at end of file diff --git a/bsp/zynqmp-r5-axu4ev/zynqmp-r5.ld b/bsp/zynqmp-r5-axu4ev/zynqmp-r5.ld new file mode 100644 index 0000000000..3c16898c3f --- /dev/null +++ b/bsp/zynqmp-r5-axu4ev/zynqmp-r5.ld @@ -0,0 +1,127 @@ +MEMORY +{ + psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000 + psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000 + psu_r5_0_atcm_MEM_0 : ORIGIN = 0x0, LENGTH = 0x10000 + psu_r5_0_btcm_MEM_0 : ORIGIN = 0x20000, LENGTH = 0x10000 + psu_r5_ddr_0_MEM_0 : ORIGIN = 0x100000, LENGTH = 0x7FE00000 + psu_r5_tcm_ram_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x40000 +} + +ENTRY(_reset) + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SECTIONS +{ + .vectors : + { + KEEP (*(.vectors)) + *(.boot) + *(.text.isr) + } > psu_r5_0_atcm_MEM_0 + + __text_start = .; + .text : + { + *(.text) + *(.text.*) + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > psu_r5_ddr_0_MEM_0 = 0 + __text_end = .; + + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > psu_r5_ddr_0_MEM_0 + __exidx_end = .; + + .note-ABI-tag : + { + KEEP (*(.note-ABI-tag)) + } > psu_r5_ddr_0_MEM_0 + + .note.gnu.build-id : + { + KEEP (*(.note.gnu.build-id)) + } > psu_r5_ddr_0_MEM_0 + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } > psu_r5_ddr_0_MEM_0 + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } > psu_r5_ddr_0_MEM_0 + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } > psu_r5_ddr_0_MEM_0 + + . = ALIGN(4); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } > psu_r5_ddr_0_MEM_0 + __data_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } > psu_r5_ddr_0_MEM_0 + . = ALIGN(4); + __bss_end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} \ No newline at end of file diff --git a/libcpu/arm/zynqmp-r5/SConscript b/libcpu/arm/zynqmp-r5/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/zynqmp-r5/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/zynqmp-r5/armv7.h b/libcpu/arm/zynqmp-r5/armv7.h new file mode 100644 index 0000000000..4c34d7da8b --- /dev/null +++ b/libcpu/arm/zynqmp-r5/armv7.h @@ -0,0 +1,67 @@ +#ifndef __ARMV7_H__ +#define __ARMV7_H__ +/* + * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef VFP_DATA_NR +#define VFP_DATA_NR 32 +#endif + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +#endif diff --git a/libcpu/arm/zynqmp-r5/cache.c b/libcpu/arm/zynqmp-r5/cache.c new file mode 100644 index 0000000000..aa8517e254 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/cache.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen first version + */ +#include +#include + +#include "xpseudo_asm_gcc.h" +#include "xreg_cortexr5.h" + +#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ + +typedef intptr_t INTPTR; +typedef rt_uint32_t u32; + +#if defined (__GNUC__) +#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + +#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) +#elif defined (__ICCARM__) +#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + +#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) +#endif + + +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Select cache L0 I-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + + while (LocalAddr < end) { + + /* Invalidate L1 I-cache line */ + asm_inval_ic_line_mva_pou(LocalAddr); + + LocalAddr += cacheline; + } + } + + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +void Xil_DCacheFlushLine(INTPTR adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); +} + +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 32U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + end = tempadr + len; + tempend = end; + /* Select L1 Data cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); + + Xil_DCacheFlushLine(tempadr); + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); + + Xil_DCacheFlushLine(tempend); + } + + while (tempadr < tempend) { + + /* Invalidate Data cache line */ + asm_inval_dc_line_mva_poc(tempadr); + + tempadr += cacheline; + } + } + + dsb(); + mtcpsr(currmask); +} + +void Xil_DCacheFlushRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr &= ~(cacheline - 1U); + + while (LocalAddr < end) { + /* Flush Data cache line */ + asm_clean_inval_dc_line_mva_poc(LocalAddr); + + LocalAddr += cacheline; + } + } + dsb(); + mtcpsr(currmask); +} + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + Xil_ICacheInvalidateRange((INTPTR)addr, size); +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + Xil_DCacheFlushRange((intptr_t)addr, size); + else if (ops == RT_HW_CACHE_INVALIDATE) + Xil_DCacheInvalidateRange((intptr_t)addr, size); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + register u32 CtrlReg; +#if defined (__GNUC__) + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif + return CtrlReg & XREG_CP15_CONTROL_I_BIT; +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + register u32 CtrlReg; +#if defined (__GNUC__) + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif + return CtrlReg & XREG_CP15_CONTROL_C_BIT; +} diff --git a/libcpu/arm/zynqmp-r5/context_gcc.S b/libcpu/arm/zynqmp-r5/context_gcc.S new file mode 100644 index 0000000000..0d660017da --- /dev/null +++ b/libcpu/arm/zynqmp-r5/context_gcc.S @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen first version + */ + +.section .text, "ax" +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mrs r0, cpsr + cpsid if + bx lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + msr cpsr, r0 + bx lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + ldr sp, [r0] @ get new task stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + ldmfd sp!, {r1} /* Restore floating point registers */ + vmsr FPEXC, r1 + ldmfd sp!, {r1} + vmsr FPSCR, r1 + vldmia sp!, {d0-d15} +#endif + + ldmfd sp!, {r4} @ pop new task spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc + + +.section .text.isr, "ax" +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file + + mrs r4, cpsr + tst lr, #0x01 + beq _ARM_MODE + orr r4, r4, #0x20 @ it's thumb code + +_ARM_MODE: + stmfd sp!, {r4} @ push cpsr + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + vstmdb sp!, {d0-d15} /* Store floating point registers */ + vmrs r4, FPSCR + stmfd sp!,{r4} + vmrs r4, FPEXC + stmfd sp!,{r4} +#endif + + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + ldmfd sp!, {r1} /* Restore floating point registers */ + vmsr FPEXC, r1 + ldmfd sp!, {r1} + vmsr FPSCR, r1 + vldmia sp!, {d0-d15} +#endif + + ldmfd sp!, {r4} @ pop new task cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r3, [r2] + ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + str r0, [r2] +_reswitch: + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + bx lr diff --git a/libcpu/arm/zynqmp-r5/cpu.c b/libcpu/arm/zynqmp-r5/cpu.c new file mode 100644 index 0000000000..a2e3b85dc7 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/cpu.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen first version + */ + +#include +#include +#include "zynqmp-r5.h" + +void rt_hw_cpu_reset() +{ + __REG32(ZynqMP_CRL_APB_BASEADDR + ZynqMP_CRL_APB_RESET_CTRL) |= ZynqMP_RESET_MASK; + while (1); /* loop forever and wait for reset to happen */ + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} diff --git a/libcpu/arm/zynqmp-r5/gic.c b/libcpu/arm/zynqmp-r5/gic.c new file mode 100644 index 0000000000..3acefbc9bf --- /dev/null +++ b/libcpu/arm/zynqmp-r5/gic.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen first version + */ + +#include +#include "board.h" +#include "gic.h" + +/* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is + * compliant to the GICv1 architecture specification. */ + +struct arm_gic +{ + rt_uint32_t offset; + + rt_uint32_t dist_hw_base; + rt_uint32_t cpu_hw_base; +}; + +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; + +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) + +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) + +static unsigned int _gic_max_irq; + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); + old_tgt |= cpumask << ((irq % 4)*8); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1 << 10) ? "has" : "no", + gic_type); +} + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint32_t cpumask = 1 << 0; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020) + _gic_max_irq = 1020; + if (_gic_max_irq > ARM_GIC_NR_IRQS) + _gic_max_irq = ARM_GIC_NR_IRQS; + + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + + GIC_DIST_CTRL(dist_base) = 0x0; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32; i < _gic_max_irq; i += 16) + GIC_DIST_CONFIG(dist_base, i) = 0x0; + + /* Set all global interrupts to this CPU only. */ + for (i = 32; i < _gic_max_irq; i += 4) + GIC_DIST_TARGET(dist_base, i) = cpumask; + + /* Set priority on all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 4) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + + /* Disable all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + + /* Enable interrupt. */ + GIC_DIST_CTRL(dist_base) = 0x01; + + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].cpu_hw_base = cpu_base; + + GIC_CPU_PRIMASK(cpu_base) = 0xf0; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01; + + return 0; +} + +void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) +{ + unsigned int reg; + + RT_ASSERT(irq <= 15); + RT_ASSERT(target_cpu <= 255); + + reg = (target_cpu << 16) | irq; + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; +} + +void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) +{ + /* SGI will be cleared automatically. */ +} \ No newline at end of file diff --git a/libcpu/arm/zynqmp-r5/gic.h b/libcpu/arm/zynqmp-r5/gic.h new file mode 100644 index 0000000000..7cffec3f88 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/gic.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen first version + */ + +#ifndef __GIC_H__ +#define __GIC_H__ + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); + +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq); +void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq); + +void arm_gic_dump_type(rt_uint32_t index); + +#endif + diff --git a/libcpu/arm/zynqmp-r5/interrupt.c b/libcpu/arm/zynqmp-r5/interrupt.c new file mode 100644 index 0000000000..12ba638345 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/interrupt.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen first version + */ + +#include +#include +#include "zynqmp-r5.h" +#include "interrupt.h" +#include "gic.h" + +#define MAX_HANDLERS IRQ_ZynqMP_MAXNR + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + + +void rt_hw_interrupt_handle(int vector, void *param) +{ + rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector); +} + +void rt_hw_interrupt_init(void) +{ + register rt_uint32_t idx; + + /* the initialization is done in fsbl */ + + /* init exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + for (idx = 0; idx < MAX_HANDLERS; idx++) + { + isr_table[idx].handler = rt_hw_interrupt_handle; + } + + /* initialize ARM GIC */ + arm_gic_dist_init(0, ZynqMP_GIC_DIST_BASE, 0); + arm_gic_cpu_init(0, ZynqMP_GIC_CPU_BASE); + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + arm_gic_mask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + arm_gic_umask(0, vector); +} + +/** + * This function returns the active interrupt number. + * @param none + */ +int rt_hw_interrupt_get_irq(void) +{ + return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_ack(int vector) +{ + arm_gic_ack(0, vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param handler the interrupt service routine to be installed + * @param param the parameter for interrupt service routine + * @param name the interrupt name + * + * @return the old handler + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(isr_table[vector].name, RT_NAME_MAX, "%s", name); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + /* set the interrupt to this cpu */ + arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); + } + + return old_handler; +} + +void rt_hw_interrupt_trigger(int vector) +{ + arm_gic_trigger(0, 1 << rt_cpu_get_smp_id(), vector); +} + +void rt_hw_interrupt_clear(int vector) +{ + /* SGI will be cleared automatically. */ +} \ No newline at end of file diff --git a/libcpu/arm/zynqmp-r5/interrupt.h b/libcpu/arm/zynqmp-r5/interrupt.h new file mode 100644 index 0000000000..71459fa0a9 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/interrupt.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); +int rt_hw_interrupt_get_irq(void); +void rt_hw_interrupt_trigger(int vector); +void rt_hw_interrupt_clear(int vector); +void rt_hw_interrupt_ack(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/libcpu/arm/zynqmp-r5/mpu.c b/libcpu/arm/zynqmp-r5/mpu.c new file mode 100644 index 0000000000..dc33a5fe65 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/mpu.c @@ -0,0 +1,288 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file mpu.c +* +* This file contains initial configuration of the MPU. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 5.04	pkp  12/18/15 Updated MPU initialization as per the proper address map
+* 6.00  pkp  06/27/16 moving the Init_MPU code to .boot section since it is a
+*                     part of processor boot process
+* 6.2   mus  01/27/17 Updated to support IAR compiler
+* 7.1   mus  09/11/19 Added warning message if DDR size is not in power of 2.
+*                     Fix for CR#1038577.
+* 7.2   asa  04/08/20 Fix warning in the function Init_MPU.
+*
+* +* @note +* +* None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ +#include +#include "zynqmp-r5.h" +#include "xreg_cortexr5.h" +#include "xpseudo_asm_gcc.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ +typedef rt_int32_t s32; +typedef rt_uint64_t u64; +typedef rt_uint32_t u32; +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +static const struct { + u64 size; + unsigned int encoding; +}region_size[] = { + { 0x20, REGION_32B }, + { 0x40, REGION_64B }, + { 0x80, REGION_128B }, + { 0x100, REGION_256B }, + { 0x200, REGION_512B }, + { 0x400, REGION_1K }, + { 0x800, REGION_2K }, + { 0x1000, REGION_4K }, + { 0x2000, REGION_8K }, + { 0x4000, REGION_16K }, + { 0x8000, REGION_32K }, + { 0x10000, REGION_64K }, + { 0x20000, REGION_128K }, + { 0x40000, REGION_256K }, + { 0x80000, REGION_512K }, + { 0x100000, REGION_1M }, + { 0x200000, REGION_2M }, + { 0x400000, REGION_4M }, + { 0x800000, REGION_8M }, + { 0x1000000, REGION_16M }, + { 0x2000000, REGION_32M }, + { 0x4000000, REGION_64M }, + { 0x8000000, REGION_128M }, + { 0x10000000, REGION_256M }, + { 0x20000000, REGION_512M }, + { 0x40000000, REGION_1G }, + { 0x80000000, REGION_2G }, + { 0x100000000, REGION_4G }, +}; + +/************************** Function Prototypes ******************************/ +#if defined (__GNUC__) +void Init_MPU(void) __attribute__((__section__(".boot"))); +static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot"))); +static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot"))); +#elif defined (__ICCARM__) +#pragma default_function_attributes = @ ".boot" +void Init_MPU(void); +static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib); +static void Xil_DisableMPURegions(void); +#endif +/***************************************************************************** +* +* Initialize MPU for a given address map and Enabled the background Region in +* MPU with default memory attributes for rest of address range for Cortex R5 +* processor. +* +* @param None. +* +* @return None. +* +* +******************************************************************************/ + +void Init_MPU(void) +{ + u32 Addr; + u32 RegSize = 0U; + u32 Attrib; + u32 RegNum = 0, i, Offset = 0; + u64 size; + + Xil_DisableMPURegions(); + + Addr = 0x00000000U; +#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR + /* If the DDR is present, configure region as per DDR size */ + size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1; + if (size < 0x80000000) { + /* Lookup the size. */ + for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { + if (size <= region_size[i].size) { + RegSize = region_size[i].encoding; + + /* Check if DDR size is in power of 2*/ + if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000) + Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; + if (region_size[i].size > (size + Offset + 1)) { + rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \ + in power of 2. As processor allocates MPU regions size \ + in power of 2, address range %llx to %x has been \ + incorrectly mapped as normal memory \n", \ + region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1)); + } + break; + } + } + } else { + /* if the DDR size is > 2GB, truncate it to 2GB */ + RegSize = REGION_2G; + } +#else + /* For DDRless system, configure region for TCM */ + RegSize = REGION_256K; +#endif + Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* + * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL. + * 512 MB - LPD-PL interface + * 256 MB - FPD-PL (HPM0) interface + * 256 MB - FPD-PL (HPM1) interface + */ + Addr = 0x80000000; + RegSize = REGION_1G; + Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ + Addr = 0xC0000000U; + RegSize = REGION_512M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ + Addr = 0xE0000000U; + RegSize = REGION_256M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ + Addr = 0xF8000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ + Addr = 0xF9000000U; + RegSize = REGION_1M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ + Addr = 0xFD000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ + Addr = 0xFE000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* + * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves, + * CSU, PMU, TCM, OCM + */ + Addr = 0xFF000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; + + /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ + Addr = 0xFFFC0000U; + RegSize = REGION_256K; + Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + + /* A total of 10 MPU regions are allocated with another 6 being free for users */ + +} + +/***************************************************************************** +* +* Set the memory attributes for a section of memory with starting address addr +* of the region size defined by reg_size having attributes attrib of region number +* reg_num +* +* @param addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* @param reg_size specifies the size for that memory region. +* @param reg_num specifies the number for that memory region. +* @return None. +* +* +******************************************************************************/ +static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) +{ + u32 Local_reg_size = reg_size; + + Local_reg_size = Local_reg_size<<1U; + Local_reg_size |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + isb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ + dsb(); + isb(); /* synchronize context on this processor */ +} + + +/***************************************************************************** +* +* Disable all the MPU regions if any of them is enabled +* +* @param None. +* +* @return None. +* +* +******************************************************************************/ +static void Xil_DisableMPURegions(void) +{ + u32 Temp = 0U; + u32 Index = 0U; + for (Index = 0; Index <= 15; Index++) { + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); +#if defined (__GNUC__) + Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); +#endif + Temp &= (~REGION_EN); + dsb(); + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + dsb(); + isb(); + } + +} + +#if defined (__ICCARM__) +#pragma default_function_attributes = +#endif diff --git a/libcpu/arm/zynqmp-r5/stack.c b/libcpu/arm/zynqmp-r5/stack.c new file mode 100644 index 0000000000..c8ba712c49 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/stack.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + * 2020-11-24 WangHuachen porting to zynqmp-r5 + */ +#include +#include "armv7.h" + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + *(--stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0xdeadbeef; /* r12 */ + *(--stk) = 0xdeadbeef; /* r11 */ + *(--stk) = 0xdeadbeef; /* r10 */ + *(--stk) = 0xdeadbeef; /* r9 */ + *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = 0xdeadbeef; /* r4 */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = 0xdeadbeef; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + { + int i; + for (i = 0; i < VFP_DATA_NR; i++) + { + *(--stk) = 0; + } + /* FPSCR TODO: do we need to set the values other than 0? */ + *(--stk) = 0; + /* FPEXC. Enable the FVP if no lazy stacking. */ + *(--stk) = 0x40000000; + } +#endif + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + diff --git a/libcpu/arm/zynqmp-r5/start_gcc.S b/libcpu/arm/zynqmp-r5/start_gcc.S new file mode 100644 index 0000000000..faea0022be --- /dev/null +++ b/libcpu/arm/zynqmp-r5/start_gcc.S @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-19 WangHuachen first version + */ + +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000000 +.equ ABT_Stack_Size, 0x00000000 +.equ FIQ_Stack_Size, 0x00000200 +.equ IRQ_Stack_Size, 0x00000200 +.equ USR_Stack_Size, 0x00000000 + +.set RPU_GLBL_CNTL, 0xFF9A0000 +.set RPU_ERR_INJ, 0xFF9A0020 +.set RPU_0_CFG, 0xFF9A0100 +.set RPU_1_CFG, 0xFF9A0200 +.set RST_LPD_DBG, 0xFF5E0240 +.set BOOT_MODE_USER, 0xFF5E0200 +.set fault_log_enable, 0x101 + +#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + +.section .data.share.isr +/* stack */ +.globl stack_start +.globl stack_top + +.align 3 +.bss +stack_start: +.rept ISR_Stack_Size +.long 0 +.endr +stack_top: + +.section .boot,"axS" +/* reset entry */ +.globl _reset +_reset: + + /* Initialize processor registers to 0 */ + mov r0,#0 + mov r1,#0 + mov r2,#0 + mov r3,#0 + mov r4,#0 + mov r5,#0 + mov r6,#0 + mov r7,#0 + mov r8,#0 + mov r9,#0 + mov r10,#0 + mov r11,#0 + mov r12,#0 + + /* set the cpu to SVC32 mode and disable interrupt */ + cpsid if, #Mode_SVC + + /* setup stack */ + bl stack_setup + + /* + * Enable access to VFP by enabling access to Coprocessors 10 and 11. + * Enables Full Access i.e. in both privileged and non privileged modes + */ + mrc p15, 0, r0, c1, c0, 2 /* Read Coprocessor Access Control Register (CPACR) */ + orr r0, r0, #(0xF << 20) /* Enable access to CP 10 & 11 */ + mcr p15, 0, r0, c1, c0, 2 /* Write Coprocessor Access Control Register (CPACR) */ + isb + + /* enable fpu access */ + vmrs r3, FPEXC + orr r1, r3, #(1<<30) + vmsr FPEXC, r1 + + /* clear the floating point register*/ + mov r1,#0 + vmov d0,r1,r1 + vmov d1,r1,r1 + vmov d2,r1,r1 + vmov d3,r1,r1 + vmov d4,r1,r1 + vmov d5,r1,r1 + vmov d6,r1,r1 + vmov d7,r1,r1 + vmov d8,r1,r1 + vmov d9,r1,r1 + vmov d10,r1,r1 + vmov d11,r1,r1 + vmov d12,r1,r1 + vmov d13,r1,r1 + vmov d14,r1,r1 + vmov d15,r1,r1 + +#ifdef __SOFTFP__ +/* Disable the FPU if SOFTFP is defined*/ + vmsr FPEXC,r3 +#endif + + /* Disable MPU and caches */ + mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/ + bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */ + bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */ + dsb /* Ensure all previous loads/stores have completed */ + mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */ + isb /* Ensure subsequent insts execute wrt new MPU settings */ + + /* Disable Branch prediction, TCM ECC checks */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */ + orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */ + orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/ + bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/ + orr r0, r0, #(0x1 << 27) /* Enable B1TCM ECC check */ + orr r0, r0, #(0x1 << 26) /* Enable B0TCM ECC check */ + orr r0, r0, #(0x1 << 25) /* Enable ATCM ECC check */ + bic r0, r0, #(0x1 << 5) /* Generate abort on parity errors, with [5:3]=b 000*/ + bic r0, r0, #(0x1 << 4) + bic r0, r0, #(0x1 << 3) + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + dsb /* Complete all outstanding explicit memory operations*/ + + /* Invalidate caches */ + mov r0,#0 /* r0 = 0 */ + dsb + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/ + isb + + /* enable fault log for lock step */ + ldr r0,=RPU_GLBL_CNTL + ldr r1, [r0] + ands r1, r1, #0x8 + /* branch to initialization if split mode*/ + bne init + /* check for boot mode if in lock step, branch to init if JTAG boot mode*/ + ldr r0,=BOOT_MODE_USER + ldr r1, [r0] + ands r1, r1, #0xF + beq init + /* reset the debug logic */ + ldr r0,=RST_LPD_DBG + ldr r1, [r0] + orr r1, r1, #(0x1 << 4) + orr r1, r1, #(0x1 << 5) + str r1, [r0] + /* enable fault log */ + ldr r0,=RPU_ERR_INJ + ldr r1,=fault_log_enable + ldr r2, [r0] + orr r2, r2, r1 + str r2, [r0] + nop + nop + +init: + bl Init_MPU /* Initialize MPU */ + + /* Enable Branch prediction */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ + bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/ + bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/ + bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/ + orr r0, r0, #(0x1 << 14) /* Disable DBWR for errata 780125 */ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + + /* Enable icahce and dcache */ + mrc p15,0,r1,c1,c0,0 + ldr r0, =0x1005 + orr r1,r1,r0 + dsb + mcr p15,0,r1,c1,c0,0 /* Enable cache */ + isb /* isb flush prefetch buffer */ + + /* Set vector table in TCM/LOVEC */ + mrc p15, 0, r0, c1, c0, 0 + mvn r1, #0x2000 + and r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + /* Clear VINITHI to enable LOVEC on reset */ +#if 1 + ldr r0, =RPU_0_CFG +#else + ldr r0, =RPU_1_CFG +#endif + ldr r1, [r0] + bic r1, r1, #(0x1 << 2) + str r1, [r0] + + /* enable asynchronous abort exception */ + mrs r0, cpsr + bic r0, r0, #0x100 + msr cpsr_xsf, r0 + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + + /* start RT-Thread Kernel */ + ldr pc, _entry + +_entry: + .word entry + +stack_setup: + ldr r0, =stack_top + + @ Set the startup stack for svc + mov sp, r0 + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + + @ Switch back to SVC + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + + bx lr + +.section .text.isr, "ax" +/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ + .align 5 +.globl vector_fiq +vector_fiq: + stmfd sp!,{r0-r7,lr} + bl rt_hw_trap_fiq + ldmfd sp!,{r0-r7,lr} + subs pc,lr,#4 + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + + .align 5 +.globl vector_irq +vector_irq: + stmfd sp!, {r0-r12,lr} +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + vstmdb sp!, {d0-d15} /* Store floating point registers */ + vmrs r1, FPSCR + stmfd sp!,{r1} + vmrs r1, FPEXC + stmfd sp!,{r1} +#endif + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + ldmfd sp!, {r1} /* Restore floating point registers */ + vmsr FPEXC, r1 + ldmfd sp!, {r1} + vmsr FPSCR, r1 + vldmia sp!, {d0-d15} +#endif + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 + +rt_hw_context_switch_interrupt_do: + mov r1, #0 @ clear flag + str r1, [r0] + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + ldmfd sp!, {r1} /* Restore floating point registers */ + vmsr FPEXC, r1 + ldmfd sp!, {r1} + vmsr FPSCR, r1 + vldmia sp!, {d0-d15} +#endif + + mov r1, sp @ r1 point to {r0-r3} in stack + add sp, sp, #4*4 + ldmfd sp!, {r4-r12,lr}@ reload saved registers + mrs r0, spsr @ get cpsr of interrupt thread + sub r2, lr, #4 @ save old task's pc to r2 + + @ Switch to SVC mode with no interrupt. + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + + stmfd sp!, {r2} @ push old task's pc + stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 + ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread + stmfd sp!, {r1-r4} @ push old task's r0-r3 + stmfd sp!, {r0} @ push old task's cpsr + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + vstmdb sp!, {d0-d15} /* Store floating point registers */ + vmrs r1, FPSCR + stmfd sp!,{r1} + vmrs r1, FPEXC + stmfd sp!,{r1} +#endif + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] @ store sp in preempted tasks's TCB + + ldr r6, =rt_interrupt_to_thread + ldr r7, [r6] + ldr sp, [r7] @ get new task's stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + ldmfd sp!, {r1} /* Restore floating point registers */ + vmsr FPEXC, r1 + ldmfd sp!, {r1} + vmsr FPSCR, r1 + vldmia sp!, {d0-d15} +#endif + + ldmfd sp!, {r4} @ pop new task's cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + +.macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ +.endm + + .align 5 + .globl vector_swi +vector_swi: + push_svc_reg + bl rt_hw_trap_swi + b . + + .align 5 + .globl vector_undef +vector_undef: + push_svc_reg + bl rt_hw_trap_undef + b . + + .align 5 + .globl vector_pabt +vector_pabt: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .align 5 + .globl vector_dabt +vector_dabt: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .align 5 + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . diff --git a/libcpu/arm/zynqmp-r5/trap.c b/libcpu/arm/zynqmp-r5/trap.c new file mode 100644 index 0000000000..7a48a3c190 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/trap.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2020-11-24 WangHuachen porting to zynqmp-r5 + */ + +#include +#include +#include + +#include "armv7.h" +#include "interrupt.h" + +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register (struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("data abort:"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +void rt_hw_trap_irq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[ir].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +} + +void rt_hw_trap_fiq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + param = isr_table[ir].param; + + /* turn to interrupt service routine */ + isr_func(ir, param); + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +} + diff --git a/libcpu/arm/zynqmp-r5/vector_gcc.S b/libcpu/arm/zynqmp-r5/vector_gcc.S new file mode 100644 index 0000000000..60d3c6cf1d --- /dev/null +++ b/libcpu/arm/zynqmp-r5/vector_gcc.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .vectors, "ax" +.code 32 + +.globl system_vectors +system_vectors: + ldr pc, _vector_reset + ldr pc, _vector_undef + ldr pc, _vector_swi + ldr pc, _vector_pabt + ldr pc, _vector_dabt + ldr pc, _vector_resv + ldr pc, _vector_irq + ldr pc, _vector_fiq + +.globl _reset +.globl vector_undef +.globl vector_swi +.globl vector_pabt +.globl vector_dabt +.globl vector_resv +.globl vector_irq +.globl vector_fiq + +_vector_reset: + .word _reset +_vector_undef: + .word vector_undef +_vector_swi: + .word vector_swi +_vector_pabt: + .word vector_pabt +_vector_dabt: + .word vector_dabt +_vector_resv: + .word vector_resv +_vector_irq: + .word vector_irq +_vector_fiq: + .word vector_fiq + +.balignl 16,0xdeadbeef diff --git a/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h b/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h new file mode 100644 index 0000000000..f3f978d9eb --- /dev/null +++ b/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h @@ -0,0 +1,249 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +* +* +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
+*
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +#if defined (__aarch64__) +/* pseudo assembler instructions */ +#define mfcpsr() ({rt_uint32_t rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define mfelrel3() ({u64 rval = 0U; \ + asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ + rval;\ + }) + +#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v)) + +#else + +/* pseudo assembler instructions */ +#define mfcpsr() ({rt_uint32_t rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#endif + +#define ldrb(adr) ({rt_uint8_t rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({rt_uint8_t rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +#if defined (__aarch64__) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) + +#else +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({rt_uint32_t rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) +#endif + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h new file mode 100644 index 0000000000..263f213567 --- /dev/null +++ b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h @@ -0,0 +1,419 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xreg_cortexr5.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, IAR, ARMCC compiler. +* +* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+*
+* +******************************************************************************/ +#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ +#define XREG_CORTEXR5_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20U +#define XREG_CPSR_MODE_BITS 0x1FU +#define XREG_CPSR_SYSTEM_MODE 0x1FU +#define XREG_CPSR_UNDEFINED_MODE 0x1BU +#define XREG_CPSR_DATA_ABORT_MODE 0x17U +#define XREG_CPSR_SVC_MODE 0x13U +#define XREG_CPSR_IRQ_MODE 0x12U +#define XREG_CPSR_FIQ_MODE 0x11U +#define XREG_CPSR_USER_MODE 0x10U + +#define XREG_CPSR_IRQ_ENABLE 0x80U +#define XREG_CPSR_FIQ_ENABLE 0x40U + +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U + +/*MPU region definitions*/ +#define REGION_32B 0x00000004U +#define REGION_64B 0x00000005U +#define REGION_128B 0x00000006U +#define REGION_256B 0x00000007U +#define REGION_512B 0x00000008U +#define REGION_1K 0x00000009U +#define REGION_2K 0x0000000AU +#define REGION_4K 0x0000000BU +#define REGION_8K 0x0000000CU +#define REGION_16K 0x0000000DU +#define REGION_32K 0x0000000EU +#define REGION_64K 0x0000000FU +#define REGION_128K 0x00000010U +#define REGION_256K 0x00000011U +#define REGION_512K 0x00000012U +#define REGION_1M 0x00000013U +#define REGION_2M 0x00000014U +#define REGION_4M 0x00000015U +#define REGION_8M 0x00000016U +#define REGION_16M 0x00000017U +#define REGION_32M 0x00000018U +#define REGION_64M 0x00000019U +#define REGION_128M 0x0000001AU +#define REGION_256M 0x0000001BU +#define REGION_512M 0x0000001CU +#define REGION_1G 0x0000001DU +#define REGION_2G 0x0000001EU +#define REGION_4G 0x0000001FU + +#define REGION_EN 0x00000001U + + + +#define SHAREABLE 0x00000004U /*shareable */ +#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ + +#define DEVICE_SHARED 0x00000001U /*device, shareable*/ +#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ + +#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ +#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ + +#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ +#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ + +#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ +#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ + +#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ +#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ + +/* inner and outer cache policies can be combined for different combinations */ + +#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ +#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ +#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ +#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ + +#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ +#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ +#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ +#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ + +#define NO_ACCESS (0x00000000U<<8U) /*No access*/ +#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ +#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ +#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ +#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ +#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ + +#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ + + +/* CP15 defines */ + +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" +#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U +/* C2 Register Defines */ +/* Not Used */ + +/* C3 Register Defines */ +/* Not Used */ + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" +#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" +#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" + +#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex R5. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" +#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex R5. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +/* Not Used */ + + +/* C9 Register Defines */ + +#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" +#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" +#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" + +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +/* Not used */ + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +/* Not used */ + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" + + + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXR5_H */ -- cgit v1.3.1 From ba83ddc3c4e2fc16865b43f87081ab403a4941a9 Mon Sep 17 00:00:00 2001 From: yangjie11 Date: Mon, 30 Nov 2020 15:45:58 +0800 Subject: [SConscript] change libcpu to LIBARCH,and correcte letter case --- bsp/allwinner_tina/libcpu/SConscript | 2 +- bsp/raspberry-pi/raspi2/cpu/SConscript | 2 +- bsp/raspberry-pi/raspi3-32/cpu/SConscript | 2 +- bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript | 2 +- components/dfs/SConscript | 2 +- components/dfs/filesystems/devfs/SConscript | 2 +- components/dfs/filesystems/elmfat/SConscript | 2 +- components/dfs/filesystems/jffs2/SConscript | 2 +- components/dfs/filesystems/nfs/SConscript | 2 +- components/dfs/filesystems/ramfs/SConscript | 2 +- components/dfs/filesystems/romfs/SConscript | 2 +- components/dfs/filesystems/uffs/SConscript | 2 +- components/finsh/SConscript | 2 +- components/libc/compilers/armlibc/SConscript | 2 +- components/libc/compilers/common/SConscript | 2 +- components/libc/compilers/minilibc/SConscript | 2 +- components/libc/compilers/newlib/SConscript | 2 +- components/libc/getline/SConscript | 2 +- components/libc/libdl/SConscript | 2 +- components/libc/mmap/SConscript | 2 +- components/libc/signal/SConscript | 2 +- components/libc/termios/SConscript | 2 +- components/net/netdev/SConscript | 2 +- examples/libc/SConscript | 2 +- libcpu/aarch64/common/SConscript | 2 +- libcpu/aarch64/cortex-a53/SConscript | 2 +- libcpu/aarch64/cortex-a72/SConscript | 2 +- libcpu/arc/common/SConscript | 2 +- libcpu/arc/em/SConscript | 2 +- libcpu/arm/AT91SAM7S/SConscript | 2 +- libcpu/arm/AT91SAM7X/SConscript | 2 +- libcpu/arm/am335x/SConscript | 2 +- libcpu/arm/arm926/SConscript | 2 +- libcpu/arm/armv6/SConscript | 2 +- libcpu/arm/common/SConscript | 2 +- libcpu/arm/cortex-a/SConscript | 2 +- libcpu/arm/cortex-m0/SConscript | 2 +- libcpu/arm/cortex-m23/SConscript | 2 +- libcpu/arm/cortex-m3/SConscript | 2 +- libcpu/arm/cortex-m33/SConscript | 2 +- libcpu/arm/cortex-m4/SConscript | 2 +- libcpu/arm/cortex-m7/SConscript | 2 +- libcpu/arm/cortex-r4/SConscript | 2 +- libcpu/arm/dm36x/SConscript | 2 +- libcpu/arm/lpc214x/SConscript | 2 +- libcpu/arm/lpc24xx/SConscript | 2 +- libcpu/arm/realview-a8-vmm/SConscript | 2 +- libcpu/arm/s3c24x0/SConscript | 2 +- libcpu/arm/s3c44b0/SConscript | 2 +- libcpu/arm/sep4020/SConscript | 2 +- libcpu/arm/zynq7000/SConscript | 2 +- libcpu/avr32/uc3/SConscript | 2 +- libcpu/blackfin/bf53x/SConscript | 2 +- libcpu/c-sky/ck802/SConscript | 2 +- libcpu/c-sky/common/SConscript | 2 +- libcpu/ia32/SConscript | 2 +- libcpu/m16c/m16c62p/SConscript | 2 +- libcpu/mips/common/SConscript | 2 +- libcpu/mips/gs232/SConscript | 2 +- libcpu/mips/gs264/SConscript | 2 +- libcpu/mips/pic32/SConscript | 2 +- libcpu/nios/nios_ii/SConscript | 2 +- libcpu/ppc/common/SConscript | 2 +- libcpu/ppc/ppc405/SConscript | 2 +- libcpu/risc-v/bumblebee/SConscript | 2 +- libcpu/risc-v/common/SConscript | 2 +- libcpu/risc-v/e310/SConscript | 2 +- libcpu/risc-v/k210/SConscript | 2 +- libcpu/risc-v/nuclei/SConscript | 2 +- libcpu/risc-v/rv32m1/SConscript | 2 +- libcpu/risc-v/t-head/e906/SConscript | 2 +- libcpu/rx/SConscript | 2 +- libcpu/sim/posix/SConscript | 2 +- libcpu/sim/win32/SConscript | 2 +- libcpu/sparc-v8/bm3803/SConscript | 2 +- libcpu/sparc-v8/common/SConscript | 2 +- libcpu/ti-dsp/c28x/SConscript | 2 +- libcpu/unicore32/sep6200/SConscript | 2 +- libcpu/v850/70f34/SConscript | 2 +- libcpu/xilinx/microblaze/SConscript | 2 +- 80 files changed, 80 insertions(+), 80 deletions(-) (limited to 'libcpu') diff --git a/bsp/allwinner_tina/libcpu/SConscript b/bsp/allwinner_tina/libcpu/SConscript index 7fd3011498..d41ab0ba74 100644 --- a/bsp/allwinner_tina/libcpu/SConscript +++ b/bsp/allwinner_tina/libcpu/SConscript @@ -8,6 +8,6 @@ CPPPATH = [cwd] if rtconfig.PLATFORM == 'gcc': src += Glob('*_gcc.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/raspberry-pi/raspi2/cpu/SConscript b/bsp/raspberry-pi/raspi2/cpu/SConscript index 748b06eeb1..2a8b3869a4 100644 --- a/bsp/raspberry-pi/raspi2/cpu/SConscript +++ b/bsp/raspberry-pi/raspi2/cpu/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/raspberry-pi/raspi3-32/cpu/SConscript b/bsp/raspberry-pi/raspi3-32/cpu/SConscript index 748b06eeb1..2a8b3869a4 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/SConscript +++ b/bsp/raspberry-pi/raspi3-32/cpu/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript index 3d5802831b..e57bdc9e77 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/SConscript @@ -15,6 +15,6 @@ if rtconfig.CROSS_TOOL == 'gcc': elif rtconfig.CROSS_TOOL == 'keil': LOCAL_CCFLAGS += ' --c99' -group = DefineGroup('Fal', src, depend = ['PKG_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS) +group = DefineGroup('FAL', src, depend = ['PKG_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS) Return('group') diff --git a/components/dfs/SConscript b/components/dfs/SConscript index 3ccaeb1080..edfd4e42b5 100644 --- a/components/dfs/SConscript +++ b/components/dfs/SConscript @@ -13,7 +13,7 @@ CPPPATH = [cwd + "/include"] if GetDepend('RT_USING_POSIX'): src += ['src/poll.c', 'src/select.c'] -group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS'], CPPPATH = CPPPATH) +group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS'], CPPPATH = CPPPATH) if GetDepend('RT_USING_DFS'): # search in the file system implementation diff --git a/components/dfs/filesystems/devfs/SConscript b/components/dfs/filesystems/devfs/SConscript index 898b04a234..a2c0d843f0 100644 --- a/components/dfs/filesystems/devfs/SConscript +++ b/components/dfs/filesystems/devfs/SConscript @@ -6,6 +6,6 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_DEVFS'], CPPPATH = CPPPATH) +group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_DEVFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/elmfat/SConscript b/components/dfs/filesystems/elmfat/SConscript index 8b7ec02d43..173c0a9d65 100644 --- a/components/dfs/filesystems/elmfat/SConscript +++ b/components/dfs/filesystems/elmfat/SConscript @@ -21,6 +21,6 @@ if GetDepend('RT_DFS_ELM_USE_LFN'): else: src += ['option/ccsbcs.c'] -group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_ELMFAT'], CPPPATH = CPPPATH) +group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_ELMFAT'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/jffs2/SConscript b/components/dfs/filesystems/jffs2/SConscript index 47854393e3..85d3a4d8d2 100644 --- a/components/dfs/filesystems/jffs2/SConscript +++ b/components/dfs/filesystems/jffs2/SConscript @@ -45,6 +45,6 @@ src/write.c CPPPATH = [cwd, cwd + '/include', cwd + '/src', cwd + '/cyg', cwd + '/kernel', cwd + '/cyg/compress'] -group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_JFFS2'], CPPPATH = CPPPATH) +group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_JFFS2'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/nfs/SConscript b/components/dfs/filesystems/nfs/SConscript index f830dfc754..b340d36de2 100644 --- a/components/dfs/filesystems/nfs/SConscript +++ b/components/dfs/filesystems/nfs/SConscript @@ -8,6 +8,6 @@ CPPPATH = [cwd] SrcRemove(src, ['rpc/auth_none.c']) -group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_NFS'], CPPPATH = CPPPATH) +group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_NFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/ramfs/SConscript b/components/dfs/filesystems/ramfs/SConscript index 1304f59629..12977adf53 100644 --- a/components/dfs/filesystems/ramfs/SConscript +++ b/components/dfs/filesystems/ramfs/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_MEMHEAP', 'RT_USING_DFS_RAMFS'], CPPPATH = CPPPATH) +group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_MEMHEAP', 'RT_USING_DFS_RAMFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/romfs/SConscript b/components/dfs/filesystems/romfs/SConscript index bfd633ce91..d31941eb8a 100644 --- a/components/dfs/filesystems/romfs/SConscript +++ b/components/dfs/filesystems/romfs/SConscript @@ -10,6 +10,6 @@ if GetDepend('DFS_ROMFS_ROOT'): # A new ROMFS root has been defined, we should remove the romfs.c SrcRemove(src, ['romfs.c']) -group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS','RT_USING_DFS_ROMFS'], CPPPATH = CPPPATH) +group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS','RT_USING_DFS_ROMFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/uffs/SConscript b/components/dfs/filesystems/uffs/SConscript index 53f7713fc2..1ccd4a6869 100644 --- a/components/dfs/filesystems/uffs/SConscript +++ b/components/dfs/filesystems/uffs/SConscript @@ -33,6 +33,6 @@ src = src + uffs CPPPATH = [cwd, cwd + '/src/inc'] -group = DefineGroup('Filesystem', src , depend = ['RT_USING_DFS', 'RT_USING_DFS_UFFS'], CPPPATH = CPPPATH) +group = DefineGroup('FileSystem', src , depend = ['RT_USING_DFS', 'RT_USING_DFS_UFFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/finsh/SConscript b/components/finsh/SConscript index 88d4713d58..706165a47e 100644 --- a/components/finsh/SConscript +++ b/components/finsh/SConscript @@ -34,6 +34,6 @@ if not GetDepend('FINSH_USING_MSH_ONLY'): CPPPATH = [cwd] -group = DefineGroup('Finsh', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH) +group = DefineGroup('FinSH', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/compilers/armlibc/SConscript b/components/libc/compilers/armlibc/SConscript index 2d366901c4..5f8f65a563 100644 --- a/components/libc/compilers/armlibc/SConscript +++ b/components/libc/compilers/armlibc/SConscript @@ -15,7 +15,7 @@ if GetDepend('RT_USING_MODULE') == False: SrcRemove(src, ['libc_syms.c']) if rtconfig.PLATFORM == 'armcc' or rtconfig.PLATFORM == 'armclang': - group = DefineGroup('Libc', src, depend = ['RT_USING_LIBC'], + group = DefineGroup('LIBC', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/compilers/common/SConscript b/components/libc/compilers/common/SConscript index 21a49d9c57..f661a1ee0d 100644 --- a/components/libc/compilers/common/SConscript +++ b/components/libc/compilers/common/SConscript @@ -17,6 +17,6 @@ if GetDepend('RT_USING_POSIX') == False: SrcRemove(src, ['unistd.c']) if not GetDepend('RT_USING_MINILIBC') and (GetDepend('RT_USING_LIBC') or GetDepend('RT_LIBC_USING_TIME')): - group = DefineGroup('Libc', src, depend = [''], CPPPATH = CPPPATH) + group = DefineGroup('LIBC', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/compilers/minilibc/SConscript b/components/libc/compilers/minilibc/SConscript index efdcf5d097..cdaf9ec32b 100644 --- a/components/libc/compilers/minilibc/SConscript +++ b/components/libc/compilers/minilibc/SConscript @@ -9,7 +9,7 @@ CPPPATH = [cwd] CPPDEFINES = ['RT_USING_MINILIBC'] if rtconfig.PLATFORM == 'gcc' and rtconfig.ARCH != 'sim' and not GetDepend('RT_USING_LIBC') and GetDepend('RT_USING_MINILIBC'): - group = DefineGroup('Libc', src, depend = [''], + group = DefineGroup('LIBC', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/compilers/newlib/SConscript b/components/libc/compilers/newlib/SConscript index bd444ab732..11de59bec4 100644 --- a/components/libc/compilers/newlib/SConscript +++ b/components/libc/compilers/newlib/SConscript @@ -15,7 +15,7 @@ CPPDEFINES = ['RT_USING_NEWLIB'] LIBS = ['c', 'm'] if rtconfig.PLATFORM == 'gcc': - group = DefineGroup('Newlib', src, depend = ['RT_USING_LIBC'], + group = DefineGroup('NewLIB', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LIBS = LIBS) Return('group') diff --git a/components/libc/getline/SConscript b/components/libc/getline/SConscript index f85843dada..6c9a2a164c 100644 --- a/components/libc/getline/SConscript +++ b/components/libc/getline/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('Libc', src, +group = DefineGroup('LIBC', src, depend = ['RT_USING_LIBC', 'RT_USING_POSIX','RT_USING_POSIX_GETLINE'], CPPPATH = CPPPATH) diff --git a/components/libc/libdl/SConscript b/components/libc/libdl/SConscript index 05efab351c..28265521f6 100644 --- a/components/libc/libdl/SConscript +++ b/components/libc/libdl/SConscript @@ -7,7 +7,7 @@ group = [] CPPPATH = [cwd] if rtconfig.PLATFORM == 'gcc': - group = DefineGroup('Libc', src, + group = DefineGroup('LIBC', src, depend = ['RT_USING_MODULE'], CPPPATH = CPPPATH) diff --git a/components/libc/mmap/SConscript b/components/libc/mmap/SConscript index 0b84003241..53036ad436 100644 --- a/components/libc/mmap/SConscript +++ b/components/libc/mmap/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('Libc', src, +group = DefineGroup('LIBC', src, depend = ['RT_USING_DFS', 'RT_USING_POSIX_MMAP'], CPPPATH = CPPPATH) diff --git a/components/libc/signal/SConscript b/components/libc/signal/SConscript index 407d60c728..f32a1221ea 100644 --- a/components/libc/signal/SConscript +++ b/components/libc/signal/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('Libc', src, +group = DefineGroup('LIBC', src, depend = ['RT_USING_SIGNALS', 'RT_USING_PTHREADS', 'RT_USING_LIBC'], CPPPATH = CPPPATH) diff --git a/components/libc/termios/SConscript b/components/libc/termios/SConscript index 977ff7e0a2..4bd0a42eb8 100644 --- a/components/libc/termios/SConscript +++ b/components/libc/termios/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('Libc', src, +group = DefineGroup('LIBC', src, depend = ['RT_USING_LIBC', 'RT_USING_POSIX', 'RT_USING_POSIX_TERMIOS'], CPPPATH = CPPPATH) diff --git a/components/net/netdev/SConscript b/components/net/netdev/SConscript index 5fa858e968..0db486b2de 100644 --- a/components/net/netdev/SConscript +++ b/components/net/netdev/SConscript @@ -8,6 +8,6 @@ src = Glob('src/*.c') CPPPATH = [cwd + '/include'] -group = DefineGroup('Netdev', src, depend = ['RT_USING_NETDEV'], CPPPATH = CPPPATH) +group = DefineGroup('NetDev', src, depend = ['RT_USING_NETDEV'], CPPPATH = CPPPATH) Return('group') diff --git a/examples/libc/SConscript b/examples/libc/SConscript index 601acd22a1..547dd215b1 100644 --- a/examples/libc/SConscript +++ b/examples/libc/SConscript @@ -1,6 +1,6 @@ from building import * src = Glob('*.c') -group = DefineGroup('LibcTest', src, depend = ['RT_USING_NEWLIB', 'RT_USING_PTHREADS']) +group = DefineGroup('LIBCTest', src, depend = ['RT_USING_NEWLIB', 'RT_USING_PTHREADS']) Return('group') diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript index e44dd04b5b..59378636fa 100644 --- a/libcpu/aarch64/common/SConscript +++ b/libcpu/aarch64/common/SConscript @@ -8,7 +8,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) # build for sub-directory list = os.listdir(cwd) diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript index 1dfa9022c5..5f509fbf5b 100644 --- a/libcpu/aarch64/cortex-a53/SConscript +++ b/libcpu/aarch64/cortex-a53/SConscript @@ -8,6 +8,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/aarch64/cortex-a72/SConscript b/libcpu/aarch64/cortex-a72/SConscript index 1dfa9022c5..5f509fbf5b 100644 --- a/libcpu/aarch64/cortex-a72/SConscript +++ b/libcpu/aarch64/cortex-a72/SConscript @@ -8,6 +8,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arc/common/SConscript b/libcpu/arc/common/SConscript index 1962dec615..19604861f2 100644 --- a/libcpu/arc/common/SConscript +++ b/libcpu/arc/common/SConscript @@ -5,6 +5,6 @@ src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('Libcpu', src, depend = [], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arc/em/SConscript b/libcpu/arc/em/SConscript index 2210cba597..215749bea4 100644 --- a/libcpu/arc/em/SConscript +++ b/libcpu/arc/em/SConscript @@ -10,6 +10,6 @@ CPPPATH = [cwd] src += Glob('*.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/AT91SAM7S/SConscript b/libcpu/arm/AT91SAM7S/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/AT91SAM7S/SConscript +++ b/libcpu/arm/AT91SAM7S/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/AT91SAM7X/SConscript b/libcpu/arm/AT91SAM7X/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/AT91SAM7X/SConscript +++ b/libcpu/arm/AT91SAM7X/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/am335x/SConscript b/libcpu/arm/am335x/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/am335x/SConscript +++ b/libcpu/arm/am335x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/arm926/SConscript b/libcpu/arm/arm926/SConscript index 705307f210..9bd0ddaf0a 100644 --- a/libcpu/arm/arm926/SConscript +++ b/libcpu/arm/arm926/SConscript @@ -20,6 +20,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/arm/armv6/SConscript b/libcpu/arm/armv6/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/armv6/SConscript +++ b/libcpu/arm/armv6/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/common/SConscript b/libcpu/arm/common/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/common/SConscript +++ b/libcpu/arm/common/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/cortex-a/SConscript +++ b/libcpu/arm/cortex-a/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m0/SConscript b/libcpu/arm/cortex-m0/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/cortex-m0/SConscript +++ b/libcpu/arm/cortex-m0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m23/SConscript b/libcpu/arm/cortex-m23/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/cortex-m23/SConscript +++ b/libcpu/arm/cortex-m23/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m3/SConscript b/libcpu/arm/cortex-m3/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/cortex-m3/SConscript +++ b/libcpu/arm/cortex-m3/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m33/SConscript b/libcpu/arm/cortex-m33/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/cortex-m33/SConscript +++ b/libcpu/arm/cortex-m33/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m4/SConscript b/libcpu/arm/cortex-m4/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/cortex-m4/SConscript +++ b/libcpu/arm/cortex-m4/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m7/SConscript b/libcpu/arm/cortex-m7/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/cortex-m7/SConscript +++ b/libcpu/arm/cortex-m7/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-r4/SConscript b/libcpu/arm/cortex-r4/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/cortex-r4/SConscript +++ b/libcpu/arm/cortex-r4/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/dm36x/SConscript b/libcpu/arm/dm36x/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/dm36x/SConscript +++ b/libcpu/arm/dm36x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/lpc214x/SConscript b/libcpu/arm/lpc214x/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/lpc214x/SConscript +++ b/libcpu/arm/lpc214x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/lpc24xx/SConscript b/libcpu/arm/lpc24xx/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/lpc24xx/SConscript +++ b/libcpu/arm/lpc24xx/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/realview-a8-vmm/SConscript b/libcpu/arm/realview-a8-vmm/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/realview-a8-vmm/SConscript +++ b/libcpu/arm/realview-a8-vmm/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/s3c24x0/SConscript b/libcpu/arm/s3c24x0/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/s3c24x0/SConscript +++ b/libcpu/arm/s3c24x0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/s3c44b0/SConscript b/libcpu/arm/s3c44b0/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/s3c44b0/SConscript +++ b/libcpu/arm/s3c44b0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/sep4020/SConscript b/libcpu/arm/sep4020/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/sep4020/SConscript +++ b/libcpu/arm/sep4020/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript index 729d9c03df..990f753abd 100644 --- a/libcpu/arm/zynq7000/SConscript +++ b/libcpu/arm/zynq7000/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/avr32/uc3/SConscript b/libcpu/avr32/uc3/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/avr32/uc3/SConscript +++ b/libcpu/avr32/uc3/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/blackfin/bf53x/SConscript b/libcpu/blackfin/bf53x/SConscript index 86d5d3973d..5908a24142 100644 --- a/libcpu/blackfin/bf53x/SConscript +++ b/libcpu/blackfin/bf53x/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_vdsp.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/c-sky/ck802/SConscript b/libcpu/c-sky/ck802/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/c-sky/ck802/SConscript +++ b/libcpu/c-sky/ck802/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/c-sky/common/SConscript b/libcpu/c-sky/common/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/c-sky/common/SConscript +++ b/libcpu/c-sky/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ia32/SConscript b/libcpu/ia32/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/ia32/SConscript +++ b/libcpu/ia32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/m16c/m16c62p/SConscript b/libcpu/m16c/m16c62p/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/m16c/m16c62p/SConscript +++ b/libcpu/m16c/m16c62p/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/common/SConscript b/libcpu/mips/common/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/mips/common/SConscript +++ b/libcpu/mips/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/gs232/SConscript b/libcpu/mips/gs232/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/mips/gs232/SConscript +++ b/libcpu/mips/gs232/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/gs264/SConscript b/libcpu/mips/gs264/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/mips/gs264/SConscript +++ b/libcpu/mips/gs264/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/pic32/SConscript b/libcpu/mips/pic32/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/mips/pic32/SConscript +++ b/libcpu/mips/pic32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/nios/nios_ii/SConscript b/libcpu/nios/nios_ii/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/nios/nios_ii/SConscript +++ b/libcpu/nios/nios_ii/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ppc/common/SConscript b/libcpu/ppc/common/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/ppc/common/SConscript +++ b/libcpu/ppc/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ppc/ppc405/SConscript b/libcpu/ppc/ppc405/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/ppc/ppc405/SConscript +++ b/libcpu/ppc/ppc405/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/bumblebee/SConscript b/libcpu/risc-v/bumblebee/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/risc-v/bumblebee/SConscript +++ b/libcpu/risc-v/bumblebee/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/common/SConscript b/libcpu/risc-v/common/SConscript index 6d6f2fca51..08a1215daf 100644 --- a/libcpu/risc-v/common/SConscript +++ b/libcpu/risc-v/common/SConscript @@ -7,6 +7,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/e310/SConscript b/libcpu/risc-v/e310/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/risc-v/e310/SConscript +++ b/libcpu/risc-v/e310/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/k210/SConscript b/libcpu/risc-v/k210/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/risc-v/k210/SConscript +++ b/libcpu/risc-v/k210/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/risc-v/nuclei/SConscript +++ b/libcpu/risc-v/nuclei/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/rv32m1/SConscript b/libcpu/risc-v/rv32m1/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/risc-v/rv32m1/SConscript +++ b/libcpu/risc-v/rv32m1/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/t-head/e906/SConscript b/libcpu/risc-v/t-head/e906/SConscript index 6d6f2fca51..08a1215daf 100644 --- a/libcpu/risc-v/t-head/e906/SConscript +++ b/libcpu/risc-v/t-head/e906/SConscript @@ -7,6 +7,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/rx/SConscript b/libcpu/rx/SConscript index 37ea22c449..57ad8ba965 100644 --- a/libcpu/rx/SConscript +++ b/libcpu/rx/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_iar.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sim/posix/SConscript b/libcpu/sim/posix/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/sim/posix/SConscript +++ b/libcpu/sim/posix/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sim/win32/SConscript b/libcpu/sim/win32/SConscript index 91589d8f5c..4488a0dbb5 100644 --- a/libcpu/sim/win32/SConscript +++ b/libcpu/sim/win32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sparc-v8/bm3803/SConscript b/libcpu/sparc-v8/bm3803/SConscript index e80809d85b..62648f9eeb 100644 --- a/libcpu/sparc-v8/bm3803/SConscript +++ b/libcpu/sparc-v8/bm3803/SConscript @@ -12,6 +12,6 @@ if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') src += Glob('*_gcc.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/sparc-v8/common/SConscript b/libcpu/sparc-v8/common/SConscript index e80809d85b..62648f9eeb 100644 --- a/libcpu/sparc-v8/common/SConscript +++ b/libcpu/sparc-v8/common/SConscript @@ -12,6 +12,6 @@ if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') src += Glob('*_gcc.S') -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/ti-dsp/c28x/SConscript b/libcpu/ti-dsp/c28x/SConscript index 7690eb5960..2265bf3bee 100644 --- a/libcpu/ti-dsp/c28x/SConscript +++ b/libcpu/ti-dsp/c28x/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*.s') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/unicore32/sep6200/SConscript b/libcpu/unicore32/sep6200/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/unicore32/sep6200/SConscript +++ b/libcpu/unicore32/sep6200/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/v850/70f34/SConscript b/libcpu/v850/70f34/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/v850/70f34/SConscript +++ b/libcpu/v850/70f34/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/xilinx/microblaze/SConscript b/libcpu/xilinx/microblaze/SConscript index fa3e28e56a..da76d51366 100644 --- a/libcpu/xilinx/microblaze/SConscript +++ b/libcpu/xilinx/microblaze/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('Libcpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') -- cgit v1.3.1 From ef62febf1f2461bdd72efcffde050905865a99c5 Mon Sep 17 00:00:00 2001 From: yangjie Date: Sat, 19 Dec 2020 16:49:11 +0800 Subject: [SConscript]update group name --- bsp/allwinner_tina/libcpu/SConscript | 2 +- bsp/amebaz/libraries/smartconfig/SConscript | 2 +- bsp/apollo2/board/SConscript | 2 +- bsp/asm9260t/platform/SConscript | 2 +- bsp/at32/Libraries/AT32_Std_Driver/SConscript | 2 +- bsp/at91sam9260/platform/SConscript | 2 +- bsp/at91sam9g45/platform/SConscript | 2 +- bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/SConscript | 2 +- bsp/dm365/drivers/SConscript | 2 +- bsp/fh8620/platform/common/SConscript | 2 +- bsp/fh8620/platform/fh8620/iot_cam/SConscript | 2 +- bsp/fh8620/platform/plat-v2/SConscript | 2 +- bsp/frdm-k64f/board/SConscript | 2 +- bsp/frdm-k64f/device/SConscript | 2 +- bsp/gkipc/armv6/SConscript | 2 +- bsp/gkipc/libraries/drv/7102C/gd/SConscript | 2 +- bsp/gkipc/libraries/drv/7102C/gd/src/SConscript | 2 +- bsp/gkipc/libraries/drv/7102C/gh/SConscript | 2 +- bsp/gkipc/libraries/drv/7102C/gh/src/SConscript | 2 +- bsp/gkipc/libraries/drv/710X/gd/SConscript | 2 +- bsp/gkipc/libraries/drv/710X/gd/src/SConscript | 2 +- bsp/gkipc/libraries/drv/710X/gh/SConscript | 2 +- bsp/gkipc/libraries/drv/710X/gh/src/SConscript | 2 +- bsp/gkipc/libraries/drv/710XS/gd/SConscript | 2 +- bsp/gkipc/libraries/drv/710XS/gd/src/SConscript | 2 +- bsp/gkipc/libraries/drv/710XS/gh/SConscript | 2 +- bsp/gkipc/libraries/drv/710XS/gh/src/SConscript | 2 +- bsp/gkipc/libraries/drv/gnu_c/SConscript | 2 +- bsp/gkipc/platform/SConscript | 2 +- bsp/imx6sx/cortex-a9/cpu/SConscript | 2 +- bsp/k210/driver/camera/SConscript | 2 +- bsp/nrf51822/Libraries/SConscript | 2 +- bsp/nrf52832/board/Sconscript | 2 +- bsp/nrf52832/startups/Sconscript | 2 +- bsp/nuvoton/libraries/m480/Device/SConscript | 2 +- bsp/nuvoton/libraries/m480/StdDriver/SConscript | 4 ++-- bsp/nuvoton/libraries/m480/rtt_port/SConscript | 2 +- bsp/nuvoton/numaker-iot-m487/board/SConscript | 2 +- bsp/nuvoton/numaker-pfm-m487/board/SConscript | 2 +- bsp/qemu-vexpress-a9/drivers/audio/SConscript | 2 +- bsp/qemu-vexpress-gemini/cpu/SConscript | 2 +- bsp/raspberry-pi/raspi2/cpu/SConscript | 2 +- bsp/raspberry-pi/raspi3-32/cpu/SConscript | 2 +- bsp/samd21/board/SConscript | 2 +- components/dfs/SConscript | 2 +- components/dfs/filesystems/devfs/SConscript | 2 +- components/dfs/filesystems/elmfat/SConscript | 2 +- components/dfs/filesystems/jffs2/SConscript | 2 +- components/dfs/filesystems/nfs/SConscript | 2 +- components/dfs/filesystems/ramfs/SConscript | 2 +- components/dfs/filesystems/romfs/SConscript | 2 +- components/dfs/filesystems/uffs/SConscript | 2 +- components/drivers/sensors/SConscript | 2 +- components/drivers/touch/SConscript | 2 +- components/finsh/SConscript | 2 +- components/libc/aio/SConscript | 2 +- components/libc/compilers/armlibc/SConscript | 2 +- components/libc/compilers/common/SConscript | 2 +- components/libc/compilers/dlib/SConscript | 2 +- components/libc/compilers/minilibc/SConscript | 2 +- components/libc/compilers/newlib/SConscript | 2 +- components/libc/getline/SConscript | 2 +- components/libc/libdl/SConscript | 2 +- components/libc/mmap/SConscript | 2 +- components/libc/pthreads/SConscript | 2 +- components/libc/signal/SConscript | 2 +- components/libc/termios/SConscript | 2 +- components/libc/time/SConscript | 2 +- components/net/lwip-1.4.1/SConscript | 2 +- components/net/lwip-2.0.2/SConscript | 2 +- components/net/lwip-2.1.2/SConscript | 2 +- components/net/lwip_dhcpd/SConscript | 2 +- components/net/lwip_nat/SConscript | 2 +- components/net/netdev/SConscript | 2 +- components/utilities/utest/SConscript | 2 +- examples/libc/SConscript | 2 +- libcpu/aarch64/common/SConscript | 2 +- libcpu/aarch64/cortex-a53/SConscript | 2 +- libcpu/aarch64/cortex-a72/SConscript | 2 +- libcpu/arc/common/SConscript | 2 +- libcpu/arc/em/SConscript | 2 +- libcpu/arm/AT91SAM7S/SConscript | 2 +- libcpu/arm/AT91SAM7X/SConscript | 2 +- libcpu/arm/am335x/SConscript | 2 +- libcpu/arm/arm926/SConscript | 2 +- libcpu/arm/armv6/SConscript | 2 +- libcpu/arm/common/SConscript | 2 +- libcpu/arm/cortex-a/SConscript | 2 +- libcpu/arm/cortex-m0/SConscript | 2 +- libcpu/arm/cortex-m23/SConscript | 2 +- libcpu/arm/cortex-m3/SConscript | 2 +- libcpu/arm/cortex-m33/SConscript | 2 +- libcpu/arm/cortex-m4/SConscript | 2 +- libcpu/arm/cortex-m7/SConscript | 2 +- libcpu/arm/cortex-r4/SConscript | 2 +- libcpu/arm/dm36x/SConscript | 2 +- libcpu/arm/lpc214x/SConscript | 2 +- libcpu/arm/lpc24xx/SConscript | 2 +- libcpu/arm/realview-a8-vmm/SConscript | 2 +- libcpu/arm/s3c24x0/SConscript | 2 +- libcpu/arm/s3c44b0/SConscript | 2 +- libcpu/arm/sep4020/SConscript | 2 +- libcpu/arm/zynq7000/SConscript | 2 +- libcpu/avr32/uc3/SConscript | 2 +- libcpu/blackfin/bf53x/SConscript | 2 +- libcpu/c-sky/ck802/SConscript | 2 +- libcpu/c-sky/common/SConscript | 2 +- libcpu/ia32/SConscript | 2 +- libcpu/m16c/m16c62p/SConscript | 2 +- libcpu/mips/common/SConscript | 2 +- libcpu/mips/gs232/SConscript | 2 +- libcpu/mips/gs264/SConscript | 2 +- libcpu/mips/pic32/SConscript | 2 +- libcpu/nios/nios_ii/SConscript | 2 +- libcpu/ppc/common/SConscript | 2 +- libcpu/ppc/ppc405/SConscript | 2 +- libcpu/risc-v/bumblebee/SConscript | 2 +- libcpu/risc-v/common/SConscript | 2 +- libcpu/risc-v/e310/SConscript | 2 +- libcpu/risc-v/k210/SConscript | 2 +- libcpu/risc-v/nuclei/SConscript | 2 +- libcpu/risc-v/rv32m1/SConscript | 2 +- libcpu/risc-v/t-head/e906/SConscript | 2 +- libcpu/rx/SConscript | 2 +- libcpu/sim/posix/SConscript | 2 +- libcpu/sim/win32/SConscript | 2 +- libcpu/sparc-v8/bm3803/SConscript | 2 +- libcpu/sparc-v8/common/SConscript | 2 +- libcpu/ti-dsp/c28x/SConscript | 2 +- libcpu/unicore32/sep6200/SConscript | 2 +- libcpu/v850/70f34/SConscript | 2 +- libcpu/xilinx/microblaze/SConscript | 2 +- 132 files changed, 133 insertions(+), 133 deletions(-) (limited to 'libcpu') diff --git a/bsp/allwinner_tina/libcpu/SConscript b/bsp/allwinner_tina/libcpu/SConscript index d41ab0ba74..aa13c2b179 100644 --- a/bsp/allwinner_tina/libcpu/SConscript +++ b/bsp/allwinner_tina/libcpu/SConscript @@ -8,6 +8,6 @@ CPPPATH = [cwd] if rtconfig.PLATFORM == 'gcc': src += Glob('*_gcc.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/amebaz/libraries/smartconfig/SConscript b/bsp/amebaz/libraries/smartconfig/SConscript index 4ae07e3815..31c98a046b 100644 --- a/bsp/amebaz/libraries/smartconfig/SConscript +++ b/bsp/amebaz/libraries/smartconfig/SConscript @@ -12,7 +12,7 @@ if rtconfig.CROSS_TOOL == 'gcc': elif rtconfig.CROSS_TOOL == 'iar': libs += ['libsmartconfig_armcm4_iar'] -group = DefineGroup('smartconfig', src, depend = ['RT_USING_SMARTCONFIG_LIB'], CPPPATH = path, LIBS = libs, LIBPATH = libpath) +group = DefineGroup('Libraries', src, depend = ['RT_USING_SMARTCONFIG_LIB'], CPPPATH = path, LIBS = libs, LIBPATH = libpath) Return('group') diff --git a/bsp/apollo2/board/SConscript b/bsp/apollo2/board/SConscript index 2f2dc9eb48..ce5e82d5dd 100644 --- a/bsp/apollo2/board/SConscript +++ b/bsp/apollo2/board/SConscript @@ -9,6 +9,6 @@ CPPPATH = [cwd] #remove other no use files #SrcRemove(src, '*.c') -group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') \ No newline at end of file diff --git a/bsp/asm9260t/platform/SConscript b/bsp/asm9260t/platform/SConscript index 5df4a5fc63..e0706a5017 100644 --- a/bsp/asm9260t/platform/SConscript +++ b/bsp/asm9260t/platform/SConscript @@ -8,5 +8,5 @@ CPPPATH = [cwd] # The set of source files associated with this SConscript file. src = Glob('*.c') -group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/at32/Libraries/AT32_Std_Driver/SConscript b/bsp/at32/Libraries/AT32_Std_Driver/SConscript index fd6b012d0a..1b7c7c1369 100644 --- a/bsp/at32/Libraries/AT32_Std_Driver/SConscript +++ b/bsp/at32/Libraries/AT32_Std_Driver/SConscript @@ -41,6 +41,6 @@ path = [ CPPDEFINES = ['USE_STDPERIPH_DRIVER'] -group = DefineGroup('AT32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/at91sam9260/platform/SConscript b/bsp/at91sam9260/platform/SConscript index 1f5de6e772..65b33d7eef 100644 --- a/bsp/at91sam9260/platform/SConscript +++ b/bsp/at91sam9260/platform/SConscript @@ -21,6 +21,6 @@ if rtconfig.PLATFORM == 'cl': if rtconfig.PLATFORM == 'mingw': src = Glob('*.c') -group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Platform', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/at91sam9g45/platform/SConscript b/bsp/at91sam9g45/platform/SConscript index 1f5de6e772..65b33d7eef 100644 --- a/bsp/at91sam9g45/platform/SConscript +++ b/bsp/at91sam9g45/platform/SConscript @@ -21,6 +21,6 @@ if rtconfig.PLATFORM == 'cl': if rtconfig.PLATFORM == 'mingw': src = Glob('*.c') -group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Platform', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/SConscript b/bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/SConscript index e7852f8abb..19d9931942 100644 --- a/bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/SConscript +++ b/bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/SConscript @@ -25,6 +25,6 @@ CPPPATH = [ cwd + '/DRIVERS/USART', ] -group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/dm365/drivers/SConscript b/bsp/dm365/drivers/SConscript index 287720aa96..a36d186e94 100644 --- a/bsp/dm365/drivers/SConscript +++ b/bsp/dm365/drivers/SConscript @@ -26,6 +26,6 @@ if GetDepend('RT_USING_SPI_CONTROL'): if GetDepend('RT_USING_EMAC'): src += ['davinci_emac.c'] -group = DefineGroup('Startup', src, depend = [''], CPPPATH = path) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/fh8620/platform/common/SConscript b/bsp/fh8620/platform/common/SConscript index 9679d6df56..b5bcf86f6d 100644 --- a/bsp/fh8620/platform/common/SConscript +++ b/bsp/fh8620/platform/common/SConscript @@ -3,6 +3,6 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') -group = DefineGroup('Platform', src, depend = ['']) +group = DefineGroup('Drivers', src, depend = ['']) Return('group') diff --git a/bsp/fh8620/platform/fh8620/iot_cam/SConscript b/bsp/fh8620/platform/fh8620/iot_cam/SConscript index 7f5236ef88..527e7976e3 100644 --- a/bsp/fh8620/platform/fh8620/iot_cam/SConscript +++ b/bsp/fh8620/platform/fh8620/iot_cam/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') path = [cwd, cwd + '/..'] -group = DefineGroup('Platform', src, depend = ['CONFIG_BOARD_IOTCAM', 'CONFIG_CHIP_FH8620'], CPPPATH = path) +group = DefineGroup('Drivers', src, depend = ['CONFIG_BOARD_IOTCAM', 'CONFIG_CHIP_FH8620'], CPPPATH = path) Return('group') diff --git a/bsp/fh8620/platform/plat-v2/SConscript b/bsp/fh8620/platform/plat-v2/SConscript index 40240950c0..7fad1e2a7e 100644 --- a/bsp/fh8620/platform/plat-v2/SConscript +++ b/bsp/fh8620/platform/plat-v2/SConscript @@ -8,6 +8,6 @@ src = Glob('*.c') path = [cwd, cwd + '/..'] -group = DefineGroup('Platform', src, depend = ['CONFIG_PLAT_V2'], CPPPATH = path) +group = DefineGroup('Drivers', src, depend = ['CONFIG_PLAT_V2'], CPPPATH = path) Return('group') diff --git a/bsp/frdm-k64f/board/SConscript b/bsp/frdm-k64f/board/SConscript index d92267623c..5db2d042e6 100644 --- a/bsp/frdm-k64f/board/SConscript +++ b/bsp/frdm-k64f/board/SConscript @@ -18,6 +18,6 @@ if GetDepend('RT_USING_LWIP'): CPPPATH = [cwd] -group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/frdm-k64f/device/SConscript b/bsp/frdm-k64f/device/SConscript index 9fa79aed4a..d91ae0576f 100644 --- a/bsp/frdm-k64f/device/SConscript +++ b/bsp/frdm-k64f/device/SConscript @@ -21,7 +21,7 @@ elif rtconfig.CROSS_TOOL == 'keil': CPPDEFINES = ['CPU_MK64FN1M0VLL12'] -group = DefineGroup('Device', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) #CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/gkipc/armv6/SConscript b/bsp/gkipc/armv6/SConscript index d0a05be403..04f6bb5a4f 100644 --- a/bsp/gkipc/armv6/SConscript +++ b/bsp/gkipc/armv6/SConscript @@ -5,6 +5,6 @@ src = Glob('*.c') src += Glob('*.s') path = [cwd, cwd + '../../../include', cwd + '/../libraries/inc', cwd + '/../drivers'] -group = DefineGroup('armv6', src, depend = [''], CPPPATH = path) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/gkipc/libraries/drv/7102C/gd/SConscript b/bsp/gkipc/libraries/drv/7102C/gd/SConscript index 70fd17741b..35c70dc595 100644 --- a/bsp/gkipc/libraries/drv/7102C/gd/SConscript +++ b/bsp/gkipc/libraries/drv/7102C/gd/SConscript @@ -7,7 +7,7 @@ path = [cwd + '/inc'] libcwd = str(Dir('#')) libinspath = libcwd + '/libraries/lib' -group = DefineGroup('gd', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) list = os.listdir(cwd) for d in list: diff --git a/bsp/gkipc/libraries/drv/7102C/gd/src/SConscript b/bsp/gkipc/libraries/drv/7102C/gd/src/SConscript index e1f3a4ae03..1b6bf54f09 100644 --- a/bsp/gkipc/libraries/drv/7102C/gd/src/SConscript +++ b/bsp/gkipc/libraries/drv/7102C/gd/src/SConscript @@ -39,6 +39,6 @@ src += ['wdog/gd_wdog.c'] path = [cwd, cwd + '/../inc'] -group = DefineGroup('gd', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') \ No newline at end of file diff --git a/bsp/gkipc/libraries/drv/7102C/gh/SConscript b/bsp/gkipc/libraries/drv/7102C/gh/SConscript index a765cdd5a1..c8786e9e35 100644 --- a/bsp/gkipc/libraries/drv/7102C/gh/SConscript +++ b/bsp/gkipc/libraries/drv/7102C/gh/SConscript @@ -9,7 +9,7 @@ libinspath = libcwd + '/libraries/lib' CPPDEFINES = ['-DDEBUG'] -group = DefineGroup('gh', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES, LIBINSPATH = libinspath) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES, LIBINSPATH = libinspath) list = os.listdir(cwd) for d in list: diff --git a/bsp/gkipc/libraries/drv/7102C/gh/src/SConscript b/bsp/gkipc/libraries/drv/7102C/gh/src/SConscript index 47f86eb9c6..d680a24896 100644 --- a/bsp/gkipc/libraries/drv/7102C/gh/src/SConscript +++ b/bsp/gkipc/libraries/drv/7102C/gh/src/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') path = [cwd + '/../inc'] -group = DefineGroup('gh', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/gkipc/libraries/drv/710X/gd/SConscript b/bsp/gkipc/libraries/drv/710X/gd/SConscript index 70fd17741b..35c70dc595 100644 --- a/bsp/gkipc/libraries/drv/710X/gd/SConscript +++ b/bsp/gkipc/libraries/drv/710X/gd/SConscript @@ -7,7 +7,7 @@ path = [cwd + '/inc'] libcwd = str(Dir('#')) libinspath = libcwd + '/libraries/lib' -group = DefineGroup('gd', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) list = os.listdir(cwd) for d in list: diff --git a/bsp/gkipc/libraries/drv/710X/gd/src/SConscript b/bsp/gkipc/libraries/drv/710X/gd/src/SConscript index 887201dc04..122ae14245 100644 --- a/bsp/gkipc/libraries/drv/710X/gd/src/SConscript +++ b/bsp/gkipc/libraries/drv/710X/gd/src/SConscript @@ -40,6 +40,6 @@ src += ['wdog/gd_wdog.c'] path = [cwd, cwd + '/../inc', cwd + '/..'] -group = DefineGroup('gd', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') \ No newline at end of file diff --git a/bsp/gkipc/libraries/drv/710X/gh/SConscript b/bsp/gkipc/libraries/drv/710X/gh/SConscript index e05ccbc4d0..35c70dc595 100644 --- a/bsp/gkipc/libraries/drv/710X/gh/SConscript +++ b/bsp/gkipc/libraries/drv/710X/gh/SConscript @@ -7,7 +7,7 @@ path = [cwd + '/inc'] libcwd = str(Dir('#')) libinspath = libcwd + '/libraries/lib' -group = DefineGroup('gh', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) list = os.listdir(cwd) for d in list: diff --git a/bsp/gkipc/libraries/drv/710X/gh/src/SConscript b/bsp/gkipc/libraries/drv/710X/gh/src/SConscript index 745ab34c86..5b01077a5c 100644 --- a/bsp/gkipc/libraries/drv/710X/gh/src/SConscript +++ b/bsp/gkipc/libraries/drv/710X/gh/src/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') path = [cwd + '/..', cwd + '/../inc', cwd + '/../../inc'] -group = DefineGroup('gh', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/gkipc/libraries/drv/710XS/gd/SConscript b/bsp/gkipc/libraries/drv/710XS/gd/SConscript index 70fd17741b..35c70dc595 100644 --- a/bsp/gkipc/libraries/drv/710XS/gd/SConscript +++ b/bsp/gkipc/libraries/drv/710XS/gd/SConscript @@ -7,7 +7,7 @@ path = [cwd + '/inc'] libcwd = str(Dir('#')) libinspath = libcwd + '/libraries/lib' -group = DefineGroup('gd', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) list = os.listdir(cwd) for d in list: diff --git a/bsp/gkipc/libraries/drv/710XS/gd/src/SConscript b/bsp/gkipc/libraries/drv/710XS/gd/src/SConscript index ac7155aa86..2d377de096 100644 --- a/bsp/gkipc/libraries/drv/710XS/gd/src/SConscript +++ b/bsp/gkipc/libraries/drv/710XS/gd/src/SConscript @@ -40,6 +40,6 @@ src += ['wdog/gd_wdog.c'] path = [cwd, cwd + '/../inc', cwd + '/..'] -group = DefineGroup('gd', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') \ No newline at end of file diff --git a/bsp/gkipc/libraries/drv/710XS/gh/SConscript b/bsp/gkipc/libraries/drv/710XS/gh/SConscript index e05ccbc4d0..35c70dc595 100644 --- a/bsp/gkipc/libraries/drv/710XS/gh/SConscript +++ b/bsp/gkipc/libraries/drv/710XS/gh/SConscript @@ -7,7 +7,7 @@ path = [cwd + '/inc'] libcwd = str(Dir('#')) libinspath = libcwd + '/libraries/lib' -group = DefineGroup('gh', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) list = os.listdir(cwd) for d in list: diff --git a/bsp/gkipc/libraries/drv/710XS/gh/src/SConscript b/bsp/gkipc/libraries/drv/710XS/gh/src/SConscript index 745ab34c86..5b01077a5c 100644 --- a/bsp/gkipc/libraries/drv/710XS/gh/src/SConscript +++ b/bsp/gkipc/libraries/drv/710XS/gh/src/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') path = [cwd + '/..', cwd + '/../inc', cwd + '/../../inc'] -group = DefineGroup('gh', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/gkipc/libraries/drv/gnu_c/SConscript b/bsp/gkipc/libraries/drv/gnu_c/SConscript index 3f500d3d4c..28ed3cc028 100644 --- a/bsp/gkipc/libraries/drv/gnu_c/SConscript +++ b/bsp/gkipc/libraries/drv/gnu_c/SConscript @@ -8,6 +8,6 @@ path = [cwd] libcwd = str(Dir('#')) libinspath = libcwd + '/libraries/lib' -group = DefineGroup('gnu_c', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, LIBINSPATH = libinspath) Return('group') diff --git a/bsp/gkipc/platform/SConscript b/bsp/gkipc/platform/SConscript index ff0e7d4169..2f71b73c25 100644 --- a/bsp/gkipc/platform/SConscript +++ b/bsp/gkipc/platform/SConscript @@ -18,6 +18,6 @@ elif GetDepend('BOARD_GK7102S_HZD_JXH42'): elif GetDepend('BOARD_GK7102C_JH'): CPPDEFINES += ['-DGK7102C_JH'] -group = DefineGroup('platform', src, depend = [''], CPPDEFINES = CPPDEFINES) +group = DefineGroup('Drivers', src, depend = [''], CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/imx6sx/cortex-a9/cpu/SConscript b/bsp/imx6sx/cortex-a9/cpu/SConscript index 61057c04cc..b45f95cc1a 100644 --- a/bsp/imx6sx/cortex-a9/cpu/SConscript +++ b/bsp/imx6sx/cortex-a9/cpu/SConscript @@ -12,6 +12,6 @@ elif rtconfig.PLATFORM == 'gcc': elif rtconfig.PLATFORM == 'armcc': src += Glob('*_rvds.S') -group = DefineGroup('AM335x', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/k210/driver/camera/SConscript b/bsp/k210/driver/camera/SConscript index cc83372570..1a80075428 100644 --- a/bsp/k210/driver/camera/SConscript +++ b/bsp/k210/driver/camera/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('camera', src, depend = ['BSP_USING_CAMERA'], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = ['BSP_USING_CAMERA'], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/nrf51822/Libraries/SConscript b/bsp/nrf51822/Libraries/SConscript index 688d7e4ddc..1fd979844b 100644 --- a/bsp/nrf51822/Libraries/SConscript +++ b/bsp/nrf51822/Libraries/SConscript @@ -22,6 +22,6 @@ path = [cwd + '/CMSIS/Include', cwd + '/nrf51822/Include'] CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'NRF51'] -group = DefineGroup('Startup Code', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/nrf52832/board/Sconscript b/bsp/nrf52832/board/Sconscript index aa1e87d860..eb2a45b9ca 100644 --- a/bsp/nrf52832/board/Sconscript +++ b/bsp/nrf52832/board/Sconscript @@ -9,6 +9,6 @@ CPPPATH = [cwd] #remove other no use files #SrcRemove(src, '*.c') -group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') \ No newline at end of file diff --git a/bsp/nrf52832/startups/Sconscript b/bsp/nrf52832/startups/Sconscript index 91c4983ebe..f28b14aae1 100644 --- a/bsp/nrf52832/startups/Sconscript +++ b/bsp/nrf52832/startups/Sconscript @@ -11,6 +11,6 @@ CPPPATH = [cwd] #remove other no use files #SrcRemove(src, '*.c') -group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') \ No newline at end of file diff --git a/bsp/nuvoton/libraries/m480/Device/SConscript b/bsp/nuvoton/libraries/m480/Device/SConscript index 26e69fb824..f86894377b 100644 --- a/bsp/nuvoton/libraries/m480/Device/SConscript +++ b/bsp/nuvoton/libraries/m480/Device/SConscript @@ -20,6 +20,6 @@ elif rtconfig.CROSS_TOOL == 'iar': path = [cwd + '/Nuvoton/M480/Include',] -group = DefineGroup('m480_device', src, depend = [''], CPPPATH = path) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) Return('group') diff --git a/bsp/nuvoton/libraries/m480/StdDriver/SConscript b/bsp/nuvoton/libraries/m480/StdDriver/SConscript index 6a932cff58..57025d2246 100644 --- a/bsp/nuvoton/libraries/m480/StdDriver/SConscript +++ b/bsp/nuvoton/libraries/m480/StdDriver/SConscript @@ -20,9 +20,9 @@ if not GetDepend('BSP_USE_STDDRIVER_SOURCE'): libs += ['libstddriver_iar'] if not libs: - group = DefineGroup('m480_stddriver', src, depend = [''], CPPPATH = cpppath) + group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath) else: src = [] - group = DefineGroup('m480_stddriver', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath) + group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath) Return('group') diff --git a/bsp/nuvoton/libraries/m480/rtt_port/SConscript b/bsp/nuvoton/libraries/m480/rtt_port/SConscript index a155044a30..77bd290714 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/SConscript +++ b/bsp/nuvoton/libraries/m480/rtt_port/SConscript @@ -30,6 +30,6 @@ elif GetDepend('BOARD_USING_HSOTG') and ( GetDepend('BSP_USING_USBD') or GetDepe print '[Hint] You already select BOARD_USING_HSOTG. Please de-select BSP_USING_USBD and BSP_USING_USBH options.' sys.exit(1) else: - group = DefineGroup('m480_rttport', src, depend = [''], CPPPATH = CPPPATH) + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/nuvoton/numaker-iot-m487/board/SConscript b/bsp/nuvoton/numaker-iot-m487/board/SConscript index 6ed8f178ba..1cea397523 100644 --- a/bsp/nuvoton/numaker-iot-m487/board/SConscript +++ b/bsp/nuvoton/numaker-iot-m487/board/SConscript @@ -15,6 +15,6 @@ NuPinConfig/nutool_pincfg.c src += Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd, cwd + '/NuClockConfig', cwd + '/NuPinConfig'] -group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/nuvoton/numaker-pfm-m487/board/SConscript b/bsp/nuvoton/numaker-pfm-m487/board/SConscript index 6ed8f178ba..1cea397523 100644 --- a/bsp/nuvoton/numaker-pfm-m487/board/SConscript +++ b/bsp/nuvoton/numaker-pfm-m487/board/SConscript @@ -15,6 +15,6 @@ NuPinConfig/nutool_pincfg.c src += Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd, cwd + '/NuClockConfig', cwd + '/NuPinConfig'] -group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/qemu-vexpress-a9/drivers/audio/SConscript b/bsp/qemu-vexpress-a9/drivers/audio/SConscript index 2118631608..9fc2acc604 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/SConscript +++ b/bsp/qemu-vexpress-a9/drivers/audio/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('drv_audio', src, depend = ['BSP_DRV_AUDIO'], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = ['BSP_DRV_AUDIO'], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/qemu-vexpress-gemini/cpu/SConscript b/bsp/qemu-vexpress-gemini/cpu/SConscript index 61057c04cc..b45f95cc1a 100644 --- a/bsp/qemu-vexpress-gemini/cpu/SConscript +++ b/bsp/qemu-vexpress-gemini/cpu/SConscript @@ -12,6 +12,6 @@ elif rtconfig.PLATFORM == 'gcc': elif rtconfig.PLATFORM == 'armcc': src += Glob('*_rvds.S') -group = DefineGroup('AM335x', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/raspberry-pi/raspi2/cpu/SConscript b/bsp/raspberry-pi/raspi2/cpu/SConscript index 2a8b3869a4..fbfee70b01 100644 --- a/bsp/raspberry-pi/raspi2/cpu/SConscript +++ b/bsp/raspberry-pi/raspi2/cpu/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/raspberry-pi/raspi3-32/cpu/SConscript b/bsp/raspberry-pi/raspi3-32/cpu/SConscript index 2a8b3869a4..fbfee70b01 100644 --- a/bsp/raspberry-pi/raspi3-32/cpu/SConscript +++ b/bsp/raspberry-pi/raspi3-32/cpu/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/samd21/board/SConscript b/bsp/samd21/board/SConscript index ea79ebb925..5001f5d8bb 100644 --- a/bsp/samd21/board/SConscript +++ b/bsp/samd21/board/SConscript @@ -15,6 +15,6 @@ if rtconfig.DEVICE_SERIES == 'SAMD20': elif rtconfig.DEVICE_SERIES == 'SAMD21': path += [cwd + '/../asflib_config', cwd + '/../asflib_config/clock_samd21_r21_da_ha1'] -group = DefineGroup('Board', src, depend = [''], CPPPATH = path) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) Return('group') diff --git a/components/dfs/SConscript b/components/dfs/SConscript index edfd4e42b5..3ccaeb1080 100644 --- a/components/dfs/SConscript +++ b/components/dfs/SConscript @@ -13,7 +13,7 @@ CPPPATH = [cwd + "/include"] if GetDepend('RT_USING_POSIX'): src += ['src/poll.c', 'src/select.c'] -group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS'], CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS'], CPPPATH = CPPPATH) if GetDepend('RT_USING_DFS'): # search in the file system implementation diff --git a/components/dfs/filesystems/devfs/SConscript b/components/dfs/filesystems/devfs/SConscript index a2c0d843f0..898b04a234 100644 --- a/components/dfs/filesystems/devfs/SConscript +++ b/components/dfs/filesystems/devfs/SConscript @@ -6,6 +6,6 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_DEVFS'], CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_DEVFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/elmfat/SConscript b/components/dfs/filesystems/elmfat/SConscript index 173c0a9d65..8b7ec02d43 100644 --- a/components/dfs/filesystems/elmfat/SConscript +++ b/components/dfs/filesystems/elmfat/SConscript @@ -21,6 +21,6 @@ if GetDepend('RT_DFS_ELM_USE_LFN'): else: src += ['option/ccsbcs.c'] -group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_ELMFAT'], CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_ELMFAT'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/jffs2/SConscript b/components/dfs/filesystems/jffs2/SConscript index 85d3a4d8d2..47854393e3 100644 --- a/components/dfs/filesystems/jffs2/SConscript +++ b/components/dfs/filesystems/jffs2/SConscript @@ -45,6 +45,6 @@ src/write.c CPPPATH = [cwd, cwd + '/include', cwd + '/src', cwd + '/cyg', cwd + '/kernel', cwd + '/cyg/compress'] -group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_JFFS2'], CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_JFFS2'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/nfs/SConscript b/components/dfs/filesystems/nfs/SConscript index b340d36de2..f830dfc754 100644 --- a/components/dfs/filesystems/nfs/SConscript +++ b/components/dfs/filesystems/nfs/SConscript @@ -8,6 +8,6 @@ CPPPATH = [cwd] SrcRemove(src, ['rpc/auth_none.c']) -group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_NFS'], CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_NFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/ramfs/SConscript b/components/dfs/filesystems/ramfs/SConscript index 12977adf53..1304f59629 100644 --- a/components/dfs/filesystems/ramfs/SConscript +++ b/components/dfs/filesystems/ramfs/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS', 'RT_USING_MEMHEAP', 'RT_USING_DFS_RAMFS'], CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_MEMHEAP', 'RT_USING_DFS_RAMFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/romfs/SConscript b/components/dfs/filesystems/romfs/SConscript index d31941eb8a..bfd633ce91 100644 --- a/components/dfs/filesystems/romfs/SConscript +++ b/components/dfs/filesystems/romfs/SConscript @@ -10,6 +10,6 @@ if GetDepend('DFS_ROMFS_ROOT'): # A new ROMFS root has been defined, we should remove the romfs.c SrcRemove(src, ['romfs.c']) -group = DefineGroup('FileSystem', src, depend = ['RT_USING_DFS','RT_USING_DFS_ROMFS'], CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS','RT_USING_DFS_ROMFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/dfs/filesystems/uffs/SConscript b/components/dfs/filesystems/uffs/SConscript index 1ccd4a6869..53f7713fc2 100644 --- a/components/dfs/filesystems/uffs/SConscript +++ b/components/dfs/filesystems/uffs/SConscript @@ -33,6 +33,6 @@ src = src + uffs CPPPATH = [cwd, cwd + '/src/inc'] -group = DefineGroup('FileSystem', src , depend = ['RT_USING_DFS', 'RT_USING_DFS_UFFS'], CPPPATH = CPPPATH) +group = DefineGroup('Filesystem', src , depend = ['RT_USING_DFS', 'RT_USING_DFS_UFFS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/drivers/sensors/SConscript b/components/drivers/sensors/SConscript index 51c4b50eef..b56ae5ce6e 100644 --- a/components/drivers/sensors/SConscript +++ b/components/drivers/sensors/SConscript @@ -7,7 +7,7 @@ src = ['sensor.c'] CPPPATH = [cwd, cwd + '/../include'] if GetDepend('RT_USING_SENSOR_CMD'): - src += ['sensor_cmd.c']; + src += ['sensor_cmd.c'] group = DefineGroup('Sensors', src, depend = ['RT_USING_SENSOR', 'RT_USING_DEVICE'], CPPPATH = CPPPATH) diff --git a/components/drivers/touch/SConscript b/components/drivers/touch/SConscript index f370b2aba6..6c2a126c9c 100644 --- a/components/drivers/touch/SConscript +++ b/components/drivers/touch/SConscript @@ -6,6 +6,6 @@ cwd = GetCurrentDir() src = ['touch.c'] CPPPATH = [cwd, cwd + '/../include'] -group = DefineGroup('Touch', src, depend = ['RT_USING_TOUCH', 'RT_USING_DEVICE'], CPPPATH = CPPPATH) +group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_TOUCH', 'RT_USING_DEVICE'], CPPPATH = CPPPATH) Return('group') diff --git a/components/finsh/SConscript b/components/finsh/SConscript index 706165a47e..be04c56616 100644 --- a/components/finsh/SConscript +++ b/components/finsh/SConscript @@ -34,6 +34,6 @@ if not GetDepend('FINSH_USING_MSH_ONLY'): CPPPATH = [cwd] -group = DefineGroup('FinSH', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH) +group = DefineGroup('finsh', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/aio/SConscript b/components/libc/aio/SConscript index 175767100a..f10462e9c4 100644 --- a/components/libc/aio/SConscript +++ b/components/libc/aio/SConscript @@ -6,6 +6,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('aio', src, depend = ['RT_USING_POSIX', 'RT_USING_POSIX_AIO'], CPPPATH = CPPPATH) +group = DefineGroup('libc', src, depend = ['RT_USING_POSIX', 'RT_USING_POSIX_AIO'], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/compilers/armlibc/SConscript b/components/libc/compilers/armlibc/SConscript index 5f8f65a563..52f7a6d93a 100644 --- a/components/libc/compilers/armlibc/SConscript +++ b/components/libc/compilers/armlibc/SConscript @@ -15,7 +15,7 @@ if GetDepend('RT_USING_MODULE') == False: SrcRemove(src, ['libc_syms.c']) if rtconfig.PLATFORM == 'armcc' or rtconfig.PLATFORM == 'armclang': - group = DefineGroup('LIBC', src, depend = ['RT_USING_LIBC'], + group = DefineGroup('libc', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/compilers/common/SConscript b/components/libc/compilers/common/SConscript index f661a1ee0d..2407301405 100644 --- a/components/libc/compilers/common/SConscript +++ b/components/libc/compilers/common/SConscript @@ -17,6 +17,6 @@ if GetDepend('RT_USING_POSIX') == False: SrcRemove(src, ['unistd.c']) if not GetDepend('RT_USING_MINILIBC') and (GetDepend('RT_USING_LIBC') or GetDepend('RT_LIBC_USING_TIME')): - group = DefineGroup('LIBC', src, depend = [''], CPPPATH = CPPPATH) + group = DefineGroup('libc', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/components/libc/compilers/dlib/SConscript b/components/libc/compilers/dlib/SConscript index 456b762496..75a5812fab 100644 --- a/components/libc/compilers/dlib/SConscript +++ b/components/libc/compilers/dlib/SConscript @@ -20,7 +20,7 @@ if rtconfig.PLATFORM == 'iar': if LooseVersion(IARVersion()) < LooseVersion("8.20.1"): CPPDEFINES = CPPDEFINES + ['_DLIB_THREAD_SUPPORT'] - group = DefineGroup('dlib', src, depend = ['RT_USING_LIBC'], + group = DefineGroup('libc', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/compilers/minilibc/SConscript b/components/libc/compilers/minilibc/SConscript index cdaf9ec32b..dec657028f 100644 --- a/components/libc/compilers/minilibc/SConscript +++ b/components/libc/compilers/minilibc/SConscript @@ -9,7 +9,7 @@ CPPPATH = [cwd] CPPDEFINES = ['RT_USING_MINILIBC'] if rtconfig.PLATFORM == 'gcc' and rtconfig.ARCH != 'sim' and not GetDepend('RT_USING_LIBC') and GetDepend('RT_USING_MINILIBC'): - group = DefineGroup('LIBC', src, depend = [''], + group = DefineGroup('libc', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/compilers/newlib/SConscript b/components/libc/compilers/newlib/SConscript index 11de59bec4..d0868bbdea 100644 --- a/components/libc/compilers/newlib/SConscript +++ b/components/libc/compilers/newlib/SConscript @@ -15,7 +15,7 @@ CPPDEFINES = ['RT_USING_NEWLIB'] LIBS = ['c', 'm'] if rtconfig.PLATFORM == 'gcc': - group = DefineGroup('NewLIB', src, depend = ['RT_USING_LIBC'], + group = DefineGroup('libc', src, depend = ['RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LIBS = LIBS) Return('group') diff --git a/components/libc/getline/SConscript b/components/libc/getline/SConscript index 6c9a2a164c..fa4c8618c1 100644 --- a/components/libc/getline/SConscript +++ b/components/libc/getline/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('LIBC', src, +group = DefineGroup('libc', src, depend = ['RT_USING_LIBC', 'RT_USING_POSIX','RT_USING_POSIX_GETLINE'], CPPPATH = CPPPATH) diff --git a/components/libc/libdl/SConscript b/components/libc/libdl/SConscript index 28265521f6..93636e4b7a 100644 --- a/components/libc/libdl/SConscript +++ b/components/libc/libdl/SConscript @@ -7,7 +7,7 @@ group = [] CPPPATH = [cwd] if rtconfig.PLATFORM == 'gcc': - group = DefineGroup('LIBC', src, + group = DefineGroup('libc', src, depend = ['RT_USING_MODULE'], CPPPATH = CPPPATH) diff --git a/components/libc/mmap/SConscript b/components/libc/mmap/SConscript index 53036ad436..1a36a15710 100644 --- a/components/libc/mmap/SConscript +++ b/components/libc/mmap/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('LIBC', src, +group = DefineGroup('libc', src, depend = ['RT_USING_DFS', 'RT_USING_POSIX_MMAP'], CPPPATH = CPPPATH) diff --git a/components/libc/pthreads/SConscript b/components/libc/pthreads/SConscript index dff99aa01d..767b406d4c 100644 --- a/components/libc/pthreads/SConscript +++ b/components/libc/pthreads/SConscript @@ -16,7 +16,7 @@ try: except : pass -group = DefineGroup('Pthreads', src, +group = DefineGroup('libc', src, depend = ['RT_USING_PTHREADS', 'RT_USING_LIBC'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/components/libc/signal/SConscript b/components/libc/signal/SConscript index f32a1221ea..f07ff58f6e 100644 --- a/components/libc/signal/SConscript +++ b/components/libc/signal/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('LIBC', src, +group = DefineGroup('libc', src, depend = ['RT_USING_SIGNALS', 'RT_USING_PTHREADS', 'RT_USING_LIBC'], CPPPATH = CPPPATH) diff --git a/components/libc/termios/SConscript b/components/libc/termios/SConscript index 4bd0a42eb8..381eb5ad8b 100644 --- a/components/libc/termios/SConscript +++ b/components/libc/termios/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('LIBC', src, +group = DefineGroup('libc', src, depend = ['RT_USING_LIBC', 'RT_USING_POSIX', 'RT_USING_POSIX_TERMIOS'], CPPPATH = CPPPATH) diff --git a/components/libc/time/SConscript b/components/libc/time/SConscript index 67d1824b9f..f7e6f7e8e9 100644 --- a/components/libc/time/SConscript +++ b/components/libc/time/SConscript @@ -6,7 +6,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -group = DefineGroup('Pthreads', src, +group = DefineGroup('libc', src, depend = ['RT_USING_PTHREADS'], CPPPATH = CPPPATH) Return('group') diff --git a/components/net/lwip-1.4.1/SConscript b/components/net/lwip-1.4.1/SConscript index 8e3a4cb9d4..848e2d8255 100644 --- a/components/net/lwip-1.4.1/SConscript +++ b/components/net/lwip-1.4.1/SConscript @@ -82,6 +82,6 @@ if GetDepend(['RT_LWIP_PPP']): if GetDepend(['RT_LWIP_USING_PING']): src += Glob('src/apps/ping/ping.c') -group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP141'], CPPPATH = path) +group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP141'], CPPPATH = path) Return('group') diff --git a/components/net/lwip-2.0.2/SConscript b/components/net/lwip-2.0.2/SConscript index 910ce63539..df04b42324 100644 --- a/components/net/lwip-2.0.2/SConscript +++ b/components/net/lwip-2.0.2/SConscript @@ -84,6 +84,6 @@ if GetDepend(['RT_USING_LWIP_IPV6']): if GetDepend(['RT_LWIP_USING_PING']): src += Glob('src/apps/ping/ping.c') -group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP202'], CPPPATH = path) +group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP202'], CPPPATH = path) Return('group') diff --git a/components/net/lwip-2.1.2/SConscript b/components/net/lwip-2.1.2/SConscript index 20afc37534..04f59167d5 100644 --- a/components/net/lwip-2.1.2/SConscript +++ b/components/net/lwip-2.1.2/SConscript @@ -260,6 +260,6 @@ if GetDepend(['RT_USING_LWIP_IPV6']): if GetDepend(['RT_LWIP_USING_PING']): src += lwipping_SRCS -group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP212'], CPPPATH = path) +group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'RT_USING_LWIP212'], CPPPATH = path) Return('group') diff --git a/components/net/lwip_dhcpd/SConscript b/components/net/lwip_dhcpd/SConscript index d4ef6da41c..16c673036a 100644 --- a/components/net/lwip_dhcpd/SConscript +++ b/components/net/lwip_dhcpd/SConscript @@ -9,6 +9,6 @@ else: CPPPATH = [cwd] -group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'LWIP_USING_DHCPD'], CPPPATH = CPPPATH) +group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'LWIP_USING_DHCPD'], CPPPATH = CPPPATH) Return('group') diff --git a/components/net/lwip_nat/SConscript b/components/net/lwip_nat/SConscript index ce684f677a..d8b95b1ce3 100644 --- a/components/net/lwip_nat/SConscript +++ b/components/net/lwip_nat/SConscript @@ -5,6 +5,6 @@ src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('LwIP', src, depend = ['RT_USING_LWIP', 'LWIP_USING_NAT'], CPPPATH = CPPPATH) +group = DefineGroup('lwIP', src, depend = ['RT_USING_LWIP', 'LWIP_USING_NAT'], CPPPATH = CPPPATH) Return('group') diff --git a/components/net/netdev/SConscript b/components/net/netdev/SConscript index 0db486b2de..ec1d2b2905 100644 --- a/components/net/netdev/SConscript +++ b/components/net/netdev/SConscript @@ -8,6 +8,6 @@ src = Glob('src/*.c') CPPPATH = [cwd + '/include'] -group = DefineGroup('NetDev', src, depend = ['RT_USING_NETDEV'], CPPPATH = CPPPATH) +group = DefineGroup('SAL', src, depend = ['RT_USING_NETDEV'], CPPPATH = CPPPATH) Return('group') diff --git a/components/utilities/utest/SConscript b/components/utilities/utest/SConscript index ea7efcfbc9..5d408ccbd0 100644 --- a/components/utilities/utest/SConscript +++ b/components/utilities/utest/SConscript @@ -3,6 +3,6 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('Utest', src, depend = ['RT_USING_UTEST'], CPPPATH = CPPPATH) +group = DefineGroup('UTest', src, depend = ['RT_USING_UTEST'], CPPPATH = CPPPATH) Return('group') diff --git a/examples/libc/SConscript b/examples/libc/SConscript index 547dd215b1..01a74356e7 100644 --- a/examples/libc/SConscript +++ b/examples/libc/SConscript @@ -1,6 +1,6 @@ from building import * src = Glob('*.c') -group = DefineGroup('LIBCTest', src, depend = ['RT_USING_NEWLIB', 'RT_USING_PTHREADS']) +group = DefineGroup('UTest', src, depend = ['RT_USING_NEWLIB', 'RT_USING_PTHREADS']) Return('group') diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript index 59378636fa..c51148525b 100644 --- a/libcpu/aarch64/common/SConscript +++ b/libcpu/aarch64/common/SConscript @@ -8,7 +8,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) # build for sub-directory list = os.listdir(cwd) diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript index 5f509fbf5b..0b74223c6f 100644 --- a/libcpu/aarch64/cortex-a53/SConscript +++ b/libcpu/aarch64/cortex-a53/SConscript @@ -8,6 +8,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/aarch64/cortex-a72/SConscript b/libcpu/aarch64/cortex-a72/SConscript index 5f509fbf5b..0b74223c6f 100644 --- a/libcpu/aarch64/cortex-a72/SConscript +++ b/libcpu/aarch64/cortex-a72/SConscript @@ -8,6 +8,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') CPPPATH = [cwd] -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arc/common/SConscript b/libcpu/arc/common/SConscript index 19604861f2..80c21d87eb 100644 --- a/libcpu/arc/common/SConscript +++ b/libcpu/arc/common/SConscript @@ -5,6 +5,6 @@ src = Glob('*.c') CPPPATH = [cwd] -group = DefineGroup('LIBARCH', src, depend = [], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arc/em/SConscript b/libcpu/arc/em/SConscript index 215749bea4..a52aa9b1e4 100644 --- a/libcpu/arc/em/SConscript +++ b/libcpu/arc/em/SConscript @@ -10,6 +10,6 @@ CPPPATH = [cwd] src += Glob('*.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/AT91SAM7S/SConscript b/libcpu/arm/AT91SAM7S/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/AT91SAM7S/SConscript +++ b/libcpu/arm/AT91SAM7S/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/AT91SAM7X/SConscript b/libcpu/arm/AT91SAM7X/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/AT91SAM7X/SConscript +++ b/libcpu/arm/AT91SAM7X/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/am335x/SConscript b/libcpu/arm/am335x/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/am335x/SConscript +++ b/libcpu/arm/am335x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/arm926/SConscript b/libcpu/arm/arm926/SConscript index 9bd0ddaf0a..2275af97d9 100644 --- a/libcpu/arm/arm926/SConscript +++ b/libcpu/arm/arm926/SConscript @@ -20,6 +20,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/arm/armv6/SConscript b/libcpu/arm/armv6/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/armv6/SConscript +++ b/libcpu/arm/armv6/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/common/SConscript b/libcpu/arm/common/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/common/SConscript +++ b/libcpu/arm/common/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/cortex-a/SConscript +++ b/libcpu/arm/cortex-a/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m0/SConscript b/libcpu/arm/cortex-m0/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/cortex-m0/SConscript +++ b/libcpu/arm/cortex-m0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m23/SConscript b/libcpu/arm/cortex-m23/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/cortex-m23/SConscript +++ b/libcpu/arm/cortex-m23/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m3/SConscript b/libcpu/arm/cortex-m3/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/cortex-m3/SConscript +++ b/libcpu/arm/cortex-m3/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m33/SConscript b/libcpu/arm/cortex-m33/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/cortex-m33/SConscript +++ b/libcpu/arm/cortex-m33/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m4/SConscript b/libcpu/arm/cortex-m4/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/cortex-m4/SConscript +++ b/libcpu/arm/cortex-m4/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-m7/SConscript b/libcpu/arm/cortex-m7/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/cortex-m7/SConscript +++ b/libcpu/arm/cortex-m7/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-r4/SConscript b/libcpu/arm/cortex-r4/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/cortex-r4/SConscript +++ b/libcpu/arm/cortex-r4/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/dm36x/SConscript b/libcpu/arm/dm36x/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/dm36x/SConscript +++ b/libcpu/arm/dm36x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/lpc214x/SConscript b/libcpu/arm/lpc214x/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/lpc214x/SConscript +++ b/libcpu/arm/lpc214x/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/lpc24xx/SConscript b/libcpu/arm/lpc24xx/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/lpc24xx/SConscript +++ b/libcpu/arm/lpc24xx/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/realview-a8-vmm/SConscript b/libcpu/arm/realview-a8-vmm/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/realview-a8-vmm/SConscript +++ b/libcpu/arm/realview-a8-vmm/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/s3c24x0/SConscript b/libcpu/arm/s3c24x0/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/s3c24x0/SConscript +++ b/libcpu/arm/s3c24x0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/s3c44b0/SConscript b/libcpu/arm/s3c44b0/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/s3c44b0/SConscript +++ b/libcpu/arm/s3c44b0/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/sep4020/SConscript b/libcpu/arm/sep4020/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/sep4020/SConscript +++ b/libcpu/arm/sep4020/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript index 990f753abd..28af7ba651 100644 --- a/libcpu/arm/zynq7000/SConscript +++ b/libcpu/arm/zynq7000/SConscript @@ -18,6 +18,6 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/avr32/uc3/SConscript b/libcpu/avr32/uc3/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/avr32/uc3/SConscript +++ b/libcpu/avr32/uc3/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/blackfin/bf53x/SConscript b/libcpu/blackfin/bf53x/SConscript index 5908a24142..85882caf6f 100644 --- a/libcpu/blackfin/bf53x/SConscript +++ b/libcpu/blackfin/bf53x/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_vdsp.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/c-sky/ck802/SConscript b/libcpu/c-sky/ck802/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/c-sky/ck802/SConscript +++ b/libcpu/c-sky/ck802/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/c-sky/common/SConscript b/libcpu/c-sky/common/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/c-sky/common/SConscript +++ b/libcpu/c-sky/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ia32/SConscript b/libcpu/ia32/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/ia32/SConscript +++ b/libcpu/ia32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/m16c/m16c62p/SConscript b/libcpu/m16c/m16c62p/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/m16c/m16c62p/SConscript +++ b/libcpu/m16c/m16c62p/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/common/SConscript b/libcpu/mips/common/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/mips/common/SConscript +++ b/libcpu/mips/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/gs232/SConscript b/libcpu/mips/gs232/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/mips/gs232/SConscript +++ b/libcpu/mips/gs232/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/gs264/SConscript b/libcpu/mips/gs264/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/mips/gs264/SConscript +++ b/libcpu/mips/gs264/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/mips/pic32/SConscript b/libcpu/mips/pic32/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/mips/pic32/SConscript +++ b/libcpu/mips/pic32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/nios/nios_ii/SConscript b/libcpu/nios/nios_ii/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/nios/nios_ii/SConscript +++ b/libcpu/nios/nios_ii/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ppc/common/SConscript b/libcpu/ppc/common/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/ppc/common/SConscript +++ b/libcpu/ppc/common/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/ppc/ppc405/SConscript b/libcpu/ppc/ppc405/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/ppc/ppc405/SConscript +++ b/libcpu/ppc/ppc405/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/bumblebee/SConscript b/libcpu/risc-v/bumblebee/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/risc-v/bumblebee/SConscript +++ b/libcpu/risc-v/bumblebee/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/common/SConscript b/libcpu/risc-v/common/SConscript index 08a1215daf..92133bfb47 100644 --- a/libcpu/risc-v/common/SConscript +++ b/libcpu/risc-v/common/SConscript @@ -7,6 +7,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/e310/SConscript b/libcpu/risc-v/e310/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/risc-v/e310/SConscript +++ b/libcpu/risc-v/e310/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/k210/SConscript b/libcpu/risc-v/k210/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/risc-v/k210/SConscript +++ b/libcpu/risc-v/k210/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/risc-v/nuclei/SConscript +++ b/libcpu/risc-v/nuclei/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/rv32m1/SConscript b/libcpu/risc-v/rv32m1/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/risc-v/rv32m1/SConscript +++ b/libcpu/risc-v/rv32m1/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/t-head/e906/SConscript b/libcpu/risc-v/t-head/e906/SConscript index 08a1215daf..92133bfb47 100644 --- a/libcpu/risc-v/t-head/e906/SConscript +++ b/libcpu/risc-v/t-head/e906/SConscript @@ -7,6 +7,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/rx/SConscript b/libcpu/rx/SConscript index 57ad8ba965..b7cb2f445a 100644 --- a/libcpu/rx/SConscript +++ b/libcpu/rx/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_iar.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sim/posix/SConscript b/libcpu/sim/posix/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/sim/posix/SConscript +++ b/libcpu/sim/posix/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sim/win32/SConscript b/libcpu/sim/win32/SConscript index 4488a0dbb5..530b5d1d78 100644 --- a/libcpu/sim/win32/SConscript +++ b/libcpu/sim/win32/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/sparc-v8/bm3803/SConscript b/libcpu/sparc-v8/bm3803/SConscript index 62648f9eeb..03ce583dc1 100644 --- a/libcpu/sparc-v8/bm3803/SConscript +++ b/libcpu/sparc-v8/bm3803/SConscript @@ -12,6 +12,6 @@ if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') src += Glob('*_gcc.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/sparc-v8/common/SConscript b/libcpu/sparc-v8/common/SConscript index 62648f9eeb..03ce583dc1 100644 --- a/libcpu/sparc-v8/common/SConscript +++ b/libcpu/sparc-v8/common/SConscript @@ -12,6 +12,6 @@ if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') src += Glob('*_gcc.S') -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/ti-dsp/c28x/SConscript b/libcpu/ti-dsp/c28x/SConscript index 2265bf3bee..760a715267 100644 --- a/libcpu/ti-dsp/c28x/SConscript +++ b/libcpu/ti-dsp/c28x/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*.s') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/unicore32/sep6200/SConscript b/libcpu/unicore32/sep6200/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/unicore32/sep6200/SConscript +++ b/libcpu/unicore32/sep6200/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/v850/70f34/SConscript b/libcpu/v850/70f34/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/v850/70f34/SConscript +++ b/libcpu/v850/70f34/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/xilinx/microblaze/SConscript b/libcpu/xilinx/microblaze/SConscript index da76d51366..20f325b692 100644 --- a/libcpu/xilinx/microblaze/SConscript +++ b/libcpu/xilinx/microblaze/SConscript @@ -9,6 +9,6 @@ src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] ASFLAGS = '' -group = DefineGroup('LIBARCH', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') -- cgit v1.3.1 From 76b6d7f90d07bb81a32953aae0f5b4c42e02c7a1 Mon Sep 17 00:00:00 2001 From: unknown Date: Wed, 23 Dec 2020 10:35:26 +0800 Subject: fix scheduler bug in simulator. --- libcpu/sim/win32/cpu_port.c | 22 ++++++++++++++++++++++ libcpu/sim/win32/cpu_port.h | 4 ++-- 2 files changed, 24 insertions(+), 2 deletions(-) (limited to 'libcpu') diff --git a/libcpu/sim/win32/cpu_port.c b/libcpu/sim/win32/cpu_port.c index 6bf3c79cf7..6caaa063aa 100644 --- a/libcpu/sim/win32/cpu_port.c +++ b/libcpu/sim/win32/cpu_port.c @@ -27,6 +27,8 @@ * The context switch is managed by the threads.So the task stack does not have to be managed directly, * although the stack stack is still used to hold an WinThreadState structure this is the only thing it * will be ever hold. +* YieldEvent used to make sure the thread does not execute before asynchronous SuspendThread() operation +* actually being performed. * the structure indirectly maps the task handle to a thread handle ********************************************************************************************************* */ @@ -35,6 +37,7 @@ typedef struct void *Param; //Thread param void (*Entry)(void *); //Thread entry void (*Exit)(void); //Thread exit + HANDLE YieldEvent; HANDLE ThreadHandle; DWORD ThreadID; }win_thread_t; @@ -171,6 +174,11 @@ rt_uint8_t* rt_hw_stack_init(void *pEntry,void *pParam,rt_uint8_t *pStackAddr,vo pWinThread->ThreadHandle = NULL; pWinThread->ThreadID = 0; + pWinThread->YieldEvent = CreateEvent(NULL, + FALSE, + FALSE, + NULL); + /* Create the winthread */ pWinThread->ThreadHandle = CreateThread(NULL, 0, @@ -277,6 +285,19 @@ void rt_hw_context_switch(rt_uint32_t from, //trigger YIELD exception(cause contex switch) TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); + // make sure the event is not already signaled + WinThread = (win_thread_t *)rt_interrupt_from_thread; + ResetEvent(WinThread->YieldEvent); + + /* + * enable interrupt in advance so that scheduler can be executed.please note that interrupt + * maybe disable twice before. + */ + rt_hw_interrupt_enable(0); + rt_hw_interrupt_enable(0); + + // wait to suspend. + WaitForSingleObject(WinThread->YieldEvent, INFINITE); } /*** rt_hw_context_switch ***/ /* @@ -578,6 +599,7 @@ void RegisterSimulateInterrupt(rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(vo if ((WinThreadFrom != NULL) && (WinThreadFrom->ThreadHandle != NULL)) { SuspendThread(WinThreadFrom->ThreadHandle); + SetEvent(WinThreadFrom->YieldEvent); } ResumeThread(WinThreadTo->ThreadHandle); diff --git a/libcpu/sim/win32/cpu_port.h b/libcpu/sim/win32/cpu_port.h index 8ab8ae23bd..cccdd48d42 100644 --- a/libcpu/sim/win32/cpu_port.h +++ b/libcpu/sim/win32/cpu_port.h @@ -17,8 +17,8 @@ * CPU INTERRUPT PRIORITY ********************************************************************************************************* */ -#define CPU_INTERRUPT_YIELD 0x00 -#define CPU_INTERRUPT_TICK 0x01 +#define CPU_INTERRUPT_YIELD 0x01 // should be set to the lowest priority. +#define CPU_INTERRUPT_TICK 0x00 -- cgit v1.3.1 From 82ae97e24898253c344a90ac21e4df04690304a4 Mon Sep 17 00:00:00 2001 From: unknown Date: Wed, 23 Dec 2020 11:13:46 +0800 Subject: fix build error --- libcpu/sim/win32/cpu_port.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'libcpu') diff --git a/libcpu/sim/win32/cpu_port.c b/libcpu/sim/win32/cpu_port.c index 6caaa063aa..cc8ad9a25c 100644 --- a/libcpu/sim/win32/cpu_port.c +++ b/libcpu/sim/win32/cpu_port.c @@ -286,7 +286,7 @@ void rt_hw_context_switch(rt_uint32_t from, TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); // make sure the event is not already signaled - WinThread = (win_thread_t *)rt_interrupt_from_thread; + win_thread_t *WinThread = (win_thread_t *)rt_interrupt_from_thread; ResetEvent(WinThread->YieldEvent); /* -- cgit v1.3.1 From 235296073ffcc53ad3c16d11ebd9367a02327cf8 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Tue, 12 Jan 2021 18:31:44 +0800 Subject: Remove platform-specific code in common. --- libcpu/arm/arm926/start_gcc.S | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) (limited to 'libcpu') diff --git a/libcpu/arm/arm926/start_gcc.S b/libcpu/arm/arm926/start_gcc.S index 35c1f1722e..658dcf8656 100644 --- a/libcpu/arm/arm926/start_gcc.S +++ b/libcpu/arm/arm926/start_gcc.S @@ -121,31 +121,7 @@ reset: /* init cpu */ bl cpu_init_crit - - /* todo:copyself to link address */ - - /* Copy vector to the correct address */ - ldr r0, =system_vectors - mrc p15, 0, r2, c1, c0, 0 - ands r2, r2, #(1 << 13) - ldreq r1, =0x00000000 - ldrne r1, =0xffff0000 - ldmia r0!, {r2-r8, r10} - stmia r1!, {r2-r8, r10} - ldmia r0!, {r2-r8, r10} - stmia r1!, {r2-r8, r10} - - /* turn off the watchdog */ - ldr r0, =0x01C20CB8 - mov r1, #0x0 - str r1, [r0] - - /* mask all IRQs source */ - ldr r1, =0xffffffff - ldr r0, =0x01C20430 - str r1, [r0], #0x04 - str r1, [r0] - + /* Call low level init function */ ldr sp, =svc_stack_start ldr r0, =rt_low_level_init -- cgit v1.3.1 From 0af3666882491d5336274ee37da9c564a0eca202 Mon Sep 17 00:00:00 2001 From: michael Date: Sun, 31 Jan 2021 21:53:00 +0800 Subject: remove unused function declarations --- libcpu/mips/gs232/interrupt.c | 1 - 1 file changed, 1 deletion(-) (limited to 'libcpu') diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c index f3e0f80763..66abea379d 100644 --- a/libcpu/mips/gs232/interrupt.c +++ b/libcpu/mips/gs232/interrupt.c @@ -22,7 +22,6 @@ #define MAX_INTR (GS232_NR_IRQS) static struct rt_irq_desc irq_handle_table[MAX_INTR]; -void rt_interrupt_dispatch(void *ptreg); void rt_hw_timer_handler(); static struct gs232_intc_regs volatile *gs232_hw0_icregs -- cgit v1.3.1 From d874ab11098e9384869db6ad4a86c5c5d65ca432 Mon Sep 17 00:00:00 2001 From: michael Date: Sun, 31 Jan 2021 21:56:30 +0800 Subject: mips:gs232:LS1C300 have 5 group INTC cells but LS1B have 4 group INTC cells --- bsp/ls1cdev/Kconfig | 2 +- bsp/ls1cdev/rtconfig.h | 2 +- libcpu/mips/gs232/gs232.h | 9 ++++++++- 3 files changed, 10 insertions(+), 3 deletions(-) (limited to 'libcpu') diff --git a/bsp/ls1cdev/Kconfig b/bsp/ls1cdev/Kconfig index 6cd2409db4..3fb6e3bbdf 100644 --- a/bsp/ls1cdev/Kconfig +++ b/bsp/ls1cdev/Kconfig @@ -19,7 +19,7 @@ source "$RTT_DIR/Kconfig" source "$RTT_DIR/libcpu/mips/common/Kconfig" source "$PKGS_DIR/Kconfig" -config SOC_1C300 +config SOC_LS1C300 bool select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN diff --git a/bsp/ls1cdev/rtconfig.h b/bsp/ls1cdev/rtconfig.h index a2bac5d6f0..55899c04e1 100644 --- a/bsp/ls1cdev/rtconfig.h +++ b/bsp/ls1cdev/rtconfig.h @@ -161,7 +161,7 @@ /* samples: kernel and components samples */ -#define SOC_1C300 +#define SOC_LS1C300 #define RT_LS1C_BAICAIBOARD #define RT_USING_SELF_BOOT #define RT_SELF_BOOT_DEBUG diff --git a/libcpu/mips/gs232/gs232.h b/libcpu/mips/gs232/gs232.h index 6e90f7ba66..95c81cf93e 100644 --- a/libcpu/mips/gs232/gs232.h +++ b/libcpu/mips/gs232/gs232.h @@ -17,7 +17,14 @@ #define INTC_BASE 0xBFD01040 +#ifdef SOC_LS1B +#define GS232_INTC_CELLS 4 +#endif + +#ifdef SOC_LS1C300 #define GS232_INTC_CELLS 5 +#endif + #define GS232_NR_IRQS (32 * GS232_INTC_CELLS) #define GMAC0_BASE 0xBFE10000 @@ -64,4 +71,4 @@ extern void rt_hw_timer_init(void); #endif -#endif \ No newline at end of file +#endif -- cgit v1.3.1 From 242530ae7017dbe0b5efae7796d6914c3c57f9ad Mon Sep 17 00:00:00 2001 From: michael Date: Sun, 31 Jan 2021 22:33:58 +0800 Subject: ls1b: fix the count of GPIO IRQ and improvement the IRQ of UARTS. from 1b manunal we know it have 64 GPIO IRQ and 12 UARTS --- libcpu/mips/gs232/ls1b.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'libcpu') diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h index 071a4aeb82..a6f244ef4f 100644 --- a/libcpu/mips/gs232/ls1b.h +++ b/libcpu/mips/gs232/ls1b.h @@ -19,6 +19,15 @@ #define LS1B_UART1_IRQ 3 #define LS1B_UART2_IRQ 4 #define LS1B_UART3_IRQ 5 +#define LS1B_UART4_IRQ 29 +#define LS1B_UART5_IRQ 30 +#define LS1B_UART6_IRQ 2 //共享LS1B_UART0_IRQ +#define LS1B_UART7_IRQ 2 +#define LS1B_UART8_IRQ 2 +#define LS1B_UART9_IRQ 3 //共享LS1B_UART1_IRQ +#define LS1B_UART10_IRQ 3 +#define LS1B_UART11_IRQ 3 + #define LS1B_CAN0_IRQ 6 #define LS1B_CAN1_IRQ 7 #define LS1B_SPI0_IRQ 8 @@ -49,7 +58,7 @@ #define LS1B_GPIO_IRQ 64 #define LS1B_GPIO_FIRST_IRQ 64 -#define LS1B_GPIO_IRQ_COUNT 96 +#define LS1B_GPIO_IRQ_COUNT 64 #define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) #define INT_PCI_INTA (1<<6) -- cgit v1.3.1 From 2e9fc0c4ff6fadd62faac32a2604430b1c8a0ae3 Mon Sep 17 00:00:00 2001 From: tangyuxin Date: Mon, 1 Feb 2021 16:53:39 +0800 Subject: [libcpu][cm33] 安全相关的函数使用宏进行隔离 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/arm/cortex-m33/trustzone.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'libcpu') diff --git a/libcpu/arm/cortex-m33/trustzone.c b/libcpu/arm/cortex-m33/trustzone.c index 86654a7199..5f37ddbb8f 100644 --- a/libcpu/arm/cortex-m33/trustzone.c +++ b/libcpu/arm/cortex-m33/trustzone.c @@ -10,11 +10,19 @@ #include +#ifdef ARM_CM33_ENABLE_TRUSTZONE extern void TZ_InitContextSystem_S(void); extern rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module); extern rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id); extern rt_uint32_t TZ_LoadContext_S(rt_uint32_t id); extern rt_uint32_t TZ_StoreContext_S(rt_uint32_t id); +#else +void TZ_InitContextSystem_S(void){} +rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module){return 0;} +rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id) {return 0;} +rt_uint32_t TZ_LoadContext_S(rt_uint32_t id){return 0;}; +rt_uint32_t TZ_StoreContext_S(rt_uint32_t id){return 0;}; +#endif extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); #define TZ_INIT_CONTEXT_ID (0x1001) -- cgit v1.3.1 From 64bd41d6540bc074d3a020b445da664f1067d4bb Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Sun, 7 Feb 2021 21:17:27 +0800 Subject: update --- libcpu/arm/s3c24x0/rtc.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'libcpu') diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index d0c80bce6b..3b4c479001 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include // #define RTC_DEBUG @@ -132,17 +132,17 @@ static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) time = (time_t *)args; switch (cmd) { - case RT_DEVICE_CTRL_RTC_GET_TIME: - /* read device */ - rt_hw_rtc_get(&tm); - *((rt_time_t *)args) = mktime(&tm); - break; - - case RT_DEVICE_CTRL_RTC_SET_TIME: - tm_ptr = localtime(time); - /* write device */ - rt_hw_rtc_set(tm_ptr); - break; + case RT_DEVICE_CTRL_RTC_GET_TIME: + /* read device */ + rt_hw_rtc_get(&tm); + *((rt_time_t *)args) = mktime(&tm); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + tm_ptr = localtime(time); + /* write device */ + rt_hw_rtc_set(tm_ptr); + break; } return RT_EOK; -- cgit v1.3.1 From 86ebf17a2360de740219cf9a5441cb72629c5a1d Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Sun, 7 Feb 2021 21:49:25 +0800 Subject: localtim改为gmtime MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/apollo2/board/rtc.c | 2 +- bsp/at32/Libraries/rt_drivers/drv_rtc.c | 2 +- bsp/essemi/es32f0271/drivers/drv_rtc.c | 2 +- bsp/essemi/es32f0334/drivers/drv_rtc.c | 2 +- bsp/essemi/es32f0654/drivers/drv_rtc.c | 2 +- bsp/essemi/es32f369x/drivers/drv_rtc.c | 2 +- bsp/hc32f4a0/drivers/drv_rtc.c | 2 +- bsp/imxrt/libraries/drivers/drv_rtc.c | 2 +- bsp/lpc55sxx/Libraries/drivers/drv_rtc.c | 2 +- bsp/ls1cdev/drivers/drv_rtc.c | 2 +- bsp/ls2kdev/drivers/drv_rtc.c | 2 +- bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c | 2 +- bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c | 2 +- bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c | 2 +- bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c | 2 +- bsp/stm32f20x/Drivers/drv_rtc.c | 2 +- bsp/swm320-lq100/drivers/drv_rtc.c | 2 +- bsp/w60x/drivers/drv_rtc.c | 4 ++-- components/dfs/filesystems/elmfat/dfs_elm.c | 2 +- libcpu/arm/s3c24x0/rtc.c | 18 +++++++++--------- 20 files changed, 29 insertions(+), 29 deletions(-) (limited to 'libcpu') diff --git a/bsp/apollo2/board/rtc.c b/bsp/apollo2/board/rtc.c index 3d2e1c8e7a..dbae7cf3c1 100644 --- a/bsp/apollo2/board/rtc.c +++ b/bsp/apollo2/board/rtc.c @@ -85,7 +85,7 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) case RT_DEVICE_CTRL_RTC_SET_TIME: time = (time_t *)args; - time_new = localtime(time); + time_new = gmtime(time); hal_time.ui32Hour = time_new->tm_hour; hal_time.ui32Minute = time_new->tm_min; diff --git a/bsp/at32/Libraries/rt_drivers/drv_rtc.c b/bsp/at32/Libraries/rt_drivers/drv_rtc.c index 3ee2a61ec6..bd4d89a9ed 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_rtc.c +++ b/bsp/at32/Libraries/rt_drivers/drv_rtc.c @@ -57,7 +57,7 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) struct tm *p_tm; - p_tm = localtime(&time_stamp); + p_tm = gmtime(&time_stamp); if (p_tm->tm_year < 100) { return -RT_ERROR; diff --git a/bsp/essemi/es32f0271/drivers/drv_rtc.c b/bsp/essemi/es32f0271/drivers/drv_rtc.c index fa1582cb0f..3e2cdd17a3 100644 --- a/bsp/essemi/es32f0271/drivers/drv_rtc.c +++ b/bsp/essemi/es32f0271/drivers/drv_rtc.c @@ -104,7 +104,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) { rt_enter_critical(); /* converts calendar time time into local time. */ - pNow = localtime((const time_t *)args); + pNow = gmtime((const time_t *)args); /* copy the statically located variable */ memcpy(&time_temp, pNow, sizeof(struct tm)); /* unlock scheduler. */ diff --git a/bsp/essemi/es32f0334/drivers/drv_rtc.c b/bsp/essemi/es32f0334/drivers/drv_rtc.c index 9cde99c8c6..9471368454 100644 --- a/bsp/essemi/es32f0334/drivers/drv_rtc.c +++ b/bsp/essemi/es32f0334/drivers/drv_rtc.c @@ -67,7 +67,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) rt_enter_critical(); /* converts calendar time time into local time. */ - pNow = localtime((const time_t *)args); + pNow = gmtime((const time_t *)args); /* copy the statically located variable */ memcpy(&time_temp, pNow, sizeof(struct tm)); /* unlock scheduler. */ diff --git a/bsp/essemi/es32f0654/drivers/drv_rtc.c b/bsp/essemi/es32f0654/drivers/drv_rtc.c index 54f0d3294e..cab5b8b61b 100644 --- a/bsp/essemi/es32f0654/drivers/drv_rtc.c +++ b/bsp/essemi/es32f0654/drivers/drv_rtc.c @@ -67,7 +67,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) rt_enter_critical(); /* converts calendar time time into local time. */ - pNow = localtime((const time_t *)args); + pNow = gmtime((const time_t *)args); /* copy the statically located variable */ memcpy(&time_temp, pNow, sizeof(struct tm)); /* unlock scheduler. */ diff --git a/bsp/essemi/es32f369x/drivers/drv_rtc.c b/bsp/essemi/es32f369x/drivers/drv_rtc.c index 54f0d3294e..cab5b8b61b 100644 --- a/bsp/essemi/es32f369x/drivers/drv_rtc.c +++ b/bsp/essemi/es32f369x/drivers/drv_rtc.c @@ -67,7 +67,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) rt_enter_critical(); /* converts calendar time time into local time. */ - pNow = localtime((const time_t *)args); + pNow = gmtime((const time_t *)args); /* copy the statically located variable */ memcpy(&time_temp, pNow, sizeof(struct tm)); /* unlock scheduler. */ diff --git a/bsp/hc32f4a0/drivers/drv_rtc.c b/bsp/hc32f4a0/drivers/drv_rtc.c index 65d09fd559..27e3a665df 100644 --- a/bsp/hc32f4a0/drivers/drv_rtc.c +++ b/bsp/hc32f4a0/drivers/drv_rtc.c @@ -45,7 +45,7 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) stc_rtc_date_t stcRtcDate = {0}; struct tm *p_tm; - p_tm = localtime(&time_stamp); + p_tm = gmtime(&time_stamp); if (p_tm->tm_year < 100) { return -RT_ERROR; diff --git a/bsp/imxrt/libraries/drivers/drv_rtc.c b/bsp/imxrt/libraries/drivers/drv_rtc.c index 22a39ac37d..96ae1006fa 100644 --- a/bsp/imxrt/libraries/drivers/drv_rtc.c +++ b/bsp/imxrt/libraries/drivers/drv_rtc.c @@ -49,7 +49,7 @@ static int set_timestamp(time_t timestamp) struct tm *p_tm; snvs_hp_rtc_datetime_t rtcDate = {0}; - p_tm = localtime(×tamp); + p_tm = gmtime(×tamp); rtcDate.second = p_tm->tm_sec ; rtcDate.minute = p_tm->tm_min ; diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c index 00361a153a..c277d82079 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c @@ -46,7 +46,7 @@ static int set_timestamp(time_t timestamp) struct tm *p_tm; rtc_datetime_t rtcDate; - p_tm = localtime(×tamp); + p_tm = gmtime(×tamp); rtcDate.second = p_tm->tm_sec ; rtcDate.minute = p_tm->tm_min ; diff --git a/bsp/ls1cdev/drivers/drv_rtc.c b/bsp/ls1cdev/drivers/drv_rtc.c index 40153dc971..ef1398fe47 100644 --- a/bsp/ls1cdev/drivers/drv_rtc.c +++ b/bsp/ls1cdev/drivers/drv_rtc.c @@ -53,7 +53,7 @@ static int set_timestamp(time_t timestamp) struct tm *p_tm; RTC_TimeTypeDef rtcDate; - p_tm = localtime(×tamp); + p_tm = gmtime(×tamp); rtcDate.Seconds= p_tm->tm_sec ; rtcDate.Minutes= p_tm->tm_min ; diff --git a/bsp/ls2kdev/drivers/drv_rtc.c b/bsp/ls2kdev/drivers/drv_rtc.c index 06ae120f82..3cea0288be 100644 --- a/bsp/ls2kdev/drivers/drv_rtc.c +++ b/bsp/ls2kdev/drivers/drv_rtc.c @@ -128,7 +128,7 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args) hw_rtc = dev->user_data; t = (time_t *)args; - time = *localtime(t); + time = *gmtime(t); rtctm.sys_toyread0 = hw_rtc->sys_toyread0; rtctm.sys_toyread1 = hw_rtc->sys_toyread1; diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c index 37459b6ad1..a80ac79627 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c @@ -232,7 +232,7 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) case RT_DEVICE_CTRL_RTC_SET_TIME: time = (time_t *) args; - tm_in = localtime(time); + tm_in = gmtime(time); if (nu_rtc_is_date_valid(time) != RT_EOK) return RT_ERROR; diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c index 49ad03e1b8..49418316d1 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c @@ -233,7 +233,7 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) case RT_DEVICE_CTRL_RTC_SET_TIME: time = (time_t *) args; - tm_in = localtime(time); + tm_in = gmtime(time); if (nu_rtc_is_date_valid(time) != RT_EOK) return -(RT_ERROR); diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c index f69788b318..147504bd16 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c @@ -194,7 +194,7 @@ static time_t raspi_get_timestamp(void) static int raspi_set_timestamp(time_t timestamp) { struct tm *tblock; - tblock = localtime(×tamp); + tblock = gmtime(×tamp); buf[0] = 0; buf[1] = tblock->tm_sec; buf[2] = tblock->tm_min; diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c index 7383464513..18fd6474a2 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c @@ -41,7 +41,7 @@ static time_t raspi_get_timestamp(void) static int raspi_set_timestamp(time_t timestamp) { struct tm *tblock; - tblock = localtime(×tamp); + tblock = gmtime(×tamp); buf[0] = 0; buf[1] = tblock->tm_sec; buf[2] = tblock->tm_min; diff --git a/bsp/stm32f20x/Drivers/drv_rtc.c b/bsp/stm32f20x/Drivers/drv_rtc.c index 3c70a417d2..6078a15249 100644 --- a/bsp/stm32f20x/Drivers/drv_rtc.c +++ b/bsp/stm32f20x/Drivers/drv_rtc.c @@ -115,7 +115,7 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) /* Change the current time */ //RTC_SetCounter(*time); - to = localtime(time); + to = gmtime(time); RTC_TimeStructure.RTC_Seconds = to->tm_sec; RTC_TimeStructure.RTC_Minutes = to->tm_min; RTC_TimeStructure.RTC_Hours = to->tm_hour; diff --git a/bsp/swm320-lq100/drivers/drv_rtc.c b/bsp/swm320-lq100/drivers/drv_rtc.c index 1ec7d02417..5219a5b013 100644 --- a/bsp/swm320-lq100/drivers/drv_rtc.c +++ b/bsp/swm320-lq100/drivers/drv_rtc.c @@ -97,7 +97,7 @@ static rt_err_t swm320_rtc_control(rt_device_t dev, int cmd, void *args) case RT_DEVICE_CTRL_RTC_SET_TIME: rt_enter_critical(); /* converts calendar time time into local time. */ - pNow = localtime((const time_t *)args); + pNow = gmtime((const time_t *)args); /* copy the statically located variable */ memcpy(&time_temp, pNow, sizeof(struct tm)); /* unlock scheduler. */ diff --git a/bsp/w60x/drivers/drv_rtc.c b/bsp/w60x/drivers/drv_rtc.c index 5fb87af355..fa0aee498c 100644 --- a/bsp/w60x/drivers/drv_rtc.c +++ b/bsp/w60x/drivers/drv_rtc.c @@ -52,7 +52,7 @@ static int wm_set_timestamp(time_t timestamp) struct tm *tblock; - tblock = localtime(×tamp); + tblock = gmtime(×tamp); ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); /* disable */ ctrl2 &= ~(1 << 16); @@ -84,7 +84,7 @@ static int wm_alarm_set_timestamp(struct rt_rtc_wkalarm *wkalarm) time_t timestamp = 0; timestamp = wm_get_timestamp(); - tblock = localtime(×tamp); + tblock = gmtime(×tamp); tls_irq_enable(PMU_RTC_INT); diff --git a/components/dfs/filesystems/elmfat/dfs_elm.c b/components/dfs/filesystems/elmfat/dfs_elm.c index 5f69b069bf..d8c38e96ae 100644 --- a/components/dfs/filesystems/elmfat/dfs_elm.c +++ b/components/dfs/filesystems/elmfat/dfs_elm.c @@ -956,7 +956,7 @@ DWORD get_fattime(void) /* lock scheduler. */ rt_enter_critical(); /* converts calendar time time into local time. */ - p_tm = localtime(&now); + p_tm = gmtime(&now); /* copy the statically located variable */ memcpy(&tm_now, p_tm, sizeof(struct tm)); /* unlock scheduler. */ diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index 3b4c479001..73de840b37 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -125,27 +125,27 @@ static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm, *tm_ptr; + struct tm tm, *tm_ptr; time_t *time; - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - time = (time_t *)args; - switch (cmd) - { + time = (time_t *)args; + switch (cmd) + { case RT_DEVICE_CTRL_RTC_GET_TIME: /* read device */ rt_hw_rtc_get(&tm); - *((rt_time_t *)args) = mktime(&tm); + *((rt_time_t *)args) = timegm(&tm); break; case RT_DEVICE_CTRL_RTC_SET_TIME: - tm_ptr = localtime(time); /* write device */ + tm_ptr = gmtime(time); rt_hw_rtc_set(tm_ptr); break; - } + } - return RT_EOK; + return RT_EOK; } void rt_hw_rtc_init(void) -- cgit v1.3.1 From 12d5ca60c59e485234f138721caef60d93c48ecd Mon Sep 17 00:00:00 2001 From: liruncong Date: Tue, 9 Feb 2021 23:25:34 +0800 Subject: [libcpu/arm]SECTION=>RT_SECTION(与catch2中SECTION冲突) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/arm/realview-a8-vmm/interrupt.c | 6 +++--- libcpu/arm/zynq7000/mmu.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'libcpu') diff --git a/libcpu/arm/realview-a8-vmm/interrupt.c b/libcpu/arm/realview-a8-vmm/interrupt.c index 5ef0bdc460..5fffb4ba36 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.c +++ b/libcpu/arm/realview-a8-vmm/interrupt.c @@ -26,9 +26,9 @@ extern volatile rt_uint8_t rt_interrupt_nest; struct rt_irq_desc isr_table[MAX_HANDLERS]; /* Those varibles will be accessed in ISR, so we need to share them. */ -rt_uint32_t rt_interrupt_from_thread SECTION(".bss.share.int"); -rt_uint32_t rt_interrupt_to_thread SECTION(".bss.share.int"); -rt_uint32_t rt_thread_switch_interrupt_flag SECTION(".bss.share.int"); +rt_uint32_t rt_interrupt_from_thread RT_SECTION(".bss.share.int"); +rt_uint32_t rt_interrupt_to_thread RT_SECTION(".bss.share.int"); +rt_uint32_t rt_thread_switch_interrupt_flag RT_SECTION(".bss.share.int"); const unsigned int VECTOR_BASE = 0x00; extern void rt_cpu_vector_set_base(unsigned int addr); diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c index fbdacca10f..8674f9f60f 100644 --- a/libcpu/arm/zynq7000/mmu.c +++ b/libcpu/arm/zynq7000/mmu.c @@ -109,7 +109,7 @@ void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) /* level1 page table, each entry for 1MB memory. */ /* MMUTable is the name used by codes of Xilinx */ -volatile unsigned long MMUTable[4*1024] SECTION("mmu_tbl") __attribute__((aligned(16*1024))); +volatile unsigned long MMUTable[4*1024] RT_SECTION("mmu_tbl") __attribute__((aligned(16*1024))); void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, -- cgit v1.3.1 From 2da5d4a5d6b5e04838b77122410a049e0a10cfa6 Mon Sep 17 00:00:00 2001 From: Bernard Xiong Date: Fri, 19 Feb 2021 23:55:17 +0800 Subject: [bsp][x86] update x86 with Kconfig and newlib toolchains. --- bsp/x86/.config | 535 +++++++++++++++++++++++++++++++++++++ bsp/x86/Kconfig | 26 ++ bsp/x86/Makefile | 46 ---- bsp/x86/SConscript | 5 +- bsp/x86/applications/application.c | 86 ------ bsp/x86/applications/main.c | 16 ++ bsp/x86/applications/mnt.c | 17 ++ bsp/x86/applications/startup.c | 103 ------- bsp/x86/drivers/board.c | 75 +++--- bsp/x86/drivers/board.h | 8 +- bsp/x86/drivers/console.c | 106 ++++---- bsp/x86/drivers/dma.h | 7 + bsp/x86/drivers/floppy.c | 65 ++--- bsp/x86/drivers/floppy.h | 7 + bsp/x86/drivers/include/bsp.h | 120 ++++----- bsp/x86/drivers/include/grub.h | 80 +++--- bsp/x86/drivers/include/i386.h | 170 ++++++------ bsp/x86/drivers/keyboard.c | 8 +- bsp/x86/drivers/keyboard.h | 7 + bsp/x86/drivers/keymap.h | 7 + bsp/x86/drivers/serial.c | 48 ++-- bsp/x86/rtconfig.h | 302 +++++++++++---------- bsp/x86/rtconfig.py | 20 +- bsp/x86/x86_ram.lds | 99 +++---- libcpu/ia32/__udivsi3.c | 8 +- libcpu/ia32/__umodsi3.c | 8 +- libcpu/ia32/backtrace.c | 20 -- libcpu/ia32/context_gcc.S | 36 +-- libcpu/ia32/cpuport.c | 77 ++++++ libcpu/ia32/hdisr_gcc.S | 8 +- libcpu/ia32/interrupt.c | 113 +++----- libcpu/ia32/showmem.c | 42 --- libcpu/ia32/stack.c | 59 ---- libcpu/ia32/start_gcc.S | 18 +- libcpu/ia32/trap.c | 17 +- libcpu/ia32/trapisr_gcc.S | 26 +- 36 files changed, 1328 insertions(+), 1067 deletions(-) create mode 100644 bsp/x86/.config create mode 100644 bsp/x86/Kconfig delete mode 100644 bsp/x86/Makefile delete mode 100644 bsp/x86/applications/application.c create mode 100644 bsp/x86/applications/main.c create mode 100644 bsp/x86/applications/mnt.c delete mode 100644 bsp/x86/applications/startup.c delete mode 100644 libcpu/ia32/backtrace.c create mode 100644 libcpu/ia32/cpuport.c delete mode 100644 libcpu/ia32/showmem.c delete mode 100644 libcpu/ia32/stack.c (limited to 'libcpu') diff --git a/bsp/x86/.config b/bsp/x86/.config new file mode 100644 index 0000000000..b796f37ae5 --- /dev/null +++ b/bsp/x86/.config @@ -0,0 +1,535 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=2048 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +CONFIG_RT_DEBUG_INIT_CONFIG=y +CONFIG_RT_DEBUG_INIT=1 +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="console" +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_IA32=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_POSIX is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_IA32=y diff --git a/bsp/x86/Kconfig b/bsp/x86/Kconfig new file mode 100644 index 0000000000..e8ac6055e5 --- /dev/null +++ b/bsp/x86/Kconfig @@ -0,0 +1,26 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config IA32 + bool + select ARCH_IA32 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/x86/Makefile b/bsp/x86/Makefile deleted file mode 100644 index eb4654193b..0000000000 --- a/bsp/x86/Makefile +++ /dev/null @@ -1,46 +0,0 @@ - -CC = gcc -O0 -m32 -fno-builtin -fno-stack-protector -nostdinc -nostdlib -LD = ld -melf_i386 -nostdlib - -all: rtthread rtsym exe dll floppy.img - @mkdir -p tmp - @sudo mount -t vfat floppy.img tmp -o loop - @sudo cp -fv rtthread.elf tmp/boot/oskernel - @sudo rm tmp/bin/* -fr - @sudo cp out/*.mo tmp/bin/ -fv - @sudo umount tmp - -rtthread: - @scons - -rtsym: - @./src/extract.sh ./rtthread-ia32.map ./src/rt_thread_sym.h - -obj: - mkdir -p obj - -out: - mkdir -p out - -dll: obj out - $(CC) -c -fPIC -Isrc src/hello.c -o out/hello.o - $(CC) -s -Wl,-shared,-melf_i386,--entry=main -o out/hello.mo out/hello.o - -disasm: obj out - $(CC) -shared -S -fPIC -Isrc src/hello.c -o obj/hello.s - cat obj/hello.s - objdump --disassemble out/hello.mo - -exe: obj out - - -clean: - scons -c clean - rm -fr build rtthread* out obj - -floppy.img: - wget https://github.com/bajdcc/tinix/raw/master/floppy.img - -# https://en.wikibooks.org/wiki/QEMU/Devices/Network -run: - qemu-system-i386 -fda floppy.img -boot a -m 64M -serial stdio -net nic,model=ne2k_pci diff --git a/bsp/x86/SConscript b/bsp/x86/SConscript index fe0ae941ae..3d15055d62 100644 --- a/bsp/x86/SConscript +++ b/bsp/x86/SConscript @@ -1,8 +1,7 @@ -# for module compiling import os -Import('RTT_ROOT') +from building import * -cwd = str(Dir('#')) +cwd = GetCurrentDir() objs = [] list = os.listdir(cwd) diff --git a/bsp/x86/applications/application.c b/bsp/x86/applications/application.c deleted file mode 100644 index 8928e6357e..0000000000 --- a/bsp/x86/applications/application.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - */ - -#include - -#ifdef RT_USING_DFS -#include -#include -#include "floppy.h" -#ifdef RT_USING_MODULE -#include -#endif -extern int elm_init(void); -#endif - -/* components initialization for simulator */ -void components_init(void) -{ -#ifdef RT_USING_DFS - rt_floppy_init(); - /* initialize the device file system */ - dfs_init(); - -#ifdef RT_USING_DFS_ELMFAT - /* initialize the elm chan FatFS file system*/ - elm_init(); -#endif - -#ifdef RT_USING_MODULE - rt_system_dlmodule_init(); -#endif -#endif -} -void rt_init_thread_entry(void *parameter) -{ - components_init(); - - /* File system Initialization */ -#ifdef RT_USING_DFS - { - -#ifdef RT_USING_DFS_ELMFAT - /* mount sd card fatfs as root directory */ - if (dfs_mount("floppy", "/", "elm", 0, 0) == 0) - rt_kprintf("fatfs initialized!\n"); - else - rt_kprintf("fatfs initialization failed!\n"); -#endif - } -#endif -} - -int rt_application_init() -{ - rt_thread_t tid; - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX / 3, 20); - - if (tid != RT_NULL) - rt_thread_startup(tid); - - return 0; -} diff --git a/bsp/x86/applications/main.c b/bsp/x86/applications/main.c new file mode 100644 index 0000000000..86aadd5a7b --- /dev/null +++ b/bsp/x86/applications/main.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + */ +#include +#include + +int main(void) +{ + printf("hello!\n"); + + return 0; +} diff --git a/bsp/x86/applications/mnt.c b/bsp/x86/applications/mnt.c new file mode 100644 index 0000000000..3ca04871f8 --- /dev/null +++ b/bsp/x86/applications/mnt.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + */ +#include + +extern int rt_floppy_init(void); + +int mnt_init(void) +{ + rt_floppy_init(); + + return 0; +} diff --git a/bsp/x86/applications/startup.c b/bsp/x86/applications/startup.c deleted file mode 100644 index 475273267f..0000000000 --- a/bsp/x86/applications/startup.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.fayfayspace.org/license/LICENSE. - * - * Change Logs: - * Date Author Notes - * 2006-09-15 QiuYi the first version - * 2006-10-10 Bernard update to 0.2.2 version - */ - -#include -#include - -#include "board.h" - -extern void rt_hw_console_init(void); -extern void rt_hw_board_init(void); -extern int rt_application_init(void); -//extern void rt_hw_interrupt_init(void); -//extern void rt_system_timer_init(void); -//extern void rt_system_scheduler_init(void); -//extern void rt_thread_idle_init(void); - -#ifdef RT_USING_FINSH -extern int finsh_system_init(void); -extern void finsh_set_device(const char *device); -#endif - -extern unsigned char __bss_start[]; -extern unsigned char __bss_end[]; - -/** - * @addtogroup QEMU - */ - - /*@{*/ - -/* clear .bss */ -void rt_hw_clear_bss(void) -{ - unsigned char *dst; - dst = __bss_start; - while (dst < __bss_end) - *dst++ = 0; -} - -/** - * This function will startup RT-Thread RTOS - */ -void rtthread_startup(void) -{ - /* clear .bss */ - rt_hw_clear_bss(); - - /* init hardware interrupt */ - rt_hw_interrupt_init(); - - /* init the console */ - rt_hw_console_init(); - rt_console_set_device("console"); - - /* init board */ - rt_hw_board_init(); - - rt_show_version(); - - /* init timer system */ - rt_system_timer_init(); - - /* init memory system */ -#ifdef RT_USING_HEAP - /* RAM 16M */ - rt_system_heap_init((void *)&__bss_end, (void *)(1024UL*1024*8)); -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - - /* init application */ - rt_application_init(); - -#ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); - finsh_set_device("console"); -#endif - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -/*@}*/ diff --git a/bsp/x86/drivers/board.c b/bsp/x86/drivers/board.c index 211ae1832a..30aba8be54 100644 --- a/bsp/x86/drivers/board.c +++ b/bsp/x86/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.fayfayspace.org/license/LICENSE. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -13,62 +9,81 @@ * 2006-10-10 Bernard add hardware related of finsh */ -#include #include +#include #include +extern unsigned char __bss_start[]; +extern unsigned char __bss_end[]; +extern void rt_hw_console_init(void); + /** * @addtogroup QEMU */ /*@{*/ - static void rt_timer_handler(int vector, void* param) { - rt_tick_increase(); + rt_tick_increase(); } #ifdef RT_USING_HOOK static void idle_hook(void) { - asm volatile("sti; hlt": : :"memory"); + asm volatile("sti; hlt": : :"memory"); } #endif +/* clear .bss */ +void rt_hw_clear_bss(void) +{ + unsigned char *dst; + dst = __bss_start; + while (dst < __bss_end) + *dst++ = 0; +} + /** * This function will init QEMU * */ void rt_hw_board_init(void) { - /* initialize 8253 clock to interrupt 1000 times/sec */ - outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); - outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) % 256); - outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) / 256); + /* clear .bss */ + rt_hw_clear_bss(); + + /* init hardware interrupt */ + rt_hw_interrupt_init(); - /* install interrupt handler */ - rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL, "tick"); - rt_hw_interrupt_umask(INTTIMER0); + /* init the console */ + rt_hw_console_init(); + rt_console_set_device("console"); + + /* initialize 8253 clock to interrupt 1000 times/sec */ + outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); + outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) % 256); + outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) / 256); + + /* install interrupt handler */ + rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL, "tick"); + rt_hw_interrupt_umask(INTTIMER0); + + /* init memory system */ +#ifdef RT_USING_HEAP + /* RAM 16M */ + rt_system_heap_init((void *)&__bss_end, (void *)(1024UL*1024*8)); +#endif #ifdef RT_USING_HOOK - rt_thread_idle_sethook(idle_hook); + rt_thread_idle_sethook(idle_hook); #endif } -void restart(void) +static int reboot(void) { outb(KBSTATP, 0xFE); /* pulse reset low */ - while(1); -} - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(restart, reboot PC) -void reboot(void) -{ - restart(); + return 0; } -FINSH_FUNCTION_EXPORT(reboot, reboot PC) -#endif +MSH_CMD_EXPORT(reboot, reboot system); /*@}*/ diff --git a/bsp/x86/drivers/board.h b/bsp/x86/drivers/board.h index bc79f9ccfb..96e1cb15af 100644 --- a/bsp/x86/drivers/board.h +++ b/bsp/x86/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/x86/drivers/console.c b/bsp/x86/drivers/console.c index f5c4fe530b..b783872bae 100644 --- a/bsp/x86/drivers/console.c +++ b/bsp/x86/drivers/console.c @@ -1,11 +1,7 @@ /* - * File : console.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -218,47 +214,46 @@ static rt_size_t rt_console_read(rt_device_t dev, rt_off_t pos, void* buffer, rt static void rt_console_isr(int vector, void* param) { char c; - rt_bool_t ret; + rt_bool_t ret; rt_base_t level; - if(INTUART0_RX == vector) - { - c = rt_serial_getc(); - ret = RT_TRUE; - } - else - { - rt_keyboard_isr(); - - ret = rt_keyboard_getc(&c); - } - - if(ret == RT_FALSE) - { - /* do nothing */ - } - else - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* save character */ - rx_buffer[save_index] = c; - save_index ++; - if (save_index >= CONSOLE_RX_BUFFER_SIZE) - save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (save_index == read_index) - { - read_index ++; - if (read_index >= CONSOLE_RX_BUFFER_SIZE) - read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } + if(INTUART0_RX == vector) + { + c = rt_serial_getc(); + ret = RT_TRUE; + } + else + { + rt_keyboard_isr(); + ret = rt_keyboard_getc(&c); + } + + if(ret == RT_FALSE) + { + /* do nothing */ + } + else + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* save character */ + rx_buffer[save_index] = c; + save_index ++; + if (save_index >= CONSOLE_RX_BUFFER_SIZE) + save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (save_index == read_index) + { + read_index ++; + if (read_index >= CONSOLE_RX_BUFFER_SIZE) + read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } /* invoke callback */ if (console_device.rx_indicate != RT_NULL) @@ -267,29 +262,25 @@ static void rt_console_isr(int vector, void* param) /* get rx length */ rx_length = read_index > save_index ? - CONSOLE_RX_BUFFER_SIZE - read_index + save_index : - save_index - read_index; + CONSOLE_RX_BUFFER_SIZE - read_index + save_index : + save_index - read_index; if(rx_length > 0) { console_device.rx_indicate(&console_device, rx_length); } } - else - { - - } } /** * This function initializes console * */ -void rt_hw_console_init(void) +int rt_hw_console_init(void) { rt_cga_init(); - rt_serial_init(); - init_keyboard(); + rt_serial_init(); + init_keyboard(); /* install keyboard isr */ rt_hw_interrupt_install(INTKEYBOARD, rt_console_isr, RT_NULL, "kbd"); @@ -311,9 +302,12 @@ void rt_hw_console_init(void) /* register a character device */ rt_device_register(&console_device, - "console", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); + "console", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); + + return 0; } +INIT_DEVICE_EXPORT(rt_hw_console_init); /** * This function is used to display a string on console, normally, it's diff --git a/bsp/x86/drivers/dma.h b/bsp/x86/drivers/dma.h index f1a8563cb1..3e5e9b08d1 100644 --- a/bsp/x86/drivers/dma.h +++ b/bsp/x86/drivers/dma.h @@ -1,3 +1,10 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + */ #ifndef _DMA_H #define _DMA_H diff --git a/bsp/x86/drivers/floppy.c b/bsp/x86/drivers/floppy.c index c7876a68f8..f4675b9194 100644 --- a/bsp/x86/drivers/floppy.c +++ b/bsp/x86/drivers/floppy.c @@ -1,4 +1,10 @@ - +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + */ #include #include @@ -17,7 +23,6 @@ typedef rt_int32_t s32; #include "floppy.h" #include "dma.h" -#define NULL RT_NULL #define SECTOR_SIZE 512 #define panic(str,...) do { rt_kprintf("panic::" str,##__VA_ARGS__); while(1); } while(0) @@ -128,17 +133,17 @@ u32 floppy_get_info(void) { case 0x02: // 1.2MB floppy_type = "1.2MB"; - floppy_size = 2458*512; + floppy_size = 2458*512; break; case 0x04: // 1.44MB 标准软盘 floppy_type = "1.44MB"; - floppy_size = 2880*512; + floppy_size = 2880*512; break; case 0x05: // 2.88MB floppy_type = "2.88MB"; - floppy_size = 2*2880*512; + floppy_size = 2*2880*512; break; } return 1; @@ -261,32 +266,32 @@ static rt_err_t rt_floppy_close(rt_device_t dev) */ static rt_size_t rt_floppy_read(rt_device_t device, rt_off_t position, void *buffer, rt_size_t size) { - rt_size_t doSize = size; + rt_size_t doSize = size; rt_mutex_take(&lock, RT_WAITING_FOREVER); - while(size>0) - { - floppy_read_cmd(position); + while(size>0) + { + floppy_read_cmd(position); - rt_sem_take(&sem, RT_WAITING_FOREVER); /* waiting isr sem forever */ + rt_sem_take(&sem, RT_WAITING_FOREVER); /* waiting isr sem forever */ - floppy_result(); - io_delay(); + floppy_result(); + io_delay(); - if(ST1 != 0 || ST2 != 0) - { - panic("ST0 %d ST1 %d ST2 %d\n",ST0,ST1,ST2); - } + if(ST1 != 0 || ST2 != 0) + { + panic("ST0 %d ST1 %d ST2 %d\n",ST0,ST1,ST2); + } - rt_memcpy(buffer, floppy_buffer, 512); + rt_memcpy(buffer, floppy_buffer, 512); - floppy_motorOff(); - io_delay(); - - position += 1; - size -= 1; - } - rt_mutex_release(&lock); + floppy_motorOff(); + io_delay(); + + position += 1; + size -= 1; + } + rt_mutex_release(&lock); return doSize; } @@ -298,7 +303,7 @@ static rt_size_t rt_floppy_read(rt_device_t device, rt_off_t position, void *buf static rt_size_t rt_floppy_write(rt_device_t device, rt_off_t position, const void *buffer, rt_size_t size) { rt_mutex_take(&lock, RT_WAITING_FOREVER); - panic("FIXME:I don't know how!\n"); + panic("FIXME:I don't know how!\n"); rt_mutex_release(&lock); return size; } @@ -325,9 +330,9 @@ static rt_err_t rt_floppy_control(rt_device_t dev, int cmd, void *args) static void rt_floppy_isr(int vector, void* param) { - (void)vector; - (void)param; - rt_sem_release(&sem); + (void)vector; + (void)param; + rt_sem_release(&sem); } void rt_floppy_init(void) @@ -335,9 +340,9 @@ void rt_floppy_init(void) struct rt_device *device; rt_mutex_init(&lock,"fdlock", RT_IPC_FLAG_FIFO); - rt_sem_init(&sem, "fdsem", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&sem, "fdsem", 0, RT_IPC_FLAG_FIFO); - rt_hw_interrupt_install(FLOPPY_IRQ, rt_floppy_isr, RT_NULL, "floppy"); + rt_hw_interrupt_install(FLOPPY_IRQ, rt_floppy_isr, RT_NULL, "floppy"); rt_hw_interrupt_umask(FLOPPY_IRQ); floppy_get_info(); diff --git a/bsp/x86/drivers/floppy.h b/bsp/x86/drivers/floppy.h index f619508c43..86de750133 100644 --- a/bsp/x86/drivers/floppy.h +++ b/bsp/x86/drivers/floppy.h @@ -1,3 +1,10 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + */ #ifndef _FLOPPY_H #define _FLOPPY_H diff --git a/bsp/x86/drivers/include/bsp.h b/bsp/x86/drivers/include/bsp.h index 724f518c6e..93e409dbfa 100644 --- a/bsp/x86/drivers/include/bsp.h +++ b/bsp/x86/drivers/include/bsp.h @@ -1,11 +1,7 @@ /* - * File : bsp.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -60,86 +56,86 @@ extern "C" { #define T_DEVICE 7 /* device not available */ #define T_DBLFLT 8 /* double fault */ /* 9 is reserved */ -#define T_TSS 10 /* invalid task switch segment */ -#define T_SEGNP 11 /* segment not present */ -#define T_STACK 12 /* stack exception */ -#define T_GPFLT 13 /* genernal protection fault */ -#define T_PGFLT 14 /* page fault */ +#define T_TSS 10 /* invalid task switch segment */ +#define T_SEGNP 11 /* segment not present */ +#define T_STACK 12 /* stack exception */ +#define T_GPFLT 13 /* genernal protection fault */ +#define T_PGFLT 14 /* page fault */ /* 15 is reserved */ -#define T_FPERR 16 /* floating point error */ -#define T_ALIGN 17 /* aligment check */ -#define T_MCHK 18 /* machine check */ -#define T_DEFAULT 500 /* catchall */ +#define T_FPERR 16 /* floating point error */ +#define T_ALIGN 17 /* aligment check */ +#define T_MCHK 18 /* machine check */ +#define T_DEFAULT 500 /* catchall */ -#define INTTIMER0 0 -#define INTKEYBOARD 1 -#define INTUART0_RX 4 -#define CLOCK_IRQ 0 +#define INTTIMER0 0 +#define INTKEYBOARD 1 +#define INTUART0_RX 4 +#define CLOCK_IRQ 0 #define KEYBOARD_IRQ 1 -#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ -#define ETHER_IRQ 3 /* default ethernet interrupt vector */ +#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ +#define ETHER_IRQ 3 /* default ethernet interrupt vector */ #define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ -#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ -#define XT_WINI_IRQ 5 /* xt winchester */ -#define FLOPPY_IRQ 6 /* floppy disk */ -#define PRINTER_IRQ 7 -#define AT_WINI_IRQ 14 /* at winchester */ +#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ +#define XT_WINI_IRQ 5 /* xt winchester */ +#define FLOPPY_IRQ 6 /* floppy disk */ +#define PRINTER_IRQ 7 +#define AT_WINI_IRQ 14 /* at winchester */ /* I/O Addresses of the two 8259A programmable interrupt controllers */ -#define IO_PIC1 0x20 /* Master(IRQs 0-7) */ -#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */ -#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */ -#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */ +#define IO_PIC1 0x20 /* Master(IRQs 0-7) */ +#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */ +#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */ +#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */ -#define MAX_HANDLERS 16 /*max number of isr handler*/ +#define MAX_HANDLERS 16 /*max number of isr handler*/ /*******************************************************************/ /* CRT Register */ /*******************************************************************/ -#define MONO_BASE 0x3b4 -#define MONO_BUF 0xb0000 -#define CGA_BASE 0x3d4 -#define CGA_BUF 0xb8000 +#define MONO_BASE 0x3b4 +#define MONO_BUF 0xb0000 +#define CGA_BASE 0x3d4 +#define CGA_BUF 0xb8000 -#define CRT_ROWS 25 -#define CRT_COLS 80 -#define CRT_SIZE (CRT_ROWS * CRT_COLS) +#define CRT_ROWS 25 +#define CRT_COLS 80 +#define CRT_SIZE (CRT_ROWS * CRT_COLS) /*******************************************************************/ /* Keyboard Register */ /*******************************************************************/ -#define KBSTATP 0x64 /* kbd controller status port(I) */ -#define KBS_DIB 0x01 /* kbd data in buffer */ -#define KBDATAP 0x60 /* kbd data port(I) */ +#define KBSTATP 0x64 /* kbd controller status port(I) */ +#define KBS_DIB 0x01 /* kbd data in buffer */ +#define KBDATAP 0x60 /* kbd data port(I) */ /* AT keyboard */ /* 8042 ports */ -#define KB_DATA 0x60 /* I/O port for keyboard data - Read : Read Output Buffer - Write: Write Input Buffer(8042 Data&8048 Command) */ -#define KB_CMD 0x64 /* I/O port for keyboard command - Read : Read Status Register - Write: Write Input Buffer(8042 Command) */ -#define LED_CODE 0xED -#define KB_ACK 0xFA +#define KB_DATA 0x60 /* I/O port for keyboard data + * Read : Read Output Buffer + * Write: Write Input Buffer(8042 Data&8048 Command) */ +#define KB_CMD 0x64 /* I/O port for keyboard command + * Read : Read Status Register + * Write: Write Input Buffer(8042 Command) */ +#define LED_CODE 0xED +#define KB_ACK 0xFA /*******************************************************************/ /* Serial Register */ /*******************************************************************/ /*Serial I/O code */ -#define COM1 0x3F8 -#define COMSTATUS 5 -#define COMDATA 0x01 -#define COMREAD 0 -#define COMWRITE 0 +#define COM1 0x3F8 +#define COMSTATUS 5 +#define COMDATA 0x01 +#define COMREAD 0 +#define COMWRITE 0 /* Bits definition of the Line Status Register (LSR)*/ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* Transmitter Holding Register Empty */ -#define TEMT 0x40 /* Transmitter Empty */ -#define ERFIFO 0x80 /* Error receive Fifo */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* Transmitter Holding Register Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define ERFIFO 0x80 /* Error receive Fifo */ #ifdef __cplusplus } diff --git a/bsp/x86/drivers/include/grub.h b/bsp/x86/drivers/include/grub.h index dcfa36b819..d5a84a48da 100644 --- a/bsp/x86/drivers/include/grub.h +++ b/bsp/x86/drivers/include/grub.h @@ -1,11 +1,7 @@ /* - * File : grub.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,63 +25,63 @@ /* the multiboot header. */ typedef struct multiboot_header { - unsigned long magic; - unsigned long flags; - unsigned long checksum; - unsigned long header_addr; - unsigned long load_addr; - unsigned long load_end_addr; - unsigned long bss_end_addr; - unsigned long entry_addr; + unsigned long magic; + unsigned long flags; + unsigned long checksum; + unsigned long header_addr; + unsigned long load_addr; + unsigned long load_end_addr; + unsigned long bss_end_addr; + unsigned long entry_addr; } multiboot_header_t; /* the section header table for elf. */ typedef struct elf_section_header_table { - unsigned long num; - unsigned long size; - unsigned long addr; - unsigned long shndx; + unsigned long num; + unsigned long size; + unsigned long addr; + unsigned long shndx; } elf_section_header_table_t; /* the multiboot information. */ typedef struct multiboot_info { - unsigned long flags; - unsigned long mem_lower; - unsigned long mem_upper; - unsigned long boot_device; - unsigned long cmdline; - unsigned long mods_count; - unsigned long mods_addr; - union - { - aout_symbol_table_t aout_sym; - elf_section_header_table_t elf_sec; - } u; - unsigned long mmap_length; - unsigned long mmap_addr; + unsigned long flags; + unsigned long mem_lower; + unsigned long mem_upper; + unsigned long boot_device; + unsigned long cmdline; + unsigned long mods_count; + unsigned long mods_addr; + union + { + aout_symbol_table_t aout_sym; + elf_section_header_table_t elf_sec; + } u; + unsigned long mmap_length; + unsigned long mmap_addr; } multiboot_info_t; /* the module structure. */ typedef struct module { - unsigned long mod_start; - unsigned long mod_end; - unsigned long string; - unsigned long reserved; + unsigned long mod_start; + unsigned long mod_end; + unsigned long string; + unsigned long reserved; } module_t; /* the memory map. be careful that the offset 0 is base_addr_low but no size. */ typedef struct memory_map { - unsigned long size; - unsigned long base_addr_low; - unsigned long base_addr_high; - unsigned long length_low; - unsigned long length_high; - unsigned long type; + unsigned long size; + unsigned long base_addr_low; + unsigned long base_addr_high; + unsigned long length_low; + unsigned long length_high; + unsigned long type; } memory_map_t; #endif diff --git a/bsp/x86/drivers/include/i386.h b/bsp/x86/drivers/include/i386.h index 68c854932b..bde4a95c3b 100644 --- a/bsp/x86/drivers/include/i386.h +++ b/bsp/x86/drivers/include/i386.h @@ -1,3 +1,10 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + */ #ifndef __I386_H_ #define __I386_H_ @@ -7,138 +14,135 @@ extern "C" { static __inline unsigned char inb(int port) { - unsigned char data; - __asm __volatile("inb %w1,%0" : "=a" (data) : "d" (port)); - return data; + unsigned char data; + __asm __volatile("inb %w1,%0" : "=a" (data) : "d" (port)); + return data; } static __inline unsigned char inb_p(unsigned short port) { - unsigned char _v; - __asm__ __volatile__ ("inb %1, %0\n\t" - // "outb %0,$0x80\n\t" - // "outb %0,$0x80\n\t" - // "outb %0,$0x80\n\t" - "outb %0,$0x80" - :"=a" (_v) - :"d" ((unsigned short) port)); - return _v; + unsigned char _v; + __asm__ __volatile__ ("inb %1, %0\n\t" + "outb %0,$0x80" + :"=a" (_v) + :"d" ((unsigned short) port)); + return _v; } static __inline unsigned short inw(int port) { - unsigned short data; - __asm __volatile("inw %w1,%0" : "=a" (data) : "d" (port)); - return data; + unsigned short data; + __asm __volatile("inw %w1,%0" : "=a" (data) : "d" (port)); + return data; } static __inline unsigned int inl(int port) { - unsigned int data; - __asm __volatile("inl %w1,%0" : "=a" (data) : "d" (port)); - return data; + unsigned int data; + __asm __volatile("inl %w1,%0" : "=a" (data) : "d" (port)); + return data; } static __inline void insl(int port, void *addr, int cnt) { - __asm __volatile("cld\n\trepne\n\tinsl" : - "=D" (addr), "=c" (cnt) : - "d" (port), "0" (addr), "1" (cnt) : - "memory", "cc"); + __asm __volatile("cld\n\trepne\n\tinsl" : + "=D" (addr), "=c" (cnt) : + "d" (port), "0" (addr), "1" (cnt) : + "memory", "cc"); } static __inline void outb(int port, unsigned char data) { - __asm __volatile("outb %0,%w1" : : "a" (data), "d" (port)); + __asm __volatile("outb %0,%w1" : : "a" (data), "d" (port)); } static __inline void outb_p(char value, unsigned short port) { - __asm__ __volatile__ ("outb %0,%1\n\t" - "outb %0,$0x80" - ::"a" ((char) value),"d" ((unsigned short) port)); + __asm__ __volatile__ ("outb %0,%1\n\t" + "outb %0,$0x80" + ::"a" ((char) value),"d" ((unsigned short) port)); } static __inline void outw(int port, unsigned short data) { - __asm __volatile("outw %0,%w1" : : "a" (data), "d" (port)); + __asm __volatile("outw %0,%w1" : : "a" (data), "d" (port)); } static __inline unsigned char readcmos(int reg) { - outb(0x70,reg); - return (unsigned char) inb(0x71); + outb(0x70,reg); + return (unsigned char) inb(0x71); } -#define io_delay() \ - __asm__ __volatile__ ("pushal \n\t"\ - "mov $0x3F6, %dx \n\t" \ - "inb %dx, %al \n\t" \ - "inb %dx, %al \n\t" \ - "inb %dx, %al \n\t" \ - "inb %dx, %al \n\t" \ - "popal") +#define io_delay() \ + __asm__ __volatile__ ("pushal \n\t" \ + "mov $0x3F6, %dx \n\t" \ + "inb %dx, %al \n\t" \ + "inb %dx, %al \n\t" \ + "inb %dx, %al \n\t" \ + "inb %dx, %al \n\t" \ + "popal") /* Gate descriptors are slightly different*/ struct Gatedesc { - unsigned gd_off_15_0 : 16; // low 16 bits of offset in segment - unsigned gd_ss : 16; // segment selector - unsigned gd_args : 5; // # args, 0 for interrupt/trap gates - unsigned gd_rsv1 : 3; // reserved(should be zero I guess) - unsigned gd_type :4; // type(STS_{TG,IG32,TG32}) - unsigned gd_s : 1; // must be 0 (system) - unsigned gd_dpl : 2; // descriptor(meaning new) privilege level - unsigned gd_p : 1; // Present - unsigned gd_off_31_16 : 16; // high bits of offset in segment + unsigned gd_off_15_0 : 16; // low 16 bits of offset in segment + unsigned gd_ss : 16; // segment selector + unsigned gd_args : 5; // # args, 0 for interrupt/trap gates + unsigned gd_rsv1 : 3; // reserved(should be zero I guess) + unsigned gd_type :4; // type(STS_{TG,IG32,TG32}) + unsigned gd_s : 1; // must be 0 (system) + unsigned gd_dpl : 2; // descriptor(meaning new) privilege level + unsigned gd_p : 1; // Present + unsigned gd_off_31_16 : 16; // high bits of offset in segment }; /* Pseudo-descriptors used for LGDT, LLDT and LIDT instructions*/ struct Pseudodesc { - rt_uint16_t pd__garbage; // LGDT supposed to be from address 4N+2 - rt_uint16_t pd_lim; // Limit - rt_uint32_t pd_base __attribute__ ((packed)); // Base address + rt_uint16_t pd__garbage; // LGDT supposed to be from address 4N+2 + rt_uint16_t pd_lim; // Limit + rt_uint32_t pd_base __attribute__ ((packed)); // Base address }; -#define SETGATE(gate, istrap, sel, off, dpl) \ -{ \ - (gate).gd_off_15_0 = (rt_uint32_t) (off) & 0xffff; \ - (gate).gd_ss = (sel); \ - (gate).gd_args = 0; \ - (gate).gd_rsv1 = 0; \ - (gate).gd_type = (istrap) ? STS_TG32 : STS_IG32; \ - (gate).gd_s = 0; \ - (gate).gd_dpl = dpl; \ - (gate).gd_p = 1; \ - (gate).gd_off_31_16 = (rt_uint32_t) (off) >> 16; \ -} +#define SETGATE(gate, istrap, sel, off, dpl) \ + { \ + (gate).gd_off_15_0 = (rt_uint32_t)(off)&0xffff; \ + (gate).gd_ss = (sel); \ + (gate).gd_args = 0; \ + (gate).gd_rsv1 = 0; \ + (gate).gd_type = (istrap) ? STS_TG32 : STS_IG32; \ + (gate).gd_s = 0; \ + (gate).gd_dpl = dpl; \ + (gate).gd_p = 1; \ + (gate).gd_off_31_16 = (rt_uint32_t)(off) >> 16; \ + } /* Global descriptor numbers*/ -#define GD_KT 0x08 // kernel text -#define GD_KD 0x10 // kernel data -#define GD_UT 0x18 // user text -#define GD_UD 0x20 // user data +#define GD_KT 0x08 // kernel text +#define GD_KD 0x10 // kernel data +#define GD_UT 0x18 // user text +#define GD_UD 0x20 // user data /* Application segment type bits*/ -#define STA_X 0x8 // Executable segment -#define STA_E 0x4 // Expand down(non-executable segments) -#define STA_C 0x4 // Conforming code segment(executable only) -#define STA_W 0x2 // Writeable(non-executable segments) -#define STA_R 0x2 // Readable(executable segments) -#define STA_A 0x1 // Accessed +#define STA_X 0x8 // Executable segment +#define STA_E 0x4 // Expand down(non-executable segments) +#define STA_C 0x4 // Conforming code segment(executable only) +#define STA_W 0x2 // Writeable(non-executable segments) +#define STA_R 0x2 // Readable(executable segments) +#define STA_A 0x1 // Accessed /* System segment type bits*/ -#define STS_T16A 0x1 // Available 16-bit TSS -#define STS_LDT 0x2 // Local Descriptor Table -#define STS_T16B 0x3 // Busy 16-bit TSS -#define STS_CG16 0x4 // 16-bit Call Gate -#define STS_TG 0x5 // Task Gate / Coum Transmitions -#define STS_IG16 0x6 // 16-bit Interrupt Gate -#define STS_TG16 0x7 // 16-bit Trap Gate -#define STS_T32A 0x9 // Available 32-bit TSS -#define STS_T32B 0xb // Busy 32-bit TSS -#define STS_CG32 0xc // 32-bit Call Gate -#define STS_IG32 0xe // 32-bit Interrupt Gate -#define STS_TG32 0xf // 32-bit Trap Gate +#define STS_T16A 0x1 // Available 16-bit TSS +#define STS_LDT 0x2 // Local Descriptor Table +#define STS_T16B 0x3 // Busy 16-bit TSS +#define STS_CG16 0x4 // 16-bit Call Gate +#define STS_TG 0x5 // Task Gate / Coum Transmitions +#define STS_IG16 0x6 // 16-bit Interrupt Gate +#define STS_TG16 0x7 // 16-bit Trap Gate +#define STS_T32A 0x9 // Available 32-bit TSS +#define STS_T32B 0xb // Busy 32-bit TSS +#define STS_CG32 0xc // 32-bit Call Gate +#define STS_IG32 0xe // 32-bit Interrupt Gate +#define STS_TG32 0xf // 32-bit Trap Gate #ifdef __cplusplus } diff --git a/bsp/x86/drivers/keyboard.c b/bsp/x86/drivers/keyboard.c index 3716c367cc..b4ae626261 100644 --- a/bsp/x86/drivers/keyboard.c +++ b/bsp/x86/drivers/keyboard.c @@ -1,11 +1,7 @@ /* - * File : keyboard.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/x86/drivers/keyboard.h b/bsp/x86/drivers/keyboard.h index f3e849df96..437d9dfc9f 100644 --- a/bsp/x86/drivers/keyboard.h +++ b/bsp/x86/drivers/keyboard.h @@ -1,3 +1,10 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + */ /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ keyboard.h diff --git a/bsp/x86/drivers/keymap.h b/bsp/x86/drivers/keymap.h index 3031438a1b..aa9880e295 100644 --- a/bsp/x86/drivers/keymap.h +++ b/bsp/x86/drivers/keymap.h @@ -1,3 +1,10 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + */ /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ keymap.h diff --git a/bsp/x86/drivers/serial.c b/bsp/x86/drivers/serial.c index 51b7a0d96d..64830135fc 100644 --- a/bsp/x86/drivers/serial.c +++ b/bsp/x86/drivers/serial.c @@ -1,18 +1,14 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-09-15 QiuYi the first version * 2006-10-10 Bernard use keyboard instead of serial */ - + #include #include @@ -28,13 +24,13 @@ */ void rt_serial_init(void) { - outb(COM1+3,0x80); /* set DLAB of line control reg */ - outb(COM1,0x0c); /* LS of divisor (48 -> 2400 bps */ - outb(COM1+1,0x00); /* MS of divisor */ - outb(COM1+3,0x03); /* reset DLAB */ - outb(COM1+4,0x0b); /* set DTR,RTS, OUT_2 */ - outb(COM1+1,0x0d); /* enable all intrs but writes */ - inb(COM1); /* read data port to reset things (?) */ + outb(COM1+3,0x80); /* set DLAB of line control reg */ + outb(COM1,0x0c); /* LS of divisor (48 -> 2400 bps */ + outb(COM1+1,0x00); /* MS of divisor */ + outb(COM1+3,0x03); /* reset DLAB */ + outb(COM1+4,0x0b); /* set DTR,RTS, OUT_2 */ + outb(COM1+1,0x0d); /* enable all intrs but writes */ + inb(COM1); /* read data port to reset things (?) */ } /** @@ -44,11 +40,9 @@ void rt_serial_init(void) */ char rt_serial_getc(void) { + while(!(inb(COM1+COMSTATUS) & COMDATA)); - while(!(inb(COM1+COMSTATUS) & COMDATA)); - - return inb(COM1+COMREAD); - + return inb(COM1+COMREAD); } /** @@ -58,15 +52,15 @@ char rt_serial_getc(void) */ void rt_serial_putc(const char c) { - int val; - - while(1) - { - if ((val = inb(COM1+COMSTATUS)) & THRE) - break; - } - - outb(COM1+COMWRITE, c&0xff); + int val; + + while(1) + { + if ((val = inb(COM1+COMSTATUS)) & THRE) + break; + } + + outb(COM1+COMWRITE, c&0xff); } /*@}*/ diff --git a/bsp/x86/rtconfig.h b/bsp/x86/rtconfig.h index c4cdac1fdc..b2a9f6db50 100644 --- a/bsp/x86/rtconfig.h +++ b/bsp/x86/rtconfig.h @@ -1,180 +1,186 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 8 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 1000 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -#define RT_DEBUG_COLOR -#define RT_DEBUG_MODULE 0 +/* RT-Thread Kernel */ +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 2048 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 +#define RT_DEBUG +#define RT_DEBUG_COLOR +#define RT_DEBUG_INIT_CONFIG +#define RT_DEBUG_INIT 1 -/* Using Software Timer */ -/* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +/* Inter-Thread communication */ -/* SECTION: IPC */ -/* Using Semaphore*/ #define RT_USING_SEMAPHORE - -/* Using Mutex */ #define RT_USING_MUTEX - -/* Using Event */ #define RT_USING_EVENT - -/* Using MailBox */ #define RT_USING_MAILBOX - -/* Using Message Queue */ #define RT_USING_MESSAGEQUEUE -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL +/* Memory Management */ -/* Using Dynamic Heap Management */ +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMTRACE #define RT_USING_HEAP -/* Using Small MM */ -#define RT_USING_SMALL_MEM +/* Kernel Device Object */ -/* SECTION: Device System */ -/* Using Device System */ #define RT_USING_DEVICE - -/* SECTION: Console options */ #define RT_USING_CONSOLE -/* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "console" +#define RT_VER_NUM 0x40003 +#define ARCH_IA32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ -#define IDLE_THREAD_STACK_SIZE 1024 /* idle stack 1K */ -/* SECTION: finsh, a C-Express shell */ +/* Command shell */ + #define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_USING_MSH_ONLY -/* Using symbol table */ +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 -// #define RT_USING_LIBC -// #define RT_USING_PTHREADS - -/* SECTION: device filesystem */ - #define RT_USING_DFS +/* Device virtual file system */ +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 #define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 #define RT_DFS_ELM_WORD_ACCESS -/* Reentrancy (thread safe) of the FatFs module. */ +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_DFS_ELM_REENTRANT -/* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 -/* Maximum sector size to be handled. */ -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 - -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 - #define RT_USING_DFS_DEVFS -/* SECTION: lwip, a lighwight TCP/IP protocol stack */ -//#define RT_USING_LWIP -/* Enable ICMP protocol*/ -#define RT_LWIP_ICMP -/* Enable UDP protocol*/ -#define RT_LWIP_UDP -/* Enable TCP protocol*/ -#define RT_LWIP_TCP -/* Enable DNS */ -#define RT_LWIP_DNS - -/* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 - -/* Using DHCP */ -/* #define RT_LWIP_DHCP */ - -/* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 30 - -/* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 - -/* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 - -/* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 - -/* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 - -/* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 -/* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 - -/* SECTION: RT-Thread/GUI */ -/* #define RT_USING_RTGUI */ - -/* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 -/* support 16 weight font */ -#define RTGUI_USING_FONT16 -/* support Chinese font */ -#define RTGUI_USING_FONTHZ -/* use DFS as file interface */ -#define RTGUI_USING_DFS_FILERW -/* use font file as Chinese font */ -#define RTGUI_USING_HZ_FILE -/* use Chinese bitmap font */ -#define RTGUI_USING_HZ_BMP -/* use small size in RTGUI */ -#define RTGUI_USING_SMALL_SIZE -/* use mouse cursor */ -/* #define RTGUI_USING_MOUSE_CURSOR */ -/* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 - -/* image support */ -/* #define RTGUI_IMAGE_XPM */ -/* #define RTGUI_IMAGE_BMP */ - -// #define RT_USING_MODULE +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* games: games run on RT-Thread console */ + +#define IA32 + #endif diff --git a/bsp/x86/rtconfig.py b/bsp/x86/rtconfig.py index b833f4de49..a03f44c39c 100644 --- a/bsp/x86/rtconfig.py +++ b/bsp/x86/rtconfig.py @@ -6,14 +6,14 @@ CPU='' CROSS_TOOL='gcc' if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') + CROSS_TOOL = os.getenv('RTT_CC') # cross_tool provides the cross compiler # EXEC_PATH is the compiler execute path, for example, CodeSourcery, if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_IA32_ELF/bin' + PLATFORM = 'gcc' + EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_IA32_ELF/bin' elif CROSS_TOOL == 'keil': print('================ERROR============================') print('Not support keil yet!') @@ -26,26 +26,26 @@ elif CROSS_TOOL == 'iar': exit(0) if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') + EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' if PLATFORM == 'gcc': # toolchains - PREFIX = '' - CC = PREFIX + 'gcc -m32 -fno-builtin -fno-stack-protector -nostdinc' - AS = PREFIX + 'gcc -m32' + PREFIX = 'i686-elf-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' AR = PREFIX + 'ar' - LINK = PREFIX + 'ld -melf_i386' + LINK = PREFIX + 'gcc' TARGET_EXT = 'elf' SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = '' + DEVICE = ' -mtune=generic' CFLAGS = DEVICE + ' -Wall' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Map rtthread-ia32.map -T x86_ram.lds -nostdlib' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T x86_ram.lds -nostartfiles' CPATH = '' LPATH = '' diff --git a/bsp/x86/x86_ram.lds b/bsp/x86/x86_ram.lds index afac69f04b..089d9973c4 100644 --- a/bsp/x86/x86_ram.lds +++ b/bsp/x86/x86_ram.lds @@ -1,55 +1,62 @@ OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) ENTRY(_start) + SECTIONS { - . = 0x00100000; - - . = ALIGN(4); - .text : - { - *(.init) - *(.text) + . = 0x00100000; + + . = ALIGN(4); + .text : + { + *(.init) + *(.text) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)); + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } + + . = ALIGN(4); + .rodata : { *(.rodata*) } - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)); - __rtmsymtab_end = .; - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } + . = ALIGN(4); + .data : { *(.data) } - . = ALIGN(4); - .data : { *(.data) } + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - __bss_end = .; - - /* stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } - - _end = .; + /* stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _end = .; } diff --git a/libcpu/ia32/__udivsi3.c b/libcpu/ia32/__udivsi3.c index ec7c59d1cb..5a5622f883 100644 --- a/libcpu/ia32/__udivsi3.c +++ b/libcpu/ia32/__udivsi3.c @@ -1,11 +1,7 @@ /* - * File : __udivsi3.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/ia32/__umodsi3.c b/libcpu/ia32/__umodsi3.c index 226a2c0800..d47fe3d295 100644 --- a/libcpu/ia32/__umodsi3.c +++ b/libcpu/ia32/__umodsi3.c @@ -1,11 +1,7 @@ /* - * File : __umodsi3.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/ia32/backtrace.c b/libcpu/ia32/backtrace.c deleted file mode 100644 index b8f094d90f..0000000000 --- a/libcpu/ia32/backtrace.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * File : backtrace.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version - */ - -#include - -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - /* no implementation */ -} diff --git a/libcpu/ia32/context_gcc.S b/libcpu/ia32/context_gcc.S index a8ad867b91..32233303c7 100644 --- a/libcpu/ia32/context_gcc.S +++ b/libcpu/ia32/context_gcc.S @@ -1,11 +1,7 @@ /* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -83,31 +79,3 @@ rt_hw_context_switch_to: pop %ds add $4, %esp /* skip irqno */ iret - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - pushl %ebp - movl %esp, %ebp - movl 0xc(%ebp), %eax - movl 0x8(%ebp), %ebx - - movl $rt_thread_switch_interrupt_flag, %ecx - movl (%ecx), %edx - cmp $0x1, %edx - jz _reswitch - - movl $0x1, %edx /*set rt_thread_switch_interrupt_flag to 1*/ - movl %edx, (%ecx) - movl $rt_interrupt_from_thread, %edx /*set rt_interrupt_from_thread*/ - movl %ebx, (%edx) -_reswitch: - movl $rt_interrupt_to_thread, %edx /*set rt_interrupt_to_thread*/ - movl %eax, (%edx) - leave - ret diff --git a/libcpu/ia32/cpuport.c b/libcpu/ia32/cpuport.c new file mode 100644 index 0000000000..69032c2f87 --- /dev/null +++ b/libcpu/ia32/cpuport.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021/02/19 Bernard Implement rt_hw_context_switch_interrupt in C + */ + +#include +#include + +volatile rt_ubase_t rt_interrupt_from_thread = 0; +volatile rt_ubase_t rt_interrupt_to_thread = 0; +volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; + +rt_base_t rt_hw_interrupt_disable(void) +{ + rt_base_t level; + + __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); + return level; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); +} + +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + + return ; +} + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(--stk) = (unsigned long)parameter; + *(--stk) = (unsigned long)texit; + *(--stk) = 0x200; /*flags*/ + *(--stk) = 0x08; /*cs*/ + *(--stk) = (unsigned long)tentry; /*eip*/ + *(--stk) = 0; /*irqno*/ + *(--stk) = 0x10; /*ds*/ + *(--stk) = 0x10; /*es*/ + *(--stk) = 0; /*eax*/ + *(--stk) = 0; /*ecx*/ + *(--stk) = 0; /*edx*/ + *(--stk) = 0; /*ebx*/ + *(--stk) = 0; /*esp*/ + *(--stk) = 0; /*ebp*/ + *(--stk) = 0; /*esi*/ + *(--stk) = 0; /*edi*/ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/libcpu/ia32/hdisr_gcc.S b/libcpu/ia32/hdisr_gcc.S index 6f79fe4c2a..24c4c17990 100644 --- a/libcpu/ia32/hdisr_gcc.S +++ b/libcpu/ia32/hdisr_gcc.S @@ -1,11 +1,7 @@ /* - * File : hdisr_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/ia32/interrupt.c b/libcpu/ia32/interrupt.c index e620cbe76c..d597848c52 100644 --- a/libcpu/ia32/interrupt.c +++ b/libcpu/ia32/interrupt.c @@ -1,38 +1,20 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015/9/15 Bernard Update to new interrupt framework. */ -#include #include +#include #include -extern rt_uint32_t rt_interrupt_nest; extern void rt_hw_idt_init(void); -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - /* exception and interrupt handler table */ struct rt_irq_desc irq_desc[MAX_HANDLERS]; @@ -50,45 +32,39 @@ void rt_hw_interrupt_handle(int vector, void* param); */ void rt_hw_pic_init() { - outb(IO_PIC1, 0x11); - outb(IO_PIC1+1, IRQ_OFFSET); - outb(IO_PIC1+1, 1<> 8)); - } - - /* init interrupt nest, and context */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + outb(IO_PIC1, 0x11); + outb(IO_PIC1+1, IRQ_OFFSET); + outb(IO_PIC1+1, 1<> 8)); + } } void rt_hw_interrupt_handle(int vector, void* param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } void rt_hw_isr(int vector) { - if (vector < MAX_HANDLERS) - { - irq_desc[vector].handler(vector, irq_desc[vector].param); - } + if (vector < MAX_HANDLERS) + { + irq_desc[vector].handler(vector, irq_desc[vector].param); + } } /** @@ -97,10 +73,10 @@ void rt_hw_isr(int vector) */ void rt_hw_interrupt_init(void) { - int idx; - - rt_hw_idt_init(); - rt_hw_pic_init(); + int idx; + + rt_hw_idt_init(); + rt_hw_pic_init(); /* init exceptions table */ for(idx=0; idx < MAX_HANDLERS; idx++) @@ -116,16 +92,16 @@ void rt_hw_interrupt_init(void) void rt_hw_interrupt_umask(int vector) { - irq_mask_8259A = irq_mask_8259A&~(1<> 8)); + irq_mask_8259A = irq_mask_8259A&~(1<> 8)); } void rt_hw_interrupt_mask(int vector) { - irq_mask_8259A = irq_mask_8259A | (1<> 8)); + irq_mask_8259A = irq_mask_8259A | (1<> 8)); } rt_isr_handler_t rt_hw_interrupt_install(int vector, @@ -152,17 +128,4 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, return old_handler; } -rt_base_t rt_hw_interrupt_disable(void) -{ - rt_base_t level; - - __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); - return level; -} - -void rt_hw_interrupt_enable(rt_base_t level) -{ - __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); -} - /*@}*/ diff --git a/libcpu/ia32/showmem.c b/libcpu/ia32/showmem.c deleted file mode 100644 index 38f037f83d..0000000000 --- a/libcpu/ia32/showmem.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * File : showmem.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include - -void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) -{ - int i = 0, j =0; - - RT_ASSERT(addr); - - addr = addr & ~0xF; - size = 4*((size + 3)/4); - - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); - - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - - addr += 4; - i++; - } - - rt_kprintf("\n"); - } - - return; -} diff --git a/libcpu/ia32/stack.c b/libcpu/ia32/stack.c deleted file mode 100644 index 9d656a73d6..0000000000 --- a/libcpu/ia32/stack.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - */ - -#include - -#include - -/** - * @addtogroup I386 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - unsigned long *stk; - - stk = (unsigned long *)stack_addr; - *(--stk) = (unsigned long)parameter; - *(--stk) = (unsigned long)texit; - *(--stk) = 0x200; /*flags*/ - *(--stk) = 0x08; /*cs*/ - *(--stk) = (unsigned long)tentry; /*eip*/ - *(--stk) = 0; /*irqno*/ - *(--stk) = 0x10; /*ds*/ - *(--stk) = 0x10; /*es*/ - *(--stk) = 0; /*eax*/ - *(--stk) = 0; /*ecx*/ - *(--stk) = 0; /*edx*/ - *(--stk) = 0; /*ebx*/ - *(--stk) = 0; /*esp*/ - *(--stk) = 0; /*ebp*/ - *(--stk) = 0; /*esi*/ - *(--stk) = 0; /*edi*/ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} -/*@}*/ diff --git a/libcpu/ia32/start_gcc.S b/libcpu/ia32/start_gcc.S index 84adc83fe2..ee7d2787fd 100644 --- a/libcpu/ia32/start_gcc.S +++ b/libcpu/ia32/start_gcc.S @@ -1,11 +1,7 @@ /* - * File : start.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -52,8 +48,8 @@ multiboot_entry: pushl $0 popf - /*rebuild globe describe table*/ - lgdt mygdtdesc + /* rebuild globe describe table */ + lgdt __gdtdesc movl $0x10,%eax movw %ax,%ds @@ -77,7 +73,7 @@ spin: .data .p2align 2 -mygdt: +__gdt: .word 0,0,0,0 .word 0x07FF /* 8Mb - limit=2047 */ @@ -90,8 +86,8 @@ mygdt: .word 0x9200 /* data read/write */ .word 0x00C0 -mygdtdesc: +__gdtdesc: .word 0x17 - .long mygdt + .long __gdt /*@}*/ diff --git a/libcpu/ia32/trap.c b/libcpu/ia32/trap.c index 5e9a51d6d2..172a078273 100644 --- a/libcpu/ia32/trap.c +++ b/libcpu/ia32/trap.c @@ -1,18 +1,14 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ - -#include + #include +#include #include @@ -29,6 +25,7 @@ struct Pseudodesc idt_pd = extern rt_isr_handler_t isr_table[]; extern rt_isr_handler_t trap_func[]; extern rt_isr_handler_t hdinterrupt_func[]; +extern void rt_hw_interrupt_handle(int vector, void* param); /** * @addtogroup I386 @@ -41,7 +38,7 @@ extern rt_isr_handler_t hdinterrupt_func[]; */ void rt_hw_idt_init(void) { - extern void Xdefault; + extern void Xdefault(void); int i, j, func; // install a default handler @@ -92,7 +89,7 @@ void rt_hw_trap_irq(int trapno) rt_kprintf("General protection interrupt\n"); RT_ASSERT(0); case T_DEFAULT: - rt_hw_interrupt_handle(T_DEFAULT); + rt_hw_interrupt_handle(T_DEFAULT, RT_NULL); return; } diff --git a/libcpu/ia32/trapisr_gcc.S b/libcpu/ia32/trapisr_gcc.S index be7e97a5fb..82887ecda3 100644 --- a/libcpu/ia32/trapisr_gcc.S +++ b/libcpu/ia32/trapisr_gcc.S @@ -1,11 +1,7 @@ /* - * File : trapisr_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -22,6 +18,7 @@ .globl proc;\ .type proc,@function;\ proc: + #define TRAPFNC(name,num)\ ENTRY(name)\ pushl $(num);\ @@ -29,6 +26,7 @@ .data;\ .long name;\ .text + #define TRAPFNC_NOEC(name,num)\ ENTRY(name)\ pushl $0;\ @@ -54,17 +52,17 @@ TRAPFNC_NOEC(Xoflow, 4) TRAPFNC_NOEC(Xbound, 5) TRAPFNC_NOEC(Xillop, 6) TRAPFNC_NOEC(Xdevice, 7) -TRAPFNC (Xdblflt, 8) -TRAPFNC (Xtss, 9) -TRAPFNC (Xsegnp, 10) -TRAPFNC (Xstack, 11) -TRAPFNC (Xgpflt, 12) -TRAPFNC (Xpgflt, 13) +TRAPFNC (Xdblflt, 8) +TRAPFNC (Xtss, 9) +TRAPFNC (Xsegnp, 10) +TRAPFNC (Xstack, 11) +TRAPFNC (Xgpflt, 12) +TRAPFNC (Xpgflt, 13) TRAPFNC_NOEC(Xfperr, 14) -TRAPFNC (Xalign, 15) +TRAPFNC (Xalign, 15) /* default handler -- not for any specific trap */ -TRAPFNC (Xdefault, 500) +TRAPFNC (Xdefault, 500) .p2align 4,0x90 .globl _traps -- cgit v1.3.1