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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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* the the People's Republic of China and other countries.
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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#ifndef __PLATFORM_GPIO_H__
#define __PLATFORM_GPIO_H__

#ifdef __cplusplus
extern "C" {
#endif

#define GPIO_MAX_BANK PN_BASE
#define BANK_BOUNDARY PL_BASE
#define SUNXI_GPIO_R_PBASE 0x07022000

#if defined(CONFIG_DRIVERS_INTC)
#define SUNXI_IRQ_R_GPIOL   (RINTC_IRQ_MASK | 6)
#define SUNXI_IRQ_R_GPIOM   (RINTC_IRQ_MASK | 7)
#define SUNXI_IRQ_R_GPION   (RINTC_IRQ_MASK | 8)
#endif

typedef enum
{
    GPIO_PL0 = GPIOL(0),
    GPIO_PL1 = GPIOL(1),
    GPIO_PL2 = GPIOL(2),
    GPIO_PL3 = GPIOL(3),
    GPIO_PL4 = GPIOL(4),
    GPIO_PL5 = GPIOL(5),
    GPIO_PL6 = GPIOL(6),
    GPIO_PL7 = GPIOL(7),
    GPIO_PL8 = GPIOL(8),
    GPIO_PL9 = GPIOL(9),
    GPIO_PL10 = GPIOL(10),

    GPIO_PM0 = GPIOM(0),
    GPIO_PM1 = GPIOM(1),
    GPIO_PM2 = GPIOM(2),
    GPIO_PM3 = GPIOM(3),
    GPIO_PM4 = GPIOM(4),
    GPIO_PM5 = GPIOM(5),
    GPIO_PM6 = GPIOM(6),
    GPIO_PM7 = GPIOM(7),
    GPIO_PM8 = GPIOM(8),

    GPIO_PN0 = GPION(0),
    GPIO_PN1 = GPION(1),
    GPIO_PN2 = GPION(2),
    GPIO_PN3 = GPION(3),
    GPIO_PN4 = GPION(4),
    GPIO_PN5 = GPION(5),
    GPIO_PN6 = GPION(6),
    GPIO_PN7 = GPION(7),
    GPIO_PN8 = GPION(8),
    GPIO_PN9 = GPION(9),
    GPIO_PN10 = GPION(10),
    GPIO_PN11 = GPION(11),
    GPIO_PN12 = GPION(12),
    GPIO_PN13 = GPION(13),
    GPIO_PN14 = GPION(14),
    GPIO_PN15 = GPION(15),
    GPIO_PN16 = GPION(16),
    GPIO_PN17 = GPION(17),
    GPIO_PN18 = GPION(18),
    GPIO_PN19 = GPION(19),
    GPIO_PN20 = GPION(20),
    GPIO_PN21 = GPION(21),
    GPIO_PN22 = GPION(22),
    GPIO_PN23 = GPION(23),

} gpio_pin_t;

#ifdef __cplusplus
}
#endif
#endif /* __PLATFORM_GPIO_H__ */