/*
* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
*
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* the the people's Republic of China and other countries.
* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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*/
#ifndef __SUN8IW18_DMIC_H_
#define __SUN8IW18_DMIC_H_

#define SUNXI_DMIC_MEMBASE (0x05095000)

/*------------------------ CLK CONFIG FOR NORMAL ---------------------------*/
#define SUNXI_DMIC_CLK_PLL_AUDIO    HAL_CLK_PLL_AUDIO
#define SUNXI_DMIC_CLK_DMIC     HAL_CLK_PERIPH_DMIC
#define SUNXI_DMIC_CLK_BUS      0
#define SUNXI_DMIC_CLK_RST      0

/*------------------------ PIN CONFIG FOR NORMAL ---------------------------*/
dmic_gpio_t g_dmic_gpio = {
    .clk    = {GPIOB(12), 3},
    .din0   = {GPIOB(11), 3},
    .din1   = {GPIOB(10), 3},
    .din2   = {GPIOB(9), 3},
    .din3   = {GPIOB(8), 3},
};

/*------------------------ SUNXI DMIC EXP DEFINE ---------------------------*/
/*0x00:SUNXI_DMIC_EN*/
#define DMIC_MAD_DATA_EN               31
/*SUNXI_DMIC_FIFO_STA:0x20*/
#define DMIC_MAD_DATA_ALIGN            8

#endif /* __SUN8IW18_DMIC_H_ */