/*
* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
*
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* the the people's Republic of China and other countries.
* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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*/
#ifndef __SUN8IW20_DMIC_H_
#define __SUN8IW20_DMIC_H_

#define SUNXI_DMIC_MEMBASE (0x02031000)

/*------------------------ CLK CONFIG FOR NORMAL ---------------------------*/
#define SUNXI_DMIC_CLK_PLL_AUDIO    CLK_PLL_AUDIO0
#define SUNXI_DMIC_CLK_DMIC     CLK_DMIC
#define SUNXI_DMIC_CLK_BUS      CLK_BUS_DMIC
#define SUNXI_DMIC_CLK_RST      RST_BUS_DMIC

/*------------------------ PIN CONFIG FOR NORMAL ---------------------------*/



/*------------------------ PIN CONFIG FOR FPGA VERIFY -----------------------*/
dmic_gpio_t g_dmic_gpio = {
    .clk    = {GPIOF(9), 2},
    .din0   = {GPIOF(28), 2},
    .din1   = {GPIOG(30), 2},
    .din2   = {GPIOG(28), 2},
    .din3   = {GPIOG(26), 2},
};

#endif /* __SUN8IW20_DMIC_H_ */