/*
** ###################################################################
**     Processors:          MCXN236VDF
**                          MCXN236VNL
**
**     Compiler:            IAR ANSI C/C++ Compiler for ARM
**     Reference manual:    MCXN23XRM
**     Version:             rev. 1.0, 2021-08-03
**     Build:               b240320
**
**     Abstract:
**         Linker file for the IAR ANSI C/C++ Compiler for ARM
**
**     Copyright 2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2024 NXP
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
** ###################################################################
*/


/* USB BDT size */
define symbol usb_bdt_size             = 0x0;
/* Stack and Heap Sizes */
if (isdefinedsymbol(__stack_size__)) {
  define symbol __size_cstack__        = __stack_size__;
} else {
  define symbol __size_cstack__        = 0x0400;
}

if (isdefinedsymbol(__heap_size__)) {
  define symbol __size_heap__          = __heap_size__;
} else {
  define symbol __size_heap__          = 0x2000;
}

define symbol m_interrupts_start               = 0x00000000;
define symbol m_interrupts_end                 = 0x000003FF;

define symbol m_text_start                     = 0x00000400;
define symbol m_text_end                       = 0x000FFFFF;

define symbol m_data_start                     = 0x20000000;
define symbol m_data_end                       = 0x20037FFF;

define symbol m_sramx_start                    = 0x04000000;
define symbol m_sramx_end                      = 0x04017FFF;


define memory mem with size = 4G;

define region TEXT_region             = mem:[from m_interrupts_start to m_interrupts_end]
                                      | mem:[from m_text_start to m_text_end];

define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__] |
                            mem:[from m_sramx_start to m_sramx_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];

define block CSTACK        with alignment = 8, size = __size_cstack__   { };
define block HEAP          with alignment = 8, size = __size_heap__     { };
define block RW            { readwrite };
define block ZI            { zi };
define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
define block QACCESS_CODE  { section CodeQuickAccess };
define block QACCESS_DATA  { section DataQuickAccess };

initialize by copy { readwrite, section .textrw };

if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
  /* Required in a multi-threaded application */
  initialize by copy with packing = none { section __DLIB_PERTHREAD };
}

place at address mem: m_interrupts_start    { readonly section .intvec };
place in TEXT_region                        { readonly };
place in DATA_region                        { block RW };
place in DATA_region                        { block ZI };
place in DATA_region                        { last block HEAP };
place in CSTACK_region                      { block CSTACK };
place in DATA_region                        { block NCACHE_VAR };
place in DATA_region                        { block QACCESS_CODE };
place in DATA_region                        { block QACCESS_DATA };