QEMU virt64 AArch64 SMP Bring-up Timeline
CPU0 enters the scheduler first, then main_thread_entry wakes the remaining CPUs through PSCI.
Firmware / PSCI
BootROM, BL1, CPU_ON handler
Boot CPU ASM
entry_point.S
Boot CPU C
components.c / setup.c
Secondary CPU ASM
_secondary_cpu_entry
Secondary CPU C
rt_hw_secondary_cpu_bsp_start
Scheduler
CPU0 first, then CPU1..N-1
1
jump to _start, x0 = DTB
2
EL1h, clear BSS, set SP_EL1, enable early MMU
3
branch to rtthread_startup()
4
rt_hw_common_setup: full MMU, GIC, UART, GTIMER, SMP IPI
5
rt_system_scheduler_start() on CPU0
6
main_thread_entry becomes the first running thread
7
rt_hw_secondary_cpu_up(): resolve entry PA and issue CPU_ON
8
firmware wakes the target core at _secondary_cpu_entry
9
read MPIDR, set TPIDR/stack, reuse early MMU
10
branch to rt_hw_secondary_cpu_bsp_start()
Convergence point
CPU0 arrives first through rtthread_startup().
CPU1..N-1 join after local BSP initialization.