path: root/bsp/beaglebone/AM335x_sk_DDR3.mac

// -----------------------------------------------------------------------
// This file contains the initial set up configuration for the AM335x.
//-------------------------------------------------------------------------

__var clk_in;

CHGBIT (addr, mask, data)
{
__var reg;
	reg  = __readMemory32(addr, "Memory");
	reg &= ~mask;
	reg |=  data;
  __writeMemory32(reg, addr, "Memory");
}

CLRBIT (addr, mask)
{
__var reg;
	reg  = __readMemory32(addr, "Memory");
	reg &= ~mask;
  __writeMemory32(reg, addr, "Memory");
}

SETBIT (addr, mask)
{
__var reg;
	reg  = __readMemory32(addr, "Memory");
	reg |= mask;
  __writeMemory32(reg, addr, "Memory");
}

TESTBIT (addr, mask)
{
	return(__readMemory32(addr, "Memory") & mask);
}


get_input_clock_frequency()
{
	__var temp;
	
	temp = __readMemory32(((0x44E10000) + 0x40), "Memory");
	temp = temp >> 22;
        temp = temp & 0x3;

	if(temp == 0)
	{	
		clk_in = 19;  //19.2MHz
		__message "Input Clock Read from SYSBOOT[15:14]:  19.2MHz\n";
	}	
	if(temp == 1)
	{
		clk_in = 24;  //24MHz
		__message "Input Clock Read from SYSBOOT[15:14]:  24MHz\n";
	}	
	if(temp == 2)
	{
		clk_in = 25;  //25MHz
		__message "Input Clock Read from SYSBOOT[15:14]:  25MHz\n";
	}	
	if(temp == 3)
	{ 
		clk_in = 26;  //26MHz
		__message "Input Clock Read from SYSBOOT[15:14]:  26MHz\n";
	}	
}

mpu_pll_config( clk_in,  N,  M,  M2)
{
	__var ref_clk,clk_out;
	__var clkmode,clksel,div_m2,idlest_dpll;
	__var temp,i;

	ref_clk     = clk_in/(N+1);
	clk_out     = (ref_clk*M)/M2;

	clkmode=__readMemory32((0x44E00000 + 0x488), "Memory");
	clksel= __readMemory32((0x44E00000 + 0x42C), "Memory");
	div_m2= __readMemory32((0x44E00000 + 0x4A8), "Memory");

	__message "****  Going to Bypass... \n";

	//put the DPLL in bypass mode
	__writeMemory32(0x4, (0x44E00000 + 0x488), "Memory");

	while(((__readMemory32((0x44E00000 + 0x420), "Memory") & 0x101) != 0x00000100)); //wait for bypass status

	__message "****  Bypassed, changing values... \n";

	//set multiply and divide values
	clksel = clksel & (~0x7FFFF);
	clksel = clksel | ((M <<0x8) | N);
	__writeMemory32(clksel, (0x44E00000 + 0x42C), "Memory");
	div_m2 = div_m2 & ~0x1F;
	div_m2 = div_m2 | M2;  
	__writeMemory32(div_m2, (0x44E00000 + 0x4A8), "Memory");

	__message "****  Locking ARM PLL\n";

	//now lock the DPLL
	clkmode = clkmode | 0x7;  //enables lock mode
	__writeMemory32(clkmode, (0x44E00000 + 0x488), "Memory");
	while(((__readMemory32((0x44E00000 + 0x420), "Memory") & 0x101) != 0x1)); //wait for lock
}


core_pll_config( clk_in,  N,  M,  M4,  M5,  M6)
{
	__var ref_clk,clk_out4,clk_out5,clk_out6;
	__var clkmode,clksel,div_m4,div_m5,div_m6,idlest_dpll;

	ref_clk     = clk_in/(N+1);
	clk_out4     = (ref_clk*M)/M4;  //M4=200MHz
	clk_out5     = (ref_clk*M)/M5;  //M5=250MHz
	clk_out6     = (ref_clk*M)/M6;  //M6=500MHz

	clkmode= __readMemory32((0x44E00000 + 0x490), "Memory");
	clksel= __readMemory32((0x44E00000 + 0x468), "Memory");
	div_m4= __readMemory32((0x44E00000 + 0x480), "Memory"); 
	div_m5= __readMemory32((0x44E00000 + 0x484), "Memory"); 
	div_m6= __readMemory32((0x44E00000 + 0x4D8), "Memory"); 

	//put DPLL in bypass mode
	clkmode = (clkmode & 0xfffffff8)|0x00000004;
	__writeMemory32(clkmode, (0x44E00000 + 0x490), "Memory");
	while((__readMemory32((0x44E00000 + 0x45C),  "Memory") & 0x00000100 )!=0x00000100); //wait for bypass status

	__message "****  Core Bypassed\n";

	//set multiply and divide values
	clksel = clksel & (~0x7FFFF);
	clksel = clksel | ((M <<0x8) | N);
	__writeMemory32(clksel, (0x44E00000 + 0x468), "Memory");
	div_m4= M4;   //200MHz
	__writeMemory32(div_m4, (0x44E00000 + 0x480), "Memory");
	div_m5=  M5;  //250MHz
	__writeMemory32(div_m5, (0x44E00000 + 0x484), "Memory");
	div_m6=  M6;  //500MHz
	__writeMemory32(div_m6, (0x44E00000 + 0x4D8), "Memory");

	__message "****  Now locking Core...\n";

	//now lock the PLL
	clkmode =(clkmode&0xfffffff8)|0x00000007;
	__writeMemory32(clkmode, (0x44E00000 + 0x490), "Memory");

	while((__readMemory32((0x44E00000 + 0x45C), "Memory") & 0x00000001 )!=0x00000001);
	__message "****  Core locked\n";
}

ddr_pll_config( clk_in,  N,  M,  M2)
{
	__var ref_clk,clk_out ;
	__var clkmode,clksel,div_m2,idlest_dpll;                

	ref_clk     = clk_in/(N+1);
	clk_out     = (ref_clk*M)/M2;

	clkmode=__readMemory32((0x44E00000 + 0x494), "Memory");
	clksel= __readMemory32((0x44E00000 + 0x440), "Memory");
	div_m2= __readMemory32((0x44E00000 + 0x4A0), "Memory");

	clkmode =(clkmode&0xfffffff8)|0x00000004;
	__writeMemory32(clkmode, (0x44E00000 + 0x494), "Memory");
	while((__readMemory32((0x44E00000 + 0x434), "Memory") & 0x00000100 )!=0x00000100);

	__message "****  DDR DPLL Bypassed\n";

	clksel = clksel & (~0x7FFFF);
	clksel = clksel | ((M <<0x8) | N);
	__writeMemory32(clksel, (0x44E00000 + 0x440), "Memory");
	div_m2 = __readMemory32((0x44E00000 + 0x4A0), "Memory");
	div_m2 = (div_m2&0xFFFFFFE0) | M2;
	__writeMemory32(div_m2, (0x44E00000 + 0x4A0), "Memory");
	clkmode =(clkmode&0xfffffff8)|0x00000007;
	__writeMemory32(clkmode, (0x44E00000 + 0x494), "Memory");

	while((__readMemory32((0x44E00000 + 0x434), "Memory") & 0x00000001 )!=0x00000001);

	__message "****  DDR DPLL Locked\n";
}

per_pll_config( clk_in,  N,  M,  M2)
{
	__var ref_clk,clk_out;
	__var clkmode,clksel,div_m2,idlest_dpll;

	ref_clk     = clk_in/(N+1);
	clk_out     = (ref_clk*M)/M2;

	clkmode=__readMemory32((0x44E00000 + 0x48C), "Memory");
	clksel= __readMemory32((0x44E00000 + 0x49C), "Memory");
	div_m2= __readMemory32((0x44E00000 + 0x4AC), "Memory");

	clkmode =(clkmode&0xfffffff8)|0x00000004;
	__writeMemory32(clkmode, (0x44E00000 + 0x48C), "Memory");
	while((__readMemory32((0x44E00000 + 0x470), "Memory") & 0x00000100 )!=0x00000100);

	__message "****  PER DPLL Bypassed\n";

	clksel = clksel & (~0x7FFFF);
	clksel = clksel | ((M <<0x8) | N);
	__writeMemory32(clksel, (0x44E00000 + 0x49C), "Memory");
	div_m2= 0xFFFFFF80 | M2;
	__writeMemory32(div_m2, (0x44E00000 + 0x4AC), "Memory");
	clkmode =(clkmode&0xfffffff8)|0x00000007;
	__writeMemory32(clkmode,(0x44E00000 + 0x48C), "Memory");

	while((__readMemory32((0x44E00000 + 0x470), "Memory") & 0x00000001 )!=0x00000001);

	__message "****  PER DPLL Locked\n";
}

disp_pll_config( clk_in,  N,  M,  M2)
{
	__var ref_clk,clk_out;
	__var clkmode,clksel,div_m2,idlest_dpll;

	__message "****  DISP PLL Config is in progress .......... \n";	

	ref_clk     = clk_in/(N+1);
	clk_out     = (ref_clk*M)/M2;

	clkmode=__readMemory32((0x44E00000 + 0x498), "Memory");
	clksel= __readMemory32((0x44E00000 + 0x454), "Memory");
	div_m2= __readMemory32((0x44E00000 + 0x4A4), "Memory");

	clkmode =(clkmode&0xfffffff8)|0x00000004;
	__writeMemory32(clkmode, (0x44E00000 + 0x498), "Memory");
	while((__readMemory32((0x44E00000 + 0x448), "Memory") & 0x00000100 )!=0x00000100);

	clksel = clksel & (~0x7FFFF);
	clksel = clksel | ((M <<0x8) | N);
	__writeMemory32(clksel, (0x44E00000 + 0x454), "Memory");
	div_m2= 0xFFFFFFE0 | M2;
	__writeMemory32(div_m2, (0x44E00000 + 0x4A4), "Memory");
	clkmode =(clkmode&0xfffffff8)|0x00000007;
	__writeMemory32(clkmode, (0x44E00000 + 0x498), "Memory");

	while((__readMemory32((0x44E00000 + 0x448), "Memory") & 0x00000001 )!=0x00000001);

	__message "****  DISP PLL Config is DONE .......... \n";
}

arm_opp120_config()
{
	__message "****  Subarctic ALL ADPLL Config for OPP == OPP100 is In Progress ......... \n";
    get_input_clock_frequency();

    if (clk_in == 24)
	{
		mpu_pll_config(clk_in, 23, 550, 1);
		core_pll_config(clk_in, 23, 1000, 10, 8, 4);
		ddr_pll_config(clk_in, 23, 303, 1);
		per_pll_config(clk_in, 23, 960, 5);
		disp_pll_config(clk_in, 23, 48, 1);
		__message "****  Subarctic ALL ADPLL Config for OPP == OPP100 is Done ......... \n";
	}
    else
    {
		__message "****  Subarctic PLL Config failed!!  Check SYSBOOT[15:14] for proper input freq config \n";
    }

}


emif_prcm_clk_enable()
{
	   __message "EMIF PRCM is in progress ....... \n";

   	   __writeMemory32(0x2, (0x44E00000 + 0x0D0), "Memory");
       __writeMemory32(0x2, (0x44E00000 + 0x028), "Memory");
   	   while(__readMemory32((0x44E00000 + 0x028), "Memory")!= 0x02);

	   __message "EMIF PRCM Done \n";
}

vtp_enable()
{
      /* Write 1 to enable VTP */
      __writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") | 0x00000040),((0x44E10000) + 0x0E0C) , "Memory");
      /* Write 0 to CLRZ bit */
	  __writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") & 0xFFFFFFFE),((0x44E10000) + 0x0E0C) ,"Memory");
      /* Write 1 to CLRZ bit */
      __writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") | 0x00000001),((0x44E10000) + 0x0E0C) , "Memory");
	  __message "Waiting for VTP Ready .......\n";
	  while((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") & 0x00000020) != 0x00000020);	 

           __message "VTP Enable Done \n";
}

cmd_macro_config( REG_PHY_CTRL_SLAVE_RATIO_value, CMD_REG_PHY_CTRL_SLAVE_FORCE_value, CMD_REG_PHY_CTRL_SLAVE_DELAY_value, PHY_DLL_LOCK_DIFF_value, CMD_PHY_INVERT_CLKOUT_value)
{
	   __message "\DDR PHY CMD0 Register configuration is in progress ....... \n";

	   __writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x01C + (0x44E12000)), "Memory");		     	
       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x020 + (0x44E12000)), "Memory");                   	
       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x024 + (0x44E12000)), "Memory");                   	
	   __writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x028 + (0x44E12000)), "Memory");   	             	
	   __writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x02C + (0x44E12000)), "Memory");

	   __message "\DDR PHY CMD1 Register configuration is in progress ....... \n";

	   __writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x050 + (0x44E12000)), "Memory");		     	
       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x054 + (0x44E12000)), "Memory");                   	
       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x058 + (0x44E12000)), "Memory");                   	
	   __writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x05C + (0x44E12000)), "Memory");   	             	
	   __writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x060 + (0x44E12000)), "Memory");

	   __message "\DDR PHY CMD2 Register configuration is in progress ....... \n";

	   __writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x084 + (0x44E12000)), "Memory");		     	
       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x088 + (0x44E12000)), "Memory");                   	
       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x08C + (0x44E12000)), "Memory");                   	
	   __writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x090 + (0x44E12000)), "Memory");   	             	
	   __writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x094 + (0x44E12000)), "Memory"); 	             	
}

data_macro_config( dataMacroNum, PHY_RD_DQS_SLAVE_RATIO_value, PHY_WR_DQS_SLAVE_RATIO_value, REG_PHY_WRLVL_INIT_RATIO_value,
		   REG_PHY_GATELVL_INIT_RATIO_value, REG_PHY_FIFO_WE_SLAVE_RATIO_value, REG_PHY_WR_DATA_SLAVE_RATIO_value)
{
        __var offset;
	if(dataMacroNum == 0)
	{
		offset = 0x00;
		__message "DDR PHY DATA0 Register configuration is in progress ....... \n";
	}
	else if(dataMacroNum == 1)
	{
		offset = 0xA4;
		__message "DDR PHY DATA1 Register configuration is in progress ....... \n";
	}	  
	
	__writeMemory32(((PHY_RD_DQS_SLAVE_RATIO_value<<30)|(PHY_RD_DQS_SLAVE_RATIO_value<<20)|(PHY_RD_DQS_SLAVE_RATIO_value<<10)|(PHY_RD_DQS_SLAVE_RATIO_value<<0)), ((0x0C8 + (0x44E12000)) + offset), "Memory");
	__writeMemory32(PHY_RD_DQS_SLAVE_RATIO_value>>2, ((0x0CC + (0x44E12000)) + offset), "Memory");

    __writeMemory32(((PHY_WR_DQS_SLAVE_RATIO_value<<30)|(PHY_WR_DQS_SLAVE_RATIO_value<<20)|(PHY_WR_DQS_SLAVE_RATIO_value<<10)|(PHY_WR_DQS_SLAVE_RATIO_value<<0)), ((0x0DC + (0x44E12000)) + offset), "Memory");
	__writeMemory32(PHY_WR_DQS_SLAVE_RATIO_value>>2, ((0x0E0 + (0x44E12000)) + offset), "Memory");

	__writeMemory32(((REG_PHY_WRLVL_INIT_RATIO_value<<30)|(REG_PHY_WRLVL_INIT_RATIO_value<<20)|(REG_PHY_WRLVL_INIT_RATIO_value<<10)|(REG_PHY_WRLVL_INIT_RATIO_value<<0)), ((0x0F0 + (0x44E12000)) + offset), "Memory");
	__writeMemory32(REG_PHY_WRLVL_INIT_RATIO_value>>2, ((0x0F4 + (0x44E12000)) + offset), "Memory");

    __writeMemory32(((REG_PHY_GATELVL_INIT_RATIO_value<<30)|(REG_PHY_GATELVL_INIT_RATIO_value<<20)|(REG_PHY_GATELVL_INIT_RATIO_value<<10)|(REG_PHY_GATELVL_INIT_RATIO_value<<0)), ((0x0FC + (0x44E12000)) + offset), "Memory");
	__writeMemory32(REG_PHY_GATELVL_INIT_RATIO_value>>2, ((0x100 + (0x44E12000)) + offset), "Memory");

	__writeMemory32(((REG_PHY_FIFO_WE_SLAVE_RATIO_value<<30)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<20)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<10)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<0)), ((0x108 + (0x44E12000)) + offset), "Memory");
	__writeMemory32(REG_PHY_FIFO_WE_SLAVE_RATIO_value>>2,((0x10C + (0x44E12000)) + offset), "Memory");

	__writeMemory32(((REG_PHY_WR_DATA_SLAVE_RATIO_value<<30)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<20)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<10)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<0)),((0x120 + (0x44E12000)) + offset), "Memory");
	__writeMemory32(REG_PHY_WR_DATA_SLAVE_RATIO_value>>2, ((0x124 + (0x44E12000)) + offset), "Memory");	  
	__writeMemory32(0x0,((0x138 + (0x44E12000)) + offset), "Memory");	  
}


emif_mmr_config( Read_Latency, Timing1, Timing2, Timing3, Sdram_Config, Ref_Ctrl)
{
	__var i;

	__message "emif Timing register configuration is in progress ....... \n";
	 
	__writeMemory32(Read_Latency, (0x4C000000 + 0x0E4), "Memory");
	__writeMemory32(Read_Latency, (0x4C000000 + 0x0E8), "Memory");
	__writeMemory32(Read_Latency, (0x4C000000 + 0x0EC), "Memory");

	__writeMemory32(Timing1, (0x4C000000 + 0x018), "Memory");
	__writeMemory32(Timing1, (0x4C000000 + 0x01C), "Memory");

	__writeMemory32(Timing2, (0x4C000000 + 0x020), "Memory");
	__writeMemory32(Timing2, (0x4C000000 + 0x024), "Memory");

	__writeMemory32(Timing3, (0x4C000000 + 0x028), "Memory");
	__writeMemory32(Timing3, (0x4C000000 + 0x02C), "Memory");

	__writeMemory32(Sdram_Config, (0x4C000000 + 0x008), "Memory");
	__writeMemory32(Sdram_Config, (0x4C000000 + 0x00C), "Memory");
	__writeMemory32(0x00004650, (0x4C000000 + 0x010), "Memory");
	__writeMemory32(0x00004650, (0x4C000000 + 0x014), "Memory"); 

	for(i=0;i<5000;i++)
    {
    }

	__writeMemory32(Ref_Ctrl, (0x4C000000 + 0x010), "Memory");
	__writeMemory32(Ref_Ctrl, (0x4C000000 + 0x014), "Memory"); 

	__writeMemory32(Sdram_Config, (0x4C000000 + 0x008), "Memory");
	__writeMemory32(Sdram_Config, (0x4C000000 + 0x00C), "Memory");

	__message "emif Timing register configuration is done ....... \n";
}

gpio_module_clk_config()
{
   __var buff;

   buff = __readMemory32((0x400 + 0x44E00000 + 0x8), "Memory");

   buff |= 0x2;

   __writeMemory32(buff, (0x400 + 0x44E00000 + 0x8), "Memory");

   while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x3) != 0x2); 

   buff = __readMemory32((0x400 + 0x44E00000 + 0x8), "Memory");

   buff |= 0x00040000;

   __writeMemory32(buff, (0x400 + 0x44E00000 + 0x8), "Memory");

   while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x00040000) != 0x00040000);

   while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x00030000) != 0x0);

   while((__readMemory32((0x400 + 0x44E00000), "Memory") & 0x00000100) != 0x00000100);

   __message "GPIO module clock configuration is done ....... \n";

}

phy_config_cmd()
{
    __var i;

    for(i = 0; i < 3; i++)
    {
        __message "DDR PHY CMD Register configuration is in progress ....... \n";
 
        __writeMemory32(0x40, ((0x44E12000 + 0x01c) + (i * 0x34)), "Memory");

        __writeMemory32(0x1, ((0x44E12000 + 0x02c) + (i * 0x34)), "Memory");

    }

}

phy_config_data()
{
    __var i;

    for(i = 0; i < 2; i++)
    {
        __message "DDR PHY Data Register configuration is in progress ....... \n";

        __writeMemory32(0x3B, ((0x44E12000 + 0x0c8) + (i * 0xA4)), "Memory");

        __writeMemory32(0x85, ((0x44E12000 + 0x0DC) + (i * 0xA4)), "Memory");

        __writeMemory32(0x100, ((0x44E12000 + 0x108) + (i * 0xA4)), "Memory");

        __writeMemory32(0xC1, ((0x44E12000 + 0x120) + (i * 0xA4)), "Memory");

    }

}

ddr3_emif_config()
{
        __message "****  AM335x OPP120 DDR3 EMIF and PHY configuration is in progress......... \n";

	emif_prcm_clk_enable();

	__message "DDR PHY Configuration In progress \n";

        /* Perform GPIO module clock configuration. */
        gpio_module_clk_config();

        __writeMemory32(0x00000067, (0x44E10000 + 0x964), "Memory");

        __writeMemory32((__readMemory32((0x44E07000 + 0x130), "Memory") & 0xFFFFFFFE), (0x44E07000 + 0x130), "Memory");

        __writeMemory32((__readMemory32((0x44E07000 + 0x10), "Memory") | 0x02), (0x44E07000 + 0x10), "Memory");

        /* Wait until GPIO module is reset. */

        while(!(__readMemory32((0x44E07000 + 0x114), "Memory") & 0x01));

        __writeMemory32((__readMemory32((0x44E07000 + 0x134), "Memory") & ~(1 << 7)), (0x44E07000 + 0x134), "Memory");

        __writeMemory32((1 << 7), (0x44E07000 + 0x194), "Memory");

        __writeMemory32((__readMemory32((0x44E10000 + 0x0E0C), "Memory") & 0xFFFFFFFE), (0x44E10000 + 0x0E0C), "Memory");

        __writeMemory32((__readMemory32((0x44E10000 + 0x0E0C), "Memory") | 0x00000001), (0x44E10000 + 0x0E0C), "Memory");

	vtp_enable(); 

        phy_config_cmd();

        phy_config_data();	

        __writeMemory32(0x18B, (0x1404 + 0x44E10000), "Memory");
        __writeMemory32(0x18B, (0x1408 + 0x44E10000), "Memory");
        __writeMemory32(0x18B, (0x140C + 0x44E10000), "Memory");
        __writeMemory32(0x18B, (0x1440 + 0x44E10000), "Memory");
        __writeMemory32(0x18B, (0x1444 + 0x44E10000), "Memory");

        __writeMemory32((__readMemory32((0x0E04 + 0x44E10000), "Memory") & ~0x10000000), (0x0E04 + 0x44E10000), "Memory");

        __writeMemory32((__readMemory32((0x131C + 0x44E10000), "Memory") | 0x00000001), (0x131C + 0x44E10000), "Memory");

        __message "EMIF Timing register configuration is in progress ....... \n";

        __writeMemory32(0x06, (0x0E4 + 0x4C000000), "Memory");
        __writeMemory32(0x06, (0x0E8 + 0x4C000000), "Memory");
        __writeMemory32(0x06, (0x0EC + 0x4C000000), "Memory");

        __writeMemory32(0x0888A39B, (0x018 + 0x4C000000), "Memory");
        __writeMemory32(0x0888A39B, (0x01C + 0x4C000000), "Memory");

        __writeMemory32(0x26337FDA, (0x020 + 0x4C000000), "Memory");
        __writeMemory32(0x26337FDA, (0x024 + 0x4C000000), "Memory");

        __writeMemory32(0x501F830F, (0x028 + 0x4C000000), "Memory");
        __writeMemory32(0x501F830F, (0x02C + 0x4C000000), "Memory");

        __writeMemory32(0x0000093B, (0x010 + 0x4C000000), "Memory");
        __writeMemory32(0x0000093B, (0x014 + 0x4C000000), "Memory");

        __writeMemory32(0x50074BE4, (0x0C8 + 0x4C000000), "Memory");

        __writeMemory32(0x61C04AB2, (0x008 + 0x4C000000), "Memory");

        __message "EMIF Timing register configuration is done ....... \n";

        if((__readMemory32((0x4C000000 + 0x004), "Memory") & 0x4) == 0x4)
        {
            __message "PHY is READY!!\n";
        }

        __message "DDR PHY Configuration done \n";

        __message "****  AM335x OPP120 DDR3 EMIF and PHY configuration is done......... \n";
}

am335x_evm_initialization()
{
__var psc_base;
__var reg;
__var module_offest;

  __message " AM335x EVM-SK Initialization is in progress .......... \n";
  arm_opp120_config();
  ddr3_emif_config();
  __message " AM335x EVM-SK Initialization is done .......... \n";
}

execUserPreload()
{
	am335x_evm_initialization();
}