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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023/03/15 flyingcys first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
static void system_clock_init(void)
{
#if 1
/* wifipll/audiopll */
GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | GLB_PLL_AUPLL);
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M);
#else
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL);
GLB_Config_AUDIO_PLL_To_384M();
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1);
GLB_Set_MCU_System_CLK_Div(0, 3);
#endif
CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1);
}
static void peripheral_clock_init(void)
{
PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
PERIPHERAL_CLOCK_SEC_ENABLE();
PERIPHERAL_CLOCK_DMA0_ENABLE();
PERIPHERAL_CLOCK_UART0_ENABLE();
PERIPHERAL_CLOCK_UART1_ENABLE();
PERIPHERAL_CLOCK_SPI0_ENABLE();
PERIPHERAL_CLOCK_I2C0_ENABLE();
PERIPHERAL_CLOCK_PWM0_ENABLE();
PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
PERIPHERAL_CLOCK_IR_ENABLE();
PERIPHERAL_CLOCK_I2S_ENABLE();
PERIPHERAL_CLOCK_USB_ENABLE();
PERIPHERAL_CLOCK_CAN_ENABLE();
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
GLB_Set_USB_CLK_From_WIFIPLL(1);
GLB_Swap_MCU_SPI_0_MOSI_With_MISO(0);
}
#ifdef BSP_USING_PSRAM
static void bflb_init_psram_gpio(void)
{
struct bflb_device_s *gpio;
gpio = bflb_device_get_by_name("gpio");
for (uint8_t i = 0; i < 12; i++) {
bflb_gpio_init(gpio, (41 + i), GPIO_INPUT | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_0);
}
}
static void psram_winbond_default_init(void)
{
PSRAM_Ctrl_Cfg_Type default_psram_ctrl_cfg = {
.vendor = PSRAM_CTRL_VENDOR_WINBOND,
.ioMode = PSRAM_CTRL_X8_MODE,
.size = PSRAM_SIZE_4MB,
.dqs_delay = 0xfff0,
};
PSRAM_Winbond_Cfg_Type default_winbond_cfg = {
.rst = DISABLE,
.clockType = PSRAM_CLOCK_DIFF,
.inputPowerDownMode = DISABLE,
.hybridSleepMode = DISABLE,
.linear_dis = ENABLE,
.PASR = PSRAM_PARTIAL_REFRESH_FULL,
.disDeepPowerDownMode = ENABLE,
.fixedLatency = DISABLE,
.brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES,
.brustType = PSRAM_WRAPPED_BURST,
.latency = PSRAM_WINBOND_6_CLOCKS_LATENCY,
.driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M,
};
PSram_Ctrl_Init(PSRAM0_ID, &default_psram_ctrl_cfg);
// PSram_Ctrl_Winbond_Reset(PSRAM0_ID);
PSram_Ctrl_Winbond_Write_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_CR0, &default_winbond_cfg);
}
static uint32_t board_psram_x8_init(void)
{
uint16_t reg_read = 0;
GLB_Set_PSRAMB_CLK_Sel(ENABLE, GLB_PSRAMB_EMI_WIFIPLL_320M, 0);
bflb_init_psram_gpio();
/* psram init*/
psram_winbond_default_init();
/* check psram work or not */
PSram_Ctrl_Winbond_Read_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_ID0, ®_read);
return reg_read;
}
#endif
/* This is the timer interrupt service routine. */
static void systick_isr(void)
{
rt_tick_increase();
}
void rt_hw_board_init(void)
{
#if defined (BSP_USING_BL61X_MODULE_DEFAULT)
bflb_flash_init();
#elif defined (BSP_USING_BL61X_MODULE_M0P)
#endif
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
#ifdef RT_USING_HEAP
/* initialize memory system */
rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x size: %d\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END, RT_HW_HEAP_END - RT_HW_HEAP_BEGIN);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
/* UART driver initialization is open by default */
#ifdef RT_USING_SERIAL
rt_hw_uart_init();
#endif
#ifdef BSP_USING_PSRAM
board_psram_x8_init();
Tzc_Sec_PSRAMB_Access_Release();
#endif
/* Set the shell console output device */
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
void rt_hw_cpu_reset(void)
{
GLB_SW_POR_Reset();
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
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