summaryrefslogtreecommitdiff
path: root/bsp/n32/libraries/n32_drivers/drv_adc.c
blob: 92a00d8dea48e318dc7e6e3591b00f7d9d65dd0c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
/*
 * Copyright (c) 2006-2022, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2022-10-19     Nations      first version
 */
#include "drv_adc.h"

#ifdef RT_USING_ADC

#if defined(BSP_USING_ADC)  || defined(BSP_USING_ADC1) || \
    defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || \
        defined(BSP_USING_ADC4)

static struct n32_adc_config adc_config[] =
{
#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
#ifdef BSP_USING_ADC
    {
            "adc",
            ADC,
    },
#endif
#endif

#ifdef BSP_USING_ADC1
    {
            "adc1",
            ADC1,
    },
#endif

#ifdef BSP_USING_ADC2
    {
            "adc2",
            ADC2,
    },
#endif

#ifdef BSP_USING_ADC3
    {
            "adc3",
            ADC3,
    },
#endif

#ifdef BSP_USING_ADC4
    {
            "adc4",
            ADC4,
    },
#endif
};

static struct n32_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])] = {0};

static void n32_adc_init(struct n32_adc_config *config)
{
    ADC_InitType ADC_InitStructure;

    ADC_DeInit((ADC_Module*)config->adc_periph);

    /* ADC configuration */
#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
    ADC_InitStructure.WorkMode       = ADC_WORKMODE_INDEPENDENT;
#endif

    ADC_InitStructure.MultiChEn      = DISABLE;
    ADC_InitStructure.ContinueConvEn = DISABLE;
    ADC_InitStructure.ExtTrigSelect  = ADC_EXT_TRIGCONV_NONE;
    ADC_InitStructure.DatAlign       = ADC_DAT_ALIGN_R;
    ADC_InitStructure.ChsNumber      = 1;
    ADC_Init((ADC_Module*)config->adc_periph, &ADC_InitStructure);

    /* Enable ADC */
    ADC_Enable((ADC_Module*)config->adc_periph, ENABLE);

    /* Check ADC Ready */
    while (ADC_GetFlagStatusNew((ADC_Module*)config->adc_periph, ADC_FLAG_RDY) == RESET);

    /* Start ADC calibration */
    ADC_StartCalibration((ADC_Module*)config->adc_periph);

    /* Check the end of ADC calibration */
    while (ADC_GetCalibrationStatus((ADC_Module*)config->adc_periph));
}

static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
    if (channel > ADC_CH_18)
    {
        return -RT_EINVAL;
    }
    return RT_EOK;
}

static rt_err_t n32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
    struct n32_adc_config *config;
    RT_ASSERT(device != RT_NULL);

    if (channel > ADC_CH_18)
    {
        return -RT_EINVAL;
    }
    config = (struct n32_adc_config *)(device->parent.user_data);

    ADC_ConfigRegularChannel((ADC_Module*)config->adc_periph, channel, 1, ADC_SAMP_TIME_239CYCLES5);

    /* Start ADC Software Conversion */
    ADC_EnableSoftwareStartConv((ADC_Module*)config->adc_periph, ENABLE);

    while (ADC_GetFlagStatus((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC)==0)
    {
    }

    ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC);
    ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_STR);
    *value = ADC_GetDat((ADC_Module*)config->adc_periph);

    return RT_EOK;
}

static struct rt_adc_ops n32_adc_ops =
{
    .enabled = n32_adc_enabled,
    .convert = n32_adc_convert,
};

int rt_hw_adc_init(void)
{
    GPIO_InitType GPIO_InitStructure;

    int i = 0;
    int result = RT_EOK;

#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) || defined(SOC_N32G4FR)
#ifdef BSP_USING_ADC
    RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
    RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC, ENABLE);

    GPIO_InitStruct(&GPIO_InitStructure);
    /* Configure PA.01 PA.02 as analog input */
    GPIO_InitStructure.Pin       = GPIO_PIN_1 | GPIO_PIN_2;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Analog;
    GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
#endif
#endif

#ifdef BSP_USING_ADC1
    RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
    RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE);

    GPIO_InitStruct(&GPIO_InitStructure);
    /* Configure PA.01 PA.03 as analog input */
    GPIO_InitStructure.Pin        = GPIO_PIN_1 | GPIO_PIN_3;
    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AIN;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
#endif /* BSP_USING_ADC1 */

#ifdef BSP_USING_ADC2
    RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
    RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE);

    GPIO_InitStruct(&GPIO_InitStructure);
    /* Configure PA.04 PA.05 as analog input */
    GPIO_InitStructure.Pin        = GPIO_PIN_4 | GPIO_PIN_5;
    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AIN;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
#endif /* BSP_USING_ADC2 */

#ifdef BSP_USING_ADC3
    RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
    RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC3, ENABLE);

    GPIO_InitStruct(&GPIO_InitStructure);
    /* Configure PB.11 PB.13 as analog input */
    GPIO_InitStructure.Pin        = GPIO_PIN_11 | GPIO_PIN_13;
    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AIN;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
#endif /* BSP_USING_ADC3 */

#ifdef BSP_USING_ADC4
    RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
    RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC4, ENABLE);

    GPIO_InitStruct(&GPIO_InitStructure);
    /* Configure PB.14 PB.15 as analog input */
    GPIO_InitStructure.Pin        = GPIO_PIN_14 | GPIO_PIN_15;
    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AIN;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
#endif /* BSP_USING_ADC4 */

    /* RCC_ADCHCLK_DIV16*/
    ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV16);
    /* Selsect HSE as RCC ADC1M CLK Source */
    RCC_ConfigAdc1mClk(RCC_ADC1MCLK_SRC_HSE, RCC_ADC1MCLK_DIV8);

    for (i = 0; i < sizeof(adc_obj) / sizeof(adc_obj[0]); i++)
    {
        adc_obj[i].config = &adc_config[i];
        n32_adc_init(&adc_config[i]);
        rt_hw_adc_register(&adc_obj[i].adc_device, \
                           adc_obj[i].config->name, &n32_adc_ops, adc_obj[i].config);
    }
    return result;
}
INIT_DEVICE_EXPORT(rt_hw_adc_init);

#endif  /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || defined(BSP_USING_ADC4) */
#endif /* RT_USING_ADC */