summaryrefslogtreecommitdiff
path: root/bsp/rx/RPDL/r_pdl_cgc.h
blob: e7869422978a7fc232f225ba0ad88a0bccda8e70 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
/*""FILE COMMENT""*******************************************************
* System Name	: CGC API
* File Name		: r_pdl_cgc.h
* Version		: 1.02
* Contents		: CGC header
* Customer		:
* Model			:
* Order			:
* CPU			: RX
* Compiler		: RXC
* OS			:
* Programmer	:
* Note			:
************************************************************************
* Copyright, 2011. Renesas Electronics Corporation
* and Renesas Solutions Corporation
************************************************************************
* History		: 2011.04.08
*				: Ver 1.02
*				: CS-5 release.
*""FILE COMMENT END""**************************************************/

#ifndef R_PDL_CGC_H
#define R_PDL_CGC_H

#include "r_pdl_common_defs_RX62Nxx.h"

/* Function prototypes */
bool R_CGC_Set(
	uint32_t,
	uint32_t,
	uint32_t,
	uint32_t,
	uint16_t
);

bool R_CGC_Control(
	uint16_t
);

bool R_CGC_GetStatus(
	uint8_t *
);

/* BCLK pin putput control */
#define PDL_CGC_BCLK_DISABLE		0x0001u
#define PDL_CGC_BCLK_DIV_1			0x0002u
#define PDL_CGC_BCLK_DIV_2			0x0004u
#define PDL_CGC_BCLK_HIGH			0x0008u

/* SDCLK pin putput control */
#define PDL_CGC_SDCLK_DISABLE		0x0010u
#define PDL_CGC_SDCLK_ENABLE		0x0020u

/* Oscillation Stop Detection control */
#define PDL_CGC_OSC_STOP_ENABLE		0x0040u
#define PDL_CGC_OSC_STOP_DISABLE	0x0080u

/* Sub-clock oscillator control */
#define PDL_CGC_SUB_CLOCK_ENABLE	0x0100u
#define PDL_CGC_SUB_CLOCK_DISABLE	0x0200u

#endif
/* End of file */