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|
ARM Macro Assembler Page 1
1 00000000 ;/*
2 00000000 ;* Copyright (c) 2006-2018, RT-Thread Development Team
3 00000000 ;*
4 00000000 ;* SPDX-License-Identifier: Apache-2.0
5 00000000 ;*
6 00000000 ; * Change Logs:
7 00000000 ; * Date Author Notes
8 00000000 ; * 2009-01-17 Bernard first version.
9 00000000 ; * 2012-01-01 aozima support context switch l
oad/store FPU register.
10 00000000 ; * 2013-06-18 aozima add restore MSP feature.
11 00000000 ; * 2013-06-23 aozima support lazy stack optim
ized.
12 00000000 ; * 2018-07-24 aozima enhancement hard fault e
xception handler.
13 00000000 ; */
14 00000000
15 00000000 ;/**
16 00000000 ; * @addtogroup cortex-m33
17 00000000 ; */
18 00000000 ;/*@{*/
19 00000000
20 00000000 E000ED08
SCB_VTOR
EQU 0xE000ED08 ; Vector Table Offs
et Register
21 00000000 E000ED04
NVIC_INT_CTRL
EQU 0xE000ED04 ; interrupt control
state register
22 00000000 E000ED20
NVIC_SYSPRI2
EQU 0xE000ED20 ; system priority r
egister (2)
23 00000000 FFFF0000
NVIC_PENDSV_PRI
EQU 0xFFFF0000 ; PendSV and SysTic
k priority value (l
owest)
24 00000000 10000000
NVIC_PENDSVSET
EQU 0x10000000 ; value to trigger
PendSV exception
25 00000000
26 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
27 00000000 THUMB
28 00000000 REQUIRE8
29 00000000 PRESERVE8
30 00000000
31 00000000 IMPORT rt_thread_switch_interrupt_flag
32 00000000 IMPORT rt_interrupt_from_thread
33 00000000 IMPORT rt_interrupt_to_thread
34 00000000 IMPORT rt_trustzone_current_context
35 00000000 IMPORT rt_trustzone_context_load
36 00000000 IMPORT rt_trustzone_context_store
37 00000000
38 00000000 ;/*
ARM Macro Assembler Page 2
39 00000000 ; * rt_base_t rt_hw_interrupt_disable();
40 00000000 ; */
41 00000000 rt_hw_interrupt_disable
PROC
42 00000000 EXPORT rt_hw_interrupt_disable
43 00000000 F3EF 8010 MRS r0, PRIMASK
44 00000004 B672 CPSID I
45 00000006 4770 BX LR
46 00000008 ENDP
47 00000008
48 00000008 ;/*
49 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level);
50 00000008 ; */
51 00000008 rt_hw_interrupt_enable
PROC
52 00000008 EXPORT rt_hw_interrupt_enable
53 00000008 F380 8810 MSR PRIMASK, r0
54 0000000C 4770 BX LR
55 0000000E ENDP
56 0000000E
57 0000000E ;/*
58 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32
to);
59 0000000E ; * r0 --> from
60 0000000E ; * r1 --> to
61 0000000E ; */
62 0000000E rt_hw_context_switch_interrupt
63 0000000E EXPORT rt_hw_context_switch_interrupt
64 0000000E rt_hw_context_switch
PROC
65 0000000E EXPORT rt_hw_context_switch
66 0000000E
67 0000000E ; set rt_thread_switch_interrupt_flag to 1
68 0000000E 4A5D LDR r2, =rt_thread_switch_interrupt
_flag
69 00000010 6813 LDR r3, [r2]
70 00000012 2B01 CMP r3, #1
71 00000014 D004 BEQ _reswitch
72 00000016 F04F 0301 MOV r3, #1
73 0000001A 6013 STR r3, [r2]
74 0000001C
75 0000001C 4A5A LDR r2, =rt_interrupt_from_thread ;
set rt_interrupt_f
rom_thread
76 0000001E 6010 STR r0, [r2]
77 00000020
78 00000020 _reswitch
79 00000020 4A5A LDR r2, =rt_interrupt_to_thread ; s
et rt_interrupt_to_
thread
80 00000022 6011 STR r1, [r2]
81 00000024
82 00000024 485A LDR r0, =NVIC_INT_CTRL ; trigger th
e PendSV exception
(causes context swi
tch)
83 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET
84 0000002A 6001 STR r1, [r0]
85 0000002C 4770 BX LR
ARM Macro Assembler Page 3
86 0000002E ENDP
87 0000002E
88 0000002E ; r0 --> switch from thread stack
89 0000002E ; r1 --> switch to thread stack
90 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from
] stack
91 0000002E PendSV_Handler
PROC
92 0000002E EXPORT PendSV_Handler
93 0000002E
94 0000002E ; disable interrupt to protect context switch
95 0000002E F3EF 8210 MRS r2, PRIMASK ; R2 = PRIMASK
96 00000032 B672 CPSID I ; disable all inter
rupt
97 00000034
98 00000034 ; get rt_thread_switch_interrupt_flag
99 00000034 4853 LDR r0, =rt_thread_switch_interrupt
_flag
; r0 = &rt_thread_s
witch_interrupt_fla
g
100 00000036 6801 LDR r1, [r0] ; r1 = *r1
101 00000038 2900 CMP r1, #0x00 ; compare r1 == 0x0
0
102 0000003A D102 BNE schedule
103 0000003C F382 8810 MSR PRIMASK, r2 ; if r1 == 0x00, do
msr PRIMASK, r2
104 00000040 4770 BX lr ; if r1 == 0x00, do
bx lr
105 00000042
106 00000042 schedule
107 00000042 B404 PUSH {r2} ; store interrupt s
tate
108 00000044
109 00000044 ; clear rt_thread_switch_interrupt_flag to 0
110 00000044 F04F 0100 MOV r1, #0x00 ; r1 = 0x00
111 00000048 6001 STR r1, [r0] ; *r0 = r1
112 0000004A
113 0000004A ; skip register save at the first time
114 0000004A 484F LDR r0, =rt_interrupt_from_thread ;
r0 = &rt_interrupt
_from_thread
115 0000004C 6801 LDR r1, [r0] ; r1 = *r0
116 0000004E B359 CBZ r1, switch_to_thread ; if r1 ==
0, goto switch_to_
thread
117 00000050
118 00000050 ; Whether TrustZone thread stack exists
119 00000050 4950 LDR r1, =rt_trustzone_current_cont
ext
; r1 = &rt_secure_c
urrent_context
120 00000052 6809 LDR r1, [r1] ; r1 = *r1
121 00000054 B1A1 CBZ r1, contex_ns_store ; if r1 ==
0, goto contex_ns_s
tore
122 00000056
123 00000056 ;call TrustZone fun, Save TrustZone stack
124 00000056 B503 STMFD sp!, {r0-r1, lr}
ARM Macro Assembler Page 4
; push register
125 00000058 4608 MOV r0, r1 ; r0 = rt_secure_cu
rrent_context
126 0000005A F7FF FFFE BL rt_trustzone_context_store ; ca
ll TrustZone store
fun
127 0000005E E8BD 4003 LDMFD sp!, {r0-r1, lr} ; pop register
128 00000062
129 00000062 ; check break from TrustZone
130 00000062 4672 MOV r2, lr ; r2 = lr
131 00000064 F012 0F40 TST r2, #0x40 ; if EXC_RETURN[6]
is 1, TrustZone sta
ck was used
132 00000068 D00A BEQ contex_ns_store ; if r2 & 0x40
== 0, goto contex_n
s_store
133 0000006A
134 0000006A ; push PSPLIM CONTROL PSP LR current_context to stack
135 0000006A F3EF 830B MRS r3, psplim ; r3 = psplim
136 0000006E F3EF 8414 MRS r4, control ; r4 = control
137 00000072 F3EF 8509 MRS r5, psp ; r5 = psp
138 00000076 E925 001E STMFD r5!, {r1-r4} ; push to thread s
tack
139 0000007A
140 0000007A ; update from thread stack pointer
141 0000007A 6800 LDR r0, [r0] ; r0 = rt_thread_sw
itch_interrupt_flag
142 0000007C 6005 STR r5, [r0] ; *r0 = r5
143 0000007E E013 b switch_to_thread ; goto switch_
to_thread
144 00000080
145 00000080 contex_ns_store
146 00000080
147 00000080 F3EF 8109 MRS r1, psp ; get from thread s
tack pointer
148 00000084
149 00000084 IF {FPU} != "SoftVFP"
150 00000084 F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4]
)
151 00000088 BF08 ED21
8B10 VSTMFDEQ r1!, {d8 - d15} ; push FPU regi
ster s16~s31
152 0000008E ENDIF
153 0000008E
154 0000008E E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11
register
155 00000092
156 00000092 4A40 LDR r2, =rt_trustzone_current_cont
ext
; r2 = &rt_secure_c
urrent_context
157 00000094 6812 LDR r2, [r2] ; r2 = *r2
158 00000096 4673 MOV r3, lr ; r3 = lr
159 00000098 F3EF 840B MRS r4, psplim ; r4 = psplim
160 0000009C F3EF 8514 MRS r5, control ; r5 = control
161 000000A0 E921 003C STMFD r1!, {r2-r5} ; push to thread s
tack
ARM Macro Assembler Page 5
162 000000A4
163 000000A4 6800 LDR r0, [r0]
164 000000A6 6001 STR r1, [r0] ; update from threa
d stack pointer
165 000000A8
166 000000A8 switch_to_thread
167 000000A8 4938 LDR r1, =rt_interrupt_to_thread
168 000000AA 6809 LDR r1, [r1]
169 000000AC 6809 LDR r1, [r1] ; load thread stack
pointer
170 000000AE
171 000000AE ; update current TrustZone context
172 000000AE C93C LDMFD r1!, {r2-r5} ; pop thread stack
173 000000B0 F384 880B MSR psplim, r4 ; psplim = r4
174 000000B4 F385 8814 MSR control, r5 ; control = r5
175 000000B8 469E MOV lr, r3 ; lr = r3
176 000000BA 4E36 LDR r6, =rt_trustzone_current_cont
ext
; r6 = &rt_secure_c
urrent_context
177 000000BC 6032 STR r2, [r6] ; *r6 = r2
178 000000BE 4610 MOV r0, r2 ; r0 = r2
179 000000C0
180 000000C0 ; Whether TrustZone thread stack exists
181 000000C0 B140 CBZ r0, contex_ns_load ; if r0 == 0
, goto contex_ns_lo
ad
182 000000C2 B40A PUSH {r1, r3} ; push lr, thread_s
tack
183 000000C4 F7FF FFFE BL rt_trustzone_context_load ; cal
l TrustZone load fu
n
184 000000C8 BC0A POP {r1, r3} ; pop lr, thread_st
ack
185 000000CA 469E MOV lr, r3 ; lr = r1
186 000000CC F013 0F40 TST r3, #0x40 ; if EXC_RETURN[6]
is 1, TrustZone sta
ck was used
187 000000D0 D000 BEQ contex_ns_load ; if r1 & 0x40 =
= 0, goto contex_ns
_load
188 000000D2 E006 B pendsv_exit
189 000000D4
190 000000D4 contex_ns_load
191 000000D4 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11
register
192 000000D8
193 000000D8 IF {FPU} != "SoftVFP"
194 000000D8 F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4]
)
195 000000DC BF08 ECB1
8B10 VLDMFDEQ r1!, {d8 - d15} ; pop FPU regis
ter s16~s31
196 000000E2 ENDIF
197 000000E2
198 000000E2 pendsv_exit
199 000000E2 F381 8809 MSR psp, r1 ; update stack poin
ter
ARM Macro Assembler Page 6
200 000000E6 ; restore interrupt
201 000000E6 BC04 POP {r2}
202 000000E8 F382 8810 MSR PRIMASK, r2
203 000000EC
204 000000EC 4770 BX lr
205 000000EE ENDP
206 000000EE
207 000000EE ;/*
208 000000EE ; * void rt_hw_context_switch_to(rt_uint32 to);
209 000000EE ; * r0 --> to
210 000000EE ; * this fucntion is used to perform the first thread sw
itch
211 000000EE ; */
212 000000EE rt_hw_context_switch_to
PROC
213 000000EE EXPORT rt_hw_context_switch_to
214 000000EE ; set to thread
215 000000EE 4927 LDR r1, =rt_interrupt_to_thread
216 000000F0 6008 STR r0, [r1]
217 000000F2
218 000000F2 IF {FPU} != "SoftVFP"
219 000000F2 ; CLEAR CONTROL.FPCA
220 000000F2 F3EF 8214 MRS r2, CONTROL ; read
221 000000F6 F022 0204 BIC r2, #0x04 ; modify
222 000000FA F382 8814 MSR CONTROL, r2 ; write-back
223 000000FE ENDIF
224 000000FE
225 000000FE ; set from thread to 0
226 000000FE 4922 LDR r1, =rt_interrupt_from_thread
227 00000100 F04F 0000 MOV r0, #0x0
228 00000104 6008 STR r0, [r1]
229 00000106
230 00000106 ; set interrupt flag to 1
231 00000106 491F LDR r1, =rt_thread_switch_interrupt
_flag
232 00000108 F04F 0001 MOV r0, #1
233 0000010C 6008 STR r0, [r1]
234 0000010E
235 0000010E ; set the PendSV and SysTick exception priority
236 0000010E 4822 LDR r0, =NVIC_SYSPRI2
237 00000110 4922 LDR r1, =NVIC_PENDSV_PRI
238 00000112 F8D0 2000 LDR.W r2, [r0,#0x00] ; read
239 00000116 EA41 0102 ORR r1,r1,r2 ; modify
240 0000011A 6001 STR r1, [r0] ; write-back
241 0000011C
242 0000011C ; trigger the PendSV exception (causes context switch)
243 0000011C 481C LDR r0, =NVIC_INT_CTRL
244 0000011E F04F 5180 LDR r1, =NVIC_PENDSVSET
245 00000122 6001 STR r1, [r0]
246 00000124
247 00000124 ; restore MSP
248 00000124 481E LDR r0, =SCB_VTOR
249 00000126 6800 LDR r0, [r0]
250 00000128 6800 LDR r0, [r0]
251 0000012A F380 8808 MSR msp, r0
252 0000012E
253 0000012E ; enable interrupts at processor level
254 0000012E B661 CPSIE F
255 00000130 B662 CPSIE I
ARM Macro Assembler Page 7
256 00000132
257 00000132 ; ensure PendSV exception taken place before subsequent
operation
258 00000132 F3BF 8F4F DSB
259 00000136 F3BF 8F6F ISB
260 0000013A
261 0000013A ; never reach here!
262 0000013A ENDP
263 0000013A
264 0000013A ; compatible with old version
265 0000013A rt_hw_interrupt_thread_switch
PROC
266 0000013A EXPORT rt_hw_interrupt_thread_switch
267 0000013A 4770 BX lr
268 0000013C ENDP
269 0000013C
270 0000013C IMPORT rt_hw_hard_fault_exception
271 0000013C EXPORT HardFault_Handler
272 0000013C HardFault_Handler
PROC
273 0000013C
274 0000013C ; get current context
275 0000013C F3EF 8008 MRS r0, msp ;get fault context
from handler
276 00000140 F01E 0F04 TST lr, #0x04 ;if(!EXC_RETURN[2])
277 00000144 D001 BEQ get_sp_done
278 00000146 F3EF 8009 MRS r0, psp ;get fault context
from thread
279 0000014A get_sp_done
280 0000014A
281 0000014A E920 0FF0 STMFD r0!, {r4 - r11} ; push r4 - r11
register
282 0000014E
283 0000014E 4A11 LDR r2, =rt_trustzone_current_cont
ext
; r2 = &rt_secure_c
urrent_context
284 00000150 6812 LDR r2, [r2] ; r2 = *r2
285 00000152 4673 MOV r3, lr ; r3 = lr
286 00000154 F3EF 840B MRS r4, psplim ; r4 = psplim
287 00000158 F3EF 8514 MRS r5, control ; r5 = control
288 0000015C E920 003C STMFD r0!, {r2-r5} ; push to thread s
tack
289 00000160
290 00000160 F840 ED04 STMFD r0!, {lr} ; push exec_return
register
291 00000164
292 00000164 F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2]
)
293 00000168 D002 BEQ update_msp
294 0000016A F380 8809 MSR psp, r0 ; update stack poin
ter to PSP
295 0000016E E001 B update_done
296 00000170 update_msp
297 00000170 F380 8808 MSR msp, r0 ; update stack poin
ter to MSP
298 00000174 update_done
299 00000174
ARM Macro Assembler Page 8
300 00000174 B500 PUSH {lr}
301 00000176 F7FF FFFE BL rt_hw_hard_fault_exception
302 0000017A F85D EB04 POP {lr}
303 0000017E
304 0000017E F04E 0E04 ORR lr, lr, #0x04
305 00000182 4770 BX lr
306 00000184 ENDP
307 00000184
308 00000184 ALIGN 4
309 00000184
310 00000184 END
00000000
00000000
00000000
E000ED04
00000000
E000ED20
FFFF0000
E000ED08
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M33 --fpu=FPv5-S
P --depend=.\build\keil\obj\context_rvds.d -o.\build\keil\obj\context_rvds.o -I
D:\1_tool_prog\2_MDK\pack\Keil\STM32H5xx_DFP\1.1.0\Drivers\CMSIS\Device\ST\STM3
2H5xx\Include --predefine="__UVISION_VERSION SETA 536" --predefine="STM32H563xx
SETA 1" --list=context_rvds.lst ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 26 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
None
Comment: .text unused
HardFault_Handler 0000013C
Symbol: HardFault_Handler
Definitions
At line 272 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 271 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: HardFault_Handler used once
PendSV_Handler 0000002E
Symbol: PendSV_Handler
Definitions
At line 91 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 92 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: PendSV_Handler used once
_reswitch 00000020
Symbol: _reswitch
Definitions
At line 78 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 71 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: _reswitch used once
contex_ns_load 000000D4
Symbol: contex_ns_load
Definitions
At line 190 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 181 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 187 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
contex_ns_store 00000080
Symbol: contex_ns_store
Definitions
At line 145 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 121 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 132 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
get_sp_done 0000014A
Symbol: get_sp_done
Definitions
At line 279 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 277 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: get_sp_done used once
pendsv_exit 000000E2
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
Symbol: pendsv_exit
Definitions
At line 198 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 188 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: pendsv_exit used once
rt_hw_context_switch 0000000E
Symbol: rt_hw_context_switch
Definitions
At line 64 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 65 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_hw_context_switch used once
rt_hw_context_switch_interrupt 0000000E
Symbol: rt_hw_context_switch_interrupt
Definitions
At line 62 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 63 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_hw_context_switch_interrupt used once
rt_hw_context_switch_to 000000EE
Symbol: rt_hw_context_switch_to
Definitions
At line 212 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 213 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_hw_context_switch_to used once
rt_hw_interrupt_disable 00000000
Symbol: rt_hw_interrupt_disable
Definitions
At line 41 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 42 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_hw_interrupt_disable used once
rt_hw_interrupt_enable 00000008
Symbol: rt_hw_interrupt_enable
Definitions
At line 51 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 52 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_hw_interrupt_enable used once
rt_hw_interrupt_thread_switch 0000013A
Symbol: rt_hw_interrupt_thread_switch
Definitions
At line 265 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 266 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_hw_interrupt_thread_switch used once
schedule 00000042
Symbol: schedule
Definitions
ARM Macro Assembler Page 3 Alphabetic symbol ordering
Relocatable symbols
At line 106 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 102 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: schedule used once
switch_to_thread 000000A8
Symbol: switch_to_thread
Definitions
At line 166 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 116 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 143 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
update_done 00000174
Symbol: update_done
Definitions
At line 298 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 295 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: update_done used once
update_msp 00000170
Symbol: update_msp
Definitions
At line 296 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 293 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: update_msp used once
18 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
NVIC_INT_CTRL E000ED04
Symbol: NVIC_INT_CTRL
Definitions
At line 21 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 82 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 243 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
NVIC_PENDSVSET 10000000
Symbol: NVIC_PENDSVSET
Definitions
At line 24 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 83 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 244 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
NVIC_PENDSV_PRI FFFF0000
Symbol: NVIC_PENDSV_PRI
Definitions
At line 23 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 237 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: NVIC_PENDSV_PRI used once
NVIC_SYSPRI2 E000ED20
Symbol: NVIC_SYSPRI2
Definitions
At line 22 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 236 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: NVIC_SYSPRI2 used once
SCB_VTOR E000ED08
Symbol: SCB_VTOR
Definitions
At line 20 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 248 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: SCB_VTOR used once
5 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
rt_hw_hard_fault_exception 00000000
Symbol: rt_hw_hard_fault_exception
Definitions
At line 270 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 301 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_hw_hard_fault_exception used once
rt_interrupt_from_thread 00000000
Symbol: rt_interrupt_from_thread
Definitions
At line 32 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 75 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 114 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 226 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
rt_interrupt_to_thread 00000000
Symbol: rt_interrupt_to_thread
Definitions
At line 33 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 79 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 167 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 215 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
rt_thread_switch_interrupt_flag 00000000
Symbol: rt_thread_switch_interrupt_flag
Definitions
At line 31 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 68 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 99 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 231 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
rt_trustzone_context_load 00000000
Symbol: rt_trustzone_context_load
Definitions
At line 35 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 183 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_trustzone_context_load used once
rt_trustzone_context_store 00000000
Symbol: rt_trustzone_context_store
Definitions
At line 36 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Uses
At line 126 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
Comment: rt_trustzone_context_store used once
rt_trustzone_current_context 00000000
Symbol: rt_trustzone_current_context
Definitions
At line 34 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
ARM Macro Assembler Page 2 Alphabetic symbol ordering
External symbols
Uses
At line 119 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 156 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 176 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
At line 283 in file ..\..\..\libcpu\arm\cortex-m33\context_rvds.S
7 symbols
365 symbols in table
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