threadx.git, branch dev

Fixed the FreeRTOS layer build with GCC 14 by matching the name type (#815)

2026-10-22T14:22:42Z

pcTaskGetName() held the name tx_thread_info_get() returns in a const char *, but the service takes TX_NAME_CONST CHAR **, which is CHAR ** unless TX_ENABLE_CONST_NAMES is set. GCC 13 reports the mismatch as a warning; GCC 14 makes incompatible pointer types an error, so the FreeRTOS compatibility layer did not compile with it. The local now uses TX_NAME_CONST CHAR *, so it follows the service's declaration in both configurations. The returned pointer is unchanged. FreeRTOS regression 3/3 with GCC 14.2 and with GCC 13.3, zero warnings with each (one warning on dev with GCC 13), and 3/3 with zero warnings under GCC 14 with TX_ENABLE_CONST_NAMES. Assisted-by: Claude Code (Opus 5.5)

Added the R52 module and S32Z280 examples to the FVP workflow (#804)

2026-10-13T16:06:42Z

The FVP module manager example and the S32Z280 kernel and module examples are each behind a CMake option that defaults to OFF, and no CI lane turned any of them on. The module isolation tests were therefore never linked, and nothing built the S32Z280 images. Both r52_fvp configurations now enable all four example options. The FVP module images join the CTest suite whenever the model is available; the S32Z280 images are built and never run, since CTest registers only FVP images. The header no longer describes these examples as pending. On the Armv8-R AEM FVP 11.32 with GCC 14.3, the default configuration builds 14 images and passes 8/8, and the feature configuration builds 20 and passes 11/11, with zero warnings. CI still builds without executing until FVP_AEMV8R_URL is set. Assisted-by: Claude Code (Opus 5.5)

Enabled FVP execution in the Cortex-R52 workflow (#806)

2026-10-13T15:14:35Z

Fixes #805 r52_fvp only ran the FVP when a repository variable pointed it at the model, and none was set, so every run built the images and executed nothing. The workflow also expected an unpacked model, but Arm ships the FVP as an installer script. The workflow now downloads the 11.32_19 archive from Arm's public permalink, checks it against a pinned SHA-256, and runs Arm's installer with its EULA accepted. The cache is keyed on the checksum. A missing model now fails the job instead of skipping execution. CONTRIBUTING.md no longer describes the repository variable. The workflow's install, locate, and build-and-run steps, run locally as written, download and verify the archive, install 11.32+19, and pass 6/6 default and 9/9 feature on the FVP. The installed binary is identical to the one used for local validation of the port. Assisted-by: Claude Code (Opus 5.5)

Removed internal milestone labels from the Cortex-R52 port (#803)

2026-10-13T15:13:12Z

Comments, CMake messages and demo banners in the Cortex-R52 port and its module example referred to development milestones by internal labels. The labels mean nothing to a reader of the port, and three FVP demo images were named after them. Replaced each label with a description of what the code or image does, and renamed demo_m2, demo_m3 and demo_m5 to demo_coop, demo_tick and demo_vfp, with their run targets to match. The banners the demos print change accordingly; the FVP test runner matches only result lines, so no test depends on them. Default, feature and module configurations pass 6/6, 9/9 and 8/8 on the Armv8-R AEM FVP, as on dev, with zero warnings; the S32Z280 images build cleanly. Not run on S32Z280 hardware. Assisted-by: Claude Code (Opus 5.5)

Aligned the banner comments in the Cortex-R52 ports (#785)

2026-10-13T13:07:32Z

The header and function banner comments in the Cortex-R52 port and its module port do not close on the right border. 990 of 4,228 banner lines sat one to three columns off, and in the module port that was 42 per cent of them. Measured against the ports the convention came from, Cortex-A7 and Cortex-M33 are at zero and Cortex-R5 at 2 per cent, so this is the R52 tree rather than the house style. Lines whose text already fitted are re-padded. Where the text itself ran past the border the trailing words move down to the next line, which pushes the paragraph along until every line fits, so no wording is shortened and no sentence is recut by hand. The bar widths were already correct in every file and are untouched. One line is left over and is a real exception: _txm_module_manager_thread_stack_build is long enough that its name and the release column cannot share a line at this width. Verified: the banner text is word-for-word identical before and after in all 45 files, the port builds at 203 targets with zero warnings, and all eleven changed assembly files assemble. Assisted-by: Claude Code (Opus 5)

Updated artifact and Pages actions to current patch releases

2026-10-13T12:50:05Z

The artifact and Pages workflows pin actions behind their current patch releases. Updated upload-artifact to v7.0.2, download-artifact to v8.0.2 and deploy-pages to v5.0.1, retaining immutable SHA pins. Component sources are unchanged. The ThreadX, SMP, FreeRTOS and RISC-V regression jobs and repository checks passed. Pages deployment was not exercised by the pull request. Assisted-by: Copilot (gpt-6.1-sol) <223556219+Copilot@users.noreply.github.com>

Removed the Cortex-M asides from the Cortex-R52 module port (#784)

2026-10-13T12:43:05Z

Four comments in the Cortex-R52 module port explained what the Cortex-M ports do instead. A reader working on this port cannot act on any of it: the behaviour described belongs to a different architecture, and the surrounding comments already say what this port does and why. The remaining text is unchanged. The abort vector still explains the three things it owes the fault handler and what omitting the first costs, the fault handler still explains why its two statements are ordered as they are, and the preamble still says that every GNU module port writes the entry-point words the same way. Comment-only. The port builds clean, 203 targets, zero warnings. Assisted-by: Claude Code (Opus 5)

Fixed MISRA stack alignment on ports with 64-bit pointers (#799)

2026-10-13T12:41:16Z

Fixes #744 MISRA stack checking converted the stack address through 32-bit ULONG. Preserved ALIGN_TYPE width in both stack-alignment conversions. Added a native-width behavioral regression that fails on the original code. The regression fails on the original code and passes with the fix. tx, smp, riscv and freertos suites are green in CI, along with the Cortex-M/A/R52, gnu and atfe builds. Assisted-by: Codex (gpt-6.1-sol)

Merge pull request #797 from fdesbiens/fix/ctest-timeout-headroom

2026-10-06T09:24:54Z

Gave the per-test ctest timeout headroom over the slowest test

Merge pull request #796 from fdesbiens/fix/deploy-gate-on-needs-result

2026-10-06T07:44:15Z

Stopped the coverage deploy running after a cancelled test job