threadx.git, branch dev

Merge remote-tracking branch 'origin/master' into dev

2026-07-22T17:36:18Z

Updated SECURITY.md (#566)

2026-06-30T21:31:42Z

Updated Cortex-R4 Thumb bit immediates (#565)

2026-06-29T20:22:52Z

Use explicit immediate syntax when testing the Thumb bit in AC6 Cortex-R4 stack build assembly. Co-authored-by: Codex

Updated Cortex-M BASEPRI zero immediates (#564)

2026-06-29T20:07:12Z

Use explicit immediate syntax when clearing BASEPRI in GNU and AC6 Cortex-M scheduler assembly. Co-authored-by: Codex

Add SysTick counter reset in Cortex-M ports (#561)

2026-06-24T16:16:51Z

* Add SysTick counter reset in Cortex-M ports The SysTick counter value (SYST_CVR @0xE000E018) is indeterminate after reset. Without clearing it prior to enabling the counter, the first tick interval becomes unpredictable. * Fixed missing comment and added generated-by header in Cortex-M0/AC6 port Added the missing inline comment on the LDR r1, =0 instruction (Build value for SysTick reset) and the required AI-generated attribution comment under the copyright header. --------- Co-authored-by: Frédéric Desbiens Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Fixed ARMv8 SMP time sources (#555)

2026-06-22T12:27:10Z

Follow up on the issue-541 execution profiling work. PR #553 fixed SMP execution profile total-time aggregation, and PR #554 fixed Armv7/R SMP timestamp hooks that used decrementing private timers. This change addresses the remaining related gap in ARMv8-A SMP ports: their timestamp hooks returned zero, which left execution profiling and trace timestamps without a progressing time source. Replace those stubs with the architectural generic physical counter, CNTPCT_EL0, across the ARMv8-A SMP GNU, AC6, IAR, and GHS variants. The local ARMv8 AArch64 system timer example already uses CNTPCT_EL0 for physical count reads, so this keeps the SMP timestamp hook aligned with the existing port examples while preserving the 32-bit ULONG return contract. Co-authored-by: Codex

Fixed private-timer timestamp issue in several ports (A5, A7, A9, R8) (#554)

2026-06-22T12:07:16Z

* Fixed Cortex-A9 SMP time source Updated Cortex-A9 SMP timestamp reads to use the global timer low counter instead of the decrementing private timer counter. Applied the change to GNU and AC5 ports. * Fixed remaining Arm SMP time sources Updated Cortex-A5, Cortex-A7, and Cortex-R8 SMP timestamp hooks so execution profiling uses incrementing time sources instead of the decrementing private timer count register. Cortex-A5 and Cortex-R8 now read the global timer count low register, matching the Cortex-A9 fix. Cortex-A7 now reads the generic timer physical count register. --------- Co-authored-by: Codex

Fixed SMP execution profile total getters (#553)

2026-06-22T12:03:46Z

Updated the SMP execution profile aggregate getters to copy each core's total into the matching output array element. Added a focused regression test for thread, ISR, and idle total getters. Co-authored-by: Codex

Fix nested comment warning in RX GCC ports (#550)

2026-06-16T14:26:26Z

The RX GCC assembly port contains an unclosed C-style comment in tx_thread_context_save.S. Because .S files are passed through the C preprocessor before assembly, the nested comment can trigger GCC warnings. Close the affected comment block without changing assembly instructions or runtime behavior. Signed-off-by: FranCDoc

Merge pull request #548 from eclipse-threadx/dev

2026-06-08T15:08:34Z

Merge changes for the v6.5.1.202602a release