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<title>threadx.git/cmake/riscv32-unknown-elf.cmake, branch dev</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/threadx.git/atom/cmake/riscv32-unknown-elf.cmake?h=dev</id>
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<updated>2026-05-13T11:46:54Z</updated>
<entry>
<title>Added a riscv32 for the OpenHW CVA6 (#511)</title>
<updated>2026-05-13T11:46:54Z</updated>
<author>
<name>Francisco Manuel Merino Torres</name>
<email>francisco.merino@quintauris.com</email>
</author>
<published>2026-05-13T11:46:54Z</published>
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<id>urn:sha1:42adda44573b7c0062138818749437e6baf1044f</id>
<content type='text'>
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</entry>
<entry>
<title>Add RISC-V32 arch. port layer</title>
<updated>2026-02-16T12:15:13Z</updated>
<author>
<name>Akif Ejaz</name>
<email>akifejaz40@gmail.com</email>
</author>
<published>2026-02-16T12:15:13Z</published>
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<id>urn:sha1:757db54d6d10edc655eee9cfe02ecd4d93be5fed</id>
<content type='text'>
This update adapts the ThreadX low-level kernel routines
for RV32, including:
  - startup and initialization logic
  - context save/restore implementations
  - interrupt control and scheduler entry
  - thread stack build and system return paths
  - timer interrupt handling
  - made it complient as per new risc-v64/gnu
      &amp; threadx style
  - added reademe for risc-v32/gnu port

These changes provide full low-level support needed to run
ThreadX on RISC-V32 targets.

Signed-off-by: Akif Ejaz &lt;akif.ejaz@10xengineers.ai&gt;
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