threadx.git/ports/cortex_m0/ac6/src, branch master

Completed the Cortex-M0 barriers and made its example build with both toolchains (#595)

2026-08-10T21:34:13Z

Two unrelated Cortex-M0 gaps, both left over from earlier work. The memory barriers from #523 reached the Cortex-M0 gnu port but not its ac6 or iar siblings, in either the inline system return in tx_port.h or the assembly routine. Both take the same GNU or IAR code path, and iar already carried the entry barrier, so the missing pieces were the entry pair for ac6 and the barrier after restoring the interrupt posture for both. All three tools now match. The Cortex-M0 example could not link with any toolchain. cortexm0_crt0.S references 23 linker script symbols and the script defined only 12 of them, so __text_start__, __text_end__, __text_load_start__, the rodata and fast section symbols, and the ctors and dtors load addresses were all unresolved. The Cortex-M4 script defines all 23, including a .fast section with no content whose symbols exist so that the startup copy is a no-op, and its comment says as much. The Cortex-M0 script is brought to that same shape. That left the example failing under LLVM only, on instructions that ARMv6-M can encode just one way. The file declared .code 16 but no syntax mode, so GNU as used the legacy divided syntax in which a plain add or sub sets the flags implicitly, while LLVM implements unified syntax only and rejected the non-flag-setting spelling. Declaring .syntax unified and writing movs, adds and subs makes both assemblers agree, and the encodings GNU produces are byte identical before and after, verified by disassembling both objects. The Cortex-M0 example now links with GNU at 22,520 bytes of text and with Arm Toolchain for Embedded at 22,866, so it comes off the list of examples not expected to link and scripts/check_clang.sh now links eight of eight. Assisted-by: Claude Code (Opus 5)

Updated copyright headers and version number constants (#509)

2026-03-05T09:46:30Z

* Updated version number constants * Removed revision history from all files * Added Eclipse ThreadX contributors' copyright header

Update the copyright for all assembly files.

2024-02-23T01:39:05Z

Update version id string.

2024-01-30T00:39:18Z

Update on 31 Mar 2023. Expand to see details.

2023-03-31T07:34:47Z

af5702cbf Include tx_user.h only when TX_INCLUDE_USER_DEFINE_FILE is defined for assembly files

Release 6.2.1 on 08 Mar 2023. Expand to see details.

2023-03-08T08:26:22Z

cee19603d Include tx_user.h conditionally. e40e08007 Update owners d69641273 Update release date and version 394aee52f Add tx_user.h to GNU port assembly files 5cca2ddd0 RISC-V 64 bit port for Microchip e0f2c373c Link Winmm.lib that required by the high-resolution timer. 6af472a68 Update Win32 port with high resolution timer. aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler 19091a262 Add .section .preamble to m3 m4 m7 module ports ced60e1b7 Add missing parenthesis in ports assembly file 309dc77ca Modules Cortex-A7 IAR new port c752a4063 Modules Cortex-A7 GNU new port dc224b90f Fix race condition in tx_thread_wait_abort and update regression test 6e261f5b7 create threadx cmsis-pack

Update on 16 Dec 2022. Expand to see details.

2022-12-16T08:16:32Z

b5d5df511 #include tx_user.h in assembly files for cortex-m ports 33e04e3d5 initial port of MIPS SMP for GHS and GNU 2eda2c17d capitalize extensions for M23 asm files 21c354ccb Fix armv7-m MPU settings for corner case, unify txm_module_port.h files 4a1ff93f9 remove uneeded include for ac6 c823e91ff update riscv iar example for latest iar tools 5559d185d check module stack for overlap (not kernel stack) efa9ce7b7 apply patch from mobileye to fix time slice processing 75fdcb722 Updated copy_armv7_cm.yml de04b9904 initialize unused MPU settings so that aliasing will work 79b317b60 add config directory to IAR RISC-V port in order to use simulator

Release 6.1.7

2021-06-02T06:45:05Z

Release 6.1.5

2021-03-05T05:38:33Z

6.1 minor release

2020-09-30T22:42:41Z