threadx.git/ports/cortex_m4/iar/inc, branch dev

Updated ThreadX version constants and port strings to 6.5.2.202603 (#781)

2026-09-28T18:36:10Z

ThreadX still declares 6.5.1.202602 with hotfix 'a', which is the previous release rather than the one being cut. prepare_release.sh updated the five version constants in tx_api.h and the version string in 211 port headers across ports, ports_smp, ports_arch and ports_module. The hotfix letter is cleared, since the target has none. Nothing else changed: every line in the port commit carries a version, and no file outside an inc/tx_port.h was touched. The port consistency checks passed before the branch was cut, which is what the script gates on. Host regression 113/113 with zero warnings, and the AI disclosure check passes. Assisted-by: Claude Code (Opus 5)

Normalized the AI disclosure comment to one fixed line per file (#740)

2026-09-15T21:17:26Z

The per-edit disclosure named the product and model, so every agent and every model version appended another line. 74 files carried two to four of them, and the same five products had accumulated 13 spellings -- Copilot against GitHub Copilot, Claude Sonnet 4.6 against claude-sonnet-4.6, four spellings of Codex. Twenty assembly lines carried a doubled comment marker, `; //` or `@ //`. Every file now carries exactly one line, fixed text naming no product: Portions of this file were generated with AI assistance. It is written with the comment character that file already uses, so the `;` and `@` assembly files keep theirs and the doubled markers are gone. Precise attribution stays on the commit, where the Assisted-by trailer is per-change, dated and attached to the diff it describes. A header line cannot hold that record honestly, because the code it names gets rewritten and the line stays. A file-level flag answers whether; the history answers who. Comment-only. 455 files, 455 insertions and 574 deletions: every removed line was a disclosure line, every added line is the fixed text, and no file is left with zero or with more than one. `scripts/check_ports.sh` passes, including the reproducibility check that would catch a ports_arch master and its generated copies drifting apart. Recompiled against dev, every file that builds without a vendor toolchain gives a byte-identical object: 19 of 19 C files under common, 100 of 100 GNU assembly files, and all 16 assemblable files whose comment marker changed. The 10 remaining marker changes are ac5 and IAR sources where `;` already started the comment and only the redundant `//` was removed. Assisted-by: Claude Code (Opus 5)

Replaced the GNU-only dsb/isb 0xF operands with the UAL sy form (#729)

2026-09-15T20:24:45Z

Fixes #551 `_tx_thread_system_return_inline()` in the Cortex-M `tx_port.h` headers spells its barriers `dsb 0xF` and `isb 0xF`. A bare hexadecimal operand is a GNU assembler extension, and IAR rejects it with `operand syntax error`, so the header cannot be included at all. The block is guarded for GCC, armclang and IAR together, so every IAR user of an affected port hits it -- four independent reports on Cortex-M33 and M7 with EWARM 9.50 and 9.70. Both operands become `sy`, the Arm UAL name for exactly what `0xF` encodes. The generated instruction is unchanged. Applied to the two `ports_arch` masters and all 32 copies under `ports`, covering M0, M23, M3, M33, M4, M52, M55, M7 and M85 across ac5, ac6, gnu, iar and keil, plus the `scripts/check_ports.sh` probes that matched the old spelling. `check_ports.sh` passes, the copy scripts still reproduce every generated port byte for byte, and `arm-none-eabi-gcc -O2` compiles a caller for every patched header, emitting `dsb sy` and `isb sy`. Three headers that need toolchain intrinsics GCC does not ship fail identically on `dev`. Assisted-by: Copilot (Opus 5)

Restored ports_arch as the source of truth for the Cortex-M ports (#590)

2026-08-09T14:42:54Z

The Cortex-M ports under ports/ are generated. scripts/copy_armv7_m.sh copies one tx_port.h and the per tool sources to fifteen M3, M4 and M7 targets, and scripts/copy_armv8_m.sh does the same for nine M33, M55 and M85 targets. The ports_arch_check workflow runs both scripts and fails if the tree is not reproducible, so those copies are meant never to be edited directly. They were. Every Cortex-M fix since #523 was applied to the generated copies and not to the source, so the source fell behind and the check went red: running the three scripts on dev changes 35 files. The check triggers only on pull requests targeting master, which is why nothing caught it while the fixes were merged into dev. Left alone, the next run of these scripts would have reverted three separate pieces of work: the memory barriers and clobbers from #523, the correction of the IAR assembly header to use the assembler's own comment syntax, and the move of tx_initialize_low_level.S into example_build for the M33, M55 and M85 GNU ports from #514. Bring the sources up to what the ports carry today, and regenerate. Two behavioural changes come with that, both deliberate. The barriers from #523 reach the ac5 and keil variants of M3, M4 and M7, which were outside the scope of that fix and never received it. The barrier that follows restoring the interrupt posture, which #523 gave only to the GNU ports because GNU was the only toolchain that could be tested, now applies to every tool; the identical asm statement already shipped in the AC6 and IAR ports, so this adds a pipeline flush rather than any new compiler exposure. Regenerating also drops a stray #endif at the end of the Cortex-M85 IAR tx_port.h, added by #523, which left that header with one more #endif than #if and unable to compile. Every other ARMv8-M port was balanced. Verified that the scripts are idempotent afterwards, that ports_arch_check would pass, that no port loses a barrier or a clobber, that every regenerated header is preprocessor balanced, and that every Cortex-M port covered by the two scripts now carries the entry barrier. Assisted-by: Claude Code (Opus 5)

Release 6.5.1.202602a preparation (#547)

2026-06-08T14:59:04Z

* Updated version number constants * Updated port version strings --------- Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Fix/issue 545 basepri endif (#546)

2026-06-08T14:51:08Z

* Fixed #else replaced with #endif in tx_port.h for cortex_m3/m4/m7 gnu/ac6/iar ports In the __set_basepri_value/#ifdef TX_PORT_USE_BASEPRI block, an #else directive was incorrectly replaced with #endif in a prior commit. This caused the TX_PORT_USE_BASEPRI guard to close prematurely and left __enable_interrupts unconditionally visible (or triggered an orphaned #endif / missing #endif error at compile time). Affected ports: cortex_m3/ac6, cortex_m3/iar, cortex_m4/ac6, cortex_m4/gnu, cortex_m4/iar, cortex_m7/ac6, cortex_m7/gnu, cortex_m7/iar. For cortex_m3/gnu and cortex_m4/gnu the fix restores the #else and the existing second #endif now correctly closes the block. For the ac6/iar variants of m3/m4 and all m7 variants, the #else is restored and a missing closing #endif is added after __enable_interrupts. Also adds Linux shell build scripts (build_threadx.sh and build_threadx_sample.sh) for the cortex_m3/gnu, cortex_m4/gnu, and cortex_m7/gnu example_build directories as Linux equivalents of the existing .bat files. * Fixed missing linker script symbols in cortex_m4/gnu example_build cortexm4_crt0.S references several symbols that were absent from sample_threadx.ld, causing undefined-reference linker errors when building the sample: - __text_load_start__, __text_start__, __text_end__ - __rodata_load_start__, __rodata_start__, __rodata_end__ - __fast_load_start__, __fast_start__, __fast_end__ - __ctors_load_start__, __dtors_load_start__ Changes: - Added __text_start__/__text_end__ bounds to the .text section and __text_load_start__ via LOADADDR(.text). - Moved .rodata out of .text into its own section with start/end/load - Added __ctors_load_start__ and __dtors_load_start__ markers within .text (load address == VMA since the section is XIP in FLASH; the crt0 copy call becomes a no-op). - Added an empty .fast section in RAM with __fast_load_start__ pointing to __fast_start__ so the crt0 fast-copy call is a no-op. * Added Linux build scripts and fixed path bug in cortex_m23 for all ports changed between v6.5.0 and v6.5.1 Added build_threadx.sh (and build_threadx_sample.sh where applicable) as Linux equivalents of the Windows .bat scripts for all GNU-toolchain ports touched between v6.5.0.202601_rel and v6.5.1.202602_rel: arm9, arm11, cortex_a5/a7/a8/a9/a12/a15/a17, cortex_m0, cortex_m23, cortex_r4, cortex_r5 For cortex_m33/m55/m85 (which had no .bat equivalent), build_threadx.sh was written from scratch using the port CMakeLists.txt source lists and the correct CPU flags (-mcpu=cortex-m33/m55/m85 -mthumb). Also fixed a pre-existing bug in cortex_m23/gnu/example_build/ build_threadx.bat (and the generated .sh): tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c were referenced as ../src/ (port directory) instead of ../../../../common/src/ where they actually live. All 16 newly added build_threadx.sh scripts were verified to compile successfully with arm-none-eabi-gcc 13.2.1. --------- Closes #545 Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Release 6.5.1.202602 preparation (#543)

2026-06-03T20:55:01Z

* Updated version number constants * Updated port version strings --------- Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Fixed race condition and message loss in Cortex-M ports (#523)

2026-04-29T13:10:57Z

* Fixed race condition and message loss in Cortex-M GNU, AC6, and IAR ports (#516) - Added compiler memory barriers to BASEPRI management functions in tx_port.h. - Added architectural barriers (DSB/ISB) to scheduler return paths in tx_port.h and tx_thread_system_return.S to prevent fall-through before context switch. - These changes address spurious thread resumption and lost messages, especially when TX_NOT_INTERRUPTABLE is enabled. - These changes ensure that pending interrupts (specifically PendSV) are recognised before subsequent instructions are executed, following Kairalite's feedback and ARM architectural guidelines. Assisted-by: Gemini (Gemini 2.0 Flash) ----- * Added a comment in common/tx_queue_cleanup to document why the NI path omits revalidation guards - In `TX_NOT_INTERRUPTABLE` mode, the caller keeps interrupts disabled across the entire cleanup call, so the race window that makes the guards necessary in the interruptable path cannot occur. Add a comment explaining this, and noting that all paths that resume a suspended thread clear tx_thread_suspend_cleanup before calling _tx_thread_system_ni_resume, making double-cleanup impossible. This prevents future false-positive suggestions (e.g. from AI tools) to add redundant checks to the NI path. Relates to: eclipse-threadx/threadx#516 Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Updated copyright headers and version number constants (#509)

2026-03-05T09:46:30Z

* Updated version number constants * Removed revision history from all files * Added Eclipse ThreadX contributors' copyright header

Updated ports version to v6.4.2.

2025-02-24T18:31:48Z