threadx.git/ports/risc-v32/gnu/src/tx_thread_context_restore.S, branch dev

Implemented lazy FPU, GP relaxation, and QEMU automation for GNU port in arch/risc-v32 (#513)

2026-05-25T20:43:24Z

This PR adds three functional improvements to the RISC-V 32-bit GNU port. Lazy FPU stacking (tx_thread_context_save.S, tx_thread_context_restore.S, tx_thread_schedule.S): FP register save/restore is now skipped whenmstatus.FS is Off, reducing context switch overhead for threads that do not use floating point. GP relaxation (cmake/riscv32_gnu.cmake, entry.s, link.lds): Enables the -mrelax compiler flag and defines __global_pointer$ in the linker script.The entry stub initializes gp at startup. gp is not saved or restored during context switches. WFI in idle loop (tx_thread_schedule.S): The scheduler issues wfi when no thread is ready, replacing busy-waiting with a low-power sleep. A Python/QEMU/GDB functional test runner is added under ports/risc-v32/gnu/example_build/qemu_virt/test/. It validates context switching, FPUcontext preservation, timer interrupts, and preemption. To run: cd ports/risc-v32/gnu/example_build/qemu_virt make check-functional-riscv32 Tested on QEMU virt machine (rv32gc). Co-authored-by: Wei-Chen Lai Winstonllllai@users.noreply.github.com Co-authored-by: Frédéric Desbiens frederic.desbiens@eclipse-foundation.org Co-authored-by: Copilot 223556219+Copilot@users.noreply.github.com

Added port for the OpenHW CORE-V MCU platform (#535)

2026-05-25T15:28:55Z

Adds a complete ThreadX port for the OpenHW CORE-V MCU SoC, targeting the Digilent Nexys A7 FPGA board with an Ashling Opella-LD debug probe. New files --------- cmake/riscv64-gcc-rv32imc.cmake CMake toolchain file for riscv64-unknown-elf-gcc targeting rv32imc_zicsr/ilp32. ports/risc-v32/gnu/example_build/core_v_mcu/ -- Full BSP + demo application: Assembly crt0.S C runtime startup (BSS clear, GP/SP init, call main) vectors.S 32-entry vectored interrupt table at 0x1c000800 tx_initialize_low_level.S mtvec setup (vectored mode), stack/free-mem pointers BSP drivers (bsp/) system_core_v_mcu.c Top-level init and ISR dispatcher (isr_table[32]) irq.c PULP APB interrupt controller (enable/disable/mask) timer_irq.c PULP FC Timer -- 100 Hz tick from 10 MHz SOC clock fll.c Frequency Locked Loop -- 5 MHz to 50 MHz (FPGA) uart_driver.c UDMA UART channel 0 -- polled TX, non-blocking RX (8-bit transfer width) gpio.c PULP apb_gpiov2 driver: set/clear/toggle/direction by pin index; pad-mux via per-pad indexed registers at APB_SOC_CTRL + 0x400 + pad*4; full pinmux API (gpio_setpinmux, gpio_getpinmux, gpio_pin_set_dir, gpio_pin_read_status) i2c_master.c Polled UDMA I2C master adt7420.c ADT7420 temperature sensor driver string.c Freestanding memset/memcpy shim (no newlib) Headers (include/) Peripheral register maps, MMIO inlines, BSP API declarations, tx_user.h Application demo_threadx.c Two threads: LED[0] blink at 1 Hz (IO pad 11, GPIO pin 4, MUX=2) + UART heartbeat with startup banner ("Eclipse ThreadX for OpenHW CORE-V MCU vX.Y.Z.BBBBB") link.ld Linker script: .vectors@0x1c000800, .text@0x1c000880 CMakeLists.txt Build definition (references THREADX_ROOT) build.sh One-shot CMake+Ninja build script Tooling install_deps.sh Automates toolchain/OpenOCD dependency setup deploy.sh One-step GDB flashing via Ashling Opella-LD; gdb-multiarch fallback when riscv64-unknown-elf-gdb is absent; supports --wsl flag required by usbipd-win v5.x openocd-nexys-Ashling-Opella-LD.cfg OpenOCD config for Opella-LD over JTAG Tests (tests/) test_irq.c / test_timer.c Host-compiled unit tests (2/2 pass) mock/mmio_mock.* Software MMIO register map for host testing Documentation README.md Hardware overview, build, flash/debug, BSP API reference Architecture notes ------------------ - CV32E40P uses the PULP/PULPissimo interrupt controller (not CLINT); IRQ lines are masked via APB registers, not the mie CSR. - mtvec must be 256-byte aligned; vectors placed at 0x1c000800 (vectored mode). - Timer IRQ = line 10; dispatch via isr_table[mcause & 0x1f]. - Build: -march=rv32imc_zicsr -mabi=ilp32, -ffreestanding, -nodefaultlibs. - Verified: ELF 11 KB text, sections at correct addresses, unit tests pass. Third-party attributions ------------------------ BSP files derived from core-v-freertos (Apache-2.0): (c) 2019-2020 ETH Zurich and University of Bologna (c) 2020 GreenWaves Technologies (c) 2011-2014 Wind River Systems, Inc. (c) 2017 SiFive Inc. (crt0.S, BSD-2-Clause portions) All original copyright notices retained; see individual file headers. SPDX: Apache-2.0 AND MIT (crt0.S: (Apache-2.0 OR BSD-2-Clause) AND MIT). Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Add QEMU based CI regression test infra for RV32 and RV64 (#526)

2026-05-19T15:03:23Z

Added a QEMU virt-machine BSP and CTest infrastructure to run the ThreadX regression suite on both RISC-V 32-bit and 64-bit targets in CI. New components: - BSP (entry, trap, PLIC, CLINT timer, UART, linker script) targeting QEMU virt machine for RV32 and RV64 - CMake build system with Ninja, supporting multiple build configs - CI scripts: install_riscv.sh (toolchain + QEMU), build_tx_riscv.sh, test_tx_riscv.sh - GitHub Actions workflow job for RISC-V regression gating Port fixes: - RV32 tx_thread_context_restore.S: set MPIE alongside MPP (0x1800 → 0x1880) so mret re-enables interrupts - RV32/RV64 tx_port.h: add TX_REGRESSION_TEST extension macros needed by the test harness - RV32/RV64 example_build scripts: add compile and QEMU launch steps Regression test portability fixes: - Block memory tests: increase pool sizes (320 → 340) to accommodate larger RISC-V block-header alignment - Byte memory test: replace hardcoded offsets with BYTE_POOL_OVERHEAD macro for portable pool-size computation - Event flag timeout test: make counter tolerance unconditional, removing linux-only guard Signed-off-by: Akif Ejaz

Updated copyright headers and version number constants (#509)

2026-03-05T09:46:30Z

* Updated version number constants * Removed revision history from all files * Added Eclipse ThreadX contributors' copyright header

Add RISC-V32 arch. port layer

2026-02-16T12:15:13Z

This update adapts the ThreadX low-level kernel routines for RV32, including: - startup and initialization logic - context save/restore implementations - interrupt control and scheduler entry - thread stack build and system return paths - timer interrupt handling - made it complient as per new risc-v64/gnu & threadx style - added reademe for risc-v32/gnu port These changes provide full low-level support needed to run ThreadX on RISC-V32 targets. Signed-off-by: Akif Ejaz