<feed xmlns='http://www.w3.org/2005/Atom'>
<title>threadx.git/ports/risc-v32/gnu/src/tx_timer_interrupt.S, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/threadx.git/atom/ports/risc-v32/gnu/src/tx_timer_interrupt.S?h=master</id>
<link rel='self' href='http://cgit.235523.xyz/threadx.git/atom/ports/risc-v32/gnu/src/tx_timer_interrupt.S?h=master'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/threadx.git/'/>
<updated>2026-03-05T09:46:30Z</updated>
<entry>
<title>Updated copyright headers and version number constants (#509)</title>
<updated>2026-03-05T09:46:30Z</updated>
<author>
<name>Frédéric Desbiens</name>
<email>frederic.desbiens@eclipse-foundation.org</email>
</author>
<published>2026-03-05T09:46:30Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/threadx.git/commit/?id=c3259a216026372e3833dd8996a68f77e8595fbd'/>
<id>urn:sha1:c3259a216026372e3833dd8996a68f77e8595fbd</id>
<content type='text'>
* Updated version number constants

* Removed revision history from all files

* Added Eclipse ThreadX contributors' copyright header </content>
</entry>
<entry>
<title>Add RISC-V32 arch. port layer</title>
<updated>2026-02-16T12:15:13Z</updated>
<author>
<name>Akif Ejaz</name>
<email>akifejaz40@gmail.com</email>
</author>
<published>2026-02-16T12:15:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/threadx.git/commit/?id=757db54d6d10edc655eee9cfe02ecd4d93be5fed'/>
<id>urn:sha1:757db54d6d10edc655eee9cfe02ecd4d93be5fed</id>
<content type='text'>
This update adapts the ThreadX low-level kernel routines
for RV32, including:
  - startup and initialization logic
  - context save/restore implementations
  - interrupt control and scheduler entry
  - thread stack build and system return paths
  - timer interrupt handling
  - made it complient as per new risc-v64/gnu
      &amp; threadx style
  - added reademe for risc-v32/gnu port

These changes provide full low-level support needed to run
ThreadX on RISC-V32 targets.

Signed-off-by: Akif Ejaz &lt;akif.ejaz@10xengineers.ai&gt;
</content>
</entry>
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