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<title>threadx.git/ports/risc-v64/gnu/example_build/erbium/CMakeLists.txt, branch dev</title>
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<updated>2026-09-30T14:49:55Z</updated>
<entry>
<title>Added simulator tests for Erbium interrupt regressions</title>
<updated>2026-09-30T14:49:55Z</updated>
<author>
<name>Frédéric Desbiens</name>
<email>frederic.desbiens@eclipse-foundation.org</email>
</author>
<published>2026-09-30T13:40:59Z</published>
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<id>urn:sha1:f19d8c267d4b9f9495407f36e154c7ea6deea63a</id>
<content type='text'>
Long polling UART writes can mask timer interrupts across several tick periods.
PLIC enable-word updates can overwrite a change made by an interrupt handler.
The board example had no simulator tests for either case.

Added two simulator images and a runner. One compares hardware timer progress with
ThreadX ticks after a long print. The other toggles one PLIC source in timer
context while a thread changes another. Both tests fail on the PR code and pass
with the corresponding local fixes.

GCC 15.2.0 and Ninja built both images. erbium_emu reproduced both failures;
control runs passed both tests. Port consistency checks passed. No silicon run.

Assisted-by: Codex (GPT-6-Sol) &lt;noreply@openai.com&gt;
</content>
</entry>
<entry>
<title>Added an Erbium example to the RISC-V64 GNU port</title>
<updated>2026-09-30T14:49:55Z</updated>
<author>
<name>Afonso Oliveira</name>
<email>afonso.oliveira707@gmail.com</email>
</author>
<published>2026-09-30T11:13:03Z</published>
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<id>urn:sha1:7212b366aeb0e02eae4cc1cdc6f9787b19bfd79e</id>
<content type='text'>
ThreadX had no board support for Erbium, the OpenHW Foundation CORE-ET RISC-V platform
that Zephyr and NuttX support. Its hart implements only part of the F extension, needs a
4 KiB aligned mtvec and uses the original Shakti UART.

The example runs the standard demo on hart 0 in machine mode. It builds the library and
the demo for rv64imc_zicsr_zifencei with the soft-float lp64 ABI and links without libc
or libgcc, so the pinned riscv64-unknown-elf toolchain can build it. It programs the
machine timer, a polling UART console and the PLIC, writing the source priorities and
threshold that silicon hardwires because the simulator resets them to 0. No shared file
changes.

The demo built without warnings and ran on erbium_emu from et-platform 836a4ab, with all
eight threads reporting and five thread 0 wakeups in 100M cycles, which matches the 2
MHz tick. Separate test images took five PLIC UART interrupts through the ThreadX ISR
path and halted with mcause 2 on an illegal instruction. check_ai_disclosure.sh and
check_ports.sh passed.

Assisted-by: Claude Code (Opus 5.5) &lt;noreply@anthropic.com&gt;
</content>
</entry>
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