threadx.git/ports/risc-v64/gnu/example_build/erbium/test, branch devUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/threadx.git/atom/ports/risc-v64/gnu/example_build/erbium/test?h=dev2026-09-30T14:49:55ZAdded simulator tests for Erbium interrupt regressions2026-09-30T14:49:55ZFrédéric Desbiensfrederic.desbiens@eclipse-foundation.org2026-09-30T13:40:59Zurn:sha1:f19d8c267d4b9f9495407f36e154c7ea6deea63a
Long polling UART writes can mask timer interrupts across several tick periods.
PLIC enable-word updates can overwrite a change made by an interrupt handler.
The board example had no simulator tests for either case.
Added two simulator images and a runner. One compares hardware timer progress with
ThreadX ticks after a long print. The other toggles one PLIC source in timer
context while a thread changes another. Both tests fail on the PR code and pass
with the corresponding local fixes.
GCC 15.2.0 and Ninja built both images. erbium_emu reproduced both failures;
control runs passed both tests. Port consistency checks passed. No silicon run.
Assisted-by: Codex (GPT-6-Sol) <noreply@openai.com>