threadx.git/ports/risc-v64/gnu/src/tx_initialize_low_level.S, branch v6.5.2.202603_rel

riscv64: spec compliance and regression test fix (#698)

2026-09-09T13:26:11Z

* spec compliance Signed-off-by: Akif Ejaz * revert the demo changes Signed-off-by: Akif Ejaz * Restored the FPU demo hook so the RISC-V64 functional test can pass The new check-functional-riscv64 target verifies FPU context switching by watching fpu_test_val advance by 1.1f on each pass through thread_6_and_7_entry. The GDB script deliberately treats a missing symbol as a failure rather than silently skipping the check, but the demo no longer defined it, so the target failed on every run: FPU_VERIFIED_FAIL_NO_SYMBOL The definition and the increment are restored, matching what the risc-v32 demo already carries. The functional target now passes end to end. Three small corrections are folded in: - tx_port.h carried a comment stating that the ISA string must include Zicsr, but nothing enforced it, so an rv64imac build failed with a wall of assembler "unrecognized opcode" errors. It now stops at one clear diagnostic. - Removed TX_RISCV_TRAP_CALL_FRAME_SIZE, which nothing referenced. - The example .gitignore listed qemu-riscv32.log, but the runner writes qemu-riscv64.log, so the generated log showed up as an untracked file. Assisted-by: Claude Code (Opus 5) --------- Signed-off-by: Akif Ejaz Co-authored-by: Frédéric Desbiens

Updated copyright headers and version number constants (#509)

2026-03-05T09:46:30Z

* Updated version number constants * Removed revision history from all files * Added Eclipse ThreadX contributors' copyright header

Cleanup the macros in tx_port.h & comments in inc/*.S

2026-02-05T11:16:59Z

- removed the trailing whitespaces Signed-off-by: Akif Ejaz

improve port robustness, portability, and CSR handling

2026-01-26T10:48:46Z

- removed tx_port.h dependency from .S files - replaced tx_timer_interrupt.c with tx_timer_interrupt.S - made some cleanups, formatting to better readability - removed macros (LOAD/STORE/REGBYTES) changed register nomenclature to use RISC-V ABI names (ra, sp, t0, etc.) - added readme_threadx.txt Signed-off-by: Akif Ejaz

riscv : add riscv qemu virt support and fix fs bit error in mstatus

2024-10-25T12:03:11Z

Update copyright.

2024-01-29T05:51:15Z

Release 6.2.1 on 08 Mar 2023. Expand to see details.

2023-03-08T08:26:22Z

cee19603d Include tx_user.h conditionally. e40e08007 Update owners d69641273 Update release date and version 394aee52f Add tx_user.h to GNU port assembly files 5cca2ddd0 RISC-V 64 bit port for Microchip e0f2c373c Link Winmm.lib that required by the high-resolution timer. 6af472a68 Update Win32 port with high resolution timer. aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler 19091a262 Add .section .preamble to m3 m4 m7 module ports ced60e1b7 Add missing parenthesis in ports assembly file 309dc77ca Modules Cortex-A7 IAR new port c752a4063 Modules Cortex-A7 GNU new port dc224b90f Fix race condition in tx_thread_wait_abort and update regression test 6e261f5b7 create threadx cmsis-pack