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<title>threadx.git/ports/risc-v64/gnu/src/tx_timer_interrupt.S, branch v6.5.2.202603_rel</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/threadx.git/atom/ports/risc-v64/gnu/src/tx_timer_interrupt.S?h=v6.5.2.202603_rel</id>
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<updated>2026-09-09T13:26:11Z</updated>
<entry>
<title>riscv64: spec compliance and regression test fix (#698)</title>
<updated>2026-09-09T13:26:11Z</updated>
<author>
<name>Akif Ejaz</name>
<email>akifejaz40@gmail.com</email>
</author>
<published>2026-09-09T13:26:11Z</published>
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<id>urn:sha1:164f211a01f6bc756c6620ec8ca55f4ccf9f6041</id>
<content type='text'>
* spec compliance

Signed-off-by: Akif Ejaz &lt;akifejaz40@gmail.com&gt;

* revert the demo changes

Signed-off-by: Akif Ejaz &lt;akifejaz40@gmail.com&gt;

* Restored the FPU demo hook so the RISC-V64 functional test can pass

The new check-functional-riscv64 target verifies FPU context switching by
watching fpu_test_val advance by 1.1f on each pass through
thread_6_and_7_entry. The GDB script deliberately treats a missing symbol
as a failure rather than silently skipping the check, but the demo no
longer defined it, so the target failed on every run:

    FPU_VERIFIED_FAIL_NO_SYMBOL

The definition and the increment are restored, matching what the risc-v32
demo already carries. The functional target now passes end to end.

Three small corrections are folded in:

- tx_port.h carried a comment stating that the ISA string must include
  Zicsr, but nothing enforced it, so an rv64imac build failed with a wall
  of assembler "unrecognized opcode" errors. It now stops at one clear
  diagnostic.
- Removed TX_RISCV_TRAP_CALL_FRAME_SIZE, which nothing referenced.
- The example .gitignore listed qemu-riscv32.log, but the runner writes
  qemu-riscv64.log, so the generated log showed up as an untracked file.

Assisted-by: Claude Code (Opus 5) &lt;noreply@anthropic.com&gt;

---------

Signed-off-by: Akif Ejaz &lt;akifejaz40@gmail.com&gt;
Co-authored-by: Frédéric Desbiens &lt;frederic.desbiens@eclipse-foundation.org&gt;</content>
</entry>
<entry>
<title>Reverted ULONG to be 4 bytes long, fixing missaligment issue in the current port (#534)</title>
<updated>2026-05-25T20:12:33Z</updated>
<author>
<name>Christos Papadopoulos</name>
<email>papadopoulos.chris@icloud.com</email>
</author>
<published>2026-05-25T20:12:33Z</published>
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<id>urn:sha1:5b1b740a6610ae3434da9fc2cd55f390f7619429</id>
<content type='text'>
* Reverted RISCV-64 port

* Fixed wrong load/store instructions used</content>
</entry>
<entry>
<title>Updated copyright headers and version number constants (#509)</title>
<updated>2026-03-05T09:46:30Z</updated>
<author>
<name>Frédéric Desbiens</name>
<email>frederic.desbiens@eclipse-foundation.org</email>
</author>
<published>2026-03-05T09:46:30Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/threadx.git/commit/?id=c3259a216026372e3833dd8996a68f77e8595fbd'/>
<id>urn:sha1:c3259a216026372e3833dd8996a68f77e8595fbd</id>
<content type='text'>
* Updated version number constants

* Removed revision history from all files

* Added Eclipse ThreadX contributors' copyright header </content>
</entry>
<entry>
<title>Cleanup the macros in tx_port.h &amp; comments in inc/*.S</title>
<updated>2026-02-05T11:16:59Z</updated>
<author>
<name>Akif Ejaz</name>
<email>akifejaz40@gmail.com</email>
</author>
<published>2026-02-05T11:16:59Z</published>
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<id>urn:sha1:21256bed516345f0918f49b314758c60b5691562</id>
<content type='text'>
- removed the trailing whitespaces

Signed-off-by: Akif Ejaz &lt;akif.ejaz@10xengineers.ai&gt;
</content>
</entry>
<entry>
<title>few cleanups</title>
<updated>2026-01-26T11:08:51Z</updated>
<author>
<name>Akif Ejaz</name>
<email>akifejaz40@gmail.com</email>
</author>
<published>2026-01-26T11:08:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/threadx.git/commit/?id=99ed67df5afeeac52827c2681438a4627c4198d7'/>
<id>urn:sha1:99ed67df5afeeac52827c2681438a4627c4198d7</id>
<content type='text'>
Signed-off-by: Akif Ejaz &lt;akif.ejaz@10xengineers.ai&gt;
</content>
</entry>
<entry>
<title>improve port robustness, portability, and CSR handling</title>
<updated>2026-01-26T10:48:46Z</updated>
<author>
<name>Akif Ejaz</name>
<email>akifejaz40@gmail.com</email>
</author>
<published>2026-01-26T10:48:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/threadx.git/commit/?id=6c25effb405cc694578dec664a798fc8af3107e1'/>
<id>urn:sha1:6c25effb405cc694578dec664a798fc8af3107e1</id>
<content type='text'>
- removed tx_port.h dependency from .S files
- replaced tx_timer_interrupt.c with tx_timer_interrupt.S
-  made some cleanups, formatting to better readability
- removed macros (LOAD/STORE/REGBYTES)
  changed register nomenclature to use RISC-V ABI
  names (ra, sp, t0, etc.)
- added readme_threadx.txt

Signed-off-by: Akif Ejaz &lt;akif.ejaz@10xengineers.ai&gt;
</content>
</entry>
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