threadx.git/ports/risc-v64/gnu/src, branch master

Reverted ULONG to be 4 bytes long, fixing missaligment issue in the current port (#534)

2026-05-25T20:12:33Z

* Reverted RISCV-64 port * Fixed wrong load/store instructions used

Added RISC-V board Bananapi BPI-F3 (SpacemiT K1 SoC) BSP Support (#531)

2026-05-25T19:59:17Z

* Add BananaPi BPI-F3 BSP support Add RISC-V supervisor support to the rv64/gnu port and provide a complete board support package for the BananaPi BPI-F3 (SpacemiT K1 SoC, X60 cores). Port changes (risc-v64/gnu): - Guard all CSR accesses with TX_RISCV_SMODE to select S-mode registers (sstatus/sepc/sie/sret) vs M-mode (mstatus/mepc/mie/mret) in context_save, context_restore, schedule, system_return, interrupt_control, and stack_build. - Add S-mode TX_INT_ENABLE/TX_DISABLE and inline TX_RESTORE macros to tx_port.h. - Add TX_RISCV_SMODE CMake option to CMakeLists.txt. BananaPi BPI-F3 BSP (example_build/bananapi-f3): - Boot flow: FSBL → OpenSBI (M-mode) → U-Boot (S-mode) → ThreadX - S-mode trap handler with context save/restore integration - SBI legacy ecall timer at 10 Hz (24 MHz timebase) - PLIC driver with S-mode context, stale-IRQ drain, and callbacks - PXA-compatible UART0 console (115200 8N1) - Linker script at 0x200000 load address Tested on risc-v board, BananaPi BPI-F3 hardware. Signed-off-by: Akif Ejaz * Fixed S-mode context restore and PLIC spurious IRQ handling - tx_thread_context_restore.S (non-nested path): set SPIE(0x20) alongside SPP(0x100) so sret re-enables interrupts in the restored thread. - tx_thread_context_restore.S (both S-mode paths): use FS=Dirty (0x6000) instead of FS=Initial (0x2000) to match tx_thread_schedule.S and prevent FP register corruption across context switches. - plic.c (plic_irq_intr): return early when plic_claim() yields 0 (no pending interrupt) to avoid completing a spurious IRQ ID 0, which is undefined behavior per the PLIC spec. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --------- Signed-off-by: Akif Ejaz Co-authored-by: Frédéric Desbiens Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Fixed MPIE being cleared leading to have interrupts being disable after an mret instruction (#522)

2026-05-13T13:00:54Z

* Fixed MPIE being cleared leading to have interrupts being disable when returning from machine mode * Removed wrong register operand and replaced by immediate value

Merge pull request #508 from goodnorning/feature/rv64_rvv_support

2026-04-14T13:26:33Z

Added rv64 rvv support

RISC-V64 arch. port support RVV Extension;

2026-04-07T03:41:33Z

Updated copyright headers and version number constants (#509)

2026-03-05T09:46:30Z

* Updated version number constants * Removed revision history from all files * Added Eclipse ThreadX contributors' copyright header

removed dead code in riscv64/gnu port

2026-02-16T08:57:51Z

Signed-off-by: Akif Ejaz

Cleanup the macros in tx_port.h & comments in inc/*.S

2026-02-05T11:16:59Z

- removed the trailing whitespaces Signed-off-by: Akif Ejaz

few cleanups

2026-01-26T11:08:51Z

Signed-off-by: Akif Ejaz

improve port robustness, portability, and CSR handling

2026-01-26T10:48:46Z

- removed tx_port.h dependency from .S files - replaced tx_timer_interrupt.c with tx_timer_interrupt.S - made some cleanups, formatting to better readability - removed macros (LOAD/STORE/REGBYTES) changed register nomenclature to use RISC-V ABI names (ra, sp, t0, etc.) - added readme_threadx.txt Signed-off-by: Akif Ejaz