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<title>threadx.git/ports_arch/ARMv7-M/threadx_modules/gnu, branch dev</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/threadx.git/atom/ports_arch/ARMv7-M/threadx_modules/gnu?h=dev</id>
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<updated>2026-09-15T21:17:26Z</updated>
<entry>
<title>Normalized the AI disclosure comment to one fixed line per file (#740)</title>
<updated>2026-09-15T21:17:26Z</updated>
<author>
<name>Frédéric Desbiens</name>
<email>frederic.desbiens@eclipse-foundation.org</email>
</author>
<published>2026-09-15T21:17:26Z</published>
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<id>urn:sha1:9e4c57138dfa004cd512b60259c1c5047a8b3dd1</id>
<content type='text'>
The per-edit disclosure named the product and model, so every agent and every
model version appended another line. 74 files carried two to four of them, and
the same five products had accumulated 13 spellings -- Copilot against GitHub
Copilot, Claude Sonnet 4.6 against claude-sonnet-4.6, four spellings of Codex.
Twenty assembly lines carried a doubled comment marker, `; //` or `@ //`.

Every file now carries exactly one line, fixed text naming no product:

    Portions of this file were generated with AI assistance.

It is written with the comment character that file already uses, so the `;`
and `@` assembly files keep theirs and the doubled markers are gone. Precise
attribution stays on the commit, where the Assisted-by trailer is per-change,
dated and attached to the diff it describes. A header line cannot hold that
record honestly, because the code it names gets rewritten and the line stays.
A file-level flag answers whether; the history answers who.

Comment-only. 455 files, 455 insertions and 574 deletions: every removed line
was a disclosure line, every added line is the fixed text, and no file is left
with zero or with more than one. `scripts/check_ports.sh` passes, including the
reproducibility check that would catch a ports_arch master and its generated
copies drifting apart. Recompiled against dev, every file that builds without a
vendor toolchain gives a byte-identical object: 19 of 19 C files under common,
100 of 100 GNU assembly files, and all 16 assemblable files whose comment
marker changed. The 10 remaining marker changes are ac5 and IAR sources where
`;` already started the comment and only the redundant `//` was removed.

Assisted-by: Claude Code (Opus 5) &lt;noreply@anthropic.com&gt;</content>
</entry>
<entry>
<title>Allowed a BASEPRI-masked interrupt to wake the Cortex-M idle loop from WFI (#711)</title>
<updated>2026-09-09T15:29:14Z</updated>
<author>
<name>Frédéric Desbiens</name>
<email>frederic.desbiens@eclipse-foundation.org</email>
</author>
<published>2026-09-09T15:29:14Z</published>
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<id>urn:sha1:3fc28d8979828b5f928650e78c3a134c562de579</id>
<content type='text'>
The idle loop in _tx_thread_schedule masks interrupts before re-reading
_tx_thread_execute_ptr, so that an interrupt cannot make a thread ready
between that read and the WFI and then be lost. With PRIMASK that is safe:
the architecture excludes PRIMASK from the WFI wake-up condition, so the
interrupt still wakes the processor and is taken as soon as the loop
re-enables interrupts.

BASEPRI is not excluded. When TX_PORT_USE_BASEPRI is defined, the mask
written at the top of the loop is still in place at the WFI, so any
interrupt at or below TX_PORT_BASEPRI fails to wake the processor at all.
On a system where every interrupt is managed by ThreadX, that is every
interrupt, and the processor stays in WFI or in the low power mode entered
by tx_low_power_enter until something outside the mask happens.

Set PRIMASK and clear BASEPRI for the duration of the WFI, then restore
BASEPRI and clear PRIMASK. Interrupts remain masked across the whole
window, so the original race is still closed, but the wake-up condition is
now evaluated with BASEPRI clear and any enabled interrupt can end the wait.
A pending interrupt is taken at the CPSIE i, or at the existing unmask
further down the loop if it falls below TX_PORT_BASEPRI.

The change is made in the ARMv7-M and ARMv8-M sources under ports_arch,
including the module manager, and propagated to the generated ports with
the copy scripts. The ghs and keil ports do not implement
TX_PORT_USE_BASEPRI, and Cortex-M0/M0+/M23 have no BASEPRI register, so
those ports are unaffected.

Verified by assembling every patched GNU port for Cortex-M3, M4, M7, M33,
M55 and M85, with and without TX_PORT_USE_BASEPRI, TX_LOW_POWER and
TX_ENABLE_EXECUTION_CHANGE_NOTIFY, and by checking the disassembly of the
idle loop.

Fixes #279

Assisted-by: Copilot (Opus 5) &lt;noreply@github.com&gt;</content>
</entry>
<entry>
<title>Updated Cortex-M BASEPRI zero immediates (#564)</title>
<updated>2026-06-29T20:07:12Z</updated>
<author>
<name>Frédéric Desbiens</name>
<email>frederic.desbiens@eclipse-foundation.org</email>
</author>
<published>2026-06-29T20:07:12Z</published>
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<id>urn:sha1:3fcfb4e4c984c66eaeaafcff908afb7e2dfb72fa</id>
<content type='text'>
Use explicit immediate syntax when clearing BASEPRI in GNU and AC6 Cortex-M scheduler assembly.

Co-authored-by: Codex &lt;codex@openai.com&gt;</content>
</entry>
<entry>
<title>Updated copyright headers and version number constants (#509)</title>
<updated>2026-03-05T09:46:30Z</updated>
<author>
<name>Frédéric Desbiens</name>
<email>frederic.desbiens@eclipse-foundation.org</email>
</author>
<published>2026-03-05T09:46:30Z</published>
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<id>urn:sha1:c3259a216026372e3833dd8996a68f77e8595fbd</id>
<content type='text'>
* Updated version number constants

* Removed revision history from all files

* Added Eclipse ThreadX contributors' copyright header </content>
</entry>
<entry>
<title>Update copyright.</title>
<updated>2024-01-29T05:51:15Z</updated>
<author>
<name>Bo Chen (from Dev Box)</name>
<email>boche@microsoft.com</email>
</author>
<published>2024-01-29T05:51:15Z</published>
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<id>urn:sha1:8276bcf71142197e09551e29f1779299fa591ec7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Release ARMv7-M and ARMv8-M architecture ports (#249)</title>
<updated>2023-04-18T10:11:20Z</updated>
<author>
<name>TiejunZhou</name>
<email>50469179+TiejunMS@users.noreply.github.com</email>
</author>
<published>2023-04-18T10:11:20Z</published>
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<id>urn:sha1:23680f5e5f01702f7327160b8766bc893a5e6c54</id>
<content type='text'>
* Release ARMv7-M and ARMv8-M architecture ports

* Add a pipeline to check ports_arch</content>
</entry>
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