diff options
| author | Frédéric Desbiens <[email protected]> | 2026-06-29 16:22:52 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-06-29 16:22:52 -0400 |
| commit | a33f6efc483da9e49fa6598d07e02ec213ea04db (patch) | |
| tree | 03ca7424e3f75de2d9e545dc179b21e9702b9e2a | |
| parent | 3fcfb4e4c984c66eaeaafcff908afb7e2dfb72fa (diff) | |
Updated Cortex-R4 Thumb bit immediates (#565)
Use explicit immediate syntax when testing the Thumb bit in AC6 Cortex-R4 stack build assembly.
Co-authored-by: Codex <[email protected]>
| -rw-r--r-- | ports/cortex_r4/ac6/src/tx_thread_stack_build.S | 3 | ||||
| -rw-r--r-- | ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/ports/cortex_r4/ac6/src/tx_thread_stack_build.S b/ports/cortex_r4/ac6/src/tx_thread_stack_build.S index a2993136..ff916007 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_r4/ac6/src/tx_thread_stack_build.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Codex (GPT-5). /**************************************************************************/ @@ -143,7 +144,7 @@ _tx_thread_stack_build: MRS r3, CPSR // Pickup CPSR BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR ORR r3, r3, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled - TST r1, 1 // Test if Thumb bit is set in entry function address + TST r1, #1 // Test if Thumb bit is set in entry function address ITE NE ORRNE r3, r3, #THUMB_BIT // Yes, set the Thumb bit BICEQ r3, r3, #THUMB_BIT // No, clear the Thumb bit diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S index 8f122083..e3142ec4 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S @@ -8,6 +8,7 @@ * * SPDX-License-Identifier: MIT **************************************************************************/ +// Some portions generated by Codex (GPT-5). /**************************************************************************/ @@ -143,7 +144,7 @@ _tx_thread_stack_build: BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR ORR r3, r3, #SYS_MODE // Build CPSR, SYS mode, interrupts enabled - TST r1, 1 // Test if Thumb bit is set in entry function address + TST r1, #1 // Test if Thumb bit is set in entry function address ITE NE ORRNE r3, r3, #THUMB_BIT // Yes, set the Thumb bit BICEQ r3, r3, #THUMB_BIT // No, clear the Thumb bit |