diff options
| author | hefanbo <[email protected]> | 2026-06-25 00:16:51 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2026-06-24 12:16:51 -0400 |
| commit | d9e7dfea89046c901100b42afa230b37823718f7 (patch) | |
| tree | dc41cc1734b73509859efdad6d9ef0d1a8280b27 | |
| parent | 2dfe5acfb0927c5b32d4810dbdbc18aeae5860a1 (diff) | |
Add SysTick counter reset in Cortex-M ports (#561)
* Add SysTick counter reset in Cortex-M ports
The SysTick counter value (SYST_CVR @0xE000E018) is indeterminate after
reset. Without clearing it prior to enabling the counter, the first tick
interval becomes unpredictable.
* Fixed missing comment and added generated-by header in Cortex-M0/AC6 port
Added the missing inline comment on the LDR r1, =0 instruction
(Build value for SysTick reset) and the required AI-generated
attribution comment under the copyright header.
---------
Co-authored-by: Frédéric Desbiens <[email protected]>
Co-authored-by: Copilot <[email protected]>
66 files changed, 199 insertions, 0 deletions
diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S index f7e3eb2d..7aad3a30 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -7,6 +7,7 @@ @ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ +@ // Some portions generated by GitHub Copilot (Claude Sonnet 4.6). @ @ @/**************************************************************************/ @@ -111,6 +112,9 @@ _tx_initialize_low_level: @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r1, =0 @ Build value for SysTick reset + STR r1, [r0, #0x10] @ Reset SysTick Control + STR r1, [r0, #0x18] @ Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] @ Setup SysTick Reload Value LDR r1, =0x7 @ Build SysTick Control Enable Value diff --git a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S index c5565bdd..1625f570 100644 --- a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ LDR r0, =0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOVW r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S index ba092253..cc8deeee 100644 --- a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S @@ -107,6 +107,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ LDR r0, =0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOVW r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m23/iar/src/tx_initialize_low_level.s b/ports/cortex_m23/iar/src/tx_initialize_low_level.s index fb6a109f..90849145 100644 --- a/ports/cortex_m23/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m23/iar/src/tx_initialize_low_level.s @@ -104,6 +104,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ LDR r0, =0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s index f0c38db2..cb0b2605 100644 --- a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s @@ -162,6 +162,9 @@ _tx_initialize_low_level ; /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S index b5ef57e5..325d21b3 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ MOV r0, #0xE000E000 @ Build address of NVIC registers + MOV r1, #0 @ Build value for SysTick reset + STR r1, [r0, #0x10] @ Reset SysTick Control + STR r1, [r0, #0x18] @ Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] @ Setup SysTick Reload Value MOV r1, #0x7 @ Build SysTick Control Enable Value diff --git a/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm index 9259c2f4..96fa7fa9 100644 --- a/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm @@ -107,6 +107,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + MOV r1, 0 ; Build value for SysTick reset + STR r1, [r0, 0x10] ; Reset SysTick Control + STR r1, [r0, 0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, 0x14] ; Setup SysTick Reload Value MOV r1, 0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S index 1a724410..4bf5d328 100644 --- a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -108,6 +108,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s index bf7b64b0..ef1f8f9e 100644 --- a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s @@ -113,6 +113,9 @@ _tx_initialize_low_level: ; /* Configure SysTick. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s index 9c6dd97c..adde4604 100644 --- a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s @@ -161,6 +161,9 @@ _tx_initialize_low_level ; /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S index 2f10e84a..b32c5ac4 100644 --- a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -103,6 +103,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m33/ac6/src/tx_initialize_low_level.S b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S index 896abe06..e74425a4 100644 --- a/ports/cortex_m33/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m33/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m33/gnu/example_build/tx_initialize_low_level.S index 5915dc96..0ddfba10 100644 --- a/ports/cortex_m33/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m33/gnu/example_build/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m33/iar/src/tx_initialize_low_level.s b/ports/cortex_m33/iar/src/tx_initialize_low_level.s index 8544e8a5..17d29846 100644 --- a/ports/cortex_m33/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m33/iar/src/tx_initialize_low_level.s @@ -108,6 +108,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s index 5f5e42b5..c08bd94e 100644 --- a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s @@ -166,6 +166,9 @@ _tx_initialize_low_level ; /* Configure SysTick. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 16dd113e..9bada308 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ MOV r0, #0xE000E000 @ Build address of NVIC registers + MOV r1, #0 @ Build value for SysTick reset + STR r1, [r0, #0x10] @ Reset SysTick Control + STR r1, [r0, #0x18] @ Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] @ Setup SysTick Reload Value MOV r1, #0x7 @ Build SysTick Control Enable Value diff --git a/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm index 1a144b7b..bf96627d 100644 --- a/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm @@ -107,6 +107,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + MOV r1, 0 ; Build value for SysTick reset + STR r1, [r0, 0x10] ; Reset SysTick Control + STR r1, [r0, 0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, 0x14] ; Setup SysTick Reload Value MOV r1, 0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S index 4c7a6223..39399ebc 100644 --- a/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S @@ -118,6 +118,9 @@ _tx_initialize_low_level: @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ MOV r0, #0xE000E000 @ Build address of NVIC registers + MOV r1, #0 @ Build value for SysTick reset + STR r1, [r0, #0x10] @ Reset SysTick Control + STR r1, [r0, #0x18] @ Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] @ Setup SysTick Reload Value MOV r1, #0x7 @ Build SysTick Control Enable Value diff --git a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s index a84667c3..8e3f7d85 100644 --- a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s @@ -113,6 +113,9 @@ _tx_initialize_low_level: ; /* Configure SysTick. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s index 58aee89c..4bce73a4 100644 --- a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s @@ -181,6 +181,9 @@ _tx_initialize_low_level ; /* Configure SysTick. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S index fdd8aaed..6e7e9eed 100644 --- a/ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S @@ -103,6 +103,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m55/ac6/src/tx_initialize_low_level.S b/ports/cortex_m55/ac6/src/tx_initialize_low_level.S index d6e39792..45f18012 100644 --- a/ports/cortex_m55/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m55/ac6/src/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m55/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m55/gnu/example_build/tx_initialize_low_level.S index ee23d9cb..0a8d5363 100644 --- a/ports/cortex_m55/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m55/gnu/example_build/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m55/iar/src/tx_initialize_low_level.s b/ports/cortex_m55/iar/src/tx_initialize_low_level.s index 312e8267..faf65817 100644 --- a/ports/cortex_m55/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m55/iar/src/tx_initialize_low_level.s @@ -108,6 +108,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s index 07c27743..7f3e8690 100644 --- a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s @@ -171,6 +171,9 @@ _tx_initialize_low_level ; /* Configure SysTick. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 11525a95..0e50bc48 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: @ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @ MOV r0, #0xE000E000 @ Build address of NVIC registers + MOV r1, #0 @ Build value for SysTick reset + STR r1, [r0, #0x10] @ Reset SysTick Control + STR r1, [r0, #0x18] @ Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] @ Setup SysTick Reload Value MOV r1, #0x7 @ Build SysTick Control Enable Value diff --git a/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm index 57c964b3..fc6e19fe 100644 --- a/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm @@ -107,6 +107,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + MOV r1, 0 ; Build value for SysTick reset + STR r1, [r0, 0x10] ; Reset SysTick Control + STR r1, [r0, 0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, 0x14] ; Setup SysTick Reload Value MOV r1, 0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S index e146e47f..2b6d9af6 100644 --- a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -108,6 +108,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s index 76d065cf..6e886e7f 100644 --- a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s @@ -113,6 +113,9 @@ _tx_initialize_low_level: ; /* Configure SysTick. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports/cortex_m85/ac6/src/tx_initialize_low_level.S b/ports/cortex_m85/ac6/src/tx_initialize_low_level.S index a3daea70..776f8760 100644 --- a/ports/cortex_m85/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m85/ac6/src/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S index 22dc0780..317d1d39 100644 --- a/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports/cortex_m85/iar/src/tx_initialize_low_level.s b/ports/cortex_m85/iar/src/tx_initialize_low_level.s index 64260c52..4935842a 100644 --- a/ports/cortex_m85/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m85/iar/src/tx_initialize_low_level.s @@ -108,6 +108,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_arch/ARMv7-M/threadx/ac5/example_build/tx_initialize_low_level.s b/ports_arch/ARMv7-M/threadx/ac5/example_build/tx_initialize_low_level.s index c51e67cf..af05fba7 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/example_build/tx_initialize_low_level.s +++ b/ports_arch/ARMv7-M/threadx/ac5/example_build/tx_initialize_low_level.s @@ -165,6 +165,9 @@ _tx_initialize_low_level #ifndef TX_NO_TIMER /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/tx_initialize_low_level.S index af332d80..617d62de 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -107,6 +107,9 @@ _tx_initialize_low_level: #ifndef TX_NO_TIMER /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_arch/ARMv7-M/threadx/ghs/example_build/tx_initialize_low_level.arm b/ports_arch/ARMv7-M/threadx/ghs/example_build/tx_initialize_low_level.arm index 57c964b3..fc6e19fe 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/example_build/tx_initialize_low_level.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/example_build/tx_initialize_low_level.arm @@ -107,6 +107,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + MOV r1, 0 ; Build value for SysTick reset + STR r1, [r0, 0x10] ; Reset SysTick Control + STR r1, [r0, 0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, 0x14] ; Setup SysTick Reload Value MOV r1, 0x7 ; Build SysTick Control Enable Value diff --git a/ports_arch/ARMv7-M/threadx/gnu/example_build/tx_initialize_low_level.S b/ports_arch/ARMv7-M/threadx/gnu/example_build/tx_initialize_low_level.S index 8fce83db..41cde163 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/example_build/tx_initialize_low_level.S +++ b/ports_arch/ARMv7-M/threadx/gnu/example_build/tx_initialize_low_level.S @@ -104,6 +104,9 @@ _tx_initialize_low_level: #ifndef TX_NO_TIMER /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_arch/ARMv7-M/threadx/iar/example_build/tx_initialize_low_level.s b/ports_arch/ARMv7-M/threadx/iar/example_build/tx_initialize_low_level.s index d2c2e07f..dd4bfce4 100644 --- a/ports_arch/ARMv7-M/threadx/iar/example_build/tx_initialize_low_level.s +++ b/ports_arch/ARMv7-M/threadx/iar/example_build/tx_initialize_low_level.s @@ -98,6 +98,9 @@ _tx_initialize_low_level: #ifndef TX_NO_TIMER /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S index 9332b7e1..e57c6b39 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S index 842dcdf4..f0b326a1 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S @@ -106,6 +106,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s index 6d8e07e8..a79f1963 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s @@ -108,6 +108,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 0c6c1e74..a5de014a 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -117,6 +117,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES MOVS r2, #0x14 STR r1, [r0, r2] // Setup SysTick Reload Value diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index dcc369ae..da703cce 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -118,6 +118,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES MOVS r2, #0x14 STR r1, [r0, r2] // Setup SysTick Reload Value diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S index 445f77cf..436ee049 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S @@ -119,6 +119,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES MOVS r2, #0x14 STR r1, [r0, r2] // Setup SysTick Reload Value diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 4928d596..667452cf 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -119,6 +119,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES MOVS r2, #0x14 STR r1, [r0, r2] // Setup SysTick Reload Value diff --git a/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s index 16404d63..44be0ae6 100644 --- a/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s @@ -123,6 +123,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =0 + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES MOVS r2, #0x14 STR r1, [r0, r2] // Setup SysTick Reload Value diff --git a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S index 00d7b325..2bc0c460 100644 --- a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -103,6 +103,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ LDR r0, =0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOVW r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S index d38525bf..28c37f36 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S @@ -105,6 +105,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ LDR r0, =0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOVW r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s index fb6a109f..90849145 100644 --- a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s @@ -104,6 +104,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ LDR r0, =0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S index 057ccc9a..0d415dc5 100644 --- a/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S @@ -185,6 +185,9 @@ _tx_initialize_low_level ; /* Configure SysTick. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 72f44643..5cf5b418 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 5f263cae..376b15c0 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S index edc1eef3..278dd9b3 100644 --- a/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -109,6 +109,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ MOV r0, #0xE000E000 @ Build address of NVIC registers + MOV r1, #0 @ Build value for SysTick reset + STR r1, [r0, #0x10] @ Reset SysTick Control + STR r1, [r0, #0x18] @ Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] @ Setup SysTick Reload Value MOV r1, #0x7 @ Build SysTick Control Enable Value diff --git a/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s index f3262e15..d31fbb33 100644 --- a/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s @@ -123,6 +123,9 @@ _tx_initialize_low_level: ; /* Configure SysTick. */ ; MOV r0, #0xE000E000 ; Build address of NVIC registers + MOV r1, #0 ; Build value for SysTick reset + STR r1, [r0, #0x10] ; Reset SysTick Control + STR r1, [r0, #0x18] ; Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] ; Setup SysTick Reload Value MOV r1, #0x7 ; Build SysTick Control Enable Value diff --git a/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S index 9e6fa804..4043e110 100644 --- a/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -103,6 +103,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S index c89394c2..dd10aeff 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S @@ -103,6 +103,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s index 43467f18..048e0a8b 100644 --- a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s @@ -104,6 +104,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S index fb461536..49b4f75c 100644 --- a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S @@ -171,6 +171,9 @@ _tx_initialize_low_level /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index ccd76ffb..fdf43991 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 4e457588..61e40d2e 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S index e922a5b5..85a88c69 100644 --- a/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S @@ -115,6 +115,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s index 07afc829..55e9fc40 100644 --- a/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s @@ -110,6 +110,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S index 62d7eb93..7ab4b450 100644 --- a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S @@ -171,6 +171,9 @@ _tx_initialize_low_level /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 2837a142..813d2577 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 2df350e5..c5715b94 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -116,6 +116,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S index e9273cbd..01c8814b 100644 --- a/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -115,6 +115,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value diff --git a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s index 2df2d19f..6919b6e1 100644 --- a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s @@ -110,6 +110,9 @@ _tx_initialize_low_level: /* Configure SysTick. */ MOV r0, #0xE000E000 // Build address of NVIC registers + MOV r1, #0 // Build value for SysTick reset + STR r1, [r0, #0x10] // Reset SysTick Control + STR r1, [r0, #0x18] // Reset SysTick Counter Value LDR r1, =SYSTICK_CYCLES STR r1, [r0, #0x14] // Setup SysTick Reload Value MOV r1, #0x7 // Build SysTick Control Enable Value |