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authorFrédéric Desbiens <[email protected]>2026-03-02 14:24:07 +0100
committerFrédéric Desbiens <[email protected]>2026-03-02 14:24:07 +0100
commitda5093f84b2bbe2aa6050b9521a7d8a818dbc96f (patch)
tree07ab30192616c931c8388b78bf17ef9e0bb9b81a /ports/cortex_a15
parenta7961fe1909a5a15730f4fdf7cd5528f660ca756 (diff)
Proposed changes to the original PR
Diffstat (limited to 'ports/cortex_a15')
-rw-r--r--ports/cortex_a15/ac6/src/tx_thread_schedule.S6
-rw-r--r--ports/cortex_a15/gnu/src/tx_thread_schedule.S6
-rw-r--r--ports/cortex_a15/iar/src/tx_thread_schedule.s2
3 files changed, 10 insertions, 4 deletions
diff --git a/ports/cortex_a15/ac6/src/tx_thread_schedule.S b/ports/cortex_a15/ac6/src/tx_thread_schedule.S
index 54127015..f46a339b 100644
--- a/ports/cortex_a15/ac6/src/tx_thread_schedule.S
+++ b/ports/cortex_a15/ac6/src/tx_thread_schedule.S
@@ -1,5 +1,6 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
+ * Copyright (C) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
@@ -40,11 +41,11 @@
#define SVC_MODE 0x13 // SVC mode
#ifdef TX_ENABLE_VFP_SUPPORT
-IRQ_MASK = 0x080
+#define IRQ_MASK 0x80
#endif
#ifdef TX_ENABLE_FIQ_SUPPORT
-FIQ_MASK = 0x040
+#define FIQ_MASK 0x40
#endif
/**************************************************************************/
@@ -267,3 +268,4 @@ no_fiq:
BX lr
#endif
+
diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S
index 54127015..f46a339b 100644
--- a/ports/cortex_a15/gnu/src/tx_thread_schedule.S
+++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S
@@ -1,5 +1,6 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
+ * Copyright (C) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
@@ -40,11 +41,11 @@
#define SVC_MODE 0x13 // SVC mode
#ifdef TX_ENABLE_VFP_SUPPORT
-IRQ_MASK = 0x080
+#define IRQ_MASK 0x80
#endif
#ifdef TX_ENABLE_FIQ_SUPPORT
-FIQ_MASK = 0x040
+#define FIQ_MASK 0x40
#endif
/**************************************************************************/
@@ -267,3 +268,4 @@ no_fiq:
BX lr
#endif
+
diff --git a/ports/cortex_a15/iar/src/tx_thread_schedule.s b/ports/cortex_a15/iar/src/tx_thread_schedule.s
index c98087aa..0d2fd007 100644
--- a/ports/cortex_a15/iar/src/tx_thread_schedule.s
+++ b/ports/cortex_a15/iar/src/tx_thread_schedule.s
@@ -1,5 +1,6 @@
;/***************************************************************************
; * Copyright (c) 2024 Microsoft Corporation
+ * Copyright (C) 2026-present Eclipse ThreadX contributors
; *
; * This program and the accompanying materials are made available under the
; * terms of the MIT License which is available at
@@ -239,3 +240,4 @@ __tx_no_thread_to_disable
END
+